Texas Instruments DS125BR401EVK User guide

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DS125BR401EVM User’s Guide

User's Guide

Literature Number: SNLU121

November 2012

User's Guide

SNLU121 – November 2012

DS125BR401EVM Evaluation Kit

The DS125BR401EVM – SMA evaluation kit provides a complete high band-width platform to evaluate the signal integrity and signal conditioning features of the Texas Instruments signal conditioning products – with Equalization and De-emphasis. SMA edge launch connectors are used as the input and the output connections for this evaluation board. Commercially available adaptor boards can be purchased to facilitate connection to cables or backplane interconnects.

Topic

...........................................................................................................................

Page

Features

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4-Level IO Control

...............................................................................................

Switch Connection Overview

................................................................................

Quick Start Guide

................................................................................................

SMBus Slave Mode of the EQ, VOD, and De-Emphasis level:

..................................

Bill of Materials for DS125BR401EVM:

Schematic for DS125BR401EVM:

.................................................................

.........................................................................

EVM Layout

......................................................................................................

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1 Features

• 4 Lane Repeater up to 12.5 Gbps

• Low 65 mW/channel power consumption, with option to power down unused channels

• Transparent management of link training protocol for PCIe, SAS, and 10G-KR

• Receive Equalization up to 30 dB at 12.5 Gbps

• Settable transmit de-emphasis driver to -12 dB

• Transmit output voltage control: 700 – 1300 mV

• Programmable via pin selection, EEPROM, or SMBus interface

• Single supply operation: VIN = 3.3V±10% or VDD = 2.5V ±5%

• -40°C to +85°C Operation

• 5 kV HBM ESD rating

• High speed signal flow–thru pin-out package: 54-pin QFN (10 mm x 5.5 mm, 0.5 mm pitch)

Applications

FR-4 Backplane Traces and High Speed Cable

Ordering Information

EVM ID

DS125BR401EVM

DEVICE ID

DS125BR401SQE/NOPB

Features

DEVICE PACKAGE

QFN-54

Figure 1. DS125BREVK REV. 1

DS125BR401/DS125BR800 Top Assembly

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Features

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Figure 2. DS125BREVK REV. 1

DS125BR401/DS125BR800 Bottom Assembly

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2 4-Level IO Control

4-Level IO Control

Many of the control pins on the DS125BR401 have more than two valid levels.

Table 1

below shows how to access each of these levels with the switch banks on the back side of the EVM.

Table 1. Switches to set the 4-Level input control pins

4-Level Input Settings

0 - Tie 1k Ω to GND

R - Tie 20k Ω to GND

F - FLOAT (open)

1 - Tie 1k Ω to VIH

Setting for 3 pin switches (3-2-1)

ON - OFF - OFF

OFF - ON - OFF

OFF - OFF - OFF

OFF - OFF - ON

The following switches are used to set the input condition for the 4-level inputs:

•

SW1, SW2, SW3, SW5, SW6, SW8, SW9

There are 3 switches connected to an input signal pin. Each switch when set to the ON position sets the pin to one of the 4-level setting. The 6 pin switches are assigned similar to the 3 pin switches. The only difference is 2 signal pins are connected and thus 6-5-4 is for the one signal pin and 3-2-1 is for another signal pin.

NOTE:

Only 1 switch at the ON position is allowed. Activating more than one switch concurrently results in an indeterminate voltage level.

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Switch Connection Overview

3 Switch Connection Overview

Component

J1 to J8

J9 to J16

SW3

SW4

SW5

SW6

SW7

SW8

J19

J20

J17

J18

SW1

SW2

SW9

SW10 www.ti.com

Table 2. Connection and Control Description

Name

IN_B2+, IN_B2-,

IN_B3+, IN_B3-,

IN_A0+, IN_A0-,

IN_A1+, IN_A1-,

OUT_B2+, OUT_B2-,

OUT_B3+, OUT_B3-,

OUT_A0+, OUT_A0-,

OUT_A1+, OUT_A1-,

VIN or VDD

Function

High-speed differential inputs

High-speed differential outputs

SDA, SCL

EEPROM

EQB[1:0] or

AD[3:2]

ENSMB

DC Power - VIN or VDD to DS125BR401SQ

Jumper – VIN or VDD to VIH power

Optional SMBUS access pins.

See the datasheet for additional information on SMBUS.

Optional socket for EEPROM

PIN MODE – EQ control for channel B inputs

SMBUS MODE – AD[3:2] device address bits

ENSMB = LOW – PIN MODE

ENSMB = HIGH – SMBUS (slave mode)

ENSMB = FLOAT – SMBUS (master mode – load configuration from

EEPROM)

PIN MODE – DE control for channel A outputs

“ON” position connects SDA and SCL lines to the device pin.

PIN MODE – DE control for channel B outputs

SMBUS MODE – AD[1:0] device address bits

DEMA[1:0]

SDA/SCL

DEMB[1:0] or

AD[1:0]

SD_TH and LPBK - RES

SD_TH – Signal detect threshold level (FLOAT = Default level)

LPBK function for BR401 only (FLOAT = Normal operation)

VDD_SEL and

RESET

EQA[1:0]

VDD_SEL – Enable or disable the internal 3.3V to 2.5V regulator.

RESET – Enable or disable the device (LOW – enable)

PIN MODE – EQ control for channel A inputs

INPUT_EN and

MODE

READ_EN

INPUT_EN – Enable or disable the internal 50 ohm to VDD terminations

MODE – Tie 1k

Ω to GND = GEN 1,2 and SAS 1,2

Float = Auto Mode Select (for PCIe and SAS-3)

Tie 20k

Ω to GND = SAS-3 and GEN-3 without De-emphasis

Tie 1k Ω to VDD = SAS-3 and GEN-3 with De-emphasis

ENSMB = FLOAT – SMBUS (master mode – load configuration from

EEPROM)

SW6: SD_TH becomes the READ_EN pin.

To start the loading at power up, set SW6 pin 3 to “ON” position (pull to

GND).

To manually control the start, set SW6 pin 1 to “ON” position (pull to VDD) and push the SW10 button for the high to low transition to start the loading.

When the loading is complete the LED – D1 light should turn OFF.

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4 Quick Start Guide

Quick Start Guide

1. Connect J19: VIN = 3.3V or VDD = 2.5V and GND.

•

For VIN = 3.3V:

Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and float VDD at J19.

•

For VIN = 2.5V:

Set SW7 pin1 (VDD_SEL) to the OFF positions (disable internal LDO regulator) and float VIN at

J19.

2. Set jumper – J20 for VIH connection to VIN or VDD.

3. Connect 50 Ohm SMA cables to the board.

• The input signals J5 to J12 can be connected from a pattern generator.Set SW7 pin1 (VDD_SEL) to the ON position (enable internal LDO regulator) and float VDD at J19.

• The output signals J1 to J4 and J13 to J16 can be connected to a scope.

A/B Channels

B-Channels

A-Channels

Table 3. SMA Channel Connections

Input Channel

J1 – OUT_B2+, J2 – OUT_B2-

J3 – OUT_B3+, J4 – OUT_B3-

J5 – IN_A0+, J6 – IN_A0-

J7 – IN_A1+, J8 – IN_A1-

Output Channel

J9 – IN_B2+, J10 – IN_B2-

J11 – IN_B3+, J12 – IN_B3-

J13 – OUT_A0+, J14 – OUT_A0-

J15 – OUT_A1+, J16 – OUT_A1-

4. Set the control pins for normal operation

• SW7 – RESET = 0 (enables the device): set switch pin2 to the ON position.

• SW9 – INPUT_EN = 1 (50 ohm input termination): set switches (3-2-1) = (OFF-OFF-ON).

• SW9 – MODE = VDD (enables SAS-3 / PCIe GEN3 mode): set switches (6-5-4) = (OFF-OFF-ON).

• SW6 – SD_TH = F (default signal detect threshold level): set switches (3-2-1) = (OFF-OFF-OFF).

• SW6 – LPBK - RES = F (normal operation): set switches (6-5-4) = (OFF-OFF-OFF).

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Quick Start Guide

Set the input equalization level.

•

For external pin mode control of the equalization level:

• Set ENSMB = 0 (1k Ω to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).

• SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.

• Refer to

Table 1

for information on the 3 switch settings for the 4 level input.

Example:

• Set EQB[1:0] with SW1 for the B bank of inputs (top 4 inputs of DS125BR401).

• SW1 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQB[1:0] = R,R (Level 6).

• Set EQA[1:0] with SW8 for the A bank of inputs (bottom 4 inputs of DS125BR401).

• SW8 (6-5-4), (3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQA[1:0] = R,R (Level 6).

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Level

EQA/B[1:0]

R, R

R, F

R, 1

F, 0

F, R

0, 0

0, R

0, F

0, 1

R, 0

F, F

F, 1

1, 0

1, R

1, F

1, 1

OFF

Table 4. EQ Settings available with PIN MODE

OFF

SW1 - EQB[1:0] or SW8 - EQA[1:0]

4 3 2

OFF

EQ (dB) @ 6 GHz

16.2

15.9

17.0

20.7

21.8

3.1

6.7

8.4

9.1

13.7

23.6

24.7

28.0

29.2

30.9

31.9

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2 www.ti.com

Quick Start Guide

Set the output VOD and De-emphasis level.

•

For external pin mode control for the VOD and De-emphasis level:

• Set ENSMB = 0 (1k Ω to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).

• SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.

• Refer to

Table 1

for information on the 3 switch settings for the 4 level input.

Example:

• Set DEMB[1:0] with SW5 for the B bank of outputs (top 4 outputs of DS125BR401).

• SW5 (6-5-4), (3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMB[1:0] = 0,1 (VOD=1.0V, DE=0 dB).

• Set DEMA[1:0] with SW3 for the A bank of outputs (bottom 4 outputs of DS125BR401).

• SW3 (6-5-4), (3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMA1:0] = 0,1 (VOD=1.0V, DE=0 dB).

Level

R, F

R, 1

F, 0

F, R

F, F

F, 1

1, 0

0, 0

0, R

0, F

0, 1

R, 0

R, R

1, R

1, F

1, 1

EQA/B[1:0]

Table 5. DE and VOD Settings available in PIN MODE

SW1 - EQB[1:0] or SW8 - EQA[1:0]

OFF

4 3 2 1

GEN1 and GEN2

Inner Amplitude

)

0.8

0.9

0.6

1.0

DE (dB)

-3.5

0.7

0.5

1.1

0.7

-3.5

-6

-3.5

0.6

1.2

0.8

0.6

1.3

0.9

0.7

0.5

-6

-3.5

-6

-3.5

-6

-9

NOTE:

The De-Emphasis levels are also available in SAS-3 / GEN-3 mode when MODE = 1

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SMBus Slave Mode of the EQ, VOD, and De-Emphasis level:

5 SMBus Slave Mode of the EQ, VOD, and De-Emphasis level:

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• Set ENSMB = 1 (1k Ω to VIH) by using the SW2 (3-2-1) = (OFF-OFF-ON).

• Set SW4 pin1,2 to the ON position so the SMBUS signals are connected.

• Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line.

• Set the SW1 and SW5 for the AD[3:0] pins. AD[3:0]=0000 sets device slave address = B0’hex.

• Connect SDA, SCL and GND to J17. Please refer to datasheet for register map for EQ, VOD and

DEM.

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6 Bill of Materials for DS125BR401EVM:

Item

Bill of Materials for DS125BR401EVM:

Qty

R1, R2, R3, R4,

R8, R11, R13,

R14, R16, R17,

R19, R20, R22,

R23, R25, R26,

R28, R29, R31,

R32, R34, R35,

R37, R38, R40,

R41, R43, R44,

R46, R47, R49

R12, R15, R18,

R21, R24, R27,

R30, R33, R36,

R39, R42, R45,

R48

R5, R6

SW1, SW3, SW5,

SW6, SW8, SW9

SW2

SW4, SW7

SW10

Reference

C3, C4, C5, C6,

C11, C12, C13,

C14, C15, C16,

C17, C18, C19,

C20, C21, C22,

C23, C24, C25,

C26

J1, J2, J3, J4, J5,

J6, J7, J8, J9,

J10, J11, J12,

J13, J14, J15,

J16

J17

J19, J20

J18

Table 6. DS125BR401EVM BOM

Digikey PN

445-3448-1-ND

445-1322-1-ND

445-4711-1-ND

587-2483-1-ND

511-1592-1-ND

J801-ND

WM6504-ND

WM6503-ND

3M5473-ND

P1.00KLCT-ND

P220LCT-ND

P20.0KLCT-ND

Manufacture PN

C1608Y5V0J106Z

C1608X5R0J105K

C0603X5R0J104M

LMK063BJ224MP-F

SML-P12PTT86

142-0761-881

22-28-4043

22-28-4033

4808-3004-CP

ERJ-2RKF1001X

ERJ-2RKF2200X

ERJ-2RKF2002X

Descriptions

CAP CER 10UF 6.3V Y5V 0603

CAP CER 1.0UF 6.3V X5R 0603

CAP CER .10UF 6.3V X5R 0201

CAP CER .22UF 10V X5R 0201

LED GRN 0.2MM 13MCD 0402 SMD

CONN JACK SMA 50 OHMS PC MOUNT

CONN HEADER 4POS .100 VERT GOLD

CONN HEADER 3POS .100 VERT GOLD

SOCKET IC 8-POS .3"

RES 1.00K 1/10W 1% 0402

RES 220 1/10W 1% 0402

RES 20.0K 1/10W 1% 0402

P4.70KLCT-ND

CT2196MST-ND

CT2193MST-ND

CT2192MST-ND

P12225SCT-ND

ERJ-2RKF4701X

219-6MST

RES 4.70K OHM 1/10W 1% 0402 SMD

SWITCH TAPE SEAL 6 POS SMD

219-3MST

219-2MST

SWITCH TAPE SEAL 3 POS SMD

SWITCH TAPE SEAL 2 POS SMD

EVQ-21505R SWITCH LT 6MM 160GF 5MM HEIGHT

DS125BR401SQ/NOPB BUFFER - REPEATER

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Schematic for DS125BR401EVM:

7 Schematic for DS125BR401EVM:

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Figure 3. DS125BR401EVM Schematic

Note: The DS125BR401 and DS125BR800 share a common EVM PCB Assembly.

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8 EVM Layout

EVM Layout

The following Figures show the DS125BR401EVM board layout. The EVM controls signal integrity functions via a combination of switches and jumpers.

The DS125BR401 is very compact and low power. The QFN package offers an exposed thermal pad to enhance electrical and thermal performance. This must be soldered to the copper landing on the PWB.

Figure 4. Top Assembly Layer

Figure 5. Bottom Assembly Layer

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