T S 6 4 M L R 7 2 V 6 F

Description

The TS64MLR72V6F is a 64M bit x 72 Synchronous

Dynamic RAM high-density memory registered DIMM module. The TS64MLR72V6F consists of 18pcs

16Mx8 bits Synchronous DRAMs, 3pcs drive ICs for input control signal, 1pc PLL and a 2048 bits serial

EEPROM on a 168-pin printed circuit board. The

TS64MLR72V6F is a Dual In-Line Memory Module and is intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

• RoHS compliant products.

• Performance Range: PC-133

• Burst Mode Operation.

• Auto and Self Refresh.

• DQM Byte Masking (Read/Write)

• Serial Presence Detect (SPD) with serial EEPROM

• LVTTL compatible inputs and outputs.

• Single 3.3V ± 0.3V power supply.

• MRS cycle with address key programs.

Latency (Access from column address)

Burst Length (1,2,4,8 & Full Page)

Data Sequence (Sequential & Interleave)

• All inputs are sampled at the positive going edge of

the system clock.

Transcend Information Inc.

1

168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

Placement

A

B

F

E

G

PCB: 09-0872

D

C

H

T S 6 4 M L R 7 2 V 6 F

Dimensions

Side Millimeters Inches

A 133.35

±0.40 5.250

±0.016

B 65.67

000 2.585

000

C 23.49

000

D 8.89

000

E 15.80

0.925

0.350

0.622

000

000

F 19.80 0.780

G 43.00

±0.20 1.693

±0.008

H 1.27

±0.10

0.050

±0.004

(Refer Placement)

168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

Pin Identification

Symbol Function

SREGE

EA0~EA2

SCL

SDA

Vcc

Vss

NC

SA0~SA12

SBA0,SBA1

SD0~SD63

SCB0~SCB7

SCK0

SCKE0

/SCS0~SCS3

/SRAS

/SCAS

/SWE

SDQM0~SDQM7

Address Input

Select Bank Address

Data Input / Output.

Check bit (data-in / data-out)

Clock Input.

Clock Enable Input.

Chip Select Input.

Row Address Strobe

Column Address Strobe

Write Enable

Data (DQ) Mask

Register Enable

Address in EEPROM

Serial PD Clock

Serial PD Add/Data input/output

+3.3 Voltage Power Supply

Ground

No Connection

Transcend Information Inc.

2

T S 6 4 M L R 7 2 V 6 F

168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

Pinouts:

Pin

No

Pin

Name

Pin

No

Pin

Name

Pin

No

Pin

Name

Pin

No

Pin

Name

01 Vss

02 DQ0

03 DQ1

04 DQ2

05 DQ3

06 Vcc

07 DQ4

08 DQ5

43 Vss

44 NC

85 Vss 127 Vss

86 DQ32 128 CKE0

45 /CS2 87 DQ33 129 */CS3

46 DQM2 88 DQ34 130 DQM6

47 DQM3 89 DQ35 131 DQM7

48 NC 90 Vcc 132 *A13

49 Vcc

50 NC

91 DQ36

92 DQ37

133 Vcc

134 NC

09 DQ6

10 DQ7

11 DQ8

12 Vss

51 NC 93 DQ38 135 NC

52 *CB2 94 DQ39 136 *CB6

53 *CB3 95 DQ40 137 *CB7

54 Vss 96 Vss 138 Vss

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 Vcc

18 Vcc 60 DQ20

101 DQ45

102 Vcc

143 Vcc

144 DQ52

19 DQ14 61 NC 103 DQ46 145 NC

20 DQ15 62 *Vref 104 DQ47 146 *Vref

21 *CB0 63 *CKE1 105 *CB4 147 *REGE

22 *CB1 64 Vss 106 *CB5 148 Vss

23 Vss

24 NC

65 DQ21

66 DQ22

107 Vss

108 NC

149 DQ53

150 DQ54

25 NC

26 Vcc

67 DQ23 109 NC

68 Vss 110 Vcc

151 DQ55

152 Vss

27 /WE 69 DQ24 111 /CAS 153 DQ56

28 DQM0 70 DQ25 112 DQM4 154 DQ57

29 DQM1 71 DQ26 113 DQM5 155 DQ58

30 /CS0 72 DQ27 114 */CS1 156 DQ59

31 NC

32 Vss

73 Vcc

74 DQ28

115 /RAS

116 Vss

157 Vcc

158 DQ60

33 A0

34 A2

35 A4

36 A6

37 A8 79 *CLK2 121 A9

38 A10/AP 80 NC 122 BA0

39 BA1

40 Vcc

81 NC

82 SDA

123 A11

124 Vcc

41 Vcc

42 CLK0

75 DQ29 117 A1

76 DQ30 118 A3

77 DQ31 119 A5

78 Vss 120 A7

83 SCL

84 Vcc

* Please refer Block Diagram

159 DQ61

160 DQ62

161 DQ63

162 Vss

163 *CLK3

164 NC

165 SA0

166 SA1

125 *CLK1 167 SA2

126 *A12 168 Vcc

Transcend Information Inc.

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Block Diagram

CKE1

/CS1

/CS0

168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

CKE0

DQM0 DQM4

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

DQM1

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U1

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U10

DQ39

DQ38

DQ37

DQ36

DQ35

DQ34

DQ33

DQ32

DQM5

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U5

DQ15

DQ14

DQ13

DQ12

DQ11

DQ10

DQ9

DQ8

DQM2

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U2

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U11

DQ47

DQ46

DQ45

DQ44

DQ43

DQ42

DQ41

DQ40

DQM6

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U6

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U3

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U12

DQ55

DQ54

DQ53

DQ52

DQ51

DQ50

DQ49

DQ48

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U7

DQM3 DQM7

DQ31

DQ30

DQ29

DQ28

DQ27

DQ26

DQ25

DQ24

DQM5

DQM1

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U4

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U13

DQ63

DQ62

DQ61

DQ60

DQ59

DQ58

DQ57

DQ56

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U8

CB2

CB6

CB3

CB7

CB1

CB5

CB0

CB4

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U9

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U18

VDD

U1~U18

VSS

Note:

1.U1~U18 are 16Mx8 SDRAM.

2.DQ-to-I/O wiring may be changed per nibble.

3.Unless otherwise noted , resister values are 10 Ohms±5%

SA0~SA12

SBA0~SBA1

/SRAS

/SCAS

/SWE

SCKE0

SCS0

SCKE1

SCS1

SDQM0~SDQM7

CK0

/RESET

P

L

L

SCL

EEPROM

WP

T

E

I

S

R

E

G

R

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

/CS CKE

U14

/CS CKE

U15

/CS CKE

U16

/CS CKE

U17

U1~U18

Register

SDA

U1~U18

U1~U18

U1~U18

U1~U18

U1~U18

U1~U9

U1~U9

U10~U18

U10~U18

U1~U18

SA0 SA1 SA2

This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.

Transcend Information Inc.

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on VDD supply to Vss

Storage temperature

Power dissipation

Short circuit current

Operating Temperature

Symbol

VIN, VOUT

VDD, VDDQ

TSTG

Value

-1.0~4.6

-1.0~4.6

-55~+150

Unit

V

V

°C

PD

IOS

18

50

W mA

T A 0~70

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70 °C)

Parameter Symbol Min Typ Max Unit

Supply voltage

Input high voltage

Input low voltage

V DD 3.0 3.3 3.6 V

V IH 2.0 3.0 DD +0.3 V

Note

1

V IL -0.3 0 0.8 V 2

Output high voltage

Output low voltage

Input leakage current

V

V

I

OH

OL

IL

2.4

-

- - V IOH=-2mA

- 0.4 V IOL=2mA

-10 - 10 uA 3

Note: 1. V

IH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.

2. V IL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V

IN

≤ V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

Transcend Information Inc.

5

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

CAPACITANCE (V DD = 3.3V, TA = 23 °C, f = 1MHz, V

REF = 1.4V

±200mV)

Parameter

Input capacitance (SA 0 ~SA 12 , SBA 0 ~ SBA 1 )

Input capacitance (/SRAS, /SCAS, /SWE)

Input capacitance (SCKE0)

Input capacitance (SCLK0)

Input capacitance (/SCS0~/SCS3)

Input capacitance (SDQM0~SDQM7)

Data input/output capacitance (SD0~SD63)

Symbol

C IN1

C IN2

C IN3

C IN4

C IN5

C IN6

C OUT

40

30

25

10

Min

85

85

50

45

40

30

15

Max

105

105

65

Data input/output capacitance (SCB0~SCB7)

Operating Current

(One Bank Active)

I CC1

C OUT 1 10 15

1,350 pF

DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, T A = 0 to 70 °C)

Parameter Symbol Test Condition CAS Latency Value Unit Note

Burst Length =1 t RC

≥t

RC (min)

I OL =0mA

Precharge Standby Current in power-down mode

I CC2 P CKE ≤V

IL( max), t CC 3

I CC2 PS CKE & CLK≤V IL( max), t CC =∞ 36

I CC2 N

CKE ≥V

IH( min), /CS ≥V

IH( min), t CC =10ns

Input signals are changed one time during 30ns

Precharge Standby Current in non power-down mode

I CC2 NS CKE≥V

IH( min), CLK ≤V

IL( max), t CC =∞

Input signals are stable

288

252 mA 3 pF pF pF pF

Unit pF pF pF

Active Standby Current in power-down mode

Active Standby Current in non power-down mode

(One Bank Active)

Operating Current

(Bust Mode)

I CC3 P CKE ≤V

IL( max), t CC =10ns

I CC3 PS CKE & CLK≤V IL( max), t CC =∞

I CC3 N CKE ≥V

IH( min), /CS ≥V

IH( min), t CC =10ns

Input signals are changed one time during 20ns

I

I

I CC3 NS CKE ≥V

IH( min), CLK ≤V

IL( max), t CC =∞

Input signals are stable

CC4

CC5

I OL= 0 mA

Page Burst tcc

D = 2CLKs t RC

≥t

RC (min)

108

108

540

450

1,530 mA mA

3

3 mA 1

Refresh Current 2,160 mA 2,3

Self Refresh Current I CC6 CKE 3

Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Transcend Information Inc.

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

AC OPERATING TEST CONDITIONS (V DD = 3.3V

±0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC Input levels (V IH /V IL ) 2.4/0.4

Input timing measurement reference level 1.4 V

Input rise and fall time

Output timing measurement reference level

Output load condition

3.3V

tr/tf=1/1

1.4

See Fig. 2

Vtt=1.4V

ns

V

50 Ohm

Output

870 Ohm

1200 Ohm

50pF

V

OH

(DC)=2.4V, I

OH

=-2mA

V

OL

(DC)=0.4V, I

OL

=2mA

Output Z0=50 Ohm

50pF

(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol Value

Row active to row active delay

/RAS to /CAS delay

Row precharge time

Unit Note t RRD (min) 15 1 t RCD (min) 20 1 t RP (min) 20 1

Row active time

Row cycle time

Last data in to new col. address delay

Last data in to row precharge t RAS (min) 45 1 t RAS (max) 100 t RC (min) 65 1 t CDL (min) 1 2 t RDL (min) 2 2

Last data in to burst stop

Col. address to col. address delay t BDL (min) 1 2 t CCD (min) 1 3

4 Number of valid output data CAS latency=3 2 ea

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with

clock cycle time, and then rounding off to the next higher integer.

2. Minimum delay is required to complete write in Reg. DIMM

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

Transcend Information Inc.

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Refer to the individual component, not the whole module.

Parameter Symbol

Min

Value

Max

Unit Note

CLK cycle time

CLK to valid output delay

Output data hold time

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to outputin Hi-Z

CAS latency=3

CAS latency=3

CAS latency=3 t t t

CC

SAC

OH

7.5 ns 1

5.4

2.7 t CH 2.5 t CL 2.5 ns 3 ns 3 t SS 1.5 ns 3 t SH 0.8 ns 3 t SLZ 1 ns 2 t SHZ 5.4 ns 1 CAS latency=3

Note: 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)= 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Transcend Information Inc.

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

SIMPLIFIED TRUTH TABLE

COMMAND SCKEn-1 SCKEn /SCS /SRAS /SCAS /SWE SDQM SBA

0,1

SA

10

/AP SA

12,

A

11

,SA

0

~SA

9

Note

Register Mode Register Set 1,2

Refresh Auto Refresh

Self

Refresh

Entry

Bank Active & Row Adders.

Read &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Write &

Column Address

Auto Precharge Disable

Auto Precharge Enable

Burst Stop

Precharge

Clock Suspend or

Active Power Down

Bank Selection

Both Banks

H

H

H

L

X

L

H X L

H X L

H

L

L

H

X

L

L

H

X

H

H

H

X

H

X

X X

X V

X

Row Address

3

3

3

3

X L 4

H Address

(SA

0

~SA

9

,SA

11

)

4, 5

X L 4

H H L X

X X X X

H

L H L X V L

X H

X

Address

(SA

0

~SA

9

,SA

11

)

X

X

4, 5

6

Precharge Power

Down Mode

Entry

Exit

L

L

L

V

X

H

X

V

V

X

H

X

V

V

X

V

X

H

X

X

X

No Operation Command

L

X

H

X

H

X

H

X X

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)

Note: 1. OP Code : Operand Code

SA

0

~SA

11

, SBA

0

~SBA

1

: Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatically precharge without row precharge command is meant by “Auto”.

Auto/self refresh can be issued only at both banks precharge state.

4. SBA

0

~SBA

1

: Bank select address.

If both SBA

0 and SBA

1 are “Low” at read, write, row active and precharge, bank A is selected.

If both SBA

0

is “Low” and SBA

1

is “High” at read, write, row active and precharge, bank B is selected.

If both SBA

0

is “High” and SBA

1

is “Low” at read, write, row active and precharge, bank C is selected.

If both SBA

0 and SBA

1 are “High” at read, write, row active and precharge, bank D is selected.

If SA

10

/AP is “High” at row precharge, SBA

0

and SBA

1

is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)

Transcend Information Inc.

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168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

Serial Presence Detect Specification

Byte No.

0

Serial Presence Detect

Function Described Standard Specification

Number of Bytes Written into Serial Memory 128bytes

1 Total Number of Bytes of S.P.D Memory

3

4

5

6

7

8

Number of Row Addresses on this Assembly

Number of Column Addresses on this Assembly

Number of Module Banks on this Assembly

Data Width of this Assembly

Data Width Continuation

Voltage Interface Standard of this Assembly

256bytes

SDRAM

13

10

2 bank

72bits

0

LVTTL3.3V

9 SDRAM Cycle Time (highest CAS latency)

10 SDRAM Access from Clock (highest CL)

11 DIMM configuration type (non-parity, ECC)

12 Refresh Rate Type

13 Primary SDRAM Width

14 Error Checking SDRAM Width

15 Min Clock Delay Back to Back Random Address

16 Burst Lengths Supported

17 Number of banks on each SDRAM device

18 CAS # Latency

19 CS # Latency

20 Write Latency

21

22

SDRAM Module Attributes

SDRAM Device Attributes: General

7.5ns

5.4ns

ECC

7.8us/Self Refresh

X8

X8

1 clock

1,2,4,8 & Full page

4 bank

3

0 clock

0 clock

Registered DQM, address/control inputs and on-card PLL

Prec All, Auto Prec, R/W

Burst

23 SDRAM Cycle Time (2 nd

highest CL)

24 SDRAM Access from Clock (2 nd

highest CL)

25 SDRAM Cycle Time (3 rd

highest CL)

26 SDRAM Access from Clock (3 rd highest CL)

27 Minimum Row Precharge Time

28 Minimum Row Active to Row Activate

29 Minimum RAS to CAS Delay

30 Minimum RAS Pulse Width

31 Density of Each Bank on Module

32 Command/Address Setup Time

33 Command/Address Hold Time

34 Data Signal Setup Time

35 Data Signal Hold Time

0ns

0ns

0ns

0ns

20ns

15ns

20ns

45ns

256MB

1.5ns

0.8ns

1.5ns

0.8ns

0E

40

15

08

15

08

14

0F

14

2D

00

00

00

00

Vendor Part

80

08

04

0D

0A

75

54

02

82

02

48

00

01

04

04

01

01

08

08

01

8F

16

16

Transcend Information Inc.

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62 SPD Data Revision Code

63 Checksum for Bytes 0-62

64-71 Manufacturers JEDEC ID Code per JEP-108E

73-90 Manufacturers Part Number

93-94 Manufacturing Date

95-98 Assembly Serial Number

126 Intel Specification Frequency

127 Intel Specification CAS# Latency/Clock Signal Support

128~ Unused Storage Locations

168PIN PC133 Registered DIMM

512MB With 32M X8 CL3

-

JEDEC 2

-

Transcend

T

TS64MLR72V6F

-

By Manufacturer

By Manufacturer

-

-

CL=3 Clock 0

Open

00

02

E9

7F, 4F

54

54 53 36 34 4D 4C

52 37 32 56 36 46

20 20 20 20 20 20

0

Variable

Variable

0

64

84

FF

Transcend Information Inc.

11