Transcend | TS64MLR72V6F | Datasheet | Transcend 512MB SDRAM PC133 ECC Registered Memory

Transcend 512MB SDRAM PC133 ECC Registered Memory
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
Description
Placement
The TS64MLR72V6F is a 64M bit x 72 Synchronous
Dynamic RAM high-density memory registered DIMM
module. The TS64MLR72V6F consists of 18pcs
16Mx8 bits Synchronous DRAMs, 3pcs drive ICs for
input control signal, 1pc PLL and a 2048 bits serial
EEPROM on a 168-pin printed circuit board. The
A
TS64MLR72V6F is a Dual In-Line Memory Module
and is intended for mounting into 168-pin edge
connector sockets.
B
Synchronous design allows precise cycle control with
the use of system clock. I/O transactions are possible
C
on every clock cycle. Range of operation frequencies,
D
programmable latencies allow the same device to be
E
F
useful for a variety of high bandwidth, high
G
performance memory system applications.
PCB: 09-0872
Features
• RoHS compliant products.
• Performance Range: PC-133
• Burst Mode Operation.
• Auto and Self Refresh.
• DQM Byte Masking (Read/Write)
• Serial Presence Detect (SPD) with serial EEPROM
• LVTTL compatible inputs and outputs.
• Single 3.3V ± 0.3V power supply.
• MRS cycle with address key programs.
Latency (Access from column address)
Burst Length (1,2,4,8 & Full Page)
Data Sequence (Sequential & Interleave)
• All inputs are sampled at the positive going edge of
the system clock.
Transcend Information Inc.
1
H
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
Dimensions
Pin Identification
Side
Millimeters
Inches
A
133.35±0.40
5.250±0.016
B
65.67000
2.585000
C
23.49000
0.925000
D
8.89000
0.350000
E
15.80
0.622
F
19.80
G
H
Symbol
Function
SA0~SA12
Address Input
SBA0,SBA1
Select Bank Address
SD0~SD63
Data Input / Output.
SCB0~SCB7
Check bit (data-in / data-out)
0.780
SCK0
Clock Input.
43.00±0.20
1.693±0.008
SCKE0
Clock Enable Input.
1.27±0.10
0.050±0.004
/SCS0~SCS3
Chip Select Input.
/SRAS
Row Address Strobe
/SCAS
Column Address Strobe
/SWE
Write Enable
(Refer Placement)
SDQM0~SDQM7 Data (DQ) Mask
Transcend Information Inc.
2
SREGE
Register Enable
EA0~EA2
Address in EEPROM
SCL
Serial PD Clock
SDA
Serial PD Add/Data input/output
Vcc
+3.3 Voltage Power Supply
Vss
Ground
NC
No Connection
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
Pinouts:
Pin
Pin
Pin
Pin
No
Name
No
Name
01
Vss
43
Vss
02
DQ0
44
NC
03
DQ1
45
/CS2
04
DQ2
46
DQM2
05
DQ3
47
DQM3
06
Vcc
48
NC
07
DQ4
49
Vcc
08
DQ5
50
NC
09
DQ6
51
NC
10
DQ7
52
*CB2
11
DQ8
53
*CB3
12
Vss
54
Vss
13
DQ9
55
DQ16
14
DQ10
56
DQ17
15
DQ11
57
DQ18
16
DQ12
58
DQ19
17
DQ13
59
Vcc
18
Vcc
60
DQ20
19
DQ14
61
NC
20
DQ15
62
*Vref
21
*CB0
63
*CKE1
22
*CB1
64
Vss
23
Vss
65
DQ21
24
NC
66
DQ22
25
NC
67
DQ23
26
Vcc
68
Vss
27
/WE
69
DQ24
28
DQM0
70
DQ25
29
DQM1
71
DQ26
30
/CS0
72
DQ27
31
NC
73
Vcc
32
Vss
74
DQ28
33
A0
75
DQ29
34
A2
76
DQ30
35
A4
77
DQ31
36
A6
78
Vss
37
A8
79
*CLK2
38
A10/AP
80
NC
39
BA1
81
NC
40
Vcc
82
SDA
41
Vcc
83
SCL
42
CLK0
84
Vcc
* Please refer Block Diagram
Transcend Information Inc.
Pin
No
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
3
Pin
Name
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
*CB4
*CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
*/CS1
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
*CLK1
*A12
Pin
No
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Pin
Name
Vss
CKE0
*/CS3
DQM6
DQM7
*A13
Vcc
NC
NC
*CB6
*CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
*Vref
*REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
*CLK3
NC
SA0
SA1
SA2
Vcc
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
Block Diagram
CKE1
/CS1
/CS0
CKE0
DQM0
DQM4
DQM
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
U1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
/CS CKE
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
U10
DQM1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
U2
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
/CS CKE
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
U11
DQM2
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
U3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
U12
DQM3
U14
/CS CKE
/CS CKE
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U6
U15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
/CS CKE
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U7
U16
DQM7
DQM
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
U5
DQM6
DQM
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
/CS CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM5
DQM
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQM
/CS CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
U4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
DQM
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
U13
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
/CS CKE
/CS CKE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U8
U17
DQM5
DQM1
DQM
CB2
CB6
CB3
CB7
CB1
CB5
CB0
CB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/CS CKE
U9
VDD
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SA0~SA12
SBA0~SBA1
/SRAS
/SCAS
/SWE
SCKE0
SCS0
SCKE1
SCS1
/CS CKE
U18
U1~U18
U1~U18
U1~U18
U1~U18
U1~U18
U1~U9
U1~U9
U10~U18
U10~U18
U1~U18
R
E
G
I
S
T
E
R
SDQM0~SDQM7
U1~U18
VSS
Note:
1.U1~U18 are 16Mx8 SDRAM.
2.DQ-to-I/O wiring may be changed per nibble.
3.Unless otherwise noted , resister values are 10 Ohms±5%
P
L
L
CK0
U1~U18
Register
/RESET
EEPROM
SCL
WP
SDA
SA0 SA1 SA2
This technical information is based on industry standard data and tests believed to be reliable. However , Transcend makes no warranties, either
expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make
changes in specifications at any time without prior notice.
Transcend Information Inc.
4
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on VDD supply to Vss
Storage temperature
Power dissipation
Short circuit current
Operating Temperature
Note:
Symbol
VIN, VOUT
VDD, VDDQ
TSTG
PD
IOS
Value
-1.0~4.6
-1.0~4.6
-55~+150
18
50
Unit
V
V
°C
W
mA
TA
0~70
°C
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device
reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
3.0
3.3
3.6
V
Input high voltage
VIH
2.0
3.0
VDD+0.3
V
Input low voltage
VIL
-0.3
0
0.8
V
Output high voltage
VOH
2.4
V
Output low voltage
VOL
0.4
V
Input leakage current
IIL
-10
10
uA
Note
1
2
IOH=-2mA
IOL=2mA
3
Note: 1. VIH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Transcend Information Inc.
5
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V±200mV)
Parameter
Symbol
Min
Max
Unit
Input capacitance (SA0~SA12, SBA0~ SBA1)
CIN1
85
105
pF
Input capacitance (/SRAS, /SCAS, /SWE)
CIN2
85
105
pF
Input capacitance (SCKE0)
CIN3
50
65
pF
Input capacitance (SCLK0)
CIN4
40
45
pF
Input capacitance (/SCS0~/SCS3)
CIN5
30
40
pF
Input capacitance (SDQM0~SDQM7)
CIN6
25
30
pF
Data input/output capacitance (SD0~SD63)
COUT
10
15
pF
Data input/output capacitance (SCB0~SCB7)
COUT1
10
15
pF
DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter
Operating Current
(One Bank Active)
Symbol
ICC1
Precharge Standby Current ICC2P
in power-down mode
ICC2PS
ICC2N
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC2NS
Test Condition
CAS Latency
Burst Length =1
tRC≥tRC(min)
IOL=0mA
36
CKE & CLK≤VIL(max), tCC=∞
36
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
Input signals are changed one time during 30ns
CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Input signals are stable
ICC3PS
CKE & CLK≤VIL(max), tCC=∞
108
ICC3N
CKE≥VIH(min), /CS≥VIH(min), tCC=10ns
IOL= 0 mA
Page Burst
3
3
252
108
ICC4
mA
mA
CKE≤VIL(max), tCC=10ns
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC=∞
Note
288
ICC3P
Input signals are changed one time during 20ns
Unit
1,350
CKE≤VIL(max), tCC=10ns
Input signals are stable
Operating Current
(Bust Mode)
Value
mA
3
540
mA
3
450
1,530
mA
1
mA
2,3
tccD = 2CLKs
Refresh Current
tRC≥tRC(min)
ICC5
2,160
Self Refresh Current
ICC6
CKE≤0.2V
90
mA
3
Note: Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading cap.
Transcend Information Inc.
6
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter
AC Input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf=1/1
ns
1.4
V
See Fig. 2
Vtt=1.4V
3.3V
50 Ohm
1200 Ohm
Output
VOH (DC)=2.4V, IOH=-2mA
VOL (DC)=0.4V, I OL=2mA
Output
Z0=50 Ohm
50pF
50pF
870 Ohm
(Fig. 2) AC Output Load Circuit
(Fig. 1) DC Output Load Circuit
OPERATING AC PARAMETER (AC operating conditions unless otherwise noted)
Value
Unit
Note
Row active to row active delay
Parameter
tRRD(min)
Symbol
15
ns
1
/RAS to /CAS delay
tRCD(min)
20
ns
1
Row precharge time
tRP(min)
20
ns
1
tRAS(min)
45
ns
1
tRAS(max)
100
us
Row cycle time
tRC(min)
65
ns
1
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to row precharge
tRDL(min)
2
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Row active time
Number of valid output data
CAS latency=3
2
ea
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with
clock cycle time, and then rounding off to the next higher integer.
2. Minimum delay is required to complete write in Reg. DIMM
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
Transcend Information Inc.
7
4
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Refer to the individual component, not the whole module.
Parameter
Symbol
Value
Unit
Note
Min
Max
7.5
1000
ns
1
5.4
ns
1, 2
CLK cycle time
CAS latency=3
tCC
CLK to valid
output delay
CAS latency=3
tSAC
Output data
hold time
CAS latency=3
tOH
2.7
ns
1, 2
CLK high pulse width
tCH
2.5
ns
3
CLK low pulse width
tCL
2.5
ns
3
Input setup time
tSS
1.5
ns
3
Input hold time
tSH
0.8
ns
3
CLK to output in Low-Z
tSLZ
1
ns
2
ns
1
CLK to outputin Hi-Z
Note:
CAS latency=3
tSHZ
5.4
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)= 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Transcend Information Inc.
8
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
SIMPLIFIED TRUTH TABLE
COMMAND
SCKEn-1 SCKEn /SCS /SRAS /SCAS /SWE SDQM SBA0,1 SA10/AP SA12,A11,SA0~SA9
Note
Register
Mode Register Set
H
X
L
L
L
L
X
OP CODE
1,2
Refresh
Auto Refresh
Self
Refresh
H
L
L
L
H
X
X
L
H
L
H
X
H
X
H
H
X
H
X
H
H
X
L
X
Bank Active & Row Adders.
L
H
L
3
3
3
3
X
V
Read &
Column Address
H
X
L
H
L
H
X
V
Entry
Exit
Auto Precharge Disable
Auto Precharge Enable
Row Address
L
Column
4
H
Address
4, 5
(SA0~SA9,SA11)
Write &
Column Address
Burst Stop
Precharge
Clock Suspend or
Active Power Down
Precharge Power
Down Mode
Auto Precharge Disable
H
X
L
H
L
L
X
V
Auto Precharge Enable
Bank Selection
Both Banks
Entry
H
H
X
X
L
L
H
L
H
H
L
L
X
X
H
L
H
X
X
X
X
Exit
L
H
L
X
V
X
V
X
V
X
X
Entry
H
L
H
X
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
H
X
X
X
X
L
H
H
H
Exit
SDQM
No Operation Command
L
H
H
H
X
L
Column
4
H
Address
4, 5
(SA0~SA9,SA11)
X
V
X
L
H
6
X
X
X
X
V
X
X
X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code : Operand Code
SA0~SA11, SBA0~SBA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatically precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. SBA0~SBA1: Bank select address.
If both SBA0 and SBA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both SBA0 is “Low” and SBA1 is “High” at read, write, row active and precharge, bank B is selected.
If both SBA0 is “High” and SBA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both SBA0 and SBA1 are “High” at read, write, row active and precharge, bank D is selected.
If SA10/AP is “High” at row precharge, SBA0 and SBA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)
Transcend Information Inc.
9
7
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
Serial Presence Detect Specification
Serial Presence Detect
Byte No.
Function Described
Standard Specification
Vendor Part
0
Number of Bytes Written into Serial Memory
128bytes
80
1
Total Number of Bytes of S.P.D Memory
256bytes
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on this Assembly
13
0D
4
Number of Column Addresses on this Assembly
10
0A
5
Number of Module Banks on this Assembly
2 bank
02
6
Data Width of this Assembly
72bits
48
7
Data Width Continuation
0
00
8
Voltage Interface Standard of this Assembly
LVTTL3.3V
01
9
SDRAM Cycle Time (highest CAS latency)
7.5ns
75
10
SDRAM Access from Clock (highest CL)
5.4ns
54
11
DIMM configuration type (non-parity, ECC)
ECC
02
12
Refresh Rate Type
7.8us/Self Refresh
82
13
Primary SDRAM Width
X8
08
14
Error Checking SDRAM Width
X8
08
15
Min Clock Delay Back to Back Random Address
1 clock
01
16
Burst Lengths Supported
1,2,4,8 & Full page
8F
17
Number of banks on each SDRAM device
4 bank
04
18
CAS # Latency
3
04
19
CS # Latency
0 clock
01
20
Write Latency
0 clock
01
21
SDRAM Module Attributes
Registered DQM,
address/control inputs and
on-card PLL
16
16
22
SDRAM Device Attributes: General
Prec All, Auto Prec, R/W
Burst
0E
23
SDRAM Cycle Time (2nd highest CL)
0ns
00
24
SDRAM Access from Clock (2nd highest CL)
0ns
00
0ns
00
25
rd
SDRAM Cycle Time (3 highest CL)
rd
26
SDRAM Access from Clock (3 highest CL)
0ns
00
27
Minimum Row Precharge Time
20ns
14
28
Minimum Row Active to Row Activate
15ns
0F
29
Minimum RAS to CAS Delay
20ns
14
30
Minimum RAS Pulse Width
45ns
2D
31
Density of Each Bank on Module
256MB
40
32
Command/Address Setup Time
1.5ns
15
33
Command/Address Hold Time
0.8ns
08
34
Data Signal Setup Time
1.5ns
15
35
Data Signal Hold Time
0.8ns
08
Transcend Information Inc.
10
168PIN PC133 Registered DIMM
512MB With 32M X8 CL3
TS64MLR72V6F
36-61
Superset Information
-
00
62
SPD Data Revision Code
JEDEC 2
02
63
Checksum for Bytes 0-62
-
E9
Transcend
7F, 4F
T
54
64-71
72
Manufacturers JEDEC ID Code per JEP-108E
Manufacturing Location
54 53 36 34 4D 4C
73-90
Manufacturers Part Number
TS64MLR72V6F
52 37 32 56 36 46
20 20 20 20 20 20
91-92
Revision Code
93-94
95-98
99-125
-
0
Manufacturing Date
By Manufacturer
Variable
Assembly Serial Number
By Manufacturer
Variable
Manufacturer Specific Data
-
0
126
Intel Specification Frequency
-
64
127
Intel Specification CAS# Latency/Clock Signal Support
CL=3 Clock 0
84
128~
Unused Storage Locations
Open
FF
Transcend Information Inc.
11
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