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Description

The JM334S643A-75 is a 32M x 64bits Synchronous

Dynamic RAM high-density for PC-133. The

JM334S643A-75 consists of 8pcs CMOS 32Mx8 bits

Synchronous DRAMs in TSOP-II 400mil packages and a 2048 bits serial EEPROM on a 168-pin printed circuit board. The JM334S643A-75 is a Dual In-Line Memory

Module and is intended for mounting into 168-pin edge connector sockets.

Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operation frequencies, programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features

• Performance Range: PC-133

• Conformed to JEDEC Standard 4 clocks.

• Burst Mode Operation.

• Auto and Self Refresh.

• CKE Power Down Mode.

• DQM Byte Masking (Read/Write)

• Serial Presence Detect (SPD) with serial EEPROM

• LVTTL compatible inputs and outputs.

• Single 3.3V ± 0.3V power supply.

• MRS cycle with address key programs.

Latency (Access from column address)

Burst Length (1,2,4,8 & Full Page)

Data Sequence (Sequential & Interleave)

• All inputs are sampled at the positive going edge of

the system clock.

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

Placement

F

E

H

G

PCB: 09-7303

E

D

C

B

I

A

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Dimensions

Side Millimeters Inches

A 133.35

±0.40 5.250±0.016

B 65.67

000 2.585

000

C 23.49

000 0.925

000

D 8.89

000 0.350

000

E 3.00

000 0.118

000

F 29.21

±0.20

0 1.150

±0.008

0

G 19.78

00 0.778

000

H 15.78 0.621

I 1.27

±0.10

0.050

±0.004

(Refer Placement)

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

Pin Identification

Symbol

A0~A12, BA0,BA1

DQ0~DQ63

CLK0, CLK2

CKE0

/CS0, /CS2

/RAS

/CAS

/WE

DQM0~DQM7

Function

Address input

Data Input / Output.

Clock Input.

Clock Enable Input.

Chip Select Input.

Row Address Strobe

Column Address Strobe

Write Enable

Data (DQ) Mask

SA0~SA2

SCL

SDA

Vcc

Address in EEPROM

Serial PD Clock

Serial PD Add/Data input/output

+3.3 Volt Power Supply

Vss

NC

Ground

No Connection

(Refer Block Diagram AND Pinouts)

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Pinouts:

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

Pin

No

Pin

Name

Pin

No

Pin

Name

Pin

No

Pin

Name

Pin

No

Pin

Name

01 Vss

02 DQ0

03 DQ1

04 DQ2

05 DQ3

06 Vcc

07 DQ4

08 DQ5

43 Vss

44 NC

85 Vss 127 Vss

86 DQ32 128 CKE0

45 /CS2 87 DQ33 129 NC

46 DQM2 88 DQ34 130 DQM6

47 DQM3 89 DQ35 131 DQM7

48 NC 90 Vcc 132 NC

49 Vcc

50 NC

91 DQ36

92 DQ37

133 Vcc

134 NC

09 DQ6

10 DQ7

11 DQ8

12 Vss

51 NC

52 NC

53 N

54 Vss

93 DQ38 135 NC

94 DQ39 136 NC

95 DQ40 137 NC

96 Vss 138 Vss

13 DQ9 55 DQ16 97 DQ41 139 DQ48

14 DQ10 56 DQ17 98 DQ42 140 DQ49

15 DQ11 57 DQ18 99 DQ43 141 DQ50

16 DQ12 58 DQ19 100 DQ44 142 DQ51

17 DQ13 59 Vcc

18 Vcc 60 DQ20

101 DQ45

102 Vcc

143 Vcc

144 DQ52

19 DQ14 61 NC

20 DQ15 62 NC

103 DQ46

104 DQ47

145 NC

146 NC

21 NC

22 NC

23 Vss

24 NC

63 NC

64 Vss

65 DQ21

66 DQ22

105 NC

106 NC

107 Vss

108 NC

147 NC

148 Vss

149 DQ53

150 DQ54

25 NC

26 Vcc

67 DQ23 109 NC

68 Vss 110 Vcc

151 DQ55

152 Vss

27 /WE 69 DQ24 111 /CAS 153 DQ56

28 DQM0 70 DQ25 112 DQM4 154 DQ57

29 DQM1 71 DQ26 113 DQM5 155 DQ58

30 /CS0 72 DQ27 114 NC 156 DQ59

31 NC

32 Vss

73 Vcc

74 DQ28

115 /RAS

116 Vss

157 Vcc

158 DQ60

33 A0

34 A2

35 A4

36 A6

37 A8

38 A10

39 BA1

40 Vcc

75 DQ29

76 DQ30

77 DQ31

78 Vss

79 CLK2

80 NC

81 NC

121 A9

122 BA0

123 A11

82 SDA 124 Vcc

41 Vcc 83 SCL

42 CLK0 84 Vcc

117 A1

118 A3

119 A5

120 A7

125 NC

126 A12

159 DQ61

160 DQ62

161 DQ63

162 Vss

163 NC

164 NC

165 SA0

166 SA1

167 SA2

168 Vcc

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JM334S643A-75-- Block Diagram

A0~A12,

BA0,BA1

DQ0~DQ63

/RAS

/CAS

/WE

/CS0

CKE0

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM0

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM1

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM2

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM3

/CS2

CLK0

CLK2

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM4

SCL

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM5

Serial

EEPROM

SCL SDA

A0 A1 A2

SA0 SA1 SA2

SDA

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM6

A0~A12,

BA0,BA1

DQ0~DQ7

/RAS

32Mx8

SDRAM

/CAS

/WE

/CS

CKE

DQM7

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes in specifications at any time without prior notice.

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256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

ABSOLUTE MAXIMUM RATINGS

Parameter

Voltage on any pin relative to Vss

Voltage on V DD supply to Vss

Storage temperature

Symbol Value

V IN , V OUT -1.0~4.6

V DD , V DDQ -1.0~4.6

T STG -55~+150

Unit

V

V

°C

Power dissipation

Short circuit current I

P D

OS

8

50

Mean time between failure MTBF 50

Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

W mA

Years

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

Recommended operating conditions (Voltage referenced to Vss = 0V, T A = 0 to 70 °C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage

Input high voltage

Input low voltage

Output high voltage

Output low voltage

Input leakage current

V DD 3.0 3.3 3.6 V

V IH 2.0 3.0 DD +0.3

V 1

V IL -0.3 0 0.8 V 2

V OH 2.4 - - V IOH=-2mA

V OL - - 0.4 V IOL=2mA

I

LI

-10 - 10 uA

Note: 1. V IH (max) = 5.6V AC .The overshoot voltage duration is ≤ 3ns.

3

2. V IL (min) = -2.0V AC .The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V

IN

≤ V

DDQ.

Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

CAPACITANCE (V DD =3.3V,T A = 23 °C, f = 1MHz,V

REF =1.4V+ 200mV)

Parameter

Input capacitance (A 0 ~A 12 , BA 0 ~ BA 1 )

Input capacitance (/RAS, /CAS, /WE)

Input capacitance (CKE0)

Input capacitance (CLK0, CLK2)

Input capacitance (/CS0, /CS2)

Input capacitance (DQM0~DQM7)

Data input/output capacitance (DQ0~DQ63)

Symbol

C IN1

C IN2

C IN3

C IN4

C IN5

C IN6

C OUT1

Min

16

8

6

30

30

30

25

Max

25

10

8

40

40

40

30

Unit pF pF pF pF pF pF pF

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256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, T A = 0 to 70 °C)

Parameter Symbol Test Condition CAS Latency

Operating Current

(One Bank Active)

I CC1

Burst Length =1 t RC

≥t

RC (min)

I OL =0mA

Value (Typ) Unit Note

Precharge Standby Current in power-down mode

I CC2 P CKE ≤V

IL( max), t CC =10ns 16

I CC2 PS CKE & CLK ≤V

IL( max), t CC =∞ 16

I CC2 N

Precharge Standby Current in non power-down mode

I CC2 NS

CKE ≥V

IH( min), /CS ≥V

IH( min), t CC =10ns

Input signals are changed one time during 30ns

CKE ≥V

IH( min), CLK ≤V

IL( max), t CC =∞

Input signals are stable

160

80 mA

Active Standby Current in power-down mode

Active Standby Current in non power-down mode

(One Bank Active)

I CC3 P CKE ≤V

IL( max), t CC =10ns

I CC3 PS CKE & CLK ≤V

IL( max), t CC =∞

I CC3 N CKE ≥V

IH( min), /CS ≥V

IH( min), t CC =10ns

Input signals are changed one time during 30ns

48

48

240 mA mA

Operating Current

(Bust Mode)

Refresh Current I

I

I CC3 NS CKE ≥V

IH( min), CLK ≤V

IL( max), t CC =∞

Input signals are stable

CC4

CC5

I OL= 0 mA

Page Burst

tcc

D = 2CLKs t RC

≥t

RC (min)

200

1600 mA 2

Self Refresh Current I CC6 CKE ≤0.2V

Note: 1. Measured with outputs open.

2. Refresh period is 64ms.

3. Unless otherwise noticed, input swing level is CMOS (V IH /V IL =V DDQ /V SSQ )

C 24

L 12 mA

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256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

AC OPERATING TEST CONDITIONS (V DD = 3.3V

±0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC Input levels (V IH /V IL ) 2.4/0.4

Input timing measurement reference level 1.4 V

Input rise and fall time

Output timing measurement reference level

Output load condition

3.3V

tr/tf=1/1

1.4

See Fig. 2

Vtt=1.4V

ns

V

50 Ohm

Output

870 Ohm

1200 Ohm

50pF

V

OH

(DC)=2.4V, I

OH

=-2mA

V

OL

(DC)=0.4V, I

OL

=2mA

Output Z0=50 Ohm

50pF

(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter

Row active to row active delay

/RAS to /CAS delay

Symbol

Value

Unit Note t RRD (min) 15 1 t RCD (min) 20 1

Row precharge time t RP (min) 20 1

Row active time

Row cycle time t RAS (min) 45 1 t RAS (max) 100 t RC (min) 65 1

Last data in to new col. Address delay t CDL (min) 1 2

Last data in to row precharge

Last data in to Active delay

Last data in to burst stop

Col. address to col. address delay t t t RDL (min) 2 2 t DAL 2CLK+t RP

BDL

CCD

-

(min) 1

(min) 1

2

3

Number of valid output data

CAS latency=3 2

Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with

clock cycle time, and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop. ea 4

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256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Refer to the individual component, not the whole module.

Parameter Symbol Min Max Unit Note

CLK cycle time

CLK to valid output delay

Output data hold time

CAS latency=3

CAS latency=3

CAS latency=3 t CC t SAC t OH

7.5 1000 ns 1

2.7 ns 2

CLK high pulse width

CLK low pulse width

Input setup time

Input hold time

CLK to output in Low-Z

CLK to output in Hi-Z

CAS latency=3 t CH 2.5 t CL 2.5 ns 3 ns 3 t SS 1.5 ns 3 t SH 0.8 ns 3 t t SLZ 1 ns 2

SHZ 5.4 ns

Note: 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5) ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)= 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered,

i.e., [(tr + tf)/2-1]ns should be added to the parameter.

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SIMPLIFIED TRUTH TABLE

COMMAND

Register Mode Register Set

Refresh Auto Refresh

Self

Refresh

Bank Active & Row Addr.

Entry

Exit

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

CKEn-1 CKEn /CS /RAS /CAS /WE DQM BA 0,1 A 10 /AP

A 11 ,A 12 ,

A 0 ~A 9

Note

H X L L L L X 1,2

H

H

L

L L L H X X

X X

3

3

3

3

H X L L H H X V Row

Read &

Column

Address

Write &

Column

Address

Burst Stop

Precharge

Auto Precharge Disable

Auto Precharge Enable

Auto Precharge Disable

Auto Precharge Enable

Bank Selection

Both Banks

Entry

H X L H L H X V

L 4

Address

H (A

0

~A

9

) 4, 5

H X L H L L X V

L 4

Address

H (A

0

~A

9

) 4, 5

H X L H H L X

H X L L H L X

X

V L

X H

X

6

Clock Suspend or

Active Power Down

Exit

L V V V

X

L H X X X X X

X

Precharge Power

Down Mode

Entry

H X X X

H L

L H H H

X

X

Exit

H X X X

L H

L V V V

X

No Operation Command

H X X X

H X

L H H H

X X

(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)

Note: 1. OP Code: Operand Code

A 0 ~A 12 , BA 0 ~BA 1 : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.

The automatically precharge without row precharge command is meant by “Auto”.

Auto/self refresh can be issued only at both banks precharge state.

4. BA 0 ~BA 1 : Bank select address.

If both BA

0 and BA

1 are “Low” at read, write, row active and precharge, bank A is selected.

If both BA

0

is “Low” and BA

1

is “High” at read, write, row active and precharge, bank B is selected.

If both BA

0

is “High” and BA

1

is “Low” at read, write, row active and precharge, bank C is selected.

If both BA

0 and BA

1 are “High” at read, write, row active and precharge, bank D is selected.

If A

10

/AP is “High” at row precharge, BA

0

and BA

1

are ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command cannot be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),

but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

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Serial Presence Detect Specification

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

Byte No.

12

13

14

15

8

9

10

11

4

5

6

7

0

1

2

3

16

17

18

19

20

21

22

27

28

29

30

23

24

25

26

31

32

33

34

35

62

63

# of Bytes Written into Serial Memory

Total # of Bytes of S.P.D Memory

Fundamental Memory Type

# of Row Addresses on this Assembly

# of Column Addresses on this Assembly

# of Module Banks on this Assembly

Data Width of this Assembly

Data Width Continuation

Voltage Interface Standard of this Assembly

SDRAM Cycle Time (highest CAS latency)

SDRAM Access from Clock (highest CL)

DIMM configuration type (non-parity, ECC)

Refresh Rate Type

Primary SDRAM Width

Error Checking SDRAM Width

Min Clock Delay Back to Back Random Address

Burst Lengths Supported

Number of banks on each SDRAM device

CAS # Latency

CS # Latency

Write Latency

SDRAM Module Attributes

SDRAM Device Attributes: General

SDRAM Cycle Time (2 nd

highest CL)

SDRAM Access from Clock (2 nd

highest CL)

SDRAM Cycle Time (3 rd

highest CL)

SDRAM Access from Clock (3 rd

highest CL)

Minimum Row Precharge Time

Minimum Row Active to Row Activate

Minimum RAS to CAS Delay

Minimum RAS Pulse Width

Density of Each Bank on Module

Command/Address Setup Time

Command/Address Hold Time

Data Signal Setup Time

Data Signal Hold Time

SPD Data Revision Code

Checksum for Bytes 0-62

64-71 Manufacturers JEDEC ID Code per JEP-108E

73-90

Serial Presence Detect

Function Described

Manufacturers Part Number

Standard

Specification

128bytes

256bytes

SDRAM

13

10

1 bank

64bits

0

LVTTL3.3V

7.5ns

5.4ns

None

7.8us/Self Refresh

X8

64bit

1 clock

1,2,4,8 & Full page

4 bank

3

0 clock

0 clock

Non Buffer

Prec All, Auto Prec,

R/W Burst

7.5

5.4

-

-

20ns

16ns

20ns

45ns

256MB

1.5ns

0.8ns

1.5ns

0.8ns

-

JEDEC2

39

Transcend

-

-

-

Vendor Part

82

08

00

01

01

75

54

00

80

08

04

0D

0A

01

40

00

8F

04

04

01

01

00

0E

75

54

00

00

14

0F

14

2D

40

15

08

15

08

00

02

C0

7F, 4F

00

00

00

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95-98 Assembly Serial Number

99-125 Manufacturer Specific Data

126 Intel Specification Frequency

127 Intel Specification CAS# Latency/Clock Signal Support

128~ Unused Storage Locations

256MB 168PIN PC133 CL3

SDRAM DIMM With 32M X 8 3.3VOLT

-

-

-

-

CL=3 Clock 0~3

Open

00

00

0

64

F4

FF

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