TSCS454

DATASHEET
TSCS454
PORTABLE AUDIO CONSUMER CODEC
DESCRIPTION
FEATURES
The TSCS454 is a low-power, high-fidelity CODEC with
integrated fixed audio DSP’s targeted to portable
applications such as portable games, personal navigation
devices, and personal audio appliances.
•
High fidelity 24-bit CODEC
•
•
•
Audio Output Processing DSP Engine
•
•
•
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In addition to a high-fidelity low-power CODEC, the device
integrates a fixed audio DSP, stereo speaker amplifier,
mono earpiece amplifier, and a true cap-less stereo
headphone amplifier.
•
•
Portable Gaming Devices
•
Personal Media Players
•
Multimedia handsets
•
Digital Cameras/Camcorders
PLL
Internal
Audio
Clocks
MCLK2
LIN1
LIN2
LIN3
M
U
X
LINE/MIC
INPUTS
RIN1
RIN2
RIN3
M
U
X
GPIO’s
ADC
To MIC
Detection
MICBIAS2
DMIC1
DMIC2
DMICCLK2
CLK
M
U
X
INT
2
I2C
ASRC3
P
R
O
C
E
S
S
O
R
2
4
S
O
U
R
C
E
S
E
L
E
C
T
TRIM
I2S/TDM/PCM
IN1
S
W
I
T
C
H
ASRC3
2
2
OUT2: I2S/
TDM/PCM
1
DSP
Class D
PWM
BTL
DAC
40 mW output power (16Ώ)
Microphone/line-in interface
•
•
•
•
Analog/ Digital microphone or line-in inputs
Automatic level control
Dual Mic bias generators
Low power with built in power management
•
•
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EAR/SUB
Out
1.6 V CODEC supports 1Vrms
Very low standby and no-signal power consumption
1.6V digital / 1.7V analog supply for low power
Line Out L
2
HP L
(Cap-less)
DSP
Line Out R
DAC
•
Commercial temperature range
•
Package options
•
68 pins 8 x8 QFN
HP R
(Cap-less)
I2S IN3
RING2
HP
Detect
Charge
Pump
HPDET
SLEEVE
MIC
Detect
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Mono Earpiece Amplifier Speaker Driver
•
SPK Out L
BTL
DAC
DSP
40 mW output power (16Ώ)
Charge-pump allows true ground centered outputs
Headphone/Headset detection logic
Global Headset detection logic
SNR (A-weighted no active signal) -122db
SNR (A-weighted -60db active signal) -102db
•
OUT3: I2S/
TDM/PCM
I2S IN2
©2014 TEMPO SEMICONDUCTOR, INC.
y
ar
M
U
X
SPK Out R
1
On-chip Class-H true cap-less headphone driver
•
•
•
•
•
•
Separate cap-less Stereo Line Outputs for Docking
BTL
2
DSP
2
3W/channel 4Ώ
DDX Technology achieves low EMI and high efficiency
Constant output power mode
Anti-Pop circuitry
Filter-less architecture reduces BOM cost
•
OUT1: I2S /
TDM/PCM
TRIM
DSP
•
M
U
X
M
U
X
2
I
N
P
U
T
ADC
VREF
DMICCLK1
el
Pr
XTAL OUT
DDX™ Digital Speaker Driver
•
•
•
•
•
•
2
XTAL/MCLK IN
•
in
Portable Audio Devices
Any 1 port can support
- Asynchronous Sample rate conversion
All port can support PCM mode
1 port can support Intel TDM mode
2 ports can support Bluetooth TDM
•
•
•
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TARGET APPLICATIONS
•
3 I2S inputs and outputs
•
The device has been designed with rapid customization in
mind. Tempo is able to rapidly provide varying levels of
integration, additional audio processing, according to the
needs of large markets or customers.
UltraBook, Laptops, Slates, Tablets
3D stereo enhancement
Parametric equalizers
Programmable compressor/limiter
Psychoacoustic Bass and Treble enhancement
processing
3rd party algorithms
•
Beyond high-fidelity for portable systems, the device offers
an enriched “audio presence” through built-in audio
processing capability.
•
5 DAC 102dB SNR
4 ADC 94dB SNR
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TSCS454
TSCS454
Portable Audio Consumer Codec
1. OVERVIEW ................................................................................................................................ 9
1.1. Block Diagram ...................................................................................................................................9
1.2. Audio Outputs ..................................................................................................................................10
1.3. Audio Inputs .....................................................................................................................................10
1.4. Digital Audio Interface ......................................................................................................................10
1.5. On-Chip PLLs ..................................................................................................................................10
2. POWER MANAGEMENT ........................................................................................................ 11
2.1. Registers .........................................................................................................................................11
2.1.1. Power Management Register 0 .........................................................................................11
2.1.2. Power Management Register 1 ........................................................................................12
2.1.3. Power Management Register 2 ........................................................................................13
2.1.4. Power Management Register 3 ........................................................................................13
2.1.5. Power Management Register 4 .........................................................................................14
3. OUTPUT AUDIO PROCESSING ............................................................................................. 15
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3.1. DC Removal ....................................................................................................................................17
3.2. Volume Control Functions ...............................................................................................................18
3.3. Master Volume Control ....................................................................................................................19
3.4. Effects Processing ...........................................................................................................................20
3.4.1. Effects Control (xFXCTL) Register .....................................................................................20
3.4.2. Stereo Depth (3D) Enhancement .......................................................................................20
3.4.3. Psychoacoustic Bass Enhancement ..................................................................................21
3.4.4. Psychoacoustic Treble Enhancement ................................................................................21
3.5. Multi-band Compressor ....................................................................................................................22
3.5.1. Multi-band_Compressor Registers .....................................................................................22
3.6. Parametric Equalizer .......................................................................................................................30
3.6.1. Prescaler & Equalizer Filter ...............................................................................................30
3.6.2. EQ Filter Register ..............................................................................................................31
3.6.3. Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM .......................................34
3.7. Gain, Limiting, and Dynamic Range Control ....................................................................................38
3.7.1. Limiter Compressor and Expander ....................................................................................39
3.7.2. Configuration .....................................................................................................................42
3.7.3. Controlling Parameters ......................................................................................................42
3.7.4. Compressor/Limiter/Expander Control Registers ...............................................................43
3.8. Mute and De-Emphasis and Phase Inversion ..................................................................................49
3.9. Output Post Processing ...................................................................................................................50
3.9.1. Interpolation and Filtering ..................................................................................................50
3.10 Analog Audio Outputs .....................................................................................................................50
3.10.1. Headphone Output ...........................................................................................................51
3.10.2 Speaker Outputs ...............................................................................................................53
3.10.3. Earpiece Output ...............................................................................................................54
3.10.4. Class D Audio Processing ...............................................................................................55
3.11. Thermal Shutdown .........................................................................................................................61
3.11.1. Algorithm description: .....................................................................................................61
3.11.2. Thermal Trip Points. ........................................................................................................61
3.11.3. Instant Cut Mode ..............................................................................................................62
3.11.4. Thermal Shutdown Registers ...........................................................................................62
3.12. Short Circuit Protection .................................................................................................................64
3.13. Analog Input to DAC/Headphone Bypass Path ............................................................................64
3.14. Headphone Switch ........................................................................................................................64
3.14.1. Headphone Switch Control Register ...............................................................................65
4. ANALOG INPUT AUDIO PROCESSING ................................................................................ 66
4.1. Overview ..........................................................................................................................................67
4.2. Analog Audio Inputs .........................................................................................................................67
4.3. Input Processor Analog Input Control ..............................................................................................67
4.3.1. Channel 0 Input Audio Control Register ...........................................................................68
4.3.2. Channel 1 Audio Input Control Register ...........................................................................68
4.3.3. Channel 2 Audio Input Control Register ...........................................................................69
4.3.4. Channel 3 Audio Input Control Register ...........................................................................69
4.4. Input Processor Digital Processing ..................................................................................................70
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TSCS454
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Portable Audio Consumer Codec
4.4.1. Input Processor Control Register 0 ...................................................................................70
4.4.2. Input Processor Control Register 1 ...................................................................................71
4.5. Microphone Bias ..............................................................................................................................71
4.6. Programmable Gain Control ............................................................................................................72
4.6.1. PGA Control Registers .....................................................................................................73
4.6.2. PGA Zero Cross Control Register .....................................................................................74
4.7. ADC Digital Filter .............................................................................................................................74
4.8. Input Channel Volume Control .........................................................................................................75
4.8.1. CH0, CH1 Input Volume Control Registers ......................................................................76
4.8.2. CH2, CH3 Input Volume Control Register .........................................................................76
4.9. Automatic Level Control (ALC) ........................................................................................................76
4.9.1. ALC Operation ..................................................................................................................77
4.9.2. ALC Control Registers .......................................................................................................78
4.9.3. Peak Limiter .......................................................................................................................79
4.9.4. Input Threshold ..................................................................................................................79
4.9.5 Digital Microphone Support .................................................................................................80
5. DIGITAL AUDIO INPUT-OUTPUT .......................................................................................... 85
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5.1. PCM Interfaces ................................................................................................................................86
5.1.1. PCM(I2S) Audio Input Interface Mapping ..........................................................................87
5.1.2. PCM(I2S) Audio Output Interface Mapping .......................................................................87
5.1.3. PCM control Register .........................................................................................................87
5.2. ASRC Input/Output Volume Controls ...............................................................................................88
5.2.1. Output Data Mux Control Register .....................................................................................88
5.2.2. Output Data Mux Control Register .....................................................................................89
5.2.3. Output Data Mux Control Register .....................................................................................89
5.2.4. I2S Input Volume Control Register ....................................................................................90
5.2.5. Volume Update Register ....................................................................................................91
5.3. Audio Interface Clocking Options ....................................................................................................91
5.4. Master and Slave Mode Operation ..................................................................................................91
5.5. Audio Data Formats .........................................................................................................................91
5.6. Digital Audio Interface Registers ......................................................................................................95
5.6.1. LRCK and BLCK Mode Control .........................................................................................95
5.6.2. Bit Clock Mode .................................................................................................................101
5.6.3. SCLK Underflow and Overflow ........................................................................................102
5.6.4. Audio Interface Output Tri-state Control .........................................................................102
5.6.5. I2S Pin Control 0 Register ...............................................................................................103
5.6.6. Pin Control 1 Register .....................................................................................................104
5.6.7. I2S Pin Control 2 Register ...............................................................................................104
5.6.8. TDM Control 0 Register ...................................................................................................105
5.6.9. TDM Control 1 Register ...................................................................................................105
5.7. ASRC's ..........................................................................................................................................106
5.7.1. Supported Input Sample Rates ........................................................................................106
5.7.2. ASRC Output Rates .........................................................................................................106
5.7.3. ASRC Control .................................................................................................................107
6. HOST CONTROL, I2C, 2-WIRE CONTROL INTERFACE .................................................... 108
6.1. I2C Device Addressing ..................................................................................................................109
6.2. Page Register Write Cycle .............................................................................................................110
6.3. Page Register Burst Write Cycle ...................................................................................................111
6.4. Page Register Read Cycle ............................................................................................................111
6.5. Page Register Burst Read Cycle ...................................................................................................112
6.6. GPIO’s ...........................................................................................................................................112
6.6.1. GPIO Usage Summary ....................................................................................................112
6.6.2. GPIO Control Registers ...................................................................................................113
6.7. Register Reset ...............................................................................................................................114
6.8. Interrupts ........................................................................................................................................114
6.8.1 nINT/nTEST - Interrupt/Test Pin ......................................................................................114
6.8.2 Interrupt Logic ...................................................................................................................114
6.8.3 Interrupt Sources ..............................................................................................................115
6.8.4. Interrupt Control Registers ...............................................................................................116
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TSCS454
TSCS454
Portable Audio Consumer Codec
6.9. Reset Pin .......................................................................................................................................117
7. CLOCK GENERATION ......................................................................................................... 118
7.1. On-Chip PLLs ................................................................................................................................118
7.2. System Clock Generation ..............................................................................................................119
7.2.1 PLL Dividers ......................................................................................................................119
7.2.2 PLL Power Down Control ..................................................................................................124
7.2.3 Audio Clock Generation ....................................................................................................124
8. HEADPHONE AND COMBO JACK DETECTION ................................................................ 132
8.1. Headphone Switch and Plug Insertion Detection ...........................................................................132
8.2 Microphone Detection .....................................................................................................................134
8.2.1 De-Glitch ...........................................................................................................................135
8.2.2 Plug Insertion Before Headset Detection Is Enabled ........................................................135
8.2.3 Headset Type Detection and Microphone Selection Process ...........................................139
8.2.4 Headphone/Headset Control Registers ............................................................................140
8.2.5 Lanyard Switch (“Turbo Button”) Support .........................................................................142
8.2.6 Lanyard Button Support Registers ....................................................................................144
9. CHARACTERISTICS ............................................................................................................. 145
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9.1. Audio Fidelity .................................................................................................................................145
9.2. Electrical Specifications .................................................................................................................145
9.2.1. Absolute Maximum Ratings: ............................................................................................145
9.3. Recommended Operating Conditions ............................................................................................145
9.4. Characteristics ..............................................................................................................................146
9.4.1. PLL Section DC Electrical Characteristics .......................................................................148
9.4.2. PLL Section AC Timing Specs .........................................................................................148
9.4.3. Typical Power Consumption ............................................................................................149
9.4.4. SNR at Sample Rates other than 48KHz .........................................................................149
9.5. PLL Section DC Electrical Characteristics .....................................................................................150
9.6. PLL Section AC Timing Specs .......................................................................................................150
9.7. Typical Power Consumption ..........................................................................................................151
9.8. Low Power Mode Power Consumption ..........................................................................................151
10. REGISTER MAP SUMMARY TABLE ................................................................................. 152
11. PIN CONFIGURATION AND DESCRIPTION ..................................................................... 162
11.1. 68-Pin QFN ..................................................................................................................................162
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12. TSCS454PACKAGE INFORMATION ................................................................................. 166
12.1. 68-Pin QFN Package Drawing .....................................................................................................166
13. TSCS454PACKAGE INFORMATION ................................................................................. 167
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13.1. Package Drawing .........................................................................................................................167
14. ORDERING INFORMATION ............................................................................................... 168
15. DISCLAIMER ....................................................................................................................... 168
16. DOCUMENT REVISION HISTORY ..................................................................................... 169
TSI CONFIDENTIAL
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TSCS454
Portable Audio Consumer Codec
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Table 1. PWRM0 Register .............................................................................................................................11
Table 2. PWRM1 Register .............................................................................................................................12
Table 3. PWRM2 Register .............................................................................................................................13
Table 4. PWRM3 Register .............................................................................................................................13
Table 5. PWRM4 Register .............................................................................................................................14
Table 6. DSP Processing Cycles ...................................................................................................................16
Table 7. DCCON Register ..............................................................................................................................17
Table 8. OVOLCTLU Register .......................................................................................................................18
Table 9. MUTEC Register ..............................................................................................................................18
Table 10. MVOLL/MVOLR Register ...............................................................................................................19
Table 11. xFXCTL Register ............................................................................................................................20
Table 12. xMBCEN Register ..........................................................................................................................22
Table 13. xMBCCTL Register ........................................................................................................................23
Table 14. xMBCMUG1 Register .....................................................................................................................23
Table 15. xMBCTHR1 Register ......................................................................................................................24
Table 16. xMBCRAT1 Register ......................................................................................................................24
Table 17. xMBCATK1L Register ....................................................................................................................24
Table 18. xMBCATK1H Register ...................................................................................................................25
Table 19. xMBCREL1L Register ....................................................................................................................25
Table 20. xMBCREL1H Register ...................................................................................................................25
Table 21. xMBCMUG2 register ......................................................................................................................26
Table 22. xMBCTHR2 Register ......................................................................................................................26
Table 23. xMBCRAT2 Register ......................................................................................................................26
Table 24. xMBCATK2L Register ....................................................................................................................26
Table 25. xMBCATK2H Register ...................................................................................................................27
Table 26. xMBCREL2L Register ....................................................................................................................27
Table 27. xMBCREL2H Register ...................................................................................................................27
Table 28. xMBCMUG3 Register .....................................................................................................................28
Table 29. xMBCTHR3 Register ......................................................................................................................28
Table 30. xMBCRAT3 Register ......................................................................................................................28
Table 31. xMBCATK3L Register ....................................................................................................................28
Table 32. xMBCATK3H Register ...................................................................................................................29
Table 33. xMBCREL3L Register ....................................................................................................................29
Table 34. xMBCREL3H Register ...................................................................................................................29
Table 35. xEQFILT Registers .........................................................................................................................31
Table 36. xCRWDL Register ..........................................................................................................................31
Table 37. xCRWDM Register .........................................................................................................................32
Table 38. xCRWDH Register .........................................................................................................................32
Table 39. xCRRDL Register ...........................................................................................................................32
Table 40. xCRRDM Register ..........................................................................................................................32
Table 41. xCRRDH Register ..........................................................................................................................33
Table 42. xCRADD Register ..........................................................................................................................33
Table 43. xCRS Register ...............................................................................................................................33
Table 44. EQ Coefficient RAM Addresses For Speaker and DAC Channels ................................................36
Table 45. EQ Coefficient RAM Addresses For Earpiece Channel .................................................................37
Table 46. EQCRAM Multi-Band Compressor/Bass/Treble/3D Addresses .....................................................38
Table 47. xCLECTL Register .........................................................................................................................43
Table 48. xCLEMUG Register ........................................................................................................................43
Table 49. xCOMPTHR Register .....................................................................................................................43
Table 50. xCOMPRAT Register .....................................................................................................................44
Table 51. xCOMPATKL Register ...................................................................................................................44
Table 52. xCOMPATKH Register ...................................................................................................................44
Table 53. xCOMPRELL Register ...................................................................................................................45
Table 54. xCOMPRELH Register ...................................................................................................................45
Table 55. xLIMTH Register ............................................................................................................................45
Table 56. xLIMTGT Register ..........................................................................................................................45
Table 57. xLIMATKL Register ........................................................................................................................46
Table 58. xLIMATKH Register .......................................................................................................................46
Table 59. xLIMRELL Register ........................................................................................................................46
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©2014 TEMPO SEMICONDUCTOR, INC.
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TSCS454
TSCS454
Portable Audio Consumer Codec
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Table 60. xLIMRELH Register .......................................................................................................................47
Table 61. xEXPTHR Register ........................................................................................................................47
Table 62. xEXPRAT Register .........................................................................................................................47
Table 63. xEXPATKL Register ......................................................................................................................48
Table 64. xEXPATKH Register ......................................................................................................................48
Table 65. xEXPRELL Register .......................................................................................................................48
Table 66. xEXPRELH Register ......................................................................................................................49
Table 67. HPVOLL/HPVOLR Register ...........................................................................................................51
Table 68. DACCTL Register ..........................................................................................................................52
Table 69. SPKVOLL/ SPKVOLR Registers ....................................................................................................53
Table 70. SPKCTL Register ...........................................................................................................................53
Table 71. SUBVOLl Register .........................................................................................................................54
Table 72. SUBCTL Register ...........................................................................................................................54
Table 73. COP0 Register ...............................................................................................................................57
Table 74. COP1 Register ...............................................................................................................................58
Table 75. COPSTAT Register ........................................................................................................................58
Table 76. PWM0 Register ..............................................................................................................................59
Table 77. PWM1 Register ..............................................................................................................................59
Table 78. PWM3 Register ..............................................................................................................................60
Table 79. THERMTS Register .......................................................................................................................62
Table 80. THERMSPK Register .....................................................................................................................63
Table 81. THRMSTAT Register .....................................................................................................................64
Table 82. SCSTAT Register ...........................................................................................................................64
Table 83. HPSW Register ..............................................................................................................................65
Table 84. Headphone Operation ....................................................................................................................65
Table 85. CH0AIC Register ............................................................................................................................68
Table 86. CH1AIC Register ............................................................................................................................68
Table 87. CH2AIC Register ............................................................................................................................69
Table 88. CH3AIC Register ............................................................................................................................69
Table 89. ICTL0 Register ...............................................................................................................................70
Table 90. ICTL1 Register ...............................................................................................................................71
Table 91. MICBIAS Register ..........................................................................................................................71
Table 92. PGACTL0 Registers .......................................................................................................................73
Table 93. PGA Zero Cross Control Register ..................................................................................................74
Table 94. ICH0VOL/ ICH1VOL Registers ......................................................................................................76
Table 95. ICH2VOL/ ICH3VOL Registers ......................................................................................................76
Table 96. ALCCTL0 /ALCCTL1 Registers .....................................................................................................78
Table 97. NGATE Register ............................................................................................................................80
Table 98. Valid Digital Mic Configurations .....................................................................................................81
Table 99. DMICCTL Register .........................................................................................................................84
Table 100. PCMPXCTL0 Register .................................................................................................................87
Table 101. PCMOXCTL1 Register .................................................................................................................88
Table 102. AUDIOMUX1 Register .................................................................................................................88
Table 103. AUDIOMUX2 Register .................................................................................................................89
Table 104. AUDIOMUX3 Register .................................................................................................................89
Table 105. ASRCILVOL/ASRCIRVOL and ASRCOLVOL/ASRCORVOL Register .....................................90
Table 106. VOLCTLU Register ......................................................................................................................91
Table 107. TDM Slot Mapping .......................................................................................................................94
Table 108. I2SP1CTL Register ......................................................................................................................96
Table 109. I2SP2CTL Register ......................................................................................................................97
Table 110. I2SP3CTL Register ......................................................................................................................98
Table 111. I2S1MRATE Register ...................................................................................................................99
Table 112. I2S2MRATE Register ...................................................................................................................99
Table 113. I2S3MRATE Register .................................................................................................................100
Table 114. I2SIDCTLRegister ......................................................................................................................100
Table 115. I2SODCTL Register ...................................................................................................................101
Table 116. I2S Ports 1-3 Clock Mode Control Register ...............................................................................102
Table 117. I2SPINC0 Register .....................................................................................................................103
Table 118. I2SPINC1 Register .....................................................................................................................104
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TSCS454
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Portable Audio Consumer Codec
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Table 119. I2SPINC2 Register .....................................................................................................................104
Table 120. TDMCTL0 Register ....................................................................................................................105
Table 121. TDMCTL1 Register ....................................................................................................................105
Table 122. Standard Audio Sample Rates ...................................................................................................106
Table 123. ASRC Register ...........................................................................................................................107
Table 124. I2C Device Address Byte Format ...............................................................................................109
Table 125. I2C Address Via Pin Strapping ...................................................................................................109
Table 126. DEVADD0 Register ....................................................................................................................109
Table 127. DEVID Register ..........................................................................................................................110
Table 128. REVID Register ..........................................................................................................................110
Table 129. GPIO Pin Usage Summary ........................................................................................................112
Table 130. GPIOCTL0 Register ...................................................................................................................113
Table 131. GPIOCTL1 Register ...................................................................................................................114
Table 132. RESET Register .........................................................................................................................114
Table 133. IRQEN Register .........................................................................................................................116
Table 134. IRQMASK Register ....................................................................................................................117
Table 135. IRQSTAT Register .....................................................................................................................117
Table 136. Typical PLL Divider Values ........................................................................................................120
Table 137. PLLSTAT Register .....................................................................................................................122
Table 138. PLL1CTL Register .....................................................................................................................122
Table 139. PLL1RDIV Register ....................................................................................................................122
Table 140. PPL1ODIV Register ...................................................................................................................122
Table 141. PLL1FDIVL Register ..................................................................................................................122
Table 142. PLL1FDIVH Register ..................................................................................................................122
Table 143. PLL2CTL Register .....................................................................................................................123
Table 144. PLL2RDIV Register ....................................................................................................................123
Table 145. PLL2ODIV Register ...................................................................................................................123
Table 146. PLL2FDIVL Register ..................................................................................................................123
Table 147. PLL2FDIVH Register .................................................................................................................123
Table 148. PLLCTL Register .......................................................................................................................124
Table 149. ISRC Register ............................................................................................................................125
Table 150. I2S1MRATE, I2S2MRATE, I2S3MRATE Register .....................................................................127
Table 151. I2SP1CTL, I2SP2CTL, I2SP3CTL Register ...............................................................................127
Table 152. SCLKCTL Register .....................................................................................................................130
Table 153. TMBASE Register ......................................................................................................................131
Table 154. HSDCTL1 Register ....................................................................................................................140
Table 155. HSDCTL2 Register ....................................................................................................................141
Table 156. HSDSTAT Register ....................................................................................................................142
Table 157. HSDELAY Register ....................................................................................................................142
Table 158. BUTCTL Register .......................................................................................................................144
Table 159. Absolute Maximum Ratings .......................................................................................................145
Table 160. Recommended Operating Conditions ........................................................................................145
Table 161. PLL Section DC Characteristics .................................................................................................150
Table 162. PLL Section AC Characteristics .................................................................................................150
Table 163. Typical Power Consumption ......................................................................................................151
Table 164. Low power mode power consumption ........................................................................................151
Table 165. Register Map ..............................................................................................................................152
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TSCS454
TSCS454
Portable Audio Consumer Codec
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Figure 1. Block Diagram ...................................................................................................................................9
Figure 2. Output Processing Flow ..................................................................................................................15
Figure 3. Output Audio DSP Processor .........................................................................................................16
Figure 4. 3D Mixer Diagram ...........................................................................................................................21
Figure 5. Prescale & Equalizer Filter Diagram ...............................................................................................30
Figure 6. EQ Coefficient RAM Write Sequence .............................................................................................34
Figure 7. EQ Coefficient RAM Read Sequence .............................................................................................35
Figure 8. Compressor, Output vs Input Gain .................................................................................................39
Figure 9. Compressor Diagram ......................................................................................................................40
Figure 10. Output Interpolators and Filtering .................................................................................................50
Figure 11. Uncorrected & Corrected Constant Output Power ........................................................................56
Figure 12. Corrected Constant Output Power ................................................................................................57
Figure 13. Input Audio Processing .................................................................................................................66
Figure 14. MIC Bias Generator ......................................................................................................................72
Figure 15. ADC Filter Data path .....................................................................................................................74
Figure 16. ADC Input processing ...................................................................................................................75
Figure 17. ALC Operation ..............................................................................................................................77
Figure 18. Single Digital Microphone (data is ported to both left and right channels) ....................................82
Figure 19. Digital Audio Interface Block Diagram ..........................................................................................85
Figure 20. Left Justified Audio Format ...........................................................................................................92
Figure 21. Right Justified Audio Format .........................................................................................................92
Figure 22. I2S Format AudioFormat ...............................................................................................................93
Figure 23. TDM Mode Timing ........................................................................................................................94
Figure 24. TDM Mode Data Source/Destination Diagram ..............................................................................95
Figure 25. I2C Register-Mixer Access Diagram ...........................................................................................108
Figure 26. Page Register Write -2 Wire Serial Control Interface .................................................................110
Figure 27. Page Register Burst Write Cycle ................................................................................................111
Figure 28. Page Register Single Byte Read Cycle ......................................................................................111
Figure 29. Page Register Burst Multi-byte) Read Cycle ..............................................................................112
Figure 30. System Clock Diagram ...............................................................................................................118
Figure 31. Clock Generation Diagram ..........................................................................................................119
Figure 32. Simplified System Clock Block Diagram .....................................................................................121
Figure 33. Headphone/Headset Plug Types ................................................................................................132
Figure 34. Example OMTP/CTIA Headset Detection Diagram ....................................................................134
Figure 35. Headset present in jack when Combo-jack detection is enabled ................................................135
Figure 36. Pin Connection Diagram for 5 Terminal OMTP/CTIA Headset Support .....................................136
Figure 37. Pin Connection Diagram for 4 Terminal OMTP/CTIA Headset Support with isolated switch .....137
Figure 38. Pin Connection Diagram for 3 Terminal with isolated switch ......................................................138
Figure 39. Pin Connection Diagram using internal MIc’s .............................................................................139
Figure 40. Lanyard Button Push Detect Diagram ........................................................................................143
Figure 41. Package Drawing ........................................................................................................................166
Figure 42. Package Outline .........................................................................................................................167
TSI CONFIDENTIAL
©2014 TEMPO SEMICONDUCTOR, INC.
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TSCS454
TSCS454
Portable Audio Consumer Codec
1. OVERVIEW
1.1.
Block Diagram
The TSCS454 is an advanced low power codec with integrated fixed audio DSP’s and Class-D amplifiers.To support the
design of audio subsystems in a portable device, the TSCS454 features an intelligent codec architecture with fixed audio
DSP functions, an integrated true cap-less Class-H headphone amplifier, programmable PLL’s, 3W/channel filter-less stereo Class D amplifier, Mono Earpiece channel Class AB amplifier, cap less stereo line out and analog and digital microphone interfaces with programmable gain.
2
X T A L /M C L K IN
M
U
X
LIN E /M IC
IN P U T S
R IN 1
R IN 2
R IN 3
ADC
VREF
D M IC C LK 1
D M IC C LK 2
C LK
M
U
X
I2 S IN 2
ASRC3
2
2
S
E
L
E
C
T
2
DSP
1
T R IM
S
W
I
T
C
H
DSP
2
M
U
X
O U T 2:I2S /
T D M /P C M
M
U
X
O U T 3 : I2 S /
T D M /P C M
T R IM
DSP
BTL
C lass D
PW M
S P K O ut L
BTL
SPK Out R
1
BTL
DAC
L ine O ut L
DAC
DSP
E A R /S U B
O ut
2
HP L
(C ap -less)
DSP
L ine O ut R
DAC
HP R
(C ap -less)
M IC
D ete ct
SLEEVE
Pr
I2 S IN 3
2
4
ASRC3
el
I2 S /T D M /P C M IN 1
P
R
O
C
E
S
S
O
R
S
O
U
R
C
E
im
T o M IC
D e te ctio n
M IC B IA S 2
D M IC 1
D M IC 2
2
I
N
P
U
T
ADC
M
U
X
2
I2 C
HP
D e te ct
C harge
P um p
HPDET
L IN 1
L IN 2
L IN 3
IN T
y
M C LK 2
G P IO ’s
RING2
In te rn a l
A u d io
C lo cks
ar
P LL
in
XTAL O UT
O U T 1 : I2 S /
T D M /P C M
M
U
X
Figure 1. Block Diagram
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TSCS454
TSCS454
Portable Audio Consumer Codec
1.2.
Audio Outputs
The TSCS454 provides multiple outputs for analog sound. Audio outputs include:
• A cap less stereo headphone port (40mw) with ground referenced outputs, capable of driving headphones without
requiring an external DC blocking capacitor.
• A cap less stereo docking (line output port) with ground referenced outputs, capable of driving 10K ohm loads
without requiring an external DC blocking capacitor.
• A mono, 40mw, Class AB output for driving a headset earpiece or for driving an external earpiece amplifier.
• A stereo 3W /channel filter-less class D amplifier. This amplifier is capable of driving the speakers typically found in
portable equipment, providing high fidelity, high efficiency, and excellent sound quality
Outputs feature independent volume controls, including a soft-mute capability which can slowly ramp up or down the
volume changes to avoid unwanted audio artifacts.
The TSCS454 output signal paths consist of digital filters, DACs and output drivers. The digital filters and DACs are
enabled when the TSCS454 is in ‘playback only’ or ‘record and playback’ mode. The output drivers can be separately
enabled by individual control bits.
ar
y
The digital filter and audio processing block processes the data to provide volume control and numerous sound
enhancement algorithms. High performance sigma-delta audio DACs convert the digital data into analog.
The digital audio data is converted to over-sampled bit streams using 24-bit digital interpolation filters, which then
enters sigma-delta DACs, and become converted to high quality analog audio signals.
Audio Inputs
Pr
1.3.
el
im
in
To enhance the sound available from the small, low-power speakers typically found in a portable device, the TSCS454
provides numerous audio enhancement capabilities. The TSCS454 features dual, independent, programmable Psychoacoustic bass and treble enhancement algorithms achieve a rich, full tone even from originally compressed content,
and even with speakers generally unable to play low-frequency sounds, left/right 6-band equalization, allowing the system designer to provide an advanced system equalizer to accommodate the specific speakers and enclosure design. A
multi-band compressor features programmable attack and release thresholds, enabling the system designer to attenuate loud noise excursions to avoid speaker artifacts, thus allowing the underlying content to be played at a louder volume without distortion. For compressed audio, a programmable expander is available to help restore the dynamic
range of the original content. A programmable limiter provides protection for driving power limited loudspeaker drivers.
A stereo depth enhancement algorithm allows common left/right content (e.g. dialog) to be attenuated separately from
other content, providing a perceived depth separation between background and foreground audio. .
The TSCS454 provides multiple audio analog and digital inputs. Audio inputs include:
•
•
•
Three mux selectable stereo analog line/microphone inputs with selectable differential input option.
Four digital microphone inputs via two stereo input pins.
Three stereo PCM, I2S type digital audio inputs, with programmable format and Asynchronous Sample Rate Converter. Analog
Line Input to Headphone Output bypass path.
A maximum of four input streams can be processed simultaneously through the Input Processor.
The Input Processor provides automatic level control and various gain and volume control functions.
1.4.
Digital Audio Interface
Three bi-directional digital audio ports are provided, with one input and output able to go to an ASRC, supporting I2S,
Left Justified, Right Justified. these I2S input and/or bluetooth PCM can be configures as TDM type interfaces.
1.5.
On-Chip PLLs
Beyond audio processing, the TSCS454 also provides a higher level of system integration. It contains a low-power,
low-jitter clock synthesizer. Using a single fundamental mode crystal the TSCS454 has two PLLs that can be used to
provide internal timing as well as generate a reference output to drive a local applications processor and other peripherals.
10
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TSCS454
TSCS454
Portable Audio Consumer Codec
2. POWER MANAGEMENT
2.1.
Registers
The TSCS454 has control registers to enable system software to control which functions are active. To minimize power
consumption, unused functions should be disabled. To avoid audio artifacts, it is important to enable or disable functions in the correct order
Power Management Register 0
Label
Type
Default
Description
7
RSVD
R
0
Reserved
INPROC3PU
RW
0
5
INPROC2PU
RW
0
Input Processor Channel2
0 = Power down
1 = Power up
4
INPROC1PU
RW
0
Input Proceesor Channel 1
0 = Power Down
1 = Pouwer Up
3
INPROC0PU
RW
0
Input Proceesor Channel 0
0 = Power Down
1 = Pouwer Up
2
MICB2PU
1
MICB1PU
0
ar
y
6
Input Processor Channel 3
0 = Power down
1 = Power up
in
Page 0, Reg 51 - 33h
PWRM0
Bit
RW
0
im
Register Address
RW
el
2.1.1.
MCLKPEN
RW
MICBIAS2
0 = Power down
1 = Power up
0
MICBIAS1
0 = Power down
1 = Power up
1
Master clock enable
0: master clock disabled
1: master clock enabled
Pr
Table 1. PWRM0 Register
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TSCS454
TSCS454
Portable Audio Consumer Codec
Power Management Register 1
Label
Type
Default
Description
7
SUBPU
RW
0
SUB Output Buffer Enable
0 = Power down
1 = Power up
6
HPLPU
RW
0
Left Headphone Output Buffer
0 = Power down
1 = Power up
5
HPRPU
RW
0
Right Headphone Output Buffer
0 = Power down
1 = Power up
4
SPKLPU
RW
0
Left Speaker Output Buffer Enable
0 = Power down
1 = Power up
3
SPKRPU
RW
0
Right Speaker Output Buffer Enable
0 = Power down
1 = Power up
2
D2S2PU
RW
0
Analog in D2S2 AMP Power Down
0 = Power down
1 = Power up
1
D2S1PU
RW
0
Analog in D2S1 AMP Power Down
0 = Power down
1 = Power up
0
RSVD
y
Page 0, Reg 52 - 34h
PWRM1
Bit
ar
Register Address
in
2.1.2.
R
0
RVSD
Pr
el
im
Table 2. PWRM1 Register
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TSCS454
TSCS454
Portable Audio Consumer Codec
Power Management Register 2
Page 0, Reg 53 - 35h
PWRM2
Bit
Label
Type
Default
Description
7:6
RSVD
R
0
Reserved
5
I2S3OPU
RW
0
I2S3 Output Power Down
0 = I2S3 Output Powered down
1 = I2S3 Output Powered up
4
I2S2OPU
RW
0
I2S2 Output Power Down
0 = I2S2 Output Powered down
1 = I2S2 Output Powered up
3
I2S1OPU
RW
0
I2S1 Output Power Down
0 = I2S Output Powered down
1 = I2S Output Powered up
2
I2S3IPU
RW
0
I2S3 Input Power Down
0 = I2S Input Powered down
1 = I2S Input Powered up
1
I2S2IPU
RW
0
I2S2 Input Power Down
0 = I2S Input Powered down
1 = Input Powered up
0
I2S1IPU
RW
y
Register Address
I2S1 Input Power Down
0 = I2S Input Powered down
1 = I2S Input Powered up
ar
2.1.3.
0
Register Address
im
Power Management Register 3
Bit
Label
Type
Default
7
RSVD
R
0
Reserved
6
BGSBUP
RW
0
Bandgap and self bias power up
0 = Powered Up
1 = Powered Down
RW
0
Input path VGB amplifier power up
0 = Powered Up
1 = Powered Down
5
VGBAPU
Pr
Page 0, Reg 54 - 36h
PWRM3
el
2.1.4.
in
Table 3. PWRM2 Register
Description
4
LLINEPU
RW
0
Left Line Output Buffer
0 = Power down
1 = Power up
3
RLINEPU
RW
0
Right Line Output Buffer
0 = Power down
1 = Power up
2:0
RSVD
R
0
Reserved
Table 4. PWRM3 Register
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TSCS454
TSCS454
Portable Audio Consumer Codec
2.1.5.
Power Management Register 4
Register Address
Bit
Label
Type
Default
7-5
RSVD
R
0
Reserved
0
Output Processor Sub Channel Power Down
0 = Powered Down
1 = Powered Up
0
Output Processor Headphone Left Channel Power
Down
0 = Powered Down
1 = Powered Up
0
Output Processor Headphone Right Channel Power
Down
0 = Power Down
1 = Power Up
0
Output Processor Speaker Left Channel Power
Downr
0 = Power Down
1 = Power Up
4
OPSUBPU
3
Page 0, Reg 55 - 37h
PWRM4
RW
OPHPLPU
2
RW
OPHPRPU
OPSPKLPU
RW
y
1
RW
Description
OPSPKRPU
R
ar
0
Output Processor Speaker Right Channel Power
Downr
0 = Power Down
1 = Power Up
0
Pr
el
im
in
Table 5. PWRM4 Register
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TSCS454
TSCS454
Portable Audio Consumer Codec
3. OUTPUT AUDIO PROCESSING
+6 to -88.5dB
In 0.75dB steps
From SSS
DSP
Interpolator
INV
HP
VOL
DAC
HP
VOL
DAC
Antipop
HP
HP Out
Left
Antipop
HP
HP Out
Right
Left Input MUX - Output
Analog Bypass
Interpolator
DSP
From SSS
V
O
L
U
M
E
DSP
0 to 95.25dB
0.375 dB
steps
From SSS
DSP
y
DSP
Interpolator
INV
Antipop
Line Out
Right
SPKR
VOL
Digital PWM
Controller
BTL
Class D
Left
INV
SPKR
VOL
Digital PWM
Controller
BTL
Class D
Right
Thermal
Limit
el
+12 to -77.25dB
In 0.75dB steps
INV
SPKR
VOL
DAC
Class AB
Earpiece
BTL
Pr
Interpolator
Line Out
Left
Thermal
Limit
+12 to -77.25dB
In 0.75dB steps
Interpolator
Antipop
ar
From SSS
Right Input MUX - Output
Analog Bypass
in
M
A
S
T
E
R
+6 to -88.5dB
In 0.75dB steps
im
From SSS
INV
Figure 2. Output Processing Flow
15
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TSCS454
TSCS454
Portable Audio Consumer Codec
Output DSP
Processor
X5 Channels
Multi- band Compressor
PA
Treble
From SSS
DC
Removal
PA
Bass
Pages 3 to 5 , Reg 31
DC- Coef_Sel
3D
EQCRAM
Comp
EQ
ADh
EQCRAM
96h
EQCRAM
AFh
EQ
Comp
EQ
Comp
EQCRAM 00 h - 3Dh
EQCRAM 40 h - 7Dh
EQ1 Coefficients
EQCRAM 80 h - 96h
EQCRAM 97 h - ADh
EQCRAM AEh - AFh
Bass Coefficients
EQCRAM B0h - BEh
Multi-Band EQ
Coefficients
Prescale
1
EQ1
COEFF WRITE DATA
COEFF READ DATA
Phase
Invert
in
,
Page 2Reg
1, 2, 3
COEFF RAM STATUS
Pages 3 to 5 - Reg 9
Pages 3 to 5 - Reg 24-29
Expander
Pages 3 to 5 - Reg 18-23
Limiter
xPOL
Channel
Volume / Mute
0 to -95.25 dB
0. 375 dB steps
To
DAC, Speaker
Interpolators
Page 2 , Reg 8-9
Page 2 , Reg 7
Master Volume
Mute Control
im
De- emphasis
EQ2
y
Gain
0 to 46.5dB
In 1.5 dB
steps
ar
Page2 , Reg2,3
Prescale
2
Pages 3 to 5 - Reg 8
Pages 3 to 5 - Reg 5,6,7
Compressor
Limiter
Expander
Treble Coefficients
3D Coefficients
COEFF RAM ADDRESS
Pages 3 to 5 - Reg 2,3,4
Deemphasis
EQ2 Coefficients
Pages 3 to 5 - Reg 10-17
Compressor
Pages 3 to 5 - Reg 30
Control
el
Figure 3. Output Audio DSP Processor
Pr
Note: The Output Processor’s audio processing functions can exceed the available DSP processing cycles when operating
at audio sample rates above 48KHz. When operating at sample rates above 48KHz the number of audio processing functions that can be enabled simultaneously will be limited by the total number of DSP processing cycles available. The maximum number of DSP processing cycles is 383.The number of DSP processing cycles required for each function. When
operating at audio sample rates above 48KHz the total number of used DSP processing cycles must be less than 383.
DSP Processing Block
DSP Processing
Cycles
Bass Enhancement
77
Treble Enhancement
65
3D
7
Multi-band Compressor Band 1
50
Multi-band Compressor Band 1
50
Multi-band Compressor Band 1
50
EQ1
83
EQ2
83
De-emphasis
13
Compressor-Expander-Limiter
21
Table 6. DSP Processing Cycles
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TSCS454
TSCS454
Portable Audio Consumer Codec
3.1.
DC Removal
Before processing, a DC removal filter removes the DC component from the incoming audio data. The DC removal filter is programmable.
Label
Type
Default
D7
SUBDCBP
RW
0
SUB DC Removal Bypass
0 = not bypassed
1 = bypassed
D6
DACDCBP
RW
0
DAC DC Removal Bypass
0 = not bypassed
1 = bypassed
D5
SPKDCBP
RW
0
Speaker DC Removal Bypass
0 = not bypassed
1 = bypassed
D4:D3
RSVD
R
0
RW
101
Reserved
DC Offset
0: dc_offset = 24'h100000; //2^^-3 = 0.125
1: dc_offset = 24'h040000;
2: dc_offset = 24'h010000;
3: dc_offset = 24'h004000;
4: dc_offset = 24'h001000;
5: dc_offset = 24'h000400;
6: dc_offset = 24'h000100; //2^^-15 = 0.00030517
7: dc_offset = 24'h000040; //2^^-17
in
D2-D0 DCCOEFSEL[2:0]
Description
y
PAGE 2, Reg 4 - 4h
DCCON
Bit
ar
Register Address
Pr
el
im
Table 7. DCCON Register
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TSCS454
Portable Audio Consumer Codec
3.2.
Volume Control Functions
The Volume Update bits control the updating of volume control data; when a bit is written as ‘0’, the Left Volume control
associated with that bit is updated whenever the left volume register is written and the Right Volume control is updated
when ever the right volume register is written. When a bit is written as ‘1’, the left volume data is placed into an internal
holding register when the left volume register is written and both the left and right volumes are updated when the right
volume register is written. This enables a simultaneous left and right volume update
Type
Default
R
0
Reserved
Description
4
DACFADE
RW
1
1 = volume fades between old/new value
0 = volume/mute changes immediately
3
SUBVOLU
RW
0
0 = SUB speaker volume updated immediately
1 = SUB speaker volume held until right speaker
volume register written.
2
DACVOLU
RW
0
0 = Left DAC volume updated immediately
1 = Left DAC volume held until right DAC volume
register written.
1
SPKVOLU
RW
0
HPVOLU
y
Label
RSVD
ar
Page 2 , Reg 6 - 6h
OVOLCTLU
Bit
7:5
0
0 = Left Speaker volume updated immediately
1 = Left Speaker volume held until right DAC volume
register written.
0 = Left headphone volume updated immediately
1 = Left headphone volume held until right
headphone volume register written.
in
Register Address
RW
0
im
Table 8. OVOLCTLU Register
Register Address
Bit
el
The output path may be muted automatically when a long string of zero data is received. The length of zeros is programmable and a detection flag indicates when a stream of zero data has been detected.
Label
Type
Default
ZEROSTAT
R
0
1 = zero detect length exceeded.
RSVD
R
0
Reserved for future use.
5:4
ZDETLEN[1:0]
RW
2
Enable mute if input consecutive zeros exceeds this
length. 0 = 512, 1 = 1k, 2 = 2k, 3 = 4k samples
3
RSVD
R
0
Reserved for future use.
2
1:0
AMUTE
RW
1
1 = auto mute if detect long string of zeros on input
RSVD
R
0
Reserved for future use.
7
6
Pr
Page 2, Reg 7 - 7h
MUTEC
Description
Table 9. MUTEC Register
18
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TSCS454
TSCS454
Portable Audio Consumer Codec
3.3.
Master Volume Control
The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps).
The level of attenuation is specified by an eight-bit code, ‘MVOLx’, where ‘x’ is L, or R. The value “00000000” indicates
mute; other values select the number of 0.375dB steps above -95.625dB for the volume level.
In each Output Processor block there is a digital volume control that is mapped to this control register. Changing the
value in this register will adjust the volume of all the outputs (Speaker, Headphone, Earpiece) simultaneously. The signal volume can be controlled digitally, across a gain and attenuation range of -95.25dB to 0dB (0.375dB steps). The
level of attenuation is specified by an eight-bit code, ‘MVOL_x’, where ‘x’ is L, or R. The value “00000000” indicates
mute; other values select the number of 0.375dB steps above -95.625dB for the volume level.
Label
Type
MVOL_L
[7:0]
7:0
RW
Default
Description
FF
(0dB)
Left Master Volume Level
0000 0000 = Digital Mute
0000 0001 = -95.25dB
0000 0010 = -94.875dB
... 0.375dB steps up to
1111 1111 = 0dB
Note: If DACVOLU is set, this setting will take effect
after the next write to the Right Input Volume register.
ar
Page 2, Reg 8 - 8h
MVOLL
Bit
y
Register Address
in
MVOL_R
[7:0]
7:0
RW
FF
(0dB)
im
Page 2, Reg 9 - 9h
MVOLR
Right Master Digital Volume Level
0000 0000 = Digital Mute
0000 0001 = -95.25dB
0000 0010 = -94.875dB
... 0.375dB steps up to
1111 1111 = 0dB
Pr
el
Table 10. MVOLL/MVOLR Register
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TSCS454
TSCS454
Portable Audio Consumer Codec
3.4.
Effects Processing
The TSCS454 offers Bass enhancement, Treble enhancement, Stereo Depth enhancement. The output effects processing
is outlined in the following sections.
3.4.1.
Effects Control (xFXCTL) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Label
Type
Default
Description
7:5
RSVD
R
000
4
3DEN
RW
0
3D Enhancement Enable
0 = Disabled
1 = Enabled
3
TEEN
RW
0
Treble Enhancement Enable
0 = Disabled
1 = Enabled
2
TNLFBYP
RW
1
BEEN
RW
0
BNLFBYP
y
Reserved
Treble Non-linear Function Bypass:
0 = Enabled
1 = Bypassed
0
Bass Enhancement Enable
0 = Disabled
1 = Enabled
ar
0
in
Page y, Reg 53 - 35h
xFXCTL
Bit
im
Register Address
RW
0
Bass Non-linear Function Bypass:
0 = Enabled
1 = Bypassed
Table 11. xFXCTL Register
3.4.2.
Pr
el
Note 1: 3D Enhancement is not available for the Earpiece processing channel.
Stereo Depth (3D) Enhancement
The TSCS454 has a digital depth enhancement option to artificially increase the separation between the left and right
channels, by enabling the attenuation of the content common to both channels. The amount of attenuation is
programmable within a range. The input is prescaled (fixed) before summation to prevent saturation. The Earpiece
channel, due to its mono nature, does support this function.
The 3D enhancement algorithm is a tried and true algorithm that uses two principles.
1
If the material common to the two channels is removed, then the speakers will sound more 3D.
2
If the material for the opposite channel is presented to the current channel inverted, it will tend to cancel any material
from the opposite channel on the current ear. For example, if the material from the right channel speaker is presented to
the left ear inverted, it will cancel some of the material from the right ear that is leaking to the left ear. This is commonly
referred to as crosstalk cancellation
20
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TSCS454
Portable Audio Consumer Codec
Left
Left
Right
Right
Figure 4. 3D Mixer Diagram
Psychoacoustic Bass Enhancement
ar
3.4.3.
y
3D_Mix specifies the amount of the common signal that is added from the left and right channels. This number is a
fractional amount between -1 and 1. For proper operation, this value is typically negative.
in
One of the primary audio quality issues with small speaker systems is their inability to reproduce significant amounts of
energy in the bass region (below 200Hz). While there is no magic mechanism to make a speaker reproduce frequencies
that it is not capable of, there are mechanisms for fooling the ear into thinking that the bass material is being heard.
Psychoacoustic Treble Enhancement
el
3.4.4.
im
The psychoacoustic bass processor relies on a psychoacoustic principle called “missing fundamental”. If the human ear
hears a proper series of harmonics for a particular bass note, the listener will hear the fundamental of that series, even if it
is not present.
Pr
One of the mechanisms used to limit the bit rate for compressed audio is to first remove high frequency information before
compression. When these files like low bit rate MP3 are decompressed, this can lead to dull sounding audio. The Tempo
treble enhancement replaces these lost high frequencies.
The psychoacoustic treble processor relies on a psychoacoustic principle called “missing fundamental”. If the human ear
hears a proper series of harmonics for a particular treble note, the listener will hear the fundamental of that series, even if it
is not present
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3.5.
Multi-band Compressor
The TSCS454 output processing includes a multi-band compressor that improves sound from small loudspeakers typically
used in portable devices. Three independent compressor blocks are each preceded by a, 2-stage, Bi-quad processing
block that filters the incoming audio so that each compressor operates on a select range of audio frequencies. The
advantage of multiband compression over full-bandwidth (full-band, or single-band) compression is that audible gain
"pumping" can be reduced. When using single band compressors high energy audio content in a narrow range of
frequencies can cause the volume of the entire audio frequency band to be affected thus causing the audio signal level to
audibly “pump”. This pumping of the audio signal level can be distracting. A multi-band compressor can effectively
eliminate or reduce the pumping to insignificant levels.
Compressor
Bi-Quad
Compressor
DATA OUT
y
Bi-Quad
ar
Compressor
in
DATA IN
Bi-Quad
im
Each band in the Multi-band Compressor is comprised of a single stage 6-tap IIR (Bi-quad) filter followed by a compressor
block. The BI-quad filter coefficients are written using the Parametric Equalizer Registers. The purpose of the Bi-quad block
is to provide a bandpass filter function for each Compressor band.
Multi-band_Compressor Registers
Pr
3.5.1.
el
For a description of the Compressor function please see Gain, Limiting, and Dynamic Range Control
3.5.1.1. Multi-band_Compressor Enable Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 10 - 0Ah
xMBCEN
Bit
Label
Type
Default
Description
7:3
RSVD
R
0h
2
xMBCEN3
RW
0
1 = enable compressor band 3
1
xMBCEN2
RW
0
1 = enable compressor band 2
0
xMBCEN1
RW
0
1 = enable compressor band 1
Reserved
Table 12. xMBCEN Register
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3.5.1.2. x_Multi-band_Compressor Control (xMBCCTL)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Label
Type
Default
Description
7:6
RSVD
R
0h
Reserved
5
LVLMODE3
RW
0
Compressor Level Detection Mode Band 3
0 = Average
1 = Peak
WINSEL3
RW
0
3
LVLMODE2
RW
0
Compressor Level Detection Mode Band 2
0 = Average
1 = Peak
0
Window width selection for level detection Band 2
0 = equivalent of 512 samples of selected Base Rate
(~10-16ms)
1 = equivalent of 64 samples of selected Base Rate
(~1.3-2ms)
y
4
Window width selection for level detection Band 3
0 = equivalent of 512 samples of selected Base Rate
(~10-16ms)
1 = equivalent of 64 samples of selected Base Rate
(~1.3-2ms)
2
WINSEL2
RW
LVLMODE1
RW
Compressor Level Detection Mode Band 1
0 = Average
1 = Peak
0
im
1
ar
Page y, Reg 11 - Bh
xMBCCTL
Bit
in
Register Address
0
RW
0
el
WINSEL1
Window width selection for level detection Band1
0 = equivalent of 512 samples of selected Base Rate
(~10-16ms)
1 = equivalent of 64 samples of selected Base Rate
(~1.3-2ms)
Pr
Table 13. xMBCCTL Register
3.5.1.3.x_Multi-band_Compressor Make-up Gain Band 1(xMBCMUG1) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 12 - Ch
xMBCMUG1
Bit
Label
Type
Default
Description
7:6
RSVD
R
0h
Reserved
5
PHASE
RW
0h
Phase of Compressor Band Output
0 = Not inverted
1 = Inverted
4:0
MUGAIN1[4:0]
RW
0h
0dB...46.5dB in 1.5dB steps
Table 14. xMBCMUG1 Register
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3.5.1.4.x_Multi-band_Compressor Threshold Band 1(xMBCTHR1)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Page y, Reg 13 - Dh
xMBCTHR1
7:0
THRESH[7:0]
RW
00h
Description
FFh...00h = 0dB...95.625dB in 0.375dB steps.
Table 15. xMBCTHR1 Register
3.5.1.5.x_Multi-band_Compression Ratio Band 1(xMBCRAT1)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Label
Type
Default
7:5
RSVD
R
000
Reserved
00h
Compressor Ratio
00h = Reserved
01h = 1.5:1
02h...14h = 2:1...20:1
15h...1Fh = Reserved
4:0
RATIO[4:0]
RW
Description
ar
Page y, Reg 14 - Eh
xMBCRAT1
Bit
y
Register Address
in
Table 16. xMBCRAT1 Register
3.5.1.6.x_Multi-band_Compressor Attack Time Constant Band 1(xMBCATK1L) (Low)
7:0
Label
Type
Default
TCATKL[7:0]
RW
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Pr
Page y, Reg 15 - Fh
xMBCATK1L
Bit
el
Register Address
im
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Table 17. xMBCATK1L Register
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3.5.1.7.x_Multi-band_Compressor Attack Time Constant Band 1(xMBCATK1H) (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
Page y, Reg 16 - 10h
xMBCATK1H
0001h = 0.96875 + 1/(2^21)
7:0
TCATKH1[7:0]
RW
00h
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
ar
y
Table 18. xMBCATK1H Register
3.5.1.8.x_Multi-band_Compressor Release Time Constant Band 1(xMBCREL1L) (Low)
7:0
Label
Type
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
TCRELL1[7:0]
RW
00h
el
Page y, Reg 17 - 11h
xMBCREL1L
Bit
im
Register Address
in
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Pr
Table 19. xMBCREL1L Register
3.5.1.9.x_Multi-band_Compressor Release Time Constant Band 1(xMBCREL1H) (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 18 - 12h
xMBCREL1H
Bit
7:0
Label
Type
TCRELH1[15:8]
RW
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor release phase. The
time constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 20. xMBCREL1H Register
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3.5.1.10.x_Multi-band_Compressor Make-up Gain Band 2(xMBCMUG2) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 19 - 13h
xMBCMUG2
Bit
Label
Type
Default
Description
7:6
RSVD
R
0h
Reserved
5
PHASE2
RW
0h
0 = Not inverted
1 = Inverted
4:0
MUGAIN2[4:0]
RW
0h
0dB...46.5dB in 1.5dB steps
Table 21. xMBCMUG2 register
3.5.1.11.x_Multi-band_Compressor Threshold Band 2(xMBCTHR2) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Bit
Label
Type
Default
Page y, Reg 20 - 14h
xMBCTHR2
7:0
THRESH2[7:0]
RW
00h
Description
y
Register Address
ar
FFh...00h = 0dB...95.625dB in 0.375dB steps.
in
Table 22. xMBCTHR2 Register
3.5.1.12.x_Multi-band_Compression Ratio Band 2(xMBCRAT2) Register
Label
7:5
RSVD
4:0
Type
Default
R
000
RATIO2[4:0]
RW
Description
Reserved
Compressor Ratio
00h = Reserved
01h = 1.5:1
02h...14h = 2:1...20:1
15h...1Fh = Reserved
00h
Pr
Page y, Reg 21 - 15h
xMBCRAT2
Bit
el
Register Address
im
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Table 23. xMBCRAT2 Register
3.5.1.13.x_Multi-band_Compressor Attack Time Constant Band 2(xMBCATK2L) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 22 - 16h
xMBCATK2L
Bit
7:0
Label
Type
TCATKL2[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 24. xMBCATK2L Register
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3.5.1.14.x_Multi-band_Compressor Attack Time Constant Band 2(xMBCATK2H) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
Page y, Reg 23 - 17h
xMBCATK2H
0001h = 0.96875 + 1/(2^21)
7:0
TCATKH2[7:0]
RW
00h
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
y
Table 25. xMBCATK2H Register
ar
3.5.1.15.x_Multi-band_Compressor Release Time Constant Band 2(xMBCREL2L) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Type
Default
Description
in
Label
7:0
Low byte of the time constant used to ramp to a new
gain value during a compressor release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
TCRELL2[7:0]
RW
00h
el
Page y, Reg 24 - 18h
xMBCREL2L
Bit
im
Register Address
Table 26. xMBCREL2L Register
Pr
3.5.1.16.x_Multi-band_Compressor Release Time Constant Band 2(xMBCREL2H) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 25 - 19h
xMBCREL2H
Bit
7:0
Label
Type
TCRELH2[15:8]
RW
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor release phase. The
time constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 27. xMBCREL2H Register
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3.5.1.17.x_Multi-band_Compressor Make-up Gain Band 3(xMBCMUG3) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 26 - 1Ah
xMBCMUG3
Bit
Label
Type
Default
Description
7:6
RSVD
R
0h
Reserved
5
PHASE3
RW
0h
0 = Not inverted
1 = Inverted
4:0
MUGAIN3[4:0]
RW
0h
0dB...46.5dB in 1.5dB steps
Table 28. xMBCMUG3 Register
3.5.1.18.x_Multi-band_Compressor Threshold Band 3(xMBCPTHR3) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Bit
Label
Type
Default
Page y, Reg 27 - 1Bh
xMBCTHR3
7:0
THRESH3[7:0]
RW
00h
Description
y
Register Address
ar
FFh...00h = 0dB...95.625dB in 0.375dB steps.
Table 29. xMBCTHR3 Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Label
7:5
RSVD
4:0
Type
Default
Description
im
Page y, Reg 28 - 1Ch
xMBCRAT3
Bit
R
000
Reserved
Compressor Ratio
00h = Reserved
01h = 1.5:1
02h...14h = 2:1...20:1
15h...1Fh = Reserved
el
Register Address
in
3.5.1.19.x_Multi-band_Compressor Compression Ratio Band 3(xMBCRAT3) Register
RATIO3[4:0]
RW
00h
Pr
Table 30. xMBCRAT3 Register
3.5.1.20.x_Multi-band_Compressor Attack Time Constant Band 3(xMBCATK3L) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 29 - 1Dh
xMBCATK3L
Bit
7:0
Label
Type
TCATKL3[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 31. xMBCATK3L Register
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3.5.1.21.x_Multi-band_Compressor Attack Time Constant Band 3(xMBCATK3H) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
Page y, Reg 30 - 1E
xMBCATK3H
0001h = 0.96875 + 1/(2^21)
7:0
TCATKH3[7:0]
RW
00h
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
ar
y
Table 32. xMBCATK3H Register
3.5.1.22.x_Multi-band_Compressor Release Time Constant Band 3(xMBCREL3L) Register (Low)
7:0
Label
Type
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
TCREL3L[7:0]
RW
00h
el
Page y, Reg 31 - 1Fh
xMBCREL3L
Bit
im
Register Address
in
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Pr
Table 33. xMBCREL3L Register
3.5.1.23.x_Multi-band_Compressor Release Time Constant Band 3(xMBCREL3H) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 32 - 20h
xMBCREL3H
Bit
7:0
Label
Type
TCRELH3[15:8]
RW
Default
Description
High byte of the time constant used to ramp to a new
gain value during a compressor release phase. The
time constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 34. xMBCREL3H Register
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3.6.
Parametric Equalizer
The TSCS454 has a dual, 6-band, digital parametric equalizer to enable fine tuning of the audio response and preferences
for a given system. For the Speaker and DAC output channels the EQ filters are stereo. For the Earpiece channel the EQ
filters are mono. This difference is reflected in the coefficient RAM table mapping. See Table 44 and Table 45. Each EQ
may be enabled or disabled independently. Typically one EQ will be used for speaker compensation and disabled when
only headphones are in use while the other EQ is used to alter the audio to make it more pleasing to the listener.This
function operates on the digital audio data before it is converted back to analog by the audio DACs.
3.6.1.
Prescaler & Equalizer Filter
The Equalizer Filter consists of a Prescaler and 6 IIR Filters. The Prescaler allows the input to be attenuated prior to the EQ
filters in case the EQ filters introduce gain, and would thus clip if not prescaled.
ar
y
Tempo provides a tool to enable an audio designer to determine appropriate coefficients for the equalizer filters. The filters
enable the implementation of a parametric equalizer with selectable frequency bands, gain, and filter characteristics (high,
low, or bandpass).
EQ
Filter 1
EQ
Filter 2
EQ
Filter 3
EQ
Filter 4
EQ
Filter 5
DATA OUT
im
EQ
Filter 0
DATA IN
in
Prescaler & EQ Filters
eq_prescale
Pr
el
Figure 5. Prescale & Equalizer Filter Diagram
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3.6.2.
EQ Filter Register
3.6.2.1.EQ Filter Control (xEQFILT) Registers
Where x = SPK, DAC, SUB, y = Page 3, 4, 5
Bit
Label
Type
Default
7
EQ2_EN
R/W
0
EQ bank 2 enable
0 = second EQ bypassed
1 = second EQ enabled
EQ2 band enable. When the EQ is enabled the
following EQ stages are executed.
0 - Prescale only
1 - Prescale and Filter Band 0
...
6 - Prescale and Filter Bands 0 to 5
7 - RESERVED
EQ2BE[2:0]
R/W
0
3
EQ1EN
R/W
0
y
6:4
Description
EQ1BE[2:0]
R/W
EQ1 band enable. When the EQ is enabled the
following EQ stages are executed.
0 - Prescale only
...
6 - Prescale and Filter Bands 0 to 5
7 - RESERVED
0
im
2:0
EQ bank 1 enable
0 = first EQ bypassed
1 = first EQ enabled
in
Page y, Reg 1 - 1h
xEQFILT
ar
Register Address
el
Table 35. xEQFILT Registers
Pr
3.6.2.2.EQ Write/Read Data Coefficient Registers
These two 24-bit registers provide the 24-bit data holding registers used when doing indirect writes/reads to the EQ
Coefficient RAM.
EQ Coefficient Write Data Low (xCRWDL) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 2 -2h
xCRWDL
Bit
7:0
Label
Type
WDATA_L[7:0]
R/W
Default
Description
0
Low byte of a 24-bit data register, contains the
values to be written to the EQ Coefficient RAM.
The address written will have be specified by the
EQ Coefficient RAM Address fields.
Table 36. xCRWDL Register
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EQ Coefficient Write Data Mid (xCRWDM) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 3 - 3h
xCRWDM
Bit
7:0
Label
Type
WDATA_M[15:8
R/W
Default
Description
0
Middle byte of a 24-bit data register, contains the
values to be written to the EQ Coefficient RAM. The
address written will have be specified by the EQ
Coefficient RAM Address fields.
Table 37. xCRWDM Register
EQ Coefficient Write Data High (xCRWDH)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
7:0
Label
Type
WDATA_H[23:16]
R/W
Default
Description
0
High byte of a 24-bit data register, contains the
values to be written to the EQ Coefficient RAM. The
address written will have be specified by the EQ
Coefficient RAM Address fields.
y
Page y, Reg 4 - 4h
xCRWDH
Bit
ar
Register Address
Table 38. xCRWDH Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5)
Label
Type
Default
7:0
RDATA_L[7:0]
R
0
el
Page y, Reg 5 -5h
xCRRDL
Bit
im
Register Address
in
EQ Coefficient Read Data Low (xCRRDL)
Description
Low byte of a 24-bit data register, contains the
contents of the most recent EQ Coefficient RAM
address read from the RAM. The address read will
have been specified by the EQ Coefficient RAM
Address fields.
Pr
Table 39. xCRRDL Register
EQ Coefficient Read Data Low (xCRRDM)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5)
Register Address
Page y, Reg 6 - 6h
xCRRDM
Bit
7:0
Label
Type
RDATA_M[15:8]
R
Default
0
Description
Middle byte of a 24-bit data register, contains the
contents of the most recent EQ Coefficient RAM
address read from the RAM. The address read will
have been specified by the EQ Coefficient RAM
Address fields.
Table 40. xCRRDM Register
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EQ Coefficient Read Data HIgh (xCRRDH)
Register Address
Page y, Reg 7 -7h
xCRRDH
Bit
7:0
Label
Type
RDATA_H[23:16]
Default
R
Description
High byte of a 24-bit data register, contains the
contents of the most recent EQ Coefficient RAM
address read from the RAM. The address read will
have been specified by the EQ Coefficient RAM
Address fields.
0
Table 41. xCRRDH Register
3.6.2.3.Coefficient Address (xCRADD) Register
This 7-bit register provides the address to the internal RAM when doing indirect writes/reads to the EQ RAM.
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Bit
Label
Type
Default
Description
Contains the address (between 0 and 255) of the EQ
Coefficient RAM to be accessed by a read or write.
This is not a byte address--it is the address of the
24-bit data item to be accessed from the EQ
Coefficient RAM.This address is automatically
incremented after writing to the xCRWD_H or
reading from xCRRDH (and the 24 bit data from the
next RAM location is fetched.)
7:0
ADDRESS[7:0]
R/W
0
in
Page y, Reg 8 - 8h
xCRADD
ar
y
Register Address
im
Table 42. xCRADD Register
3.6.2.4.x_Coefficient Status (xCRS) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Page y, Reg 9 - 9h
xCRS
Bit
Label
Type
Default
7
xDACOEFR
R
0
1 = read/write to EQ Coefficient RAM in progress,
cleared by HW when done.
6:0
RSVD
R
0
Reserved
Pr
Register Address
el
This control register provides the write/read enable when doing indirect writes/reads to the EQ RAM.
Description
Table 43. xCRS Register
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Portable Audio Consumer Codec
3.6.3.
Equalizer, Bass, Treble Coefficient & Equalizer Prescaler RAM
The EQ Coefficient RAM is a single port 161x24 synchronous RAM. It is programmed indirectly through the I2C Control
interface. Writing to the EQ coefficient RAM is done in the following manner as shown in the figure below:
1
Write EQ coefficient RAM target address to xCRADDregister. (EQ data is pre-fetched even if we don’t use it)
a I2C Start command followed by the I2C Device Address and Write flag
b Write the Register Address for the xCRADD register
c Write Register Data (EQ Coefficient RAM address)
2
Start a multiple write cycle
a I2C Start command followed by the I2C Device Address and Write Flag
b Register Address of the xCRADD register
c Write D7:0 to the xCRWDL register
d Write D15:8 to the xCRWDM register
e Write D23:16 to the xCRWDH register
On successful receipt of the WDATA_H data, the part will automatically start a write cycle. The ACCSTAT bit will be set
high to indicate that a write is in progress.
4
On completion of the internal write cycle, the ACCSTAT bit will be 0 (when operating the control interface at high speeds
- TBD - software must poll this bit to ensure the write cycle is complete before starting another write cycle.)
5
The bus cycle may be terminated by the host or steps 2-3 may be repeated for writes to consecutive EQ RAM locations.
in
ar
y
3
Generic write operation
DA6
DA0
W
AS
RA7
RA1
RA0
AS
RD7
RD0
im
SDA
multiple write cycle
writing 1 reigster
S
SCL
multiple write cycle
P
AS
RD7
RD0
AS
RD7
RD0
AS
el
2.5 uS
min.
EQ_A updated;
EQ RAM read req = 1
Pr
EQ RAM write operation
write EQ RAM
Address
1a
S
DA[6:0], W
1b
1c
RA[7:0]
RD[7:0]
S
register writen here
EQ RAM read finished;
EQ Read Data valid (time not fixed)
write EQ RAM
write EQ RAM
Write Mid
Write Lo
register writen here
28 SCL cycles
70 uS min. 4
3
EQ RAM write req = 1
write EQ RAM
Write Hi
2a
2b
2c
2d
2e
DA[6:0], W
RA[7:0]
RD[7:0]
RD[7:0]
RD[7:0]
EQ RAM Write Lo
updated here
EQ RAM write must have
finished here; EQ_A ++
write EQ RAM
Write Lo
5
S
DA[6:0], W
RA[7:0]
RD[7:0]
write EQ RAM
Write Mid
RD[7:0]
repeat for multiple consecutive EQ RAM locations writes
Figure 6. EQ Coefficient RAM Write Sequence
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Reading back a value from the EQ Coefficient RAM is done in this manner:
1
Write target address to xCRADD register.(EQ data is pre-fetched for read even if we don’t use it)
a I2C Start command followed by the I2C Device Address and Write flag
b Write the Register Address for the xCRADD register
c Write Register Data (EQ Coefficient RAM address)
2
I2C Start (or repeat start) a write cycle to xCRRDL and after the second byte (register address) is acknowledged, go to
step 3. (Do not complete the write cycle.)
a I2C Start command followed by the I2C Device Address and Write Flag
b Write Register Address of the xCRRDL register
Signal a repeat start, provide the I2C device address, and indicate a read operation
4
Read D7:0 (register address incremented after ack by host)
5
Read D15:8 (register address incremented after ack by host)
6
Read D23:16 (register address incremented and next EQ location pre-fetched after ack by host)
7
The host stops the bus cycle
y
3
To repeat a read cycle for consecutive EQ RAM locations:
Start (or repeat start instead of stopping the bus cycle in step 7) a write cycle indicating xCRRDL as the target address.
9
After the second byte is acknowledged, signal a repeated start.
ar
8
10 Indicate a read operation
in
11 Read the xCRRDL register as described in step 4
12 Read the xCRRDM register as described in step 5
im
13 Read the xCRRDH register as described in step 6
Generic read operation
el
14 Repeat steps 8-13 as desire
read 1 register
multiple read cycle
multiple read cycle
Sr
RA7
RA1
SCL
RA0
AS
DA6
DA0
Pr
SDA
EQ_A updated;
EQ RAM read req = 1
EQ RAM read operation
R
1a
1b
30 SCL cycles
75 uS min.
2a
DA[6:0], W
RA[7:0]
RD[7:0]
AM
RD7
DA[6:0], W
RA[7:0]
RD0
AM
RD7
RD0
NM
EQ RAM Data
must be valid here
EQ_A ++; prefetch data
read EQ RAM
Data Lo
read EQ RAM
Data Mid
read EQ RAM
Data Hi
4
5
6
Sr
P S
S
3
2b
RD0
EQ RAM Data
must be valid here
truncate write cycle
1c
RD7
NACK from master to end read cycle
Write
EQ RAM Read Lo
write EQ RAM Address
AS
7
8
write EQ RAM
Read Lo,
truncate
RD[7:0]
RD[7:0]
RD[7:0]
11
10
read EQ RAM
Data Lo
12
Sr
P S
DA[6:0], R
9
DA[6:0], W
RA[7:0]
DA[6:0], R
RD[7:0]
repeat for multiple consecutive EQ RAM locations reads
Figure 7. EQ Coefficient RAM Read Sequence
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Table 44. EQ Coefficient RAM Addresses For Speaker and DAC Channels
EQ 1
EQ2
Channel 0
Coefficients
Addr
Channel 1
Coefficients
Addr
Channel 0
Coefficients
Addr
Channel 1
Coefficients
0x00
EQ_COEF_0F0_B0
0x20
EQ_COEF_1F0_B0
0x40
EQ_COEF_2F0_B0
0x60
EQ_COEF_3F0_B0
0x01
EQ_COEF_0F0_B1
0x21
EQ_COEF_1F0_B1
0x41
EQ_COEF_2F0_B1
0x61
EQ_COEF_3F0_B1
0x02
EQ_COEF_0F0_B2
0x22
EQ_COEF_1F0_B2
0x42
EQ_COEF_2F0_B2
0x62
EQ_COEF_3F0_B2
0x03
EQ_COEF_0F0_A1
0x23
EQ_COEF_1F0_A1
0x43
EQ_COEF_2F0_A1
0x63
EQ_COEF_3F0_A1
0x04
EQ_COEF_0F0_A2
0x24
EQ_COEF_1F0_A2
0x44
EQ_COEF_2F0_A2
0x64
EQ_COEF_3F0_A2
0x05
EQ_COEF_0F1_B0
0x25
EQ_COEF_1F1_B0
0x45
EQ_COEF_2F1_B0
0x65
EQ_COEF_3F1_B0
0x06
EQ_COEF_0F1_B1
0x26
EQ_COEF_1F1_B1
0x46
EQ_COEF_2F1_B1
0x66
EQ_COEF_3F1_B1
0x07
EQ_COEF_0F1_B2
0x27
EQ_COEF_1F1_B2
0x47
EQ_COEF_2F1_B2
0x67
EQ_COEF_3F1_B2
0x08
EQ_COEF_0F1_A1
0x28
EQ_COEF_1F1_A1
0x48
EQ_COEF_2F1_A1
0x68
EQ_COEF_3F1_A1
0x09
EQ_COEF_0F1_A2
0x29
EQ_COEF_1F1_A2
0x49
EQ_COEF_2F1_A2
0x69
EQ_COEF_3F1_A2
0x0A
EQ_COEF_0F2_B0
0x2A
EQ_COEF_1F2_B0
0x4A
EQ_COEF_2F2_B0
0x6A
EQ_COEF_3F2_B0
0x0B
EQ_COEF_0F2_B1
0x2B
EQ_COEF_1F2_B1
0x4B
EQ_COEF_2F2_B1
0x6B
EQ_COEF_3F2_B1
0x0C
EQ_COEF_0F2_B2
0x2C
EQ_COEF_1F2_B2
0x0D
EQ_COEF_0F2_A1
0x2D
EQ_COEF_1F2_A1
0x0E
EQ_COEF_0F2_A2
0x2E
EQ_COEF_1F2_A2
0x0F
EQ_COEF_0F3_B0
0x2F
EQ_COEF_1F3_B0
0x4F
0x10
EQ_COEF_0F3_B1
0x30
EQ_COEF_1F3_B1
0x50
EQ_COEF_2F3_B1
0x70
EQ_COEF_3F3_B1
0x11
EQ_COEF_0F3_B2
0x31
EQ_COEF_1F3_B2
0x51
EQ_COEF_2F3_B2
0x71
EQ_COEF_3F3_B2
0x12
EQ_COEF_0F3_A1
0x32
EQ_COEF_1F3_A1
0x52
EQ_COEF_2F3_A1
0x72
EQ_COEF_3F3_A1
0x13
EQ_COEF_0F3_A2
0x33
EQ_COEF_1F3_A2
0x53
EQ_COEF_2F3_A2
0x73
EQ_COEF_3F3_A2
0x14
EQ_COEF_0F4_B0
0x34
EQ_COEF_1F4_B0
0x54
EQ_COEF_2F4_B0
0x74
EQ_COEF_3F4_B0
0x15
EQ_COEF_0F4_B1
0x35
EQ_COEF_1F4_B1
0x55
EQ_COEF_2F4_B1
0x75
EQ_COEF_3F4_B1
0x16
EQ_COEF_0F4_B2
0x36
EQ_COEF_1F4_B2
0x56
EQ_COEF_2F4_B2
0x76
EQ_COEF_3F4_B2
0x17
EQ_COEF_0F4_A1
0x37
EQ_COEF_1F4_A1
0x57
EQ_COEF_2F4_A1
0x77
EQ_COEF_3F4_A1
0x18
EQ_COEF_0F4_A2
0x38
EQ_COEF_1F4_A2
0x58
EQ_COEF_2F4_A2
0x78
EQ_COEF_3F4_A2
0x19
EQ_COEF_0F5_B0
0x39
EQ_COEF_1F5_B0
0x59
EQ_COEF_2F5_B0
0x79
EQ_COEF_3F5_B0
0x1A
EQ_COEF_0F5_B1
0x3A
EQ_COEF_1F5_B1
0x5A
EQ_COEF_2F5_B1
0x7A
EQ_COEF_3F5_B1
0x1B
EQ_COEF_0F5_B2
0x3B
EQ_COEF_1F5_B2
0x5B
EQ_COEF_2F5_B2
0x7B
EQ_COEF_3F5_B2
0x1C
EQ_COEF_0F5_A1
0x3C
EQ_COEF_1F5_A1
0x5C
EQ_COEF_2F5_A1
0x7C
EQ_COEF_3F5_A1
0x1D
EQ_COEF_0F5_A2
0x3D
EQ_COEF_1F5_A2
0x5D
EQ_COEF_2F5_A2
0x7D
EQ_COEF_3F5_A2
0x1E
-
0x3E
-
0x5E
-
0x7E
-
0x1F
EQ_PRESCALE0
0x3F
EQ_PRESCALE1
0x5F
EQ_PRESCALE2
0x7F
EQ_PRESCALE3
ar
EQ_COEF_2F2_B2
0x6C
EQ_COEF_3F2_B2
0x4D
EQ_COEF_2F2_A1
0x6D
EQ_COEF_3F2_A1
0x4E
EQ_COEF_2F2_A2
0x6E
EQ_COEF_3F2_A2
0x6F
EQ_COEF_3F3_B0
in
0x4C
im
el
Pr
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Table 45. EQ Coefficient RAM Addresses For Earpiece Channel
EQ 1
EQ2
Channel
Coefficients
Addr
Channel
Coefficients
0x00
EQ_COEF_0F0_B0
0x20
EQ_COEF_1F0_B0
0x01
EQ_COEF_0F0_B1
0x21
EQ_COEF_1F0_B1
0x02
EQ_COEF_0F0_B2
0x22
EQ_COEF_1F0_B2
0x03
EQ_COEF_0F0_A1
0x23
EQ_COEF_1F0_A1
0x04
EQ_COEF_0F0_A2
0x24
EQ_COEF_1F0_A2
0x05
EQ_COEF_0F1_B0
0x25
EQ_COEF_1F1_B0
0x06
EQ_COEF_0F1_B1
0x26
EQ_COEF_1F1_B1
0x07
EQ_COEF_0F1_B2
0x27
EQ_COEF_1F1_B2
0x08
EQ_COEF_0F1_A1
0x28
EQ_COEF_1F1_A1
0x09
EQ_COEF_0F1_A2
0x29
EQ_COEF_1F1_A2
0x0A
EQ_COEF_0F2_B0
0x2A
EQ_COEF_1F2_B0
0x0B
EQ_COEF_0F2_B1
0x2B
EQ_COEF_1F2_B1
0x0C
EQ_COEF_0F2_B2
0x0D
EQ_COEF_0F2_A1
0x0E
EQ_COEF_0F2_A2
0x0F
EQ_COEF_0F3_B0
0x2F
EQ_COEF_1F3_B0
0x10
EQ_COEF_0F3_B1
0x30
EQ_COEF_1F3_B1
0x11
EQ_COEF_0F3_B2
0x31
EQ_COEF_1F3_B2
0x12
EQ_COEF_0F3_A1
0x32
EQ_COEF_1F3_A1
0x13
EQ_COEF_0F3_A2
0x33
EQ_COEF_1F3_A2
0x14
EQ_COEF_0F4_B0
0x34
EQ_COEF_1F4_B0
0x15
EQ_COEF_0F4_B1
0x35
EQ_COEF_1F4_B1
0x16
EQ_COEF_0F4_B2
0x36
EQ_COEF_1F4_B2
0x17
EQ_COEF_0F4_A1
0x37
EQ_COEF_1F4_A1
ar
EQ_COEF_1F2_B2
0x2D
EQ_COEF_1F2_A1
0x2E
EQ_COEF_1F2_A2
Pr
el
im
in
0x2C
0x18
EQ_COEF_0F4_A2
0x38
EQ_COEF_1F4_A2
0x19
EQ_COEF_0F5_B0
0x39
EQ_COEF_1F5_B0
0x1A
EQ_COEF_0F5_B1
0x3A
EQ_COEF_1F5_B1
0x1B
EQ_COEF_0F5_B2
0x3B
EQ_COEF_1F5_B2
0x1C
EQ_COEF_0F5_A1
0x3C
EQ_COEF_1F5_A1
0x1D
EQ_COEF_0F5_A2
0x3D
EQ_COEF_1F5_A2
0x1E
-
0x3E
-
0x1F
EQ_PRESCALE0
0x3F
EQ_PRESCALE1
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Table 46. EQCRAM Multi-Band Compressor/Bass/Treble/3D Addresses
Addr
Bass
Addr
Treble
Addr
Addr
Coefficients
Multiband
Coefficients
BASS_COEF_EXT1_B0
0x97 TREB_COEF_EXT1_B0
0xAE
3D_COEF
0xB0
MBC1_BQ1_COEFF0
0x81
BASS_COEF_EXT1_B1
0x98 TREB_COEF_EXT1_B1
0xAF
3D_MIX
0xB1
MBC1_BQ1_COEFF1
0x82
BASS_COEF_EXT1_B2
0x99 TREB_COEF_EXT1_B2
0xB2
MBC1_BQ1_COEFF2
0x83
BASS_COEF_EXT1_A1
0x9A TREB_COEF_EXT1_A1
0xB3
MBC1_BQ1_COEFF3
0x84
BASS_COEF_EXT1_A2
0x9B TREB_COEF_EXT1_A2
0xB4
MBC1_BQ1_COEFF4
0x85
BASS_COEF_EXT2_B0
0x9C TREB_COEF_EXT2_B0
0xB5
MBC1_BQ2_COEFF0
0x86
BASS_COEF_EXT2_B1
0x9D TREB_COEF_EXT2_B1
0xB6
MBC1_BQ2_COEFF1
0x87
BASS_COEF_EXT2_B2
0x9E TREB_COEF_EXT2_B2
0xB7
MBC1_BQ2_COEFF2
0x88
BASS_COEF_EXT2_A1
0x9F TREB_COEF_EXT2_A1
0xB8
MBC1_BQ2_COEFF3
0x89
BASS_COEF_EXT2_A2
0xA0 TREB_COEF_EXT2_A2
0xB9
MBC1_BQ2_COEFF4
0x8A
BASS_COEF_NLF_M1
0xA1
TREB_COEF_NLF_M1
0xBA
MBC2_BQ1_COEFF0
0x8B
BASS_COEF_NLF_M2
0xA2
TREB_COEF_NLF_M2
0xBB
MBC2_BQ1_COEFF1
0x8C
BASS_COEF_LMT_B0
0xA3
TREB_COEF_LMT_B0
0xBC
MBC2_BQ1_COEFF2
0x8D
BASS_COEF_LMT_B1
0xA4
TREB_COEF_LMT_B1
0xBD
MBC2_BQ1_COEFF3
0x8E
BASS_COEF_LMT_B2
0xA5
TREB_COEF_LMT_B2
0xBE
MBC2_BQ1_COEFF4
0x8F
BASS_COEF_LMT_A1
0xA6
TREB_COEF_LMT_A1
0xBF
MBC2_BQ2_COEFF0
0x90
BASS_COEF_LMT_A2
0xA7
TREB_COEF_LMT_A2
0xC0
MBC2_BQ2_COEFF1
0x91
BASS_COEF_CTO_B0
0xA8
TREB_COEF_CTO_B0
0xC1
MBC2_BQ2_COEFF2
0x92
BASS_COEF_CTO_B1
0xA9
TREB_COEF_CTO_B1
0xC2
MBC2_BQ2_COEFF3
0x93
BASS_COEF_CTO_B2
0xAA TREB_COEF_CTO_B2
0xC3
MBC2_BQ2_COEFF4
0x94
BASS_COEF_CTO_A1
0xAB TREB_COEF_CTO_A1
0xC4
MBC3_BQ1_COEFF0
0x95
BASS_COEF_CTO_A2
0xAC TREB_COEF_CTO_A2
0xC5
MBC3_BQ1_COEFF1
0x96
BASS_MIX
0xAD
0xC6
MBC3_BQ1_COEFF2
0xC7
MBC3_BQ1_COEFF3
0xC8
MBC3_BQ1_COEFF4
0xC9
MBC3_BQ2_COEFF0
0xCA
MBC3_BQ2_COEFF1
el
in
ar
y
0x80
TREB_MIX
Pr
3.7.
3D
Coefficients
im
Coefficients
0xCB
MBC3_BQ2_COEFF2
0xCC
MBC3_BQ2_COEFF3
0xCD
MBC3_BQ2_COEFF4
Gain, Limiting, and Dynamic Range Control
The gain for a given channel is controlled by the MVOL_x registers. The range of gain supported is from -95.625db to 0db
in 0.375db steps. If the result of the gain multiply step would result in overflow of the 24-bit output word width, the output is
saturated at the max positive or negative value. In addition to simple gain control, the TSCS454 also provides sophisticated
dynamic range control. The dynamic range control processing element implements limiting, dynamic range compression,
and dynamic range expansion functions.
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3.7.1.
Limiter Compressor and Expander
The Limiter function will limit the audio output of the DSP module to the DAC’s and Class-D outputs. If the signal is greater
than 0dB it will saturate at 0dB as the final processing step within the DSP module.
There are times when the user may intentionally want the output Limiter to perform this saturation, for example +6dB of
gain applied within the DSP gain control and then limited to 0dB when output to the Class-D module would result in a
clipped signal driving the Speaker output. This clipped signal would obviously contribute to increased distortion on the
Speaker output which from the user listening perception it would “sound louder”.
At other times, the system designer may wish to protect speakers from overheating or provide hearing protection by
intentionally limiting the output level before full scale is reached. A limit threshold, independent of the compressor threshold
is provided for this purpose. It is expected that the limit threshold is set to a higher level than the compressor threshold.
-6 dBFS
Limit Threshold:
Compressor Threshold: -14.25 dBFS
Expander Threshold:
-18 dBFS
Compressor Ratio:
Expander Ratio:
3:1
1:2
ar
-4
-6
in
Output (dBFS)
-2
y
0
-8
im
-10
-12 Compressed Output Range
el
-14
Natural Output Range
Compressor Threshold
Pr
-16
-18
-20
Limit Threshold
Expander Threshold
Expanded
Output Range
-22
-22
-20
-18
-16
-14
-12
I
-10
t (dBFS)
-8
-6
-4
-2
0
Figure 8. Compressor, Output vs Input Gain
The traditional compressor algorithm provides two functions simultaneously (depending on signal level). For higher level
signals, it can provide a compression function to reduce the signal level. For lower level signals, it can provide an
expansion function for either increasing dynamic range or noise gating.
The compressor monitors the signal level and, if the signal is higher than a threshold, will reduce the gain by a programmed
ratio to restrict the dynamic range. Limiting is an extreme example of the compressor where, as the input signal level is
increased, the gain is decreased to maintain a specific output level.
In addition to limiting the bandwidth of the compressed audio, it is common for compressed audio to also compress the
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dynamic range of the audio. The expansion function inTSCS454 can help restore the original dynamics to the audio.
The expander is a close relative of the compressor. Rather than using signal dependent gain to restrict the dynamic range,
the expander uses signal dependent gain to expand the dynamic range. Thus if a signal level is below a particular
threshold, the expander will reduce the gain even further to extend the dynamic range of the material.
A basic block diagram of the compressor is shown below:
Audio In
Audio Out
Compare to Thresholds Lowpass filter
Gains based on
Calc Gain
Attack and release
ar
Peak or RMS
Attack/
release
filter
Gain
Calc
y
Level
Detector
Figure 9. Compressor Diagram
in
As this diagram shows, there are 3 primary components of the compressor.
Compressor Level Detector
el
Compressor Gain Calculation
im
The level detector, detects the level of the incoming signal. Since the comp/limiter is designed to work on blocks of signals,
the level detector will either find the peak value of the block of samples to be processed or the rms level of the samples
within a block.
The gain calculation block is responsible for taking the output of the level detector and calculating a target gain based on
that level and the compressor and expander thresholds.
Pr
The compressor recalculates the target gain value every block, typically every 10ms.
The gain calculation operates in 3 regions:
•
•
•
Linear region – If the level is higher than the expander threshold and lower than the compression threshold, then the gain is 1.0
Compression region – When the level is higher than the compressor threshold, then the comp/limiter is in the compression
region. The gain is a function of the compressor ratio and the signal level.
Expansion region – When the signal is lower than the expansion threshold, the comp/limiter is in the expansion region. In this
region, the gain is a function of the signal level and the expansion ratio.
Compression region gain calculation
In the compression region, the gain calculation is:
Atten(in db) = (1-1/ratio)(threshold(in db) – level(in db);
For example,
•
•
•
Ratio = 4:1 compression
Threshold = -16db
Level = -4 db
The required attenuation is: 9db or a gain coefficient of 0.1259.
Translating this calculation from log space to linear yields the formula:
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Gain =(level/threshold)1/ratio*(threshold/level)
Expansion region gain calculation
In the expansion region, the attenuation calculation is:
Atten(in db) = (1 - ratio)(threshold-level);
For example,
•
•
•
Ratio = 3:1
Threshold = -40db
Level = -44 db
The resulting attenuation required is 8db or a gain value of 0.1585.
The linear equation for calculating the gain is:
Gain =(level/threshold)ratio*(threshold/level)
y
If the calculated attenuation is more than the maximum possible attenuation(-96dB)the
the target gain value will be 0.0 or -00dB, which effectively creates a noise gate
function.
ar
State Transitions
In the compression region:
•
•
In the expansion region:
•
•
•
If the gain calculated is less than the last gain calculated (more compression is being applied), then the filter coefficient is the
compressor attack.
If the gain calculated is more than the last gain calculated (less compression), the filter coefficient is the compressor release.
im
•
If the calculated gain is less than the last gain calculated (closing expander, the filter coefficient is the expander attack.
If the calculated gain is more than the last gain calculated, the filter coefficient is the expander release.
In the linear region:
el
•
in
In addition to calculating the new gain for the compressor, the gain calculation block will also select the filter coefficient for
the attack/release filter. The rules for selecting the coefficient are as follows:
Modify gain until a gain of 1.0 is obtained.
If the last non-linear state was compression, use the compressor release.
If the last non-linear state was expansion, use the expander attack.
Pr
•
•
Attack/Release filter
In order to prevent objectionable artifacts, the gain is smoothly ramped from the current value to the new value calculated
by the gain calculation block. In the PC-based comp/limiter, this is achieved using a simple tracking lowpass filter to smooth
out the abrupt transitions. The calculation (using the coefficient (coeff) selected by the gain block) is:
Filtered_gain = coeff*last_filtered_gain + (1.0 - coeff)*target_gain;
This creates a exponential ramp from the current gain value to the new value.
3.7.2.
Configuration
This compressor limiter provides the following configurable parameters.
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Compressor/limiter
•
•
•
•
•
Expander
•
•
•
•
•
•
•
Threshold – The threshold below which the expander will increase the dynamic range of the audio.
Ratio – The ratio between the input dynamic range and the output dynamic range of the audio in the expansion range. For
example a ratio of 3 will take an input dynamic range of 9db and expand it to 27db.
Attack Time– The amount of time that changes in gain are smoothed over during the attack phase of the expander
Release Time
- The amount of time that changes in gain are smoothed over during the release phase of the expander.
Two level detection algorithms
•
•
RMS – Use an RMS measurement for the level.
Peak – Use a peak measurement for the level.
3.7.3.
y
•
Threshold – The threshold above which the compressor will reduce the dynamic range of the audio in the compression region.
Ratio – The ratio between the input dynamic range and the output dynamic range. For example, a ratio of 3 will reduce an input
dynamic range of 9db to 3db.
Attack Time – The amount of time that changes in gain are smoothed over during the attack phase of the compressor.
Release Time – The amount of time that changes in gain are smoothed over during the release phase of the compressor.
Makeup gain – Used to increase the overall level of the compressed audio.
ar
•
Controlling Parameters
Compressor/limiter
Expander
•
•
•
•
•
Threshold - -30 to -60 dB
Ratio – 1 to 6
Attack Time – same as above
Release Time – same as above.
el
•
Threshold - -40db to 0db relative to full scale.
Ratio – 1 to 20
Attack Time – typically 0 to 500ms
Release Time – typically 25ms to 2 seconds
Makeup gain – 0 to 40db
im
•
•
•
•
•
Two level detection algorithms
•
•
RMS
Peak
Pr
•
in
In order to control this processing, there are a number of configurable parameters. The parameters and their ranges are:
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3.7.4.
Compressor/Limiter/Expander Control Registers
3.7.4.1.General Compressor/Limiter/Expander Control Registers
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Type
Default
Description
7:5
RSVD
R
0h
Reserved
4
LVLMODE
RW
0
CLE Level Detection Mode:
0 = Average
1 = Peak
3
WINSEL
RW
0
CLE Level Detection Window:
0 = Equivalent of 512 samples at the selected Base
Rate (~10-16ms)
1 = Equivalent of 64 samples at the selected Base
Rate (~1.3-2ms
2
EXPEN
RW
0
Expander Enable:
0 = Disabled
1 = Enabled
1
LIMEN
RW
0
0
COMPEN
RW
ar
y
Label
Limiter Enable:
0 = Disabled
1 = Enabled
in
Page y, Reg 33 -21h
xCLECTL
Bit
0
Compressor Enable:
0 = Disabled
1 = Enabled
im
Register Address
el
Table 47. xCLECTL Register
3.7.4.2.x_Compressor Make-up Gain (xCLEMUG) Register
Register Address
Page y, Reg 34 - 22h
xCLEMUG
Pr
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Bit
Label
Type
Default
Description
7:5
RSVD
R
0h
Reserved
4:0
xMUGAIN[4:0]
RW
0h
0dB...46.5dB in 1.5dB steps
Table 48. xCLEMUG Register
3.7.4.3.x_Compressor Threshold (xCOMPTHR) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Page y, Reg 35 - 23h
xCOMPTHR
7:0
xTHRESH[7:0]
RW
00h
Description
FFh...00h = 0dB...95.625dB in 0.375dB steps.
Table 49. xCOMPTHR Register
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3.7.4.4.x_Compressor Compression Ratio (xCOMPRAT) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 36 -24h
xCOMPRAT
Bit
Label
Type
Default
7:5
RSVD
R
000
Reserved
00h
Compressor Ratio
00h = Reserved
01h = 1.5:1
02h...14h = 2:1...20:1
15h...1Fh = Reserved
4:0
xRATIO[4:0]
RW
Description
Table 50. xCOMPRAT Register
3.7.4.5.Compressor Attack Time Constant (xCOMPATKL) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
xTCATKL[7:0]
RW
Default
00h
Description
y
Type
Low byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
ar
7:0
Label
im
Page y, Reg 37 -25h
xCOMPATKL
Bit
in
Register Address
Table 51. xCOMPATKL Register
3.7.4.6.Compressor Attack Time Constant (xCOMPATKH) Register (High)
Bit
Label
Type
Default
Pr
Register Address
el
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Page y, Reg 38 - 26h
xCOMPATKH
7:0
xTCATKH[7:0]
RW
Description
High byte of the time constant used to ramp to a new
gain value during a compressor attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
00h
0002h = 0.96875 + 2/(2^21)
... (step = 1/(2^21))
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
Table 52. xCOMPATKH Register
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3.7.4.7.Compressor Release Time Constant (xCOMPRELL) Register (Low)
Register Address
Page y, Reg 39 - 27h
xCOMPRELL
Bit
7:0
Label
Type
xTCRELL[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a compressor release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 53. xCOMPRELL Register
3.7.4.8.Compressor Release Time Constant (xCOMPRELH) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
xTCRELH[15:8]
RW
Default
00h
Description
y
Type
High byte of the time constant used to ramp to a new
gain value during a compressor release phase. The
time constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
ar
7:0
Label
im
Page y, Reg 40 - 28h
xCOMPRELH
Bit
in
Register Address
Table 54. xCOMPRELH Register
el
3.7.4.9.Limiter Threshold (xLIMTH) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Page y, Reg 41 - 29h
xLIMTH
Bit
Label
Type
Pr
Register Address
7:0
xTHRESH[7:0]
RW
Default
00h
Description
FFh...00h = 0dB...95.625dB in 0.375dB steps.
Table 55. xLIMTH Register
3.7.4.10.Limiter Target (xLIMTGT) Register
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Label
Type
Default
Page y, Reg 42 - 2Ah
xLIMTGT
7:0
xTARGET[7:0]
RW
00h
Description
FFh...00h = 0dB...95.625dB in 0.375dB steps.
Table 56. xLIMTGT Register
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3.7.4.11.Limiter Attack Time Constant (xLIMATKL) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Page y, Reg 43 2Bh
xLIMATKL
7:0
Label
Type
xTCATKL[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a limiter attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 57. xLIMATKL Register
3.7.4.12.Limiter Attack Time Constant (xLIMATKH) Register (High)
Bit
Label
Type
Default
Description
ar
Register Address
y
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
xTCATKH[15:8
RW
in
7:0
00h
im
Page y, Reg 44 - 2Ch
xLIMATKH
High byte of the time constant used to ramp to a new
gain value during a limiter attack phase. The time
constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
el
Table 58. xLIMATKH Register
3.7.4.13.Limiter Release Time Constant (xLIMRELL) Register (Low)
Register Address
Pr
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Page y, Reg 45 - 2Dh
xLIMRELL
Bit
7:0
Label
Type
xTCRELL[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a limiter release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 59. xLIMRELL Register
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3.7.4.14.Limiter Release Time Constant (xLIMRELH) Register (High)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Bit
Page y, Reg 46 - 2Eh
xLIMRELH
7:0
Label
Type
xTCRELH[15:8]
RW
Default
Description
High byte of the time constant used to ramp to a new
gain value during a limiter release phase. The time
constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
3.7.4.15.Expander Threshold (xEXPTHR) Register
Bit
Label
Type
Page y, Reg 47 - 2Fh
xEXPTHR
7:0
xTHRESH[7:0]
RW
Default
Description
in
Register Address
ar
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
y
Table 60. xLIMRELH Register
00h
Expander threshold: 0...95.625dB in 0.375dB steps
im
Table 61. xEXPTHR Register
3.7.4.16.Expander Ratio (xEXPRAT) Register
Register Address
Bit
Page y, Reg 48 - 30h
xEXPRAT
Label
Type
Default
RSVD
R
00h
Reserved
000
Expander Ratio
0h...1h = Reserved
2h...7h = 1:2...1:7
Pr
7:3
el
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
xRATIO[2:0]
RW
Description
Table 62. xEXPRAT Register
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3.7.4.17.Expander Attack Time Constant (xEXPATKL) Register (Low)
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Register Address
Page y, Reg 49 - 31h
xEXPATKL
Bit
7:0
Label
Type
xTCATKL[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a expander attack phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
00h
Table 63. xEXPATKL Register
3.7.4.18.Expander Attack Time Constant (xEXPATKH) Register (High)
Bit
Label
Type
Default
Description
ar
Register Address
y
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
xTCATKH[15:8]
RW
in
7:0
00h
im
Page y, Reg 50 - 32h
xEXPATKH
High byte of the time constant used to ramp to a new
gain value during a expander attack phase. The time
constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
el
Table 64. xEXPATKH Register
3.7.4.19.Expander Release Time Constant (xEXPRELL) Register (Low)
Register Address
Page y, Reg 51 - 33h
xEXPRELL
Pr
Where x = SPK, DAC, SUB, y= Page 3, 4, 5
Bit
7:0
Label
Type
xTCRELL[7:0]
RW
Default
Description
Low byte of the time constant used to ramp to a new
gain value during a expander release phase.
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
0
Table 65. xEXPRELL Register
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3.7.4.20.Expander Release Time Constant (xEXPRELH) Register (High)
Where x = SPK, DAC, SUBSUB, y= Page 3, 4, 5
Register Address
Page y, Reg 52 - 34h
xEXPRELH
Bit
7:0
Label
Type
xTCRELH[15:8]
RW
Default
Description
High byte of the time constant used to ramp to a new
gain value during a expander release phase. The
time constant is [high byte, low byte]
0000h = 0 (instantaneous)
0001h = 0.96875 + 1/(2^21)
0002h = 0.96875 + 2/(2^21)
... ( step = 1/(2^21) )
FFFEh = [(2^21)-2]/(2^21)
FFFFh = [(2^21)-1]/(2^21)
0
3.8.
Mute and De-Emphasis and Phase Inversion
y
Table 66. xEXPRELH Register
in
ar
The TSCS454 has a Soft Mute function, which is used to gradually attenuate the digital signal volume to zero. The gain
returns to its previous setting if the soft mute is removed. At startup, the codec is muted by default; to enable audio play, the
mute bit must be cleared to 0.
im
After the equalization filters, de-emphasis may be performed on the audio data to compensate for pre-emphasis that may
be included in the audio stream. De-emphasis filtering is only available for 48kHz, and 44.1kHz sample rates.
Normal stereo operation converts left and right channel digital audio data to analog in separate DACs. However, it is also
possible to have the same signal (left or right) appear on both analog output channels by disabling one channel. The DAC
output defaults to non-inverted. Setting DACPOLL and DACPOLR bits will invert the DAC
Pr
el
See xCTL registers ( (x = DAC, SPK and SUB) in the following sections for the control of the mute, de-emphasis and phase
inversion.
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3.9.
Output Post Processing
Following the Output Processor the digital audio data is up-sampled and sent to the PWM/DAC blocks for analog
conversion.
Interpolation and Filtering
Input Rate =
32/44.1/48kHz (1X):
Input Rate =
64/88.2/96kHz (2X):
22
57T FIR-A
2X
24
2X
2X
24
64kHz
88.2kHz
96kHz
Full
Input Rate =
From I2S
16/22.05/24kHz (HX):
Input Rate =
32/44.1/48kHz (1X):
From I2S
Input Rate =
64/88.2/96kHz (2X):
From I2S
2X
24
2X
24
2X
24
Input Rate =
From I2S
16/22.05/24kHz (HX):
2X
24
32kHz
44.1kHz
48kHz
2X
22
57T FIR-A
64kHz
88.2kHz
96kHz
To Analog DAC
To Analog DAC
2X
2X
22
7T FIR-C
32kHz
44.1kHz
48kHz
2X
20X
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
1
SDM
128kHz
176.4kHz
192kHz
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
1
SDM
128kHz
176.4kHz
192kHz
20X
1
SDM
128kHz
176.4kHz
192kHz
20
7T FIR-C
64kHz
88.2kHz
96kHz
20X
20
7T FIR-D
64kHz
88.2kHz
96kHz
22
20X
1
5.120MHz
7.056MHz
7.680MHz
1
22
2X
To Analog DAC
5.120MHz
7.056MHz
7.680MHz
5.120MHz
7.056MHz
7.680MHz
11T FIR-B
64kHz
88.2kHz
96kHz
24
From I2S
20X
To Analog DAC
5.120MHz
7.056MHz
7.680MHz
1
SDM
SDM
SDM
11T FIR-B
22
57T FIR-A
From I2S
2X
20X
256kHz
352.8kHz
384kHz
22
22
32kHz
44.1kHz
48kHz
20X
1
SDM
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
1
SDM
128kHz
176.4kHz
192kHz
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
Pr
Input Rate =
64/88.2/96kHz (2X):
2X
256kHz
352.8kHz
384kHz
20
256kHz
352.8kHz
384kHz
20
7T FIR-C
128kHz
176.4kHz
192kHz
20
2X
57T FIR-A
2X
256kHz
352.8kHz
384kHz
11T FIR-B
2X
7T FIR-D
20X
20
7T FIR-E
128kHz
176.4kHz
192kHz
20
128kHz
176.4kHz
192kHz
el
Input Rate =
32/44.1/48kHz (1X):
2X
11T FIR-B
16kHz
22.05kHz
24kHz
24
2X
2X
20
7T FIR-D
64kHz
88.2kHz
96kHz
7T FIR-C
64kHz
88.2kHz
96kHz
22
22
57T FIR-A
16kHz
22.05kHz
24kHz
2X
128kHz
176.4kHz
192kHz
24
8kHz
11.025kHz
12kHz
2X
22
22
22
57T FIR-A
2X
Input Rate =
From I2S
8/11.024/12kHz (QX):
2X
7T FIR-C
11T FIR-B
64kHz
88.2kHz
96kHz
64kHz
88.2kHz
96kHz
Half
2X
22
57T FIR-A
To Analog DAC
5.120MHz
7.056MHz
7.680MHz
32kHz
44.1kHz
48kHz
11T FIR-B
To Analog DAC
5.120MHz
7.056MHz
7.680MHz
1
SDM
22
22
32kHz
44.1kHz
48kHz
1
SDM
256kHz
352.8kHz
384kHz
20
11T FIR-B
57T FIR-A
32kHz
44.1kHz
48kHz
20X
256kHz
352.8kHz
384kHz
22
16kHz
22.05kHz
24kHz
20X
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
20
11T FIR-B
57T FIR-A
16kHz
22.05kHz
24kHz
2X
To Analog DAC
2.560MHz
3.528MHz
3.840MHz
1
SDM
7T FIR-C
128kHz
176.4kHz
192kHz
2X
24
8kHz
11.025kHz
12kHz
2X
20X
1
SDM
128kHz
176.4kHz
192kHz
20
128kHz
176.4kHz
192kHz
22
128kHz
176.4kHz
192kHz
2X
Input Rate =
From I2S
8/11.024/12kHz (QX):
2X
22
57T FIR-A
From I2S
2X
7T FIR-C
64kHz
88.2kHz
96kHz
11T FIR-B
64kHz
88.2kHz
96kHz
20X
20
7T FIR-D
64kHz
88.2kHz
96kHz
22
22
57T FIR-A
32kHz
44.1kHz
48kHz
2X
22
7T FIR-C
32kHz
44.1kHz
48kHz
11T FIR-B
32kHz
44.1kHz
48kHz
24
From I2S
2X
22
57T FIR-A
16kHz
22.05kHz
24kHz
2X
22
11T FIR-B
16kHz
22.05kHz
24kHz
y
Input Rate =
From I2S
16/22.05/24kHz (HX):
2X
24
8kHz
11.025kHz
12kHz
ar
2X
Input Rate =
From I2S
8/11.024/12kHz (QX):
in
AUTO
im
3.9.1.
Figure 10. Output Interpolators and Filtering
3.10
Analog Audio Outputs
Refer to Figure 2, “Output Processing Flow,” on page 15. After the audio data is selected by the SSS the data is sent to the
Output Processor, interpolator-filters, and finally to the DAC and output amplifiers for analog output generation. For digital
audio data I2S PCM outputs are provided. A analog in bypass path exists that enables analog audio input via the Line
Input1 to be sent directly and summed with the DAC output.
Following the Output Processor the digital audio data is up-sampled via the interpolator and sent to the PWM/DAC blocks
for analog conversion.
The Analog Audio outputs are specified as follows:
•
Stereo, Class D, BTL Amplified Outputs - 1W into 8 ohms, 2W into 4 ohms
•
Mono, Class AB, Earpiece Amplified Output - 40mw into 16 ohms
•
Stereo, Class H, Headphone Amplified Outputs - 40mw into 16 ohms, Capless
•
Stereo, Class AB, Line Level Output - 1VRMS into 10K ohm load, Capless
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3.10.1.
Headphone Output
The HPOut pins can drive a 16 or 32 headphone. The signal volume of the headphone amplifier can be independently
adjusted under software control by writing to HPVOL_L and HPVOL_R. Setting the volume to 0000000 will mute the output
driver; the output remains at ground, so that no click noise is produced when muting or un-muting.
Gains above 0dB run the risk of clipping large signals.
To minimize artifacts such as clicks and zipper noise, the headphone outputs feature a volume fade function that smoothly
changes volume from the current value to the target value.
3.10.1.1. DAC/Headphone Volume Control Register
Type
Default
7
RSVD
R
0
Reserved
y
Left Headphone Volume, 0.75dB per step
1111111 = +6dB
1111110 = +5.25dB
…
1110111 = 0dB
1110111
...
(0dB)
0000001 = -88.5dB
0000000 = Analog mute
Note: If HPVOLU is set, this setting will take effect
after the next write to the Right Headphone Volume
register.
RW
7
RSVD
R
ar
HPVOL_L
[6:0]
6:0
Description
in
6:0
HPVOL_R
[6:0]
RW
Pr
Page 2, Reg 11 -Bh
HPVOLR
Label
0
Reserved
im
Page 2, Reg 10 -Ah
HPVOLL
Bit
Right Headphone Volume, 0.75dB per step
1111111 = +6dB
1111110 = +5.25dB
…
1110111
1110111 = 0dB
...
0000001 = -88.5dB
0000000 = Analog mute
el
Register Address
Table 67. HPVOLL/HPVOLR Register
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3.10.1.2.DAC Control Register
Register Address
Bit
Label
Type
Default
7
DACPOLR
RW
0
Invert DAC Right signal
6
DACPOLL
RW
0
Invert DAC Left signal
5:4
DACDITH
RW
00
DAC Dither Mode: 0h = Dynamic, Half Amplitude; 1h
= Dynamic, Full Amplitude; 2h = Disabled; 3h = Static
3
DACMU
RW
1
Digital Soft Mute
1 = mute
0 = no mute (signal active)
2
DACDEM
RW
0
De-emphasis Enable
1 = De-emphasis Enabled
0 = No De-emphasis
1
RSVD
R
0
Reserved
0
ABYPASS
RW
0
Analog Bypass from MUXLIN, MUXRIN to HP Output
0 = Analog Bypass to Headphone Output Disabled
1 = Analog Bypass to Headphone Output Enabled
ar
y
Page 2, Reg 1 - 1h
DACCTL
Description
Table 68. DACCTL Register
in
3.10.1.3.Low Power Analog Input to Headphone Output Passthrough Mode.
Pr
el
im
A low power operating mode is provided that allows the output from the Input Analog Mux to be selected to drive the input
to the headphone amplifier (DACCTL register, Bit 0 -ABYPASS). In this mode the TSCS454 can be put into a very low
power consumption state while allowing the selected analog audio input to be selected as the source for the headphone
amplifier output.
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3.10.2 Speaker Outputs
3.10.2.1.Speaker Volume Control
The LSPKOut (L+, L-) and RSPKOut (R+, R-) pins are controlled similarly, but independently of, the headphone output
pins. They are intended to drive an 8 ohm speaker pair.
Register Address
Label
Type
Default
7
RSVD
R
0
6:0
SPKVOL_L
[6:0]
RW
7
RSVD
R
Description
Reserved
Left Speaker Volume
1111111 = +12dB
1111110 = +11.25dB
…
1101111 1101111 = 0dB
(0dB)
...
0001000 to 0000001 = -77.25dB
0000000= Mute
Note: If SPKVOLU is set, this setting will take effect
after the next write to the Right Input Volume register.
SPKVOL_R
[6:0]
RW
Reserved
Right Speaker Volume
1111111 = +12dB
1111110 = +11.25dB
1101111 …
(0dB)
1101111 = 0dB
...
0001000 to 0000001 = -77.25dB
0000000 = Mute
in
6:0
0
im
Page 2, Reg 13 - Dh
SPKVOLR
ar
y
Page 2, Reg 12 - Ch
SPKVOLL
Bit
el
Table 69. SPKVOLL/ SPKVOLR Registers
Register Address
Page 2, Reg 2 - 2h
SPKCTL
Pr
3.10.2.2.Speaker Control Register
Bit
Label
Type
Default
Description
7
SPKPOLR
RW
0
Speaker Right Polarity
0 = normal
1 = invert
6
SPKPOLL
RW
0
Speaker Left Polarity
0 = normal
1 = invert
5:4
RSVD
R
00
Reserved
3
SPKMUTE
RW
1
Mute
1 = mute
0 = no mute (signal active)
2
SPKDEM
RW
0
De-emphasis Enable
1 = De-emphasis Enabled
0 = No De-emphasis
1:0
RSVD
R
00
Reserved
Table 70. SPKCTL Register
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Portable Audio Consumer Codec
3.10.3.
Earpiece Output
3.10.3.1.SUB Volume Control
The SUBOut (+, -) pins are controlled similarly, but independently of, the headphone output pins. They are intended to drive
a 16 or 32 ohm speaker.
Register Address
Bit
Label
Type
Default
7
RSVD
R
0
6:0
SUBVOL
[6:0]
RW
Description
Reserved
1101111 SUB Speaker Volume
(0dB)
1111111 = +12dB
1111110 = +11.25dB
…
1101111 = 0dB
...
0001000 to 0000001 = -77.25dB
0000000= Mute
Note: If SPKVOLU is set, this setting will take effect
after the next write to the Right Input Volume register.
ar
y
Page 2, Reg 16 - 10h
SUBVOL
in
Table 71. SUBVOL Register
Bit
Label
7
SUBPOL
6:4
Default
RW
0
SUB Polarity
0 = normal
1 = invert
R
0
Reserved
RSVD
Description
3
SUBMU
RW
1
Mute
1 = mute
0 = no mute (signal active)
2
SUBDEM
RW
0
De-emphasis Enable
1 = De-emphasis Enabled
0 = No De-emphasis
1
SUBMUX
RW
0
Selects Input Into SUB Amplifier
0 = Output Process
1 = Mix from Output Processor Left/2 + Right/2
0
SUBILDIS
R
0
Sub Output Current Limiter
1 = Disable
0 = Enable
Pr
Page 2, Reg 3 - 3h
SUBCTL
Type
el
Register Address
im
3.10.3.2.SUB Speaker Output Control Register
Table 72. SUBCTL Register
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Portable Audio Consumer Codec
3.10.4.
Class D Audio Processing
For additional information on the DDXTM Class D solution, please see the application note on www.Temposemi.com.
The DDXTM Class D PWM Controller performs the following signal processing:
•
Feedback filters are applied to shape any noise. The filters move noise from audible frequencies
to frequencies above the audio range.
•
The PWM block converts the data streams to tri-state PWM signals and sends them to the
power stages.
•
Finally, the Class-D controller block adjusts the output volume to provide constant output power
across supply voltage.
The power stages boost the signals to higher levels, sufficient to drive speakers at a comfortable listening level.
3.10.4.1.Constant Output Power Mode
ar
y
In normal operation the BTL amplifier is rated at 0.5W (full scale digital with 6dB BTL gain) into an 8 ohm load at 3.6V but
will vary from about 0.38W to about 1.2W across a 3.1V to 5.5V supply range. However, when constant output power
mode is enabled, the full scale output is held constant from 3.1V to 5.5V
in
The BTL amplifier in TSCS454 will continuously adjust to power supply changes to ensure that the full scale output power
remains constant. This is not an automatic level control. Rather, this function prevents sudden volume changes when
switching between battery and line power. Please note, when in this mode the amplifier efficiency may be reduced and
decreases with higher supply voltages and lower target values.
im
A simple 5-bit ADC is used to monitor PVDD. As PVDD raises or lowers, the analog circuit will send a 5-bit code to the
digital section that will average and then calculate a gain adjustment. The BTL audio signal will be multiplied by this gain
value (in addition to the user volume controls).
Pr
el
The user will select a target value for the circuit. The constant output function will calculate a gain adjustment that will
provide approximately the same full scale output voltage as provided when PVDD causes the same code value. So, if the
target is 9 then a PVDD voltage of about 3.7V would generate a code value of 9 and a full scale output power of about
630mW into 8 ohms. If PVDD should rise to 4V, generating a code of 13, then the constant output power circuit would
reduce the gain by 0.75dB (4 codes * 0.1875dB) to keep the full scale output at the target level.
The circuit may be configured to add gain, attenuation, or both to maintain the full-scale output level. If the needed
adjustment falls outside of the range of the circuit (only attenuation is enabled and gain is needed, for example) then the
circuit will apply as much correction as it is able. Through the use of gain, attenuation, and target values, different behaviors
may be implemented:
a Attenuation only, target set to mimic a low supply voltage - Constant output level across battery state with constant
quality (THD/SNR)
b Attenuation only, target set to mimic a moderate supply voltage - Output limiting to an approximate power level. Level
will decrease at lower supply voltages but won’t increase beyond a specific point.
c Gain only, target at or near max - Output will remain relatively constant but distortion will increase as PVDD is
lowered. This mimics the behavior of common class-AB amplifiers.
d Gain and attenuation - Output remains at a level below the maximum possible at the highest supply voltage and
above the theoretical full scale at minimum supply. Full scale PCM input clips when the supply voltage is low but
won’t become too loud when the supply voltage is high.
In addition to maintaining a constant output level, PVDD may be monitored for a large, sudden, change. If the High Delta
function is enabled and PVDD changes more than 4 code steps since the last cycle, the output will be rapidly reduced then
gradually increased to the target level.
55
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When using this circuit, please take note of the following:
a The full scale output power may be limited by the supply voltage.
b Full scale output power is affected by other gain controls in the output path including the EQ and compressor/limiter.
c The Constant Output Power function is intended to help maintain a constant output level, not an exact output level.
The output level for a specific target may vary part to part. If limiting is required for safety or other reasons, be
conservative and set the target well below the maximum allowable level.
d Noise on the PVDD supply may cause erratic behavior. Use the recommended supply decoupling caps and verify
that the power supply can support the peak currents demanded by a class-D amplifier.
Constant Output Power error (dB) relative to a target of 8 for an ideal part and the output error if left uncorrected across a
3.1 to 5.5V supply range.
3
y
2
0
4.1
Pr
‐3
Nom dB
el
‐1
‐2
5.1
relative to target
im
3.1
in
ar
1
Figure 11. Uncorrected & Corrected Constant Output Power
Constant Output Power for nominal and high/low reference across a 3.1 to 5.5V supply range.(Uncorrected power shown
56
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for reference) A target of 8 roughly corresponds to 0.5W at 3.6V into 8 ohms.
1.2
1.1
1
0.9
0.8
Off
0.7
Nom
Hi
Low
0.6
y
0.5
ar
0.4
0.3
0.2
4.1
in
3.1
5.1
im
Figure 12. Corrected Constant Output Power
3.10.4.2.Under Voltage Lock Out
el
When the PVDD supply becomes low, the BTL amplifier may be disabled to help prevent undesirable amplifier operation
(overheat) or system level problems (battery under-voltage.)
Pr
The same circuit that monitors the PVDD supply to help maintain a constant output power is used to monitor the PVDD
supply for a critical under-voltage situation. If the sense circuit consistently returns a 0 code then the PVDD supply is less
than the minimum required for proper operation. To prevent accidental shutdown due to a noisy supply at the minimum
operating range, the output of the PVDD sense circuit will be averaged for at least 200ms.
3.10.4.3.Constant Output Power 0 (COP0) Register
Register Address
Page 2, Reg 17 - 11h
COP0
Bit
Label
Type
Default
Description
7
COPATTEN
RW
0
1 = Constant Output Power function will attenuate
the BTL output if the PVDD sense circuit returns a
code higher than the target value.
6
COPGAIN
RW
0
1 = Constant Output Power function will increase the
BTL output if the PVDD sense circuit returns a code
higher than the target value.
5
HDELTA
RW
0
1 = If the PVDD code value has changed more than
4 counts since the last gain adjustment, the output
will be reduced rapidly then slowly returned to the
target level.
4:0
COPTARGET[4:0]
RW
8h
5-bit target for the Constant Output Power function.
Table 73. COP0 Register
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3.10.4.4.Constant Output Power 1 (COP1) Register
Register Address
Bit
Label
Type
Default
7
RSVD
R
0
Reserved
0
0 = Compare current poll value to last average to
detect high delta event.
1 = Compare current poll value to last poll value to
detect high delta event.
6
5:2
RW
AVGLENGTH[3:0]
RW
Number of sense cycles to average:
0000 = 1
0001 = 2
0010 = 4
0011 = 8
0100 = 16
0101 = 32
0110 = 64
0111 = 128
1000 = 256
1001 = 512
1010 - 1111 = Reserved
0000
MONRATE[2:0]
RW
10
Rate the PVDD supply is monitored:
00 = 0.25ms
01 = 0.5ms
10 = 1ms
11 = 2ms
in
1:0
ar
y
Page 2 ,Reg 18 - 12h
COP1
HDCOMPMODE
Description
im
Table 74. COP1 Register
3.10.4.5.Constant Output Power Status (COPSTAT) Register
Bit
Page 2, Reg 19 - 13h
COPSTAT
Type
Default
HDELTADET
R
0
1 = A high delta situation has been detected (positive
code change > 4) and the constant output power
function is adjusting.
0
1 = PVDD is below the under voltage lockout
threshold.
0h
Amount that the Constant Output Power function is
adjusting the signal gain. Value is 2s compliment with
each step equal to 0.1875dB. The approximate
range is +/- 6dB
Pr
7
Label
el
Register Address
6
5:0
UV
R
COPADJ[5:0]
R
Description
Table 75. COPSTAT Register
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3.10.4.6.PWM Control 0 Register
Bit
Type
Default
Description
7:6
SCTO[1:0]
RW
11
Class-D Short Circuit Detect Time-out
00 = 10uS
01 = 100uS
10 = 500uS
11 = 100mS
5
UVLO
RW
0
Under Voltage Lock Out
1 = BTL output disabled if PVDD sense circuit
returns code 0
R
1
Reserved
4
3
BFDIS
RW
0
1 = disable binomial filter
2
PWMMODE
RW
1
PWM Modulation Type: 0 = Binary; 1 = Ternary
R
0
Reserved
RW
0
PWM Frame Offset Disable: 0 = Right Frame Offset
from Left; 1 = Left & Right Frames Alligned
1
0
NOOFFSET
y
Page 2, Reg 20 - 14h
PWM0
Label
ar
Register Address
3.10.4.7.PWM Control 1 Register
Label
7
RSVD
6:4
DITHPOS[4:0]
3:2
Default
Description
R
0
Reserved
RW
0
PWM Dither Position: 0h = Full Dither; 1h = 1/2
Dither; 2h = 1/4 Static Only; 3h = 1/8 Static Only; 4h =
1/16 Static Only; 5h .. 7h = Reserved
R
Reserved
DYNDITH
RW
1
PWM Dynamic Dither: 0 = Static Dither; 1 = Dynamic
Dither
DITHDIS
RW
0
PWM Dither clear: 0 = Dither not cleared; 1 = Dither
cleared
Pr
1
Type
im
Page 2 , Reg 21 - 15h
PWM1
Bit
el
Register Address
in
Table 76. PWM0 Register
0
Table 77. PWM1 Register
NOTE: Dither is currently not implemented/working. This register retained for future revisions.
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3.10.4.8.PWM Control 3 Register
Register Address
Page 4, Reg 23 - 17h
PWM3
Bit
7:6
Label
Type
PWMMUX[1:0]
5:3
2:0
CVALUE[5:0]
Default
Description
RW
00
pwm output muxing
0 = normal
1 = swap 0/1
2 = ch0 on both
3 = ch1 on both
R
00
Reserved
RW
03h
tristate constant field, must be even and not 0
Pr
el
im
in
ar
y
Table 78. PWM3 Register
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3.11. Thermal Shutdown
To avoid overpower and overheating the codec when the amplifier outputs are driving large currents, the TSCS454
incorporates a thermal protection circuit. If enabled, and the device temperature reaches approximately 150°C, the speaker
and headphone amplifier outputs will be disabled. Once the device cools, the outputs will be automatically re-enabled.
3.11.1.
Algorithm description:
There are 2 trip points, “high” and “low”. High indicates a critical overheat requiring a reduction in volume to avoid damage
to the part. Low is set for a slightly lower temperature point, indicating that the current level is safe but that increased
volume would result in a critical overheat condition.
y
Normally, the overheat bits are polled every 8ms but may be polled at 4ms, 8ms, 16ms, or 32ms by adjusting the Poll value.
Reductions in volume will be allowed to happen at the Poll rate. Increases in volume are programmable to happen every 1,
2, 4, or 8 Poll cycles and in steps of 0.75dB to 6dB. This allows a full scale volume increase in a range of 10s of
milliseconds to 10s of seconds.
in
ar
When both overheat bits are 0, the volume is allowed to increment by the IncStep size, unless the volume has already
reached the maximum value allowed. Any subsequent increment will be held off until the programmed number of polling
cycles have occurred.
im
When the low overheat bit is 1 and the high overheat bit is 0, this indicates that the volume is currently at a safe point but
the temperature is higher than desired and incrementing the volume may cause severe overheating. The volume is held at
the current value.
Thermal Trip Points.
Pr
3.11.2.
el
When the high overheat bit is 1, damage could occur, so the volume setting will be immediately reduced by the Decrement
Step value. As the overheat bits are re-polled, this volume reduction will continue until the high overheat bit drops to 0 or
the volume value reaches the minimum setting. If the high overheat bit remains 1 even at the minimum setting, then the
mute control bit will be asserted. If the high overheat bit persists even after mute, then the BTL amp will be powered down.
The high and low trip points can be adjusted to suit the needs of a particular system implementation. There is a “shift” value
(TripShift) which sets the low trip point, and there is a “split” value (TripSplit) that sets how many degrees above the low trip
point the high trip point is.
By default:
TripShift = 2 (140 degrees C)
TripSplit = 0 (15 degrees C)
Therefore:
High Trip Point = 155°C.
Low Trip Point = 140°C.
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3.11.3.
Instant Cut Mode
This mode can be used to make our algorithm react faster to reduce thermal output but will cause more pronounced
volume changes. If enabled:
•
•
•
•
Only the high overheat is used, the low overheat is ignored.
Whenever polled, if the high overheat is 1, then the volume setting will immediately be set to 0h.
Conversely, if the high overheat is 0, the volume setting will immediately be set to the MaxVol value.
Both volume clear and volume set events occur at the polling rate.
During this mode, the algorithm still possesses the ability to mute and then power down the BTL amp if the high overheat
continues to be 1.
This mode is disabled by default.
3.11.4.
Thermal Shutdown Registers
3.11.4.1.Temp Sensor Control/Status
Label
Type
Default
7
TRIPHS
R
0
6
TRIPLS
R
5:4
TRIPSPLIT[1:0]
3:2
TRIPSHIFT[1:0]
RW
2h
Temp sensor “shift” setting. Determines the low trip
temperature:
0h = 110 Degrees C
1h = 125 Degrees C
2h = 140 Degrees C
3h = 155 Degrees C.
1:0
TSPOLL[1:0]
RW
1h
Temp sensor polling interval
0h = 4ms
1h = 8ms
2h = 16ms
3h = 32ms
in
Temp sensor high trip point status
0 = Normal Operation
1 = Over Temp Condition
0
Temp sensor low trip point status
0 = Normal Operation
1 = Over Temp Condition
im
RW
Pr
Page 2, Reg 25 - 19h
THERMTS
Description
ar
Bit
0h
Temp sensor “split” setting. Determines how many
degrees above the low trip point the high trip is set:
0h = 15 Degrees C
1h = 30 Degrees C
2h = 45 Degrees C
3h = 60 Degrees C.
el
Register Address
y
The temperature sensor circuit is configured and monitored using the Temp Sensor Control/Status Register
Table 79. THERMTS Register
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3.11.4.2.Speaker Thermal Shutdown Control Register
The thermal shutdown algorithm is configured using the Speaker Thermal Algorithm Control Register
Register Address
Bit
7
Type
FORCEPWD
INSTCUTMD
RW
RW
Default
Description
1
Force powerdown enable for the speaker thermal
algorithm:
0 = Speaker will remain powered up even if the temp
sensor continues to report an overheat condition at
minimum volume (mute)
1 = Speaker will be powered down if the temp sensor
reports an overheat at the minimum volume (mute)
0
Instant Cut Mode
0 = Both temp sensor status bits used to smoothly
adjust the volume.
1 = Only the high temp sensor status bit will be used
to set the volume. volume will be set to the full
volume or mute (IncStep and DecStep are ignored.)
0h
Increment interval ratio. Determines the ratio
between the speaker volume increment interval and
the speaker volume decrement interval (increment
rate is equal to or slower than decrement rate):
0h = 1:1
1h = 2:1
2h = 4:1
3h = 8:1
5:4
INCRATIO[1:0]
RW
in
Page 2, Reg 26 - 1Ah
THERMSPK
ar
y
6
Label
im
INCSTEP[1:0]
RW
0h
Pr
el
3:2
Increment step size for the speaker thermal control
algorithm (occurs at the temp sensor polling rate X
the increment interval ratio.)
0h = 0.75dB
1h = 1.5dB
2h = 3.0dB
3h = 6.0dB
1:0
DECSTEP[1:0]
RW
Decrement step size for the speaker thermal control
algorithm (occurs at the temp sensor polling rate.)
0h = 3dB
1h = 6dB
2h = 12dB
3h = 24dB
1h
Table 80. THERMSPK Register
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3.11.4.3.Speaker Thermal Algorithm Status Register
The thermal shutdown algorithm is monitored using the Speaker Thermal Algorithm Status Register
Register Address
Bit
Label
7
Type
FPWDS
R
Default
0: Speaker not powered down due to thermal
algorithm
1: Speaker has been powered down because
overtemp condition was present even though the
speaker was muted.
0
Page 2, Reg 27 - 1Bh
THRMSTAT
6:0
VOLSTAT[6:0]
R
Description
Current speaker volume value. If no overheat is
being reported by the temperature sensor, this value
should be equal to the greater of the left or right
speaker volume setting.
NA
Table 81. THRMSTAT Register
Short Circuit Protection
y
3.12.
Label
7:5
Reserved
R
0h
Reserved
4:3
ESDF
R
0h
ESD fault detected
2
CPF
R
0h
charge pump fault detected
R
0h
Class D fault detected
1:0
Type
Default
CLSDF
Description
im
Page 2 Reg 28 - 1Ch
SCSTAT
Bit
el
Register Address
in
ar
To avoid damage to the outputs if a short circuit condition should occur, both the headphone and BTL amplifiers implement
short circuit protection circuits. The headphone output amplifier will detect the load current and limit its output if in an over
current state. The BTL amplifier will sense a short to PVDD, ground, or between its +/- outputs and disable its output if a
short is detected. After a brief time, controlled by SCTO[1:0], the amplifier will turn on again. If a short circuit condition is still
present, the amplifier will disable itself again.
3.13.
Pr
Table 82. SCSTAT Register
Analog Input to DAC/Headphone Bypass Path
A low power mode exists to allow the output from the analog input multiplexer to be selected as an input to the
Headphone/Line Out amplifier. See A mux is used to control the source selection for the HP/LineOut amplifier. The MUX
selection is controlled by the ABYPASS bit.
3.14.
Headphone Switch
The HPDET pin is used to detect connection of a headphone when this pin is connected to a mechanical switch located
within the headphone jack. When headphone insertion into the headphone jack is detected, the codec can automatically
disable the speaker outputs and enable the headphone outputs. Control bits determine the meaning and polarity of the
input.
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Portable Audio Consumer Codec
Register Address
Bit
Label
Type
Default
Description
7:5
RSVD
R
0
Reserved
4
HPDSTATE
R
0
HP-DET Pin State
0 = HP_DET pin low
1 = HP_DET pin high
Headphone Switch Enable
00 =: Headphone switch disabled
01 =: Headphone switch enabled for Speaker
Outputs
10 and 11 are Reserved
3:2
HPSWEN[1:0]
RW
00b
1
HPSWPOL
RW
0
Headphone Switch Polarity
0: HPDETECT high = headphone
1: HPDETECT high = speaker
0
TSDEN
RW
0
Thermal Shutdown Enable
0: thermal shutdown disabled
1: thermal shutdown enabled
ar
Page 2, Reg 24 - 18h
HPSW
Headphone Switch Control Register
y
3.14.1.
im
in
Table 83. HPSW Register
HPSWPOL
HP_DET Pin
state
HPOut
SPKOut
HeadPhone
Enable
Speaker
Enabled
00
X
X
0
0
no
no
00
X
X
0
1
no
yes
00
X
X
1
0
yes
no
00
X
X
1
1
yes
yes
0
0
X
0
no
no
0
0
X
1
no
yes
0
1
0
X
no
no
01
0
1
1
X
yes
no
01
1
0
0
X
no
no
01
1
0
1
X
yes
no
01
1
1
X
0
no
no
01
1
1
X
1
no
yes
01
01
Pr
01
el
HPSWEN
Table 84. Headphone Operation
Note:HPOut = Logical OR of the HPL and HPR enable (power state) bits1.
Note:SPKOut = Logical OR of the SPKL and SPKR enable (power state) bits
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Page 0, Reg 33h
Page 1, 1Eh
ALC Control 1
ALC Control 0
Noise Gate Control
ALC Control 3
ALC Control 2
Page 1, 1Dh
Page 1, 20h
Page 1, 1Fh
Page 1, 21h
Page 1, Reg 06h
M
U
X
Page 1, Reg 07h
M
U
X
CIC
CIC
Input Processor Select
1
0
ar
y
ADC Power
Management
ADC-L
ADC-R
0
1
CIC
CIC
in
Page 1, Reg 0Dh
G
-17.25 to +30dB in 0.75dB steps
M
U
X
PGA
G
MIC Bias
192KHz
CH0 Boost
PGA
Page 1, Reg 06h
Boost
Page 1, Reg 0Dh
PGA
Digital Gain Stage
for Digital MIC
Page 1, Reg 0Eh
Boost
Page 1, Reg 07h
CH1 Boost
192KHz
192KHz
192KHz
CH3 Boost
im
Zero Cross Detect
A
Left input volume
Page 1, Reg 0Dh
To HP
Passthrough
Boost
Left Boost
Page 1, Reg 06h
Left ADC Input Select
M
U
X
Page 1, Reg 07h
Right ADC Input Select
A
PGA
-17.25 to +30dB in 0.75dB steps
Page 1, Reg 0Eh
+
PGA
Page 1, Reg 0Fh
PGA
Page 1, Reg 10h
Digital Gain Stage
for Digital MIC
Boost
Page 1, Reg 09h
Boost
Page 1, Reg 08h
CH2 Boost
el
Left Input Select
M
U
X
Page 1, Reg 06h
D2S1
Page 1, Reg 06h
Right Boost
Boost
To HP
Passthrough
+0/+10/+20/+30 dB
M
U
X
Page 1, Reg 07h
Right input volume
Mic Bias
Vref
Page 1, Reg 0Ch
AGND
Page 1, Reg 12h
VOL
mute
mute
-71.25 to +24 dB
In 0.375 dB steps
CH0 Digital Volume
FIR
VOL
MIXER
CH1
VOL
mute
mute
MIXER
CH4
MIXER
CH3
MIXER
CH2
FIR
VOL
Page 1, Reg 15h
CH3 Digital Volume
-71.25 to +24 dB
In 0.375 dB steps
FIR
-71.25 to +24 dB
In 0.375 dB steps
CH2 Digital Volume
Page 1, Reg 14h
Page 1, Reg 13h
CH1 Digital Volume
-71.25 to +24 dB
In 0.375 dB steps
FIR
Base Audio
Sample
Rate
Page 1, 0Ah
CH1, CH0 HPF
CH1, CH0 Polarity
CH1, CH0 Mute
HPF
CH0 input volume
HPF
CH1 input volume
Page 1, 0Bh
CH3 input volume
HPF
CH2 input volume
HPF
CH3, CH2 HPF
CH3, CH2 Polarity
CH3, CH2 Mute
Pr
LIN1
LIN2
LIN3
RIN1
RIN2
RIN3
D2S2
Page 1, Reg 07h
D2S2
D2S1
-
+
-
Right Input Select +0/+10/+20/+30 dB
DMIC1
D2S
D2S
V 1.1 10/16
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TSCS454
©2014 TEMPO SEMICONDUCTOR, INC.
DMIC2
LIN2
LIN1
RIN2
RIN1
+
TSCS454
Portable Audio Consumer Codec
4. ANALOG INPUT AUDIO PROCESSING
Figure 13. Input Audio Processing
TSCS454
Portable Audio Consumer Codec
4.1.
Overview
The TSCS454 supports three stereo analog and one stereo differential, four digital microphone inputs, and three digital,
stereo I2S inputs,The analog and digital mic inputs of the TSCS454 are processed and controlled through a four channel
Input Processor. The first two channels of the Input Processor can process either the output from the ADC or the digital mic
input from the DIGMIC1 input. The remaining two channels of the Input Processor are dedicated to the digital microphone
input via the DIGMIC2 pin. The Input Processor supports volume control functions, ALC, high-pass filter, polarity, and mute
functions for each channel.
4.2.
Analog Audio Inputs
4.3.
Input Processor Analog Input Control
ar
y
The TSCS454 provides multiple high impedance, low capacitance AC-coupled analog inputs with an input signal path to
the stereo ADCs. Prior to the ADC, there is a multiplexor that allows the system to select which analog input is selected for
input to the ADC. Following the mux, there is a programmable gain amplifier (PGA) and also an optional microphone gain
boost. The gain of the PGA can be controlled either by the system, or by the on-chip level control function. Signal inputs are
biased internally so AC coupling capacitors are required when connecting microphones (due to the 2.5V microphone bias)
or when offsets would cause unacceptable “zipper noise” or pops when changing PGA or boost gain settings. To avoid
audio artifacts, the line inputs are kept biased to analog ground when they are muted or the device is placed into standby
mode.
Pr
el
im
in
The TSCS454 Input Processor controls the selection of the analog input to the ADC, gain boost, microphone bias generation, and differential input control.
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Channel 0 Input Audio Control Register
Bit
Label
Type
Default
7:6
INSELL[1:0]
RW
00
Left Channel Analog Input Select
00 = LINPUT1 01 = LINPUT2
10 = LINPUT3 11 = D2S
00
Left Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 10dB boost
10 = 20dB boost
11 = 30dB boost
5:4
RW
3:2
LADCIN
RW
0
Left Channel ADC Input Select
00 = LINPUT1 Bypass
01 = LINPUT2 Bypass
10 = LINPUT3 Bypass
11 = Left Input MUX Output
1
BYPSPGA0
RW
0
Bypass left channel PGA amplifier
1 = Bypass PGA amplifier
0 = PGA amplifier
0
IPCH0S
RW
0
y
Page 1, Reg 6 -6h
CH0AIC
MICBST0[1:0]
Description
ar
Register Address
Input Processor Channel 0 Input Select - The Left
ADC is powered when the DMIC input is selected.
0 = Select ADC Left
1 = Select DMIC Channel 0
in
4.3.1.
Channel 1 Audio Input Control Register
Bit
Label
7:6
INSELR[1:0]
Type
RW
Pr
Register Address
5:4
Page 1, Reg 7 - 7h
CH1AIC
Default
MICBST1[1:0]
RW
Description
00
Right Channel Analog Input Select
00 = RINPUT1 01 = RINPUT2
10 = RINPUT3 11 = D2S
00
Right Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 10dB boost
10 = 20dB boost
11 = 30dB boost
el
4.3.2.
im
Table 85. CH0AIC Register
3:2
RADCIN
RW
0
Right Channel ADC Input Select
00 = RINPUT1 Bypass
01 = RINPUT2 Bypass
10 = RINPUT3 Bypass
11 = Right Input MUX Output
1
BYPSPGA1
RW
0
Bypass right channel PGA amplifier
1 = Bypass PGA amplifier
0 = PGA amplifier
0
Input Processor Channel 1 Input Select - The Right
ADC is powered when the DMIC input is selected.
0 = Select ADC Right
1 = Select DMIC Channel 1
0
IPCH1S
RW
Table 86. CH1AIC Register
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4.3.3.
Channel 2 Audio Input Control Register
Register Address
Page 1, Reg 8 -8h
CH2AIC
Bit
Label
Type
Default
Description
7:6
RSVD
R
0
Reserved
5:4
MICBST2[1:0]
RW
0
Right Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 10dB boost
10 = 20dB boost
11 = 30dB boost
3:0
RSVD
R
0
Reserved
Table 87. CH2AIC Register
Channel 3 Audio Input Control Register
Page 1, Reg 9 - 9h
CH3AIC
Label
Type
Default
7:6
RSVD
R
0
Reserved
0
Right Channel Microphone Gain Boost
00 = Boost off (bypassed)
01 = 10dB boost
10 = 20dB boost
11 = 30dB boost
5:4
MICBST3[1:0]
RW
3:0
RSVD
R
Description
y
Bit
ar
Register Address
in
4.3.4.
0
Reserved
Pr
el
im
Table 88. CH3AIC Register
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4.4.
Input Processor Digital Processing
The Input Processor also provides control of polarity, mixing, volume/gain, limiting, and automatic level control.
Input Processor Control Register 0
Label
Type
Default
Description
7
IN1POL
RW
0
Input Channel 1 Polarity
0 = normal
1 = inverted
6
IN0POL
RW
0
Input Channel 0 Polarity
0 = normal
1 = inverted
5:4
INPCH10SEL[1:0]
RW
0
Input Processor Channel 1, 0 Select
00 = Stereo, Channel 0 = Left Channel 1 = Right
01 = Channel 0 output on Channels 1 and 0
10 = Channel 1 output on Channels 1 and 0
11 = 1/2 Channel 0 and 1/2 Channel 1 output on
Channels 1 and 0
3
IN1MUTE
RW
1
0 = Input channel 1 un-muted
1 = Input channel 1 muted
2
IN0MUTE
RW
1
IN1HP
RW
0
IN0HP
y
Page 1, Reg 10 - Ah
ICTL0
Bit
ar
Register Address
1
0 = Input channel 0 un-muted
1 = Input channel 0 muted
0
Input Channel 1 High Pass Filter Disable
in
4.4.1.
RW
0
Input Channel 0 High Pass Filter Disable
Pr
el
im
Table 89. ICTL0 Register
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Input Processor Control Register 1
Label
Type
Default
Description
7
IN3POL
RW
0
Input Channel 3 Polarity
0 = normal
1 = inverted
6
IN2POL
RW
0
Input Channel 2 Polarity
0 = normal
1 = inverted
5:4
INPCH32SEL[1:0]
RW
0
Input Processor Channel 3, 2 Select
00 = Stereo, Channel 2 = Left Channel 3 = Right
01 = Channel 2 output on Channels 3 and 2
10 = Channel 3 output on Channels 3 and 2
11 = 1/2 Channel 2 and 1/2 Channel 3 output on
Channels 3 and 2
3
IN3MUTE
RW
1
0 = Input channel 3 un-muted
1 = Input channels 3 muted
2
IN2MUTE
RW
1
0 = Input channel 2 un-muted
1 = Input channels 2 muted
1
IN3HP
RW
0
0
IN2HP
RW
y
Page 1, Reg 11 - Bh
ICTL1
Bit
ar
Register Address
Input Channel 3 High Pass Filter Disable
in
4.4.2.
0
Input Channel 2 High Pass Filter Disable
4.5.
Microphone Bias
im
Table 90. ICTL1 Register
el
The MICBIAS1,2 outputs are used to bias electric type microphones. They provide a low noise reference voltage used for
an external resistor biasing network. The MICBx control bits are used to enable the individual outputs. A series 2.2K ohm
resistor is provided in series with each MICBIAS output.
Register Address
Pr
Each MICBIAS output can source up to 500uA of current
Bit
7:6
Label
Type
MICBOV1[1:0]
RW
Default
Description
00b
Mic Bias 1 Output Voltage
00 = 2.5V
01 = 2.1V
10 = 1.8V
11 = Bypass, uses MICBIAS VDD Supply
Page 1, Reg 12 - Ch
MICBIAS
5:4
MICBOV2[1:0]
RW
00b
Mic Bias 2 Output Voltage
00 = 2.5V
01 = 2.1V
10 = 1.8V
11 = Bypass, uses MICBIAS VDD Supply
3:0
RSVD
RW
00b
Reserved
Table 91. MICBIAS Register
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Portable Audio Consumer Codec
2.5V
2.1V
1.8V
MICBIAS VDD Supply
M
U
X
AGND
M
U
X
AGND
+
Mic Bias 1
2.2K
2.5V
2.1V
1.8V
MICBIAS VDD Supply
+
Mic Bias 2
2.2K
Figure 14. MIC Bias Generator
Programmable Gain Control
y
4.6.
in
ar
The Programmable Gain Amplifier (PGA) enables the input signal level to be matched to the ADC input range. Amplifier
gain is adjustable across the range +30dB to –17.25dB (using 0.75dB steps). The PGA can be controlled directly by the
system software using the PGA Control registers (PGACTL0, PGACTL1, PGACTL2 and PGACTL3), or alternately the
Automatic Level Control (ALC) function can automatically control the gain. If the ALC function is used, writing to the PGA
Control registers has no effect.
im
Left and right input gains are independently adjustable. By controlling the update bit PGAVOLU Page 1, Reg 28 - VOLCTLU register, the left and right gain settings can be simultaneously updated. To eliminate zipper noise, PGA0ZC and
PGA1ZC bits enable a zero-cross detector to insure changes only occur when the signal is at zero. A time-out for
zero-cross is also provided, using TOEN in register Page 1, R17.
Pr
el
Software can also mute the inputs in the analog domain.
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PGA Control Registers
Bit
7
Page 1, Reg 15 - Fh
PGACTL2
Page 1, Reg 16 - 10h
PGACTL3
PGA0MUTE
6
PGA0ZC
RW
Default
Channel 0 PGA Mute
1 = Mute
0 = Un mute
1
RW
0
Channel 0 Zero Cross Detector
1 = Change gain on zero cross only
0 = Change gain immediately
Note: If PGAVOLU is set, this setting will take effect
after the next write to the PGA0VOL[5:0]
PGA0VOL[5:0]
RW
7
PGA1MUTE
RW
1
R
0
Channel 1 PGA Mute
1 = Mute
0 = Un mute
ar
PGA1ZC
5:0
PGA1VOL[5:0]
7
PGA2MUTE
RW
6
RSVD
R
Channel 1 Zero Cross Detector
1 = Change gain on zero cross only
0 = Change gain immediately
Note: If PGAVOLU is set, this setting will take effect
after the next write to the PGA1VOL[5:0]
RW
010111
(0dB)
Channel 1 Input Volume Control
111111 = +30dB
111110 = +29.25dB
... 0.75dB steps down to 000000 = -17.25dB
Channel 2 PGA Mute
1 = Mute
0 = Un mute
1
Reserved
5:0
PGA2VOL[5:0]
RW
010111
(0dB)
7
PGA3MUTE
RW
1
6
RSVD
R
5:0
Channel 0 Input Volume Control
111111 = +30dB
111110 = +29.25dB
... 0.75dB steps down to 000000 = -17.25dB
y
5:0
010111
(0dB)
6
Description
in
Page 1, Reg 14 - Eh
PGACTL1
Type
Pr
Page 1, Reg 13 - Dh
PGACTL0
Label
im
Register Address
el
4.6.1.
PGA3VOL[5:0]
RW
Channel 2 Input Volume Control
111111 = +30dB
111110 = +29.25dB
... 0.75dB steps down to 000000 = -17.25dB
Channel 3 PGA Mute
1 = Mute
0 = Un mute
Reserved
010111
(0dB)
Channel 3 Input Volume Control
111111 = +30dB
111110 = +29.25dB
... 0.75dB steps down to 000000 = -17.25dB
Table 92. PGACTL0 Registers
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Portable Audio Consumer Codec
4.6.2.
PGA Zero Cross Control Register
Register Address
Bit
Label
Type
Default
7:2
RSVD
R
0
Reserved
0
Input High-Pass Filter Offset Result (applies to all 4
input processor channels)
0 = discard calculated offset when HPF disabled
1 = store and use last calculated offset when HPF
disabled
0
Zero Cross Time-out Enable
0: Time-out Disabled
1: Time-out Enabled - volumes updated if no zero
cross event has occurred before time-out
1
INHPOR
RW
Page 1, Reg 17 - 11h
PGAZ
0
TOEN
RW
Description
Table 93. PGA Zero Cross Control Register
ADC Digital Filter
y
4.7.
im
in
ar
To provide the correct sampling frequency on the digital audio outputs, ADC filters perform true 24-bit signal processing
and convert the raw multi-bit oversampled data from the ADC using the digital filter path illustrated below.
Pr
el
Figure 15. ADC Filter Data path
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Portable Audio Consumer Codec
1
5.120MHz
7.056MHz
7.68MHz
1/80X
1
Output Rate =
16/22.05/24kHz (HX):
From Analog ADC
Output Rate =
32/44.1/48kHz (1X):
From Analog ADC
Output Rate =
64/88.2/96kHz (2X):
From Analog ADC
1/2X
64kHz
88.2kHz
96kHz
1/80X
1
1/80X
1
1/80X
1
Output Rate =
16/22.05/24kHz (HX):
From Analog ADC
Output Rate =
32/44.1/48kHz (1X):
From Analog ADC
Output Rate =
64/88.2/96kHz (2X):
From Analog ADC
1/2X
1/80X
128kHz
176.4kHz
192kHz
1/80X
1
Output Rate =
32/44.1/48kHz (1X):
From Analog ADC
Output Rate =
64/88.2/96kHz (2X):
From Analog ADC
1/2X
1/80X
5.120MHz
7.056MHz
7.68MHz
1/80X
1
32kHz
44.1kHz
48kHz
1/2X
16kHz
22.05kHz
24kHz
1/2X
To I2S
8kHz
11.025kHz
12kHz
24
57T FIR-A
32kHz
44.1kHz
48kHz
24
57T FIR-A
22
To I2S
16kHz
22.05kHz
24kHz
24
57T FIR-A
64kHz
88.2kHz
96kHz
im
1/80X
1
1/2X
22
11T FIR-B
11T FIR-B
64kHz
88.2kHz
96kHz
To I2S
1/2X
17
CIC
5.120MHz
7.056MHz
7.68MHz
1/2X
To I2S
16kHz
22.05kHz
24kHz
24
22
17
CIC
24
32kHz
44.1kHz
48kHz
To I2S
7T FIR-C
64kHz
88.2kHz
96kHz
To I2S
8kHz
11.025kHz
12kHz
32kHz
44.1kHz
48kHz
in
From Analog ADC
24
64kHz
88.2kHz
96kHz
17
1
Output Rate =
16/22.05/24kHz (HX):
1/2X
57T FIR-A
CIC
1/2X
24
57T FIR-A
16kHz
22.05kHz
24kHz
57T FIR-A
57T FIR-A
64kHz
88.2kHz
96kHz
1/2X
22
11T FIR-B
22
17
1
5.120MHz
7.056MHz
7.68MHz
1/2X
128kHz
176.4kHz
192kHz
1/80X
Output Rate =
From Analog ADC
8/11.025/12kHz (QX):
1/2X
1/2X
22
11T FIR-B
32kHz
44.1kHz
48kHz
22
64kHz
88.2kHz
96kHz
11T FIR-B
CIC
10.240MHz
14.112MHz
15.360MHz
Half
1/2X
17
128kHz
176.4kHz
192kHz
1/2X
22
7T FIR-C
7T FIR-C
CIC
10.240MHz
14.112MHz
15.360MHz
1/2X
22
64kHz
88.2kHz
96kHz
17
1
To I2S
7T FIR-D
128kHz
176.4kHz
192kHz
CIC
10.240MHz
14.112MHz
15.360MHz
24
17
CIC
To I2S
32kHz
44.1kHz
48kHz
64kHz
88.2kHz
96kHz
128kHz
176.4kHz
192kHz
1
10.240MHz
14.112MHz
15.360MHz
24
57T FIR-A
57T FIR-A
1/80X
Output Rate =
From Analog ADC
8/11.025/12kHz (QX):
1/2X
To I2S
16kHz
22.05kHz
24kHz
22
1/2X
To I2S
8kHz
11.025kHz
12kHz
24
64kHz
88.2kHz
96kHz
17
10.240MHz
14.112MHz
15.360MHz
Full
1/2X
11T FIR-B
CIC
16kHz
22.05kHz
24kHz
57T FIR-A
32kHz
44.1kHz
48kHz
17
128kHz
176.4kHz
192kHz
1/2X
24
57T FIR-A
22
11T FIR-B
CIC
10.240MHz
14.112MHz
15.360MHz
1/2X
22
11T FIR-B
32kHz
44.1kHz
48kHz
17
64kHz
88.2kHz
96kHz
1/2X
22
7T FIR-C
CIC
5.120MHz
7.056MHz
7.68MHz
1/2X
17
CIC
y
1/80X
Output Rate =
From Analog ADC
8/11.025/12kHz (QX):
ar
AUTO
To I2S
32kHz
44.1kHz
48kHz
17
CIC
To I2S
64kHz
88.2kHz
96kHz
5.120MHz
7.056MHz
7.68MHz
el
Figure 16. ADC Input processing
Pr
The ADC digital filters contain a software-selectable digital high pass filter. When the high-pass filter is enabled, the dc offset is continuously calculated and subtracted from the input signal. The HPOR bit enables the last calculated DC offset
value to be stored when the high-pass filter is disabled; this value will then continue to be subtracted from the input signal.
To provide support for calibration, the stored and subtracted value will not change unless the high-pass filter is enabled
even if the DC value is changed. The high pass filter may be enabled separately for each of the left and right channels.
The output data format can be programmed by the system. This allows stereo or mono recording streams at both inputs.
Software can change the polarity of the output signal.
4.8.
Input Channel Volume Control
Channel volume can be controlled digitally, across a gain and attenuation range of -71.25dB to +24dB (0.375dB steps). The
level of attenuation is specified by an eight-bit code ICH0VOL, ICH1VOL, ICH2VOL and ICH3VOL. The value “00000000”
indicates mute; other values describe the number of 0.375dB steps above -71.25dB.
The INPVOLU bit (Section 7.3.1 “Input Volume Update” on page 117) controls the updating of digital volume control data.
for the Input Channels. When INPVOLU is written as ‘0’, the ADC digital volume is immediately updated with the ICH0VOL
data when the Left ADC Digital Volume register is written. When INPVOLU is set to ‘1’, the ICH0VOL data is held in an
internal holding register until the ICH1VOL is written.
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4.8.1.
CH0, CH1 Input Volume Control Registers
Register Address
Bit
Page 1, Reg 18 - 12h
ICH0VOL
7:0
Page 1, Reg 19 -13h
ICH1VOL
7:0
Label
ICH0VOL
[7:0]
ICH1VOL
[7:0]
Type
RW
RW
Default
Description
10111111
(0dB)
Channel 0 Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -71.25dB
0000 0010 = -70.875dB
... 0.375dB steps up to 1111 1111 = +24dB
Note: If INPVOLU is set, this setting will take effect
after the next write to the ICH1VOL register.
10111111
(0dB)
Channel 1 Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -71.25dB
0000 0010 = -70.875dB
... 0.375dB steps up to 1111 1111 = +24dB
Page 1, Reg 20 - 14H
ICH2VOL
Page 1, Reg 21 - 15h
ICH3VOL
7:0
7:0
Label
ICH2VOL
[7:0]
ICH3VOL
[7:0]
Type
RW
Default
Description
Channel 2 Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -71.25dB
0000 0010 = -70.875dB
... 0.375dB steps up to 1111 1111 = +24dB
Note: If IPNVOLU is set, this setting will take effect
after the next write to theICH3VOL register.
in
Bit
10111111
(0dB)
im
Register Address
ar
CH2, CH3 Input Volume Control Register
RW
10111111
(0dB)
el
4.8.2.
y
Table 94. ICH0VOL/ ICH1VOL Registers
Channel 3 Digital Volume Control
0000 0000 = Digital Mute
0000 0001 = -71.25dB
0000 0010 = -70.875dB
... 0.375dB steps up to 1111 1111 = +24dB
4.9.
Pr
Table 95. ICH2VOL/ ICH3VOL Registers
Automatic Level Control (ALC)
The TSCS454 has an automatic level control to achieve recording volume across a range of input signal levels. The device
uses a digital peak detector to monitor and adjusts the PGA gain to provide a signal level at the ADC input. A range of
adjustment between –6dB and –28.5dB (relative to ADC full scale) can be selected. The device provides programmable
attack, hold, and decay times to smooth adjustments. The level control also features a peak limiter to prevent clipping when
the ADC input exceeds a threshold. Note that if the ALC is enabled, the input volume controls are ignored.
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ar
y
4.9.1. ALC Operation
in
Figure 17. ALC Operation
im
When ALC is enabled, the recording volume target can be programmed between –6dB and –28.5dB (relative to ADC full
scale). The ALC will attempt to keep the ADC input level to within +/-0.5dB of the target level. An upper limit for the PGA
gain can also be imposed, using the MAXGAIN control bits.
el
Hold time specifies the delay between detecting a peak level being below target, and the PGA gain beginning to ramp up.
It is specified as 2n*2.67mS, enabling a range between 0mS and over 40s.; ramp-down begins immediately if the signal
level is above the target.
Pr
Decay (Gain Ramp-Up) Time is the time that it takes for the PGA to ramp up across 90% of its range. The time is 2n*24mS.
The time required for the recording level to return to its target value therefore depends on the decay time and on the gain
adjustment required.
Attack (Gain Ramp-Down) Time is the time that it takes for the PGA to ramp down across 90% of its range. Time is specified as 2n*24mS. The time required for the recording level to return to its target value depends on both the attack time and
on the gain adjustment required.
When operating ,the peak detector can be programmed to use a specific channel maximum peak value or take the
maximum of the currently enabled processing channels,, and all the PGAs use the same gain setting. If the ALC function is
only enabled on specific channels, only that PGA is controlled by the ALC mechanism, and the other channels runs
independently using the PGA gain set through the control registers.
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4.9.2. ALC Control Registers
Label
Type
Default
7
ALCMODE
RW
0
ALC Mode Selection
0 = ALC Mode
1 = Limiter Mode
ALC Reference Channel Selection
000: Channel 0
001: Channel 1
010: Channel 2
011: Channel 3
100-111: Peal Across All Enabled Channels
Description
ALC REF
RW
4h
3
ALCEN3
RW
0
(OFF)
Channel 3 ALC function select
0 = ALC off
1 = ALC On
2
ALCEN2
RW
0
(OFF)
Channel 2 ALC function select
0 = ALC off
1 = ALC On
1
ALCEN1
RW
0
(OFF)
0
ALCEN0
RW
7
RSVD
6:4
ar
Channel 1 ALC function select
0 = ALC off
1 = ALC On
in
0
(OFF)
R
RW
Pr
Page 1, Reg 30 - 1Eh
ALCCTL1
MAXGAIN
[2:0]
y
6:4
im
Page 1, Reg 29 - 1Dh
ALCCTL0
Bit
0
Channel 0 ALC function select
0 = ALC off
1 = ALC On
Reserved
Set Maximum Gain of PGA
111: +30dB
110: +24dB
111
(+30dB) ….(-6dB steps)
001: -6dB
000: -12dB
el
Register Address
3:0
ALCL
[3:0]
RW
1011
(-12dB)
ALC target – sets signal level at ADC input
0000 = -28.5dB fs
0001 = -27.0dB fs
… (1.5dB steps)
1110 = -7.5dB fs
1111 = -6dB fs
Table 96. ALCCTL0 /ALCCTL1 Registers
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Register Address
Bit
Label
Type
7
ALCZC
RW
6:4
MINGAIN[2:0]
RW
Default
0 (zero
ALC uses zero cross detection circuit.
cross off)
000
Page 3, Reg 31 - 1Fh
ALCCTL2
HLD
[3:0]
RW
0000
(0ms)
Sets the minimum gain of the PGA
000 = -17.25db
001 = -11.25
...
110 = +18.75dB
111 = +24.75db
where each value represents a 6dB step.
ALC hold time before gain is increased.
0000 = 0ms
0001 = 2.67ms
0010 = 5.33ms
… (time doubles with every step)
1111 = 43.691s
y
3:0
Description
Page 3, Reg 32 - 20h
ALCCTL3
RW
0010
(24ms)
im
ATK
[3:0]
3:0
ar
RW
in
DCY
[3:0]
7:4
ALC decay (gain ramp-up) time
0000 = 24ms
0011
0001 = 48ms
(192ms) 0010 = 96ms
… (time doubles with every step)
1010 or higher = 24.58s
ALC attack (gain ramp-down) time
0000 = 6ms
0001 = 12ms
0010 = 24ms
… (time doubles with every step)
1010 or higher = 6.14s
4.9.3. Peak Limiter
el
Table 96. ALCCTL0 /ALCCTL1 Registers
Pr
To prevent clipping, the ALC circuit also includes a limiter function. If the ADC input signal exceeds 87.5% of full scale
(–1.16dB), the PGA gain is ramped down at the maximum attack rate, until the signal level falls below 87.5% of full scale.
This function is automatically enabled whenever the ALC is enabled.
4.9.4. Input Threshold
To avoid hissing during quiet periods, the TSCS454 has an input threshold noise gate function that compares the signal
level at the inputs to a noise gate threshold. Below the threshold, the programmable gain can be held , or the ADC output
can be muted. The threshold can be adjusted in increments of 1.5dB.
The noise gate activates when the signal-level at the input pin is less than the Noise Gate Threshold (NGTH) setting.
The ADC output can be muted. Alternatively, the PGA gain can be held .
The threshold is adjusted in 1.5dB steps. The noise gate only works in conjunction with the ALC, and always operates on
the same channel(s) as the ALC.
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Noise Gate Control Register
Page 1, Reg 33 - 21h
NGATE
Bit
Label
Type
Default
Description
7:3
NGTH
[4:0]
RW
00000
2:1
NGG
[1:0]
RW
00
Noise gate type
X0 = PGA gain held constant
01 = mute ADC output
11 = reserved (do not use this setting)
0
NGAT
RW
0
Noise gate function enable
1 = enable
0 = disable
Noise gate threshold (compared to ADC full-scale
range)
00000 -76.5dBfs
00001 -75dBfs
… 1.5 dB steps
11110 -31.5dBfs
11111 -30dBfs
ar
Table 97. NGATE Register
y
Register Address
in
4.9.5 Digital Microphone Support
TSCS454 supports input connection for up to four digital microphones via two stereo DMIC_x pins.
im
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the DMIC_x, and
DMIC_CLK 2-pin interface. DMIC_DATx is an input that carries individual channels of digital microphone data to the Input
Processor. In the event that a single microphone is used, the data is ported to both Input Processor channels. This mode is
selected using a control bit and the left time slot is copied to the left and right inputs.
Pr
el
The DMIC_CLK output is synchronous to the internal clock and is adjustable in 4 steps. Each step provides a clock that is
a multiple of the chosen internal ICLK base rate and modulator rate.The default frequency is and 80 times the base rate for
44.1KHz and 48KHz base rates.
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4.9.5.1.DMIC Clock
SDM Rate
DMRate [1:0]
Base Rate
Internal
CLK
DMIC_CLK
divisor
DMIC_CLK
Full
00
44.1 KHz
56.448 MHz
16
3.528 MHz
48 KHz
61.440 MHz
16
3.84 MHz
01
44.1 KHz
56.448 MHz
20
2.8224 MHz
48 KHz
61.440 MHz
20
3.072 MHz
10
44.1 KHz
56.448 MHz
24
2.352 MHz
48 KHz
61.440 MHz
24
2.56 MHz
44.1 KHz
56.448 MHz
32
1.764 MHz
48 KHz
61.440 MHz
32
1.92 MHz
00
44.1 KHz
56.448 MHz
16
3.528 MHz
48 KHz
61.440 MHz
16
01
44.1 KHz
56.448 MHz
24
48 KHz
61.440 MHz
24
44.1 KHz
56.448 MHz
48 KHz
61.440 MHz
44.1 KHz
56.448 MHz
48 KHz
61.440 MHz
10
11
y
2.56 MHz
32
1.764 MHz
32
1.92 MHz
40
1.4112 MHz
40
1.536 MHz
im
.
3.84 MHz
2.352 MHz
ar
Half
in
11
el
To conserve power, the analog portion of the ADC will be turned off if the D-mic input is selected. When switching from the
digital microphone to an analog input to the ADC, the analog portion of the ADC will be brought back to a full power state
and allowed to stabilize before switching from the digital microphone to the analog input. This should take less than 10mS.
Pr
If the ADC path is powered down, the DMIC_CLK output will be driven low to place the DMIC element into a low power
state. (Many digital microphones will enter a low power state if the clock input is held at a DC level or toggled at a slow
rate.)
The TSCS454 device supports the following digital microphone configurations:
Digital Mics
Data Sample
Notes
0
1
N/A
Single Edge
No Digital Microphones
When using a microphone that supports multiplexed operation (2-mics
can share a common data line), configure the microphone for “Left”
and select mono operation.
2
Double Edge
“Left” D-mic data is used for ADC left and right channels.
External logic required to support sampling on a single Digital Mic pin
channel on rising edge and second Digital Mic right channel on falling
edge of DMIC_CLK for those digital microphones that don’t support
alternative clock edge (multiplexed output) capability.
Table 98. Valid Digital Mic Configurations
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Portable Audio Consumer Codec
Off-Chip
Digital
Microphone
On-Chip
Single Line In
DMIC_DAT
MUX
Pin
Stereo Channels
Output
To Input
Processing
DMIC_CLK
Pin
On-Chip
Multiplexer
Valid Data
Right
Channel
Valid Data
Valid Data
ar
DMIC_DAT
y
Single Microphone not supporting multiplexed output.
Left
Channel
in
DMIC_CLK
DMIC_DAT
im
Single “Left” Microphone, DMIC input set to mono input mode.
Valid Data
Valid Data
Valid Data
Valid Data
Pr
DMIC_CLK
el
Left & Right
Channel
Figure 18. Mono Digital Microphone (data is ported to both left and right channels)
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Portable Audio Consumer Codec
Off-Chip
Digital
Microphones
On-Chip
External
Multiplexer
On-Chip
Multiplexer
DMIC_DAT
y
DMIC_CLK
Valid
Data R
Valid
Data R
Valid
Data L
in
Valid
Data L
Valid
Data R
Left
Channel
im
Right
Channel
DMIC_CLK
ar
Pin
DMIC_DAT
STEREO
ADC
PCM
MUX
MUX
Pin
Stereo Channels
Output
Pr
el
Figure 19. Stereo Digital Microphone
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4.9.5.2.Digital Mic Control Register
Register Address
Label
Type
Default
Description
7
DMIC2EN
RW
0
Digital Microphone 2 Enable
0 = DMIC interface is disabled (DMIC_CLK2 low,
DMIC muted)
1 = DMIC interface is enabled
6
DMIC1EN
RW
0
Digital Microphone 1 Enable
0 = DMIC interface is disabled (DMIC_CLK1 low,
DMIC muted)
1 = DMIC interface is enabled
5
RSVD
R
00
Reserved
4
DMONO
RW
0
0 = stereo operation, 1 = mono operation (left
channel duplicated on right)
3:2
DMDCLKj[1:0]
RW
00
Selects when the D-Mic data is latched relative to the
DMIC_CLKx.
00 = Left data rising edge / right data falling edge
01 = Left data center of high / right data center of low
10 = Left data falling edge / right data rising edge
11 = Left data center of low / right data center of high
1:0
DMRATE[1:0]
RW
00
ar
y
Page 1, Reg 34 - 22h
DMICCTL
Bit
in
Selects the DMIC clock rate: See DMIC clock table
Pr
el
im
Table 99. DMICCTL Register
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5. DIGITAL AUDIO INPUT-OUTPUT
LRCLK#/BCLK#
ICLK
GEN
DIV
ADC
/DMIC
PORT#
CLK
GEN
S
O
U
R
C
E
ASRC
In
ar
M
U
X
2
2
y
MCLK1
MCLK2 PLL1 CLK1
BCLK
CLK2
PLL2
XTAL
SDIN1
S
E
L
E
C
T
in
SDIN2
Pr
el
im
SDIN3
M
U
X
SDOUT1
M
U
X
SDOUT2
M
U
X
SDOUT3
ASRC
Out
S
W
I
T
C
H
Output
Processor
Output
Processor
Output
Processor
SPKR AMP
DAC
DAC
SUB
HP
Figure 20. Digital Audio Interface Block Diagram
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5.1.
PCM Interfaces
•
For digital audio data, the TSCS454 uses four pins for each I2S/PCM audio interface.
•
SDOUT1: I2S/TDM data output
•
SDOUT2: I2S/PCM2 data output
•
SDOUT3: I2S/PCM3 data output
•
LRCLK1: I2S/TDM data alignment clock
•
LRCLK2: I2S/PCM2 data alignment clock
•
LRCLK3: I2S/PCM3 data alignment clock
•
•
BCLK1: I2S1/TDM1 Bit clock, for synchronization
•
BCLK2: I2S2/PCM2 Bit clock, for synchronization
•
BCLK3: I2S3/PCM3 Bit clock, for synchronization
SDIN1: I2S/PCM1 data input
•
SDIN2: I2S/PCM2 data input
•
SDIN3: I2S/PCM3 data input
ar
•
y
•
INPUT
OUTPUT
INPUT
I2S Port 1
OUTPUT
I2S Port 2
im
I2S Port
in
I2S AUDIO INTERFACES
SDIN1
SDOUT1
SDIN2
Master/Slave
Master/Slave
Master/Slave
Master/Slave
SDOUT2
OUTPUT
I2S Port 3
SDIN3
SDOUT3
Master/Slave Master/Slave Master/Slave
el
INPUT/OUTPUT
Pins
INPUT
•
•
•
Pr
Different data formats are supported as below:
I2S
• Left justified
• Right justified
TDM
PCM
• Linear
All of these modes are MSB first.
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5.1.1. PCM(I2S) Audio Input Interface Mapping
The PCM Inputs are connected to the functional blocks as follows:
I2S Audio Input
Functional Blocks
SDIN1
I2S Input Port1
SSS
or ASRC In -->
SSS
SDIN2
I2S Input Port2
SSS
or ASRC In -->
SSS
I2S Input Port3
SSS
or ASRC In -->
SSS
SDIN3
The outputs of the I2S Inputs Ports 1-3 are connected to the ASRC’s 1-3 respectively.
y
5.1.2. PCM(I2S) Audio Output Interface Mapping
I2S Output
ar
Audio Data Source
Source Select Switch (SSS) or ASRC Out
SDOUT1
SDOUT2
in
Source Select Switch (SSS) or ASRC Out
5.1.3. PCM control Register
7:3
RSVD
2
Read/
Write
Reset
Value
R
0
Reserved
RW
0
PCM Frame Length in master mode, 0 = 128 bits
peer frame, 1 = 256 bits per frame
RW
0
hort-Long Frame Sync, 0 = one clock wide, 1 = one
slot wide
RW
0
el
Label
PCMFLENPX
Pr
Page 0, Reg 31 - 2Fh
PCMPXCTL0
Bit
SDOUT3
im
Source Select Switch (SSS) or ASRC Out
1
SLSYNCPX
0
BDELAYPX
Description
Data delay relative to start of frame in PCM mode, 0
= data not delayed relative to start of frame, 1 = data
delayed by one clock relative to start of frame
Table 100. PCMPXCTL0 Register
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Label
Read/
Write
Reset
Value
7
RSVD
R
0
Reserved
6
PCMMOMP2
RW
0
PCM mono output mode, 0- When number of slots =
1, select left data for slot0, 1-select left data for slot0
= 1, select right data for slot0.
5
PCMSOP2
RW
0
Number of Active Slots per PCM Output Frame, 0 =
one, 1 = two
4:3
PCMDSSP2
RW
0
PCM Data Slots Size, 00 = 16 bit, 01 =24 bit, 10 = 32
bit, 11=Reserved
R
0
Reserved
0
PCM mono input mode, 0- When number of slots = 1,
select left data for slot0, silence for slot1, 1-When
number of slots = 1, select left and right data for
slot0.
0
Numver of Active Slots per PCM Input Frame, 0 =
one, 1 = two;
1
PCMMIMP2
0
PCMSIP2
y
2
Description
ar
Page 0, Reg 3 - 2Eh
PCMPXCTL1
Bit
Table 101. PCMOXCTL1 Register
ASRC Input/Output Volume Controls
in
5.2.
el
im
These controls provide adjustment of volume for the PCM audio streams sourced by the ASRC’s. The ASRCVOLU bit
controls the updating of digital volume control data. for the ASRCs. When ASRCVOLU is written as ‘0’, the digital volume is
immediately updated with the ASRCxLVOL data when the Left ASRC Digital Volume register is written. When ASRCxVOLU
is set to ‘1’, the ASRCxLVOL data is held in an internal holding register until the Right ASRC Digital Volume Register is
written.
5.2.1. Output Data Mux Control Register
Bit
Label
Pr
Register Address
7:6
Page 0, Reg 3A
AUDIOMUX1
5:3
2:0
ASRCIMUX
I2S2MUX
I2S1MUX
Type
Default
RW
0
RW
00
RW
00
Description
Input ASRC MUX:00-no input asrc, 01-input asrc
assigned to i2si1, 10-input asrc assigned to i2si2,
11-input asrc assigned to i2si3
I2S2 output Mux Control:3'h0-i2si1, 3'h2-i2si2,
3'h3-i2si3,3'h4-ADC/DMIC1,3'h5-dmic2,3'h6-classd
dsp out,3'h6-dac dsp out-sub dsp out
I2S1 output Mux Control:3'h0-i2si1, 3'h2-i2si2,
3'h3-i2si3,3'h4-ADC/DMIC1,3'h5-dmic2,3'h6-classd
dsp out,3'h6-dac dsp out-sub dsp out
Table 102. AUDIOMUX1 Register
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Portable Audio Consumer Codec
5.2.2. Output Data Mux Control Register
Register Address
Bit
Label
Type
Default
7:6
ASRCOMUX
RW
0
5:3
DACMUX
RW
00
2:0
I2S3MUX
RW
00
Description
Output ASRC MUX:00-no input asrc, 01-input asrc
assigned to i2so1, 10-input asrc assigned to i2so2,
11-input asrc assigned to i2so3
Page 0, Reg 3B
AUDIOMUX2
5.2.3. Output Data Mux Control Register
Label
Type
Page 0, Reg 3C
AUDIOMUX3
7:3
SUBMUX
RW
2:0
CLASSDMUX
Default
ar
Bit
0
Description
Reserved
in
Register Address
y
Table 103. AUDIOMUX2 Register
RW
00
Pr
el
im
Table 104. AUDIOMUX3 Register
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Portable Audio Consumer Codec
5.2.4. I2S Input Volume Control Register
Page 1, Reg 22 - 16h
ASRCILVOL
7:0
7:0
Label
Type
ASRCILVOL
[7:0]
ASRCIRVOL
[7:0]
RW
RW
Default
Description
11101111
(0dB)
ASRC Input Left Digital Volume Control - 0.375dB
steps
0000 0000 = Mute
0000 0001 = -90.25dB
0000 0010 = 89.875dB
1111 1111 = +6dB
Note: If ASRCVOLU is set, this setting will take effect
after the next right to the Right Input Volume
registers.
11101111
(0dB)
ASRC Input Right Digital Volume Control - 0.375dB
steps
0000 0000 = Mute
0000 0001 = -90.25dB
0000 0010 = 89.875dB
1111 1111 = +6dB
Note: If ASRCVOLU is set, this setting will take effect
after the next right to the Right Input Volume
registers.
in
ar
Page 1, Reg 23 - 17h
ASRCIRVOL
Bit
y
Register Address
im
7:0
ASRCOLVOL
[7:0]
RW
11101111
(0dB)
Page 1, Reg 25 - 19h
ASRCORVOL
Pr
el
Page 1, Reg 24 - 18h
ASRCOLVOL
7:0
ASRC Output Left Digital Volume Control - 0.375dB
steps
0000 0000 = Mute
0000 0001 = -90.25dB
0000 0010 = 89.875dB
1111 1111 = +6dB
Note: If ASRCVOLU is set, this setting will take effect
after the next right to the Right Input Volume
registers.
ASRCORVOL
[7:0]
RW
11101111
(0dB)
ASRC Output Right Digital Volume Control - 0.375dB
steps
0000 0000 = Mute
0000 0001 = -90.25dB
0000 0010 = 89.875dB
1111 1111 = +6dB
Note: If ASRCVOLU is set, this setting will take effect
after the next right to the Right Input Volume
registers.
Table 105. ASRCILVOL/ASRCIRVOL and ASRCOLVOL/ASRCORVOL Register
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Portable Audio Consumer Codec
5.2.5. Volume Update Register
Bit
Label
Read/
Write
Reset
Value
7:4
RSVD
R
0
Reserved
1
1 = Input Processor volume fades between old/new
value
0 = Input Processor volume/mute changes
immediately
RW
0
1 = Left Input Processor volume held until right input
volume register written
0 = Left Input Processor volume updated
immediately
RW
0
1 = Left PGA input volume held until right input
volume register
0 = Left PGA input volume updated immediately
RW
0
1 = Left ASRC volume held until right input volume
register written. This affects input and output ASRC
volume controls.
0 = Left ASRC volume updated immediately
RW
2
INPVOLU
1
PGAVOLU
0
y
Page 1, Reg 28 - 1Ch
VOLCTLU
IFADE
ar
3
Description
ASRCVOLU
Audio Interface Clocking Options
el
5.3.
im
in
Table 106. VOLCTLU Register
5.4.
Pr
Three pairs of bit clock and frame signals (BCLK/LRCLK) are available for clocking the various I2S interface ports. I2S
Ports 1-3 are associated with I2S inputs and the BCLK/LRCLK signals can be inputs (Slave operation) or outputs (Master
Operation). .Each I2S port has register bits for controlling the I2S format, the number of bits, and the polarity of the BCLK
and LRCLK signals.
Master and Slave Mode Operation
The TSCS454 I2S ports can be used as either a master or slave device, selected by the PORTxMS Bits. Both the I2S
inputs and outputs operate at the same rate. When an I2S Port is operating as a master, the TSCS454 generates the bit
clocks and frame clock signals. In slave mode, the TSCS454 assumes the input audio data is aligned to clocks it receives.
5.5.
Audio Data Formats
The TSCS454 supports 4 common audio interface formats and programmable clocking that provides broad compatibility
with DSPs, Consumer Audio and Video SOCs, FPGAs, handset chip sets, and many other products.
In all modes, depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each
LRCLK transition. If the converter word length is smaller than the number of clocks per sample in the frame then the DAC
will ignore (truncate) the extra bits while the ADC will zero pad the output data. If the converter word length chosen is larger
than the number of clocks available per sample in the frame, the ADC data will be truncated to fit the frame and the DAC
data will be zero padded.
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Left Justified Audio Interface:
Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits are
then transmitted in order. The LRCLK signal is high when left channel data is present and low when right channel data is
present
.
1/fs
Left Justified
Left Channel
Right Channel
LRCLK
1
2
3
n-2 n-1
MSB
n
1
2
3
LSB
MSB
LSB
in
Word Length (WL)
n
n-2 n-1
ar
SDI / SDO
y
BCLK
el
im
Figure 21. Left Justified Audio Format
Pr
Right Justified Audio Interface (assuming n-bit word length):
Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are
transmitted in order. The LRCLK signal is high when left channel data is present and low when right channel data is
present.
1/fs
Right Justified
Left Channel
Right Channel
LRCLK
BCLK
SDI / SDO
1
2
3
n-2 n-1
MSB
n
1
LSB
MSB
2
3
n-2 n-1
n
LSB
Word Length (WL)
Figure 22. Right Justified Audio Format
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Portable Audio Consumer Codec
5.5.0.1.I2S Format Audio Interface
I2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the
LSB are then transmitted in order.
1/fs
I2S
Left Channel
Right Channel
LRCLK
BCLK
1
2
3
n-2 n-1
MSB
n
1
LSB
2
3
MSB
n-2 n-1
n
LSB
ar
SDI / SDO
1 BCLK
y
1 BCLK
Word Length (WL)
im
in
Figure 23. I2S Format AudioFormat
el
5.5.0.2.TDM (DSP) Format Audio Interface
Pr
TDM Mode is a time-division multiplexed format for transmitting and receiving multiple channels of audio information over a
single data connection. When TDM mode is enabled the SDIN1 and SDOUT1 pins are used to input and output TDM data
respectively. TDM data is transferred MSB first and the LRCLK/BCLK (frame clock/bit clock) ratio is fixed at two rates;
200Fs and 256Fs. Each digital audio input and output supports up to six,16, 24, or 32 bit time slots, with the audio data left
justified within the time slot by padding the unused bits with zeros. Valid audio data word lengths are 16, 20, or 24.(MSB
justified within a slot) The defined audio data word length is always the same for both TDM input and output. Short or Long
frame syncs are supported. The data lines are tri-stated after the programmed number of data slots have been transmitted
or received. The TDM interface operates in either slave or master mode. Data is sampled on the falling edge of the bit clock
and transmitted on the rising edge. A control bit selects between a delayed and non-delayed data timing relative to the start
of the frame sync. The BCLK invert bit is functional in this mode. The LRCLK is one bit clock long for a Short Frame Sync
and one slot wide for a Long Frame Sync.Operating I2S Port 1 in TDM mode does not prevent the other I2S interfaces
(Ports 2,3) to be used if four or fewer time slots are enabled.
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Portable Audio Consumer Codec
N o n - D e la y e d T im in g
2 5 6 /2 0 0 c lk s
LR C LK
BC LK
S D IN 1
LSB
M SB
M SB
LSB
SLO T 0
SD O U T2
LSB
M SB
LSB
M SB
SLO T 1
M SB
SLO T 0
LSB
M SB
SLO T 2
LSB
M SB
S LO T 1
LSB
M SB
SLO T 3
LSB
M SB
SLO T 2
LSB
LSB
M SB
S LO T 3
LSB
M SB
SLO T 4
S LO T 5
LSB
M SB
SLO T 4
H i- z
LSB
SLO T 5
H i- z
D e la y e d T im in g
2 5 6 /2 0 0 c lk s
LR C LK
BC LK
M SB
LSB
SLO T 0
SD O U T2
M SB
M SB
LSB
M S B
S LO T 1
LSB
SLO T 0
M SB
LSB
M S B
SLO T 2
M SB
LSB
M S B
SLO T 1
LSB
M S B
LSB
S LO T 3
LSB
M S B
S LO T 2
M S B -1
LSB
M S B
SLO T 3
n
LSB
SLO T 4
LSB+1
LSB
SLO T 5
M SB
H i- z
LSB
SLO T 5
H i- z
LSB
b its
in
16, 24, or 32
M SB
S LO T 4
y
LSB
ar
S D IN 2
Figure 24. TDM Mode Timing
im
TDM Slot Mapping:
SLOT1
TDM Output Source
SDOUT1
Pr
TDM Input Destination
SDIN1
el
For TDM mode the audio data is mapped in slots according to the following table. The mapping is fixed. The TDM input
data stream, via SDIN1, data slots are routed to the SSS via the same data path as the I2S inputs. Thus the SDIN2 and
SDIN3 I2S inputs are not available in TDM mode when the TDM interface is programmed for more than 2 or 4 slots. The
TDM output data stream is sourced from the data streams driving the I2S outputs
DSPIN1
SDOUT1-L
SLOT1
DSPIN2
SDOUT1-R
SLOT2
SLOT3
DSPIN3
SDOUT2-L
SLOT3
SLOT4
DSPIN4
SDOUT2-R
SLOT4
SLOT5
DSPIN5
SDOUT3-L
SLOT5
SLOT6
DSPIN6
SDOUT3-R
SLOT6
SLOT2
Table 107. TDM Slot Mapping
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2
I2 S S D O U T 1
ASRCO
TDM
M
U
X
S L O T 1 /2
M
U
X
S L O T 3 /4
TD M _O U T
2
M
U
X
2
ADC/
D M IC
2
S L O T 5 /6
TDM
2
S L O T 1 /2
O u tp u t
2
P ro c e s s o r
S D IN 1
(T D M _ IN )
S o u rc e
S e le c t
S w it c h
S L O T 3 /4
S L O T 5 /6
SPK O ut L
C la s s D
PW M
BTL
SPK O ut R
1
O u tp u t
P ro c e s s o r
1
BTL
DAC
I2 S 2 S D IN 2
I2 S 3 S D IN 3
2
O u tp u t
P ro c e s s o r
2
DAC
y
ASRCI
E A R /S U B
O ut
H P / L in e O u t
L in e O u t
ar
M
U
X
I2 S S D O U T 2
I2 S S D O U T 3
5.6.
Digital Audio Interface Registers
in
Figure 25. TDM Mode Data Source/Destination Diagram
im
The register bits controlling audio format, word length and master / slave mode are shown below. In Master mode
BCLK1:3, LRCK1:3, are outputs; in slave mode, they are inputs.
el
The I2S interface can be operated in either Master or Slave mode. When operating in Slave mode one input can be
redirected towards ASRCI is active and will auto-detect the incoming audio sample rate and convert the audio sample rate
to currently defined ASRC output sample rare. rate to the currently defined ASRC output sample rate.The ASRC can
power down independently of I2S port.
Pr
5.6.1. LRCK and BLCK Mode Control
The TSCS454 includes three input PCM audio interfaces labeled as TDM, PCM2, and PCM3. The clocking of data through
the PCM/TDM interface is controlled by Frame Sync (LRCLK) and Bit Clock (BCLK) signals.
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5.6.1.1. I2S Port 1 Control Register
Register Address
Bit
Type
Default
Description
7
BCLK1STAT
RW
0
Valid when operating in “Slave Mode” Bit when set
indicates a loss of the BCLK has occurred. This bit is
sticky and is reset by writing a “1” to this bit.
0 = no loss of BCLK1 has occurred
1 = loss of BCLK1 has occurred
6
BCLKP1
RW
0
BCLKP1 invert bit (for master and slave modes)
0 = BCLKP1 not inverted
1 = BCLKP1 inverted
5
PORT1MS
RW
0
Port1 Master/Slave.
0 = Slave
1 = Master
0
Right, left and I2S modes – LRCLKP1 polarity
0 = LRCLKP1 not inverted
1 = LRCLKP1 inverted
10
Audio Data Word Length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRCLKP1
RW
RW
FORMAT1[1:0]
RW
Audio Data Format Select
11 = TDM Format
10 = I2S Format
01 = Left justified
00 = Right justified
10
im
1:0
WL1[1:0]
in
3:2
ar
y
Page 0, Reg 26 - 1Ah
I2SP1CTL
Label
Pr
el
Table 108. I2SP1CTL Register
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5.6.1.2.I2S Port 2 Control Register
Register Address
Bit
Type
Default
Description
7
BCLK2STAT
RW
0
Valid when operating in “Slave Mode” Bit when set
indicates a loss of the BCLK has occurred. This bit is
sticky and is reset by writing a “1” to this bit.
0 = no loss of BCLK2 has occurred
1 = loss of BCLK2 has occurred
6
BCLKP2
RW
0
BCLKP2 invert bit (for master and slave modes)
0 = BCLKP2 not inverted
1 = BCLKP2 inverted
5
PORT2MS
RW
0
Port 2 Master/Slave.
0 = Slave
1 = Master
0
Right, left and I2S modes – LRCLK2 polarity
0 = LRCLK2 not inverted
1 = LRCLK2 inverted
10
Audio Data Word Length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRCLKP2
RW
RW
FORMAT2[1:0]
RW
Audio Data Format Select
11 =PCM Format
10 = I2S Format
01 = Left justified
00 = Right justified
10
im
1:0
WL2[1:0]
in
3:2
ar
y
Page 0, Reg 27 - 1Bh
I2SP2CTL
Label
Pr
el
Table 109. I2SP2CTL Register
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5.6.1.3.I2S Port 3 Control Register
Register Address
Label
Type
Default
Description
7
BCLK3STAT
RW
0
Valid when operating in “Slave Mode” Bit when set
indicates a loss of the BCLK has occurred. This bit is
sticky and is reset by writing a “1” to this bit.
0 = no loss of BCLK3 has occurred
1 = loss of BCLK3 has occurred
6
BCLKP3
RW
0
BCLKP3 invert bit (for master and slave modes)
0 = BCLKP3 not inverted
1 = BCLKP3 inverted
5
PORT3MS
RW
0
Port 3 Master/Slave.
0 = Slave
1 = Master
0
Right, left and I2S modes – LRCLK3 polarity
0 = LRCLKP3 not inverted
1 = LRCLKP3 inverted
10
Audio Data Word Length
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRCLKP3
RW
RW
FORMAT3[1:0]
RW
Audio Data Format Select
11 = PCM Format
10 = I2S Format
01 = Left justified
00 = Right justified
10
im
1:0
WL3[1:0]
in
3:2
ar
y
Page 0, Reg 28 - 1C
I2SP3CTL
Bit
Pr
el
Table 110. I2SP3CTL Register
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5.6.1.4.I2S Port 1 Master Sample Rate Register
Bit
Label
Type
Default
7
I2S1MCLKHALF
RW
0
I2S1 MCLK Divide By 2
0 = Divide by 2
1 = Divide by 1
0
I2S1 MCLK Divider when I2S1MBR= 11
00 = 125
01 = 128
10 = 136
11 = 192
6:5
I2S1MCLKDIV[1:0]
RW
4:3
I2S1MBR
RW
10
I2S1 Base Rate
00 = 32KHz
01 = 44.1KHz
10 = 48KHz
11 = MCLK2 mode
2
RSVD
R
0
Reserved
I2S1MBM
RW
10
in
1:0
I2S1 Base Rate Multiplier
00 = 0.25x
01 = 0.50x
10 = 1x
11 = 2x
ar
Page 0, Reg 29 - 1Dh
I2S1MRATE
Description
y
Register Address
Table 111. I2S1MRATE Register
Label
Type
Default
7
I2S2MCLKHALF
RW
0
I2S2 MCLK Divide By 2
0 = Divide by 2
1 = Divide by 1
0
I2S2 MCLK Divider when I2S1MBR= 11
00 = 125
01 = 128
10 = 136
11 = 192
el
Bit
Pr
Register Address
im
5.6.1.5.I2S Port 2 Master Sample Rate Register
6:5
I2S2MCLKDIV[1:0]
RW
Description
4:2
I2S2MBR
RW
10
I2S2 Base Rate
00 = 32KHz
01 = 44.1KHz
10 = 48KHz
11 = MCLK2 mode
2
RSVD
R
0
Reserved
10
I2S2 Base Rate Multiplier
00 = 0.25x
01 = 0.50x
10 = 1x
11 = 2x
Page 0, Reg 30 - 1Eh
I2S2MRATE
1:0
I2S2MBM
RW
Table 112. I2S2MRATE Register
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Portable Audio Consumer Codec
5.6.1.6.I2S Port 3 Master Sample Rate Register
Register Address
Bit
Label
Type
Default
7
I2S3MCLKHALF
RW
0
I2S3 MCLK Divide By 2
0 = Divide by 2
1 = Divide by 1
0
I2S3 MCLK Divider when I2S1MBR= 11
00 = 125
01 = 128
10 = 136
11 = 192
6:5
I2S3MCLKDIV[1:0]
RW
4:2
I2S3MBR
RW
10
I2S3 Base Rate
00 = 32KHz
01 = 44.1KHz
10 = 48KHz
11 = MCLK2 mode
2
RSVD
R
0
Reserved
ar
I2S3MBM
I2S3 Base Rate Multiplier
00 = 0.25x
01 = 0.50x
10 = 1x
11 = 2x
RW
10
in
1:0
y
Page 0, Reg 31 - 1Fh
I2S3MRATE
Description
Table 113. I2S3MRATE Register
Bit
Label
7:6
RSVD
Page 0, Reg 56 - 38h
I2S Input Data
Mapping Control
Default
R
0
I2S3IDCTL[1:0]
RW
Pr
5:4
Type
3:2
1:0
I2S2IDCTL[1:0]
I2S1IDCTL[1:0]
RW
RW
Description
Reserved
el
Register Address
im
5.6.1.7. I2S Input Data Mapping Control Register
0
I2S 3 Input Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
0
I2S 2 Input Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
0
I2S 1 Input Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
Table 114. I2SIDCTLRegister
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5.6.1.8. I2S Output Data Mapping Control Register
Bit
Label
Type
Default
7:6
RSVD
R
0
Reserved
0
I2S 3 Output Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
0
I2S 2 Output Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
0
I2S 1 Output Data Mapping
00 = Normal
01 = Left on both Channels
10 = Right on both Channels
11 = Swap Left and Right Channels
5:4
Page 0, Reg 57 - 39h
I2S Output Data
Mapping Control
3:2
I2S2ODCTL[1:0]
I2S1ODCTL[1:0]
RW
RW
RW
ar
1:0
I2S3ODCTL[1:0]
Description
y
Register Address
el
5.6.2. Bit Clock Mode
im
in
Table 115. I2SODCTL Register
Pr
The default master mode bit clock generator for each I2S port automatically produces a bit clock frequency based on the
sample rate and word length. When enabled by setting the appropriate BCM bits, the bit clock mode (BCM) function
overrides the default master mode bit clock generator to produce the bit clock frequency shown below: Note that selecting
a word length of 24-bits in Auto mode generates 64 clocks per frame (64fs).
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Portable Audio Consumer Codec
5.6.2.1. I2S Ports Bit 1-3 Clock Mode Control Register
Bit
Label
Type
Default
7:6
RSVD
R
0
Reserved
0
I2S Port 3 Bit Clock Mode
00 = Auto
01 = 32 x fs
10 = 40 x fs
11 = 64 x fs
0
I2S Port 2 Bit Clock Mode
00 = Auto
01 = 32 x fs
10 = 40 x fs
11 = 64 x fs
0
I2S Port 1 BIt Clock Mode
00 = Auto
01 = 32 x fs
10 = 40 x fs
11 = 64 x fs
5:4
Page 0, Reg 32 - 20h
I2SP1-3CMC
I2S Ports 1-3 Bit
Clock Mode Control
3:2
BCMP2[1:0]
BCMP1[1:0]
RW
RW
RW
ar
1:0
BCMP3[1:0]
Description
y
Register Address
Table 116. I2S Ports 1-3 Clock Mode Control Register
im
in
The BCM mode bit clock generator produces 16, 20, or 32 bit cycles per sample.
LRCLK
Fs x 40
Pr
Fs x 32
el
Fs x 64
Note: The clock cycles are evenly distributed throughout the frame (true multiple of LRCLK not a gated clock.)
5.6.3. SCLK Underflow and Overflow
When the serial audio interface is configured in stereo mode, an SCLK overflow condition occurs when there are more than
32 SCLK cycles between consecutive edges of the LRCLK. Similarly, an SCLK underflow condition occurs when there are
less than 32 SCLK cycles between consecutive edges of the LRCLK. In an SCLK overflow condition, the extra SCLK
cycles are ignored. In an SCLK underflow condition, all remaining non-loaded data bits are filled with zeros.
5.6.4.
Audio Interface Output Tri-state Control
TRI is used to tri-state the SDOUT3:1, LRCLK3:1, BCLK3:1 pins. The Tri-stated pins are pulled low with an internal
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TSCS454
TSCS454
Portable Audio Consumer Codec
I2Spull-down resistor unless that resistor is disabled.
5.6.5. I2S Pin Control 0 Register
Type
Default
7
SDO3TRI
RW
0
Tri-state pin.
0 = SDOUT3 is an output
1 = SDOUT3 is high impedance
6
SDO2TRI
RW
0
Tri-state pin.
0 = SDOUT2 is an output
1 = SDOUT2 is high impedance
5
SDO1TRI
RW
0
Tri-state pin.
0 = SDOUT1 is an output
1 = SDOUT1 is high impedance
4:3
RSVD
R
0
Reserved
0
Tri-state pin.
0 = LRCK3, BCLK3 are inputs (slave mode) or outputs
(master mode)
1 = LRCK3, BCLK3 are high impedance
1
0
PCM3TRI
PCM2TRI
PCM1TRI
RW
RW
0
ar
2
Description
y
Label
Tri-state pin.
0 = LRCK2, BCLK2 are inputs (slave mode) or outputs
(master mode)
1 = LRCK2, BCLK2 are high impedance
in
Page 0, Reg 34 - 22h
I2SPINC0
Bit
Tri-state pin.
0 = LRCK1, BCLK1 are inputs (slave mode) or outputs
(master mode)
1 = LRCK1, BCLK1 are high impedance
im
Register Address
RW
0
Pr
el
Table 117. I2SPINC0 Register
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TSCS454
Portable Audio Consumer Codec
Pin Control 1 Register
Register Address
Page 0, Reg 35 - 23h
I2SPINC1
Bit
Label
Type
Default
Description
7:3
RSVD
R
0
Reserved
2
SDO3PDD
RW
0
SDOUT3 Pull-Down Disable
0 = Pull-Down active when tri-stated 1 = Pull-Down
always disabled
1
SDO2PDD
RW
0
SDOUT2 Pull-Down Disable
0 = Pull-Down active when tri-stated 1 = Pull-Down
always disabled
0
SDO1PDD
RW
0
SDOUT1 Pull-Down Disable
0 = Pull-Down active when tri-stated
1 = Pull-Down always disabled
5.6.7. I2S Pin Control 2 Register
Label
Type
Default
7:6
RSVD
R
0
5
LR3PDD
RW
4
BC3PDD
3
Description
in
Reserved
LRCLK3 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
im
0
0
BCLK3 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
el
Page 0, Reg 36 - 24h
I2SPINC2
Bit
0
LRCLK2 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
LR2PDD
RW
RW
Pr
Register Address
ar
Table 118. I2SPINC1 Register
y
5.6.6.
2
BC2PDD
RW
0
BCLK2 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
1
LR1PDD
RW
0
LRCLK1 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
0
BC1PDD
RW
0
BCLK1 Pull-Down Disable
0 = Pull-Down active when configured as input
1 = Pull-Down always disabled
Table 119. I2SPINC2 Register
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TSCS454
Portable Audio Consumer Codec
5.6.8. TDM Control 0 Register
Page 0, Reg 45 - 2Dh
TDMCTL0
Bit
Label
Type
Default
7:3
RSVD
R
0
Reserved
2
TDMMODE
RW
0
TDM Mode
0 = 200 bits per frame
1 = 256 bits per frame
1
SLSYNC
RW
0
Short-Long Frame Sync
0 = short frame sync, one clock wide
1 = long frame sync, half of frame wide
0
Bit Clock Delay relative to start of data in TDM mode
0 = bit clock not delayed relative to start of data
1 = bit clock delayed by one clock relative to start of
data
0
BDELAY
RW
Description
ar
Table 120. TDMCTL0 Register
5.6.9. TDM Control 1 Register
Type
7
RSVD
R
6:5
4:3
TDMSO[1:0]
RW
TDMDSS
RW
Pr
Page 0, Reg 46 - 2Eh
TDMCTL1
2
1:0
Default
Description
in
Label
0
Reserved
Number of slots per TDM Output Frame
00 = 2
01 = 4
10 = 6
11 = Reserved
im
Bit
01
0
TDM Data Slot Width
00 = 24 bit
01 = 16 bit
10 = 32 bit
11 = reserved
0
Reserved
01
Number of slots per TDM Output Frame
00 = 2
01 = 4
10 = 6
11 = Reserved
el
Register Address
y
Register Address
RSVD
TDMSI[1:0]
R
RW
Table 121. TDMCTL1 Register
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TSCS454
Portable Audio Consumer Codec
5.7.
ASRC's
The three digital I2S audio input ports can be muxed to one Asynchronous Sample Rate Converters (ASRC) to converter
the incoming audio data streams from whatever sample rate they are running at to an internal known sample rate. The
three digital I2S audio output ports can mux ASRC output which converts the internal audio data streams from a known
sample rate to another sample rate. ASRC’s can also provide attenuation of incoming audio source jitter which may
improve the audio performance of the design.
5.7.1. Supported Input Sample Rates
The ASRC must support input sample rates from 8KHz to 96KHz.
Autorate Detection
12KHz
16KHz
22.050KHz
24KHz
32KHz
44.100KHz
48KHz
64KHz
88.2KHz
96KHz
Table 122. Standard Audio Sample Rates
ar
11.025KHz
in
8KHz
y
Standard Audio Sample Input Rates
5.7.1.1.Master/Slave Operation
im
The incoming audio sample rate is unknown when the audio interface is operating in slave mode and therefore must be
estimated. Typically the audio frame period (sample rate) is determined by counting the number of clock pulses that occur
during the frame. No programming should be required to support the range of input sample rates.
Pr
el
The ASRC can operates either in Master or Slave mode. In Master mode the audio sample rate and signal timing on the
input side is defined by a set of registers based on internal clocks. In Slave mode the ASRC auto detects the incoming
audio sample rate and adjusts the processing to match the defined ASRC output audio sample rate. In Slave mode
operation Autorate detection of sample rate is required.
5.7.2. ASRC Output Rates
The ASRC’s convert the incoming audio sample rate to one of two sample rates as specified by the System Clock Control
and internal Sample Rate Control Register. See “Figure 33 shows the simplified block diagram. The TSCS454 utilizes
internal PLLs to generate the PLL clocks at 112.896 MHz (22.5792MHz *5) and122.880 MHz (24.576 *5). Intermediate
clocks (61.44MHz, 40.96MHz, 56.448MHz) are then generated which are then used to generate the audio sample rates.
There is one internal clock rate that can be specified to operate at 11.025KHz, 12 KHz, 22.050KHz, 24KHz, 44.1KHz,
48KHz,88.2KHz, and 96KHz. When changing sample rates a delay of up to 5mS may be needed for the part to properly
lock PLLs, flush filters, etc.” on page 124.
5.7.2.1.ASRC Bypass
The ASRC’s may be bypassed. When the ASRC is bypassed it is put into a powered down state to save power. The
ASRC’s are bypassed via the ASRCx Bypass Bit when the incoming I2S rate is synchronized to the currently defined
Internal ICLK audio rate. In this case the input clock (MCLK) to the TSCS454 would need to be driven by the external
master audio source and the timing of the I2S interface synchronized to this clock. The ASRC volume control function is
Active in bypass mode
Note: this may require that the internal clock generation must support an external sync mode so that the internal clock
timing of the TSCS454 can be synchronized to an external I2S source when the ASRC’s are bypassed.
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Portable Audio Consumer Codec
5.7.3. ASRC Control
Bit
7
Type
ASRCOBW
RW
Default
Description
0
Output ASRC High-Bandwidth Support:
0 = Audio content is assumed to be 20kHz or less
(filtering is limited for higher rates, to save cycles)
1 = Audio content can be as high as allowed by the
sample rate
ASRCIBW
RW
0
5
ASRCOB
RW
0
Output ASRC1 Bypass
0 = Output ASRC Active
1 = Output ASRC Bypassed
4
ASRCIB
RW
0
3
ASRCOL
R
2
ASRCIL
1:0
RSVD
ar
y
6
Input ASRC High-Bandwidth Support:
0 = Audio content is assumed to be 20kHz or less
(filtering is limited for higher rates, to save cycles)
1 = Audio content can be as high as allowed by the
sample rate
Input ASRC1 Bypass
0 = Input ASRC Active
1 = Input ASRC Bypassed
Output ASRC1 Lock Status
0 = Output ASRC Unlocked
1 = Output ASRC Locked
in
0
R
0
Input ASRC1 Lock Status
0 = Input ASRC Unlocked
1 = Input ASRC Locked
R
0
Reserved
el
Page 0, Reg 40 - 28h
ASRC
Label
im
Register Address
Pr
Table 123. ASRC Register
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TSCS454
Portable Audio Consumer Codec
6. HOST CONTROL, I2C, 2-WIRE CONTROL INTERFACE
The TSCS454 device includes a 2-Wire I2C compatible interface for communicating with an external controller. This interface supports communication to external micro-controller or other I2C compatible peripheral chips. The I2C interface supports normal and fast mode operation. The TSCS454 incorporates a Paged accessing scheme.
The device address can be set using hardware pin strapping via the GPIO0, GPIO1 pins or via a register. When using the
hardware pin strapping method the Mixer device address is always offset from the register device address by + 0x2 The
default I2C device address is 0xD2 for the registers. The TSCS454 registers are accessed through a unique serial control
interface using a multi-word protocol comprised of 8-bit words. The first 8 bits provide the device address and Read/Write
flag. In a write cycle, the next 8 bits provide the register address; all Subsequent words contain the data, corresponding to
the 8 bits in each control register.
The control interface operates as a slave device when communicating to an external controller.
Register
Access
im
in
I2C
Address
Data
Pr
el
Registers
256 Pages
Page ...
Page 2
Page 1
Page 0
Device Address
#1
ar
Logic
y
Programming
Figure 26. I2C Register-Mixer Access Diagram
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Portable Audio Consumer Codec
6.1.
I2C Device Addressing
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
A2
A1
1
R/W
Table 124. I2C Device Address Byte Format
GPIO0
A2
A1
I2C
Device Address
ar
GPIO1
y
The address byte format is shown in Table 124. The TSCS454 slave addresses are set with the GPIO0/ADDR1,
GPIO1/ADDR2 pins. The address resides in the first seven bits of the I2C write. The LSB of this byte sets either a read or
write operation. Logic Level 1 corresponds to a read operation, and Logic Level 0 corresponds to a write operation. Bits 3
and 2 of the address are set by tying the GPIO1, GPIO0 pins of the TSCS454 to Logic Level 0 or Logic Level 1.The state
of these pins is latched on power-up via an internal power-valid signal. Once the device address has been configured, The
SEL Bit 1 is generated by the host controller’s I2C address and decoded by the TSCS454 to access the Register address
space. The device address mapping is shown below in Table 125
in
SEL= 1
0
0xD2
1
0xD6
im
0
0
1
0
0xDA
1
1
0xDE
el
Table 125. I2C Address Via Pin Strapping
Pr
The TSCS454 default I2C slave address can be configured via the GPIO0/ADDR1, and GPIO1/ADDR2 pins but it may be
necessary sometimes to use a different address. The TSCS454 has a device address register for this purpose. The device
address register can be updated by an external micro-controller. The device address can be uniquely specified for the Register address spaces. It should be noted that the TSCS454 must be accessed via one of the default I2C device addresses
as defined by the GPIO0/ADDR1, GPIO1ADDR2 pins in order for the device address to be changed.
Device Address Register
Register Address
Page 0, Reg 6 -6h
DEVADD0
Bit
Label
Type
7:1
ADDR[7:1]
RW
0
I2C_ADDRLK
RW
Default
Description
See note 7-bit slave address for registers
Locks I2C address if set to 1. Part must be powered
down to reset this bit
0
Table 126. DEVADD0 Register
Note: The default setting is determined by the GPIO0/ADDR1 and GPIO1/ADDR2 pins on power-up. The state of the pins
determines the default value for bits 3:2 of this register.
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Portable Audio Consumer Codec
Device Identification Register
Register Address
Bit
Label
Type
Page 0, Reg 8 - 8h
DEVID
7:0
DID[:7:0]
R
Default
Description
8-bit device identification number. The least
01000xx
significant three bits reflect the state of the Bond-Out
xb
pins.
Table 127. DEVID Register
Device Revision Register
Page 0, Reg 9 - 9h
REVID
Bit
Label
Type
Default
Description
7:4
MAJ_REV[3:0]
R
0001
4-bit major revision number (all layer)
currently = 1 (1st release)
MMMM.mmmm currently = 1.0
3:0
MNR_REV[3:0]
R
0000
4-bit minor revision number (metal revision)
currently = 0 (no revisions-initial release)
Page Register Write Cycle
in
6.2.
ar
Table 128. REVID Register
y
Register Address
el
im
The controller indicates the start of data transfer with a high to low transition on SDA while SCL remains high, signalling
that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next
eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the
TSCS454 and the R/W bit is ‘0’, indicating a write, then the TSCS454 responds by pulling SDA low on the next clock pulse
(ACK); otherwise, the TSCS454 returns to the idle condition to wait for a new start condition and valid address.
Once the TSCS454 has acknowledged a correct device address, the controller sends the TSCS454 register address. The
TSCS454 acknowledges the register address by pulling SDA low for one clock pulse (ACK). The controller then sends a
byte of data (B7 to B0), and the TSCS454 acknowledges again by pulling SDA low.
Pr
When there is a low to high transition on SDA while SCL is high, the transfer is complete. After receiving a complete
address and data sequence the TSCS454 returns to the idle state. If a start or stop condition is detected out of sequence,
the device returns to the idle condition.
Device
Address
W
Register
A
Address
[7:0]
S
Device Address DA [6:0]
W
Register Address RA
S
A
S
Data [7:0]
A
S
S
SCL
SDA
[7:0]
Register Data RD [7:0]
ACK
ACK
START
ACK
STOP
I2C Register Write
Figure 27. Page Register Write -2 Wire Serial Control Interface
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TSCS454
Portable Audio Consumer Codec
6.3.
Page Register Burst Write Cycle
The controller may write more than one register within a single write cycle. To write additional registers, the controller will
not generate a stop or start (repeated start) command after receiving the acknowledge for the second byte of information
(register address and data). Instead the controller will continue to send bytes of data. After each byte of data is received,
the register address is incremented.
S
Device
Address
W
Register
A
S Address [7:0]
A
S
A
S
Data [7:0]
Data [...]
A
S
Data [n]
A
S
S
SCL
Device Address DA
SDA
[6:0]
W
Register Address RA
[7:0]
ACK
Register Data RD
[7:0]
ACK
[7:0]
Register Data RD
@RA[7:0]+1
Register Data RD [7:0]
@ RA [7:0]+ n
ACK
ACK
ACK
START
STOP
Write Register 2
Address = RA+1
Write Register n
Address = RA+n
y
Write Register 1 Address = RA
6.4.
ar
Figure 28. Page Register Burst Write Cycle
Page Register Read Cycle
in
The controller indicates the start of data transfer with a high to low transition on SDA while SCL remains high, signalling
that a device address and data will follow. If the device address received matches the address of the TSCS454 and the
R/W bit is ‘0’, indicating a write, then the TSCS454 responds by pulling SDA low on the next clock pulse (ACK); otherwise,
the TSCS454 returns to the idle condition to wait for a new start condition and valid address.
el
im
Once the TSCS454 has acknowledged a correct address, the controller sends a restart command (high to low transition on
SDA while SCL remains high). The controller then re-sends the devices address with the R/W bit set to ‘1’ to indicate a read
cycle.The TSCS454 acknowledges by pulling SDA low for one clock pulse. The controller then receives a byte of register
data (B7 to B0).
S
Pr
For a single byte transfer, the host controller will not acknowledge (high on data line) the data byte and generate a low to
high transition on SDA while SCL is high, completing the transfer. If a start or stop condition is detected out of sequence,
the device returns to the idle condition.
Device
Address
W
Register
A
Address
[7:0]
S
Device
Address
A
S
S
R A
S
Data [7:0]
NA S
SCL
Device Address DA [6:0]
SDA
Register Address RA [7:0]
W
ACK
START
Device Address DA [6:0]
ACK
RESTART
Register Data RD
R
[7:0]
nACK
ACK
STOP
I2C Register Read
Figure 29. Page Register Single Byte Read Cycle
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TSCS454
Portable Audio Consumer Codec
6.5.
Page Register Burst Read Cycle
The controller may read more than one register within a single read cycle. To read additional registers, the controller will not
generate a stop or start (repeated start) command after sending the acknowledge for the byte of data. Instead the controller
will continue to provide clocks and acknowledge after each byte of received data. The TSCS454 will automatically increment the internal register address after each register has had its data successfully read (ACK from host) but will not increment the register address if the data is not received correctly by the host (nACK from host) or if the bus cycle is terminated
unexpectedly (however the EQ/Filter address will be incremented even if the register address is not incremented when performing EQ/Filter RAM reads). By automatically incrementing the internal register address after each byte is read, all the
internal registers of the TSCS454 may be read in a single read cycle.
S
Device
Address
W
Register
A
S Address [7:0]
Device
Address
A
S
S
R A
S
N
S
A
Data [7:0]
SCL
Register Address RA [7:0]
W
Device Address DA [6:0]
ACK
ACK
START
W
Register
A
S Address [7:0]
A
S
S
Device
Address
[6:0]
W
Register Address RA
ACK
[7:0]
Device Address DA [6:0]
ACK
START
RESTART
Data [7:0]
A
Data [7:0]
N S
Address = n+1 M Address = n+2 A
in
Device Address DA
A
M
Data [7:0]
Address = n
R A
S
SCL
SDA
nACK
STOP
RESTART
Device
Address
[7:0]
ACK
ar
S
Register Data RD
R
y
Device Address DA [6:0]
SDA
R
Register Data RD
[7:0]
ACK
im
Read Register 1 Address = RA
[7:0]
Register Data RD
@RA[7:0]+1
Register Data RD [7:0]
@ RA [7:0]+ n
nACK
ACK
ACK
STOP
Read Register 2
Address = RA+1
Read Register n
Address = RA+n
I2C Register Burst Read
6.6.
el
Figure 30. Page Register Burst Multi-byte) Read Cycle
GPIO’s
Pr
Four GPIO’s are available on the GPIO3-GPIO0 pins. These GPIO pins are accessed via register bits.The GPIO1-GPIO0
pins are also used to specify the I2C device address on power-up. The general-purpose input/output (GPIO) pins can be
used as either inputs or outputs. These pins are readable and can be set or read through the control interface. These pins
are useful for interfacing to external hardware.
6.6.1.
GPIO Usage Summary
GPIO Pin
Function 1
Function 2
Pull-Up
Pull-Down
GPIO0
I2C address 0
GPIO0 Register Bit
Pull-Down
GPIO1
I2C Address 1
GPIO1 Register Bit
Pull-Down
RSVD
Pull-Up
RSVD
Pull-Up
GPIO2
GPIO3
GPIO2 Register Bit
GPIO3 Register Bit
Table 129. GPIO Pin Usage Summary
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Portable Audio Consumer Codec
6.6.2.
GPIO Control Registers
6.6.2.1.GPIO Control 0 Register
Bit
7
Label
GPIO3INTP
Type
Default
Description
RW
0
GPIO3 Interrupt Polarity
0 = generate interrupt on high going edge
1 = generate interrupt on low going edge
GPIO2INTP
RW
0
GPIO2 Interrupt Polarity
0 = generate interrupt on high going edge
1 = generate interrupt on low going edge
5
GPIO3CFG
RW
0
GPIO3 Configuration
0 = GPIO3 Configured as Input/Output
1 = GPIO3 Configured as Interrupt
4
GPIO2CFG
RW
0
GPIO2 Configuration
0 = GPIO2 Configured as Input/Output
1 = GPIO2 Configured as Interrupt
3
GPIO3IO
RW
0
2
GPIO2IO
RW
1
GPIO1IO
RW
0
GPIO1 Input/Output
0 = GPIO1 configured as input
1 = GPIO1 configured as output
0
GPIO0IO
RW
0
GPIO0 Input/Output
0 = GPIO0 configured as input
1 = GPIO0 configured as output
GPIO3 Input/Output
0 = GPIO3 configured as input
1 = GPIO3 configured as output
GPIO2 Input/Output
0 = GPIO2 configured as input
1 = GPIO2 configured as output
in
Page 0, Reg 25-25h
GPIOCTL0
y
6
ar
Register Address
el
im
0
Pr
Table 130. GPIOCTL0 Register
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Portable Audio Consumer Codec
6.6.2.2.GPIO Control 1 Register
Register Address
Page 0, Reg 26-26h
GPIOCTL1
Bit
Label
Type
Default
Description
7
GPIO3
RW
0
Register bit that is driven onto the GPIO3 pin
6
GPIO2
RW
0
Register bit that is driven onto the GPIO2 pin
5
GPIO1
RW
0
Register bit that is driven onto the GPIO1 pin
4
GPIO0
RW
0
Register bit that is driven onto the GPIO0 pin
3
GPIO3RD
R
0
Reports the state of the GPIO3 pin
2
GPIO2RD
R
0
Reports the state of the GPIO2 pin
1
GPIO1RD
R
0
Reports the state of the GPIO1 pin
0
GPIO0RD
R
0
Reports the state of the GPIO0 pin
6.7.
ar
y
Table 131. GPIOCTL1 Register
Register Reset
Reset Register
im
in
The TSCS454 registers may be reset to their default values using the reset register. Writing a special, non-zero value to
this register causes all other registers to assume their default states. Device status bits will not necessarily change their values depending on the state of the device.
Bit
Label
Page 0, Reg 1-01h
RESET
7:0
Reset[7:0]
Type
Default
Description
RW
00h
Reset register
Writing a value of 85h will cause registers to assume
their default values. Reading this register returns 00h
el
Register Address
Pr
Table 132. RESET Register
6.8.
Interrupts
6.8.1
nINT/nTEST - Interrupt/Test Pin
The nINT interrupt pin is an open drain, active low, output that indicates a number of error conditions or chip states. The
BTNDET, HDSINT, HDPNINT, EEND and CKSUM status bits are cleared by either issuing a RESET or by writing any value
to the Interrupt Status Register.
When the nINT/nTEST is held low when the nRESET pin transitions high the device will enter TESTMODE operation.
6.8.2 Interrupt Logic
The interrupt generation logic consists of a interrupt enable/disable control, an interrupt mask control, and a interrupt
status/clear mechanism.
Each interrupt may be “Enabled/disabled” by the corresponding interrupt enable control bit located in the Interrupt Enable
Register.
Each interrupt can be “Masked” from generating an interrupt on the IRQ pin by the corresponding interrupt mask bit located
in the Interrupt Mask Register.
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Portable Audio Consumer Codec
Each interrupt can be “Cleared” bit writing a “one” to the corresponding interrupt status bit located in the Interrupt Status
Register.
VDD
INT EVENT
S
INT CLR
R
SET
CLR
Q
IRQ PIN
Q
INT ENABLE
INT MASK
INT EVENT
S
INT CLR
R
SET
CLR
Q
Q
INT ENABLE
S
INT CLR
R
SET
CLR
Q
Q
ar
INT EVENT
y
INT MASK
INT ENABLE
in
INT MASK
6.8.3 Interrupt Sources
im
6.8.3.1.Thermal Protection Interrupt
el
An interrupt will be generated, if enabled, whenever the ACS42201C device detects an over temperature condition. The
THERMTS register can then be read to determine the thermal status.
6.8.3.2.Headphone/Headset Detection Interrupts
Pr
An interrupt can be generated by due to headphone and headset detection, or a headset button push
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6.8.4.
Interrupt Control Registers
6.8.4.1.Interrupt Enable Register
Type
Default
Description
7
RSVD
R
0
Reserved
6
THRMINTEN
RW
0
Thermal (Over Temp) Detect Interrupt Enable
0 = Interrupt Disabled
1 = Interrupt Enabled
5
HBPINTEN
RW
0
Headset Button Push Detect Interrupt Enable
4
HSDINTEN
RW
0
Headset Detected Interrupt Enable
0 = Interrupt Disabled
1 = Interrupt Enabled
3
HPDINTEN
RW
0
Headphone Detected Interrupt Enable
0 = Interrupt Disabled
1 = Interrupt Enabled
2
RSVD
R
0
Reserved
1
GPIO3INTEN
RW
0
1
GPIO2INTEN
RW
ar
y
Label
GPIO 3 Interrupt Enable
0 = Interrupt Disabled
1 = Interrupt Enabled
GPIO 2 Interrupt Enable
0 = Interrupt Disabled
1 = Interrupt Enabled
0
im
Page 0, Reg 2-2h
IRQEN
Bit
in
Register Address
Pr
el
Table 133. IRQEN Register
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Portable Audio Consumer Codec
6.8.4.2.Interrupt Mask Register
Type
Default
Description
7
RSVD
R
0
Reserved
6
THRMIM
RW
0
Thermal (Over Temp) Detect Interrupt Mask
0 = Interrupt Disabled
1 = Interrupt Enabled
5
HBPIM
RW
0
Button Push Detect Interrupt Mask
4
HDDIM
RW
0
Headset Detection Interrupt Mask
0 = Interrupt Disabled
1 = Interrupt Enabled
3
HDPIM
RW
0
Headphone Detection Interrupt Mask
0 = Interrupt Disabled
1 = Interrupt Enabled
2
RSVD
R
0
Reserved
1
GPIO3M
RW
0
GPIO 3 Interrupt Mask
0 = Interrupt Disabled
1 = Interrupt Enabled
0
GPIO2M
RW
0
y
Label
ar
Page 0, Reg 3-3h
IRQMASK
Bit
GPIO 2 Interrupt Mask
0 = Interrupt Disabled
1 = Interrupt Enabled
in
Register Address
im
Table 134. IRQMASK Register
6.8.4.3.Interrupt Status Register
All interrupts are cleared by writing a one to the interrupt specific bits in this register.
Bit
Type
Default
RSVD
R
1
Reserved
THRMIS
RW
0
Over Temperature Detect Interrupt Status
5
HBPINT
RW
0
Headset Button Push Detect Interrupt Status
This is an “OR” of the Long and Short button push
detect logic
4
HSDINT
RW
0
Headset Detected Interrupt Status
3
HDPINT
RW
0
Headphone Detected Interrupt Status
2
RSVD
R
0
Reserved
1
GPIO3INT
RW
0
GPIO 3 Interrupt Status
0
GPIO2INT
RW
0
GPIO 2 Interrupt Status
7
Page 0, Reg 4-4h
IRQSTAT
Pr
6
Label
el
Register Address
Description
Table 135. IRQSTAT Register
6.9.
Reset Pin
The Reset pin resets all internal registers to their default states and put the TSCS454 into it’s lowest power state. While the
Reset pin is held active the TSCS454 should consume zero power.
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Portable Audio Consumer Codec
7. CLOCK GENERATION
The TSCS454 uses two PLL’s to generate two high frequency reference clocks. The clock frequencies of each reference
clock are based on multiples of 44.1KHz and 48KHz sample rates.The clock source for the PLL’s can be the XTAL input,
MCLK1 input via the XTAL_IN pin, the MCLK2 pin, or one of the I2S interface BCLK inputs. Each PLL can be independently
powered down if the audio sample rates generated by that particular PLL are not required.
7.1.
On-Chip PLLs
The TSCS454 generates two high-quality, high-frequency clocks122.880MHz and 112.896MHz. The PLL’s support a wide
range of input clock frequencies. Some typical frequencies are 19.2Mhz, 22MHz, 22.5792MHz, 24MHz, 24.576 MHz,
27MHz, and 36MHz. It should be noted that some input clock frequencies may not result in being able to generate the
122.880MHz and 112.896Mhz clocks exactly resulting in an error in the audio sample rate.
Audio Clocks - Each PLL generates one of two clock frequencies based on two audio sample rates.
y
122.880 MHz (2560 x 48 KHz)
112.896 MHz (2560 x 44.1 KHz)
ar
It is important that the crystal oscillator and needed PLLs remain on until all audio functions, including jack detection, are
disabled.
Reference
Divider
P
H
A
S
E
VCO
el
Input
Clock
im
in
For supporting System Master Clock (MCLK OUT) generation a 22.5792MHz,24.576MHz, or the PLL2 output may be
selected to be output on the MCLK2 pin. This low jitter high frequency clock also can be used to drive external audio
sources. The MCLK2 output frequency is limited to 50MHz. The MCLK2 pin can also be configured to input a high frequency clock from an external oscillator or other external clock source.
Feedback
Divider
Output
Divider
Output
Clock
Pr
PLL
Figure 31. System Clock Diagram
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Portable Audio Consumer Codec
Clock or Crystal Input
(22.5792M, 24.576M, 27M,
36M)
MCLK1
X1
XTAL OSC/
Clock Buffer
M
U
X
X2
Optional tuning
caps
PLL1
122.88MHz
PLL2
112.896MHz
BCLK1
BCLK2
BCLK3
/5
M
U
X
/2
/5
/3
/2
Internal Clock Generator
24.576MHz
M
U
X
56.448MHz
BR
44.1KHz
48KHz
22.5792MHz
40.960MHz
EN
61.44 MHz
/640
ar
24.576MHz
24.000MHz
12.288MHz
12.000MHz
22.5792MHz
16.384MHz
11.2896MHz
8.192MHz
/1
/2
/4
/8
INTERNAL
BIT CLK
y
MCLK2
A1BCM
(32fs)
(40fs
(64fs)
INTERNAL
LR CLK
Base Rate
Multiplier
11.025KHz
12KHz
22.050KHz
24KHz
44.1KHz
48KHz
88.2KHz
96KHz
I2S Master Clock Generator X 3
INTERNAL
BIT CLK
el
im
in
BR
44.1KHz
48KHz
A1BCM
(32fs)
(40fs
(64fs)
/1
/2
A1BCM
(32fs)
(40fs
(64fs)
/640
/1
/2
/4
/8
INTERNAL
LR CLK
Base Rate
Multiplier
INTERNAL
BIT CLK
/192
/136
/128
/125
/1
/2
/4
/8
11.025KHz
12KHz
22.050KHz
24KHz
44.1KHz
48KHz
88.2KHz
96KHz
Pr
Base Rate
Multiplier
INTERNAL
LR CLK
11.025KHz
12KHz
22.050KHz
24KHz
44.1KHz
48KHz
88.2KHz
96KHz
Figure 32. Clock Generation Diagram
7.2.
System Clock Generation
The TSCS454 supports an internal clock and audio sample rate that is selectable between 11.025KHz, 12 KHz,
22.050KHz, 24KHz, 44.1KHz, 48KHz, 88.2KHz, and 96KHz. ASRC’s are used to sample rate convert the external audio
source timing to the specified internal rate. Three bi-directional stereo I2S interfaces are available. Each I2S interface may
operate as a slave or as a timing master. Separate input and output ASRC’s are used. In Slave mode each ASRC will rate
detect the incoming audio sample rate and adjust the ASRC automatically. In Master mode an internal timing generator is
used to specify the audio sample rate. The sample rate specified in Master mode is independent from the internal clock
rate.and the specified range is 8KHz to 96KHz. A variety of sample rates based on 44.1K, 48K and 32K are supported. A
highly programmable PLL enables just about any input frequency to be used.
7.2.1 PLL Dividers
The chosen input frequency is multiplied up by the PLL’s to generate the required output frequencies; 122.88MHz and
112.896MHz. It should be noted that it may not always be possible to generate the required output frequencies with zero
error. Some values for the PLL dividers relative a specific input frequency are shown in the table below.
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TSCS454
Portable Audio Consumer Codec
Output Frequency
PLL1 - 122.88MHz
PLL2 - 112.896MHz
Reference
Divider
Feedback
Divider
Output
Divider
Freq
Error
ppm
VCO
(MHz)
Freq
Reference
Divider
Feedback
Divider
Output
Divider
Freq
Error
ppm
VCO
Freq
(MHz)
1.4112
N/A
N/A
N/A
N/A
N/A
4
960
3
0
338.688
1.536
2
480
3
0
368.64
2
441
3
0
338.688
2.8224
N/A
N/A
N/A
N/A
N/A
3
360
3
0
338.688
3.072
7
840
3
0
368.64
7
1029
4
0
451.584
5.6448
N/A
N/A
N/A
N/A
N/A
6.144
5
300
3
0
368.64
12
25
768
3
0
19.2
20
384
3
22
55
1536
5
22.5792
49
800
24
25
384
24.576
29
435
25
55
811
27
45
1024
5
36
25
256
2
y
Input
Frequency
(MHz)
840
3
0
338.688
8
441
3
0
338.688
368.64
25
1176
5
0
564.48
0
368.64
25
441
3
0
338.688
0
614.4
38
585
3
-11.887
338.684
im
in
ar
14
0
368.64
29
435
3
0
338.688
3
0
368.64
25
588
5
0
564.48
3
0
368.64
24
441
4
0
451.584
3
-9.864
368.64
42
569
3
7.3111
338.688
0
614.4
125
1568
3
0
338.688
PD=
210Khz
0
368.64
125
1176
3
0
338.688
PD=
280Khz
Pr
el
3
Table 136. Typical PLL Divider Values
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Portable Audio Consumer Codec
LRCLK#/BCLK#
ICLK
GEN
DIV
2
2
ADC
/DMIC
PORT#
CLK
GEN
ASRC
ar
M
U
X
S
O
U
R
C
E
SDIN1
SDIN2
Pr
el
im
in
SDIN3
S
E
L
E
C
T
M
U
X
SDOUT1
M
U
X
SDOUT2
M
U
X
SDOUT3
Output
Processor
SPKR AMP
y
MCLK1
MCLK2 PLL1 CLK1
BCLK
CLK2
PLL2
XTAL
ASRC
S
W
I
T
C
H
Output
Processor
Output
Processor
DAC
DAC
SUB
HP
Figure 33. Simplified System Clock Block Diagram
The ADC internal processing blocks, DAC internal processing, Digital Mixer, input timing of the output ASRC’s and output
timing of the input ASRC’s run at the ICLK (internal clock) rate. The sample rate of the audio source input to and out of the
ASRC’s is independent from the internal sample rate. The function of the ASCR’s is to sample rate convert the incoming
and outgoing audio to the fixed internal sample rate as defined by ICLK defined clock rate.
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7.2.1.1. PLL Status Register
Register Address
Page 0 , Reg 10 - Ah
PLLSTAT
Bit
Label
Type
Default
Description
7:2
RSVD
R
00h
1
PLL2LK
R
0
1 = PLL2 has obtained lock
0
PLL1LK
R
0
1 = PLL1 has obtained lock
Reserved
Table 137. PLLSTAT Register
7.2.1.2.PLL1 Control Register
Label
Type
Default
Description
7
RSVD
R
0
Reserved
6:5
VCCI_PLL1
RW
1h
PLL1 voo/ico current setting
4:3
RZ_PLL1
RW
2h
PLL1 Zero R setting
2:0
CP_PLL1
RW
3h
PLL1 main charge pump current setting
ar
Page 0, Reg 11 - Bh
PLL1CTL
Bit
y
Register Address
Table 138. PLL1CTL Register
Bit
Label
Type
Page 0, Reg 12 - Ch
PLL1RDIV
7:0
REFDIV_PLL1
RW
Default
19h
Description
im
Register Address
in
7.2.1.3.PLL1 Reference Clock Divider Register
PLL1 refclk divider
Table 139. PLL1RDIV Register
Page 0, Reg 13 - Dh
PLL1ODIV
Bit
Label
Type
Pr
Register Address
el
7.2.1.4.PLL1 Output Divider Register
7:0
OUTDIV_PLL1
RW
Default
03h
Description
PLL1 output divider
Table 140. PPL1ODIV Register
7.2.1.5.PLL1 Feedback Divider Low Register
Register Address
Bit
Label
Type
Default
Page 0, Reg 14 - Eh
PLL1FDIVL
7:0
FBDIVL_PLL1
RW
80h
Description
PLL1 feedback divider
Table 141. PLL1FDIVL Register
7.2.1.6.PLL1 Feedback Divider High Register
Register Address
Bit
Label
Type
Default
Description
Page 0, Reg 15 - Fh
PLL1FDIVH
7:4
RSVD
R
0
Reserved
3:0
FBDIVH_PLL1
RW
1h
PLL1 feedback divider
Table 142. PLL1FDIVH Register
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Portable Audio Consumer Codec
7.2.1.7.PLL2 Control Register
Register Address
Bit
Label
Type
Default
Description
Page 0, Reg 16 - 10h
PLL2CTL
7:6
VCCI_PLL2
RW
0
PLL2 voo/ico current setting
5:3
RZ_PLL2
RW
1h
PLL2 Zero R setting
2:0
CP_PLL2
RW
6h
PLL2 main charge pump current setting
Table 143. PLL2CTL Register
7.2.1.8. PLL2 Reference Clock Divider Register
Bit
Label
Type
Default
Page 0, Reg 17 - 11h
PLL2RDIV
7:0
REFDIV_PLL2
RW
19h
Description
y
Register Address
ar
PLL2 reference clock divider
7.2.1.9.PLL2 Output Divider Register
Bit
Label
Type
Page 0, Reg 18 - 12h
PLL2ODIV
7:0
OUTDIV_PLL2
RW
Default
05h
Description
im
Register Address
in
Table 144. PLL2RDIV Register
PLL2 output divider
Table 145. PLL2ODIV Register
Page 0, Reg 19 - 13h
PLL2FDIVL
Bit
Label
Type
Pr
Register Address
el
7.2.1.10.PLL2 Feedback Divider Low Register
7:0
FBDIVL_PLL2
RW
Default
4ch
Description
PLL2 feedback low divider
Table 146. PLL2FDIVL Register
7.2.1.11.PLL2 Feedback Divider High Register
Register Address
Bit
Label
Type
Default
Description
Page 0, Reg 20 - 14h
PLL2FDIVH
7:4
RSVD
R
0
Reserved
3:0
FBDIVH_PLL2
RW
2h
PLL2 feedback high divider
Table 147. PLL2FDIVH Register
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Portable Audio Consumer Codec
7.2.1.12.PLL Control Register
Label
Type
Default
7
PU_PLL2
RW
0
Power Up PLL 2
1 = Power Up
0 = Power Down
6
PU_PLL1
RW
0
Power Up PLL 1
1 = Power Up
0 = Power Down
5
EN_PLL2
RW
0
Enable output of PLL 2
1 = Enable Output
0 = Disable Output
4
EN_PLL1
RW
0
Enable output of PLL 1
1 = Enable Output
0 = Disable Output
BCLKSEL
00h
PLLISEL
RW
0
im
1:0
RW
BCLK Input Select For PLL when PLLISEL = 11
00 = BCLK1
01 = BCLK2
10 = BCLK3
11= reserved
y
3:2
Description
ar
Page 0, Reg 21 - 15h
PLLCTL
Bit
Selects XTAL, MCLK1,MCLK2, I2S BCLK as PLL
input
00 = XTAL selected as PLL input
01 = MCLK1 selected as PLL input
10 = MCLK2 selected as PLL input
11 = BCLK selected as PLL input
in
Register Address
Table 148. PLLCTL Register
el
7.2.2 PLL Power Down Control
Pr
Each PLL can be powered down to save power if only one set of base audio rates is required. The base audio rates are
defined as 44.1KHz based rates or 48KHz based rates. If support for either 44.1KHz or 48KHz based rates is not needed
then the PLL associated with the unused rate can be powered down.
7.2.3 Audio Clock Generation
Figure 33 shows the simplified block diagram. The TSCS454 utilizes internal PLLs to generate the PLL clocks at 112.896 MHz
(22.5792MHz *5) and122.880 MHz (24.576 *5). Intermediate clocks (61.44MHz, 40.96MHz, 56.448MHz) are then generated which are then used to generate the audio sample rates. There is one internal clock rate that can be specified to operate at 11.025KHz, 12 KHz, 22.050KHz, 24KHz, 44.1KHz, 48KHz,88.2KHz, and 96KHz. When changing sample rates a
delay of up to 5mS may be needed for the part to properly lock PLLs, flush filters, etc.
7.2.3.1.PLL Clock Source
The clock source for the PLL’s can be selected from the XTAL input, MCLK1 input via the XTAL_IN pin, the MCLK2 pin or
one of the I2S BCLK inputs via a selectable mux.
7.2.3.2. Internal Sample Rate Control Register
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Portable Audio Consumer Codec
This register defines the internal sample rate.
Register Address
Bit
Label
Default
7:3
RSVD
00h
2
IBR
1
Page 0, Reg 22 - 16h
ISRC
1:0
Description
Reserved
ICLK Internal Base Rate
0 = 44.1KHz
1 = 48KHz
ICLK Internal Base Rate Multiplier
00 = 0.25
01 = 0.5
10 = 1x
11 = 2x
IBM
Table 149. ISRC Register
xBM [1:0]
BASE RATE
00
1
11.025kHz(MCLK/5120)
01
56.448MHz
22.050kHz(MCLK/2560)
44.1 kHz (MCLK/1280)
11
88.2 kHz (MCLK/640)
00
22kHz(MCLK/5120)
in
10
im
0
SAMPLE RATE
ar
IBR
y
Internal Sample Rates
01
61.44 MHz
10
48 kHz (MCLK/1280)
96 kHz (MCLK/640)
Pr
el
11
24kHz(MCLK/2560)
7.2.3.3. MCLK2 Pin
The MCLK2 pin can be configured to be an input or an output. When configured as an input it can provide a clock to drive
the input to the PLL’s or or the I2S Master Mode clock generators. When the MCLK2 pin is configured as an output it can
provide either a 22.5792MHz, 24.576MHz, clock or when driven by PLL2 just about any desired clock frequency as can be
programmed by the PLL2 registers.
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Portable Audio Consumer Codec
MCLK2 Pin Control Register
Register Address
Page 0, Reg 33-21h
MCLK2PINC
Bit
Label
Type
Default
7:4
SLEWOUT[3:0]
RW
1000b
3
RSVD
R
0
Reserved
2
MCLK2IO
RW
0
Configure MCLK2 as input or output.
0 = MCLK2 pin is an input
1 = MCLK2 pin is an output
1:0
MCLK2OS[1:0]
RW
Description
Slew rate setting for MCLK2 Output
MCLK2 Pin Output Clock Select
00 = 24.576 MHz
01 = 22.5792 MHz
10 = PLL21
11 = Reserved
01b
ar
7.2.3.4. I2S Master Mode Clock Generation
y
1.The maximum supported output frequency for MCLK2 is 50MHz
im
in
Each I2S input audio source (PCM1, PCM2, and PCM3) can operate as a timing Slave or Master. When operated in Slave
mode the ASRC will automatically detect the incoming audio sample rate and convert it to the current, internally defined,
input/output sample rate. When operated in Master Mode an internal clock generator is used to produce the required bit
and frame clocks to be driven out of the LRCLK and BCLK pins of each input I2S interface. The clock source for the I2S
master clock generation can be selected between the PLL generated internal timing or an externally supplied clock via the
MCLK2 input.
7.2.3.5. I2S Master Mode Sample Rate Control
Pr
el
These registers set the I2S Master Mode sample rates. For normal operation the PLL1 and PLL2 outputs are used for generating the timing for the I2S ports when operating in Master Mode. Optionally the MCLK2 input may be used for generating
the timing for the I2S ports when operating in Master Mode. External MCLK timing mode is selected when the MBR[1:0]
bits are set to 11. In this mode the MCLK/2 and MCLKDIV[1:0] bits become active. The MBM[2:0] bits are also active in this
mode. The I2SxMBR bits set the base audio sample to be either 44.1Khz or 48KHz. The I2SxMBM bits are then used to set
the base rate multiplier ratio. When the MCLK2 input is selected as a clocks source for the I2S Master Mode clock generation the I2SxMCLK/2 and I2SxMCLKDIV[1:0] bits are used to divide down the MCLK2 input to the desired audio sample
rate.
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Portable Audio Consumer Codec
7.2.3.6.
Bit
Label
Default
7
I2SxMCLK/2
0
MCLK2 Pre-Divide
0 = MCLK2 divide = 1
1 = MCLK2 divide = 2
0
MCLK2 Mode Divide. When MBR[1:0] = 11
00 = 125
01 = 128
10 = 136
11 = 192
6:5
4:3
I2SxMBR[1:0]
10
Base Rate
00 = reserved
01 = 44.1KHz
10 = 48KHz
11 = External MCLK Mode - MCLK2 input used for I2S
master mode clock
2
RSVD
0
Reserved
I2SxMBM[2:0]
010
Base Rate Multiplier
00 = 0.25x
01 = 0.50x
10 = 1x
11 = 2x
in
1:0
y
Page 0, Reg 29, 30, 31 1Dh, 1Eh, 1Fh
I2S1MRATE,
I2S2MRATE,
I2S3MRATE
I2SxMCLKDIV[1:0]
Description
ar
Register Address
I2S MasterMode Control Registers
im
Table 150. I2S1MRATE, I2S2MRATE, I2S3MRATE Register
Note: 1 x=1,2,3
Bit
Label
Description
BCLKxSTAT
0
I2Sx BClk Loss Status, Slave Mode (Clear by writing1):
0 = BClk not lost; 1 = BClk loss detected
BCLKPx
0
I2Sx BClk Polarity: 0 = Not inverted; 1 = Inverted
5
PORT1MS
0
I2Sx Master/Slave Selection: 0 = Slave; 1 = Master
4
LRCLKP1
0
I2Sx LRClk Polarity: 0 = Not inverted; 1 = Inverted
3:2
WLx1[1:0]
10
I2Sx Word Length: 0h = 16 bits; 1h = 20 bits; 2h = 24
bits; 3h = 32 bits
1:0
FORMATx[1:0]
10
I2Sx Format: 0h = Right justified; 1h = Left justified; 2h
= I2S format; 3h = TDM mode
7
Pr
6
Page 0, Reg 26, 30, 31 1Ah, 1Bh, 1Ch
I2SP1CTL, I2SP2CTL,
I2SP3CTL
Default
el
Register Address
Table 151. I2SP1CTL, I2SP2CTL, I2SP3CTL Register
Note: 1 x=1,2,3
127
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TSCS454
Portable Audio Consumer Codec
The table below shows the typical I2S Master Mode Audio Sample Rates when using the MCLK2 input as the
input clock source.
MCLKDIV[1:0]
128
24.576
/2
192
MBM [2:0]
SAMPLE RATE(KHz)
ERROR
000
12
0
001
24
0
010
48
0
011
96
0
000
8
0
001
16
0
010
32
0
64
0
12
0
24
0
010
48
0
011
96
0
000
8
0
001
16
0
010
32
0
011
64
0
000
12
0
001
24
0
010
48
0
011
96
0
000
11.0294
.04%
001
22.0588
.04%
010
44.1176
.04%
011
88.235
.04%
011
000
001
Pr
el
192
im
/1
in
128
12.288
y
MCLK/2
ar
MCLK2(MHZ)
125
24.000
/2
136
128
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TSCS454
Portable Audio Consumer Codec
MCLKDIV[1:0]
125
12.000
/1
135
22.5792
/2
128
MBM [2:0]
SAMPLE RATE(KHz)
ERROR
000
12
0
001
24
0
010
48
0
011
96
0
000
11.0294
.04%
001
22.0588
.04%
010
44.1176
.04%
011
88.235
.04%
000
11.025
0
001
22.050
0
010
44.1
0
88.2
0
11.025
0
22.050
0
010
44.1
0
011
88.2
0
000
8.0
0
001
16.0
0
010
32.0
0
011
64.0
0
011
000
in
001
128
/2
128
Pr
el
16.384
/1
im
11.2896
y
MCLK/2
ar
MCLK2(MHZ)
129
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Portable Audio Consumer Codec
7.2.3.7. DAC/ADC Clock Control
The power consumption and audio quality may be adjusted by changing the converter modulator rate. By default the DAC
and ADC Sigma-Delta modulators run at a high rate for the best audio quality. The modulator rates for the converters may
be forced to run at half their nominal rate to conserve power. A third option allows the modulator rate to automatically drop
to half rate when low sampling rates are chosen (1/2 or 1/4 the base rate.) The DACs and ADCs are independently cocotrolled.
Register Address
Bit
7:6
Label
Type
ASDM[1:0]
Default
RW
Description
10h
ADC Modulator Rate
00 = Reserved
01 = Half
10 = Full
11 = Auto
DAC Modulator Rate
00 = Reserved
01 = Half
10 = Full
11 = Auto
DSDM[1:0]
RW
10h
3:0
RSVD
R
0
Reserved
ar
5:4
y
Page 0, Reg 24 - 18h
SCLKCTL
Table 152. SCLKCTL Register
BM [2:0]
00
NA
Modulator Rate
im
DSDM[1:0]
ASDM[1:0]
in
ADC and DAC Modulator Rates
Reserved
000 (1/4x)
001 (1/2x)
010 (1x)
Pr
011 (2x)
Half
el
01
000 (1/4x)
10
001 (1/2x)
010 (1x)
Full
011 (2x)
11
000 (1/4x)
Auto (Half)
001 (1/2x)
Auto (Half)
010 (1x)
Auto (Full)
011 (2x)
Auto (Full)
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Portable Audio Consumer Codec
7.2.3.8.TMBASE - Timebase Register
Register Address
Bit
Label
Type
Default
Page 0, Reg 27 - 19h
TMBASE
7-0
TIMEBASE[7:0]
RW
2F
Description
Internal Time Base Divider. This value should be
programmed as [round(ref clock/256000)]-1
Pr
el
im
in
ar
y
Table 153. TMBASE Register
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Portable Audio Consumer Codec
8. HEADPHONE AND COMBO JACK DETECTION
The TSCS454 supports headphone/headset detection, button press detection, and OMTP/CTIA type Headsets. The
TSCS454 can be programmed to generate an interrupt when headphone/headset insert/removal or a button press is
sensed. In addition when headphone insertion is detected, the TSCS454 can automatically disable the speaker outputs
and enable the headphone outputs.
8.1.
Headphone Switch and Plug Insertion Detection
The HPDET pin is used to detect connection of a headphone when this pin is connected to a isolated or non-isolated switch
located inside the headphone jack. Alternately a non-switch detection mode is provided to support jack types without
switches.
ar
y
A 4 conductor (combo) jack with switch is typically used to support this feature in conjunction with the Headphone Detect
(HPDET) pin. In the most common implementation, the 4 conductor plug has the same mechanical dimensions as a 3
conductor 3.5mm plug, but the sleeve portion has been split into two segments:S1 and S2. When a 4-conductor plug
(headset) is inserted into the jack T (Tip) = Left headphone audio, R (Ring) = Right headphone audio, S1 (First half of
sleeve) = microphone input, and S2 (Second half of sleeve) = return (GND). When a 3-conductor plug (headphones) is
inserted into the jack; T (Tip) = Left audio, R (Ring) = Right audio, S1(sleeve) = return (GND). By monitoring the S1
connection to see if it is shorted to ground, we can distinguish between headsets and headphones. Please note that analog
microphone plugs (3-conductor-Lmic/Rmic/GND) and optical SPDIF plugs are not supported.
in
3-Conductor Plug, no MIC
Right Headphone
Ground
im
TRS – Tip, Ring, Sleeve
Left Headphone
el
Nokia (OMTP) Plug Type
4-Conductor Plug
TRRS – Tip, Ring 1, Ring 2, Sleeve
Pr
Left Headphone
Right Headphone
Microphone
Ground
Apple (CTIA) - Plug Type)
4-Conductor Plug
Left Headphone
TRRS – Tip, Ring 1, Ring 2, Sleeve
Right Headphone
Ground
Microphone
Figure 34. Headphone/Headset Plug Types
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Portable Audio Consumer Codec
Requirements
Available pins include a Headphone detect pin (HPDET), Microphone Detect pin (MICDET), MICBIAS outputs, and analog
line inputs.
Supports headphone output connections to Tip and Ring 1.
Supports TRS and TRRS plug types.
Plug insertion is reported on the headphone port using the switch integrated into the jack or by sensing the presence of
signals that occur when a plug is inserted into a jack. The jack characteristics have a direct impact on what can be sensed
thus a summary of various jack types and configurations will need to be provided.
The existing circuit monitors the voltage at various points on the jack to determine if a microphone is present on the Ring 2
or Sleeve. Both OMTP and CTIA plug types must be supported.
The non-microphone sensed Ring 2 or Sleeve connection must be connected to ground with minimal impedance.
Detection of a microphone is not reported unless plug insertion is also detected.
Provision should be made for preventing false detection by debouncing the headphone and microphone detection.
ar
y
MIcrophone Bias output generator. Software may disable the MIC bias output to conserve power if the presence of a
microphone is not detected.
Pr
el
im
in
Pops should be minimized when upon plug insertion/removal or when detecting the presence of a microphone.
.
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8.2
Microphone Detection
The TSCS454 supports detection of a microphone located on the “Sleeve” or Ring2 connection of a TRRS jack. The
detection can be programmed to automatically control the MICBIAS, analog input selection, and ground switches or these
can be controlled manually through register bits.
A
D
C
ar
INPUT
MUX
A
D
C
y
INPUT
MUX
Sleeve_Sense
in
MIC_BIAS
el
im
Ring2_Sense
Sleeve
Ring2
Pr
Control
S2
S1
GND
Figure 35. Example OMTP/CTIA Headset Detection Diagram
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Portable Audio Consumer Codec
8.2.1 De-Glitch
To prevent anomalous plug insertion detect readings, a de-glitch circuit is provided. This logic circuit monitors the presence
signal from the headset detection module (analog) for a transition (both positive and negative edges). The presence signal
is considered valid if it remains stable for longer than a delay defined by the parameter T_STABLE. T_STABLE may be
programmed as described in the table below.
Duration of de-glitch window
000
64ms
001
128ms
010
256ms(default)
011
512ms
100
1s
101
2s
110
4s
111
8s
ar
y
T_STABLE [3:0]
Note: Assumes correct timebase settings
in
The detection result status bit is updated when the de-glitch circuitry has determined the impedance state is stable.If the
de-glitch circuitry has determined that the impedance state is not stable then the headset presence bit will not be set.
8.2.2 Plug Insertion Before Headset Detection Is Enabled
Pr
el
im
Before Headset detection is enabled, the presence of a headphone inserted into the jack is determined by the HP_DET
input. If a headphone is present when power is applied to the CODEC or if the CODEC is returning from a low power state,
the CODEC will not detect a change in state and would normally not attempt to detect a microphone.To prevent this
problem, the CODEC will automatically start a microphone detection cycle when Headset detection is enabled if the
presence of the HP_DET detect true.
Headset _ detect_en
Headset_Insertion
Headset_Removal
Headset_Removed
_
Headphone Plug
Insertion Detected
Plug Removal
Detected
T_Stable (De-Glitch Period)
Plug Removal
Detected Valid
Plug Insertion
Detected Valid
T_Stable (De-Glitch Period)
Figure 36. Headset present in jack when Combo-jack detection is enabled
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Portable Audio Consumer Codec
The following diagrams show the connections to different headset jack configurations.
LIN1
LIN2
LIN3
LINE/MIC
INPUTS
RIN1
RIN2
RIN3
Sleeve
M
U
X
TIP
Ring
Ring 2
ADC
M
U
X
ADC
2.5V
2.1V
1.8V
MICVDD
y
MICBIAS2
TIP
M
U
X
M
U
X
ar
SLEEVE
in
RING2
im
S2
HP DET
el
HP Out L
S1
2.5V
2.1V
1.8V
MICVDD
DETECT
LOGIC
GND
DAC
(Cap-less)
Pr
HP Out R
DAC
Figure 37. Pin Connection Diagram for 5 Terminal OMTP/CTIA Headset Support
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Portable Audio Consumer Codec
LIN1
LIN2
LIN3
LINE/MIC
INPUTS
RIN1
RIN2
RIN3
Sleeve
M
U
X
TIP
Ring
Ring 2
ADC
M
U
X
ADC
2.5V
2.1V
1.8V
MICVDD
y
MICBIAS2
M
U
X
MICBIAS1
M
U
X
ar
SLEEVE
MICBIAS1
in
RING2
im
S2
HPDET
el
HP Out L
S1
2.5V
2.1V
1.8V
MICVDD
DETECT
LOGIC
GND
DAC
(Cap-less)
Pr
HP Out R
DAC
Figure 38. Pin Connection Diagram for 4 Terminal OMTP/CTIA Headset Support with isolated switch
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Portable Audio Consumer Codec
LIN1
LIN2
LIN3
LINE/MIC
INPUTS
RIN1
RIN2
RIN3
Sleeve
M
U
X
MICBIAS2
TIP
M
U
X
ADC
2.5V
2.1V
1.8V
MICVDD
M
U
X
in
ar
SLEEVE
RING2
SW
ADC
y
Ring
Ring 2
M
U
X
im
S2
HP DET
el
HP Out L
S1
2.5V
2.1V
1.8V
MICVDD
DETECT
LOGIC
GND
DAC
(Cap-less)
Pr
HP Out R
DAC
Figure 39. Pin Connection Diagram for 3 Terminal with isolated switch
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Portable Audio Consumer Codec
LIN1
LIN2
LIN3
LINE/MIC
INPUTS
RIN1
RIN2
RIN3
M
U
X
ADC
M
U
X
ADC
2.5V
2.1V
1.8V
MICVDD
y
MICBIAS2
M
U
X
M
U
X
ar
SLEEVE
in
RING2
S1
DETECT
LOGIC
im
S2
2.5V
2.1V
1.8V
MICVDD
HP DET
DAC
el
HP Out L
GND
(Cap-less)
Pr
HP Out R
DAC
Figure 40. Pin Connection Diagram using internal MIc’s
8.2.3 Headset Type Detection and Microphone Selection Process
The process by which the headset type is detected is a follows:
•Headphone Detection and Headset Detection are enabled
•Headphone/Headset Plug insertion is detected and de-bounced
•If plug insertion is detected then the Headset Detection process is started
•The microphone is detected on either RING2 or SLEEVE
•The MICBIAS is enabled onto the microphone detected pin and the other pin is connected to GND.
•The Analog Input MUX is set to select the input that is connected to the microphone.
The process can be set to be automatic or controlled manually.
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8.2.4 Headphone/Headset Control Registers
8.2.4.1 Headphone/Headset Detection Control Register 1
Label
Type
Default
7
HPJKTYP
RW
0
Ring2/Sleeve ground connection for 3-terminal plug.
0 = Mode 0, normal operation
1 = Mode 1, Ring2 remains off for 3-terminal plug
6
CONDETPWD
RW
1
Connection Detection Powerdown
0 = GHS connection detection analog circuitry on
1 = GHS connection detection analog circuitry off
RW
10b
3
HPDLYBYP
RW
0
0
Headphone plug insertion detect delay bypass
0 = Headphone plug detect delay enabled
1 = Headphone plug detect delay bypassed
Polarity for headset detect trigger
0 = headset detection triggered on low to high
transition of HP_DET pin.
1 = headset detection triggered on high to low
transition of HP_DET pin
2
HSDETPOL
1
HPID_EN
RW
0
Headphone Plug Insertion Detect Enable
0 = Plug Insertion detect disabled
1 = Plug Insertion detect enabled
0
GBLHS_EN
RW
0
OMTP, CTIA Headset Detect Enable
0 = OMTP, CTIA Headset support disabled
1 = OMTP, CTIA headset support enabled
in
RW
y
DETCYC[1:0]
Number of consecutive matching Cycles for detection
00 = 1
01 = 2
10 = 3(default)
11 = 4
ar
5:4
Description
im
Page 1, Reg 1-1h
HSDCTL1
Bit
el
Register Address
Pr
Table 154. HSDCTL1 Register
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Portable Audio Consumer Codec
8.2.4.2 Headphone/Headset Detection Control Register 2
Bit
7:6
Type
FMICBIAS1[1:0]
RW
Default
Description
00b
Force MICBIAS1 Drive to the headset jack when
MB1MODE is set to 1
00 = Off
01 = Force Mic Bias on Ring2
10 = Force Mic Bias on Sleeve
11 = Invalid (Force Mic Bias on both Ring2 and Sleeve)
5
MB1MODE
RW
0
MICBIAS1 MODE
1 = MICBIAS1 is manually configured
0 = MICBIAS1 is automatically configured by the
headset detection circuit
4
FORCETRG
RW
0
Force Detection - “0” to “1” transition forces detection.
Bit is reset to “0” after detection process ends.
3
SWMODE
RW
0
Ring 2/Sleeve/MICBIAS1 Switch Control
0 = Switching is manual
1 = Switching is automatic
2
GHSHIZ
RW
0
y
Page 1, Reg 2-2h
HSDCTL2
Label
ar
Register Address
0 = sleeve and rin2 switches enabled
1 = force sleeve and ring2 switches Hi-Z
FPLUGTYPE[1:0]
RW
00 = 4 terminal plug with mic on Ring2 (OMTP)
01 = 4 terminal plug with mic on sleeve (CTIA)
10 = Reserved (3 terminal plug)
11 = 3 terminal plug (headphone only)
11
im
1:0
in
Force Plug Type when SWMODE= 0 AND GHSHIZ = 0
Pr
el
Table 155. HSDCTL2 Register
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8.2.4.3 Headphone/Headset Detection Status Register
Label
Type
Default
Description
7
RSVD
R
0
Reserved
MBIAS1DRV[1:0]
R
00
4
RSVD
R
0
Reserved
0
Headset Detect Status - Presence of a plug in the
headset jack as reported to the detection state
machine.0 = Nothing plugged in1 = Plug inserted in
jack
Detected Headset Type
00 = OMTP
01 = CTIA
10 = Headphones (detect cycle not run)
11 = Headphones
3
HSDETSTAT
R
2:1
PLUGTYPE[1:0]
R
11
0
HSDETDONE
R
0
y
6:5
Status of MICBIAS1
00 = Off
01 = MICBIAS1 active on Ring2
10 =MICBIAS1 active on Sleeve
11 = Invalid (MICBIAS1 active on Ring2 and Sleeve)
Headset Detect Done
0 = Headset detection not started/in process
1 = Headset detection completed
in
Page 1, Reg 3-3h
HSDSTAT
Bit
ar
Register Address
im
Table 156. HSDSTAT Register
8.2.4.4 Headset Detection Delay Register
Bit
Page 1, Reg 4-4h
HSDELAY
Type
Default
R
0
RSVD
Pr
7:3
Label
el
Register Address
2:0
T_STABLE[2:0]
RW
Description
Reserved
010b
Delay for plug insertion detect
000 = 64ms
001 = 128ms
010 = 256ms(default)
011 = 512ms
100 = 1s
101 = 2s
110 = 4s
111 = 8s
Table 157. HSDELAY Register
Note: Assumes correct time base settings
8.2.5 Lanyard Switch (“Turbo Button”) Support
Many headsets that implement a 4-pin plug will provide a push-button switch. The switch may connected in parallel or in
series with the microphone signal. If the switch is connected in series then the microphone input connection will temporarily
be open circuit (high-impedance). If the switch is connected in parallel the switch will temporarily short the microphone
input to ground. The switch is typically used to support call answer, call hang-up, pause/resume, track advance or other
142
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Portable Audio Consumer Codec
functions. This switch is commonly known as a lanyard switch or “turbo button.
The Lanyard switch detection requirements are:
Support for a single switch function
Lanyard switch support can be enabled or disabled. When disabled the circuitry associated with the function should be
powered down.
The Lanyard switch button press detection is only enabled if a headset is detected.
The detection of a button press generated an interrupt
The button press detection should be de-bounced to prevent false detections.
Support for short and long button press detection should be provided.
y
H eadset _ detect_ en
ar
H eadset_ insert
M IC B IA S
H eadphone Jack
Insertion D etected
in
T _S table (D e -G litch P eriod )
el
B utton P ress E nable
B utton P ress
T _delay
im
H eadset D etected
B utton D etect S hort
Pr
P arallel S w itch - G N D
B _S T A B LE_S (D e -G litch P eriod)
B _ S T A B LE _L (D e-G litch P eriod )
B utton D etect Long
Figure 41. Lanyard Button Push Detect Diagram
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Portable Audio Consumer Codec
8.2.6 Lanyard Button Support Registers
Register Address
Bit
Label
Type
Default
Description
7
BPUSHSTAT
R
0
Button Push Status
0 = short
1 = long
6
BPUSHDET
RW
0
Button Push Detected - Cleared by writing a zero to
this register.
0 = Button push not detected
1 = Button push detected
5
BPUSHEN
RW
0
Button Push Detect Enable
0 = Button push detect disabled
1 = Button Push Detect Enabled
Page 1, Reg 5-5h
BUTCTL
RW
0
y
B_STABLE_L[1:0]
ar
4:3
Delay for button push detection long
00 = 500ms
01 = 1s
10 = 1.5s
11 = 2.0s
RW
in
B_STABLE_S[2:0]
000b
im
2:0
Delay for button push detection short
000 = 0 (OFF)
001 = 50ms
010 = 100ms
011 = 150ms
100 = 200ms
101 = 250ms
110 = 300ms
111 = 350ms
Table 158. BUTCTL Register
Pr
el
Note: Assumes correct timebase settings
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Portable Audio Consumer Codec
9. CHARACTERISTICS
9.1.
Audio Fidelity
DAC SNR: >102dB, A-Weighted, 3.3V/4.75V
ADC SNR: >95dB, A-Weighted, 3.3V/4.75V
Electrical Specifications
9.2.1.
Absolute Maximum Ratings:
Vss - 0.3V TO Vdd + 0.3V
Operating Temperature
0 oC TO 70 oC
Storage Temperature
-55 oC TO +125 oC
Soldering Temperature
260 oC
MICBias Output Current
3mA
Amplifier Maximum Supply Voltage
6 Volts = PVDD
Audio Maximum Supply Voltage
3 Volts = AVDD/CPVDD
Digital I/O Maximum Supply Voltage
3.6 Volts = DVDD_IO
Digital Core Maximum Supply Voltage
2.0 Volts = DVDD
y
Voltage on any pin relative to Ground
in
ar
9.2.
9.3.
im
Table 159. Absolute Maximum Ratings
Recommended Operating Conditions
Parameter
el
Power Supplies
DVDD_Core
Typ
1.4
Max
Unit
2.0
V
1.6
3.3
3.5
AVDD/CPVDD
1.7
1.9
2.0
PVDD
3.0
3.7
5.5
V
0
25
70
oC
150
oC
Pr
DVDD_IO
Min
Ambient Temperature
Tj
Table 160. Recommended Operating Conditions
Note: ESD: The TSCS454 codec is an ESD (Electrostatic discharge) sensitive device. Even
though the TSCS454 family implements internal ESD protection circuitry, proper ESD precautions
should be followed to avoid damaging the functionality or performance.
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9.4.
Characteristics
Test Conditions
Unless stated otherwise, DVDD_CORE=DVDD_IO=1.6V, AVDD=1.7V, PVDD=3.6V, TA=+25C, 997Hz signal, fs=48KHz, Input Gain=0dB, 24-bit audio
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Analog Inputs (LIN1, LIN2, LIN3, RIN1, RIN2, RIN3)
L/RIN1,2,3 Single Ended
0.5
-6
Vrms
dBV
L/RIN1,2,3 Differential Mic
0.5
-6
Vrms
dBV
Input Impedance
50
K
Input Capacitance
10
pF
Programmable Gain Min
0.0
dB
Programmable Gain Max
30.0
dB
10.0
dB
-17.25
dB
30.0
dB
0.75
dB
-97
dB
30.0
dB
0.5
dB
-999
dB
90
dB
-80
0.01
dB
%
90
dB
Full Scale Input Voltage
VFSIV
y
Analog Input Boost Amplifier
Programmable Gain Step Size
ar
Analog Input PGA
Programmable Gain Min
Programmable Gain Max
Guaranteed Monotonic
in
Programmable Gain Step Size
Digital Volume Control Amplifier
Programmable Gain Max
Programmable Gain Step Size
Mute Attenuation
im
Programmable Gain Min
Guaranteed Monotonic
el
Analog Inputs (LIN1/RIN1, LIN2/RIN2 Differential) to ADC
Signal To Noise Ratio
A-weighted 20-20KHz
THD+N
-1dBFS input
Pr
Total Harmonic Distortion + Noise
SNR
85
Analog Inputs (LIN1, LIN2, LIN3, RIN1, RIN2, RIN3 Single Ended) to ADC
Signal To Noise Ratio
SNR
A-weighted 20-20KHz
THD+N
-1dBFS input
-80
0.01
dB
%
ADC channel Separation
997Hz full scale signal
70
dB
Channel Matching
997Hz signal
Total Harmonic Distortion + Noise
85
2
%
DAC to Line-Out (with 10K / 50pF load)
Signal to Noise Ratio1
SNR
A-weighted
102
dB
Total Harmonic Distortion +Noise2
THD+N
997Hz full scale signal
-82
dB
Channel Separation
997Hz full scale signal
70
dB
-999
dB
RL = 10K
1.0
Vrms
RL = 16
0.8
Vrms
997Hz full scale signal, RL =
16
40
mW (avg)
Mute attenuation
Headphone Outputs (HPL, HPR)
Full Scale Output Level
Output Power
VFSOV
PO
146
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TSCS454
TSCS454
Portable Audio Consumer Codec
Parameter
Symbol
Test Conditions
Signal to Noise Ratio
SNR
A-weighted, RL = 16
102
dB
RL = 16, -3dBFS
-72
dB
RL = 16, -6dBFS
-78
dB
RL = 32, -3dBFS
-75
dB
RL = 32, -6dBFS
-80
dB
RL = 10K
1.0
Vrms
Total Harmonic Distortion +Noise
THD+N
Min
Typ
Max
Unit
Earpiece Output (SUB+, SUB-)
Full Scale Output Level
VFSOV
Output Power
Signal to Noise Ratio
RL = 16
0.8
Vrms
PO
997Hz full scale signal, RL =
16
40
mW (avg)
SNR
A-weighted, RL = 16
102
dB
RL = 16, -3dBFS
-72
dB
RL = 16, -6dBFS
-78
dB
RL = 32, -3dBFS
-75
dB
RL = 32, -6dBFS
-80
dB
Total Harmonic Distortion +Noise
ar
y
THD+N
Analog Voltage Reference Levels
V-
Microphone Bias (MICBIAS1, MICBIAS2)
Bias Voltage
VMICBIAS
Power Supply Rejection Ratio
Digital Input/Output
PSRRMICBIAS
-AVDD
+100mV
+5%
V
-
2.5
-
V
3
mA
3.3V<PVDD<5.5V
80
dB
3.0V<PVDD<3.3v
40
dB
30
MHz
Fmax
el
ADC/DAC BCLK input rate
-5%
im
BIAS current Source
in
Charge Pump Output
I2S BCLK/LRCLK ratio
32
1022
Pr
0.7x
DVDD_IO
Input High Level
VIH
Input LOW Level
VIL
Output High Level
VOH
IOH=-1mA
Output LOW Level
VOL
IOL=1mA
V
0.3xDVD
D_IO
0.9x DVDD_IO
Input Capacitance
Input Leakage
-0.9
clocks/fram
e
V
V
0.1xDVDD_IO
V
5
pF
0.9
uA
ESD / Latchup
IEC1000-4-2
1
Level
JESD22-A114-B
2
Class
JESD22-C101
4
Class
1.Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 kHz bandwidth. (AES17-1991
Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
2.THD+N ratio as defined in AES17 and outlined in AES6id,non-weighted, swept over 20 Hz to 20 kHz bandwidth.
147
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TSCS454
TSCS454
Portable Audio Consumer Codec
9.4.1.
Sample Rate
(kHz)
SNR at Sample Rates other than 48KHz
DAC SNR
(dB ratio)
ADC SNR
(dB ratio)
96
102
90
ADC SNR is a design target. Typical is listed as 90
48
102
90
ADC SNR is a design target. Typical is listed as 90
24
96
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
12
96
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
Notes
48 kHz based rates
44.1 kHz based rates
102
90
ADC SNR is a design target. Typical is listed as 90
44.1
102
90
ADC SNR is a design target. Typical is listed as 90
22.05
96
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
11.025
96
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
in
ar
y
88.2
im
32 kHz based rates
101
90
ADC SNR is a design target. Typical is listed as 90
32
101
90
ADC SNR is a design target. Typical is listed as 90
16
89
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
8
88
90
SDM at 1/2 rate. ADC SNR is a design target. Typical
is listed as 90
Pr
el
64
148
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TSCS454
TSCS454
Portable Audio Consumer Codec
9.5.
PLL Section DC Electrical Characteristics
Unless stated otherwise, DVDD_Core=1.8V -0.1V/+0.2V, Ambient Temp -10C to +80C
Symbol
Test Conditions
Operating Voltage
DVDD_CORE
Supply Current
IDVDD_CORE(PLL)
Input High Level
VIH
Input LOW Level
VIL
Output High Level
VOH
IOH=-2mA
Output LOW Level
VOL
IOL=2mA
Min
Typ
Max
1.7
1.8
2.0
V
11
15
mA
No Load, VDD=1.9V
Unit
0.7x
DVDD_CORE
V
0.3xDVDD_CORE
0.8x
DVDD_CORE
0.2xDVDD_CORE
V
TBD
pF
5
Input Capacitance
CIN
Load Capacitance, X1 and X2
CL
Internal Pull-Down Resistor
RPD
All clock outputs
Internal Pull-Up Resistor
RPU
All pins with pull-up or
pull-down
V
V
pF
TBD
TBD
75
250
k
50
k
y
Parameter
9.6.
ar
Table 161. PLL Section DC Characteristics
PLL Section AC Timing Specs
Parameter
Symbol
fIN
Output Rise Time
Output Fall Time
Typ
Max
Unit
TBD
TBD
TBD
MHz
20% to 80%1
1.1
2.2
3.3
ns
tOF
20%1
1.1
2.2
3.3
ns
33
46
68
W
45
50
55
%
45
50
55
%
RO
80% to
VO=VDD/2
VDD/2, 19.2MHz
Frequency Synthesis Error
1
VDD/21
All Outputs
Pr
Cycle to cycle Jitter
(all outputs)
Min
tOR
el
Output Impedance
Output Clock Duty Cycle
Test Conditions
im
Input Frequency
in
Unless stated otherwise, DVDD_Core=1.8V -0.1V/+0.2V, Ambient Temp -10C to +80C
0
250
ppm
300
ps
750
ps
4
ms
Output Enable Time
20
ns
Output Disable Time
20
ns
Long Term Jitter (all outputs)
n=1000
Power Up Time
From minimum VDD to
outputs stable
1.Measured with a 5pF load.
tPU
Table 162. PLL Section AC Characteristics
149
©2014 TEMPO SEMICONDUCTOR, INC.
1.5
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TSCS454
TSCS454
Portable Audio Consumer Codec
9.7.
Typical Power Consumption
DVDD_IO
PVDD
DVDD_CORE
(V)
(V)
Mode
AVDD
(V)
Playback to
Headphone
only
1.7
3.0
Record only
1.7
3.0
IDVDD_I IDVDD_CO
PTOTAL
O
RE
(mW)
(mA)
(mA)
IAVDD
(mA)
IPVDD
(mA)
1.7
TBD
TBD
TBD
TBD
4
1.7
TBD
TBD
TBD
TBD
TBD
Notes
Full scale 1Vrms/10Kohm, does not
include PLL/clock buffer section.
fs=48kHz, stereo.
Full scale 500mVrms; does not
include PLL/clock buffer section.
fs=48kHz, stereo.
Table 163. Typical Power Consumption
Low Power Mode Power Consumption
Record only
1.7
3.0
1.7
Record only
1.7
3.0
1.7
IAVDD
(mA)
IPVDD
(mA)
IDVDD_I IDVDD_CO
PTOTAL
O
RE
(mW)
(mA)
(mA)
in
AVDD
(V)
Notes
y
DVDD_IO
PVDD
DVDD_CORE
(V)
(V)
Mode
TBD
Full scale 500mVrms; does not
include PLL/clock buffer section.
fs=48kHz, stereo.
TBD
Full scale 500mVrms; does not
include PLL/clock buffer section.
fs=8kHz, stereo.
ar
9.8.
im
Table 164. Low power mode power consumption
Pr
el
Low Power Settings
1) DAC/ADC modulators set to half rate
2) Constant Output Power function disabled
3) All unused functions disabled (for example, Input PGA, Input mux, and ADC disabled for playback
tests)
6) PLL block power consumption not included
150
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TSCS454
TSCS454
Portable Audio Consumer Codec
10. REGISTER MAP SUMMARY TABLE
Table 165. Register Map
Register
(D15:9)
Name
Remarks
R0 (00h)
PAGESEL
Page Select
PAGESEL[7:0]
R1 (01h)
RESET
RESET
RESET[7:0]
R2 (02h)
IRQEN
IRQ Mask
RSVD
Page 0
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Default
Reset/Control/Device Setup/PLL/Clocking/ASRC
THRMINTEN
HBPINTEN
HSDINTEN
00h
77h
HPDINTEN
RSVD
GPIO3INTEN GPIO2INTEN
00h
R3 (03h)
IRQMASK
IRQ Mask
RSVD
THRMIM
HBPIM
HSDIM
HPDIM
RSVD
GPIO3IM
GPIO2IM
R4 (04h)
IRQSTAT
IRQ Status
RSVD
THRMINT
HBPINT
HSDINT
HPDINT
RSVD
GPIO3INT
GPIO2INT
00
R6(06h)
DEVADD0
Device Address 0
RSVD
68h
R8(08h)
DEVID
Device ID 0
R9(09h)
DEVREV
Device Revision
DEV_ADD0[6:0]
00h
DEV_ID[7:0]
40h
MAJ_REV[3:0]
MIN_REV[3:0]
R10(0Ah)
PLLSTAT
PLL Status
R11(0Bh)
PLL1CTL
PLL1 Control
R12(0Ch)
PLL1RDIV
PlL1 Ref Divider
REFDIV_PLL1[7:0]
R13(0Dh)
PLL1ODIV
PLL1 Output Divider
OUTDIV_PLL1[7:0]
03h
R14(0Eh)
PLL1FDIVL
PLL1 FBDBK Divider Low
FBDIVL_PLL1[7:0]
80h
R15(0Fh)
PLL1FDIVH
PLL1 FBDBK Divider High
R16(10h)
PLL2CTL
PLL2 Control
R17(11h)h
PLL2RDIV
PlL2 Ref Divider
R20(14h)
PLL1FDIVH
PLL2 FBDBK Divider High
R21(15h)
PLLCTL
PLL Control
R22(16h)
ISRC
Internal Sample rate
R24(18h)
SCLKCTL
System Clock Control
R25(19h)
TMBASE
Time Base
PU_PLL1
PU_PLL2
RSVD
PLL2CLKEN
BCLK1STAT
1
BCLK1P
BCLK3P
PORT3MS
LRCLKP3
WL3[1:0]
FORMAT3[1:0]
0Ah
I2S2MRATE
I2S Port 2 Sample Rate
I2S2MCLKH
ALF
I2S2MCLKDIV[1:0]
R30(1Eh)
I2S3MRATE
I2S Port 3 Sample Rate
I2S3MCLKH
ALF
I2S3MCLKDIV[1:0]
R31(1Fh)
R32(20h)
I2SCMC
I2S Ports Clock Mode
R33(21h)
MCLK2PINC
MCLK2 Pin Control
R34(22h)
I2SPINC0
PCM Pin Control 0
R35(23h)
I2SPINC1
PCM Pin Control 1
R36(24h)
I2SPINC2
PCM Pin Control 2
R37(25h)
GPIOCTL0
GPIO Control 0
GPIO3INTP
R38(26h)
GPIOCTL1
GPIO Control 1
Pr
el
I2S1MCLKDIV[1:0]
PCM Port 2 Control 1
RSVD
I2S1MBR[1:0]
RSVD
I2S1MBM[2:0]
12h
I2S2MBR[1:0]
RSVD
I2S2MBM[2:0]
12h
I2S3MBR[1:0]
RSVD
I2S3MBM[2:0]
12h
BCMP3[1:0]
BCMP2[1:0]
SLEWOUT[3:0]
SDO2TRI
SDO1TRI
RSVD
RSVD
RSVD
RSVD
RSVD
MCLK2IO
BCMP1[1:0]
12h
MCLK2OS[1:0]
81h
PCM3TRI
PCM2TRI
PCM1TRI
E0h
SDO3PDD
SDO2PDD
SDO1PDD
00h
LR3PDD
BC3PDD
LR2PDD
BC2PDD
LR1PDD
BC1PDD
00h
GPIO2INTP
GPIO3CFG
GPIO2CFG
GPIO3IO
GPIO2IO
GPIO1IO
GPIO0IO
00h
GPIO3
GPIO2
GPIO1
GPIO0
GPIO3RD
GPIO1RD
GPIO0RD
00h
ASRCOBW
ASRCIBW
ASRCOB
SLSYNC
BDELAY
00h
RSVD
TDMSO[2:0]
TDMMD
TDMDSS
RSVD
RSVD
PCMMOMP2
PCMSOP2
GPIO2RD
00h
RSVD
151
©2014 TEMPO SEMICONDUCTOR, INC.
61h
0Ah
I2S1MCLKH
ALF
PCMP2CTL1
TIMEBASE[7:0]
FORMAT2[1:0]
I2S Port 1 Sample Rate
R48(30h)
A0h
WL2[1:0]
I2S1MRATE
TDM Control 1
12h
RSVD
LRCLKP2
R29(1Dh)
PCM Port 2 Control 0
IBM[1:0]
IBR
DSDM[1:0]
00h
PORT2MS
BCLK3STAT
3
SDO3TRI
02h
PLLISEL
BCLK2P
I2S Port 3 Control
TDMCTL1
BCLKSEL
0Ah
I2SP3CTL
PCMP2CTL0
FBDIVH_PLL2[3:0]
PLL1CLKEN
FORMAT1[1:0]
R28(1Ch)
R47(2Fh)
4Ch
WL1[1:0]
BCLK2STAT
2
R46(2Eh)
05h
FBDIVL_PLL2[7:0]
LRCLKP1
I2S Port 2 Control
ASRC Control
9B
19h
PORT1MS
I2SP2CTL
TDM Control 0
01h
CP_PLL2[2:0]
OUTDIV_PLL2[7:0]
RSVD
ASDM[1:0]
R27(1Bh)
ASRC
FBDIVH_PLL1[3:0]
REFDIV_PLL2[7:0]
I2S Port 1 Control
TDMCTL0
93h
19h
RZ_PLL2[2:0]
I2SP1CTL
R40(28h)
00h
y
RSVD
VCCI_PLL2[1:0]
R26(1Ah)
R45(2Dh)
PLL1LK
CP_PLL1[2:0]
ar
PLL2 Output Divider
PLL2 FBDBK Divider Low
PLL2LK
RZ_PLL1[2:0]
in
PLL2ODIV
PLL2FDIVL
VCCI_PLL1[1:0]
im
R18(12h)
R19(13h)
RSVD
10h
PCMDSSP2[1:0]
RSVD
TDMSI[2:0]
21h
PCMFLENP2
SLSYNCP2
BDELAYP2
00h
RSVD
PCMMIMP2
PCMSIP2
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
Bit[7]
Bit[6]
Bit[5]
R49(31h)
PCMP3CTL0
PCM Port 3 Control 0
R50(32h)
PCMP3CTL1
PCM Port 3 Control 1
RSVD
PCMMOMP3
PCMSOP3
R51(33h)
PWRM0
Power Management 0
RSVD
INPROC3PU
INPROC2PU
R52(34h)
PWRM1
Power Management 1
SUBPU
R53(35h)
PWRM2
Power Management 2
R54(36h)
PWRM3
Power Management 3
R55(37h)
PWRM4
Power Management 4
R56(38h)
I2SIDCTL
I2S Input Data Control
R57(39h)
I2SODCTL
I2S Output Data Control
Bit[4]
Bit[2]
Bit[1]
Bit[0]
Default
PCMFLENP3
SLSYNCP3
BDELAYP3
00h
RSVD
PCMMIMP3
PCMSIP3
00h
INPROC0PU
MICB2PU
MICB1PU
MCLKPEN
00h
RSVD
HPLPU
RSVD
RSVD
BGSBUP
PCMDSSP3[1:0]
INPROC1PU
HPRPU
SPKLPU
SPKRPU
D2S2PU
D2S1PU
RSVD
00h
I2S3OPU
I2S2OPU
I2S1OPU
I2S3IPU
I2S2IPU
I2S1IPU
00h
VGBAPU
LLINEPU
RSVD
RLINEPU
OPEARPU
I2SI3DCTL
R58(3Ah)
AUDIOMUX1
ASRCOMUX
I2S2MUX
AUDIOMUX2
ASRCOMUX
DACMUX
R60(3Ch)
AUDIOMUX3
RSVD
OPSPKLPU OPSPKRPU
I2SI1DCTL
00h
I2SO2DCTL
I2SO1DCTL
00h
00h
I2S1MUX
I2S3MUX
CLSSDMUX
SUBMUX
Page 1
00h
OPHPLPU
OPHPRPU
I2SI2DCTL
I2SO3DCTL
R59(3Bh)
Capture/ADC/Input Processing
R1(01h)
HSDCTL1
Headphone/Headset
Detection Control 1
R2(02h)
HSDCTL2
Headphone/Headset
Detection Control 2
R3(03h)
HSDSTAT
Headphone/Headset
Detection Status
R4(04h)
HSDDELAY
Headphone/Headset
Detection Delay
PAGESEL[7:0]
HPJKTYPE
CONDETPWD
DETCYC[1:0]
FMICBIAS1[1:0]
RSVD
MB1MODE
HPDLYBYP
00h
HSDETPOL
FORCETRG
MBIAS1DRV[1:0]
SWMODE
RSVD
HSDETSTAT
BUTCTL
Button Control
CH0AIC
Ch0 Audio Input Control
BPUSHSTAT
INSELL[1:0]
BPUSHDET
R7(07h)
CH1AIC
CH1 Audio Input Control
INSELR[1:0]
R8(08h)
CH2AIC
CJH2 Audio Input Control
RSVD
R9(09h)
CH3AIC
CH3 Audio Input Control
R10(0Ah)
ICTL0
Input Control 0
BPUSHEN
LADCIN[1:0]
MICBST1[1:0]
RSVD
T_STABLE[2:0]
RADCIN[1:0]
RSVD
MICBST3[1:0]
RSVD
06h
02h
B_STABLE_S[2:0]
MICBST2[1:0]
60h
03h
HSDETDON
E
PLUGTYPE[1:0]
B_STABLE_L[1:0]
MICBST0[1:0]
im
R5(05h)
GBLHS_EN
FPLUGTYPE[1:0]
GHSHIZ
RSVD
R6(06h)
HPID_EN
y
Page Select
ar
PAGESEL
in
R0 (00h)
Bit[3]
00h
INHPOR
IPCH0S
00h
RSVD
IPCH1S
00h
00h
00h
IN1POL
IN0POL
INCH10SEL[1:0]
INMUTE1
INMUTE0
IN1HP
IN3POL
IN2POL
INCH32SEL[1:0]
INMUTE3
INMUTE2
IN3HP
IN0HP
0Ch
IN2HP
0Ch
R11(0Bh)
ICTL1
Input Control 1
R12(0Ch)
MICBIAS
Microphone Bias
R13(0Dh)
PGACTL0
PGA Control 0
PGA0MUTE
PGA0ZC
R14(0Eh)
PGACTL1
PGA Control 1
PGA1MUTE
PGA1ZC
PGA1VOL[5:0]
17h
R15(0Fh)
PGACTL2
PGA Control 2
PGA2MUTE
RSVD
PGA2VOL[5:0]
17h
R16(10h)
PGACTL3
PGA Control 3
PGA3MUTE
RSVD
R17(11h)
PGAZ
ICH0VOL
ICH1VOL
R20(14h)
ICH2VOL
R21(15h)
ICH3VOL
R22(16h)
ASRCIL VOL
R23(17h)
ASRCR VOL
R24(18h)
ASRCOL VOL
R25(19h)
ASRCOR VOL
MICBOV2[1:0]
RSVD
el
Pr
R18(12h)
R19(13h)
MICBOV1[1:0]
RSVD
00h
PGA0VOL[5:0]
17h
PGA3VOL[5:0]
PGA Zero Cross
17h
RSVD
INHPOR
TOEN
00h
In Channel 0 Volume
ICH0VOL[7:0]
BFh
In Channel 1 Volume
ICH1VOL[7:0]
BFh
In Channel 2 Volume
ICH2VOL[7:0]
BFh
In Channel 3 Volume
ICH3VOL[7:0]
BFh
ASRCI Left Volume
ASRCILVOL[7:0]
EFh
ASRCI Right Volume
ASRCIRVOL[7:0]
EFh
ASRCO Left Volume
ASRCOLVOL[7:0]
EFh
ASRCO Right Volume
ASRCORVOL[7:0]
EFh
RSVD
RSVD
R27(1Bh)
RSVD
RSVD
R28(1Ch)
IVOLCTLU
Input Volume Control
Update
R29(1Dh)
ALCCTL0
ALC Control 0
ALCMODE
ALCREF[2:0]
R30(1Eh)
ALCCTL1
ALC Control 1
RSVD
MAXGAIN[2:0]
ALCL[3:0]
ALCZC
MINGAIN[2:0]
HLD[3:0]
00h
ATK[3:0]
32h
R26 (1Ah)
R31(1Fh)
ALCCTL2
ALC Control 2
R32(20h)
ALCCTL3
ALC Control 3
R33(21h)
NGATE
Noise Gate
R34(22h)
DMICCTL
D-Mic Control
R35-R255
RSVD
Reserved
RSVD
IFADE
INPVOLU
PGAVOLU
ASRCVOLU
ALCEN3
ALCEN2
ALCEN1
ALCEN0
DCY[3:0]
NGTH[4:0]
DMIC2EN
DMIC1EN
RSVD
NGG[1:0]
DMONO
DMDCLK[1:0]
08h
40h
7Bh
NGAT
DMRATE[1:0]
00h
00h
Reserved
152
©2014 TEMPO SEMICONDUCTOR, INC.
BFh
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
Bit[7]
Bit[6]
R0(00h)
PAGESEL
Page Select
R1(01h)
DACCTL
DAC Control
DACPOLR
DACPOLL
RSVD
R2(02h)
SPKRCTL
Speaker Control
SPKPOLR
SPKPOLL
RSVD
R3(03h)
SUBCTL
SUB Control
SUBPOL
RSVD
SUBDCBYP
SPKDCVBY
P
Page 2
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
DACMUTE
DACDEM
RSVD
ABYPASS
SPKMUTE
SPKDEM
SUBMUTE
SUBDEM
Default
Playback Output Control
R4(04h)
DCCTL
DC Offset Control 1
R5(05h)
RSVD
Reserved
R6(06h)
OVOLCTLU
Output Volume Control
Update
R7(07h)
MUTEC
Mute Control
R8(08h)
MVOLL
Master Volume Left
PAGESEL[7:0]
DACDCBYP
00h
RSVD
08h
RSVD
SUBMUX
08h
SUBILIMDIS
DCCOEFSEL[2:0]
05h
RSVD
RSVD
ZDSTAT
OFADE
RSVD
ZDLEN[1:0]
08h
00h
SUBVOLU
MVOLU
RSVD
AMUTE
SPKVOLU
HPVOLU
08h
RSVD
22h
MVOL_L(7:0)
FFh
MVOL_R(70)
FFh
R9(09h)
MVOLR
Master Volume Right
R10(0Ah)
HPVOLL
HP Volume Left
RSVD
HPVOL_L(6:0)
R11(0Bh)
HPLOLR
HP Volume Right
RSVD
HPVOL_R(6:0)
77h
R12(0Ch)
SPKVOLL
Speaker Volume Left
RSVD
SPKVOL_L(6:0)
6Fh
R13(0Dh)
SPKVOLR
Speaker Volume Right
RSVD
R14(0Eh)
RSVD
Reserved
R15(0Fh)
RSVD
Reserved
R16(10h)
SUBVOL
SUB Volume
RSVD
R17(11h)
COP0
Constant Output Power 0
COPATTEN
COPGAIN
y
77h
SPKVOL_R(6:0)
6Fh
ar
RSVD
00h
RSVD
00h
SUBVOL(6:0)
COP1
Constant Output Power 1
RSVD
R19 (13h)
COPSTAT
Constant Output
Power Status
HDELTADET
UV
COPTARGETt[4:0]
AVGLENGTH[3:0]
MONRATE[1:0]
02h
COPADJ[5:0
PWM Control 0
PWM Control 1
R22 (16h)
PWM2
PWM Control 2
R23(17h)
PWM3
PWM Control 3
R24(18h)
HPSW
Headphone Switch
R25(19h)
THERMTS
Temp Sensor Control
TRIPHS
TRIPLS
TRIPSPLIT[1:0]
TRIPSHIFT[1:0]
TSPOLL[1:0]
09h
R26(1Ah)
THERMSPK1
Speaker Thermal Algorithm
Control
FORCEPWD
INSTCUTMOD
E
INCRATIO[1:0]
INCSTEP[1:0]
DECSTEP[1:0]
81h
Thermal Status
FPWDS
CLSDF[:1:0]
00h
R29(1Dh)
SDMON
R30-R255
RSVD
Page 3
PWMMUX[1:0]
Short Circuit Status
Supply Monitoring
BFORDER
SDFORCE
NSSEL
QUANTSEL
DITHRNG
DITHDIS
00h
RSVD
PWMMODE
61h
HPSWPOL
TSDEN
CVALUE[5:0]
RSVD
el
SCSTAT
BFDIS
DITHPOS[4:0]
DVALUE{5:0]
Pr
THERMTS
im
PWM0
PWM1
RSVD
ROUNDUP
00h
R20 (14h)
R27(1Bh)
UVLO
08h
R21 (15h)
R28(1Ch)
SCTO[1:0]
HDELTAEN
in
R18(12h)
HDCOMPMO
DE
6Fh
HPSWEN
0Ah
00h
VOLSTAT[6:0]
RSVD
ESDF[1:0]
RSVD
08h
CPF
SDVALUE[4:0]
Reserved
D4h
00h
Reserved
Speaker Output Processing
R0(00h)
PAGESEL
Page Select
R1(01h)
SPKEQFILT
SPK Eq Filter Control
PAGESEL[7:0]
R2(02h)
SPKCRWDL
SPK Coeff Write Data L
WDATA_L[7:0]
00h
R3(03h)
SPKCRDWM
SPK Coeff Write Data M
WDATA_M[15:8]
00h
EQ2EN
EQ2BE[2:0]
00h
EQ1EN
EQ1BE{2:0]
00h
R4(04)
SPKCRWDH
SPK Coeff Write Data H
WDATA_H[23:16]
00h
R5(05h)
SPKCRRDL
SPK CoefF Read Data L
RDATA_L[7:0]
00h
R6(06h)
SPKCRRDM
SPKBCoefF Read Data M
RDATA_M[15:8]
00h
R7(07h)
SPKCRRDH
SPK CoefF Read Data H
RDATA_H[23:16]
00h
R8(08h)
SPKCRADD
SPK Coeff RAM Address
ADDRESS[7:0]
R9(09h)
SPKCRS
SPK Coeff RAM Status
SPKCOEFR
R10(0Ah)
SPKMBCEN
SPK Multi-band Comp En
R11(0Bh)
SPKMBCCTL
SPK Multi-band Comp CTL
RSVD
LVLMODE3
R12(0Ch)
SPKMBCMUG
1
SPK Multi-band
Compressor Make Up Gain
Band 1
RSVD
PHASE
RSVD
153
©2014 TEMPO SEMICONDUCTOR, INC.
00h
RSVD
WINSEL3
LVLMODE2
00h
MBCPEN3
SMBCPEN2
MBCPEN1
00h
WINSEL2
LVLMODE1
WINSEL1
00h
MUGAIN[4:0]
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R13(0Dh)
SPKMBCTHR1
SPK Multi-band
Compressor Threshold
Band 1
R14(0Eh)
SPKMBCRAT1‘
SPK Multi-band
Compressor Ratio Band 1
R15(0Fh)
SPKMBCATK1
L
SPK Multi-band Comp
Attack time const Low Band
1
TCATKL[7:0]
00h
R16(10h)
SPKMBCATK1
H
SPK Multi-band Comp
Attack time const High Band
1
TCATKH1[7:0]
00h
R17(11h)
SPKMBCREL1
L
SPK Multi-band Comp
release time const Low
Band 1
TCRELL[7:0]
00h
R18(12h)
SPKMBCREL1
H
SPK Multi-band Comp
release time const High
Band 1
TCRELH[7:0]
00h
R19(13h)
SPKMBCMUG
2
SPK Multi-band
Compressor Make Up Gain
Band 2
R20(14h)
SPKMBCTHR2
SPK Multi-band
Compressor Threshold
Band 2
R21(15h)
SPKMBCRAT2‘
SPK Multi-band
Compressor Ratio Band 2
R22(16h)
SPKMBCATK2
L
SPK Multi-band Comp
Attack time const Low Band
2
R23(17h)
SPKMBCATK2
H
SPK Multi-band Comp
Attack time const High Band
2
R24(18h)
SPKMBCREL2
L
SPK Multi-band Comp
release time const Low
Band 2
R25(19h)
SPKMBCREL3
2H
SPK Multi-band Comp
release time const High
Band 2
R26(1Ah)
SPKMBCMUG
3
SPK Multi-band
Compressor Make Up Gain
Band 3
R27(1Bh)
SPKMBCTHR3
SPK Multi-band
Compressor Threshold
Band 3
R28(1Ch)
SPKMBCRAT3
SPK Multi-band
Compressor Ratio Band 3
R29(1Dh)
SPKMBCATK3
L
SPK Multi-band Comp
Attack time const Low Band
3
TCATKL[7:0]
00h
R30(11h)
SPKMBCATK3
H
SPK Multi-band Comp
Attack time const High Band
3
TCATKH1[7:0]
00h
R31(1Eh)
SPKMBCREL3
L
SPK Multi-band Comp
release time const Low
Band 3
TCRELL[7:0]
00h
R32(20h)
SPKMBCREL3
H
SPK Multi-band Comp
release time const High
Band 3
TCRELH[7:0]
00h
R33(21h)
SPKCLECTL
SPK Comp Limiter CTL
RSVD
SPKCLEMUG
SPK Compressor Make Up
Gain
RSVD
R34(22h)
Bit[7]
Bit[6]
SPKCOMPRAT
SPK Compressor Ratio
R37(25h)
SPKCOMPATK
L
SPK Comp Attack time
const Low
Bit[2]
Bit[1]
Bit[0]
00h
MUGAIN[4:0]
PHASE
00h
y
RSVD
00h
ar
THRESH[7:0]
RSVD
RATIO1[4:0]
00h
00h
im
in
TCATKL[7:0]
RSVD
Default
00h
RATIO1[4:0]
TCATKH1[7:0]
00h
TCRELL[7:0]
00h
TCRELH[7:0]
00h
MUGAIN[4:0]
PHASE
00h
THRESH[7:0]
RSVD
00h
RATIO1[4:0]
LVLMODE
WINSEL
EXPEN
MUGAIN[4:0]
THRESH[7:0]
RSVD
TCATKL[7:0]
00h
LIMIEN
COMPEN
00h
00h
00h
RATIO1[4:0]
154
©2014 TEMPO SEMICONDUCTOR, INC.
Bit[3]
RSVD
el
SPKCOMPTHR SPK Compressor Threshold
Bit[4]
THRESH[7:0]
Pr
R35(23h)
R36(24h)
Bit[5]
00h
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R38(26h)
SPKCOMATKH
SPK Comp Attack time
const High
TCATKH1[7:0]
00h
R39(27h)
SPKCOMPREL
L
SPK Comp release time
const Low
TCRELL[7:0]
00h
R40(28h)
SPKCOMPREL
H
SPK Comp release time
const High
TCRELH[7:0]
00h
R41(29h)
SPKLIMTHR
SPK Limiter Threshold
THRESH[7:0]
00h
R42(2Ah)
SPKLIMTGT
SPK Limiter Target
TARGET[7:0]
00h
R43(2Bh)
SPKLIMATKL
SPK Limiter Attack time
constant Low
TCATKLL[7:0]
00h
R44(2Ch)
SPKLIMATKH
SPK Limiter Attack time
constant High
TCATKH[7:0]
00h
R45(2Dh)
SPKLIMRELL
SPK Limiter Release time
constant Low
TCRELL[7:0]
00h
R46(2Eh)
SPKLIMRELH
SPK Limiter Release time
constant High
TCRELH[7:0]
00h
R47(2Fh)
SPKEXPTHR
SPK Expander Threshold
THRESH[7:0]
00h
R48(30h)
SPKEXPRAT
SPK Expander Ratio
RATIO[7:0]
00h
R49(31h)
SPKEXPATKL
SPK Expander Attack time
constant Low
TCATKL[7:0]
00h
R50(32h)
SPKEXPATKH
SPK Expander Attack time
constant High
R51(33h)
SPKEXPRELL
SPK Expander Release time
constant Low
R52(34h)
SPKEXPRELH
SPK Expander Release time
constant High
R53(35h)
SPKFXCTL
SPK Effects Control
R54-R255
RSVD
Reserved
R0(00h)
PAGESEL
Page Select
R1(01h)
DACEQFILT
DAC Eq Filter Control
R2(02h)
DACCRWDL
DAC Coeff Write Data L
R3(03h)
DACCRWDM
DAC Coeff Write Data M
R4(04)
DACCRWDH
DAC Coeff Write Data H
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Default
ar
y
Bit[6]
TCATKH[7:0]
00h
TCRELL[7:0]
00h
TCRELH[7:0]
00h
in
RSVD
3DEN
TBEN
TNLFBYP
BEEN
BNLFBYP
00h
im
RSVD
DAC/Headphone Output Processing
EQ2EN
PAGESEL[7:0]
EQ2BE[2:0]
el
Page 4
Bit[7]
00h
EQ1EN
EQ1BE{2:0]
00h
WDATA_L[7:0]
00h
WDATA_M[15:8]
00h
WDATA_H[23:16]
00h
DACCRRDL
DAC CoefF Read Data L
RDATA_L[7:0]
00h
DACCRRDM
DAC CoefF Read Data M
RDATA_M[15:8]
00h
R7(07h)
DACCRRDH
DAC CoefF Read Data H
RDATA_H[23:16]
00h
R8(08h)
DACCRADD
DAC Coeff RAM Address
ADDRESS[7:0]
00h
Pr
R5(05h)
R6(06h)
R9(09h)
DACCRS
R10(0Ah)
DACMBCEN
DAC Coeff RAM Status
SPKCOEFR
RSVD
R11(0Bh)
DACMBCCTL
DAC Multi-band Comp CT2
RSVD
LVLMODE3
R12(0Ch)
DACMBCMUG
1
DAC Multi-band
Compressor Make Up Gain
Band 1
RSVD
PHASE
R13(0Dh)
DACMBCTHR1
DAC Multi-band
Compressor Threshold
Band 1
R14(0Eh)
DACMBCRAT1
DAC Multi-band
Compressor Ratio Band 1
R15(0Fh)
DACMBCATK1
L
DAC Multi-band Comp
Attack time const Low Band
1
TCATKL[7:0]
00h
R16(10h)
DACMBCATK1
H
DAC Multi-band Comp
Attack time const High Band
1
TCATKH1[7:0]
00h
R17(11h)
DACMBCREL1
L
DAC Multi-band Comp
release time const Low
Band 1
TCRELL[7:0]
00h
DAC Multi-band Comp En
RSVD
LVLMODE2
SMBCPEN2
MBCPEN1
00h
WINSEL2
LVLMODE1
WINSEL1
00h
MUGAIN[4:0]
THRESH[7:0]
RSVD
00h
00h
RATIO1[4:0]
155
©2014 TEMPO SEMICONDUCTOR, INC.
WINSEL3
00h
MBCPEN3
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R18(12h)
DACMBCREL1
H
DAC Multi-band Comp
release time const High
Band 1
R19(13h)
DACMBCMUG
2
DAC Multi-band
Compressor Make Up Gain
Band 2
R20(14h)
DACMBCTHR2
DAC Multi-band
Compressor Threshold
Band 2
R21(15h)
DACMBCPAT2‘
DAC Multi-band
Compressor Ratio Band 2
R22(16h)
DACMBCATK2
L
DAC Multi-band Comp
Attack time const Low Band
2
TCATKL[7:0]
00h
R23(17h)
DACMBCATK2
H
DAC Multi-band Comp
Attack time const High Band
2
TCATKH1[7:0]
00h
R24(18h)
DACMBCREL2
L
DAC Multi-band Comp
release time const Low
Band 2
TCRELL[7:0]
00h
R25(19h)
DACMBCREL3
H
DAC Multi-band Comp
release time const High
Band 2
R26(1Ah)
DACMBCMUG
3
DAC Multi-band
Compressor Make Up Gain
Band 3
R27(1Bh)
DACMBCTHR3
DAC Multi-band
Compressor Threshold
Band 3
R28(1Ch)
DACMBCRAT3
DAC Multi-band
Compressor Ratio Band 3
R29(1Dh)
DACMBCATK3
L
DAC Multi-band Comp
Attack time const Low Band
3
R30(1Eh)
DACMBCATK3
H
DAC Multi-band Comp
Attack time const High Band
3
R31(1Eh)
DACMBCREL3
L
R32(20h)
DACMBCREL3
H
R33(21h)
DACCLECTL
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
TCRELH[7:0]
RSVD
00h
MUGAIN[4:0]
PHASE
00h
THRESH[7:0]
00h
RATIO1[4:0]
00h
y
RSVD
00h
ar
TCRELH[7:0]
RSVD
MUGAIN[4:0]
PHASE
00h
in
THRESH[7:0]
im
RSVD
Default
00h
RATIO1[4:0]
00h
00h
TCATKH1[7:0]
00h
DAC Multi-band Comp
release time const Low
Band 3
TCRELL[7:0]
00h
DAC Multi-band Comp
release time const High
Band 3
TCRELH[7:0]
00h
Pr
el
TCATKL[7:0]
DAC Comp Limiter CTL
RSVD
DAC Compressor Make Up
Gain
RSVD
LVLMODE
WINSEL
EXPEN
MUGAIN[4:0]
LIMIEN
COMPEN
00h
R34(22h)
DACCLEMUG
R35(23h)
DACCOMPTH
R
DAC Compressor Threshold
R36(24h)
DACCOMPRAT
DAC Compressor Ratio
R37(25h)
DACCOMPATK
L
DAC Comp Attack time
const Low
TCATKL[7:0]
00h
R38(26h)
DACCOMPATK
H
DAC Comp Attack time
const High
TCATKH1[7:0]
00h
R39(27h)
DACCOMPREL
L
DAC Comp release time
const Low
TCRELL[7:0]
00h
R40(28h)
DACCMPRELH
DAC Comp release time
const High
TCRELH[7:0]
00h
R41(29h)
DACLIMTHR
DAC Limiter Threshold
THRESH[7:0]
00h
R42(2Ah)
DACLIMTGT
DAC Limiter Target
TARGET[7:0]
00h
R43(2Bh)
DACLIMATKL
DAC Limiter Attack time
constant Low
TCATKLL[7:0]
00h
R44(2Ch)
DACLIMATKH
DAC Limiter Attack time
constant High
TCATKH[7:0]
00h
THRESH[7:0]
RSVD
00h
RATIO1[4:0]
156
©2014 TEMPO SEMICONDUCTOR, INC.
00h
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R45(2Dh)
DACLIMRELL
DAC Limiter Release time
constant Low
TCRELL[7:0]
00h
R46(2Eh)
DACLIMRELH
DAC Limiter Release time
constant High
TCRELH[7:0]
00h
R47(2Fh)
DACEXPTHR
DAC Expander Threshold
THRESH[7:0]
00h
R48(30h)
DACEXPRAT
DAC Expander Ratio
RATIO[7:0]
00h
R49(31h)
DACEXPATKL
DAC Expander Attack time
constant Low
TCATKL[7:0]
00h
R50(32h)
DACEXPATKH
DAC Expander Attack time
constant High
TCATKH[7:0]
00h
R51(34h)
DACEXPRELL
DAC Expander Release
time constant Low
TCRELL[7:0]
00h
R52(34h)
DACEXPRELH
DAC Expander Release
time constant High
TCRELH[7:0]
00h
R53(35h)
DACFXCTL
DAC Effects Control
R0(00h)
PAGESEL
Page Select
R1(01h)
SUBEQFILT
SUB Eq Filter Control
R2(02h)
SUBCRWDL
SUB Coeff Write Data L
R3(03h)
SUBCRWDM
SUB Coeff Write Data M
R4(04)
SUBCRWDH
SUB Coeff Write Data H
R5(05h)
SUBCRRDL
SUB CoefF Read Data L
R6(06h)
SUBCRRDM
SUB CoefF Read Data M
R7(07h)
SUBCRRDH
SUB CoefF Read Data H
R8(08h)
SUBCRADD
SUB Coeff RAM Address
R9(09h)
SUBCRS
SUB Coeff RAM Status
Bit[7]
Bit[6]
Bit[5]
RSVD
Page 5
Bit[4]
3DEN
Bit[3]
TBEN
Bit[2]
TNLFBYP
Bit[1]
BEEN
Bit[0]
Default
BNLFBYP
00h
SUB Output Processing
PAGESEL[7:0]
00h
EQ1EN
y
EQ2BE[2:0]
EQ1BE{2:0]
00h
WDATA_L[7:0]
00h
WDATA_M[15:8]
00h
ar
EQ2EN
WDATA_H[23:16]
00h
RDATA_L[7:0]
00h
in
RDATA_M[15:8]
00h
RDATA_H[23:16]
00h
ADDRESS[7:0]
SPKCOEFR
00h
RSVD
R10(0Ah)
SUBMBCEN
SUB Multi-band Comp En
R11(0Bh)
SUBMBCCTL
SUB Multi-band Comp CTL
R12(0Ch)
SUBMBCMUG
1
SUB Multi-band
Compressor Make Up Gain
Band 1
R13(0Dh)
SUBMBCTHR1
SUB Multi-band
Compressor Threshold
Band 1
R14(0Eh)
SUBMBCRAT1‘
SUB Multi-band
Compressor Ratio Band 1
R15(0Fh)
SUBMBCATK1
L
SUB Multi-band Comp
Attack time const Low Band
1
TCATKL[7:0]
00h
R16(10h)
SUBMBCATK1
H
SUB Multi-band Comp
Attack time const High Band
1
TCATKH1[7:0]
00h
R17(11h)
SUBMBCREL1
L
SUB Multi-band Comp
release time const Low
Band 1
TCRELL[7:0]
00h
R18(12h)
SUBMBCREL1
H
SUB Multi-band Comp
release time const High
Band 1
TCRELH[7:0]
00h
R19(13h)
SUBMBCUMG
2
SUB Multi-band
Compressor Make Up Gain
Band 2
R20(14h)
SUBMBCTHR2
SUB Multi-band
Compressor Threshold
Band 2
R21(15h)
SUBMBCRAT2‘
SUB Multi-band
Compressor Ratio Band 2
R22(16h)
SUBMBCATK2
L
SUB Multi-band Comp
Attack time const Low Band
2
im
RSVD
00h
LVLMODE3
RSVD
PHASE
el
RSVD
LVLMODE2
SMBCPEN2
MBCPEN1
00h
WINSEL2
LVLMODE1
WINSEL1
00h
SUBMBCPG1[4:0]
PHASE
MUGAIN[4:0]
THRESH[7:0]
RSVD
00h
00h
00h
RATIO1[4:0]
TCATKL[7:0]
00h
00h
RATIO1[4:0]
Pr
RSVD
RSVD
MBCPEN3
THRESH[7:0]
157
©2014 TEMPO SEMICONDUCTOR, INC.
WINSEL3
00h
00h
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R23(17h)
SUBMBCATK2
H
SUB Multi-band Comp
Attack time const High Band
2
TCATKH1[7:0]
00h
R24(18h)
SUBMBCREL2
L
SUB Multi-band Comp
release time const Low
Band 2
TCRELL[7:0]
00h
R25(19h)
SUBMBCREL2
H
SUB Multi-band Comp
release time const High
Band 2
TCRELH[7:0]
00h
R26(1Ah)
SUBMBCMUG
3
SUB Multi-band
Compressor Make Up Gain
Band 3
R27(1Bh)
SUBMBCTHR3
SUB Multi-band
Compressor Threshold
Band 3
R28(1Ch)
SUBMBCRAT3
SUB Multi-band
Compressor Ratio Band 3
R29(1Dh)
SUBMBCATK3
L
SUB Multi-band Comp
Attack time const Low Band
3
R30(1Eh)
SUBMBCATK3
H
SUB Multi-band Comp
Attack time const High Band
3
R31(1Eh)
SUBMBCREL3
L
SUB Multi-band Comp
release time const Low
Band 3
R32(20h)
SUBMBCREL3
H
SUB Multi-band Comp
release time const High
Band 3
R33(21h)
SUBCLECTL
SUB Comp Limiter CTL
RSVD
R34(22h)
SUBCLEMUG
SUB Compressor Make Up
Gain
RSVD
R35(23h)
SUBCOMPTH
R
SUB Compressor Threshold
R36(24h)
SUBCOMPRAT
SUB Compressor Ratio
R37(25h)
SUBCOMPATK
L
SUB Comp Attack time
const Low
R38(26h)
SUBCOMPATK
H
R39(27h)
Bit[7]
Bit[6]
RSVD
Bit[5]
Bit[4]
Bit[3]
PHASE
Bit[2]
Bit[1]
Bit[0]
MUGAIN[4:0]
00h
THRESH[7:0]
RSVD
00h
RATIO1[4:0]
00h
00h
y
TCATKL[7:0]
00h
ar
TCATKH1[7:0]
00h
TCRELH[7:0]
00h
in
TCRELL[7:0]
LVLMODE
im
Default
WINSEL
EXPEN
MUGAIN[4:0]
THRESH[7:0]
RSVD
LIMIEN
COMPEN
00h
00h
00h
RATIO1[4:0]
00h
00h
SUB Comp Attack time
const High
TCATKH1[7:0]
00h
SUBCOMPREL
L
SUB Comp release time
const Low
TCRELL[7:0]
00h
R40(28h)
SUBCOMPREL
H
SUB Comp release time
const High
TCRELH[7:0]
00h
SUB Limiter Threshold
THRESH[7:0]
00h
SUB Limiter Target
TARGET[7:0]
00h
Pr
el
TCATKL[7:0]
R41(29h)
SUBLIMTHR
R42(2Ah)
SUBLIMTGT
R43(2Bh)
SUBLIMATKL
SUB Limiter Attack time
constant Low
TCATKLL[7:0]
00h
R44(2Ch)
SUBLIMATKH
SUB Limiter Attack time
constant High
TCATKH[7:0]
00h
R45(2Dh)
SUBLIMRELL
SUB Limiter Release time
constant Low
TCRELL[7:0]
00h
R46(2Eh)
SUBLIMRELH
SUB Limiter Release time
constant High
TCRELH[7:0]
00h
R47(2Fh)
SUBEXPTH
SUB Expander Threshold
THRESH[7:0]
00h
R48(30h)
SUBSUBEXPR
AT
SUB Expander Ratio
RATIO[7:0]
00h
R49(31h)
SUBEXPATKL
SUB Expander Attack time
constant Low
TCATKL[7:0]
00h
R50(32h)
SUBEXPATKH
SUB Expander Attack time
constant High
TCATKH[7:0]
00h
R51(33h)
SUBEXPRELL
SUB Expander Release
time constant Low
TCRELL[7:0]
00h
158
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TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
Remarks
R52(34h)
SUBEXPRELH
SUB Expander Release
time constant High
R53(35h)
SUBFXCTL
SUB Effects Control
R534-R255
RSVD
Reserved
R1(01h)
ASRCCAPT
ASRC Input/Output Ratio
R2(02h)
ASRCRATIO1
INT
R3(03h)
ASRCRATIO2
FRACH
R4(04h)
ASRCRATIO3
FRACM
R5(05h)
ASRCRATIO4
FRACL
R6(10h)
DTEST0
DTEST0
R7(12h)
DTEST1
DTEST1
R8(13h)
DTEST2
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
TCRELH[7:0]
RSVD
TBEN
00h
TNLFBYP
RSVD
Page 10
Default
BEEN
BNLFBYP
00h
00h
Reserved For Future Use
ATEST1
R14(42h)
ATEST2
R15(43h)
ATEST3
R16(44h)
ATEST4
R17(45h)
ATEST5
R18(46h)
ATEST6
R19(47h)
ATEST7
R20(48h)
ATEST8
R21(49h)
ATEST9
R22(4Ah)
ATEST10
R23(4Bh)
ATEST11
R24(4Eh)
ATEST12
R25(4Fh)
ATEST13
R26(50h)
ATEST14
R27(51h)
ATEST15
R28(52h)
ATEST16
R29(53h)
ATEST17
R30(54h)
ATEST18
R31(55h)
ATEST19
R32(56h)
ATEST20
R33(57h)
ATEST21
R34(58h)
ATEST22
R35(59h)
ATEST23
R36(5Ah)
ATEST24
R37(5Bh)
ATEST25
R38(5Ch)
ATEST26
y
R13(41h)
DTEST5
ATEST0
ATEST1
ar
ATEST0
ATEST2
ATEST3
ATEST4
ATEST5
in
DTEST5
ATEST6
im
R11(16h)
R12(40h)
el
DTEST3
DTEST4
ATEST8
ATEST9
ATEST10
ATEST11
ATEST12
ATEST13
ATEST14
ATEST15
ATEST16
Pr
R9(14h)
R10(15h)
SEL
ATEST18
ATEST19
ATEST20
ATEST21
ATEST23
R39(5Dh)
ATEST27
R40(5Eh)
ATEST28
ATEST27
ATEST28
ATEST27
R41(5Fh)
ATEST29
ATEST29
R42(60h)
ATEST30
ATEST30
R43(61h)
ATEST31
R44(62h)
ATEST32
R45(63h)
ATEST33
R46(64h)
ATEST34
R47(80h)
BISTCTL
159
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TSCS454
Portable Audio Consumer Codec
Register
(D15:9)
Name
R48(84h)
BIST1CFG0
R49(89h)
BIST2CFG0
Remarks
Bit[7]
Bit[6]
DONE
ACTIVE
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
Default
RAM
R50(90h)
BIST1STAT
R51(94h)
BIST1FADDR0
ADDR0
R52(95h)
BIST1FADDR1
ADDR1
R53(98h)
BIST1FDATA0
BYTE0
R54(99h)
BIST1FDATA1
BYTE1
R55(9Ah)
BIST1FDATA2
BYTE2
R56(9Bh)
BIST1FDATA3
R57(A0h)
BIST2STAT
R58(A4h)
BIST2FADDR0
ADDR0
R59(A5h)
BIST2FADDR1
ADDR1
R60(A8h)
BIST2FDATA0
BYTE0
A61(A9h)
BIST2FDATA1
BYTE1
A61(AAh)
BIST2FDATA2
BYTE2
A62(01h)
BONDOVER
A63(02h)
FIPMUTE
BYTE3
ACTIVE
RAM
FIPMUTE1
FIPMUTE0
Pr
el
im
in
ar
FIPMUTE2
y
DONE
160
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Portable Audio Consumer Codec
11. PIN CONFIGURATION AND DESCRIPTION
35 CAP+
36 CPGND
37 CAP-
38 HP R
39 HP L
40 VNEG
41 LO R
42 LO L
43 HP DET
44 RING2
45 AVSS2
46 SLEEVE
47 AVDD2
48 VDD_MIC
49 MIC BIAS2
50 SUB +
51 SUB -
11.1. 68-Pin QFN
34 VPOS
VREF 52
33 CPVDD
AFILT L 54
32 PVDD
y
AFILT R 53
AVSS1 55
30 L-
ar
AVDD1 56
31 L+
RIN 1 57
28 PVSS
in
LIN 1 58
29 PVSS
TSCS454
(Top View)
RIN 2 59
26 R+
im
LIN 2 60
27 R-
DVSS
RIN 3 61
24 GPIO 3
el
LIN 3 62
25 PVDD
XI 63
22 GPIO 1
Pr
XO 64
23 GPIO 2
MCLK2 65
21 GPIO 0
DVDD1 66
20 DVDD2
161
©2014 TEMPO SEMICONDUCTOR, INC.
SDIN 1 17
LRCLK 1 16
BCLK 1 15
SDOUT 1 14
SDIN 2 13
LRCLK 2 12
BCLK 2 11
DVDD IO 10
SDOUT 2 9
SDIN 3 8
LRCLK 3 7
BCLK 3 6
SDOUT 3 5
DCLK 2 4
18 SCL
DMIC 2 3
DMIC 1 68
DCLK 1 2
19 SDA
nINT/TEST 1
nRESET 67
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TSCS454
TSCS454
Portable Audio Consumer Codec
POWER
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
PVDD1-3
BTL supply/Mic Bias Supply
I(Power)
-
PVSS1-3
BTL supply
I(Power)
-
DVDD_Core
Core logic+clocks
I(Power)
-
2
2
Interface (I S, I C, GPIO)
I(Power)
-
DVSS
Digital return
I(Power)
-
AVDD1-2
Analog core supply
I(Power)
-
AVDD_IO
Analog Power IO
I(Power)
-
AVSS1-2
Analog return
I(Power)
-
CPVDD
Charge pump supply
I(Power)
-
CPGND
Charge pump return
I(Power)
-
CAP+
Flying cap
(CAP-)1-2
Flying cap
V+
Positive Analog supply (Bypass cap)
(V-)
Negative Analog supply (Bypass cap)
y
DVDD_IO
-
I/O(Power)
-
O(Power)
-
O(Power)
-
in
ar
I/O(Power)
im
REFERENCE
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
2.5V 1.5 mA microphone Bias Output 1
O(Analog)
None
MICBIAS2
2.5V 1.5 mA microphone Bias Output2
O(Analog)
None
AFILT1
ADC Input Filter cap
I(Analog)
None
AFILT2
ADC Input Filter cap
I(Analog)
None
VREF
VREF reference pin (bypass)
I(Analog)
None
Pr
ANALOG INPUT
el
MICBIAS1
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
LIN1
Analog Audio Left Line/Mic Input 1
I(Analog)
None
RIN1
Analog Audio Right Line/Mic Input 1
I(Analog)
None
LIN2
Analog Audio Left Line/Mic Input 2
I(Analog)
None
RIN2
Analog Audio Right Line/Mic Input 2
I(Analog)
None
LIN3
Analog Audio Left Line/Mic Input 3
I(Analog)/
None
RIN3
Analog Audio Right Line/Mic Input 3
I(Analog)
None
162
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TSCS454
Portable Audio Consumer Codec
ANALOG OUTPUT
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
HPL
Audio Headphone Output Left - ground referenced
O(Analog)
None
HPR
Audio Headphone Output Right - ground referenced
O(Analog)
None
EAR+
BTL Subwoofer positive output
O(Analog)
None
EAR-
BTL Subwoofer negative output
O(Analog)
None
LINEOUTL
Audio Line Output Left - signal is a buffered version of
Headphone Output Left
O(Analog)
None
LINEOUTR
Audio Line Output Right- signal is a buffered version of
Headphone Output Right
O(Analog)
None
M_DET
Microphone Detect
I(Analog)
None
Pin Function
BCLK1
I2S Bit Clock 1
LRCLK1
I2S
Framing Clock 1
SDIN1
I2S
Input Data 1
BCLK2
I2S
Bit Clock 2
LRCLK2
I2S
Framing Clock 2
SDIN2
I2S
input Data 2
BCLK3
I2S
Bit Clock 3
LRCLK3
I2S
Framing Clock 3
SDIN3
I2S
SDOUT1
I2S
SDOUT2
I2S
SDOUT3
I2S
SCL
I2C
SDA
2
I/O
ar
Pin Name
y
DATA and CONTROL
Internal Pull-up
Pull-down
Pull-Down
I/O(Digital)
Pull-Down
I(Digital)
Pull-Down
I/O(Digital)
Pull-Down
I/O(Digital)
Pull-Down
I(Digital)
Pull-Down
I/O(Digital)
Pull-Down
I/O(Digital)
Pull-Down
Input data 3
I(Digital)
Pull-Down
Output Data 1
O(Digital)
Pull-Down
Output Data 2
O(Digital)
Pull-Down
Output Data 3
O(Digital)
Pull-Down
shift clock for serial control port
I(Digital)
Pull-Up
I C shift data for serial control port
I/O(Digital)
Pull-Up
DCLK1
Digital MIC Clock 1 clock output for digital MIC 1
ODigital)
Pull-Down
DCLK2
Digital MIC Clock 2 clock output for Digital MIC 2
O(Digital)
Pull-Down
DMIC1
Digital MIC Data Input 1 data input for Digital MIC 1
I(Digital)
Pull-Down
DMIC2
Digital MIC Data Input 2 data input for Digital MIC 2
I(Digital)
Pull-Down
GPIO0
General Purpose I/O
I/O(Digital)
Pull-Up
GPIO1
General Purpose I/O
I/O(Digital)
Pull-Up
GPIO2
General Purpose I/O
I/O(Digital)
Pull-Up
GPIO3
General Purpose I/O
I/O(Digital)
Pull-Up
BOOT
Boot Mode input
0 = boot from I2C
1 = Reserved
IDigital)
Pull-Down
Pr
el
im
in
I/O(Digital)
163
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V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
nINT/nTEST
Interrupt /Test Pin (Input/Output) Open collector output driven low
I/O(Digital)
when an interrupt has been generated.
Pull-Up
HP_DET
Headphone jack detection (Input)
I(Digital)
Pull-Up
M_DET
Microphone Detect
nRESET
RESET (Input) The device is put into a low power state when this
pin is driven low
IDigital)
Pull-Down
PLL SECTION
Pin Name
Pin Function
I/O
Internal Pull-up
Pull-down
XTAL/MCLK1 (Input) Clock input connection to Crystal Oscillator
or Digital Clock source
I(XTAL)
None
XTAL_OUT
XTA_OUTL (Input) Clock input connection to Crystal Oscillator
O(XTAL)
None
MCLKIO
MCLK (Output)/MCLK2 (Input) High frequency output clock
O(XTAL)
None
Pr
el
im
in
ar
y
XTAL_IN/MCLK
164
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V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
12. TSCS454PACKAGE INFORMATION
12.1. 68-Pin QFN Package Drawing
5(9
PP;PP4)132'
3$&.$*(287/,1('5$:,1*
32',1%277209,(:
ϴ͘ϬϬ“
ϲϴ
'$36,=([
ϱϭ
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in
ϲ͘Ϯϱ“
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ϭϳ
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5HI
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Pr
ϯϰ
%6&
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32',16,'(9,(:
7HPSR6HPLFRQGXFWRU,QF
7HPSR6HPLFRQGXWRU,QF
10R3DF([ZD\6XLWH$XVWLQ7;
3$&.$*(
/4)1[PP
/HDGSLWFKPP
'2&)250$7-$1
7HPSR&RQILGHQWLDO
6&$/(PP
6+((7 2I Figure 42. Package Drawing
165
©2014 TEMPO SEMICONDUCTOR, INC.
V 1.1 10/16
TSCS454
TSCS454
Portable Audio Consumer Codec
13. ORDERING INFORMATION
TSCS454XX1NTGXyyX
68 pin QFN package
yy is the silicon revision, Contact TSI Sales to get the current revision.
Add an 8 to the end of the part number for Tape And Reel delivery.
14. DISCLAIMER
Pr
el
im
in
ar
y
While the information presented herein has been checked for both accuracy and reliability, manufacturer assumes no responsibility for either its use or for the infringement of any patents or other rights
of third parties, which would result from its use. No other circuits, patents, or licenses are implied.
This product is intended for use in normal commercial applications. Any other applications, such as
those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements, are not recommended without additional processing by manufacturer. Manufacturer
reserves the right to change any circuitry or specifications without notice. Manufacturer does not
authorize or warrant any product for use in life support devices or critical medical instruments.
166
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TSCS454
Portable Audio Consumer Codec
15. DOCUMENT REVISION HISTORY
Revision
Date
0.1
July 2014
0.2
August 2014
0.3
April 2015
0.8
August 2015
May 2016
1.0
September 2016
1.1
October 2016
initial release
Update to registers and register map
Update packaging and specs
Added relevant registers
Updated registers and format
Updated register and format errors
Updated Diagrams
Pr
el
im
in
ar
y
0.95
Description of Change
www.temposemi.com
8627 N MoPac Expwy Suite 130
Austin, Texas 78759
DISCLAIMER Tempo Semiconductor, Inc. (TSI) and its subsidiaries reserve the right to modify the products and/or specifications described
herein at any time and at TSI’s sole discretion. All information in this document, including descriptions of product features and performance, is
subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the
independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is
provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of TSI’s products
for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of TSI or any third parties.
TSI’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an TSI product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an TSI product in such a manner does so at their own
risk, absent an express, written agreement by TSI.
Tempo Semiconductor, TSI and the TSI logo are registered trademarks of TSI. Other trademarks and service marks used herein, including
protected names, logos and designs, are the property of TSI or their respective third party owners.