STMicroelectronics STM32F30x STM32F302xx, STM32F303xx, STM32F31x xx microcontroller Application note

AN4152

Application note

Clock configuration tool for

STM32F302xx/STM32F303xx/STM32F31xxx microcontrollers

Introduction

This application note presents the clock system configuration tool for the

STM32F302xx/STM32F303xx/STM32F31xxx microcontroller family.

The purpose of this tool is to help the user configure the microcontroller clocks, taking into consideration product parameters such as power supply and Flash access mode.

The configuration tool is implemented in the “STM32F30x_Clock_Configuration_VX.Y.Z.xls” file which is supplied with the STM32F30xxx Standard Peripherals Library and can be downloaded from

www.st.com

.

●

●

●

●

This tool supports the following functionalities for

STM32F302xx/STM32F303xx/STM32F31xxx microcontrollers:

Configuration of the system clock, HCLK source, and output frequency

Configuration of the Flash latency (number of wait states depending on the HCLK frequency)

Setting of the PCLK1, PCLK2, TIMCLK (timer clocks), and I2SCLK frequencies

Generation of a ready-to-use system_stm32f30x.c file with all the above settings

(STM32F30x CMSIS Cortex-M4 device peripheral access layer system source file)

The STM32F30x_Clock_Configuration_VX.Y.Z.xls is referred to as “clock tool” throughout this document.

Before using the clock tool, it is essential to read the STM32F30xxx/STM32F31xxx microcontroller reference manual (RM0316). This application note is not a substitute for the reference manual.

This tool supports only the STM32F302xx/STM32F303xx/STM32F31xxx devices.

For VX.Y.Z, please refer to the tool version, example V1.0.0.

In the software menus, STM32F30x is used to refer to STM32F302xx, STM32F303xx and

STM32F31xxx devices.

Table 1.

Type

Applicable products

Microcontrollers

STM32F302xx, STM32F303xx

STM32F31xxx

Part numbers

October 2012 Doc ID 023560 Rev 1 1/17

www.st.com

4

5

6

1

2

Contents

Contents

3

AN4152

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.1

Software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.2

Hardware requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1

2.2.2

2.2.3

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

I2S clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Tutorials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1

Wizard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2

Expert mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Known limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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AN4152

List of tables

List of tables

Table 1.

Table 2.

Table 3.

Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Definition of terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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List of figures

List of figures

AN4152

Figure 1.

Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 2.

I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 3.

Wizard mode user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4.

Select the clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5.

File generation error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 6.

Expert mode user interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 7.

System clock frequency is exceeded . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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AN4152

1 Glossary

Table 2.

Definition of terms

Term

HCLK

PCLK1

PCLK2

TIMCLK

F

CPU

Ext.Clock

V

DD

HSI

HSE

MCLK

I2S

Fs

I2SCLK

AHB clock

APB1 clock

APB2 clock

Timer clock

Cortex-M4 clock

External clock

Power supply

High-speed internal clock

High-speed external clock

Master clock

Integrated interchip sound

Sampling frequency

I2S clock

Description

Glossary

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Getting started AN4152

This section describes the requirements and procedures needed to start using the clock tool.

To use the clock tool with Windows operating system, a recent version of Windows, such as

Windows XP, Vista or Windows 7, must be installed on the PC with at least 256 Mbytes of

RAM.

Before starting to use the clock tool, make sure that Microsoft Office is installed on your machine and then follow these steps:

●

Download the latest version of the clock tool for the STM32F30xxx product from

www.st.com

.

● Enable macros and ActiveX controls

Excel 1997-2003 version

1.

Click Tools in the menu bar

Note: If ActiveX controls are not enabled, a warning message is displayed asking you to enable

ActiveX. In this case, you should click “OK” to enable it.

Excel 2007 version

1.

Click the Microsoft Office button and then click Excel options

Note:

recommended; potentiality dangerous controls can run)

For more information about how to enable macros and ActiveX controls please refer to the

Microsoft Office website.

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AN4152 Getting started

2.2.1 Introduction

The clock tool is designed to configure the system clocks and generate the

system_stm32f30x.c file for STM32F302xx/STM32F303xx/STM32F31xxx microcontrollers.

The system_stm32f30x.c file is provided as a template system clock configuration file which can be easily modified to select the corresponding system clock frequency and to configure the Flash latency.

Note:

This section describes the system clock scheme that is dependent on the voltage requirements (V

DD

) versus the system clock frequency and Flash latency versus the system clock frequency.

Three different clock sources can be used to drive the system clock (SYSCLK):

1.

HSI (8 MHz) oscillator clock

2. HSE (4 MHz to 32 MHz) oscillator clock

3. Main phase-locked loop (PLL) clock with a PLL voltage-controlled oscillator

(PLLVCO) input frequency.

All peripheral clocks are derived from the SYSCLK.

The number of Flash memory wait states (latency) is defined according to the frequency of the CPU (Cortex-M4):

- Zero wait states if 0 < SYSCLK <= 24 MHz

- One wait state if 24 MHz <SYSCLK <= 48 MHz

- Two wait state if 48MHz <SYSCLK <= 72MHz

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Getting started AN4152

Figure 1.

Clock scheme

FLITFCLK to Flash programming interface

HSI

SYSCLK to I2Cx (x = 1,2)

OSC_OUT

OSC_IN

OSC32_IN

OSC32_OUT

MCO to I2Sx (x = 2,3)

8 MHz

HSI RC

HSI

/2

PLLSRC

PLLMUL

PLL x2,x3,..

x16

HSI

PLLCLK

HSE

SW prescaler

/1,2,..512

SYSCLK

/2,/3,...

/16

CSS

HCLK

/8

APB1 prescaler

/1,2,4,8,16

4-32 MHz

HSE OSC

USB prescaler

/1,1.5

PCLK1

If (APB1 prescaler

=1) x1 else x2

PCLK1

SYSCLK

HSI

LSE

USBCLK to USB interface to AHB bus, core, memory and DMA to cortex System timer

FHCLK Cortex free running clock to APB1 peripherals to TIM 2,3,4,6,7 to USARTx (x = 2..5)

APB2 prescaler

/1,2,4,8,16

PCLK2 to APB2 peripherals

/32

RTCCLK

LSE OSC

32.768kHz

LSE

RTCSEL[1:0] to RTC

LSI RC

40kHz

LSI to IWWDG

IWWDGCLK

Main clock output

MCO

/2

PLLCLK

HSI

LSI

HSE

SYSCLK

If (APB2 prescaler

=1) x1 else x2

PCLK2

SYSCLK

HSI

LSE to TIM 15,16,17 to USART1

TIM1/8

ADC

Prescaler

/1,2,4

ADC

Prescaler

/1,2,4,6,8,10,12,16,

32,64,128,256 to ADCxy

(xy = 12, 34)

MS19989V1

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AN4152

2.2.3 I2S clock generator

This section describes the I2S clock generator. It is dependent on:

●

●

●

Master clock MCLK (enable or disable)

Frame width

I2S peripheral clock (I2SCLK)

Figure 2.

I2S clock generator architecture

Getting started

MCK

I2SxCLK

8-bit linear divider + reshaping stage

MCKOE

ODD

I2SDIV[7:0]

Divider by 4

I2SMOD

Div2 0

1

0

1

MCKOE

CHLEN

CK

Note:

The audio sampling frequency may be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz,

22.05 kHz, 16 kHz, 11.025 kHz or 8 kHz. To reach the desired frequency, the linear divider

(DIV) needs to be programmed according to the formulas below:

When the master clock is generated (MCKOE bit in the SPI_I2SPR register is set):

●

●

FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD)*8)] when the channel frame is 16 bits wide

FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD)*4)] when the channel frame is 32 bits wide

Where ODD is an odd factor for the prescaler

●

●

When the master clock is disabled (MCKOE bit cleared):

FS = I2SxCLK/[(16*2)*((2*I2SDIV)+ODD))] when the channel frame is 16 bits wide

FS = I2SxCLK/[(32*2)*((2*I2SDIV)+ODD))] when the channel frame is 32 bits wide

This tool does not configure the I2S register.

The sampling frequency error is computed as an indicator according to the I2S parameters which are not configured in the output file “system_stm32f30x.c”.

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Tutorials

3 Tutorials

AN4152

This section describes how to use the clock tool to configure all system clocks and generate the system_stm32f30x.c file. Two modes are available: Wizard and Expert. The selection is made in the Configuration mode list box.

This mode (default mode) guides you through a series of steps to obtain the desired clock system configuration quickly and easily.

Figure 3.

Wizard mode user interface

Note: The ‘Reset’ button permits the system clock for the default configuration to be set.

The wizard guides you through the following steps:

1.

Set the HSE frequency (if it is used in your application) between a minimum of 4 MHz and a maximum of 32 MHz if a crystal oscillator is used for the STM32F3xxxx. If the frequency entered is out of range, an error message is displayed, and a valid frequency must be entered. The definition of HSE_VALUE in the stm32f30x.h file must be modified each time the user changes the HSE oscillator value.

3. Specify if the I2S clock is needed. If needed, enable it and follow steps 7, 8 and 9.

Otherwise, go to step 4.

4. Specify that the USB clock is needed

5. Set the desired HCLK frequency. If the value entered is higher than the maximum

HCLK frequency, an error message is displayed.

6. Select the PCLK1 and PCLK2 prescaler settings from the list box to obtain the desired

PCLK1 and PCLK2 frequencies. The TIMCLK frequencies are configured automatically depending on the PCLK1 and PCLK2 prescaler settings.

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AN4152

Note:

Tutorials

In this product PCLK1 and PCLK2 share the some clock signal, so APB1 prescaler should always equal APB2 prescaler.

7. If the I2S clock is needed, select the frame width (16 or 32 bits)

8. Specify if the master clock is enabled or disabled (Select ON/OFF from the list box)

9. Select the frequency from the list box. The Fs value can be 192 kHz, 96 kHz, 48 kHz,

44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz, or 8 kHz.

If more than one clock source is possible, a message box displays the clock sources that can be selected (see

Figure 4

). Choose HSE, HSI or PLL (which are sourced by

the HSI or HSE).

Figure 4.

Select the clock source

The system_stm32f30x.c file is generated in the same location as the clock tool.

Display the file to verify the value of the system clock, SystemCoreClock, and the values of HCLK, PCLK1, PCLK2, Flash access mode, and other parameters which are defined in the SetSysClock function.

If the file is not generated, an error message is displayed as shown

Figure 5

.

Figure 5.

File generation error

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Tutorials AN4152

This mode provides more flexibility regarding the configuration setup but the user must ensure that the configuration is correct.

Figure 6.

Expert mode user interface

The ‘Reset’ button permits the system clock to be reset to the default configuration.

Expert mode allows the user to:

1.

Configure the SYSCLK frequency

2. If required, enable the I2S clock and configure the I2S clock frequency

3. Optionally , configure the prefetch buffer

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AN4152

Note:

Tutorials

1.

Configure the SYSCLK frequency

a) If the HSE is used in your application, set its frequency to between 4 MHz and

32 MHz (set the frequency to 32 MHz if a crystal oscillator is used for the

STM32F3xxxx). If the frequency entered is out of range, an error message is displayed. A valid frequency must be entered.

The definition of HSE_VALUE in the stm32F30x.h file must be modified each time the user changes the HSE oscillator value.

b) Configure the SYSCLK source (PLL, HSE or HSI). If the clock source selection is

invalid (HCLK frequency is too high) the error message in

Figure 7

is displayed.

Figure 7.

System clock frequency is exceeded

Note:

c) If PLL is selected as the SYSCLK source, it is necessary to select the source clock for the PLL (HSE or HSI).

d) If PLL is selected as the SYSCLK source, configure the main PLL (PLLMUL).

Configure the PLL division factor (PREDIV) if the HSE is selected as the PLL clock source.

the prescaler using the AHBPrescaler list box to obtain the desired

HCLK frequency.

the prescaler settings from the list box to obtain the desired PCLK1 frequency. The TIMCLK frequencies are configured automatically depending on the PCLK1 prescaler settings.

the prescaler settings from the list box to obtain the desired PCLK2 frequency. The TIMCLK frequencies are configured automatically depending on the PCLK2 prescaler settings.

In this product, the PCLK1 and PCLK2 share the some clock signal, so the APB1 prescaler should always equal the APB2 prescaler.

h) Configure the Flash Latency: after setting the HCLK prescaler, the number of

Flash wait states is configured automatically with the best value (lowest possible value) which can be modified to any value higher than the best value.

i) Generate the clock configuration files by clicking on the Generate button

2. If required, enable the I2S clock and configure the I2S clock frequency

a) Select the frame width (16 or 32 bits) and specify if the master clock is enabled or not.

b) Select the Fs from the list box. The Fs value can be 192 kHz, 96 kHz, 48 kHz, 44.1 kHz, 32 kHz, 22.05 kHz, 16 kHz, 11.025 kHz and 8 kHz.

3. Optionally, configure the prefetch buffer

To do this, select

 

"ON" or “OFF” from the list box.

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Known limitations AN4152

Click the Generate button to automatically generate the system_stm32f30x.c file in the same location as the clock tool. It can be displayed to verify the value of the SYSCLK,

SystemCoreClock, and the values of HCLK, PCLK1, PCLK2, Flash access mode, and other parameters which are defined in the “SetSysClock” function. This generrated file should be added in the working project to be built.

This section describes the known limitations of the clock configuration tool.

This tool does not support configurations that use the HSE external clock source (HSE bypass).

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AN4152

5 Conclusion

Conclusion

This application note provides a description of how to use the clock tool with

STM32F302xx/STM32F303xx/STM32F31xxx microcontroller devices.

●

●

This tool generates a source code file system_stm32f30x.c to configure the clock system of the STM32F302xx/STM32F303xx/STM32F31xxx. It can be accessed from either of the two configuration modes:

Wizard mode, which provides a quick and easy way to configure the system clocks

Expert mode, which offers more flexibility in setting up the system clock configuration while still respecting all the product constraints.

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Revision history

Table 3.

Date

Document revision history

Revision

25-Oct-2012 1 Initial release

Changes

AN4152

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AN4152

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