TDA7266D
5W+5W DUAL BRIDGE AMPLIFIER
PRELIMINARY DATA
■
■
■
■
WIDE SUPPLY VOLTAGE RANGE (3.5 - 12V)
OUTPUT POWER
5+5W @THD = 10%, R
L
= 8
Ω
, V
CC
= 9.5V
SINGLE SUPPLY
MINIMUM EXTERNAL COMPONENTS
– NO SVR CAPACITOR
– NO BOOTSTRAP
– NO BOUCHEROT CELLS
– INTERNALLY FIXED GAIN
■ STAND-BY & MUTE FUNCTIONS
■ SHORT CIRCUIT PROTECTION
■ THERMAL OVERLOAD PROTECTION
TECHNOLOGY BI20II
PowerSO20 Slug Down
ORDERING NUMBER: TDA7266D designed for LCD TV/Monitor, PC Motherboard, TV and Portable Audio applications.
DESCRIPTION
The TDA7266D is a dual bridge amplifier specially
TEST AND APPLICATION CIRCUIT
VCC
+5V
JP1
R1
47K
R2
47K
IN1
C3 0.22
µ
F
7
S-GND
13
ST-BY
R3 10K
9
C4
10
µ
F
Vref
C5 0.22
µ
F
MUTE
IN2
R4 10K
14
8
1
C6
µ
F
PW-GND
1
10
11
20
+
-
6 15
2 OUT1+
C1
470
µ
F
C2
100nF
C7
100nF
+
-
+
5 OUT1-
19 OUT2+
+
16 OUT2-
D02AU1407
May 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/13
TDA7266D
ABSOLUTE MAXIMUM RATINGS
Symbol
Supply Voltage V s
I
O
P tot
T op
T stg,
T j
Parameter
Output Peak Current (internally limited)
Total Power Dissipation (T amb
= 70°C
Operating Temperature
Storage and Junction Temperature
Value
20
1.5
25
0 to 70
-40 to 150
THERMAL DATA
Symbol Parameter
R th j-case
Thermal Resistance Junction-case
R th j-amb
Thermal Resistance Junction-ambient (on recomended PCB) note1
Notes: 1. See Application note AN668, available on WEB FR4 with 15 via holes and ground layer.
Value
2.1
15
PIN CONNECTION
Unit
°C/W
°C/W
W
°C
°C
Unit
V
A
PW GND
OUT1+
N.C.
N.C.
OUT1-
V CC
IN1
MUTE
ST BY
PW GND
5
6
7
8
9
10
1
2
3
4
D02AU1408
20
19
18
17
16
15
14
13
12
11
PW GND
OUT2+
N.C.
N.C.
OUT2-
V CC
IN2-
SGND
N.C.
PW GND
2/13
TDA7266D
ELECTRICAL CHARACTERISTCS (Refer to test circuit) V
CC
= 9.5V, R
L
= 8
Ω
, f = 1KHz, T amb
= 25°C unless otherwise specified)
Symbol Parameter Test Condition Min. Typ.
Max.
Unit
3.5 V
CC
I q
V
OS
P
O
THD
Supply Range
Total Quiescent Current
Output Offset Voltage
Output Power
Total Harmonic Distortion
THD 10% 4.3
9.5
50
5
0.05
12
60
120
V mA mV
W
P
O
= 1W
P
O
= 0.1W to 2W f = 100Hz to 15KHz f = 100Hz, VR =0.5V
0.2
1
%
%
SVR
CT
A
MUTE
T w
Supply Voltage Rejection
Crosstalk
Mute Attenuation
Thermal Threshold
G
V
∆
G
V
R i
Closed Loop Voltage Gain
Voltage Gain Matching
Input Resistance
VT
MUTE
Mute Threshold
VT
ST-BY
St-by Threshold
St-by Current V6 = GND I
ST-BY e
N
Total Output Voltage for V
CC
> 6.4V; Vo = -30dB for V
CC
< 6.4V; Vo = -30dB
A Curve
40
46
60
25
25
2.3
V
CC
/2
-1
0.8
56
60
80
150
26
30
2.9
V
CC
/2
-0.75
1.3
150
27
0.5
4.1
V
CC
/2
-0.5
1.8
100
V
µ
A
µ
V dB dB dB
°C dB dB
K
Ω
V
V
3/13
TDA7266D
APPLICATIVE SUGGESTIONS
STAND-BY AND MUTE FUNCTIONS
(A) Microprocessor Application
In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guarantee the right Stby and mute signals sequence.It is quite simple to obtain this function using a microprocessor (Fig. 1 and 2).
At first St-by signal (from
µ
P) goes high and the voltage across the St-by terminal (Pin 9) starts to increase exponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs.
When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C1, C3) start to charge.
It's necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers.
A delay of 100-200ms between St-by and mute signals is suitable for a proper operation.
Figure 1. Microprocessor Application
µ
P
C1 0.22
µ
F
IN1
ST-BY R1 10K
C2
10
µ
F
7
9
C3 0.22
µ
F
IN2
MUTE R2 10K
C4
1
µ
F
S-GND
13
14
Vref
8
PW-GND
1
10
11
20
+
-
6
VCC
15
2 OUT1+
C5
470
µ
F
C6
100nF
-
+
+
-
5 OUT1-
19 OUT2+
-
+
16 OUT2-
D02AU1409
4/13
TDA7266D
Figure 2. Microprocessor Driving Signals
+V
S
(V)
+18
V
IN
(mV)
V
ST-BY pin 9
1.8
1.3
0.8
V
MUTE pin 8
4.1
2.9
2.3
I q
(mA)
V
OUT
(V)
OFF
ST-BY
MUTE
PLAY MUTE ST-BY OFF
D02AU1411
B) Low Cost Application
In low cost applications where the mP is not present, the suggested circuit is shown in fig.3.
The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage divider.
The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by and mute threshold exceeding, avoiding "Popping" problems.
So to avoid any popping or clicking sond, it is important to clock: a Correct Sequence: At turn-ON, the Stand-by must be removed at first, then the Mute must be released after a delay of about 100-200ms. On the contrary at turn-OFF the Mute must be activated as first and then the Stand-by.
With the values suggested in the Application circuit the right operation is guaranteed.
b Correct Threshold Voltages: In order to avoid that due to the spread in the internal thresholds (see the above limits) a wrong external voltage causes uncertain commutations for the two functions we suggest to use the following values:
Mute for Vcc>6.4V
Mute for Vcc<6.4V
Stand-by
: VT = 2.3V
: VT = Vcc/2 - 1
: VT = 0.8V
5/13
TDA7266D
Figure 3. Stand-alone low-cost Application
R1
47K
R2
47K
C4
10
µ
F
C3 0.22
µ
F
IN1
ST-BY
7
9
S-GND
C5 0.22
IN2
µ
F
13
Vref
14
PW-GND
MUTE
8
1
10
11
20
+
-
6
VCC
15
2 OUT1+
C1
470
µ
F
C2
100nF
C7
100nF
-
+
+
-
-
+
5
19
16
OUT1-
OUT2+
OUT2-
D02AU1410
PCB Layout and External Components:
Regarding the PCB layout care must be taken for three main subjects: c) Signal and Power Gnd separation d) Dissipating Copper Area e) Filter Capacitors positioning
)Signal and Power Gnd separation: c To the Signal GND must be referred the Audio Input Signals, the Mute and Stand-by Voltages and the device PIN.13. This Gnd path must be as clean as possible in order to improve the device
THD+Noise and to avoid spurious oscillations across the speakers.
The Power GND is directly connected to the Output power Stage transistors (Emitters) and is crossed by large amount of current, this path is also used in this device to dissipate the heating generated (no needs of external heatsinker).
Referring to the typical application circuit, the separation between the two GND paths must be obtained connecting them separately (star routing) to the bulk
Electrolithic capacitor C1 (470
µ
F).
Regarding the Power Gnd dimensioning we have to consider the Dissipated Power the Thermal Protection Threshold and the Package thermal Characteristics.
6/13
TDA7266D d Dissipating Copper Area:
Dissipated Power:
The max dissipated power happens for a THD near 1% and is given by the formula:
P = 2
⋅
V
2
-------------+ I q
π 2
2
V
CC
This gives for: Vcc = 9.5V, Rl = 8
Ω
,Iq = 50mA a dissipated power of Pd = 5W.
Thermal Protection:
The thermal protection threshold is placed at a junction temperature of 150°C.
Package Thermal Characteristics:
The thermal resistance Junction to Ambient obtainable with a GND copper Area of 3x3 cm and with 16 via holes (see picture) is about 15°C/W. This means that with the above mentioned max dissipated Power (Pd=5W) we can expect a 75°C, this gives a safety margin before the thermal protection intervention in the consumer environments where a 50°C ambient is specified as maximum
The Thermal constraints determine the max supply voltage that can be used for the different Load Impedances, this in order to avoid the thermal Protection Intervention.
The max. dissipated power must be not in excess of 5W , this at turns gives the following operating supply voltages:
Load (Ohm) Supply Voltage (V)
4 6.5
6
8
16
8.5
9.5
14 e Filter Capacitors Positioning:
The two Ceramic capacitors C2/C7 (100nF) must be placed as close as possible respectively to the two Vcc pins ( 6 - 15) in order to avoid the possibiltiy of oscillations arising on the output Audio signals.
Package Informations:
You can find a complete description for the PowerSO package into the APPLICATION NOTE AN668 available on web.
Here we want to focalize the attention only on the the Dissipating elements and ground layer.
7/13
TDA7266D
Considering the dissipated power involved in the TDA7266D application that is in the range of 5W, as explained in a previous section, we suggest via holes ( see fig. 4).
Using via holes a more direct thermal path is obtained from the slug to the ground layer.The number of vias is chosen accordingly to the desired performance (in our demonstration board we use 15 vias).
In fig.4 is shown as an example the footprint to be used to create the vias.
Figure 4.
The above metioned mounting solution is enough to dissipate the power involved
In the most part of the application using the TDA7266D.
If necessary a further improvement in the Rth J-Ambient can be obtained as shown in fig.5 where the
PowerSO20 is soldered onto a via hole structure with a metal plate glued on the opposite side of the board.
Figure 5. Mounting on epoxy FR4 using via Holes for heat transfer and external metal plate
8/13
Figure 6. Distortion vs Frequency
THD(%)
10
Vcc = 9.5 V
Rl = 8 ohm
1
0.1
0.010
100
Pout = 100mW
Pout = 2W
1k frequency (Hz)
10k 20k
Figure 7. Gain vs Frequency
Level(dBr)
5.0000
4.0000
3.0000
2.0000
1.0000
0.0
-1.000
-2.000
-3.000
-4.000
-5.000
10
Vcc = 9.5V
Rl = 8 ohm
Pout = 1W
100 1k frequency (Hz)
10k 100k
Figure 8. Mute Attenuation vs Vpin.8
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
Attenuation (dB)
1.5
2 2.5
3
Vpin.6(V)
3.5
4 4.5
5
TDA7266D
Figure 9. Stand-By attenuation vs Vpin 9
Attenuation (dB)
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
0 0.2
0.4
0.6
0.8
1 1.2
1.4
1.6
1.8
2 2.2
2.4
Vpin.7 (V)
Figure 10. Quiescent Current vs Supply Voltage
70
Iq (mA)
65
60
55
50
45
40
35
30
3 4 5 6 7 8 9 10 11 12
Vsupply(V)
Figure 11. Total Power Dissipation & Efficiency vs Pout
9/13
TDA7266D
Figure 12. THD+N vs Output Power Figure 13. THD+N vs Output Power
3 4 5
Figure 14. PC Board Component Layout
500m 700m 1
10/13
Figure 15. Evaluation Board Top Layer Layout
TDA7266D
Figure 16. Evaluation Board Bottom Layer Layout
11/13
TDA7266D
DIM.
A a1 a2 mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.1
3.6
0.3
3.3
0.004
0.142
0.012
0.130
a3 b
E e
0
0.4
c 0.23
D (1) 15.8
D1 9.4
13.9
1.27
11.43
0.1
0.53
0.32
16
9.8
14.5
0.000
0.016
0.009
0.622
0.370
0.547
0.050
0.450
0.004
0.021
0.013
0.630
0.386
0.570
e3
E1 (1) 10.9
E2
11.1
2.9
0.429
0.437
0.114
E3
G
H h
L
5.8
0
15.5
0.8
6.2
0.1
0.228
0.000
15.9
0.610
1.1
1.1
0.031
N
S
8˚ (typ.)
8˚ (max.)
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.
0.244
0.004
0.626
0.043
0.043
N N a2 A b e
DETAIL A e3
H
MECHANICAL DATA
Weight: 1.9gr
R
DETAIL B lead
OUTLINE AND
JEDEC MO-166
PowerSO20
E a1 c
DETAIL A
D slug
20 11 a3
DETAIL B
Gage Plane
BOTTOM VIEW
S
0.35
L
E2 E1
- C -
SEATING PLANE
G C
(COPLANARITY)
T
E3
1 10
D1
PSO20MEC h x 45
0056635
12/13
TDA7266D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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© 2003 STMicroelectronics - All Rights Reserved
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