STMicroelectronics STM32F75xxx, STM32F74xxx Microcontroller User Manual

RM0385
Reference manual
STM32F75xxx and STM32F74xxx advanced ARM®-based
32-bit MCUs
Introduction
This reference manual targets application developers. It provides complete information on
how to use the STM32F75xxx and STM32F74xxx microcontroller memory and peripherals.
The STM32F75xxx and STM32F74xxx is a family of microcontrollers with different memory
sizes, packages and peripherals.
For ordering information, mechanical and electrical device characteristics please refer to the
datasheets.
For information on the ARM® Cortex®-M7 with FPU core, please refer to the Cortex®-M7
with FPU Technical Reference Manual.
Related documents
Available from STMicroelectronics web site www.st.com:
• STM32F75xxx and STM32F74xxx datasheets
• STM32F7 Series Cortex®-M7 processor programming manual (PM0253)
October 2016
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Contents
RM0385
Contents
1
2
Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.1
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
1.2
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
1.3
Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.1
2.2
3
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System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.1.1
Multi AHB BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.1.2
AHB/APB bridges (APB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.1.3
CPU AXIM bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.4
ITCM bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.5
DTCM bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.6
CPU AHBS bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.7
AHB peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.1.8
DMA memory bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.9
DMA peripheral bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.10
Ethernet DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.11
USB OTG HS DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.12
LCD-TFT controller DMA bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.1.13
DMA2D bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.2.2
Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 65
2.3
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.4
Flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
2.5
Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Embedded Flash memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.2
Flash main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
3.3
Flash functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.1
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
3.3.2
Read access latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
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3.5
4
3.3.3
Flash program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.3.4
Unlocking the Flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.5
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3.3.6
Flash erase sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.7
Flash programming sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.3.8
Flash Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
FLASH Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.4.1
Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.4.2
Option bytes programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
FLASH memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.1
Read protection (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.5.2
Write protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.6
One-time programmable bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.7
FLASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.7.1
Flash access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . 87
3.7.2
Flash key register (FLASH_KEYR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.7.3
Flash option key register (FLASH_OPTKEYR) . . . . . . . . . . . . . . . . . . . 88
3.7.4
Flash status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.7.5
Flash control register (FLASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.7.6
Flash option control register (FLASH_OPTCR) . . . . . . . . . . . . . . . . . . . 91
3.7.7
Flash option control register (FLASH_OPTCR1) . . . . . . . . . . . . . . . . . . 92
3.7.8
Flash interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Power controller (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.1
4.2
4.3
Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.1.1
Independent A/D converter supply and reference voltage . . . . . . . . . . . 96
4.1.2
Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.1.3
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.1.4
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 103
4.2.2
Brownout reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.2.3
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 104
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.3.1
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.2
Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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4.4
4.5
5
Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.3.4
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.3.5
Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.3.6
Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.7
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
4.4.1
PWR power control register (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . 119
4.4.2
PWR power control/status register (PWR_CSR1) . . . . . . . . . . . . . . . . 121
4.4.3
PWR power control/status register 2 (PWR_CR2) . . . . . . . . . . . . . . . 123
4.4.4
PWR power control register 2 (PWR_CSR2) . . . . . . . . . . . . . . . . . . . 124
PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1
5.2
5.3
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4.3.3
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.1
System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.2
Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5.1.3
Backup domain reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.2.1
HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.2.2
HSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.2.3
PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.2.4
LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.5
LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.6
System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.7
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2.8
RTC/AWU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.2.9
Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.10
Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.11
Internal/external clock measurement using TIM5/TIM11 . . . . . . . . . . . 137
5.2.12
Peripheral clock enable register (RCC_AHBxENR,
RCC_APBxENRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.1
RCC clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.3.2
RCC PLL configuration register (RCC_PLLCFGR) . . . . . . . . . . . . . . . 142
5.3.3
RCC clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . 144
5.3.4
RCC clock interrupt register (RCC_CIR) . . . . . . . . . . . . . . . . . . . . . . . 146
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5.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR) . . . . . . . . . . 149
5.3.6
RCC AHB2 peripheral reset register (RCC_AHB2RSTR) . . . . . . . . . . 152
5.3.7
RCC AHB3 peripheral reset register (RCC_AHB3RSTR) . . . . . . . . . . 153
5.3.8
RCC APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . 153
5.3.9
RCC APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . 157
5.3.10
RCC AHB1 peripheral clock register (RCC_AHB1ENR) . . . . . . . . . . . 159
5.3.11
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR) . . . . . 161
5.3.12
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR) . . . . . 162
5.3.13
RCC APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . 162
5.3.14
RCC APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . 166
5.3.15
RCC AHB1 peripheral clock enable in low-power mode register
(RCC_AHB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
5.3.16
RCC AHB2 peripheral clock enable in low-power mode register
(RCC_AHB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
5.3.17
RCC AHB3 peripheral clock enable in low-power mode register
(RCC_AHB3LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
5.3.18
RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
5.3.19
RCC APB2 peripheral clock enabled in low-power mode register
(RCC_APB2LPENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
5.3.20
RCC backup domain control register (RCC_BDCR) . . . . . . . . . . . . . . 179
5.3.21
RCC clock control & status register (RCC_CSR) . . . . . . . . . . . . . . . . 180
5.3.22
RCC spread spectrum clock generation register (RCC_SSCGR) . . . . 182
5.3.23
RCC PLLI2S configuration register (RCC_PLLI2SCFGR) . . . . . . . . . 183
5.3.24
RCC PLLSAI configuration register (RCC_PLLSAICFGR) . . . . . . . . . 186
5.3.25
RCC dedicated clocks configuration register (RCC_DKCFGR1) . . . . 187
5.3.26
RCC dedicated clocks configuration register (DCKCFGR2) . . . . . . . . 189
5.3.27
RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.2
GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3
GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.3.1
General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.3.2
I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 198
6.3.3
I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.4
I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.3.5
I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
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6.3.6
GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.7
I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.8
External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.3.9
Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.10
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.3.11
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.3.12
Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.3.13
Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 203
6.3.14
Using the GPIO pins in the backup supply domain . . . . . . . . . . . . . . . 203
GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.4.1
GPIO port mode register (GPIOx_MODER) (x =A..K) . . . . . . . . . . . . . 204
6.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A..K) . . . . . . . 204
6.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.4.5
GPIO port input data register (GPIOx_IDR) (x = A..K) . . . . . . . . . . . . 206
6.4.6
GPIO port output data register (GPIOx_ODR) (x = A..K) . . . . . . . . . . 206
6.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K) . . . . . . . . . 206
6.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.4.9
GPIO alternate function low register (GPIOx_AFRL)
(x = A..K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.4.10
GPIO alternate function high register (GPIOx_AFRH)
(x = A..J) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.4.11
GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 212
7.1
I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.2
SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP) . . . . . . . . . . 212
7.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC) . . 213
7.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
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7.2.6
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.2.7
Compensation cell control register (SYSCFG_CMPCR) . . . . . . . . . . . 216
7.2.8
SYSCFG register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 218
8.1
DMA introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.2
DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
8.3
DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.1
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.2
DMA overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
8.3.3
DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.4
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
8.3.5
Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.3.6
DMA streams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
8.3.7
Source, destination and transfer modes . . . . . . . . . . . . . . . . . . . . . . . 223
8.3.8
Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
8.3.9
Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.3.10
Double buffer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
8.3.11
Programmable data width, packing/unpacking, endianness . . . . . . . . 228
8.3.12
Single and burst transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.3.13
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
8.3.14
DMA transfer completion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
8.3.15
DMA transfer suspension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.3.16
Flow controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
8.3.17
Summary of the possible DMA configurations . . . . . . . . . . . . . . . . . . . 235
8.3.18
Stream configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
8.3.19
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
8.4
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
8.5
DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
8.5.1
DMA low interrupt status register (DMA_LISR) . . . . . . . . . . . . . . . . . . 239
8.5.2
DMA high interrupt status register (DMA_HISR) . . . . . . . . . . . . . . . . . 240
8.5.3
DMA low interrupt flag clear register (DMA_LIFCR) . . . . . . . . . . . . . . 241
8.5.4
DMA high interrupt flag clear register (DMA_HIFCR) . . . . . . . . . . . . . 241
8.5.5
DMA stream x configuration register (DMA_SxCR) (x = 0..7) . . . . . . . 242
8.5.6
DMA stream x number of data register (DMA_SxNDTR) (x = 0..7) . . . 245
8.5.7
DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7) . 246
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8.5.8
DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7) 246
8.5.9
DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7) 246
8.5.10
DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7) . . . . . . 247
8.5.11
DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Chrom-Art Accelerator™ controller (DMA2D) . . . . . . . . . . . . . . . . . . 253
9.1
DMA2D introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
9.2
DMA2D main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
9.3
DMA2D functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
9.3.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
9.3.2
DMA2D control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
9.3.3
DMA2D foreground and background FIFOs . . . . . . . . . . . . . . . . . . . . 255
9.3.4
DMA2D foreground and background pixel format converter (PFC) . . . 256
9.3.5
DMA2D foreground and background CLUT interface . . . . . . . . . . . . . 258
9.3.6
DMA2D blender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.3.7
DMA2D output PFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.3.8
DMA2D output FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
9.3.9
DMA2D AHB master port timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
9.3.10
DMA2D transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
9.3.11
DMA2D configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
9.3.12
DMA2D transfer control (start, suspend, abort and completion) . . . . . 264
9.3.13
Watermark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.3.14
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.3.15
AHB dead time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.4
DMA2D interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
9.5
DMA2D registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
9.5.1
DMA2D control register (DMA2D_CR) . . . . . . . . . . . . . . . . . . . . . . . . 266
9.5.2
DMA2D Interrupt Status Register (DMA2D_ISR) . . . . . . . . . . . . . . . . 268
9.5.3
DMA2D interrupt flag clear register (DMA2D_IFCR) . . . . . . . . . . . . . . 269
9.5.4
DMA2D foreground memory address register (DMA2D_FGMAR) . . . 270
9.5.5
DMA2D foreground offset register (DMA2D_FGOR) . . . . . . . . . . . . . . 270
9.5.6
DMA2D background memory address register (DMA2D_BGMAR) . . 270
9.5.7
DMA2D background offset register (DMA2D_BGOR) . . . . . . . . . . . . . 271
9.5.8
DMA2D foreground PFC control register (DMA2D_FGPFCCR) . . . . . 272
9.5.9
DMA2D foreground color register (DMA2D_FGCOLR) . . . . . . . . . . . . 274
9.5.10
DMA2D background PFC control register (DMA2D_BGPFCCR) . . . . 275
9.5.11
DMA2D background color register (DMA2D_BGCOLR) . . . . . . . . . . . 277
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DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
9.5.13
DMA2D background CLUT memory address register
(DMA2D_BGCMAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
9.5.14
DMA2D output PFC control register (DMA2D_OPFCCR) . . . . . . . . . . 278
9.5.15
DMA2D output color register (DMA2D_OCOLR) . . . . . . . . . . . . . . . . . 279
9.5.16
DMA2D output memory address register (DMA2D_OMAR) . . . . . . . . 280
9.5.17
DMA2D output offset register (DMA2D_OOR) . . . . . . . . . . . . . . . . . . 281
9.5.18
DMA2D number of line register (DMA2D_NLR) . . . . . . . . . . . . . . . . . 281
9.5.19
DMA2D line watermark register (DMA2D_LWR) . . . . . . . . . . . . . . . . . 282
9.5.20
DMA2D AHB master timer configuration register (DMA2D_AMTCR) . 282
9.5.21
DMA2D register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 285
10.1
11
9.5.12
NVIC features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
10.1.1
SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
10.1.2
Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . 290
11.1
EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
11.2
EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
11.3
Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
11.4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
11.5
Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
11.6
Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
11.7
Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
11.8
External interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
11.9
EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
11.9.1
Interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
11.9.2
Event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
11.9.3
Rising trigger selection register (EXTI_RTSR) . . . . . . . . . . . . . . . . . . 294
11.9.4
Falling trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . . . . . 294
11.9.5
Software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . . . . . 295
11.9.6
Pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
11.9.7
EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 297
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12.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
12.2
CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
12.3
CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
12.4
13
12.3.1
CRC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
12.3.2
CRC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
12.3.3
CRC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
12.4.1
Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
12.4.2
Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 300
12.4.3
Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
12.4.4
Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
12.4.5
CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
12.4.6
CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
13.1
FMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
13.2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
13.3
AHB interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
13.3.1
13.4
13.5
13.6
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Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 305
External device address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
13.4.1
NOR/PSRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
13.4.2
NAND Flash memory address mapping . . . . . . . . . . . . . . . . . . . . . . . 308
13.4.3
SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
NOR Flash/PSRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
13.5.1
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
13.5.2
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . 315
13.5.3
General timing rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
13.5.4
NOR Flash/PSRAM controller asynchronous transactions . . . . . . . . . 317
13.5.5
Synchronous transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
13.5.6
NOR/PSRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
NAND Flash controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
13.6.1
External memory interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
13.6.2
NAND Flash supported memories and transactions . . . . . . . . . . . . . . 350
13.6.3
Timing diagrams for NAND Flash memory . . . . . . . . . . . . . . . . . . . . . 350
13.6.4
NAND Flash operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
13.6.5
NAND Flash prewait functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
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13.7
13.8
14
13.6.6
Computation of the error correction code (ECC)
in NAND Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
13.6.7
NAND Flashcontroller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
SDRAM controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
13.7.1
SDRAM controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
13.7.2
SDRAM External memory interface signals . . . . . . . . . . . . . . . . . . . . . 360
13.7.3
SDRAM controller functional description . . . . . . . . . . . . . . . . . . . . . . . 361
13.7.4
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
13.7.5
SDRAM controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
Quad-SPI interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.2
QUADSPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.3
QUADSPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.3.1
QUADSPI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
14.3.2
QUADSPI Command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
14.3.3
QUADSPI signal interface protocol modes . . . . . . . . . . . . . . . . . . . . . 385
14.3.4
QUADSPI indirect mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
14.3.5
QUADSPI status flag polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
14.3.6
QUADSPI memory-mapped mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
14.3.7
QUADSPI Flash memory configuration . . . . . . . . . . . . . . . . . . . . . . . . 390
14.3.8
QUADSPI delayed data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
14.3.9
QUADSPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
14.3.10 QUADSPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
14.3.11 Sending the instruction only once . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
14.3.12 QUADSPI error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
14.3.13 QUADSPI busy bit and abort functionality . . . . . . . . . . . . . . . . . . . . . . 393
14.3.14 nCS behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
14.4
QUADSPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
14.5
QUADSPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
14.5.1
QUADSPI control register (QUADSPI_CR) . . . . . . . . . . . . . . . . . . . . . 396
14.5.2
QUADSPI device configuration register (QUADSPI_DCR) . . . . . . . . . 399
14.5.3
QUADSPI status register (QUADSPI_SR) . . . . . . . . . . . . . . . . . . . . . 400
14.5.4
QUADSPI flag clear register (QUADSPI_FCR) . . . . . . . . . . . . . . . . . . 401
14.5.5
QUADSPI data length register (QUADSPI_DLR) . . . . . . . . . . . . . . . . 401
14.5.6
QUADSPI communication configuration register (QUADSPI_CCR) . . 402
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14.5.7
QUADSPI address register (QUADSPI_AR) . . . . . . . . . . . . . . . . . . . . 404
14.5.8
QUADSPI alternate bytes registers (QUADSPI_ABR) . . . . . . . . . . . . 405
14.5.9
QUADSPI data register (QUADSPI_DR) . . . . . . . . . . . . . . . . . . . . . . . 405
14.5.10 QUADSPI polling status mask register (QUADSPI _PSMKR) . . . . . . . 406
14.5.11 QUADSPI polling status match register (QUADSPI _PSMAR) . . . . . . 406
14.5.12 QUADSPI polling interval register (QUADSPI _PIR) . . . . . . . . . . . . . . 407
14.5.13 QUADSPI low-power timeout register (QUADSPI_LPTR) . . . . . . . . . . 407
14.5.14 QUADSPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
15
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.1
ADC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.2
ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3
ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
15.3.1
ADC on-off control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
15.3.2
ADC1/2 and ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
15.3.3
ADC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.3.4
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
15.3.5
Single conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.3.6
Continuous conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.3.7
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
15.3.8
Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
15.3.9
Scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.3.10 Injected channel management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
15.3.11 Discontinuous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
15.4
Data alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
15.5
Channel-wise programmable sampling time . . . . . . . . . . . . . . . . . . . . . 422
15.6
Conversion on external trigger and trigger polarity . . . . . . . . . . . . . . . . 423
15.7
Fast conversion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
15.8
Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
15.9
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Using the DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
15.8.2
Managing a sequence of conversions without using the DMA . . . . . . 425
15.8.3
Conversions without DMA and without overrun detection . . . . . . . . . . 426
Multi ADC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
15.9.1
Injected simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
15.9.2
Regular simultaneous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
15.9.3
Interleaved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
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15.9.4
Alternate trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
15.9.5
Combined regular/injected simultaneous mode . . . . . . . . . . . . . . . . . . 435
15.9.6
Combined regular simultaneous + alternate trigger mode . . . . . . . . . . 435
15.10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
15.11 Battery charge monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
15.12 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
15.13 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
15.13.1 ADC status register (ADC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
15.13.2 ADC control register 1 (ADC_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
15.13.3 ADC control register 2 (ADC_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
15.13.4 ADC sample time register 1 (ADC_SMPR1) . . . . . . . . . . . . . . . . . . . . 445
15.13.5 ADC sample time register 2 (ADC_SMPR2) . . . . . . . . . . . . . . . . . . . . 445
15.13.6 ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) . . 446
15.13.7 ADC watchdog higher threshold register (ADC_HTR) . . . . . . . . . . . . . 446
15.13.8 ADC watchdog lower threshold register (ADC_LTR) . . . . . . . . . . . . . . 447
15.13.9 ADC regular sequence register 1 (ADC_SQR1) . . . . . . . . . . . . . . . . . 447
15.13.10 ADC regular sequence register 2 (ADC_SQR2) . . . . . . . . . . . . . . . . . 448
15.13.11 ADC regular sequence register 3 (ADC_SQR3) . . . . . . . . . . . . . . . . . 449
15.13.12 ADC injected sequence register (ADC_JSQR) . . . . . . . . . . . . . . . . . . 450
15.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4) . . . . . . . . . . . . . . 450
15.13.14 ADC regular data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . 451
15.13.15 ADC Common status register (ADC_CSR) . . . . . . . . . . . . . . . . . . . . . 451
15.13.16 ADC common control register (ADC_CCR) . . . . . . . . . . . . . . . . . . . . . 452
15.13.17 ADC common regular data register for dual and triple modes
(ADC_CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
15.13.18 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
16
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
16.1
DAC introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
16.2
DAC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
16.3
DAC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
16.3.1
DAC channel enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
16.3.2
DAC output buffer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
16.3.3
DAC data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
16.3.4
DAC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
16.3.5
DAC output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
16.3.6
DAC trigger selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
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16.4
16.3.7
DMA request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
16.3.8
Noise generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
16.3.9
Triangle-wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Dual DAC channel conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
16.4.1
Independent trigger without wave generation . . . . . . . . . . . . . . . . . . . 466
16.4.2
Independent trigger with single LFSR generation . . . . . . . . . . . . . . . . 466
16.4.3
Independent trigger with different LFSR generation . . . . . . . . . . . . . . 466
16.4.4
Independent trigger with single triangle generation . . . . . . . . . . . . . . . 467
16.4.5
Independent trigger with different triangle generation . . . . . . . . . . . . . 467
16.4.6
Simultaneous software start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
16.4.7
Simultaneous trigger without wave generation . . . . . . . . . . . . . . . . . . 468
16.4.8
Simultaneous trigger with single LFSR generation . . . . . . . . . . . . . . . 468
16.4.9
Simultaneous trigger with different LFSR generation . . . . . . . . . . . . . 468
16.4.10 Simultaneous trigger with single triangle generation . . . . . . . . . . . . . . 469
16.4.11 Simultaneous trigger with different triangle generation . . . . . . . . . . . . 469
16.5
DAC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
16.5.1
DAC control register (DAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
16.5.2
DAC software trigger register (DAC_SWTRIGR) . . . . . . . . . . . . . . . . . 473
16.5.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
16.5.4
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
16.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
16.5.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
16.5.7
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
16.5.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
16.5.9
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
16.5.10 DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
16.5.11 DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
16.5.12 DAC channel1 data output register (DAC_DOR1) . . . . . . . . . . . . . . . . 477
16.5.13 DAC channel2 data output register (DAC_DOR2) . . . . . . . . . . . . . . . . 477
16.5.14 DAC status register (DAC_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
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16.5.15 DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
17
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.1
DCMI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.2
DCMI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.3
DCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.4
DCMI clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
17.5
DCMI functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
17.6
17.5.1
DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.5.2
DCMI physical interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
17.5.3
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
17.5.4
Capture modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
17.5.5
Crop feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
17.5.6
JPEG format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
17.5.7
FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Data format description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.6.1
Data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.6.2
Monochrome format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
17.6.3
RGB format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.6.4
YCbCr format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.6.5
YCbCr format - Y only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
17.6.6
Half resolution image extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.7
DCMI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.8
DCMI register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.8.1
DCMI control register (DCMI_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
17.8.2
DCMI status register (DCMI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
17.8.3
DCMI raw interrupt status register (DCMI_RIS) . . . . . . . . . . . . . . . . . . 496
17.8.4
DCMI interrupt enable register (DCMI_IER) . . . . . . . . . . . . . . . . . . . . 497
17.8.5
DCMI masked interrupt status register (DCMI_MIS) . . . . . . . . . . . . . . 498
17.8.6
DCMI interrupt clear register (DCMI_ICR) . . . . . . . . . . . . . . . . . . . . . . 499
17.8.7
DCMI embedded synchronization code register (DCMI_ESCR) . . . . . 500
17.8.8
DCMI embedded synchronization unmask register (DCMI_ESUR) . . 501
17.8.9
DCMI crop window start (DCMI_CWSTRT) . . . . . . . . . . . . . . . . . . . . . 502
17.8.10 DCMI crop window size (DCMI_CWSIZE) . . . . . . . . . . . . . . . . . . . . . . 502
17.8.11 DCMI data register (DCMI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
17.8.12 DCMI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
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18
RM0385
LCD-TFT Display Controller (LTDC) . . . . . . . . . . . . . . . . . . . . . . . . . . 505
18.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
18.2
LTDC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
18.3
LTDC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
18.4
18.3.1
LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
18.3.2
LTDC reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
18.3.3
LCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
LTDC programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
18.4.1
LTDC Global configuration parameters . . . . . . . . . . . . . . . . . . . . . . . . 508
18.4.2
Layer programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
18.5
LTDC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
18.6
LTDC programming procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
18.7
LTDC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518
18.7.1
LTDC Synchronization Size Configuration Register (LTDC_SSCR) . . 518
18.7.2
LTDC Back Porch Configuration Register (LTDC_BPCR) . . . . . . . . . . 518
18.7.3
LTDC Active Width Configuration Register (LTDC_AWCR) . . . . . . . . . 519
18.7.4
LTDC Total Width Configuration Register (LTDC_TWCR) . . . . . . . . . . 520
18.7.5
LTDC Global Control Register (LTDC_GCR) . . . . . . . . . . . . . . . . . . . . 520
18.7.6
LTDC Shadow Reload Configuration Register (LTDC_SRCR) . . . . . . 522
18.7.7
LTDC Background Color Configuration Register (LTDC_BCCR) . . . . 522
18.7.8
LTDC Interrupt Enable Register (LTDC_IER) . . . . . . . . . . . . . . . . . . . 523
18.7.9
LTDC Interrupt Status Register (LTDC_ISR) . . . . . . . . . . . . . . . . . . . . 524
18.7.10 LTDC Interrupt Clear Register (LTDC_ICR) . . . . . . . . . . . . . . . . . . . . . 524
18.7.11 LTDC Line Interrupt Position Configuration Register (LTDC_LIPCR) . 525
18.7.12 LTDC Current Position Status Register (LTDC_CPSR) . . . . . . . . . . . . 525
18.7.13 LTDC Current Display Status Register (LTDC_CDSR) . . . . . . . . . . . . 526
18.7.14 LTDC Layerx Control Register (LTDC_LxCR) (where x=1..2) . . . . . . . 527
18.7.15 LTDC Layerx Window Horizontal Position Configuration Register
(LTDC_LxWHPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
18.7.16 LTDC Layerx Window Vertical Position Configuration Register
(LTDC_LxWVPCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
18.7.17 LTDC Layerx Color Keying Configuration Register
(LTDC_LxCKCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
18.7.18 LTDC Layerx Pixel Format Configuration Register
(LTDC_LxPFCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
18.7.19 LTDC Layerx Constant Alpha Configuration Register
(LTDC_LxCACR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
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18.7.20 LTDC Layerx Default Color Configuration Register
(LTDC_LxDCCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531
18.7.21 LTDC Layerx Blending Factors Configuration Register
(LTDC_LxBFCR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
18.7.22 LTDC Layerx Color Frame Buffer Address Register
(LTDC_LxCFBAR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.7.23 LTDC Layerx Color Frame Buffer Length Register
(LTDC_LxCFBLR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533
18.7.24 LTDC Layerx ColorFrame Buffer Line Number Register
(LTDC_LxCFBLNR) (where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 534
18.7.25 LTDC Layerx CLUT Write Register (LTDC_LxCLUTWR)
(where x=1..2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
18.7.26 LTDC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
19
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
19.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
19.2
RNG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
19.3
RNG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
19.4
20
19.3.1
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
19.3.2
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
RNG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.4.1
RNG control register (RNG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.4.2
RNG status register (RNG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
19.4.3
RNG data register (RNG_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
19.4.4
RNG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Cryptographic processor (CRYP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
20.1
CRYP introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
20.2
CRYP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
20.3
CRYP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
20.3.1
CRYP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
20.3.2
DES/TDES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
20.3.3
AES cryptographic core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
20.3.4
Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
20.3.5
Initialization vectors - CRYP_IV0...1(L/R) . . . . . . . . . . . . . . . . . . . . . . 566
20.3.6
CRYP busy state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
20.3.7
Procedure to perform an encryption or a decryption . . . . . . . . . . . . . . 568
20.3.8
Context swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
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20.4
CRYP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571
20.5
CRYP DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.6
CRYP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.6.1
CRYP control register (CRYP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
20.6.2
CRYP status register (CRYP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
20.6.3
CRYP data input register (CRYP_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 576
20.6.4
CRYP data output register (CRYP_DOUT) . . . . . . . . . . . . . . . . . . . . . 577
20.6.5
CRYP DMA control register (CRYP_DMACR) . . . . . . . . . . . . . . . . . . . 578
20.6.6
CRYP interrupt mask set/clear register (CRYP_IMSCR) . . . . . . . . . . . 578
20.6.7
CRYP raw interrupt status register (CRYP_RISR) . . . . . . . . . . . . . . . 579
20.6.8
CRYP masked interrupt status register (CRYP_MISR) . . . . . . . . . . . . 579
20.6.9
CRYP key registers (CRYP_K0...3(L/R)R) . . . . . . . . . . . . . . . . . . . . . 580
20.6.10 CRYP initialization vector registers (CRYP_IV0...1(L/R)R) . . . . . . . . . 582
20.6.11 CRYP context swap registers (CRYP_CSGCMCCM0..7R and
CRYP_CSGCM0..7R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584
20.6.12 CRYP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
21
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Hash processor (HASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
21.1
HASH introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
21.2
HASH main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
21.3
HASH functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
21.3.1
HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
21.3.2
HASH processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
21.3.3
Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589
21.3.4
Message digest computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
21.3.5
Message padding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592
21.3.6
Hash operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
21.3.7
HMAC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
21.3.8
Context swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
21.4
HASH interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
21.5
HASH registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
21.5.1
HASH control register (HASH_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
21.5.2
HASH data input register (HASH_DIN) . . . . . . . . . . . . . . . . . . . . . . . . 600
21.5.3
HASH start register (HASH_STR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601
21.5.4
HASH digest registers (HASH_HR0..4/5/6/7) . . . . . . . . . . . . . . . . . . . 602
21.5.5
HASH interrupt enable register (HASH_IMR) . . . . . . . . . . . . . . . . . . . 604
21.5.6
HASH status register (HASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605
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21.5.7
HASH context swap registers (HASH_CSRx) . . . . . . . . . . . . . . . . . . . 606
21.5.8
HASH register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Advanced-control timers (TIM1/TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 609
22.1
TIM1/TIM8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
22.2
TIM1/TIM8 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
22.3
TIM1/TIM8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611
22.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
22.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613
22.3.3
Repetition counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
22.3.4
External trigger input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
22.3.5
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
22.3.6
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
22.3.7
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634
22.3.8
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
22.3.9
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
22.3.10 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
22.3.11 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
22.3.12 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
22.3.13 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
22.3.14 Combined 3-phase PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
22.3.15 Complementary outputs and dead-time insertion . . . . . . . . . . . . . . . . 643
22.3.16 Using the break function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
22.3.17 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 651
22.3.18 6-step PWM generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
22.3.19 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
22.3.20 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 655
22.3.21 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
22.3.22 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658
22.3.23 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
22.3.24 Interfacing with Hall sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
22.3.25 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
22.3.26 ADC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
22.3.27 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
22.3.28 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
22.4
TIM1/TIM8 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
22.4.1
TIM1/TIM8 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 668
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22.4.2
TIM1/TIM8 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 669
22.4.3
TIM1/TIM8 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . 672
22.4.4
TIM1/TIM8 DMA/interrupt enable register (TIMx_DIER) . . . . . . . . . . . 674
22.4.5
TIM1/TIM8 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 676
22.4.6
TIM1/TIM8 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 678
22.4.7
TIM1/TIM8 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . 679
22.4.8
TIM1/TIM8 capture/compare mode register 2 (TIMx_CCMR2) . . . . . . 683
22.4.9
TIM1/TIM8 capture/compare enable register (TIMx_CCER) . . . . . . . . 685
22.4.10 TIM1/TIM8 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
22.4.11 TIM1/TIM8 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
22.4.12 TIM1/TIM8 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 689
22.4.13 TIM1/TIM8 repetition counter register (TIMx_RCR) . . . . . . . . . . . . . . 690
22.4.14 TIM1/TIM8 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . 690
22.4.15 TIM1/TIM8 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . 691
22.4.16 TIM1/TIM8 capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . 691
22.4.17 TIM1/TIM8 capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . 692
22.4.18 TIM1/TIM8 break and dead-time register (TIMx_BDTR) . . . . . . . . . . . 692
22.4.19 TIM1/TIM8 DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . 695
22.4.20 TIM1/TIM8 DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . 696
22.4.21 TIM1/TIM8 capture/compare mode register 3 (TIMx_CCMR3) . . . . . . 697
22.4.22 TIM1/TIM8 capture/compare register 5 (TIMx_CCR5) . . . . . . . . . . . . 698
22.4.23 TIM1/TIM8 capture/compare register 6 (TIMx_CCR6) . . . . . . . . . . . . 699
22.4.24 TIM1 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
22.4.25 TIM8 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
23
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General-purpose timers (TIM2/TIM3/TIM4/TIM5) . . . . . . . . . . . . . . . . . 704
23.1
TIM2/TIM3/TIM4/TIM5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
23.2
TIM2/TIM3/TIM4/TIM5 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
23.3
TIM2/TIM3/TIM4/TIM5 functional description . . . . . . . . . . . . . . . . . . . . . 706
23.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
23.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
23.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
23.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
23.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724
23.3.6
PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
23.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
23.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727
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23.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
23.3.10 Asymmetric PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
23.3.11 Combined PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732
23.3.12 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 733
23.3.13 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
23.3.14 Retriggerable one pulse mode (OPM) . . . . . . . . . . . . . . . . . . . . . . . . . 736
23.3.15 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
23.3.16 UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
23.3.17 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
23.3.18 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 740
23.3.19 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
23.3.20 DMA burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
23.3.21 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
23.4
TIM2/TIM3/TIM4/TIM5 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
23.4.1
TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 749
23.4.2
TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 750
23.4.3
TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 752
23.4.4
TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 755
23.4.5
TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756
23.4.6
TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 757
23.4.7
TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 758
23.4.8
TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 762
23.4.9
TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 764
23.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
23.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
23.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 766
23.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 767
23.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 767
23.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 768
23.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 768
23.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 769
23.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 769
23.4.19 TIM2 option register 1 (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
23.4.20 TIM2 option register 1 (TIM5_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770
23.4.21 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
24
General-purpose timers (TIM9/TIM10/TIM11/TIM12/TIM13/TIM14) . . 774
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RM0385
24.1
TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 introduction . . . . . . . . . . . . . . 774
24.2
TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 main features . . . . . . . . . . . . . 774
24.3
24.2.1
TIM9/TIM12 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774
24.2.2
TIM10/TIM11/TIM13/TIM14 main features . . . . . . . . . . . . . . . . . . . . . . 775
TIM9/TIM10/TIM11/TIM12/TIM13/TIM14 functional description . . . . . . . 777
24.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777
24.3.2
Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
24.3.3
Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
24.3.4
Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
24.3.5
Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786
24.3.6
PWM input mode (only for TIM9/TIM12) . . . . . . . . . . . . . . . . . . . . . . . 787
24.3.7
Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
24.3.8
Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
24.3.9
PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
24.3.10 Combined PWM mode (TIM9/TIM12 only) . . . . . . . . . . . . . . . . . . . . . 791
24.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
24.3.12 TIM9/TIM12 external trigger synchronization . . . . . . . . . . . . . . . . . . . 794
24.3.13 Timer synchronization (TIM9/TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . 797
24.3.14 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
24.4
TIM9/TIM12 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797
24.4.1
TIM9/TIM12 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . 797
24.4.2
TIM9/TIM12 slave mode control register (TIMx_SMCR) . . . . . . . . . . . 798
24.4.3
TIM9/TIM12 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . 800
24.4.4
TIM9/TIM12 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . 801
24.4.5
TIM9/TIM12 event generation register (TIMx_EGR) . . . . . . . . . . . . . . 802
24.4.6
TIM9/TIM12 capture/compare mode register 1 (TIMx_CCMR1) . . . . . 804
24.4.7
TIM9/TIM12 capture/compare enable register (TIMx_CCER) . . . . . . . 807
24.4.8
TIM9/TIM12 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
24.4.9
TIM9/TIM12 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
24.4.10 TIM9/TIM12 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . 808
24.4.11 TIM9/TIM12 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . 809
24.4.12 TIM9/TIM12 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . 809
24.4.13 TIM9/TIM12 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
24.5
22/1671
TIM10/TIM11/TIM13/TIM14 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
24.5.1
TIM10/TIM11/TIM13/TIM14 control register 1 (TIMx_CR1) . . . . . . . . . 812
24.5.2
TIM10/TIM11/TIM13/TIM14 Interrupt enable register (TIMx_DIER) . . 813
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24.5.3
TIM10/TIM11/TIM13/TIM14 status register (TIMx_SR) . . . . . . . . . . . . 813
24.5.4
TIM10/TIM11/TIM13/TIM14 event generation register (TIMx_EGR) . . 814
24.5.5
TIM10/TIM11/TIM13/TIM14 capture/compare mode register 1
(TIMx_CCMR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
24.5.6
TIM10/TIM11/TIM13/TIM14 capture/compare enable register
(TIMx_CCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
24.5.7
TIM10/TIM11/TIM13/TIM14 counter (TIMx_CNT) . . . . . . . . . . . . . . . . 819
24.5.8
TIM10/TIM11/TIM13/TIM14 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . 819
24.5.9
TIM10/TIM11/TIM13/TIM14 auto-reload register (TIMx_ARR) . . . . . . 819
24.5.10 TIM10/TIM11/TIM13/TIM14 capture/compare register 1
(TIMx_CCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
24.5.11 TIM11 option register 1 (TIM11_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . 820
24.5.12 TIM10/TIM11/TIM13/TIM14 register map . . . . . . . . . . . . . . . . . . . . . . 820
25
Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
25.1
TIM6/TIM7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
25.2
TIM6/TIM7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
25.3
TIM6/TIM7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
25.4
26
25.3.1
Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
25.3.2
Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
25.3.3
UIF bit remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
25.3.4
Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
25.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
TIM6/TIM7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830
25.4.1
TIM6/TIM7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . 830
25.4.2
TIM6/TIM7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . 832
25.4.3
TIM6/TIM7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . 832
25.4.4
TIM6/TIM7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . 833
25.4.5
TIM6/TIM7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . 833
25.4.6
TIM6/TIM7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833
25.4.7
TIM6/TIM7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
25.4.8
TIM6/TIM7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . 834
25.4.9
TIM6/TIM7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
26.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
26.2
LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
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26.3
LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
26.4
LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
26.4.1
LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
26.4.2
LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
26.4.3
Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
26.4.4
Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
26.4.5
Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
26.4.6
Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
26.4.7
Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841
26.4.8
Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
26.4.9
Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
26.4.10 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
26.4.11 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844
26.4.12 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
27
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26.5
LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
26.6
LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847
26.6.1
LPTIM interrupt and status register (LPTIM_ISR) . . . . . . . . . . . . . . . . 847
26.6.2
LPTIM interrupt clear register (LPTIM_ICR) . . . . . . . . . . . . . . . . . . . . 848
26.6.3
LPTIM interrupt enable register (LPTIM_IER) . . . . . . . . . . . . . . . . . . . 849
26.6.4
LPTIM configuration register (LPTIM_CFGR) . . . . . . . . . . . . . . . . . . . 850
26.6.5
LPTIM control register (LPTIM_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . 853
26.6.6
LPTIM compare register (LPTIM_CMP) . . . . . . . . . . . . . . . . . . . . . . . 854
26.6.7
LPTIM autoreload register (LPTIM_ARR) . . . . . . . . . . . . . . . . . . . . . . 854
26.6.8
LPTIM counter register (LPTIM_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . 855
26.6.9
LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.2
IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.3
IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.3.1
IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
27.3.2
Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858
27.3.3
Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
27.3.4
Low-power freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
27.3.5
Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 859
27.3.6
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
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27.3.7
27.4
28
IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
27.4.1
Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860
27.4.2
Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861
27.4.3
Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862
27.4.4
Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863
27.4.5
Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864
27.4.6
IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 866
28.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
28.2
WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
28.3
WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
28.4
29
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859
28.3.1
Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
28.3.2
Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
28.3.3
Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . . 867
28.3.4
How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 868
28.3.5
Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
28.4.1
Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
28.4.2
Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 870
28.4.3
Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
28.4.4
WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
29.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872
29.2
RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873
29.3
RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
29.3.1
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
29.3.2
GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
29.3.3
Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
29.3.4
Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
29.3.5
Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878
29.3.6
Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
29.3.7
RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 880
29.3.8
Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881
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29.3.9
Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
29.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
29.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 883
29.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
29.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 886
29.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 887
29.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
29.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 889
29.4
RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
29.5
RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
29.6
RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
29.6.1
RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
29.6.2
RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892
29.6.3
RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
29.6.4
RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 896
29.6.5
RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 899
29.6.6
RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 900
29.6.7
RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 901
29.6.8
RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 902
29.6.9
RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 903
29.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 903
29.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 904
29.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 905
29.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 906
29.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 907
29.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 908
29.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . . 909
29.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 912
29.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 913
29.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914
29.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 914
29.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
30
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Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 917
30.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
30.2
I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 917
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30.3
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
30.4
I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
30.4.1
I2C block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
30.4.2
I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
30.4.3
Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 920
30.4.4
I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
30.4.5
Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
30.4.6
Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
30.4.7
I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
30.4.8
I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 938
30.4.9
I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 950
30.4.10 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
30.4.11 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
30.4.12 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 956
30.4.13 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
30.4.14 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
30.4.15 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 966
30.4.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
30.5
I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
30.6
I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
30.7
I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
30.7.1
Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
30.7.2
Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
30.7.3
Own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 975
30.7.4
Own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 976
30.7.5
Timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
30.7.6
Timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 978
30.7.7
Interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . . . . 979
30.7.8
Interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
30.7.9
PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
30.7.10 Receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
30.7.11 Transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
30.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
31
Universal synchronous asynchronous receiver
transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
31.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
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31.2
USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
31.3
USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987
31.4
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
31.5
USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
31.5.1
USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
31.5.2
USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
31.5.3
USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
31.5.4
USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
31.5.5
Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . 1004
31.5.6
USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1005
31.5.7
Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . 1006
31.5.8
Modbus communication using USART . . . . . . . . . . . . . . . . . . . . . . . 1008
31.5.9
USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
31.5.10 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . 1010
31.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012
31.5.12 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . 1015
31.5.13 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
31.5.14 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1020
31.5.15 USART continuous communication in DMA mode . . . . . . . . . . . . . . 1022
31.5.16 RS232 hardware flow control and RS485 driver enable
using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
31.6
USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
31.7
USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
31.8
USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
31.8.1
Control register 1 (USART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029
31.8.2
Control register 2 (USART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032
31.8.3
Control register 3 (USART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
31.8.4
Baud rate register (USART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1038
31.8.5
Guard time and prescaler register (USART_GTPR) . . . . . . . . . . . . . 1039
31.8.6
Receiver timeout register (USART_RTOR) . . . . . . . . . . . . . . . . . . . . 1040
31.8.7
Request register (USART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041
31.8.8
Interrupt and status register (USART_ISR) . . . . . . . . . . . . . . . . . . . . 1042
31.8.9
Interrupt flag clear register (USART_ICR) . . . . . . . . . . . . . . . . . . . . . 1046
31.8.10 Receive data register (USART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 1047
31.8.11 Transmit data register (USART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 1048
31.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
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Serial peripheral interface / inter-IC sound (SPI/I2S) . . . . . . . . . . . . 1050
32.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
32.2
SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050
32.3
I2S main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
32.4
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051
32.5
SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
32.5.1
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
32.5.2
Communications between one master and one slave . . . . . . . . . . . . 1053
32.5.3
Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . 1055
32.5.4
Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
32.5.5
Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . 1057
32.5.6
Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
32.5.7
Configuration of SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1060
32.5.8
Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061
32.5.9
Data transmission and reception procedures . . . . . . . . . . . . . . . . . . 1061
32.5.10 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1071
32.5.11 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1072
32.5.12 NSS pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.5.13 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
32.5.14 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
32.6
SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
32.7
I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
32.7.1
I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
32.7.2
I2S full duplex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078
32.7.3
Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
32.7.4
Start-up description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1086
32.7.5
Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
32.7.6
I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1090
32.7.7
I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1092
32.7.8
I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1093
32.7.9
I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
32.7.10 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
32.8
I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1095
32.9
SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
32.9.1
SPI control register 1 (SPIx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1097
32.9.2
SPI control register 2 (SPIx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1099
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32.9.3
SPI status register (SPIx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1102
32.9.4
SPI data register (SPIx_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1103
32.9.5
SPI CRC polynomial register (SPIx_CRCPR) . . . . . . . . . . . . . . . . . . 1103
32.9.6
SPI Rx CRC register (SPIx_RXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1105
32.9.7
SPI Tx CRC register (SPIx_TXCRCR) . . . . . . . . . . . . . . . . . . . . . . . 1105
32.9.8
SPIx_I2S configuration register (SPIx_I2SCFGR) . . . . . . . . . . . . . . . 1106
32.9.9
SPIx_I2S prescaler register (SPIx_I2SPR) . . . . . . . . . . . . . . . . . . . . 1108
32.9.10 SPI/I2S register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
33
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
33.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110
33.2
SAI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
33.3
SAI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
33.3.1
SAI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
33.3.2
Main SAI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1113
33.3.3
SAI synchronization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114
33.3.4
Audio data size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
33.3.5
Frame synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
33.3.6
Slot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
33.3.7
SAI clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
33.3.8
Internal FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1122
33.3.9
AC’97 link controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
33.3.10 SPDIF output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
33.3.11 Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
33.3.12 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
33.3.13 Disabling the SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
33.3.14 SAI DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1136
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33.4
SAI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1137
33.5
SAI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1138
33.5.1
Global configuration register (SAI_GCR) . . . . . . . . . . . . . . . . . . . . . . 1138
33.5.2
Configuration register 1 (SAI_ACR1 / SAI_BCR1) . . . . . . . . . . . . . . 1138
33.5.3
Configuration register 2 (SAI_ACR2 / SAI_BCR2) . . . . . . . . . . . . . . 1141
33.5.4
Frame configuration register (SAI_AFRCR / SAI_BFRCR) . . . . . . . . 1143
33.5.5
Slot register (SAI_ASLOTR / SAI_BSLOTR) . . . . . . . . . . . . . . . . . . . 1144
33.5.6
Interrupt mask register 2 (SAI_AIM / SAI_BIM) . . . . . . . . . . . . . . . . . 1146
33.5.7
Status register (SAI_ASR / SAI_BSR) . . . . . . . . . . . . . . . . . . . . . . . . 1147
33.5.8
Clear flag register (SAI_ACLRFR / SAI_BCLRFR) . . . . . . . . . . . . . . 1149
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33.5.9
Data register (SAI_ADR / SAI_BDR) . . . . . . . . . . . . . . . . . . . . . . . . . 1150
33.5.10 SAI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
34
SPDIF Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 1153
34.1
SPDIFRX interface introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1153
34.2
SPDIFRX main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1153
34.3
SPDIFRX functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1153
34.3.1
S/PDIF protocol (IEC-60958) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
34.3.2
SPDIFRX Decoder (SPDIFRX_DC) . . . . . . . . . . . . . . . . . . . . . . . . . 1156
34.3.3
SPDIFRX tolerance to clock deviation . . . . . . . . . . . . . . . . . . . . . . . . 1160
34.3.4
SPDIFRX Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1160
34.3.5
SPDIFRX Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
34.3.6
Data Reception Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1164
34.3.7
Dedicated Control Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
34.3.8
Reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
34.3.9
Clocking Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
34.3.10 Symbol clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
34.3.11 DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
34.3.12 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
34.3.13 Register Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
34.4
34.5
Programming Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1175
34.4.1
Initialization phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175
34.4.2
Handling of interrupts coming from SPDIFRX . . . . . . . . . . . . . . . . . . 1176
34.4.3
Handling of interrupts coming from DMA . . . . . . . . . . . . . . . . . . . . . . 1177
SPDIFRX interface registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1178
34.5.1
Control register (SPDIFRX_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1178
34.5.2
Interrupt mask register (SPDIFRX_IMR) . . . . . . . . . . . . . . . . . . . . . . 1181
34.5.3
Status register (SPDIFRX_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1182
34.5.4
Interrupt Flag Clear register (SPDIFRX_IFCR) . . . . . . . . . . . . . . . . . 1184
34.5.5
Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1185
34.5.6
Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1186
34.5.7
Data input register (SPDIFRX_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . 1187
34.5.8
Channel Status register (SPDIFRX_CSR) . . . . . . . . . . . . . . . . . . . . . 1188
34.5.9
Debug Information register (SPDIFRX_DIR) . . . . . . . . . . . . . . . . . . . 1189
34.5.10 SPDIFRX version register (SPDIFRX_VERR) . . . . . . . . . . . . . . . . . . 1190
34.5.11 SPDIFRX identification register (SPDIFRX_IDR) . . . . . . . . . . . . . . . 1190
34.5.12 SPDIFRX size identification register (SPDIFRX_SIDR) . . . . . . . . . . 1191
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34.5.13 SPDIFRX interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
35
SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . 1193
35.1
SDMMC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193
35.2
SDMMC bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1193
35.3
SDMMC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1195
35.4
35.3.1
SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
35.3.2
SDMMC APB2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1208
Card functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
35.4.1
Card identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1209
35.4.2
Card reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
35.4.3
Operating voltage range validation . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
35.4.4
Card identification process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1210
35.4.5
Block write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1211
35.4.6
Block read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
35.4.7
Stream access, stream write and stream read
(MultiMediaCard only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212
35.4.8
Erase: group erase and sector erase . . . . . . . . . . . . . . . . . . . . . . . . 1214
35.4.9
Wide bus selection or deselection . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
35.4.10 Protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1214
35.4.11 Card status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
35.4.12 SD status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
35.4.13 SD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1225
35.4.14 Commands and responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1226
35.5
35.6
32/1671
Response formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
35.5.1
R1 (normal response command) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
35.5.2
R1b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
35.5.3
R2 (CID, CSD register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
35.5.4
R3 (OCR register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
35.5.5
R4 (Fast I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
35.5.6
R4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
35.5.7
R5 (interrupt request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
35.5.8
R6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
SDIO I/O card-specific operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
35.6.1
SDIO I/O read wait operation by SDMMC_D2 signalling . . . . . . . . . . 1233
35.6.2
SDIO read wait operation by stopping SDMMC_CK . . . . . . . . . . . . . 1234
35.6.3
SDIO suspend/resume operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
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35.6.4
SDIO interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
35.7
HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1234
35.8
SDMMC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1235
35.8.1
SDMMC power control register (SDMMC_POWER) . . . . . . . . . . . . . 1235
35.8.2
SDMMC clock control register (SDMMC_CLKCR) . . . . . . . . . . . . . . 1235
35.8.3
SDMMC argument register (SDMMC_ARG) . . . . . . . . . . . . . . . . . . . 1237
35.8.4
SDMMC command register (SDMMC_CMD) . . . . . . . . . . . . . . . . . . 1237
35.8.5
SDMMC command response register (SDMMC_RESPCMD) . . . . . . 1238
35.8.6
SDMMC response 1..4 register (SDMMC_RESPx) . . . . . . . . . . . . . . 1238
35.8.7
SDMMC data timer register (SDMMC_DTIMER) . . . . . . . . . . . . . . . . 1239
35.8.8
SDMMC data length register (SDMMC_DLEN) . . . . . . . . . . . . . . . . . 1240
35.8.9
SDMMC data control register (SDMMC_DCTRL) . . . . . . . . . . . . . . . 1240
35.8.10 SDMMC data counter register (SDMMC_DCOUNT) . . . . . . . . . . . . . 1242
35.8.11 SDMMC status register (SDMMC_STA) . . . . . . . . . . . . . . . . . . . . . . 1242
35.8.12 SDMMC interrupt clear register (SDMMC_ICR) . . . . . . . . . . . . . . . . 1243
35.8.13 SDMMC mask register (SDMMC_MASK) . . . . . . . . . . . . . . . . . . . . . 1245
35.8.14 SDMMC FIFO counter register (SDMMC_FIFOCNT) . . . . . . . . . . . . 1247
35.8.15 SDMMC data FIFO register (SDMMC_FIFO) . . . . . . . . . . . . . . . . . . 1248
35.8.16 SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
36
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
36.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
36.2
bxCAN main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1251
36.3
bxCAN general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
36.4
36.5
36.3.1
CAN 2.0B active core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
36.3.2
Control, status and configuration registers . . . . . . . . . . . . . . . . . . . . 1252
36.3.3
Tx mailboxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
36.3.4
Acceptance filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
bxCAN operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
36.4.1
Initialization mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
36.4.2
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1254
36.4.3
Sleep mode (low-power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
36.5.1
Silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
36.5.2
Loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
36.5.3
Loop back combined with silent mode . . . . . . . . . . . . . . . . . . . . . . . . 1257
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RM0385
36.6
Behavior in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
36.7
bxCAN functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Transmission handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
36.7.2
Time triggered communication mode . . . . . . . . . . . . . . . . . . . . . . . . . 1259
36.7.3
Reception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
36.7.4
Identifier filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1261
36.7.5
Message storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
36.7.6
Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
36.7.7
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1267
36.8
bxCAN interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
36.9
CAN registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
36.9.1
Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
36.9.2
CAN control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1271
36.9.3
CAN mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1281
36.9.4
CAN filter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1288
36.9.5
bxCAN register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
USB on-the-go full-speed/high-speed (OTG_FS/OTG_HS) . . . . . . . 1296
37.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1296
37.2
USB_OTG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
37.2.1
General features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1298
37.2.2
Host-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.2.3
Peripheral-mode features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.3
USB_OTG Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
37.4
USB OTG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
37.5
37.6
34/1671
36.7.1
37.4.1
USB OTG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
37.4.2
OTG core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
37.4.3
Full-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
37.4.4
Embedded full speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1302
37.4.5
High-speed OTG PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
37.4.6
External Full-speed OTG PHY using the I2C interface . . . . . . . . . . . 1303
OTG dual role device (DRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
37.5.1
ID line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
37.5.2
HNP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
37.5.3
SRP dual role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1304
USB peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
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37.7
37.8
37.9
37.6.1
SRP-capable peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
37.6.2
Peripheral states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1306
37.6.3
Peripheral endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1307
USB host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1309
37.7.1
SRP-capable host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
37.7.2
USB host states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
37.7.3
Host channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312
37.7.4
Host scheduler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313
SOF trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
37.8.1
Host SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
37.8.2
Peripheral SOFs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1314
Power options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1315
37.10 Dynamic update of the OTG_HFIR register . . . . . . . . . . . . . . . . . . . . . 1315
37.11 USB data FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
37.11.1 Peripheral FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1317
37.11.2 Host FIFO architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1318
37.11.3 FIFO RAM allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1319
37.12 OTG_FS system performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
37.13 OTG_FS/OTG_HS interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1321
37.14 OTG_FS/OTG_HS control and status registers . . . . . . . . . . . . . . . . . . 1322
37.14.1 CSR memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323
37.15 OTG_FS/OTG_HS registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329
37.15.1 OTG control and status register (OTG_GOTGCTL) . . . . . . . . . . . . . 1329
37.15.2 OTG interrupt register (OTG_GOTGINT) . . . . . . . . . . . . . . . . . . . . . 1332
37.15.3 OTG AHB configuration register (OTG_GAHBCFG) . . . . . . . . . . . . . 1333
37.15.4 OTG USB configuration register (OTG_GUSBCFG) . . . . . . . . . . . . . 1335
37.15.5 OTG reset register (OTG_GRSTCTL) . . . . . . . . . . . . . . . . . . . . . . . . 1339
37.15.6 OTG core interrupt register (OTG_GINTSTS) . . . . . . . . . . . . . . . . . . 1341
37.15.7 OTG interrupt mask register (OTG_GINTMSK) . . . . . . . . . . . . . . . . . 1346
37.15.8 OTG_FS Receive status debug read/OTG status read and
pop registers (OTG_GRXSTSR/OTG_GRXSTSP) . . . . . . . . . . . . . . 1350
37.15.9 OTG Receive FIFO size register (OTG_GRXFSIZ) . . . . . . . . . . . . . . 1351
37.15.10 OTG Host non-periodic transmit FIFO size register
(OTG_HNPTXFSIZ)/Endpoint 0 Transmit FIFO size
(OTG_DIEPTXF0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1352
37.15.11 OTG non-periodic transmit FIFO/queue status register
(OTG_HNPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1353
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37.15.12 OTG I2C access register (OTG_GI2CCTL) . . . . . . . . . . . . . . . . . . . . 1353
37.15.13 OTG general core configuration register (OTG_GCCFG) . . . . . . . . . 1355
37.15.14 OTG core ID register (OTG_CID) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1355
37.15.15 OTG core LPM configuration register (OTG_GLPMCFG) . . . . . . . . . 1356
37.15.16 OTG Host periodic transmit FIFO size register
(OTG_HPTXFSIZ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
37.15.17 OTG device IN endpoint transmit FIFO size register
(OTG_DIEPTXFx) (x = 1..5[FS] /8[HS], where x is the
FIFO_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
37.15.18 Host-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1360
37.15.19 OTG Host configuration register (OTG_HCFG) . . . . . . . . . . . . . . . . . 1361
37.15.20 OTG Host frame interval register (OTG_HFIR) . . . . . . . . . . . . . . . . . 1361
37.15.21 OTG Host frame number/frame time remaining register
(OTG_HFNUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362
37.15.22 OTG_Host periodic transmit FIFO/queue status register
(OTG_HPTXSTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1363
37.15.23 OTG Host all channels interrupt register (OTG_HAINT) . . . . . . . . . . 1364
37.15.24 OTG Host all channels interrupt mask register
(OTG_HAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1365
37.15.25 OTG Host port control and status register (OTG_HPRT) . . . . . . . . . 1365
37.15.26 OTG Host channel-x characteristics register (OTG_HCCHARx)
(x = 0..15[HS] / 11[FS], where x = Channel_number) . . . . . . . . . . . . 1368
37.15.27 OTG Host channel-x split control register (OTG_HCSPLTx)
(x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1369
37.15.28 OTG Host channel-x interrupt register (OTG_HCINTx)
(x = 0..15[HS] / 11[FS], where x = Channel_number) . . . . . . . . . . . . 1370
37.15.29 OTG Host channel-x interrupt mask register (OTG_HCINTMSKx)
(x = 0..15[HS] / 11[FS], where x = Channel_number) . . . . . . . . . . . . 1371
37.15.30 OTG Host channel-x transfer size register (OTG_HCTSIZx)
(x = 0..15[HS] / 11[FS], where x = Channel_number) . . . . . . . . . . . . 1373
37.15.31 OTG Host channel-x DMA address register (OTG_HCDMAx)
(x = 0..15, where x = Channel_number) . . . . . . . . . . . . . . . . . . . . . . 1374
37.15.32 Device-mode registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1375
37.15.33 OTG device configuration register (OTG_DCFG) . . . . . . . . . . . . . . . 1375
37.15.34 OTG device control register (OTG_DCTL) . . . . . . . . . . . . . . . . . . . . 1376
37.15.35 OTG device status register (OTG_DSTS) . . . . . . . . . . . . . . . . . . . . . 1378
37.15.36 OTG device IN endpoint common interrupt mask register
(OTG_DIEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1379
37.15.37 OTG device OUT endpoint common interrupt mask register
(OTG_DOEPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1381
37.15.38 OTG device all endpoints interrupt register (OTG_DAINT) . . . . . . . . 1382
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37.15.39 OTG all endpoints interrupt mask register
(OTG_DAINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
37.15.40 OTG device VBUS discharge time register
(OTG_DVBUSDIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1383
37.15.41 OTG device VBUS pulsing time register
(OTG_DVBUSPULSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1384
37.15.42 OTG Device threshold control register (OTG_DTHRCTL) . . . . . . . . 1384
37.15.43 OTG device each endpoint interrupt register (OTG_DEACHINT) . . . 1385
37.15.44 OTG device IN endpoint FIFO empty interrupt mask register
(OTG_DIEPEMPMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
37.15.45 OTG device each endpoint interrupt register mask
(OTG_DEACHINTMSK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1386
37.15.46 OTG device control IN endpoint 0 control register
(OTG_DIEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387
37.15.47 OTG device endpoint-x control register (OTG_DIEPCTLx)
(x = 1..5[FS] / 0..8[HS], where x = Endpoint_number) . . . . . . . . . . . . 1388
37.15.48 OTG device control OUT endpoint 0 control register
(OTG_DOEPCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1390
37.15.49 OTG device endpoint-x control register (OTG_DOEPCTLx)
(x = 1..5[FS] /8[HS], where x = Endpoint_number) . . . . . . . . . . . . . . 1392
37.15.50 OTG device endpoint-x interrupt register (OTG_DIEPINTx)
(x = 0..5[FS] /8[HS], where x = Endpoint_number) . . . . . . . . . . . . . . 1394
37.15.51 OTG device endpoint-x interrupt register (OTG_DOEPINTx)
(x = 0..5[FS] /8[HS], where x = Endpoint_number) . . . . . . . . . . . . . . 1396
37.15.52 OTG device IN endpoint 0 transfer size register
(OTG_DIEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1397
37.15.53 OTG Device channel-x DMA address register (OTG_DIEPDMAx)
(x = 0..15, where x= Channel_number) . . . . . . . . . . . . . . . . . . . . . . . 1398
37.15.54 OTG Device channel-x DMA address register (OTG_DOEPDMAx)
(x = 0..15, where x= Channel_number) . . . . . . . . . . . . . . . . . . . . . . . 1398
37.15.55 OTG device OUT endpoint 0 transfer size register
(OTG_DOEPTSIZ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1399
37.15.56 OTG device IN endpoint-x transfer size register (OTG_DIEPTSIZx)
(x = 1..5[FS] /8[HS], where x= Endpoint_number) . . . . . . . . . . . . . . . 1399
37.15.57 OTG device IN endpoint transmit FIFO status register
(OTG_DTXFSTSx) (x = 0..5[FS] /8[HS], where
x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1400
37.15.58 OTG device OUT endpoint-x transfer size register
(OTG_DOEPTSIZx) (x = 1..5[FS] /8[HS],
where x = Endpoint_number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1401
37.15.59 OTG power and clock gating control register (OTG_PCGCCTL) . . . 1402
37.15.60 OTG_FS/OTG_HS register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
37.16 OTG_FS/OTG_HS programming model . . . . . . . . . . . . . . . . . . . . . . . 1416
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37.16.1 Core initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1416
37.16.2 Host initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
37.16.3 Device initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1417
37.16.4 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
37.16.5 Host programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1418
37.16.6 Device programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1450
37.16.7 Worst case response time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1470
37.16.8 OTG programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
38
Ethernet (ETH): media access control (MAC) with
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
38.1
Ethernet introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
38.2
Ethernet main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1479
MAC core features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1480
38.2.2
DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
38.2.3
PTP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1481
38.3
Ethernet pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
38.4
Ethernet functional description: SMI, MII and RMII . . . . . . . . . . . . . . . 1483
38.5
38.6
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38.2.1
38.4.1
Station management interface: SMI . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
38.4.2
Media-independent interface: MII . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
38.4.3
Reduced media-independent interface: RMII . . . . . . . . . . . . . . . . . . 1489
38.4.4
MII/RMII selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Ethernet functional description: MAC 802.3 . . . . . . . . . . . . . . . . . . . . . 1491
38.5.1
MAC 802.3 frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1491
38.5.2
MAC frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1495
38.5.3
MAC frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
38.5.4
MAC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
38.5.5
MAC filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
38.5.6
MAC loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
38.5.7
MAC management counters: MMC . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
38.5.8
Power management: PMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512
38.5.9
Precision time protocol (IEEE1588 PTP) . . . . . . . . . . . . . . . . . . . . . . 1515
Ethernet functional description: DMA controller operation . . . . . . . . . . 1521
38.6.1
Initialization of a transfer using DMA . . . . . . . . . . . . . . . . . . . . . . . . . 1522
38.6.2
Host bus burst access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
38.6.3
Host data buffer alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
38.6.4
Buffer size calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1523
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38.6.5
DMA arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
38.6.6
Error response to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
38.6.7
Tx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524
38.6.8
Rx DMA configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1536
38.6.9
DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1548
38.7
Ethernet interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
38.8
Ethernet register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
38.8.1
MAC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1550
38.8.2
MMC register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1570
38.8.3
IEEE 1588 time stamp registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1575
38.8.4
DMA register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582
38.8.5
Ethernet register maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
HDMI-CEC controller (HDMI-CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
39.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
39.2
HDMI-CEC controller main features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602
39.3
HDMI-CEC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
39.4
39.3.1
HDMI-CEC pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
39.3.2
HDMI-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
39.3.3
Message description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
39.3.4
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
39.4.1
39.5
SFT option bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
39.5.1
Bit error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
39.5.2
Message error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
39.5.3
Bit Rising Error (BRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
39.5.4
Short Bit Period Error (SBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
39.5.5
Long Bit Period Error (LBPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1608
39.5.6
Transmission Error Detection (TXERR) . . . . . . . . . . . . . . . . . . . . . . . 1610
39.6
HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1611
39.7
HDMI-CEC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
39.7.1
CEC control register (CEC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1612
39.7.2
CEC configuration register (CEC_CFGR) . . . . . . . . . . . . . . . . . . . . . 1613
39.7.3
CEC Tx data register (CEC_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . 1616
39.7.4
CEC Rx Data Register (CEC_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . 1616
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RM0385
39.7.5
CEC Interrupt and Status Register (CEC_ISR) . . . . . . . . . . . . . . . . . 1616
39.7.6
CEC interrupt enable register (CEC_IER) . . . . . . . . . . . . . . . . . . . . . 1618
39.7.7
HDMI-CEC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
40.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
40.2
Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1622
40.3
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . 1622
40.3.1
40.4
Mechanism to select the JTAG-DP or the SW-DP . . . . . . . . . . . . . . . 1623
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
40.4.1
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
40.4.2
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
40.4.3
Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . 1625
40.4.4
Using serial wire and releasing the unused debug pins as GPIOs . . 1626
40.5
STM32F75xxx and STM32F74xxx JTAG Debug Port connection . . . . 1626
40.6
ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
40.6.1
MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
40.6.2
Boundary scan Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
40.6.3
Cortex®-M7 with FPU Debug Port . . . . . . . . . . . . . . . . . . . . . . . . . . . 1628
40.6.4
Cortex®-M7 with FPU JEDEC-106 ID code . . . . . . . . . . . . . . . . . . . . 1629
40.7
JTAG debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
40.8
SW debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
40.9
40.8.1
SW protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
40.8.2
SW protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1631
40.8.3
SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . 1632
40.8.4
DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
40.8.5
SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
40.8.6
SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1634
AHB-AP (AHB access port) - valid for both JTAG-DP
and SW-DP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
40.10 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
40.11 Capability of the debugger host to connect under system reset . . . . . 1637
40.12 FPB (Flash patch breakpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1637
40.13 DWT (data watchpoint trigger) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
40.14 ITM (instrumentation trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . 1638
40.14.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1638
40/1671
DocID026670 Rev 6
RM0385
Contents
40.14.2 Time stamp packets, synchronization and overflow packets . . . . . . . 1638
40.15 ETM (Embedded trace macrocell) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
40.15.1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
40.15.2 Signal protocol, packet types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1640
40.15.3 Main ETM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
40.15.4 Configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
40.16 MCU debug component (DBGMCU) . . . . . . . . . . . . . . . . . . . . . . . . . . 1641
40.16.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . 1641
40.16.2 Debug support for timers, watchdog, bxCAN and I2C . . . . . . . . . . . . 1642
40.16.3 Debug MCU configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . 1642
40.16.4 DBGMCU_CR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1643
40.16.5 Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) . . . . . . . . 1644
40.16.6 Debug MCU APB2 Freeze register (DBGMCU_APB2_FZ) . . . . . . . . 1646
40.17 Pelican TPIU (trace port interface unit) . . . . . . . . . . . . . . . . . . . . . . . . 1647
40.17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
40.17.2 TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
40.17.3 TPIU formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1650
40.17.4 TPIU frame synchronization packets . . . . . . . . . . . . . . . . . . . . . . . . . 1650
40.17.5 Transmission of the synchronization frame packet . . . . . . . . . . . . . . 1650
40.17.6 Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
40.17.7 Asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
40.17.8 TRACECLKIN connection inside the
STM32F75xxx and STM32F74xxx . . . . . . . . . . . . . . . . . . . . . . . . . . 1651
40.17.9 TPIU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
40.17.10 Example of configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
40.18 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
41
42
Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
41.1
Unique device ID register (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1654
41.2
Flash size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1655
41.3
Package data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1656
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
DocID026670 Rev 6
41/1671
41
List of tables
RM0385
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
42/1671
STM32F75xxx and STM32F74xxx register boundary addresses . . . . . . . . . . . . . . . . . . . . 65
Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Flash memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Number of wait states according to CPU clock (HCLK) frequency . . . . . . . . . . . . . . . . . . . 74
Program/erase parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Access versus read protection level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
OTP area organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Flash register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . 101
Low-power mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Sleep-now entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Sleep-on-exit entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Stop operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Stop mode entry and exit (STM32F75xxx and STM32F74xxx) . . . . . . . . . . . . . . . . . . . . 114
Standby mode entry and exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
DMA1 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DMA2 request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Source and destination address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Source and destination address registers in double buffer mode (DBM=1) . . . . . . . . . . . 228
Packing/unpacking & endian behavior (bit PINC = MINC = 1) . . . . . . . . . . . . . . . . . . . . . 229
Restriction on NDT versus PSIZE and MSIZE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
FIFO threshold configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Possible DMA configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
Supported color mode in input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Alpha mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
Supported CLUT color mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
CLUT data order in system memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Supported color mode in output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Data order in memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
DMA2D interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
DMA2D register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
STM32F75xxx and STM32F74xxx vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
External interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . . 296
CRC internal input/output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
NOR/PSRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
NOR/PSRAM External memory address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
DocID026670 Rev 6
RM0385
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
List of tables
NAND memory mapping and timing registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
NAND bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
SDRAM bank selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
SDRAM address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
SDRAM address mapping with 8-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
SDRAM address mapping with 16-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
SDRAM address mapping with 32-bit data bus width. . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Programmable NOR/PSRAM access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Non-multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
16-bit multiplexed I/O NOR Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
Non-multiplexed I/Os PSRAM/SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
16-Bit multiplexed I/O PSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
NOR Flash/PSRAM: example of supported memories and transactions . . . . . . . . . . . . . 316
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
FMC_BWTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
FMC_BCRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
FMC_BTRx bit fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Programmable NAND Flash access parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
8-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
16-bit NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
Supported memories and transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
ECC result relevant bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
SDRAM signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
FMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
QUADSPI interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
QUADSPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
External trigger for regular channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
External trigger for injected channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
ADC global register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
ADC register map and reset values for each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
ADC register map and reset values (common ADC registers) . . . . . . . . . . . . . . . . . . . . . 457
DAC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
DocID026670 Rev 6
43/1671
47
List of tables
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
44/1671
RM0385
External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
DAC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
DCMI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
DCMI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Positioning of captured data bytes in 32-bit words (8-bit width) . . . . . . . . . . . . . . . . . . . . 483
Positioning of captured data bytes in 32-bit words (10-bit width) . . . . . . . . . . . . . . . . . . . 483
Positioning of captured data bytes in 32-bit words (12-bit width) . . . . . . . . . . . . . . . . . . . 484
Positioning of captured data bytes in 32-bit words (14-bit width) . . . . . . . . . . . . . . . . . . . 484
Data storage in monochrome progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . 490
Data storage in RGB progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Data storage in YCbCr progressive video format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Data storage in YCbCr progressive video format - Y extraction mode . . . . . . . . . . . . . . . 492
DCMI interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
DCMI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
Clock domain for each register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
LCD-TFT pins and signal interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Pixel Data mapping versus Color Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
LTDC interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
LTDC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
RNG register map and reset map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Number of cycles required to process each 128-bit block . . . . . . . . . . . . . . . . . . . . . . . . 544
Data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
CRYP register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
HASH register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607
Behavior of timer outputs versus BRK/BRK2 inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
Output control bits for complementary OCx and OCxN channels with break feature . . . . 688
TIM1 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
TIM8 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
TIM2/TIM3/TIM4/TIM5 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
TIMx internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808
TIM9/TIM12 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818
TIM10/TIM11/TIM13/TIM14 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . 821
TIM6/TIM7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835
STM32F75xxx and STM32F74xxx LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836
Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839
Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845
LPTIM external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852
LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856
IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871
RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875
RTC pin PI8 configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876
RTC pin PC2 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
RTC functions over modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877
Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890
DocID026670 Rev 6
RM0385
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
List of tables
Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 891
RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
STM32F75xxx and STM32F74xxx I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 918
Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922
I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925
I2C configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929
I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 940
Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 950
Examples of timings settings for fI2CCLK = 48 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953
SMBUS with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 956
Examples of TIMEOUTA settings for various I2CCLK frequencies
(max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
STM32F75xxx and STM32F74xxx USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Error calculation for programmed baud rates at fCK = 216 MHz
in both cases of oversampling by 8 (OVER8 = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Error calculation for programmed baud rates at fCK = 216 MHz
in both cases of oversampling by 16 (OVER8 = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . 1004
Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . 1005
Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1027
USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048
STM32F75xxx and STM32F74xxx SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . 1051
SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076
Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . 1089
I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1096
SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1109
External Synchronization Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
Example of possible audio frequency sampling range . . . . . . . . . . . . . . . . . . . . . . . . . . 1121
SOPD pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Parity bit calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Audio sampling frequency versus symbol rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1128
SAI interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1137
SAI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1151
Transition sequence for preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
Minimum SPDIFRX_CLK frequency versus audio sampling rate . . . . . . . . . . . . . . . . . . 1169
Spdifrx_ck_symb generation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Bit field property versus SPDIFRX state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
SPDIFRX interface register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
SDMMC I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1196
Command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Short response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
DocID026670 Rev 6
45/1671
47
List of tables
Table 201.
Table 202.
Table 203.
Table 204.
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
46/1671
RM0385
Long response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Command path status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202
Data token format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205
DPSM flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1206
Transmit FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Receive FIFO status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1207
Card status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1218
SD status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1221
Speed class code field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1222
Performance move field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
AU_SIZE field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Maximum AU size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1223
Erase size field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Erase timeout field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Erase offset field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1224
Block-oriented write commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1227
Block-oriented write protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
Erase commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
I/O mode commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1228
Lock card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
Application-specific commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1229
R1 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
R2 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1230
R3 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
R4 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
R4b response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1231
R5 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232
R6 response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1233
Response type and SDMMC_RESPx registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1239
SDMMC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1249
Transmit mailbox mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Receive mailbox mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
bxCAN register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292
OTG_HS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
OTG_FS speeds supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1297
USB_OTG Implementation for STM32F75/6xxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1299
Core global control and status registers (CSRs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323
Host-mode control and status registers (CSRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1324
Device-mode control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1326
Data FIFO (DFIFO) access register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1328
Power and clock gating control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 1329
TRDT values (FS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338
TRDT values (HS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1338
Minimum duration for soft disconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1378
OTG_FS/OTG_HS register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1403
Alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482
Management frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
Clock range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
TX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
RX interface signal encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1488
Frame statuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1504
Destination address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1510
DocID026670 Rev 6
RM0385
List of tables
Table 253. Source address filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1511
Table 254. Receive descriptor 0 - encoding for bits 7, 5 and 0 (normal descriptor
format only, EDFE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1543
Table 255. Time stamp snapshot dependency on registers bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 1577
Table 256. Ethernet register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1597
Table 257. HDMI pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
Table 258. Error handling timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
Table 259. TXERR timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
Table 260. HDMI-CEC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1611
Table 261. HDMI-CEC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1620
Table 262. SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
Table 263. Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624
Table 264. JTAG debug port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1629
Table 265. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . 1631
Table 266. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
Table 267. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
Table 268. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632
Table 269. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1633
Table 270. Cortex®-M7 with FPU AHB-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1635
Table 271. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1636
Table 272. Main ITM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1639
Table 273. Asynchronous TRACE pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Table 274. Synchronous TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1648
Table 275. Flexible TRACE pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1649
Table 276. Important TPIU registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652
Table 277. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1653
Table 278. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662
DocID026670 Rev 6
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47
List of figures
RM0385
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
48/1671
System architecture for STM32F75xxx and STM32F74xxx devices . . . . . . . . . . . . . . . . . 61
Flash memory interface connection inside system architecture
(STM32F75xxx and STM32F74xxx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
VDDUSB connected to VDD power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
VDDUSB connected to external independent power supply . . . . . . . . . . . . . . . . . . . . . . . 98
Backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Frequency measurement with TIM5 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . . 138
Frequency measurement with TIM11 in Input capture mode . . . . . . . . . . . . . . . . . . . . . . 139
Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Peripheral-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Memory-to-peripheral mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
FIFO structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
DMA2D block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
External interrupt/event controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
External interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
FMC block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
FMC memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Mode1 read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Mode1 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
ModeA read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
ModeA write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Mode2 and mode B read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Mode2 write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
ModeB write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
ModeC read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325
ModeC write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
ModeD read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
ModeD write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Muxed read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
Muxed write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
Asynchronous wait during a read access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
DocID026670 Rev 6
RM0385
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
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Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
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Figure 79.
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Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
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Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
List of figures
Asynchronous wait during a write access waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Wait configuration waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM) . . . . . . . . . . . 337
Synchronous multiplexed write mode waveforms - PSRAM (CRAM). . . . . . . . . . . . . . . . 339
NAND Flash controller waveforms for common memory access . . . . . . . . . . . . . . . . . . . 351
Access to non ‘CE don’t care’ NAND-Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Burst write SDRAM access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
Burst read SDRAM access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0) . . . . . . . . . . . . 364
Read access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Write access crossing row boundary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Self-refresh mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
QUADSPI block diagram when dual-flash mode is disabled . . . . . . . . . . . . . . . . . . . . . . 381
QUADSPI block diagram when dual-flash mode is enabled. . . . . . . . . . . . . . . . . . . . . . . 382
An example of a read command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
An example of a DDR command in quad mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
nCS when CKMODE = 0 (T = CLK period). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
nCS when CKMODE = 1 in SDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 394
nCS when CKMODE = 1 in DDR mode (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . 395
nCS when CKMODE = 1 with an abort (T = CLK period) . . . . . . . . . . . . . . . . . . . . . . . . . 395
Single ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
ADC1 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
ADC2 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
ADC3 connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Analog watchdog’s guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Injected conversion latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
Right alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Left alignment of 12-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Left alignment of 6-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Multi ADC block diagram(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Injected simultaneous mode on 4 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . . 430
Injected simultaneous mode on 4 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . . 430
Regular simultaneous mode on 16 channels: dual ADC mode . . . . . . . . . . . . . . . . . . . . 431
Regular simultaneous mode on 16 channels: triple ADC mode . . . . . . . . . . . . . . . . . . . . 431
Interleaved mode on 1 channel in continuous conversion mode: dual ADC mode. . . . . . 432
Interleaved mode on 1 channel in continuous conversion mode: triple ADC mode . . . . . 433
Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Alternate trigger: 4 injected channels (each ADC) in discontinuous mode . . . . . . . . . . . . 434
Alternate trigger: injected group of each ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
Alternate + regular simultaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Case of trigger occurring during injected conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 437
DAC channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
DAC output buffer connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 462
DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 464
DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
DocID026670 Rev 6
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List of figures
Figure 100.
Figure 101.
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Figure 109.
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Figure 111.
Figure 112.
Figure 113.
Figure 114.
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Figure 120.
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Figure 136.
Figure 137.
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Figure 141.
Figure 142.
Figure 143.
Figure 144.
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Figure 146.
Figure 147.
Figure 148.
Figure 149.
Figure 150.
Figure 151.
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RM0385
DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 465
DCMI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
Top-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
DCMI signal waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
Frame capture waveforms in snapshot mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Frame capture waveforms in continuous grab mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Coordinates and size of the window after cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488
Data capture waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
Pixel raster scan order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
LTDC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
LCD-TFT synchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Layer window programmable parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Blending two layers with background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539
Cryptographic processor block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
DES/TDES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
DES/TDES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
DES/TDES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
DES/TDES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
AES-ECB mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
AES-ECB mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
AES-CBC mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
AES-CBC mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
AES-CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
AES-CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
Initial counter block structure for the Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
64-bit block construction according to DATATYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
Initialization vectors use in the TDES-CBC encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
HASH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588
Bit, byte and half-word swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590
HASH interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
Advanced-control timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 612
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 612
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615
Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) . . . . . 616
Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) . . . . . . . . 616
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619
Counter timing diagram, update event when repetition counter is not used . . . . . . . . . . . 620
Counter timing diagram, internal clock divided by 1, TIMx_ARR = 0x6 . . . . . . . . . . . . . . 621
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622
Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 622
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623
Counter timing diagram, update event with ARPE=1 (counter underflow) . . . . . . . . . . . . 623
DocID026670 Rev 6
RM0385
Figure 152.
Figure 153.
Figure 154.
Figure 155.
Figure 156.
Figure 157.
Figure 158.
Figure 159.
Figure 160.
Figure 161.
Figure 162.
Figure 163.
Figure 164.
Figure 165.
Figure 166.
Figure 167.
Figure 168.
Figure 169.
Figure 170.
Figure 171.
Figure 172.
Figure 173.
Figure 174.
Figure 175.
Figure 176.
Figure 177.
Figure 178.
Figure 179.
Figure 180.
Figure 181.
Figure 182.
Figure 183.
Figure 184.
Figure 185.
Figure 186.
Figure 187.
Figure 188.
Figure 189.
Figure 190.
Figure 191.
Figure 192.
Figure 193.
Figure 194.
Figure 195.
Figure 196.
Figure 197.
Figure 198.
Figure 199.
Figure 200.
Figure 201.
Figure 202.
Figure 203.
List of figures
Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 624
Update rate examples depending on mode and TIMx_RCR register settings . . . . . . . . . 625
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 627
TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629
Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 631
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
Output stage of capture/compare channel (channel 1, idem ch. 2 and 3) . . . . . . . . . . . . 632
Output stage of capture/compare channel (channel 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 633
Output stage of capture/compare channel (channel 5, idem ch. 6) . . . . . . . . . . . . . . . . . 633
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 641
Combined PWM mode on channel 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
3-phase combined PWM signals with multiple trigger pulses per period . . . . . . . . . . . . . 643
Complementary output with dead-time insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Dead-time waveforms with delay greater than the negative pulse . . . . . . . . . . . . . . . . . . 644
Dead-time waveforms with delay greater than the positive pulse. . . . . . . . . . . . . . . . . . . 645
Break and Break2 circuitry overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647
Various output behavior in response to a break event on BRK (OSSI = 1) . . . . . . . . . . . 649
PWM output state following BRK and BRK2 pins assertion (OSSI=1) . . . . . . . . . . . . . . . 650
PWM output state following BRK assertion (OSSI=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 651
Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652
6-step generation, COM example (OSSR=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653
Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654
Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656
Example of counter operation in encoder interface mode. . . . . . . . . . . . . . . . . . . . . . . . . 657
Example of encoder interface mode with TI1FP1 polarity inverted. . . . . . . . . . . . . . . . . . 658
Measuring time interval between edges on 3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659
Example of Hall sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662
Control circuit in Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 665
General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 707
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 707
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 710
Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 711
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
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Figure 204. Counter timing diagram, Update event when repetition counter
is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Figure 205. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 715
Figure 206. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
Figure 207. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 716
Figure 208. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
Figure 209. Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 717
Figure 210. Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 718
Figure 211. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 719
Figure 212. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Figure 213. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Figure 214. External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Figure 215. Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Figure 216. Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 723
Figure 217. Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
Figure 218. Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 724
Figure 219. PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726
Figure 220. Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728
Figure 221. Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Figure 222. Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731
Figure 223. Generation of 2 phase-shifted PWM signals with 50% duty cycle . . . . . . . . . . . . . . . . . . 732
Figure 224. Combined PWM mode on channels 1 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733
Figure 225. Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734
Figure 226. Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735
Figure 227. Retriggerable one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737
Figure 228. Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 738
Figure 229. Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 739
Figure 230. Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Figure 231. Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
Figure 232. Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
Figure 233. Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Figure 234. Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
Figure 235. Gating TIM with OC1REF of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744
Figure 236. Gating TIM with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745
Figure 237. Triggering TIM with update of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 238. Triggering TIM with Enable of TIM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746
Figure 239. Triggering TIM3 and TIM2 with TIM3 TI1 input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 240. General-purpose timer block diagram (TIM9/TIM12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775
Figure 241. General-purpose timer block diagram (TIM10/TIM11/TIM13/TIM14) . . . . . . . . . . . . . . . . 776
Figure 242. Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 778
Figure 243. Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 778
Figure 244. Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779
Figure 245. Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 246. Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780
Figure 247. Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 248. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781
Figure 249. Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
Figure 250. Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 251. TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783
Figure 252. Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784
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Figure 253.
Figure 254.
Figure 255.
Figure 256.
Figure 257.
Figure 258.
Figure 259.
Figure 260.
Figure 261.
Figure 262.
Figure 263.
Figure 264.
Figure 265.
Figure 266.
Figure 267.
Figure 268.
Figure 269.
Figure 270.
Figure 271.
Figure 272.
Figure 273.
Figure 274.
Figure 275.
Figure 276.
Figure 277.
Figure 278.
Figure 279.
Figure 280.
Figure 281.
Figure 282.
Figure 283.
Figure 284.
Figure 285.
Figure 286.
Figure 287.
Figure 288.
Figure 289.
Figure 290.
Figure 291.
Figure 292.
Figure 293.
Figure 294.
Figure 295.
Figure 296.
Figure 297.
Figure 298.
Figure 299.
Figure 300.
Figure 301.
List of figures
Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 785
Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785
Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 786
PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788
Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Combined PWM mode on channel 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792
Example of one pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795
Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796
Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 825
Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 825
Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826
Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
Counter timing diagram, update event when ARPE=1 (TIMx_ARR
preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 830
Low-power timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837
Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838
LPTIM output waveform, Single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 840
LPTIM output waveform, Single counting mode configuration
and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 841
Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843
Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846
Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857
Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874
I2C block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919
I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 921
Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923
I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926
Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927
Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 933
Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 934
Transfer bus diagrams for I2C slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935
Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 936
Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 937
Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 937
Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 941
10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942
DocID026670 Rev 6
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List of figures
Figure 302.
Figure 303.
Figure 304.
Figure 305.
Figure 306.
Figure 307.
Figure 308.
Figure 309.
Figure 310.
Figure 311.
Figure 312.
Figure 313.
Figure 314.
Figure 315.
Figure 316.
Figure 317.
Figure 318.
Figure 319.
Figure 320.
Figure 321.
Figure 322.
Figure 323.
Figure 324.
Figure 325.
Figure 326.
Figure 327.
Figure 328.
Figure 329.
Figure 330.
Figure 331.
Figure 332.
Figure 333.
Figure 334.
Figure 335.
Figure 336.
Figure 337.
Figure 338.
Figure 339.
Figure 340.
Figure 341.
Figure 342.
Figure 343.
Figure 344.
Figure 345.
Figure 346.
Figure 347.
Figure 348.
Figure 349.
Figure 350.
Figure 351.
Figure 352.
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RM0385
Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . 943
Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 944
Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . . 947
Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 948
Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954
Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 958
Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 958
Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 960
Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 961
Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962
Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969
USART block diagram
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990
Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994
TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . 1011
Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . 1012
USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1022
Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1023
Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1025
RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1026
USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1028
SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053
Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054
Simplex single master/single slave application (master in transmit-only/
slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1056
Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057
Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1058
Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1059
Data alignment when data length is not equal to 8-bit or 16-bit . . . . . . . . . . . . . . . . . . . 1060
Packing data in FIFO for transmission and reception . . . . . . . . . . . . . . . . . . . . . . . . . . 1064
Master full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1067
Slave full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1068
DocID026670 Rev 6
RM0385
Figure 353.
Figure 354.
Figure 355.
Figure 356.
Figure 357.
Figure 358.
Figure 359.
Figure 360.
Figure 361.
Figure 362.
Figure 363.
Figure 364.
Figure 365.
Figure 366.
Figure 367.
Figure 368.
Figure 369.
Figure 370.
Figure 371.
Figure 372.
Figure 373.
Figure 374.
Figure 375.
Figure 376.
Figure 377.
Figure 378.
Figure 379.
Figure 380.
Figure 381.
Figure 382.
Figure 383.
Figure 384.
Figure 385.
Figure 386.
Figure 387.
Figure 388.
Figure 389.
Figure 390.
Figure 391.
Figure 392.
Figure 393.
Figure 394.
Figure 395.
Figure 396.
Figure 397.
Figure 398.
Figure 399.
Figure 400.
Figure 401.
Figure 402.
Figure 403.
List of figures
Master full-duplex communication with CRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
Master full-duplex communication in packed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1070
NSSP pulse generation in Motorola SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1073
TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1074
I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1077
Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1079
I2S Philips protocol waveforms (16/32-bit full accuracy). . . . . . . . . . . . . . . . . . . . . . . . . 1080
I2S Philips standard waveforms (24-bit frame) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1080
Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081
I2S Philips standard (16-bit extended to 32-bit packet frame) . . . . . . . . . . . . . . . . . . . . 1081
Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . 1081
MSB Justified 16-bit or 32-bit full-accuracy length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
MSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1082
MSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
LSB justified 16-bit or 32-bit full-accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
LSB justified 24-bit frame length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083
Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
LSB justified 16-bit extended to 32-bit packet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084
Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . 1085
PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085
PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . 1086
Start sequence in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087
Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1088
Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
Audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115
FS role is start of frame + channel side identification (FSDEF = TRIS = 1) . . . . . . . . . . 1117
FS role is start of frame (FSDEF = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1118
Slot size configuration with FBOFF = 0 in SAI_xSLOTR . . . . . . . . . . . . . . . . . . . . . . . . 1119
First bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
Audio block clock generator overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1120
AC’97 audio frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1124
Example of typical AC’97 configuration on devices featuring at least
2 embedded SAIs (three external AC’97 decoders) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
SPDIF format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
SAI_xDR register ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1127
Data companding hardware in an audio block in the SAI . . . . . . . . . . . . . . . . . . . . . . . . 1130
Tristate strategy on SD output line on an inactive slot . . . . . . . . . . . . . . . . . . . . . . . . . . 1132
Tristate on output data line in a protocol like I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133
Overrun detection error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
FIFO underrun event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1134
SPDIFRX block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
S/PDIF Sub-Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1154
S/PDIF block format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
S/PDIF Preambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155
Channel coding example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1156
SPDIFRX_DC Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
Noise filtering and Edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1157
Thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1159
Synchronization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1161
DocID026670 Rev 6
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List of figures
Figure 404.
Figure 405.
Figure 406.
Figure 407.
Figure 408.
Figure 409.
Figure 410.
Figure 411.
Figure 412.
Figure 413.
Figure 414.
Figure 415.
Figure 416.
Figure 417.
Figure 418.
Figure 419.
Figure 420.
Figure 421.
Figure 422.
Figure 423.
Figure 424.
Figure 425.
Figure 426.
Figure 427.
Figure 428.
Figure 429.
Figure 430.
Figure 431.
Figure 432.
Figure 433.
Figure 434.
Figure 435.
Figure 436.
Figure 437.
Figure 438.
Figure 439.
Figure 440.
Figure 441.
Figure 442.
Figure 443.
Figure 444.
Figure 445.
Figure 446.
Figure 447.
Figure 448.
Figure 449.
Figure 450.
Figure 451.
Figure 452.
Figure 453.
Figure 454.
Figure 455.
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Synchronization process scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1162
SPDIFRX States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
SPDIFRX_DR register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165
Channel/User data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1166
S/PDIF overrun error when RXSTEO = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1168
S/PDIF overrun error when RXSTEO = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
SPDIFRX interface interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
“No response” and “no data” operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
(Multiple) block read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
(Multiple) block write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1194
Sequential read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
Sequential write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
SDMMC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195
SDMMC adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1197
Control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1198
SDMMC_CK clock dephasing (BYPASS = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
SDMMC adapter command path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1199
Command path state machine (SDMMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1200
SDMMC command transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1201
Data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1203
Data path state machine (DPSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1204
CAN network topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1252
Dual CAN block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1253
bxCAN operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1255
bxCAN in silent mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
bxCAN in loop back mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1256
bxCAN in combined mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257
Transmit mailbox states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1259
Receive FIFO states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1260
Filter bank scale configuration - register organization . . . . . . . . . . . . . . . . . . . . . . . . . . 1263
Example of filter numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1264
Filtering mechanism - example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1265
CAN error state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1266
Bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1268
CAN frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1269
Event flags and interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1270
Can mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282
OTG full-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1300
OTG high-speed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1301
OTG_FS A-B device connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1303
USB_FS peripheral-only connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1305
USB_FS host-only connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1310
SOF connectivity (SOF trigger output to TIM and ITR1 connection) . . . . . . . . . . . . . . . 1314
Updating OTG_HFIR dynamically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1316
Device-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . 1317
Host-mode FIFO address mapping and AHB FIFO access mapping . . . . . . . . . . . . . . . 1318
Interrupt hierarchy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322
Transmit FIFO write task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420
Receive FIFO read task . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421
Normal bulk/control OUT/SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1423
Bulk/control IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1427
Normal interrupt OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1430
DocID026670 Rev 6
RM0385
Figure 456.
Figure 457.
Figure 458.
Figure 459.
Figure 460.
Figure 461.
Figure 462.
Figure 463.
Figure 464.
Figure 465.
Figure 466.
Figure 467.
Figure 468.
Figure 469.
Figure 470.
Figure 471.
Figure 472.
Figure 473.
Figure 474.
Figure 475.
Figure 476.
Figure 477.
Figure 478.
Figure 479.
Figure 480.
Figure 481.
Figure 482.
Figure 483.
Figure 484.
Figure 485.
Figure 486.
Figure 487.
Figure 488.
Figure 489.
Figure 490.
Figure 491.
Figure 492.
Figure 493.
Figure 494.
Figure 495.
Figure 496.
Figure 497.
Figure 498.
Figure 499.
Figure 500.
Figure 501.
Figure 502.
Figure 503.
Figure 504.
Figure 505.
Figure 506.
Figure 507.
List of figures
Normal interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1434
Isochronous OUT transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1436
Isochronous IN transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1439
Normal bulk/control OUT/SETUP transactions - DMA . . . . . . . . . . . . . . . . . . . . . . . . . . 1441
Normal bulk/control IN transaction - DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1443
Normal interrupt OUT transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1444
Normal interrupt IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1445
Normal isochronous OUT transaction - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1446
Normal isochronous IN transactions - DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1447
Receive FIFO packet read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1453
Processing a SETUP packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1455
Bulk OUT transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1461
TRDT max timing case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472
A-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1473
B-device SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1474
A-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1475
B-device HNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1477
ETH block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1483
SMI interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1484
MDIO timing and frame structure - Write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1485
MDIO timing and frame structure - Read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1486
Media independent interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1487
MII clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
Reduced media-independent interface signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1489
RMII clock sources- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1490
Address field format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492
MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
Tagged MAC frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1494
Transmission bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Transmission with no collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1501
Transmission with collision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
Frame transmission in MMI and RMII modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502
Receive bit order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1506
Reception with no error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Reception with errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
Reception with false carrier indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1507
MAC core interrupt masking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1508
Wakeup frame filter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1513
Networked time synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516
System time update using the Fine correction method. . . . . . . . . . . . . . . . . . . . . . . . . . 1518
PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1520
PPS output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1521
Descriptor ring and chain structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522
TxDMA operation in default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1526
TxDMA operation in OSF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1528
Normal transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1529
Enhanced transmit descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1535
Receive DMA operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1538
Normal Rx DMA descriptor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1540
Enhanced receive descriptor field format with IEEE1588 time stamp enabled. . . . . . . . 1546
Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1549
DocID026670 Rev 6
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List of figures
RM0385
Figure 508.
Figure 509.
Figure 510.
Figure 511.
Figure 512.
Figure 513.
Figure 514.
Figure 515.
Figure 516.
Figure 517.
Figure 518.
Figure 519.
Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR). . . . . . . . . . . 1560
HDIM-CEC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1603
Message structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1604
Bit timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
Signal free time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1605
Arbitration phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
SFT of three nominal bit periods. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1606
Error bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1607
Error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1609
TXERR detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1610
Block diagram of STM32 MCU and Cortex®-M7 with FPU -level
debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1621
Figure 520. SWJ debug port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623
Figure 521. JTAG Debug Port connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1627
Figure 522. TPIU block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1647
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Documentation conventions
1
Documentation conventions
1.1
List of abbreviations for registers
The following abbreviations are used in register descriptions:
read/write (rw)
Software can read and write to this bit.
read-only (r)
Software can only read this bit.
write-only (w)
Software can only write to this bit. Reading this bit returns the reset value.
read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the
bit value.
read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the
bit value.
read/clear by read Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing this bit
(rc_r)
has no effect on the bit value.
read/set (rs)
Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value.
Reserved (Res.)
Reserved bit, must be kept at reset value.
DocID026670 Rev 6
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Documentation conventions
1.2
RM0385
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
•
The CPU core integrates two debug ports:
–
JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
–
SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols, please refer to the Cortex®-M7 Technical
Reference Manual.
1.3
•
Word: data of 32-bit length.
•
Half-word: data of 16-bit length.
•
Byte: data of 8-bit length.
•
Double word: data of 64-bit length.
•
IAP (in-application programming): IAP is the ability to re-program the Flash memory
of a microcontroller while the user program is running.
•
ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the
device is mounted on the user application board.
•
Option bytes: product configuration bits stored in the Flash memory.
•
AHB: advanced high-performance bus.
•
AHBS: AHB Slave bus.
•
AXIM: AXI master bus.
•
ITCM: Instruction Tighly Coupled Memory.
•
DTCM: Data Tighly Coupled Memory.
•
CPU: refers to the Cortex®-M7 core.
Peripheral availability
For peripheral availability and number across all sales types, please refer to the particular
device datasheet.
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RM0385
System and memory overview
2
System and memory overview
2.1
System architecture
The main system architecture is based on 2 sub-systems:
•
•
An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
–
1x AXI to 64-bit AHB bridge connected to the embedded flash
–
3x AXI to 32bit AHB bridge connected to AHB bus matrix
A multi-AHB Bus-Matrix
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System and memory overview
RM0385
The multi-AHB Bus-Matrix interconnects all the masters and slaves and it consists on:
–
32-bit multi-AHB Bus-Matrix
–
64-bit multi-AHB Bus-Matrix: It interconnects the 64-bit AHB bus from CPU
through the AXI to AHB bridge and the 32-bit AHB bus from GP DMAs and
peripheral DMAs upsized to 64-bit to the internal flash.
The multi AHB bus matrix interconnects:
•
•
2.1.1
12 bus masters:
–
3x32-bit AHB bus Cortex®-M7 AXI Master bus 64-bits, splitted 4 masters through
the AXI to AHB bridge.
–
1x64-bit AHB bus connected to the embedded flash
–
Cortex® -M7 AHB Peripherals bus
–
DMA1 memory bus
–
DMA2 memory bus
–
DMA2 peripheral bus
–
Ethernet DMA bus
–
USB OTG HS DMA bus
–
LCD Controller DMA-bus
–
Chrom-Art Accelerator™ (DMA2D) memory bus
Eight bus slaves:
–
the embedded Flash on AHB bus (for Flash read/write access, for code execution
and data access)
–
Cortex®-M7 AHBS slave interface for DMAs data transfer on DTCM RAM only.
–
Main internal SRAM1 (240 KB)
–
Auxiliary internal SRAM2 (16 KB)
–
AHB1peripherals including AHB to APB bridges and APB peripherals
–
AHB2 peripherals including AHB to APB bridges and APB peripherals
–
FMC
–
Quad SPI
Multi AHB BusMatrix
The multi AHB BusMatrix manages the access arbitration between masters. The arbitration
uses a round-robin algorithm.
It provides access from a master to a slave, enabling concurrent access and efficient
operation even when several high-speed peripherals work simultaneously.
The DTCM and ITCM RAMs (tightly coupled memories) are not part of the bus matrix.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave bus of the CPU.
The instruction TCM RAM is reserved only for CPU. it is accessed at CPU clock speed with
0 wait states. The architecture is shown in Figure 1.
2.1.2
AHB/APB bridges (APB)
The two AHB/APB bridges, APB1 and APB2, provide full synchronous connections between
the AHB and the two APB buses, allowing flexible selection of the peripheral frequency.
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System and memory overview
Refer to the device datasheets for more details on APB1 and APB2 maximum frequencies,
and to Table 1 for the address mapping of AHB and APB peripherals.
After each device reset, all peripheral clocks are disabled (except for the SRAM, DTCM,
ITCM RAM and Flash memory interface). Before using a peripheral you have to enable its
clock in the RCC_AHBxENR or RCC_APBxENR register.
Note:
When a 16- or an 8-bit access is performed on an APB register, the access is transformed
into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector.
2.1.3
CPU AXIM bus
This bus connects the Instruction and data bus of the Cortex®-M7 with FPU core to the
multi-AHB Bus-Matrix through AXI to AHB bridge. There are 4 AXI bus accesses:
2.1.4
–
CPU AXI bus access 1: The target of this AXI bus is the external memory FMC
containing code or data. For the NAND Bank mapped at address 0x8000 0000 to
0x8FFF FFFF, the MPU memory attribute for this space must be reconfigured by
software to Device.
–
CPU AXI bus access 2: The target of this AXI bus is the external memory Quad
SPI containing code or data.
–
CPU AXI bus access 3: The target of this AXI bus is the internal SRAMs (SRAM1
and SRAM2) containing code or data.
–
CPU AXI bus access 4: The target of this AXI bus is the embedded Flash mapped
on AXI interface containing code or data.
ITCM bus
This bus is used by the Cortex®-M7 for instruction fetches and data access on the
embedded flash mapped on ITCM interface and instruction fetches only on ITCM RAM.
2.1.5
DTCM bus
This bus is used by the Cortex®-M7 for data access on the DTCM RAM. It can be also used
for instruction fetches.
2.1.6
CPU AHBS bus
This bus connects the AHB Slave bus of the Cortex®-M7 to the BusMatrix. This bus is used
by DMAs and Peripherals DMAs for Data transfer on DTCM RAM only.
The ITCM bus is not accessible on AHBS. So the DMA data transfer to/from ITCM RAM is
not supported. For DMA transfer to/from Flash on ITCM interface, all the transfers are
forced through AHB bus
2.1.7
AHB peripheral bus
This bus connects the AHB Peripheral bus of the Cortex®-M7 to the BusMatrix. This bus is
used by the core to perform all data accesses to peripherals.
The target of this bus is the AHB1 peripherals including the APB peripherals and the AHB2
peripherals.
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2.1.8
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DMA memory bus
This bus connects the DMA memory bus master interface to the BusMatrix. It is used by the
DMA to perform transfer to/from memories. The targets of this bus are data memories:
internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7) internal Flash
memory and external memories through the FMC or Quad SPI.
2.1.9
DMA peripheral bus
This bus connects the DMA peripheral master bus interface to the BusMatrix. This bus is
used by the DMA to access AHB peripherals or to perform memory-to-memory transfers.
The targets of this bus are the AHB and APB peripherals plus data memories: internal
SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7) internal Flash memory
and external memories through the FMC or Quad SPI.
2.1.10
Ethernet DMA bus
This bus connects the Ethernet DMA master interface to the BusMatrix. This bus is used by
the Ethernet DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7)
internal Flash memory, and external memories through the FMC or Quad SPI.
2.1.11
USB OTG HS DMA bus
This bus connects the USB OTG HS DMA master interface to the BusMatrix. This bus is
used by the USB OTG DMA to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7),
internal Flash memory, and external memories through the FMC or Quad SPI.
2.1.12
LCD-TFT controller DMA bus
This bus connects the LCD controller DMA master interface to the BusMatrix. It is used by
the LCD-TFT DMA to load data from a memory. The targets of this bus are data memories:
internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7), external
memories through FMC or Quad SPI, and internal Flash memory.
2.1.13
DMA2D bus
This bus connect the DMA2D master interface to the BusMatrix. This bus is used by the
DMA2D graphic Accelerator to load/store data to a memory. The targets of this bus are data
memories: internal SRAM1, SRAM2 and DTCM (through the AHBS bus of Cortex®-M7),
external memories through FMC or Quad SPI, and internal Flash memory.
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2.2
Memory organization
2.2.1
Introduction
Program memory, data memory, registers and I/O ports are organized within the same linear
4-Gbyte address space.
The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word
is considered the word’s least significant byte and the highest numbered byte the most
significant.
The addressable memory space is divided into 8 main blocks, of 512 Mbytes each.
All the memory areas that are not allocated to on-chip memories and peripherals are
considered “Reserved”. For the detailed mapping of available memory and register areas,
please refer to Memory map and register boundary addresses and peripheral sections.
2.2.2
Memory map and register boundary addresses
See the datasheet corresponding to your device for a comprehensive diagram of the
memory map.
The following table gives the boundary addresses of the peripherals available in the
devices.
Table 1. STM32F75xxx and STM32F74xxx register boundary addresses
Boundary address
Peripheral
Bus
Register map
0xA000 1000 - 0xA0001FFF
QuadSPI Control
Register
AHB3
0xA000 0000 - 0xA000 0FFF
FMC control register
0x5006 0800 - 0x5006 0BFF
RNG
Section 19.4.4: RNG register map on page 543
0x5006 0400 - 0x5006 07FF
HASH
Section 21.5.8: HASH register map on page 607
0x5006 0000 - 0x5006 03FF
CRYP
0x5005 0000 - 0x5005 03FF
DCMI
Section 17.8.12: DCMI register map on page 503
0x5000 0000 - 0x5003 FFFF
USB OTG FS
Section 37.15.60: OTG_FS/OTG_HS register map
on page 1403
Section 14.5.14: QUADSPI register map on
page 409
Section 13.8: FMC register map on page 378
AHB2
Section 20.6.12: CRYP register map on page 585
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Table 1. STM32F75xxx and STM32F74xxx register boundary addresses (continued)
Boundary address
Peripheral
0x4004 0000 - 0x4007 FFFF
USB OTG HS
Bus
Register map
Section 37.15.60: OTG_FS/OTG_HS register map
on page 1403
0x4002 B000 - 0x4002 BBFF Chrom-ART (DMA2D)
Section 9.5.21: DMA2D register map on page 283
0x4002 8000 - 0x4002 93FF
ETHERNET MAC
Section 38.8.5: Ethernet register maps on
page 1597
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
Flash interface
register
0x4002 3800 - 0x4002 3BFF
RCC
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2800 - 0x4002 2BFF
GPIOK
0x4002 2400 - 0x4002 27FF
GPIOJ
0x4002 2000 - 0x4002 23FF
GPIOI
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0x4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
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Section 8.5.11: DMA register map on page 249
Section 5.3.27: RCC register map on page 192
Section 3.7.8: Flash interface register map
Section 5.3.27: RCC register map on page 192
AHB1
Section 12.4.6: CRC register map on page 302
Section 6.4.11: GPIO register map on page 210
Section 6.4.11: GPIO register map on page 210
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Table 1. STM32F75xxx and STM32F74xxx register boundary addresses (continued)
Boundary address
Peripheral
Bus
Register map
0x4001 6800 - 0x4001 6BFF
LCD-TFT
0x4001 5C00 - 0x4001 5FFF
SAI2
Section : on page 1151
0x4001 5800 - 0x4001 5BFF
SAI1
Section : on page 1151
0x4001 5400 - 0x4001 57FF
SPI6
0x4001 5000 - 0x4001 53FF
SPI5
Section 32.9.10: SPI/I2S register map on
page 1109
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
Section 24.4.13: TIM9/TIM12 register map on
page 810
0x4001 3C00 - 0x4001 3FFF
EXTI
Section 11.9.7: EXTI register map on page 296
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4
Section 32.9.10: SPI/I2S register map on
page 1109
0x4001 3000 - 0x4001 33FF
SPI1
Section 32.9.10: SPI/I2S register map on
page 1109
0x4001 2C00 - 0x4001 2FFF
SDMMC1
Section 35.8.16: SDMMC register map on
page 1249
Section 18.7.26: LTDC register map on page 536
Section 24.5.12: TIM10/TIM11/TIM13/TIM14
register map on page 820
APB2
Section 7.2.8: SYSCFG register maps on
page 217
0x4001 2000 - 0x4001 23FF ADC1 - ADC2 - ADC3
Section 15.13.18: ADC register map on page 455
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
Section 31.8.12: USART register map on
page 1048
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
Section 22.4.24: TIM1 register map on page 700
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Table 1. STM32F75xxx and STM32F74xxx register boundary addresses (continued)
Boundary address
Peripheral
Bus
Register map
0x4000 7C00 - 0x4000 7FFF
UART8
0x4000 7800 - 0x4000 7BFF
UART7
0x4000 7400 - 0x4000 77FF
DAC
Section 16.5.15: DAC register map on page 479
0x4000 7000 - 0x4000 73FF
PWR
Section 4.4.4: PWR power control register 2
(PWR_CSR2) on page 124
0x4000 6C00 - 0x4000 6FFF
HDMI-CEC
Section 39.7.7: HDMI-CEC register map on
page 1620
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
I2C4
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
SPDIFRX
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
Section 31.8.12: USART register map on
page 1048
Section 36.9.5: bxCAN register map on page 1292
Section 30.7.12: I2C register map on page 984
Section 30.7.12: I2C register map on page 984
Section 31.8.12: USART register map on
page 1048
APB1
Section 34.5.13: SPDIFRX interface register map
on page 1192
Section 32.9.10: SPI/I2S register map on
page 1109
Section 27.4.6: IWDG register map on page 865
Section 28.4.4: WWDG register map on page 871
0x4000 2800 - 0x4000 2BFF RTC & BKP Registers
Section 29.6.21: RTC register map on page 915
0x4000 2400 - 0x4000 27FF
LPTIM1
Section 26.6.9: LPTIM register map on page 856
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
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Section 24.5.12: TIM10/TIM11/TIM13/TIM14
register map on page 820
Section 24.4.13: TIM9/TIM12 register map on
page 810
Section 25.4.9: TIM6/TIM7 register map on
page 835
Section 23.4.21: TIMx register map on page 771
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2.3
Embedded SRAM
The STM32F75xxx and STM32F74xxx feature:
•
System SRAM up to 320 Kbytes including Data TCM RAM 64 Kbytes
•
Instruction RAM (ITCM-RAM) 16 Kbytes.
•
4 Kbytes of backup SRAM (see section 5.1.2: Battery backup domain)
The embedded SRAM is divided into up to four blocks:
•
•
System SRAM:
–
SRAM1 mapped at address 0x2001 0000 and accessible by all AHB masters from
AHB bus Matrix.
–
SRAM2 mapped at address 0x2004 C000 and accessible by all AHB masters from
AHB bus Matrix.
–
DTCM-RAM on TCM interface (Tightly Coupled Memory interface) mapped at
address 0x2000 0000 and accessible by all AHB masters from AHB bus Matrix but
through a specific AHB slave bus of the CPU.
Instruction SRAM:
–
Instruction RAM (ITCM-RAM) mapped at address 0x0000 0000 and accessible
only by CPU.
The SRAM1 and SRAM2 can be accessed as bytes, half-words (16 bits) or full words (32
bits). While DTCM and ITCM RAMs can be accessed as bytes, half-words (16 bits), full
words (32 bits) or double words (64 bits). These memories can be addressed at maximum
system clock frequency without wait state.
The AHB masters support concurrent SRAM accesses (from the Ethernet or the USB OTG
HS): for instance, the Ethernet MAC can read/write from/to SRAM2 while the CPU is
reading/writing from/to SRAM1.
2.4
Flash memory overview
The Flash memory interface manages CPU AXI and TCM accesses to the Flash memory. It
implements the erase and program Flash memory operations and the read and write
protection mechanisms. It accelerates code execution with ART on TCM interface or L1Cache on AXIM interface.
The Flash memory is organized as follows:
•
A main memory block divided into sectors.
•
An information block:
–
System memory from which the device boots in System memory boot mode
–
1024 OTP (one-time programmable) bytes for user data.
–
Option bytes to configure read and write protection, BOR level, software/hardware
watchdog, boot memory base address and reset when the device is in Standby or
Stop mode.
Refer to Section 9: Embedded Flash memory (FLASH) for more details.
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2.5
Boot configuration
In the STM32F75xxx and STM32F74xxx, two different boot areas can be selected through
the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
BOOT_ADD1 option bytes as shown in the Table 2.
Table 2. Boot modes
Boot mode selection
Boot area
BOOT
Boot address option
bytes
0
BOOT_ADD0[15:0]
Boot address defined by user option byte BOOT_ADD0[15:0]
ST programmed value: Flash on ITCM at 0x0020 0000
1
BOOT_ADD1[15:0]
Boot address defined by user option byte BOOT_ADD1[15:0]
ST programmed value: System bootloader at 0x0010 0000
The values on the BOOT pin are latched on the 4th rising edge of SYSCLK after reset
release. It is up to the user to set the BOOT pin after reset.
The BOOT pin is also resampled when the device exits the Standby mode. Consequently,
they must be kept in the required Boot mode configuration when the device is in the Standby
mode.
After startup delay, the selection of the boot area is done before releasing the processor
reset.
The BOOT_ADD0 and BOOT_ADD1 address option bytes allows to program any boot
memory address from 0x0000 0000 to 0x3FFF FFFF which includes:
•
All Flash address space mapped on ITCM or AXIM interface
•
All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•
The System memory bootloader
The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after reset in order to boot
from any other boot address after next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved
area, the default boot fetch address is programmed as follows:
–
Boot address 0: ITCM-FLASH at 0x0020 0000
–
Boot address 1: ITCM-RAM at 0x0000 0000
When flash level 2 protection is enabled, only boot from Flash (on ITCM or AXIM interface)
or system bootloader will be available. If the already programmed boot address in the
BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range or RAM
address (on ITCM or AXIM) the default fetch will be forced from Flash on ITCM interface at
address 0x00200000.
Embedded bootloader
The embedded bootloader code is located in the system memory. It is programmed by ST
during production. For full information, refer to the application note (AN2606) STM32
microcontroller system memory boot mode.
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By default, when the boot from system bootloader is selected, the code is executed from
TCM interface. It could be executed from AXIM interface by reprogramming the
BOOT_ADDx address option bytes to 0x1FF0 0000.
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3
Embedded Flash memory (FLASH)
3.1
Introduction
The Flash memory interface manages Cortex®-M7 AXI and TCM accesses to the Flash
memory. It implements the erase and program Flash memory operations and the read and
write protection mechanisms.
The Flash memory interface accelerates code execution with a system of instruction
prefetch and cache lines on ITCM interface (ART Accelerator™).
3.2
Flash main features
•
Flash memory read operations
•
Flash memory program/erase operations
•
Read / write protections
•
64 cache lines of 256 bits on ITCM interface (ART Accelerator™)
•
Prefetch on TCM instruction code
Figure 2 shows the Flash memory interface connection inside the system architecture.
/dD
Figure 2. Flash memory interface connection inside system architecture
(STM32F75xxx and STM32F74xxx)
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Embedded Flash memory (FLASH)
3.3
Flash functional description
3.3.1
Flash memory organization
The Flash memory has the following main features:
•
Capacity up to 1 Mbyte
•
256 bits wide data read
•
Byte, half-word, word and double word write
•
Sector and mass erase
The Flash memory is organized as follows:
•
A main memory block divided into 4 sectors of 32 Kbytes, 1 sector of 128 Kbytes, and 3
sectors of 256 Kbytes
•
Information blocks containing:
–
System memory from which the device boots in System memory boot mode
–
1024 OTP (one-time programmable) for user data
–
The OTP area contains 16 additional bytes used to lock the corresponding OTP
data block.
–
Option bytes to configure read and write protection, BOR level, software/hardware
watchdog, boot memory base address and reset when the device is in Standby or
Stop mode.
The embedded flash has three main interfaces:
•
•
•
64-bits ITCM interface:
–
It is connected to the ITCM bus of Cortex-M7 and used for instruction execution
and data read access.
–
Write accesses are not supported on ITCM interface
–
Supports a unified 64 cache lines of 256 bits (ART accelerator)
64-bits AHB interface:
–
It is connected to the AXI bus of Cortex-M7 through the AHB bus matrix and used
for code execution, read and write accesses.
–
DMAs and peripherals DMAs data transfer on Flash are done through the AHB
interface whatever the addressed flash interface TCM or AHB.
32-bits AHB register interface:
–
It is used for control and status register accesses.
The main memory and information block organization are shown in Table 3.
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Table 3. Flash memory organization
Block
Main memory
block
Name
Bloc base address on AXIM
interface
Block base address
on ICTM interface
Sector
size
Sector 0
0x0800 0000 - 0x0800 7FFF
0x0020 0000 - 0x0020 7FFF
32 KB
Sector 1
0x0800 8000 - 0x0800 FFFF
0x0020 8000 - 0x0020 FFFF
32 KB
Sector 2
0x0801 0000 - 0x0801 7FFF
0x0021 0000 - 0x0021 7FFF
32 KB
Sector 3
0x0801 8000 - 0x0801 FFFF
0x0021 8000 - 0x0021 FFFF
32 KB
Sector 4
0x0802 0000 - 0x0803 FFFF
0x0022 0000 - 0x0023 FFFF
128 KB
Sector 5
0x0804 0000 - 0x0807 FFFF
0x0024 0000 - 0x0027 FFFF
256 KB
Sector 6
0x0808 0000 - 0x080B FFFF 0x0028 0000 - 0x002B FFFF
256 KB
Sector 7
0x080C 0000 - 0x080F FFFF
256 KB
System memory
Information block
3.3.2
0x002C 0000 - 0x02F FFFF
0x1FF0 0000 - 0x1FF0 EDBF 0x0010 0000 - 0x0010 EDBF 60 Kbytes
OTP
0x1FF0 F000 - 0x1FF0 F41F
Option bytes
0x1FFF 0000 - 0x1FFF 001F
0x0010 F000 - 0x0010 F41F 1024 bytes
-
32 bytes
Read access latency
To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the Flash access control register (FLASH_ACR) according to the
frequency of the CPU clock (HCLK) and the supply voltage of the device.
The correspondence between wait states and CPU clock frequency is given in Table 13 and
Table 4.
Note:
- when VOS[1:0] = '0x01', the maximum value of fHCLK is 144 MHz.
- when VOS[1:0] = '0x10', the maximum value of fHCLK is 168 MHz. It can be extended to
180 MHz by activating the over-drive mode.
- when VOS[1:0] = '0x11, the maximum value of fHCLK is 180 MHz. It can be extended to
216 MHz by activating the over-drive mode.
- The over-drive mode is not available when VDD ranges from 1.8 to 2.1 V.
Refer to Section 4.1.4: Voltage regulator for details on how to activate the over-drive mode.
Table 4. Number of wait states according to CPU clock (HCLK) frequency
HCLK (MHz)
Wait states (WS)
Voltage range
Voltage range
Voltage range
Voltage range
2.7 V - 3.6 V
2.4 V - 2.7 V
2.1 V - 2.4 V
1.8 V - 2.1 V
0 WS (1 CPU cycle)
0 < HCLK ≤ 30
0 < HCLK ≤ 24
0 < HCLK ≤ 22
0 < HCLK ≤ 20
1 WS (2 CPU cycles)
30 < HCLK ≤ 60
24 < HCLK ≤ 48
22 <HCLK ≤ 44
20 < HCLK ≤ 40
2 WS (3 CPU cycles)
60 < HCLK ≤ 90
48 < HCLK ≤ 72
44 < HCLK ≤ 66
40 < HCLK ≤ 60
3 WS (4 CPU cycles)
90 < HCLK ≤ 120
72 < HCLK ≤ 96
66 < HCLK ≤ 88
60 < HCLK ≤ 80
4 WS (5 CPU cycles)
120 < HCLK ≤ 150
96 < HCLK ≤ 120
88 < HCLK ≤ 110
80 < HCLK ≤ 100
(LATENCY)
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Embedded Flash memory (FLASH)
Table 4. Number of wait states according to CPU clock (HCLK) frequency (continued)
HCLK (MHz)
Wait states (WS)
Voltage range
Voltage range
Voltage range
Voltage range
2.7 V - 3.6 V
2.4 V - 2.7 V
2.1 V - 2.4 V
1.8 V - 2.1 V
5 WS (6 CPU cycles)
150 < HCLK ≤ 180
120 < HCLK ≤ 144
110 < HCLK ≤ 132
100 < HCLK ≤ 120
6 WS (7 CPU cycles)
180 < HCLK ≤ 210
144 < HCLK ≤ 168
132 < HCLK ≤ 154
120 < HCLK ≤ 140
7 WS (8 CPU cycles)
210 < HCLK ≤ 216
168 < HCLK ≤ 192
154 < HCLK ≤ 176
140 < HCLK ≤ 160
8 WS (9 CPU cycles)
-
192 < HCLK ≤ 216
176 < HCLK ≤ 198
160 < HCLK ≤ 180
9 WS (10 CPU cycles)
-
-
198 < HCLK ≤ 216
-
(LATENCY)
After reset, the CPU clock frequency is 16 MHz and 0 wait state (WS) is configured in the
FLASH_ACR register.
It is highly recommended to use the following software sequences to tune the number of
wait states to access the Flash memory with the CPU frequency.
Increasing the CPU frequency
1.
Program the new number of wait states to the LATENCY bits in the FLASH_ACR
register
2.
Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register
3.
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
4.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
5.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register.
Decreasing the CPU frequency
1.
Note:
Modify the CPU clock source by writing the SW bits in the RCC_CFGR register
2.
If needed, modify the CPU clock prescaler by writing the HPRE bits in RCC_CFGR
3.
Check that the new CPU clock source or/and the new CPU clock prescaler value is/are
taken into account by reading the clock source status (SWS bits) or/and the AHB
prescaler value (HPRE bits), respectively, in the RCC_CFGR register
4.
Program the new number of wait states to the LATENCY bits in FLASH_ACR
5.
Check that the new number of wait states is used to access the Flash memory by
reading the FLASH_ACR register
A change in CPU clock configuration or wait state (WS) configuration may not be effective
straight away. To make sure that the current CPU clock frequency is the one you have
configured, you can check the AHB prescaler factor and clock source status values. To
make sure that the number of WS you have programmed is effective, you can read the
FLASH_ACR register.
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Instruction prefetch
Each flash read operation provides 256 bits representing 8 instructions of 32 bits to 16
instructions of 16 bits according to the program launched. So, in case of sequential code, at
least 8 CPU cycles are needed to execute the previous instruction line read. The prefetch
on ITCM bus allows to read the sequential next line of instructions in the flash while the
current instruction line is requested by the CPU. The prefetch can be enabled by setting the
PRFTEN bit of the FLASH_ACR register. This feature is useful if at least one Wait State is
needed to access the flash. When the code is not sequential (branch), the instruction may
not be present neither in the current instruction line used nor in the prefetched instruction
line. In this case (miss), the penalty in term of number of cycles is at least equal to the
number of Wait States.
Adaptive real-time memory accelerator (ART Accelerator™)
The proprietary Adaptive real-time (ART) memory accelerator is optimized for STM32
industry-standard ARM® Cortex®-M7 with FPU processors. It balances the inherent
performance advantage of the ARM® Cortex®-M7 with FPU over Flash memory
technologies, which normally requires the processor to wait for the Flash memory at higher
operating frequencies.
To release the processor full performance, the accelerator implements a unified cache of an
instruction and branch cache which increases program execution speed from the 256-bit
Flash memory. Based on CoreMark benchmark, the performance achieved thanks to the
ART accelerator is equivalent to 0 wait state program execution from Flash memory at a
CPU frequency up to 216 MHz.
The ART accelerator is available only for flash access on ITCM interface.
To limit the time lost due to jumps, it is possible to retain 64 lines of 256 bits in the ART
accelerator. This feature can be enabled by setting the ARTEN bit of the FLASH_CR
register. The ART Accelerator is unified, it contains instruction as well as data literal pools.
Each time a miss occurs (requested data not present in the current data line used or in the
instruction cache memory), the read line is copied in the instruction cache memory of ART. If
a data contained in the instruction cache memory is requested by the CPU, the data is
provided without inserting delay. Once all the cache memory lines are filled, the LRU (Least
Recently Used) policy is used to determine the line to replace in the memory cache. This
feature is particularly useful in case of code containing loops.
Note:
Data in user configuration sector are not cacheable.
3.3.3
Flash program and erase operations
For any Flash memory program operation (erase or program), the CPU clock frequency
(HCLK) must be at least 1 MHz. The contents of the Flash memory are not guaranteed if a
device reset occurs during a Flash memory operation.
Any attempt to read the Flash memory while it is being written or erased, causes the bus to
stall. Read operations are processed correctly once the program operation has completed.
This means that code or data fetches cannot be performed while a write/erase operation is
ongoing.
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3.3.4
Embedded Flash memory (FLASH)
Unlocking the Flash control register
After reset, write is not allowed in the Flash control register (FLASH_CR) to protect the
Flash memory against possible unwanted operations due, for example, to electric
disturbances. The following sequence is used to unlock this register:
1.
Write KEY1 = 0x45670123 in the Flash key register (FLASH_KEYR)
2.
Write KEY2 = 0xCDEF89AB in the Flash key register (FLASH_KEYR)
Any wrong sequence will return a bus error and lock up the FLASH_CR register until the
next reset.
The FLASH_CR register can be locked again by software by setting the LOCK bit in the
FLASH_CR register.
Note:
The FLASH_CR register is not accessible in write mode when the BSY bit in the FLASH_SR
register is set. Any attempt to write to it with the BSY bit set will cause the AHB bus to stall
until the BSY bit is cleared.
3.3.5
Program/erase parallelism
The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It
represents the number of bytes to be programmed each time a write operation occurs to the
Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP
supply is used or not. It must therefore be correctly configured in the FLASH_CR register
before any programming/erasing operation.
A Flash memory erase operation can only be performed by sector, bank or for the whole
Flash memory (mass erase). The erase time depends on PSIZE programmed value. For
more details on the erase time, refer to the electrical characteristics section of the device
datasheet.
Table 5 provides the correct PSIZE values.
Table 5. Program/erase parallelism
Voltage range 2.7 - 3.6 V
with External VPP
Voltage range
2.7 - 3.6 V
Parallelism size
x64
x32
x16
x8
PSIZE(1:0)
11
10
01
00
Note:
Voltage range
2.4 - 2.7 V
Voltage range
2.1 - 2.4 V
Voltage range
1.8 V - 2.1 V
Any program or erase operation started with inconsistent program parallelism/voltage range
settings may lead to unpredicted results. Even if a subsequent read operation indicates that
the logical value was effectively written to the memory, this value may not be retained.
To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP
pad. The external supply must be able to sustain this voltage range even if the DC
consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on
the factory line. The VPP supply must not be applied for more than an hour, otherwise the
Flash memory might be damaged.
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Flash erase sequences
The Flash memory erase operation can be performed at sector level or on the whole Flash
memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration
sector.
Sector Erase
To erase a sector, follow the procedure below:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the SER bit and select the sector out of the 8 in the main memory block) you wish
to erase (SNB) in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
Mass Erase
To perform Mass Erase, the following sequence is recommended:
Note:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Set the MER bit in the FLASH_CR register
3.
Set the STRT bit in the FLASH_CR register
4.
Wait for the BSY bit to be cleared
If MERx and SER bits are both set in the FLASH_CR register, mass erase is performed.
If both MERx and SER bits are reset and the STRT bit is set, an unpredictable behavior may
occur without generating any error flag. This condition should be forbidden.
Note:
When setting the STRT bit in the FLASH_CR register and before polling the BSY bit to be
cleared, the software can issue a DSB instruction to guarantee the completion of a previous
access to FLASH_CR register.
3.3.7
Flash programming sequences
Standard programming
The Flash memory programming sequence is as follows:
1.
Check that no main Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register.
2.
Set the PG bit in the FLASH_CR register
3.
Perform the data write operation(s) to the desired memory address (inside main
memory block or OTP area):
4.
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–
Byte access in case of x8 parallelism
–
Half-word access in case of x16 parallelism
–
Word access in case of x32 parallelism
–
Double word access in case of x64 parallelism
Wait for the BSY bit to be cleared.
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RM0385
Note:
Embedded Flash memory (FLASH)
Successive write operations are possible without the need of an erase operation when
changing bits from ‘1’ to ‘0’. Writing ‘1’ requires a Flash memory erase operation.
If an erase and a program operation are requested simultaneously, the erase operation is
performed first.
Note:
After performing a data write operation and before polling the BSY bit to be cleared, the
software can issue a DSB instruction to guarantee the completion of a previous data write
operation.
Programming errors
In case of error, the Flash operation (programming or erasing) is aborted with one of the
following errors:
•
PGAERR: Alignment Programming error
It is not allowed to program data to the Flash memory that would cross the 128-bit row
boundary. In such a case, the write operation is not performed and the program
alignment error flag (PGAERR) is set in the FLASH_SR register.
•
PGEPRR: Programming parallelism error
The write access type (byte, half-word, word or double word) must correspond to the
type of parallelism chosen (x8, x16, x32 or x64). If not, the write operation is not
performed and the program parallelism error flag (PGPERR) is set in the FLASH_SR
register.
•
ERSERR: Erase sequence error
When an erase operation to the flash is performed by the code while the control
register has not been correctly configured, the ERSERR error flag is set
•
WRPERR: Write Protection Error
WRPERR is set if one of the following conditions occurs:
–
Attempt to program or erase in a write protected area (WRP)
–
Attempt to program or erase the system memory area.
–
A write in the OTP area which is already locked
–
Attempt to modify the option bytes when the read protection (RDP) is set to Level
–
The Flash memory is read protected and an intrusion is detected
If an erase operation in Flash memory also concerns data in the ART accelerator, you have
to make sure that these data are rewritten before they are accessed during code execution.
If this cannot be done safely, it is recommended to flush and/or desactivate the ART
accelerator by setting respectively the bits ARTRST or ARTEN of the FLASH_CR register.
Note:
The ART cache can be flushed only if the ART accelerator is disabled (ARTEN = 0).
3.3.8
Flash Interrupts
Setting the end of operation interrupt enable bit (EOPIE) in the FLASH_CR register enables
interrupt generation when an erase or program operation ends, that is when the busy bit
(BSY) in the FLASH_SR register is cleared (operation completed, correctly or not). In this
case, the end of operation (EOP) bit in the FLASH_SR register is set.
If an error occurs during a program, an erase, or a read operation request, one of the
following error flags is set in the FLASH_SR register:
•
PGAERR, PGPERR, ERSERR (Program error flags)
•
WRPERR (Protection error flag)
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In this case, if the error interrupt enable bit (ERRIE) is set in the FLASH_CR register, an
interrupt is generated and the operation error bit (OPERR) is set in the FLASH_SR register.
Note:
If several successive errors are detected (for example, in case of DMA transfer to the Flash
memory), the error flags cannot be cleared until the end of the successive write requests.
Table 6. Flash interrupt request
Interrupt event
Event flag
Enable control bit
EOP
EOPIE
WRPERR
ERRIE
PGAERR, PGPERR, ERSERR
ERRIE
End of operation
Write protection error
Programming error
3.4
FLASH Option bytes
3.4.1
Option bytes description
The option bytes are configured by the end user depending on the application requirements.
Table 7 shows the organization of these bytes inside the information block.
The option bytes can be read from the user configuration memory locations or from the
Option byte registers:
•
Flash option control register (FLASH_OPTCR)
•
Flash option control register (FLASH_OPTCR1)
Table 7. Option byte organization
AXI address
[63:16]
[15:0]
0x1FFF 0000
Reserved
ROP & user option bytes (RDP & USER)
0x1FFF 0008
Reserved
IWDG_STOP, IWDG_STBY and Write protection nWRP
(sector 0 to 7) and user option bytes
0x1FFF 0010
Reserved
BOOT_ADD0
0x1FFF 0018
Reserved
BOOT_ADD1
User and read protection option bytes
Memory address: 0x1FFF 0000
ST programmed value: 0x5500AAFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
RDP
r
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STDBY STOP
r
r
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SW
_SW
r
r
BOR_LEV[1:0]
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r
RM0385
Embedded Flash memory (FLASH)
Bits 31:13 Not used.
Bit 15:8 RDP: Read Out Protection
The read protection helps the user protect the software code stored in Flash memory.
0xAA: Level0, no Protection
0xCC: Level2, chip protection (debug & boot in RAM features disabled)
others: Level1, read protection of memories (debug features limited)
Bit 7 nRST_STDBY
0: Reset generated when entering Standby mode.
1: No reset generated.
Bit 6 nRST_STOP
0: Reset generated when entering Stop mode.
1: No reset generated.
Bit 5 IWDG_SW: Independant watchdog selection
0: Hardware independant watchdog.
1: Software independant watchdog.
Bit 4 WWDG_SW: Window watchdog selection
0: Hardware window watchdog.
1: Software window watchdog.
Bits 3:2 BOR_LEV: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level value into Flash memory.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
Note: For full details on BOR characteristics, refer to the “Electrical characteristics” section
of the product datasheet.
Bits 1:0 Not used
User and write protection option bytes
Memory address: 0x1FFF 0008
ST programmed value: 0x0000FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
IWDG_ST IWDG_ST
OP
DBY
r
r
nWRPi
r
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Bits 31:16 Not used.
Bit 15 IWDG_STOP: Independent watchdog counter freeze in stop mode
0: Freeze IWDG counter in stop mode.
1: IWDG counter active in stop mode.
Bit 14 IWDG_STDBY: Independent watchdog counter freeze in Standby mode
1: IWDG counter active in standby mode.
Bit 13:8 Not used
Bits 7:0 nWRPi: Non Write Protection of sector i
0: Write protection active on sector i.
1: Write protection not active on sector i.
Boot address option bytes when Boot pin =0
Memory address: 0x1FFF 0010
ST programmed value: 0xFF7F 0080 (ITCM-FLASH base address)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
BOOT_ADD0[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Not used.
Bit 15:0 BOOT_ADD0[15:0]: Boot memory base address when Boot pin =0
BOOT_ADD0[15:0] correspond to address [29:14],
The boot base address supports address range only from 0x0000 0000 to 0x2004 FFFF
with a granularity of 16KB.
Example:
BOOT_ADD0 = 0x0000: Boot from ITCM RAM (0x0000 0000)
BOOT_ADD0 = 0x0040: Boot from system memory bootloader (0x0010 0000)
BOOT_ADD0 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)
BOOT_ADD0 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)
BOOT_ADD0 = 0x8000: Boot from DTCM RAM (0x2000 0000)
BOOT_ADD0 = 0x8004: Boot from SRAM1 (0x2001 0000)
BOOT_ADD0 = 0x8013: Boot from SRAM2 (0x2004 C000)
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Embedded Flash memory (FLASH)
Boot address option bytes when Boot pin =1
Memory address: 0x1FFF 0018
ST programmed value: 0xFFBF0040 (system memory bootoader address)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
BOOT_ADD1[15:0]
r
r
r
r
Bits 31:16
Bit 15:0
3.4.2
r
r
r
r
r
Not used
BOOT_ADD1[15:0]: Boot memory base address when Boot pin =1
BOOT_ADD1[15:0] correspond to address [29:14],
The boot base address supports address range only from 0x0000 0000 to 0x2004 FFFF
with a granularity of 16KB.
Example:
BOOT_ADD1 = 0x0000: Boot from ITCM RAM(0x0000 0000)
BOOT_ADD1 = 0x0040: Boot from system memory bootloader (0x0010 0000)
BOOT_ADD1 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)
BOOT_ADD1 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)
BOOT_ADD1 = 0x8000: Boot from DTCM RAM (0x2000 0000)
BOOT_ADD1 = 0x8004: Boot from SRAM1 (0x2001 0000)
BOOT_ADD1 = 0x8013: Boot from SRAM2 (0x2004 C000)
Option bytes programming
To run any operation on this sector, the option lock bit (OPTLOCK) in the Flash option
control register (FLASH_OPTCR) must be cleared. To be allowed to clear this bit, you have
to perform the following sequence:
1.
Write OPTKEY1 = 0x0819 2A3B in the Flash option key register (FLASH_OPTKEYR)
2.
Write OPTKEY2 = 0x4C5D 6E7F in the Flash option key register (FLASH_OPTKEYR)
The user option bytes can be protected against unwanted erase/program operations by
setting the OPTLOCK bit by software.
Modifying user option bytes
To modify the user option value, follow the sequence below:
Note:
1.
Check that no Flash memory operation is ongoing by checking the BSY bit in the
FLASH_SR register
2.
Write the desired option value in the FLASH_OPTCR register.
3.
Set the option start bit (OPTSTRT) in the FLASH_OPTCR register
4.
Wait for the BSY bit to be cleared.
The value of an option is automatically modified by first erasing the information block and
then programming all the option bytes with the values contained in the FLASH_OPTCR
register.
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Note:
When setting the OPTSTRT bit in the FLASH_OPTCR register and before polling the BSY
bit to be cleared, the software can issue a DSB instruction to guarantee the completion of a
previous access to the FLASH_OPTCR register.
3.5
FLASH memory protection
3.5.1
Read protection (RDP)
The user area in the Flash memory can be protected against read operations by an
entrusted code. Three read protection levels are defined:
•
Level 0: no read protection
When the read protection level is set to Level 0 by writing 0xAA into the read protection
option byte (RDP), all read/write operations (if no write protection is set) from/to the
Flash memory or the backup SRAM are possible in all boot configurations (Flash user
boot, debug or boot from RAM).
•
Level 1: read protection enabled
It is the default read protection level after option byte erase. The read protection Level
1 is activated by writing any value (except for 0xAA and 0xCC used to set Level 0 and
Level 2, respectively) into the RDP option byte. When the read protection Level 1 is set:
–
No access (read, erase, program) to Flash memory or backup SRAM can be
performed while the debug feature is connected or while booting from RAM or
system memory bootloader. A bus error is generated in case of read request.
–
When booting from Flash memory, accesses (read, erase, program) to Flash
memory and backup SRAM from user code are allowed.
When Level 1 is active, programming the protection option byte (RDP) to Level 0
causes the Flash memory and the backup SRAM to be mass-erased. As a result the
user code area is cleared before the read protection is removed. The mass erase only
erases the user code area. The other option bytes including write protections remain
unchanged from before the mass-erase operation. The OTP area is not affected by
mass erase and remains unchanged. Mass erase is performed only when Level 1 is
active and Level 0 requested. When the protection level is increased (0->1, 1->2, 0->2)
there is no mass erase.
•
Level 2: debug/chip read disabled
The read protection Level 2 is activated by writing 0xCC to the RDP option byte. When
the read protection Level 2 is set:
–
All protections provided by Level 1 are active.
–
Booting from RAM is no more allowed.
–
Booting system memory bootloader is possible and all the commands are not
accessible except Get, GetID and GetVersion. Refer to AN2606.
–
JTAG, SWV (serial-wire viewer), ETM, and boundary scan are disabled.
–
User option bytes can no longer be changed.
–
When booting from Flash memory, accesses (read, erase and program) to Flash
memory and backup SRAM from user code are allowed.
Memory read protection Level 2 is an irreversible operation. When Level 2 is activated,
the level of protection cannot be decreased to Level 0 or Level 1.
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Embedded Flash memory (FLASH)
Note:
The JTAG port is permanently disabled when Level 2 is active (acting as a JTAG fuse). As a
consequence, boundary scan cannot be performed. STMicroelectronics is not able to
perform analysis on defective parts on which the Level 2 protection has been set.
Note:
If the read protection is set while the debugger is still connected through JTAG/SWD, apply
a POR (power-on reset).
Table 8. Access versus read protection level
Memory area
Protection
Level
Debug features, Boot from RAM or
from System memory bootloader
Read
Main Flash Memory
and Backup SRAM
Option Bytes
OTP
Level 1
Write
Erase
Booting from Flash memory
Read
Write
NO(1)
NO
Erase
YES
Level 2
NO
YES
Level 1
YES
YES
Level 2
NO
NO
Level 1
NO
NA
YES
NA
Level 2
NO
NA
YES
NA
1. The main Flash memory and backup SRAM are only erased when the RDP changes from level 1 to 0. The OTP area
remains unchanged.
Figure 3 shows how to go from one RDP level to another.
Figure 3. RDP levels
2$0!!H##H
/THERSOPTIONSMODIFIED
,EVEL
2$0!!H
2$0##H
DEFAULT
7RITEOPTIONS
INCLUDING
2$0##H
7RITEOPTIONSINCLUDING
2$0##H!!H
, EV E L 2 $ 0 # # H
7RITEOPTIONS
INCLUDING
2$0!!H
, EV E L 7RITEOPTIONS
INCLUDING
2$0##H
/PTIONSWRITE2$0LEVELINCREASEINCLUDES
/PTIONSERASE
.EWOPTIONSPROGRAM
/PTIONSWRITE2$0LEVELDECREASEINCLUDES
-ASSERASE
/PTIONSERASE
.EWOPTIONSPROGRAM
2 $ 0 ! ! H
2$0!!H
/THERSOPTIONSMODIFIED
/PTIONSWRITE2$0LEVELIDENTICALINCLUDES
/PTIONSERASE
.EWOPTIONSPROGRAM
AI
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Embedded Flash memory (FLASH)
3.5.2
RM0385
Write protections
Up to 8 user sectors in Flash memory can be protected against unwanted write operations
due to loss of program counter contexts. When the non-write protection nWRPi bit (0 ≤ i ≤ 7)
in the FLASH_OPTCR or FLASH_OPTCR1 registers is low, the corresponding sector
cannot be erased or programmed. Consequently, a mass erase cannot be performed if one
of the sectors is write-protected.
If an erase/program operation to a write-protected part of the Flash memory is attempted
(sector protected by write protection bit, OTP part locked or part of the Flash memory that
can never be written like the ICP), the write protection error flag (WRPERR) is set in the
FLASH_SR register.
Note:
When the memory read protection level is selected (RDP level = 1), it is not possible to
program or erase Flash memory sector i if the CPU debug features are connected (JTAG or
single wire) or boot code is being executed from RAM, even if nWRPi = 1.
Write protection error flag
If an erase/program operation to a write protected area of the Flash memory is performed,
the Write Protection Error flag (WRPERR) is set in the FLASH_SR register.
If an erase operation is requested, the WRPERR bit is set when:
•
A sector erase is requested and the Sector Number SNB field is not valid
•
A mass erase is requested while at least one of the user sector is write protected by
option bit (MER and nWRi = 0 with 0 ≤ i ≤ 7 bits in the FLASH_OPTCR register
•
A sector erase is requested on a write protected sector. (SER = 1, SNB = i and
nWRPi = 0 with 0 ≤ i ≤ 7 bits in the FLASH_OPTCR register)
•
The Flash memory is readout protected and an intrusion is detected.
If a program operation is requested, the WRPERR bit is set when:
3.6
•
A write operation is performed on system memory or on the reserved part of the user
specific sector.
•
A write operation is performed to the information block
•
A write operation is performed on a sector write protected by option bit.
•
A write operation is requested on an OTP area which is already locked
•
The Flash memory is read protected and an intrusion is detected.
One-time programmable bytes
Table 9 shows the organization of the one-time programmable (OTP) part of the OTP area.
Table 9. OTP area organization
OTP
[255:224] [223:193] [192:161] [160:128]
Block
0
1
86/1671
[127:96]
[95:64]
[63:32]
[31:0]
Address
byte 0
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
0x1FF0 F000
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
OTP0
0x1FF0 F020
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
0x1FF0 F040
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
OTP1
0x1FF0 F060
DocID026670 Rev 6
RM0385
Embedded Flash memory (FLASH)
Table 9. OTP area organization (continued)
OTP
[255:224] [223:193] [192:161] [160:128]
Block
14
15
Lock
block
[127:96]
[95:64]
[63:32]
[31:0]
Address
byte 0
-
-
-
-
-
-
-
-
-
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
0x1FF0 F380
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
OPT14
0x1FF0 F3A0
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
0x1FF0 F3C0
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
OPT15
0x1FF0 F3E0
reserved
reserved
reserved
reserved
LOCK15... LOCK11... LOCK7... LOCK3...
0x1FF0 F400
LOCKB12 LOCKB8 LOCKB4 LOCKB0
The OTP area is divided into 16 OTP data blocks of 64 bytes and one lock OTP block of 16
bytes. The OTP data and lock blocks cannot be erased. The lock block contains 16 bytes
LOCKBi (0 ≤ i ≤ 15) to lock the corresponding OTP data block (blocks 0 to 15). Each OTP
data block can be programmed until the value 0x00 is programmed in the corresponding
OTP lock byte. The lock bytes must only contain 0x00 and 0xFF values, otherwise the OTP
bytes might not be taken into account correctly.
3.7
FLASH registers
3.7.1
Flash access control register (FLASH_ACR)
The Flash access control register is used to enable/disable the acceleration features and
control the Flash memory access time according to CPU frequency.
Address offset: 0x00
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
9
8
3
2
1
0
15
14
13
12
11
10
Res.
Res.
Res.
Res.
ARTRST
Res.
rw
ARTEN PRFTEN
rw
7
6
5
4
Res.
Res.
Res.
Res.
rw
LATENCY[3:0]
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept cleared.
Bit 11 ARTRST: ART Accelerator reset
0: ART Accelerator is not reset
1: ART Accelerator is reset
Bit 10 Reserved, must be kept cleared.
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Embedded Flash memory (FLASH)
RM0385
Bit 9 ARTEN: ART Accelerator Enable
0: ART Accelerator is disabled
1: ART Accelerator is enabled
Bit 8 PRFTEN: Prefetch enable
0: Prefetch is disabled
1: Prefetch is enabled
Bits 7:4 Reserved, must be kept cleared.
Bits 3:0 LATENCY[3:0]: Latency
These bits represent the ratio of the CPU clock period to the Flash memory access time.
0000: Zero wait state
0001: One wait state
0010: Two wait states
1110: Fourteen wait states
1111: Fifteen wait states
3.7.2
Flash key register (FLASH_KEYR)
The Flash key register is used to allow access to the Flash control register and so, to allow
program and erase operations.
Address offset: 0x04
Reset value: 0x0000 0000
Access: no wait state, word access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
KEY[31:16]
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
KEY[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 FKEYR[31:0]: FPEC key
The following values must be programmed consecutively to unlock the FLASH_CR register
and allow programming/erasing it:
a) KEY1 = 0x45670123
b) KEY2 = 0xCDEF89AB
3.7.3
Flash option key register (FLASH_OPTKEYR)
The Flash option key register is used to allow program and erase operations in the
information block.
Address offset: 0x08
Reset value: 0x0000 0000
Access: no wait state, word access
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Embedded Flash memory (FLASH)
31
30
29
28
27
26
25
24
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
w
w
w
w
w
w
w
w
7
6
5
4
3
2
1
0
w
w
w
w
w
w
w
OPTKEYR[31:16]
OPTKEYR[15:0]
w
w
w
w
w
w
w
w
w
Bits 31:0 OPTKEYR[31:0]: Option byte key
The following values must be programmed consecutively to unlock the FLASH_OPTCR
register and allow programming it:
a) OPTKEY1 = 0x08192A3B
b) OPTKEY2 = 0x4C5D6E7F
3.7.4
Flash status register (FLASH_SR)
The Flash status register gives information on ongoing program and erase operations.
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSY
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OPERR
EOP
rc_w1
rc_w1
r
ERSERR PGPERR PGAERR WRPERR
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:17 Reserved, must be kept cleared.
Bit 16 BSY: Busy
This bit indicates that a Flash memory operation is in progress. It is set at the beginning of a
Flash memory operation and cleared when the operation finishes or an error occurs.
0: no Flash memory operation ongoing
1: Flash memory operation ongoing
Bits 15:8 Reserved, must be kept cleared.
Bit 7 ERSERR: Erase Sequence Error
Set by hardware when a write access to the Flash memory is performed by the code while
the control register has not been correctly configured.
Cleared by writing 1.
Bit 6 PGPERR: Programming parallelism error
Set by hardware when the size of the access (byte, half-word, word, double word) during the
program sequence does not correspond to the parallelism configuration PSIZE (x8, x16,
x32, x64).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 128-bit Flash
memory row.
Cleared by writing 1.
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Embedded Flash memory (FLASH)
RM0385
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-protected
part of the Flash memory.
Cleared by writing 1.
Bits 3:2 Reserved, must be kept cleared.
Bit 1 OPERR: Operation error
Set by hardware when a flash operation (programming / erase /read) request is detected and
can not be run because of parallelism, alignment, or write protection error. This bit is set only
if error interrupts are enabled (ERRIE = 1).
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operations (program/erase) has/have
completed successfully. It is set only if the end of operation interrupts are enabled (EOPIE =
1).
Cleared by writing a 1.
3.7.5
Flash control register (FLASH_CR)
The Flash control register is used to configure and start Flash memory operations.
Address offset: 0x10
Reset value: 0x8000 0000
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
LOCK
Res.
Res.
Res.
Res.
Res.
ERRIE
EOPIE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
STRT
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
MER
SER
PG
rw
rw
rw
rw
rw
rs
PSIZE[1:0]
rw
rw
rs
Res.
SNB[3:0]
rw
rw
Bit 31 LOCK: Lock
Write to 1 only. When it is set, this bit indicates that the FLASH_CR register is locked. It is
cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Bits 30:26 Reserved, must be kept cleared.
Bit 25 ERRIE: Error interrupt enable
This bit enables the interrupt generation when the OPERR bit in the FLASH_SR register is
set to 1.
0: Error interrupt generation disabled
1: Error interrupt generation enabled
Bit 24 EOPIE: End of operation interrupt enable
This bit enables the interrupt generation when the EOP bit in the FLASH_SR register goes
to 1.
0: Interrupt generation disabled
1: Interrupt generation enabled
Bits 23:17 Reserved, must be kept cleared.
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Embedded Flash memory (FLASH)
Bit 16 STRT: Start
This bit triggers an erase operation when set. It is set only by software and cleared when the
BSY bit is cleared.
Bits 15:10 Reserved, must be kept cleared.
Bits 9:8 PSIZE: Program size
These bits select the program parallelism.
00 program x8
01 program x16
10 program x32
11 program x64
Bit 7 Reserved, must be kept cleared.
Bits 6:3 SNB[3:0]: Sector number
These bits select the sector to erase.
0000 sector 0
0001 sector 1
...
0111 sector 7
Others not allowed
Bit 2 MER: Mass Erase
Erase activated for all user sectors.
Bit 1 SER: Sector Erase
Sector Erase activated.
Bit 0 PG: Programming
Flash programming activated.
3.7.6
Flash option control register (FLASH_OPTCR)
The FLASH_OPTCR register is used to modify the user option bytes.
Address offset: 0x14
Reset value: 0xC0FFAAFD. The option bytes are loaded with values from Flash memory at
reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
IWDG_ IWDG_
STOP STDBY
rw
rw
15
14
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
8
rw
rw
rw
rw
22
rw
rw
rw
21
20
19
18
17
16
nWRP[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
nRST_ nRST_
STDBY STOP
RDP[7:0]
rw
23
rw
rw
DocID026670 Rev 6
IWDG_ WWDG
SW
_SW
rw
rw
BOR_LEV[1:0]
rw
rw
OPTST OPTLO
RT
CK
rs
rs
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Embedded Flash memory (FLASH)
RM0385
Bit 31 IWDG_STOP: Independent watchdog counter freeze in Stop mode
0: Freeze IWDG counter in STOP mode.
1: IWDG counter active in STOP mode.
Bit 30 IWDG_STDBY: Independent watchdog counter freeze in standby mode
0: Freeze IWDG counter in standby mode.
1: IWDG counter active in standby mode.
Bits 29:24 Reserved, must be kept cleared.
Bits 23:16 nWRP[7:0]: Not write protect
These bits contain the value of the write-protection option bytes for sectors 0 to 7 after reset.
They can be written to program a new write-protect into Flash memory.
0: Write protection active on sector i
1: Write protection not active on sector i
Bits 15:8 RDP[7:0]: Read protect
These bits contain the value of the read-protection option level after reset. They can be
written to program a new read protection value into Flash memory.
0xAA: Level 0, read protection not active
0xCC: Level 2, chip read protection active
Others: Level 1, read protection of memories active
Bits 7:4 USER: User option bytes
These bits contain the value of the user option byte after reset. They can be written to
program a new user option byte value into Flash memory.
Bit 7: nRST_STDBY
Bit 6: nRST_STOP
Bit 5: IWDG_SW
Bit 4: WWDG_SW
Bits 3:2 BOR_LEV[1:0]: BOR reset Level
These bits contain the supply level threshold that activates/releases the reset. They can be
written to program a new BOR level. By default, BOR is off. When the supply voltage (VDD)
drops below the selected BOR level, a device reset is generated.
00: BOR Level 3 (VBOR3), brownout threshold level 3
01: BOR Level 2 (VBOR2), brownout threshold level 2
10: BOR Level 1 (VBOR1), brownout threshold level 1
11: BOR off, POR/PDR reset threshold level is applied
Note: For full details on BOR characteristics, refer to the “Electrical characteristics” section of
the product datasheet.
Bit 1 OPTSTRT: Option start
This bit triggers a user option operation when set. It is set only by software and cleared when
the BSY bit is cleared.
Bit 0 OPTLOCK: Option lock
Write to 1 only. When this bit is set, it indicates that the FLASH_OPTCR register is locked.
This bit is cleared by hardware after detecting the unlock sequence.
In the event of an unsuccessful unlock operation, this bit remains set until the next reset.
Note:
When modifying the IWDG_SW, IWDG_STOP or IWDG_STDBY option byte, a system
reset is required to make the change effective.
3.7.7
Flash option control register (FLASH_OPTCR1)
The FLASH_OPTCR1 register is used to modify the user option bytes.
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Embedded Flash memory (FLASH)
Address offset: 0x18
Reset value: 0xFF7F 0080 (ITCM-FLASH). The option bytes are loaded with values from
Flash memory at reset release.
Access: no wait state when no Flash memory operation is ongoing, word, half-word and
byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
BOOT_ADD1[15:0]
rw
15
14
13
12
11
10
9
8
7
BOOT_ADD0[15:0]
rw
Bits 31:16 BOOT_ADD1[15:0]: Boot base address when Boot pin =1
BOOT_ADD1[15:0] correspond to address [29:14],
The boot memory address can be programmed to any address in the range 0x0000 0000 to
0x2004 FFFF with a granularity of 16KB.
Example:
BOOT_ADD1 = 0x0000: Boot from ITCM RAM (0x0000 0000)
BOOT_ADD1 = 0x0040: Boot from System memory bootloader (0x0010 0000)
BOOT_ADD1 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)
BOOT_ADD1 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)
BOOT_ADD1 = 0x8000: Boot from DTCM RAM (0x2000 0000)
BOOT_ADD1 = 0x8004: Boot from SRAM1 (0x2001 0000)
BOOT_ADD1 = 0x8013: Boot from SRAM2 (0x2004 C000)
Bits 15:0 BOOT_ADD0[15:0]: Boot base address when Boot pin =0
BOOT_ADD0[15:0] correspond to address [29:14],
The boot base address can be programmed to any address in the range 0x0000 0000 to
0x2004 FFFF with a granularity of 16KB.
Example:
BOOT_ADD0 = 0x0000: Boot from ITCM RAM (0x0000 0000)
BOOT_ADD0 = 0x0040: Boot from System memory bootloader (0x0010 0000)
BOOT_ADD0 = 0x0080: Boot from Flash on ITCM interface (0x0020 0000)
BOOT_ADD0 = 0x2000: Boot from Flash on AXIM interface (0x0800 0000)
BOOT_ADD0 = 0x8000: Boot from DTCM RAM (0x2000 0000)
BOOT_ADD0 = 0x8004: Boot from SRAM1 (0x2001 0000)
BOOT_ADD0 = 0x8013: Boot from SRAM2 (0x2004 C000)
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Embedded Flash memory (FLASH)
3.7.8
RM0385
Flash interface register map
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FLASH_SR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BSY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
nWRP[7:0]
1
1
1
1
1
1
1
1
0
1
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
RDP[7:0]
1
1
1
0
1
0
1
0
BOOT_ADD1[15:0]
1
0
0
PSIZE[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EOPIE
Res.
Res.
ERRIE
Res.
Res.
0
1
FLASH_
OPTCR1
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LOCK
IWDG_STOP
IWDG_STDBY
1
0
0
0
1
0
SNB[3:0]
0
0
0
1
1
EOP
0
Reset value
0
0
0
PG
0
FLASH_OPTCR
0
0
0
0
0
OPTLOCK
0
0
0
OPERR
0
0
0
SER
0
1
0
MER
0
Reset value
0
OPTSTRT
0
0x14
0
OPTKEYR[15:0]
0
FLASH_CR
Res.
PRFTEN
0
OPTKEYR[31:16]
Reset value
94/1671
0
Reset value
0x10
0
Res.
0
BOR_LEV[1:0]
0
Res.
0
WRPERR
0
WWDG_SW
0
KEY[15:0]
PGAERR
0
0
IWDG_SW
0
0
PGPERR
0
0
nRST_STOP
0
0
Res.
0
LATENCY[3:0]
ERSERR
0
FLASH_
OPTKEYR
0x0C
0x18
Res.
KEY[31:16]
Res.
0x08
0
Res.
Reset value
0
nRST_STDBY
FLASH_KEYR
STRT
0x04
0
ARTEN
Res.
Reset value
ARTRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FLASH_ACR
0x00
Res.
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 10. Flash register map and reset values
1
1
1
1
0
1
0
0
0
0
0
BOOT_ADD0[15:0]
1
1
1
1
1
DocID026670 Rev 6
0
0
0
0
0
0
0
0
1
0
0
RM0385
Power controller (PWR)
4
Power controller (PWR)
4.1
Power supplies
The device requires a 1.8 to 3.6 V operating voltage supply (VDD). An embedded linear
voltage regulator is used to supply the internal 1.2 V digital power.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM)
can be powered from the VBAT voltage when the main VDD supply is powered off.
Note:
Depending on the operating power supply range, some peripheral may be used with limited
functionality and performance. For more details refer to section "General operating
conditions" in STM32F75xxx and STM32F74xxx datasheets.
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Power controller (PWR)
RM0385
Figure 4. Power supply overview
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1. VDDA and VSSA must be connected to VDD and VSS, respectively.
4.1.1
Independent A/D converter supply and reference voltage
To improve conversion accuracy, the ADC has an independent power supply which can be
separately filtered and shielded from noise on the PCB.
•
The ADC voltage supply input is available on a separate VDDA pin.
•
An isolated supply ground connection is provided on pin VSSA.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external
reference voltage ADC input on VREF. The voltage on VREF ranges from 1.8 V to VDDA.
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4.1.2
Power controller (PWR)
Independent USB transceivers supply
The VDDUSB is an independent USB power supply for full speed transceivers (USB OTG FS
and USB OTG HS in FS mode). It can be connected either to VDD or an external
independent power supply (3.0 to 3.6V) for USB transceivers (refer Figure 5 and Figure 6).
For example, when the device is powered at 1.8V, an independent power supply 3.3V can
be connected to VDDUSB. When the VDDUSB is connected to a separated power supply, it is
independent from VDD or VDDA but it must be the last supply to be provided and the first to
disappear. The following conditions VDDUSB must be respected:
•
During power-on phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD
•
During power-down phase (VDD < VDD_MIN), VDDUSB should be always lower than VDD
•
VDDUSB rising and falling time rate specifications must be respected
•
In operating mode phase, VDDUSB could be lower or higher than VDD:
–
If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
VDDUSB are operating between VDDUSB_MIN and VDDUSB_MAX.
–
The VDDUSB supplies both USB transceiver (USB OTG_HS and USB OTG_FS). If
only one USB transceiver is used in the application, the GPIOs associated to the
other USB transceiver are still supplied at by VDDUSB.
–
If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
VDDUSB are operating between VDD_MIN and VDD_MAX.
Figure 5. VDDUSB connected to VDD power supply
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Power controller (PWR)
RM0385
Figure 6. VDDUSB connected to external independent power supply
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4.1.3
Battery backup domain
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a
battery or by another source.
To allow the RTC to operate even when the main digital supply (VDD) is turned off, the VBAT
pin powers the following blocks:
•
The RTC
•
The LSE oscillator
•
The backup SRAM when the low-power backup regulator is enabled
•
PC13 to PC15 I/Os, plus PI8 I/O (when available)
The switch to the VBAT supply is controlled by the power-down reset embedded in the Reset
block.
Warning:
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During tRSTTEMPO (temporization at VDD startup) or after a PDR
is detected, the power switch between VBAT and VDD remains
connected to VBAT.
During the startup phase, if VDD is established in less than
tRSTTEMPO (Refer to the datasheet for the value of tRSTTEMPO)
and VDD > VBAT + 0.6 V, a current may be injected into VBAT
through an internal diode connected between VDD and the
power switch (VBAT).
If the power supply/battery connected to the VBAT pin cannot
support this current injection, it is strongly recommended to
DocID026670 Rev 6
RM0385
Power controller (PWR)
connect an external low-drop diode between this power
supply and the VBAT pin.
If no external battery is used in the application, it is recommended to connect the VBAT pin to
VDD with a 100 nF external decoupling ceramic capacitor in parallel.
When the backup domain is supplied by VDD (analog switch connected to VDD), the
following functions are available:
Note:
•
PC14 and PC15 can be used as either GPIO or LSE pins
•
PC13 and PI8 can be used as a GPIO pin (refer to Table 148: RTC pin PC13
configuration and Table 149: RTC pin PI8 configuration for more details about these
pins configuration)
Due to the fact that the switch only sinks a limited amount of current (3 mA), the use of
GPIOs PI8 and PC13 to PC15 are restricted: only one I/O at a time can be used as an
output, the speed has to be limited to 2 MHz with a maximum load of 30 pF and these I/Os
must not be used as a current source (e.g. to drive an LED).
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the following functions are available:
•
PC14 and PC15 can be used as LSE pins only
•
PC13 can be used as tamper pin (TAMP1)
•
PI8 can be used as tamper pin (TAMP2)
Backup domain access
After reset, the backup domain (RTC registers, RTC backup register and backup SRAM) is
protected against possible unwanted write accesses. To enable access to the backup
domain, proceed as follows:
•
Access to the RTC and RTC backup registers
1.
Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 5.3.13)
2.
Set the DBP bit in the PWR power control register (PWR_CR1) to enable access to the
backup domain
3.
Select the RTC clock source: see Section 5.2.8: RTC/AWU clock
4.
Enable the RTC clock by programming the RTCEN [15] bit in the RCC backup domain
control register (RCC_BDCR)
•
Access to the backup SRAM
1.
Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR
register (see Section 5.3.13)
2.
Set the DBP bit in the PWR power control register (PWR_CR1) to enable access to the
backup domain
3.
Enable the backup SRAM clock by setting BKPSRAMEN bit in the RCC APB1
peripheral clock enable register (RCC_APB1ENR).
RTC and RTC backup registers
The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable
wakeup flag with interrupt capability. The RTC contains 32 backup data registers (128 bytes)
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Power controller (PWR)
RM0385
which are reset when a tamper detection event occurs. For more details refer to Section 29:
Real-time clock (RTC).
Backup SRAM
The backup domain includes 4 Kbytes of backup SRAM addressed in 32-bit, 16-bit or 8-bit
mode. Its content is retained even in Standby or VBAT mode when the low-power backup
regulator is enabled. It can be considered as an internal EEPROM when VBAT is always
present.
When the backup domain is supplied by VDD (analog switch connected to VDD), the backup
SRAM is powered from VDD which replaces the VBAT power supply to save battery life.
When the backup domain is supplied by VBAT (analog switch connected to VBAT because
VDD is not present), the backup SRAM is powered by a dedicated low-power regulator. This
regulator can be ON or OFF depending whether the application needs the backup SRAM
function in Standby and VBAT modes or not. The power-down of this regulator is controlled
by a dedicated bit, the BRE control bit of the PWR_CSR1 register (see Section 4.4.2: PWR
power control/status register (PWR_CSR1)).
The backup SRAM is not mass erased by an tamper event. It is read protected to prevent
confidential data, such as cryptographic private key, from being accessed. The backup
SRAM can be erased only through the Flash interface when a protection level change from
level 1 to level 0 is requested. Refer to the description of Read protection (RDP) option byte.
Figure 7. Backup domain
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4.1.4
Voltage regulator
An embedded linear voltage regulator supplies all the digital circuitries except for the backup
domain and the Standby circuitry. The regulator output voltage is around 1.2 V.
This voltage regulator requires two external capacitors to be connected to two dedicated
pins, VCAP_1 and VCAP_2 available in all packages. Specific pins must be connected either to
VSS or VDD to activate or deactivate the voltage regulator. These pins depend on the
package.
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Power controller (PWR)
When activated by software, the voltage regulator is always enabled after Reset. It works in
three different modes depending on the application modes (Run, Stop, or Standby mode).
•
In Run mode, the main regulator supplies full power to the 1.2 V domain (core,
memories and digital peripherals). In this mode, the regulator output voltage (around
1.2 V) can be scaled by software to different voltage values (scale 1, scale 2, and scale
3 can be configured through VOS[1:0] bits of the PWR_CR1 register). The scale can
be modified only when the PLL is OFF and the HSI or HSE clock source is selected as
system clock source. The new value programmed is active only when the PLL is ON.
When the PLL is OFF, the voltage scale 3 is automatically selected.
The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency. After exit from Stop mode, the voltage
scale 3 is automatically selected.(see Section 4.4.1: PWR power control register
(PWR_CR1).
2 operating modes are available:
•
–
Normal mode: The CPU and core logic operate at maximum frequency at a given
voltage scaling (scale 1, scale 2 or scale 3)
–
Over-drive mode: This mode allows the CPU and the core logic to operate at a
higher frequency than the normal mode for the voltage scaling scale 1 and scale
2.
In Stop mode: the main regulator or low-power regulator supplies a low-power voltage
to the 1.2V domain, thus preserving the content of registers and internal SRAM.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured by software as follows:
–
–
•
Note:
Normal mode: the 1.2 V domain is preserved in nominal leakage mode. It is the
default mode when the main regulator (MR) or the low-power regulator (LPR) is
enabled.
Under-drive mode: the 1.2 V domain is preserved in reduced leakage mode. This
mode is only available with the main regulator or the low-power regulator mode
(see Table 11).
In Standby mode: the regulator is powered down. The content of the registers and
SRAM are lost except for the Standby circuitry and the backup domain.
Over-drive and under-drive mode are not available when the regulator is bypassed.
For more details, refer to the voltage regulator section in the datasheets.
Table 11. Voltage regulator configuration mode versus device operating mode(1)
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down mode
-
-
-
Yes
Over-drive
mode(2)
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.8 to 2.1 V.
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Entering Over-drive mode
It is recommended to enter Over-drive mode when the application is not running critical
tasks and when the system clock source is either HSI or HSE. To optimize the configuration
time, enable the Over-drive mode during the PLL lock phase.
To enter Over-drive mode, follow the sequence below:
Note:
1.
Select HSI or HSE as system clock.
2.
Configure RCC_PLLCFGR register and set PLLON bit of RCC_CR register.
3.
Set ODEN bit of PWR_CR1 register to enable the Over-drive mode and wait for the
ODRDY flag to be set in the PWR_CSR1 register.
4.
Set the ODSW bit in the PWR_CR1 register to switch the voltage regulator from
Normal mode to Over-drive mode. The System will be stalled during the switch but the
PLL clock system will be still running during locking phase.
5.
Wait for the ODSWRDY flag in the PWR_CSR1 to be set.
6.
Select the required Flash latency as well as AHB and APB prescalers.
7.
Wait for PLL lock.
8.
Switch the system clock to the PLL.
9.
Enable the peripherals that are not generated by the System PLL (I2S clock, LCD-TFT
clock, SAI1 clock, USB_48MHz clock....).
The PLLI2S and PLLSAI can be configured at the same time as the system PLL.
During the Over-drive switch activation, no peripheral clocks should be enabled. The
peripheral clocks must be enabled once the Over-drive mode is activated.
Entering Stop mode disables the Over-drive mode, as well as the PLL. The application
software has to configure again the Over-drive mode and the PLL after exiting from Stop
mode.
Exiting from Over-drive mode
It is recommended to exit from Over-drive mode when the application is not running critical
tasks and when the system clock source is either HSI or HSE.There are two sequences that
allow exiting from over-drive mode:
•
By resetting simultaneously the ODEN and ODSW bits bit in the PWR_CR1 register
(sequence 1)
•
By resetting first the ODSW bit to switch the voltage regulator to Normal mode and then
resetting the ODEN bit to disable the Over-drive mode (sequence 2).
Example of sequence 1:
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1.
Select HSI or HSE as system clock source.
2.
Disable the peripheral clocks that are not generated by the System PLL (I2S clock,
LCD-TFT clock, SAI1 clock, USB_48MHz clock,....)
3.
Reset simultaneously the ODEN and the ODSW bits in the PWR_CR1 register to
switch back the voltage regulator to Normal mode and disable the Over-drive mode.
4.
Wait for the ODWRDY flag of PWR_CSR1 to be reset.
DocID026670 Rev 6
RM0385
Power controller (PWR)
Example of sequence 2:
1.
Select HSI or HSE as system clock source.
2.
Disable the peripheral clocks that are not generated by the System PLL (I2S clock,
LCD-TFT clock, SAI1 clock, USB_48MHz clock,....).
3.
Reset the ODSW bit in the PWR_CR1 register to switch back the voltage regulator to
Normal mode. The system clock is stalled during voltage switching.
4.
Wait for the ODWRDY flag of PWR_CSR1 to be reset.
5.
Reset the ODEN bit in the PWR_CR1 register to disable the Over-drive mode.
Note:
During step 3, the ODEN bit remains set and the Over-drive mode is still enabled but not
active (ODSW bit is reset). If the ODEN bit is reset instead, the Over-drive mode is disabled
and the voltage regulator is switched back to the initial voltage.
4.2
Power supply supervisor
4.2.1
Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows proper operation starting
from 1.8 V.
The device remains in Reset mode when VDD/VDDA is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power-down reset threshold, refer to the electrical characteristics of the
datasheet.
Figure 8. Power-on reset/power-down reset waveform
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Power controller (PWR)
4.2.2
RM0385
Brownout reset (BOR)
During power on, the Brownout reset (BOR) keeps the device under reset until the supply
voltage reaches the specified VBOR threshold.
VBOR is configured through device option bytes. By default, BOR is off. 3 programmable
VBOR threshold levels can be selected:
Note:
•
BOR Level 3 (VBOR3). Brownout threshold level 3.
•
BOR Level 2 (VBOR2). Brownout threshold level 2.
•
BOR Level 1 (VBOR1). Brownout threshold level 1.
For full details about BOR characteristics, refer to the "Electrical characteristics" section in
the device datasheet.
When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is
generated.
The BOR can be disabled by programming the device option bytes. In this case, the
power-on and power-down is then monitored by the POR/ PDR (see Section 4.2.1: Poweron reset (POR)/power-down reset (PDR)).
The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the
supply voltage).
Figure 9. BOR thresholds
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4.2.3
Programmable voltage detector (PVD)
You can use the PVD to monitor the VDD power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to
indicate if VDD is higher or lower than the PVD threshold. This event is internally connected
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Power controller (PWR)
to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The
PVD output interrupt can be generated when VDD drops below the PVD threshold and/or
when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge
configuration. As an example the service routine could perform emergency shutdown tasks.
Figure 10. PVD thresholds
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4.3
Low-power modes
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, short startup time and available
wakeup sources.
The devices feature three low-power modes:
•
Sleep mode (Cortex®-M7 core stopped, peripherals kept running)
•
Stop mode (all clocks are stopped)
•
Standby mode (1.2 V domain powered off)
In addition, the power consumption in Run mode can be reduce by one of the following
means:
•
Slowing down the system clocks
•
Gating the clocks to the APBx and AHBx peripherals when they are unused.
Entering low-power mode
Low-power modes are entered by the MCU by executing the WFI (Wait For Interrupt), or
WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M7
System Control register is set on Return from ISR.
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Entering Low-power mode through WFI or WFE will be executed only if no interrupt is
pending or no event is pending.
Exiting low-power mode
The MCU exits from Sleep and Stop modes low-power mode depending on the way the lowpower mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device.
•
If the WFE instruction is used to enter the low-power mode, the MCU exits the lowpower mode as soon as an event occurs. The wakeup event can be generated either
by:
–
NVIC IRQ interrupt:
When SEVONPEND = 0 in the Cortex®-M7 System Control register: by enabling
an interrupt in the peripheral control register and in the NVIC. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the NVIC peripheral
IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be
cleared. Only NVIC interrupts with sufficient priority will wakeup and interrupt the
MCU.
When SEVONPEND = 1 in the Cortex®-M7 System Control register: by enabling
an interrupt in the peripheral control register and optionally in the NVIC. When the
MCU resumes from WFE, the peripheral interrupt pending bit and when enabled
the NVIC peripheral IRQ channel pending bit (in the NVIC interrupt clear pending
register) have to be cleared. All NVIC interrupts will wakeup the MCU, even the
disabled ones.Only enabled NVIC interrupts with sufficient priority will wakeup and
interrupt the MCU.
–
Event
This is done by configuring a EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the EXTI peripheral interrupt pending bit or
the NVIC IRQ channel pending bit as the pending bits corresponding to the event
line is not set. It may be necessary to clear the interrupt flag in the peripheral.
The MCU exits from Standby low-power mode through an external reset (NRST pin), an
IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event occurs (see
Figure 284: RTC block diagram).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, option bytes loading, reset vector is fetched, etc.).
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
Table 12. Low-power mode summary
Mode name
Entry
Wakeup
Sleep
(Sleep now
or Sleep-onexit)
WFI
Any interrupt
WFE
Wakeup event
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Effect on 1.2 V
domain clocks
Effect on
VDD
domain
clocks
Voltage regulator
CPU CLK OFF
no effect on other
clocks or analog
clock sources
None
ON
DocID026670 Rev 6
RM0385
Power controller (PWR)
Table 12. Low-power mode summary (continued)
Mode name
Any EXTI line (configured
in the EXTI registers,
internal and external lines)
WKUP pin rising or falling
edge, RTC alarm (Alarm A
PDDS bit +
or Alarm B), RTC Wakeup
SLEEPDEEP bit event, RTC tamper events,
+ WFI or WFE
RTC time stamp event,
external reset in NRST
pin, IWDG reset
HSI and
HSE
oscillators
OFF
All 1.2 V domain
clocks OFF
Voltage regulator
Main regulator or
Low-power
regulator (depends
on PWR power
control register
(PWR_CR1))
OFF
Table 13. Features over all modes (1)
Stop
Standby
-
-
-
-
-
-
Flash access
Y
Y
-
-
-
-
-
DTCM RAM
Y
Y
Y
-
-
-
-
ITCM RAM
Y
Y
Y
-
-
-
-
SRAM1
Y
Y
Y
-
-
-
-
SRAM2
Y
Y
Y
-
-
-
-
FMC
O
O
-
-
-
-
-
QUADSPI
O
O
-
-
-
-
-
Backup Registers
Y
Y
Y
-
Y
-
Y
Backup RAM
Y
Y
Y
-
Y
-
Y
Brown-out reset (BOR)
Y
Y
Y
Y
Y
Y
Programmable Voltage
Detector (PVD)
O
O
O
O
-
-
-
High Speed Internal (HSI)
O
O
(2)
-
-
-
-
High Speed External (HSE)
O
O
-
-
-
-
Low Speed Internal (LSI)
O
O
O
-
O
-
-
Low Speed External (LSE)
O
O
O
-
O
-
O
RTC
O
O
O
O
O
O
O
DocID026670 Rev 6
VBAT
Y
Wakeup
CPU
Peripheral
Wakeup
Sleep
Standby
SLEEPDEEP bit
+ WFI or WFE
Wakeup
Run
Stop
Entry
Effect on
VDD
domain
clocks
Effect on 1.2 V
domain clocks
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Table 13. Features over all modes (continued)(1)
3
3
3
3
2
CRC calculation unit
O
O
-
-
-
-
-
GPIOs
Y
Y
Y
Y
-
6 pins
2
tamper
DMA
O
O
-
-
-
-
-
Chrom-Art Accelerator
(DMA2D)
O
O
-
-
-
-
-
LCD-TFT
O
O
-
-
-
-
-
DCMI
O
O
-
-
-
-
-
USARTx (x=1..8)
O
O
-
-
-
-
-
I2Cx (x=1,2,3,4)
O
O
-
-
-
-
-
SPIx (x=1..6)
O
O
-
-
-
-
-
SAIx (x=1,2)
O
O
-
-
-
-
-
SPDIFRX
O
O
-
-
-
-
-
ADCx (x=1,2,3)
O
O
-
-
-
-
-
DACx (x=1,2)
O
O
-
-
-
-
-
Temperature sensor
O
O
-
-
-
-
-
Timers (TIMx)
O
O
-
-
-
-
-
Low-power timer 1 (LPTIM1)
O
O
O
O
-
-
-
Independent watchdog (IWDG)
O
O
O
O
O
O
-
Window watchdog (WWDG)
O
O
-
-
-
-
-
Systick timer
O
O
-
-
-
-
-
Random number generator
(RNG)
O
O
-
-
-
-
-
Cryptographic processor
(CRYP)
O
O
-
-
-
-
-
Hash processor (HASH)
O
O
-
-
-
-
-
SDMMC
O
O
-
-
-
-
-
CANx ( x=1,2)
O
O
-
-
-
-
-
USB OTG FS
O
O
-
O
-
-
-
USB OTG HS
O
O
-
O
-
-
-
Ethernet
O
O
-
O
-
-
-
HDMI-CEC
O
O
-
-
-
-
-
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VBAT
3
Wakeup
3
Wakeup
Sleep
Number of RTC tamper pins
Peripheral
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Standby
Run
Stop
RM0385
Power controller (PWR)
1. Legend: Y = Yes (Enable). O = Optional (Disable by default. Can be enabled by software). - = Not
available. Wakeup highlighted in gray.
2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is
woken up by the peripheral, and only feeds the peripheral which requested it. HSI is automatically put off
when the peripheral does not need it anymore.
4.3.1
Debug mode
By default, the debug connection is lost when the devices enters in Stop or Standby mode
while the debug features are used. This is due to the fact that the Cortex®-M7 core is no
longer clocked.
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 40.16.1: Debug support for low-power modes.
4.3.2
Run mode
Slowing down system clocks
In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be
reduced by programming the prescaler registers. These prescalers can also be used to slow
down peripherals before entering Sleep mode.
For more details refer to Section 5.3.3: RCC clock configuration register (RCC_CFGR).
Peripheral clock gating
In Run mode, the HCLKx and PCLKx for individual peripherals and memories can be
stopped at any time to reduce power consumption.
To further reduce power consumption in Sleep mode the peripheral clocks can be disabled
prior to executing the WFI or WFE instructions.
Peripheral clock gating is controlled by the AHB1 peripheral clock enable register
(RCC_AHB1ENR), AHB2 peripheral clock enable register (RCC_AHB2ENR), AHB3
peripheral clock enable register (RCC_AHB3ENR) (see Section 5.3.10: RCC AHB1
peripheral clock register (RCC_AHB1ENR), Section 5.3.11: RCC AHB2 peripheral clock
enable register (RCC_AHB2ENR), and Section 5.3.12: RCC AHB3 peripheral clock enable
register (RCC_AHB3ENR).
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in RCC_AHBxLPENR and RCC_APBxLPENR registers.
4.3.3
Low-power mode
Entering low-power mode
Low-power modes are entered by the MCU executing the WFI (Wait For Interrupt), or WFE
(Wait For Event) instructions, or when the SLEEPONEXIT bit in the Cortex®-M7 System
Control register is set on Return from ISR.
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Exiting low-power mode
From Sleep and Stop modes the MCU exits low-power mode depending on the way the
mode was entered:
•
If the WFI instruction or Return from ISR was used to enter the low-power mode, any
peripheral interrupt acknowledged by the NVIC can wake up the device
•
If the WFE instruction was used to enter the low-power mode, the MCU exits the mode
as soon as an event occurs. The wakeup event can by generated either by:
–
NVIC IRQ interrupt
- When SEVEONPEND=0 in the Cortex®-M7 System Control register.
By enabling an interrupt in the peripheral control register and in the NVIC. When
the MCU resumes from WFE, the peripheral interrupt pending bit and the NVIC
peripheral IRQ channel pending bit (in the NVIC interrupt clear pending register)
have to be cleared.
Only NVIC interrupts with sufficient priority will wakeup and interrupt the MCU.
- When SEVEONPEND=1 in the Cortex®-M7 System Control register.
By enabling an interrupt in the peripheral control register and optionally in the
NVIC. When the MCU resumes from WFE, the peripheral interrupt pending bit and
(when enabled) the NVIC peripheral IRQ channel pending bit (in the NVIC
interrupt clear pending register) have to be cleared.
All NVIC interrupts will wakeup the MCU, even the disabled ones.
Only enabled NVIC interrupts with sufficient priority will wakeup and interrupt the
MCU.
- Event
Configuring a EXTI line in event mode. When the CPU resumes from WFE, it is
not necessary to clear the EXTI peripheral interrupt pending bit or the NVIC IRQ
channel pending bit as the pending bits corresponding to the event line is not set.
It may be necessary to clear the interrupt flag in the peripheral.
From Standby mode the MCU exits Low-power mode through an external reset (NRST pin),
an IWDG reset, a rising edge on one of the enabled WKUPx pins or a RTC event (see
Figure 284: RTC block diagram).
4.3.4
Sleep mode
I/O states in Sleep mode
In Sleep mode, all I/O pins keep the same state as in Run mode.
Entering Sleep mode
The Sleep mode is entered by executing the WFI (Wait For Interrupt) or WFE (Wait for
Event) instructions. Two options are available to select the Sleep mode entry mechanism,
depending on the SLEEPONEXIT bit in the Cortex®-M7 System Control register:
•
Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon
as WFI or WFE instruction is executed.
•
Sleep-on-exit: if the SLEEPONEXIT bit is set, the MCU enters Sleep mode as soon as
it exits the lowest priority ISR.
Refer to Table 14 and Table 15 for details on how to enter Sleep mode.
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Exiting Sleep mode
If the WFI instruction is used to enter Sleep mode, any peripheral interrupt acknowledged by
the nested vectored interrupt controller (NVIC) can wake up the device from Sleep mode.
If the WFE instruction is used to enter Sleep mode, the MCU exits Sleep mode as soon as
an event occurs. The wakeup event can be generated either by:
•
Enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M7 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
•
Or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
This mode offers the lowest wakeup time as no time is wasted in interrupt entry/exit.
Refer to Table 14 and Table 15 for more details on how to exit Sleep mode.
Table 14. Sleep-now entry and exit
Sleep-now mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0, and
– No interrupt (for WFI) or event (for WFE) is pending.
Refer to the Cortex®-M7 System Control register.
Mode entry
On Return from ISR while:
– SLEEPDEEP = 0 and
– SLEEPONEXIT = 1,
– No interrupt is pending.
Refer to the Cortex®-M7 System Control register.
Mode exit
If WFI or Return from ISR was used for entry:
Interrupt: Refer to Table 43: STM32F75xxx and STM32F74xxx vector
table
If WFE was used for entry and SEVONPEND = 0
Wakeup event: Refer to Section 11.3: Wakeup event management
If WFE was used for entry and SEVONPEND = 1
Interrupt even when disabled in NVIC: refer to Table 43: STM32F75xxx
and STM32F74xxx vector table and Wakeup event (see Section 11.3:
Wakeup event management).
Wakeup latency
None
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Table 15. Sleep-on-exit entry and exit
Sleep-on-exit
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP = 0, and
– No interrupt (for WFI) or event (for WFE) is pending.
Refer to the Cortex®-M7 System Control register.
4.3.5
Mode entry
On Return from ISR while:
– SLEEPDEEP = 0, and
– SLEEPONEXIT = 1, and
– No interrupt is pending.
Refer to the Cortex®-M7 System Control register.
Mode exit
Interrupt: refer to Table 43: STM32F75xxx and STM32F74xxx vector table
Wakeup latency
None
Stop mode
The Stop mode is based on the Cortex®-M7 deepsleep mode combined with peripheral
clock gating. The voltage regulator can be configured either in normal or low-power mode.
In Stop mode, all clocks in the 1.2 V domain are stopped, the PLLs, the HSI and the HSE
RC oscillators are disabled. Internal SRAM and register contents are preserved.
In Stop mode, the power consumption can be further reduced by using additional settings in
the PWR_CR1 register. However this will induce an additional startup delay when waking up
from Stop mode (see Table 16).
Table 16. Stop operating modes
UDEN[1:0]
bits
MRUDS
bit
LPUDS
bit
STOP MR
(Main Regulator)
-
0
-
0
0
HSI RC startup time
STOP MR- FPD
-
0
-
0
1
HSI RC startup time +
Flash wakeup time from powerdown mode
STOP LP
-
0
0
1
0
HSI RC startup time +
regulator wakeup time from LP
mode
1
HSI RC startup time +
Flash wakeup time from powerdown mode +
regulator wakeup time from LP
mode
Voltage Regulator Mode
Normal
mode
STOP LP-FPD
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-
-
0
LPDS FPDS
bit
bit
1
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Table 16. Stop operating modes (continued)
Voltage Regulator Mode
STOP UMRFPD
UDEN[1:0]
bits
3
MRUDS
bit
1
LPUDS
bit
-
LPDS FPDS
bit
bit
0
-
HSI RC startup time +
Flash wakeup time from powerdown mode +
Main regulator wakeup time from
under-drive mode + Core logic to
nominal mode
-
HSI RC startup time +
Flash wakeup time from powerdown mode +
regulator wakeup time from LP
under-drive mode + Core logic to
nominal mode
Underdrive
Mode
STOP ULP-FPD
3
-
1
1
Wakeup latency
I/O states in Stop mode
In stop mode, all I/Os pins keep the same state as in the run mode
Entering Stop mode
The Stop mode is entered according to Entering low-power mode, when the SLEEPDEEP
bit in Cortex®-M7 System Control register is set.
Refer to Table 17 for details on how to enter the Stop mode.
When the microcontroller enters in Stop mode, the voltage scale 3 is automatically selected.
To further reduce power consumption in Stop mode, the internal voltage regulator can be put
in low-power or low voltage mode. This is configured by the LPDS, MRUDS, LPUDS and
UDEN bits of the PWR power control register (PWR_CR1).
If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory
access is finished.
If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB
access is finished.
If the Over-drive mode was enabled before entering Stop mode, it is automatically disabled
during when the Stop mode is activated.
In Stop mode, the following features can be selected by programming individual control bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a Reset. See
Section 27.3 in Section 27: Independent watchdog (IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the RCC backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC clock
control & status register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
RCC backup domain control register (RCC_BDCR).
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The ADC or DAC can also consume power during the Stop mode, unless they are disabled
before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit
in the DAC_CR register must both be written to 0.
Note:
Before entering Stop mode, it is recommended to enable the clock security system (CSS)
feature to prevent external oscillator (HSE) failure from impacting the internal MCU
behavior.
Exiting Stop mode
Refer to Table 17 for more details on how to exit Stop mode.
When exiting Stop mode by issuing an interrupt or a wakeup event, the HSI RC oscillator is
selected as system clock.
If the Under-drive mode was enabled, it is automatically disabled after exiting Stop mode.
When the voltage regulator operates in low-power mode, an additional startup delay is
incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop
mode, the consumption is higher although the startup time is reduced.
When the voltage regulator operates in Under-drive mode, an additional startup delay is
induced when waking up from Stop mode.
Table 17. Stop mode entry and exit (STM32F75xxx and STM32F74xxx)
Stop mode
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– No interrupt (for WFI) or event (for WFE) is pending.
– SLEEPDEEP bit is set in Cortex®-M7 System Control register,
– PDDS bit is cleared in Power Control register (PWR_CR1),
– Select the voltage regulator mode by configuring LPDS, MRUDS, LPUDS
and UDEN bits in PWR_CR (see Table 16: Stop operating modes).
Mode entry
On Return from ISR while:
– No interrupt is pending,
– SLEEPDEEP bit is set in Cortex®-M7 System Control register, and
– SLEEPONEXIT = 1, and
– PDDS is cleared in Power Control register (PWR_CR1).
Note: To enter Stop mode, all EXTI Line pending bits (in Pending register
(EXTI_PR)), all peripheral interrupts pending bits, the RTC Alarm
(Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time
stamp flags, must be reset. Otherwise, the Stop mode entry
procedure is ignored and program execution continues.
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Table 17. Stop mode entry and exit (STM32F75xxx and STM32F74xxx) (continued)
Stop mode
4.3.6
Description
Mode exit
If WFI or Return from ISR was used for entry:
All EXTI lines configured in Interrupt mode (the corresponding EXTI
Interrupt vector must be enabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 43: STM32F75xxx and STM32F74xxx vector table on page 285.
If WFE was used for entry and SEVONPEND = 0:
All EXTI Lines configured in event mode. Refer to Section 11.3: Wakeup
event management on page 291
If WFE was used for entry and SEVONPEND = 1:
– Any EXTI lines configured in Interrupt mode (even if the corresponding
EXTI Interrupt vector is disabled in the NVIC). The interrupt source can
be external interrupts or peripherals with wakeup capability. Refer to
Table 43: STM32F75xxx and STM32F74xxx vector table on page 285.
– Wakeup event: refer to Section 11.3: Wakeup event management on
page 291.
Wakeup latency
Refer to Table 16: Stop operating modes
Standby mode
The Standby mode allows to achieve the lowest power consumption. It is based on the
Cortex®-M7 deepsleep mode, with the voltage regulator disabled. The 1.2 V domain is
consequently powered off. The PLLs, the HSI oscillator and the HSE oscillator are also
switched off. SRAM and register contents are lost except for registers in the backup domain
(RTC registers, RTC backup register and backup SRAM), and Standby circuitry (see
Figure 4).
Entering Standby mode
The Standby mode is entered according to Entering low-power mode, when the
SLEEPDEEP bit in the Cortex®-M7 System Control register is set.
Refer to Table 18 for more details on how to enter Standby mode.
In Standby mode, the following features can be selected by programming individual control
bits:
•
Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by
hardware option. Once started it cannot be stopped except by a reset. See
Section 27.3 in Section 27: Independent watchdog (IWDG).
•
Real-time clock (RTC): this is configured by the RTCEN bit in the backup domain
control register (RCC_BDCR)
•
Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status
register (RCC_CSR).
•
External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the
backup domain control register (RCC_BDCR)
Exiting Standby mode
The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG
Reset, a rising or falling edge on WKUP pin, an RTC alarm, a tamper event, or a time stamp
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event is detected. All registers are reset after wakeup from Standby except for PWR power
control/status register (PWR_CSR1).
After waking up from Standby mode, program execution restarts in the same way as after a
Reset (boot pin sampling, vector reset is fetched, etc.). The SBF status flag in the PWR
power control/status register (PWR_CSR1) indicates that the MCU was in Standby mode.
Refer to Table 18 for more details on how to exit Standby mode.
Table 18. Standby mode entry and exit
Standby mode
Mode entry
Description
WFI (Wait for Interrupt) or WFE (Wait for Event) while:
– SLEEPDEEP is set in Cortex®-M7 System Control register,
– PDDS bit is set in Power Control register (PWR_CR1),
– No interrupt (for WFI) or event (for WFE) is pending,
– WUIF bit is cleared in Power Control and Status register (PWR_CSR1),
– the RTC flag corresponding to the chosen wakeup source (RTC Alarm A,
RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared.
– EIWUP bit is set in Power Control register (PWR_CSR1).
On return from ISR while:
– SLEEPDEEP bit is set in Cortex®-M7 System Control register, and
– SLEEPONEXIT = 1, and
– PDDS bit is set in Power Control register (PWR_CR1), and
– No interrupt is pending,
– WUIF bit is cleared in Power Control and Status register (PWR_CSR1),
– The RTC flag corresponding to the chosen wakeup source (RTC Alarm
A, RTC Alarm B, RTC wakeup, Tamper or Timestamp flags) is cleared.
Mode exit
WKUP pin rising or falling edge, RTC alarm (Alarm A and Alarm B), RTC
wakeup, tamper event, time stamp event, external reset in NRST pin,
IWDG reset.
Wakeup latency
Reset phase.
I/O states in Standby mode
In Standby mode, all I/O pins are high impedance except for:
4.3.7
•
Reset pad (still available)
•
PC13 if configured for tamper, time stamp, RTC Alarm out, or RTC clock calibration out
•
WKUP pins (PA0/PA2/PC1/PC13/PI8/PI11), if enabled
Programming the RTC alternate functions to wake up the device from
the Stop and Standby modes
The MCU can be woken up from a low-power mode by an RTC alternate function.
The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), RTC wakeup, RTC
tamper event detection and RTC time stamp event detection.
These RTC alternate functions can wake up the system from the Stop and Standby lowpower modes.
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The system can also wake up from low-power modes without depending on an external
interrupt (Auto-wakeup mode), by using the RTC alarm or the RTC wakeup events.
The RTC provides a programmable time base for waking up from the Stop or Standby mode
at regular intervals.
For this purpose, two of the three alternate RTC clock sources can be selected by
programming the RTCSEL[1:0] bits in the RCC backup domain control register
(RCC_BDCR):
•
Low-power 32.768 kHz external crystal oscillator (LSE OSC)
This clock source provides a precise time base with a very low-power consumption
(additional consumption of less than 1 µA under typical conditions)
•
Low-power internal RC oscillator (LSI RC)
This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This
internal RC oscillator is designed to use minimum power.
RTC alternate functions to wake up the device from the Stop mode
•
•
•
To wake up the device from the Stop mode with an RTC alarm event, it is necessary to:
a)
Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC Alarm Interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC alarm
To wake up the device from the Stop mode with an RTC tamper or time stamp event, it
is necessary to:
a)
Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC time stamp Interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
c)
Configure the RTC to detect the tamper or time stamp event
To wake up the device from the Stop mode with an RTC wakeup event, it is necessary
to:
a)
Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt or Event
modes)
b)
Enable the RTC wakeup interrupt in the RTC_CR register
c)
Configure the RTC to generate the RTC Wakeup event
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RTC alternate functions to wake up the device from the Standby mode
•
•
•
To wake up the device from the Standby mode with an RTC alarm event, it is necessary
to:
a)
Enable the RTC alarm interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC alarm
c)
Enable the RTC internal wakeup event from standby by setting the EIWUP bit in
the PWR_CSR1 register
To wake up the device from the Standby mode with an RTC tamper or time stamp
event, it is necessary to:
a)
Enable the RTC time stamp interrupt in the RTC_CR register or the RTC tamper
interrupt in the RTC_TAFCR register
b)
Configure the RTC to detect the tamper or time stamp event
c)
Enable the RTC internal wakeup event from standby by setting the EIWUP bit in
the PWR_CSR1 register
To wake up the device from the Standby mode with an RTC wakeup event, it is
necessary to:
a)
Enable the RTC wakeup interrupt in the RTC_CR register
b)
Configure the RTC to generate the RTC wakeup event
c)
Enable the RTC internal wakeup event from standby by setting the EIWUP bit in
the PWR_CSR1 register
Safe RTC alternate function wakeup flag clearing sequence
To avoid bouncing on the pins onto which the RTC alternate functions are mapped, and exit
correctly from the Stop and Standby modes, it is recommended to follow the sequence
below before entering the Standby mode:
•
•
•
•
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When using RTC alarm to wake up the device from the low-power modes:
a)
Disable the RTC alarm interrupt (ALRAIE or ALRBIE bits in the RTC_CR register)
b)
Clear the RTC alarm (ALRAF/ALRBF) flag
c)
Enable the RTC alarm interrupt
d)
Re-enter the low-power mode
When using RTC wakeup to wake up the device from the low-power modes:
a)
Disable the RTC Wakeup interrupt (WUTIE bit in the RTC_CR register)
b)
Enable the RTC Wakeup interrupt
c)
Re-enter the low-power mode
When using RTC tamper to wake up the device from the low-power modes:
a)
Disable the RTC tamper interrupt (TAMPIE bit in the RTC_TAFCR register)
b)
Clear the Tamper (TAMP1F/TSF) flag
c)
Enable the RTC tamper interrupt
d)
Re-enter the low-power mode
When using RTC time stamp to wake up the device from the low-power modes:
a)
Disable the RTC time stamp interrupt (TSIE bit in RTC_CR)
b)
Clear the RTC time stamp (TSF) flag
c)
Enable the RTC TimeStamp interrupt
d)
Re-enter the low-power mode
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4.4
Power control registers
4.4.1
PWR power control register (PWR_CR1)
Address offset: 0x00
Reset value: 0x0000 C000 (reset by wakeup from Standby mode)
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
Res.
22
Res.
21
Res.
20
Res.
19
UDEN[1:0]
rw
15
14
VOS[1:0]
rw
rw
13
12
ADCDC1 Res.
rw
11
10
9
8
MRUDS
LPUDS
FPDS
DBP
rw
rw
rw
rw
7
6
5
PLS[2:0]
rw
rw
rw
18
rw
17
16
ODSWE
ODEN
N
rw
rw
4
3
2
1
0
PVDE
CSBF
Res.
PDDS
LPDS
rw
rc_w1
rw
rw
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 UDEN[1:0]: Under-drive enable in stop mode
These bits are set by software. They allow to achieve a lower power consumption in Stop
mode but with a longer wakeup time.
When set, the digital area has less leakage consumption when the device enters Stop mode.
00: Under-drive disable
01: Reserved
10: Reserved
11:Under-drive enable
Bit 17 ODSWEN: Over-drive switching enabled.
This bit is set by software. It is cleared automatically by hardware after exiting from Stop
mode or when the ODEN bit is reset. When set, It is used to switch to Over-drive mode.
To set or reset the ODSWEN bit, the HSI or HSE must be selected as system clock.
The ODSWEN bit must only be set when the ODRDY flag is set to switch to Over-drive
mode.
0: Over-drive switching disabled
1: Over-drive switching enabled
Note: On any over-drive switch (enabled or disabled), the system clock will be stalled during
the internal voltage set up.
Bit 16 ODEN: Over-drive enable
This bit is set by software. It is cleared automatically by hardware after exiting from Stop
mode. It is used to enabled the Over-drive mode in order to reach a higher frequency.
To set or reset the ODEN bit, the HSI or HSE must be selected as system clock. When the
ODEN bit is set, the application must first wait for the Over-drive ready flag (ODRDY) to be
set before setting the ODSWEN bit.
0: Over-drive disabled
1: Over-drive enabled
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Bits 15:14 VOS[1:0]: Regulator voltage scaling output selection
These bits control the main internal voltage regulator output voltage to achieve a trade-off
between performance and power consumption when the device does not operate at the
maximum frequency (refer to the STM32F75xxx and STM32F74xxx datasheets for more
details).
These bits can be modified only when the PLL is OFF. The new value programmed is active
only when the PLL is ON. When the PLL is OFF, the voltage scale 3 is automatically
selected.
00: Reserved (Scale 3 mode selected)
01: Scale 3 mode
10: Scale 2 mode
11: Scale 1 mode (reset value)
Bit 13 ADCDC1:
0: No effect.
1: Refer to AN4073 for details on how to use this bit.
Note: This bit can only be set when operating at supply voltage range 2.7 to 3.6V.
Bit 12 Reserved, must be kept at reset value.
Bit 11 MRUDS: Main regulator in deepsleep under-drive mode
This bit is set and cleared by software.
0: Main regulator ON when the device is in Stop mode
1: Main Regulator in under-drive mode and Flash memory in power-down when the device is
in Stop under-drive mode.
Bit 10 LPUDS: Low-power regulator in deepsleep under-drive mode
This bit is set and cleared by software.
0: Low-power regulator ON if LPDS bit is set when the device is in Stop mode
1: Low-power regulator in under-drive mode if LPDS bit is set and Flash memory in powerdown when the device is in Stop under-drive mode.
Bit 9 FPDS: Flash power-down in Stop mode
When set, the Flash memory enters power-down mode when the device enters Stop mode.
This allows to achieve a lower consumption in stop mode but a longer restart time.
0: Flash memory not in power-down when the device is in Stop mode
1: Flash memory in power-down when the device is in Stop mode
Bit 8 DBP: Disable backup domain write protection
In reset state, the RCC_BDCR register, the RTC registers (including the backup registers),
and the BRE bit of the PWR_CSR1 register, are protected against parasitic write access. This
bit must be set to enable write access to these registers.
0: Access to RTC and RTC Backup registers and backup SRAM disabled
1: Access to RTC and RTC Backup registers and backup SRAM enabled
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Power controller (PWR)
Bits 7:5 PLS[2:0]: PVD level selection
These bits are written by software to select the voltage threshold detected by the Power
Voltage Detector
000: 2.0 V
001: 2.1 V
010: 2.3 V
011: 2.5 V
100: 2.6 V
101: 2.7 V
110: 2.8 V
111: 2.9 V
Note: Refer to the electrical characteristics of the datasheet for more details.
Bit 4 PVDE: Power voltage detector enable
This bit is set and cleared by software.
0: PVD disabled
1: PVD enabled
Bit 3 CSBF: Clear standby flag
This bit is always read as 0.
0: No effect
1: Clear the SDF Standby Flag (write)
Bit 2 Reserved, must be kept at reset value
Bit 1 PDDS: Power-down deepsleep
This bit is set and cleared by software. It works together with the LPDS bit.
0: Enter Stop mode when the CPU enters deepsleep. The regulator status depends on the
LPDS bit.
1: Enter Standby mode when the CPU enters deepsleep.
Bit 0 LPDS: Low-power deepsleep
This bit is set and cleared by software. It works together with the PDDS bit.
0:Main voltage regulator ON during Stop mode
1: Low-power voltage regulator ON during Stop mode
4.4.2
PWR power control/status register (PWR_CSR1)
Address offset: 0x04
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rc_w1
rc_w1
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
VOS
RDY
Res.
Res.
Res.
Res.
BRE
EIWUP
Res.
Res.
Res.
Res.
BRR
PVDO
SBF
WUIF
rw
rw
r
r
r
r
r
DocID026670 Rev 6
19
18
UDRDY[1:0]
17
16
ODSWRDY ODRDY
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Power controller (PWR)
RM0385
Bits 31:20 Reserved, must be kept at reset value.
Bits 19:18 UDRDY[1:0]: Under-drive ready flag
These bits are set by hardware when the Under-drive mode is enabled in Stop mode and
cleared by programming them to 1.
00: Under-drive is disabled
01: Reserved
10: Reserved
11:Under-drive mode is activated in Stop mode.
Bit 17 ODSWRDY: Over-drive mode switching ready
0: Over-drive mode is not active.
1: Over-drive mode is active on digital area on 1.2 V domain
Bit 16 ODRDY: Over-drive mode ready
0: Over-drive mode not ready.
1: Over-drive mode ready
Bit 14 VOSRDY: Regulator voltage scaling output selection ready bit
0: Not ready
1: Ready
Bits 13:10 Reserved, must be kept at reset value.
Bit 9 BRE: Backup regulator enable
When set, the Backup regulator (used to maintain backup SRAM content in Standby and
VBAT modes) is enabled. If BRE is reset, the backup regulator is switched off. The backup
SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
the data written into the RAM will be maintained in the Standby and VBAT modes.
0: Backup regulator disabled
1: Backup regulator enabled
Note: This bit is not reset when the device wakes up from Standby mode, by a system reset,
or by a power reset.
Bit 8 EIWUP: Enable internal wakeup
This bit must be set when RTC events (Alarm A or Alarm B, RTC Tamper, RTC TimeStamp
or RTC Wakeup time) are used to wake up the system from Standby mode.
This bit is always read as 0.
0: Disable internal wakeup sources (RTC events) during Standby mode
1: Enable internal wakeup sources (RTC events) during Standby mode
Bits 7:4 Reserved, must be kept at reset value.
Bit 3 BRR: Backup regulator ready
Set by hardware to indicate that the Backup Regulator is ready.
0: Backup Regulator not ready
1: Backup Regulator ready
Note: This bit is not reset when the device wakes up from Standby mode or by a system reset
or power reset.
Bit 2 PVDO: PVD output
This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit.
0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits.
1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits.
Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after
Standby or reset until the PVDE bit is set.
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RM0385
Power controller (PWR)
Bit 1 SBF: Standby flag
This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down
reset) or by setting the CSBF bit in the PWR power control register (PWR_CR1)
0: Device has not been in Standby mode
1: Device has been in Standby mode
Bit 0 WUIF: Wakeup internal flag
This bit is set when a wakeup is detected on the internal wakeup line in standby mode. It is
cleared when all internal wakeup sources are cleared.
0: No wakeup internal event occurred
1: A wakeup event was detected from the RTC alarm (Alarm A or Alarm B), RTC Tamper
event, RTC TimeStamp event or RTC Wakeup
4.4.3
PWR power control/status register 2 (PWR_CR2)
Address offset: 0x08
Reset value: 0x0000 0000 (not reset by wakeup from Standby mode)
31
30
Res. Res.
15
14
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
13
12
11
10
9
8
23
22
Res. Res.
7
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
5
4
3
2
1
0
6
Res. Res. WUPP6 WUPP5 WUPP4 WUPP3 WUPP2 WUPP1 Res. Res. CWUPF6 CWUPF5 CWUPF4 CWUPF3 CWUPF2 CWUPF1
rw
rw
rw
rw
rw
rw
r
r
r
r
r
r
Bits 31:14 Reserved, always read as 0.
Bits 13 WUPP6: Wakeup pin polarity bit for PI11
These bits define the polarity used for event detection on external wake-up pin PI11.
0: Detection on rising edge
1: Detection on falling edge
Bit 12 WUPP5: Wakeup pin polarity bit for PI8
These bits define the polarity used for event detection on external wake-up pin PI8.
0: Detection on rising edge
1: Detection on falling edge
Bit 11 WUPP4: Wakeup pin polarity bit for PC13
These bits define the polarity used for event detection on external wake-up pin PC13.
0: Detection on rising edge
1: Detection on falling edge
Bit 10 WUPP3: Wakeup pin polarity bit for PC1
These bits define the polarity used for event detection on external wake-up pin PC1.
0: Detection on rising edge
1: Detection on falling edge
Bit 9 WUPP2: Wakeup pin polarity bit for PA2
These bits define the polarity used for event detection on external wake-up pin PA2.
0: Detection on rising edge
1: Detection on falling edge
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RM0385
Bit 8 WUPP1: Wakeup pin polarity bit for PA0
These bits define the polarity used for event detection on external wake-up pin PA0.
0: Detection on rising edge
1: Detection on falling edge
Bits 7:6 Reserved, always read as 0
Bit 5 CWUPF6: Clear Wakeup Pin flag for PI11
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
Bit 4 CWUPF5: Clear Wakeup Pin flag for PI8
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
Bit 3 CWUPF4: Clear Wakeup Pin flag for PC13
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
Bit 2 CWUPF3: Clear Wakeup Pin flag for PC1
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
Bit 1 CWUPF2: Clear Wakeup Pin flag for PA2
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
Bit 0 CWUPF1: Clear Wakeup Pin flag for PA0
These bits are always read as 0
0: No effect
1: Clear the WUPF Wakeup Pin flag after 2 System clock cycles.
4.4.4
PWR power control register 2 (PWR_CSR2)
Address offset: 0x0C
Reset value: 0x0000 0000 (reset by wakeup from Standby mode, except wakeup flags
which are reset by RESET pin)
Additional APB cycles are needed to read this register versus a standard APB read.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
WUPF2
WUPF1
r
r
EWUP6 EWUP5 EWUP4 EWUP3 EWUP2 EWUP1
rw
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rw
rw
rw
Res.
Res. WUPF6 WUPF5 WUPF4 WUPF3
rw
DocID026670 Rev 6
r
r
r
r
RM0385
Power controller (PWR)
Bits 31:14 Reserved, always read as 0.
Bits 13 EWUP6: Enable Wakeup pin for PI11
This bit is set and cleared by software.
0: An event on WKUP pin PI11 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PI11 wakes-up the system from Standby mode.
Bit 12 EWUP5: Enable Wakeup pin for PI8
This bit is set and cleared by software.
0: An event on WKUP pin PI8 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PI8 wakes-up the system from Standby mode.
Bit 11 EWUP4: Enable Wakeup pin for PC13
This bit is set and cleared by software.
0: An event on WKUP pin PC13 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PC13 wakes-up the system from Standby mode.
Bit 10 EWUP3: Enable Wakeup pin for PC1
This bit is set and cleared by software.
0: An event on WKUP pin PC1 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PC1 wakes-up the system from Standby mode.
Bit 9 EWUP2: Enable Wakeup pin for PA2
This bit is set and cleared by software.
0: An event on WKUP pin PA2 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PA2 wakes-up the system from Standby mode.
Bit 8 EWUP1: Enable Wakeup pin for PA0
This bit is set and cleared by software.
0: An event on WKUP pin PA0 does not wake-up the device from Standby mode.
1: A rising or falling edge on WKUP pin PA0 wakes-up the system from Standby mode.
Bits 7:6 Reserved, always read as 0
Bit 5 WUPF6: Wakeup Pin flag for PI11
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF6 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PI11
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP6
bit) when WKUP pin PI11 level is already high.
Bit 4 WUPF5: Wakeup Pin flag for PI8
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF5 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PI8
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP5
bit) when WKUP pin PI8 level is already high.
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Power controller (PWR)
RM0385
Bit 3 WUPF4: Wakeup Pin flag for PC13
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF4 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PC13
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP4
bit) when WKUP pin PC13 level is already high.
Bit 2 WUPF3: Wakeup Pin flag for PC1
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF3 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PC1
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP3
bit) when WKUP pin PC1 level is already high.
Bit 1 WUPF2: Wakeup Pin flag for PA2
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF2 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PA2
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP2
bit) when WKUP pin PA2 level is already high.
Bit 0 WUPF1: Wakeup Pin flag for PA0
This bit is set by hardware and cleared only by a Reset pin or by setting the CWUPF1 bit in
the PWR power control register 2 (PWR_CR2).
0: No Wakeup event occured
1: A wakeup event is detected on WKUP PA0
Note: An additional wakeup event is detected if WKUP pin is enabled (by setting the EWUP1
bit) when WKUP pin PA0 level is already high.
4.5
PWR register map
The following table summarizes the PWR registers.
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LPDS
Res.
0
WUIF
Res.
0
0
0
0
0
Res.
Res.
0
0
PDDS
EIWUP
0
0
SBF
0
CSBF
0
PVDO
0
PVDE
DBP
0
Res.
FPDS
0
PLS[2:0]
BRR
LPUDS
1
BRE
VOS[1:0]
0
1
Res.
Res.
0
Res.
VOSRDY
0
MRUDS
0
Res.
1
ADCDC1
1
Res.
ODEN
1
Res.
0
ODSWEN
0
1
ODRDY
UDRDY[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
ODSWRDY
Reset value
Res.
PWR_CSR1
Res.
0x004
1
Res.
Reset value
UDEN[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PWR_CR1
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x000
Register
Res.
Offset
Res.
Table 19. PWR - register map and reset values
0x00C
PWR_CSR2
DocID026670 Rev 6
WUPP3
WUPP2
WUPP1
0
0
0
0
EWUP4
EWUP3
EWUP2
EWUP1
0
0
0
0
0
0
CWUPF5
CWUPF4
CWUPF3
CWUPF2
CWUPF1
0
0
0
0
0
WUPF5
WUPF4
WUPF3
WUPF2
WUPF1
Res.
CWUPF6
0
WUPF6
Res.
Res.
WUPP4
0
Res.
WUPP5
0
EWUP5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
WUPP6
Res.
Reset value
EWUP6
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PWR_CR2
Res.
Register
Res.
0x008
Res.
Offset
Res.
RM0385
Power controller (PWR)
Table 19. PWR - register map and reset values (continued)
0
0
0
0
0
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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RM0385
5
Reset and clock control (RCC)
5.1
Reset
There are three types of reset, defined as system Reset, power Reset and backup domain
Reset.
5.1.1
System reset
A system reset sets all registers to their reset values except the reset flags in the clock
controller CSR register and the registers in the Backup domain (see Figure 11).
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset)
2.
Window watchdog end of count condition (WWDG reset)
3.
Independent watchdog end of count condition (IWDG reset)
4.
A software reset (SW reset) (see Software reset)
5.
Low-power management reset (see Low-power management reset)
Software reset
The reset source can be identified by checking the reset flags in the RCC clock control &
status register (RCC_CSR).
The SYSRESETREQ bit in Cortex®-M7 Application Interrupt and Reset Control Register
must be set to force a software reset on the device. Refer to the Cortex®-M7 technical
reference manual for more details.
Low-power management reset
There are two ways of generating a low-power management reset:
1.
Reset generated when entering the Standby mode:
This type of reset is enabled by resetting the nRST_STDBY bit in the user option bytes.
In this case, whenever a Standby mode entry sequence is successfully executed, the
device is reset instead of entering the Standby mode.
2.
Reset when entering the Stop mode:
This type of reset is enabled by resetting the nRST_STOP bit in the user option bytes.
In this case, whenever a Stop mode entry sequence is successfully executed, the
device is reset instead of entering the Stop mode.
5.1.2
Power reset
A power reset is generated when one of the following events occurs:
1.
Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset
2.
When exiting the Standby mode
A power reset sets all registers to their reset values except the Backup domain (see
Figure 11)
These sources act on the NRST pin and it is always kept low during the delay phase. The
RESET service routine vector is fixed at address 0x0000_0004 in the memory map.
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Reset and clock control (RCC)
The system reset signal provided to the device is output on the NRST pin. The pulse
generator guarantees a minimum reset pulse duration of 20 µs for each internal reset
source. In case of an external reset, the reset pulse is generated while the NRST pin is
asserted low.
Figure 11. Simplified diagram of the reset circuit
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The Backup domain has two specific resets that affect only the Backup domain (see
Figure 11).
5.1.3
Backup domain reset
The backup domain reset sets all RTC registers and the RCC_BDCR register to their reset
values. The BKPSRAM is not affected by this reset. The only way of resetting the
BKPSRAM is through the Flash interface by requesting a protection level change from 1 to
0.
A backup domain reset is generated when one of the following events occurs:
5.2
1.
Software reset, triggered by setting the BDRST bit in the RCC backup domain control
register (RCC_BDCR).
2.
VDD or VBAT power on, if both supplies have previously been powered off.
Clocks
Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock
•
HSE oscillator clock
•
Main PLL (PLL) clock
The devices have the two following secondary clock sources:
•
32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and,
optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
•
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC
clock (RTCCLK)
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
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Reset and clock control (RCC)
RM0385
Figure 12. Clock tree
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1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
2. When TIMPRE bit of the RCC_DKCFGR1 register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise
TIMxCLK = 2x PCLKx.
3. When TIMPRE bit in the RCC_DCKCFGR1 register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise
TIMxCLK = 4x PCLKx.
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RM0385
Reset and clock control (RCC)
The clock controller provides a high degree of flexibility to the application in the choice of the
external crystal or the oscillator to run the core and peripherals at the highest frequency
All peripheral clocks are derived from their bus clock (HCLK,PLCK1, PCLK2) except for:
•
•
•
•
The 48MHz clock, used for USB OTG FS, SDMMC and RNG. This clock is derived
from one of the following sources:
–
main PLL VCO (PLLQ Clock)
–
PLLSAI VCO (PLLSAI clock)
The U(S)ARTs clocks which are derived from one of the following sources:
–
System clock (SYSCLK)
–
HSI clock
–
LSE clock
–
APB1 or APB2 clock (PCLK1 or PCLK2 depending on which APB is mapped the
U(S)ART)
The I2Cs clocks which are derived from one of the following sources:
–
System clock (SYSCLK)
–
HSI clock
–
APB1 clock (PCLK1)
I2S clock
To achieve high-quality audio performance, the I2S clock can be derived either from a
specific PLL (PLLI2S) or from an external clock mapped on the I2S_CKIN pin. For
more information about I2S clock frequency and precision, refer to Section 32.7.5:
Clock generator.
•
•
The SAI1 and SAI2 clocks which are derived from one of the following sources:
–
PLLSAI VCO (PLLSAIQ)
–
PLLI2S VCO ( PLLI2SQ)
–
External clock mapped on the I2S_CKIN pin.
LTDC clock
The LTDC clock is generated from a specific PLL (PLLSAI).
•
The low-power timer (LPTIM1) clock which is derived from one of the following
sources:
–
LSI clock
–
LSE clock
–
HSI clock
–
APB1 clock (PCLK1)
–
External clock mapped on LPTIM1_IN1
•
The USB OTG HS (60 MHz) clock which is provided from the external PHY
•
The Ethernet MAC clocks (TX, RX and RMII) which are provided from the external
PHY. For further information on the Ethernet configuration, please refer to
Section 38.4.4: MII/RMII selection in the Ethernet peripheral description. When the
Ethernet is used, the AHB clock frequency must be at least 25 MHz.
•
SPDIFRX clock: which is generated from PLLI2SP VCO.
•
The HDMI-CEC clock which is derived from one of the following sources:
–
LSE clock
–
HSI clock divided by 488
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•
RM0385
The RTC clock which is derived from one of the following sources:
–
LSE clock
–
LSI clock
–
HSE clock divided by 32
•
The IWDG clock which is always the LSI clock.
•
The timer clock frequencies are automatically set by hardware. There are two cases
depending on the value of TIMPRE bit in RCC_CFGR register:
–
If TIMPRE bit in RCC_DKCFGR1 register is reset:
If the APB prescaler is configured to a division factor of 1, the timer clock
frequencies (TIMxCLK) are set to PCLKx. Otherwise, the timer clock frequencies
are twice the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
–
If TIMPRE bit in RCC_DKCFGR1 register is set:
If the APB prescaler is configured to a division factor of 1, 2 or 4, the timer clock
frequencies (TIMxCLK) are set to HCLK. Otherwise, the timer clock frequencies is
four times the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.
The RCC feeds the external clock of the Cortex System Timer (SysTick) with the AHB clock
(HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex clock
(HCLK), configurable in the SysTick control and status register.
FCLK acts as Cortex®-M7 free-running clock. For more details, refer to the Cortex®-M7
technical reference manual.
5.2.1
HSE clock
The high speed external clock signal (HSE) can be generated from two possible clock
sources:
•
HSE external crystal/ceramic resonator
•
HSE external user clock
The resonator and the load capacitors have to be placed as close as possible to the
oscillator pins in order to minimize output distortion and startup stabilization time. The
loading capacitance values must be adjusted according to the selected oscillator.
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Figure 13. HSE/ LSE clock sources
Hardware configuration
26&B287
External clock
+,=
([WHUQDOFORFN
VRXUFH
06Y9
26&B,1
26&B287
Crystal/ceramic
resonators
&/
/RDG
FDSDFLWRUV
&/
06Y9
External source (HSE bypass)
In this mode, an external clock source must be provided. You select this mode by setting the
HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock
signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin while the
OSC_OUT pin should be left HI-Z. See Figure 13.
External crystal/ceramic resonator (HSE crystal)
The HSE has the advantage of producing a very accurate rate on the main clock.
The associated hardware configuration is shown in Figure 13. Refer to the electrical
characteristics section of the datasheet for more details.
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed
external oscillator is stable or not. At startup, the clock is not released until this bit is set by
hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE Crystal can be switched on and off using the HSEON bit in the RCC clock control
register (RCC_CR).
5.2.2
HSI clock
The HSI clock signal is generated from an internal 16 MHz RC oscillator and can be used
directly as a system clock, or used as PLL input.
The HSI RC oscillator has the advantage of providing a clock source at low cost (no external
components). It also has a faster startup time than the HSE crystal oscillator however, even
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with calibration the frequency is less accurate than an external crystal oscillator or ceramic
resonator.
Calibration
RC oscillator frequencies can vary from one chip to another due to manufacturing process
variations, this is why each device is factory calibrated by ST for 1% accuracy at TA= 25 °C.
After reset, the factory calibration value is loaded in the HSICAL[7:0] bits in the RCC clock
control register (RCC_CR).
If the application is subject to voltage or temperature variations this may affect the RC
oscillator speed. You can trim the HSI frequency in the application using the HSITRIM[4:0]
bits in the RCC clock control register (RCC_CR).
The HSIRDY flag in the RCC clock control register (RCC_CR) indicates if the HSI RC is
stable or not. At startup, the HSI RC output clock is not released until this bit is set by
hardware.
The HSI RC can be switched on and off using the HSION bit in the RCC clock control
register (RCC_CR).
The HSI signal can also be used as a backup source (Auxiliary clock) if the HSE crystal
oscillator fails. Refer to Section 5.2.7: Clock security system (CSS) on page 135.
5.2.3
PLL
The devices feature three PLLs:
•
A main PLL (PLL) clocked by the HSE or HSI oscillator and featuring two different
output clocks:
–
The first output is used to generate the high speed system clock (up to 216 MHz)
–
The second output is used to generate 48MHz clock for the USB OTG FS,
SDMMC and RNG.
•
PLLI2S is used to generate an accurate clock to achieve high-quality audio
performance on the I2S, SAIs and SPDIFRX interfaces.
•
PLLSAI is used to generate clock for SAIs intefraces, LCD-TFT clock and the 48MHz
(PLLSAI48CLK) that can be seleced for the USB OTG FS, SDMMC and RNG.
Since the main-PLL configuration parameters cannot be changed once PLL is enabled, it is
recommended to configure PLL before enabling it (selection of the HSI or HSE oscillator as
PLL clock source, and configuration of division factors M, N, P, and Q).
The PLLI2S and PLLSAI use the same input clock as PLL (PLLM[5:0] and PLLSRC bits are
common to both PLLs). However, the PLLI2S and PLLSAI have dedicated enable/disable
and division factors (N and R) configuration bits. Once the PLLI2S and PLLSAI are enabled,
the configuration parameters cannot be changed.
The three PLLs are disabled by hardware when entering Stop and Standby modes, or when
an HSE failure occurs when HSE or PLL (clocked by HSE) are used as system clock. RCC
PLL configuration register (RCC_PLLCFGR),RCC clock configuration register
(RCC_CFGR), and RCC dedicated clocks configuration register (RCC_DKCFGR1) can be
used to configure PLL, PLLI2S, and PLLSAI.
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5.2.4
Reset and clock control (RCC)
LSE clock
The LSE clock is generated from a 32.768 kHz low-speed external crystal or ceramic
resonator. It has the advantage providing a low-power but highly accurate clock source to
the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The LSE oscillator is switched on and off using the LSEON bit in RCC backup domain
control register (RCC_BDCR).
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released
until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock
interrupt register (RCC_CIR).
External source (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. You select this mode by setting the LSEBYP and LSEON bits in the RCC backup
domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle)
with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be
left HI-Z. See Figure 13.
5.2.5
LSI clock
The LSI RC acts as an low-power clock source that can be kept running in Stop and
Standby mode for the independent watchdog (IWDG) and Auto-wakeup unit (AWU). The
clock frequency is around 32 kHz. For more details, refer to the electrical characteristics
section of the datasheets.
The LSI RC can be switched on and off using the LSION bit in the RCC clock control &
status register (RCC_CSR).
The LSIRDY flag in the RCC clock control & status register (RCC_CSR) indicates if the lowspeed internal oscillator is stable or not. At startup, the clock is not released until this bit is
set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
5.2.6
System clock (SYSCLK) selection
After a system reset, the HSI oscillator is selected as the system clock. When a clock source
is used directly or through PLL as the system clock, it is not possible to stop it.
A switch from one clock source to another occurs only if the target clock source is ready
(clock stable after startup delay or PLL locked). If a clock source that is not yet ready is
selected, the switch occurs when the clock source is ready. Status bits in the RCC clock
control register (RCC_CR) indicate which clock(s) is (are) ready and which clock is currently
used as the system clock.
5.2.7
Clock security system (CSS)
The clock security system can be activated by software. In this case, the clock detector is
enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock
failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an
interrupt is generated to inform the software about the failure (clock security system
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interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the
Cortex®-M7 NMI (non-maskable interrupt) exception vector.
Note:
When the CSS is enabled, if the HSE clock happens to fail, the CSS generates an interrupt,
which causes the automatic generation of an NMI. The NMI is executed indefinitely unless
the CSS interrupt pending bit is cleared. As a consequence, the application has to clear the
CSS interrupt in the NMI ISR by setting the CSSC bit in the Clock interrupt register
(RCC_CIR).
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that
it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is
detected, then the system clock switches to the HSI oscillator and the HSE oscillator is
disabled.
If the HSE oscillator clock was the clock source of PLL used as the system clock when the
failure occurred, PLL is also disabled. In this case, if the PLLI2S or PLLSAI was enabled, it
is also disabled when the HSE fails.
5.2.8
RTC/AWU clock
Once the RTCCLK clock source has been selected, the only possible way of modifying the
selection is to reset the power domain.
The RTCCLK clock source can be either the HSE 1 MHz (HSE divided by a programmable
prescaler), the LSE or the LSI clock. This is selected by programming the RTCSEL[1:0] bits
in the RCC backup domain control register (RCC_BDCR) and the RTCPRE[4:0] bits in RCC
clock configuration register (RCC_CFGR). This selection cannot be modified without
resetting the Backup domain.
If the LSE is selected as the RTC clock, the RTC will work normally if the backup or the
system supply disappears. If the LSI is selected as the AWU clock, the AWU state is not
guaranteed if the system supply disappears. If the HSE oscillator divided by a value
between 2 and 31 is used as the RTC clock, the RTC state is not guaranteed if the backup
or the system supply disappears.
The LSE clock is in the Backup domain, whereas the HSE and LSI clocks are not. As a
consequence:
•
•
If LSE is selected as the RTC clock:
–
The RTC continues to work even if the VDD supply is switched off, provided the
VBAT supply is maintained.
–
The RTC remains clocked and functional under system reset.
If LSI is selected as the Auto-wakeup unit (AWU) clock:
–
•
If the HSE clock is used as the RTC clock:
–
Note:
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The AWU state is not guaranteed if the VDD supply is powered off. Refer to
Section 5.2.5: LSI clock on page 135 for more details on LSI calibration.
The RTC state is not guaranteed if the VDD supply is powered off or if the internal
voltage regulator is powered off (removing power from the 1.2 V domain) and also
when entering in Stop mode
To read the RTC calendar register when the APB1 clock frequency is less than seven times
the RTC clock frequency (fAPB1 < 7xfRTCLCK), the software must read the calendar time and
date registers twice. The data are correct if the second read access to RTC_TR gives the
same result than the first one. Otherwise a third read access must be performed.
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5.2.9
Reset and clock control (RCC)
Watchdog clock
If the independent watchdog (IWDG) is started by either hardware option or software
access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator
temporization, the clock is provided to the IWDG.
5.2.10
Clock-out capability
Two microcontroller clock output (MCO) pins are available:
•
MCO1
You can output four different clock sources onto the MCO1 pin (PA8) using the
configurable prescaler (from 1 to 5):
–
HSI clock
–
LSE clock
–
HSE clock
–
PLL clock
The desired clock source is selected using the MCO1PRE[2:0] and MCO1[1:0] bits in
the RCC clock configuration register (RCC_CFGR).
•
MCO2
You can output four different clock sources onto the MCO2 pin (PC9) using the
configurable prescaler (from 1 to 5):
–
HSE clock
–
PLL clock
–
System clock (SYSCLK)
–
PLLI2S clock
The desired clock source is selected using the MCO2PRE[2:0] and MCO2 bits in the
RCC clock configuration register (RCC_CFGR).
For the different MCO pins, the corresponding GPIO port has to be programmed in alternate
function mode.
5.2.11
Internal/external clock measurement using TIM5/TIM11
It is possible to indirectly measure the frequencies of all on-board clock source generators
by means of the input capture of TIM5 channel4 and TIM11 channel1 as shown in Figure 14
and Figure 14.
Internal/external clock measurement using TIM5 channel4
TIM5 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through the TI4_RMP [1:0] bits
in the TIM5_OR register.
The primary purpose of having the LSE connected to the channel4 input capture is to be
able to precisely measure the HSI (this requires to have the HSI used as the system clock
source). The number of HSI clock counts between consecutive edges of the LSE signal
provides a measurement of the internal clock period. Taking advantage of the high precision
of LSE crystals (typically a few tens of ppm) we can determine the internal clock frequency
with the same resolution, and trim the source to compensate for manufacturing-process
and/or temperature- and voltage-related frequency deviations.
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The HSI oscillator has dedicated, user-accessible calibration bits for this purpose.
The basic concept consists in providing a relative measurement (e.g. HSI/LSE ratio): the
precision is therefore tightly linked to the ratio between the two clock sources. The greater
the ratio, the better the measurement.
It is also possible to measure the LSI frequency: this is useful for applications that do not
have a crystal. The ultra-low-power LSI oscillator has a large manufacturing process
deviation: by measuring it versus the HSI clock source, it is possible to determine its
frequency with the precision of the HSI. The measured value can be used to have more
accurate RTC time base timeouts (when LSI is used as the RTC clock source) and/or an
IWDG timeout with an acceptable accuracy.
Use the following procedure to measure the LSI frequency:
1.
Enable the TIM5 timer and configure channel4 in Input capture mode.
2.
This bit is set the TI4_RMP bits in the TIM5_OR register to 0x01 to connect the LSI
clock internally to TIM5 channel4 input capture for calibration purposes.
3.
Measure the LSI clock frequency using the TIM5 capture/compare 4 event or interrupt.
4.
Use the measured LSI frequency to update the prescaler of the RTC depending on the
desired time base and/or to compute the IWDG timeout.
Figure 14. Frequency measurement with TIM5 in Input capture mode
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24#?7AKE5P?)4
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4)
AI6
Internal/external clock measurement using TIM11 channel1
TIM11 has an input multiplexer which allows choosing whether the input capture is triggered
by the I/O or by an internal clock. This selection is performed through TI1_RMP [1:0] bits in
the TIM11_OR register. The HSE_RTC clock (HSE divided by a programmable prescaler) is
connected to channel 1 input capture to have a rough indication of the external crystal
frequency. This requires that the HSI is the system clock source. This can be useful for
instance to ensure compliance with the IEC 60730/IEC 61335 standards which require to be
able to determine harmonic or subharmonic frequencies (–50/+100% deviations).
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Figure 15. Frequency measurement with TIM11 in Input capture mode
7,0
7,B503>@
*3,2
7,
+6(B57&0+]
069
5.2.12
Peripheral clock enable register (RCC_AHBxENR,
RCC_APBxENRy)
Each peripheral clock can be enabled by the xxxxEN bit of the RCC_AHBxENR or
RCC_APBxENRy registers.
When the peripheral clock is not active, the peripheral registers read or write accesses are
not supported.The peripheral enable bit has a synchronization mechanism to create a glitch
free clock for the peripheral.
After the enable bit is set, there is a 2 peripheral clock cycles delay before the clock being
active.
Caution:
Just after enabling the clock for a peripheral, software must wait for a 2 peripheral clock
cycles delay before accessing the peripheral registers.
5.3
RCC registers
Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in
register descriptions.
5.3.1
RCC clock control register (RCC_CR)
Address offset: 0x00
Reset value: 0x0000 XX83 where X is undefined.
Access: no wait state, word, half-word and byte access
31
30
Res.
Res.
15
14
29
28
27
26
25
PLLSAI PLLSAI PLLI2S PLLI2S PLLRD
RDY
ON
RDY
ON
Y
24
23
22
21
20
19
18
17
16
PLLON
Res.
Res.
Res.
Res.
CSS
ON
HSE
BYP
HSE
RDY
HSE
ON
rw
rw
r
rw
3
2
1
0
Res.
HSI
RDY
HSION
r
rw
r
rw
r
rw
r
rw
13
12
11
10
9
8
7
6
HSICAL[7:0]
r
r
r
r
r
5
4
HSITRIM[4:0]
r
r
r
rw
rw
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Bits 31:28 Reserved, must be kept at reset value.
Bit 29 PLLSAIRDY: PLLSAI clock ready flag
Set by hardware to indicate that the PLLSAI is locked.
0: PLLSAI unlocked
1: PLLSAI locked
Bit 28 PLLSAION: PLLSAI enable
Set and cleared by software to enable PLLSAI.
Cleared by hardware when entering Stop or Standby mode.
0: PLLSAI OFF
1: PLLSAI ON
Bit 27 PLLI2SRDY: PLLI2S clock ready flag
Set by hardware to indicate that the PLLI2S is locked.
0: PLLI2S unlocked
1: PLLI2S locked
Bit 26 PLLI2SON: PLLI2S enable
Set and cleared by software to enable PLLI2S.
Cleared by hardware when entering Stop or Standby mode.
0: PLLI2S OFF
1: PLLI2S ON
Bit 25 PLLRDY: Main PLL (PLL) clock ready flag
Set by hardware to indicate that PLL is locked.
0: PLL unlocked
1: PLL locked
Bit 24 PLLON: Main PLL (PLL) enable
Set and cleared by software to enable PLL.
Cleared by hardware when entering Stop or Standby mode. This bit cannot be reset if PLL
clock is used as the system clock.
0: PLL OFF
1: PLL ON
Bits 23:20 Reserved, must be kept at reset value.
Bit 19 CSSON: Clock security system enable
Set and cleared by software to enable the clock security system. When CSSON is set, the
clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by
hardware if an oscillator failure is detected.
0: Clock security system OFF (Clock detector OFF)
1: Clock security system ON (Clock detector ON if HSE oscillator is stable, OFF if not)
Bit 18 HSEBYP: HSE clock bypass
Set and cleared by software to bypass the oscillator with an external clock. The external
clock must be enabled with the HSEON bit, to be used by the device.
The HSEBYP bit can be written only if the HSE oscillator is disabled.
0: HSE oscillator not bypassed
1: HSE oscillator bypassed with an external clock
Bit 17 HSERDY: HSE clock ready flag
Set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared,
HSERDY goes low after 6 HSE oscillator clock cycles.
0: HSE oscillator not ready
1: HSE oscillator ready
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Bit 16 HSEON: HSE clock enable
Set and cleared by software.
Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This
bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock.
0: HSE oscillator OFF
1: HSE oscillator ON
Bits 15:8 HSICAL[7:0]: Internal high-speed clock calibration
These bits are initialized automatically at startup.
Bits 7:3 HSITRIM[4:0]: Internal high-speed clock trimming
These bits provide an additional user-programmable trimming value that is added to the
HSICAL[7:0] bits. It can be programmed to adjust to variations in voltage and temperature
that influence the frequency of the internal HSI RC.
Bit 2 Reserved, must be kept at reset value.
Bit 1 HSIRDY: Internal high-speed clock ready flag
Set by hardware to indicate that the HSI oscillator is stable. After the HSION bit is cleared,
HSIRDY goes low after 6 HSI clock cycles.
0: HSI oscillator not ready
1: HSI oscillator ready
Bit 0 HSION: Internal high-speed clock enable
Set and cleared by software.
Set by hardware to force the HSI oscillator ON when leaving the Stop or Standby mode or in
case of a failure of the HSE oscillator used directly or indirectly as the system clock. This bit
cannot be cleared if the HSI is used directly or indirectly as the system clock.
0: HSI oscillator OFF
1: HSI oscillator ON
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5.3.2
RM0385
RCC PLL configuration register (RCC_PLLCFGR)
Address offset: 0x04
Reset value: 0x2400 3010
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLL clock outputs according to the formulas:
31
Res.
30
Res.
•
f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
•
f(PLL general clock output) = f(VCO clock) / PLLP
•
f(USB OTG FS, SDMMC, RNG clock output) = f(VCO clock) / PLLQ
29
Res.
28
27
Res.
14
13
12
25
24
PLLQ[3:0]
rw
15
26
11
Res.
rw
rw
rw
10
9
8
23
22
21
20
19
18
Res.
PLLSR
C
Res.
Res.
Res.
Res.
rw
7
6
5
4
PLLN[8:0]
rw
rw
rw
rw
rw
3
2
17
16
PLLP[1:0]
rw
rw
1
0
rw
rw
PLLM[5:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 PLLQ[3:0]: Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
generator clocks
Set and cleared by software to control the frequency of USB OTG FS clock, the random
number generator clock and the SDMMC clock. These bits should be written only if PLL is
disabled.
Caution: The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC and the
random number generator need a frequency lower than or equal to 48 MHz to work
correctly.
USB OTG FS clock frequency = VCO frequency / PLLQ with 2 ≤ PLLQ ≤ 15
0000: PLLQ = 0, wrong configuration
0001: PLLQ = 1, wrong configuration
0010: PLLQ = 2
0011: PLLQ = 3
0100: PLLQ = 4
...
1111: PLLQ = 15
Bit 23 Reserved, must be kept at reset value.
Bit 22 PLLSRC: Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
Set and cleared by software to select PLL and PLLI2S clock source. This bit can be written
only when PLL and PLLI2S are disabled.
0: HSI clock selected as PLL and PLLI2S clock entry
1: HSE oscillator clock selected as PLL and PLLI2S clock entry
Bits 21:18 Reserved, must be kept at reset value.
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Bits 17:16 PLLP[1:0]: Main PLL (PLL) division factor for main system clock
Set and cleared by software to control the frequency of the general PLL output clock. These
bits can be written only if PLL is disabled.
Caution: The software has to set these bits correctly not to exceed 216 MHz on this domain.
PLL output clock frequency = VCO frequency / PLLP with PLLP = 2, 4, 6, or 8
00: PLLP = 2
01: PLLP = 4
10: PLLP = 6
11: PLLP = 8
Bits 14:6 PLLN[8:0]: Main PLL (PLL) multiplication factor for VCO
Set and cleared by software to control the multiplication factor of the VCO. These bits can
be written only when PLL is disabled. Only half-word and word accesses are allowed to
write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz.
VCO output frequency = VCO input frequency × PLLN with 50 ≤ PLLN ≤ 432
000000000: PLLN = 0, wrong configuration
000000001: PLLN = 1, wrong configuration
...
000110010: PLLN = 50
...
001100011: PLLN = 99
001100100: PLLN = 100
...
110110000: PLLN = 432
110110001: PLLN = 433, wrong configuration
...
111111111: PLLN = 511, wrong configuration
Note: Between 50 and 99, multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 PLLM[5:0]: Division factor for the main PLLs (PLL, PLLI2S and PLLSAI) input clock
Set and cleared by software to divide the PLL and PLLI2S input clock before the VCO.
These bits can be written only when the PLL and PLLI2S are disabled.
Caution: The software has to set these bits correctly to ensure that the VCO input frequency
ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit
PLL jitter.
VCO input frequency = PLL input clock frequency / PLLM with 2 ≤ PLLM ≤ 63
000000: PLLM = 0, wrong configuration
000001: PLLM = 1, wrong configuration
000010: PLLM = 2
000011: PLLM = 3
000100: PLLM = 4
...
111110: PLLM = 62
111111: PLLM = 63
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Reset and clock control (RCC)
5.3.3
RM0385
RCC clock configuration register (RCC_CFGR)
Address offset: 0x08
Reset value: 0x0000 0000
Access: 0 ≤ wait state ≤ 2, word, half-word and byte access
1 or 2 wait states inserted only if the access occurs during a clock source switch.
31
30
29
MCO2
14
26
rw
25
24
23
22
I2SSC
R
MCO1 PRE[2:0]
rw
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
Res.
Res.
rw
rw
rw
rw
PPRE1[2:0]
rw
rw
21
20
19
MCO1
13
PPRE2[2:0]
rw
27
MCO2 PRE[2:0]
rw
15
28
18
17
16
RTCPRE[4:0]
5
rw
rw
rw
rw
rw
4
3
2
1
0
SWS1
SWS0
SW1
SW0
r
r
rw
rw
HPRE[3:0]
rw
rw
Bits 31:30 MCO2[1:0]: Microcontroller clock output 2
Set and cleared by software. Clock source selection may generate glitches on MCO2. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and the PLLs.
00: System clock (SYSCLK) selected
01: PLLI2S clock selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 27:29 MCO2PRE: MCO2 prescaler
Set and cleared by software to configure the prescaler of the MCO2. Modification of this
prescaler may generate glitches on MCO2. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLLs.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bits 24:26 MCO1PRE: MCO1 prescaler
Set and cleared by software to configure the prescaler of the MCO1. Modification of this
prescaler may generate glitches on MCO1. It is highly recommended to change this
prescaler only after reset before enabling the external oscillators and the PLL.
0xx: no division
100: division by 2
101: division by 3
110: division by 4
111: division by 5
Bit 23 I2SSRC: I2S clock selection
Set and cleared by software. This bit allows to select the I2S clock source between the
PLLI2S clock and the external clock. It is highly recommended to change this bit only after
reset and before enabling the I2S module.
0: PLLI2S clock used as I2S clock source
1: External clock mapped on the I2S_CKIN pin used as I2S clock source
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RM0385
Reset and clock control (RCC)
Bits 22:21 MCO1: Microcontroller clock output 1
Set and cleared by software. Clock source selection may generate glitches on MCO1. It is
highly recommended to configure these bits only after reset before enabling the external
oscillators and PLL.
00: HSI clock selected
01: LSE oscillator selected
10: HSE oscillator clock selected
11: PLL clock selected
Bits 20:16 RTCPRE: HSE division factor for RTC clock
Set and cleared by software to divide the HSE clock input clock to generate a 1 MHz clock
for RTC.
Caution: The software has to set these bits correctly to ensure that the clock supplied to the
RTC is 1 MHz. These bits must be configured if needed before selecting the RTC
clock source.
00000: no clock
00001: no clock
00010: HSE/2
00011: HSE/3
00100: HSE/4
...
11110: HSE/30
11111: HSE/31
Bits 15:13 PPRE2: APB high-speed prescaler (APB2)
Set and cleared by software to control APB high-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 108 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE2 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Bits 12:10 PPRE1: APB Low-speed prescaler (APB1)
Set and cleared by software to control APB low-speed clock division factor.
Caution: The software has to set these bits correctly not to exceed 54 MHz on this domain.
The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
PPRE1 write.
0xx: AHB clock not divided
100: AHB clock divided by 2
101: AHB clock divided by 4
110: AHB clock divided by 8
111: AHB clock divided by 16
Bits 9:8 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
RM0385
Bits 7:4 HPRE: AHB prescaler
Set and cleared by software to control AHB clock division factor.
Caution: The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after
HPRE write.
Caution: The AHB clock frequency must be at least 25 MHz when the Ethernet is used.
0xxx: system clock not divided
1000: system clock divided by 2
1001: system clock divided by 4
1010: system clock divided by 8
1011: system clock divided by 16
1100: system clock divided by 64
1101: system clock divided by 128
1110: system clock divided by 256
1111: system clock divided by 512
Bits 3:2 SWS: System clock switch status
Set and cleared by hardware to indicate which clock source is used as the system clock.
00: HSI oscillator used as the system clock
01: HSE oscillator used as the system clock
10: PLL used as the system clock
11: not applicable
Bits 1:0 SW: System clock switch
Set and cleared by software to select the system clock source.
Set by hardware to force the HSI selection when leaving the Stop or Standby mode or in
case of failure of the HSE oscillator used directly or indirectly as the system clock.
00: HSI oscillator selected as system clock
01: HSE oscillator selected as system clock
10: PLL selected as system clock
11: not allowed
5.3.4
RCC clock interrupt register (RCC_CIR)
Address offset: 0x0C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
Res.
30
Res.
29
Res.
28
Res.
27
Res.
26
Res.
25
Res.
24
Res.
23
w
15
14
13
Res.
PLLSAI
RDYIE
PLLI2S
RDYIE
rw
rw
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12
11
10
PLL
HSE
HSI
RDYIE RDYIE RDYIE
rw
rw
rw
22
21
PLLSAI PLLI2S
CSSC
RDYC RDYC
9
8
LSE
RDYIE
LSI
RDYIE
7
CSSF
rw
rw
r
w
w
6
5
PLLSAI PLLI2S
RDYF
RDYF
DocID026670 Rev 6
r
r
20
19
18
17
16
PLL
RDYC
HSE
RDYC
HSI
RDYC
LSE
RDYC
LSI
RDYC
w
w
w
w
w
4
3
2
1
0
PLL
RDYF
HSE
RDYF
HSI
RDYF
LSE
RDYF
LSI
RDYF
r
r
r
r
r
RM0385
Reset and clock control (RCC)
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 CSSC: Clock security system interrupt clear
This bit is set by software to clear the CSSF flag.
0: No effect
1: Clear CSSF flag
Bit 22 PLLSAIRDYC: PLLSAI Ready Interrupt Clear
This bit is set by software to clear PLLSAIRDYF flag. It is reset by hardware when the
PLLSAIRDYF is cleared.
0: PLLSAIRDYF not cleared
1: PLLSAIRDYF cleared
Bit 21 PLLI2SRDYC: PLLI2S ready interrupt clear
This bit is set by software to clear the PLLI2SRDYF flag.
0: No effect
1: PLLI2SRDYF cleared
Bit 20 PLLRDYC: Main PLL(PLL) ready interrupt clear
This bit is set by software to clear the PLLRDYF flag.
0: No effect
1: PLLRDYF cleared
Bit 19 HSERDYC: HSE ready interrupt clear
This bit is set by software to clear the HSERDYF flag.
0: No effect
1: HSERDYF cleared
Bit 18 HSIRDYC: HSI ready interrupt clear
This bit is set software to clear the HSIRDYF flag.
0: No effect
1: HSIRDYF cleared
Bit 17 LSERDYC: LSE ready interrupt clear
This bit is set by software to clear the LSERDYF flag.
0: No effect
1: LSERDYF cleared
Bit 16 LSIRDYC: LSI ready interrupt clear
This bit is set by software to clear the LSIRDYF flag.
0: No effect
1: LSIRDYF cleared
Bit 15 Reserved, must be kept at reset value.
Bit 14 PLLSAIRDYIE: PLLSAI Ready Interrupt Enable
This bit is set and reset by software to enable/disable interrupt caused by PLLSAI lock.
0: PLLSAI lock interrupt disabled
1: PLLSAI lock interrupt enabled
Bit 13 PLLI2SRDYIE: PLLI2S ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by PLLI2S lock.
0: PLLI2S lock interrupt disabled
1: PLLI2S lock interrupt enabled
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RM0385
Bit 12 PLLRDYIE: Main PLL (PLL) ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by PLL lock.
0: PLL lock interrupt disabled
1: PLL lock interrupt enabled
Bit 11 HSERDYIE: HSE ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSE
oscillator stabilization.
0: HSE ready interrupt disabled
1: HSE ready interrupt enabled
Bit 10 HSIRDYIE: HSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the HSI
oscillator stabilization.
0: HSI ready interrupt disabled
1: HSI ready interrupt enabled
Bit 9 LSERDYIE: LSE ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by the LSE
oscillator stabilization.
0: LSE ready interrupt disabled
1: LSE ready interrupt enabled
Bit 8 LSIRDYIE: LSI ready interrupt enable
This bit is set and cleared by software to enable/disable interrupt caused by LSI oscillator
stabilization.
0: LSI ready interrupt disabled
1: LSI ready interrupt enabled
Bit 7 CSSF: Clock security system interrupt flag
This bit is set by hardware when a failure is detected in the HSE oscillator.
It is cleared by software by setting the CSSC bit.
0: No clock security interrupt caused by HSE clock failure
1: Clock security interrupt caused by HSE clock failure
Bit 6 PLLSAIRDYF: PLLSAI Ready Interrupt flag
This bit is set by hardware when the PLLSAI is locked and PLLSAIRDYDIE is set.
It is cleared by software by setting the PLLSAIRDYC bit.
0: No clock ready interrupt caused by PLLSAI lock
1: Clock ready interrupt caused by PLLSAI lock
Bit 5 PLLI2SRDYF: PLLI2S ready interrupt flag
This bit is set by hardware when the PLLI2S is locked and PLLI2SRDYDIE is set.
It is cleared by software by setting the PLLRI2SDYC bit.
0: No clock ready interrupt caused by PLLI2S lock
1: Clock ready interrupt caused by PLLI2S lock
Bit 4 PLLRDYF: Main PLL (PLL) ready interrupt flag
This bit is set by hardware when PLL is locked and PLLRDYDIE is set.
It is cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
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RM0385
Reset and clock control (RCC)
Bit 3 HSERDYF: HSE ready interrupt flag
This bit is set by hardware when External High Speed clock becomes stable and
HSERDYDIE is set.
It is cleared by software by setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Bit 2 HSIRDYF: HSI ready interrupt flag
This bit is set by hardware when the Internal High Speed clock becomes stable and
HSIRDYDIE is set.
It is cleared by software by setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI oscillator
1: Clock ready interrupt caused by the HSI oscillator
Bit 1 LSERDYF: LSE ready interrupt flag
This bit is set by hardware when the External low-speed clock becomes stable and
LSERDYDIE is set.
It is cleared by software by setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Bit 0 LSIRDYF: LSI ready interrupt flag
This bit is set by hardware when the internal low-speed clock becomes stable and
LSIRDYDIE is set.
It is cleared by software by setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
5.3.5
RCC AHB1 peripheral reset register (RCC_AHB1RSTR)
Address offset: 0x10
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
Res.
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
OTGH
S
RST
Res.
Res.
Res.
ETHMAC
RST
Res.
DMA2D
RST
DMA2
RST
DMA1
RST
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
7
6
5
4
3
2
1
rw
15
Res.
14
Res.
rw
13
12
Res.
CRCR
ST
rw
11
10
9
8
Res.
GPIOK
RST
GPIOJ
RST
GPIOI
RST
rw
rw
rw
0
GPIOH GPIOGG GPIOF GPIOE GPIOD GPIOC GPIOB
RST
RST
RST
RST
RST
RST
RST
rw
rw
rw
rw
rw
rw
rw
GPIOA
RST
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 OTGHSRST: USB OTG HS module reset
This bit is set and cleared by software.
0: does not reset the USB OTG HS module
1: resets the USB OTG HS module
Bits 28:26 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
RM0385
Bit 25 ETHMACRST: Ethernet MAC reset
This bit is set and cleared by software.
0: does not reset Ethernet MAC
1: resets Ethernet MAC
Bit 24 Reserved, must be kept at reset value.
Bit 23 DMA2DRST: DMA2D reset
This bit is set and reset by software.
0: does not reset DMA2D
1: resets DMA2D
Bit 22 DMA2RST: DMA2 reset
This bit is set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bit 21 DMA1RST: DMA2 reset
This bit is set and cleared by software.
0: does not reset DMA2
1: resets DMA2
Bits 20:13 Reserved, must be kept at reset value.
Bit 12 CRCRST: CRC reset
This bit is set and cleared by software.
0: does not reset CRC
1: resets CRC
Bit 11 Reserved, must be kept at reset value.
Bit 10 GPIOKRST: IO port K reset
This bit is set and cleared by software.
0: does not reset IO port K
1: resets IO port K
Bit 9 GPIOJRST: IO port J reset
This bit is set and cleared by software.
0: does not reset IO port J
1: resets IO port J
Bit 8 GPIOIRST: IO port I reset
This bit is set and cleared by software.
0: does not reset IO port I
1: resets IO port I
Bit 7 GPIOHRST: IO port H reset
This bit is set and cleared by software.
0: does not reset IO port H
1: resets IO port H
Bit 6 GPIOGRST: IO port G reset
This bit is set and cleared by software.
0: does not reset IO port G
1: resets IO port G
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RM0385
Reset and clock control (RCC)
Bit 5 GPIOFRST: IO port F reset
This bit is set and cleared by software.
0: does not reset IO port F
1: resets IO port F
Bit 4 GPIOERST: IO port E reset
This bit is set and cleared by software.
0: does not reset IO port E
1: resets IO port E
Bit 3 GPIODRST: IO port D reset
This bit is set and cleared by software.
0: does not reset IO port D
1: resets IO port D
Bit 2 GPIOCRST: IO port C reset
This bit is set and cleared by software.
0: does not reset IO port C
1: resets IO port C
Bit 1 GPIOBRST: IO port B reset
This bit is set and cleared by software.
0: does not reset IO port B
1:resets IO port B
Bit 0 GPIOARST: IO port A reset
This bit is set and cleared by software.
0: does not reset IO port A
1: resets IO port A
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Reset and clock control (RCC)
5.3.6
RM0385
RCC AHB2 peripheral reset register (RCC_AHB2RSTR)
Address offset: 0x14
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
OTGFS
RST
RNG
RST
HASH
RST
CRYP
RST
Res.
DCMI
RST
rw
rw
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSRST: USB OTG FS module reset
Set and cleared by software.
0: does not reset the USB OTG FS module
1: resets the USB OTG FS module
Bit 6 RNGRST: Random number generator module reset
Set and cleared by software.
0: does not reset the random number generator module
1: resets the random number generator module
Bit 5 HASHRST: Hash module reset
Set and cleared by software.
0: does not reset the HASH module
1: resets the HASH module
Bit 4 CRYPRST: Cryptographic module reset
Set and cleared by software.
0: does not reset the cryptographic module
1: resets the cryptographic module
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMIRST: Camera interface reset
Set and cleared by software.
0: does not reset the Camera interface
1: resets the Camera interface
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Res.
Res.
rw
RM0385
Reset and clock control (RCC)
5.3.7
RCC AHB3 peripheral reset register (RCC_AHB3RSTR)
Address offset: 0x18
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QSPIRST FMCRST
rw
rw
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIRST: Quad SPI memory controller reset
Set and cleared by software.
0: does not reset the QUADSPI memory controller
1: resets the QUADSPI memory controller
Bit 0 FMCRST: Flexible memory controller module reset
Set and cleared by software.
0: does not reset the FMC module
1: resets the FMC module
5.3.8
RCC APB1 peripheral reset register (RCC_APB1RSTR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
UART8R UART7R
PWR
CAN2
DACRST
CECRST
ST
ST
RST
RST
rw
rw
rw
rw
15
14
13
12
11
10
SPI3
RST
SPI2
RST
Res.
Res.
WWDG
RST
Res.
rw
rw
rw
25
24
CAN1
I2C4RST
RST
23
22
21
I2C3
RST
I2C2
RST
I2C1
RST
20
19
18
17
16
UART5 UART4 UART3 UART2 SPDIFR
RST
RST
RST
RST
XRST
rw
rw
rw
rw
rw
rw
rw
rw
rw
9
8
7
6
5
4
3
2
1
0
TIM13
RST
TIM12
RST
TIM7
RST
TIM6
RST
TIM5
RST
TIM4
RST
TIM3
RST
TIM2
RST
rw
rw
rw
rw
rw
rw
rw
rw
LPTIM1 TIM14
RST
RST
rw
rw
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Reset and clock control (RCC)
RM0385
Bit 31 UART8RST: UART8 reset
Set and cleared by software.
0: does not reset UART8
1: resets UART8
Bit 30 UART7RST: UART7 reset
Set and cleared by software.
0: does not reset UART7
1: resets UART7
Bit 29 DACRST: DAC reset
Set and cleared by software.
0: does not reset the DAC interface
1: resets the DAC interface
Bit 28 PWRRST: Power interface reset
Set and cleared by software.
0: does not reset the power interface
1: resets the power interface
Bit 27 CECRST: HDMI-CEC reset
Set and cleared by software.
0: does not reset HDMI-CEC
1: resets HDMI-CEC
Bit 26 CAN2RST: CAN2 reset
Set and cleared by software.
0: does not reset CAN2
1: resets CAN2
Bit 25 CAN1RST: CAN1 reset
Set and cleared by software.
0: does not reset CAN1
1: resets CAN1
Bit 24 I2C4RST: I2C4 reset
Set and cleared by software.
0: does not reset I2C4
1: resets I2C4
Bit 23 I2C3RST: I2C3 reset
Set and cleared by software.
0: does not reset I2C3
1: resets I2C3
Bit 22 I2C2RST: I2C2 reset
Set and cleared by software.
0: does not reset I2C2
1: resets I2C2
Bit 21 I2C1RST: I2C1 reset
Set and cleared by software.
0: does not reset I2C1
1: resets I2C1
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RM0385
Reset and clock control (RCC)
Bit 20 UART5RST: UART5 reset
Set and cleared by software.
0: does not reset UART5
1: resets UART5
Bit 19 UART4RST: USART4 reset
Set and cleared by software.
0: does not reset UART4
1: resets UART4
Bit 18 USART3RST: USART3 reset
Set and cleared by software.
0: does not reset USART3
1: resets USART3
Bit 17 USART2RST: USART2 reset
Set and cleared by software.
0: does not reset USART2
1: resets USART2
Bit 16 SPDIFRXRST: SPDIFRX reset
Set and cleared by software.
0: does not reset SPDIFRX
1: resets SPDIFRX
Bit 15 SPI3RST: SPI3 reset
Set and cleared by software.
0: does not reset SPI3
1: resets SPI3
Bit 14 SPI2RST: SPI2 reset
Set and cleared by software.
0: does not reset SPI2
1: resets SPI2
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGRST: Window watchdog reset
Set and cleared by software.
0: does not reset the window watchdog
1: resets the window watchdog
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1RST: Low-power timer 1 reset
Set and cleared by software.
0: does not reset LPTMI1
1: resets LPTMI1
Bit 8 TIM14RST: TIM14 reset
Set and cleared by software.
0: does not reset TIM14
1: resets TIM14
Bit 7 TIM13RST: TIM13 reset
Set and cleared by software.
0: does not reset TIM13
1: resets TIM13
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Reset and clock control (RCC)
RM0385
Bit 6 TIM12RST: TIM12 reset
Set and cleared by software.
0: does not reset TIM12
1: resets TIM12
Bit 5 TIM7RST: TIM7 reset
Set and cleared by software.
0: does not reset TIM7
1: resets TIM7
Bit 4 TIM6RST: TIM6 reset
Set and cleared by software.
0: does not reset TIM6
1: resets TIM6
Bit 3 TIM5RST: TIM5 reset
Set and cleared by software.
0: does not reset TIM5
1: resets TIM5
Bit 2 TIM4RST: TIM4 reset
Set and cleared by software.
0: does not reset TIM4
1: resets TIM4
Bit 1 TIM3RST: TIM3 reset
Set and cleared by software.
0: does not reset TIM3
1: resets TIM3
Bit 0 TIM2RST: TIM2 reset
Set and cleared by software.
0: does not reset TIM2
1: resets TIM2
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RM0385
Reset and clock control (RCC)
5.3.9
RCC APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x24
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
LTDC
RST
15
14
13
12
11
10
Res.
SYSCFG
RST
SPI4
RST
SPI1
RST
SDMMC1
RST
rw
rw
rw
rw
25
24
23
22
21
20
Res.
Res.
SAI2
RST
SAI1
RST
SPI6
RST
SPI5
RST
rw
rw
rw
rw
9
8
7
6
5
4
Res.
ADC
RST
rw
Res.
Res.
Res.
rw
USART6 USART1
RST
RST
rw
rw
19
18
17
16
Res.
TIM11
RST
TIM10
RST
TIM9
RST
rw
rw
rw
2
1
0
Res.
TIM8
RST
TIM1
RST
rw
rw
3
Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCRST: LTDC reset
This bit is set and reset by software.
0: does not reset LCD-TFT
1: resets LCD-TFT
Bits 27:24 Reserved, must be kept at reset value.
Bit 23 SAI2RST: SAI2 reset
This bit is set and cleared by software.
0: does not reset SAI2
1: resets SAI2
Bit 22 SAI1RST: SAI1 reset
This bit is set and reset by software.
0: does not reset SAI1
1: resets SAI1
Bit 21 SPI6RST: SPI6 reset
This bit is set and cleared by software.
0: does not reset SPI6
1: resets SPI6
Bit 20 SPI5RST: SPI5 reset
This bit is set and cleared by software.
0: does not reset SPI5
1: resets SPI5
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11RST: TIM11 reset
This bit is set and cleared by software.
0: does not reset TIM11
1: resets TIM14
Bit 17 TIM10RST: TIM10 reset
This bit is set and cleared by software.
0: does not reset TIM10
1: resets TIM10
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Reset and clock control (RCC)
RM0385
Bit 16 TIM9RST: TIM9 reset
This bit is set and cleared by software.
0: does not reset TIM9
1: resets TIM9
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGRST: System configuration controller reset
This bit is set and cleared by software.
0: does not reset the System configuration controller
1: resets the System configuration controller
Bit 13 SPI4RST: SPI4 reset
This bit is set and cleared by software.
0: does not reset SPI4
1: resets SPI4
Bit 12 SPI1RST: SPI1 reset
This bit is set and cleared by software.
0: does not reset SPI1
1: resets SPI1
Bit 11 SDMMC1RST: SDMMC1 reset
This bit is set and cleared by software.
0: does not reset the SDMMC1 module
1: resets the SDMMC1 module
Bits 10:9 Reserved, must be kept at reset value.
Bit 8 ADCRST: ADC interface reset (common to all ADCs)
This bit is set and cleared by software.
0: does not reset the ADC interface
1: resets the ADC interface
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6RST: USART6 reset
This bit is set and cleared by software.
0: does not reset USART6
1: resets USART6
Bit 4
USART1RST: USART1 reset
This bit is set and cleared by software.
0: does not reset USART1
1: resets USART1
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8RST: TIM8 reset
This bit is set and cleared by software.
0: does not reset TIM8
1: resets TIM8
Bit 0 TIM1RST: TIM1 reset
This bit is set and cleared by software.
0: does not reset TIM1
1: resets TIM1
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RM0385
5.3.10
Reset and clock control (RCC)
RCC AHB1 peripheral clock register (RCC_AHB1ENR)
Address offset: 0x30
Reset value: 0x0010 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
ETHM ETHM
OTGHS OTGHS
Res.
ACPTP ACRX
ULPIEN
EN
EN
EN
15
Res.
26
25
24
23
22
21
20
19
18
17
16
ETHM
ACTX
EN
ETHMA
CEN
Res.
DMA2D
EN
DMA2
EN
DMA1
EN
DTCMRA
MEN
Res.
BKPSR
AMEN
Res.
Res.
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
5
4
Res.
CRC
EN
Res.
GPIOK
EN
GPIOJ
EN
GPIOI
EN
GPIOH
EN
GPIOG
EN
GPIOF
EN
GPIOE
EN
rw
rw
rw
rw
rw
rw
rw
Res.
rw
rw
3
2
GPIOD GPIOC GPIO GPIO
EN
EN
BEN AEN
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPIEN: USB OTG HSULPI clock enable
This bit is set and cleared by software.
0: USB OTG HS ULPI clock disabled
1: USB OTG HS ULPI clock enabled
Bit 29 OTGHSEN: USB OTG HS clock enable
This bit is set and cleared by software.
0: USB OTG HS clock disabled
1: USB OTG HS clock enabled
Bit 28 ETHMACPTPEN: Ethernet PTP clock enable
This bit is set and cleared by software.
0: Ethernet PTP clock disabled
1: Ethernet PTP clock enabled
Bit 27 ETHMACRXEN: Ethernet Reception clock enable
This bit is set and cleared by software.
0: Ethernet Reception clock disabled
1: Ethernet Reception clock enabled
Bit 26 ETHMACTXEN: Ethernet Transmission clock enable
This bit is set and cleared by software.
0: Ethernet Transmission clock disabled
1: Ethernet Transmission clock enabled
Bit 25 ETHMACEN: Ethernet MAC clock enable
This bit is set and cleared by software.
0: Ethernet MAC clock disabled
1: Ethernet MAC clock enabled
Bit 24 Reserved, must be kept at reset value.
Bit 23 DMA2DEN: DMA2D clock enable
This bit is set and cleared by software.
0: DMA2D clock disabled
1: DMA2D clock enabled
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Reset and clock control (RCC)
RM0385
Bit 22 DMA2EN: DMA2 clock enable
This bit is set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 21 DMA1EN: DMA1 clock enable
This bit is set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
Bit 20 DTCMRAMEN: DTCM data RAM clock enable
This bit is set and cleared by software.
0: DTCM RAM clock disabled
1: DTCM RAM clock enabled
Bit 19 Reserved, must be kept at reset value.
Bit 18 BKPSRAMEN: Backup SRAM interface clock enable
This bit is set and cleared by software.
0: Backup SRAM interface clock disabled
1: Backup SRAM interface clock enabled
Bits 17:13 Reserved, must be kept at reset value.
Bit 12 CRCEN: CRC clock enable
This bit is set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 11 Reserved, must be kept at reset value.
Bit 10 GPIOKEN: IO port K clock enable
This bit is set and cleared by software.
0: IO port K clock disabled
1: IO port K clock enabled
Bit 9 GPIOJEN: IO port J clock enable
This bit is set and cleared by software.
0: IO port J clock disabled
1: IO port J clock enabled
Bit 8 GPIOIEN: IO port I clock enable
This bit is set and cleared by software.
0: IO port I clock disabled
1: IO port I clock enabled
Bit 7 GPIOHEN: IO port H clock enable
This bit is set and cleared by software.
0: IO port H clock disabled
1: IO port H clock enabled
Bit 6 GPIOGEN: IO port G clock enable
This bit is set and cleared by software.
0: IO port G clock disabled
1: IO port G clock enabled
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RM0385
Reset and clock control (RCC)
Bit 5 GPIOFEN: IO port F clock enable
This bit is set and cleared by software.
0: IO port F clock disabled
1: IO port F clock enabled
Bit 4 GPIOEEN: IO port E clock enable
This bit is set and cleared by software.
0: IO port E clock disabled
1: IO port E clock enabled
Bit 3 GPIODEN: IO port D clock enable
This bit is set and cleared by software.
0: IO port D clock disabled
1: IO port D clock enabled
Bit 2 GPIOCEN: IO port C clock enable
This bit is set and cleared by software.
0: IO port C clock disabled
1: IO port C clock enabled
Bit 1 GPIOBEN: IO port B clock enable
This bit is set and cleared by software.
0: IO port B clock disabled
1: IO port B clock enabled
Bit 0 GPIOAEN: IO port A clock enable
This bit is set and cleared by software.
0: IO port A clock disabled
1: IO port A clock enabled
5.3.11
RCC AHB2 peripheral clock enable register (RCC_AHB2ENR)
Address offset: 0x34
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
OTGFS
EN
RNG
EN
HASH
EN
CRYP
EN
Res.
DCMI
EN
rw
rw
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSEN: USB OTG FS clock enable
This bit is set and cleared by software.
0: USB OTG FS clock disabled
1: USB OTG FS clock enabled
Bit 6 RNGEN: Random number generator clock enable
This bit is set and cleared by software.
0: Random number generator clock disabled
1: Random number generator clock enabled
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Reset and clock control (RCC)
RM0385
Bit 5 HASHEN: Hash modules clock enable
This bit is set and cleared by software.
0: Hash modules clock disabled
1: Hash modules clock enabled
Bit 4 CRYPEN: Cryptographic modules clock enable
This bit is set and cleared by software.
0: cryptographic module clock disabled
1: cryptographic module clock enabled
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMIEN: Camera interface enable
This bit is set and cleared by software.
0: Camera interface clock disabled
1: Camera interface clock enabled
5.3.12
RCC AHB3 peripheral clock enable register (RCC_AHB3ENR)
Address offset: 0x38
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QSPIEN
FMCEN
rw
rw
17
16
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 QSPIEN: Quad SPI memory controller clock enable
This bit is set and cleared by software.
0: QUASPI controller clock disabled
1: QUASPI controller clock enabled
Bit 0 FMCEN: Flexible memory controller clock enable
This bit is set and cleared by software.
0: FMC clock disabled
1: FMC clock enabled
5.3.13
RCC APB1 peripheral clock enable register (RCC_APB1ENR)
Address offset: 0x40
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
UART8 UART7
EN
EN
rw
162/1671
rw
29
28
27
26
25
24
DAC
EN
PWR
EN
CEC
EN
CAN2
EN
CAN1
EN
rw
rw
rw
rw
rw
I2C4
EN
23
22
21
I2C3
EN
I2C2
EN
I2C1
EN
rw
rw
rw
DocID026670 Rev 6
20
19
18
USART USART
UART5 UART4
SPDIFRX
3
2
EN
EN
EN
EN
EN
rw
rw
rw
rw
rw
RM0385
Reset and clock control (RCC)
15
14
13
12
11
10
SPI3
EN
SPI2
EN
Res.
Res.
WWDG
EN
Res.
rw
rw
rw
9
8
LPTIM1 TIM14
EN
EN
rw
rw
7
6
5
4
3
2
1
0
TIM13
EN
TIM12
EN
TIM7
EN
TIM6
EN
TIM5
EN
TIM4
EN
TIM3
EN
TIM2
EN
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 UART8EN: UART8 clock enable
This bit is set and cleared by software.
0: UART8 clock disabled
1: UART8 clock enabled
Bit 30 UART7EN: UART7 clock enable
This bit is set and cleared by software.
0: UART7 clock disabled
1: UART7 clock enabled
Bit 29 DACEN: DAC interface clock enable
This bit is set and cleared by software.
0: DAC interface clock disabled
1: DAC interface clock enable
Bit 28 PWREN: Power interface clock enable
This bit is set and cleared by software.
0: Power interface clock disabled
1: Power interface clock enable
Bit 27 CECEN: HDMI-CEC clock enable
This bit is set and cleared by software.
0: HDMI-CEC clock disabled
1: HDMI-CEC clock enabled
Bit 26 CAN2EN: CAN 2 clock enable
This bit is set and cleared by software.
0: CAN 2 clock disabled
1: CAN 2 clock enabled
Bit 25 CAN1EN: CAN 1 clock enable
This bit is set and cleared by software.
0: CAN 1 clock disabled
1: CAN 1 clock enabled
Bit 24 I2C4: I2C4 clock enable
This bit is set and cleared by software.
0: I2C4 clock disabled
1: I2C4 clock enabled
Bit 23 I2C3EN: I2C3 clock enable
This bit is set and cleared by software.
0: I2C3 clock disabled
1: I2C3 clock enabled
Bit 22 I2C2EN: I2C2 clock enable
This bit is set and cleared by software.
0: I2C2 clock disabled
1: I2C2 clock enabled
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Reset and clock control (RCC)
RM0385
Bit 21 I2C1EN: I2C1 clock enable
This bit is set and cleared by software.
0: I2C1 clock disabled
1: I2C1 clock enabled
Bit 20 UART5EN: UART5 clock enable
This bit is set and cleared by software.
0: UART5 clock disabled
1: UART5 clock enabled
Bit 19 UART4EN: UART4 clock enable
This bit is set and cleared by software.
0: UART4 clock disabled
1: UART4 clock enabled
Bit 18 USART3EN: USART3 clock enable
This bit is set and cleared by software.
0: USART3 clock disabled
1: USART3 clock enabled
Bit 17 USART2EN: USART2 clock enable
This bit is set and cleared by software.
0: USART2 clock disabled
1: USART2 clock enabled
Bit 16 SPDIFRXEN: SPDIFRX clock enable
This bit is set and cleared by software.
0: SPDIFRX clock disabled
1: SPDIFRX clock enable
Bit 15 SPI3EN: SPI3 clock enable
This bit is set and cleared by software.
0: SPI3 clock disabled
1: SPI3 clock enabled
Bit 14 SPI2EN: SPI2 clock enable
This bit is set and cleared by software.
0: SPI2 clock disabled
1: SPI2 clock enabled
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGEN: Window watchdog clock enable
This bit is set and cleared by software.
0: Window watchdog clock disabled
1: Window watchdog clock enabled
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTMI1EN: Low-power timer 1 clock enable
This bit is set and cleared by software.
0: LPTIM1 clock disabled
1: LPTIM1 clock enabled
Bit 8 TIM14EN: TIM14 clock enable
This bit is set and cleared by software.
0: TIM14 clock disabled
1: TIM14 clock enabled
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RM0385
Reset and clock control (RCC)
Bit 7 TIM13EN: TIM13 clock enable
This bit is set and cleared by software.
0: TIM13 clock disabled
1: TIM13 clock enabled
Bit 6 TIM12EN: TIM12 clock enable
This bit is set and cleared by software.
0: TIM12 clock disabled
1: TIM12 clock enabled
Bit 5 TIM7EN: TIM7 clock enable
This bit is set and cleared by software.
0: TIM7 clock disabled
1: TIM7 clock enabled
Bit 4 TIM6EN: TIM6 clock enable
This bit is set and cleared by software.
0: TIM6 clock disabled
1: TIM6 clock enabled
Bit 3 TIM5EN: TIM5 clock enable
This bit is set and cleared by software.
0: TIM5 clock disabled
1: TIM5 clock enabled
Bit 2 TIM4EN: TIM4 clock enable
This bit is set and cleared by software.
0: TIM4 clock disabled
1: TIM4 clock enabled
Bit 1 TIM3EN: TIM3 clock enable
This bit is set and cleared by software.
0: TIM3 clock disabled
1: TIM3 clock enabled
Bit 0 TIM2EN: TIM2 clock enable
This bit is set and cleared by software.
0: TIM2 clock disabled
1: TIM2 clock enabled
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Reset and clock control (RCC)
5.3.14
RM0385
RCC APB2 peripheral clock enable register (RCC_APB2ENR)
Address offset: 0x44
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
LTDC
EN
15
14
13
12
11
25
24
Res.
Res.
10
9
8
ADC3
EN
ADC2
EN
ADC1
EN
rw
rw
rw
rw
Res.
SYSCFG SPI4
EN
EN
rw
rw
SPI1 SDMMC1
EN
EN
rw
rw
23
22
20
SAI2EN SAI1EN SPI6EN SPI5EN
rw
rw
rw
rw
7
6
5
4
Res.
Res.
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCEN: LTDC clock enable
This bit is set and cleared by software.
0: LTDC clock disabled
1: LTDC clock enabled
Bits 27: 24 Reserved, must be kept at reset value.
Bit 23 SAI2EN: SAI2 clock enable
This bit is set and cleared by software.
0: SAI2 clock disabled
1: SAI2 clock enabled
Bit 22 SAI1EN: SAI1 clock enable
This bit is set and cleared by software.
0: SAI1 clock disabled
1: SAI1 clock enabled
Bit 21 SPI6EN: SPI6 clock enable
This bit is set and cleared by software.
0: SPI6 clock disabled
1: SPI6 clock enabled
Bit 20 SPI5EN: SPI5 clock enable
This bit is set and cleared by software.
0: SPI5 clock disabled
1: SPI5 clock enabled
Bit 18 TIM11EN: TIM11 clock enable
This bit is set and cleared by software.
0: TIM11 clock disabled
1: TIM11 clock enabled
Bit 17 TIM10EN: TIM10 clock enable
This bit is set and cleared by software.
0: TIM10 clock disabled
1: TIM10 clock enabled
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DocID026670 Rev 6
USART6 USART1
EN
EN
rw
rw
19
18
17
16
Res.
TIM11
EN
TIM10
EN
TIM9
EN
rw
rw
rw
2
1
0
Res.
TIM8
EN
TIM1
EN
rw
rw
3
Res.
RM0385
Reset and clock control (RCC)
Bit 16 TIM9EN: TIM9 clock enable
This bit is set and cleared by software.
0: TIM9 clock disabled
1: TIM9 clock enabled
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGEN: System configuration controller clock enable
This bit is set and cleared by software.
0: System configuration controller clock disabled
1: System configuration controller clock enabled
Bit 13 SPI4EN: SPI4 clock enable
This bit is set and cleared by software.
0: SPI4 clock disabled
1: SPI4 clock enabled
Bit 12 SPI1EN: SPI1 clock enable
This bit is set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 SDMMC1EN: SDMMC1 clock enable
This bit is set and cleared by software.
0: SDMMC1 module clock disabled
1: SDMMC1 module clock enabled
Bit 10 ADC3EN: ADC3 clock enable
This bit is set and cleared by software.
0: ADC3 clock disabled
1: ADC3 clock disabled
Bit 9
ADC2EN: ADC2 clock enable
This bit is set and cleared by software.
0: ADC2 clock disabled
1: ADC2 clock disabled
Bit 8
ADC1EN: ADC1 clock enable
This bit is set and cleared by software.
0: ADC1 clock disabled
1: ADC1 clock disabled
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6EN: USART6 clock enable
This bit is set and cleared by software.
0: USART6 clock disabled
1: USART6 clock enabled
Bit 4 USART1EN: USART1 clock enable
This bit is set and cleared by software.
0: USART1 clock disabled
1: USART1 clock enabled
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Reset and clock control (RCC)
RM0385
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8EN: TIM8 clock enable
This bit is set and cleared by software.
0: TIM8 clock disabled
1: TIM8 clock enabled
Bit 0 TIM1EN: TIM1 clock enable
This bit is set and cleared by software.
0: TIM1 clock disabled
1: TIM1 clock enabled
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RM0385
5.3.15
Reset and clock control (RCC)
RCC AHB1 peripheral clock enable in low-power mode register
(RCC_AHB1LPENR)
Address offset: 0x50
Reset value: 0x7EF7 B7FFh
Access: no wait state, word, half-word and byte access.
31
Res.
30
rw
15
FLITF
LPEN
rw
29
28
27
26
25
OTGHS
ETHMA
OTGHS ETHPTP ETHRX ETHTX
C
ULPI
LPEN
LPEN
LPEN
LPEN
LPEN
LPEN
rw
rw
rw
11
10
9
Res.
GPIOK
LPEN
GPIOIJ
LPEN
rw
rw
14
13
12
Res.
AXI
LPEN
CRC
LPEN
rw
rw
rw
24
Res.
23
22
21
20
DMA2D
LPEN
DMA2
LPEN
rw
rw
rw
rw
7
6
5
4
rw
8
DMA1 DTCM
LPEN LPEN
19
Res.
18
17
16
BKPS
SRAM2 SRAM1
RAM
LPEN LPEN
LPEN
3
rw
rw
rw
2
1
0
GPIOI GPIOH GPIOGG GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA
LPEN LPEN
LPEN
LPEN LPEN LPEN LPEN LPEN LPEN
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 Reserved, must be kept at reset value.
Bit 30 OTGHSULPILPEN: USB OTG HS ULPI clock enable during Sleep mode
This bit is set and cleared by software.
0: USB OTG HS ULPI clock disabled during Sleep mode
1: USB OTG HS ULPI clock enabled during Sleep mode
Bit 29 OTGHSLPEN: USB OTG HS clock enable during Sleep mode
This bit is set and cleared by software.
0: USB OTG HS clock disabled during Sleep mode
1: USB OTG HS clock enabled during Sleep mode
Bit 28 ETHMACPTPLPEN: Ethernet PTP clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet PTP clock disabled during Sleep mode
1: Ethernet PTP clock enabled during Sleep mode
Bit 27 ETHMACRXLPEN: Ethernet reception clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet reception clock disabled during Sleep mode
1: Ethernet reception clock enabled during Sleep mode
Bit 26 ETHMACTXLPEN: Ethernet transmission clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet transmission clock disabled during sleep mode
1: Ethernet transmission clock enabled during sleep mode
Bit 25 ETHMACLPEN: Ethernet MAC clock enable during Sleep mode
This bit is set and cleared by software.
0: Ethernet MAC clock disabled during Sleep mode
1: Ethernet MAC clock enabled during Sleep mode
Bit 24 Reserved, must be kept at reset value.
Bit 23 DMA2DLPEN: DMA2D clock enable during Sleep mode
This bit is set and cleared by software.
0: DMA2D clock disabled during Sleep mode
1: DMA2D clock enabled during Sleep mode
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Reset and clock control (RCC)
RM0385
Bit 22 DMA2LPEN: DMA2 clock enable during Sleep mode
This bit is set and cleared by software.
0: DMA2 clock disabled during Sleep mode
1: DMA2 clock enabled during Sleep mode
Bit 21 DMA1LPEN: DMA1 clock enable during Sleep mode
This bit is set and cleared by software.
0: DMA1 clock disabled during Sleep mode
1: DMA1 clock enabled during Sleep mode
Bit 20 DTCMLPEN: DTCM RAM interface clock enable during Sleep mode
This bit is set and cleared by software.
0: DTCM RAM interface clock disabled during Sleep mode
1: DTCM RAM interface clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 BKPSRAMLPEN: Backup SRAM interface clock enable during Sleep mode
This bit is set and cleared by software.
0: Backup SRAM interface clock disabled during Sleep mode
1: Backup SRAM interface clock enabled during Sleep mode
Bit 17 SRAM2LPEN: SRAM2 interface clock enable during Sleep mode
This bit is set and cleared by software.
0: SRAM2 interface clock disabled during Sleep mode
1: SRAM2 interface clock enabled during Sleep mode
Bit 16 SRAM1LPEN: SRAM1 interface clock enable during Sleep mode
This bit is set and cleared by software.
0: SRAM1 interface clock disabled during Sleep mode
1: SRAM1 interface clock enabled during Sleep mode
Bit 15 FLITFLPEN: Flash interface clock enable during Sleep mode
This bit is set and cleared by software.
0: Flash interface clock disabled during Sleep mode
1: Flash interface clock enabled during Sleep mode
Bit 14 Reserved, must be kept at reset value.
Bit 13 AXILPEN: AXI to AHB bridge clock enable during Sleep mode
This bit is set and cleared by software.
0: AXI to AHB bridge clock disabled during Sleep mode
1: AXI to AHB bridge clock enabled during Sleep mode
Bit 12 CRCLPEN: CRC clock enable during Sleep mode
This bit is set and cleared by software.
0: CRC clock disabled during Sleep mode
1: CRC clock enabled during Sleep mode
Bit 11 Reserved, must be kept at reset value.
Bit 10 GPIOKLPEN: IO port K clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port K clock disabled during Sleep mode
1: IO port K clock enabled during Sleep mode
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RM0385
Reset and clock control (RCC)
Bit 9 GPIOJLPEN: IO port J clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port J clock disabled during Sleep mode
1: IO port J clock enabled during Sleep mode
Bit 8 GPIOILPEN: IO port I clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port I clock disabled during Sleep mode
1: IO port I clock enabled during Sleep mode
Bit 7 GPIOHLPEN: IO port H clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port H clock disabled during Sleep mode
1: IO port H clock enabled during Sleep mode
Bits 6 GPIOGLPEN: IO port G clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port G clock disabled during Sleep mode
1: IO port G clock enabled during Sleep mode
Bit 5 GPIOFLPEN: IO port F clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port F clock disabled during Sleep mode
1: IO port F clock enabled during Sleep mode
Bit 4 GPIOELPEN: IO port E clock enable during Sleep mode
Set and cleared by software.
0: IO port E clock disabled during Sleep mode
1: IO port E clock enabled during Sleep mode
Bit 3 GPIODLPEN: IO port D clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port D clock disabled during Sleep mode
1: IO port D clock enabled during Sleep mode
Bit 2 GPIOCLPEN: IO port C clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port C clock disabled during Sleep mode
1: IO port C clock enabled during Sleep mode
Bit 1 GPIOBLPEN: IO port B clock enable during Sleep mode
This bit is set and cleared by software.
0: IO port B clock disabled during Sleep mode
1: IO port B clock enabled during Sleep mode
Bit 0 GPIOALPEN: IO port A clock enable during sleep mode
This bit is set and cleared by software.
0: IO port A clock disabled during Sleep mode
1: IO port A clock enabled during Sleep mode
5.3.16
RCC AHB2 peripheral clock enable in low-power mode register
(RCC_AHB2LPENR)
Address offset: 0x54
Reset value: 0x0000 00F1
Access: no wait state, word, half-word and byte access.
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RM0385
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
HASH
LPEN
CRYP
LPEN
Res.
DCMI
LPEN
rw
rw
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OTGFS RNG
LPEN LPEN
rw
rw
Res.
Res.
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 OTGFSLPEN: USB OTG FS clock enable during Sleep mode
This bit is set and cleared by software.
0: USB OTG FS clock disabled during Sleep mode
1: USB OTG FS clock enabled during Sleep mode
Bit 6 RNGLPEN: Random number generator clock enable during Sleep mode
This bit is set and cleared by software.
0: Random number generator clock disabled during Sleep mode
1: Random number generator clock enabled during Sleep mode
Bit 5 HASHLPEN: Hash modules clock enable during Sleep mode
This bit is set and cleared by software.
0: Hash modules clock disabled during Sleep mode
1: Hash modules clock enabled during Sleep mode
Bit 4 CRYPLPEN: Cryptography modules clock enable during Sleep mode
This bit is set and cleared by software.
0: cryptography modules clock disabled during Sleep mode
1: cryptography modules clock enabled during Sleep mode
Bits 3:1 Reserved, must be kept at reset value.
Bit 0 DCMILPEN: Camera interface enable during Sleep mode
This bit is set and cleared by software.
0: Camera interface clock disabled during Sleep mode
1: Camera interface clock enabled during Sleep mode
5.3.17
RCC AHB3 peripheral clock enable in low-power mode register
(RCC_AHB3LPENR)
Address offset: 0x58
Reset value: 0x0000 0003
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QSPI
LPEN
FMC
LPEN
rw
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Reset and clock control (RCC)
Bits 31:2Reserved, must be kept at reset value.
Bit 1 QSPILPEN: QUADSPI memory controller clock enable during Sleep mode
This bit is set and cleared by software.
0: QUADSPI controller clock disabled during Sleep mode
1: QUADSPI controller clock enabled during Sleep mode
Bit 0 FMCLPEN: Flexible memory controller module clock enable during Sleep mode
This bit is set and cleared by software.
0: FMC module clock disabled during Sleep mode
1: FMC module clock enabled during Sleep mode
5.3.18
RCC APB1 peripheral clock enable in low-power mode register
(RCC_APB1LPENR)
Address offset: 0x60
Reset value: 0xFFFF CBFFh
Access: no wait state, word, half-word and byte access.
31
30
29
28
27
26
25
24
23
22
21
DAC
LPEN
PWR
LPEN
CEC
LPEN
CAN2
LPEN
CAN1
LPEN
I2C4
LPEN
I2C3
LPEN
I2C2
LPEN
I2C1
LPEN
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
7
6
Res.
WWDG
LPEN
UART8 UART7
LPEN LPEN
rw
15
14
SPI3
LPEN
SPI2
LPEN
rw
rw
Res.
rw
10
Res.
9
8
LPTMI1 TIM14
LPEN
LPEN
rw
TIM13 TIM12
LPEN LPEN
rw
rw
20
19
18
17
16
UART5 UART4 USART3 USART2 SPDIFRX
LPEN
LPEN LPEN
LPEN
LPEN
rw
rw
rw
rw
rw
5
4
3
2
1
0
TIM7
LPEN
TIM6
LPEN
TIM5
LPEN
TIM4
LPEN
TIM3
LPEN
TIM2
LPEN
rw
rw
rw
rw
rw
rw
Bit 31 UART8LPEN: UART8 clock enable during Sleep mode
This bit is set and cleared by software.
0: UART8 clock disabled during Sleep mode
1: UART8 clock enabled during Sleep mode
Bit 30 UART7LPEN: UART7 clock enable during Sleep mode
This bit is set and cleared by software.
0: UART7 clock disabled during Sleep mode
1: UART7 clock enabled during Sleep mode
Bit 29 DACLPEN: DAC interface clock enable during Sleep mode
This bit is set and cleared by software.
0: DAC interface clock disabled during Sleep mode
1: DAC interface clock enabled during Sleep mode
Bit 28 PWRLPEN: Power interface clock enable during Sleep mode
This bit is set and cleared by software.
0: Power interface clock disabled during Sleep mode
1: Power interface clock enabled during Sleep mode
Bit 27 CECLPEN: HDMI-CEC clock enable during Sleep mode
This bit is set and cleared by software.
0: HDMI-CEC clock disabled during Sleep mode
1: HDMI-CEC clock enabled during Sleep mode
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Bit 26 CAN2LPEN: CAN 2 clock enable during Sleep mode
This bit is set and cleared by software.
0: CAN 2 clock disabled during sleep mode
1: CAN 2 clock enabled during sleep mode
Bit 25 CAN1LPEN: CAN 1 clock enable during Sleep mode
This bit is set and cleared by software.
0: CAN 1 clock disabled during Sleep mode
1: CAN 1 clock enabled during Sleep mode
Bit 24 I2C4LPEN: I2C4 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C4 clock disabled during Sleep mode
1: I2C4 clock enabled during Sleep mode
Bit 23 I2C3LPEN: I2C3 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C3 clock disabled during Sleep mode
1: I2C3 clock enabled during Sleep mode
Bit 22 I2C2LPEN: I2C2 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C2 clock disabled during Sleep mode
1: I2C2 clock enabled during Sleep mode
Bit 21 I2C1LPEN: I2C1 clock enable during Sleep mode
This bit is set and cleared by software.
0: I2C1 clock disabled during Sleep mode
1: I2C1 clock enabled during Sleep mode
Bit 20 UART5LPEN: UART5 clock enable during Sleep mode
This bit is set and cleared by software.
0: UART5 clock disabled during Sleep mode
1: UART5 clock enabled during Sleep mode
Bit 19 UART4LPEN: UART4 clock enable during Sleep mode
This bit is set and cleared by software.
0: UART4 clock disabled during Sleep mode
1: UART4 clock enabled during Sleep mode
Bit 18 USART3LPEN: USART3 clock enable during Sleep mode
This bit is set and cleared by software.
0: USART3 clock disabled during Sleep mode
1: USART3 clock enabled during Sleep mode
Bit 17 USART2LPEN: USART2 clock enable during Sleep mode
This bit is set and cleared by software.
0: USART2 clock disabled during Sleep mode
1: USART2 clock enabled during Sleep mode
Bit 16 SPDIFRXLPEN: SPDIFRX clock enable during Sleep mode
This bit is set and cleared by software.
0: SPDIFRX clock disabled during Sleep mode
1: SPDIFRX clock enabled during Sleep mode
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Reset and clock control (RCC)
Bit 15 SPI3LPEN: SPI3 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI3 clock disabled during Sleep mode
1: SPI3 clock enabled during Sleep mode
Bit 14 SPI2LPEN: SPI2 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI2 clock disabled during Sleep mode
1: SPI2 clock enabled during Sleep mode
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 WWDGLPEN: Window watchdog clock enable during Sleep mode
This bit is set and cleared by software.
0: Window watchdog clock disabled during sleep mode
1: Window watchdog clock enabled during sleep mode
Bit 10 Reserved, must be kept at reset value.
Bit 9 LPTIM1LPEN: low-power timer 1 clock enable during Sleep mode
This bit is set and cleared by software.
0: LPTIM1 clock disabled during Sleep mode
1: LPTIM1 clock enabled during Sleep mode
Bit 8 TIM14LPEN: TIM14 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM14 clock disabled during Sleep mode
1: TIM14 clock enabled during Sleep mode
Bit 7 TIM13LPEN: TIM13 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM13 clock disabled during Sleep mode
1: TIM13 clock enabled during Sleep mode
Bit 6 TIM12LPEN: TIM12 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM12 clock disabled during Sleep mode
1: TIM12 clock enabled during Sleep mode
Bit 5 TIM7LPEN: TIM7 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM7 clock disabled during Sleep mode
1: TIM7 clock enabled during Sleep mode
Bit 4 TIM6LPEN: TIM6 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM6 clock disabled during Sleep mode
1: TIM6 clock enabled during Sleep mode
Bit 3 TIM5LPEN: TIM5 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM5 clock disabled during Sleep mode
1: TIM5 clock enabled during Sleep mode
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Bit 2 TIM4LPEN: TIM4 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM4 clock disabled during Sleep mode
1: TIM4 clock enabled during Sleep mode
Bit 1 TIM3LPEN: TIM3 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM3 clock disabled during Sleep mode
1: TIM3 clock enabled during Sleep mode
Bit 0 TIM2LPEN: TIM2 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM2 clock disabled during Sleep mode
1: TIM2 clock enabled during Sleep mode
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Reset and clock control (RCC)
5.3.19
RCC APB2 peripheral clock enabled in low-power mode register
(RCC_APB2LPENR)
Address offset: 0x64
Reset value: 0x04F7 7F33h
Access: no wait state, word, half-word and byte access.
31
Res.
30
Res.
29
Res.
28
Res.
27
26
Res.
LTDC
LPEN
25
Res.
24
23
22
21
20
Res.
SAI2
LPEN
SAI1
LPEN
SPI6
LPEN
SPI5
LPEN
rw
rw
rw
rw
7
6
5
4
rw
15
14
13
12
11
10
9
8
Res.
SYSCFG
LPEN
SPI4
LPEN
SPI1
LPEN
SDMMC1
LPEN
ADC3
LPEN
ADC2
LPEN
ADC1
LPEN
rw
rw
rw
rw
rw
rw
rw
Res.
Res.
USART6 USART1
LPEN
LPEN
rw
rw
19
18
17
16
Res.
TIM11
LPEN
TIM10
LPEN
TIM9
LPEN
rw
rw
rw
3
Res.
2
1
0
Res.
TIM8
LPEN
TIM1
LPEN
rw
rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 LTDCLPEN: LTDC clock enable during Sleep mode
This bit is set and cleared by software.
0: LTDC clock disabled during Sleep mode
1: LTDC clock enabled during Sleep mode
Bits 25:24 Reserved, must be kept at reset value.
Bit 23 SAI2LPEN: SAI2 clock enable during Sleep mode
This bit is set and cleared by software.
0: SAI2 clock disabled during Sleep mode
1: SAI2 clock enabled during Sleep mode
Bit 22 SAI1LPEN: SAI1 clock enable during Sleep mode
This bit is set and cleared by software.
0: SAI1 clock disabled during Sleep mode
1: SAI1 clock enabled during Sleep mode
Bit 21 SPI6LPEN: SPI6 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI6 clock disabled during Sleep mode
1: SPI6 clock enabled during Sleep mode
Bit 20 SPI5LPEN: SPI5 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI5 clock disabled during Sleep mode
1: SPI5 clock enabled during Sleep mode
Bit 19 Reserved, must be kept at reset value.
Bit 18 TIM11LPEN: TIM11 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM11 clock disabled during Sleep mode
1: TIM11 clock enabled during Sleep mode
Bit 17 TIM10LPEN: TIM10 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM10 clock disabled during Sleep mode
1: TIM10 clock enabled during Sleep mode
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Bit 16 TIM9LPEN: TIM9 clock enable during sleep mode
This bit is set and cleared by software.
0: TIM9 clock disabled during Sleep mode
1: TIM9 clock enabled during Sleep mode
Bit 15 Reserved, must be kept at reset value.
Bit 14 SYSCFGLPEN: System configuration controller clock enable during Sleep mode
This bit is set and cleared by software.
0: System configuration controller clock disabled during Sleep mode
1: System configuration controller clock enabled during Sleep mode
Bit 13 SPI4LPEN: SPI4 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI4 clock disabled during Sleep mode
1: SPI4 clock enabled during Sleep mode
Bit 12 SPI1LPEN: SPI1 clock enable during Sleep mode
This bit is set and cleared by software.
0: SPI1 clock disabled during Sleep mode
1: SPI1 clock enabled during Sleep mode
Bit 11 SDMMC1LPEN: SDMMC1 clock enable during Sleep mode
This bit is set and cleared by software.
0: SDMMC1 module clock disabled during Sleep mode
1: SDMMC1 module clock enabled during Sleep mode
Bit 10 ADC3LPEN: ADC 3 clock enable during Sleep mode
This bit is set and cleared by software.
0: ADC 3 clock disabled during Sleep mode
1: ADC 3 clock enabled during Sleep mode
Bit 9 ADC2LPEN: ADC2 clock enable during Sleep mode
This bit is set and cleared by software.
0: ADC2 clock disabled during Sleep mode
1: ADC2 clock enabled during Sleep mode
Bit 8 ADC1LPEN: ADC1 clock enable during Sleep mode
This bit is set and cleared by software.
0: ADC1 clock disabled during Sleep mode
1: ADC1 clock enabled during Sleep mode
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 USART6LPEN: USART6 clock enable during Sleep mode
This bit is set and cleared by software.
0: USART6 clock disabled during Sleep mode
1: USART6 clock enabled during Sleep mode
Bit 4 USART1LPEN: USART1 clock enable during Sleep mode
This bit is set and cleared by software.
0: USART1 clock disabled during Sleep mode
1: USART1 clock enabled during Sleep mode
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Reset and clock control (RCC)
Bits 3:2 Reserved, must be kept at reset value.
Bit 1 TIM8LPEN: TIM8 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM8 clock disabled during Sleep mode
1: TIM8 clock enabled during Sleep mode
Bit 0 TIM1LPEN: TIM1 clock enable during Sleep mode
This bit is set and cleared by software.
0: TIM1 clock disabled during Sleep mode
1: TIM1 clock enabled during Sleep mode
5.3.20
RCC backup domain control register (RCC_BDCR)
Address offset: 0x70
Reset value: 0x0000 0000, reset by Backup domain reset.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC backup domain control
register (RCC_BDCR) are in the Backup domain. As a result, after Reset, these bits are
write-protected and the DBP bit in the PWR power control register (PWR_CR1) has to be
set before these can be modified. Refer to Section 5.1.1: System reset on page 128 for
further information. These bits are only reset after a Backup domain Reset (see
Section 5.1.3: Backup domain reset). Any internal or external Reset will not have any effect
on these bits.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BDRST
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
RTCEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
RTCSEL[1:0]
rw
rw
LSEDRV[1:0]
rw
rw
0
LSEBYP LSERDY LSEON
rw
r
rw
Bits 31:17 Reserved, must be kept at reset value.
Bit 16 BDRST: Backup domain software reset
This bit is set and cleared by software.
0: Reset not activated
1: Resets the entire Backup domain
Note: The BKPSRAM is not affected by this reset, the only way of resetting the BKPSRAM is
through the Flash interface when a protection level change from level 1 to level 0 is
requested.
Bit 15 RTCEN: RTC clock enable
This bit is set and cleared by software.
0: RTC clock disabled
1: RTC clock enabled
Bits 14:10 Reserved, must be kept at reset value.
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Bits 9:8 RTCSEL[1:0]: RTC clock source selection
These bits are set by software to select the clock source for the RTC. Once the RTC clock
source has been selected, it cannot be changed anymore unless the Backup domain is
reset. The BDRST bit can be used to reset them.
00: No clock
01: LSE oscillator clock used as the RTC clock
10: LSI oscillator clock used as the RTC clock
11: HSE oscillator clock divided by a programmable prescaler (selection through the
RTCPRE[4:0] bits in the RCC clock configuration register (RCC_CFGR)) used as the RTC
clock
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:3 LSEDRV[1:0]: LSE oscillator drive capability
Set by software to modulate the LSE oscillator’s drive capability.
00: Low driving capability
01: Medium high driving capability
10: Medium low driving capability
11: High driving capability
Bit 2 LSEBYP: External low-speed oscillator bypass
This bit is set and cleared by software to bypass the oscillator. This bit can be written only
when the LSE clock is disabled.
0: LSE oscillator not bypassed
1: LSE oscillator bypassed
Bit 1 LSERDY: External low-speed oscillator ready
This bit is set and cleared by hardware to indicate when the external 32 kHz oscillator is
stable. After the LSEON bit is cleared, LSERDY goes low after 6 external low-speed
oscillator clock cycles.
0: LSE clock not ready
1: LSE clock ready
Bit 0 LSEON: External low-speed oscillator enable
This bit is set and cleared by software.
0: LSE clock OFF
1: LSE clock ON
5.3.21
RCC clock control & status register (RCC_CSR)
Address offset: 0x74
Reset value: 0x0E00 0000, reset by system reset, except reset flags by power reset only.
Access: 0 ≤ wait state ≤ 3, word, half-word and byte access
Wait states are inserted in case of successive accesses to this register.
31
30
LPWR WWDG
RSTF RSTF
r
r
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IWDG
RSTF
SFT
RSTF
POR
RSTF
PIN
RSTF
BOR
RSTF
RMVF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
r
r
r
r
r
r
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LSIRDY LSION
r
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RM0385
Reset and clock control (RCC)
Bit 31 LPWRRSTF: Low-power reset flag
This bit is set by hardware when a Low-power management reset occurs.
Cleared by writing to the RMVF bit.
0: No Low-power management reset occurred
1: Low-power management reset occurred
For further information on Low-power management reset, refer to Low-power management
reset.
Bit 30 WWDGRSTF: Window watchdog reset flag
This bit is set by hardware when a window watchdog reset occurs.
Cleared by writing to the RMVF bit.
0: No window watchdog reset occurred
1: Window watchdog reset occurred
Bit 29 IWDGRSTF: Independent watchdog reset flag
This bit is set by hardware when an independent watchdog reset from VDD domain occurs.
Cleared by writing to the RMVF bit.
0: No watchdog reset occurred
1: Watchdog reset occurred
Bit 28 SFTRSTF: Software reset flag
This bit is set by hardware when a software reset occurs.
Cleared by writing to the RMVF bit.
0: No software reset occurred
1: Software reset occurred
Bit 27 PORRSTF: POR/PDR reset flag
This bit is set by hardware when a POR/PDR reset occurs.
Cleared by writing to the RMVF bit.
0: No POR/PDR reset occurred
1: POR/PDR reset occurred
Bit 26 PINRSTF: PIN reset flag
This bit is set by hardware when a reset from the NRST pin occurs.
Cleared by writing to the RMVF bit.
0: No reset from NRST pin occurred
1: Reset from NRST pin occurred
Bit 25 BORRSTF: BOR reset flag
Cleared by software by writing the RMVF bit.
This bit is set by hardware when a POR/PDR or BOR reset occurs.
0: No POR/PDR or BOR reset occurred
1: POR/PDR or BOR reset occurred
Bit 24 RMVF: Remove reset flag
This bit is set by software to clear the reset flags.
0: No effect
1: Clear the reset flags
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Bits 23:2 Reserved, must be kept at reset value.
Bit 1 LSIRDY: Internal low-speed oscillator ready
This bit is set and cleared by hardware to indicate when the internal RC 40 kHz oscillator is
stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI clock cycles.
0: LSI RC oscillator not ready
1: LSI RC oscillator ready
Bit 0 LSION: Internal low-speed oscillator enable
This bit is set and cleared by software.
0: LSI RC oscillator OFF
1: LSI RC oscillator ON
5.3.22
RCC spread spectrum clock generation register (RCC_SSCGR)
Address offset: 0x80
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
The spread spectrum clock generation is available only for the main PLL.
The RCC_SSCGR register must be written either before the main PLL is enabled or after
the main PLL disabled.
Note:
For full details about PLL spread spectrum clock generation (SSCG) characteristics, refer to
the “Electrical characteristics” section in your device datasheet.
31
30
29
28
SSCG
EN
SPR
EAD
SEL
Res.
Res.
13
12
rw
rw
15
14
27
26
25
24
23
rw
21
20
19
18
17
16
INCSTEP
rw
rw
rw
11
10
9
8
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
INCSTEP
rw
22
MODPER
rw
rw
rw
rw
rw
rw
rw
rw
Bit 31 SSCGEN: Spread spectrum modulation enable
This bit is set and cleared by software.
0: Spread spectrum modulation DISABLE. (To write after clearing CR[24]=PLLON bit)
1: Spread spectrum modulation ENABLE. (To write before setting CR[24]=PLLON bit)
Bit 30 SPREADSEL: Spread Select
This bit is set and cleared by software.
To write before to set CR[24]=PLLON bit.
0: Center spread
1: Down spread
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Reset and clock control (RCC)
Bits 29:28 Reserved, must be kept at reset value.
Bits 27:13 INCSTEP: Incrementation step
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile amplitude.
Bits 12:0 MODPER: Modulation period
These bits are set and cleared by software. To write before setting CR[24]=PLLON bit.
Configuration input for modulation profile period.
5.3.23
RCC PLLI2S configuration register (RCC_PLLI2SCFGR)
Address offset: 0x84
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLI2S clock outputs according to the formulas:
f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN / PLLM)
f(PLLI2S_P) = f(VCO clock) / PLLI2SP
f(PLLI2S_Q) = f(VCO clock) / PLLI2SQ
f(PLLI2S_R) = f(VCO clock) / PLLI2SR
31
30
Res.
15
29
28
27
PLLI2SR[2:0]
26
25
24
PLLI2SQ[0:3]
rw
rw
rw
rw
14
13
12
11
Res.
rw
rw
rw
10
9
8
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
rw
7
6
PLLI2SN[8:0]
rw
rw
rw
rw
rw
rw
rw
DocID026670 Rev 6
17
rw
16
PLLI2SP[1:0]
rw
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
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RM0385
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLI2SR[2:0]: PLLI2S division factor for I2S clocks
These bits are set and cleared by software to control the I2S clock frequency. These bits
should be written only if the PLLI2S is disabled. The factor must be chosen in accordance
with the prescaler values inside the I2S peripherals, to reach 0.3% error when using
standard crystals and 0% error with audio crystals. For more information about I2S clock
frequency and precision, refer to Section 32.7.4: Start-up description in the I2S chapter.
Caution: The I2Ss requires a frequency lower than or equal to 192 MHz to work correctly.
I2S clock frequency = VCO frequency / PLLR with 2 ≤ PLLR ≤ 7
000: PLLR = 0, wrong configuration
001: PLLR = 1, wrong configuration
010: PLLR = 2
...
111: PLLR = 7
Bits 27:24 PLLI2SQ[3:0]: PLLI2S division factor for SAIs clock
These bits are set and cleared by software to control the SAIs clock frequency.
They should be written when the PLLI2S is disabled.
SAI clock frequency = VCO frequency / PLLI2SQ with 2 <= PLLI2SIQ <= 15
0000: PLLI2SQ = 0, wrong configuration
0001: PLLI2SQ = 1, wrong configuration
0010: PLLI2SQ = 2
0011: PLLI2SQ = 3
0100: PLLI2SQ = 4
0101: PLLI2SQ = 5
...
1111: PLLI2SQ = 15
Bits 23:18 Reserved, must be kept at reset value.
Bits 17:16 PLLI2SP[1:0]: PLLI2S division factor for SPDIFRX clock
These bits are set and cleared by software to control the SPDIFRX clock. These
bits can be written only if the PLLI2S is disabled.
The factor must be chosen in accordance with the prescaler values inside the SPDIF to
reach an audio clock close to 44 kHz or 48 kHz according to the SPDIF mode
SPDIF clock frequency = VCO frequency / PLLI2SP with PLLI2S P = 2, 4, 6, or 8
00: PLLI2SP = 2
01: PLLI2SP = 4
10: PLLI2SP = 6
11: PLLI2SP = 8
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RM0385
Reset and clock control (RCC)
Bit 15 Reserved, must be kept at reset value.
Bits 14:6 PLLI2SN[8:0]: PLLI2S multiplication factor for VCO
These bits are set and cleared by software to control the multiplication factor of the VCO.
These bits can be written only when the PLLI2S is disabled. Only half-word and word
accesses are allowed to write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output
frequency is between 100 and 432 MHz.
VCO output frequency = VCO input frequency × PLLI2SN with 50 ≤ PLLI2SN ≤ 432
000000000: PLLI2SN = 0, wrong configuration
000000001: PLLI2SN = 1, wrong configuration
...
001100010: PLLI2SN = 50
...
001100011: PLLI2SN = 99
001100100: PLLI2SN = 100
001100101: PLLI2SN = 101
001100110: PLLI2SN = 102
...
110110000: PLLI2SN = 432
110110000: PLLI2SN = 433, wrong configuration
...
111111111: PLLI2SN = 511, wrong configuration
Note: Between 50 and 99, multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 Reserved, must be kept at reset value.
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5.3.24
RM0385
RCC PLLSAI configuration register (RCC_PLLSAICFGR)
Address offset: 0x88
Reset value: 0x2400 3000
Access: no wait state, word, half-word and byte access.
This register is used to configure the PLLSAI clock outputs according to the formulas:
31
30
Res.
15
•
f(VCO clock) = f(PLLSAI clock input) × (PLLSAIN / PLLM)
•
f(PLLISAI_P) = f(VCO clock) / PLLSAIP
•
f(PLLISAI_Q) = f(VCO clock) / PLLSAIQ
•
f(PLLISAI_R) = f(VCO clock) / PLLSAIR
29
28
27
PLLSAIR[2:0]
26
25
24
PLLSAIQ[4:0]
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
14
13
12
11
10
9
8
7
6
rw
rw
rw
rw
rw
rw
rw
rw
Res.
PLLSAIN[8:0]
rw
Bit 31 Reserved, must be kept at reset value.
Bits 30:28 PLLSAIR[2:0]: PLLSAI division factor for LCD clock
Set and reset by software to control the LCD clock frequency.
These bits should be written when the PLLSAI is disabled.
LCD clock frequency = VCO frequency / PLLSAIR with 2 ≤ PLLSAIR ≤ 7
000: PLLSAIR = 0, wrong configuration
001: PLLSAIR = 1, wrong configuration
010: PLLSAIR = 2
...
111: PLLSAIR = 7
Bits 27:24 PLLSAIQ[3:0]: PLLSAI division factor for SAI clock
Set and reset by software to control the frequency of SAI clock.
These bits should be written when the PLLSAI is disabled.
SAI1 clock frequency = VCO frequency / PLLSAIQ with 2 ≤ PLLSAIQ ≤ 15
0000: PLLSAIQ = 0, wrong configuration
0001: PLLSAIQ = 1, wrong configuration
...
0010: PLLSAIQ = 2
0011: PLLSAIQ = 3
0100: PLLSAIQ = 4
0101: PLLSAIQ = 5
...
1111: PLLSAIQ = 15
Bits 23:18 Reserved, must be kept at reset value.
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17
16
PLLSAIP[1:0]
RM0385
Reset and clock control (RCC)
Bits 17:16 PLLSAIP[1:0]: PLLSAI division factor for 48MHz clock
Set and reset by software to control the frequency of the PLLSAI output clock
(PLLSAI48CLK). This output can be selected for USB, RNG, SDMMC (48 MHz clock). These
bits should be written only if the PLLSAI is disabled.
Only half-word and word accesses are allowed to write these bits.
PLLSAI48 output clock frequency = VCO frequency / PLLSAIP with PLLSAI P = 2, 4, 6, or 8
00: PLLSAIP = 2
01: PLLSAIP = 4
10: PLLSAIP = 6
11: PLLSAIP = 8
Bit 15 Reserved, must be kept at reset value.
Bits 14:6 PLLSAIN[8:0]: PLLSAI division factor for VCO
Set and reset by software to control the multiplication factor of the VCO.
These bits should be written when the PLLSAI is disabled.
Only half-word and word accesses are allowed to write these bits.
Caution: The software has to set these bits correctly to ensure that the VCO output frequency
is between 100 and 432 MHz.
VCO output frequency = VCO input frequency x PLLSAIN with 50 ≤ PLLSAIN ≤ 432
000000000: PLLSAIN = 0, wrong configuration
000000001: PLLSAIN = 1, wrong configuration
......
001100010: PLLISAIN = 50
...
001100011: PLLISAIN = 99
001100100: PLLISAIN = 100
001100101: PLLISAIN = 101
001100110: PLLISAIN = 102
...
110110000: PLLSAIN = 432
110110000: PLLSAIN = 433, wrong configuration
...
111111111: PLLSAIN = 511, wrong configuration
Note: Between 50 and 99, multiplication factors are possible for VCO input frequency higher
than 1 MHz. However care must be taken to fulfill the minimum VCO output frequency
as specified above.
Bits 5:0 Reserved, must be kept at reset value
5.3.25
RCC dedicated clocks configuration register (RCC_DKCFGR1)
Address offset: 0x8C
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access.
This register allows to configure the timer clock prescalers and the PLLSAI and PLLI2S
output clock dividers for SAIs and LTDC peripherals according to the following formula:
f(PLLSAIDIVQ clock output) = f(PLLSAI_Q) / PLLSAIDIVQ
f(PLLSAIDIVR clock output) = f(PLLSAI_R) / PLLSAIDIVR
f(PLLI2SDIVQ clock output) = f(PLLI2S_Q) / PLLI2SDIVQ
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Reset and clock control (RCC)
RM0385
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TIMPRE
15
14
13
Res.
Res.
Res.
12
11
10
9
rw
rw
rw
22
SAI2SEL[1:0]
21
20
SAI1SEL[1:0]
rw
rw
rw
rw
rw
8
7
6
5
4
Res.
Res.
Res.
PLLSAIDIVQ[4:0]
rw
23
rw
19
18
Res.
Res.
3
2
17
16
PLLSAIDIVR[1:0]
rw
rw
1
0
rw
rw
PLLI2SDIVQ[4:0]
rw
rw
rw
Bits 31:25 Reserved, must be kept at reset value.
Bit 24 TIMPRE: Timers clocks prescalers selection
This bit is set and reset by software to control the clock frequency of all the timers connected
to APB1 and APB2 domain.
0: If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, TIMxCLK = PCLKx. Otherwise, the timer clock frequencies are set to
twice to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 2xPCLKx.
1:If the APB prescaler (PPRE1, PPRE2 in the RCC_CFGR register) is configured to a
division factor of 1, 2 or 4, TIMxCLK = HCLK. Otherwise, the timer clock frequencies are set
to four times to the frequency of the APB domain to which the timers are connected:
TIMxCLK = 4xPCLKx.
Bits 23:22 SAI2SEL[1:0]: SAI2 clock source selection:
These bits are set and cleared by software to control the SAI2 clock frequency.
They should be written when the PLLSAI and PLLI2S are disabled.
00: SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
01: SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
10: SAI2 clock frequency = Alternate function input frequency
11: wrong configuration
Bits 21:20 SAI1SEL[1:0]: SAI1 clock source selection
These bits are set and cleared by software to control the SAI1 clock frequency.
They should be written when the PLLSAI and PLLI2S are disabled.
00: SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ
01: SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ
10: SAI1 clock frequency = Alternate function input frequency
11: wrong configuration
Bits 19: 18 Reserved, must be kept at reset value.
Bits 17:16 PLLSAIDIVR[1:0]: division factor for LCD_CLK
These bits are set and cleared by software to control the frequency of LCD_CLK.
They should be written only if PLLSAI is disabled.
LCD_CLK frequency = f(PLLSAI_R) / PLLSAIDIVR with 2 ≤ PLLSAIDIVR ≤ 16
00: PLLSAIDIVR = /2
01: PLLSAIDIVR = /4
10: PLLSAIDIVR = /8
11: PLLSAIDIVR = /16
Bits 15: 13 Reserved, must be kept at reset value.
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Reset and clock control (RCC)
Bits 12:8 PLLSAIDIVQ[4:0]: PLLSAI division factor for SAI1 clock
These bits are set and reset by software to control the SAI1 clock frequency.
They should be written only if PLLSAI is disabled.
SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ with 1 ≤ PLLSAIDIVQ ≤ 31
00000: PLLSAIDIVQ = /1
00001: PLLSAIDIVQ = /2
00010: PLLSAIDIVQ = /3
00011: PLLSAIDIVQ = /4
00100: PLLSAIDIVQ = /5
...
11111: PLLSAIDIVQ = /32
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 PLLI2SDIV[4:0]: PLLI2S division factor for SAI1 clock
These bits are set and reset by software to control the SAI1 clock frequency.
They should be written only if PLLI2S is disabled.
SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ with 1 <= PLLI2SDIVQ <= 31
00000: PLLI2SDIVQ = /1
00001: PLLI2SDIVQ = /2
00010: PLLI2SDIVQ = /3
00011: PLLI2SDIVQ = /4
00100: PLLI2SDIVQ = /5
...
11111: PLLI2SDIVQ = /32
5.3.26
RCC dedicated clocks configuration register (DCKCFGR2)
Address: 0x90h
Reset value: 0x0000 0000h
Access: no wait state, word, half-word and byte access
This register allows to select the source clock for the 48MHz, SDMMC, HDMI-CEC,
LPTIM1, UARTs, USARTs and I2Cs clocks.
31
30
29
Res.
Res.
Res.
15
14
13
28
26
SDMM CK48M CECSE
C1SEL
SEL
L
25
24
LPTIM1SEL
23
22
I2C4SEL
21
20
I2C3SEL
19
18
I2C2SEL
17
16
I2C1SEL
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
12
11
10
9
8
7
6
5
4
3
2
1
0
UART8SEL
UART7SEL
rw
rw
rw
27
rw
USART6SEL
rw
rw
UART5SEL
UART4SEL
UART3SEL
UART2SEL
UART1SEL
rw
rw
rw
rw
rw
rw
rw
DocID026670 Rev 6
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rw
rw
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Reset and clock control (RCC)
RM0385
Bits 31:29 Reserved, must be kept at reset value.
Bit 28 SDMMCSEL: SDMMC clock source selection
Set and reset by software.
0: 48 MHz clock is selected as SDMMC clock
1: System clock is selected as SDMMC clock
Bit 27 CK48MSEL: 48MHz clock source selection
Set and reset by software.
0: 48MHz clock from PLL is selected
1: 48MHz clock from PLLSAI is selected.
Bit 26 CECSEL: HDMI-CEC clock source selection
Set and reset by software.
0: LSE clock is selected as HDMI-CEC clock
1: HSI divided by 488 clock is selected as HDMI-CEC clock
Bits 25:24 LPTIM1SEL: Low-power timer 1 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) selected as LPTILM1 clock
01: LSI clock is selected as LPTILM1 clock
10: HSI clock is selected as LPTILM1 clock
11: LSE clock is selected as LPTILM1 clock
Bits 23:22 I2C4SEL: I2C4 clock source selection
Set and reset by software.
00: APB1 clock ( PCLK1) is selected as I2C4 clock
01: System clock is selected as I2C4 clock
10: HSI clock is selected as I2C4 clock
11: reserved
Bits 21:20 I2C3SEL: I2C3 clock source selection
Set and reset by software.
00: APB clock is selected as I2C3 clock
01: System clock is selected as I2C3 clock
10: HSI clock is selected as I2C3 clock
11: reserved
Bits 19:18 I2C2SEL: I2C2 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) is selected as I2C2 clock
01: System clock is selected as I2C2 clock
10: HSI clock is selected as I2C2 clock
11: reserved
Bits 17:16 I2C1SEL: I2C1 clock source selection
Set and reset by software.
00: APB clock (PCLK1) is selected as I2C1 clock
01: System clock is selected as I2C1 clock
10: HSI clock is selected as I2C1 clock
11: reserved
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RM0385
Reset and clock control (RCC)
Bits 15:14 UART8SEL[1:0]: UART 8 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) is selected as UART 8 clock
01: System clock is selected as UART 8 clock
10: HSI clock is selected as UART 8 clock
11: LSE clock is selected as UART 8 clock
Bits 13:12 UART7SEL[1:0]: UART 7 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) is selected as UART 7 clock
01: System clock is selected as UART 7 clock
10: HSI clock is selected as UART 7 clock
11: LSE clock is selected as UART 7 clock
Bits 11:10 USART6SEL[1:0]: USART 6 clock source selection
Set and reset by software.
00: APB2 clock(PCLK2) is selected as USART 6 clock
01: System clock is selected as USART 6 clock
10: HSI clock is selected as USART 6 clock
11: LSE clock is selected as USART 6 clock
Bits 9:8 UART5SEL[1:0]: UART 5 clock source selection
Set and reset by software.
00: APB1 clock(PCLK1) is selected as UART 5 clock
01: System clock is selected as UART 5 clock
10: HSI clock is selected as UART 5 clock
11: LSE clock is selected as UART 5 clock
Bits7:6 UART4SEL[1:0]: UART 4 clock source selection
Set and reset by software.
00: APB1 clock (PLCLK1) is selected as UART 4 clock
01: System clock is selected as UART 4 clock
10: HSI clock is selected as UART 4 clock
11: LSE clock is selected as UART 4 clock
Bits5:4 USART3SEL[1:0]: USART 3 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) is selected as USART 3 clock
01: System clock is selected as USART 3 clock
10: HSI clock is selected as USART 3 clock
11: LSE clock is selected as USART 3 clock
Bits 3:2 USART2SEL[1:0]: USART 2 clock source selection
Set and reset by software.
00: APB1 clock (PCLK1) is selected as USART 2 clock
01: System clock is selected as USART 2 clock
10: HSI clock is selected as USART 2 clock
11: LSE clock is selected as USART 2 clock
Bits 1:0 USART1SEL[1:0]: USART 1 clock source selection
Set and reset by software.
00: APB2 clock (PCLK2) is selected as USART 1 clock
01: System clock is selected as USART 1 clock
10: HSI clock is selected as USART 1 clock
11: LSE clock is selected as USART 1 clock
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0x14
RCC_AHB2RS
TR
0x18
RCC_AHB3RS
TR
0x1C
Reserved
0x20
RCC_APB1RS
TR
0x24
RCC_APB2RS
TR
0x28
Reserved
0x2C
Reserved
0x30
RCC_
AHB1ENR
Res.
0x34
RCC_
AHB2ENR
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DMA2EN
DMA1EN
Res.
Res.
Res.
DocID026670 Rev 6
GPIOAEN
GPIOFEN
DCMIEN
GPIOGEN
RNGEN
HASHEN
GPIOBEN
GPIOHEN
OTGFSEN
Res.
GPIOIEN
Res.
GPIOCEN
GPIOJEN
Res.
Res.
GPIOKEN
Res.
GPIOEEN
Res.
Res.
GPIODEN
CRCEN
Res.
Res.
Res. Res.
Res.
Res.
CRYPEN
Res. Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
TIM5RST
TIM4RST
TIM3RST
TIM2RST
Res.
Res.
TIM8RST
TIM1RST
TIM6RST
Res. Res.
Res. Res. USART1RST
TIM12RST Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
RNGRST
GPIOIRST
GPIOJRST
GPIOKRST
Res.
CRCRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA1RST
Res.
Res.
Res.
CSSF
LSIRDYIE
LSERDYIE
HSIRDYIE
HSERDYIE
PLLRDYIE
PLLI2SRDYIE
GPIOARST
GPIOBRST
GPIOCRST
GPIODRST
LSIRDYF
LSERDYF
HSIRDYF
HSERDYF
PLLRDYF
GPIOFRST PLLI2SRDYF
Res.
Res.
Res.
PLL SAION
PLL SAIRDY
Res.
Res.
Res.
Res.
Res.
Res.
PPRE2 2
SW 0
SW 1
SWS 0
SWS 1
HPRE 0
HPRE 1
HPRE 2
HPRE 3
Res.
Res.
HSICAL 0
HSICAL 1
HSICAL 2
HSICAL 3
HSICAL 4
HSICAL 5
HSICAL 6
HSICAL 7
HSEON
HSERDY
HSEBYP
CSSON
Res.
Res.
Res.
Res.
PLL ON
PLL RDY
PLLM 0
PLLM 1
PLLM 2
HSION
HSIRDY
Reserved
PLLM 3 HSITRIM 0
PLLM 4 HSITRIM 1
PLLM 5 HSITRIM 2
PLLN 0 HSITRIM 3
PLLN 1 HSITRIM 4
PLLN 2
PLLN 3
PPRE1 2 PLLN 6
PPRE1 1 PLLN 5
PPRE1 0 PLLN 4
PPRE2 0 PLLN 7
PLLN 8
Res.
RTCPRE 0 PLLP 0
RTCPRE 1 PLLP 1
RTCPRE 2
RTCPRE 3
MCO1 0
RTCPRE 4
MCO1 1 PLLSRC
I2SSRC
MCO1PRE1 PLLQ 1
MCO1PRE0 PLLQ 0
MCO1PRE2 PLLQ 2 PLL I2SON
MCO2PRE0 PLLQ 3 PLL I2SRDY
MCO2PRE1
MCO2PRE2
MCO2 0
PLLSAIRDYIE PPRE2 1
Res.
LSIRDYC
LSERDYC
HSIRDYC
HSERDYC
PLLRDYC
PLLI2SRDYC
GPIOGRST PLLSAIRDYF
CRYPRST GPIOERST
HASHRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CSSC
DMA2RST PLLSAIRDYC
DMA2DRST
Res.
ETHMACRST
Res.
Res.
Res.
OTGHSRST
Res.
OTGFSRST GPIOHRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. FMCRST DCMIRST
Res. QSPIRST
Res.
Res.
Res.
Res.
TIM13RST Res.
Res.
TIM7RST
TIM14RST Res.
ADCRST
Res.
LPTIM1RST Res.
Res.
Res.
Res.
Res. Res. USART6RST
Res. Res.
Res. Res.
Res. Res.
Res.
Res.
Res.
Res. Res. SDMMC1RST WWDGRST Res.
Res.
SPI1RST
Res.
Res.
Res.
Res.
SPI2RST
SP45RST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res. SYSCFGRST
Res. Res.
Res.
Res.
Res.
SPI3RST
SPDIFRXRST Res.
TIM9RST
Res.
Res.
Res.
UART2RST Res.
Res. Res.
UART3RST Res.
Res. Res. TIM10RST
Res.
UART4RST Res.
Res.
BKPSRAMEN Res. Res. TIM11RST
Res. Res.
Res.
Reserved
Res.
Res.
Res.
Res.
UART5RST Res.
I2C1RST
I2C2RST
I2C3RST
I2C4RST
CAN1RST Res.
CAN2RST Res.
Res.
Res.
Res.
SPI5RST
SPI6RST
SAI1RST
Res.
SAI2RST
Res.
CECRST
PWRRST
DACRST
UART7RST Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
DTCMRAMEN Res. Res.
Res.
Res.
Res.
ETHMACEN
ETHMACTXEN Res. Res. LTDCRST
Res.
Res.
Res.
Res.
Res.
ETHMACRXEN Res. Res.
Res. Res.
Res.
OTGHSEN
ETHMACPTPEN Res. Res.
Res.
Res.
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_AHB1RS
TR
Res.
0x10
Res.
RCC_CIR
MCO2 1
0x0C
Res.
RCC_CFGR
Res.
0x08
Res.
RCC_PLLCFG
R
Res.
0x04
UART8RST Res.
RCC_CR
Res.
0x00
Res. Res.
Register
name
OTGHSULPIEN Res. Res.
5.3.27
Res.
Addr.
offset
Res.
Reset and clock control (RCC)
RM0385
RCC register map
Table 20 gives the register map and reset values.
Table 20. RCC register map and reset values
0x68
Reserved
0x6C
Reserved
0x70
RCC_BDCR
0x74
RCC_CSR
0x78
Reserved
0x7C
Reserved
DocID026670 Rev 6
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
LSION
Res.
Res. Res.
Res. Res.
Res.
Res. Res.
LSIRDY
Res.
Res. Res.
Res. Res.
Res.
Res. Res.
Res.
Res.
Res. Res.
Res. Res.
Res.
RMVF
Res. Res.
Res.
SPI5LPEN
SPI6LPEN
SAI1LPEN
SAI2LPEN
Res.
Res.
Res.
TIM9LPEN
SPI1LPEN
SPI4LPEN
Res. Res. ADC3LPEN
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
LSERDY
LSEON
Res. Res.
TIM1LPEN
TIM8LPEN
Res.
Res.
Res. Res. USART1LPEN
Res. Res. USART6LPEN
Res. Res.
LSEBYP
LSEDRV[1:0]
Res.
Res.
Res. Res.
RTCSEL 0 Res. Res. ADC1LPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SPI2LPEN
SPI3LPEN
Res.
Res.
Res.
Res.
SPDIFRXLPEN Res.
USART2LPEN Res.
USART3LPEN Res.
UART4LPEN Res.
UART5LPEN Res.
I2C1LPEN
I2C2LPEN
I2C3LPEN
I2C4LPEN
CAN1LPEN Res.
CAN2LPEN Res.
CECLPEN
PWRLPEN
DACLPEN
UART7LPEN Res.
Res.
TIM2LPEN
TIM3LPEN
TIM4LPEN
TIM5LPEN
TIM6LPEN
TIM7LPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRYPLPEN
HASHLPEN
RNGLPEN
OTGFSLPEN
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. FMCLPEN DCMILPEN
Res. QSPILPEN
Res.
Res.
Res.
Res.
TIM12LPEN Res.
TIM13LPEN Res.
TIM14LPEN Res.
LPTIM1LPEN Res.
Res.
Res. Res. SDMMC1LPEN WWDGLPEN Res.
Res. Res.
Res. Res.
Res. Res. SYSCFGLPEN
Res. Res.
Res. Res.
Res. Res. TIM10LPEN
Res. Res. TIM11LPEN
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res. LTDCLPEN
Res.
Res.
Res.
Res.
RTCSEL 1 Res. Res. ADC2LPEN
Res.
Res.
Res.
Res.
Res.
RTCEN
BDRST
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res. Res. BORRSTF
Res.
RCC_APB2LP
ENR
Res. Res. PADRSTF
0x64
Res. Res.
RCC_APB1LP
ENR
Res.
0x60
Res. Res. PORRSTF
Reserved
Res. Res.
0x5C
Res. Res.
RCC_AHB3LP
ENR
Res.
0x58
Res.
RCC_AHB2LP
ENR
Res. Res. SFTRSTF
0x54
Res. Res. WDGRSTF
RCC_AHB1LP
ENR
Res. Res.
Res.
Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res.
SPI5EN
SPI6EN
SAI1EN
SAI2EN
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
UART4EN Res. Res.
UART5EN Res. Res.
I2C1EN
I2C2EN
I2C3EN
I2C4EN
CAN1EN Res. Res.
CAN2EN Res. Res.
CECEN
PWREN
DACEN
SPI7EN
GPIOALPEN
GPIOBLPEN
GPIOCLPEN
GPIODLPEN
GPIOELPEN
GPIOFLPEN
GPIOGLPEN
GPIOHLPEN
GPIOILPEN
GPIOJLPEN
GPIOKLPEN
Res.
CRCLPEN
AXILPEN
Res.
FLITFLPEN
SRAM1LPEN
SRAM2LPEN
Res.
TIM9EN
SPI1EN
SPI4EN
Res.
Res.
SPI2EN
SPI3EN
Res. Res.
Res. Res.
Res. Res.
Res. Res.
SPDIFRXEN Res. Res.
Res.
Res.
Res. Res.
Res. Res.
Res. Res.
Res. Res.
TIM1EN
TIM8EN
Res.
Res.
Res. Res. USART1EN
Res. Res. USART6EN
Res. Res.
Res. Res.
Res. Res. ADC1EN
Res. Res. ADC2EN
Res. Res. ADC3EN
Res. Res.
TIM2EN
TIM3EN
TIM4EN
TIM5EN
TIM6EN
TIM7EN
Res. FMCEN
Res. QSPIEN
Res. Res.
Res. Res.
Res. Res.
Res. Res.
TIM12EN Res. Res.
TIM13EN Res. Res.
TIM14EN Res. Res.
LPTIM1EN Res. Res.
Res.
Res. Res. SDMMC1EN WWDGEN Res. Res.
Res. Res.
Res. Res.
Res. Res. SYSCFGEN
Res. Res.
Res. Res.
Res. Res. TIM10EN USART2EN Res. Res.
BKPSRAMLPEN Res. Res. TIM11EN USART3EN Res. Res.
Res.
DTCMLPEN
DMA1LPEN
DMA2LPEN
DMA2DLPEN
Res.
ETHMACLPEN
ETHMACTXLPEN Res. Res. LTDCEN
ETHMACRXLPEN Res. Res.
ETHMACPTPLPEN Res. Res.
OTGHSLPEN
OTGHSULPILPEN Res. Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x50
Res. Res.
Reserved
SPI8EN
0x4C
Res.
Reserved
Res. Res.
0x48
Res.
RCC_
APB2ENR
Res.
0x44
Res.
RCC_
APB1ENR
UART8LPEN Res.
0x40
Res.
Reserved
Res. Res.
0x3C
Res. Res.
RCC_
AHB3ENR
Res.
0x38
Res.
Register
name
Res. Res. WWDGRSTF
Addr.
offset
Res. Res. LPWRRSTF
RM0385
Reset and clock control (RCC)
Table 20. RCC register map and reset values (continued)
193/1671
194
194/1671
DocID026670 Rev 6
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
UART1SEL
Res.
Res.
Res.
PLLSAIDIVQ[4:0]
UART2SEL
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PLLSAIN[8:0]
Res.
PLLI2SN[8:0]
UART3SEL
Res.
Res.
PLLSAIDIVR[1:0] PLLSAIP[1:0] PLLI2SP[1:0]
Res.
Res.
Res.
Res.
Res.
Res.
INCSTEP
UART4SEL
UART5SEL
UART6SEL
UART7SEL
UART8SEL
I2C1SEL
I2C2SEL
Res.
Res.
Res.
SAI1SEL[1:0]
I2C3SEL
Res.
Res.
PLLSAIQ[4:0]
Res.
SAI2SEL[1:0]
TIMPRE
Res.
Res.
Res.
PLLI2SR[2:
PLLI2SQ[3:0]
0]
I2C4SEL
LPTIM1SEL
Res.
Res.
CECSEL
Res.
RCC_DCKCF
GR2
Res.
Res.
0x90
CK48MSEL
RCC_DCKCF
GR1
PLLSAIR[2:0]
Res.
0x8C
Res.
RCC_PLLSAI
CFGR
Res.
0x88
Res.
RCC_PLLI2SC
FGR
SDMMC1SEL
0x84
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCC_SSCGR
SSCGEN
0x80
SPREADSEL
Register
name
Res.
Addr.
offset
Res.
Reset and clock control (RCC)
RM0385
Table 20. RCC register map and reset values (continued)
MODPER
PLLI2SDIVQ[4:0]
RM0385
General-purpose I/Os (GPIO)
6
General-purpose I/Os (GPIO)
6.1
Introduction
Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers
(GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition
all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function
selection registers (GPIOx_AFRH and GPIOx_AFRL).
6.2
6.3
GPIO main features
•
Output states: push-pull or open drain + pull-up/down
•
Output data from output data register (GPIOx_ODR) or peripheral (alternate function
output)
•
Speed selection for each I/O
•
Input states: floating, pull-up/down, analog
•
Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
•
Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR
•
Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations
•
Analog function
•
Alternate function selection registers
•
Fast toggle capable of changing every two clock cycles
•
Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several
peripheral functions
GPIO functional description
Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each
port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in
several modes:
•
Input floating
•
Input pull-up
•
Input-pull-down
•
Analog
•
Output open-drain with pull-up or pull-down capability
•
Output push-pull with pull-up or pull-down capability
•
Alternate function push-pull with pull-up or pull-down capability
•
Alternate function open-drain with pull-up or pull-down capability
Each I/O port bit is freely programmable, however the I/O port registers have to be
accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and
GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR
registers. In this way, there is no risk of an IRQ occurring between the read and the modify
access.
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General-purpose I/Os (GPIO)
RM0385
Figure 16 and Figure 17 shows the basic structures of a standard and a 5 V tolerant I/O port
bit, respectively. Table 21 gives the possible port bit configurations.
Figure 16. Basic structure of an I/O port bit
!NALOG
4OONCHIP
PERIPHERAL
!LTERNATEFUNCTIONINPUT
)NPUTDATAREGISTER
TRIGGER
ONOFF
0ROTECTION
DIODE
0ULL
UP
)NPUTDRIVER
)/PIN
/UTPUTDRIVER
6$$
ONOFF
0ROTECTION
DIODE
0ULL
DOWN
0-/3
633
/UTPUT
CONTROL
633
.-/3
2EADWRITE
&ROMONCHIP
PERIPHERAL
6$$
6$$
/UTPUTDATAREGISTER
"ITSETRESETREGISTERS
2EAD
7RITE
ONOFF
633
!LTERNATEFUNCTIONOUTPUT
0USHPULL
OPENDRAINOR
DISABLED
!NALOG
AI
Figure 17. Basic structure of a five-volt tolerant I/O port bit
!NALOG
4OONCHIP
PERIPHERAL
)NPUTDATAREGISTER
!LTERNATEFUNCTIONINPUT
2EADWRITE
&ROMONCHIP
PERIPHERAL
/UTPUTDATAREGISTER
7RITE
"ITSETRESETREGISTERS
2EAD
ONOFF
6$$
44,3CHMITT
TRIGGER
ONOFF
0ULL
UP
6$$?&4 0ROTECTION
DIODE
)NPUTDRIVER
)/PIN
/UTPUTDRIVER
6$$
ONOFF
0-/3
/UTPUT
CONTROL
0ULL
DOWN
633
0ROTECTION
DIODE
633
.-/3
633
!LTERNATEFUNCTIONOUTPUT
0USHPULL
OPENDRAINOR
DISABLED
!NALOG
AIB
1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD.
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DocID026670 Rev 6
RM0385
General-purpose I/Os (GPIO)
Table 21. Port bit configuration table(1)
MODE(i)
[1:0]
01
10
00
11
OTYPER(i)
OSPEED(i)
[1:0]
PUPD(i)
[1:0]
I/O configuration
0
0
0
GP output
PP
0
0
1
GP output
PP + PU
0
1
0
GP output
PP + PD
1
1
Reserved
0
0
GP output
OD
1
0
1
GP output
OD + PU
1
1
0
GP output
OD + PD
1
1
1
Reserved (GP output OD)
0
0
0
AF
PP
0
0
1
AF
PP + PU
0
1
0
AF
PP + PD
1
1
Reserved
0
0
AF
OD
1
0
1
AF
OD + PU
1
1
0
AF
OD + PD
1
1
1
Reserved
0
SPEED
[1:0]
1
0
SPEED
[1:0]
1
x
x
x
0
0
Input
Floating
x
x
x
0
1
Input
PU
x
x
x
1
0
Input
PD
x
x
x
1
1
Reserved (input floating)
x
x
x
0
0
Input/output
x
x
x
0
1
x
x
x
1
0
x
x
x
1
1
Analog
Reserved
1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate
function.
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General-purpose I/Os (GPIO)
6.3.1
RM0385
General-purpose I/O (GPIO)
During and just after reset, the alternate functions are not active and most of the I/O ports
are configured in input floating mode.
The debug pins are in AF pull-up/pull-down after reset:
•
PA15: JTDI in pull-up
•
PA14: JTCK/SWCLK in pull-down
•
PA13: JTMS/SWDAT in pull-up
•
PB4: NJTRST in pull-up
•
PB3: JTDO in floating state
When the pin is configured as output, the value written to the output data register
(GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull
mode or open-drain mode (only the low level is driven, high level is HI-Z).
The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB
clock cycle.
All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or
not depending on the value in the GPIOx_PUPDR register.
6.3.2
I/O pin alternate function multiplexer and mapping
The device I/O pins are connected to on-board peripherals/modules through a multiplexer
that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In
this way, there can be no conflict between peripherals available on the same I/O pin.
Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that
can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to
15) registers:
•
After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are
configured in alternate function mode through GPIOx_MODER register.
•
The specific alternate function assignments for each pin are detailed in the device
datasheet.
•
Cortex-M7 with FPU EVENTOUT is mapped on AF15
In addition to this flexible I/O multiplexing architecture, each peripheral has alternate
functions mapped onto different I/O pins to optimize the number of peripherals available in
smaller packages.
To use an I/O in a given configuration, the user has to proceed as follows:
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•
Debug function: after each device reset these pins are assigned as alternate function
pins immediately usable by the debugger host
•
System function: MCOx pins have to be configured in alternate function mode.
•
GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER
register.
•
Peripheral alternate function:
–
Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH
register.
–
Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER,
GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively.
DocID026670 Rev 6
RM0385
General-purpose I/Os (GPIO)
–
•
•
Configure the desired I/O as an alternate function in the GPIOx_MODER register.
Additional functions:
–
For the ADC and DAC, configure the desired I/O in analog mode in the
GPIOx_MODER register and configure the required function in the ADC and DAC
registers.
–
For the additional functions likeRTC_OUT, RTC_TS, RTC_TAMPx, WKUPx and
oscillators, configure the required function in the related RTC, PWR and RCC
registers. These functions have priority over the configuration in the standard
GPIO registers. For details about I/O control by the RTC, refer to Section 29.3:
RTC functional description on page 874.
EVENTOUT
–
Configure the I/O pin used to output the core EVENTOUT signal by connecting it
to AF15.
Please refer to the “Alternate function mapping” table in the device datasheet for the
detailed mapping of the alternate function I/O pins.
6.3.3
I/O port control registers
Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The
GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The
GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction.
6.3.4
I/O port data registers
Each GPIO has two 16-bit memory-mapped data registers: input and output data registers
(GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write
accessible. The data input through the I/O are stored into the input data register
(GPIOx_IDR), a read-only register.
See Section 6.4.5: GPIO port input data register (GPIOx_IDR) (x = A..K) and Section 6.4.6:
GPIO port output data register (GPIOx_ODR) (x = A..K) for the register descriptions.
6.3.5
I/O data bitwise handling
The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to
set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset
register has twice the size of GPIOx_ODR.
To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i).
When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i)
resets the ODR(i) corresponding bit.
Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in
GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set
action takes priority.
Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a
“one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always
be accessed directly. The GPIOx_BSRR register provides a way of performing atomic
bitwise handling.
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General-purpose I/Os (GPIO)
RM0385
There is no need for the software to disable interrupts when programming the GPIOx_ODR
at bit level: it is possible to modify one or more bits in a single atomic AHB write access.
6.3.6
GPIO locking mechanism
It is possible to freeze the GPIO control registers by applying a specific write sequence to
the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER,
GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When
the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used
to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must
be the same). When the LOCK sequence has been applied to a port bit, the value of the port
bit can no longer be modified until the next MCU reset or peripheral reset. Each
GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER,
GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
The LOCK sequence (refer to Section 6.4.8: GPIO port configuration lock register
(GPIOx_LCKR) (x = A..K)) can only be performed using a word (32-bit long) access to the
GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same
time as the [15:0] bits.
For more details please refer to LCKR register description in Section 6.4.8: GPIO port
configuration lock register (GPIOx_LCKR) (x = A..K).
6.3.7
I/O alternate function input/output
Two registers are provided to select one of the alternate function inputs/outputs available for
each I/O. With these registers, the user can connect an alternate function to some other pin
as required by the application.
This means that a number of possible peripheral functions are multiplexed on each GPIO
using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can
thus select any one of the possible functions for each I/O. The AF selection signal being
common to the alternate function input and alternate function output, a single channel is
selected for the alternate function input/output of a given I/O.
To know which functions are multiplexed on each GPIO pin, refer to the device datasheet.
6.3.8
External interrupt/wakeup lines
All ports have external interrupt capability. To use external interrupt lines, the port must be
configured in input mode. Refer to Section 13.2: Extended interrupts and events controller
(EXTI) and to Section 13.2.3: Wakeup event management.
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RM0385
6.3.9
General-purpose I/Os (GPIO)
Input configuration
When the I/O port is programmed as input:
•
The output buffer is disabled
•
The Schmitt trigger input is activated
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register provides the I/O state
Figure 18 shows the input configuration of the I/O port bit.
)NPUTDATAREGISTER
Figure 18. Input floating/pull up/pull down configurations
2EADWRITE
/UTPUTDATAREGISTER
7RITE
"ITSETRESETREGISTERS
2EAD
ON
44,3CHMITT
TRIGGER
6$$ 6$$
ONOFF
PULL
UP
INPUTDRIVER
PROTECTION
DIODE
)/PIN
ONOFF
OUTPUTDRIVER
PULL
DOWN
633
PROTECTION
DIODE
633
AIB
6.3.10
Output configuration
When the I/O port is programmed as output:
•
The output buffer is enabled:
–
Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1”
in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
–
Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in
the Output register activates the P-MOS
•
The Schmitt trigger input is activated
•
The pull-up and pull-down resistors are activated depending on the value in the
GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
•
A read access to the output data register gets the last written value
Figure 19 shows the output configuration of the I/O port bit.
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RM0385
)NPUTDATAREGISTER
Figure 19. Output configuration
7RITE
2EADWRITE
ON
6$$
6$$
44,3CHMITT
TRIGGER
ONOFF
)NPUTDRIVER
/UTPUTDATAREGISTER
"ITSETRESETREGISTERS
2EAD
PROTECTION
DIODE
PULL
UP
/UTPUTDRIVER
6$$
)/PIN
ONOFF
0-/3
/UTPUT
CONTROL
PROTECTION
DIODE
PULL
DOWN
633
633
.-/3
0USHPULLOR
633
/PENDRAIN
AIB
6.3.11
Alternate function configuration
When the I/O port is programmed as alternate function:
•
The output buffer can be configured in open-drain or push-pull mode
•
The output buffer is driven by the signals coming from the peripheral (transmitter
enable and data)
•
The Schmitt trigger input is activated
•
The weak pull-up and pull-down resistors are activated or not depending on the value
in the GPIOx_PUPDR register
•
The data present on the I/O pin are sampled into the input data register every AHB
clock cycle
•
A read access to the input data register gets the I/O state
Figure 20 shows the Alternate function configuration of the I/O port bit.
Figure 20. Alternate function configuration
!LTERNATEFUNCTIONINPUT
2EADWRITE
&ROMONCHIP
PERIPHERAL
6$$ 6$$
44,3CHMITT
TRIGGER
ONOFF
PROTECTION
DIODE
0ULL
UP
)NPUTDRIVER
/UTPUTDATAREGISTER
"ITSETRESETREGISTERS
2EAD
7RITE
ON
)NPUTDATAREGISTER
4OONCHIP
PERIPHERAL
)/PIN
/UTPUTDRIVER
ONOFF
6$$
0-/3
/UTPUT
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PROTECTION
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DOWN
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OPENDRAIN
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6.3.12
General-purpose I/Os (GPIO)
Analog configuration
When the I/O port is programmed as analog configuration:
•
The output buffer is disabled
•
The Schmitt trigger input is deactivated, providing zero consumption for every analog
value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
•
The weak pull-up and pull-down resistors are disabled by hardware
•
Read access to the input data register gets the value “0”
Figure 21 shows the high-impedance, analog-input configuration of the I/O port bit.
Figure 21. High impedance-analog configuration
)NPUTDATAREGISTER
!NALOG
4OONCHIP
PERIPHERAL
2EADWRITE
&ROMONCHIP
PERIPHERAL
6.3.13
/UTPUTDATAREGISTER
7RITE
"ITSETRESETREGISTERS
2EAD
OFF
6$$
44,3CHMITT
TRIGGER
PROTECTION
DIODE
)NPUTDRIVER
)/PIN
PROTECTION
DIODE
633
!NALOG
AI
Using the HSE or LSE oscillator pins as GPIOs
When the HSE or LSE oscillator is switched OFF (default state after reset), the related
oscillator pins can be used as normal GPIOs.
When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the
RCC_CSR register) the oscillator takes control of its associated pins and the GPIO
configuration of these pins has no effect.
When the oscillator is configured in a user external clock mode, only the OSC_IN or
OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be
used as normal GPIO.
6.3.14
Using the GPIO pins in the backup supply domain
The PC13/PC14/PC15/PI8 GPIO functionality is lost when the core supply domain is
powered off (when the device enters Standby mode). In this case, if their GPIO configuration
is not bypassed by the RTC configuration, these pins are set in an analog input mode.
Section 29.3: RTC functional description on page 874.
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6.4
RM0385
GPIO registers
This section gives a detailed description of the GPIO registers.
For a summary of register bits, register address offsets and reset values, refer to Table 22.
The peripheral registers can be written in word, half word or byte mode.
6.4.1
GPIO port mode register (GPIOx_MODER) (x =A..K)
Address offset:0x00
Reset values:
31
30
•
0xA800 0000 for port A
•
0x0000 0280 for port B
•
0x0000 0000 for other ports
29
MODER15[1:0]
28
MODER14[1:0]
27
26
MODER13[1:0]
25
24
MODER12[1:0]
23
22
MODER11[1:0]
21
20
MODER10[1:0]
19
18
MODER9[1:0]
17
16
MODER8[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODER7[1:0]
rw
rw
MODER6[1:0]
rw
rw
MODER5[1:0]
rw
rw
MODER4[1:0]
rw
rw
MODER3[1:0]
rw
rw
MODER2[1:0]
rw
rw
MODER1[1:0]
rw
rw
MODER0[1:0]
rw
rw
Bits 2y+1:2y MODERy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O mode.
00: Input mode (reset state)
01: General purpose output mode
10: Alternate function mode
11: Analog mode
6.4.2
GPIO port output type register (GPIOx_OTYPER) (x = A..K)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OT15
OT14
OT13
OT12
OT11
OT10
OT9
OT8
OT7
OT6
OT5
OT4
OT3
OT2
OT1
OT0
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 OTy: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output type.
0: Output push-pull (reset state)
1: Output open-drain
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General-purpose I/Os (GPIO)
6.4.3
GPIO port output speed register (GPIOx_OSPEEDR)
(x = A..K)
Address offset: 0x08
Reset value:
31
•
0x0C00 0000 for port A
•
0x0000 00C0 for port B
•
0x0000 0000 for other ports
30
29
OSPEEDR15
[1:0]
28
27
OSPEEDR14
[1:0]
26
25
OSPEEDR13
[1:0]
24
OSPEEDR12
[1:0]
23
22
OSPEEDR11
[1:0]
21
20
OSPEEDR10
[1:0]
19
18
17
16
OSPEEDR9
[1:0]
OSPEEDR8
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OSPEEDR7
[1:0]
OSPEEDR6
[1:0]
OSPEEDR5
[1:0]
OSPEEDR4
[1:0]
OSPEEDR3
[1:0]
OSPEEDR2
[1:0]
OSPEEDR1
[1:0]
OSPEEDR0
[1:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 2y+1:2y OSPEEDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O output speed.
00: Low speed
01: Medium speed
10: High speed
11: Very high speed
Note: Refer to the product datasheets for the values of OSPEEDRy bits versus VDD range
and external load.
6.4.4
GPIO port pull-up/pull-down register (GPIOx_PUPDR)
(x = A..K)
Address offset: 0x0C
Reset values:
31
30
PUPDR15[1:0]
•
0x6400 0000 for port A
•
0x0000 0100 for port B
•
0x0000 0000 for other ports
29
28
PUPDR14[1:0]
27
26
PUPDR13[1:0]
25
24
PUPDR12[1:0]
23
22
PUPDR11[1:0]
21
20
PUPDR10[1:0]
19
18
PUPDR9[1:0]
17
16
PUPDR8[1:0]
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PUPDR7[1:0]
rw
rw
PUPDR6[1:0]
rw
rw
PUPDR5[1:0]
rw
rw
PUPDR4[1:0]
rw
rw
PUPDR3[1:0]
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PUPDR1[1:0]
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Bits 2y+1:2y PUPDRy[1:0]: Port x configuration bits (y = 0..15)
These bits are written by software to configure the I/O pull-up or pull-down
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
6.4.5
GPIO port input data register (GPIOx_IDR) (x = A..K)
Address offset: 0x10
Reset value: 0x0000 XXXX (where X means undefined)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDR15
IDR14
IDR13
IDR12
IDR11
IDR10
IDR9
IDR8
IDR7
IDR6
IDR5
IDR4
IDR3
IDR2
IDR1
IDR0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 IDRy: Port input data bit (y = 0..15)
These bits are read-only. They contain the input value of the corresponding I/O port.
6.4.6
GPIO port output data register (GPIOx_ODR) (x = A..K)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
ODR15 ODR14 ODR13 ODR12 ODR11 ODR10
rw
rw
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rw
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rw
9
8
7
6
5
4
3
2
1
0
ODR9
ODR8
ODR7
ODR6
ODR5
ODR4
ODR3
ODR2
ODR1
ODR0
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rw
rw
rw
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Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 ODRy: Port output data bit (y = 0..15)
These bits can be read and written by software.
Note: For atomic bit set/reset, the ODR bits can be individually set and/or reset by writing to
the GPIOx_BSRR or GPIOx_BRR registers (x = A..F).
6.4.7
GPIO port bit set/reset register (GPIOx_BSRR) (x = A..K)
Address offset: 0x18
Reset value: 0x0000 0000
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General-purpose I/Os (GPIO)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
BR15
BR14
BR13
BR12
BR11
BR10
BR9
BR8
BR7
BR6
BR5
BR4
BR3
BR2
BR1
BR0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BS15
BS14
BS13
BS12
BS11
BS10
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
Bits 31:16 BRy: Port x reset bit y (y = 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Resets the corresponding ODRx bit
Note: If both BSx and BRx are set, BSx has priority.
Bits 15:0 BSy: Port x set bit y (y= 0..15)
These bits are write-only. A read to these bits returns the value 0x0000.
0: No action on the corresponding ODRx bit
1: Sets the corresponding ODRx bit
6.4.8
GPIO port configuration lock register (GPIOx_LCKR)
(x = A..K)
This register is used to lock the configuration of the port bits when a correct write sequence
is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the
GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the
LOCK sequence has been applied on a port bit, the value of this port bit can no longer be
modified until the next MCU reset or peripheral reset.
Note:
A specific write sequence is used to write to the GPIOx_LCKR register. Only word access
(32-bit long) is allowed during this locking sequence.
Each lock bit freezes a specific configuration register (control and alternate function
registers).
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
LCKK
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LCK15
LCK14
LCK13
LCK12
LCK11
LCK10
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
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Bits 31:17 Reserved, must be kept at reset value.
Bit 16 LCKK: Lock key
This bit can be read any time. It can only be modified using the lock key write sequence.
0: Port configuration lock key not active
1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU
reset or peripheral reset.
LOCK key write sequence:
WR LCKR[16] = ‘1’ + LCKR[15:0]
WR LCKR[16] = ‘0’ + LCKR[15:0]
WR LCKR[16] = ‘1’ + LCKR[15:0]
RD LCKR
RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active)
Note: During the LOCK key write sequence, the value of LCK[15:0] must not change.
Any error in the lock sequence aborts the lock.
After the first lock sequence on any bit of the port, any read access on the LCKK bit will
return ‘1’ until the next MCU reset or peripheral reset.
Bits 15:0 LCKy: Port x lock bit y (y= 0..15)
These bits are read/write but can only be written when the LCKK bit is ‘0.
0: Port configuration not locked
1: Port configuration locked
6.4.9
GPIO alternate function low register (GPIOx_AFRL)
(x = A..K)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
AFR7[3:0]
26
25
24
23
22
AFR6[3:0]
21
20
19
AFR5[3:0]
18
17
16
AFR4[3:0]
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFR3[3:0]
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AFR2[3:0]
rw
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AFR1[3:0]
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AFR0[3:0]
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Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 0..7)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
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1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
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RM0385
General-purpose I/Os (GPIO)
6.4.10
GPIO alternate function high register (GPIOx_AFRH)
(x = A..J)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
AFR15[3:0]
26
25
24
23
22
AFR14[3:0]
21
20
19
AFR13[3:0]
18
17
16
AFR12[3:0]
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rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AFR11[3:0]
rw
rw
rw
AFR10[3:0]
rw
rw
rw
rw
AFR9[3:0]
rw
rw
rw
rw
AFR8[3:0]
rw
rw
rw
rw
rw
Bits 31:0 AFRy[3:0]: Alternate function selection for port x pin y (y = 8..15)
These bits are written by software to configure alternate function I/Os
AFSELy selection:
0000: AF0
0001: AF1
0010: AF2
0011: AF3
0100: AF4
0101: AF5
0110: AF6
0111: AF7
1000: AF8
1001: AF9
1010: AF10
1011: AF11
1100: AF12
1101: AF13
1110: AF14
1111: AF15
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0x08
Reset value
GPIOB_OSPEEDR
Reset value
GPIOx_OSPEEDR
(where x = C..K)
Reset value
0x0C
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GPIOA_PUPDR
Reset value
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOx_OTYPER
(where x = A..K)
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DocID026670 Rev 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OT1
OT0
MODER0[1:0]
MODER0[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
OSPEEDR0[1:0]
MODER1[1:0]
0
OSPEEDR0[1:0]
MODER1[1:0]
0
OSPEEDR0[1:0]
OT2
0
PUPDR0[1:0]
OT3
0
OSPEEDR1[1:0]
MODER2[1:0]
0
OSPEEDR1[1:0]
MODER2[1:0]
0
OSPEEDR1[1:0]
OT4
0
PUPDR1[1:0]
OT5
1
OSPEEDR2[1:0]
MODER3[1:0]
0
OSPEEDR2[1:0]
MODER3[1:0]
0
OSPEEDR2[1:0]
OT6
0
PUPDR2[1:0]
OT7
1
OSPEEDR3[1:0]
MODER4[1:0]
0
OSPEEDR3[1:0]
MODER4[1:0]
0
OSPEEDR3[1:0]
OT8
0
PUPDR3[1:0]
OT9
0
OSPEEDR4[1:0]
0
OSPEEDR4[1:0]
MODER5[1:0]
0
OSPEEDR4[1:0]
MODER5[1:0]
0
PUPDR4[1:0]
OT11
OT10
0
OSPEEDR5[1:0]
MODER6[1:0]
0
OSPEEDR5[1:0]
MODER6[1:0]
0
OSPEEDR5[1:0]
OT12
0
PUPDR5[1:0]
OT13
0
OSPEEDR6[1:0]
0
OSPEEDR6[1:0]
MODER7[1:0]
0
OSPEEDR6[1:0]
MODER7[1:0]
0
PUPDR6[1:0]
OT14
0
OT15
0
OSPEEDR7[1:0]
MODER8[1:0]
0
OSPEEDR7[1:0]
MODER8[1:0]
0
OSPEEDR7[1:0]
0
Res.
0
PUPDR7[1:0]
0
Res.
0
OSPEEDR8[1:0]
MODER9[1:0]
0
OSPEEDR8[1:0]
MODER9[1:0]
0
OSPEEDR8[1:0]
0
Res.
0
PUPDR8[1:0]
0
Res.
0
OSPEEDR9[1:0]
MODER10[1:0]
0
OSPEEDR9[1:0]
MODER10[1:0]
0
OSPEEDR9[1:0]
0
Res.
0
PUPDR9[1:0]
0
Res.
0
OSPEEDR10[1:0]
MODER11[1:0]
0
OSPEEDR10[1:0]
MODER11[1:0]
0
OSPEEDR10[1:0]
0
Res.
0
PUPDR10[1:0]
0
Res.
0
OSPEEDR11[1:0]
MODER12[1:0]
0
OSPEEDR11[1:0]
MODER12[1:0]
0
OSPEEDR11[1:0]
0
Res.
0
PUPDR11[1:0]
0
Res.
0
OSPEEDR12[1:0]
MODER13[1:0]
0
OSPEEDR12[1:0]
MODER13[1:0]
1
OSPEEDR12[1:0]
0
Res.
0
PUPDR12[1:0]
0
Res.
MODER14[1:0]
0
OSPEEDR13[1:0]
MODER14[1:0]
0
OSPEEDR13[1:0]
0
Res.
MODER15[1:0]
1
OSPEEDR13[1:0]
GPIOA_OSPEEDR
0
PUPDR13[1:0]
0
Res.
GPIOx_MODER
(where x = C..K)
OSPEEDR14[1:0]
0x00
0
OSPEEDR14[1:0]
Reset value
1
OSPEEDR14[1:0]
0x08
GPIOB_MODER
MODER15[1:0]
Reset value
PUPDR14[1:0]
0x08
0
Res.
0x04
Reset value
Res.
0x00
MODER0[1:0]
MODER1[1:0]
MODER2[1:0]
MODER3[1:0]
MODER4[1:0]
MODER5[1:0]
MODER6[1:0]
MODER7[1:0]
MODER8[1:0]
MODER9[1:0]
MODER10[1:0]
MODER11[1:0]
MODER12[1:0]
MODER13[1:0]
MODER14[1:0]
MODER15[1:0]
GPIOA_MODER
OSPEEDR15[1:0]
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
OSPEEDR15[1:0]
Offset
OSPEEDR15[1:0]
6.4.11
PUPDR15[1:0]
General-purpose I/Os (GPIO)
RM0385
GPIO register map
The following table gives the GPIO register map and reset values.
Table 22. GPIO register map and reset values
0
0
0
0
0
0
0
0
0
0
RM0385
General-purpose I/Os (GPIO)
PUPDR0[1:0]
0
0
0
0
0
0
BS9
BS8
BS7
BS6
BS5
BS4
BS3
BS2
BS1
BS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LCK9
LCK8
LCK7
LCK6
LCK5
LCK4
LCK3
LCK2
LCK1
LCK0
ODR0
BS11
BS10
0
LCK11
0
LCK10
0
BS12
0
BS13
0
LCK12
0
LCK13
0
BS14
0
BS15
0
LCK14
0
LCK15
0
BR0
0
BR1
0
Res.
0
LCKK
0
BR2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AFR4[3:0]
0
x
ODR1
Res.
0
x
ODR2
Res.
0
x
ODR3
Res.
0
x
ODR4
Res.
0
x
ODR5
Res.
0
x
ODR6
Res.
0
x
ODR7
Res.
0
x
ODR8
Res.
0
x
ODR9
Res.
0
x
ODR11
Res.
Reset value
0
x
ODR10
Res.
Reset value
AFR5[3:0]
x
ODR12
Res.
0x24
GPIOx_AFRH
(where x = A..J)
AFR6[3:0]
x
0
Reset value
AFR7[3:0]
x
ODR13
Res.
0x20
GPIOx_AFRL
(where x = A..K)
x
ODR14
0x1C
Reset value
x
ODR15
0
Res.
0
Res.
BR3
0
Res.
BR4
0
Res.
BR5
0
Res.
BR6
0
Res.
BR7
0
Res.
BR8
0
Res.
BR9
0
Res.
BR11
BR10
0
Res.
BR12
0
Res.
BR13
0
Res.
BR14
0
Res.
BR15
Reset value
GPIOx_LCKR
(where x = A..K)
Res.
0x18
GPIOx_BSRR
(where x = A..I/J/K)
Res.
GPIOx_ODR
(where x = A..K)
Res.
0x14
Res.
Reset value
IDR0
0
IDR1
0
Res.
PUPDR1[1:0]
0
IDR2
0
IDR3
1
Res.
PUPDR2[1:0]
0
IDR4
0
IDR5
0
Res.
PUPDR3[1:0]
0
IDR6
0
IDR7
0
Res.
PUPDR4[1:0]
0
IDR8
0
IDR9
0
Res.
PUPDR5[1:0]
0
IDR11
0
IDR10
0
Res.
PUPDR6[1:0]
0
IDR12
0
IDR13
0
Res.
PUPDR7[1:0]
0
IDR14
0
IDR15
0
Res.
PUPDR8[1:0]
0
Res.
PUPDR9[1:0]
PUPDR10[1:0]
0
Res.
PUPDR11[1:0]
PUPDR12[1:0]
0
Res.
PUPDR13[1:0]
0
Res.
PUPDR14[1:0]
0
Res.
PUPDR15[1:0]
Reset value
GPIOx_IDR
(where x = A..I/J/K)
Res.
0x10
GPIOB_PUPDR
Res.
0x0C
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 22. GPIO register map and reset values (continued)
0
0
0
AFR3[3:0]
0
0
0
0
AFR2[3:0]
0
0
0
0
AFR15[3:0]
AFR14[3:0]
AFR13[3:0]
AFR12[3:0]
AFR11[3:0]
AFR10[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AFR1[3:0]
0
0
0
0
AFR9[3:0]
0
0
0
0
AFR0[3:0]
0
0
0
0
AFR8[3:0]
0
0
0
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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System configuration controller (SYSCFG)
7
RM0385
System configuration controller (SYSCFG)
The system configuration controller is mainly used to:
7.1
•
Remap the memory areas
•
Select the Ethernet PHY interface
•
Manage the external interrupt line connection to the GPIOs.
I/O compensation cell
By default the I/O compensation cell is not used. However when the I/O output buffer speed
is configured in 50 MHz or 100 MHz mode, it is recommended to use the compensation cell
for slew rate control on I/O tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power
supply.
When the compensation cell is enabled, a READY flag is set to indicate that the
compensation cell is ready and can be used. The I/O compensation cell can be used only
when the supply voltage ranges from 2.4 to 3.6 V.
7.2
SYSCFG registers
7.2.1
SYSCFG memory remap register (SYSCFG_MEMRMP)
This register is used for specific configurations on memory mapping:
•
1bit is used to indicate which option bytes BOOT_ADD0 or BOOT_ADD1 defines the
boot memory base address.
•
Other bits are used to swap FMC SDRAM Banks with FMC NOR/PSRAM bank
Address offset: 0x00
Reset value: 0x0000 0000
)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MEM_
BOOT
SWP_FMC[1:0]
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RM0385
System configuration controller (SYSCFG)
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:10 SWP_FMC[1:0]: FMC memory mapping swap
Set and cleared by software. These bits are used to swap the FMC SDRAM
banks and FMC NOR/PSRAM in order to enable the code execution from
SDRAM Banks without modifying the default MPU attribute
00: No FMC memory mapping swapping
SDRAM bank1 and Bank2 are mapped at 0xC000 0000 and 0xD000 0000
respectively (default mapping)
NOR/RAM is accessible @ 0x60000000 (default mapping)
01: NOR/RAM and SDRAM memory mapping swapped,
SDRAM bank1 and bank2 are mapped at 0x6000 0000 and 0x7000 0000,
respectively
NOR/PSRAM bank is mapped at 0xC000 0000
10: Reserved
11: Reserved
Bits 9:1 Reserved, must be kept at reset value.
Bits 0 MEM_BOOT: Memory boot mapping
This bit indicates which option bytes BOOT_ADD0 or BOOT_ADD1 defines the
boot memory base address.
0: Boot memory base address is defined by BOOT_ADD0 option byte
(Factory Reset value: TCM-FLASH mapped at 0x00200000).
1: Boot memory base address is defined by BOOT_ADD1 option byte
(Factory Reset value: System memory mapped at 0x001 0000).
Note: Refer to section 2.3: Memory map for details about the boot memory base
address selection.
7.2.2
SYSCFG peripheral mode configuration register (SYSCFG_PMC)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MII_RMII
_SEL
Res.
Res.
Res.
Res.
18
17
16
ADCxDC2
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rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 MII_RMII_SEL: Ethernet PHY interface selection
Set and Cleared by software.These bits control the PHY interface for the
Ethernet MAC.
0: MII interface is selected
1: RMII PHY interface is selected
Note: This configuration must be done while the MAC is under reset and before
enabling the MAC clocks.
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System configuration controller (SYSCFG)
RM0385
Bits 22:19 Reserved, must be kept at reset value.
Bits 18:16 ADCxDC2:
0: No effect.
1: Refer to AN4073 on how to use this bit.
Note: These bits can be set only if the following conditions are met:
- ADC clock higher or equal to 30 MHz.
- Only one ADCxDC2 bit must be selected if ADC conversions do not start
at the same time and the sampling times differ.
- These bits must not be set when the ADCDC1 bit is set in PWR_CR
register.
Bits 15:0 Reserved, must be kept at reset value.
7.2.3
SYSCFG external interrupt configuration register 1
(SYSCFG_EXTICR1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXTI3[3:0]
rw
rw
rw
EXTI2[3:0]
rw
rw
rw
EXTI1[3:0]
rw
rw
rw
rw
rw
EXTI0[3:0]
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001:PJ[x] pin
1010:PK[x] pin
7.2.4
SYSCFG external interrupt configuration register 2
(SYSCFG_EXTICR2)
Address offset: 0x0C
Reset value: 0x0000 0000
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System configuration controller (SYSCFG)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXTI7[3:0]
rw
rw
rw
EXTI6[3:0]
rw
rw
rw
EXTI5[3:0]
rw
rw
rw
rw
rw
EXTI4[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7)
These bits are written by software to select the source input for the EXTIx
external interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001:PJ[x] pin
1010:PK[x] pin
7.2.5
SYSCFG external interrupt configuration register 3
(SYSCFG_EXTICR3)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EXTI11[3:0]
rw
rw
rw
EXTI10[3:0]
rw
rw
rw
rw
EXTI9[3:0]
rw
rw
rw
rw
EXTI8[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1000: PI[x] pin
1001:PJ[x] pin
1010:PK[x] pin
Note: PK[11:8] are not used
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System configuration controller (SYSCFG)
7.2.6
RM0385
SYSCFG external interrupt configuration register 4
(SYSCFG_EXTICR4)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
EXTI15[3:0]
rw
rw
rw
EXTI14[3:0]
rw
rw
rw
rw
EXTI13[3:0]
rw
rw
rw
rw
EXTI12[3:0]
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15)
These bits are written by software to select the source input for the EXTIx external
interrupt.
0000: PA[x] pin
0001: PB[x] pin
0010: PC[x] pin
0011: PD[x] pin
0100: PE[x] pin
0101: PF[x] pin
0110: PG[x] pin
0111: PH[x] pin
1001:PJ[x] pin
1010:PK[x] pin
Note: PK[15:12] are not used
7.2.7
Compensation cell control register (SYSCFG_CMPCR)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
READY
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CMP_PD
r
Bits 31:9 Reserved, must be kept at reset value.
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System configuration controller (SYSCFG)
Bit 8 READY: Compensation cell ready flag
0: I/O compensation cell not ready
1: O compensation cell ready
Bits 7:2 Reserved, must be kept at reset value.
Bit 0 CMP_PD: Compensation cell power-down
0: I/O compensation cell power-down mode
1: I/O compensation cell enabled
7.2.8
SYSCFG register maps
The following table gives the SYSCFG register map and the reset values.
0
0
EXTI2[3:0]
0
0
0
0
EXTI6[3:0]
0
0
0
0
EXTI11[3:0]
EXTI10[3:0]
0
0
Res.
MEM_BOOT
Res.
Res.
Res.
Res.
Res.
0
0
EXTI9[3:0]
Res.
Res.
Res.
0
0
0
EXTI8[3:0]
EXTI15[3:0]
EXTI14[3:0]
EXTI13[3:0]
EXTI12[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CMP_PD
0
Res.
0
Res.
0
Res.
0
Res.
0
EXTI4[3:0]
0
Res.
0
0
Res.
0
0
READY
0
Res.
Res.
Res.
Res.
Res.
0
0
Res.
0
EXTI5[3:0]
0
EXTI0[3:0]
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
EXTI1[3:0]
0
Res.
0
Res.
Res.
Res.
Res.
Res.
SWP_FMC[1:0]
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_CMPCR
Res.
0x20
Res.
Reset value
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR4
Res.
0x14
Res.
Reset value
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR3
Res.
0x10
0
EXTI7[3:0]
0
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR2
Res.
0x0C
EXTI3[3:0]
0
Res.
Reset value
Res.
ADC1DC2
0
Res.
ADC2DC2
0
Res.
ADC3DC2
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_EXTICR1
Res.
0x08
0
Res.
Reset value
MII_RMII_SEL
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_PMC
Res.
0x04
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SYSCFG_
MEMRMP
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Res.
Register
Res.
Offset
Res.
Table 23. SYSCFG register map and reset values
Reset value
0
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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Direct memory access controller (DMA)
RM0385
8
Direct memory access controller (DMA)
8.1
DMA introduction
Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory and between memory and memory. Data can be quickly moved by
DMA without any CPU action. This keeps CPU resources free for other operations.
The DMA controller combines a powerful dual AHB master bus architecture with
independent FIFO to optimize the bandwidth of the system, based on a complex bus matrix
architecture.
The two DMA controllers have 16 streams in total (8 for each controller), each dedicated to
managing memory access requests from one or more peripherals. Each stream can have
up to 8 channels (requests) in total. And each has an arbiter for handling the priority
between DMA requests.
8.2
DMA main features
The main DMA features are:
•
Dual AHB master bus architecture, one dedicated to memory accesses and one
dedicated to peripheral accesses
•
AHB slave programming interface supporting only 32-bit accesses
•
8 streams for each DMA controller, up to 8 channels (requests) per stream
•
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream, that can be
used in FIFO mode or direct mode:
–
FIFO mode: with threshold level software selectable between 1/4, 1/2 or 3/4 of the
FIFO size
–
Direct mode
Each DMA request immediately initiates a transfer from/to the memory. When it is
configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads only one data from the memory to the internal
FIFO to ensure an immediate data transfer as soon as a DMA request is triggered
by a peripheral.
•
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Each stream can be configured by hardware to be:
–
a regular channel that supports peripheral-to-memory, memory-to-peripheral and
memory-to-memory transfers
–
a double buffer channel that also supports double buffering on the memory side
•
Each of the 8 streams are connected to dedicated hardware DMA channels (requests)
•
Priorities between DMA stream requests are software-programmable (4 levels
consisting of very high, high, medium, low) or hardware in case of equality (request 0
has priority over request 1, etc.)
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Direct memory access controller (DMA)
•
Each stream also supports software trigger for memory-to-memory transfers (only
available for the DMA2 controller)
•
Each stream request can be selected via among up to 8 possible channel requests.
This selection is software-configurable and allows several peripherals to initiate DMA
requests
•
The number of data items to be transferred can be managed either by the DMA
controller or by the peripheral:
–
DMA flow controller: the number of data items to be transferred is softwareprogrammable from 1 to 65535
–
Peripheral flow controller: the number of data items to be transferred is unknown
and controlled by the source or the destination peripheral that signals the end of
the transfer by hardware
•
Independent source and destination transfer width (byte, half-word, word): when the
data widths of the source and destination are not equal, the DMA automatically
packs/unpacks the necessary transfers to optimize the bandwidth. This feature is only
available in FIFO mode
•
Incrementing or non-incrementing addressing for source and destination
•
Supports incremental burst transfers of 4, 8 or 16 beats. The size of the burst is
software-configurable, usually equal to half the FIFO size of the peripheral
•
Each stream supports circular buffer management
•
5 event flags (DMA Half Transfer, DMA Transfer complete, DMA Transfer Error, DMA
FIFO Error, Direct Mode Error) logically ORed together in a single interrupt request for
each stream
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8.3
DMA functional description
8.3.1
DMA block diagram
Figure 22 shows the block diagram of a DMA.
Figure 22. DMA block diagram
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8.3.2
DMA overview
The DMA controller performs direct memory transfer: as an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
It can carry out the following transactions:
•
peripheral-to-memory
•
memory-to-peripheral
•
memory-to-memory
The DMA controller provides two AHB master ports: the AHB memory port, intended to be
connected to memories and the AHB peripheral port, intended to be connected to
peripherals. However, to allow memory-to-memory transfers, the AHB peripheral port must
also have access to the memories.
The AHB slave port is used to program the DMA controller (it supports only 32-bit
accesses).
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Note:
Direct memory access controller (DMA)
The DMA1 controller AHB peripheral port is not connected to the bus matrix like in the case
of the DMA2 controller, thus only DMA2 streams are able to perform memory-to-memory
transfers.
See Figure 1 for the implementation of the system of two DMA controllers.
8.3.3
DMA transactions
A DMA transaction consists of a sequence of a given number of data transfers. The number
of data items to be transferred and their width (8-bit, 16-bit or 32-bit) are softwareprogrammable.
Each DMA transfer consists of three operations:
•
A loading from the peripheral data register or a location in memory, addressed through
the DMA_SxPAR or DMA_SxM0AR register
•
A storage of the data loaded to the peripheral data register or a location in memory
addressed through the DMA_SxPAR or DMA_SxM0AR register
•
A post-decrement of the DMA_SxNDTR register, which contains the number of
transactions that still have to be performed
After an event, the peripheral sends a request signal to the DMA controller. The DMA
controller serves the request depending on the channel priorities. As soon as the DMA
controller accesses the peripheral, an Acknowledge signal is sent to the peripheral by the
DMA controller. The peripheral releases its request as soon as it gets the Acknowledge
signal from the DMA controller. Once the request has been deasserted by the peripheral,
the DMA controller releases the Acknowledge signal. If there are more requests, the
peripheral can initiate the next transaction.
8.3.4
Channel selection
Each stream is associated with a DMA request that can be selected out of 8 possible
channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR
register.
Figure 23. Channel selection
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The 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected
to each channel and their connection depends on the product implementation.
Table 24 and Table 25 give examples of DMA request mappings.
Table 24. DMA1 request mapping
Peripheral
requests
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Channel 0
SPI3_RX
SPDIFRX_DT
SPI3_RX
SPI2_RX
SPI2_TX
SPI3_TX
SPDIFRX_CS
SPI3_TX
Channel 1
I2C1_RX
I2C3_RX
TIM7_UP
TIM7_UP
I2C1_RX
I2C1_TX
I2C1_TX
Channel 2
TIM4_CH1
-
I2C4 _RX
TIM4_CH2
-
I2C4 _RX
TIM4_UP
TIM4_CH3
Channel 3
-
TIM2_UP
TIM2_CH3
I2C3_RX
-
I2C3_TX
TIM2_CH1
TIM2_CH2
TIM2_CH4
TIM2_UP
TIM2_CH4
Channel 4
UART5_RX
USART3_RX
UART4_RX
USART3_TX
UART4_TX
USART2_RX
USART2_TX
UART5_TX
UART7_RX
TIM3_CH1
TIM3_TRIG
TIM3_CH2
UART8_RX
TIM3_CH3
Channel 5
UART8_TX
UART7_TX
TIM3_CH4
TIM3_UP
Channel 6
TIM5_CH3
TIM5_UP
TIM5_CH4
TIM5_TRIG
TIM5_CH1
TIM5_CH4
TIM5_TRIG
TIM5_CH2
-
TIM5_UP
-
Channel 7
-
TIM6_UP
I2C2_RX
I2C2_RX
USART3_TX
DAC1
DAC2
I2C2_TX
Table 25. DMA2 request mapping
Peripheral
requests
Stream 0
Stream 1
Stream 2
Stream 3
Stream 4
Stream 5
Stream 6
Stream 7
Channel 0
ADC1
SAI1_A
TIM8_CH1
TIM8_CH2
TIM8_CH3
SAI1_A
ADC1
SAI1_B
TIM1_CH1
TIM1_CH2
TIM1_CH3
SAI2_B
Channel 1
-
DCMI
ADC2
ADC2
SAI1_B
SPI6_TX
SPI6_RX
DCMI
Channel 2
ADC3
ADC3
-
SPI5_RX
SPI5_TX
CRYP_OUT
CRYP_IN
HASH_IN
Channel 3
SPI1_RX
-
SPI1_RX
SPI1_TX
SAI2_A
SPI1_TX
SAI2_B
QUADSPI
Channel 4
SPI4_RX
SPI4_TX
USART1_RX
SDMMC1
-
USART1_RX
SDMMC1
USART1_TX
Channel 5
-
USART6_RX
USART6_RX
SPI4_RX
SPI4_TX
-
USART6_TX
USART6_TX
TIM1_UP
TIM1_CH3
-
SPI5_RX
SPI5_TX
TIM8_CH4
TIM8_TRIG
TIM8_COM
Channel 6
TIM1_TRIG
TIM1_CH1
TIM1_CH2
TIM1_CH1
TIM1_CH4
TIM1_TRIG
TIM1_COM
Channel 7
-
TIM8_UP
TIM8_CH1
TIM8_CH2
TIM8_CH3
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8.3.5
Direct memory access controller (DMA)
Arbiter
An arbiter manages the 8 DMA stream requests based on their priority for each of the two
AHB master ports (memory and peripheral ports) and launches the peripheral/memory
access sequences.
Priorities are managed in two stages:
•
•
8.3.6
Software: each stream priority can be configured in the DMA_SxCR register. There are
four levels:
–
Very high priority
–
High priority
–
Medium priority
–
Low priority
Hardware: If two requests have the same software priority level, the stream with the
lower number takes priority over the stream with the higher number. For example,
Stream 2 takes priority over Stream 4.
DMA streams
Each of the 8 DMA controller streams provides a unidirectional transfer link between a
source and a destination.
Each stream can be configured to perform:
•
Regular type transactions: memory-to-peripherals, peripherals-to-memory or memoryto-memory transfers
•
Double-buffer type transactions: double buffer transfers using two memory pointers for
the memory (while the DMA is reading/writing from/to a buffer, the application can
write/read to/from the other buffer).
The amount of data to be transferred (up to 65535) is programmable and related to the
source width of the peripheral that requests the DMA transfer connected to the peripheral
AHB port. The register that contains the amount of data items to be transferred is
decremented after each transaction.
8.3.7
Source, destination and transfer modes
Both source and destination transfers can address peripherals and memories in the entire
4 GB area, at addresses comprised between 0x0000 0000 and 0xFFFF FFFF.
The direction is configured using the DIR[1:0] bits in the DMA_SxCR register and offers
three possibilities: memory-to-peripheral, peripheral-to-memory or memory-to-memory
transfers. Table 26 describes the corresponding source and destination addresses.
Table 26. Source and destination address
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
00
Peripheral-to-memory
DMA_SxPAR
01
Memory-to-peripheral
DMA_SxM0AR
DMA_SxPAR
10
Memory-to-memory
DMA_SxPAR
DMA_SxM0AR
11
Reserved
-
-
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DMA_SxM0AR
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When the data width (programmed in the PSIZE or MSIZE bits in the DMA_SxCR register)
is a half-word or a word, respectively, the peripheral or memory address written into the
DMA_SxPAR or DMA_SxM0AR/M1AR registers has to be aligned on a word or half-word
address boundary, respectively.
Peripheral-to-memory mode
Figure 24 describes this mode.
When this mode is enabled (by setting the bit EN in the DMA_SxCR register), each time a
peripheral request occurs, the stream initiates a transfer from the source to fill the FIFO.
When the threshold level of the FIFO is reached, the contents of the FIFO are drained and
stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is ‘0’), the threshold
level of the FIFO is not used: after each single data transfer from the peripheral to the FIFO,
the corresponding data are immediately drained and stored into the destination.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Figure 24. Peripheral-to-memory mode
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1. For double-buffer mode.
Memory-to-peripheral mode
Figure 25 describes this mode.
When this mode is enabled (by setting the EN bit in the DMA_SxCR register), the stream
immediately initiates transfers from the source to entirely fill the FIFO.
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Direct memory access controller (DMA)
Each time a peripheral request occurs, the contents of the FIFO are drained and stored into
the destination. When the level of the FIFO is lower than or equal to the predefined
threshold level, the FIFO is fully reloaded with data from the memory.
The transfer stops once the DMA_SxNDTR register reaches zero, when the peripheral
requests the end of transfers (in case of a peripheral flow controller) or when the EN bit in
the DMA_SxCR register is cleared by software.
In direct mode (when the DMDIS value in the DMA_SxFCR register is '0'), the threshold
level of the FIFO is not used. Once the stream is enabled, the DMA preloads the first data to
transfer into an internal FIFO. As soon as the peripheral requests a data transfer, the DMA
transfers the preloaded value into the configured destination. It then reloads again the
empty internal FIFO with the next data to be transfer. The preloaded data size corresponds
to the value of the PSIZE bitfield in the DMA_SxCR register.
The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Figure 25. Memory-to-peripheral mode
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1. For double-buffer mode.
Memory-to-memory mode
The DMA channels can also work without being triggered by a request from a peripheral.
This is the memory-to-memory mode, described in Figure 26.
When the stream is enabled by setting the Enable bit (EN) in the DMA_SxCR register, the
stream immediately starts to fill the FIFO up to the threshold level. When the threshold level
is reached, the FIFO contents are drained and stored into the destination.
The transfer stops once the DMA_SxNDTR register reaches zero or when the EN bit in the
DMA_SxCR register is cleared by software.
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The stream has access to the AHB source or destination port only if the arbitration of the
corresponding stream is won. This arbitration is performed using the priority defined for
each stream using the PL[1:0] bits in the DMA_SxCR register.
Note:
When memory-to-memory mode is used, the Circular and direct modes are not allowed.
Only the DMA2 controller is able to perform memory-to-memory transfers.
Figure 26. Memory-to-memory mode
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1. For double-buffer mode.
8.3.8
Pointer incrementation
Peripheral and memory pointers can optionally be automatically post-incremented or kept
constant after each transfer depending on the PINC and MINC bits in the DMA_SxCR
register.
Disabling the Increment mode is useful when the peripheral source or destination data are
accessed through a single register.
If the Increment mode is enabled, the address of the next transfer will be the address of the
previous one incremented by 1 (for bytes), 2 (for half-words) or 4 (for words) depending on
the data width programmed in the PSIZE or MSIZE bits in the DMA_SxCR register.
In order to optimize the packing operation, it is possible to fix the increment offset size for
the peripheral address whatever the size of the data transferred on the AHB peripheral port.
The PINCOS bit in the DMA_SxCR register is used to align the increment offset size with
the data size on the peripheral AHB port, or on a 32-bit address (the address is then
incremented by 4). The PINCOS bit has an impact on the AHB peripheral port only.
If the PINCOS bit is set, the address of the following transfer is the address of the previous
one incremented by 4 (automatically aligned on a 32-bit address), whatever the PSIZE
value. The AHB memory port, however, is not impacted by this operation.
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8.3.9
Direct memory access controller (DMA)
Circular mode
The Circular mode is available to handle circular buffers and continuous data flows (e.g.
ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_SxCR
register.
When the circular mode is activated, the number of data items to be transferred is
automatically reloaded with the initial value programmed during the stream configuration
phase, and the DMA requests continue to be served.
Note:
In the circular mode, it is mandatory to respect the following rule in case of a burst mode
configured for memory:
DMA_SxNDTR = Multiple of ((Mburst beat) × (Msize)/(Psize)), where:
–
(Mburst beat) = 4, 8 or 16 (depending on the MBURST bits in the DMA_SxCR
register)
–
((Msize)/(Psize)) = 1, 2, 4, 1/2 or 1/4 (Msize and Psize represent the MSIZE and
PSIZE bits in the DMA_SxCR register. They are byte dependent)
–
DMA_SxNDTR = Number of data items to transfer on the AHB peripheral port
For example: Mburst beat = 8 (INCR8), MSIZE = ‘00’ (byte) and PSIZE = ‘01’ (half-word), in
this case: DMA_SxNDTR must be a multiple of (8 × 1/2 = 4).
If this formula is not respected, the DMA behavior and data integrity are not guaranteed.
NDTR must also be a multiple of the Peripheral burst size multiplied by the peripheral data
size, otherwise this could result in a bad DMA behavior.
8.3.10
Double buffer mode
This mode is available for all the DMA1 and DMA2 streams.
The Double buffer mode is enabled by setting the DBM bit in the DMA_SxCR register.
A double-buffer stream works as a regular (single buffer) stream with the difference that it
has two memory pointers. When the Double buffer mode is enabled, the Circular mode is
automatically enabled (CIRC bit in DMA_SxCR is don’t care) and at each end of transaction,
the memory pointers are swapped.
In this mode, the DMA controller swaps from one memory target to another at each end of
transaction. This allows the software to process one memory area while the second memory
area is being filled/used by the DMA transfer. The double-buffer stream can work in both
directions (the memory can be either the source or the destination) as described in
Table 27: Source and destination address registers in double buffer mode (DBM=1).
Note:
In Double buffer mode, it is possible to update the base address for the AHB memory port
on-the-fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled, by respecting the
following conditions:
•
When the CT bit is ‘0’ in the DMA_SxCR register, the DMA_SxM1AR register can be
written. Attempting to write to this register while CT = '1' sets an error flag (TEIF) and
the stream is automatically disabled.
•
When the CT bit is ‘1’ in the DMA_SxCR register, the DMA_SxM0AR register can be
written. Attempting to write to this register while CT = '0', sets an error flag (TEIF) and
the stream is automatically disabled.
To avoid any error condition, it is advised to change the base address as soon as the TCIF
flag is asserted because, at this point, the targeted memory must have changed from
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memory 0 to 1 (or from 1 to 0) depending on the value of CT in the DMA_SxCR register in
accordance with one of the two above conditions.
For all the other modes (except the Double buffer mode), the memory address registers are
write-protected as soon as the stream is enabled.
Table 27. Source and destination address registers in double buffer mode (DBM=1)
Bits DIR[1:0] of the
DMA_SxCR register
Direction
Source address
Destination address
00
Peripheral-to-memory
DMA_SxPAR
DMA_SxM0AR / DMA_SxM1AR
01
Memory-to-peripheral DMA_SxM0AR / DMA_SxM1AR
DMA_SxPAR
Not allowed(1)
10
11
Reserved
-
-
1. When the Double buffer mode is enabled, the Circular mode is automatically enabled. Since the memory-to-memory mode
is not compatible with the Circular mode, when the Double buffer mode is enabled, it is not allowed to configure the
memory-to-memory mode.
8.3.11
Programmable data width, packing/unpacking, endianness
The number of data items to be transferred has to be programmed into DMA_SxNDTR
(number of data items to transfer bit, NDT) before enabling the stream (except when the
flow controller is the peripheral, PFCTRL bit in DMA_SxCR is set).
When using the internal FIFO, the data widths of the source and destination data are
programmable through the PSIZE and MSIZE bits in the DMA_SxCR register (can be 8-,
16- or 32-bit).
When PSIZE and MSIZE are not equal:
•
The data width of the number of data items to transfer, configured in the DMA_SxNDTR
register is equal to the width of the peripheral bus (configured by the PSIZE bits in the
DMA_SxCR register). For instance, in case of peripheral-to-memory, memory-toperipheral or memory-to-memory transfers and if the PSIZE[1:0] bits are configured for
half-word, the number of bytes to be transferred is equal to 2 × NDT.
•
The DMA controller only copes with little-endian addressing for both source and
destination. This is described in Table 28: Packing/unpacking & endian behavior (bit
PINC = MINC = 1).
This packing/unpacking procedure may present a risk of data corruption when the operation
is interrupted before the data are completely packed/unpacked. So, to ensure data
coherence, the stream may be configured to generate burst transfers: in this case, each
group of transfers belonging to a burst are indivisible (refer to Section 8.3.12: Single and
burst transfers).
In direct mode (DMDIS = 0 in the DMA_SxFCR register), the packing/unpacking of data is
not possible. In this case, it is not allowed to have different source and destination transfer
data widths: both are equal and defined by the PSIZE bits in the DMA_SxCR MSIZE bits are
don’t care).
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Direct memory access controller (DMA)
Table 28. Packing/unpacking & endian behavior (bit PINC = MINC = 1)
Number
AHB
AHB
of data
memory peripheral
items to
port
port
transfer
width
width
(NDT)
Peripheral port address / byte lane
Memory
transfer
number
Memory port
address / byte
lane
Peripheral
transfer
number
PINCOS = 1
PINCOS = 0
8
8
4
1
2
3
4
0x0 / B1|B0[15:0]
2
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
0x0 / B1|B0[15:0]
16
1
2
3
4
1
8
2
0x4 / B3|B2[15:0]
0x2 / B3|B2[15:0]
1
2
3
4
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
0x0 /
B3|B2|B1|B0[31:0]
0x0 /
B3|B2|B1|B0[31:0]
1
0x0 / B1|B0[15:0]
2
0x2 / B3|B2[15:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
0x0 / B1|B0[15:0]
1
0x0 / B1|B0[15:0]
0x0 / B1|B0[15:0]
2
0x2 / B1|B0[15:0]
2
0x4 / B3|B2[15:0]
0x2 / B3|B2[15:0]
1
2
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
1
0x0 /
B3|B2|B1|B0[31:0]
0x0 /
B3|B2|B1|B0[31:0]
1
0x0 / B3|B2|B1|B0[31:0] 1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
0x0 /B3|B2|B1|B0[31:0]
1
2
0x0 / B1|B0[15:0]
0x4 / B3|B2[15:0]
0x0 / B1|B0[15:0]
0x2 / B3|B2[15:0]
1
0x0 /B3|B2|B1|B0 [31:0] 1
0x0 /B3|B2|B1|B0
[31:0]
0x0 /
B3|B2|B1|B0[31:0]
8
32
1
16
8
4
16
16
2
16
32
1
32
8
4
32
16
2
32
32
1
Note:
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
1
2
3
4
0x0 / B0[7:0]
0x4 / B1[7:0]
0x8 / B2[7:0]
0xC / B3[7:0]
0x0 / B0[7:0]
0x1 / B1[7:0]
0x2 / B2[7:0]
0x3 / B3[7:0]
Peripheral port may be the source or the destination (it could also be the memory source in
the case of memory-to-memory transfer).
PSIZE, MSIZE and NDT[15:0] have to be configured so as to ensure that the last transfer
will not be incomplete. This can occur when the data width of the peripheral port (PSIZE
bits) is lower than the data width of the memory port (MSIZE bits). This constraint is
summarized in Table 29.
Table 29. Restriction on NDT versus PSIZE and MSIZE
PSIZE[1:0] of DMA_SxCR
MSIZE[1:0] of DMA_SxCR
NDT[15:0] of DMA_SxNDTR
00 (8-bit)
01 (16-bit)
must be a multiple of 2
00 (8-bit)
10 (32-bit)
must be a multiple of 4
01 (16-bit)
10 (32-bit)
must be a multiple of 2
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Direct memory access controller (DMA)
8.3.12
RM0385
Single and burst transfers
The DMA controller can generate single transfers or incremental burst transfers of 4, 8 or 16
beats.
The size of the burst is configured by software independently for the two AHB ports by using
the MBURST[1:0] and PBURST[1:0] bits in the DMA_SxCR register.
The burst size indicates the number of beats in the burst, not the number of bytes
transferred.
To ensure data coherence, each group of transfers that form a burst are indivisible: AHB
transfers are locked and the arbiter of the AHB bus matrix does not degrant the DMA master
during the sequence of the burst transfer.
Depending on the single or burst configuration, each DMA request initiates a different
number of transfers on the AHB peripheral port:
•
When the AHB peripheral port is configured for single transfers, each DMA request
generates a data transfer of a byte, half-word or word depending on the PSIZE[1:0] bits
in the DMA_SxCR register
•
When the AHB peripheral port is configured for burst transfers, each DMA request
generates 4,8 or 16 beats of byte, half word or word transfers depending on the
PBURST[1:0] and PSIZE[1:0] bits in the DMA_SxCR register.
The same as above has to be considered for the AHB memory port considering the
MBURST and MSIZE bits.
In direct mode, the stream can only generate single transfers and the MBURST[1:0] and
PBURST[1:0] bits are forced by hardware.
The address pointers (DMA_SxPAR or DMA_SxM0AR registers) must be chosen so as to
ensure that all transfers within a burst block are aligned on the address boundary equal to
the size of the transfer.
The burst configuration has to be selected in order to respect the AHB protocol, where
bursts must not cross the 1 KB address boundary because the minimum address space that
can be allocated to a single slave is 1 KB. This means that the 1 KB address boundary
should not be crossed by a burst block transfer, otherwise an AHB error would be
generated, that is not reported by the DMA registers.
8.3.13
FIFO
FIFO structure
The FIFO is used to temporarily store data coming from the source before transmitting them
to the destination.
Each stream has an independent 4-word FIFO and the threshold level is softwareconfigurable between 1/4, 1/2, 3/4 or full.
To enable the use of the FIFO threshold level, the direct mode must be disabled by setting
the DMDIS bit in the DMA_SxFCR register.
The structure of the FIFO differs depending on the source and destination data widths, and
is described in Figure 27: FIFO structure.
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RM0385
Direct memory access controller (DMA)
Figure 27. FIFO structure
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AI
FIFO threshold and burst configuration
Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the DMA_SxFCR
register) and the size of the memory burst (MBURST[1:0] of the DMA_SxCR register): The
content pointed by the FIFO threshold must exactly match an integer number of memory
burst transfers. If this is not in the case, a FIFO error (flag FEIFx of the DMA_HISR or
DMA_LISR register) will be generated when the stream is enabled, then the stream will be
automatically disabled. The allowed and forbidden configurations are described in Table 30.
The forbidden configurations are highlighted in gray in the table.
Table 30. FIFO threshold configurations
MSIZE
Byte
FIFO level
MBURST = INCR4
MBURST = INCR8
1/4
1 burst of 4 beats
forbidden
1/2
2 bursts of 4 beats
1 burst of 8 beats
3/4
3 bursts of 4 beats
forbidden
Full
4 bursts of 4 beats
2 bursts of 8 beats
DocID026670 Rev 6
MBURST = INCR16
forbidden
1 burst of 16 beats
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Direct memory access controller (DMA)
RM0385
Table 30. FIFO threshold configurations (continued)
MSIZE
Half-word
FIFO level
MBURST = INCR4
1/4
forbidden
1/2
1 burst of 4 beats
3/4
forbidden
Full
2 bursts of 4 beats
MBURST = INCR8
forbidden
1 burst of 8 beats
1/4
Word
1/2
forbidden
3/4
Full
MBURST = INCR16
forbidden
forbidden
1 burst of 4 beats
In all cases, the burst size multiplied by the data size must not exceed the FIFO size (data
size can be: 1 (byte), 2 (half-word) or 4 (word)).
Incomplete Burst transfer at the end of a DMA transfer may happen if one of the following
conditions occurs:
•
For the AHB peripheral port configuration: the total number of data items (set in the
DMA_SxNDTR register) is not a multiple of the burst size multiplied by the data size
•
For the AHB memory port configuration: the number of remaining data items in the
FIFO to be transferred to the memory is not a multiple of the burst size multiplied by the
data size
In such cases, the remaining data to be transferred will be managed in single mode by the
DMA, even if a burst transaction was requested during the DMA stream configuration.
Note:
When burst transfers are requested on the peripheral AHB port and the FIFO is used
(DMDIS = 1 in the DMA_SxCR register), it is mandatory to respect the following rule to
avoid permanent underrun or overrun conditions, depending on the DMA stream direction:
If (PBURST × PSIZE) = FIFO_SIZE (4 words), FIFO_Threshold = 3/4 is forbidden with
PSIZE = 1, 2 or 4 and PBURST = 4, 8 or 16.
This rule ensures that enough FIFO space at a time will be free to serve the request from
the peripheral.
FIFO flush
The FIFO can be flushed when the stream is disabled by resetting the EN bit in the
DMA_SxCR register and when the stream is configured to manage peripheral-to-memory or
memory-to-memory transfers: If some data are still present in the FIFO when the stream is
disabled, the DMA controller continues transferring the remaining data to the destination
(even though stream is effectively disabled). When this flush is completed, the transfer
complete status bit (TCIFx) in the DMA_LISR or DMA_HISR register is set.
The remaining data counter DMA_SxNDTR keeps the value in this case to indicate how
many data items are currently available in the destination memory.
Note that during the FIFO flush operation, if the number of remaining data items in the FIFO
to be transferred to memory (in bytes) is less than the memory data width (for example 2
bytes in FIFO while MSIZE is configured to word), data will be sent with the data width set in
the MSIZE bit in the DMA_SxCR register. This means that memory will be written with an
232/1671
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RM0385
Direct memory access controller (DMA)
undesired value. The software may read the DMA_SxNDTR register to determine the
memory area that contains the good data (start address and last address).
If the number of remaining data items in the FIFO is lower than a burst size (if the MBURST
bits in DMA_SxCR register are set to configure the stream to manage burst on the AHB
memory port), single transactions will be generated to complete the FIFO flush.
Direct mode
By default, the FIFO operates in direct mode (DMDIS bit in the DMA_SxFCR is reset) and
the FIFO threshold level is not used. This mode is useful when the system requires an
immediate and single transfer to or from the memory after each DMA request.
When the DMA is configured in direct mode (FIFO disabled), to transfer data in memory-toperipheral mode, the DMA preloads one data from the memory to the internal FIFO to
ensure an immediate data transfer as soon as a DMA request is triggered by a peripheral.
To avoid saturating the FIFO, it is recommended to configure the corresponding stream with
a high priority.
This mode is restricted to transfers where:
•
The source and destination transfer widths are equal and both defined by the
PSIZE[1:0] bits in DMA_SxCR (MSIZE[1:0] bits are don’t care)
•
Burst transfers are not possible (PBURST[1:0] and MBURST[1:0] bits in DMA_SxCR
are don’t care)
Direct mode must not be used when implementing memory-to-memory transfers.
8.3.14
DMA transfer completion
Different events can generate an end of transfer by setting the TCIFx bit in the DMA_LISR
or DMA_HISR status register:
•
•
Note:
In DMA flow controller mode:
–
The DMA_SxNDTR counter has reached zero in the memory-to-peripheral mode
–
The stream is disabled before the end of transfer (by clearing the EN bit in the
DMA_SxCR register) and (when transfers are peripheral-to-memory or memoryto-memory) all the remaining data have been flushed from the FIFO into the
memory
In Peripheral flow controller mode:
–
The last external burst or single request has been generated from the peripheral
and (when the DMA is operating in peripheral-to-memory mode) the remaining
data have been transferred from the FIFO into the memory
–
The stream is disabled by software, and (when the DMA is operating in peripheralto-memory mode) the remaining data have been transferred from the FIFO into
the memory
The transfer completion is dependent on the remaining data in FIFO to be transferred into
memory only in the case of peripheral-to-memory mode. This condition is not applicable in
memory-to-peripheral mode.
If the stream is configured in noncircular mode, after the end of the transfer (that is when the
number of data to be transferred reaches zero), the DMA is stopped (EN bit in DMA_SxCR
register is cleared by Hardware) and no DMA request is served unless the software
reprograms the stream and re-enables it (by setting the EN bit in the DMA_SxCR register).
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Direct memory access controller (DMA)
8.3.15
RM0385
DMA transfer suspension
At any time, a DMA transfer can be suspended to be restarted later on or to be definitively
disabled before the end of the DMA transfer.
There are two cases:
•
The stream disables the transfer with no later-on restart from the point where it was
stopped. There is no particular action to do, except to clear the EN bit in the
DMA_SxCR register to disable the stream. The stream may take time to be disabled
(ongoing transfer is completed first). The transfer complete interrupt flag (TCIF in the
DMA_LISR or DMA_HISR register) is set in order to indicate the end of transfer. The
value of the EN bit in DMA_SxCR is now ‘0’ to confirm the stream interruption. The
DMA_SxNDTR register contains the number of remaining data items at the moment
when the stream was stopped so that the software can determine how many data items
have been transferred before the stream was interrupted.
•
The stream suspends the transfer before the number of remaining data items to be
transferred in the DMA_SxNDTR register reaches 0. The aim is to restart the transfer
later by re-enabling the stream. In order to restart from the point where the transfer was
stopped, the software has to read the DMA_SxNDTR register after disabling the stream
by writing the EN bit in DMA_SxCR register (and then checking that it is at ‘0’) to know
the number of data items already collected. Then:
–
The peripheral and/or memory addresses have to be updated in order to adjust
the address pointers
–
The SxNDTR register has to be updated with the remaining number of data items
to be transferred (the value read when the stream was disabled)
–
The stream may then be re-enabled to restart the transfer from the point it was
stopped
Note:
Note that a Transfer complete interrupt flag (TCIF in DMA_LISR or DMA_HISR) is set to
indicate the end of transfer due to the stream interruption.
8.3.16
Flow controller
The entity that controls the number of data to be transferred is known as the flow controller.
This flow controller is configured independently for each stream using the PFCTRL bit in the
DMA_SxCR register.
The flow controller can be:
•
The DMA controller: in this case, the number of data items to be transferred is
programmed by software into the DMA_SxNDTR register before the DMA stream is
enabled.
•
The peripheral source or destination: this is the case when the number of data items to
be transferred is unknown. The peripheral indicates by hardware to the DMA controller
when the last data are being transferred. This feature is only supported for peripherals
which are able to signal the end of the transfer, that is:
–
SDMMC1
When the peripheral flow controller is used for a given stream, the value written into the
DMA_SxNDTR has no effect on the DMA transfer. Actually, whatever the value written, it will
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RM0385
Direct memory access controller (DMA)
be forced by hardware to 0xFFFF as soon as the stream is enabled, to respect the following
schemes:
•
Anticipated stream interruption: EN bit in DMA_SxCR register is reset to 0 by the
software to stop the stream before the last data hardware signal (single or burst) is sent
by the peripheral. In such a case, the stream is switched off and the FIFO flush is
triggered in the case of a peripheral-to-memory DMA transfer. The TCIFx flag of the
corresponding stream is set in the status register to indicate the DMA completion. To
know the number of data items transferred during the DMA transfer, read the
DMA_SxNDTR register and apply the following formula:
–
Note:
Number_of_data_transferred = 0xFFFF – DMA_SxNDTR
•
Normal stream interruption due to the reception of a last data hardware signal: the
stream is automatically interrupted when the peripheral requests the last transfer
(single or burst) and when this transfer is complete. the TCIFx flag of the corresponding
stream is set in the status register to indicate the DMA transfer completion. To know the
number of data items transferred, read the DMA_SxNDTR register and apply the same
formula as above.
•
The DMA_SxNDTR register reaches 0: the TCIFx flag of the corresponding stream is
set in the status register to indicate the forced DMA transfer completion. The stream is
automatically switched off even though the last data hardware signal (single or burst)
has not been yet asserted. The already transferred data will not be lost. This means
that a maximum of 65535 data items can be managed by the DMA in a single
transaction, even in peripheral flow control mode.
When configured in memory-to-memory mode, the DMA is always the flow controller and
the PFCTRL bit is forced to 0 by hardware.
The Circular mode is forbidden in the peripheral flow controller mode.
8.3.17
Summary of the possible DMA configurations
Table 31 summarizes the different possible DMA configurations. The forbidden
configurations are highlighted in gray in the table.
Table 31. Possible DMA configurations
DMA transfer
mode
Peripheral-tomemory
Memory-toperipheral
Memory-tomemory
Source
Destination
Flow
controller
Circular
mode
DMA
possible
Peripheral
forbidden
DMA
possible
Peripheral
forbidden
DMA only
forbidden
AHB
AHB
peripheral port memory port
AHB
memory port
AHB
peripheral port
AHB
AHB
peripheral port memory port
DocID026670 Rev 6
Transfer
type
Direct
mode
single
possible
burst
forbidden
single
possible
burst
forbidden
single
possible
burst
forbidden
single
possible
burst
forbidden
single
burst
forbidden
Double
buffer mode
possible
forbidden
possible
forbidden
forbidden
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Direct memory access controller (DMA)
8.3.18
RM0385
Stream configuration procedure
The following sequence should be followed to configure a DMA stream x (where x is the
stream number):
1.
If the stream is enabled, disable it by resetting the EN bit in the DMA_SxCR register,
then read this bit in order to confirm that there is no ongoing stream operation. Writing
this bit to 0 is not immediately effective since it is actually written to 0 once all the
current transfers have finished. When the EN bit is read as 0, this means that the
stream is ready to be configured. It is therefore necessary to wait for the EN bit to be
cleared before starting any stream configuration. All the stream dedicated bits set in the
status register (DMA_LISR and DMA_HISR) from the previous data block DMA
transfer should be cleared before the stream can be re-enabled.
2.
Set the peripheral port register address in the DMA_SxPAR register. The data will be
moved from/ to this address to/ from the peripheral port after the peripheral event.
3.
Set the memory address in the DMA_SxMA0R register (and in the DMA_SxMA1R
register in the case of a double buffer mode). The data will be written to or read from
this memory after the peripheral event.
4.
Configure the total number of data items to be transferred in the DMA_SxNDTR
register. After each peripheral event or each beat of the burst, this value is
decremented.
5.
Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register.
6.
If the peripheral is intended to be the flow controller and if it supports this feature, set
the PFCTRL bit in the DMA_SxCR register.
7.
Configure the stream priority using the PL[1:0] bits in the DMA_SxCR register.
8.
Configure the FIFO usage (enable or disable, threshold in transmission and reception)
9.
Configure the data transfer direction, peripheral and memory incremented/fixed mode,
single or burst transactions, peripheral and memory data widths, Circular mode,
Double buffer mode and interrupts after half and/or full transfer, and/or errors in the
DMA_SxCR register.
10. Activate the stream by setting the EN bit in the DMA_SxCR register.
As soon as the stream is enabled, it can serve any DMA request from the peripheral
connected to the stream.
Once half the data have been transferred on the AHB destination port, the half-transfer flag
(HTIF) is set and an interrupt is generated if the half-transfer interrupt enable bit (HTIE) is
set. At the end of the transfer, the transfer complete flag (TCIF) is set and an interrupt is
generated if the transfer complete interrupt enable bit (TCIE) is set.
Warning:
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To switch off a peripheral connected to a DMA stream
request, it is mandatory to, first, switch off the DMA stream to
which the peripheral is connected, then to wait for EN bit = 0.
Only then can the peripheral be safely disabled.
DocID026670 Rev 6
RM0385
8.3.19
Direct memory access controller (DMA)
Error management
The DMA controller can detect the following errors:
•
•
•
Transfer error: the transfer error interrupt flag (TEIFx) is set when:
–
A bus error occurs during a DMA read or a write access
–
A write access is requested by software on a memory address register in Double
buffer mode whereas the stream is enabled and the current target memory is the
one impacted by the write into the memory address register (refer to
Section 8.3.10: Double buffer mode)
FIFO error: the FIFO error interrupt flag (FEIFx) is set if:
–
A FIFO underrun condition is detected
–
A FIFO overrun condition is detected (no detection in memory-to-memory mode
because requests and transfers are internally managed by the DMA)
–
The stream is enabled while the FIFO threshold level is not compatible with the
size of the memory burst (refer to Table 30: FIFO threshold configurations)
Direct mode error: the direct mode error interrupt flag (DMEIFx) can only be set in the
peripheral-to-memory mode while operating in direct mode and when the MINC bit in
the DMA_SxCR register is cleared. This flag is set when a DMA request occurs while
the previous data have not yet been fully transferred into the memory (because the
memory bus was not granted). In this case, the flag indicates that 2 data items were be
transferred successively to the same destination address, which could be an issue if
the destination is not able to manage this situation
In direct mode, the FIFO error flag can also be set under the following conditions:
•
In the peripheral-to-memory mode, the FIFO can be saturated (overrun) if the memory
bus is not granted for several peripheral requests
•
In the memory-to-peripheral mode, an underrun condition may occur if the memory bus
has not been granted before a peripheral request occurs
If the TEIFx or the FEIFx flag is set due to incompatibility between burst size and FIFO
threshold level, the faulty stream is automatically disabled through a hardware clear of its
EN bit in the corresponding stream configuration register (DMA_SxCR).
If the DMEIFx or the FEIFx flag is set due to an overrun or underrun condition, the faulty
stream is not automatically disabled and it is up to the software to disable or not the stream
by resetting the EN bit in the DMA_SxCR register. This is because there is no data loss
when this kind of errors occur.
When the stream's error interrupt flag (TEIF, FEIF, DMEIF) in the DMA_LISR or DMA_HISR
register is set, an interrupt is generated if the corresponding interrupt enable bit (TEIE,
FEIE, DMIE) in the DMA_SxCR or DMA_SxFCR register is set.
Note:
When a FIFO overrun or underrun condition occurs, the data are not lost because the
peripheral request is not acknowledged by the stream until the overrun or underrun
condition is cleared. If this acknowledge takes too much time, the peripheral itself may
detect an overrun or underrun condition of its internal buffer and data might be lost.
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Direct memory access controller (DMA)
8.4
RM0385
DMA interrupts
For each DMA stream, an interrupt can be produced on the following events:
•
Half-transfer reached
•
Transfer complete
•
Transfer error
•
FIFO error (overrun, underrun or FIFO level error)
•
Direct mode error
Separate interrupt enable control bits are available for flexibility as shown in Table 32.
Table 32. DMA interrupt requests
Interrupt event
Event flag
Enable control bit
Half-transfer
HTIF
HTIE
Transfer complete
TCIF
TCIE
Transfer error
TEIF
TEIE
FIFO overrun/underrun
FEIF
FEIE
DMEIF
DMEIE
Direct mode error
Note:
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Before setting an Enable control bit to ‘1’, the corresponding event flag should be cleared,
otherwise an interrupt is immediately generated.
DocID026670 Rev 6
RM0385
Direct memory access controller (DMA)
8.5
DMA registers
The DMA registers have to be accessed by words (32 bits).
8.5.1
DMA low interrupt status register (DMA_LISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
TCIF3
HTIF3
TEIF3
DMEIF3
Res.
FEIF3
TCIF2
HTIF2
TEIF2
DMEIF2
Res.
FEIF2
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
TCIF1
HTIF1
TEIF1
DMEIF1
Res.
FEIF1
TCIF0
HTIF0
TEIF0
DMEIF0
Res.
FEIF0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x = 3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No Direct Mode Error on stream x
1: A Direct Mode Error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=3..0)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_LIFCR register.
0: No FIFO Error event on stream x
1: A FIFO Error event occurred on stream x
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Direct memory access controller (DMA)
8.5.2
RM0385
DMA high interrupt status register (DMA_HISR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
TCIF7
HTIF7
TEIF7
DMEIF7
Res.
FEIF7
TCIF6
HTIF6
TEIF6
DMEIF6
Res.
FEIF6
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
TCIF5
HTIF5
TEIF5
DMEIF5
Res.
FEIF5
TCIF4
HTIF4
TEIF4
DMEIF4
Res.
FEIF4
r
r
r
r
r
r
r
r
r
r
r
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 TCIFx: Stream x transfer complete interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer complete event on stream x
1: A transfer complete event occurred on stream x
Bits 26, 20, 10, 4 HTIFx: Stream x half transfer interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No half transfer event on stream x
1: A half transfer event occurred on stream x
Bits 25, 19, 9, 3 TEIFx: Stream x transfer error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No transfer error on stream x
1: A transfer error occurred on stream x
Bits 24, 18, 8, 2 DMEIFx: Stream x direct mode error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No Direct mode error on stream x
1: A Direct mode error occurred on stream x
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 FEIFx: Stream x FIFO error interrupt flag (x=7..4)
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_HIFCR register.
0: No FIFO error event on stream x
1: A FIFO error event occurred on stream x
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RM0385
Direct memory access controller (DMA)
8.5.3
DMA low interrupt flag clear register (DMA_LIFCR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
27
15
14
13
12
Res.
Res.
Res.
Res.
26
25
24
CTCIF3 CHTIF3 CTEIF3 CDMEIF3
w
w
w
w
11
10
9
8
CTCIF1 CHTIF1 CTEIF1 CDMEIF1
w
w
w
23
22
21
Res.
CFEIF3
CTCIF2
20
19
18
CHTIF2 CTEIF2 CDMEIF2
w
w
w
w
w
7
6
5
4
3
2
Res.
CFEIF1
CTCIF0
w
w
w
CHTIF0 CTEIF0 CDMEIF0
w
w
17
16
Res.
CFEIF2
w
1
0
Res.
CFEIF0
w
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_LISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_LISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_LISR register
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_LISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 3..0)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_LISR register
8.5.4
DMA high interrupt flag clear register (DMA_HIFCR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res. Res. Res. Res. CTCIF7 CHTIF7 CTEIF7 CDMEIF7
15
14
13
12
w
w
w
w
11
10
9
8
Res. Res. Res. Res. CTCIF5 CHTIF5 CTEIF5 CDMEIF5
w
w
w
23
22
21
20
Res.
CFEIF7
CTCIF6
CHTIF6
w
w
w
7
6
5
4
Res.
CFEIF5
CTCIF4
CHTIF4
w
w
w
w
19
18
CTEIF6 CDMEIF6
w
w
3
2
CTEIF4 CDMEIF4
w
17
16
Res.
CFEIF6
w
1
0
Res.
CFEIF4
w
w
Bits 31:28, 15:12 Reserved, must be kept at reset value.
Bits 27, 21, 11, 5 CTCIFx: Stream x clear transfer complete interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TCIFx flag in the DMA_HISR register
Bits 26, 20, 10, 4 CHTIFx: Stream x clear half transfer interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding HTIFx flag in the DMA_HISR register
Bits 25, 19, 9, 3 CTEIFx: Stream x clear transfer error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding TEIFx flag in the DMA_HISR register
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Direct memory access controller (DMA)
RM0385
Bits 24, 18, 8, 2 CDMEIFx: Stream x clear direct mode error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding DMEIFx flag in the DMA_HISR register
Bits 23, 17, 7, 1 Reserved, must be kept at reset value.
Bits 22, 16, 6, 0 CFEIFx: Stream x clear FIFO error interrupt flag (x = 7..4)
Writing 1 to this bit clears the corresponding CFEIFx flag in the DMA_HISR register
8.5.5
DMA stream x configuration register (DMA_SxCR) (x = 0..7)
This register is used to configure the concerned stream.
Address offset: 0x10 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
27
rw
15
PINCOS
rw
14
13
12
11
MSIZE[1:0]
PSIZE[1:0]
rw
rw
rw
26
25
24
CHSEL[2:0]
rw
rw
23
MBURST [1:0]
rw
22
rw
rw
rw
7
6
10
9
8
MINC
PINC
CIRC
rw
rw
rw
DIR[1:0]
rw
21
PBURST[1:0]
rw
20
19
18
Res.
CT
DBM
rw
rw
rw
17
rw
5
4
3
2
1
0
TCIE
HTIE
TEIE
DMEIE
EN
rw
rw
rw
rw
rw
rw
Bits 27:25 CHSEL[2:0]: Channel selection
These bits are set and cleared by software.
000: channel 0 selected
001: channel 1 selected
010: channel 2 selected
011: channel 3 selected
100: channel 4 selected
101: channel 5 selected
110: channel 6 selected
111: channel 7 selected
These bits are protected and can be written only if EN is ‘0’
Bits 24:23 MBURST: Memory burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is ‘0’
In direct mode, these bits are forced to 0x0 by hardware as soon as bit EN= '1'.
Bits 22:21 PBURST[1:0]: Peripheral burst transfer configuration
These bits are set and cleared by software.
00: single transfer
01: INCR4 (incremental burst of 4 beats)
10: INCR8 (incremental burst of 8 beats)
11: INCR16 (incremental burst of 16 beats)
These bits are protected and can be written only if EN is ‘0’
In direct mode, these bits are forced to 0x0 by hardware.
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PFCTRL
Bits 31:28 Reserved, must be kept at reset value.
Bit 20 Reserved, must be kept at reset value.
16
PL[1:0]
RM0385
Direct memory access controller (DMA)
Bit 19 CT: Current target (only in double buffer mode)
This bits is set and cleared by hardware. It can also be written by software.
0: The current target memory is Memory 0 (addressed by the DMA_SxM0AR pointer)
1: The current target memory is Memory 1 (addressed by the DMA_SxM1AR pointer)
This bit can be written only if EN is ‘0’ to indicate the target memory area of the first transfer.
Once the stream is enabled, this bit operates as a status flag indicating which memory area
is the current target.
Bit 18 DBM: Double buffer mode
This bits is set and cleared by software.
0: No buffer switching at the end of transfer
1: Memory target switched at the end of the DMA transfer
This bit is protected and can be written only if EN is ‘0’.
Bits 17:16 PL[1:0]: Priority level
These bits are set and cleared by software.
00: Low
01: Medium
10: High
11: Very high
These bits are protected and can be written only if EN is ‘0’.
Bit 15 PINCOS: Peripheral increment offset size
This bit is set and cleared by software
0: The offset size for the peripheral address calculation is linked to the PSIZE
1: The offset size for the peripheral address calculation is fixed to 4 (32-bit alignment).
This bit has no meaning if bit PINC = '0'.
This bit is protected and can be written only if EN = '0'.
This bit is forced low by hardware when the stream is enabled (bit EN = '1') if the direct
mode is selected or if PBURST are different from “00”.
Bits 14:13 MSIZE[1:0]: Memory data size
These bits are set and cleared by software.
00: byte (8-bit)
01: half-word (16-bit)
10: word (32-bit)
11: reserved
These bits are protected and can be written only if EN is ‘0’.
In direct mode, MSIZE is forced by hardware to the same value as PSIZE as soon as bit EN
= '1'.
Bits 12:11 PSIZE[1:0]: Peripheral data size
These bits are set and cleared by software.
00: Byte (8-bit)
01: Half-word (16-bit)
10: Word (32-bit)
11: reserved
These bits are protected and can be written only if EN is ‘0’
Bit 10 MINC: Memory increment mode
This bit is set and cleared by software.
0: Memory address pointer is fixed
1: Memory address pointer is incremented after each data transfer (increment is done
according to MSIZE)
This bit is protected and can be written only if EN is ‘0’.
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RM0385
Bit 9 PINC: Peripheral increment mode
This bit is set and cleared by software.
0: Peripheral address pointer is fixed
1: Peripheral address pointer is incremented after each data transfer (increment is done
according to PSIZE)
This bit is protected and can be written only if EN is ‘0’.
Bit 8 CIRC: Circular mode
This bit is set and cleared by software and can be cleared by hardware.
0: Circular mode disabled
1: Circular mode enabled
When the peripheral is the flow controller (bit PFCTRL=1) and the stream is enabled (bit
EN=1), then this bit is automatically forced by hardware to 0.
It is automatically forced by hardware to 1 if the DBM bit is set, as soon as the stream is
enabled (bit EN ='1').
Bits 7:6 DIR[1:0]: Data transfer direction
These bits are set and cleared by software.
00: Peripheral-to-memory
01: Memory-to-peripheral
10: Memory-to-memory
11: reserved
These bits are protected and can be written only if EN is ‘0’.
Bit 5 PFCTRL: Peripheral flow controller
This bit is set and cleared by software.
0: The DMA is the flow controller
1: The peripheral is the flow controller
This bit is protected and can be written only if EN is ‘0’.
When the memory-to-memory mode is selected (bits DIR[1:0]=10), then this bit is
automatically forced to 0 by hardware.
Bit 4 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disabled
1: TC interrupt enabled
Bit 3 HTIE: Half transfer interrupt enable
This bit is set and cleared by software.
0: HT interrupt disabled
1: HT interrupt enabled
Bit 2 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disabled
1: TE interrupt enabled
Bit 1 DMEIE: Direct mode error interrupt enable
This bit is set and cleared by software.
0: DME interrupt disabled
1: DME interrupt enabled
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RM0385
Direct memory access controller (DMA)
Bit 0 EN: Stream enable / flag stream ready when read low
This bit is set and cleared by software.
0: Stream disabled
1: Stream enabled
This bit may be cleared by hardware:
–
on a DMA end of transfer (stream ready to be configured)
–
if a transfer error occurs on the AHB master buses
–
when the FIFO threshold on memory AHB port is not compatible with the size of the
burst
When this bit is read as 0, the software is allowed to program the Configuration and FIFO
bits registers. It is forbidden to write these registers when the EN bit is read as 1.
Note: Before setting EN bit to '1' to start a new transfer, the event flags corresponding to the
stream in DMA_LISR or DMA_HISR register must be cleared.
8.5.6
DMA stream x number of data register (DMA_SxNDTR) (x = 0..7)
Address offset: 0x14 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
NDT[15:0]
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 NDT[15:0]: Number of data items to transfer
Number of data items to be transferred (0 up to 65535). This register can be written only
when the stream is disabled. When the stream is enabled, this register is read-only,
indicating the remaining data items to be transmitted. This register decrements after each
DMA transfer.
Once the transfer has completed, this register can either stay at zero (when the stream is in
normal mode) or be reloaded automatically with the previously programmed value in the
following cases:
–
when the stream is configured in Circular mode.
–
when the stream is enabled again by setting EN bit to '1'
If the value of this register is zero, no transaction can be served even if the stream is
enabled.
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Direct memory access controller (DMA)
8.5.7
RM0385
DMA stream x peripheral address register (DMA_SxPAR) (x = 0..7)
Address offset: 0x18 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PAR[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
PAR[15:0]
rw
Bits 31:0 PAR[31:0]: Peripheral address
Base address of the peripheral data register from/to which the data will be read/written.
These bits are write-protected and can be written only when bit EN = '0' in the DMA_SxCR register.
8.5.8
DMA stream x memory 0 address register (DMA_SxM0AR) (x = 0..7)
Address offset: 0x1C + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
M0A[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
M0A[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 M0A[31:0]: Memory 0 address
Base address of Memory area 0 from/to which the data will be read/written.
These bits are write-protected. They can be written only if:
–
the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
–
the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '1' in the
DMA_SxCR register (in Double buffer mode).
8.5.9
DMA stream x memory 1 address register (DMA_SxM1AR) (x = 0..7)
Address offset: 0x20 + 0x18 × stream number
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
M1A[31:16]
M1A[15:0]
rw
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RM0385
Direct memory access controller (DMA)
Bits 31:0 M1A[31:0]: Memory 1 address (used in case of Double buffer mode)
Base address of Memory area 1 from/to which the data will be read/written.
This register is used only for the Double buffer mode.
These bits are write-protected. They can be written only if:
–
the stream is disabled (bit EN= '0' in the DMA_SxCR register) or
–
the stream is enabled (EN=’1’ in DMA_SxCR register) and bit CT = '0' in the
DMA_SxCR register.
8.5.10
DMA stream x FIFO control register (DMA_SxFCR) (x = 0..7)
Address offset: 0x24 + 0x24 × stream number
Reset value: 0x0000 0021
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
5
4
3
2
1
0
15
14
13
12
11
10
9
8
7
6
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FEIE
Res.
rw
FS[2:0]
r
r
DMDIS
r
rw
FTH[1:0]
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bit 7 FEIE: FIFO error interrupt enable
This bit is set and cleared by software.
0: FE interrupt disabled
1: FE interrupt enabled
Bit 6 Reserved, must be kept at reset value.
Bits 5:3 FS[2:0]: FIFO status
These bits are read-only.
000: 0 < fifo_level < 1/4
001: 1/4 ≤ fifo_level < 1/2
010: 1/2 ≤ fifo_level < 3/4
011: 3/4 ≤ fifo_level < full
100: FIFO is empty
101: FIFO is full
others: no meaning
These bits are not relevant in the direct mode (DMDIS bit is zero).
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RM0385
Bit 2 DMDIS: Direct mode disable
This bit is set and cleared by software. It can be set by hardware.
0: Direct mode enabled
1: Direct mode disabled
This bit is protected and can be written only if EN is ‘0’.
This bit is set by hardware if the memory-to-memory mode is selected (DIR bit in
DMA_SxCR are “10”) and the EN bit in the DMA_SxCR register is ‘1’ because the direct
mode is not allowed in the memory-to-memory configuration.
Bits 1:0 FTH[1:0]: FIFO threshold selection
These bits are set and cleared by software.
00: 1/4 full FIFO
01: 1/2 full FIFO
10: 3/4 full FIFO
11: full FIFO
These bits are not used in the direct mode when the DMIS value is zero.
These bits are protected and can be written only if EN is ‘0’.
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0x002C
0x0030
DMA_S1NDTR
Reset value
0
0
0
0
0
0
0
0
0
0
Res
0
0
0
0
0
0
0
0
0
0
DMA_S0M1AR
DMA_S1PAR
0
0
0
0
0
0
0
0
0
Reset value
0
DocID026670 Rev 6
0
0
0
0
0
0
0
0
0
0
0
0
CDMEIF5
0
Reset value
0
0
TCIE
HTIE
TEIE
DMEIE
EN
0
PFCTRL
DIR[1:0]
CTCIF4
CHTIF4
CTEIF4
CDMEIF4
CHTIF1
CTEIF1
CDMEIF1
CFEIF1
CTCIF0
CHTIF0
CTEIF0
CDMEIF0
0
0
0
0
0
0
0
0
0
TEIF5
DMEIF5
FEIF5
TCIF4
HTIF4
TEIF4
DMEIF4
HTIF1
TEIF1
DMEIF1
FEIF1
TCIF0
HTIF0
TEIF0
DMEIF0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S0FCR
0
FS[2:0]
Reserved
FEIF0
Reserved
FEIF4
Res.
TCIF1
Res.
Res.
Res.
Res.
0
CFEIF0
HTIF5
0
Res
TCIF5
Res
Res
Res
Res
0
Reserved
Res
CTCIF1
Res
Res
Res
Res
Res.
FEIF2
0
CFEIF4
CFEIF2
0
Reserved
CFEIF5
Res
CTEIF5
PINC
CIRC
CHTIF5
MINC
Res
Res
CTCIF5
PSIZE[1:0]
MSIZE[1:0]
0
EN
DMA_S0M0AR
0
0
0
DMDIS
0
0
0
0
DMEIE
0
Res
0
0
0
TEIE
0
FEIE
DMA_S0PAR
0
0
HTIE
0
Res
Reset value
0
0
TCIE
0
Res
0
0
0
PFCTRL
0
Res
0
0
Res
0
Res
0
DIR[1:0]
0
Res
0
0
0
PINCOS
FEIF6
0
Res
0
Res
Res
CFEIF6
Res
0
CIRC
0
Res
0
0
PL[1:0]
0
PINC
0
Res
0
0
Res
0
Res
TEIF2
DMEIF2
0
DMEIF6
CDMEIF2
CDMEIF6
0
DBM
0
Res
HTIF2
0
TEIF6
CTEIF2
CTEIF6
0
CT
0
Res
TCIF2
0
HTIF6
CHTIF2
0
TCIF6
CTCIF2
0
CHTIF6
0
CTCIF6
0
FEIF7
0
Res
0
Res.
FEIF3
0
Res
0
MINC
0
Res
0
CFEIF3
Reserved
0
PSIZE[1:0]
0
Res
0
0
CFEIF7
TEIF3
DMEIF7
DMEIF3
TEIF7
Res.
Res.
HTIF3
HTIF7
Res.
0
MSIZE[1:0]
0
Res
0
0
PINCOS
0
Res
0
0
0
PL[1:0]
0
0
Res
0
PBURST[1:0]
0
Res
0
Res
0
Res
0
Reserved
0
DBM
0
Res
0
Res
0
Res
0
MBURST[1:0]
CDMEIF3
0
Res
0
Res
CDMEIF7
TEIF3
0
CT
0
Res
0
Res
CHTIF3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DMA_LISR
Res.
Register
TCIF3
TCIF7
Res
Res
0
Res
0
Res
0
CTEIF7
CTCIF3
Res
Res
Res
Res
0
Res
0
Res
0
CHTIF7
Res
CHSEL[2:0]
CTCIF7
Res
DMA_S0CR
Res
Res
Res
0
PBURST[1:0]
0
Res
0
Res
Res
Res
0
MBURST[1:]
0
Res
0
Res
Res
Res
0
Res
0
Res
Reset value
Res
0
Res
0
Res
0
Res
0
0
0
Res
Reset value
CHSEL[2:0]
0
Res
0
0
Res
Res
Res
Reset value
Res
DMA_S1CR
0
Res
Res
Reset value
Res
Reset value
Res
0x0028
DMA_HIFCR
Res
Reset value
Res
0x0024
Reset value
Res
0x0020
Res
Reset value
0
Res
0x001C
0
Res
Reset value
Res
0x0018
DMA_S0NDTR
Res
0x0014
DMA_LIFCR
Res
0x0010
DMA_HISR
Res
0x000C
Res
0x0008
Res
0x0004
Res
0x0000
Res
Offset
Res
8.5.11
Res
RM0385
Direct memory access controller (DMA)
DMA register map
Table 33 summarizes the DMA registers.
Table 33. DMA register map and reset values
0
0
0
0
NDT[15:.]
0
0
0
0
0
0
0
PA[31:0]
M0A[31:0]
M1A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FTH
[1:0]
1
0
0
0
0
1
NDT[15:.]
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
249/1671
252
Direct memory access controller (DMA)
RM0385
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S1FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S2FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
250/1671
DMEIE
EN
0
1
TEIE
0
0
HTIE
0
0
0
0
0
0
0
0
DIR[1:0]
0
0
TCIE
0
CIRC
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S3M1AR
Reset value
0
0
PA[31:0]
DMA_S3M0AR
Reset value
0
1
NDT[15:.]
0
DMA_S3PAR
MSIZE[1:0]
PINCOS
PL[1:0]
Reset value
0
FTH
[1:0]
PFCTRL
Res
0
PINC
Res
0
MINC
Res
0
Res
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
Res
Res
Res
DMA_S3NDTR
Res
Res
Res
Res
Res
0
FS[2:0]
DMDIS
0
Res
M1A[31:0]
0
0x0060
0x0068
0
M0A[31:0]
Reset value
0x0064
0
Reset value
DMA_S3CR
1
PA[31:0]
DMA_S2M1AR
0x0058
0
NDT[15:.]
Reset value
0x005C
0
0
EN
0
0
TEIE
0
0
DMEIE
0
1
HTIE
0
FTH
[1:0]
TCIE
0
CIRC
0
PINC
0
MINC
0
PSIZE[1:0]
MSIZE[1:0]
PINCOS
PL[1:0]
0
Res
Res
0
Res
Res
DBM
Res
0
Res
Res
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
0
DMA_S2M0AR
Reset value
0x0054
0
DMA_S2PAR
Reset value
0x0050
0
Reset value
0x0048
0x004C
Res
DMA_S2NDTR
Res
0x0044
Res
Reset value
Res
Res
Res
Res
DMA_S2CR
0x0040
0
Res
Reset value
FS[2:0]
DMDIS
Reset value
Res
M1A[31:0]
Res
DMA_S1M1AR
0
Res
0
Res
0x003C
0
Res
0x0038
0
PFCTRL
Reset value
Res
M0A[31:0]
FEIE
DMA_S1M0AR
DIR
[1:0]
Offset
0x0034
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 33. DMA register map and reset values (continued)
0
0
0
0
M1A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DocID026670 Rev 6
0
0
RM0385
Direct memory access controller (DMA)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0x00A8
0x00AC
EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S4FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S5M0AR
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S5FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
Reset value
EN
0
1
DMEIE
0
0
TEIE
0
0
0
0
0
0
0
0
DIR[1:0]
0
0
HTIE
0
0
TCIE
0
CIRC
PSIZE[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PA[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S6M0AR
Reset value
0
1
NDT[15:.]
0
DMA_S6PAR
MSIZE[1:0]
PINCOS
PL[1:0]
Reset value
0
FTH
[1:0]
PFCTRL
Res
0
PINC
Res
0
MINC
Res
0
Res
Res
0
Res
0
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
Res
Res
Res
DMA_S6NDTR
Res
Res
Res
Res
Res
0
FS[2:0]
DMDIS
Reset value
Res
M1A[31:0]
Res
DMA_S5M1AR
DMA_S6CR
1
EN
0
0
DMEIE
0
DIR[1:0]
0
CIRC
0
0
TEIE
0
0
HTIE
0
0
NDT[15:.]
0
DMA_S5PAR
0
1
TCIE
0
FTH
[1:0]
PFCTRL
0
PSIZE[1:0]
MSIZE[1:0]
PINCOS
PL[1:0]
0
PINC
Res
0
MINC
Res
0
Res
Res
0
Res
Res
DBM
0
Res
0
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
Res
Res
Res
0
Res
Res
Res
Res
Res
0
FS[2:0]
DMDIS
0
Reset value
DMDIS
TEIE
DMEIE
0
M1A[31:0]
Reset value
0x00A4
HTIE
0
Reset value
0x00A0
0
Res
0x009C
0
Res
0x0098
0
Res
0x0094
0
0
Reset value
1
0
Res
0x0090
0
0
Reset value
DMA_S5NDTR
0
0
Res
DMA_S4M1AR
DMA_S5CR
0
M0A[31:0]
Reset value
0x008C
0
0
NDT[15:.]
Reset value
0x0088
Res
Res
0
DIR
[1:0]
0
CIRC
0
1
TCIE
0
FTH
[1:0]
PFCTRL
0
PINC
0
FS[2:0]
PA[31:0]
DMA_S4M0AR
Reset value
0
MINC
Res
Reset value
0
PSIZE[1:0]
0
DMA_S4PAR
Reset value
MSIZE[1:0]
PINCOS
0
Res
PL[1:0]
DBM
Res
0
Res
Res
CT
Res
0
Res
Res
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
Res
Res
0
Res
0x0084
0
Res
0x0080
0
Res
0x007C
0
Res
0x0078
0
Res
0x0074
Res
Reset value
DMA_S4NDTR
Res
Res
Res
DMA_S4CR
Res
0x0070
0
Res
Reset value
FEIE
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
DMA_S3FCR
Res
0x006C
Register
Res
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 33. DMA register map and reset values (continued)
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DocID026670 Rev 6
0
0
251/1671
252
Direct memory access controller (DMA)
RM0385
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S6FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
0
0
0
FTH
[1:0]
0
0
1
EN
0
TEIE
0
DMEIE
1
0
0
0
0
0
0
NDT[15:.]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
M0A[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA_S7FCR
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
Res
FEIE
Res
Reset value
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
DocID026670 Rev 6
FS[2:0]
1
0
0
DMDIS
Reset value
Res
M1A[31:0]
Res
DMA_S7M1AR
252/1671
0
HTIE
0
0
TCIE
0
FS[2:0]
0
0
DIR[1:0]
0
CIRC
0
0
PFCTRL
0
PINC
0
MINC
0
0
PA[31:0]
DMA_S7M0AR
Reset value
0
PSIZE[1:0]
0
Reset value
Reset value
MSIZE[1:0]
PINCOS
PL[1:0]
0
Res
Res
0
Res
Res
DBM
Res
0
Res
Res
CT
0
Res
0
Res
0
Res
Res
PBURST[1:0]
MBURST[1:0]
CHSEL[2:0]
0
Res
Res
Res
0
Res
0x00CC
0
Res
0x00C8
0
DMA_S7PAR
0x00C0
0x00C4
Res
0x00BC
Res
Reset value
DMA_S7NDTR
Res
Res
Res
Res
DMA_S7CR
0x00B8
0
Res
Reset value
0
DMDIS
0
Res
0
Res
0
Res
M1A[31:0]
Reset value
Res
0x00B4
DMA_S6M1AR
Res
0x00B0
Register
FEIE
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 33. DMA register map and reset values (continued)
0
FTH
[1:0]
0
1
RM0385
Chrom-Art Accelerator™ controller (DMA2D)
9
Chrom-Art Accelerator™ controller (DMA2D)
9.1
DMA2D introduction
The Chrom-Art Accelerator™ (DMA2D) is a specialized DMA dedicated to image
manipulation. It can perform the following operations:
•
Filling a part or the whole of a destination image with a specific color
•
Copying a part or the whole of a source image into a part or the whole of a destination
image
•
Copying a part or the whole of a source image into a part or the whole of a destination
image with a pixel format conversion
•
Blending a part and/or two complete source images with different pixel format and copy
the result into a part or the whole of a destination image with a different color format.
All the classical color coding schemes are supported from 4-bit up to 32-bit per pixel with
indexed or direct color mode. The DMA2D has its own dedicated memories for CLUTs (color
look-up tables).
9.2
DMA2D main features
The main DMA2D features are:
•
Single AHB master bus architecture.
•
AHB slave programming interface supporting 8/16/32-bit accesses (except for CLUT
accesses which are 32-bit).
•
User programmable working area size
•
User programmable offset for sources and destination areas
•
User programmable sources and destination addresses on the whole memory space
•
Up to 2 sources with blending operation
•
Alpha value can be modified (source value, fixed value or modulated value)
•
User programmable source and destination color format
•
Up to 11 color formats supported from 4-bit up to 32-bit per pixel with indirect or direct
color coding
•
2 internal memories for CLUT storage in indirect color mode
•
Automatic CLUT loading or CLUT programming via the CPU
•
User programmable CLUT size
•
Internal timer to control AHB bandwidth
•
4 operating modes: register-to-memory, memory-to-memory, memory-to-memory with
pixel format conversion, and memory-to-memory with pixel format conversion and
blending
DocID026670 Rev 6
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284
Chrom-Art Accelerator™ controller (DMA2D)
•
Area filling with a fixed color
•
Copy from an area to another
•
Copy with pixel format conversion between source and destination images
•
Copy from two sources with independent color format and blending
•
Abort and suspend of DMA2D operations
•
Watermark interrupt on a user programmable destination line
•
Interrupt generation on bus error or access conflict
•
Interrupt generation on process completion
9.3
DMA2D functional description
9.3.1
General description
RM0385
The DMA2D controller performs direct memory transfer. As an AHB master, it can take the
control of the AHB bus matrix to initiate AHB transactions.
The DMA2D can operate in the following modes:
•
Register-to-memory
•
Memory-to-memory
•
Memory-to-memory with Pixel Format Conversion
•
Memory-to-memory with Pixel Format Conversion and Blending
The AHB slave port is used to program the DMA2D controller.
The block diagram of the DMA2D is shown in Figure 28: DMA2D block diagram.
254/1671
DocID026670 Rev 6
RM0385
Chrom-Art Accelerator™ controller (DMA2D)
Figure 28. DMA2D block diagram
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9.3.2
DMA2D control
The DMA2D controller is configured through the DMA2D Control Register (DMA2D_CR)
which allows selecting:
The user application can perform the following operations:
9.3.3
•
Select the operating mode
•
Enable/disable the DMA2D interrupt
•
Start/suspend/abort ongoing data transfers
DMA2D foreground and background FIFOs
The DMA2D foreground (FG) FG FIFO and background (BG) FIFO fetch the input data to
be copied and/or processed.
The FIFOs fetch the pixels according to the color format defined in their respective pixel
format converter (PFC).
DocID026670 Rev 6
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284
Chrom-Art Accelerator™ controller (DMA2D)
RM0385
They are programmed through a set of control registers:
•
DMA2D foreground memory address register (DMA2D_FGMAR)
•
DMA2D foreground offset register (DMA2D_FGOR)
•
DMA2D background memory address register (DMA2D_BGMAR)
•
DMA2D background offset register (DMA2D_BGBOR)
•
DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
When the DMA2D operates in register-to-memory mode, none of the FIFOs is activated.
When the DMA2D operates in memory-to-memory mode (no pixel format conversion nor
blending operation), only the FG FIFO is activated and acts as a buffer.
When the DMA2D operates in memory-to-memory operation with pixel format conversion
(no blending operation), the BG FIFO is not activated.
9.3.4
DMA2D foreground and background pixel format converter (PFC)
DMA2D foreground pixel format converter (PFC) and background pixel format converter
perform the pixel format conversion to generate a 32-bit per pixel value. The PFC can also
modify the alpha channel.
The first stage of the converter converts the color format. The original color format of the
foreground pixel and background pixels are configured through the CM[3:0] bits of the
DMA2D_FGPFCCR and DMA2D_BGPFCCR, respectively.
The supported input formats are given in Table 34: Supported color mode in input.
Table 34. Supported color mode in input
CM[3:0]
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Color mode
0000
ARGB8888
0001
RGB888
0010
RGB565
0011
ARGB1555
0100
ARGB4444
0101
L8
0110
AL44
0111
AL88
1000
L4
1001
A8
1010
A4
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The color format are coded as follows:
•
Alpha value field: transparency
0xFF value corresponds to an opaque pixel and 0x00 to a transparent one.
•
R field for Red
•
G field for Green
•
B field for Blue
•
L field: luminance
This field is the index to a CLUT to retrieve the three/four RGB/ARGB components.
If the original format was direct color mode (ARGB/RGB), then the extension to 8-bit per
channel is performed by copying the MSBs into the LSBs. This ensures a perfect linearity of
the conversion.
If the original format is indirect color mode (L/AL), a CLUT is required and each pixel format
converter is associated with a 256 entry 32-bit CLUT.
If the original format does not include an alpha channel, the alpha value is automatically set
to 0xFF (opaque).
For the specific alpha mode A4 and A8, no color information is stored nor indexed. The color
to be used for the image generation is fixed and is defined in the DMA2D_FGCOLR for
foreground pixels and in the DMA2D_BGCOLR register for background pixels.
The order of the fields in the system memory is defined in Table 35: Data order in memory.
Table 35. Data order in memory
Color Mode
@+3
@+2
@+1
@+0
ARGB8888
A0[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
B1[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
G2[7:0]
B2[7:0]
R1[7:0]
G1[7:0]
R3[7:0]
G3[7:0]
B3[7:0]
R2[7:0]
RGB565
R1[4:0]G1[5:3]
G1[2:0]B1[4:0]
R0[4:0]G0[5:3]
G0[2:0]B0[4:0]
ARGB1555
A1[0]R1[4:0]G1[4:3]
G1[2:0]B1[4:0]
A0[0]R0[4:0]G0[4:3]
G0[2:0]B0[4:0]
ARGB4444
A1[3:0]R1[3:0]
G1[3:0]B1[3:0]
A0[3:0]R0[3:0]
G0[3:0]B0[3:0]
L8
L3[7:0]
L2[7:0]
L1[7:0]
L0[7:0]
AL44
A3[3:0]L3[3:0]
A2[3:0]L2[3:0]
A1[3:0]L1[3:0]
A0[3:0]L0[3:0]
AL88
A1[7:0]
L1[7:0]
A0[7:0]
L0[7:0]
L4
L7[3:0]L6[3:0]
L5[3:0]L4[3:0]
L3[3:0]L2[3:0]
L1[3:0]L0[3:0]
A8
A3[7:0]
A2[7:0]
A1[7:0]
A0[7:0]
A4
A7[3:0]A6[3:0]
A5[3:0]A4[3:0]
A3[3:0]A2[3:0]
A1[3:0]A0[3:0]
RGB888
The 24-bit RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
Once the 32-bit value is generated, the alpha channel can be modified according to the
AM[1:0] field of the DMA2D_FGPFCCR/DMA2D_BGPFCCR registers as shown in
Table 36: Alpha mode configuration.
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The alpha channel can be:
•
kept as it is (no modification),
•
replaced by the ALPHA[7:0] value of DMA2D_FGPFCCR/DMA2D_BGPFCCR,
•
or replaced by the original alpha value multiplied by the ALPHA[7:0] value of
DMA2D_FGPFCCR/DMA2D_BGPFCCR divided by 255.
Table 36. Alpha mode configuration
9.3.5
AM[1:0]
Alpha mode
00
No modification
01
Replaced by value in DMA2D_xxPFCCR
10
Replaced by original value multiplied by the value in DMA2D_xxPFCCR / 255
11
Reserved
DMA2D foreground and background CLUT interface
The CLUT interface manages the CLUT memory access and the automatic loading of the
CLUT.
Three kinds of accesses are possible:
•
CLUT read by the PFC during pixel format conversion operation
•
CLUT accessed through the AHB slave port when the CPU is reading or writing data
into the CLUT
•
CLUT written through the AHB master port when an automatic loading of the CLUT is
performed
The CLUT memory loading can be done in two different ways:
•
Automatic loading
The following sequence should be followed to load the CLUT:
a)
Program the CLUT address into the DMA2D_FGCMAR register (foreground
CLUT) or DMA2D_BGCMAR register (background CLUT)
b)
Program the CLUT size in the CS[7:0] field of the DMA2D_FGPFCCR register
(foreground CLUT) or DMA2D_BGPFCCR register (background CLUT).
c)
Set the START bit of the DMA2D_FGPFCCR register (foreground CLUT) or
DMA2D_BGPFCCR register (background CLUT) to start the transfer. During this
automatic loading process, the CLUT is not accessible by the CPU. If a conflict
occurs, a CLUT access error interrupt is raised assuming CAEIE is set to ‘1’ in
DMA2D_CR.
•
Manual loading
The application has to program the CLUT manually through the DMA2D AHB slave
port to which the local CLUT memory is mapped.The foreground CLUT is located at
address offset 0x0400 and the background CLUT at address offset 0x0800.
The CLUT format can be 24 or 32 bits. It is configured through the CCM bit of the
DMA2D_FGPFCCR register (foreground CLUT) or DMA2D_BGPFCCR register
(background CLUT) as shown in Table 37: Supported CLUT color mode.
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Table 37. Supported CLUT color mode
CCM
CLUT color mode
0
32-bit ARGB8888
1
24-bit RGB888
The way the CLUT data are organized in the system memory is specified in Table 38: CLUT
data order in system memory.
Table 38. CLUT data order in system memory
CLUT Color Mode
ARGB8888
RGB888
9.3.6
@+3
@+2
@+1
@+0
A0[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
B1[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
G2[7:0]
B2[7:0]
R1[7:0]
G1[7:0]
R3[7:0]
G3[7:0]
B3[7:0]
R2[7:0]
DMA2D blender
The DMA2D blender blends the source pixels by pair to compute the resulting pixel.
The blending is performed according to the following equation:
with αMult =
αFG . αBG
255
αOUT = αFG + αBG - αMult
COUT =
CFG.αFG + CBG.αBG - CBG.αMult
αOUT
with C = R or G or B
Division is rounded to the nearest lower integer
No configuration register is required by the blender. The blender usage depends on the
DMA2D operating mode defined in MODE[1:0] field of the DMA2D_CR register.
9.3.7
DMA2D output PFC
The output PFC performs the pixel format conversion from 32 bits to the output format
defined in the CM[2:0] field of the DMA2D output pixel format converter configuration
register (DMA2D_OPFCCR).
The supported output formats are given in Table 39: Supported color mode in output
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Table 39. Supported color mode in output
CM[2:0]
9.3.8
Color mode
000
ARGB8888
001
RGB888
010
RGB565
011
ARGB1555
100
ARGB4444
DMA2D output FIFO
The output FIFO programs the pixels according to the color format defined in the output
PFC.
The destination area is defined through a set of control registers:
•
DMA2D output memory address register (DMA2D_OMAR)
•
DMA2D output offset register (DMA2D_OOR)
•
DMA2D number of lines register (number of lines and pixel per lines) (DMA2D_NLR)
If the DMA2D operates in register-to-memory mode, the configured output rectangle is filled
by the color specified in the DMA2D output color register (DMA2D_OCOLR) which contains
a fixed 32-bit, 24-bit or 16-bit value. The format is selected by the CM[2:0] field of the
DMA2D_OPFCCR register.
The data are stored into the memory in the order defined in Table 40: Data order in memory
Table 40. Data order in memory
Color Mode
@+3
@+2
@+1
@+0
ARGB8888
A0[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
B1[7:0]
R0[7:0]
G0[7:0]
B0[7:0]
G2[7:0]
B2[7:0]
R1[7:0]
G1[7:0]
R3[7:0]
G3[7:0]
B3[7:0]
R2[7:0]
RGB565
R1[4:0]G1[5:3]
G1[2:0]B1[4:0]
R0[4:0]G0[5:3]
G0[2:0]B0[4:0]
ARGB1555
A1[0]R1[4:0]G1[4:3]
G1[2:0]B1[4:0]
A0[0]R0[4:0]G0[4:3]
G0[2:0]B0[4:0]
ARGB4444
A1[3:0]R1[3:0]
G1[3:0]B1[3:0]
A0[3:0]R0[3:0]
G0[3:0]B0[3:0]
RGB888
The RGB888 aligned on 32-bit is supported through the ARGB8888 mode.
9.3.9
DMA2D AHB master port timer
An 8-bit timer is embedded into the AHB master port to provide an optional limitation of the
bandwidth on the crossbar.
This timer is clocked by the AHB clock and counts a dead time between two consecutive
accesses. This limits the bandwidth usage.
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The timer enabling and the dead time value are configured through the AHB master port
timer configuration register (DMA2D_AMPTCR).
9.3.10
DMA2D transactions
DMA2D transactions consist of a sequence of a given number of data transfers. The
number of data and the width can be programmed by software.
Each DMA2D data transfer is composed of up to 4 steps:
9.3.11
1.
Data loading from the memory location pointed by the DMA2D_FGMAR register and
pixel format conversion as defined in DMA2D_FGCR.
2.
Data loading from a memory location pointed by the DMA2D_BGMAR register and
pixel format conversion as defined in DMA2D_BGCR.
3.
Blending of all retrieved pixels according to the alpha channels resulting of the PFC
operation on alpha values.
4.
Pixel format conversion of the resulting pixels according to the DMA2D_OCR register
and programming of the data to the memory location addressed through the
DMA2D_OMAR register.
DMA2D configuration
Both source and destination data transfers can target peripherals and memories in the
whole 4 Gbyte memory area, at addresses ranging between 0x0000 0000 and
0xFFFF FFFF.
The DMA2D can operate in any of the four following modes selected through MODE[1:0]
bits of the DMA2D_CR register:
•
Register-to-memory
•
Memory-to-memory
•
Memory-to-memory with PFC
•
Memory-to-memory with PFC and blending
Register-to-memory
The register-to-memory mode is used to fill a user defined area with a predefined color.
The color format is set in the DMA2D_OPFCCR.
The DMA2D does not perform any data fetching from any source. It just writes the color
defined in the DMA2D_OCOLR register to the area located at the address pointed by the
DMA2D_OMAR and defined in the DMA2D_NLR and DMA2D_OOR.
Memory-to-memory
In memory-to-memory mode, the DMA2D does not perform any graphical data
transformation. The foreground input FIFO acts as a buffer and the data are transferred
from the source memory location defined in DMA2D_FGMAR to the destination memory
location pointed by DMA2D_OMAR.
The color mode programmed in the CM[3:0] bits of the DMA2D_FGPFCCR register defines
the number of bits per pixel for both input and output.
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The size of the area to be transferred is defined by the DMA2D_NLR and DMA2D_FGOR
registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the
destination.
Memory-to-memory with PFC
In this mode, the DMA2D performs a pixel format conversion of the source data and stores
them in the destination memory location.
The size of the areas to be transferred are defined by the DMA2D_NLR and DMA2D_FGOR
registers for the source, and by DMA2D_NLR and DMA2D_OOR registers for the
destination.
Data are fetched from the location defined in the DMA2D_FGMAR register and processed
by the foreground PFC. The original pixel format is configured through the
DMA2D_FGPFCCR register.
If the original pixel format is direct color mode, then the color channels are all expanded to 8
bits.
If the pixel format is indirect color mode, the associated CLUT has to be loaded into the
CLUT memory.
The CLUT loading can be done automatically by following the sequence below:
1.
Set the CLUT address into the DMA2D_FGCMAR.
2.
Set the CLUT size in the CS[7:0] bits of the DMA2D_FGPFCCR register.
3.
Set the CLUT format (24 or 32 bits) in the CCM bit of the DMA2D_FGPFCCR register.
4.
Start the CLUT loading by setting the START bit of the DMA2D_FGPFCCR register.
Once the CLUT loading is complete, the CTCIF flag of the DMA2D_IFR register is raised,
and an interrupt is generated if the CTCIE bit is set in DMA2D_CR. The automatic CLUT
loading process can not work in parallel with classical DMA2D transfers.
The CLUT can also be filled by the CPU or by any other master through the APB port. The
access to the CLUT is not possible when a DMA2D transfer is ongoing and uses the CLUT
(indirect color format).
In parallel to the color conversion process, the alpha value can be added or changed
depending on the value programmed in the DMA2D_FGPFCCR register. If the original
image does not have an alpha channel, a default alpha value of 0xFF is automatically added
to obtain a fully opaque pixel. The alpha value can be modified according to the AM[1:0] bits
of the DMA2D_FGPFCCR register:
•
It can be unchanged.
•
It can be replaced by the value defined in the ALPHA[7:0] value of the
DMA2D_FGPFCCR register.
•
It can be replaced by the original value multiplied by the ALPHA[7:0] value of the
DMA2D_FGPFCCR register divided by 255.
The resulting 32-bit data are encoded by the OUT PFC into the format specified by the
CM[2:0] field of the DMA2D_OPFCCR register. The output pixel format cannot be the
indirect mode since no CLUT generation process is supported.
The processed data are written into the destination memory location pointed by
DMA2D_OMAR.
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Memory-to-memory with PFC and blending
In this mode, 2 sources are fetched in the foreground FIFO and background FIFO from the
memory locations defined by DMA2D_FGMAR and DMA2D_BGMAR.
The two pixel format converters have to be configured as described in the memory-tomemory mode. Their configurations can be different as each pixel format converter are
independent and have their own CLUT memory.
Once each pixel has been converted into 32 bits by their respective PFCs, they are blended
according to the equation below:
with αMult =
αFG . αBG
255
αOUT = αFG + αBG - αMult
COUT =
CFG.αFG + CBG.αBG - CBG.αMult
αOUT
with C = R or G or B
Division are rounded to the nearest lower integer
The resulting 32-bit pixel value is encoded by the output PFC according to the specified
output format, and the data are written into the destination memory location pointed by
DMA2D_OMAR.
Configuration error detection
The DMA2D checks that the configuration is correct before any transfer. The configuration
error interrupt flag is set by hardware when a wrong configuration is detected when a new
transfer/automatic loading starts. An interrupt is then generated if the CEIE bit of the
DMA2D_CR is set.
The wrong configurations that can be detected are listed below:
•
Foreground CLUT automatic loading: MA bits of DMA2D_FGCMAR are not aligned
with CCM of DMA2D_FGPFCCR.
•
Background CLUT automatic loading: MA bits of DMA2D_BGCMAR are not aligned
with CCM of DMA2D_BGPFCCR
•
Memory transfer (except in register-to-memory mode): MA bits of DMA2D_FGMAR are
not aligned with CM of DMA2D_FGPFCCR
•
Memory transfer (except in register-to-memory mode): CM bits of DMA2D_FGPFCCR
are invalid
•
Memory transfer (except in register-to-memory mode): PL bits of DMA2D_NLR are odd
while CM of DMA2D_FGPFCCR is A4 or L4
•
Memory transfer (except in register-to-memory mode): LO bits of DMA2D_FGOR are
odd while CM of DMA2D_FGPFCCR is A4 or L4
•
Memory transfer (only in blending mode): MA bits of DMA2D_BGMAR are not aligned
with the CM of DMA2D_BGPFCCR
•
Memory transfer: (only in blending mode) CM bits of DMA2D_BGPFCCR are invalid
•
Memory transfer (only in blending mode): PL bits of DMA2D_NLR odd while CM of
DMA2D_BGPFCCR is A4 or L4
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•
Memory transfer (only in blending mode): LO bits of DMA2D_BGOR are odd while CM
of DMA2D_BGPFCCR is A4 or L4
•
Memory transfer (except in memory to memory mode): MA bits of DMA2D_OMAR are
not aligned with CM bits of DMA2D_OPFCCR.
•
Memory transfer (except in memory to memory mode): CM bits of DMA2D_OPFCCR
are invalid
•
Memory transfer: NL bits of DMA2D_NLR = 0
•
Memory transfer: PL bits of DMA2D_NLR = 0
DMA2D transfer control (start, suspend, abort and completion)
Once the DMA2D is configured, the transfer can be launched by setting the START bit of the
DMA2D_CR register. Once the transfer is completed, the START bit is automatically reset
and the TCIF flag of the DMA2D_ISR register is raised. An interrupt can be generated if the
TCIE bit of the DMA2D_CR is set.
The user application can suspend the DMA2D at any time by setting the SUSP bit of the
DMA2D_CR register. The transaction can then be aborted by setting the ABORT bit of the
DMA2D_CR register or can be restarted by resetting the SUSP bit of the DMA2D_CR
register.
The user application can abort at any time an ongoing transaction by setting the ABORT bit
of the DMA2D_CR register. In this case, the TCIF flag is not raised.
Automatic CLUT transfers can also be aborted or suspended by using the ABORT or the
SUSP bit of the DMA2D_CR register.
9.3.13
Watermark
A watermark can be programmed to generate an interrupt when the last pixel of a given line
has been written to the destination memory area.
The line number is defined in the LW[15:0] field of the DMA2D_LWR register.
When the last pixel of this line has been transferred, the TWIF flag of the DMA2D_ISR
register is raised and an interrupt is generated if the TWIE bit of the DMA2D_CR is set.
9.3.14
Error management
Two kind of errors can be triggered:
•
AHB master port errors signaled by the TEIF flag of the DMA2D_ISR register.
•
Conflicts caused by CLUT access (CPU trying to access the CLUT while a CLUT
loading or a DMA2D transfer is ongoing) signalled by the CAEIF flag of the
DMA2D_ISR register.
Both flags are associated to their own interrupt enable flag in the DMA2D_CR register to
generate an interrupt if need be (TEIE and CAEIE).
9.3.15
AHB dead time
To limit the AHB bandwidth usage, a dead time between two consecutive AHB accesses
can be programmed.
This feature can be enabled by setting the EN bit in the DMA2D_AMTCR register.
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The dead time value is stored in the DT[7:0] field of the DMA2D_AMTCR register. This
value represents the guaranteed minimum number of cycles between two consecutive
transactions on the AHB bus.
The update of the dead time value while the DMA2D is running will be taken into account for
the next AHB transfer.
9.4
DMA2D interrupts
An interrupt can be generated on the following events:
•
Configuration error
•
CLUT transfer complete
•
CLUT access error
•
Transfer watermark reached
•
Transfer complete
•
Transfer error
Separate interrupt enable bits are available for flexibility.
Table 41. DMA2D interrupt requests
Interrupt event
Event flag
Enable control bit
CEIF
CEIE
CLUT transfer complete
CTCIF
CTCIE
CLUT access error
CAEIF
CAEIE
Transfer watermark
TWF
TWIE
Transfer complete
TCIF
TCIE
Transfer error
TEIF
TEIE
Configuration error
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9.5
DMA2D registers
9.5.1
DMA2D control register (DMA2D_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
CEIE
CTCIE
CAEIE
TWIE
TCIE
TEIE
Res.
Res.
Res.
Res.
Res.
ABORT
SUSP
START
rw
rw
rw
rw
rw
rw
rs
rw
rs
MODE[1:0]
Bits 31:18 Reserved, must be kept at reset value
Bits 17:16 MODE[1:0]: DMA2D mode
These bits are set and cleared by software. They cannot be modified while a transfer is
ongoing.
00: Memory-to-memory (FG fetch only)
01: Memory-to-memory with PFC (FG fetch only with FG PFC active)
10: Memory-to-memory with blending (FG and BG fetch with PFC and blending)
11: Register-to-memory (no FG nor BG, only output stage active)
Bits 15:14 Reserved, must be kept at reset value
Bit 13 CEIE: Configuration Error Interrupt Enable
This bit is set and cleared by software.
0: CE interrupt disable
1: CE interrupt enable
Bit 12 CTCIE: CLUT transfer complete interrupt enable
This bit is set and cleared by software.
0: CTC interrupt disable
1: CTC interrupt enable
Bit 11 CAEIE: CLUT access error interrupt enable
This bit is set and cleared by software.
0: CAE interrupt disable
1: CAE interrupt enable
Bit 10 TWIE: Transfer watermark interrupt enable
This bit is set and cleared by software.
0: TW interrupt disable
1: TW interrupt enable
Bit 9 TCIE: Transfer complete interrupt enable
This bit is set and cleared by software.
0: TC interrupt disable
1: TC interrupt enable
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Bit 8 TEIE: Transfer error interrupt enable
This bit is set and cleared by software.
0: TE interrupt disable
1: TE interrupt enable
Bits 7:3 Reserved, must be kept at reset value
Bit 2 ABORT: Abort
This bit can be used to abort the current transfer. This bit is set by software and is
automatically reset by hardware when the START bit is reset.
0: No transfer abort requested
1: Transfer abort requested
Bit 1 SUSP: Suspend
This bit can be used to suspend the current transfer. This bit is set and reset by
software. It is automatically reset by hardware when the START bit is reset.
0: Transfer not suspended
1: Transfer suspended
Bit 0 START: Start
This bit can be used to launch the DMA2D according to the parameters loaded in the
various configuration registers. This bit is automatically reset by the following events:
–
At the end of the transfer
–
When the data transfer is aborted by the user application by setting the ABORT
bit in DMA2D_CR
–
When a data transfer error occurs
–
When the data transfer has not started due to a configuration error or another
transfer operation already ongoing (automatic CLUT loading).
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9.5.2
RM0385
DMA2D Interrupt Status Register (DMA2D_ISR)
Address offset: 0x0004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CEIF
CTCIF
CAEIF
TWIF
TCIF
TEIF
r
r
r
r
r
r
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CEIF: Configuration error interrupt flag
This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or
DMA2D_BGPFCCR is set and a wrong configuration has been programmed.
Bit 4 CTCIF: CLUT transfer complete interrupt flag
This bit is set when the CLUT copy from a system memory area to the internal DMA2D
memory is complete.
Bit 3 CAEIF: CLUT access error interrupt flag
This bit is set when the CPU accesses the CLUT while the CLUT is being automatically
copied from a system memory to the internal DMA2D.
Bit 2 TWIF: Transfer watermark interrupt flag
This bit is set when the last pixel of the watermarked line has been transferred.
Bit 1 TCIF: Transfer complete interrupt flag
This bit is set when a DMA2D transfer operation is complete (data transfer only).
Bit 0 TEIF: Transfer error interrupt flag
This bit is set when an error occurs during a DMA transfer (data transfer or automatic
CLUT loading).
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.3
DMA2D interrupt flag clear register (DMA2D_IFCR)
Address offset: 0x0008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CCEIF CCTCIF CAECIF CTWIF
CTCIF
CTEIF
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:6 Reserved, must be kept at reset value
Bit 5 CCEIF: Clear configuration error interrupt flag
Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register
Bit 4 CCTCIF: Clear CLUT transfer complete interrupt flag
Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register
Bit 3 CAECIF: Clear CLUT access error interrupt flag
Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register
Bit 2 CTWIF: Clear transfer watermark interrupt flag
Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register
Bit 1 CTCIF: Clear transfer complete interrupt flag
Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register
Bit 0 CTEIF: Clear Transfer error interrupt flag
Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.4
RM0385
DMA2D foreground memory address register (DMA2D_FGMAR)
Address offset: 0x000C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 MA[31: 0]: Memory address
Address of the data used for the foreground image. This register can only be written
when data transfers are disabled. Once the data transfer has started, this register is
read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4bit per pixel format must be 8-bit aligned.
9.5.5
DMA2D foreground offset register (DMA2D_FGOR)
Address offset: 0x0010
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
rw
rw
rw
rw
rw
rw
LO[13:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line offset
Line offset used for the foreground expressed in pixel. This value is used to generate
the address. It is added at the end of each line to determine the starting address of the
next line.
These bits can only be written when data transfers are disabled. Once a data transfer
has started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
9.5.6
DMA2D background memory address register (DMA2D_BGMAR)
Address offset: 0x0014
Reset value: 0x0000 0000
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Chrom-Art Accelerator™ controller (DMA2D)
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31: 0 MA[31: 0]: Memory address
Address of the data used for the background image. This register can only be written
when data transfers are disabled. Once a data transfer has started, this register is readonly.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4bit per pixel format must be 8-bit aligned.
9.5.7
DMA2D background offset register (DMA2D_BGOR)
Address offset: 0x0018
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
rw
rw
rw
rw
rw
rw
LO[13:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line offset
Line offset used for the background image (expressed in pixel). This value is used for
the address generation. It is added at the end of each line to determine the starting
address of the next line.
These bits can only be written when data transfers are disabled. Once data transfer has
started, they become read-only.
If the image format is 4-bit per pixel, the line offset must be even.
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.8
RM0385
DMA2D foreground PFC control register (DMA2D_FGPFCCR)
Address offset: 0x001C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
ALPHA[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
CS[7:0]
rw
rw
rw
rw
rw
rw
rw
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
Res.
Res.
START
CCM
rs
rw
rw
17
16
AM[1:0]
rw
rw
1
0
rw
rw
CM[3:0]
rw
rw
Bits 31:24 ALPHA[7: 0]: Alpha value
These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied by the original alpha value according to the alpha mode selected
through the AM[1:0] bits.
These bits can only be written when data transfers are disabled. Once a transfer has
started, they become read-only.
Bits 23:18 Reserved, must be kept at reset value
Bits 17:16 AM[1: 0]: Alpha mode
These bits select the alpha channel value to be used for the foreground image. They
can only be written data the transfer are disabled. Once the transfer has started, they
become read-only.
00: No modification of the foreground image alpha channel value
01: Replace original foreground image alpha channel value by ALPHA[7: 0]
10: Replace original foreground image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
other configurations are meaningless
Bits 15:8 CS[7: 0]: CLUT size
These bits define the size of the CLUT used for the foreground image. Once the CLUT
transfer has started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value
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Chrom-Art Accelerator™ controller (DMA2D)
Bit 5 START: Start
This bit can be set to start the automatic loading of the CLUT. It is automatically reset:
–
at the end of the transfer
–
when the transfer is aborted by the user application by setting the ABORT bit in
DMA2D_CR
–
when a transfer error occurs
–
when the transfer has not started due to a configuration error or another
transfer operation already ongoing (data transfer or automatic background
CLUT transfer).
Bit 4 CCM: CLUT color mode
This bit defines the color format of the CLUT. It can only be written when the transfer is
disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3: 0]: Color mode
These bits defines the color format of the foreground image. They can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.9
RM0385
DMA2D foreground color register (DMA2D_FGCOLR)
Address offset: 0x0020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
23
22
21
rw
rw
rw
rw
19
18
17
16
RED[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
GREEN[7:0]
rw
20
BLUE[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value
Bits 23:16 RED[7: 0]: Red Value
These bits defines the red value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Bits 15:8 GREEN[7: 0]: Green Value
These bits defines the green value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
Bits 7:0 BLUE[7: 0]: Blue Value
These bits defines the blue value for the A4 or A8 mode of the foreground image. They
can only be written when data transfers are disabled. Once the transfer has started,
They are read-only.
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.10
DMA2D background PFC control register (DMA2D_BGPFCCR)
Address offset: 0x0024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
ALPHA[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
CS[7:0]
rw
rw
rw
rw
rw
rw
rw
23
22
21
20
19
18
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
Res.
Res.
START
CCM
rs
rw
rw
17
16
AM[1:0]
rw
rw
1
0
rw
rw
CM[3:0]
rw
rw
Bits 31:24 ALPHA[7: 0]: Alpha value
These bits define a fixed alpha channel value which can replace the original alpha value
or be multiplied with the original alpha value according to the alpha mode selected with
bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
Bits 23:18 Reserved, must be kept at reset value
Bits 17:16 AM[1: 0]: Alpha mode
These bits define which alpha channel value to be used for the background image.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
00: No modification of the foreground image alpha channel value
01: Replace original background image alpha channel value by ALPHA[7: 0]
10: Replace original background image alpha channel value by ALPHA[7:0] multiplied
with original alpha channel value
others: meaningless
Bits 15:8 CS[7: 0]: CLUT size
These bits define the size of the CLUT used for the BG. Once the CLUT transfer has
started, this field is read-only.
The number of CLUT entries is equal to CS[7:0] + 1.
Bits 7:6 Reserved, must be kept at reset value
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RM0385
Bit 5 START: Start
This bit is set to start the automatic loading of the CLUT. This bit is automatically reset:
–
at the end of the transfer
–
when the transfer is aborted by the user application by setting the ABORT bit in
the DMA2D_CR
–
when a transfer error occurs
–
when the transfer has not started due to a configuration error or another
transfer operation already on going (data transfer or automatic foreground
CLUT transfer).
Bit 4 CCM: CLUT Color mode
These bits define the color format of the CLUT. This register can only be written when
the transfer is disabled. Once the CLUT transfer has started, this bit is read-only.
0: ARGB8888
1: RGB888
others: meaningless
Bits 3:0 CM[3: 0]: Color mode
These bits define the color format of the foreground image. These bits can only be
written when data transfers are disabled. Once the transfer has started, they are readonly.
0000: ARGB8888
0001: RGB888
0010: RGB565
0011: ARGB1555
0100: ARGB4444
0101: L8
0110: AL44
0111: AL88
1000: L4
1001: A8
1010: A4
others: meaningless
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.11
DMA2D background color register (DMA2D_BGCOLR)
Address offset: 0x0028
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
23
22
21
rw
rw
rw
rw
19
18
17
16
RED[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
rw
GREEN[7:0]
rw
20
BLUE[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value
Bits 23:16 RED[7: 0]: Red Value
These bits define the red value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Bits 15:8 GREEN[7: 0]: Green Value
These bits define the green value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
Bits 7:0 BLUE[7: 0]: Blue Value
These bits define the blue value for the A4 or A8 mode of the background. These bits
can only be written when data transfers are disabled. Once the transfer has started,
they are read-only.
9.5.12
DMA2D foreground CLUT memory address register
(DMA2D_FGCMAR)
Address offset: 0x002C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
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RM0385
Bits 31: 0 MA[31: 0]: Memory Address
Address of the data used for the CLUT address dedicated to the foreground image. This
register can only be written when no transfer is ongoing. Once the CLUT transfer has
started, this register is read-only.
If the foreground CLUT format is 32-bit, the address must be 32-bit aligned.
9.5.13
DMA2D background CLUT memory address register
(DMA2D_BGCMAR)
Address offset: 0x0030
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31: 0 MA[31: 0]: Memory address
Address of the data used for the CLUT address dedicated to the background image.
This register can only be written when no transfer is on going. Once the CLUT transfer
has started, this register is read-only.
If the background CLUT format is 32-bit, the address must be 32-bit aligned.
9.5.14
DMA2D output PFC control register (DMA2D_OPFCCR)
Address offset: 0x0034
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CM[2:0]
rw
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rw
RM0385
Chrom-Art Accelerator™ controller (DMA2D)
Bits 31: 3 Reserved, must be kept at reset value
Bits 19:3 Reserved, must be kept at reset value
Bits 2:0 CM[2: 0]: Color mode
These bits define the color format of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
000: ARGB8888
001: RGB888
010: RGB565
011: ARGB1555
100: ARGB4444
others: meaningless
9.5.15
DMA2D output color register (DMA2D_OCOLR)
Address offset: 0x0038
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
ALPHA[7:0]
19
18
17
16
RED[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GREEN[7:0]
BLUE[7:0]
RED[4:0]
A
GREEN[5:0]
RED[4:0]
GREEN[4:0]
ALPHA[3:0]
rw
rw
rw
RED[3:0]
rw
BLUE[4:0]
rw
rw
rw
BLUE[4:0]
GREEN[3:0]
rw
rw
rw
rw
BLUE[3:0]
rw
rw
rw
rw
rw
Bits 31:24 ALPHA[7: 0]: Alpha Channel Value
These bits define the alpha channel of the output color. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 23:16 RED[7: 0]: Red Value
These bits define the red value of the output image. These bits can only be written when
data transfers are disabled. Once the transfer has started, they are read-only.
Bits 15:8 GREEN[7: 0]: Green Value
These bits define the green value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
Bits 7:0 BLUE[7: 0]: Blue Value
These bits define the blue value of the output image. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.16
RM0385
DMA2D output memory address register (DMA2D_OMAR)
Address offset: 0x003C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MA[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
MA[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31: 0 MA[31: 0]: Memory Address
Address of the data used for the output FIFO. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
The address alignment must match the image format selected e.g. a 32-bit per pixel
format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned.
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.17
DMA2D output offset register (DMA2D_OOR)
Address offset: 0x0040
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
rw
rw
rw
rw
rw
rw
LO[13:0]
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:14 Reserved, must be kept at reset value
Bits 13:0 LO[13: 0]: Line Offset
Line offset used for the output (expressed in pixels). This value is used for the address
generation. It is added at the end of each line to determine the starting address of the
next line. These bits can only be written when data transfers are disabled. Once the
transfer has started, they are read-only.
9.5.18
DMA2D number of line register (DMA2D_NLR)
Address offset: 0x0044
Reset value: 0x0000 0000
31
30
Res.
Res.
15
14
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PL[13:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
NL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value
Bits 29:16 PL[13: 0]: Pixel per lines
Number of pixels per lines of the area to be transferred. These bits can only be written
when data transfers are disabled. Once the transfer has started, they are read-only.
If any of the input image format is 4-bit per pixel, pixel per lines must be even.
Bits 15:0 NL[15: 0]: Number of lines
Number of lines of the area to be transferred. These bits can only be written when data
transfers are disabled. Once the transfer has started, they are read-only.
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Chrom-Art Accelerator™ controller (DMA2D)
9.5.19
RM0385
DMA2D line watermark register (DMA2D_LWR)
Address offset: 0x0048
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
LW[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value
Bits 15:0 LW[15:0]: Line watermark
These bits allow to configure the line watermark for interrupt generation.
An interrupt is raised when the last pixel of the watermarked line has been transferred.
These bits can only be written when data transfers are disabled. Once the transfer has
started, they are read-only.
9.5.20
DMA2D AHB master timer configuration register (DMA2D_AMTCR)
Address offset: 0x004C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EN
DT[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved
Bits 15:8 DT[7: 0]: Dead Time
Dead time value in the AHB clock cycle inserted between two consecutive accesses on
the AHB master port. These bits represent the minimum guaranteed number of cycles
between two consecutive AHB accesses.
Bits 7:1 Reserved
Bit 0 EN: Enable
Enables the dead time functionality.
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9.5.21
Chrom-Art Accelerator™ controller (DMA2D)
DMA2D register map
The following table summarizes the DMA2D registers. Refer to Section 2.2.2 on page 65 for
the DMA2D register base address.
CCEIF
CCTCIF
CAECIF
CTWIF
CTCIF
CTEIF
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA2D_FGOR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
LO[13:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
0
0
0
0
0
0
0
0
DMA2D_BGCOLR
Res.
Res.
Res.
Res.
Res.
ALPHA[7:0]
Res.
DMA2D_BGPFCCR
Reset value
AM[1:0]
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
RED[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
GREEN[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CS[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
RED[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA2D_FGCMAR
0
0
0
0
0
0
0
0
0
0
CM[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GREEN[7:0]
0
CM[3:0]
BLUE[7:0]
CCM
Res.
Reset value
0
START
DMA2D_FGCOLR
0
0
Res.
0
0
Res.
0
0
CS[7:0]
AM[1:0]
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Reset value
Res.
ALPHA[7:0]
Res.
DMA2D_FGPFCCR
Res.
0
Res.
Reset value
LO[13:0]
CCM
0
START
0
Res.
0
Res.
Reset value
DMA2D_BGOR
Reset value
0
MA[31:0]
Res.
DMA2D_BGMAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BLUE[7:0]
MA[31:0]
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA2D_OPFCCR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MA[31:0]
Res.
DMA2D_BGCMAR
Res.
0x0034
0
Res.
0x0030
0
Res.
0x002C
0
Res.
0x0028
SUSP
TEIF
0
Res.
0x0024
0
Res.
0x0020
0
Res.
0x001C
Reset value
Res.
0x0018
START
TCIF
0
MA[31:0]
Res.
0x0014
Res.
0
Res.
0x0010
ABORT
TWIF
0
Res.
0x000C
Res.
Res.
0
Reset value
DMA2D_FGMAR
0
CAEIF
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_IFCR
0
0
Reset value
0x0008
0
CTCIF
Res.
Res.
TEIE
0
CEIF
TCIE
0
Res.
TWIE
0
Res.
CAEIE
0
Res.
CTCIE
0
Res.
Res.
CEIE
0
Res.
Res.
Res.
0
Res.
MODE[1:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_ISR
Res.
0x0004
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMA2D_CR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x0000
Register
Res.
Offset
Res.
Table 42. DMA2D register map and reset values
Reset value
CM[2:0]
0
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0
0
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Chrom-Art Accelerator™ controller (DMA2D)
RM0385
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
Res. Res. Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMA2D_OOR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
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Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
Res.
0
0
0
0
0
0
RED[7:0][255:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LW[15:0]
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DT[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ALPHA[7:0][255:0]
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
GREEN[7:0][255:0]
0
Res.
0
BLUE[7:0][255:0]
Res.
Res.
Res.
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
Res.
DMA2D_BGCLUT
0
Res.
0
Res.
0x08000x0BFF
Reset value
0
Res.
0
Res.
DMA2D_FGCLUT
Res.
0x04000x07FC
Res.
Reserved
0
Res.
0
Reset value
0x0050Ox03FC
0
Res.
0
Res.
Res.
Res.
DMA2D_AMTCR
0
NL[15:0]
0
Reset value
0x004C
0
LO[13:0]
PL[13:0]
0
Res.
Res.
DMA2D_LWR
Res.
Reset value
0x0048
0
Res.
Res.
DMA2D_NLR
Res.
Reset value
0x0044
BLUE[3:0]
0
MA[31:0]
Res.
0x0040
GREEN[3:0]
0
Res.
0x003C
RED[3:0]
0
Res.
DMA2D_OMAR
ALPHA[3:0]
EN
Res. Res. Res.
0
Res.
Res. Res. Res.
0
Res.
Res. Res. Res.
0
BLUE[4:0]
Res.
Res. Res. Res.
0
GREEN[4:0]
Res.
Res. Res. Res.
0
RED[4:0]
BLUE[4:0]
Res.
Res. Res. Res.
0
BLUE[7:0]
GREEN[5:0]
Res.
Res. Res. Res.
A
RED[4:0]
Res.
Res. Res. Res.
Reset value
Res. Res. Res.
0x0038
GREEN[7:0]
Res. Res. Res.
DMA2D_OCOLR
RED[7:0]
Res. Res. Res.
ALPHA[7:0]
Res.
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 42. DMA2D register map and reset values (continued)
RED[7:0][255:0]
GREEN[7:0][255:0]
BLUE[7:0][255:0]
X X X X X X X X X X X X X X X X X X X X X X X X
DocID026670 Rev 6
RM0385
Nested vectored interrupt controller (NVIC)
10
Nested vectored interrupt controller (NVIC)
10.1
NVIC features
The nested vector interrupt controller NVIC includes the following features:
•
up to 98 maskable interrupt channels for STM32F75xxx and STM32F74xxx (not
including the 16 interrupt lines of Cortex®-M7 with FPU)
•
16 programmable priority levels (4 bits of interrupt priority are used)
•
low-latency exception and interrupt handling
•
power management control
•
implementation of system control registers
The NVIC and the processor core interface are closely coupled, which enables low latency
interrupt processing and efficient processing of late arriving interrupts.
All interrupts including the core exceptions are managed by the NVIC. For more information
on exceptions and NVIC programming, refer to programming manual PMxxxx.
10.1.1
SysTick calibration value register
The SysTick calibration value is fixed to 18750, which gives a reference time base of 1 ms
with the SysTick clock set to 18.75 MHz (HCLK/8, with HCLK set to 150 MHz).
10.1.2
Interrupt and exception vectors
See Table 43, for the vector table for the STM32F75xxx and STM32F74xxx devices.
Position
Priority
Table 43. STM32F75xxx and STM32F74xxx vector table
Type of
priority
-
-
-
-
-3
-
Acronym
Description
Address
-
Reserved
0x0000 0000
fixed
Reset
Reset
0x0000 0004
-2
fixed
NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked
to the NMI vector.
0x0000 0008
-
-1
fixed
HardFault
All class of fault
0x0000 000C
-
0
settable
MemManage
Memory management
0x0000 0010
-
1
settable
BusFault
Pre-fetch fault, memory access fault
0x0000 0014
-
2
settable
UsageFault
Undefined instruction or illegal state
0x0000 0018
-
-
-
-
Reserved
DocID026670 Rev 6
0x0000 001C - 0x0000
002B
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RM0385
Position
Priority
Table 43. STM32F75xxx and STM32F74xxx vector table (continued)
Type of
priority
-
3
settable
SVCall
System service call via SWI
instruction
0x0000 002C
-
4
settable
Debug Monitor
Debug Monitor
0x0000 0030
-
-
-
-
Reserved
0x0000 0034
-
5
settable
PendSV
Pendable request for system service
0x0000 0038
-
6
settable
SysTick
System tick timer
0x0000 003C
0
7
settable
WWDG
Window Watchdog interrupt
0x0000 0040
1
8
settable
PVD
PVD through EXTI line detection
interrupt
0x0000 0044
2
9
settable
TAMP_STAMP
Tamper and TimeStamp interrupts
through the EXTI line
0x0000 0048
3
10
settable
RTC_WKUP
RTC Wakeup interrupt through the
EXTI line
0x0000 004C
4
11
settable
FLASH
Flash global interrupt
0x0000 0050
5
12
settable
RCC
RCC global interrupt
0x0000 0054
6
13
settable
EXTI0
EXTI Line0 interrupt
0x0000 0058
7
14
settable
EXTI1
EXTI Line1 interrupt
0x0000 005C
8
15
settable
EXTI2
EXTI Line2 interrupt
0x0000 0060
9
16
settable
EXTI3
EXTI Line3 interrupt
0x0000 0064
10
17
settable
EXTI4
EXTI Line4 interrupt
0x0000 0068
11
18
settable
DMA1_Stream0
DMA1 Stream0 global interrupt
0x0000 006C
12
19
settable
DMA1_Stream1
DMA1 Stream1 global interrupt
0x0000 0070
13
20
settable
DMA1_Stream2
DMA1 Stream2 global interrupt
0x0000 0074
14
21
settable
DMA1_Stream3
DMA1 Stream3 global interrupt
0x0000 0078
15
22
settable
DMA1_Stream4
DMA1 Stream4 global interrupt
0x0000 007C
16
23
settable
DMA1_Stream5
DMA1 Stream5 global interrupt
0x0000 0080
17
24
settable
DMA1_Stream6
DMA1 Stream6 global interrupt
0x0000 0084
18
25
settable
ADC
ADC1, ADC2 and ADC3 global
interrupts
0x0000 0088
19
26
settable
CAN1_TX
CAN1 TX interrupts
0x0000 008C
20
27
settable
CAN1_RX0
CAN1 RX0 interrupts
0x0000 0090
21
28
settable
CAN1_RX1
CAN1 RX1 interrupt
0x0000 0094
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Acronym
Description
DocID026670 Rev 6
Address
RM0385
Nested vectored interrupt controller (NVIC)
Position
Priority
Table 43. STM32F75xxx and STM32F74xxx vector table (continued)
Type of
priority
22
29
settable
CAN1_SCE
CAN1 SCE interrupt
0x0000 0098
23
30
settable
EXTI9_5
EXTI Line[9:5] interrupts
0x0000 009C
24
31
settable
TIM1_BRK_TIM9
TIM1 Break interrupt and TIM9 global
interrupt
0x0000 00A0
25
32
settable
TIM1_UP_TIM10
TIM1 Update interrupt and TIM10
global interrupt
0x0000 00A4
26
33
settable
TIM1_TRG_COM_TIM11
TIM1 Trigger and Commutation
interrupts and TIM11 global interrupt
0x0000 00A8
27
34
settable
TIM1_CC
TIM1 Capture Compare interrupt
0x0000 00AC
28
35
settable
TIM2
TIM2 global interrupt
0x0000 00B0
29
36
settable
TIM3
TIM3 global interrupt
0x0000 00B4
30
37
settable
TIM4
TIM4 global interrupt
0x0000 00B8
Acronym
Description
2C1
event interrupt
31
38
settable
I2C1_EV
I
32
39
settable
I2C1_ER
I2C1 error interrupt
33
40
settable
Address
0x0000 00BC
0x0000 00C0
I2C2_EV
I
2C2
event interrupt
0x0000 00C4
error interrupt
0x0000 00C8
34
41
settable
I2C2_ER
I2C2
35
42
settable
SPI1
SPI1 global interrupt
0x0000 00CC
36
43
settable
SPI2
SPI2 global interrupt
0x0000 00D0
37
44
settable
USART1
USART1 global interrupt
0x0000 00D4
38
45
settable
USART2
USART2 global interrupt
0x0000 00D8
39
46
settable
USART3
USART3 global interrupt
0x0000 00DC
40
47
settable
EXTI15_10
EXTI Line[15:10] interrupts
0x0000 00E0
41
48
settable
RTC_Alarm
RTC Alarms (A and B) through EXTI
line interrupt
0x0000 00E4
42
49
settable
OTG_FS WKUP
USB On-The-Go FS Wakeup through
EXTI line interrupt
0x0000 00E8
43
50
settable
TIM8_BRK_TIM12
TIM8 Break interrupt and TIM12
global interrupt
0x0000 00EC
44
51
settable
TIM8_UP_TIM13
TIM8 Update interrupt and TIM13
global interrupt
0x0000 00F0
45
52
settable
TIM8_TRG_COM_TIM14
TIM8 Trigger and Commutation
interrupts and TIM14 global interrupt
0x0000 00F4
46
53
settable
TIM8_CC
TIM8 Capture Compare interrupt
0x0000 00F8
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RM0385
Position
Priority
Table 43. STM32F75xxx and STM32F74xxx vector table (continued)
Type of
priority
47
54
settable
DMA1_Stream7
DMA1 Stream7 global interrupt
0x0000 00FC
48
55
settable
FSMC
FSMC global interrupt
0x0000 0100
49
56
settable
SDMMC1
SDMMC1 global interrupt
0x0000 0104
50
57
settable
TIM5
TIM5 global interrupt
0x0000 0108
51
58
settable
SPI3
SPI3 global interrupt
0x0000 010C
52
59
settable
UART4
UART4 global interrupt
0x0000 0110
53
60
settable
UART5
UART5 global interrupt
0x0000 0114
54
61
settable
TIM6_DAC
TIM6 global interrupt,
DAC1 and DAC2 underrun error
interrupts
0x0000 0118
55
62
settable
TIM7
TIM7 global interrupt
0x0000 011C
56
63
settable
DMA2_Stream0
DMA2 Stream0 global interrupt
0x0000 0120
57
64
settable
DMA2_Stream1
DMA2 Stream1 global interrupt
0x0000 0124
58
65
settable
DMA2_Stream2
DMA2 Stream2 global interrupt
0x0000 0128
59
66
settable
DMA2_Stream3
DMA2 Stream3 global interrupt
0x0000 012C
60
67
settable
DMA2_Stream4
DMA2 Stream4 global interrupt
0x0000 0130
61
68
settable
ETH
Ethernet global interrupt
0x0000 0134
62
69
settable
ETH_WKUP
Ethernet Wakeup through EXTI line
interrupt
0x0000 0138
63
70
settable
CAN2_TX
CAN2 TX interrupts
0x0000 013C
64
71
settable
CAN2_RX0
CAN2 RX0 interrupts
0x0000 0140
65
72
settable
CAN2_RX1
CAN2 RX1 interrupt
0x0000 0144
66
73
settable
CAN2_SCE
CAN2 SCE interrupt
0x0000 0148
67
74
settable
OTG_FS
USB On The Go FS global interrupt
0x0000 014C
68
75
settable
DMA2_Stream5
DMA2 Stream5 global interrupt
0x0000 0150
69
76
settable
DMA2_Stream6
DMA2 Stream6 global interrupt
0x0000 0154
70
77
settable
DMA2_Stream7
DMA2 Stream7 global interrupt
0x0000 0158
71
78
settable
USART6
USART6 global interrupt
0x0000 015C
Acronym
Description
2C3
event interrupt
Address
0x0000 0160
72
79
settable
I2C3_EV
I
73
80
settable
I2C3_ER
I2C3 error interrupt
0x0000 0164
74
81
settable
OTG_HS_EP1_OUT
USB On The Go HS End Point 1 Out
global interrupt
0x0000 0168
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Nested vectored interrupt controller (NVIC)
Position
Priority
Table 43. STM32F75xxx and STM32F74xxx vector table (continued)
Type of
priority
75
82
settable
OTG_HS_EP1_IN
USB On The Go HS End Point 1 In
global interrupt
0x0000 016C
76
83
settable
OTG_HS_WKUP
USB On The Go HS Wakeup through
EXTI interrupt
0x0000 0170
77
84
settable
OTG_HS
USB On The Go HS global interrupt
0x0000 0174
78
85
settable
DCMI
DCMI global interrupt
0x0000 0178
79
86
settable
CRYP
CRYP crypto global interrupt
0x0000 017C
80
87
settable
HASH_RNG
Hash and Rng global interrupt
0x0000 0180
81
88
settable
FPU
FPU global interrupt
0x0000 0184
82
89
settable
UART7
UART7 global interrupt
0x0000 0188
83
90
settable
UART8
UART8 global interrupt
0x0000 018C
84
91
settable
SPI4
SPI4 global interrupt
0x0000 0190
85
92
settable
SPI5
SPI5 global interrupt
0x0000 0194
86
93
settable
SPI6
SPI6 global interrupt
0x0000 0198
87
94
settable
SAI1
SAI1 global interrupt
0x0000 019C
88
95
settable
LCD-TFT
LCD-TFT global interrupt
0x0000 01A0
89
96
settable
LCD-TFT
LCD-TFT global Error interrupt
0x0000 01A4
90
97
settable
DMA2D
DMA2D global interrupt
0x0000 01A8
91
98
settable
SAI2
SAI2 global interrupt
0x0000 01AC
92
99
settable
QuadSPI
QuadSPI global interrupt
0x0000 01B0
93
100
settable
LP Timer1
LP Timer1 global interrupt
0x0000 01B4
94
101
settable
HDMI-CEC
HDMI-CEC global interrupt
0x0000 01B8
95
102
settable
I2C4_EV
I2C4 event interrupt
0x0000 01BC
96
103
settable
I2C4_ER
I2C4 Error interrupt
0x0000 01C0
97
104
settable
SPDIFRX
SPDIFRX global interrupt
0x0000 01C4
Acronym
Description
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Address
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Extended interrupts and events controller (EXTI)
11
RM0385
Extended interrupts and events controller (EXTI)
The external interrupt/event controller consists of up to 24 edge detectors for generating
event/interrupt requests. Each input line can be independently configured to select the type
(interrupt or event) and the corresponding trigger event (rising or falling or both). Each line
can also masked independently. A pending register maintains the status line of the interrupt
requests.
11.1
EXTI main features
The main features of the EXTI controller are the following:
11.2
•
independent trigger and mask on each interrupt/event line
•
dedicated status bit for each interrupt line
•
generation of up to 24 software event/interrupt requests
•
detection of external signals with a pulse width lower than the APB2 clock period. Refer
to the electrical characteristics section of the STM32F75xxx and STM32F74xxx
datasheets for details on this parameter.
EXTI block diagram
Figure 29 shows the block diagram.
Figure 29. External interrupt/event controller block diagram
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11.3
Extended interrupts and events controller (EXTI)
Wakeup event management
The STM32F75xxx and STM32F74xxx devices are able to handle external or internal
events in order to wake up the core (WFE). The wakeup event can be generated either by:
•
enabling an interrupt in the peripheral control register but not in the NVIC, and enabling
the SEVONPEND bit in the Cortex®-M7 System Control register. When the MCU
resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ
channel pending bit (in the NVIC interrupt clear pending register) have to be cleared.
•
or configuring an external or internal EXTI line in event mode. When the CPU resumes
from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC
IRQ channel pending bit as the pending bit corresponding to the event line is not set.
To use an external line as a wakeup event, refer to Section 11.4: Functional description.
11.4
Functional description
To generate the interrupt, the interrupt line should be configured and enabled. This is done
by programming the two trigger registers with the desired edge detection and by enabling
the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register.
When the selected edge occurs on the external interrupt line, an interrupt request is
generated. The pending bit corresponding to the interrupt line is also set. This request is
reset by writing a ‘1’ in the pending register.
To generate the event, the event line should be configured and enabled. This is done by
programming the two trigger registers with the desired edge detection and by enabling the
event request by writing a ‘1’ to the corresponding bit in the event mask register. When the
selected edge occurs on the event line, an event pulse is generated. The pending bit
corresponding to the event line is not set.
An interrupt/event request can also be generated by software by writing a ‘1’ in the software
interrupt/event register.
11.5
Hardware interrupt selection
To configure a line as interrupt sources, use the following procedure:
11.6
1.
Configure the corresponding mask bit (EXTI_IMR)
2.
Configure the Trigger selection bits of the interrupt lines (EXTI_RTSR and EXTI_FTSR)
3.
Configure the enable and mask bits that control the NVIC IRQ channel mapped to the
external interrupt controller (EXTI) so that an interrupt coming from one of the 24 lines
can be correctly acknowledged.
Hardware event selection
To configure a line as event sources, use the following procedure:
1.
Configure the corresponding mask bit (EXTI_EMR)
2.
Configure the Trigger selection bits of the event line (EXTI_RTSR and EXTI_FTSR)
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Extended interrupts and events controller (EXTI)
11.7
RM0385
Software interrupt/event selection
The line can be configured as software interrupt/event line. The following is the procedure to
generate a software interrupt.
11.8
1.
Configure the corresponding mask bit (EXTI_IMR, EXTI_EMR)
2.
Set the required bit in the software interrupt register (EXTI_SWIER)
External interrupt/event line mapping
Up to 168 GPIOs are connected to the 16 external interrupt/event lines in the following
manner:
Figure 30. External interrupt/event GPIO mapping
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Extended interrupts and events controller (EXTI)
The eight other EXTI lines are connected as follows:
11.9
•
EXTI line 16 is connected to the PVD output
•
EXTI line 17 is connected to the RTC Alarm event
•
EXTI line 18 is connected to the USB OTG FS Wakeup event
•
EXTI line 19 is connected to the Ethernet Wakeup event
•
EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
•
EXTI line 21 is connected to the RTC Tamper and TimeStamp events
•
EXTI line 22 is connected to the RTC Wakeup event
•
EXTI line 23 is connected to the LPTIM1 asynchronous event
EXTI registers
Refer to Section 1.1 on page 59 for a list of abbreviations used in register descriptions.
11.9.1
Interrupt mask register (EXTI_IMR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IM23
IM22
IM21
IM20
IM19
IM18
IM17
IM16
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IM15
IM14
IM13
IM12
IM11
IM10
IM9
IM8
IM7
IM6
IM5
IM4
IM3
IM2
IM1
IM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 IMx: Interrupt mask on line x
0: Interrupt request from line x is masked
1: Interrupt request from line x is not masked
11.9.2
Event mask register (EXTI_EMR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EM23
EM22
EM21
EM20
EM19
EM18
EM17
EM16
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EM15
EM14
EM13
EM12
EM11
EM10
EM9
EM8
EM7
EM6
EM5
EM4
EM3
EM2
EM1
EM0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
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RM0385
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 EMx: Event mask on line x
0: Event request from line x is masked
1: Event request from line x is not masked
11.9.3
Rising trigger selection register (EXTI_RTSR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TR23
TR22
TR21
TR20
TR19
TR18
TR17
TR16
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 TRx: Rising trigger event configuration bit of line x
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a rising edge occurs on the external interrupt line while writing to the EXTI_RTSR register,
the pending bit is be set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
11.9.4
Falling trigger selection register (EXTI_FTSR)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
TR23
TR22
TR21
TR20
TR19
TR18
TR17
TR16
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TR15
TR14
TR13
TR12
TR11
TR10
TR9
TR8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 TRx: Falling trigger event configuration bit of line x
0: Falling trigger disabled (for Event and Interrupt) for input line
1: Falling trigger enabled (for Event and Interrupt) for input line.
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Note:
The external wakeup lines are edge triggered, no glitch must be generated on these lines.
If a falling edge occurs on the external interrupt line while writing to the EXTI_FTSR register,
the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this configuration,
both generate a trigger condition.
11.9.5
Software interrupt event register (EXTI_SWIER)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
SWIER SWIER SWIER SWIER SWIER SWIER SWIER
15
14
13
12
11
10
9
rw
rw
rw
rw
rw
rw
rw
23
22
21
20
19
18
17
16
SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
23
22
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER SWIER
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 SWIERx: Software Interrupt on line x
If interrupt are enabled on line x in the EXTI_IMR register, writing '1' to SWIERx bit when it is
set at '0' sets the corresponding pending bit in the EXTI_PR register, thus resulting in an
interrupt request generation.
This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to the bit).
11.9.6
Pending register (EXTI_PR)
Address offset: 0x14
Reset value: undefined
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
PR23
PR22
PR21
PR20
PR19
PR18
PR17
PR16
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PR15
PR14
PR13
PR12
PR11
PR10
PR9
PR8
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:0 PRx: Pending bit
0: No trigger request occurred
1: selected trigger request occurred
This bit is set when the selected edge event arrives on the external interrupt line.
This bit is cleared by programming it to ‘1’.
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11.9.7
RM0385
EXTI register map
Table 44 gives the EXTI register map and the reset values.
Res.
Res.
Res.
Res.
Res.
EXTI_IMR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
Res.
Offset
Res.
Table 44. External interrupt/event controller register map and reset values
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_PR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SWIER[23:0]
0
Res.
Reset value
0x14
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_SWIER
0
TR[23:0]
0
Res.
Reset value
0x10
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_FTSR
0
TR[23:0]
0
Res.
Reset value
0x0C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_RTSR
0
EM[23:0]
0
Res.
Reset value
0x08
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
EXTI_EMR
0x04
0
Res.
Reset value
IM[23:0]
0
0
PR[23:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 on page 65for the register boundary addresses.
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Cyclic redundancy check calculation unit (CRC)
12
Cyclic redundancy check calculation unit (CRC)
12.1
Introduction
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the functional safety standards, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
12.2
CRC main features
•
Fully programmable polynomial with programmable size (7, 8, 16, 32 bits).
•
Handles 8-,16-, 32-bit data size
•
Programmable CRC initial value
•
Single input/output 32-bit data register
•
Input buffer to avoid bus stall during calculation
•
CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size
•
General-purpose 8-bit register (can be used for temporary storage)
•
Reversibility option on I/O data
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RM0385
12.3
CRC functional description
12.3.1
CRC block diagram
Figure 31. CRC calculation unit block diagram
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12.3.2
CRC internal signals
Table 45. CRC internal input/output signals
12.3.3
Signal name
Signal type
crc_hclk
Digital input
Description
AHB clock
CRC operation
The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to
input new data (write access), and holds the result of the previous CRC calculation (read
access).
Each write operation to the data register creates a combination of the previous CRC value
(stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data
word or byte by byte depending on the format of the data being written.
The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned
byte. For the other registers only 32-bit access is allowed.
The duration of the computation depends on data width:
•
4 AHB clock cycles for 32-bit
•
2 AHB clock cycles for 16-bit
•
1 AHB clock cycles for 8-bit
An input buffer allows to immediately write a second data without waiting for any wait states
due to the previous CRC calculation.
The data size can be dynamically adjusted to minimize the number of write accesses for a
given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write
followed by a byte write.
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Cyclic redundancy check calculation unit (CRC)
The input data can be reversed, to manage the various endianness schemes. The reversing
operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits
in the CRC_CR register.
For example: input data 0x1A2B3C4D is used for CRC calculation as:
0x58D43CB2 with bit-reversal done by byte
0xD458B23C with bit-reversal done by half-word
0xB23CD458 with bit-reversal done on the full word
The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register.
The operation is done at bit level: for example, output data 0x11223344 is converted into
0x22CC4488.
The CRC calculator can be initialized to a programmable value using the RESET control bit
in the CRC_CR register (the default value is 0xFFFFFFFF).
The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR
register is automatically initialized upon CRC_INIT register write access.
The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It
is not affected by the RESET bit in the CRC_CR register.
Polynomial programmability
The polynomial coefficients are fully programmable through the CRC_POL register, and the
polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the
POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported.
If the CRC data is less than 32-bit, its value can be read from the least significant bits of the
CRC_DR register.
To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can
not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the
application must either reset it or perform a CRC_DR read before changing the polynomial.
The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7.
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12.4
CRC registers
12.4.1
Data register (CRC_DR)
RM0385
Address offset: 0x00
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
DR[31:16]
rw
15
14
13
12
11
10
9
8
7
DR[15:0]
rw
Bits 31:0 DR[31:0]: Data register bits
This register is used to write new data to the CRC calculator.
It holds the previous CRC calculation result when it is read.
If the data size is less than 32 bits, the least significant bits are used to write/read the
correct value.
12.4.2
Independent data register (CRC_IDR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
IDR[7:0]
rw
Bits 31:8 Reserved, must be kept cleared.
Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits
These bits can be used as a temporary storage location for one byte.
This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register
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Cyclic redundancy check calculation unit (CRC)
12.4.3
Control register (CRC_CR)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
REV_
OUT
Res.
Res.
RESET
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
REV_IN[1:0]
rw
rw
POLYSIZE[1:0]
rw
rw
rs
Bits 31:8 Reserved, must be kept cleared.
Bit 7 REV_OUT: Reverse output data
This bit controls the reversal of the bit order of the output data.
0: Bit order not affected
1: Bit-reversed output format
Bits 6:5 REV_IN[1:0]: Reverse input data
These bits control the reversal of the bit order of the input data
00: Bit order not affected
01: Bit reversal done by byte
10: Bit reversal done by half-word
11: Bit reversal done by word
Bits 4:3 POLYSIZE[1:0]: Polynomial size
These bits control the size of the polynomial.
00: 32 bit polynomial
01: 16 bit polynomial
10: 8 bit polynomial
11: 7 bit polynomial
Bits 2:1 Reserved, must be kept cleared.
Bit 0 RESET: RESET bit
This bit is set by software to reset the CRC calculation unit and set the data register to the value
stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware
12.4.4
Initial CRC value (CRC_INIT)
Address offset: 0x10
Reset value: 0xFFFF FFFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
CRC_INIT[31:16]
rw
15
14
13
12
11
10
9
8
7
CRC_INIT[15:0]
rw
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Bits 31:0 CRC_INIT: Programmable initial CRC value
This register is used to write the CRC initial value.
12.4.5
CRC polynomial (CRC_POL)
Address offset: 0x14
Reset value: 0x04C11DB7
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
POL[31:16]
rw
15
14
13
12
11
10
9
8
7
POL[15:0]
rw
Bits 31:0 POL[31:0]: Programmable polynomial
This register is used to write the coefficients of the polynomial to be used for CRC calculation.
If the polynomial size is less than 32-bits, the least significant bits have to be used to program the
correct value.
12.4.6
CRC register map
Offset
Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 46. CRC register map and reset values
CRC_DR
DR[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_IDR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CRC_CR
0
Res.
0x08
Reset value
0x10
CRC_INIT
Reset value
0x14
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
CRC_INIT[31:0]
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CRC_POL
Polynomial coefficients
Reset value
0x04C11DB7
1
1
1
1
1
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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1
IDR[7:0]
REV_OUT
0x04
1
Res.
1
RESET
1
Res.
1
POLYSIZE[1:0]
1
REV_IN[1:0]
Reset value
Res.
0x00
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13
Flexible memory controller (FMC)
Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
13.1
•
The NOR/PSRAM memory controller
•
The NAND memory controller
•
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
FMC main features
The FMC functional block makes the interface with: synchronous and asynchronous static
memories, SDRAM memories, and NAND flash memory. Its main purposes are:
•
to translate AHB transactions into the appropriate external device protocol
•
to meet the access time requirements of the external memory devices
All external memories share the addresses, data and control signals with the controller.
Each external device is accessed by means of a unique Chip Select. The FMC performs
only one access at a time to an external device.
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
Interface with parallel LCD modules, supporting Intel 8080 and Motorola 6800 modes.
•
Burst mode support for faster access to synchronous devices such as NOR Flash
memory, PSRAM and SDRAM)
•
Programmable continuous clock output for asynchronous and synchronous accesses
•
8-,16- or 32-bit wide data bus
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write enable and byte lane select outputs for use with PSRAM, SRAM and SDRAM
devices
•
External asynchronous wait control
•
Write FIFO with 16 x32-bit depth
•
Cacheable Read FIFO with 6 x32-bit depth (6 x14-bit address tag) for SDRAM
controller.
The Write FIFO is common to all memory controllers and consists of:
•
a Write Data FIFO which stores the AHB data to be written to the memory (up to 32
bits) plus one bit for the AHB transfer (burst or not sequential mode)
•
a Write Address FIFO which stores the AHB address (up to 28 bits) plus the AHB data
size (up to 2 bits). When operating in burst mode, only the start address is stored
except when crossing a page boundary (for PSRAM and SDRAM). In this case, the
AHB burst is broken into two FIFO entries.
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The Write FIFO can be disabled by setting the WFDIS bit in the FMC_BCR1 register.
At startup the FMC pins must be configured by the user application. The FMC I/O pins which
are not used by the application can be used for other purposes.
The FMC registers that define the external device type and associated characteristics are
usually set at boot time and do not change until the next reset or power-up. However, the
settings can be changed at any time.
13.2
Block diagram
The FMC consists of the following main blocks:
•
The AHB interface (including the FMC configuration registers)
•
The NOR Flash/PSRAM/SRAM controller
•
The SDRAM controller
•
The NAND Flash controller
The block diagram is shown in the figure below.
Figure 32. FMC block diagram
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13.3
Flexible memory controller (FMC)
AHB interface
The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle
between the consecutive accesses except in case of access mode D when the extended
mode is enabled.
The FMC generates an AHB error in the following conditions:
•
When reading or writing to an FMC bank (Bank 1 to 4) which is not enabled.
•
When reading or writing to the NOR Flash bank while the FACCEN bit is reset in the
FMC_BCRx register.
•
When writing to a write protected SDRAM bank (WP bit set in the SDRAM_SDCRx
register).
•
When the SDRAM address range is violated (access to reserved address range)
The effect of an AHB error depends on the AHB master which has attempted the R/W
access:
•
If the access has been attempted by the Cortex®-M7 CPU, a hard fault interrupt is
generated.
•
If the access has been performed by a DMA controller, a DMA transfer error is
generated and the corresponding DMA channel is automatically disabled.
The AHB clock (HCLK) is the reference clock for the FMC.
13.3.1
Supported memories and transactions
General transaction rules
The requested AHB transaction data size can be 8-, 16- or 32-bit wide whereas the
accessed external device has a fixed data width. This may lead to inconsistent transfers.
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Therefore, some simple transaction rules must be followed:
•
AHB transaction size and memory data size are equal
There is no issue in this case.
•
AHB transaction size is greater than the memory size:
In this case, the FMC splits the AHB transaction into smaller consecutive memory
accesses to meet the external data width. The FMC Chip Select (FMC_NEx) does not
toggle between the consecutive accesses.
•
AHB transaction size is smaller than the memory size:
The transfer may or not be consistent depending on the type of external device:
–
Accesses to devices that have the byte select feature (SRAM, ROM, PSRAM,
SDRAM)
In this case, the FMC allows read/write transactions and accesses the right data
through its byte lanes NBL[3:0].
Bytes to be written are addressed by NBL[3:0].
All memory bytes are read (NBL[3:0] are driven low during read transaction) and
the useless ones are discarded.
–
Accesses to devices that do not have the byte select feature (NOR and NAND
Flash memories)
This situation occurs when a byte access is requested to a 16-bit wide Flash
memory. Since the device cannot be accessed in byte mode (only 16-bit words
can be read/written from/to the Flash memory), Write transactions and Read
transactions are allowed (the controller reads the entire 16-bit memory word and
uses only the required byte).
Wrap support for NOR Flash/PSRAM and SDRAM
The synchronous memories must be configured in linear burst mode of undefined length as
not all masters can issue a wrap transactions.
If a master generates an AHB wrap transaction:
•
The read is splited into two linear burst transactions.
•
The write is splited into two linear burst transactions if the write fifo is enabled and into
several linear burst transactions if the write fifo is disabled.
Configuration registers
The FMC can be configured through a set of registers. Refer to Section 13.5.6, for a
detailed description of the NOR Flash/PSRAM controller registers. Refer to Section 13.6.7,
for a detailed description of the NAND Flash registers and to Section 13.7.5 for a detailed
description of the SDRAM controller registers.
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13.4
Flexible memory controller (FMC)
External device address mapping
From the FMC point of view, the external memory is divided into fixed-size banks of
256 Mbytes each (see Figure 33):
•
Bank 1 used to address up to 4 NOR Flash memory or PSRAM devices. This bank is
split into 4 NOR/PSRAM subbanks with 4 dedicated Chip Selects, as follows:
–
Bank 1 - NOR/PSRAM 1
–
Bank 1 - NOR/PSRAM 2
–
Bank 1 - NOR/PSRAM 3
–
Bank 1 - NOR/PSRAM 4
•
Bank 3 used to address NAND Flash memory devices.The MPU memory attribute for
this space must be reconfigured by software to Device.
•
Bank 4 and 5 used to address SDRAM devices (1 device per bank).
For each bank the type of memory to be used can be configured by the user application
through the Configuration register.
Figure 33. FMC memory banks
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13.4.1
RM0385
NOR/PSRAM address mapping
HADDR[27:26] bits are used to select one of the four memory banks as shown in Table 47.
Table 47. NOR/PSRAM bank selection
HADDR[27:26](1)
Selected bank
00
Bank 1 - NOR/PSRAM 1
01
Bank 1 - NOR/PSRAM 2
10
Bank 1 - NOR/PSRAM 3
11
Bank 1 - NOR/PSRAM 4
1. HADDR are internal AHB address lines that are translated to external memory.
The HADDR[25:0] bits contain the external memory address. Since HADDR is a byte
address whereas the memory is addressed at word level, the address actually issued to the
memory varies according to the memory data width, as shown in the following table.
Table 48. NOR/PSRAM External memory address
Memory width(1)
Data address issued to the memory
Maximum memory capacity (bits)
8-bit
HADDR[25:0]
64 Mbytes x 8 = 512 Mbit
16-bit
HADDR[25:1] >> 1
64 Mbytes/2 x 16 = 512 Mbit
32-bit
HADDR[25:2] >> 2
64 Mbytes/4 x 32 = 512 Mbit
1. In case of a 16-bit external memory width, the FMC will internally use HADDR[25:1] to generate the
address for external memory FMC_A[24:0]. In case of a 32-bit memory width, the FMC will internally use
HADDR[25:2] to generate the external address.
Whatever the external memory width, FMC_A[0] should be connected to external memory address A[0].
13.4.2
NAND Flash memory address mapping
The NAND bank is divided into memory areas as indicated in Table 49.
Table 49. NAND memory mapping and timing registers
Start address
End address
0x8800 0000
0x8BFF FFFF
0x8000 0000
0x83FF FFFF
FMC bank
Bank 3 - NAND Flash
Memory space
Timing register
Attribute
FMC_PATT (0x8C)
Common
FMC_PMEM (0x88)
For NAND Flash memory, the common and attribute memory spaces are subdivided into
three sections (see in Table 50 below) located in the lower 256 Kbytes:
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Data section (first 64 Kbytes in the common/attribute memory space)
•
Command section (second 64 Kbytes in the common / attribute memory space)
•
Address section (next 128 Kbytes in the common / attribute memory space)
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Table 50. NAND bank selection
Section name
HADDR[17:16]
Address range
Address section
1X
0x020000-0x03FFFF
Command section
01
0x010000-0x01FFFF
Data section
00
0x000000-0x0FFFF
The application software uses the 3 sections to access the NAND Flash memory:
•
To sending a command to NAND Flash memory, the software must write the
command value to any memory location in the command section.
•
To specify the NAND Flash address that must be read or written, the software
must write the address value to any memory location in the address section. Since an
address can be 4 or 5 bytes long (depending on the actual memory size), several
consecutive write operations to the address section are required to specify the full
address.
•
To read or write data, the software reads or writes the data from/to any memory
location in the data section.
Since the NAND Flash memory automatically increments addresses, there is no need to
increment the address of the data section to access consecutive memory locations.
13.4.3
SDRAM address mapping
The HADDR[28] bit (internal AHB address line 28) is used to select one of the two memory
banks as indicated in Table 51.
Table 51. SDRAM bank selection
HADDR[28]
Selected bank
Control register
Timing register
0
SDRAM Bank1
FMC_SDCR1
FMC_SDTR1
1
SDRAM Bank2
FMC_SDCR2
FMC_SDTR2
The following table shows SDRAM mapping for a 13-bit row, a 11-bit column and a 4 internal
bank configuration.
Table 52. SDRAM address mapping
Memory width(1)
Internal bank
Row address
Column
address(2)
Maximum
memory capacity
(Mbytes)
8-bit
HADDR[25:24]
HADDR[23:11]
HADDR[10:0]
64 Mbytes:
4 x 8K x 2K
16-bit
HADDR[26:25]
HADDR[24:12]
HADDR[11:1]
128 Mbytes:
4 x 8K x 2K x 2
32-bit
HADDR[27:26]
HADDR[25:13]
HADDR[12:2]
256 Mbytes:
4 x 8K x 2K x 4
1. When interfacing with a 16-bit memory, the FMC internally uses the HADDR[11:1] internal AHB address
lines to generate the external address. Whatever the memory width, FMC_A[0] has to be connected to the
external memory address A[0].
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2. The AutoPrecharge is not supported. FMC_A[10] must be connected to the external memory address
A[10] but it will be always driven ‘low’.
The HADDR[27:0] bits are translated to external SDRAM address depending on the
SDRAM controller configuration:
•
Data size:8, 16 or 32 bits
•
Row size:11, 12 or 13 bits
•
Column size: 8, 9, 10 or 11 bits
•
Number of internal banks: two or four internal banks
The following tables show the SDRAM address mapping versus the SDRAM controller
configuration.
Table 53. SDRAM address mapping with 8-bit data bus width(1)(2)
Row size
configuration
HADDR(AHB Internal Address Lines)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bank
[1:0]
Res.
Bank
[1:0]
Res.
11-bit row size
configuration
Bank
[1:0]
Res.
Bank
[1:0]
Row[11:0]
Row[11:0]
Row[11:0]
Bank
[1:0]
Bank
[1:0]
Res.
Res.
Row[11:0]
Bank
[1:0]
Res.
Res.
Row[10:0]
Bank
[1:0]
Res.
13-bit row size
configuration
Row[10:0]
Bank
[1:0]
Res.
Res.
Row[10:0]
Bank
[1:0]
Res.
Res.
12-bit row size
configuration
Row[10:0]
Bank
[1:0]
Bank
[1:0]
Row[12:0]
Row[12:0]
Row[12:0]
Row[12:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved (Res.) address range generates an AHB error.
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Table 54. SDRAM address mapping with 16-bit data bus width(1)(2)
Bank
Row[10:0]
[1:0]
Bank
Res.
Row[10:0]
11-bit row size
[1:0]
Bank
configuration
Res.
Row[10:0]
[1:0]
Bank
Res.
Row[10:0]
[1:0]
Bank
Res.
Row[11:0]
[1:0]
Bank
Res.
Row[11:0]
12-bit row size
[1:0]
Bank
configuration
Res.
Row[11:0]
[1:0]
Bank
Res.
Row[11:0]
[1:0]
Bank
Res.
Row[12:0]
[1:0]
Bank
Res.
Row[12:0]
13-bit row size
[1:0]
Bank
configuration
Res.
Row[12:0]
[1:0]
Re Bank
Row[12:0]
s. [1:0]
Res.
0
10
9
8
7
6
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Row size
Configuration
27
HADDR(AHB address Lines)
BM0(3)
Column[7:0]
Column[8:0]
BM0
Column[9:0]
BM0
Column[10:0]
BM0
Column[7:0]
BM0
Column[8:0]
BM0
Column[9:0]
BM0
Column[10:0]
BM0
Column[7:0]
BM0
Column[8:0]
BM0
Column[9:0]
BM0
Column[10:0]
BM0
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AHB error.
3. BM0: is the byte mask for 16-bit access.
Table 55. SDRAM address mapping with 32-bit data bus width(1)(2)
Bank
[1:0]
Bank
Res.
[1:0]
Bank
Res.
[1:0]
Bank
Res.
[1:0]
Res.
11-bit row size
configuration
Row[10:0]
Row[10:0]
Row[10:0]
Row[10:0]
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Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
0
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
21
22
23
24
25
26
Row size
configuration
27
HADDR(AHB address Lines)
BM[1:0](3)
BM[1:0]
BM[1:0]
BM[1:0]
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Table 55. SDRAM address mapping with 32-bit data bus width(1)(2) (continued)
Bank
[1:0]
Bank
Res.
12-bit row size
[1:0]
Bank
configuration
Res.
[1:0]
Bank
Res.
[1:0]
Bank
Res.
[1:0]
Bank
Res.
13-bit row size
[1:0]
configuration Res. Bank
[1:0]
Bank
[1:0]
Res.
Row[11:0]
Row[11:0]
Row[11:0]
Row[11:0]
Row[12:0]
Row[12:0]
Row[12:0]
Row[12:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
Column[7:0]
Column[8:0]
Column[9:0]
Column[10:0]
0
1
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
21
22
23
24
25
26
Row size
configuration
27
HADDR(AHB address Lines)
BM[1:0]
BM[1:0]
BM[1:0]
BM[1:0]
BM[1:0
BM[1:0
BM[1:0
BM[1:0
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AHB error.
3. BM[1:0]: is the byte mask for 32-bit access.
13.5
NOR Flash/PSRAM controller
The FMC generates the appropriate signal timings to drive the following types of memories:
•
•
•
Asynchronous SRAM and ROM
–
8 bits
–
16 bits
–
32 bits
PSRAM (Cellular RAM)
–
Asynchronous mode
–
Burst mode for synchronous accesses
–
Multiplexed or non-multiplexed
NOR Flash memory
–
Asynchronous mode
–
Burst mode for synchronous accesses
–
Multiplexed or non-multiplexed
The FMC outputs a unique Chip Select signal, NE[4:1], per bank. All the other signals
(addresses, data and control) are shared.
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The FMC supports a wide range of devices through a programmable timings among which:
•
Programmable wait states (up to 15)
•
Programmable bus turnaround cycles (up to 15)
•
Programmable output enable and write enable delays (up to 15)
•
Independent read and write timings and protocol to support the widest variety of
memories and timings
•
Programmable continuous clock (FMC_CLK) output.
The FMC Clock (FMC_CLK) is a submultiple of the HCLK clock. It can be delivered to the
selected external device either during synchronous accesses only or during asynchronous
and synchronous accesses depending on the CCKEN bit configuration in the FMC_BCR1
register:
•
If the CCLKEN bit is reset, the FMC generates the clock (CLK) only during
synchronous accesses (Read/write transactions).
•
If the CCLKEN bit is set, the FMC generates a continuous clock during asynchronous
and synchronous accesses. To generate the FMC_CLK continuous clock, Bank 1 must
be configured in synchronous mode (see Section 13.5.6: NOR/PSRAM controller
registers). Since the same clock is used for all synchronous memories, when a
continuous output clock is generated and synchronous accesses are performed, the
AHB data size has to be the same as the memory data width (MWID) otherwise the
FMC_CLK frequency will be changed depending on AHB data transaction (refer to
Section 13.5.5: Synchronous transactions for FMC_CLK divider ratio formula).
The size of each bank is fixed and equal to 64 Mbytes. Each bank is configured through
dedicated registers (see Section 13.5.6: NOR/PSRAM controller registers).
The programmable memory parameters include access times (see Table 56) and support
for wait management (for PSRAM and NOR Flash accessed in burst mode).
Table 56. Programmable NOR/PSRAM access parameters
Parameter
Function
Access mode
Unit
Min.
Max.
Address
setup
Duration of the address
setup phase
Asynchronous
AHB clock cycle
(HCLK)
0
15
Address hold
Duration of the address hold
phase
Asynchronous,
muxed I/Os
AHB clock cycle
(HCLK)
1
15
Data setup
Duration of the data setup
phase
Asynchronous
AHB clock cycle
(HCLK)
1
256
Bust turn
Duration of the bus
turnaround phase
Asynchronous and
AHB clock cycle
synchronous read
(HCLK)
/ write
0
15
Clock divide
ratio
Number of AHB clock cycles
(HCLK) to build one memory
clock cycle (CLK)
Synchronous
AHB clock cycle
(HCLK)
2
16
Data latency
Number of clock cycles to
issue to the memory before
the first data of the burst
Synchronous
Memory clock
cycle (CLK)
2
17
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13.5.1
RM0385
External memory interface signals
Table 57, Table 58 and Table 59 list the signals that are typically used to interface with NOR
Flash memory, SRAM and PSRAM.
Note:
The prefix “N” identifies the signals which are active low.
NOR Flash memory, non-multiplexed I/Os
Table 57. Non-multiplexed I/O NOR Flash memory
FMC signal name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:0]
O
Address bus
D[31:0]
I/O
Bidirectional data bus
NE[x]
O
Chip Select, x = 1..4
NOE
O
Output enable
NWE
O
Write enable
NL(=NADV)
O
Latch enable (this signal is called address
valid, NADV, by some NOR Flash devices)
NWAIT
I
NOR Flash wait input signal to the FMC
The maximum capacity is 512 Mbits (26 address lines).
NOR Flash memory, 16-bit multiplexed I/Os
Table 58. 16-bit multiplexed I/O NOR Flash memory
FMC signal name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:16]
O
Address bus
AD[15:0]
I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x]
O
Chip Select, x = 1..4
NOE
O
Output enable
NWE
O
Write enable
NL(=NADV)
O
Latch enable (this signal is called address valid, NADV, by some NOR
Flash devices)
NWAIT
I
NOR Flash wait input signal to the FMC
The maximum capacity is 512 Mbits.
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PSRAM/SRAM, non-multiplexed I/Os
Table 59. Non-multiplexed I/Os PSRAM/SRAM
FMC signal name
I/O
Function
CLK
O
Clock (only for PSRAM synchronous access)
A[25:0]
O
Address bus
D[31:0]
I/O
Data bidirectional bus
NE[x]
O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE
O
Output enable
NWE
O
Write enable
NL(= NADV)
O
Address valid only for PSRAM input (memory signal name: NADV)
NWAIT
I
PSRAM wait input signal to the FMC
NBL[3:0]
O
Byte lane output. Byte 0 to Byte 3 control (Upper and lower byte enable)
The maximum capacity is 512 Mbits.
PSRAM, 16-bit multiplexed I/Os
Table 60. 16-Bit multiplexed I/O PSRAM
FMC signal name
I/O
Function
CLK
O
Clock (for synchronous access)
A[25:16]
O
Address bus
AD[15:0]
I/O
16-bit multiplexed, bidirectional address/data bus (the 16-bit address
A[15:0] and data D[15:0] are multiplexed on the databus)
NE[x]
O
Chip Select, x = 1..4 (called NCE by PSRAM (Cellular RAM i.e. CRAM))
NOE
O
Output enable
NWE
O
Write enable
NL(= NADV)
O
Address valid PSRAM input (memory signal name: NADV)
NWAIT
I
PSRAM wait input signal to the FMC
NBL[1:0]
O
Byte lane output. Byte 0 and Byte 1 control (upper and lower byte enable)
The maximum capacity is 512 Mbits (26 address lines).
13.5.2
Supported memories and transactions
Table 61 below shows an example of the supported devices, access modes and
transactions when the memory data bus is 16-bit wide for NOR Flash memory, PSRAM and
SRAM. The transactions not allowed (or not supported) by the FMC are shown in gray in
this example.
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Table 61. NOR Flash/PSRAM: example of supported memories and transactions
Device
NOR Flash
(muxed I/Os
and nonmuxed
I/Os)
PSRAM
(multiplexed
I/Os and nonmultiplexed
I/Os)
SRAM and
ROM
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Mode
R/W
AHB
data
size
Memory
data size
Allowed/
not
allowed
Comments
Asynchronous
R
8
16
Y
-
Asynchronous
W
8
16
N
-
Asynchronous
R
16
16
Y
-
Asynchronous
W
16
16
Y
-
Asynchronous
R
32
16
Y
Split into 2 FMC accesses
Asynchronous
W
32
16
Y
Split into 2 FMC accesses
Asynchronous
page
R
-
16
N
Mode is not supported
Synchronous
R
8
16
N
-
Synchronous
R
16
16
Y
-
Synchronous
R
32
16
Y
-
Asynchronous
R
8
16
Y
-
Asynchronous
W
8
16
Y
Use of byte lanes NBL[1:0]
Asynchronous
R
16
16
Y
-
Asynchronous
W
16
16
Y
-
Asynchronous
R
32
16
Y
Split into 2 FMC accesses
Asynchronous
W
32
16
Y
Split into 2 FMC accesses
Asynchronous
page
R
-
16
N
Mode is not supported
Synchronous
R
8
16
N
-
Synchronous
R
16
16
Y
-
Synchronous
R
32
16
Y
-
Synchronous
W
8
16
Y
Use of byte lanes NBL[1:0]
Synchronous
W
16/32
16
Y
-
Asynchronous
R
8 / 16
16
Y
-
Asynchronous
W
8 / 16
16
Y
Use of byte lanes NBL[1:0]
Asynchronous
R
32
16
Y
Split into 2 FMC accesses
Asynchronous
W
32
16
Y
Split into 2 FMC accesses
Use of byte lanes NBL[1:0]
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13.5.3
Flexible memory controller (FMC)
General timing rules
Signals synchronization
13.5.4
•
All controller output signals change on the rising edge of the internal clock (HCLK)
•
In synchronous mode (read or write), all output signals change on the rising edge of
HCLK. Whatever the CLKDIV value, all outputs change as follows:
–
NOEL/NWEL/ NEL/NADVL/ NADVH /NBLL/ Address valid outputs change on the
falling edge of FMC_CLK clock.
–
NOEH/ NWEH / NEH/ NOEH/NBLH/ Address invalid outputs change on the rising
edge of FMC_CLK clock.
NOR Flash/PSRAM controller asynchronous transactions
Asynchronous static memories (NOR Flash, PSRAM, SRAM)
•
Signals are synchronized by the internal clock HCLK. This clock is not issued to the
memory
•
The FMC always samples the data before de-asserting the NOE signal. This
guarantees that the memory data hold timing constraint is met (minimum Chip Enable
high to data transition is usually 0 ns)
•
If the extended mode is enabled (EXTMOD bit is set in the FMC_BCRx register), up to
four extended modes (A, B, C and D) are available. It is possible to mix A, B, C and D
modes for read and write operations. For example, read operation can be performed in
mode A and write in mode B.
•
If the extended mode is disabled (EXTMOD bit is reset in the FMC_BCRx register), the
FMC can operate in Mode1 or Mode2 as follows:
–
Mode 1 is the default mode when SRAM/PSRAM memory type is selected (MTYP
= 0x0 or 0x01 in the FMC_BCRx register)
–
Mode 2 is the default mode when NOR memory type is selected (MTYP = 0x10 in
the FMC_BCRx register).
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Mode 1 - SRAM/PSRAM (CRAM)
The next figures show the read and write transactions for the supported modes followed by
the required configuration of FMC_BCRx, and FMC_BTRx/FMC_BWTRx registers.
Figure 34. Mode1 read access waveforms
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Figure 35. Mode1 write access waveforms
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The one HCLK cycle at the end of the write transaction helps guarantee the address and
data hold time after the NWE rising edge. Due to the presence of this HCLK cycle, the
DATAST value must be greater than zero (DATAST > 0).
Table 62. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x0
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Don’t care
5:4
MWID
As needed
3:2
MTYP
As needed, exclude 0x2 (NOR Flash memory)
1
MUXE
0x0
0
MBKEN
0x1
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 63. FMC_BTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
Don’t care
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses, DATAST HCLK cycles for read accesses).
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
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Mode A - SRAM/PSRAM (CRAM) OE toggling
Figure 36. ModeA read access waveforms
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1. NBL[3:0] are driven low during the read access
Figure 37. ModeA write access waveforms
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The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.
Table 64. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Don’t care
5:4
MWID
As needed
3:2
MTYP
As needed, exclude 0x2 (NOR Flash memory)
1
MUXEN
0x0
0
MBKEN
0x1
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 65. FMC_BTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
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Table 66. FMC_BWTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for write
accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
Mode 2/B - NOR Flash
Figure 38. Mode2 and mode B read access waveforms
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Figure 39. Mode2 write access waveforms
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Figure 40. ModeB write access waveforms
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The differences with Mode1 are the toggling of NWE and the independent read and write
timings when extended mode is set (Mode B).
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Table 67. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1 for mode B, 0x0 for mode 2
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
As needed
3:2
MTYP
0x2 (NOR Flash memory)
1
MUXEN
0x0
0
MBKEN
0x1
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 68. FMC_BTRx bit fields
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Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x1 if extended mode is set
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the access second phase (DATAST HCLK cycles) for
read accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
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Flexible memory controller (FMC)
Table 69. FMC_BWTRx bit fields
Note:
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x1 if extended mode is set
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the access second phase (DATAST HCLK cycles) for
write accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the access first phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
The FMC_BWTRx register is valid only if the extended mode is set (mode B), otherwise its
content is don’t care.
Mode C - NOR Flash - OE toggling
Figure 41. ModeC read access waveforms
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Figure 42. ModeC write access waveforms
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The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.
Table 70. FMC_BCRx bit fields
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Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
As needed
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Flexible memory controller (FMC)
Table 70. FMC_BCRx bit fields (continued)
Bit number
Bit name
Value to set
3:2
MTYP
1
MUXEN
0x0
0
MBKEN
0x1
0x02 (NOR Flash memory)
Table 71. FMC_BTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x2
27:24
DATLAT
0x0
23:20
CLKDIV
0x0
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
Table 72. FMC_BWTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x2
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7:4
ADDHLD
Don’t care
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
Time between NEx high to NEx low (BUSTURN HCLK).
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Mode D - asynchronous access with extended address
Figure 43. ModeD read access waveforms
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Figure 44. ModeD write access waveforms
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The differences with Mode1 are the toggling of NOE that goes on toggling after NADV
changes and the independent read and write timings.
Table 73. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x1
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
Set according to memory support
5:4
MWID
As needed
3:2
MTYP
As needed
1
MUXEN
0x0
0
MBKEN
0x1
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
Table 74. FMC_BTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x3
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles) for read
accesses.
7:4
ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
Time between NEx high to NEx low (BUSTURN HCLK).
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Table 75. FMC_BWTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x3
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST + 1 HCLK cycles) for
write accesses.
7:4
ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 1.
Time between NEx high to NEx low (BUSTURN HCLK).
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 45. Muxed read access waveforms
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Figure 46. Muxed write access waveforms
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The difference with ModeD is the drive of the lower address byte(s) on the data bus.
Table 76. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31:22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
0x0 (no effect in asynchronous mode)
18:16
CPSIZE
0x0 (no effect in asynchronous mode)
15
ASYNCWAIT
14
EXTMOD
0x0
13
WAITEN
0x0 (no effect in asynchronous mode)
12
WREN
As needed
11
WAITCFG
Don’t care
10
Reserved
0x0
9
WAITPOL
Meaningful only if bit 15 is 1
8
BURSTEN
0x0
7
Reserved
0x1
6
FACCEN
0x1
5:4
MWID
0x000
Set to 1 if the memory supports this feature. Otherwise keep at 0.
As needed
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Table 76. FMC_BCRx bit fields (continued)
Bit number
Bit name
Value to set
3:2
MTYP
1
MUXEN
0x1
0
MBKEN
0x1
0x2 (NOR Flash memory) or 0x1(PSRAM)
Table 77. FMC_BTRx bit fields
Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27:24
DATLAT
Don’t care
23:20
CLKDIV
Don’t care
19:16
BUSTURN
15:8
DATAST
Duration of the second access phase (DATAST HCLK cycles for read
accesses and DATAST+1 HCLK cycles for write accesses).
7:4
ADDHLD
Duration of the middle phase of the access (ADDHLD HCLK cycles).
3:0
ADDSET
Duration of the first access phase (ADDSET HCLK cycles). Minimum
value for ADDSET is 1.
Time between NEx high to NEx low (BUSTURN HCLK).
WAIT management in asynchronous accesses
If the asynchronous memory asserts the WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FMC_BCRx register.
If the WAIT signal is active (high or low depending on the WAITPOL bit), the second access
phase (Data setup phase), programmed by the DATAST bits, is extended until WAIT
becomes inactive. Unlike the data setup phase, the first access phases (Address setup and
Address hold phases), programmed by the ADDSET and ADDHLD bits, are not WAIT
sensitive and so they are not prolonged.
The data setup phase must be programmed so that WAIT can be detected 4 HCLK cycles
before the end of the memory transaction. The following cases must be considered:
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1.
The memory asserts the WAIT signal aligned to NOE/NWE which toggles:
DATAST ≥ ( 4 × HCLK ) + max_wait_assertion_time
2.
The memory asserts the WAIT signal aligned to NEx (or NOE/NWE not toggling):
if
max_wait_assertion_time > address_phase + hold_phase
then:
DATAST ≥ ( 4 × HCLK ) + ( max_wait_assertion_time
– address_phase – hold_phase )
otherwise
DATAST ≥ 4 × HCLK
where max_wait_assertion_time is the maximum time taken by the memory to assert
the WAIT signal once NEx/NOE/NWE is low.
Figure 47 and Figure 48 show the number of HCLK clock cycles that are added to the
memory access phase after WAIT is released by the asynchronous memory (independently
of the above cases).
Figure 47. Asynchronous wait during a read access waveforms
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1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
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Figure 48. Asynchronous wait during a write access waveforms
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1. NWAIT polarity depends on WAITPOL bit setting in FMC_BCRx register.
13.5.5
Synchronous transactions
The memory clock, FMC_CLK, is a submultiple of HCLK. It depends on the value of
CLKDIV and the MWID/ AHB data size, following the formula given below:
FMC_CLK divider ratio = max (CLKDIV + 1,MWID ( AHB data size ))
If MWID is 16 or 8-bit, the FMC_CLK divider ratio is always defined by the programmed
CLKDIV value.
If MWID is 32-bit, the FMC_CLK divider ratio depends also on AHB data size.
Example:
•
If CLKDIV=1, MWID = 32 bits, AHB data size=8 bits, FMC_CLK=HCLK/4.
•
If CLKDIV=1, MWID = 16 bits, AHB data size=8 bits, FMC_CLK=HCLK/2.
NOR Flash memories specify a minimum time from NADV assertion to CLK high. To meet
this constraint, the FMC does not issue the clock to the memory during the first internal
clock cycle of the synchronous access (before NADV assertion). This guarantees that the
rising edge of the memory clock occurs in the middle of the NADV low pulse.
Data latency versus NOR memory latency
The data latency is the number of cycles to wait before sampling the data. The DATLAT
value must be consistent with the latency value specified in the NOR Flash configuration
register. The FMC does not include the clock cycle when NADV is low in the data latency
count.
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Caution:
Some NOR Flash memories include the NADV Low cycle in the data latency count, so that
the exact relation between the NOR Flash latency and the FMC DATLAT parameter can be
either:
•
NOR Flash latency = (DATLAT + 2) CLK clock cycles
•
or NOR Flash latency = (DATLAT + 3) CLK clock cycles
Some recent memories assert NWAIT during the latency phase. In such cases DATLAT can
be set to its minimum value. As a result, the FMC samples the data and waits long enough
to evaluate if the data are valid. Thus the FMC detects when the memory exits latency and
real data are processed.
Other memories do not assert NWAIT during latency. In this case the latency must be set
correctly for both the FMC and the memory, otherwise invalid data are mistaken for good
data, or valid data are lost in the initial phase of the memory access.
Single-burst transfer
When the selected bank is configured in burst mode for synchronous accesses, if for
example an AHB single-burst transaction is requested on 16-bit memories, the FMC
performs a burst transaction of length 1 (if the AHB transfer is 16 bits), or length 2 (if the
AHB transfer is 32 bits) and de-assert the Chip Select signal when the last data is strobed.
Such transfers are not the most efficient in terms of cycles compared to asynchronous read
operations. Nevertheless, a random asynchronous access would first require to re-program
the memory access mode, which would altogether last longer.
Cross boundary page for Cellular RAM 1.5
Cellular RAM 1.5 does not allow burst access to cross the page boundary. The FMC
controller allows to split automatically the burst access when the memory page size is
reached by configuring the CPSIZE bits in the FMC_BCR1 register following the memory
page size.
Wait management
For synchronous NOR Flash memories, NWAIT is evaluated after the programmed latency
period, which corresponds to (DATLAT+2) CLK clock cycles.
If NWAIT is active (low level when WAITPOL = 0, high level when WAITPOL = 1), wait
states are inserted until NWAIT is inactive (high level when WAITPOL = 0, low level when
WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the Chip Select and output enable signals valid. It does not
consider the data as valid.
In burst mode, there are two timing configurations for the NOR Flash NWAIT signal:
•
The Flash memory asserts the NWAIT signal one data cycle before the wait state
(default after reset).
•
The Flash memory asserts the NWAIT signal during the wait state
The FMC supports both NOR Flash wait state configurations, for each Chip Select, thanks
to the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
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Figure 49. Wait configuration waveforms
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Figure 50. Synchronous multiplexed read mode waveforms - NOR, PSRAM (CRAM)
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1. Byte lane outputs (NBL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM)
access, they are held low.
Table 78. FMC_BCRx bit fields
Bit number
Bit name
Value to set
31-22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
CBURSTRW
18:16
CPSIZE
15
ASYNCWAIT
0x0
14
EXTMOD
0x0
13
WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise
12
WREN
No effect on synchronous read
11
WAITCFG
To be set according to memory
10
Reserved
0x0
0x000
No effect on synchronous read
0x0 (no effect in asynchronous mode)
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Table 78. FMC_BCRx bit fields (continued)
Bit number
Bit name
Value to set
9
WAITPOL
To be set according to memory
8
BURSTEN
0x1
7
Reserved
0x1
6
FACCEN
Set according to memory support (NOR Flash memory)
5-4
MWID
As needed
3-2
MTYP
0x1 or 0x2
1
MUXEN
As needed
0
MBKEN
0x1
Table 79. FMC_BTRx bit fields
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Bit number
Bit name
Value to set
31:30
Reserved
0x0
29:28
ACCMOD
0x0
27-24
DATLAT
Data latency
27-24
DATLAT
Data latency
23-20
CLKDIV
0x0 to get CLK = HCLK (Not supported)
0x1 to get CLK = 2 × HCLK
..
19-16
BUSTURN
15-8
DATAST
Don’t care
7-4
ADDHLD
Don’t care
3-0
ADDSET
Don’t care
Time between NEx high to NEx low (BUSTURN HCLK).
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Flexible memory controller (FMC)
Figure 51. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)
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DATA
DATA
CLOCK CLOCK
AIF
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed
to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Table 80. FMC_BCRx bit fields
Bit number
Bit name
31-22
Reserved
21
WFDIS
As needed
20
CCLKEN
As needed
19
18:16
15
Value to set
0x000
CBURSTRW 0x1
CPSIZE
As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
14
EXTMOD
0x0
13
WAITEN
To be set to 1 if the memory supports this feature, to be kept at 0
otherwise.
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Table 80. FMC_BCRx bit fields (continued)
Bit number
Bit name
Value to set
12
WREN
0x1
11
WAITCFG
0x0
10
Reserved
0x0
9
WAITPOL
to be set according to memory
8
BURSTEN
no effect on synchronous write
7
Reserved
0x1
6
FACCEN
Set according to memory support
5-4
MWID
As needed
3-2
MTYP
0x1
1
MUXEN
As needed
0
MBKEN
0x1
Table 81. FMC_BTRx bit fields
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Bit number
Bit name
Value to set
31-30
Reserved
0x0
29:28
ACCMOD
0x0
27-24
DATLAT
Data latency
23-20
CLKDIV
0x0 to get CLK = HCLK (not supported)
0x1 to get CLK = 2 × HCLK
19-16
BUSTURN
15-8
DATAST
Don’t care
7-4
ADDHLD
Don’t care
3-0
ADDSET
Don’t care
Time between NEx high to NEx low (BUSTURN HCLK).
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Flexible memory controller (FMC)
13.5.6
NOR/PSRAM controller registers
SRAM/NOR-Flash chip-select control registers 1..4 (FMC_BCR1..4)
Address offset: 8 * (x – 1), x = 1...4
Reset value: 0x0000 30DB for Bank1 and 0x0000 30D2 for Bank 2 to 4
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR Flash memories.
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
ASYNC
WAIT
EXT
MOD
WAIT
EN
WREN
WAIT
CFG
Res.
WAIT
POL
BURST
EN
Res.
FACC
EN
rw
rw
rw
rw
rw
rw
rw
rw
21
20
19
WFDIS
CCLK
EN
CBURST
RW
rw
rw
rw
rw
rw
5
4
3
2
1
0
MUX
EN
MBK
EN
rw
rw
MWID
rw
18
rw
16
CPSIZE[2:0]
MTYP[1:0]
rw
17
rw
rw
Bits 31: 22 Reserved, must be kept at reset value
Bit 21 WFDIS: Write FIFO Disable
This bit disables the Write FIFO used by the FMC controller.
0 : Write FIFO enabled (Default after reset)
1: Write FIFO disabled
Note: The WFDIS bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register.
Bit 20 CCLKEN: Continuous Clock Enable.
This bit enables the FMC_CLK clock output to external memory devices.
0: The FMC_CLK is only generated during the synchronous memory access (read/write
transaction). The FMC_CLK clock ratio is specified by the programmed CLKDIV value in the
FMC_BCRx register (default after reset) .
1: The FMC_CLK is generated continuously during asynchronous and synchronous access. The
FMC_CLK clock is activated when the CCLKEN is set.
Note: The CCLKEN bit of the FMC_BCR2..4 registers is don’t care. It is only enabled through the
FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the
FMC_CLK continuous clock.
Note: If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the
FMC_BTR1 register. CLKDIV in FMC_BWTR1 is don’t care.
Note: If the synchronous mode is used and CCLKEN bit is set, the synchronous memories
connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in
the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)
Bit 19 CBURSTRW: Write burst enable.
For PSRAM (CRAM) operating in burst mode, the bit enables synchronous accesses during write
operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx
register.
0: Write operations are always performed in asynchronous mode
1: Write operations are performed in synchronous mode.
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Bits 18:16 CPSIZE[2:0]: CRAM page size.
These are used for Cellular RAM 1.5 which does not allow burst access to cross the address
boundaries between pages. When these bits are configured, the FMC controller splits
automatically the burst access when the memory page size is reached (refer to memory datasheet
for page size).
000: No burst split when crossing page boundary (default after reset)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
Others: reserved
Bit 15 ASYNCWAIT: Wait signal during asynchronous transfers
This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol.
0: NWAIT signal is not taken in to account when running an asynchronous protocol (default after
reset)
1: NWAIT signal is taken in to account when running an asynchronous protocol
Bit 14 EXTMOD: Extended mode enable.
This bit enables the FMC to program the write timings for non multiplexed asynchronous accesses
inside the FMC_BWTR register, thus resulting in different timings for read and write operations.
0: values inside FMC_BWTR register are not taken into account (default after reset)
1: values inside FMC_BWTR register are taken into account
Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows:
–
Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP
=0x0 or 0x01)
–
Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10).
Bit 13 WAITEN: Wait enable bit.
This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in
synchronous mode.
0: NWAIT signal is disabled (its level not taken into account, no wait state inserted after the
programmed Flash latency period)
1: NWAIT signal is enabled (its level is taken into account after the programmed latency period to
insert wait states if asserted) (default after reset)
Bit 12 WREN: Write enable bit.
This bit indicates whether write operations are enabled/disabled in the bank by the FMC:
0: Write operations are disabled in the bank by the FMC, an AHB error is reported,
1: Write operations are enabled for the bank by the FMC (default after reset).
Bit 11 WAITCFG: Wait timing configuration.
The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be
inserted when accessing the memory in synchronous mode. This configuration bit determines if
NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:
0: NWAIT signal is active one data cycle before wait state (default after reset),
1: NWAIT signal is active during wait state (not used for PSRAM).
Bit 10 Reserved, must be kept at reset value
Bit 9 WAITPOL: Wait signal polarity bit.
Defines the polarity of the wait signal from memory used for either in synchronous or
asynchronous mode:
0: NWAIT active low (default after reset),
1: NWAIT active high.
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Bit 8 BURSTEN: Burst enable bit.
This bit enables/disables synchronous accesses during read operations. It is valid only for
synchronous memories operating in burst mode:
0: Burst mode disabled (default after reset). Read accesses are performed in asynchronous mode.
1: Burst mode enable. Read accesses are performed in synchronous mode.
Bit 7 Reserved, must be kept at reset value
Bit 6 FACCEN: Flash access enable
Enables NOR Flash memory access operations.
0: Corresponding NOR Flash memory access is disabled
1: Corresponding NOR Flash memory access is enabled (default after reset)
Bits 5:4 MWID[1:0]: Memory data bus width.
Defines the external memory device width, valid for all type of memories.
00: 8 bits
01: 16 bits (default after reset)
10: 32 bits
11: reserved
Bits 3:2 MTYP[1:0]: Memory type.
Defines the type of external memory attached to the corresponding memory bank:
00: SRAM (default after reset for Bank 2...4)
01: PSRAM (CRAM)
10: NOR Flash/OneNAND Flash (default after reset for Bank 1)
11: reserved
Bit 1 MUXEN: Address/data multiplexing enable bit.
When this bit is set, the address and data values are multiplexed on the data bus, valid only with
NOR and PSRAM memories:
0: Address/Data nonmultiplexed
1: Address/Data multiplexed on databus (default after reset)
Bit 0 MBKEN: Memory bank enable bit.
Enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a
disabled bank causes an ERROR on AHB bus.
0: Corresponding memory bank is disabled
1: Corresponding memory bank is enabled
SRAM/NOR-Flash chip-select timing registers 1..4 (FMC_BTR1..4)
Address offset: 0x04 + 8 * (x – 1), x = 1..4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank, used for SRAMs,
PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then
this register is partitioned for write and read access, that is, 2 registers are available: one to
configure read accesses (this register) and one to configure write accesses (FMC_BWTRx
registers).
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31
30
Res.
Res.
15
14
29
28
RM0385
27
26
ACCMOD
25
24
23
22
DATLAT
rw
20
19
18
CLKDIV
17
16
BUSTURN
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATAST
rw
21
rw
rw
rw
ADDHLD
rw
rw
rw
rw
rw
rw
ADDSET
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value
Bits 29:28 ACCMOD[1:0]: Access mode
Specifies the asynchronous access modes as shown in the timing diagrams. These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:24 DATLAT[3:0]: (see note below bit descriptions): Data latency for synchronous memory
For synchronous access with read/write burst mode enabled (BURSTEN / CBURSTRW bits
set), defines the number of memory clock cycles (+2) to issue to the memory before
reading/writing the first data:
This timing parameter is not expressed in HCLK periods, but in FMC_CLK periods.
For asynchronous access, this value is don't care.
0000: Data latency of 2 CLK clock cycles for first burst access
1111: Data latency of 17 CLK clock cycles for first burst access (default value after reset)
Bits 23:20 CLKDIV[3:0]: Clock divide ratio (for FMC_CLK signal)
Defines the period of FMC_CLK clock output signal, expressed in number of HCLK cycles:
0000: Reserved
0001: FMC_CLK period = 2 × HCLK periods
0010: FMC_CLK period = 3 × HCLK periods
1111: FMC_CLK period = 16 × HCLK periods (default value after reset)
In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is don’t care.
Note: Refer to Section 13.5.5: Synchronous transactions for FMC_CLK divider ratio formula)
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Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
These bits are written by software to add a delay at the end of a write-to-read (and read-towrite) transaction. This delay allows to match the minimum time between consecutive
transactions (tEHEL from NEx high to NEx low) and the maximum time needed by the
memory to free the data bus after a read access (tEHQZ). The programmed bus turnaround
delay is inserted between an asynchronous read (muxed or mode D) or write transaction and
any other asynchronous /synchronous read or write to or from a static bank. The bank can be
the same or different in case of read, in case of write the bank can be different except for
muxed or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is
fixed
as follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write
transfers to the same static memory bank except for modes muxed and D.
• There is a bus turnaround delay of 1 HCLK clock cycle between:
–Two consecutive asynchronous read transfers to the same static memory bank except for
modes muxed and D.
–An asynchronous read to an asynchronous or synchronous write to any static bank or
dynamic bank except for modes muxed and D.
–An asynchronous (modes 1, 2, A, B or C) read and a read from another static bank.
• There is a bus turnaround delay of 2 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) access and an asynchronous write or read transfer
to or from static memory bank (the bank can be the same or different for the case of
read.
–Two consecutive synchronous reads (burst or single) followed by any
synchronous/asynchronous read or write from/to another static memory bank.
• There is a bus turnaround delay of 3 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) access and a synchronous read from the same or a
different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 x HCLK clock cycles added (default value after reset)
Bits 15:8 DATAST[7:0]: Data-phase duration
These bits are written by software to define the duration of the data phase (refer to Figure 34
to Figure 46), used in asynchronous accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
For each memory type and access mode data-phase duration, please refer to the respective
figure (Figure 34 to Figure 46).
Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 HCLK
clock cycles.
Note: In synchronous accesses, this value is don’t care.
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Bits 7:4 ADDHLD[3:0]: Address-hold phase duration
These bits are written by software to define the duration of the address hold phase (refer to
Figure 34 to Figure 46), used in mode D or multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration =1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address-hold phase duration, please refer to the respective figure
(Figure 34 to Figure 46).
Note: In synchronous accesses, this value is not used, the address hold phase is always 1
memory clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration
These bits are written by software to define the duration of the address setup phase (refer to
Figure 34 to Figure 46), used in SRAMs, ROMs, asynchronous NOR Flash and PSRAM:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
For each access mode address setup phase duration, please refer to the respective figure
(refer to Figure 34 to Figure 46).
Note: In synchronous accesses, this value is don’t care.
In Muxed mode or Mode D, the minimum value for ADDSET is 1.
Note:
PSRAMs (CRAMs) have a variable latency due to internal refresh. Therefore these
memories issue the NWAIT signal during the whole latency phase to prolong the latency as
needed.
With PSRAMs (CRAMs) the filled DATLAT must be set to 0, so that the FMC exits its latency
phase soon and starts sampling NWAIT from memory, then starts to read or write when the
memory is ready.
This method can be used also with the latest generation of synchronous Flash memories
that issue the NWAIT signal, unlike older Flash memories (check the datasheet of the
specific Flash memory being used).
SRAM/NOR-Flash write timing registers 1..4 (FMC_BWTR1..4)
Address offset: 0x104 + 8 * (x – 1), x = 1...4
Reset value: 0x0FFF FFFF
This register contains the control information of each memory bank. It is used for SRAMs,
PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx
register, then this register is active for write access.
31
30
Res.
Res.
15
14
29
28
ACCMOD
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13
12
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
DATAST
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17
16
BUSTURN
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3
2
1
0
ADDHLD
Bits 31:30 Reserved, must be kept at reset value
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Bits 29:28 ACCMOD[1:0]: Access mode.
Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are
taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
00: access mode A
01: access mode B
10: access mode C
11: access mode D
Bits 27:20 Reserved, must be kept at reset value
Bits 19:16 BUSTURN[3:0]: Bus turnaround phase duration
The programmed bus turnaround delay is inserted between an asynchronous write transfer and
any other asynchronous /synchronous read or write transfer to or from a static bank. The bank can
be the same or different in case of read, in case of write the bank can be different expect for muxed
or mode D.
In some cases, whatever the programmed BUSTURN values, the bus turnaround delay is fixed as
follows:
• The bus turnaround delay is not inserted between two consecutive asynchronous write transfers
to the same static memory bank except for modes muxed and D.
• There is a bus turnaround delay of 2 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to the same bank.
–A synchronous write (burst or single) transfer and an asynchronous write or read transfer to or
from static memory bank.
• There is a bus turnaround delay of 3 HCLK clock cycle between:
–Two consecutive synchronous writes (burst or single) to different static bank.
–A synchronous write (burst or single) transfer and a synchronous read from the same or a
different bank.
0000: BUSTURN phase duration = 0 HCLK clock cycle added
...
1111: BUSTURN phase duration = 15 HCLK clock cycles added (default value after reset)
Bits 15:8 DATAST[7:0]: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to Figure 34 to
Figure 46), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 43 to Figure 46), used in asynchronous multiplexed accesses:
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
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Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to Figure 34 to Figure 46), used in asynchronous accesses:
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.
13.6
NAND Flash controller
The FMC generates the appropriate signal timings to drive the following types of device:
•
8- and 16-bit NAND Flash memories
The NAND bank is configured through dedicated registers (Section 13.6.7). The
programmable memory parameters include access timings (shown in Table 82) and ECC
configuration.
Table 82. Programmable NAND Flash access parameters
13.6.1
Parameter
Function
Access mode
Unit
Min. Max.
Memory setup
time
Number of clock cycles (HCLK)
required to set up the address
before the command assertion
Read/Write
AHB clock cycle
(HCLK)
1
255
Memory wait
Minimum duration (in HCLK clock
cycles) of the command assertion
Read/Write
AHB clock cycle
(HCLK)
2
255
Memory hold
Number of clock cycles (HCLK)
during which the address must be
held (as well as the data if a write
access is performed) after the
command de-assertion
Read/Write
AHB clock cycle
(HCLK)
1
254
Memory
databus high-Z
Number of clock cycles (HCLK)
during which the data bus is kept
in high-Z state after a write
access has started
Write
AHB clock cycle
(HCLK)
1
255
External memory interface signals
The following tables list the signals that are typically used to interface NAND Flash memory.
Note:
The prefix “N” identifies the signals which are active low.
8-bit NAND Flash memory
Table 83. 8-bit NAND Flash
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I/O
Function
A[17]
O
NAND Flash address latch enable (ALE) signal
A[16]
O
NAND Flash command latch enable (CLE) signal
D[7:0]
I/O
8-bit multiplexed, bidirectional address/data bus
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Table 83. 8-bit NAND Flash (continued)
FMC signal name
I/O
Function
NCE
O
Chip Select
NOE(= NRE)
O
Output enable (memory signal name: read enable, NRE)
NWE
O
Write enable
NWAIT/INT
I
NAND Flash ready/busy input signal to the FMC
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.
16-bit NAND Flash memory
Table 84. 16-bit NAND Flash
FMC signal name
I/O
Function
A[17]
O
NAND Flash address latch enable (ALE) signal
A[16]
O
NAND Flash command latch enable (CLE) signal
D[15:0]
I/O
16-bit multiplexed, bidirectional address/data bus
NCE
O
Chip Select
NOE(= NRE)
O
Output enable (memory signal name: read enable, NRE)
NWE
O
Write enable
NWAIT/INT
I
NAND Flash ready/busy input signal to the FMC
Theoretically, there is no capacity limitation as the FMC can manage as many address
cycles as needed.
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13.6.2
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NAND Flash supported memories and transactions
Table 85 shows the supported devices, access modes and transactions. Transactions not
allowed (or not supported) by the NAND Flash controller are shown in gray.
Table 85. Supported memories and transactions
Device
NAND 8-bit
NAND 16-bit
13.6.3
AHB
Memory
Allowed/
data size data size not allowed
Mode
R/W
Comments
Asynchronous
R
8
8
Y
-
Asynchronous
W
8
8
Y
-
Asynchronous
R
16
8
Y
Split into 2 FMC accesses
Asynchronous
W
16
8
Y
Split into 2 FMC accesses
Asynchronous
R
32
8
Y
Split into 4 FMC accesses
Asynchronous
W
32
8
Y
Split into 4 FMC accesses
Asynchronous
R
8
16
Y
-
Asynchronous
W
8
16
N
-
Asynchronous
R
16
16
Y
-
Asynchronous
W
16
16
Y
-
Asynchronous
R
32
16
Y
Split into 2 FMC accesses
Asynchronous
W
32
16
Y
Split into 2 FMC accesses
Timing diagrams for NAND Flash memory
The NAND Flash memory bank is managed through a set of registers:
•
Control register: FMC_PCR
•
Interrupt status register: FMC_SR
•
ECC register: FMC_ECCR
•
Timing register for Common memory space: FMC_PMEM
•
Timing register for Attribute memory space: FMC_PATT
Each timing configuration register contains three parameters used to define number of
HCLK cycles for the three phases of any NAND Flash access, plus one parameter that
defines the timing for starting driving the data bus when a write access is performed.
Figure 52 shows the timing parameter definitions for common memory accesses, knowing
that Attribute memory space access timings are similar.
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Figure 52. NAND Flash controller waveforms for common memory access
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1. NOE remains high (inactive) during write accesses. NWE remains high (inactive) during read accesses.
2. For write access, the hold phase delay is (MEMHOLD) HCLK cycles and for read access is
(MEMHOLD + 2) HCLK cycles.
13.6.4
NAND Flash operations
The command latch enable (CLE) and address latch enable (ALE) signals of the NAND
Flash memory device are driven by address signals from the FMC controller. This means
that to send a command or an address to the NAND Flash memory, the CPU has to perform
a write to a specific address in its memory space.
A typical page read operation from the NAND Flash device requires the following steps:
3.
Program and enable the corresponding memory bank by configuring the FMC_PCR
and FMC_PMEM (and for some devices, FMC_PATT, see Section 13.6.5: NAND Flash
prewait functionality) registers according to the characteristics of the NAND Flash
memory (PWID bits for the data bus width of the NAND Flash, PTYP = 1, PWAITEN =
0 or 1 as needed, see Section 13.4.2: NAND Flash memory address mapping for
timing configuration).
4.
The CPU performs a byte write to the common memory space, with data byte equal to
one Flash command byte (for example 0x00 for Samsung NAND Flash devices). The
LE input of the NAND Flash memory is active during the write strobe (low pulse on
NWE), thus the written byte is interpreted as a command by the NAND Flash memory.
Once the command is latched by the memory device, it does not need to be written
again for the following page read operations.
5.
The CPU can send the start address (STARTAD) for a read operation by writing four
bytes (or three for smaller capacity devices), STARTAD[7:0], STARTAD[16:9],
STARTAD[24:17] and finally STARTAD[25] (for 64 Mb x 8 bit NAND Flash memories) in
the common memory or attribute space. The ALE input of the NAND Flash device is
active during the write strobe (low pulse on NWE), thus the written bytes are
interpreted as the start address for read operations. Using the attribute memory space
makes it possible to use a different timing configuration of the FMC, which can be used
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to implement the prewait functionality needed by some NAND Flash memories (see
details in Section 13.6.5: NAND Flash prewait functionality).
13.6.5
6.
The controller waits for the NAND Flash memory to be ready (R/NB signal high), before
starting a new access to the same or another memory bank. While waiting, the
controller holds the NCE signal active (low).
7.
The CPU can then perform byte read operations from the common memory space to
read the NAND Flash page (data field + Spare field) byte by byte.
8.
The next NAND Flash page can be read without any CPU command or address write
operation. This can be done in three different ways:
–
by simply performing the operation described in step 5
–
a new random address can be accessed by restarting the operation at step 3
–
a new command can be sent to the NAND Flash device by restarting at step 2
NAND Flash prewait functionality
Some NAND Flash devices require that, after writing the last part of the address, the
controller waits for the R/NB signal to go low. (see Figure 53).
Figure 53. Access to non ‘CE don’t care’ NAND-Flash
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1. CPU wrote byte 0x00 at address 0x7001 0000.
2. CPU wrote byte A7~A0 at address 0x7002 0000.
3. CPU wrote byte A16~A9 at address 0x7002 0000.
4. CPU wrote byte A24~A17 at address 0x7002 0000.
5. CPU wrote byte A25 at address 0x7802 0000: FMC performs a write access using FMC_PATT timing
definition, where ATTHOLD ≥ 7 (providing that (7+1) × HCLK = 112 ns > tWB max). This guarantees that
NCE remains low until R/NB goes low and high again (only requested for NAND Flash memories where
NCE is not don’t care).
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When this functionality is required, it can be ensured by programming the MEMHOLD value
to meet the tWB timing. However any CPU read access to the NAND Flash memory has a
hold delay of (MEMHOLD + 2) HCLK cycles and CPU write access has a hold delay of
(MEMHOLD) HCLK cycles inserted between the rising edge of the NWE signal and the next
access.
To cope with this timing constraint, the attribute memory space can be used by
programming its timing register with an ATTHOLD value that meets the tWB timing, and by
keeping the MEMHOLD value at its minimum value. The CPU must then use the common
memory space for all NAND Flash read and write accesses, except when writing the last
address byte to the NAND Flash device, where the CPU must write to the attribute memory
space.
13.6.6
Computation of the error correction code (ECC)
in NAND Flash memory
The FMC NAND Card controller includes two error correction code computation hardware
blocks, one per memory bank. They reduce the host CPU workload when processing the
ECC by software.
These two ECC blocks are identical and associated with Bank 2 and Bank 3. As a
consequence, no hardware ECC computation is available for memories connected to Bank
4.
The ECC algorithm implemented in the FMC can perform 1-bit error correction and 2-bit
error detection per 256, 512, 1 024, 2 048, 4 096 or 8 192 bytes read or written from/to the
NAND Flash memory. It is based on the Hamming coding algorithm and consists in
calculating the row and column parity.
The ECC modules monitor the NAND Flash data bus and read/write signals (NCE and
NWE) each time the NAND Flash memory bank is active.
The ECC operates as follows:
•
When accessing NAND Flash memory bank 2 or bank 3, the data present on the
D[15:0] bus is latched and used for ECC computation.
•
When accessing any other address in NAND Flash memory, the ECC logic is idle, and
does not perform any operation. As a result, write operations to define commands or
addresses to the NAND Flash memory are not taken into account for ECC
computation.
Once the desired number of bytes has been read/written from/to the NAND Flash memory
by the host CPU, the FMC_ECCR registers must be read to retrieve the computed value.
Once read, they should be cleared by resetting the ECCEN bit to ‘0’. To compute a new data
block, the ECCEN bit must be set to one in the FMC_PCR registers.
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To perform an ECC computation:
13.6.7
1.
Enable the ECCEN bit in the FMC_PCR register.
2.
Write data to the NAND Flash memory page. While the NAND page is written, the ECC
block computes the ECC value.
3.
Read the ECC value available in the FMC_ECCR register and store it in a variable.
4.
Clear the ECCEN bit and then enable it in the FMC_PCR register before reading back
the written data from the NAND page. While the NAND page is read, the ECC block
computes the ECC value.
5.
Read the new ECC value available in the FMC_ECCR register.
6.
If the two ECC values are the same, no correction is required, otherwise there is an
ECC error and the software correction routine returns information on whether the error
can be corrected or not.
NAND Flashcontroller registers
NAND Flash control registers (FMC_PCR)
Address offset: 0x80
Reset value: 0x0000 0018
31
30
29
28
27
26
25
24
23
22
21
20
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
TAR
rw
rw
10
9
TCLR
rw
rw
rw
rw
8
7
6
Res.
Res.
ECCEN
rw
rw
5
4
PWID
rw
19
18
17
ECCPS
TAR
rw
rw
rw
3
2
1
PTYP PBKEN PWAITEN
rw
rw
rw
rw
Bits 31:20 Reserved, must be kept at reset value
Bits 19:17 ECCPS[2:0]: ECC page size.
Defines the page size for the extended ECC:
000: 256 bytes
001: 512 bytes
010: 1024 bytes
011: 2048 bytes
100: 4096 bytes
101: 8192 bytes
Bits 16:13 TAR[3:0]: ALE to RE delay.
Sets time from ALE low to RE low in number of AHB clock cycles (HCLK).
Time is: t_ar = (TAR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
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Bits 12:9 TCLR[3:0]: CLE to RE delay.
Sets time from CLE low to RE low in number of AHB clock cycles (HCLK).
Time is t_clr = (TCLR + SET + 2) × THCLK where THCLK is the HCLK clock period
0000: 1 HCLK cycle (default)
1111: 16 HCLK cycles
Note: SET is MEMSET or ATTSET according to the addressed space.
Bits 8:7 Reserved, must be kept at reset value
Bit 6 ECCEN: ECC computation logic enable bit
0: ECC logic is disabled and reset (default after reset),
1: ECC logic is enabled.
Bits 5:4 PWID[1:0]: Data bus width.
Defines the external memory device width.
00: 8 bits
01: 16 bits (default after reset).
10: reserved.
11: reserved.
Bit 3 PTYP: Memory type.
Defines the type of device attached to the corresponding memory bank:
0: Reserved, must be kept at reset value
1: NAND Flash (default after reset)
Bit 2 PBKEN: NAND Flash memory bank enable bit.
Enables the memory bank. Accessing a disabled memory bank causes an ERROR on AHB
bus
0: Corresponding memory bank is disabled (default after reset)
1: Corresponding memory bank is enabled
Bit 1 PWAITEN: Wait feature enable bit.
Enables the Wait feature for the NAND Flash memory bank:
0: disabled
1: enabled
Bit 0 Reserved, must be kept at reset value
FIFO status and interrupt register (FMC_SR)
Address offset: 0x84
Reset value: 0x0000 0040
This register contains information about the FIFO status and interrupt. The FMC features a
FIFO that is used when writing to memories to transfer up to 16 words of data from the AHB.
This is used to quickly write to the FIFO and free the AHB for transactions to peripherals
other than the FMC, while the FMC is draining its FIFO into the memory. One of these
register bits indicates the status of the FIFO, for ECC purposes.
The ECC is calculated while the data are written to the memory. To read the correct ECC,
the software must consequently wait until the FIFO is empty.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
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15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FEMPT
IFEN
ILEN
IREN
IFS
ILS
IRS
r
rw
rw
rw
rw
rw
rw
Bits 31:7 Reserved, must be kept at reset value
Bit 6 FEMPT: FIFO empty.
Read-only bit that provides the status of the FIFO
0: FIFO not empty
1: FIFO empty
Bit 5 IFEN: Interrupt falling edge detection enable bit
0: Interrupt falling edge detection request disabled
1: Interrupt falling edge detection request enabled
Bit 4 ILEN: Interrupt high-level detection enable bit
0: Interrupt high-level detection request disabled
1: Interrupt high-level detection request enabled
Bit 3 IREN: Interrupt rising edge detection enable bit
0: Interrupt rising edge detection request disabled
1: Interrupt rising edge detection request enabled
Bit 2 IFS: Interrupt falling edge status
The flag is set by hardware and reset by software.
0: No interrupt falling edge occurred
1: Interrupt falling edge occurred
Note: If this bit is written by software to 1 it will be set.
Bit 1 ILS: Interrupt high-level status
The flag is set by hardware and reset by software.
0: No Interrupt high-level occurred
1: Interrupt high-level occurred
Bit 0 IRS: Interrupt rising edge status
The flag is set by hardware and reset by software.
0: No interrupt rising edge occurred
1: Interrupt rising edge occurred
Note: If this bit is written by software to 1 it will be set.
Common memory space timing register 2..4 (FMC_PMEM)
Address offset: Address: 0x88
Reset value: 0xFCFC FCFC
The FMC_PMEM read/write register contains the timing information for NAND Flash
memory bank. This information is used to access either the common memory space of the
NAND Flash for command, address write access and data read/write access.
31
30
29
28
27
26
25
24
23
22
21
MEMHIZx
20
19
18
17
16
MEMHOLDx
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
MEMWAITx
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rw
MEMSETx
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Flexible memory controller (FMC)
Bits 31:24 MEMHIZ[7:0]: Common memory x data bus Hi-Z time
Defines the number of HCLK clock cycles during which the data bus is kept Hi-Z after the
start of a NAND Flash write access to common memory space on socket. This is only valid
for write transactions:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 MEMHOLD[7:0]: Common memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write accesses) after the
command is deasserted (NWE, NOE), for NAND Flash read or write access to common
memory space on socket x:
0000 0000: reserved.
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 MEMWAIT[7:0]: Common memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to common memory space on socket. The
duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.
Bits 7:0 MEMSET[7:0]: Common memory x setup time
Defines the number of HCLK (+1) clock cycles to set up the address before the command
assertion (NWE, NOE), for NAND Flash read or write access to common memory space on
socket x:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved
Attribute memory space timing registers (FMC_PATT)
Address offset: 0x8C
Reset value: 0xFCFC FCFC
The FMC_PATT read/write register contains the timing information for NAND Flash memory
bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the
last address write access if the timing must differ from that of previous accesses (for
Ready/Busy management, refer to Section 13.6.5: NAND Flash prewait functionality).
31
30
29
28
27
26
25
24
23
22
21
ATTHIZ
20
19
18
17
16
ATTHOLD
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
ATTWAIT
rw
ATTSET
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Bits 31:24 ATTHIZ[7:0]: Attribute memory data bus Hi-Z time
Defines the number of HCLK clock cycles during which the data bus is kept in Hi-Z after the
start of a NAND Flash write access to attribute memory space on socket. Only valid for writ
transaction:
0000 0000: 0 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
Bits 23:16 ATTHOLD[7:0]: Attribute memory hold time
Defines the number of HCLK clock cycles for write access and HCLK (+2) clock cycles for
read access during which the address is held (and data for write access) after the command
deassertion (NWE, NOE), for NAND Flash read or write access to attribute memory space
on socket:
0000 0000: reserved
0000 0001: 1 HCLK cycle for write access / 3 HCLK cycles for read access
1111 1110: 254 HCLK cycles for write access / 256 HCLK cycles for read access
1111 1111: reserved.
Bits 15:8 ATTWAIT[7:0]: Attribute memory wait time
Defines the minimum number of HCLK (+1) clock cycles to assert the command (NWE,
NOE), for NAND Flash read or write access to attribute memory space on socket x. The
duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the
end of the programmed value of HCLK:
0000 0000: reserved
0000 0001: 2 HCLK cycles (+ wait cycle introduced by deassertion of NWAIT)
1111 1110: 255 HCLK cycles (+ wait cycle introduced by deasserting NWAIT)
1111 1111: reserved.
Bits 7:0 ATTSET[7:0]: Attribute memory setup time
Defines the number of HCLK (+1) clock cycles to set up address before the command
assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space on
socket:
0000 0000: 1 HCLK cycle
1111 1110: 255 HCLK cycles
1111 1111: reserved.
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Flexible memory controller (FMC)
ECC result registers (FMC_ECCR)
Address offset: 0x94
Reset value: 0x0000 0000
This register contain the current error correction code value computed by the ECC
computation modules of the FMC NAND controller. When the CPU reads the data from a
NAND Flash memory page at the correct address (refer to Section 13.6.6: Computation of
the error correction code (ECC) in NAND Flash memory), the data read/written from/to the
NAND Flash memory are processed automatically by the ECC computation module. When
X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU
must read the computed ECC value from the FMC_ECC registers. It then verifies if these
computed parity data are the same as the parity value recorded in the spare area, to
determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register
should be cleared after being read by setting the ECCEN bit to ‘0’. To compute a new data
block, the ECCEN bit must be set to ’1’.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ECCx
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
ECCx
r
r
r
r
r
r
r
r
Bits 31:0 ECC: ECC result
This field contains the value computed by the ECC computation logic. Table 86 describes
the contents of these bit fields.
Table 86. ECC result relevant bits
ECCPS[2:0]
Page size in bytes
ECC bits
000
256
ECC[21:0]
001
512
ECC[23:0]
010
1024
ECC[25:0]
011
2048
ECC[27:0]
100
4096
ECC[29:0]
101
8192
ECC[31:0]
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13.7
SDRAM controller
13.7.1
SDRAM controller main features
The main features of the SDRAM controller are the following:
13.7.2
•
Two SDRAM banks with independent configuration
•
8-bit, 16-bit, 32-bit data bus width
•
13-bits Address Row, 11-bits Address Column, 4 internal banks: 4x16Mx32bit
(256 MB), 4x16Mx16bit (128 MB), 4x16Mx8bit (64 MB)
•
Word, half-word, byte access
•
SDRAM clock can be HCLK/2 or HCLK/3
•
Automatic row and bank boundary management
•
Multibank ping-pong access
•
Programmable timing parameters
•
Automatic Refresh operation with programmable Refresh rate
•
Self-refresh mode
•
Power-down mode
•
SDRAM power-up initialization by software
•
CAS latency of 1,2,3
•
Cacheable Read FIFO with depth of 6 lines x32-bit (6 x14-bit address tag)
SDRAM External memory interface signals
At startup, the SDRAM I/O pins used to interface the FMC SDRAM controller with the
external SDRAM devices must configured by the user application. The SDRAM controller
I/O pins which are not used by the application, can be used for other purposes.
Table 87. SDRAM signals
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SDRAM signal
I/O
type
Description
Alternate function
SDCLK
O
SDRAM clock
-
SDCKE[1:0]
O
SDCKE0: SDRAM Bank 1 Clock Enable
SDCKE1: SDRAM Bank 2 Clock Enable
-
SDNE[1:0]
O
SDNE0: SDRAM Bank 1 Chip Enable
SDNE1: SDRAM Bank 2 Chip Enable
-
A[12:0]
O
Address
FMC_A[12:0]
D[31:0]
I/O
Bidirectional data bus
FMC_D[31:0]
BA[1:0]
O
Bank Address
FMC_A[15:14]
NRAS
O
Row Address Strobe
-
NCAS
O
Column Address Strobe
-
SDNWE
O
Write Enable
-
NBL[3:0]
O
Output Byte Mask for write accesses
(memory signal name: DQM[3:0]
FMC_NBL[3:0]
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13.7.3
Flexible memory controller (FMC)
SDRAM controller functional description
All SDRAM controller outputs (signals, address and data) change on the falling edge of the
memory clock (FMC_SDCLK).
SDRAM initialization
The initialization sequence is managed by software. If the two banks are used, the
initialization sequence must be generated simultaneously to Bank 1and Bank 2 by setting
the Target Bank bits CTB1 and CTB2 in the FMC_SDCMR register:
1.
Program the memory device features into the FMC_SDCRx register. The SDRAM
clock frequency, RBURST and RPIPE must be programmed in the FMC_SDCR1
register.
2.
Program the memory device timing into the FMC_SDTRx register. The TRP and TRC
timings must be programmed in the FMC_SDTR1 register.
3.
Set MODE bits to ‘001’ and configure the Target Bank bits (CTB1 and/or CTB2) in the
FMC_SDCMR register to start delivering the clock to the memory (SDCKE is driven
high).
4.
Wait during the prescribed delay period. Typical delay is around 100 μs (refer to the
SDRAM datasheet for the required delay after power-up).
5.
Set MODE bits to ‘010’ and configure the Target Bank bits (CTB1 and/or CTB2) in the
FMC_SDCMR register to issue a “Precharge All” command.
6.
Set MODE bits to ‘011’, and configure the Target Bank bits (CTB1 and/or CTB2) as well
as the number of consecutive Auto-refresh commands (NRFS) in the FMC_SDCMR
register. Refer to the SDRAM datasheet for the number of Auto-refresh commands that
should be issued. Typical number is 8.
7.
Configure the MRD field according to the SDRAM device, set the MODE bits to '100',
and configure the Target Bank bits (CTB1 and/or CTB2) in the FMC_SDCMR register
to issue a "Load Mode Register" command in order to program the SDRAM device.
In particular:
a)
the CAS latency must be selected following configured value in FMC_SDCR1/2
registers
b)
the Burst Length (BL) of 1 must be selected by configuring the M[2:0] bits to 000 in
the mode register. Please refer to SDRAM device datasheet.
If the Mode Register is not the same for both SDRAM banks, this step has to be
repeated twice, once for each bank, and the Target Bank bits set accordingly.
8.
Program the refresh rate in the FMC_SDRTR register
The refresh rate corresponds to the delay between refresh cycles. Its value must be
adapted to SDRAM devices.
9.
For mobile SDRAM devices, to program the extended mode register it should be done
once the SDRAM device is initialized: First, a dummy read access should be performed
while BA1=1 and BA=0 (refer to SDRAM address mapping section for BA[1:0] address
mapping) in order to select the extended mode register instead of the load mode
register and then program the needed value.
At this stage the SDRAM device is ready to accept commands. If a system reset occurs
during an ongoing SDRAM access, the data bus might still be driven by the SDRAM device.
Therefor the SDRAM device must be first reinitialized after reset before issuing any new
access by the NOR Flash/PSRAM/SRAM or NAND Flash controller.
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Note:
RM0385
If two SDRAM devices are connected to the FMC, all the accesses performed at the same
time to both devices by the Command Mode register (Load Mode Register command) are
issued using the timing parameters configured for SDRAM Bank 1 (TMRD andTRAS
timings) in the FMC_SDTR1 register.
SDRAM controller write cycle
The SDRAM controller accepts single and burst write requests and translates them into
single memory accesses. In both cases, the SDRAM controller keeps track of the active row
for each bank to be able to perform consecutive write accesses to different banks (Multibank
ping-pong access).
Before performing any write access, the SDRAM bank write protection must be disabled by
clearing the WP bit in the FMC_SDCRx register.
Figure 54. Burst write SDRAM access waveforms
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-36
The SDRAM controller always checks the next access.
•
If the next access is in the same row or in another active row, the write operation is
carried out,
•
if the next access targets another row (not active), the SDRAM controller generates a
precharge command, activates the new row and initiates a write command.
SDRAM controller read cycle
The SDRAM controller accepts single and burst read requests and translates them into
single memory accesses. In both cases, the SDRAM controller keeps track of the active row
in each bank to be able to perform consecutive read accesses in different banks (Multibank
ping-pong access).
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Flexible memory controller (FMC)
Figure 55. Burst read SDRAM access
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The FMC SDRAM controller features a Cacheable read FIFO (6 lines x 32 bits). It is used to
store data read in advance during the CAS latency period and the RPIPE delay following the
below formula. The RBURST bit must be set in the FMC_SDCR1 register to anticipate the
next read access.
Number for anticipated data = CAS latency + 1 + (RPIPE delay)/2
Examples:
•
CAS latency = 3, RPIPE delay = 0: Four data (not committed) are stored in the FIFO.
•
CAS latency = 3, RPIPE delay = 0: Five data (not committed) are stored in the FIFO.
The read FIFO features a 14-bit address tag to each line to identify its content: 11 bits for the
column address, 2 bits to select the internal bank and the active row, and 1 bit to select the
SDRAM device
When the end of the row is reached in advance during an AHB burst read, the data read in
advance (not committed) are not stored in the read FIFO. For single read access, data are
correctly stored in the FIFO.
Each time a read request occurs, the SDRAM controller checks:
•
If the address matches one of the address tags, data are directly read from the FIFO
and the corresponding address tag/ line content is cleared and the remaining data in
the FIFO are compacted to avoid empty lines.
•
Otherwise, a new read command is issued to the memory and the FIFO is updated with
new data. If the FIFO is full, the older data are lost.
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Figure 56. Logic diagram of Read access with RBURST bit set (CAS=1, RPIPE=0)
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During a write access or a Precharge command, the read FIFO is flushed and ready to be
filled with new data.
After the first read request, if the current access was not performed to a row boundary, the
SDRAM controller anticipates the next read access during the CAS latency period and the
RPIPE delay (if configured). This is done by incrementing the memory address. The
following condition must be met:
•
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RBURST control bit should be set to ‘1’ in the FMC_SDCR1 register.
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Flexible memory controller (FMC)
The address management depends on the next AHB request:
•
Next AHB request is sequential (AHB Burst)
In this case, the SDRAM controller increments the address.
•
Next AHB request is not sequential
–
If the new read request targets the same row or another active row, the new
address is passed to the memory and the master is stalled for the CAS latency
period, waiting for the new data from memory.
–
If the new read request does not target an active row, the SDRAM controller
generates a Precharge command, activates the new row, and initiates a read
command.
If the RURST is reset, the read FIFO is not used.
Row and bank boundary management
When a read or write access crosses a row boundary, if the next read or write access is
sequential and the current access was performed to a row boundary, the SDRAM controller
executes the following operations:
1.
Precharge of the active row,
2.
Activation of the new row
3.
Start of a read/write command.
At a row boundary, the automatic activation of the next row is supported for all columns and
data bus width configurations.
If necessary, the SDRAM controller inserts additional clock cycles between the following
commands:
•
Between Precharge and Active commands to match TRP parameter (only if the next
access is in a different row in the same bank),
•
Between Active and Read commands to match the TRCD parameter.
These parameters are defined into the FMC_SDTRx register.
Refer to Figure 54 and Figure 55 for read and burst write access crossing a row boundary.
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Figure 57. Read access crossing row boundary
420
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-36
Figure 58. Write access crossing row boundary
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Flexible memory controller (FMC)
If the next access is sequential and the current access crosses a bank boundary, the
SDRAM controller activates the first row in the next bank and initiates a new read/write
command. Two cases are possible:
•
If the current bank is not the last one, the active row in the new bank must be
precharged.At a bank boundary, the automatic activation of the next row is supported
for all rows/columns and data bus width configuration.
•
If the current bank is the last one, the automatic activation of the next row is supported
only when addressing 13-bit rows, 11-bit columns, 4 internal banks and 32-bit data bus
SDRAM devices. Otherwise, the SDRAM address range is violated and an AHB error is
generated.
•
In case of 13-bit row address, 11-bit column address, 4 internal banks and bus width
32-bit SDRAM memories, at boundary bank, the SDRAM controller continues to
read/write from the second SDRAM device (assuming it has been initialized):
a)
The SDRAM controller activates the first row (after precharging the active row, if
there is already an active row in the first internal bank, and initiates a new
read/write command.
b)
If the first row is already activated, the SDRAM controller just initiates a read/write
command.
SDRAM controller refresh cycle
The Auto-refresh command is used to refresh the SDRAM device content. The SDRAM
controller periodically issues auto-refresh commands. An internal counter is loaded with the
COUNT value in the register FMC_SDRTR. This value defines the number of memory clock
cycles between the refresh cycles (refresh rate). When this counter reaches zero, an
internal pulse is generated.
If a memory access is ongoing, the auto-refresh request is delayed. However, if the memory
access and the auto-refresh requests are generated simultaneously, the auto-refresh
request takes precedence.
If the memory access occurs during an auto-refresh operation, the request is buffered and
processed when the auto-refresh is complete.
If a new auto-refresh request occurs while the previous one was not served, the RE
(Refresh Error) bit is set in the Status register. An Interrupt is generated if it has been
enabled (REIE = ‘1’).
If SDRAM lines are not in idle state (not all row are closed), the SDRAM controller generates
a PALL (Precharge ALL) command before the auto-refresh.
If the Auto-refresh command is generated by the FMC_SDCMR Command Mode register
(Mode bits = ‘011’), a PALL command (Mode bits =’ 010’) must be issued first.
13.7.4
Low-power modes
Two low-power modes are available:
•
Self-refresh mode
The auto-refresh cycles are performed by the SDRAM device itself to retain data
without external clocking.
•
Power-down mode
The auto-refresh cycles are performed by the SDRAM controller.
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Self-refresh mode
This mode is selected by setting the MODE bits to ‘101’ and by configuring the Target Bank
bits (CTB1 and/or CTB2) in the FMC_SDCMR register.
The SDRAM clock stops running after a TRAS delay and the internal refresh timer stops
counting only if one of the following conditions is met:
•
A Self-refresh command is issued to both devices
•
One of the devices is not activated (SDRAM bank is not initialized).
Before entering Self-Refresh mode, the SDRAM controller automatically issues a PALL
command.
If the Write data FIFO is not empty, all data are sent to the memory before activating the
Self-refresh mode and the BUSY status flag remains set.
In Self-refresh mode, all SDRAM device inputs become don’t care except for SDCKE which
remains low.
The SDRAM device must remain in Self-refresh mode for a minimum period of time of
TRAS and can remain in Self-refresh mode for an indefinite period beyond that. To
guarantee this minimum period, the BUSY status flag remains high after the Self-refresh
activation during a TRAS delay.
As soon as an SDRAM device is selected, the SDRAM controller generates a sequence of
commands to exit from Self-refresh mode. After the memory access, the selected device
remains in Normal mode.
To exit from Self-refresh, the MODE bits must be set to ‘000’ (Normal mode) and the Target
Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.
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Flexible memory controller (FMC)
Figure 59. Self-refresh mode
4
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-36
Power-down mode
This mode is selected by setting the MODE bits to ‘110’ and by configuring the Target Bank
bits (CTB1 and/or CTB2) in the FMC_SDCMR register.
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Figure 60. Power-down mode
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-36
If the Write data FIFO is not empty, all data are sent to the memory before activating the
Power-down mode.
As soon as an SDRAM device is selected, the SDRAM controller exits from the Power-down
mode. After the memory access, the selected SDRAM device remains in Normal mode.
During Power-down mode, all SDRAM device input and output buffers are deactivated
except for the SDCKE which remains low.
The SDRAM device cannot remain in Power-down mode longer than the refresh period and
cannot perform the Auto-refresh cycles by itself. Therefore, the SDRAM controller carries
out the refresh operation by executing the operations below:
1.
Exit from Power-down mode and drive the SDCKE high
2.
Generate the PALL command only if a row was active during Power-down mode
3.
Generate the auto-refresh command
4.
Drive SDCKE low again to return to Power-down mode.
To exit from Power-down mode, the MODE bits must be set to ‘000’ (Normal mode) and the
Target Bank bits (CTB1 and/or CTB2) must be configured in the FMC_SDCMR register.
13.7.5
SDRAM controller registers
SDRAM Control registers 1,2 (FMC_SDCR1,2)
Address offset: 0x140+ 4* (x – 1), x = 1,2
Reset value: 0x0000 02D0
This register contains the control parameters for each SDRAM memory bank
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Flexible memory controller (FMC)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
6
5
4
3
2
1
Res.
RPIPE[1:0]
rw
rw
RBURST
rw
SDCLK
rw
rw
WP
rw
7
CAS
rw
NB
rw
rw
MWID
rw
NR
rw
rw
0
NC
rw
rw
rw
Bits 31:15 Reserved, must be kept at reset value
Bits 14:13 RPIPE[1:0]: Read pipe
These bits define the delay, in clock cycles, for reading data after CAS latency.
00: No clock cycle delay
01: One clock cycle delay
10: Two clock cycle delay
11: reserved.
Note: The corresponding bits in the FMC_SDCR2 register is read only.
Bit 12 RBURST: Burst read
This bit enables burst read mode. The SDRAM controller anticipates the next read commands
during the CAS latency and stores data in the Read FIFO.
0: single read requests are not managed as bursts
1: single read requests are always managed as bursts
Note: The corresponding bit in the FMC_SDCR2 register is don’t care.
Bits 11:10 SDCLK[1:0]: SDRAM clock configuration
These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock
before changing the frequency. In this case the SDRAM must be re-initialized.
00: SDCLK clock disabled
01: reserved
10: SDCLK period = 2 x HCLK periods
11: SDCLK period = 3 x HCLK periods
Note: The corresponding bits in the FMC_SDCR2 register are don’t care.
Bit 9 WP: Write protection
This bit enables write mode access to the SDRAM bank.
0: Write accesses allowed
1: Write accesses ignored
Bits 8:7 CAS[1:0]: CAS Latency
This bits sets the SDRAM CAS latency in number of memory clock cycles
00: reserved.
01: 1 cycle
10: 2 cycles
11: 3 cycles
Bit 6 NB: Number of internal banks
This bit sets the number of internal banks.
0: Two internal Banks
1: Four internal Banks
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Flexible memory controller (FMC)
RM0385
Bits 5:4 MWID[1:0]: Memory data bus width.
These bits define the memory device width.
00: 8 bits
01: 16 bits
10: 32 bits
11: reserved.
Bits 3:2 NR[1:0]: Number of row address bits
These bits define the number of bits of a row address.
00: 11 bit
01: 12 bits
10: 13 bits
11: reserved.
Bits 1:0 NC[1:0]: Number of column address bits
These bits define the number of bits of a column address.
00: 8 bits
01: 9 bits
10: 10 bits
11: 11 bits.
Note:
Before modifying the RBURST or RPIPE settings or disabling the SDCLK clock, the user
must first send a PALL command to make sure ongoing operations are complete.
SDRAM Timing registers 1,2 (FMC_SDTR1,2)
Address offset: 0x148 + 4 * (x – 1), x = 1,2
Reset value: 0x0FFF FFFF
This register contains the timing parameters of each SDRAM bank
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
27
26
rw
rw
11
10
rw
24
23
22
rw
rw
rw
rw
9
8
7
6
TRCD
TRC
rw
25
rw
rw
rw
20
19
18
rw
rw
rw
rw
5
4
3
2
TRP
TRAS
rw
21
rw
rw
rw
16
rw
rw
1
0
rw
rw
TWR
TXSR
rw
17
TMRD
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value
Bits 27:24 TRCD[3:0]: Row to column delay
These bits define the delay between the Activate command and a Read/Write command in number
of memory clock cycles.
0000: 1 cycle.
0001: 2 cycles
....
1111: 16 cycles
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Flexible memory controller (FMC)
Bits 23:20 TRP[3:0]: Row precharge delay
These bits define the delay between a Precharge command and another command in number of
memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two
SDRAM devices are used, the TRP must be programmed with the timing of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: The corresponding bits in the FMC_SDTR2 register are don’t care.
Bits 19:16 TWR[3:0]: Recovery delay
These bits define the delay between a Write and a Precharge command in number of memory clock
cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM
datasheet, and to guarantee that:
TWR ≥ TRAS - TRCD and TWR ≥TRC - TRCD - TRP
Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR >= 2 cycles. TWR must be
programmed to 0x1.
If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed
with the same TWR timing corresponding to the slowest SDRAM device.
Bits 15:12 TRC[3:0]: Row cycle delay
These bits define the delay between the Refresh command and the Activate command, as well as
the delay between two consecutive Refresh commands. It is expressed in number of memory clock
cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are
used, the TRC must be programmed with the timings of the slowest device.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM
device datasheet.
Note: The corresponding bits in the FMC_SDTR2 register are don’t care.
Bits 11:8 TRAS[3:0]: Self refresh time
These bits define the minimum Self-refresh period in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Bits 7:4 TXSR[3:0]: Exit Self-refresh delay
These bits define the delay from releasing the Self-refresh command to issuing the Activate
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed
with the same TXSR timing corresponding to the slowest SDRAM device.
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Flexible memory controller (FMC)
RM0385
Bits 3:0 TMRD[3:0]: Load Mode Register to Active
These bits define the delay between a Load Mode Register command and an Active or Refresh
command in number of memory clock cycles.
0000: 1 cycle
0001: 2 cycles
....
1111: 16 cycles
Note:
If two SDRAM devices are connected, all the accesses performed simultaneously to both
devices by the Command Mode register (Load Mode Register command) are issued using
the timing parameters configured for Bank 1 (TMRD and TRAS timings) in the FMC_SDTR1
register.
The TRP and TRC timings are only configured in the FMC_SDTR1 register. If two SDRAM
devices are used, the TRP and TRC timings must be programmed with the timings of the
slowest device.
SDRAM Command Mode register (FMC_SDCMR)
Address offset: 0x150
Reset value: 0x0000 0000
This register contains the command issued when the SDRAM device is accessed. This
register is used to initialize the SDRAM device, and to activate the Self-refresh and the
Power-down modes. As soon as the MODE field is written, the command will be issued only
to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register
is the same for both SDRAM banks.
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
CTB1
CTB2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
MRD
rw
21
20
19
18
17
16
rw
rw
rw
rw
3
2
1
0
MRD
NRFS
MODE
rw
rw
rw
Bits 31:22 Reserved, must be kept at reset value
Bits 21:9 MRD[12:0]: Mode Register definition
This 13-bit field defines the SDRAM Mode Register content. The Mode Register is programmed
using the Load Mode Register command.
Bits 8:5 NRFS[3:0]: Number of Auto-refresh
These bits define the number of consecutive Auto-refresh commands issued when MODE = ‘011’.
0000: 1 Auto-refresh cycle
0001: 2 Auto-refresh cycles
....
1110: 15 Auto-refresh cycles
1111: 16 Auto-refresh cycles
Bit 4 CTB1: Command Target Bank 1
This bit indicates whether the command will be issued to SDRAM Bank 1 or not.
0: Command not issued to SDRAM Bank 1
1: Command issued to SDRAM Bank 1
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Flexible memory controller (FMC)
Bit 3 CTB2: Command Target Bank 2
This bit indicates whether the command will be issued to SDRAM Bank 2 or not.
0: Command not issued to SDRAM Bank 2
1: Command issued to SDRAM Bank 2
Bits 2:0 MODE[2:0]: Command mode
These bits define the command issued to the SDRAM device.
000: Normal Mode
001: Clock Configuration Enable
010: PALL (“All Bank Precharge”) command
011: Auto-refresh command
100: Load Mode Register
101: Self-refresh command
110: Power-down command
111: Reserved
Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be
set otherwise the command will be ignored.
Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued
simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will
be ignored.
Note: If only one SDRAM bank is used and a command is issued with it’s associated CTB bit set, the
other CTB bit of the the unused bank must be kept to 0.
SDRAM Refresh Timer register (FMC_SDRTR)
Address offset:0x154
Reset value: 0x0000 0000
This register sets the refresh rate in number of SDCLK clock cycles between the refresh
cycles by configuring the Refresh Timer Count value.
Refresh rate = ( COUNT + 1 ) × SDRAM clock frequency
COUNT = ( SDRAM refresh period ⁄ Number of rows ) – 20
Example
Refresh rate = 64 ms ⁄ ( 8196rows ) = 7.81μs
where 64 ms is the SDRAM refresh period.
7.81μs × 60MHz = 468.6
The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to
obtain a safe margin if an internal refresh request occurs when a read request has been
accepted. It corresponds to a COUNT value of ‘0000111000000’ (448).
This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This
timer generates a refresh pulse when zero is reached. The COUNT value must be set at
least to 41 SDRAM clock cycles.
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RM0385
As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value
programmed in the register is ’0’, no refresh is carried out. This register must not be
reprogrammed after the initialization procedure to avoid modifying the refresh rate.
Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.
If a memory access is in progress, the Auto-refresh request is delayed. However, if the
memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh
takes precedence. If the memory access occurs during a refresh operation, the request is
buffered to be processed when the refresh is complete.
This register is common to SDRAM bank 1 and bank 2.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Res.
REIE
rw
COUNT
rw
rw
rw
rw
rw
rw
rw
0
CRE
rw
rw
rw
rw
rw
rw
w
Bits 31: 15 Reserved, must be kept at reset value
Bit 14 REIE: RES Interrupt Enable
0: Interrupt is disabled
1: An Interrupt is generated if RE = 1
Bits 13:1 COUNT[12:0]: Refresh Timer Count
This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory
clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29).
Refresh rate = (COUNT + 1) x SDRAM frequency clock
COUNT = (SDRAM refresh period / Number of rows) - 20
Bit 0 CRE: Clear Refresh error flag
This bit is used to clear the Refresh Error Flag (RE) in the Status Register.
0: no effect
1: Refresh Error flag is cleared
Note:
The programmed COUNT value must not be equal to the sum of the following timings:
TWR+TRP+TRC+TRCD+4 memory clock cycles .
SDRAM Status register (FMC_SDSR)
Address offset: 0x158
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
4
3
2
1
15
14
13
12
11
10
9
8
7
6
5
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BUSY
r
Bits 31:5 Reserved, must be kept at reset value
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MODES2
MODES1
r
r
r
r
0
RE
r
RM0385
Flexible memory controller (FMC)
Bit 5 BUSY: Busy status
This bit defines the status of the SDRAM controller after a Command Mode request
0: SDRAM Controller is ready to accept a new request
1; SDRAM Controller is not ready to accept a new request
Bits 4:3 MODES2[1:0]: Status Mode for Bank 2
This bit defines the Status Mode of SDRAM Bank 2.
00: Normal Mode
01: Self-refresh mode
10: Power-down mode
Bits 2:1 MODES1[1:0]: Status Mode for Bank 1
This bit defines the Status Mode of SDRAM Bank 1.
00: Normal Mode
01: Self-refresh mode
10: Power-down mode
Bit 0 RE: Refresh error flag
0: No refresh error has been detected
1: A refresh error has been detected
An interrupt is generated if REIE = 1 and RE = 1
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13.8
RM0385
FMC register map
The following table summarizes the FMC registers.
Reset value
378/1671
0
0
WAITPOL
BURSTEN
0
0
0
1
CPSIZE
[2:0]
FACCEN
WAITEN
WREN
WAITCFG
WAITPOL
BURSTEN
0
1
1
0
0
0
1
CPSIZE
[2:0]
WAITEN
WREN
WAITCFG
WAITPOL
BURSTEN
FACCEN
0
0
1
1
0
0
0
0
0
0
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
1
1
1
1
1
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
1
1
1
1
1
1
1
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
1
1
1
1
1
DATLAT[3:0]
CLKDIV[3:0] BUSTURN[3:0]
1
1
1
1
1
1
1
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
Res.
1
1
1
1
1
1
1
1
1
1
DocID026670 Rev 6
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Res.
0
MWID MTYP
[1:0] [1:0]
0
0
1
0
MWID MTYP
[1:0] [1:0]
1
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
DATAST[7:0]
1
1
1
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
1
0
0
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
1
1
MWID MTYP
[1:0] [1:0]
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
BUSTURN[3:0]
1
Res.
DATAST[7:0]
Res.
EXTMOD
0
0
Res.
ASYNCWAIT
0
0
MBKEN
WAITCFG
1
MUXEN
WREN
1
1
1
MBKEN
FACCEN
WAITEN
0
Res.
EXTMOD
0
0
Res.
ASYNCWAIT
0
0
1
1
MUXEN
CPSIZE
[2:0]
0
0
MBKEN
1
MUXEN
BURSTEN
0
MBKEN
WAITPOL
0
MWID MTYP
[1:0] [1:0]
MUXEN
WREN
WAITCFG
0
Res.
WAITEN
1
FACCEN
EXTMOD
1
Res.
ASYNCWAIT
0
0
Res.
0
ACCMOD[1:0]
FMC_BWTR1
Res.
0x104
0
Res.
Reset value
0
ACCMOD[1:0]
Res.
FMC_BTR4
0x1C
0
Res.
Reset value
0
ACCMOD[1:0]
Res.
FMC_BTR3
0x14
0
Res.
Reset value
0
ACCMOD[1:0]
Res.
FMC_BTR2
0x0C
0
Res.
Reset value
ACCMOD[1:0]
Res.
FMC_BTR1
0x04
0
Res.
Reset value
0
0
EXTMOD
Res.
Res.
CBURSTRW
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BCR4
Res.
0
Res.
Reset value
CBURSTRW
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BCR3
0
CPSIZE
[2:0]
ASYNCWAIT
CCLKEN
CBURSTRW
0
CBURSTRW
Res.
WFDIS
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
Res.
0x18
0
Reset value
Res.
0x10
Res.
FMC_BCR2
0x08
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_BCR1
0x00
Res.
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 88. FMC register map
1
1
1
1
1
1
1
1
ADDHLD[3:0] ADDSET[3:0]
1
1
1
1
1
1
1
1
1
1
RM0385
Flexible memory controller (FMC)
1
1
1
0
0
Res.
Res.
Res.
1
TCLR[3:0]
0
0
0
0
0
1
1
1
1
1
1
MEMHOLDx[7:0]
0
0
1
1
ATTHIZ[7:0]
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
ATTSET[7:0]
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RPIPE[
1:0]
0
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
1
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
TMRD[3:0]
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TMRD[3:0]
0
NRFS[3:0]
1
MODE[2:0]
COUNT[12:0]
0
DocID026670 Rev 6
0
TXSR[3:0]
Res.
0
1
Res.
0
1
Res.
0
0
TXSR[3:0]
Res.
0
0
Res.
0
1
TRAS[3:0]
MRD[12:0]
Res.
Res.
Res.
Res.
Res.
Res.
1
0
0
CRE
1
1
Res.
Res.
Res.
1
1
0
TRAS[3:0]
TRC[3:0]
REIE
Res.
Res.
1
Res.
Res.
1
Res.
Res.
1
1
Res.
1
1
TWR[3:0]
Res.
1
Res.
1
Res.
1
Res.
1
TRC[3:0]
Res.
1
Res.
1
1
Res.
1
1
SDCLK
CAS
MWID
WP
NB
NR[1:0] NC
[1:0]
[1:0]
[1:0]
0
0
Res.
Res.
Res.
Res.
Res.
Res.
0
MWID
CAS
SDCLK
NR[1:0] NC
NB
WP
[1:0]
[1:0]
[1:0]
MODES1[1:0]
0
CTB2
0
MODES2[1:0]
0
TWR[3:0]
TRP[3:0]
1
Res.
Res.
Res.
Res.
Res.
FMC_SDSR
0
CTB1
0
Reset value
0x158
0
MEMSETx[7:0]
Res.
1
1
Res.
Res.
Res.
Res.
Res.
FMC_SDRTR
1
BUSY
0
Res.
1
Res.
Res.
1
TRCD[3:0]
Res.
Res.
Res.
Res.
Res.
1
TRP[3:0]
Reset value
0x154
1
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x150
Reset value
FMC_SDCMR
TRCD[3:0]
1
Res.
0x14C
0
1
0
Reset value
FMC_SDTR2
PWID
[1:0]
1
1
RBURST
0
0
Res.
0x148
1
1
Reset value
FMC_SDTR1
1
1
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
FMC_SDCR2
1
ATTWAIT[7:0]
Reset value
0x144
1
1
ECCx[31:0]
Res.
FMC_SDCR1
0
Res.
FMC_ECCR
Reset value
0
ATTHOLD[7:0]
1
1
0
MEMWAITx[7:0]
Res.
Reset value
1
Res.
0x140
1
Res.
0x94
1
FMC_PATT
Res.
0x8C
Reset value
Res.
0x88
1
1
MEMHIZx[7:0]
1
Res.
1
Reset value
FMC_PMEM
1
PWAITEN
0
1
ILS
0
1
IRS
0
1
ADDHLD[3:0] ADDSET[3:0]
Res.
0
Res.
TAR[3:0]
1
1
PTYP
1
1
PBKEN
1
1
IFS
1
1
ADDHLD[3:0] ADDSET[3:0]
DATAST[7:0]
1
1
ILEN
1
1
IREN
ECCPS
[2:0]
1
1
IFEN
1
1
Res.
1
1
ECCEN
1
1
1
FEMPT
1
1
Res.
1
1
Res.
1
1
Res.
1
1
Res.
1
Res.
Res.
Res.
Res.
Res.
1
DATAST[7:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
FMC_SR
Res.
0x84
1
BUSTURN[3:0]
1
Reset value
1
ADDHLD[3:0] ADDSET[3:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ACCMOD[1:0]
ACCMOD[1:0]
0
1
DATAST[7:0]
BUSTURN[3:0]
1
Res.
FMC_PCR
Res.
0x80
0
Res.
Reset value
BUSTURN[3:0]
1
0
ACCMOD[1:0]
FMC_BWTR4
Res.
0x11C
0
Res.
Reset value
0
Res.
FMC_BWTR3
Res.
0x114
0
Res.
Reset value
Res.
FMC_BWTR2
Res.
0x10C
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 88. FMC register map (continued)
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Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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14
Quad-SPI interface (QUADSPI)
14.1
Introduction
The QUADSPI is a specialized communication interface targeting single, dual or quad SPI
Flash memories. It can operate in any of the three following modes:
•
indirect mode: all the operations are performed using the QUADSPI registers
•
status polling mode: the external Flash memory status register is periodically read and
an interrupt can be generated in case of flag setting
•
memory-mapped mode: the external Flash memory is mapped to the microcontroller
address space and is seen by the system as if it was an internal memory
Both throughput and capacity can be increased two-fold using dual-flash mode, where two
Quad-SPI Flash memories are accessed simultaneously.
14.2
QUADSPI main features
•
Three functional modes: indirect, status-polling, and memory-mapped
•
Dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two
Flash memories in parallel.
•
SDR and DDR support
•
Fully programmable opcode for both indirect and memory mapped mode
•
Fully programmable frame format for both indirect and memory mapped mode
•
Integrated FIFO for reception and transmission
•
8, 16, and 32-bit data accesses are allowed
•
DMA channel for indirect mode operations
•
Interrupt generation on FIFO threshold, timeout, operation complete, and access error
14.3
QUADSPI functional description
14.3.1
QUADSPI block diagram
Figure 61. QUADSPI block diagram when dual-flash mode is disabled
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Figure 62. QUADSPI block diagram when dual-flash mode is enabled
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The QUADSPI uses 6 signals to interface with a single Flash memory, or 10 to 11 signals to
interface with two Flash memories (FLASH 1 and FLASH 2) in dual-flash mode:
14.3.2
–
CLK - Clock output, for both memories
–
BK1_IO0/SO - Bidirectional IO in dual/quad modes or serial output in single mode,
for FLASH 1
–
BK1_IO1/SI - Bidirectional IO in dual/quad modes or serial input in single mode,
for FLASH 1
–
BK1_IO2 - Bidirectional IO in quad mode, for FLASH 1
–
BK1_IO3 - Bidirectional IO in quad mode, for FLASH 1
–
BK2_IO0/SO - Bidirectional IO in dual/quad modes or serial output in single mode,
for FLASH 2
–
BK2_IO1/SI - Bidirectional IO in dual/quad modes or serial input in single mode,
for FLASH 2
–
BK2_IO2 - Bidirectional IO in quad mode, for FLASH 2
–
BK2_IO3 - Bidirectional IO in quad mode, for FLASH 2
–
BK1_nCS - Chip select output (active low), for FLASH 1. Can also be used for
FLASH 2 if QUADSPI is always used in dual-flash mode.
–
BK2_nCS - Chip select output (active low), for FLASH 2. Can also be used for
FLASH 1 if QUADSPI is always used in dual-flash mode.
QUADSPI Command sequence
The QUADSPI communicates with the Flash memory using commands. Each command
can include 5 phases: instruction, address, alternate byte, dummy, data. Any of these
phases can be configured to be skipped, but at least one of the instruction, address,
alternate byte, or data phase must be present.
nCS falls before the start of each command and rises again after each command finishes.
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Figure 63. An example of a read command in quad mode
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Instruction phase
During this phase, an 8-bit instruction, configured in INSTRUCTION field of
QUADSPI_CCR[7:0] register, is sent to the Flash memory, specifying the type of operation
to be performed.
Though most Flash memories can receive instructions only one bit at a time from the
IO0/SO signal (single SPI mode), the instruction phase can optionally send 2 bits at a time
(over IO0/IO1 in dual SPI mode) or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the IMODE[1:0] field of QUADSPI_CCR[9:8] register.
When IMODE = 00, the instruction phase is skipped, and the command sequence starts
with the address phase, if present.
Address phase
In the address phase, 1-4 bytes are sent to the Flash memory to indicate the address of the
operation. The number of address bytes to be sent is configured in the ADSIZE[1:0] field of
QUADSPI_CCR[13:12] register. In indirect and automatic-polling modes, the address bytes
to be sent are specified in the ADDRESS[31:0] field of QUADSPI_AR register, while in
memory-mapped mode the address is given directly via the AHB (from the Cortex® or from
a DMA).
The address phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a time
(over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the ADMODE[1:0] field of QUADSPI_CCR[11:10]
register.
When ADMODE = 00, the address phase is skipped, and the command sequence proceeds
directly to the next phase, if any.
Alternate-bytes phase
In the alternate-bytes phase, 1-4 bytes are sent to the Flash memory, generally to control
the mode of operation. The number of alternate bytes to be sent is configured in the
ABSIZE[1:0] field of QUADSPI_CCR[17:16] register. The bytes to be sent are specified in
the QUADSPI_ABR register.
The alternate-bytes phase can send 1 bit at a time (over SO in single SPI mode), 2 bits at a
time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14]
register.
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When ABMODE = 00, the alternate-bytes phase is skipped, and the command sequence
proceeds directly to the next phase, if any.
There may be times when only a single nibble needs to be sent during the alternate-byte
phase rather than a full byte, such as when dual-mode is used and only two cycles are used
for the alternate bytes. In this case, firmware can use quad-mode (ABMODE = 11) and send
a byte with bits 7 and 3 of ALTERNATE set to ‘1’ (keeping the IO3 line high), and bits 6 and
2 set to ‘0’ (keeping the IO2 line low). In this case the upper two bits of the nibble to be sent
are placed in bits 4:3 of ALTERNATE while the lower two bits are placed in bits 1 and 0. For
example, if the nibble 2 (0010) is to be sent over IO0/IO1, then ALTERNATE should be set
to 0x8A (1000_1010).
Dummy-cycles phase
In the dummy-cycles phase, 1-31 cycles are given without any data being sent or received,
in order to allow the Flash memory the time to prepare for the data phase when higher clock
frequencies are used. The number of cycles given during this phase is specified in the
DCYC[4:0] field of QUADSPI_CCR[22:18] register. In both SDR and DDR modes, the
duration is specified as a number of full CLK cycles.
When DCYC is zero, the dummy-cycles phase is skipped, and the command sequence
proceeds directly to the data phase, if present.
The operating mode of the dummy-cycles phase is determined by DMODE.
In order to assure enough “turn-around” time for changing the data signals from output
mode to input mode, there must be at least one dummy cycle when using dual or quad
mode to receive data from the Flash memory.
Data phase
During the data phase, any number of bytes can be sent to, or received from the Flash
memory.
In indirect and automatic-polling modes, the number of bytes to be sent/received is specified
in the QUADSPI_DLR register.
In indirect write mode the data to be sent to the Flash memory must be written to the
QUADSPI_DR register, while in indirect read mode the data received from the Flash
memory is obtained by reading from the QUADSPI_DR register.
In memory-mapped mode, the data which is read is sent back directly over the AHB to the
Cortex or to a DMA.
The data phase can send/receive 1 bit at a time (over SO/SI in single SPI mode), 2 bits at a
time (over IO0/IO1 in dual SPI mode), or 4 bits at a time (over IO0/IO1/IO2/IO3 in quad SPI
mode). This can be configured using the ABMODE[1:0] field of QUADSPI_CCR[15:14]
register.
When DMODE = 00, the data phase is skipped, and the command sequence finishes
immediately by raising nCS. This configuration must only be used in only indirect write
mode.
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14.3.3
Quad-SPI interface (QUADSPI)
QUADSPI signal interface protocol modes
Single SPI mode
Legacy SPI mode allows just a single bit to be sent/received serially. In this mode, data is
sent to the Flash memory over the SO signal (whose I/O shared with IO0). Data received
from the Flash memory arrives via SI (whose I/O shared with IO1).
The different phases can each be configured separately to use this single bit mode by
setting the IMODE/ADMODE/ABMODE/DMODE fields (in QUADSPI_CCR) to 01.
In each phase which is configured in single mode:
•
IO0 (SO) is in output mode
•
IO1 (SI) is in input mode (high impedance)
•
IO2 is in output mode and forced to ‘0’ (to deactivate the “write protect” function)
•
IO3 is in output mode and forced to ‘1’ (to deactivate the “hold” function)
This is the case even for the dummy phase if DMODE = 01.
Dual SPI mode
In dual SPI mode, two bits are sent/received simultaneously over the IO0/IO1 signals.
The different phases can each be configured separately to use dual SPI mode by setting the
IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 10.
In each phase which is configured in dual mode:
•
IO0/IO1 are at high-impedance (input) during the data phase for read operations, and
outputs in all other cases
•
IO2 is in output mode and forced to ‘0’
•
IO3 is in output mode and forced to ‘1’
In the dummy phase when DMODE = 01, IO0/IO1 are always high-impedance.
Quad SPI mode
In quad SPI mode, four bits are sent/received simultaneously over the IO0/IO1/IO2/IO3
signals.
The different phases can each be configured separately to use quad SPI mode by setting
the IMODE/ADMODE/ABMODE/DMODE fields of QUADSPI_CCR register to 11.
In each phase which is configured in quad mode, IO0/IO1/IO2/IO3 are all are at highimpedance (input) during the data phase for read operations, and outputs in all other cases.
In the dummy phase when DMODE = 11, IO0/IO1/IO2/IO3 are all high-impedance.
IO2 and IO3 are used only in Quad SPI mode. If none of the phases are configured to use
Quad SPI mode, then the pins corresponding to IO2 and IO3 can be used for other functions
even while QUADSPI is active.
SDR mode
By default, the DDRM bit (QUADSPI_CCR[31]) is 0 and the QUADSPI operates in single
data rate (SDR) mode.
In SDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals, these
signals transition only with the falling edge of CLK.
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When receiving data in SDR mode, the QUADSPI assumes that the Flash memories also
send the data using CLK’s falling edge. By default (when SSHIFT = 0), the signals are
sampled using the following (rising) edge of CLK.
DDR mode
When the DDRM bit (QUADSPI_CCR[31]) is set to 1, the QUADSPI operates in double data
rate (DDR) mode.
In DDR mode, when the QUADSPI is driving the IO0/SO, IO1, IO2, IO3 signals in the
address/alternate-byte/data phases, a bit is sent on each of the falling and rising edges of
CLK.
The instruction phase is not affected by DDRM. The instruction is always sent using CLK’s
falling edge.
When receiving data in DDR mode, the QUADSPI assumes that the Flash memories also
send the data using both rising and falling CLK edges. When DDRM = 1, firmware must
clear SSHIFT bit (QUADSPI_CR[4]). Thus, the signals are sampled one half of a CLK cycle
later (on the following, opposite edge).
Figure 64. An example of a DDR command in quad mode
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Dual-flash mode
When the DFM bit (QUADSPI_CR[6]) is 1, the QUADSPI is in dual-flash mode, where two
external quad SPI Flash memories (FLASH 1 and FLASH 2) are used in order to
send/receive 8 bits (or 16 bits in DDR mode) every cycle, effectively doubling the throughput
as well as the capacity.
Each of the Flash memories use the same CLK and optionally the same nCS signals, but
each have separate IO0, IO1, IO2, and IO3 signals.
Dual-flash mode can be used in conjunction with single-bit, dual-bit, and quad-bit modes, as
well as with either SDR or DDR mode.
The Flash memory size, as specified in FSIZE[4:0] (QUADSPI_DCR[20:16]), should reflect
the total Flash memory capacity, which is double the size of one individual component.
If address X is even, then the byte which the QUADSPI gives for address X is the byte at the
address X/2 of FLASH 1, and the byte which the QUADSPI gives for address X+1 is the
byte at the address X/2 of FLASH 2. In other words, bytes at even addresses are all stored
in FLASH 1 and bytes at odd addresses are all stored in FLASH 2.
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When reading the Flash memories status registers in dual-flash mode, twice as many bytes
should be read compared to doing the same read in single-flash mode. This means that if
each Flash memory gives 8 valid bits after the instruction for fetching the status register,
then the QUADSPI must be configured with a data length of 2 bytes (16 bits), and the
QUADSPI will receive one byte from each Flash memory. If each Flash memory gives a
status of 16 bits, then the QUADSPI must be configured to read 4 bytes to get all the status
bits of both Flash memories in dual-flash mode. The least-significant byte of the result (in
the data register) is the least-significant byte of FLASH 1 status register, while the next byte
is the least-significant byte of FLASH 2 status register. Then, the third byte of the data
register is FLASH 1 second byte, while the forth byte is FLASH 2 second byte (in the case
that the Flash memories have 16-bit status registers).
An even number of bytes must always be accessed in dual-flash mode. For this reason, bit
0 of the data length field (QUADSPI_DLR[0]) is stuck at 1 when DRM = 1.
In dual-flash mode, the behavior of FLASH 1 interface signals are basically the same as in
normal mode. FLASH 2 interface signals have exactly the same waveforms as FLASH 1
during the instruction, address, alternate-byte, and dummy-cycles phases. In other words,
each Flash memory always receives the same instruction and the same address. Then,
during the data phase, the BK1_IOx and BK2_IOx buses are both transferring data in
parallel, but the data that are sent to (or received from) FLASH 1 are distinct from those of
FLASH 2.
14.3.4
QUADSPI indirect mode
When in indirect mode, commands are started by writing to QUADSPI registers and data is
transferred by writing or reading the data register, in the same way as for other
communication peripherals.
When FMODE = 00 (QUADSPI_CCR[27:26]), the QUADSPI is in indirect write mode,
where bytes are sent to the Flash memory during the data phase. Data are provided by
writing to the data register (QUADSPI_DR).
When FMODE = 01, the QUADSPI is in indirect read mode, where bytes are received from
the Flash memory during the data phase. Data are recovered by reading QUADSPI_DR.
The number of bytes to be read/written is specified in the data length register
(QUADSPI_DLR). If QUADSPI_DLR = 0xFFFF_FFFF (all 1’s), then the data length is
considered undefined and the QUADSPI simply continues to transfer data until the end of
Flash memory (as defined by FSIZE) is reached. If no bytes are to be transferred, DMODE
(QUADSPI_CCR[25:24]) should be set to 00.
If QUADSPI_DLR = 0xFFFF_FFFF and FSIZE = 0x1F (max value indicating a 4GB Flash
memory), then in this special case the transfers continue indefinitely, stopping only after an
abort request or after the QUADSPI is disabled. After the last memory address is read (at
address 0xFFFF_FFFF), reading continues with address = 0x0000_0000.
When the programmed number of bytes to be transmitted or received is reached, TCF is set
and an interrupt is generated if TCIE = 1. In the case of undefined number of data, the TCF
is set when the limit of the external SPI memory is reached according to the Flash memory
size defined in the QUADSPI_CR.
Triggering the start of a command
Essentially, a command starts as soon as firmware gives the last information that is
necessary for this command. Depending on the QUADSPI configuration, there are three
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different ways to trigger the start of a command in indirect mode. The commands starts
immediately after:
1.
a write is performed to INSTRUCTION[7:0] (QUADSPI_CCR), if no address is
necessary (when ADMODE = 00) and if no data needs to be provided by the firmware
(when FMODE = 01 or DMODE = 00)
2.
a write is performed to ADDRESS[31:0] (QUADSPI_AR), if an address is necessary
(when ADMODE != 00) and if no data needs to be provided by the firmware (when
FMODE = 01 or DMODE = 00)
3.
a write is performed to DATA[31:0] (QUADSPI_DR), if an address is necessary (when
ADMODE != 00) and if data needs to be provided by the firmware (when FMODE = 00
and DMODE != 00)
Writes to the alternate byte register (QUADSPI_ABR) never trigger the communication start.
If alternate bytes are required, they must be programmed before.
As soon as a command is started, the BUSY bit (bit 5 of QUADSPI_SR) is automatically set.
FIFO and data management
In indirect mode, data go through a 32-byte FIFO which is internal to the QUADSPI.
FLEVEL[5:0] (QUADSPI_SR[13:8]) indicates how many bytes are currently being held in
the FIFO.
In indirect write mode (FMODE = 00), firmware adds data to the FIFO when it writes
QUADSPI_DR. Word writes add 4 bytes to the FIFO, halfword writes add 2 bytes, and byte
writes add only 1 byte. If firmware adds too many bytes to the FIFO (more than is indicated
by DL[31:0]), the extra bytes are flushed from the FIFO at the end of the write operation
(when TCF is set).
Byte/halfword accesses to QUADSPI_DR must be done only to the least significant
byte/halfword of the 32-bit register.
FTHRES[3:0] is used to define a FIFO threshold. When the threshold is reached, the FTF
(FIFO threshold flag) is set. In indirect read mode, FTF is set when the number of valid
bytes to be read from the FIFO is above the threshold. FTF is also set if there are data in the
FIFO after the last byte is read from the Flash memory, regardless of the FTHRES setting.
In indirect write mode, FTF is set when the number of empty bytes in the FIFO is above the
threshold.
If FTIE = 1, there is an interrupt when FTF is set. If DMAEN = 1, a DMA transfer is initiated
when FTF is set. FTF is cleared by HW as soon as the threshold condition is no longer true
(after enough data has been transferred by the CPU or DMA).
In indirect read mode when the FIFO becomes full, the QUADSPI temporarily stops reading
bytes from the Flash memory to avoid an overrun. Please note that the reading of the Flash
memory does not restart until 4 bytes become vacant in the FIFO (when FLEVEL ≤ 11).
Thus, when FTHRES ≥ 13, the application must take care to read enough bytes to assure
that the QUADSPI will start retrieving data from the Flash memory again. Otherwise, the
FTF flag will stay at '0' as long as 11 < FLEVEL < FTHRES.
14.3.5
QUADSPI status flag polling mode
In automatic-polling mode, the QUADSPI periodically starts a command to read a defined
number of status bytes (up to 4). The received bytes can be masked to isolate some status
bits and an interrupt can be generated when the selected bits have a defined value.
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The accesses to the Flash memory begin in the same way as in indirect read mode: if no
address is required (AMODE = 00), accesses begin as soon as the QUADSPI_CCR is
written. Otherwise, if an address is required, the first access begins when QUADSPI_AR is
written. BUSY goes high at this point and stays high even between the periodic accesses.
The contents of MASK[31:0] (QUADSPI_PSMAR) are used to mask the data from the Flash
memory in automatic-polling mode. If the MASK[n] = 0, then bit n of the result is masked
and not considered. If MASK[n] = 1, and the content of bit[n] is the same as MATCH[n]
(QUADSPI_PSMAR), then there is a match for bit n.
If the polling match mode bit (PMM, QUADSPI_CR[23]) is 0, then “AND” match mode is
activated. This means status match flag (SMF) is set only when there is a match on all of the
unmasked bits.
If PMM = 1, then “OR” match mode is activated. This means SMF is set if there is a match
on any of the unmasked bits.
An interrupt is called when SMF is set if SMIE = 1.
If the automatic-polling-mode-stop (APMS) bit is set, operation stops and BUSY goes to 0
as soon as a match is detected. Otherwise, BUSY stays at ‘1’ and the periodic accesses
continue until there is an abort or the QUADSPI is disabled (EN = 0).
The data register (QUADSPI_DR) contains the latest received status bytes (the FIFO is
deactivated). The content of the data register is not affected by the masking used in the
matching logic. The FTF status bit is set as soon as a new reading of the status is complete,
and FTF is cleared as soon as the data is read.
14.3.6
QUADSPI memory-mapped mode
When configured in memory-mapped mode, the external SPI device is seen as an internal
memory.
It is forbidden to access QUADSPI Flash bank area before having properly configured and
enabled the QUADSPI peripheral.
No more than 256MB can addressed even if the Flash memory capacity is larger.
If an access is made to an address outside of the range defined by FSIZE but still within the
256MB range, then an AHB error is given. The effect of this error depends on the AHB
master that attempted the access:
•
If it is the Cortex® CPU, a hard fault interrupt is generated
•
If it is a DMA, a DMA transfer error is generated and the corresponding DMA channel is
automatically disabled.
Byte, halfword, and word access types are all supported.
Support for execute in place (XIP) operation is implemented, where the QUADSPI
anticipates the next microcontroller access and load in advance the byte at the following
address. If the subsequent access is indeed made at a continuous address, the access will
be completed faster since the value is already prefetched.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with nCS maintained low, even if no access to the Flash memory occurs for
a long time. Since Flash memories tend to consume more when nCS is held low, the
application might want to activate the timeout counter (TCEN = 1, QUADSPI_CR[3]) so that
nCS is released after a period of TIMEOUT[15:0] (QUADSPI_LPTR) cycles have elapsed
without any access since when the FIFO becomes full with prefetch data.
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BUSY goes high as soon as the first memory-mapped access occurs. Because of the
prefetch operations, BUSY does not fall until there is a timeout, there is an abort, or the
peripheral is disabled.
14.3.7
QUADSPI Flash memory configuration
The device configuration register (QUADSPI_DCR) can be used to specify the
characteristics of the external SPI Flash memory.
The FSIZE[4:0] field defines the size of external memory using the following formula:
Number of bytes in Flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the Flash memory.
The Flash memory capacity can be up to 4GB (addressed using 32 bits) in indirect mode,
but the addressable space in memory-mapped mode is limited to 256MB.
If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.
When the QUADSPI executes two commands, one immediately after the other, it raises the
chip select signal (nCS) high between the two commands for only one CLK cycle by default.
If the Flash memory requires more time between commands, the chip select high time
(CSHT) field can be used to specify the minimum number of CLK cycles (up to 8) that nCS
must remain high.
The clock mode (CKMODE) bit indicates the CLK signal logic level in between commands
(when nCS = 1).
14.3.8
QUADSPI delayed data sampling
By default, the QUADSPI samples the data driven by the Flash memory one half of a CLK
cycle after the Flash memory drives the signal.
In case of external signal delays, it may be beneficial to sample the data later. Using the
SSHIFT bit (QUADSPI_CR[4]), the sampling of the data can be shifted by half of a CLK
cycle.
Clock shifting is not supported in DDR mode: the SSHIFT bit must be clear when DDRM bit
is set.
14.3.9
QUADSPI configuration
The QUADSPI configuration is done in two phases:
•
QUADSPI IP configuration
•
QUADSPI Flash memory configuration
Once configured and enabled, the QUADSPI can be used in one of its three operating
modes: indirect mode, status-polling mode, or memory-mapped mode.
QUADSPI IP configuration
The QUADSPI IP is configured using the QUADSPI_CR. The user shall configure the clock
prescaler division factor and the sample shifting settings for the incoming data.
DDR mode can be set through the DDRM bit. Once enabled, the address and the alternate
bytes are sent on both clock edges and the data are sent/received on both clock edges.
Regardless of the DDRM bit setting, instructions are always sent in SDR mode.
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The DMA requests are enabled setting the DMAEN bit. In case of interrupt usage, their
respective enable bit can be also set during this phase.
FIFO level for either DMA request generation or interrupt generation is programmed in the
FTHRES bits.
If timeout counter is needed, the TCEN bit can be set and the timeout value programmed in
the QUADSPI_LPTR register.
Dual-flash mode can be activated by setting DFM to 1.
QUADSPI Flash memory configuration
The parameters related to the targeted external Flash memory are configured through the
QUADSPI_DCR register.The user shall program the Flash memory size in the FSIZE bits,
the Chip Select minimum high time in the CSHT bits, and the functional mode (Mode 0 or
Mode 3) in the MODE bit.
14.3.10
QUADSPI usage
The operating mode is selected using FMODE[1:0] (QUADSPI_CCR[27:26]).
Indirect mode procedure
When FMODE is programmed to 00, indirect write mode is selected and data can be sent to
the Flash memory. With FMODE = 01, indirect read mode is selected where data can be
read from the Flash memory.
When the QUADSPI is used in indirect mode, the frames are constructed in the following
way:
1.
Specify a number of data bytes to read or write in the QUADSPI_DLR
2.
Specify the frame format, mode and instruction code in the QUADSPI_CCR
3.
Specify optional alternate byte to be sent right after the address phase in the
QUADSPI_ABR
4.
Specify the operating mode in the QUADSPI_CR. If FMODE = 00 (indirect write mode)
and DMAEN = 1, then QUADSPI_AR should be specified before QUADSPI_CR,
because otherwise QUADSPI_DR might be written by the DMA before QUADSPI_AR
is updated (if the DMA controller has already been enabled)
5.
Specify the targeted address in the QUADSPI_AR
6.
Read/Write the data from/to the FIFO through the QUADSPI_DR
When writing the control register (QUADSPI_CR) the user specifies the following settings:
•
The enable bit (EN) set to ‘1’
•
The DMA enable bit (DMAEN) for transferring data to/from RAM
•
Timeout counter enable bit (TCEN)
•
Sample shift setting (SSHIFT)
•
FIFO threshold level (FTRHES) to indicate when the FTF flag should be set
•
Interrupt enables
•
Automatic polling mode parameters: match mode and stop mode (valid when
FMODE = 11)
•
Clock prescaler
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When writing the communication configuration register (QUADSPI_CCR) the user specifies
the following parameters:
•
The instruction byte through the INSTRUCTION bits
•
The way the instruction has to be sent through the IMODE bits (1/2/4 lines)
•
The way the address has to be sent through the ADMODE bits (None/1/2/4 lines)
•
The address size (8/16/24/32-bit) through the ADSIZE bits
•
The way the alternate bytes have to be sent through the ABMODE (None/1/2/4 lines)
•
The alternate bytes number (1/2/3/4) through the ABSIZE bits
•
The presence or not of dummy bytes through the DBMODE bit
•
The number of dummy bytes through the DCYC bits
•
The way the data have to be sent/received (None/1/2/4 lines) through the DMODE bits
If neither the address register (QUADSPI_AR) nor the data register (QUADSPI_DR) need to
be updated for a particular command, then the command sequence starts as soon as
QUADSPI_CCR is written. This is the case when both ADMODE and DMODE are 00, or if
just ADMODE = 00 when in indirect read mode (FMODE = 01).
When an address is required (ADMODE is not 00) and the data register does not need to be
written (when FMODE = 01 or DMODE = 00), the command sequence starts as soon as the
address is updated with a write to QUADSPI_AR.
In case of data transmission (FMODE = 00 and DMODE! = 00), the communication start is
triggered by a write in the FIFO through QUADSPI_DR.
Status flag polling mode
The status flag polling mode is enabled setting the FMODE field (QUADSPI_CCR[27:26]) to
10. In this mode, the programmed frame will be sent and the data retrieved periodically.
The maximum amount of data read in each frame is 4 bytes. If more data is requested in
QUADSPI_DLR, it will be ignored and only 4 bytes will be read.
The periodicity is specified in the QUADSPI_PISR register.
Once the status data has been retrieved, it can internally be processed i order to:
•
set the status match flag and generate an interrupt if enabled
•
stop automatically the periodic retrieving of the status bytes
The received value can be masked with the value stored in the QUADSPI_PSMKR and
ORed or ANDed with the value stored in the QUADSPI_PSMAR.
In case of match, the status match flag is set and an interrupt is generated if enabled, and
the QUADSPI can be automatically stopped if the AMPS bit is set.
In any case, the latest retrieved value is available in the QUADSPI_DR.
Memory-mapped mode
In memory-mapped mode, the external Flash memory is seen as internal memory but with
some latency during accesses. Only read operations are allowed to the external Flash
memory in this mode.
Memory-mapped mode is entered by setting the FMODE to 11 in the QUADSPI_CCR
register.
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The programmed instruction and frame is sent when an AHB master is accessing the
memory mapped space.
The FIFO is used as a prefetch buffer to anticipate linear reads. Any access to
QUADSPI_DR in this mode returns zero.
The data length register (QUADSPI_DLR) has no meaning in memory-mapped mode.
14.3.11
Sending the instruction only once
Some Flash memories (e.g. Winbound) might provide a mode where an instruction must be
sent only with the first command sequence, while subsequent commands start directly with
the address. One can take advantage of such a feature using the SIOO bit
(QUADSPI_CCR[28]).
SIOO is valid for all functional modes (indirect, automatic polling, and memory-mapped). If
the SIOO bit is set, the instruction is sent only for the first command following a write to
QUADSPI_CCR. Subsequent command sequences skip the instruction phase, until there is
a write to QUADSPI_CCR.
SIOO has no effect when IMODE = 00 (no instruction).
14.3.12
QUADSPI error management
A error can be generated in the following case:
14.3.13
•
In indirect mode or status flag polling mode when a wrong address has been
programmed in the QUADSPI_AR (according to the Flash memory size defined by
FSIZE[4:0] in the QUADSPI_DCR): this will set the TEF and an interrupt is generated if
enabled.
•
Also in indirect mode, if the address plus the data length exceeds the Flash memory
size, TEF will be set as soon as the access is triggered.
•
In memory-mapped mode, when an out of range access is done by an AHB master or
when the QUADSPI is disabled: this will generate an AHB error as a response to the
faulty AHB request.
•
When an AHB master is accessing the memory mapped space while the memory
mapped mode is disabled: this will generate an AHB error as a response to the faulty
AHB request.
QUADSPI busy bit and abort functionality
Once the QUADSPI starts an operation with the Flash memory, the BUSY bit is
automatically set in the QUADSPI_SR.
In indirect mode, the BUSY bit is reset once the QUADSPI has completed the requested
command sequence and the FIFO is empty.
In automatic-polling mode, BUSY goes low only after the last periodic access is complete,
due to a match when APMS = 1, or due to an abort.
After the first access in memory-mapped mode, BUSY goes low only on a timeout event or
on an abort.
Any operation can be aborted by setting the ABORT bit in the QUADSPI_CR. Once the
abort is completed, the BUSY bit and the ABORT bit are automatically reset, and the FIFO
is flushed.
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Note:
Some Flash memories might misbehave if a write operation to a status registers is aborted.
14.3.14
nCS behavior
By default, nCS is high, deselecting the external Flash memory. nCS falls before an
operation begins and rises as soon as it finishes.
When CKMODE = 0 (“mode0”, where CLK stays low when no operation is in progress) nCS
falls one CLK cycle before an operation first rising CLK edge, and nCS rises one CLK cycle
after the operation final rising CLK edge, as shown in Figure 65.
Figure 65. nCS when CKMODE = 0 (T = CLK period)
7
7
Q&6
6&/.
069
When CKMODE=1 (“mode3”, where CLK goes high when no operation is in progress) and
DDRM=0 (SDR mode), nCS still falls one CLK cycle before an operation first rising CLK
edge, and nCS rises one CLK cycle after the operation final rising CLK edge, as shown in
Figure 66.
Figure 66. nCS when CKMODE = 1 in SDR mode (T = CLK period)
7
7
Q&6
6&/.
069
When CKMODE = 1 (“mode3”) and DDRM = 1 (DDR mode), nCS falls one CLK cycle
before an operation first rising CLK edge, and nCS rises one CLK cycle after the operation
final active rising CLK edge, as shown in Figure 67. Because DDR operations must finish
with a falling edge, CLK is low when nCS rises, and CLK rises back up one half of a CLK
cycle afterwards.
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Figure 67. nCS when CKMODE = 1 in DDR mode (T = CLK period)
7
7
7
Q&6
6&/.
069
When the FIFO stays full in a read operation or if the FIFO stays empty in a write operation,
the operation stalls and CLK stays low until firmware services the FIFO. If an abort occurs
when an operation is stalled, nCS rises just after the abort is requested and then CLK rises
one half of a CLK cycle later, as shown in Figure 68.
Figure 68. nCS when CKMODE = 1 with an abort (T = CLK period)
7
&ORFNVWDOOHG
7
Q&6
6&/.
$ERUW
069
When not in dual-flash mode (DFM = 0), only FLASH 1 is accessed and thus the BK2_nCS
stays high. In dual-flash mode, BK2_nCS behaves exactly the same as BK1_nCS. Thus, if
there is a FLASH 2 and if the application always stays in dual-flash mode, then FLASH 2
may use BK1_nCS and the pin outputting BK2_nCS can be used for other functions.
14.4
QUADSPI interrupts
An interrupt can be produced on the following events:
•
Timeout
•
Status match
•
FIFO threshold
•
Transfer complete
•
Transfer error
Separate interrupt enable bits are available for flexibility.
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Table 89. QUADSPI interrupt requests
Interrupt event
Event flag
Enable control bit
Timeout
TOF
TOIE
Status match
SMF
SMIE
FIFO threshold
FTF
FTIE
Transfer complete
TCF
TCIE
Transfer error
TEF
TEIE
14.5
QUADSPI registers
14.5.1
QUADSPI control register (QUADSPI_CR)
Address offset: 0x0000
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
PRESCALER
23
22
21
20
19
18
17
16
PMM
APMS
Res.
TOIE
SMIE
FTIE
TCIE
TEIE
rw
rw
rw
rw
rw
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
Res.
Res.
Res.
FSEL
DFM
Res.
SSHIFT
TCEN
rw
rw
rw
rw
FTHRES
rw
rw
rw
rw
rw
DMAEN ABORT
w1s
rw
EN
w1s
Bits 31: 24 PRESCALER[7:0]: Clock prescaler
This field defines the scaler factor for generating CLK based on the AHB clock
(value+1).
0: FCLK = FAHB, AHB clock used directly as QUADSPI CLK (prescaler bypassed)
1: FCLK = FAHB/2
2: FCLK = FAHB/3
...
255: FCLK = FAHB/256
For odd clock division factors, CLK’s duty cycle is not 50%. The clock signal remains
high one cycle longer than it stays low.
This field can be modified only when BUSY = 0.
Bit 23 PMM: Polling match mode
This bit indicates which method should be used for determining a “match” during
automatic polling mode.
0: AND match mode. SMF is set if all the unmasked bits received from the Flash
memory match the corresponding bits in the match register.
1: OR match mode. SMF is set if any one of the unmasked bits received from the Flash
memory matches its corresponding bit in the match register.
This bit can be modified only when BUSY = 0.
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Bit 22 APMS: Automatic poll mode stop
This bit determines if automatic polling is stopped after a match.
0: Automatic polling mode is stopped only by abort or by disabling the QUADSPI.
1: Automatic polling mode stops as soon as there is a match.
This bit can be modified only when BUSY = 0.
Bit 21 Reserved, must be kept at reset value.
Bit 20 TOIE: TimeOut interrupt enable
This bit enables the TimeOut interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 19 SMIE: Status match interrupt enable
This bit enables the status match interrupt.
0: Interrupt disable
1: Interrupt enabled
Bit 18 FTIE: FIFO threshold interrupt enable
This bit enables the FIFO threshold interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 17 TCIE: Transfer complete interrupt enable
This bit enables the transfer complete interrupt.
0: Interrupt disabled
1: Interrupt enabled
Bit 16 TEIE: Transfer error interrupt enable
This bit enables the transfer error interrupt.
0: Interrupt disable
1: Interrupt enabled
Bits 15:13 Reserved, must be kept at reset value.
Bits 12:8 FTHRES[4:0] FIFO threshold level
Defines, in indirect mode, the threshold number of bytes in the FIFO that will cause the
FIFO threshold flag (FTF, QUADSPI_SR[2]) to be set.
In indirect write mode (FMODE = 00):
0: FTF is set if there are 1 or more free bytes available to be written to in the FIFO
1: FTF is set if there are 2 or more free bytes available to be written to in the FIFO
...
31: FTF is set if there are 32 free bytes available to be written to in the FIFO
In indirect read mode (FMODE = 01):
0: FTF is set if there are 1 or more valid bytes that can be read from the FIFO
1: FTF is set if there are 2 or more valid bytes that can be read from the FIFO
...
31: FTF is set if there are 32 valid bytes that can be read from the FIFO
If DMAEN = 1, then the DMA controller for the corresponding channel must be disabled
before changing the FTHRES value.
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Bit 7 FSEL: Flash memory selection
This bit selects the Flash memory to be addressed in single flash mode (when DFM =
0).
0: FLASH 1 selected
1: FLASH 2 selected
This bit can be modified only when BUSY = 0.
This bit is ignored when DFM = 1.
Bit 6 DFM: Dual-flash mode
This bit activates dual-flash mode, where two external Flash memories are used
simultaneously to double throughput and capacity.
0: Dual-flash mode disabled
1: Dual-flash mode enabled
This bit can be modified only when BUSY = 0.
Bit 5 Reserved, must be kept at reset value.
Bit 4 SSHIFT: Sample shift
By default, the QUADSPI samples data 1/2 of a CLK cycle after the data is driven by the
Flash memory. This bit allows the data is to be sampled later in order to account for
external signal delays.
0: No shift
1: 1/2 cycle shift
Firmware must assure that SSHIFT = 0 when in DDR mode (when DDRM = 1).
This field can be modified only when BUSY = 0.
Bit 3 TCEN: Timeout counter enable
This bit is valid only when memory-mapped mode (FMODE = 11) is selected. Activating
this bit causes the chip select (nCS) to be released (and thus reduces consumption) if
there has not been an access after a certain amount of time, where this time is defined
by TIMEOUT[15:0] (QUADSPI_LPTR).
Enable the timeout counter.
By default, the QUADSPI never stops its prefetch operation, keeping the previous read
operation active with nCS maintained low, even if no access to the Flash memory
occurs for a long time. Since Flash memories tend to consume more when nCS is held
low, the application might want to activate the timeout counter (TCEN = 1,
QUADSPI_CR[3]) so that nCS is released after a period of TIMEOUT[15:0]
(QUADSPI_LPTR) cycles have elapsed without an access since when the FIFO
becomes full with prefetch data.
0: Timeout counter is disabled, and thus the chip select (nCS) remains active
indefinitely after an access in memory-mapped mode.
1: Timeout counter is enabled, and thus the chip select is released in memory-mapped
mode after TIMEOUT[15:0] cycles of Flash memory inactivity.
This bit can be modified only when BUSY = 0.
Bit 2 DMAEN: DMA enable
In indirect mode, DMA can be used to input or output data via the QUADSPI_DR
register. DMA transfers are initiated when the FIFO threshold flag, FTF, is set.
0: DMA is disabled for indirect mode
1: DMA is enabled for indirect mode
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Bit 1 ABORT: Abort request
This bit aborts the on-going command sequence. It is automatically reset once the abort
is complete.
This bit stops the current transfer.
In polling mode or memory-mapped mode, this bit also reset the APM bit or the DM bit.
0: No abort requested
1: Abort requested
Bit 0 EN: Enable
Enable the QUADSPI.
0: QUADSPI is disabled
1: QUADSPI is enabled
14.5.2
QUADSPI device configuration register (QUADSPI_DCR)
Address offset: 0x0004
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
Res.
14
Res.
13
Res.
12
Res.
11
10
Res.
9
8
CSHT
rw
rw
7
Res.
6
Res.
rw
5
Res.
20
19
18
17
16
rw
FSIZE
rw
rw
rw
rw
4
3
2
1
0
Res.
CKMODE
Res.
Res.
Res.
rw
Bits 31: 21 Reserved, must be kept at reset value.
Bits 20: 16 FSIZE[4:0]: Flash memory size
This field defines the size of external memory using the following formula:
Number of bytes in Flash memory = 2[FSIZE+1]
FSIZE+1 is effectively the number of address bits required to address the Flash
memory. The Flash memory capacity can be up to 4GB (addressed using 32 bits) in
indirect mode, but the addressable space in memory-mapped mode is limited to
256MB.
If DFM = 1, FSIZE indicates the total capacity of the two Flash memories together.
This field can be modified only when BUSY = 0.
Bits 15: 11 Reserved, must be kept at reset value.
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Bits 10:8 CSHT[2:0]: Chip select high time
CSHT+1 defines the minimum number of CLK cycles which the chip select (nCS) must
remain high between commands issued to the Flash memory.
0: nCS stays high for at least 1 cycle between Flash memory commands
1: nCS stays high for at least 2 cycles between Flash memory commands
...
7: nCS stays high for at least 8 cycles between Flash memory commands
This field can be modified only when BUSY = 0.
Bits 7: 1 Reserved, must be kept at reset value.
Bit 0 CKMODE: Mode 0 / mode 3
This bit indicates the level that CLK takes between commands (when nCS = 1).
0: CLK must stay low while nCS is high (chip select released). This is referred to as
mode 0.
1: CLK must stay high while nCS is high (chip select released). This is referred to as
mode 3.
This field can be modified only when BUSY = 0.
14.5.3
QUADSPI status register (QUADSPI_SR)
Address offset: 0x0008
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
BUSY
TOF
SMF
FTF
TCF
TEF
r
r
r
r
r
r
FLEVEL[5:0]
r
r
r
r
r
r
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:8 FLEVEL[5:0]: FIFO level
This field gives the number of valid bytes which are being held in the FIFO. FLEVEL = 0
when the FIFO is empty, and 32 when it is full. In memory-mapped mode and in
automatic status polling mode, FLEVEL is zero.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 BUSY: Busy
This bit is set when an operation is on going. This bit clears automatically when the
operation with the Flash memory is finished and the FIFO is empty.
Bit 4 TOF: Timeout flag
This bit is set when timeout occurs. It is cleared by writing 1 to CTOF.
Bit 3 SMF: Status match flag
This bit is set in automatic polling mode when the unmasked received data matches the
corresponding bits in the match register (QUADSPI_PSMAR). It is cleared by writing 1
to CSMF.
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Bit 2 FTF: FIFO threshold flag
In indirect mode, this bit is set when the FIFO threshold has been reached, or if there is
any data left in the FIFO after reads from the Flash memory are complete. It is cleared
automatically as soon as threshold condition is no longer true.
In automatic polling mode this bit is set every time the status register is read, and the bit
is cleared when the data register is read.
Bit 1 TCF: Transfer complete flag
This bit is set in indirect mode when the programmed number of data has been
transferred or in any mode when the transfer has been aborted.It is cleared by writing 1
to CTCF.
Bit 0 TEF: Transfer error flag
This bit is set in indirect mode when an invalid address is being accessed in indirect
mode. It is cleared by writing 1 to CTEF.
14.5.4
QUADSPI flag clear register (QUADSPI_FCR)
Address offset: 0x000C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
CTOF
CSMF
Res.
CTCF
CTEF
w1o
w1o
w1o
w1o
Bits 31: 4 Reserved, must be kept at reset value.
Bit 4 CTOF: Clear timeout flag
Writing 1 clears the TOF flag in the QUADSPI_SR register
Bit 3 CSMF: Clear status match flag
Writing 1 clears the SMF flag in the QUADSPI_SR register
Bit 2 Reserved, must be kept at reset value.
Bit 1 CTCF: Clear transfer complete flag
Writing 1 clears the TCF flag in the QUADSPI_SR register
Bit 0 CTEF: Clear transfer error flag
Writing 1 clears the TEF flag in the QUADSPI_SR register
14.5.5
QUADSPI data length register (QUADSPI_DLR)
Address offset: 0x0010
Reset value: 0x0000 0000
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31
30
29
28
27
26
RM0385
25
24
23
22
21
20
19
18
17
16
DL[31:16]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
DL[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:0 DL[31: 0]: Data length
Number of data to be retrieved (value+1) in indirect and status-polling modes. A value
no greater than 3 (indicating 4 bytes) should be used for status-polling mode.
All 1s in indirect mode means undefined length, where QUADSPI will continue until the
end of memory, as defined by FSIZE.
0x0000_0000: 1 byte is to be transferred
0x0000_0001: 2 bytes are to be transferred
0x0000_0002: 3 bytes are to be transferred
0x0000_0003: 4 bytes are to be transferred
...
0xFFFF_FFFD: 4,294,967,294 (4G-2) bytes are to be transferred
0xFFFF_FFFE: 4,294,967,295 (4G-1) bytes are to be transferred
0xFFFF_FFFF: undefined length -- all bytes until the end of Flash memory (as defined
by FSIZE) are to be transferred. Continue reading indefinitely if FSIZE = 0x1F.
DL[0] is stuck at ‘1’ in dual-flash mode (DFM = 1) even when ‘0’ is written to this bit, thus
assuring that each access transfers an even number of bytes.
This field has no effect when in memory-mapped mode (FMODE = 10).
This field can be written only when BUSY = 0.
14.5.6
QUADSPI communication configuration register (QUADSPI_CCR)
Address offset: 0x0014
Reset value: 0x0000 0000
31
30
29
28
DDRM
DHHC
Res.
SIOO
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25
FMODE[1:0]
24
DMODE
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12
11
10
9
8
ADSIZE
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27
rw
ADMODE
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23
22
21
Res.
7
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19
18
17
DCYC[4:0]
16
ABSIZE
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5
4
3
2
1
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Quad-SPI interface (QUADSPI)
Bit 31 DDRM: Double data rate mode
This bit sets the DDR mode for the address, alternate byte and data phase:
0: DDR Mode disabled
1: DDR Mode enabled
This field can be written only when BUSY = 0.
Bit 30 DHHC: DDR hold
Delay the data output by 1/4 of the QUADSPI output clock cycle in DDR mode:
0: Delay the data output using analog delay
1: Delay the data output by 1/4 of a QUADSPI output clock cycle.
This feature is only active in DDR mode.
This field can be written only when BUSY = 0.
Bit 29 Reserved, must be kept at reset value.
Bit 28 SIOO: Send instruction only once mode
See Section 14.3.11: Sending the instruction only once on page 393. This bit has no
effect when IMODE = 00.
0: Send instruction on every transaction
1: Send instruction only for the first command
This field can be written only when BUSY = 0.
Bits 27:26 FMODE[1:0]: Functional mode
This field defines the QUADSPI functional mode of operation.
00: Indirect write mode
01: Indirect read mode
10: Automatic polling mode
11: Memory-mapped mode
If DMAEN = 1 already, then the DMA controller for the corresponding channel must be
disabled before changing the FMODE value.
This field can be written only when BUSY = 0.
Bits 25:24 DMODE[1:0]: Data mode
This field defines the data phase’s mode of operation:
00: No data
01: Data on a single line
10: Data on two lines
11: Data on four lines
This field also determines the dummy phase mode of operation.
This field can be written only when BUSY = 0.
Bit 23 Reserved, must be kept at reset value.
Bits 22:18 DCYC[4:0]: Number of dummy cycles
This field defines the duration of the dummy phase. In both SDR and DDR modes, it
specifies a number of CLK cycles (0-31).
This field can be written only when BUSY = 0.
Bits 17:16 ABSIZE[1:0]: Alternate bytes size
This bit defines alternate bytes size:
00: 8-bit alternate byte
01: 16-bit alternate bytes
10: 24-bit alternate bytes
11: 32-bit alternate bytes
This field can be written only when BUSY = 0.
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Bits 15:14 ABMODE[1:0]: Alternate bytes mode
This field defines the alternate-bytes phase mode of operation:
00: No alternate bytes
01: Alternate bytes on a single line
10: Alternate bytes on two lines
11: Alternate bytes on four lines
This field can be written only when BUSY = 0.
Bits 13:12 ADSIZE[1:0]: Address size
This bit defines address size:
00: 8-bit address
01: 16-bit address
10: 24-bit address
11: 32-bit address
This field can be written only when BUSY = 0.
Bits 11:10 ADMODE[1:0]: Address mode
This field defines the address phase mode of operation:
00: No address
01: Address on a single line
10: Address on two lines
11: Address on four lines
This field can be written only when BUSY = 0.
Bits 9:8 IMODE[1:0]: Instruction mode
This field defines the instruction phase mode of operation:
00: No instruction
01: Instruction on a single line
10: Instruction on two lines
11: Instruction on four lines
This field can be written only when BUSY = 0.
Bits 7: 0 INSTRUCTION[7: 0]: Instruction
Instruction to be send to the external SPI device.
This field can be written only when BUSY = 0.
14.5.7
QUADSPI address register (QUADSPI_AR)
Address offset: 0x0018
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ADDRESS[31:16]
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10
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2
1
0
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Quad-SPI interface (QUADSPI)
Bits 31:0 ADDRESS[31 0]: Address
Address to be send to the external Flash memory
Writes to this field are ignored when BUSY = 0 or when FMODE = 11 (memory-mapped
mode).
In dual flash mode, ADDRESS[0] is automatically stuck to ‘0’ as the address should
always be even
14.5.8
QUADSPI alternate bytes registers (QUADSPI_ABR)
Address offset: 0x001C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ALTERNATE[31:16]
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14
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12
11
10
9
8
7
6
5
4
3
2
1
0
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ALTERNATE[15:0]
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Bits 31: 0 ALTERNATE[31: 0]: Alternate Bytes
Optional data to be send to the external SPI device right after the address.
This field can be written only when BUSY = 0.
14.5.9
QUADSPI data register (QUADSPI_DR)
Address offset: 0x0020
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA[31:16]
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12
11
10
9
8
7
6
5
4
3
2
1
0
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DATA[15:0]
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Bits 31: 0 DATA[31: 0]: Data
Data to be sent/received to/from the external SPI device.
In indirect write mode, data written to this register is stored on the FIFO before it is sent
to the Flash memory during the data phase. If the FIFO is too full, a write operation is
stalled until the FIFO has enough space to accept the amount of data being written.
In indirect read mode, reading this register gives (via the FIFO) the data which was
received from the Flash memory. If the FIFO does not have as many bytes as requested
by the read operation and if BUSY=1, the read operation is stalled until enough data is
present or until the transfer is complete, whichever happens first.
In automatic polling mode, this register contains the last data read from the Flash
memory (without masking).
Word, halfword, and byte accesses to this register are supported. In indirect write mode,
a byte write adds 1 byte to the FIFO, a halfword write 2, and a word write 4. Similarly, in
indirect read mode, a byte read removes 1 byte from the FIFO, a halfword read 2, and a
word read 4. Accesses in indirect mode must be aligned to the bottom of this register: a
byte read must read DATA[7:0] and a halfword read must read DATA[15:0].
14.5.10
QUADSPI polling status mask register (QUADSPI _PSMKR)
Address offset: 0x0024
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MASK[31:16]
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15
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13
12
11
10
9
8
7
6
5
4
3
2
1
0
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MASK[15:0]
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Bits 31: 0 MASK[31: 0]: Status mask
Mask to be applied to the status bytes received in polling mode.
For bit n:
0: Bit n of the data received in automatic polling mode is masked and its value is not
considered in the matching logic
1: Bit n of the data received in automatic polling mode is unmasked and its value is
considered in the matching logic
This field can be written only when BUSY = 0.
14.5.11
QUADSPI polling status match register (QUADSPI _PSMAR)
Address offset: 0x0028
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Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MATCH[31:16]
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13
12
11
10
9
8
7
6
5
4
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2
1
0
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MATCH[15:0]
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Bits 31: 0 MATCH[31: 0]: Status match
Value to be compared with the masked status register to get a match.
This field can be written only when BUSY = 0.
14.5.12
QUADSPI polling interval register (QUADSPI _PIR)
Address offset: 0x002C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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INTERVAL[15:0]
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Bits 31: 16 Reserved, must be kept at reset value.
Bits 15: 0 INTERVAL[15: 0]: Polling interval
Number of CLK cycles between to read during automatic polling phases.
This field can be written only when BUSY = 0.
14.5.13
QUADSPI low-power timeout register (QUADSPI_LPTR)
Address offset: 0x0030
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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TIMEOUT[15:0]
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Bits 31: 16 Reserved, must be kept at reset value.
Bits 15: 0 TIMEOUT[15: 0]: Timeout period
After each access in memory-mapped mode, the QUADSPI prefetches the subsequent
bytes and holds these bytes in the FIFO. This field indicates how many CLK cycles the
QUADSPI waits after the FIFO becomes full until it raises nCS, putting the Flash
memory in a lower-consumption state.
This field can be written only when BUSY = 0.
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14.5.14
QUADSPI register map
0x0018
0x001C
0x0020
0x0024
0
0
0
0
0
0
0
0
0
0
Reset value
0
0
DCYC[4:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ABORT
EN
Res.
TEF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INSTRUCTION[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA[31:0]
QUADSPI_
PSMKR
0
0
0
MASK[31:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
QUADSPI_
PSMAR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
QUADSPI_PIR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
MATCH[31:0]
Reset value
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
INTERVAL[15:0]
0
Res.
QUADSPI_
LPTR
CKMODE
TCF
0
ALTERNATE[31:0]
Reset value
0x0030
TCEN
0
ADDRESS[31:0]
0
QUADSPI_DR
Reset value
DMAEN
0
CTEF
0
QUADSPI_ABR
Reset value
Res.
FTF
0
CTCF
0
IMODE[1:0]
0
Res.
0x002C
0
QUADSPI_AR
Reset value
0x0028
0
ADMODE[1:0]
0
0
ADSIZE[1:0]
0
0
ABMODE[1:0]
0
0
ABSIZE[1:0]
0
0
Res.
Reset value
0
DMODE[1:0]
QUADSPI_CCR
0
FMODE[1:0]
0
Res.
0
SIOO
Reset value
DHHC
0x0014
Res.
DFM
Res.
Res.
0
DL[31:0]
DDRM
0x0010
SSHIFT
0
Reset value
QUADSPI_DLR
Res.
FSEL
Res.
Res.
SMF
0
Res.
0
CSMF
0
TOF
0
0
CTOF
0
0
BUSY
0
0
Res.
0
Res.
Res.
Res.
Res.
Res.
FLEVEL[6:0]
0
0
0
Res.
0
0
Res.
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
QUADSPI_FCR
Res.
0
Reset value
0x000C
CSHT
Res.
0
0
Res.
0
0
Res.
0
0
Res.
0
0
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
FSIZE[4:0]
Res.
Res.
Res.
0
FTHRES
[4:0]
Res.
Res.
Res.
TEIE
Res.
Res.
0
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
QUADSPI_SR
Res.
Reset value
0x0008
0
Res.
QUADSPI_DCR
0
FTIE
0
TCIE
0
Res.
0
SMIE
0
Res.
0
Res.
0
Res.
0
TOIE
0
PRESCALER[7:0]
Res.
0
QUADSPI_CR
Res.
PMM
APMS
0
Res.
0x0004
Reset value
Res.
0x0000
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 90. QUADSPI register map and reset values
Reset value
0
0
0
0
TIMEOUT[15:0]
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 for the register boundary addresses.
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15
Analog-to-digital converter (ADC)
15.1
ADC introduction
The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19
multiplexed channels allowing it to measure signals from 16 external sources, two internal
sources, and the VBAT channel. The A/D conversion of the channels can be performed in
single, continuous, scan or discontinuous mode. The result of the ADC is stored into a leftor right-aligned 16-bit data register.
The analog watchdog feature allows the application to detect if the input voltage goes
beyond the user-defined, higher or lower thresholds.
15.2
ADC main features
•
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
•
Interrupt generation at the end of conversion, end of injected conversion, and in case of
analog watchdog or overrun events
•
Single and continuous conversion modes
•
Scan mode for automatic conversion of channel 0 to channel ‘n’
•
Data alignment with in-built data coherency
•
Channel-wise programmable sampling time
•
External trigger option with configurable polarity for both regular and injected
conversions
•
Discontinuous mode
•
Dual/Triple mode (on devices with 2 ADCs or more)
•
Configurable DMA data storage in Dual/Triple ADC mode
•
Configurable delay between conversions in Dual/Triple interleaved mode
•
ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower
speed
•
ADC input range: VREF– ≤ VIN ≤ VREF+
•
DMA request generation during regular channel conversion
Figure 69 shows the block diagram of the ADC.
Note:
VREF–, if available (depending on package), must be tied to VSSA.
15.3
ADC functional description
Figure 69 shows a single ADC block diagram and Table 91 gives the ADC pin description.
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Figure 69. Single ADC block diagram
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Table 91. ADC pins
Name
15.3.1
Signal type
Remarks
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the ADC,
1.8 V ≤ VREF+ ≤ VDDA
VDDA
Input, analog supply
Analog power supply equal to VDD and
2.4 V ≤VDDA ≤VDD (3.6 V) for full speed
1.8 V ≤VDDA ≤VDD (3.6 V) for reduced speed
VREF–
Input, analog reference
negative
The lower/negative reference voltage for the ADC,
VREF– = VSSA
VSSA
Input, analog supply
ground
Ground for analog power supply equal to VSS
ADCx_IN[15:0]
Analog input signals
16 analog input channels
ADC on-off control
The ADC is powered on by setting the ADON bit in the ADC_CR2 register. When the ADON
bit is set for the first time, it wakes up the ADC from the Power-down mode.
Conversion starts when either the SWSTART or the JSWSTART bit is set.
You can stop conversion and put the ADC in power down mode by clearing the ADON bit. In
this mode the ADC consumes almost no power (only a few µA).
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15.3.2
Analog-to-digital converter (ADC)
ADC1/2 and ADC3 connectivity
ADC1, ADC2 and ADC3 are tightly coupled and share some external channels as described
in Figure 70, Figure 71 and Figure 72.
Figure 70. ADC1 connectivity
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RM0385
Figure 71. ADC2 connectivity
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Analog-to-digital converter (ADC)
Figure 72. ADC3 connectivity
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Analog-to-digital converter (ADC)
15.3.3
RM0385
ADC clock
The ADC features two clock schemes:
•
Clock for the analog circuitry: ADCCLK, common to all ADCs
This clock is generated from the APB2 clock divided by a programmable prescaler that
allows the ADC to work at fPCLK2/2, /4, /6 or /8. Refer to the datasheets for the
maximum value of ADCCLK.
•
Clock for the digital interface (used for registers read/write access)
This clock is equal to the APB2 clock. The digital interface clock can be
enabled/disabled individually for each ADC through the RCC APB2 peripheral clock
enable register (RCC_APB2ENR).
15.3.4
Channel selection
There are 16 multiplexed channels. It is possible to organize the conversions in two groups:
regular and injected. A group consists of a sequence of conversions that can be done on
any channel and in any order. For instance, it is possible to implement the conversion
sequence in the following order: ADC_IN3, ADC_IN8, ADC_IN2, ADC_IN2, ADC_IN0,
ADC_IN2, ADC_IN2, ADC_IN15.
•
A regular group is composed of up to 16 conversions. The regular channels and their
order in the conversion sequence must be selected in the ADC_SQRx registers. The
total number of conversions in the regular group must be written in the L[3:0] bits in the
ADC_SQR1 register.
•
An injected group is composed of up to 4 conversions. The injected channels and
their order in the conversion sequence must be selected in the ADC_JSQR register.
The total number of conversions in the injected group must be written in the L[1:0] bits
in the ADC_JSQR register.
If the ADC_SQRx or ADC_JSQR registers are modified during a conversion, the current
conversion is reset and a new start pulse is sent to the ADC to convert the newly chosen
group.
Temperature sensor, VREFINT and VBAT internal channels
•
The temperature sensor is internally connected to ADC1_IN18 channel which is shared
with VBAT. Only one conversion, temperature sensor or VBAT, must be selected at a
time. When the temperature sensor and VBAT conversion are set simultaneously, only
the VBAT conversion is performed.
The internal reference voltage VREFINT is connected to ADC1_IN17.
The VBAT channel is connected to ADC1_IN18 channel. It can also be converted as an
injected or regular channel.
Note:
416/1671
The temperature sensor, VREFINT and the VBAT channel are available only on the master
ADC1 peripheral.
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RM0385
15.3.5
Analog-to-digital converter (ADC)
Single conversion mode
In Single conversion mode the ADC does one conversion. This mode is started with the
CONT bit at 0 by either:
•
setting the SWSTART bit in the ADC_CR2 register (for a regular channel only)
•
setting the JSWSTART bit (for an injected channel)
•
external trigger (for a regular or injected channel)
Once the conversion of the selected channel is complete:
•
•
If a regular channel was converted:
–
The converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
If an injected channel was converted:
–
The converted data are stored into the 16-bit ADC_JDR1 register
–
The JEOC (end of conversion injected) flag is set
–
An interrupt is generated if the JEOCIE bit is set
Then the ADC stops.
15.3.6
Continuous conversion mode
In continuous conversion mode, the ADC starts a new conversion as soon as it finishes one.
This mode is started with the CONT bit at 1 either by external trigger or by setting the
SWSTRT bit in the ADC_CR2 register (for regular channels only).
After each conversion:
•
If a regular group of channels was converted:
–
The last converted data are stored into the 16-bit ADC_DR register
–
The EOC (end of conversion) flag is set
–
An interrupt is generated if the EOCIE bit is set
Note:
Injected channels cannot be converted continuously. The only exception is when an injected
channel is configured to be converted automatically after regular channels in continuous
mode (using JAUTO bit), refer to Auto-injection section).
15.3.7
Timing diagram
As shown in Figure 73, the ADC needs a stabilization time of tSTAB before it starts
converting accurately. After the start of the ADC conversion and after 15 clock cycles, the
EOC flag is set and the 16-bit ADC data register contains the result of the conversion.
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RM0385
Figure 73. Timing diagram
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15.3.8
Analog watchdog
The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is
below a lower threshold or above a higher threshold. These thresholds are programmed in
the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can
be enabled by using the AWDIE bit in the ADC_CR1 register.
The threshold value is independent of the alignment selected by the ALIGN bit in the
ADC_CR2 register. The analog voltage is compared to the lower and higher thresholds
before alignment.
Table 92 shows how the ADC_CR1 register should be configured to enable the analog
watchdog on one or more channels.
Figure 74. Analog watchdog’s guarded area
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Channels guarded by the analog
watchdog
418/1671
ADC_CR1 register control bits (x = don’t care)
AWDSGL bit
AWDEN bit
JAWDEN bit
None
x
0
0
All injected channels
0
0
1
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RM0385
Analog-to-digital converter (ADC)
Table 92. Analog watchdog channel selection (continued)
Channels guarded by the analog
watchdog
ADC_CR1 register control bits (x = don’t care)
AWDSGL bit
AWDEN bit
JAWDEN bit
All regular channels
0
1
0
All regular and injected channels
0
1
1
Single(1)
injected channel
1
0
1
regular channel
1
1
0
1
1
1
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Single
Single (1) regular or injected channel
1. Selected by the AWDCH[4:0] bits
15.3.9
Scan mode
This mode is used to scan a group of analog channels.
The Scan mode is selected by setting the SCAN bit in the ADC_CR1 register. Once this bit
has been set, the ADC scans all the channels selected in the ADC_SQRx registers (for
regular channels) or in the ADC_JSQR register (for injected channels). A single conversion
is performed for each channel of the group. After each end of conversion, the next channel
in the group is converted automatically. If the CONT bit is set, regular channel conversion
does not stop at the last selected channel in the group but continues again from the first
selected channel.
If the DMA bit is set, the direct memory access (DMA) controller is used to transfer the data
converted from the regular group of channels (stored in the ADC_DR register) to SRAM
after each regular channel conversion.
The EOC bit is set in the ADC_SR register:
•
At the end of each regular group sequence if the EOCS bit is cleared to 0
•
At the end of each regular channel conversion if the EOCS bit is set to 1
The data converted from an injected channel are always stored into the ADC_JDRx
registers.
15.3.10
Injected channel management
Triggered injection
To use triggered injection, the JAUTO bit must be cleared in the ADC_CR1 register.
1.
Start the conversion of a group of regular channels either by external trigger or by
setting the SWSTART bit in the ADC_CR2 register.
2.
If an external injected trigger occurs or if the JSWSTART bit is set during the
conversion of a regular group of channels, the current conversion is reset and the
injected channel sequence switches to Scan-once mode.
3.
Then, the regular conversion of the regular group of channels is resumed from the last
interrupted regular conversion.
If a regular event occurs during an injected conversion, the injected conversion is not
interrupted but the regular sequence is executed at the end of the injected sequence.
Figure 75 shows the corresponding timing diagram.
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Note:
RM0385
When using triggered injection, one must ensure that the interval between trigger events is
longer than the injection sequence. For instance, if the sequence length is 30 ADC clock
cycles (that is two conversions with a sampling time of 3 clock periods), the minimum
interval between triggers must be 31 ADC clock cycles.
Auto-injection
If the JAUTO bit is set, then the channels in the injected group are automatically converted
after the regular group of channels. This can be used to convert a sequence of up to 20
conversions programmed in the ADC_SQRx and ADC_JSQR registers.
In this mode, external trigger on injected channels must be disabled.
If the CONT bit is also set in addition to the JAUTO bit, regular channels followed by injected
channels are continuously converted.
Note:
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Figure 75. Injected conversion latency
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15.3.11
Discontinuous mode
Regular group
This mode is enabled by setting the DISCEN bit in the ADC_CR1 register. It can be used to
convert a short sequence of n conversions (n ≤ 8) that is part of the sequence of
conversions selected in the ADC_SQRx registers. The value of n is specified by writing to
the DISCNUM[2:0] bits in the ADC_CR1 register.
When an external trigger occurs, it starts the next n conversions selected in the ADC_SQRx
registers until all the conversions in the sequence are done. The total sequence length is
defined by the L[3:0] bits in the ADC_SQR1 register.
420/1671
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RM0385
Analog-to-digital converter (ADC)
Example:
Note:
•
n = 3, channels to be converted = 0, 1, 2, 3, 6, 7, 9, 10
•
1st trigger: sequence converted 0, 1, 2. An EOC event is generated at each
conversion.
•
2nd trigger: sequence converted 3, 6, 7. An EOC event is generated at each
conversion
•
3rd trigger: sequence converted 9, 10.An EOC event is generated at each conversion
•
4th trigger: sequence converted 0, 1, 2. An EOC event is generated at each conversion
When a regular group is converted in discontinuous mode, no rollover occurs.
When all subgroups are converted, the next trigger starts the conversion of the first
subgroup. In the example above, the 4th trigger reconverts the channels 0, 1 and 2 in the
1st subgroup.
Injected group
This mode is enabled by setting the JDISCEN bit in the ADC_CR1 register. It can be used to
convert the sequence selected in the ADC_JSQR register, channel by channel, after an
external trigger event.
When an external trigger occurs, it starts the next channel conversions selected in the
ADC_JSQR registers until all the conversions in the sequence are done. The total sequence
length is defined by the JL[1:0] bits in the ADC_JSQR register.
Example:
n = 1, channels to be converted = 1, 2, 3
1st trigger: channel 1 converted
2nd trigger: channel 2 converted
3rd trigger: channel 3 converted and JEOC event generated
4th trigger: channel 1
Note:
When all injected channels are converted, the next trigger starts the conversion of the first
injected channel. In the example above, the 4th trigger reconverts the 1st injected channel
1.
It is not possible to use both the auto-injected and discontinuous modes simultaneously.
Discontinuous mode must not be set for regular and injected groups at the same time.
Discontinuous mode must be enabled only for the conversion of one group.
15.4
Data alignment
The ALIGN bit in the ADC_CR2 register selects the alignment of the data stored after
conversion. Data can be right- or left-aligned as shown in Figure 76 and Figure 77.
The converted data value from the injected group of channels is decreased by the userdefined offset written in the ADC_JOFRx registers so the result can be a negative value.
The SEXT bit represents the extended sign value.
For channels in a regular group, no offset is subtracted so only twelve bits are significant.
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RM0385
Figure 76. Right alignment of 12-bit data
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Special case: when left-aligned, the data are aligned on a half-word basis except when the
resolution is set to 6-bit. in that case, the data are aligned on a byte basis as shown in
Figure 78.
Figure 78. Left alignment of 6-bit data
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15.5
Channel-wise programmable sampling time
The ADC samples the input voltage for a number of ADCCLK cycles that can be modified
using the SMP[2:0] bits in the ADC_SMPR1 and ADC_SMPR2 registers. Each channel can
be sampled with a different sampling time.
The total conversion time is calculated as follows:
Tconv = Sampling time + 12 cycles
Example:
With ADCCLK = 30 MHz and sampling time = 3 cycles:
Tconv = 3 + 12 = 15 cycles = 0.5 µs with APB2 at 60 MHz
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15.6
Analog-to-digital converter (ADC)
Conversion on external trigger and trigger polarity
Conversion can be triggered by an external event (e.g. timer capture, EXTI line). If the
EXTEN[1:0] control bits (for a regular conversion) or JEXTEN[1:0] bits (for an injected
conversion) are different from “0b00”, then external events are able to trigger a conversion
with the selected polarity. Table 93 provides the correspondence between the EXTEN[1:0]
and JEXTEN[1:0] values and the trigger polarity.
Table 93. Configuring the trigger polarity
Source
Note:
EXTEN[1:0] / JEXTEN[1:0]
Trigger detection disabled
00
Detection on the rising edge
01
Detection on the falling edge
10
Detection on both the rising and falling edges
11
The polarity of the external trigger can be changed on the fly.
The EXTSEL[3:0] and JEXTSEL[3:0] control bits are used to select which out of 16 possible
events can trigger conversion for the regular and injected groups.
Table 94 gives the possible external trigger for regular conversion.
Table 94. External trigger for regular channels
Source
Type
EXTSEL[3:0]
TIM1_CH1
0000
TIM1_CH2
0001
TIM1_CH3
0010
TIM2_CH2
0011
TIM5_TRGO
0100
TIM4_CH4
0101
TIM3_CH4
TIM8_TRGO
Internal signal from on-chip timers
0110
0111
TIM8_TRGO(2)
1000
TIM1_TRGO
1001
TIM1_TRGO(2)
1010
TIM2_TRGO
1011
TIM4_TRGO
1100
TIM6_TRGO
1101
EXTI line11
External pin
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RM0385
Table 95 gives the possible external trigger for injected conversion.
Table 95. External trigger for injected channels
Source
Connection type
JEXTSEL[3:0]
TIM1_TRGO
0000
TIM1_CH4
0001
TIM2_TRGO
TIM2_CH1
Internal signal from on-chip timers
0010
0011
TIM3_CH4
0100
TIM4_TRGO
0101
TIM8_CH4
0111
TIM1_TRGO(2)
1000
TIM8_TRGO
1001
TIM8_TRGO(2)
TIM3_CH3
Internal signal from on-chip timers
1010
1011
TIM5_TRGO
1100
TIM3_CH1
1101
TIM6_TRGO
1110
Software source trigger events can be generated by setting SWSTART (for regular
conversion) or JSWSTART (for injected conversion) in ADC_CR2.
A regular group conversion can be interrupted by an injected trigger.
Note:
The trigger selection can be changed on the fly. However, when the selection changes,
there is a time frame of 1 APB clock cycle during which the trigger detection is disabled.
This is to avoid spurious detection during transitions.
15.7
Fast conversion mode
It is possible to perform faster conversion by reducing the ADC resolution. The RES bits are
used to select the number of bits available in the data register. The minimum conversion
time for each resolution is then as follows:
424/1671
•
12 bits: 3 + 12 = 15 ADCCLK cycles
•
10 bits: 3 + 10 = 13 ADCCLK cycles
•
8 bits: 3 + 8 = 11 ADCCLK cycles
•
6 bits: 3 + 6 = 9 ADCCLK cycles
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RM0385
Analog-to-digital converter (ADC)
15.8
Data management
15.8.1
Using the DMA
Since converted regular channel values are stored into a unique data register, it is useful to
use DMA for conversion of more than one regular channel. This avoids the loss of the data
already stored in the ADC_DR register.
When the DMA mode is enabled (DMA bit set to 1 in the ADC_CR2 register), after each
conversion of a regular channel, a DMA request is generated. This allows the transfer of the
converted data from the ADC_DR register to the destination location selected by the
software.
Despite this, if data are lost (overrun), the OVR bit in the ADC_SR register is set and an
interrupt is generated (if the OVRIE enable bit is set). DMA transfers are then disabled and
DMA requests are no longer accepted. In this case, if a DMA request is made, the regular
conversion in progress is aborted and further regular triggers are ignored. It is then
necessary to clear the OVR flag and the DMAEN bit in the used DMA stream, and to reinitialize both the DMA and the ADC to have the wanted converted channel data transferred
to the right memory location. Only then can the conversion be resumed and the data
transfer, enabled again. Injected channel conversions are not impacted by overrun errors.
When OVR = 1 in DMA mode, the DMA requests are blocked after the last valid data have
been transferred, which means that all the data transferred to the RAM can be considered
as valid.
At the end of the last DMA transfer (number of transfers configured in the DMA controller’s
DMA_SxNTR register):
•
No new DMA request is issued to the DMA controller if the DDS bit is cleared to 0 in the
ADC_CR2 register (this avoids generating an overrun error). However the DMA bit is
not cleared by hardware. It must be written to 0, then to 1 to start a new transfer.
•
Requests can continue to be generated if the DDS bit is set to 1. This allows
configuring the DMA in double-buffer circular mode.
To recover the ADC from OVR state when the DMA is used, follow the steps below:
15.8.2
1.
Reinitialize the DMA (adjust destination address and NDTR counter)
2.
Clear the ADC OVR bit in ADC_SR register
3.
Trigger the ADC to start the conversion.
Managing a sequence of conversions without using the DMA
If the conversions are slow enough, the conversion sequence can be handled by the
software. In this case the EOCS bit must be set in the ADC_CR2 register for the EOC status
bit to be set at the end of each conversion, and not only at the end of the sequence. When
EOCS = 1, overrun detection is automatically enabled. Thus, each time a conversion is
complete, EOC is set and the ADC_DR register can be read. The overrun management is
the same as when the DMA is used.
To recover the ADC from OVR state when the EOCS is set, follow the steps below:
1.
Clear the ADC OVR bit in ADC_SR register
2.
Trigger the ADC to start the conversion.
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Analog-to-digital converter (ADC)
15.8.3
RM0385
Conversions without DMA and without overrun detection
It may be useful to let the ADC convert one or more channels without reading the data each
time (if there is an analog watchdog for instance). For that, the DMA must be disabled
(DMA = 0) and the EOC bit must be set at the end of a sequence only (EOCS = 0). In this
configuration, overrun detection is disabled.
15.9
Multi ADC mode
In devices with two ADCs or more, the Dual (with two ADCs) and Triple (with three ADCs)
ADC modes can be used (see Figure 79).
In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the
ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the
MULTI[4:0] bits in the ADC_CCR register.
Note:
In multi ADC mode, when configuring conversion trigger by an external event, the
application must set trigger by the master only and disable trigger by slaves to prevent
spurious triggers that would start unwanted slave conversions.
The four possible modes below are implemented:
•
Injected simultaneous mode
•
Regular simultaneous mode
•
Interleaved mode
•
Alternate trigger mode
It is also possible to use the previous modes combined in the following ways:
Note:
426/1671
•
Injected simultaneous mode + Regular simultaneous mode
•
Regular simultaneous mode + Alternate trigger mode
In multi ADC mode, the converted data can be read on the multi-mode data register
(ADC_CDR). The status bits can be read in the multi-mode status register (ADC_CSR).
DocID026670 Rev 6
RM0385
Analog-to-digital converter (ADC)
Figure 79. Multi ADC block diagram(1)
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1. Although external triggers are present on ADC2 and ADC3 they are not shown in this diagram.
2. In the Dual ADC mode, the ADC3 slave part is not present.
3. In Triple ADC mode, the ADC common data register (ADC_CDR) contains the ADC1, ADC2 and ADC3’s
regular converted data. All 32 register bits are used according to a selected storage order.
In Dual ADC mode, the ADC common data register (ADC_CDR) contains both the ADC1 and ADC2’s
regular converted data. All 32 register bits are used.
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•
RM0385
DMA requests in Multi ADC mode:
In Multi ADC mode the DMA may be configured to transfer converted data in three
different modes. In all cases, the DMA streams to use are those connected to the ADC:
–
DMA mode 1: On each DMA request (one data item is available), a half-word
representing an ADC-converted data item is transferred.
In Dual ADC mode, ADC1 data are transferred on the first request, ADC2 data are
transferred on the second request and so on.
In Triple ADC mode, ADC1 data are transferred on the first request, ADC2 data
are transferred on the second request and ADC3 data are transferred on the third
request; the sequence is repeated. So the DMA first transfers ADC1 data followed
by ADC2 data followed by ADC3 data and so on.
DMA mode 1 is used in regular simultaneous triple mode.
Example:
Regular simultaneous triple mode: 3 consecutive DMA requests are generated
(one for each converted data item)
1st request: ADC_CDR[31:0] = ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC2_DR[15:0]
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0]
4th request: ADC_CDR[31:0] = ADC1_DR[15:0]
–
DMA mode 2: On each DMA request (two data items are available) two halfwords representing two ADC-converted data items are transferred as a word.
In Dual ADC mode, both ADC2 and ADC1 data are transferred on the first request
(ADC2 data take the upper half-word and ADC1 data take the lower half-word) and
so on.
In Triple ADC mode, three DMA requests are generated. On the first request, both
ADC2 and ADC1 data are transferred (ADC2 data take the upper half-word and
ADC1 data take the lower half-word). On the second request, both ADC1 and
ADC3 data are transferred (ADC1 data take the upper half-word and ADC3 data
take the lower half-word).On the third request, both ADC3 and ADC2 data are
transferred (ADC3 data take the upper half-word and ADC2 data take the lower
half-word) and so on.
DMA mode 2 is used in interleaved mode and in regular simultaneous mode (for
Dual ADC mode only).
Example:
a)
Interleaved dual mode: a DMA request is generated each time 2 data items are
available:
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
b)
Interleaved triple mode: a DMA request is generated each time 2 data items are
available
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]
4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
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RM0385
Analog-to-digital converter (ADC)
–
DMA mode 3: This mode is similar to the DMA mode 2. The only differences are
that the on each DMA request (two data items are available) two bytes
representing two ADC converted data items are transferred as a half-word. The
data transfer order is similar to that of the DMA mode 2.
DMA mode 3 is used in interleaved mode in 6-bit and 8-bit resolutions.
Example:
a)
Interleaved dual mode: a DMA request is generated each time 2 data items are
available
1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
b)
Interleaved triple mode: a DMA request is generated each time 2 data items are
available
1st request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
2nd request: ADC_CDR[15:0] = ADC1_DR[7:0] | ADC3_DR[15:0]
3rd request: ADC_CDR[15:0] = ADC3_DR[7:0] | ADC2_DR[7:0]
4th request: ADC_CDR[15:0] = ADC2_DR[7:0] | ADC1_DR[7:0]
Overrun detection: If an overrun is detected on one of the concerned ADCs (ADC1 and
ADC2 in dual and triple modes, ADC3 in triple mode only), the DMA requests are no longer
issued to ensure that all the data transferred to the RAM are valid. It may happen that the
EOC bit corresponding to one ADC remains set because the data register of this ADC
contains valid data.
15.9.1
Injected simultaneous mode
This mode converts an injected group of channels. The external trigger source comes from
the injected group multiplexer of ADC1 (selected by the JEXTSEL[3:0] bits in the ADC1_CR2
register). A simultaneous trigger is provided to ADC2 and ADC3.
Note:
Do not convert the same channel on the two/three ADCs (no overlapping sampling times for
the two/three ADCs when converting the same channel).
In simultaneous mode, one must convert sequences with the same length or ensure that the
interval between triggers is longer than the longer of the 2 sequences (Dual ADC mode) /3
sequences (Triple ADC mode). Otherwise, the ADC with the shortest sequence may restart
while the ADC with the longest sequence is completing the previous conversions.
Regular conversions can be performed on one or all ADCs. In that case, they are
independent of each other and are interrupted when an injected event occurs. They are
resumed at the end of the injected conversion group.
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Analog-to-digital converter (ADC)
RM0385
Dual ADC mode
At the end of conversion event on ADC1 or ADC2:
•
The converted data are stored into the ADC_JDRx registers of each ADC interface.
•
A JEOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2’s injected channels have all been converted.
Figure 80. Injected simultaneous mode on 4 channels: dual ADC mode
!$#
!$#
#(
#(
#(
#(
#(
#(
#(
#( #(
#(
%NDOFCONVERSIONON!$#AND!$#
4RIGGER
3AMPLING
#ONVERSION
AI
Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
•
The converted data are stored into the ADC_JDRx registers of each ADC interface.
•
A JEOC interrupt is generated (if enabled on one of the three ADC interfaces) when the
ADC1/ADC2/ADC3’s injected channels have all been converted.
Figure 81. Injected simultaneous mode on 4 channels: triple ADC mode
!$#
#(
#(
#(
#(
!$#
#(
#(
#(
!$#
#(
#(
#(
#( #( #(
#(
#(
%NDOFCONVERSIONON!$#!$#AND!$#
4RIGGER
3AMPLING
#ONVERSION
15.9.2
AI
Regular simultaneous mode
This mode is performed on a regular group of channels. The external trigger source comes
from the regular group multiplexer of ADC1 (selected by the EXTSEL[3:0] bits in the
ADC1_CR2 register). A simultaneous trigger is provided to ADC2 and ADC3.
Note:
Do not convert the same channel on the two/three ADCs (no overlapping sampling times for
the two/three ADCs when converting the same channel).
In regular simultaneous mode, one must convert sequences with the same length or ensure
that the interval between triggers is longer than the long conversion time of the 2 sequences
(Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the ADC with the shortest
sequence may restart while the ADC with the longest sequence is completing the previous
conversions.
Injected conversions must be disabled.
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RM0385
Analog-to-digital converter (ADC)
Dual ADC mode
At the end of conversion event on ADC1 or ADC2:
•
A 32-bit DMA transfer request is generated (if DMA[1:0] bits in the ADC_CCR register
are equal to 0b10). This request transfers the ADC2 converted data stored in the upper
half-word of the ADC_CDR 32-bit register to the SRAM and then the ADC1 converted
data stored in the lower half-word of ADC_CCR to the SRAM.
•
An EOC interrupt is generated (if enabled on one of the two ADC interfaces) when the
ADC1/ADC2’s regular channels have all been converted.
Figure 82. Regular simultaneous mode on 16 channels: dual ADC mode
!$#
!$#
#(
#(
#(
#(
#(
#(
#(
#( #(
#(
%NDOFCONVERSIONON!$#AND!$#
4RIGGER
3AMPLING
#ONVERSION
AI
Triple ADC mode
At the end of conversion event on ADC1, ADC2 or ADC3:
•
Three 32-bit DMA transfer requests are generated (if DMA[1:0] bits in the ADC_CCR
register are equal to 0b01). Three transfers then take place from the ADC_CDR 32-bit
register to SRAM: first the ADC1 converted data, then the ADC2 converted data and
finally the ADC3 converted data. The process is repeated for each new three
conversions.
•
An EOC interrupt is generated (if enabled on one of the three ADC interfaces) when the
ADC1/ADC2/ADC3’s regular channels are have all been converted.
Figure 83. Regular simultaneous mode on 16 channels: triple ADC mode
!$#
#(
#(
#(
#(
#( #( !$#
#(
#(
#(
!$#
#(
#(
#(
#(
#(
#(
%NDOFCONVERSIONON!$#!$#AND!$#
4RIGGER
3AMPLING
#ONVERSION
15.9.3
AI
Interleaved mode
This mode can be started only on a regular group (usually one channel). The external
trigger source comes from the regular channel multiplexer of ADC1.
Dual ADC mode
After an external trigger occurs:
•
ADC1 starts immediately
•
ADC2 starts after a delay of several ADC clock cycles
DocID026670 Rev 6
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Analog-to-digital converter (ADC)
RM0385
The minimum delay which separates 2 conversions in interleaved mode is configured in the
DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the
complementary ADC is still sampling its input (only one ADC can sample the input signal at
a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For
instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on both ADCs,
then 17 clock cycles will separate conversions on ADC1 and ADC2).
If the CONT bit is set on both ADC1 and ADC2, the selected regular channels of both ADCs
are continuously converted.
Note:
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
After an EOC interrupt is generated by ADC2 (if enabled through the EOCIE bit) a 32-bit
DMA transfer request is generated (if the DMA[1:0] bits in ADC_CCR are equal to 0b10).
This request first transfers the ADC2 converted data stored in the upper half-word of the
ADC_CDR 32-bit register into SRAM, then the ADC1 converted data stored in the register’s
lower half-word into SRAM.
Figure 84. Interleaved mode on 1 channel in continuous conversion mode: dual ADC
mode
%NDOFCONVERSIONON!$#
#(
!$#
!$#
#(
4RIGGER
#ONVERSION
#(
3AMPLING
#(
%NDOFCONVERSIONON!$#
!$##,+
CYCLES
AI
Triple ADC mode
After an external trigger occurs:
•
ADC1 starts immediately and
•
ADC2 starts after a delay of several ADC clock cycles
•
ADC3 starts after a delay of several ADC clock cycles referred to the ADC2 conversion
The minimum delay which separates 2 conversions in interleaved mode is configured in the
DELAY bits in the ADC_CCR register. However, an ADC cannot start a conversion if the
complementary ADC is still sampling its input (only one ADC can sample the input signal at
a given time). In this case, the delay becomes the sampling time + 2 ADC clock cycles. For
instance, if DELAY = 5 clock cycles and the sampling takes 15 clock cycles on the three
ADCs, then 17 clock cycles will separate the conversions on ADC1, ADC2 and ADC3).
If the CONT bit is set on ADC1, ADC2 and ADC3, the selected regular channels of all ADCs
are continuously converted.
Note:
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
In this mode a DMA request is generated each time 2 data items are available, (if the
DMA[1:0] bits in the ADC_CCR register are equal to 0b10). The request first transfers the
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RM0385
Analog-to-digital converter (ADC)
first converted data stored in the lower half-word of the ADC_CDR 32-bit register to SRAM,
then it transfers the second converted data stored in ADC_CDR’s upper half-word to SRAM.
The sequence is the following:
•
1st request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0]
•
2nd request: ADC_CDR[31:0] = ADC1_DR[15:0] | ADC3_DR[15:0]
•
3rd request: ADC_CDR[31:0] = ADC3_DR[15:0] | ADC2_DR[15:0]
•
4th request: ADC_CDR[31:0] = ADC2_DR[15:0] | ADC1_DR[15:0], ...
Figure 85. Interleaved mode on 1 channel in continuous conversion mode: triple ADC
mode
%NDOFCONVERSIONON!$#
$-!REQUESTEVERYCONVERSIONS
!$#
#(
!$#
!$#
#(
#(
#(
#(
#(
#(
#(
#(
3AMPLING
#ONVERSION
%NDOFCONVERSIONON!$#
4RIGGER
%NDOFCONVERSIONON!$#
!$##,+
CYCLES
15.9.4
AI
Alternate trigger mode
This mode can be started only on an injected group. The source of external trigger comes
from the injected group multiplexer of ADC1.
Note:
Regular conversions can be enabled on one or all ADCs. In this case the regular
conversions are independent of each other. A regular conversion is interrupted when the
ADC has to perform an injected conversion. It is resumed when the injected conversion is
finished.
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
The time interval between 2 trigger events must be greater than or equal to 1 ADC clock
period. The minimum time interval between 2 trigger events that start conversions on the
same ADC is the same as in the single ADC mode.
Dual ADC mode
•
When the 1st trigger occurs, all injected ADC1 channels in the group are converted
•
When the 2nd trigger occurs, all injected ADC2 channels in the group are converted
•
and so on
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group
have been converted.
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Analog-to-digital converter (ADC)
RM0385
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group
have been converted.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts by converting the injected ADC1
channels in the group.
Figure 86. Alternate trigger: injected group of each ADC
STTRIGGER
%/#*%/#
ON!$#
RDTRIGGER
NTHTRIGGER
%/#*%/#
ON!$#
!$#
!$#
NDTRIGGER
%/#*%/#
ON!$#
THTRIGGER
%/#*%/#
ON!$#
3AMPLING
NTHTRIGGER
#ONVERSION
AI
If the injected discontinuous mode is enabled for both ADC1 and ADC2:
•
When the 1st trigger occurs, the first injected ADC1 channel is converted.
•
When the 2nd trigger occurs, the first injected ADC2 channel are converted
•
and so on
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group
have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group
have been converted.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts.
Figure 87. Alternate trigger: 4 injected channels (each ADC) in discontinuous mode
STTRIGGER
RDTRIGGER
THTRIGGER
THTRIGGER
*%/#ON!$#
3AMPLING
#ONVERSION
!$#
!$#
*%/#ON!$#
NDTRIGGER
THTRIGGER
THTRIGGER
THTRIGGER
AI
Triple ADC mode
434/1671
•
When the 1st trigger occurs, all injected ADC1 channels in the group are converted.
•
When the 2nd trigger occurs, all injected ADC2 channels in the group are converted.
•
When the 3rd trigger occurs, all injected ADC3 channels in the group are converted.
•
and so on
DocID026670 Rev 6
RM0385
Analog-to-digital converter (ADC)
A JEOC interrupt, if enabled, is generated after all injected ADC1 channels in the group
have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC2 channels in the group
have been converted.
A JEOC interrupt, if enabled, is generated after all injected ADC3 channels in the group
have been converted.
If another external trigger occurs after all injected channels in the group have been
converted then the alternate trigger process restarts by converting the injected ADC1
channels in the group.
Figure 88. Alternate trigger: injected group of each ADC
STTRIGGER
%/#*%/#
ON!$#
THTRIGGER
%/#*%/#
ON!$#
!$#
NTHTRIGGER
3AMPLING
#ONVERSION
!$#
NDTRIGGER
NTHTRIGGER
RDTRIGGER
%/#*%/#
ON!$#
NTHTRIGGER
THTRIGGER
%/#*%/#
ON!$#
AI
15.9.5
Combined regular/injected simultaneous mode
It is possible to interrupt the simultaneous conversion of a regular group to start the
simultaneous conversion of an injected group.
Note:
In combined regular/injected simultaneous mode, one must convert sequences with the
same length or ensure that the interval between triggers is longer than the long conversion
time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode). Otherwise, the
ADC with the shortest sequence may restart while the ADC with the longest sequence is
completing the previous conversions.
15.9.6
Combined regular simultaneous + alternate trigger mode
It is possible to interrupt the simultaneous conversion of a regular group to start the alternate
trigger conversion of an injected group. Figure 89 shows the behavior of an alternate trigger
interrupting a simultaneous regular conversion.
The injected alternate conversion is immediately started after the injected event. If regular
conversion is already running, in order to ensure synchronization after the injected
conversion, the regular conversion of all (master/slave) ADCs is stopped and resumed
synchronously at the end of the injected conversion.
Note:
In combined regular simultaneous + alternate trigger mode, one must convert sequences
with the same length or ensure that the interval between triggers is longer than the long
conversion time of the 2 sequences (Dual ADC mode) /3 sequences (Triple ADC mode).
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Analog-to-digital converter (ADC)
RM0385
Otherwise, the ADC with the shortest sequence may restart while the ADC with the longest
sequence is completing the previous conversions.
If the conversion sequence is interrupted (for instance when DMA end of transfer occurs),
the multi-ADC sequencer must be reset by configuring it in independent mode first (bits
DUAL[4:0] = 00000) before reprogramming the interleaved mode.
Figure 89. Alternate + regular simultaneous
STTRIGGER
#(
!$#REG
#(
#(
#(
#(
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#(
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#(
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#(
!$#REG
#(
#(
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!$#INJ
SYNCHRONOTLOST
NDTRIGGER
AI
If a trigger occurs during an injected conversion that has interrupted a regular conversion, it
is ignored. Figure 90 shows the behavior in this case (2nd trigger is ignored).
Figure 90. Case of trigger occurring during injected conversion
STTRIGGER
#(
!$#REG
#(
#(
RDTRIGGER
#(
#(
#(
#(
!$#INJ
#(
!$#REG
#(
#(
#(
#(
#(
#(
#(
#(
#(
!$#INJ
NDTRIGGER
NDTRIGGER
AI
15.10
Temperature sensor
The temperature sensor can be used to measure the ambient temperature (TA) of the
device.
•
436/1671
On STM32F75xxx and STM32F74xxx devices, the temperature sensor is internally
connected to the same input channel, ADC1_IN18, as VBAT: ADC1_IN18 is used to
convert the sensor output voltage or VBAT into a digital value. Only one conversion,
temperature sensor or VBAT, must be selected at a time. When the temperature sensor
and the VBAT conversion are set simultaneously, only the VBAT conversion is
performed.
DocID026670 Rev 6
RM0385
Analog-to-digital converter (ADC)
Figure 91 shows the block diagram of the temperature sensor.
When not in use, the sensor can be put in power down mode.
The TSVREFE bit must be set to enable the conversion of both internal channels: the
ADC1_IN18 (temperature sensor) and the ADC1_IN17 (VREFINT).
Main features
•
Supported temperature range: –40 to 125 °C
•
Precision: ±1.5 °C
Figure 91. Temperature sensor and VREFINT channel block diagram
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1. VSENSE is input to ADC1_IN18.
DocID026670 Rev 6
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Analog-to-digital converter (ADC)
RM0385
Reading the temperature
To use the sensor:
3.
Select ADC1_IN18 input channel.
4.
Select a sampling time greater than the minimum sampling time specified in the
datasheet.
5.
Set the TSVREFE bit in the ADC_CCR register to wake up the temperature sensor
from power down mode
6.
Start the ADC conversion by setting the SWSTART bit (or by external trigger)
7.
Read the resulting VSENSE data in the ADC data register
8.
Calculate the temperature using the following formula:
Temperature (in °C) = {(VSENSE – V25) / Avg_Slope} + 25
Where:
–
V25 = VSENSE value for 25° C
–
Avg_Slope = average slope of the temperature vs. VSENSE curve (given in mV/°C
or µV/°C)
Refer to the datasheet electrical characteristics section for the actual values of V25 and
Avg_Slope.
Note:
The sensor has a startup time after waking from power down mode before it can output
VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize
the delay, the ADON and TSVREFE bits should be set at the same time.
The temperature sensor output voltage changes linearly with temperature. The offset of this
linear function depends on each chip due to process variation (up to 45 °C from one chip to
another).
The internal temperature sensor is more suited for applications that detect temperature
variations instead of absolute temperatures. If accurate temperature reading is required, an
external temperature sensor should be used.
15.11
Battery charge monitoring
The VBATE bit in the ADC_CCR register is used to switch to the battery voltage. As the
VBAT voltage could be higher than VDDA, to ensure the correct operation of the ADC, the
VBAT pin is internally connected to a bridge divider.
When the VBATE is set, the bridge is automatically enabled to connect:
•
Note:
438/1671
VBAT/4 to the ADC1_IN18 input channel
The VBAT and temperature sensor are connected to the same ADC internal channel
(ADC1_IN18). Only one conversion, either temperature sensor or VBAT, must be selected
at a time. When both conversion are enabled simultaneously, only the VBAT conversion is
performed.
DocID026670 Rev 6
RM0385
15.12
Analog-to-digital converter (ADC)
ADC interrupts
An interrupt can be produced on the end of conversion for regular and injected groups,
when the analog watchdog status bit is set and when the overrun status bit is set. Separate
interrupt enable bits are available for flexibility.
Two other flags are present in the ADC_SR register, but there is no interrupt associated with
them:
•
JSTRT (Start of conversion for channels of an injected group)
•
STRT (Start of conversion for channels of a regular group)
Table 96. ADC interrupts
Interrupt event
Event flag
Enable control bit
End of conversion of a regular group
EOC
EOCIE
End of conversion of an injected group
JEOC
JEOCIE
Analog watchdog status bit is set
AWD
AWDIE
Overrun
OVR
OVRIE
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15.13
RM0385
ADC registers
Refer to Section 1.1 on page 59 for a list of abbreviations used in register descriptions.
The peripheral registers must be written at word level (32 bits). Read accesses can be done
by bytes (8 bits), half-words (16 bits) or words (32 bits).
15.13.1
ADC status register (ADC_SR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
OVR
STRT
JSTRT
JEOC
EOC
AWD
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
rc_w0
Bits 31:6 Reserved, must be kept at reset value.
Bit 5 OVR: Overrun
This bit is set by hardware when data are lost (either in single mode or in dual/triple mode). It
is cleared by software. Overrun detection is enabled only when DMA = 1 or EOCS = 1.
0: No overrun occurred
1: Overrun has occurred
Bit 4 STRT: Regular channel start flag
This bit is set by hardware when regular channel conversion starts. It is cleared by software.
0: No regular channel conversion started
1: Regular channel conversion has started
Bit 3 JSTRT: Injected channel start flag
This bit is set by hardware when injected group conversion starts. It is cleared by software.
0: No injected group conversion started
1: Injected group conversion has started
Bit 2 JEOC: Injected channel end of conversion
This bit is set by hardware at the end of the conversion of all injected channels in the group.
It is cleared by software.
0: Conversion is not complete
1: Conversion complete
Bit 1 EOC: Regular channel end of conversion
This bit is set by hardware at the end of the conversion of a regular group of channels. It is
cleared by software or by reading the ADC_DR register.
0: Conversion not complete (EOCS=0), or sequence of conversions not complete (EOCS=1)
1: Conversion complete (EOCS=0), or sequence of conversions complete (EOCS=1)
Bit 0 AWD: Analog watchdog flag
This bit is set by hardware when the converted voltage crosses the values programmed in
the ADC_LTR and ADC_HTR registers. It is cleared by software.
0: No analog watchdog event occurred
1: Analog watchdog event occurred
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RM0385
Analog-to-digital converter (ADC)
15.13.2
ADC control register 1 (ADC_CR1)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
Res.
Res.
Res.
Res.
Res.
OVRIE
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
SCAN
rw
DISCNUM[2:0]
rw
rw
rw
25
24
RES
JDISCEN DISCEN JAUTO AWDSGL
rw
rw
rw
rw
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
6
5
4
3
2
1
0
JEOCIE
AWDIE
EOCIE
rw
rw
rw
rw
rw
rw
rw
AWDEN JAWDEN
AWDCH[4:0]
rw
Bits 31:27 Reserved, must be kept at reset value.
Bit 26 OVRIE: Overrun interrupt enable
This bit is set and cleared by software to enable/disable the Overrun interrupt.
0: Overrun interrupt disabled
1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set.
Bits 25:24 RES[1:0]: Resolution
These bits are written by software to select the resolution of the conversion.
00: 12-bit (minimum 15 ADCCLK cycles)
01: 10-bit (minimum 13 ADCCLK cycles)
10: 8-bit (minimum 11 ADCCLK cycles)
11: 6-bit (minimum 9 ADCCLK cycles)
Bit 23 AWDEN: Analog watchdog enable on regular channels
This bit is set and cleared by software.
0: Analog watchdog disabled on regular channels
1: Analog watchdog enabled on regular channels
Bit 22 JAWDEN: Analog watchdog enable on injected channels
This bit is set and cleared by software.
0: Analog watchdog disabled on injected channels
1: Analog watchdog enabled on injected channels
Bits 21:16 Reserved, must be kept at reset value.
Bits 15:13 DISCNUM[2:0]: Discontinuous mode channel count
These bits are written by software to define the number of regular channels to be converted
in discontinuous mode, after receiving an external trigger.
000: 1 channel
001: 2 channels
...
111: 8 channels
Bit 12 JDISCEN: Discontinuous mode on injected channels
This bit is set and cleared by software to enable/disable discontinuous mode on the injected
channels of a group.
0: Discontinuous mode on injected channels disabled
1: Discontinuous mode on injected channels enabled
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RM0385
Bit 11 DISCEN: Discontinuous mode on regular channels
This bit is set and cleared by software to enable/disable Discontinuous mode on regular
channels.
0: Discontinuous mode on regular channels disabled
1: Discontinuous mode on regular channels enabled
Bit 10 JAUTO: Automatic injected group conversion
This bit is set and cleared by software to enable/disable automatic injected group conversion
after regular group conversion.
0: Automatic injected group conversion disabled
1: Automatic injected group conversion enabled
Bit 9 AWDSGL: Enable the watchdog on a single channel in scan mode
This bit is set and cleared by software to enable/disable the analog watchdog on the channel
identified by the AWDCH[4:0] bits.
0: Analog watchdog enabled on all channels
1: Analog watchdog enabled on a single channel
Bit 8 SCAN: Scan mode
This bit is set and cleared by software to enable/disable the Scan mode. In Scan mode, the
inputs selected through the ADC_SQRx or ADC_JSQRx registers are converted.
0: Scan mode disabled
1: Scan mode enabled
Note: An EOC interrupt is generated if the EOCIE bit is set:
–
At the end of each regular group sequence if the EOCS bit is cleared to 0
–
At the end of each regular channel conversion if the EOCS bit is set to 1
Note: A JEOC interrupt is generated only on the end of conversion of the last channel if the
JEOCIE bit is set.
Bit 7 JEOCIE: Interrupt enable for injected channels
This bit is set and cleared by software to enable/disable the end of conversion interrupt for
injected channels.
0: JEOC interrupt disabled
1: JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set.
Bit 6 AWDIE: Analog watchdog interrupt enable
This bit is set and cleared by software to enable/disable the analog watchdog interrupt.
0: Analog watchdog interrupt disabled
1: Analog watchdog interrupt enabled
Bit 5 EOCIE: Interrupt enable for EOC
This bit is set and cleared by software to enable/disable the end of conversion interrupt.
0: EOC interrupt disabled
1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set.
Bits 4:0 AWDCH[4:0]: Analog watchdog channel select bits
These bits are set and cleared by software. They select the input channel to be guarded by
the analog watchdog.
Note: 00000: ADC analog input Channel0
00001: ADC analog input Channel1
...
01111: ADC analog input Channel15
10000: ADC analog input Channel16
10001: ADC analog input Channel17
10010: ADC analog input Channel18
Other values reserved
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15.13.3
ADC control register 2 (ADC_CR2)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
Res.
SWSTART
29
28
27
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
DDS
DMA
Res.
Res.
Res.
Res.
Res.
Res.
CONT
ADON
rw
rw
rw
rw
EXTEN
26
25
24
EXTSEL[3:0]
ALIGN EOCS
rw
rw
23
22
Res.
JSWSTART
21
20
19
JEXTEN
18
17
16
JEXTSEL[3:0]
Bit 31 Reserved, must be kept at reset value.
Bit 30 SWSTART: Start conversion of regular channels
This bit is set by software to start conversion and cleared by hardware as soon as the
conversion starts.
0: Reset state
1: Starts conversion of regular channels
Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 29:28 EXTEN: External trigger enable for regular channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of a regular group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 27:24 EXTSEL[3:0]: External event select for regular group
These bits select the external event used to trigger the start of conversion of a regular group:
0000: Timer 1 CH1
0001: Timer 1 CH2
0010: Timer 1 CH3
0011: Timer 2 CH2
0100: Timer 5 TRGO
0101: Timer 4 CH4
0110: Timer 3 CH4
0111: Timer 8 TRGO
1000: Timer 8 TRGO(2)
1001: Timer 1 TRGO
1010: Timer 1 TRGO(2)
1011: Timer 2 TRGO
1100: Timer 4 TRGO
1101: Timer 6 TRGO
1110: Reserved
1111: EXTI line11
Bit 23 Reserved, must be kept at reset value.
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RM0385
Bit 22 JSWSTART: Start conversion of injected channels
This bit is set by software and cleared by hardware as soon as the conversion starts.
0: Reset state
1: Starts conversion of injected channels
Note: This bit can be set only when ADON = 1 otherwise no conversion is launched.
Bits 21:20 JEXTEN: External trigger enable for injected channels
These bits are set and cleared by software to select the external trigger polarity and enable
the trigger of an injected group.
00: Trigger detection disabled
01: Trigger detection on the rising edge
10: Trigger detection on the falling edge
11: Trigger detection on both the rising and falling edges
Bits 19:16 JEXTSEL[3:0]: External event select for injected group
These bits select the external event used to trigger the start of conversion of an injected
group.
0000: Timer 1 TRGO
0001: Timer 1 CH4
0010: Timer 2 TRGO
0011: Timer 2 CH1
0100: Timer 3 CH4
0101: Timer4 TRGO
0110: Reserved
0111: Timer 8 CH4
1000: Timer 1 TRGO(2)
1001: Timer 8 TRGO
1010: Timer 8 TRGO(2)
1011: Timer 3 CH3
1100: Timer 5 TRGO
1101: Timer 3 CH1
1110: Timer 6 TRGO
1111: Reserved
Bits 15:12 Reserved, must be kept at reset value.
Bit 11 ALIGN: Data alignment
This bit is set and cleared by software. Refer to Figure 76 and Figure 77.
0: Right alignment
1: Left alignment
Bit 10 EOCS: End of conversion selection
This bit is set and cleared by software.
0: The EOC bit is set at the end of each sequence of regular conversions. Overrun detection
is enabled only if DMA=1.
1: The EOC bit is set at the end of each regular conversion. Overrun detection is enabled.
Bit 9 DDS: DMA disable selection (for single ADC mode)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA controller)
1: DMA requests are issued as long as data are converted and DMA=1
Bit 8 DMA: Direct memory access mode (for single ADC mode)
This bit is set and cleared by software. Refer to the DMA controller chapter for more details.
0: DMA mode disabled
1: DMA mode enabled
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Analog-to-digital converter (ADC)
Bits 7:2 Reserved, must be kept at reset value.
Bit 1 CONT: Continuous conversion
This bit is set and cleared by software. If it is set, conversion takes place continuously until it
is cleared.
0: Single conversion mode
1: Continuous conversion mode
Bit 0 ADON: A/D Converter ON / OFF
This bit is set and cleared by software.
Note: 0: Disable ADC conversion and go to power down mode
1: Enable ADC
15.13.4
ADC sample time register 1 (ADC_SMPR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
Res.
Res.
Res.
Res.
Res.
15
14
SMP15_0
13
12
rw
rw
25
24
23
SMP18[2:0]
11
SMP14[2:0]
rw
26
rw
rw
rw
10
9
8
SMP13[2:0]
rw
rw
22
21
rw
rw
rw
rw
rw
7
6
5
rw
19
18
SMP16[2:0]
SMP12[2:0]
rw
20
SMP17[2:0]
rw
rw
rw
rw
4
3
2
rw
16
SMP15[2:1]
SMP11[2:0]
rw
17
rw
rw
1
0
SMP10[2:0]
rw
rw
rw
rw
Bits 31: 27 Reserved, must be kept at reset value.
Bits 26:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sampling cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
15.13.5
ADC sample time register 2 (ADC_SMPR2)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
Res.
Res.
15
14
SMP5_0
rw
29
28
27
25
24
23
SMP8[2:0]
22
21
20
SMP7[2:0]
19
18
SMP6[2:0]
17
16
SMP5[2:1]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
SMP4[2:0]
rw
26
SMP9[2:0]
rw
SMP3[2:0]
rw
SMP2[2:0]
rw
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RM0385
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:0 SMPx[2:0]: Channel x sampling time selection
These bits are written by software to select the sampling time individually for each channel.
During sample cycles, the channel selection bits must remain unchanged.
Note: 000: 3 cycles
001: 15 cycles
010: 28 cycles
011: 56 cycles
100: 84 cycles
101: 112 cycles
110: 144 cycles
111: 480 cycles
15.13.6
ADC injected channel data offset register x (ADC_JOFRx) (x=1..4)
Address offset: 0x14-0x20
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
JOFFSETx[11:0]
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 JOFFSETx[11:0]: Data offset for injected channel x
These bits are written by software to define the offset to be subtracted from the raw
converted data when converting injected channels. The conversion result can be read from
in the ADC_JDRx registers.
15.13.7
ADC watchdog higher threshold register (ADC_HTR)
Address offset: 0x24
Reset value: 0x0000 0FFF
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
HT[11:0]
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 HT[11:0]: Analog watchdog higher threshold
These bits are written by software to define the higher threshold for the analog watchdog.
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Analog-to-digital converter (ADC)
Note:
The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
15.13.8
ADC watchdog lower threshold register (ADC_LTR)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
LT[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 LT[11:0]: Analog watchdog lower threshold
These bits are written by software to define the lower threshold for the analog watchdog.
Note:
The software can write to these registers when an ADC conversion is ongoing. The
programmed value will be effective when the next conversion is complete. Writing to this
register is performed with a write delay that can create uncertainty on the effective time at
which the new value is programmed.
15.13.9
ADC regular sequence register 1 (ADC_SQR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
SQ16_0
rw
SQ15[4:0]
rw
rw
rw
23
22
21
20
19
L[3:0]
rw
rw
rw
17
16
SQ16[4:1]
rw
rw
rw
rw
rw
rw
rw
rw
7
6
5
4
3
2
1
0
rw
rw
SQ14[4:0]
rw
18
rw
SQ13[4:0]
rw
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RM0385
Bits 31:24 Reserved, must be kept at reset value.
Bits 23:20 L[3:0]: Regular channel sequence length
These bits are written by software to define the total number of conversions in the regular
channel conversion sequence.
0000: 1 conversion
0001: 2 conversions
...
1111: 16 conversions
Bits 19:15 SQ16[4:0]: 16th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 16th in
the conversion sequence.
Bits 14:10 SQ15[4:0]: 15th conversion in regular sequence
Bits 9:5 SQ14[4:0]: 14th conversion in regular sequence
Bits 4:0 SQ13[4:0]: 13th conversion in regular sequence
15.13.10 ADC regular sequence register 2 (ADC_SQR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
Res.
Res.
15
14
29
28
rw
rw
13
12
26
25
24
23
rw
rw
rw
rw
rw
11
10
9
8
7
SQ12[4:0]
SQ10_0
rw
27
rw
rw
21
20
19
18
rw
rw
rw
rw
rw
rw
rw
6
5
4
3
2
1
0
rw
rw
SQ11[4:0]
SQ9[4:0]
rw
22
rw
rw
rw
rw
16
SQ10[4:1]
SQ8[4:0]
rw
17
SQ7[4:0]
rw
rw
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:26 SQ12[4:0]: 12th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 12th in
the sequence to be converted.
Bits 24:20 SQ11[4:0]: 11th conversion in regular sequence
Bits 19:15 SQ10[4:0]: 10th conversion in regular sequence
Bits 14:10 SQ9[4:0]: 9th conversion in regular sequence
Bits 9:5 SQ8[4:0]: 8th conversion in regular sequence
Bits 4:0 SQ7[4:0]: 7th conversion in regular sequence
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Analog-to-digital converter (ADC)
15.13.11 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
Res.
Res.
29
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
27
26
25
24
23
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
SQ6[4:0]
SQ4_0
rw
28
SQ3[4:0]
rw
22
21
20
19
SQ5[4:0]
17
16
SQ4[4:1]
SQ2[4:0]
rw
18
SQ1[4:0]
rw
Bits 31:30 Reserved, must be kept at reset value.
Bits 29:25 SQ6[4:0]: 6th conversion in regular sequence
These bits are written by software with the channel number (0..18) assigned as the 6th in the
sequence to be converted.
Bits 24:20 SQ5[4:0]: 5th conversion in regular sequence
Bits 19:15 SQ4[4:0]: 4th conversion in regular sequence
Bits 14:10 SQ3[4:0]: 3rd conversion in regular sequence
Bits 9:5 SQ2[4:0]: 2nd conversion in regular sequence
Bits 4:0 SQ1[4:0]: 1st conversion in regular sequence
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15.13.12 ADC injected sequence register (ADC_JSQR)
Address offset: 0x38
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
JSQ4[0]
JSQ3[4:0]
rw
rw
21
20
19
JL[1:0]
17
16
JSQ4[4:1]
JSQ2[4:0]
rw
18
JSQ1[4:0]
rw
Bits 31:22 Reserved, must be kept at reset value.
Bits 21:20 JL[1:0]: Injected sequence length
These bits are written by software to define the total number of conversions in the injected
channel conversion sequence.
00: 1 conversion
01: 2 conversions
10: 3 conversions
11: 4 conversions
Bits 19:15 JSQ4[4:0]: 4th conversion in injected sequence (when JL[1:0]=3, see note below)
These bits are written by software with the channel number (0..18) assigned as the 4th in the
sequence to be converted.
Bits 14:10 JSQ3[4:0]: 3rd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 9:5 JSQ2[4:0]: 2nd conversion in injected sequence (when JL[1:0]=3, see note below)
Bits 4:0 JSQ1[4:0]: 1st conversion in injected sequence (when JL[1:0]=3, see note below)
Note:
When JL[1:0]=3 (4 injected conversions in the sequencer), the ADC converts the channels
in the following order: JSQ1[4:0], JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=2 (3 injected conversions in the sequencer), the ADC converts the channels in the
following order: JSQ2[4:0], JSQ3[4:0], and JSQ4[4:0].
When JL=1 (2 injected conversions in the sequencer), the ADC converts the channels in
starting from JSQ3[4:0], and then JSQ4[4:0].
When JL=0 (1 injected conversion in the sequencer), the ADC converts only JSQ4[4:0]
channel.
15.13.13 ADC injected data register x (ADC_JDRx) (x= 1..4)
Address offset: 0x3C - 0x48
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
JDATA[15:0]
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Analog-to-digital converter (ADC)
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 JDATA[15:0]: Injected data
These bits are read-only. They contain the conversion result from injected channel x. The
data are left -or right-aligned as shown in Figure 76 and Figure 77.
15.13.14 ADC regular data register (ADC_DR)
Address offset: 0x4C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
DATA[15:0]
r
r
r
r
r
r
r
r
r
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 DATA[15:0]: Regular data
These bits are read-only. They contain the conversion result from the regular
channels. The data are left- or right-aligned as shown in Figure 76 and
Figure 77.
15.13.15 ADC Common status register (ADC_CSR)
Address offset: 0x00 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
This register provides an image of the status bits of the different ADCs. Nevertheless it is
read-only and does not allow to clear the different status bits. Instead each status bit must
be cleared by writing it to 0 in the corresponding ADC_SR register.
31
Res.
30
Res.
15
14
Res.
Res.
29
Res.
13
28
Res.
12
OVR2 STRT2
27
26
Res.
11
Res.
10
JSTRT
JEOC2
2
25
Res.
24
Res.
9
8
EOC2
AWD2
r
r
23
Res.
22
Res.
7
6
Res.
Res.
21
OVR3
20
19
r
r
17
16
EOC3
AWD3
ADC3
r
r
r
r
r
r
5
4
3
2
1
0
EOC1
AWD1
r
r
OVR1
STRT1 JSTRT1 JEOC 1
ADC2
r
18
STRT3 JSTRT3 JEOC 3
ADC1
r
r
r
r
r
Bits 31:22 Reserved, must be kept at reset value.
Bit 21 OVR3: Overrun flag of ADC3
This bit is a copy of the OVR bit in the ADC3_SR register.
Bit 20 STRT3: Regular channel Start flag of ADC3
This bit is a copy of the STRT bit in the ADC3_SR register.
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RM0385
Bit 19 JSTRT3: Injected channel Start flag of ADC3
This bit is a copy of the JSTRT bit in the ADC3_SR register.
Bit 18 JEOC3: Injected channel end of conversion of ADC3
This bit is a copy of the JEOC bit in the ADC3_SR register.
Bit 17 EOC3: End of conversion of ADC3
This bit is a copy of the EOC bit in the ADC3_SR register.
Bit 16 AWD3: Analog watchdog flag of ADC3
This bit is a copy of the AWD bit in the ADC3_SR register.
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 OVR2: Overrun flag of ADC2
This bit is a copy of the OVR bit in the ADC2_SR register.
Bit 12 STRT2: Regular channel Start flag of ADC2
This bit is a copy of the STRT bit in the ADC2_SR register.
Bit 11 JSTRT2: Injected channel Start flag of ADC2
This bit is a copy of the JSTRT bit in the ADC2_SR register.
Bit 10 JEOC2: Injected channel end of conversion of ADC2
This bit is a copy of the JEOC bit in the ADC2_SR register.
Bit 9 EOC2: End of conversion of ADC2
This bit is a copy of the EOC bit in the ADC2_SR register.
Bit 8 AWD2: Analog watchdog flag of ADC2
This bit is a copy of the AWD bit in the ADC2_SR register.
Bits 7:6 Reserved, must be kept at reset value.
Bit 5 OVR1: Overrun flag of ADC1
This bit is a copy of the OVR bit in the ADC1_SR register.
Bit 4 STRT1: Regular channel Start flag of ADC1
This bit is a copy of the STRT bit in the ADC1_SR register.
Bit 3 JSTRT1: Injected channel Start flag of ADC1
This bit is a copy of the JSTRT bit in the ADC1_SR register.
Bit 2 JEOC1: Injected channel end of conversion of ADC1
This bit is a copy of the JEOC bit in the ADC1_SR register.
Bit 1 EOC1: End of conversion of ADC1
This bit is a copy of the EOC bit in the ADC1_SR register.
Bit 0 AWD1: Analog watchdog flag of ADC1
This bit is a copy of the AWD bit in the ADC1_SR register.
15.13.16 ADC common control register (ADC_CCR)
Address offset: 0x04 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
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Analog-to-digital converter (ADC)
31
30
29
28
27
26
25
24
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
DMA[1:0]
rw
rw
13
12
DDS
Res.
rw
11
10
9
8
DELAY[3:0]
rw
rw
rw
23
22
TSVREFE VBATE
21
20
19
18
Res.
Res.
Res.
Res.
rw
rw
7
6
5
Res.
Res.
Res.
rw
4
3
2
17
16
ADCPRE
rw
rw
1
0
rw
rw
MULTI[4:0]
rw
rw
rw
Bits 31:24 Reserved, must be kept at reset value.
Bit 23 TSVREFE: Temperature sensor and VREFINT enable
This bit is set and cleared by software to enable/disable the temperature sensor and the
VREFINT channel.
0: Temperature sensor and VREFINT channel disabled
1: Temperature sensor and VREFINT channel enabled
Note: VBATE must be disabled when TSVREFE is set. If both bits are set, only the VBAT
conversion is performed.
Bit 22 VBATE: VBAT enable
This bit is set and cleared by software to enable/disable the VBAT channel.
0: VBAT channel disabled
1: VBAT channel enabled
Bits 21:18 Reserved, must be kept at reset value.
Bits 17:16 ADCPRE: ADC prescaler
Set and cleared by software to select the frequency of the clock to the ADC. The clock is
common for all the ADCs.
Note: 00: PCLK2 divided by 2
01: PCLK2 divided by 4
10: PCLK2 divided by 6
11: PCLK2 divided by 8
Bits 15:14 DMA: Direct memory access mode for multi ADC mode
This bit-field is set and cleared by software. Refer to the DMA controller section for more
details.
00: DMA mode disabled
01: DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)
10: DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)
11: DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2)
Bit 13 DDS: DMA disable selection (for multi-ADC mode)
This bit is set and cleared by software.
0: No new DMA request is issued after the last transfer (as configured in the DMA
controller). DMA bits are not cleared by hardware, however they must have been cleared
and set to the wanted mode by software before new DMA requests can be generated.
1: DMA requests are issued as long as data are converted and DMA = 01, 10 or 11.
Bit 12 Reserved, must be kept at reset value.
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RM0385
Bit 11:8 DELAY: Delay between 2 sampling phases
Set and cleared by software. These bits are used in dual or triple interleaved modes.
0000: 5 * TADCCLK
0001: 6 * TADCCLK
0010: 7 * TADCCLK
...
1111: 20 * TADCCLK
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 MULTI[4:0]: Multi ADC mode selection
These bits are written by software to select the operating mode.
– All the ADCs independent:
00000: Independent mode
– 00001 to 01001: Dual mode, ADC1 and ADC2 working together, ADC3 is independent
00001: Combined regular simultaneous + injected simultaneous mode
00010: Combined regular simultaneous + alternate trigger mode
00011: Reserved
00101: Injected simultaneous mode only
00110: Regular simultaneous mode only
00111: interleaved mode only
01001: Alternate trigger mode only
– 10001 to 11001: Triple mode: ADC1, 2 and 3 working together
10001: Combined regular simultaneous + injected simultaneous mode
10010: Combined regular simultaneous + alternate trigger mode
10011: Reserved
10101: Injected simultaneous mode only
10110: Regular simultaneous mode only
10111: interleaved mode only
11001: Alternate trigger mode only
All other combinations are reserved and must not be programmed
Note: In multi mode, a change of channel configuration generates an abort that can cause a
loss of synchronization. It is recommended to disable the multi ADC mode before any
configuration change.
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Analog-to-digital converter (ADC)
15.13.17 ADC common regular data register for dual and triple modes
(ADC_CDR)
Address offset: 0x08 (this offset address is relative to ADC1 base address + 0x300)
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DATA2[15:0]
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
DATA1[15:0]
r
Bits 31:16 DATA2[15:0]: 2nd data item of a pair of regular conversions
– In dual mode, these bits contain the regular data of ADC2. Refer to Dual ADC mode.
– In triple mode, these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.
Refer to Triple ADC mode.
Bits 15:0 DATA1[15:0]: 1st data item of a pair of regular conversions
– In dual mode, these bits contain the regular data of ADC1. Refer to Dual ADC mode
– In triple mode, these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
Refer to Triple ADC mode.
15.13.18 ADC register map
The following table summarizes the ADC registers.
Table 97. ADC global register map
Offset
Register
0x000 - 0x04C
ADC1
0x050 - 0x0FC
Reserved
0x100 - 0x14C
ADC2
0x118 - 0x1FC
Reserved
0x200 - 0x24C
ADC3
0x250 - 0x2FC
Reserved
0x300 - 0x308
Common registers
DocID026670 Rev 6
AWDIE
EOCIE
0
0
0
0
0
0
0
0
STRT
JSTRT
JEOC
EOC
AWD
Res.
JEOCIE
0
SCAN
0
AWD SGL
0
JAUTO
Res.
Res.
Res.
Res.
Res.
0
Res.
0
DISCEN
0
DISC
NUM [2:0]
0
JDISCEN
0
JAWDEN
RES[1:0]
Res.
Res.
OVRIE
0
AWDEN
Reset value
Res.
ADC_CR1
Res.
0x04
Res.
Reset value
OVR
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_SR
Res.
0x00
Register
Res.
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 98. ADC register map and reset values for each ADC
0
0
0
0
0
AWDCH[4:0]
0
0
0
0
0
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RM0385
0
0
0
0
0
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC_JOFR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
DDS
0
0
0
0
0
0
0
0
JOFFSET2[11:0]
0
0
0
0
0
0
0
JOFFSET3[11:0]
0
0
0
0
0
0
0
JOFFSET4[11:0]
0
0
0
0
0
0
HT[11:0]
1
1
1
1
1
1
LT[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
JDATA[15:0]
0
0
0
0
0
0
0
0
0
Regular DATA[15:0]
0
DocID026670 Rev 6
0
JDATA[15:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Reset value
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JOFFSET1[11:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x4C
0
JDATA[15:0]
0
Res.
Reset value
ADC_DR
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x48
0
0
Res.
Reset value
ADC_JDR4
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_JDR3
0
0
Res.
Reset value
0x44
0
0
Res.
0x40
0
0
Injected channel sequence JSQx_x bits
Reset value
ADC_JDR2
0
JL[1:0]
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
ADC_JDR1
0
Res.
0
Reset value
0x3C
0
0
Regular channel sequence SQx_x bits
Res.
Res.
0x38
Res.
Reset value
ADC_JSQR
0
Res.
ADC_SQR3
0
0
Regular channel sequence SQx_x bits
0
Res.
Reset value
0x34
0
0
Regular channel sequence SQx_x bits
Res.
0x30
L[3:0]
0
Res.
Reset value
ADC_SQR2
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_SQR1
0
0
Res.
Reset value
0x2C
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x28
0
1
Res.
Reset value
ADC_LTR
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_HTR
0
0
Res.
Reset value
0x24
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0x20
0
0
Res.
Reset value
ADC_JOFR4
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_JOFR3
0
0
Res.
Reset value
0x1C
0
0
Res.
Reset value
0x18
0
Sample time bits SMPx_x
Reset value
ADC_JOFR2
0
DMA
Res.
Res.
Res.
0
Sample time bits SMPx_x
ADC_SMPR2
0x14
0
Res.
JEXTEN[1:0]
JSWSTART
Res.
0
ADON
0
CONT
0
EOCS
0
ADC_SMPR1
Res.
0x10
0
JEXTSEL
[3:0]
Res.
0x0C
0
EXTSEL [3:0]
ALIGN
Reset value
EXTEN[1:0]
ADC_CR2
0x08
Res.
Register
SWSTART
Offset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Table 98. ADC register map and reset values for each ADC (continued)
0
0
0
0
0
0
0
0
0
0
RM0385
Analog-to-digital converter (ADC)
0x08
ADC_CDR
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
DDS
DMA[1:0]
0
JEOC
EOC
AWD
STRT
0
0
0
0
0
ADC1
DELAY [3:0]
Regular DATA2[15:0]
0
0
JSTRT
0
Res.
0
OVR
0
Res.
0
ADC2
ADCPRE[1:0]
Res.
Res.
0
Res.
0
Res.
VBATE
Reset value
TSVREFE
Res.
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CCR
Res.
0x04
EOC
0
AWD
0
JEOC
STRT
0
ADC3
JSTRT
0
Res.
0
OVR
0
Res.
EOC
AWD
0
JEOC
STRT
0
JSTRT
Res.
Reset value
OVR
Res.
Res.
Res.
Res.
Res.
Res.
ADC_CSR
Res.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x00
Register
Res.
Offset
Res.
Table 99. ADC register map and reset values (common ADC registers)
0
MULTI [4:0]
0
0
0
0
0
0
0
0
0
0
Regular DATA1[15:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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Digital-to-analog converter (DAC)
RM0385
16
Digital-to-analog converter (DAC)
16.1
DAC introduction
The DAC module is a 12-bit, voltage output digital-to-analog converter. The DAC can be
configured in 8- or 12-bit mode and may be used in conjunction with the DMA controller. In
12-bit mode, the data could be left- or right-aligned. The DAC has two output channels, each
with its own converter. In dual DAC channel mode, conversions could be done
independently or simultaneously when both channels are grouped together for synchronous
update operations. An input reference pin, VREF+ (shared with ADC) is available for better
resolution.
16.2
DAC main features
•
Two DAC converters: one output channel each
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channel for independent or simultaneous conversions
•
DMA capability for each channel
•
DMA underrun error detection
•
External triggers for conversion
•
Input voltage reference, VREF+
Figure 92 shows the block diagram of a DAC channel and Table 100 gives the pin
description.
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Digital-to-analog converter (DAC)
Figure 92. DAC channel block diagram
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Table 100. DAC pins
Name
Signal type
Remarks
VREF+
Input, analog reference
positive
The higher/positive reference voltage for the DAC,
1.8 V ≤ VREF+ ≤ VDDA
VDDA
Input, analog supply
Analog power supply
VSSA
Input, analog supply ground
Ground for analog power supply
DAC_OUTx
Analog output signal
DAC channelx analog output
Note:
Once the DAC channelx is enabled, the corresponding GPIO pin (PA4 or PA5) is
automatically connected to the analog converter output (DAC_OUTx). In order to avoid
parasitic consumption, the PA4 or PA5 pin should first be configured to analog (AIN).
16.3
DAC functional description
16.3.1
DAC channel enable
Each DAC channel can be powered on by setting its corresponding ENx bit in the DAC_CR
register. The DAC channel is then enabled after a startup time tWAKEUP.
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Digital-to-analog converter (DAC)
RM0385
Note:
The ENx bit enables the analog DAC Channelx macrocell only. The DAC Channelx digital
interface is enabled even if the ENx bit is reset.
16.3.2
DAC output buffer enable
The DAC integrates two output buffers that can be used to reduce the output impedance,
and to drive external loads directly without having to add an external operational amplifier.
Each DAC channel output buffer can be enabled and disabled using the corresponding
BOFFx bit in the DAC_CR register.
Figure 93. DAC output buffer connection
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16.3.3
DAC data format
Depending on the selected configuration mode, the data have to be written into the specified
register as described below:
•
Single DAC channelx, there are three possibilities:
–
8-bit right alignment: the software has to load data into the DAC_DHR8Rx [7:0]
bits (stored into the DHRx[11:4] bits)
–
12-bit left alignment: the software has to load data into the DAC_DHR12Lx [15:4]
bits (stored into the DHRx[11:0] bits)
–
12-bit right alignment: the software has to load data into the DAC_DHR12Rx [11:0]
bits (stored into the DHRx[11:0] bits)
Depending on the loaded DAC_DHRyyyx register, the data written by the user is shifted and
stored into the corresponding DHRx (data holding registerx, which are internal non-memorymapped registers). The DHRx register is then loaded into the DORx register either
automatically, by software trigger or by an external event trigger.
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Digital-to-analog converter (DAC)
Figure 94. Data registers in single DAC channel mode
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•
Dual DAC channels, there are three possibilities:
–
8-bit right alignment: data for DAC channel1 to be loaded into the DAC_DHR8RD
[7:0] bits (stored into the DHR1[11:4] bits) and data for DAC channel2 to be loaded
into the DAC_DHR8RD [15:8] bits (stored into the DHR2[11:4] bits)
–
12-bit left alignment: data for DAC channel1 to be loaded into the DAC_DHR12LD
[15:4] bits (stored into the DHR1[11:0] bits) and data for DAC channel2 to be
loaded into the DAC_DHR12LD [31:20] bits (stored into the DHR2[11:0] bits)
–
12-bit right alignment: data for DAC channel1 to be loaded into the
DAC_DHR12RD [11:0] bits (stored into the DHR1[11:0] bits) and data for DAC
channel2 to be loaded into the DAC_DHR12LD [27:16] bits (stored into the
DHR2[11:0] bits)
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memorymapped registers). The DHR1 and DHR2 registers are then loaded into the DOR1 and
DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.
Figure 95. Data registers in dual DAC channel mode
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DLE
16.3.4
DAC conversion
The DAC_DORx cannot be written directly and any data transfer to the DAC channelx must
be performed by loading the DAC_DHRx register (write to DAC_DHR8Rx, DAC_DHR12Lx,
DAC_DHR12Rx, DAC_DHR8RD, DAC_DHR12LD or DAC_DHR12RD).
Data stored in the DAC_DHRx register are automatically transferred to the DAC_DORx
register after one APB1 clock cycle, if no hardware trigger is selected (TENx bit in DAC_CR
register is reset). However, when a hardware trigger is selected (TENx bit in DAC_CR
register is set) and a trigger occurs, the transfer is performed three APB1 clock cycles later.
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RM0385
When DAC_DORx is loaded with the DAC_DHRx contents, the analog output voltage
becomes available after a time tSETTLING that depends on the power supply voltage and the
analog output load.
Figure 96. Timing diagram for conversion with trigger disabled TEN = 0
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16.3.5
AIB
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and VREF+.
The analog output voltages on each DAC channel pin are determined by the following
equation:
DOR
DACoutput = V REF × -------------4096
16.3.6
DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which out of 8
possible events will trigger conversion as shown in Table 101.
Table 101. External triggers
Source
Type
TSEL[2:0]
Timer 6 TRGO event
000
Timer 8 TRGO event
001
Timer 7 TRGO event
Timer 5 TRGO event
Internal signal from on-chip
timers
010
011
Timer 2 TRGO event
100
Timer 4 TRGO event
101
EXTI line9
External pin
110
SWTRIG
Software control bit
111
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
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Digital-to-analog converter (DAC)
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note:
TSELx[2:0] bit cannot be changed when the ENx bit is set.
When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DORx register takes only one APB1 clock cycle.
16.3.7
DMA request
Each DAC channel has a DMA capability. Two DMA channels are used to service DAC
channel DMA requests.
A DAC DMA request is generated when an external trigger (but not a software trigger)
occurs while the DMAENx bit is set. The value of the DAC_DHRx register is then transferred
into the DAC_DORx register.
In dual mode, if both DMAENx bits are set, two DMA requests are generated. If only one
DMA request is needed, you should set only the corresponding DMAENx bit. In this way, the
application can manage both DAC channels in dual mode by using one DMA request and a
unique DMA channel.
DMA underrun
The DAC DMA request is not queued so that if a second external trigger arrives before the
acknowledgement for the first external trigger is received (first request), then no new
request is issued and the DMA channelx underrun flag DMAUDRx in the DAC_SR register
is set, reporting the error condition. DMA data transfers are then disabled and no further
DMA request is treated. The DAC channelx continues to convert old data.
The software should clear the DMAUDRx flag by writing “1”, clear the DMAEN bit of the
used DMA stream and re-initialize both DMA and DAC channelx to restart the transfer
correctly. The software should modify the DAC trigger conversion frequency or lighten the
DMA workload to avoid a new DMA underrun. Finally, the DAC conversion could be
resumed by enabling both DMA data transfer and conversion trigger.
For each DAC channelx, an interrupt is also generated if its corresponding DMAUDRIEx bit
in the DAC_CR register is enabled.
16.3.8
Noise generation
In order to generate a variable-amplitude pseudonoise, an LFSR (linear feedback shift
register) is available. DAC noise generation is selected by setting WAVEx[1:0] to “01”. The
preloaded value in LFSR is 0xAAA. This register is updated three APB1 clock cycles after
each trigger event, following a specific calculation algorithm.
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RM0385
Figure 97. DAC LFSR register calculation algorithm
;25
;
; ;
;
;
125
DLF
The LFSR value, that may be masked partially or totally by means of the MAMPx[3:0] bits in
the DAC_CR register, is added up to the DAC_DHRx contents without overflow and this
value is then stored into the DAC_DORx register.
If LFSR is 0x0000, a ‘1 is injected into it (antilock-up mechanism).
It is possible to reset LFSR wave generation by resetting the WAVEx[1:0] bits.
Figure 98. DAC conversion (SW trigger enabled) with LFSR wave generation
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Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
16.3.9
Triangle-wave generation
It is possible to add a small-amplitude triangular waveform on a DC or slowly varying signal.
DAC triangle-wave generation is selected by setting WAVEx[1:0] to “10”. The amplitude is
configured through the MAMPx[3:0] bits in the DAC_CR register. An internal triangle counter
is incremented three APB1 clock cycles after each trigger event. The value of this counter is
then added to the DAC_DHRx register without overflow and the sum is stored into the
DAC_DORx register. The triangle counter is incremented as long as it is less than the
maximum amplitude defined by the MAMPx[3:0] bits. Once the configured amplitude is
reached, the counter is decremented down to 0, then incremented again and so on.
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Digital-to-analog converter (DAC)
It is possible to reset triangle wave generation by resetting the WAVEx[1:0] bits.
Figure 99. DAC triangle wave generation
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CR
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CR
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Figure 100. DAC conversion (SW trigger enabled) with triangle wave generation
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Note:
The DAC trigger must be enabled for noise generation by setting the TENx bit in the
DAC_CR register.
The MAMPx[3:0] bits must be configured before enabling the DAC, otherwise they cannot
be changed.
16.4
Dual DAC channel conversion
To efficiently use the bus bandwidth in applications that require the two DAC channels at the
same time, three dual registers are implemented: DHR8RD, DHR12RD and DHR12LD. A
unique register access is then required to drive both DAC channels at the same time.
Eleven possible conversion modes are possible using the two DAC channels and these dual
registers. All the conversion modes can nevertheless be obtained using separate DHRx
registers if needed.
All modes are described in the paragraphs below.
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16.4.1
RM0385
Independent trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DHR1 register is transferred into DAC_DOR1
(three APB1 clock cycles later).
When a DAC channel2 trigger arrives, the DHR2 register is transferred into DAC_DOR2
(three APB1 clock cycles later).
16.4.2
Independent trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask
value in the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DHR12RD, DHR12LD
or DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the same mask, is added to
the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles
later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the same mask, is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). Then the LFSR2 counter is updated.
16.4.3
Independent trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR masks
values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the LFSR1 counter, with the mask configured by
MAMP1[3:0], is added to the DHR1 register and the sum is transferred into DAC_DOR1
(three APB1 clock cycles later). Then the LFSR1 counter is updated.
When a DAC channel2 trigger arrives, the LFSR2 counter, with the mask configured by
MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the LFSR2 counter is updated.
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16.4.4
Digital-to-analog converter (DAC)
Independent trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum
amplitude value in the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with the same
triangle amplitude, is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle counter is then
updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with the same
triangle amplitude, is added to the DHR2 register and the sum is transferred into
DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle counter is then
updated.
16.4.5
Independent trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure different trigger sources by setting different values in the TSEL1[2:0] and
TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a DAC channel1 trigger arrives, the DAC channel1 triangle counter, with a triangle
amplitude configured by MAMP1[3:0], is added to the DHR1 register and the sum is
transferred into DAC_DOR1 (three APB1 clock cycles later). The DAC channel1 triangle
counter is then updated.
When a DAC channel2 trigger arrives, the DAC channel2 triangle counter, with a triangle
amplitude configured by MAMP2[3:0], is added to the DHR2 register and the sum is
transferred into DAC_DOR2 (three APB1 clock cycles later). The DAC channel2 triangle
counter is then updated.
16.4.6
Simultaneous software start
To configure the DAC in this conversion mode, the following sequence is required:
•
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
In this configuration, one APB1 clock cycle later, the DHR1 and DHR2 registers are
transferred into DAC_DOR1 and DAC_DOR2, respectively.
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16.4.7
RM0385
Simultaneous trigger without wave generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Load the dual DAC channel data to the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DHR1 and DHR2 registers are transferred into DAC_DOR1 and
DAC_DOR2, respectively (after three APB1 clock cycles).
16.4.8
Simultaneous trigger with single LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and the same LFSR mask
value in the MAMPx[3:0] bits
•
Load the dual DAC channel data to the desired DHR register (DHR12RD, DHR12LD or
DHR8RD)
When a trigger arrives, the LFSR1 counter, with the same mask, is added to the DHR1
register and the sum is transferred into DAC_DOR1 (three APB1 clock cycles later). The
LFSR1 counter is then updated. At the same time, the LFSR2 counter, with the same mask,
is added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1
clock cycles later). The LFSR2 counter is then updated.
16.4.9
Simultaneous trigger with different LFSR generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “01” and set different LFSR mask
values using the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the LFSR1 counter, with the mask configured by MAMP1[3:0], is
added to the DHR1 register and the sum is transferred into DAC_DOR1 (three APB1 clock
cycles later). The LFSR1 counter is then updated.
At the same time, the LFSR2 counter, with the mask configured by MAMP2[3:0], is added to
the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock cycles
later). The LFSR2 counter is then updated.
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16.4.10
Digital-to-analog converter (DAC)
Simultaneous trigger with single triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and the same maximum
amplitude value using the MAMPx[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with the same triangle
amplitude, is added to the DHR1 register and the sum is transferred into DAC_DOR1 (three
APB1 clock cycles later). The DAC channel1 triangle counter is then updated.
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three APB1 clock
cycles later). The DAC channel2 triangle counter is then updated.
16.4.11
Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
•
Set the two DAC channel trigger enable bits TEN1 and TEN2
•
Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1[2:0] and TSEL2[2:0] bits
•
Configure the two DAC channel WAVEx[1:0] bits as “1x” and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits
•
Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD)
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three APB1 clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three APB1 clock cycles later). Then the DAC channel2 triangle counter is updated.
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16.5
RM0385
DAC registers
Refer to Section 1 on page 59 for a list of abbreviations used in register descriptions.
The peripheral registers have to be accessed by words (32 bits).
16.5.1
DAC control register (DAC_CR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
DMAU
DRIE2
DMA
EN2
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
Res.
DMAU
DRIE1
DMA
EN1
rw
rw
Res.
27
26
25
24
MAMP2[3:0]
rw
rw
22
21
WAVE2[1:0]
MAMP1[3:0]
rw
23
rw
rw
19
18
17
16
TEN2
BOFF2
EN2
rw
rw
rw
rw
3
2
1
0
TEN1
BOFF1
EN1
rw
rw
rw
TSEL2[2:0]
WAVE1[1:0]
rw
20
TSEL1[2:0]
rw
rw
rw
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DMAUDRIE2: DAC channel2 DMA underrun interrupt enable
This bit is set and cleared by software.
0: DAC channel2 DMA underrun interrupt disabled
1: DAC channel2 DMA underrun interrupt enabled
Bit 28 DMAEN2: DAC channel2 DMA enable
This bit is set and cleared by software.
0: DAC channel2 DMA mode disabled
1: DAC channel2 DMA mode enabled
Bits 27:24 MAMP2[3:0]: DAC channel2 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 23:22 WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable
These bits are set/reset by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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Digital-to-analog converter (DAC)
Bits 21:19 TSEL2[2:0]: DAC channel2 trigger selection
These bits select the external event used to trigger DAC channel2
000: Timer 6 TRGO event
001: Timer 8 TRGO event
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
Bit 18 TEN2: DAC channel2 trigger enable
This bit is set and cleared by software to enable/disable DAC channel2 trigger
0: DAC channel2 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR2 register
1: DAC channel2 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR2 register
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DOR2 register takes only one APB1 clock cycle.
Bit 17 BOFF2: DAC channel2 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel2 output buffer.
0: DAC channel2 output buffer enabled
1: DAC channel2 output buffer disabled
Bit 16 EN2: DAC channel2 enable
This bit is set and cleared by software to enable/disable DAC channel2.
0: DAC channel2 disabled
1: DAC channel2 enabled
Bits 15:14 Reserved, must be kept at reset value.
Bit 13 DMAUDRIE1: DAC channel1 DMA Underrun Interrupt enable
This bit is set and cleared by software.
0: DAC channel1 DMA Underrun Interrupt disabled
1: DAC channel1 DMA Underrun Interrupt enabled
Bit 12 DMAEN1: DAC channel1 DMA enable
This bit is set and cleared by software.
0: DAC channel1 DMA mode disabled
1: DAC channel1 DMA mode enabled
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RM0385
Bits 11:8 MAMP1[3:0]: DAC channel1 mask/amplitude selector
These bits are written by software to select mask in wave generation mode or amplitude in
triangle generation mode.
0000: Unmask bit0 of LFSR/ triangle amplitude equal to 1
0001: Unmask bits[1:0] of LFSR/ triangle amplitude equal to 3
0010: Unmask bits[2:0] of LFSR/ triangle amplitude equal to 7
0011: Unmask bits[3:0] of LFSR/ triangle amplitude equal to 15
0100: Unmask bits[4:0] of LFSR/ triangle amplitude equal to 31
0101: Unmask bits[5:0] of LFSR/ triangle amplitude equal to 63
0110: Unmask bits[6:0] of LFSR/ triangle amplitude equal to 127
0111: Unmask bits[7:0] of LFSR/ triangle amplitude equal to 255
1000: Unmask bits[8:0] of LFSR/ triangle amplitude equal to 511
1001: Unmask bits[9:0] of LFSR/ triangle amplitude equal to 1023
1010: Unmask bits[10:0] of LFSR/ triangle amplitude equal to 2047
≥ 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
Bits 7:6 WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable
These bits are set and cleared by software.
00: wave generation disabled
01: Noise wave generation enabled
1x: Triangle wave generation enabled
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bits 5:3 TSEL1[2:0]: DAC channel1 trigger selection
These bits select the external event used to trigger DAC channel1.
000: Timer 6 TRGO event
001: Timer 8 TRGO event
010: Timer 7 TRGO event
011: Timer 5 TRGO event
100: Timer 2 TRGO event
101: Timer 4 TRGO event
110: External line9
111: Software trigger
Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
Bit 2 TEN1: DAC channel1 trigger enable
This bit is set and cleared by software to enable/disable DAC channel1 trigger.
0: DAC channel1 trigger disabled and data written into the DAC_DHRx register are
transferred one APB1 clock cycle later to the DAC_DOR1 register
1: DAC channel1 trigger enabled and data from the DAC_DHRx register are transferred
three APB1 clock cycles later to the DAC_DOR1 register
Note: When software trigger is selected, the transfer from the DAC_DHRx register to the
DAC_DOR1 register takes only one APB1 clock cycle.
Bit 1 BOFF1: DAC channel1 output buffer disable
This bit is set and cleared by software to enable/disable DAC channel1 output buffer.
0: DAC channel1 output buffer enabled
1: DAC channel1 output buffer disabled
Bit 0 EN1: DAC channel1 enable
This bit is set and cleared by software to enable/disable DAC channel1.
0: DAC channel1 disabled
1: DAC channel1 enabled
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Digital-to-analog converter (DAC)
16.5.2
DAC software trigger register (DAC_SWTRIGR)
Address offset: 0x04
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG2 SWTRIG1
w
w
Bits 31:2 Reserved, must be kept at reset value.
Bit 1 SWTRIG2: DAC channel2 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2
register value has been loaded into the DAC_DOR2 register.
Bit 0 SWTRIG1: DAC channel1 software trigger
This bit is set and cleared by software to enable/disable the software trigger.
0: Software trigger disabled
1: Software trigger enabled
Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1
register value has been loaded into the DAC_DOR1 register.
16.5.3
DAC channel1 12-bit right-aligned data holding register
(DAC_DHR12R1)
Address offset: 0x08
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
Res.
Res.
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
DACC1DHR[11:0]
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
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Digital-to-analog converter (DAC)
16.5.4
RM0385
DAC channel1 12-bit left aligned data holding register
(DAC_DHR12L1)
Address offset: 0x0C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
16.5.5
DAC channel1 8-bit right aligned data holding register
(DAC_DHR8R1)
Address offset: 0x10
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DACC1DHR[7:0]
rw
rw
rw
rw
rw
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
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Digital-to-analog converter (DAC)
16.5.6
DAC channel2 12-bit right aligned data holding register
(DAC_DHR12R2)
Address offset: 0x14
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
rw
rw
15
14
13
12
Res.
Res.
Res.
Res.
DACC2DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
16.5.7
DAC channel2 12-bit left aligned data holding register
(DAC_DHR12L2)
Address offset: 0x18
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
DACC2DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
3
2
1
0
Res.
Res.
Res.
Res.
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved, must be kept at reset value.
16.5.8
DAC channel2 8-bit right-aligned data holding register
(DAC_DHR8R2)
Address offset: 0x1C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
7
6
5
4
3
2
1
0
rw
rw
rw
15
14
13
12
11
10
9
8
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DACC2DHR[7:0]
rw
rw
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RM0385
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
16.5.9
Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31
30
29
28
Res.
Res.
Res.
Res.
15
14
13
12
Res.
Res.
Res.
Res.
27
26
25
24
23
22
rw
rw
rw
rw
rw
rw
11
10
9
8
7
6
21
20
19
18
17
16
rw
rw
rw
rw
rw
rw
5
4
3
2
1
0
rw
rw
rw
rw
rw
DACC2DHR[11:0]
DACC1DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DHR[11:0]: DAC channel1 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
16.5.10
DUAL DAC 12-bit left aligned data holding register
(DAC_DHR12LD)
Address offset: 0x24
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
DACC2DHR[11:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
15
14
13
12
11
10
9
8
7
6
5
4
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
DACC1DHR[11:0]
rw
rw
19
18
17
16
Res.
Res.
Res.
Res.
3
2
1
0
Res.
Res.
Res.
Res.
Bits 31:20 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
Bits 19:16 Reserved, must be kept at reset value.
Bits 15:4 DACC1DHR[11:0]: DAC channel1 12-bit left-aligned data
These bits are written by software which specifies 12-bit data for DAC channel1.
Bits 3:0 Reserved, must be kept at reset value.
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Digital-to-analog converter (DAC)
16.5.11
DUAL DAC 8-bit right aligned data holding register
(DAC_DHR8RD)
Address offset: 0x28
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
rw
rw
rw
DACC2DHR[7:0]
rw
rw
rw
rw
DACC1DHR[7:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:8 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel2.
Bits 7:0 DACC1DHR[7:0]: DAC channel1 8-bit right-aligned data
These bits are written by software which specifies 8-bit data for DAC channel1.
16.5.12
DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
15
14
13
12
Res.
Res.
Res.
Res.
DACC1DOR[11:0]
r
r
r
r
r
r
r
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
16.5.13
DAC channel2 data output register (DAC_DOR2)
Address offset: 0x30
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
11
10
9
8
7
6
5
4
3
2
1
0
r
r
r
r
r
15
14
13
12
Res.
Res.
Res.
Res.
DACC2DOR[11:0]
r
r
r
r
r
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Digital-to-analog converter (DAC)
RM0385
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
These bits are read-only, they contain data output for DAC channel2.
16.5.14
DAC status register (DAC_SR)
Address offset: 0x34
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Res.
Res.
DMAUDR2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Res.
Res.
DMAUDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
rc_w1
Bits 31:30 Reserved, must be kept at reset value.
Bit 29 DMAUDR2: DAC channel2 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel2
1: DMA underrun error condition occurred for DAC channel2 (the currently selected trigger is
driving DAC channel2 conversion at a frequency higher than the DMA service capability rate)
Bits 28:14 Reserved, must be kept at reset value.
Bit 13 DMAUDR1: DAC channel1 DMA underrun flag
This bit is set by hardware and cleared by software (by writing it to 1).
0: No DMA underrun error condition occurred for DAC channel1
1: DMA underrun error condition occurred for DAC channel1 (the currently selected trigger is
driving DAC channel1 conversion at a frequency higher than the DMA service capability rate)
Bits 12:0 Reserved, must be kept at reset value.
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0x34
DAC_SR
Reset value
0
DocID026670 Rev 6
Reset value
Reset value
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
0
0
0
0
Res.
Res.
Res.
0
0
0
0
Res.
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
0
0
0
0
0
DACC1DHR[11:0]
Reset value
0
0
DACC1DHR[7:0]
0
Reset value
0
0
0
0
0
0
0
DACC2DHR[7:0]
0
0
0
DACC2DHR[11:0]
DACC2DHR[7:0]
0
0
0
0
0
0
0
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Res.
0
0
Res.
DACC2DHR[11:0]
0
Res.
0
0
0
Res.
0
0
0
0
0
Res.
0
Res.
0
Res.
0
Res.
0
0
0
DACC1DOR[11:0]
0
DACC2DOR[11:0]
0
0
0
0
0
0
0
0
0
Res.
0
Res.
0
0
Res.
0
Res.
Res.
Res.
0
Res.
0
Res.
Reserved
Res.
0
Res.
0
Res.
Reset value
Res.
0
Res.
0
Res.
Reset value
0
Res.
Reset value
Res.
0
Res.
0
0
Res.
Reset value
Res.
Reset value
Res.
Res.
Res.
Res.
Res.
EN2
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
BOFF1
EN1
0
0
0
0
0
0
0
0
0
0
0
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
SWTRIG1
Reset value
SWTRIG2
Res.
DMAEN1
0
TEN1
TSEL1[2:0]
WAVE1[2:0]
DMAUDRIE1
Res.
Res.
TSEL2[2:0]
MAMP1[3:0]
Res.
Res.
Res.
TEN2
BOFF2
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
WAVE2[2:0]
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAEN2
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
DMAUDRIE2
0
Res.
Res.
Res.
0
Res.
DACC2DHR[11:0]
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
DMAUDR1
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
Res.
MAMP2[3:0]
Res.
Res.
Res.
0
Res.
0
0
Res.
0
Res.
0
Res.
Res.
0
0
Res.
Res.
0
Res.
Res.
0
Res.
Res.
Res.
Res.
0
Res.
Res.
Res.
Res.
Res.
DACC2DHR[11:0]
0
Res.
Res.
Res.
Res.
DAC_
DHR8RD
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
0
Res.
Res.
Res.
Res.
0
0
Res.
Res.
Res.
Res.
Res.
0
0
Res.
DAC_
DOR2
Res.
Reset value
DAC_
DHR12LD
Reset value
0
Res.
0x30
DAC_
DOR1
Res.
0x2C
DAC_
DHR12RD
Res.
0x28
DAC_
DHR8R2
Res.
0x24
DAC_
DHR12L2
Res.
0x20
DAC_
DHR12R2
Res.
Reset value
DMAUDR2
0x1C
DAC_
DHR8R1
Res.
0x18
DAC_
DHR12L1
Res.
0x14
Res.
0x10
Res.
0x0C
DAC_
DHR12R1
Res.
0x08
DAC_
SWTRIGR
Res.
0x04
DAC_CR
Res.
0x00
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register
name
Res.
Offset
Res.
16.5.15
Res.
RM0385
Digital-to-analog converter (DAC)
DAC register map
Table 102 summarizes the DAC registers.
Table 102. DAC register map
0
0
DACC1DHR[11:0]
DACC1DHR[11:0]
0
0
0
0
0
0
0
0
Reserved
DACC1DHR[7:0]
0
Refer to Section 2.2.2 on page 65 for the register boundary addresses.
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Digital camera interface (DCMI)
RM0385
17
Digital camera interface (DCMI)
17.1
DCMI introduction
The digital camera is a synchronous parallel interface able to receive a high-speed data flow
from an external 8-, 10-, 12- or 14-bit CMOS camera module. It supports different data
formats: YCbCr4:2:2/RGB565 progressive video and compressed data (JPEG).
This interface is for use with black & white cameras, X24 and X5 cameras, and it is
assumed that all preprocessing like resizing is performed in the camera module.
17.2
17.3
DCMI main features
●
8-, 10-, 12- or 14-bit parallel interface
●
Embedded/external line and frame synchronization
●
Continuous or snapshot mode
●
Crop feature
●
Supports the following data formats:
–
8/10/12/14- bit progressive video: either monochrome or raw bayer
–
YCbCr 4:2:2 progressive video
–
RGB 565 progressive video
–
Compressed data: JPEG
DCMI pins
Table 103 shows the DCMI pins.
Table 103.DCMI pins
Name
17.4
Signal type
D[0:13]
Data inputs
HSYNC
Horizontal synchronization input
VSYNC
Vertical synchronization input
PIXCLX
Pixel clock input
DCMI clocks
The digital camera interface uses two clock domains PIXCLK and HCLK. The signals
generated with PIXCLK are sampled on the rising edge of HCLK once they are stable. An
enable signal is generated in the HCLK domain, to indicate that data coming from the
camera are stable and can be sampled. The maximum PIXCLK period must be higher than
2.5 HCLK periods.
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17.5
Digital camera interface (DCMI)
DCMI functional overview
The digital camera interface is a synchronous parallel interface that can receive high-speed
(up to 54 Mbytes/s) data flows. It consists of up to 14 data lines (D13-D0) and a pixel clock
line (PIXCLK). The pixel clock has a programmable polarity, so that data can be captured on
either the rising or the falling edge of the pixel clock.
The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a
general-purpose DMA channel. The image buffer is managed by the DMA, not by the
camera interface.
The data received from the camera can be organized in lines/frames (raw YUB/RGB/Bayer
modes) or can be a sequence of JPEG images. To enable JPEG image reception, the JPEG
bit (bit 3 of DCMI_CR register) must be set.
The data flow is synchronized either by hardware using the optional HSYNC (horizontal
synchronization) and VSYNC (vertical synchronization) signals or by synchronization codes
embedded in the data flow.
Figure 101 shows the DCMI block diagram.
Figure 101.DCMI block diagram
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DocID026670 Rev 6
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Digital camera interface (DCMI)
RM0385
Figure 102.Top-level block diagram
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17.5.1
DMA interface
The DMA interface is active when the CAPTURE bit in the DCMI_CR register is set. A DMA
request is generated each time the camera interface receives a complete 32-bit data block
in its register.
17.5.2
DCMI physical interface
The interface is composed of 11/13/15/17 inputs. Only the Slave mode is supported.
The camera interface can capture 8-bit, 10-bit, 12-bit or 14-bit data depending on the
EDM[1:0] bits in the DCMI_CR register. If less than 14 bits are used, the unused input pins
must be connected to ground.
Table 104.DCMI signals
Signal name
8 bits
10 bits
12 bits
14 bits
D[0..7]
D[0..9]
D[0..11]
D[0..13]
Signal description
Data
PIXCLK
Pixel clock
HSYNC
Horizontal synchronization / Data valid
VSYNC
Vertical synchronization
The data are synchronous with PIXCLK and change on the rising/falling edge of the pixel
clock depending on the polarity.
The HSYNC signal indicates the start/end of a line.
The VSYNC signal indicates the start/end of a frame
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Digital camera interface (DCMI)
Figure 103.DCMI signal waveforms
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1. The capture edge of DCMI_PIXCLK is the falling edge, the active state of DCMI_HSYNC and
DCMI_VSYNC is 1.
2. DCMI_HSYNC and DCMI_VSYNC can change states at the same time.
8-bit data
When EDM[1:0] in DCMI_CR are programmed to “00” the interface captures 8 LSBs at its
input (D[0:7]) and stores them as 8-bit data. The D[13:8] inputs are ignored. In this case, to
capture a 32-bit word, the camera interface takes four pixel clock cycles.
The first captured data byte is placed in the LSB position in the 32-bit word and the 4th
captured data byte is placed in the MSB position in the 32-bit word. Table 105 gives an
example of the positioning of captured data bytes in two 32-bit words.
Table 105.Positioning of captured data bytes in 32-bit words (8-bit width)
Byte address
31:24
23:16
15:8
7:0
0
Dn+3[7:0]
Dn+2[7:0]
Dn+1[7:0]
Dn[7:0]
4
Dn+7[7:0]
Dn+6[7:0]
Dn+5[7:0]
Dn+4[7:0]
10-bit data
When EDM[1:0] in DCMI_CR are programmed to “01”, the camera interface captures 10-bit
data at its input D[0..9] and stores them as the 10 least significant bits of a 16-bit word. The
remaining most significant bits in the DCMI_DR register (bits 11 to 15) are cleared to zero.
So, in this case, a 32-bit data word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 106.
Table 106.Positioning of captured data bytes in 32-bit words (10-bit width)
Byte address
31:26
25:16
15:10
9:0
0
0
Dn+1[9:0]
0
Dn[9:0]
4
0
Dn+3[9:0]
0
Dn+2[9:0]
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12-bit data
When EDM[1:0] in DCMI_CR are programmed to “10”, the camera interface captures the
12-bit data at its input D[0..11] and stores them as the 12 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 107.
Table 107.Positioning of captured data bytes in 32-bit words (12-bit width)
Byte address
31:28
27:16
15:12
11:0
0
0
Dn+1[11:0]
0
Dn[11:0]
4
0
Dn+3[11:0]
0
Dn+2[11:0]
14-bit data
When EDM[1:0] in DCMI_CR are programmed to “11”, the camera interface captures the
14-bit data at its input D[0..13] and stores them as the 14 least significant bits of a 16-bit
word. The remaining most significant bits are cleared to zero. So, in this case a 32-bit data
word is made up every two pixel clock cycles.
The first captured data are placed in the LSB position in the 32-bit word and the 2nd
captured data are placed in the MSB position in the 32-bit word as shown in Table 108.
Table 108.Positioning of captured data bytes in 32-bit words (14-bit width)
17.5.3
Byte address
31:30
29:16
15:14
13:0
0
0
Dn+1[13:0]
0
Dn[13:0]
4
0
Dn+3[13:0]
0
Dn+2[13:0]
Synchronization
The digital camera interface supports embedded or hardware (HSYNC & VSYNC)
synchronization. When embedded synchronization is used, it is up to the digital camera
module to make sure that the 0x00 and 0xFF values are used ONLY for synchronization
(not in data). Embedded synchronization codes are supported only for the 8-bit parallel data
interface width (that is, in the DCMI_CR register, the EDM[1:0] bits should be cleared to
“00”).
For compressed data, the DCMI supports only the hardware synchronization mode. In this
case, VSYNC is used as a start/end of the image, and HSYNC is used as a Data Valid
signal. Figure 104 shows the corresponding timing diagram.
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Digital camera interface (DCMI)
Figure 104.Timing diagram
"EGINNINGOF*0%'STREAM
*0%'PACKETSIZE
PROGRAMMABLE
0ADDINGDATAATTHE
ENDOFTHE*0%'STREAM
*0%'DATA
%NDOF*0%' STREAM
(39.#
639.#
*0%'PACKETDATA
0ACKETDISPATCHINGDEPENDSONTHEIMAGECONTENT
4HISRESULTSINAVARIABLEBLANKINGDURATION
AI
Hardware synchronization mode
In hardware synchronization mode, the two synchronization signals (HSYNC/VSYNC) are
used.
Depending on the camera module/mode, data may be transmitted during horizontal/vertical
synchronization periods. The HSYNC/VSYNC signals act like blanking signals since all the
data received during HSYNC/VSYNC active periods are ignored.
In order to correctly transfer images into the DMA/RAM buffer, data transfer is synchronized
with the VSYNC signal. When the hardware synchronization mode is selected, and capture
is enabled (CAPTURE bit set in DCMI_CR), data transfer is synchronized with the
deactivation of the VSYNC signal (next start of frame).
Transfer can then be continuous, with successive frames transferred by DMA to successive
buffers">