Samsung M378T5663EH3-CE6 memory module Datasheet

UDIMM DDR2 SDRAM

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 1Gb E-die

64/72-bit Non-ECC/ECC

60FBGA & 84FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 25

Rev. 1.02 October 2008

UDIMM

Table of Contents

DDR2 SDRAM

1.0 DDR2 Unbuffered DIMM Ordering Information ..........................................................................4

2.0 Features .........................................................................................................................................4

3.0 Address Configuration .................................................................................................................4

4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................5

5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................6

6.0 Pin Description ..............................................................................................................................6

7.0 Input/Output Function Description .............................................................................................7

8.0 Functional Block Diagram : .........................................................................................................8

8.1 1GB, 128Mx64 Module - M378T2863EHS ...........................................................................................8

8.2 1GB, 128Mx72 ECC Module - M391T2863EH3 ....................................................................................9

8.3 2GB, 256Mx64 Module - M378T5663EH3 .........................................................................................10

8.4 2GB, 256Mx72 ECC Module - M391T5663EH3 ..................................................................................11

8.5 512MB, 64Mx64 Module - M378T6464EHS .......................................................................................12

9.0 Absolute Maximum DC Ratings .................................................................................................13

10.0 AC & DC Operating Conditions ...............................................................................................13

10.1 Recommended DC Operating Conditions (SSTL - 1.8) ....................................................................13

10.2 Operating Temperature Condition ................................................................................................14

10.3 Input DC Logic Level ..................................................................................................................14

10.4 Input AC Logic Level ..................................................................................................................14

10.5 AC Input Test Conditions ............................................................................................................14

11.0 IDD Specification Parameters Definition ................................................................................15

12.0 Operating Current Table : .........................................................................................................16

12.1 M378T2863EHS : 1GB(128Mx8 *8) Module ....................................................................................16

12.2 M378T5663EH3 : 2GB(128Mx8 *16) Module ..................................................................................16

12.3 M391T2863EH3 : 1GB(128Mx8 *9) ECC Module ..............................................................................17

12.4 M391T5663EH3 : 2GB(128Mx8 *18) ECC Module ............................................................................17

12.5 M378T6464EHS : 512MB(64Mx16 *4) Module .................................................................................18

13.0 Input/Output Capacitance ........................................................................................................19

14.0 Electrical Characteristics & AC Timing for DDR2-800/667 ....................................................19

14.1 Refresh Parameters by Device Density .........................................................................................19

14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ..............................................19

14.3 Timing Parameters by Speed Grade .............................................................................................20

15.0 Physical Dimensions : ..............................................................................................................22

15.1 128Mbx8 based 128Mx64 Module (1 Rank) ....................................................................................22

15.2 128Mbx8 based 128M x72 Module (1 Rank) ...................................................................................23

15.3 128Mbx8 based 256Mx64/x72 Module (2 Ranks) .............................................................................24

15.4 64Mbx16 based 64Mx64 Module (1 Rank) ......................................................................................25

2 of 25

Rev. 1.02 October 2008

UDIMM

Revision History

Revision

1.0

1.01

1.02

Month

August

October

March

Year

2008 - Initial Release

2008 - Typo correction

2009 - Corrected Typo

History

DDR2 SDRAM

3 of 25

Rev. 1.02 October 2008

UDIMM

1.0 DDR2 Unbuffered DIMM Ordering Information

Part Number

M378T2863EHS-CE7/F7/E6

M378T5663EH3-CE7/F7/E6

M378T6464EHS-CE7/F7/E6

M391T2863EH3-CE7/F7/E6

M391T5663EH3-CE7/F7/E6

Density

1GB

2GB

512MB

1GB

2GB

Organization x64 Non ECC

Component Composition

128Mx64

256Mx64

64Mx64

128Mx8(K4T1G084QE)*8

128Mx8(K4T1G084QE)*16

64Mx16(K4T1G164QE)*4 x72 ECC

128Mx72

256Mx72

128Mx8(K4T1G084QE)*9

128Mx8(K4T1G084QE)*18

Note :

1. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.

2. “3” of Part number(13th digit) stands for Dummy Pad PCB products.

3. “S” of Part number(13th digit) stands for reduced layer PCB products.

2.0 Features

• Performance range

Speed@CL3

Speed@CL4

Speed@CL5

Speed@CL6

E7 (DDR2-800)

400

533

800

-

F7 (DDR2-800)

-

533

667

800

E6 (DDR2-667)

400

533

667

-

CL-tRCD-tRP 5-5-5 6-6-6 5-5-5

• JEDEC standard V

DD

= 1.8V ± 0.1V Power Supply

• V

DDQ

= 1.8V ± 0.1V

• 333MHz f

CK

for 667Mb/sec/pin, 400MHz f

CK

for 800Mb/sec/pin

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5, 6

• Programmable Additive Latency: 0, 1 , 2 , 3, 4, 5

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/Nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination with selectable values(50/75/150 ohms or disable)

• Average Refresh Period 7.8us at lower than a T

CASE

85 °C, 3.9us at 85°C < T

CASE

< 95 °C

- Support High Temperature Self-Refresh rate enable feature

• Package: 60ball FBGA - 128Mx8 and 84ball FBGA - 64Mx16

• All of products are Lead-Free, Halogen-Free, and RoHS compliant

Unit

Mbps

Mbps

Mbps

Mbps

CK

DDR2 SDRAM

Number of Rank

1

2

1

1

2

Height

30mm

30mm

30mm

30mm

30mm

3.0 Address Configuration

Organization

128Mx8(1Gb) based Module

64Mx16(1Gb) based Module

Row Address

A0-A13

A0-A12

Column Address

A0-A9

A0-A9

Bank Address

BA0-BA2

BA0-BA2

Auto Precharge

A10

A10

4 of 25

Rev. 1.02 October 2008


4.0 x64 DIMM Pin Configurations (Front side/Back side)

DQ17

V

SS

DQS2

DQS2

V

SS

DQ18

NC

V

SS

DQ10

DQ11

V

SS

DQ16

DQ9

V

SS

DQS1

DQS1

V

SS

NC

Front

V

REF

V

SS

DQ0

DQ1

V

SS

DQS0

DQS0

V

SS

DQ2

DQ3

V

SS

DQ8

25

26

27

28

29

30

21

22

23

24

17

18

19

20

13

14

15

16

8

9

6

7

Pin

1

2

3

4

5

10

11

12

145

146

147

148

149

150

141

142

143

144

137

138

139

140

133

134

135

136

126

127

128

129

Pin

121

122

123

124

125

130

131

132

55

56

57

58

59

60

51

52

53

54

47

48

49

50

43

44

45

46

36

37

38

39

Pin

31

32

33

34

35

40

41

42

BA2

NC

V

DDQ

A11

A7

V

DD

A5

NC

V

SS

NC

NC

V

SS

NC

NC

V

SS

V

DDQ

CKE0

V

DD

Front

DQ19

V

SS

DQ24

DQ25

V

SS

DQS3

DQS3

V

SS

DQ26

DQ27

V

SS

NC

DQ21

V

SS

DM2

NC

V

SS

DQ22

DQ23

NC

V

SS

CK1

CK1

V

SS

DQ14

DQ15

V

SS

DQ20

Back

V

SS

DQ4

DQ5

V

SS

DM0

NC

V

SS

DQ6

DQ7

V

SS

DQ12

DQ13

V

SS

DM1

84

85

86

87

88

89

90

80

81

82

83

76

77

78

79

72

73

74

75

69

70

71

65

66

67

68

171

172

173

174

175

176

177

178

179

180

167

168

169

170

163

164

165

166

Pin

151

152

153

154

155

156

157

158

159

160

161

162

NC

V

DDQ

A12

A9

V

DD

A8

A6

NC

V

SS

NC

NC

V

SS

V

DDQ

CKE1

V

DD

NC

Back

V

SS

DQ28

DQ29

V

SS

DM3

NC

V

SS

DQ30

DQ31

V

SS

NC

NC

V

SS

NC

Pin

61

62

63

64

DQ33

V

SS

DQS4

DQS4

V

SS

DQ34

DQ35

V

SS

DQ40

DQ41

CAS

V

DDQ

S1

ODT1

V

DDQ

V

SS

DQ32

Front

V

A4

DDQ

A2

V

DD

V

SS

V

SS

V

DD

NC

V

DD

A10/AP

BA0

V

DDQ

WE

Pin

181

182

183

KEY

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

Back

V

DDQ

A3

A1

V

DD

115

116

117

118

119

120

111

112

113

114

107

108

109

110

103

104

105

106

96

97

98

99

Pin

91

92

93

94

95

100

101

102

RAS

S0

V

DDQ

ODT0

A13 1

V

DD

V

SS

DQ36

CK0

CK0

V

DD

A0

V

DD

BA1

V

DDQ

DQ37

V

SS

DM4

NC

V

SS

DQ38

DQ39

V

SS

DQ44

DQ45

V

SS

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

DQS6

DQS6

V

SS

DQ50

DQ51

V

SS

DQ56

DQ57

V

SS

DQS7

Front

V

SS

DQS5

DQS5

V

SS

DQ42

DQ43

V

SS

DQ48

DQ49

V

SS

SA2

NC, TEST

2

V

SS

DQS7

V

SS

DQ58

DQ59

V

SS

SDA

SCL

235

236

237

238

239

240

231

232

233

234

227

228

229

230

223

224

225

226

216

217

218

219

Pin

211

212

213

214

215

220

221

222

CK2

V

SS

DM6

NC

V

SS

DQ54

Back

DM5

NC

V

SS

DQ46

DQ47

V

SS

DQ52

DQ53

V

SS

CK2

DQ55

V

SS

DQ60

DQ61

V

SS

DM7

NC

V

SS

DQ62

DQ63

V

SS

V

DDSPD

SA0

SA1

5 of 25

Rev. 1.02 October 2008


5.0 x72 DIMM Pin Configurations (Front side/Back side)

20

21

22

23

24

25

16

17

18

19

26

27

28

29

30

12

13

14

15

8

9

10

11

6

7

4

5

Pin

1

2

3

140

141

142

143

144

145

136

137

138

139

146

147

148

149

150

132

133

134

135

128

129

130

131

124

125

126

127

Pin

121

122

123

NC

V

SS

DQ10

DQ11

V

SS

DQ16

DQ17

V

SS

DQS2

DQS2

V

SS

DQ18

DQ3

V

SS

DQ8

DQ9

V

SS

DQS1

DQS1

V

SS

NC

Front

V

REF

V

SS

DQ0

DQ1

V

SS

DQS0

DQS0

V

SS

DQ2

170

171

172

173

174

175

166

167

168

169

176

177

178

179

180

162

163

164

165

158

159

160

161

154

155

156

157

Pin

151

152

153

50

51

52

53

54

55

46

47

48

49

56

57

58

59

60

42

43

44

45

38

39

40

41

34

35

36

37

Pin

31

32

33

DQ27

V

SS

CB0

CB1

V

SS

DQS8

DQS8

V

SS

CB2

CB3

V

SS

V

DDQ

Front

DQ19

V

SS

DQ24

DQ25

V

SS

DQS3

DQS3

V

SS

DQ26

CKE0

V

DD

BA2

NC

V

DDQ

A11

A7

V

DD

A5

CK1

V

SS

DQ14

DQ15

V

SS

DQ20

DQ13

V

SS

DM1

NC

V

SS

CK1

DQ21

V

SS

DM2

NC

V

SS

DQ22

DQ23

NC

V

SS

DQ6

DQ7

V

SS

DQ12

Back

V

SS

DQ4

DQ5

V

SS

DM0

77

78

79

80

73

74

75

76

69

70

71

72

65

66

67

68

85

86

87

88

89

90

81

82

83

84

CB5

V

SS

DM8

NC

V

SS

CB6

CB7

V

SS

V

DDQ

NC

V

SS

DQ30

DQ31

V

SS

CB4

Back

V

SS

DQ28

DQ29

V

SS

DM3

CKE1

V

DD

NC

NC

V

DDQ

A12

A9

V

DD

A8

A6

Pin

61

62

63

64

DQ32

DQ33

V

SS

DQS4

DQS4

V

SS

DQ34

DQ35

V

SS

DQ40

DQ41

BA0

V

DDQ

WE

CAS

V

DDQ

S1

ODT1

V

DDQ

V

SS

Front

A4

V

DDQ

A2

V

DD

V

SS

V

SS

V

DD

NC

V

DD

A10/AP

KEY

184

185

186

187

188

189

190

Pin

181

182

183

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

Back

V

DDQ

A3

A1

V

DD

S0

V

DDQ

ODT0

A13

V

DD

V

SS

DQ36

DQ37

V

SS

DM4

NC

V

SS

DQ38

DQ39

V

SS

DQ44

DQ45

V

SS

CK0

CK0

V

DD

A0

V

DD

BA1

V

DDQ

RAS

113

114

115

116

117

118

119

120

109

110

111

112

105

106

107

108

Pin

91

92

93

94

95

Front

V

SS

DQS5

DQS5

V

SS

DQ42

96

97

98

99

DQ43

V

SS

DQ48

DQ49

V

SS

100

101 SA2

102 NC, TEST 2

103 V

SS

104 DQS6

DQS6

V

SS

DQ50

DQ51

V

SS

DQ56

DQ57

V

SS

DQS7

DQS7

V

SS

DQ58

DQ59

V

SS

SDA

SCL

NC = No Connect, RFU = Reserved for Future Use

1. Pin196(A13) is used for x4/x8 base Unbuffered DIMM.

2. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products (DIMMs.)

230

231

232

233

234

235

226

227

228

229

236

237

238

239

240

222

223

224

225

218

219

220

221

214

215

216

217

Pin

211

212

213

DQ55

V

SS

DQ60

DQ61

V

SS

DM7

CK2

V

SS

DM6

NC

V

SS

DQ54

NC

V

SS

DQ62

DQ63

V

SS

V

DDSPD

SA0

SA1

Back

DM5

NC

V

SS

DQ46

DQ47

V

SS

DQ52

DQ53

V

SS

CK2

6.0 Pin Description

Pin Name

A0-A13

BA0-BA2

RAS

CAS

WE

S0, S1

CKE0,CKE1

ODT0, ODT1

DQ0 - DQ63

CB0 - CB7

DQS0 - DQS8

DM(0-8)

Description

DDR2 SDRAM address bus

DDR2 SDRAM bank select

DDR2 SDRAM row address strobe

DDR2 SDRAM column address strobe

DDR2 SDRAM wirte enable

DIMM Rank Select Lines

DDR2 SDRAM clock enable lines

On-die termination control lines

DIMM memory data bus

DIMM ECC check bits

DDR2 SDRAM data strobes

DDR2 SDRAM data masks

DQS0-DQS8 DDR2 SDRAM differential data strobes

*The V

DD and V

DDQ

pins are tied to the single power-plane on PCB.

Pin Name

CK0, CK1, CK2

CK0, CK1, CK2

SCL

SDA

SA0-SA2

V

DD

*

V

DDQ

*

V

REF

V

SS

V

DDSPD

NC

RESET

TEST

Description

DDR2 SDRAM clocks (positive line of differential pair)

DDR2 SDRAM clocks (negative line of differential pair)

I

2

C serial bus clock for EEPROM

I

2

C serial bus data line for EEPROM

I

2

C serial address select for EEPROM

DDR2 SDRAM core power supply

DDR2 SDRAM I/O Driver power supply

DDR2 SDRAM I/O reference supply

Power supply return (ground)

Serial EEPROM positive power supply

Spare Pins(no connect)

Not used on UDIMM

Used by memory bus analysis tools

(unused on memory DIMMs)

6 of 25

Rev. 1.02 October 2008


7.0 Input/Output Function Description

Symbol Type

CK0-CK2

CK0-CK2

CKE0-CKE1

S0-S1

RAS, CAS, WE

ODT0-ODT1

V

REF

V

DDQ

BA0-BA2

A0-A13

Input

Input

Input

Input

Input

Supply

Supply

Input

Input

Description

CK and CK are differential clock inputs. All the SDRAM addr/cntl inputs are sampled on the crossing of positive edge of CK and negative edge of CK. Output (read) data is reference to the crossing of CK and CK

(Both directions of crossing)

Activates the SDRAM CK signal when high and deactivates the CK Signal When low. By deactivating the clocks, CKE low initiates the Powe Down mode, or the Self-Refresh mode

Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disbled, new command are ignored but previous operations continue.

This signal provides for external rank selection on systems with multiple ranks

RAS, CAS, and WE (ALONG WITH CS) define the command being entered.

When high, termination resistance is enabled for all DQ, DQ and DM pins, assuming the function is enabled in the Extended Mode Register Set (EMRS).

Reference voltage for SSTL 18 inputs.

Power supply for the DDR II SDRAM output buffers to provide improved noise immunity. For all current

DDR2 unbuffered DIMM designs, V

DDQ

shares the same power plane as V

DD

pins.

Selects which SDRAM BANK of four is activated.

During a Bank Activate command cycle, Address input defines the row address (RA0-RA13)

During a Read or Write command cycle, Address input defines the colum address, In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0-BA2 defines the bank to be precharged. If AP is low, autoprecharge is disbled. During a precharge command cycle, AP is used in conjunction with BA0-BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0-BA2.

If AP is low, BA0, BA1, BA2 are used to define which bank to precharge.

DQ0-DQ63

CB0-CB7

In/Out Data and Check Bit Input/Output pins.

DM0-DM8

V

DD

,V

SS

DQS0-DQS8

DQS0-DQS8

SA0-SA2

SDA

Input

Supply

In/Out

Input

In/Out

DM is an input mask signal for write data. Input data is masked when DM is sampled High coincident with that input data during a write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.

Power and ground for DDR2 SDRAM input buffers, and core logic. V

V

DDQ

planes on these modules.

DD

and V

DDQ

pins are tied to V

DD

/

Data strobe for input and output data. For Rawcards using x16 orginized DRAMs DQ0-7 connect to the

LDQS pin of the DRAMs and DQ8-17 connect to the UDQS pin of the DRAM

These signals and tied at the system planar to either V address range.

SS

or V

DD

to configure the serial SPD EERPOM

This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V

DD

to act as a pullup on the system board.

7 of 25

Rev. 1.02 October 2008

UDIMM

8.0 Functional Block Diagram :

8.1 1GB, 128Mx64 Module - M378T2863EHS

(Populated as 1 rank of x8 DDR2 SDRAMs)

S0

DQS0

DQS0

DM0

DQS4

DQS4

DM4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D0

DQS1

DQS1

DM1

DQS5

DQS5

DM5

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D1

DQS2

DQS2

DM2

DQS6

DQS6

DM6

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D2

DQS3

DQS3

DM3

DQS7

DQS7

DM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

NU/ CS DQS DQS

D3

DDR2 SDRAM

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D4

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D5

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D6

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D7

SCL

WP

BA0 - BA2

A0 - A13

RAS

CAS

CKE0

WE

ODT0

A0

Serial PD

SA0

A1

SA1

A2

SA2

SDA

V

DDSPD

V

DD

/V

DDQ

V

REF

V

SS

BA0-BA2 : DDR2 SDRAMs D0 - D7

A0-A13 : DDR2 SDRAMs D0 - D7

RAS : DDR2 SDRAMs D0 - D7

CAS : DDR2 SDRAMs D0 - D7

CKE : DDR2 SDRAMs D0 - D7

WE : DDR2 SDRAMs D0 - D7

ODT : DDR2 SDRAMs D0 - D7

Serial PD

D0 - D7

D0 - D7

D0 - D7

* Clock Wiring

Clock Input DDR2 SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

2 DDR2 SDRAMs

3 DDR2 SDRAMs

3 DDR2 SDRAMs

*Wire per Clock Loading

Table/Wiring Diagrams

Note :

1. DQ,DM, DQS/DQS resistors : 22 Ohms ± 5%.

2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.

8 of 25

Rev. 1.02 October 2008


8.2 1GB, 128Mx72 ECC Module - M391T2863EH3


S0

DQS0

DQS0

DM0

DQS4

DQS4

DM4

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D0

DQS1

DQS1

DM1

DQS5

DQS5

DM5

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D1

DQS2

DQS2

DM2

DQS6

DQS6

DM6

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D2

DQS3

DQS3

DM3

DQS7

DQS7

DM7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D3

DQS8

DQS8

DM8

BA0 - BA2

A0 - A13

RAS

CAS

CKE0

WE

ODT0

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D8








DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D5

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D6

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D7

V

DDSPD

V

DD

/V

DDQ

V

REF

V

SS

SCL

WP

Serial PD

SDA

A0 A1 A2

SA0 SA1 SA2

Serial PD

D0 - D8

D0 - D8

D0 - D8

* Clock Wiring


*CK0/CK0

*CK1/CK1

*CK2/CK2

3 DDR2 SDRAMs

3 DDR2 SDRAMs

3 DDR2 SDRAMs



Note :


2. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms ± 5%.

9 of 25

Rev. 1.02 October 2008


8.3 2GB, 256Mx64 Module - M378T5663EH3

(Populated as 2 ranks of x8 DDR2 SDRAMs)

S1

S0

DQS0

DQS0

DM0

DQS1

DQS1

DM1

DQS2

DQS2

DM2

DQS3

DQS3

DM3

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D0

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D8

DQS5

DQS5

DM5

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D1

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D9

DQS6

DQS6

DM6

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D2

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D10

DQS7

DQS7

DM7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D3

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D11

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D12

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D5

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D13

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D6

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D14

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D15

BA0 - BA2

A0 - A13

CKE0

CKE1

RAS

CAS

WE

ODT0

ODT1

V

DDSPD

V

DD

/V

DDQ

V

REF

V

SS

Serial PD

D0 - D15

D0 - D15

D0 - D15










Serial PD

SCL

WP SDA

A0 A1 A2

SA0 SA1 SA2

* Clock Wiring


*CK0/CK0

*CK1/CK1

*CK2/CK2

4 DDR2 SDRAMs

6 DDR2 SDRAMs

6 DDR2 SDRAMs



Note :


2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.

10 of 25

Rev. 1.02 October 2008


8.4 2GB, 256Mx72 ECC Module - M391T5663EH3

(Populated as 2 ranks of x8 DDR2 SDRAMs)

S1

S0

DQS0

DQS0

DM0

DQS1

DQS1

DM1

DQS2

DQS2

DM2

DQS3

DQS3

DM3

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS4

DQS4

DM4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D0

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D9

DQS5

DQS5

DM5

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D1

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D10

DQS6

DQS6

DM6

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D2

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D11

DQS7

DQS7

DM7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D3

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D12

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D4

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D13

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D5

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D14

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D6

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D15

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D7

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D16

DQS8

DQS8

DM8

BA0 - BA2

A0 - A13

CKE0

CKE1

RAS

CAS

WE

ODT0

ODT1

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Serial PD

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

CS DQS DQS

D8

DM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7










CS DQS DQS

D17

SCL

WP SDA

A0 A1 A2

SA0 SA1 SA2

V

DDSPD

V

DD

/V

DDQ

V

REF

V

SS

Serial PD

D0 - D17

D0 - D17

* Clock Wiring


*CK0/CK0

*CK1/CK1

*CK2/CK2

6 DDR2 SDRAMs

6 DDR2 SDRAMs

6 DDR2 SDRAMs



D0 - D17

Note :


2. BAx, Ax, RAS, CAS, WE resistors : 7.5 Ohms ± 5%.

11 of 25

Rev. 1.02 October 2008

UDIMM

8.5 512MB, 64Mx64 Module - M378T6464EHS


S0

DQS1

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS0

DQS0

DM0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS3

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS2

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

CS

LDQS

LDOS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

D0

CS

LDQS

LDOS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

D1

DQS5

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS4

DQS4

DM4

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS7

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQS6

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

CS

LDQS

LDOS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

D2

CS

LDQS

LDOS

LDM

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

UDQS

UDOS

UDM

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

D3

DDR2 SDRAM

Serial PD

SCL

WP

A0 A1 A2

SA0 SA1 SA2

SDA

V

DDSPD

V

DD

/V

DDQ

V

REF

V

SS

Serial PD

D0 - D3

D0 - D3

D0 - D3

Clock Input

*CK0/ CK0

*CK1/ CK1

*CK2/ CK2

* Clock Wiring

DDR2 SDRAMs

NC

2 DDR2 SDRAMs

2 DDR2 SDRAMs



BA0 - BA1

A0 - A12

CKE0

RAS

CAS

WE

ODT0








Notes :

1. DQ,DM, DQS/DQS resistors : 22 Ohms

±

5%.

4. BAx, Ax, RAS, CAS, WE resistors : 10 Ohms

±

5%.

12 of 25

Rev. 1.02 October 2008


9.0 Absolute Maximum DC Ratings

Symbol Parameter

V

DD

V

DDQ

Voltage on V

DD

pin relative to V

SS

Voltage on V

DDQ

pin relative to V

SS

V

DDL

T

STG

Voltage on V

DDL

pin relative to V

SS

V

IN,

V

OUT

Voltage on any pin relative to V

SS

Storage Temperature

Rating

- 1.0 V ~ 2.3 V

- 0.5 V ~ 2.3 V

- 0.5 V ~ 2.3 V

- 0.5 V ~ 2.3 V

-55 to +100

Units

V

V

V

V

Notes

1

1

1

1

Note :

1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.

10.0 AC & DC Operating Conditions

10.1 Recommended DC Operating Conditions (SSTL - 1.8)

Symbol Parameter

Min.

Rating

Typ. Max.

Units Notes

V

DD

V

DDL

V

DDQ

V

REF

V

TT

Supply Voltage

Supply Voltage for DLL

Supply Voltage for Output

Input Reference Voltage

Termination Voltage

1.7

1.7

1.7

0.49*V

V

REF

DDQ

-0.04

1.8

1.8

1.8

0.50*V

DDQ

V

REF

1.9

1.9

1.9

0.51*V

V

REF

DDQ

+0.04

V

V

V mV

V

4

4

1,2

3

Note : There is no specific device V

DD x V to V

DD

DDQ

.

1. The value of V

REF

2. Peak to peak AC noise on V

REF

supply voltage requirement for SSTL-1.8 compliance. However under all conditions V

DDQ

must be less than or equal

may be selected by the user to provide optimum noise margin in the system. Typically the value of V

REF

is expected to be about 0.5

of the transmitting device and V

REF

3. V

TT

of transmitting device must track V

REF

is expected to track variations in V

may not exceed +/-2% V

REF

of receiving device.

4. AC parameters are measured with V

DD

, V

DDQ

and V

DDL

(DC).

tied together.

DDQ

.

13 of 25

Rev. 1.02 October 2008


10.2 Operating Temperature Condition

Symbol

T

OPER

Parameter

Operating Temperature

Rating

0 to 95

Units Notes

Note :

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to

JESD51.2 standard.

2. At 85 - 95 °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3.9 us ) is required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate.

10.3 Input DC Logic Level

Symbol

V

IH

(DC)

V

IL

(DC)

Parameter

DC input logic high

DC input logic low

Min.

V

REF

+ 0.125

- 0.3

Max.

V

DDQ

+ 0.3

V

REF

- 0.125

Units

V

V

Notes

10.4 Input AC Logic Level

Symbol

V

IH

(AC)

V

IL

(AC)

Parameter

AC input logic high

AC input logic low

DDR2-667, DDR2-800

Min.

Max.

V

REF

+ 0.200

V

REF

- 0.200

Units

V

V

Notes

10.5 AC Input Test Conditions

Symbol Condition Value Units Notes

V

REF

V

SWING(MAX)

SLEW

Input reference voltage

Input signal maximum peak to peak swing

0.5 * V

1.0

DDQ

V

V

1

1

Input signal minimum slew rate 1.0

V/ns 2, 3

Notes:

1. Input waveform timing is referenced to the input signal crossing through the V

IH/IL

(AC) level applied to the device under test.

2. The input signal minimum slew rate is to be maintained over the range from V

REF to V

IH

(AC) min for rising edges and the range from V max for falling edges as shown in the below figure.

REF

to V

IL

(AC)

3. AC timings are referenced with input waveforms switching from V

IL

(AC) to V

IH

(AC) on the positive transitions and V

IH transitions.

(AC) to V

IL

(AC) on the negative

V

SWING(MAX)

V

DDQ

V

IH

(AC) min

V

IH

(DC) min

V

REF

V

IL

(DC) max

V

IL

(AC) max

V

SS delta TF delta TR

Falling Slew =

V

REF

- V

IL

(AC) max

delta TF

Rising Slew =

V

IH

(AC) min - V

delta TR

REF

< AC Input Test Signal Waveform >

14 of 25

Rev. 1.02 October 2008


11.0 IDD Specification Parameters Definition

(IDD values are for full operating range of Voltage and Temperature)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P

IDD3N

IDD4W

IDD4R

IDD5B

IDD6

IDD7

Proposed Conditions

Operating one bank active-precharge current;

tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH between valid commands;

Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W

Precharge power-down current;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

Active power-down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING

Fast PDN Exit MRS(12) = 0

Slow PDN Exit MRS(12) = 1

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCH-

ING; Data pattern is same as IDD4W

Burst auto refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING

Self refresh current;

CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are

FLOATING; Data bus inputs are FLOATING

Normal

Low Power

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tFAW = tFAW(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for detailed timing conditions

Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA

Note

15 of 25

Rev. 1.02 October 2008


12.0 Operating Current Table :

12.1 M378T2863EHS : 1GB(128Mx8 *8) Module

(T

A

=0 o C, V

DD

= 1.9V)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5

IDD6

IDD7

800@CL=5

CE7

416

464

80

184

224

208

120

296

576

720

960

80

1,360

800@CL6

CF7

416

464

80

184

224

208

120

296

576

720

960

80

1,360

667@CL=5

CE6

400

440

80

184

216

200

120

280

520

640

920

80

1,240

Units mA mA mA mA mA mA mA mA mA mA mA mA mA

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Notes

12.2 M378T5663EH3 : 2GB(128Mx8 *16) Module

(T

A

=0 o C, V

DD

= 1.9V)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5

IDD6

IDD7

800@CL=5

CE7

640

688

160

368

448

416

240

520

800

944

1,184

160

1,584

800@CL=6

CF7

640

688

160

368

448

416

240

520

800

944

1,184

160

1,584

667@CL=5

CE6

616

656

160

368

432

400

240

496

736

856

1,136

160

1,456



Notes

16 of 25

Rev. 1.02 October 2008


12.3 M391T2863EH3 : 1GB(128Mx8 *9) ECC Module

(T

A

=0 o C, V

DD

= 1.9V)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5

IDD6

IDD7

800@CL=5

CE7

468

522

90

207

252

234

135

333

648

810

1,080

90

1,530

800@CL=6

CF7

468

522

90

207

252

234

135

333

648

810

1,080

90

1,530

667@CL=5

CE6

450

495

90

207

243

225

135

315

585

720

1,035

90

1,395



Notes

12.4 M391T5663EH3 : 2GB(128Mx8 *18) ECC Module

(T

A

=0 o C, V

DD

= 1.9V)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5

IDD6

IDD7

800@CL=5

CE7

720

774

180

414

504

468

270

585

900

1,062

1,332

180

1,782

800@CL=6

CF7

720

774

180

414

504

468

270

585

900

1,062

1,332

180

1,782

667@CL=5

CE6

693

738

180

414

486

450

270

558

828

963

1,278

180

1,638



Notes

17 of 25

Rev. 1.02 October 2008


12.5 M378T6464EHS : 512MB(64Mx16 *4) Module

(T

A

=0 o C, V

DD

= 1.9V)

Symbol

IDD0

IDD1

IDD2P

IDD2Q

IDD2N

IDD3P-F

IDD3P-S

IDD3N

IDD4W

IDD4R

IDD5

IDD6

IDD7

60

160

380

500

460

40

800

800@CL=5

CE7

260

300

40

100

128

112

60

160

380

500

460

40

800

800@CL=6

CF7

260

300

40

100

128

112

60

148

360

460

440

40

740

667@CL=5

CE6

240

280

40

100

120

108



Notes

18 of 25

Rev. 1.02 October 2008

UDIMM

13.0 Input/Output Capacitance

Parameter

Non-ECC

Symbol

Input capacitance, CK and CK

CCK0

CCK1

CCK2

Input capacitance, CKE and CS

Input capacitance, Addr, RAS, CAS, WE

Input/output capacitance, DQ, DM, DQS, DQS

ECC

CI1

CI2

CIO

Input capacitance, CK and CK

CCK0

CCK1

Input capacitance, CKE and CS

CCK2

CI

1

Input capacitance, Addr, RAS, CAS, WE CI

2

Input/output capacitance, DQ, DM, DQS, DQS CIO

Note : DM is internally loaded to match DQ and DQS identically.

Min Max

M378T2863EHS

24

-

-

25

25

-

-

-

M391T2863EH3

25

25

-

-

42

42

6

25

44

-

-

44

6

DDR2 SDRAM

Min Max

M378T5663EH3

26

-

-

28

28

-

-

-

M391T5663EH3

28

28

-

-

42

42

10

28

44

-

-

44

10

(V

DD

=1.8V, V

DDQ

=1.8V, T

A

=25 o

C)

-

-

-

Min Max

M378T6464EHS

22

-

-

24

24

34

34

6

Units pF

Units pF

14.0 Electrical Characteristics & AC Timing for DDR2-800/667

(0 °C < T

OPER

< 95 °C; V

DDQ

= 1.8V + 0.1V; V

DD

= 1.8V + 0.1V)

14.1 Refresh Parameters by Device Density

Parameter

Refresh to active/Refresh command time tRFC

Average periodic refresh interval tREFI

Symbol

0 °C ≤ T

CASE

≤ 85°C

85 °C < T

CASE

≤ 95°C

256Mb

75

7.8

3.9

512Mb

105

7.8

3.9

1Gb

127.5

7.8

3.9

2Gb

195

7.8

3.9

4Gb

327.5

7.8

3.9

Units ns

µs

µs

14.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

Speed

Bin (CL - tRCD - tRP)

Parameter tCK, CL=3 tCK, CL=4 tCK, CL=5 tCK, CL=6 tRCD tRP tRC tRAS

12.5

12.5

57.5

45

DDR2-800(E7)

5 - 5 - 5 min max

5

3.75

2.5

-

8

-

8

8

-

-

-

70000

15

15

60

45

DDR2-800(F7)

6 - 6- 6 min max

-

3.75

3

2.5

8

8

-

8

-

-

-

70000

15

15

60

45

DDR2-667(E6)

5 - 5 - 5 min max

5

3.75

3

-

8

-

8

8

-

-

-

70000

Units ns ns ns ns ns ns ns ns

19 of 25

Rev. 1.02 October 2008


14.3 Timing Parameters by Speed Grade

(Refer to notes for informations related to this table at the component datasheet)

CK half pulse period

Parameter

DQ output access time from CK/CK

DQS output access time from CK/CK

Average clock HIGH pulse width

Average clock LOW pulse width

Symbol tAC tDQSCK tCH(avg) tCL(avg) tHP

Average clock period

DQ and DM input hold time

DQ and DM input setup time

Control & Address input pulse width for each input

DQ and DM input pulse width for each input

Data-out high-impedance time from CK/CK

DQS/DQS low-impedance time from CK/CK

DQ low-impedance time from CK/CK

DQS-DQ skew for DQS and associated DQ signals

DQ hold skew factor

DQ/DQS output hold time from DQS

DQS latching rising transitions to associated clock edges

DQS input HIGH pulse width

DQS input LOW pulse width

DQS falling edge to CK setup time

DQS falling edge hold time from CK

Mode register set command cycle time

MRS command to ODT update delay

Write postamble

Write preamble

Address and control input hold time

Address and control input setup time

Read preamble

Read postamble tMRD tMOD tWPST tWPRE tIH(base) tIS(base) tRPRE tRPST

Activate to activate command period for 1KB page size products tRRD

Activate to activate command period for 2KB page size products tRRD tDQSQ tQHS tQH tDQSS tDQSH tDQSL tDSS tDSH tCK(avg) tDH(base) tDS(base) tIPW tDIPW tHZ tLZ(DQS) tLZ(DQ) min

DDR2-800 max

250

175

0.9

0.4

2

0

0.4

0.35

7.5

10 x x tHP - tQHS

- 0.25

0.35

0.35

0.2

0.2

-400

-350

0.48

0.48

Min(tCL(abs), tCH(abs))

2500

125

50

0.6

0.35

x tAC(min)

2* tAC(min)

400

350

0.52

0.52

x x x x x

200

300 x

0.25

8000 x x x x tAC(max) tAC(max) tAC(max)

1.1

0.6

x x x

12

0.6

x x x min

DDR2-667 max

275

200

0.9

0.4

2

0

0.4

0.35

7.5

10 x x tHP - tQHS

-0.25

0.35

0.35

0.2

0.2

-450

-400

0.48

0.48

Min(tCL(abs), tCH(abs))

3000

175

100

0.6

0.35

x tAC(min)

2* tAC(min)

450

400

0.52

0.52

x x x x x

240

340 x

0.25

8000 x x x x tAC(max) tAC(max) tAC(max) x x

1.1

0.6

x x x

12

0.6

x

Units Notes ps ps tCK(avg) tCK(avg) ps ps ps ps tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg) ps ps ps tCK(avg) tCK(avg) ps ps ps nCK ns tCK(avg) tCK(avg) ps ps tCK(avg) tCK(avg) ns ns

40

40

35,36

35,36

37

35,36

6,7,8,21,28,31

6,7,8,20,28,31

18,40

18,40

18,40

13

38

39

30

30

30

32

10

5,7,9,23,29

5,7,9,22,29

19,41

19,42

4,32

4,32

20 of 25

Rev. 1.02 October 2008


Parameter Symbol

Four Activate Window for 1KB page size products

Four Activate Window for 2KB page size products

CAS to CAS command delay

Write recovery time

Auto precharge write recovery + precharge time

Internal write to read command delay

Internal read to precharge command delay

Exit self refresh to a non-read command

Exit self refresh to a read command

Exit precharge power down to any command

Exit active power down to read command

Exit active power down to read command

(slow exit, lower power)

CKE minimum pulse width (HIGH and LOW pulse width)

ODT turn-on delay

ODT turn-on

ODT turn-on (Power-Down mode)

ODT turn-off delay

ODT turn-off

ODT turn-off (Power-Down mode) tFAW tFAW tCCD tWR tDAL tWTR tRTP tXSNR tXSRD tXP tXARD tXARDS tCKE tAOND tAON tAONPD tAOFD tAOF tAOFPD

ODT to power down entry latency

ODT power down exit latency tANPD tAXPD

OCD drive mode output delay tOIT

Minimum time clocks remains ON after CKE asynchronously drops LOW tDelay min

DDR2-800 max

35

45

2

15

WR + tnRP

7.5

7.5

tRFC + 10

200

2

2 x x x x x x x x x x x min

DDR2-667 max

37.5

50

2

15

WR + tnRP

7.5

7.5

tRFC + 10

200

2

2 x x x x x x x x x x x

8 - AL x 7 - AL x

3

2 tAC(min) tAC(min)+2

2.5

tAC(min) tAC(min)+2

3

8

0 tIS+tCK(avg)

+tIH x

2 tAC(max)+0.7

2*tCK(avg)

+tAC(max)+1

2.5

tAC(max)+0.6

2.5*tCK(avg)

+tAC(max)+1 x x

12 x

3

2 tAC(min) tAC(min)+2

2.5

tAC(min) tAC(min)+2

3

8

0 tIS+tCK(avg)

+tIH x

2 tAC(max)+0.7

2*tCK(avg)

+tAC(max)+1

2.5

tAC(max)+0.6

2.5*tCK(avg)

+tAC(max)+1 x x

12 x

Units nCK nCK nCK ns ns ns nCK ns nCK ns ns ns nCK nCK nCK ns nCK ns ns nCK nCK ns ns

1

1,2

27

16

6,16,40

17,45

17,43,45

32

15

Notes

32

32

32

33

24,32

3,32

32

21 of 25

Rev. 1.02 October 2008

UDIMM

15.0 Physical Dimensions :

15.1 128Mbx8 based 128Mx64 Module(1 Rank)

- M378T2863EHS

133.35

131.35

128.95

(2)

2.50

63.00

A B

55.00

SPD

DDR2 SDRAM

Units : Millimeters

2.7

30.00

1.270 ± 0.10

4.00

5.00

2.50

1.50±0.10

Detail A

4.00

3.80

The used device is 128M x8 DDR2 SDRAM, FBGA.

DDR2 SDRAM Part NO : K4T1G084QE

1.00

Detail B

0.80±0.05

0.20

4.00

3.00

22 of 25

Rev. 1.02 October 2008

UDIMM

15.2 128Mbx8 based 128Mx72 Module(1 Rank)

- M391T2863EH3

133.35

131.35

128.95

ECC

(for x72)

SPD

(2)

2.50

63.00

A B

55.00

DDR2 SDRAM

Units : Millimeters

30.00

2.7

1.270 ± 0.10

4.00

5.00

2.50

1.50±0.10

Detail A

4.00

3.80



1.00

Detail B

0.80±0.05

0.20

4.00

3.00

23 of 25

Rev. 1.02 October 2008

UDIMM

15.3 128Mbx8 based 256Mx64/x72 Module(2 Ranks)

- M378T5663EH3/M391T5663EH3

133.35

131.35

128.95

N/A

(for x64)

ECC

(for x72)

SPD

(2)

2.50

63.00

N/A

(for x64)

ECC

(for x72)

A B

55.00

DDR2 SDRAM

Units : Millimeters

4.0 mm

30.00

1.0 max

1.27 ± 0.10

4.00

5.00

4.00

3.80

2.50

1.50±0.10

Detail A



1.00

Detail B

0.80±0.05

0.20

4.00

3.00

24 of 25

Rev. 1.02 October 2008

UDIMM

15.4 64Mbx16 based 64Mx64 Module (1 Rank)

- M378T6464EHS

133.35

131.35

128.95

DDR2 SDRAM

Units : Millimeters

SPD

30.00

(2)

2.50

63.00

A B

55.00

2.7

4.00

5.00

4.00

3.80

2.50

1.50±0.10

Detail A



1.00

Detail B

0.80±0.05

0.20

4.00

3.00

1.270 ± 0.10

25 of 25

Rev. 1.02 October 2008

Samsung M378T5663EH3-CE6 memory module Datasheet

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 1Gb E-die

64/72-bit Non-ECC/ECC

60FBGA & 84FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

Table of Contents

Revision History

Key Features

Related manuals

Table of contents

Samsung M378T5663EH3-CE6 memory module Datasheet

DDR2 Unbuffered SDRAM MODULE

240pin Unbuffered Module based on 1Gb E-die

64/72-bit Non-ECC/ECC

60FBGA & 84FBGA with Lead-Free and Halogen-Free

(RoHS compliant)

Table of Contents

Revision History

Key Features

Related manuals

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Table of contents