Microsemi SmartFusion2, IGLOO2, and RTG4 SmartDebug User’s Guide

SmartDebug for Software v11.6
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User’s Guide
SmartDebug for Software v11.6
Table of Contents
SmartDebug for SmartFusion2, IGLOO2, and RTG4 ................................................................ 5
Using SmartDebug with SmartFusion2 and IGLOO2 ................................................................ 6
Device Status Report - SmartFusion2 and IGLOO2 .................................................................. 7
Debug SERDES ......................................................................................................................... 7
Debug SERDES- PRBS Test..................................................................................................... 8
Debug SERDES - Loopback Test .............................................................................................. 9
Debug FPGA Array .................................................................................................................. 10
Memory Blocks Tab ................................................................................................................. 14
Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4 ...................................... 15
SmartDebug Tcl Commands .................................................................................................... 18
Device Debug ........................................................................................................................... 19
Getting Started with Device Debug .......................................................................................... 20
Using Device Debug ................................................................................................................ 20
Embedded Flash Memory (NVM) - Failure when Programming/Verifying............................... 21
Analog System Not Working as Expected ............................................................................... 21
ADC Not Sampling the Correct Value ...................................................................................... 21
How do I unlock the device security so I can debug? .............................................................. 23
How do I export a report? ........................................................................................................ 23
How do I generate diagnostic reports for my target device? ................................................... 23
Where can I find files to compare my contents/settings? ........................................................ 24
What is a UFC file? What is an EFC file? ................................................................................ 24
Is my FPGA fabric enabled? .................................................................................................... 24
Is my Embedded Flash Memory (NVM) programmed? ........................................................... 25
How do I display Embedded Flash Memory (NVM) content in the Client partition? ................ 25
How do I know if I have Embedded Flash Memory (NVM) corruption? ................................... 25
Why does Embedded Flash Memory (NVM) corruption happen? ........................................... 25
How do I recover from Embedded Flash Memory corruption? ................................................ 26
What is a JTAG IR-Capture value?.......................................................................................... 26
What does the ECC1/ECC2 error mean? ................................................................................ 26
How can I tell if my FlashROM is programmed? ..................................................................... 26
Can I compare serialization data? ........................................................................................... 26
Can I tell what security options are programmed in my device? ............................................. 26
Is my analog system configured? ............................................................................................ 26
How do I interpret data in the Device Status report? ............................................................... 27
Device Status Report: User Info .............................................................................................. 27
Device Status Report: Device State......................................................................................... 28
Device Status Report: Analog Block ........................................................................................ 29
Device Status Report: Factory Data ........................................................................................ 29
Device Status Report: Security ................................................................................................ 30
How do I interpret data in the Flash Memory (NVM) Status Report? ...................................... 31
Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4 ...................................... 32
Inspect Device Dialog Box ....................................................................................................... 39
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Table of Contents
Device Status Report ............................................................................................................... 39
Analog Block Configuration Dialog Box (SmartFusion and Fusion Only) ................................ 40
Embedded Flash Memory (NVM) Content ............................................................................... 42
Embedded Flash Memory: Browse Retrieved Data ................................................................. 43
Embedded Flash Memory: Compare Memory Client ............................................................... 45
FlashROM Content Dialog Box ................................................................................................ 45
Device Debug Tcl Commands ................................................................................................. 46
Product Support .......................................................................................... 49
Contacting the Customer Technical Support Center ............................................................... 49
Non-Technical Customer Service ............................................................................................ 49
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SmartDebug for SmartFusion2, IGLOO2, and RTG4
SmartDebug for SmartFusion2, IGLOO2, and RTG4 supports probe capabilities in the device architecture
and device debug features for memory.
To open SmartDebug, in the Design Flow window expand Debug Design and double-click SmartDebug
Design (as shown in the figure below).
The SmartDebug application appears and lists your Device, the ID Code read from your device, and your
Programmer.
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SmartDebug enables you to:
View Device Status – Displays the Device Summary Report. It is a summary of your device state, user
information, factory serial number and security information. Use this dialog box to save or print your
information for future reference.
View Flash Memory Content - Use this information to view, save or print the flash memory content in your
design.
Debug FPGA Array – SmartFusion2, IGLOO2, and RTG4 devices have built in probe points that greatly
enhance the ability to debug logic elements within the device. The enhanced debug features implemented
into the devices give access to any logic element and enable designers to check the state of inputs and
outputs in real time. Live Probe and Active Probe are only available for the SmartFusion2, IGLOO2, and
RTG4 families.
•
With Live Probe, dedicated probes (two for SmartFusion2/IGLOO2 and one for RTG4) can be
configured to observe a Probe Point (any input or output of a logic element). The probe data can then
be sent to an oscilloscope or even redirected back to the FPGA Fabric to drive a software logic
analyzer.
•
Active Probe allows dynamic asynchronous read and write to a flip-flop or probe point. This enables
you to quickly observe the output of the logic internally or to quickly experiment on how the logic will be
affected by writing to a probe point.
•
Memory debug lets you perform dynamic asynchronous reads and writes to a micro SRAM or large
SRAM block so you can quickly verify if the content of the memory is changing as expected.
•
Probe Insertion lets you route certain nodes (or debug points) in the FPGA design to the external world
through unused I/Os. You can attach an oscilloscope/logic analyzer to monitor them as live signals.
Debug SERDES - Enables you to examine and debug the SERDES blocks in your design. You can
configure your SERDES debug, and run PRBS and Loopback tests.
File Menu
The File Menu lets you execute SmartDebug-specific Tcl scripts (File > Execute Script) and export
SmartDebug-specific commands to a script file (File > Export Script File). You may pass the Tcl script to
SmartDebug for batch-mode execution from Libero. Refer to run_tool (SmartFusion2, IGLOO2 and RTG4)
for details.
View Log
SmartDebug displays the Log Window by default when it is invoked. To suppress the Log window display,
select the View menu and toggle View Log.
The Log Windows contains four tabs:
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Message window – displays standard output messages
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Errors window – displays error messages
•
Warnings windows – displays warning messages
•
Info window – displays general information
Using SmartDebug with SmartFusion2 and IGLOO2
The most common flow for Device Debug is:
1.
2.
Expand Debug Design and double-click Smart Debug Design in the Design Flow window.
SmartDebug opens for your target device.
3.
Click View Device Status to view the device status report and check for issues.
4.
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Create your design. You must have a FlashPro programmer connected in order to use SmartDebug.
Examine individual silicon features, such as FPGA debug.
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Device Status Report - SmartFusion2 and IGLOO2
Device Status Report - SmartFusion2 and IGLOO2
This dialog box displays the Device Information report. The Device Information report is a summary of your
device state, user information, factory serial number and security information. Use this dialog box to save or
print your information for future reference.
Debug SERDES
The Debug SERDES dialog box (as shown in the figure below) enables you to examine and debug the
SERDES blocks in your design.
To Debug SERDES, expand SmartDebug in the Design Flow window and double-click Debug SERDES.
Debug SERDES Configuration is explained below. See the PRBS Test and Loopback Test topics for
information specific to those procedures.
SERDES Block identifies which SERDES block you are configuring. Use the dropdown menu to select from
the list of SERDES blocks in you design.
Debug SERDES - Configuration
Configuration Report
The Configuration Report output depends on the options you selected in your PRBS Test and Loopback
Tests. The default report lists the following for each Lane in your SERDES block:
Lane mode - Indicates the programmed mode on a SERDES lane as defined by the SERDES system
register.
PMA Ready - Indicates whether PMA has completed its internal calibration sequence for the specific lane
and the PMA is operational. See the SmartFusion2 or IGLOO2 High Speed Serial Interfaces User's Guide
on the Microsemi website for details.
TxPll status - Indicates the loss-of-lock status for the TXPLL is asserted and remains asserted until the PLL
reacquires lock.
RxCDR status - Indicates the RxCDR loss-of-lock for the channel when asserted and locking to the
incoming data stream.
Click Refresh Report to update the contents of your SERDES Configuration Report. Any changes to the
specified SERDES register programming can be read back to the report.
SERDES Register Read or Write
Script - Runs your MSS Read/Write using a script. Enter the full pathname for the script location or click the
Browse button to navigate to your script file. Click Execute to run the script.
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Figure 1 · Debug SERDES - Configuration
Debug SERDES- PRBS Test
PRBS data stream patterns are generated and checked by the internal SERDES block. These are used to
self-test signal integrity of the device. You can switch the device through several predefined patterns.
View Loopback Test settings in the Debug SERDES - Loopback Test topic.
SERDES Block identifies which SERDES block you are configuring. Use the dropdown menu to select from
the list of SERDES blocks in you design.
SERDES Lanes
Select the Lane and Lane Status on which you wish to run the PRBS test. Lane mode indicates the
programmed mode on a SERDES lane as defined by the SERDES system register.
Test Type
Near End Serial Loopback (On-Die) enables a self test of the device. The serial data stream is sent from
the SERDES TX output and folded back onto the SERDES RX input.
Serial Data (Off-Die) is the normal system operation where the data stream is sent off chip from the TX
output and must be connected to the RX input via a cable or other type of electrical interconnection
Pattern
The SERDESIF includes an embedded test pattern generator and checker used to perform serial
diagnostics on the serial channel, as shown in the table below.
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Debug SERDES - Loopback Test
Pattern
Type
PRBS7
Pseudo-Random data stream of 2^7 polynomial sequences
PRBS11
Pseudo-Random data stream of 2^11 polynomial sequences
PRBS23
Pseudo-Random data stream of 2^23 polynomial sequences
PRBS31
Pseudo-Random data stream of 2^31 polynomial sequences
Error Count
Lists the number of errors after running your PRBS test. Click Reset to reset to zero.
Figure 2 · Debug SERDES - PRBS Test
Debug SERDES - Loopback Test
Loopback data stream patterns are generated and checked by the internal SERDES block. These are used
to self-test signal integrity of the device. You can switch the device through predefined tests.
See the PRBS Test topic for more information on the PRBS test options.
SERDES Block identifies which SERDES block you are configuring. Use the dropdown menu to select from
the list of SERDES blocks in you design.
SERDES Lanes
Select the Lane and Lane Status on which you wish to run the Loopback test. Lane mode indicates the
programmed mode on a SERDES lane as defined by the SERDES system register.
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Test Type
PCS Far End PMA RX to TX Loopback- See the SmartFusion2 or IGLOO2 High Speed Serial Interfaces
User's Guide on the Microsemi website for details.
Figure 3 · Debug SERDES - Loopback Test
Debug FPGA Array
The Debug FPGA Array dialog box enables you to view your Live Probes, Active Probes and Memory
Blocks and allows you to Insert Probes (Probe Insertion).
Debug File - Shows a path to your Debug File. The Debug file contains information used by SmartDebug
mainly for mapping user design names to their respective physical addresses. It also contains other
information used during debug process.
The Debug file is generated by Libero SoC during Place and Route and is stored in the design folder.
The Debug FPGA Array dialog box includes the following four tabs:
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•
Live Probes
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Active Probes
•
Memory Blocks
•
Probe Insertion
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Debug FPGA Array
Live Probes (SmartFusion2, IGLOO2, and RTG4)
The Live Probes tab shows a table with the probe name and pin type.
Note: SmartFusion2 and IGLOO2 support two probe channels, and RTG4 supports one probe channel.
SmartFusion2 and IGLOO2
Two Probe Channels (ChannelA and ChannelB) are available. Once a Probe Name is selected, it can be
assigned to either ChannelA or ChannelB.
Note: At least one channel must be set; if you intend to use both probes, they must be set at the same time.
Note: The Active Probes READ/WRITE will overwrite the settings of Live Probe channels (if any).
After the channels have been set, SmartDebug configures the ChannelA and ChannelB IO’s to monitor the
desired probe points. The maximum number of simultaneous probes is two internal signals. There is also a
Filter box to filter through the Probe Names. As you begin typing in the Filter box, the Probe Name table only
shows results for the queried names.
RTG4
One Probe Channel (Probe Read Data Pin) is available for RTG4 for debug. Once a Probe Name is
selected, it can be assigned to the Probe Channel (Probe Read Data Pin).
The Active Probes READ/WRITE will overwrite the settings of Live Probe channels (if any).
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Debug FPGA Array
Active Probes (SmartFusion2, IGLOO2, and RTG4)
On the Active Probes tab a table of Probe Names is shown with the Name, Type (which is the physical
location of the flip-flop) and Value.
Click the Select Active Probes button to open a window that lists all the Available Probe Points and
Selected Probe Points. Both lists can be filtered using the inline Filter box. Between the two lists of Probe
points are buttons for adding and removing probe points from either list.
Figure 4 · Active Probes Tab in SmartDebug FPGA Array Dialog Box
Once you have selected the desired probe, points appear in the Active Probe Data chart and you can read
and write multiple probes at the same time (as shown in the figure below).
The Value column fields are editable for each of the probe points. Clicking the circle shaped icon changes
the value, and clicking the back-arrow resets the value. Fields that have been changed are indicated by red
text. After the probes have been written, the values return to black text.
Figure 5 · Active Probes Tab - Select Active Probe Points
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Memory Blocks Tab
The Memory Blocks tab shows a dropdown menu of defined memory blocks that are specified in your design
and generate a debug file. Once you select a memory block you can click Read Block to show the current
contents of the memory or write to individual memory locations. Each field is editable and multiple memory
locations can be written at the same time.
Each field is a 9 bit memory word so valid inputs are hexadecimal values between 0x0 and 0x1FF (as shown
in the figure below).
Figure 6 · Debug FPGA Array - Memory Blocks Tab
Fields that have changed but have not yet been written appear in red text until you click the Write Block
button to initiate a memory write (as shown in the figure below).
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Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
Figure 7 · Memory Blocks with Updated Values
Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
Introduction
Probe insertion is a post-layout debug process that enables internal nets in the FPGA design to be routed to
unused I/Os, as shown. Nets are selected and assigned to probes using the Probe Insertion window in the
SmartDebug tools. The re-routed design can then be programmed into the FPGA, where an external logic
analyzer or oscilloscope can be used to view the activity of the probed signal.
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Probe Insertion in the Design Process
The Probe Insertion debug feature is complementary to the Live Probes and Active Probes. In the case of
Live Probes and Active Probes, a special dedicated probe circuitry is used.
Probe Insertion
1.
Double-click SmartDebug Design in the Design Flow window to open the SmartDebug window.
Note: FlashPro Programmer must be connected for SmartDebug to open.
2.
Select Debug FPGA Array and then select the Probe Insertion tab.
Figure 8 · Probe Insertion Tab
3.
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Click Add Probe.
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Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
The Add Probe dialog box displays the nets available to be probed on the right side. Each entry has a
Net and Driver name which identifies that probe point. The left (filter) pane allows filtering of the probe
points by net names or instance names.
To add filtering for Cell Types, enter the Cell Type Name in the Cell Type field. Enter, for example,
SEQ in the Cell Type field and all SEQ (Sequential) cell types will be displayed. If you enter COMB in
the Cell Type field, all COMB (Combinational Cells) will be displayed.
Figure 9 · Add Probe(s) Dialog Box
4.
Select one or more nets to probe and click OK.
The selected net(s) will appear in the Probes table in the Probe Insertion tab, as shown in the figure
below. SmartDebug automatically generates the Port Name for the probe. You can change the Port
Name from the default if desired.
5.
Assign a package pin to the probe using the drop-down list in the Package Pin column. You can assign
the probe to any unused package pin (spare I/O).
Figure 10 · Debug FPGA Array > Probe Insertion > Add Probe
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6.
Click Run.
This triggers Place and Route in the incremental mode, and the selected probe nets are routed to the
selected package pin. After incremental Place and Route, Libero automatically reprograms the device
(with the added probes).
The log window shows the status of the Probe Insertion run.
Edit Probes
To edit/change a probe, select the probe and click Edit Probe. The Edit Net for Probe dialog box appears.
Figure 11 · Edit Net for Probe Dialog Box
Click and select a net to replace the original net for the Probe.
Probe Deletion
To delete a probe, select the probe and click Delete. To delete all the probes, click Delete All.
Note: Deleting probes from the probes list without Run does not automatically remove the probes from the
design.
Reverting to the Original Design
To revert to the original design after you have finished debugging:
1.
2.
In SmartDebug, click Delete All to delete all probes.
Click Run.
3.
Wait until the action has completed by monitoring the activity indicator (spinning blue circle). Action is
completed when the activity indicator disappears.
4.
Close SmartDebug.
See Also
Debug FPGA Array
SmartDebug Tcl Commands
The following table lists the Tcl commands related to Device Debug for SmartFusion2 and IGLOO2. Click
the command to view more information.
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Device Debug
Table 1 · Device Debug Tcl Commands
Command
Action
Debug File
set_debug_data_file Sets the debug file
Probe
set_live_probe
Set Live probe channels A and/or B to the specified probe point
(or points)
select_active_probe Manages the current selection of active probe points to be used
by active probe READ operations
read_active_probe
Reads active probe values from the device
write_active_probe
Sets the target probe point on the device to the specified value
LSRAM
read_lsram
Reads a specified block of large SRAM from the device
write_lsram
Writes a seven bit word into the specified large
SRAM location
uSRAM
read_usram
Reads a uSRAM block from the device.
write_usram
Writes a seven bit word into the specified
uSRAM location.
Device Debug
Device Debug / SmartDebug enables you to use JTAG to interrogate and view embedded silicon features
and device status (FlashROM, Security Settings, Embedded Flash Memory (NVM) and Analog System).
It provides tools to help troubleshoot some of the common issues related to the Embedded Flash Memory
and Analog System.
Device Debug supports IGLOO, ProASIC3, SmartFusion and Fusion devices. SmartDebug supports
SmartFusion2 and ProASIC3 devices.
The user support is separated into two sections:
•
Using Device Debug to Find Solutions to Common Issues - Contains common issues and
troubleshooting instructions that will enable you to solve your problems as quickly as possible.
•
Frequently Asked Questions - Answers to the most frequently asked questions about the tools and
silicon features related to your solution.
If you are unfamiliar with Device Debug, you may find it helpful to review the Getting Started with Device
Debug topic. You can view descriptions of the Device Debug interface in the Reference section of the help.
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Getting Started with Device Debug
This topic introduces the basic elements and features of Device Debug. If you are already familiar with the
user interface then proceed to Solutions to Common Problems or Frequently Asked Questions sections.
Device Debug (SmartDebug for some families) enables you to use JTAG to interrogate and view embedded
silicon features and device status (FlashROM, Security Settings, Embedded Flash Memory (NVM) and
Analog System). Device Debug is available as a part of the FlashPro programming tool.
See the Using Device Debug topic for an overview of the use flow.
You can use the debugger to:
•
Get device status and view diagnostics
•
Use the FlashROM debug GUI to read out and compare content
•
Use the Embedded Flash Memory Debug GUI to read out and compare your content with your original
files
•
Use the Analog System Debug to read out and compare your analog block configuration with your
original file
Using Device Debug
The most common flow for Device Debug is:
1.
2.
Start FlashPro. If necessary, create a new project.
Set up your FlashPro Project with or without a PDB file. If you are in single-device mode you will need
a PDB file. You can create a PDB file in both Single Device and Chain mode.
With a PDB, you will get additional information such as FlashROM and Embedded Flash Memory
partitions when debugging the silicon features. Best practice is to use a PDB with a valid-use design to
start a debug session.
3.
4.
5.
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Select the target device from your chain and click Inspect Device.
Click Device Status to get device status and check for issues
Examine individual silicon features (FlashROM, Embedded Flash Memory Block and Analog System)
on the device.
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Embedded Flash Memory (NVM) - Failure when Programming/Verifying
Solutions to Common Issues Using Device
Debug
Embedded Flash Memory (NVM) - Failure when
Programming/Verifying
If the Embedded Flash Memory failed verification when executing the PROGRAM_NVM, VERIFY_NVM or
PROGRAM_NVM_ACTIVE_ARRAY action, the failing page may be corrupted. To confirm and address this
issue:
1.
In the Inspect Device window click View Flash Memory Content.
3.
Click Read from Device; the retrieved data appears in the lower part of the window.
2.
4.
Select the Flash Memory block and client (or page range) to retrieve from the device.
Click View Detailed Status to check the NVM Status.
Note: You can use the check_flash_memory and read_flash_memory Tcl commands to perform
diagnostics similar to the commands outlined above.
5.
If the NVM is corrupted you must reset the affected NVM pages.
To reset the affected NVM pages, either re-program the pages with your original data or ‘zero-out’ the
pages by using the Tcl command recover_flash_memory.
If the Embedded Flash Memory failed verification when executing a VERIFY_NVM or
VERIFY_NVM_ACTIVE_ARRAY action, the failure may be due to the change of content in your design. To
confirm this, repeat steps 1-3 above.
Note: NVM corruption is still possible when writing from user design. Check NVM status for confirmation.
Analog System Not Working as Expected
If the Analog System is not working correctly, it may be due the following:
1.
System supply issue. To troubleshoot:
•
Physically verify that all the supplies are properly connected to the device and they are at the proper
level. Then confirm by running the Device Status.
•
Physically verify that the relevant channels are correctly connected to the device.
2.
Analog system is not properly configured. You can confirm this by examining the Analog System.
ADC Not Sampling the Correct Value
If the ADC is sampling all zero values then the wrong analog pin may be connected to the system, or the
analog pin is disconnected. If that is not the case and the ADC is not sampling the correct value, it may be
due to the following:
1.
System supply issues - Run the device status to confirm.
2.
Analog system is not configured at all - To confirm, read out the ACM configuration and verify if the
ACM content is all zero.
3.
Analog system is not configured correctly - To confirm, read out the ACM configuration and verify that
the configuration is as expected .
Once analog block configuration has been confirmed, you can use the sample_analog_channel Tcl
command for debug sampling of the analog channel with user-supplied sampling parameters.
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If you have access to your Analog System Builder settings project (<Libero IDE
project>/Smartgen/AnalogBlock), you may use the compare function provided by the tool.
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How do I unlock the device security so I can debug?
Frequently Asked Questions
How do I unlock the device security so I can debug?
You must provide the PDB file with a User Pass Key in order to unlock the device and continue debugging.
If you do not have a PDB with User Pass Key, you can create a PDB file in FlashPro (if you know the Pass
Key value).
How do I export a report?
You can export three reports from the Device Debug GUI: Device Status, Client Detailed Status from the
NVM, or the Compare Client Content report from the NVM. Each of those reports can be saved and printed.
If using a Tcl command, you can use the –file <filename> option for the following commands:
read_flash_memory
check_flash_memory
compare_memory_client
read_device_status
read_flashrom
read_analog_block_config
sample_analog_channel
compare_flashrom_client
compare_analog_config
For example, you can use the following command to export the content of the client 'datastore1' in NVM
block 0 to the report file datastore1_content.txt:
read_flash_memory –client “datastore1” –file {C:\temp\datastore1_content.txt}
How do I generate diagnostic reports for my target device?
A set of diagnostic reports can be generated for your target device depending on which silicon feature you
are debugging. A set of Tcl commands are available to export those reports. The following is a summary of
those Tcl commands based on the silicon features.
When using the –file parameter, ensure that you use a different file name for each command so you do not
overwrite the report content. If you do not specify the –file option in the Tcl, the output results will be directed
to the FlashPro log window.
For the overall device:
read_device_status
read_id_code
For FlashROM:
compare_flashrom_client
read_flashrom
For Embedded Flash Memory (NVM):
compare_memory_client
check_flash_memory
read_flash_memory
For Analog Block:
read_analog_block_config
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compare_analog_config
sample_analog_channel
To execute the Tcl command, from the File menu choose Run Script.
Where can I find files to compare my contents/settings?
FlashROM
You can compare the FlashROM content in the device with the data in the PDB file. You can find the PDB in
the <Libero IDE project>/Designer/Impl directory.
Embedded Flash Memory (NVM)
You can compare the Embedded Flash Memory content in the device with the data in the PDB file. You can
find the PDB in the <Libero IDE project>/Designer/Impl directory.
Analog System
You can compare the Analog System configuration in the device with the data in the loaded PDB file or in
the Analog System folder. Go to:
•
Fusion devices - <Libero IDE project>/Smartgen/AnalogBlock
•
SmartFusion devices - <Libero IDE Project>/component/<SmartDesign Project>/MSS_ACE_0
The tool automatically identifies the necessary files in the selected folder for comparison.
What is a UFC file? What is an EFC file?
UFC is the User FlashROM Configuration file, generated by the FlashROM configurator; it contains the
partition information set by the user. It also contains the user-selected data for region types with static data.
However, for AUTO_INC and READ_FROM_FILE, regions the UFC file contains only:
•
Start value, end value, and step size for AUTO_INC regions, and
•
File directory for READ_FROM_FILE regions
EFC is the Embedded Flash Configuration file, generated by the Flash Memory Builder in the Project
Manager Catalog; it contains the partition information and data set by the user.
Both UFC and EFC information is embedded in the PDB when you generate the PDB file.
Is my FPGA fabric enabled?
When your FPGA fabric is programmed, you will see the following statement under Device State in the
Device Status report:
FPGA Array Status: Programmed and Enabled
If the FPGA fabric is not programmed, the Device State shows:
FPGA Array Status: Not Enabled
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Is my Embedded Flash Memory (NVM) programmed?
Embedded Flash Memory (NVM) Frequently
Asked Questions
Is my Embedded Flash Memory (NVM) programmed?
To figure out if your NVM is programmed, read out and view the NVM content or perform verification with the
PDB file.
To examine the NVM content, see the FlashROM Memory Content Dialog Box.
To verify the NVM with the PDB select the VERIFY or VERIFY_NVM action in FlashPro.
How do I display Embedded Flash Memory (NVM) content in the
Client partition?
You must load your PDB into your FlashPro project in order to view the Embedded Flash Memory content in
the Client partition. To view NVM content in the client partition:
1.
2.
3.
4.
5.
6.
Load your PDB into your FlashPro project.
Click Inspect Device.
Click View Flash Memory Content.
Choose a block from the drop-down menu.
Select a client.
Click Read from Device. The Embedded Flash Memory content from the device appears in the Flash
Memory dialog box.
See the Flash Memory Dialog Box topic for more description on viewing the NVM content.
How do I know if I have Embedded Flash Memory (NVM)
corruption?
When Embedded Flash Memory is corrupted, checking Embedded Flash Memory may return with any or all
of the following page status:
•
ECC1/ECC2 failure
•
Page write count exceeds the 10-year retention threshold
•
Page write count is invalid
•
Page protection is set illegally (set when it should not be)
See the How do I interpret data in the Flash Memory (NVM) Status Report? topic for details.
If your Embedded Flash Memory is corrupted, you can recover by reprogramming with original design data.
Alternatively, you can ‘zero-out’ the pages by using the Tcl command recover_flash_memory.
Why does Embedded Flash Memory (NVM) corruption happen?
Embedded Flash Memory corruption occurs when Embedded Flash Memory programming is interrupted due
to:
•
Supply brownout; monitor power supplies for brownout conditions. For SmartFusion monitor the
VCC_ENVM/VCC_ROSC voltage levels; for Fusion, monitor VCC_NVM/VCC_OSC.
•
Reset signal is not properly tied off in your design. Check the Embedded Memory reset signal.
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How do I recover from Embedded Flash Memory corruption?
Reprogram with original design data or ‘zero-out’ the pages by using the Tcl command
recover_flash_memory.
What is a JTAG IR-Capture value?
JTAG IR-Capture value contains private and public device status values. The public status value in the value
read is ISC_DONE, which indicates if the FPGA Array is programmed and enabled.
The ISC_DONE signal is implemented as part of IEEE 1532 specification.
What does the ECC1/ECC2 error mean?
ECC is the Error Correction Code embedded in each Flash Memory page.
ECC1 – One bit error and correctable.
ECC2 – Two or more errors found, and not correctable.
How can I tell if my FlashROM is programmed?
To verify that your FlashROM is programmed, read out and view the FlashROM content or perform
verification with the PDB file by selecting the VERIFY or VERIFY_FROM action in FlashPro.
Can I compare serialization data?
To compare the serialization data, you can read out the FlashROM content and visually check data in the
serialization region. Note that a serialization region can be an AUTO_INC or READ_FROM_FILE region.
For serialization data in the AUTO_INC region, check to make sure that the data is within the specified
range for that region.
For READ_FROM_FILE region, you can search for a match in the source data file.
Can I tell what security options are programmed in my device?
To determine the programmed security settings, run the Device Status option from the Inspect Device dialog
and examine the Security Section in the report.
This section lists the security status of the FlashROM, FPGA Array and Flash Memory blocks.
Is my analog system configured?
To determine if the analog block is configured, run the Device Status option from the Inspect Device dialog
and examine the Analog Block Section in the report. For example, the excerpt from the Device Status report
below shows that the analog block status is operational:
Analog Block:
OABTR Register (HEX): 0dbe37b
3.3V (vdd33): PASS
1.5V (vdd15): PASS
Bandgap: PASS
-3.3V (vddn33): PASS
ADC Reference: PASS
FPGA_Good: PASS
Status: Analog Block is operational
If you read out an all zero value when examining the Analog System Configuration, then it is possible that
the Analog System is not configured.
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How do I interpret data in the Device Status report?
You need to compare your analog system configuration with the design configuration from the Analog
System Builder
The -3.3V (vddn33) voltage is optional.
How do I interpret data in the Device Status report?
The Device Status Report generated from the FlashPro Device Debug Feature contains the following
sections:
•
IDCode (see below)
•
User Information
•
Device State
•
Analog Block (SmartFusion and Fusion only)
•
Factory Data
•
Security Settings
IDCode
The IDCode section shows the raw IDCode read from the device. For example, in the Device Status report
for an AFS600 device, you will find the following statement:
IDCode (HEX): 233261cf
The IDCode is compliant to IEEE 1149.1. The following table lists the IDCode bit assignments:
Table 2 · IDCode Bit Assignments
Bit Field (little
endian)
Example Bit Value for
AFS600 (HEX)
Description
Bit [31-28] (4 bits)
2
Silicon Revision
Bit [27-12] (16
bits)
3326
Device ID
Bit [11-0] (12 bits)
1cf
IEEE 1149.1 Manufacturer ID for
Microsemi
Device Status Report: User Info
The User Information section reports the information read from the User ROW (UROW) of IGLOO,
ProASIC3, SmartFusion and Fusion devices. The User Row includes user design information as well as
troubleshooting information, including:
•
Design name (10 characters max)
•
Design check sum (16-bit CRC)
•
Last programming setup used to program/erase any of the silicon features.
•
FPGA Array / Fabric programming cycle count
For example:
User Information:
UROW data (HEX): 603a04e0a1c2860e59384af926fe389f
Programming Method: STAPL
Programmer: FlashPro3
Programmer Software: FlashPro vX.X
Design Name: ABCBASICTO
Design Check Sum: 603A
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Algorithm Version: 19
Array Prog. Cycle Count: 19
Table 3 · Device Status Report User Info Description
Category
Field
Description
User Row Data
(Example)
Raw data from User Row
UROW data (HEX):
(UROW)
603a04e0a1c2860e59384af926fe389f
Programming
Troubleshooting
Info
(Example)
Programming Method: STAPL
Programmer: FlashPro3
Programmer Software: FlashPro v8.6
Algorithm Version: 19
Known programming setup
used. This includes:
Programming method/file,
programmer and software. It
also includes programming
Algorithm version used.
Design Info
(Example)
Design Name: ABCASICTO
Design Check Sum: 603A
Design name (limited to 10
characters) and check sum.
Design check sum is a 16bit CRC calculated from the
fabric (FPGA Array)
datastream generated for
programming. If encrypted
datastream is generated
selected, the encrypted
datastream is used for
calculating the check sum.
Device Status Report: Device State
The device state section contains:.
•
IR-Capture register value, and
•
The FPGA status
The IR-Capture is the value captured by the IEEE1149.1 instruction register when going through the IRCapture state of the IEEE 1149.1 state machine. It contains information reflecting some of the states of the
devices that is useful for troubleshooting.
One of the bits in the value captured is the ISC_DONE value, specified by IEEE 1532 standard. When the
value is ‘1’ it means that the FPGA array/fabric is programmed and enabled. This is available for IGLOO,
ProASIC3, SmartFusion and Fusion devices.
For example:
Device State:
IRCapture Register (HEX): 55
FPGA Array Status: Programmed and enabled
For a blank device:
Device State:
IRCapture Register (HEX): 51
FPGA Array Status: Not enabled
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Device Status Report: Analog Block
Device Status Report: Analog Block
The Analog block of the SmartFusion and Fusion devices monitors some of the key power supplies needed
by the device to function. These power supply status is captured in the OABTR test register in the Analog
block.
For example, if you run Device Status when the Fabric and Analog configuration is programmed and
powered up successfully the report indicates:
Analog Block:
OABTR Register (HEX): 0dbe3bb
3.3V (vdd33): PASS
1.5V (vdd15): PASS
Bandgap: PASS
-3.3V (vddn33): PASS
ADC Reference: PASS
FPGA_Good: PASS
Status: Analog Block is operational
Table 4 · Device Status Report - Analog Block Description
Analog Block Status
Description
OABTR Register
RAW data captured from the device
3.3V (vdd33)
Vcc33a supply status
1.5V (vdd15)
Vccnvm supply status
Bandgap
Internal bandgap supply status
ADC Reference
ADC reference voltage status
-3.3V (vddn33)
Vddn33 supply status (optional voltage)
FPGA Good
FPGA array or Fabric status
If the Fusion device is erased, the report indicates:
Analog Block:
OABTR Register (HEX): 188e3ba
3.3V (vdd33): PASS
1.5V (vdd15): PASS
Bandgap: PASS
-3.3V (vddn33): FAIL
ADC Reference: FAIL
FPGA_Good: FAIL
Status: Analog Block is non-operational
Analog Block is not programmed
Device Status Report: Factory Data
The Factory Data section lists the Factory Serial Number (FSN).
Each of the IGLOO, ProASIC3, SmartFusion and Fusion devices has a unique 48-bit FSN.
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Device Status Report: Security
The security section shows the security options for the FPGA Array, FlashROM and Flash Memory (NVM)
block that you programmed into the device.
For example, using a Fusion AFS600 device:
Security:
Security Register (HEX): 0000000088c01b
FlashROM
Write/Erase protection: Off
Read protection: Off
Encrypted programming: Off
FPGA Array
Write/Erase protection: Off
Verify protection: Off
Encrypted programming: Off
FlashMemory Block 0
Write protection: On
Read protection: On
Encrypted programming: Off
FlashMemory Block 1
Write protection: On
Read protection: On
Encrypted programming: Off
Table 5 · Device Status Report - Security Description
Security
Status Info
Description
Security
Register (HEX)
Raw data captured from the device's security status register
Write/Erase
Protection
Write protection is applicable to FlashROM, FPGA Array (Fabric)and
Flash Memory (NVM) blocks. When On, the Silicon feature is
write/erase protected by user passkey.
Read
Protection
Read protection is applicable to FlashROM and Flash Memory (NVM)
blocks. When On, the Silicon feature is read protected by user
passkey.
Verify
Protection
Verify Protection is only applicable to FPGA Array (Fabric) only. When
On, the FPGA Array require user passkey for verification.
Reading back from the FPGA Array (Fabric) is not supported.
Verification is accomplished by sending in the expected data for
verification.
Encrypted
Programming
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Encrypted Programming is supported for FlashROM, FPGA Array
(Fabric) and Flash Memory (NVM) blocks. When On, the silicon
feature is enable for encrypted programmed. This allows field design
update with encrypted datastream so the user design is protected.
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How do I interpret data in the Flash Memory (NVM) Status Report?
Encrypted Programming
To allow encrypted programming of the features, the target feature cannot be Write/Erase protected by user
passkey.
The security settings of each silicon feature when they are enabled for encrypted programming are listed
below.
FPGA Array (Fabric)
Write/Erase protection: Off
Verify protection: Off
Encrypted programming: On
Set automatically by Designer or FlashPro when you select to enable encrypted programming of the FPGA
Array (Fabric). This setting allows the FPGA Array (Fabric) to be programmed and verified with an encrypted
datastream.
FlashROM
Write/Erase protection: Off
Read protection: On
Encrypted programming: On
Set automatically by Designer or FlashPro when you select to enable encrypted programming of the
FlashROM. This setting allows the FlashROM to be programmed and verified with an encrypted datastream.
FlashROM always allows verification. If encrypted programming is set, verification has to be performed with
encrypted datastream.
Designer and FlashPro automatically set the FlashROM to be read protected by user passkey when
encrypted programming is enabled. This protects the content from being read out of the JTAG port after
encrypted programming.
Flash Memory (NVM) Block
Write/Erase protection: Off
Read protection: On
Encrypted programming: On
The above setting is set automatically set by Designer or FlashPro when you select to enable encrypted
programming of the Flash Memory (NVM) block. This setting allows the Flash Memory (NVM) block to be
programmed with an encrypted datastream.
The Flash Memory (NVM) block does not support verification with encrypted datastream.
Designer and FlashPro automatically set the Flash Memory (NVM) block to be read protected by user
passkey when encrypted programming is enabled. This protects the content from being read out of the
JTAG port after encrypted programming.
How do I interpret data in the Flash Memory (NVM) Status Report?
The Embedded Flash Memory (NVM) Status Report generated from the FlashPro Device Debug Feature
consists of the page status of each NVM page. For example:
Flash Memory Content [ Page 34 to 34 ]
FlashMemory Page #34:
Status Register(HEX): 00090000
Status ECC2 check: Pass
Data ECC2 Check: Pass
Write Count: Pass (2304 writes)
Total number of pages with status ECC2 errors: 0
Total number of pages with data ECC2 errors: 0
Total number of pages with write count out of range: 0
FlashMemory Check PASSED for [ Page 34 to 34 ]
The 'check_flash_memory' command succeeded.
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The Execute Script command succeeded.
Table 6 · Embedded Flash Memory Status Report Description
Flash
Memory
Status Info
Description
Status
Register
(HEX)
Raw page status register captured from device
Status
ECC2
Check
Check for ECC2 issue in the page status
Data ECC2
Check
Check for ECC2 issue in the page data
Write Count
Check if the page-write count is within the expected range.
The expected write count is greater than or equal to:
6,384 - SmartFusion devices
2,288 - Fusion devices
Note: Write count, if corrupted, cannot be reset to a valid value within the
customer flow;invalid write count will not prevent device from being
programmed with the FlashPro tool.
The write count on all good eNVM pages is set to be 2288 instead of 0 in
the manufacturing flow. The starting count of the eNVM is 2288. Each
time the page is programmed or erased the count increments by one.
There is a Threshold that is set to 12288, which equals to 3 * 4096.
Since the threshold can only be set in multiples of 4096 (2^12), to set a
10,000 limit, the Threshold is set to 12288 and the start count is set to
2288; and thus the eNVM has a 10k write cycle limit. After the write count
exceeds the threshold, the STATUS bit goes to 11 when attempting to
erase/program the page.
Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
Introduction
Probe insertion is a post-layout debug process that enables internal nets in the FPGA design to be routed to
unused I/Os, as shown. Nets are selected and assigned to probes using the Probe Insertion window in the
SmartDebug tools. The re-routed design can then be programmed into the FPGA, where an external logic
analyzer or oscilloscope can be used to view the activity of the probed signal.
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Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
Probe Insertion in the Design Process
The Probe Insertion debug feature is complementary to the Live Probes and Active Probes. In the case of
Live Probes and Active Probes, a special dedicated probe circuitry is used.
Probe Insertion
1.
Double-click SmartDebug Design in the Design Flow window to open the SmartDebug window.
Note: FlashPro Programmer must be connected for SmartDebug to open.
2.
Select Debug FPGA Array and then select the Probe Insertion tab.
Figure 12 · Probe Insertion Tab
3.
Click Add Probe.
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The Add Probe dialog box displays the nets available to be probed on the right side. Each entry has a
Net and Driver name which identifies that probe point. The left (filter) pane allows filtering of the probe
points by net names or instance names.
To add filtering for Cell Types, enter the Cell Type Name in the Cell Type field. Enter, for example,
SEQ in the Cell Type field and all SEQ (Sequential) cell types will be displayed. If you enter COMB in
the Cell Type field, all COMB (Combinational Cells) will be displayed.
Figure 13 · Add Probe(s) Dialog Box
4.
Select one or more nets to probe and click OK.
The selected net(s) will appear in the Probes table in the Probe Insertion tab, as shown in the figure
below. SmartDebug automatically generates the Port Name for the probe. You can change the Port
Name from the default if desired.
5.
Assign a package pin to the probe using the drop-down list in the Package Pin column. You can assign
the probe to any unused package pin (spare I/O).
Figure 14 · Debug FPGA Array > Probe Insertion > Add Probe
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Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
6.
Click Run.
This triggers Place and Route in the incremental mode, and the selected probe nets are routed to the
selected package pin. After incremental Place and Route, Libero automatically reprograms the device
(with the added probes).
The log window shows the status of the Probe Insertion run.
Edit Probes
To edit/change a probe, select the probe and click Edit Probe. The Edit Net for Probe dialog box appears.
Figure 15 · Edit Net for Probe Dialog Box
Click and select a net to replace the original net for the Probe.
Probe Deletion
To delete a probe, select the probe and click Delete. To delete all the probes, click Delete All.
Note: Deleting probes from the probes list without Run does not automatically remove the probes from the
design.
Reverting to the Original Design
To revert to the original design after you have finished debugging:
1.
2.
In SmartDebug, click Delete All to delete all probes.
Click Run.
3.
Wait until the action has completed by monitoring the activity indicator (spinning blue circle). Action is
completed when the activity indicator disappears.
4.
Close SmartDebug.
See Also
Debug FPGA Array
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Active Probes (SmartFusion2, IGLOO2, and RTG4)
On the Active Probes tab a table of Probe Names is shown with the Name, Type (which is the physical
location of the flip-flop) and Value.
Click the Select Active Probes button to open a window that lists all the Available Probe Points and
Selected Probe Points. Both lists can be filtered using the inline Filter box. Between the two lists of Probe
points are buttons for adding and removing probe points from either list.
Figure 16 · Active Probes Tab in SmartDebug FPGA Array Dialog Box
Once you have selected the desired probe, points appear in the Active Probe Data chart and you can read
and write multiple probes at the same time (as shown in the figure below).
The Value column fields are editable for each of the probe points. Clicking the circle shaped icon changes
the value, and clicking the back-arrow resets the value. Fields that have been changed are indicated by red
text. After the probes have been written, the values return to black text.
Figure 17 · Active Probes Tab - Select Active Probe Points
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Probe Insertion (Post-Layout) - SmartFusion2, IGLOO2, and RTG4
Live Probes (SmartFusion2, IGLOO2, and RTG4)
The Live Probes tab shows a table with the probe name and pin type.
Note: SmartFusion2 and IGLOO2 support two probe channels, and RTG4 supports one probe channel.
SmartFusion2 and IGLOO2
Two Probe Channels (ChannelA and ChannelB) are available. Once a Probe Name is selected, it can be
assigned to either ChannelA or ChannelB.
Note: At least one channel must be set; if you intend to use both probes, they must be set at the same time.
Note: The Active Probes READ/WRITE will overwrite the settings of Live Probe channels (if any).
After the channels have been set, SmartDebug configures the ChannelA and ChannelB IO’s to monitor the
desired probe points. The maximum number of simultaneous probes is two internal signals. There is also a
Filter box to filter through the Probe Names. As you begin typing in the Filter box, the Probe Name table only
shows results for the queried names.
RTG4
One Probe Channel (Probe Read Data Pin) is available for RTG4 for debug. Once a Probe Name is
selected, it can be assigned to the Probe Channel (Probe Read Data Pin).
The Active Probes READ/WRITE will overwrite the settings of Live Probe channels (if any).
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Inspect Device Dialog Box
Device Debug User Interface
Inspect Device Dialog Box
Inspect Device is available as a part of the FlashPro programming tool. Refer to Using Device Debug for
information on how to configure the FlashPro to get access to this feature.
The Inspect Device dialog box enables you to access all the Device Debug features, such as the FlashROM,
Embedded Flash Memory (NVM) and Analog Block. If you have multiple devices and programmers
connected, choose your target device/programmer from the dropdown menu and use the ID code to verify
that you are inspecting the correct device.
View Device Status - Displays the Device Status Report. The Device Status Report is a complete summary
of your device state, analog block test values, user information, factory data and security information. Use
this dialog box to save or print your information for future reference.
View Analog Block Configuration - Opens the Analog Block Configuration dialog box. Enables you to view
the channel configuration for your analog block and compare the channel configuration with any other
analog block file.
View Flash Memory Content - Opens the Flash Memory dialog box. This dialog box enables you to view
the details for each flash memory block in your device.
View FlashROM Content - Opens the FlashROM data dialog box, enables you to view a list of the physical
blocks in your FlashROM and the client partitions in FlashROM configuration files.
Figure 18 · Inspect Device Dialog Box
Device Status Report
This dialog box displays the Device Information report. The Device Information report is a complete
summary of your device state, analog block test values, user information, factory serial number and security
information. Use this dialog box to save or print your information for future reference. See the Interpreting
the Device Status Report topic for information on the report contents.
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Figure 19 · Device Status Report
Analog Block Configuration Dialog Box (SmartFusion and Fusion
Only)
Enables you to:
•
View the channel configuration on your analog system, identify if/how the channels are configured.
•
Compare with the design configuration from the Analog System Builder for Fusion and SmartDesign
MSS Configurator for SmartFusion
The values displayed for each channel vary depending on the device family and channel you select; the
Channel configuration register read from the ACM is shown for each analog channel. Individual, decoded bit
fields of the register are listed immediately beneath (as described in Fusion and SmartFusion handbook).
The dialog box may display the following values:
Fusion Device
40
•
Analog MUX select
•
Internal chip T monitor
SmartDebug for Software v11.6
Analog Block Configuration Dialog Box (SmartFusion and Fusion Only)
•
Scaling factor control
•
Current monitor switch
•
Current monitor drive control
•
Direct analog input switch
•
Pad polarity - G, T, V, C pad polarity, positive or negative
•
Select low/high drive
•
Prescaler op amp mode
SmartFusion Device
•
Gain select
•
Channel state
•
Direct Input state
•
Current Monitor state
•
Current monitor strobe state
•
Comparator state
•
Hysteresis select
•
Analog MUX select
•
DAC input select
•
Temperature monitor state
•
Temperature monitor strobe state
•
Vref switch state
To use the compare feature, select the Compare with checkbox. If the loaded PDB file contains Analog
Block configuration information the comparison appear automatically.
To use a specific Project File, click Browse and navigate to the Analog System Builder directory for for
Fusion or SmartDesign for SmartFusion. In a typical IDE project, this directory is located at:
•
Fusion - <project_root>/smartgen/<analog_block_core_name>
•
SmartFusion - <project root>/component/work/<SmartDesign project>/MSS_ACE_0
After specifying the compare directory the differences (if any) are indicated in red on a channel by channel
basis, as shown in the figure below.
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Figure 20 · Analog Block Configuration Dialog Box for a Fusion Device (Differences in Red)
Embedded Flash Memory (NVM) Content
The NVM content dialog is divided into two sections. The top section shows the data that is retrieved from
the PDB that you specified. The bottom section shows the data that is retrieved from the actual device. The
View Flash Memory Content diagnostic enables you to:
•
View content of Flash Memory pages (as shown in the figure below)
•
Compare device content with original design content (requires a PDB that contains your EFC data)
•
Check page status and identify if a page is corrupted or if the write count limit has exceeded the 10year retention threshold
Fusion Devices: Choose your block from the From block dropdown list This action populates the Select
dropdown list with the names of the clients in the selected block that is configured in the Flash Memory
System Builder.
SmartFusion Devices: Block selection is unused and unavailable.
Choose a client name from the Select dropdown list and click Read from Device to view the values. You
can also view a specific page range by selecting the <Page Range> option in the Select dropdown list and
then specifying the start page and the end page.
You must click Read from device each time you specify a new page range to update the view.
If you do not have your original design programming database (PDB) file, then you can also examine and
retrieve a range of pages. Specify a page range if you wish to examine a specific set of pages.
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Embedded Flash Memory: Browse Retrieved Data
Figure 21 ·
Figure 22 · Flash Memory Dialog Box for a SmartFusion Device (Device Debug)
Embedded Flash Memory: Browse Retrieved Data
The retrieved data table displays the content of the selected client or the page range selection. Corrupted
pages content is displayed in red. Read-only page content, corresponding to clients defined with the Prevent
read option in Flash Memory System Builder, is displayed on gray background. If content cannot be read
(e.g. pages are read-protected, but security has been erased), it is displayed as XX. The mouse tooltip
summarizes abnormal content status (as shown in the figure below).
The corresponding page number and address (relative to the current block) are displayed in the left column.
The client size specified in the Flash Memory System Builder is shown at the top of the content table.
In the Retrieved Data View you can enter an Address value (such as 0010) in the Go to Address field and
click the corresponding button to go directly to that address.
Click View Detailed Status for a detailed report on the page range you have selected.
For example, if you want to view a report on pages 1-3, set the Start Page to 1, End Page to 3 and click
Read from Device, then click View Detailed Status; the figure below is an example of the data for a
specific page range.
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Figure 23 · Flash Memory Details Dialog Box (Device Debug)
Figure 24 · Flash Memory Browse Retrieved Data
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Embedded Flash Memory: Compare Memory Client
Embedded Flash Memory: Compare Memory Client
After you retrieve the data from the device, the Compare Client Content button enables you to compare the
content of the selected client from the device with the original programming database (PDB) file. The
differences are shown in the Compare Memory Client dialog (as shown in the figure below).
Note: This option is not available when you select to retrieve the data based on a page range.
Figure 25 · Compare Memory Client Dialog Box
FlashROM Content Dialog Box
Enables you to view the physical blocks in your FlashROM and the client partitions specified in the original
design content (requires a PDB that contains your UFC data). If the project’s PDB does not contain UFC
data, only the physical blocks are displayed.
Scroll through the table to view the Words and Pages for your physical blocks.
The Client Partitions section lists the names and configuration details of the clients set up in the FlashROM
Builder. It automatically finds all mismatched client regions. To view the differences between a client and the
device content, select a region row in the Client Partitions table. This action will highlight the corresponding
device content in the Physical Blocks table. The mismatch details are displayed below the Client Partitions
table.
To copy to clipboard the content of the Physical Blocks table, select one or more cells in the table and type
Ctrl+C.
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Figure 26 · FlashROM Content Dialog Box
Device Debug Tcl Commands
The following table lists the Tcl commands related to Device Debug. Click the command to view more
information.
Table 7 · Device Debug Tcl Commands
Command
Action
Type
check_flash_memory
Performs diagnostics of the page status and Embedded
data information
Flash
Memory
(NVM)
compare_analog_config
Compares the content of the analog block
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Analog Block
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Device Debug Tcl Commands
Command
Action
Type
configurations in your design against the
actual values in the device.
compare_flashrom_client
Compares the content of the FlashROM
configurations in your design against the
actual values in the selected device.
FlashROM
compare_memory_client
Compares the memory
client in a specific device
and block
Embedded
Flash
Memory
(NVM)
read_analog_block_config
Reads each channel
Analog Block
configuration on your
analog system, enabling
you to identify if/how each
channel is configured.
read_device_status
Displays a summary of the selected device
read_flashrom
Reads the content of the FlashROM from
the selected device
FlashROM
read_flash_memory
Reads information from the NVM modules
(page status and page data)
Embedded
Flash
Memory
(NVM)
read_id_code
Reads IDCode from the device without
masking any IDCode fields
recover_flash_memory
Removes ECC2 errors due to memory
corruption by reprogramming specified flash
memory (NVM) pages and initializing all
pages to zeros.
sample_analog_channel
Samples analog channel; enables you to
debug ADC conversion of the preconfigured
analog channel (you must provide ADC
conversion parameters )
set_debug_device
Identifies the device you intend to debug.
set_debug_programmer
Identifies the programmer you want to use
for debugging (if you have more than one).
SmartDebug for Software v11.6
Embedded
Flash
Memory
(NVM)
47
NOTE: Links and cross-references in this PDF file may point to external files and generate an error
when clicked. View the online help included with software to enable all linked content.
Product Support
The Microsemi SoC Products Group backs its products with various support services including a Customer
Technical Support Center and Non-Technical Customer Service. This appendix contains information about
contacting the SoC Products Group and using these support services.
Contacting the Customer Technical Support Center
Microsemi staffs its Customer Technical Support Center with highly skilled engineers who can help answer
your hardware, software, and design questions. The Customer Technical Support Center spends a great
deal of time creating application notes and answers to FAQs. So, before you contact us, please visit our
online resources. It is very likely we have already answered your questions.
Technical Support
Microsemi customers can receive technical support on Microsemi SoC products by calling Technical
Support Hotline anytime Monday through Friday. Customers also have the option to interactively submit and
track cases online at My Cases or submit questions through email anytime during the week.
Web: www.actel.com/mycases
Phone (North America): 1.800.262.1060
Phone (International): +1 650.318.4460
Email: [email protected]
ITAR Technical Support
Microsemi customers can receive ITAR technical support on Microsemi SoC products by calling ITAR
Technical Support Hotline: Monday through Friday, from 9 AM to 6 PM Pacific Time. Customers also have
the option to interactively submit and track cases online at My Cases or submit questions through email
anytime during the week.
Web: www.actel.com/mycases
Phone (North America): 1.888.988.ITAR
Phone (International): +1 650.318.4900
Email: [email protected]
Non-Technical Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
Microsemi’s customer service representatives are available Monday through Friday, from 8 AM to 5 PM
Pacific Time, to answer non-technical questions.
Phone: +1 650.318.2470
SmartDebug for Software v11.6
49
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for communications, defense and security, aerospace, and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs, and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
approximately 3,400 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the
entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly
or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
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5-02-00638-0/07.15
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