STMicroelectronics L6382D5 Datasheet
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L6382D5
Power management unit for microcontrolled ballast
Features
■
■
■
■
■
■
■
■
■
Integrated high-voltage start-up
4 drivers for PFC, half-bridge & pre-heating
MOSFETs
Fully integrated power management for all operating modes
5V microcontroller compatible
Internal two point V
CC regulator
Over-current protection with digital output signal
Cross-conduction protection (interlocking)
Under voltage lock-out
Integrated bootstrap diode
Applications
■
Dimmable / non-dimmable ballast
SO-20
Description
The L6382D5 is suitable for microcontrolled electronic ballasts embedding a PFC stage and a half-bridge stage. The L6382D5 includes 4
MOSFET driving stages (for the PFC, for the half bridge, for the preheating MOSFET) plus a power management unit (PMU) featuring also a reference able to supply the microcontroller in any condition.
Besides increasing the application efficiency, the
L6382D5 reduces the bill of materials because different tasks (regarding drivers and power management) are performed by a single IC, which improves the application reliability.
Figure 1.
Block diagram
March 2007 Rev 3 1/21
www.st.com
21
Contents
Contents
L6382D5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
OPERATING Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Internal logic, over current protection (OCP) and interlocking function . . 16
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2/21
L6382D5 Device description
Designed in High-voltage BCD Off-line technology, the L6382D5 is provided with 4 inputs pin and a high voltage start-up generator conceived for applications managed by a microcontroller. It allows the designer to use the same ballast circuit for different lamp wattage/type by simply changing the
µC software.
The digital input pins - able to receive signals up to 400KHz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D5 embeds one driver for the PFC pre-regulator stage, two drivers for the ballast half-bridge stage (High
Voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated filaments in dimmable applications.
A precise reference voltage (+5V ±2%) able to provide up to 30mA is available to supply the
µC in operating mode. Instead, during start-up and save mode the current available at V
REF is up to 10mA and it is provided by the internal high voltage start-up generator.
The chip has been conceived with advanced power management logic to minimize power losses and increase the application reliability.
In the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode.
The L6382D5 integrates also a function that regulates the IC supply voltage (without the need of any external charge pump) and optimizes the current consumption.
Figure 2.
Typical system block diagram
3/21
Pin settings
Figure 3.
Pin connection (top view)
L6382D5
4/21
Table 1. Pin description
Name
1
Pin N°
PFI
Description
Digital input signal to control the PFC gate driver. This pin has to be connected to a 5V CMOS compatible signal.
2
3
4
5
6
7
8
LSI
HSI
HEI
PFG
Digital input signal to control the half-bridge low side driver. This pin has to be connected to a 5V CMOS compatible signal.
Digital input signal to control the half-bridge high side driver. This pin has to be connected to a 5V CMOS compatible signal.
Digital input signal to control the HEG output. This pin has to be connected to a
5V CMOS compatible signal.
PFC Driver Output. This pin must be connected to the PFC power MOSFET gate. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current. An internal 10K
Ω resistor toward ground avoids spurious and undesired MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 250mA sink.
N.C.
Not connected
TPR
Input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the Vcc.
GND
Chip ground. Current return for both the low-side gate-drive currents and the bias current of the IC. All of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return.
L6382D5 Pin settings
Table 1. Pin description (continued)
Name
9
Pin N°
LSG
Description
Low Side Driver Output. This pin must be connected to the gate of the halfbridge low side power MOSFET. A resistor connected between this pin and the power MOS gate can be used to reduce the peak current.
An internal 20K
Ω resistor toward ground avoids spurious and undesired
MOSFET turn-on.
The totem pole output stage is able to drive power with a peak current of
120mA source and 120mA sink.
10
11
12
13
14
15
16
17
18
19
20
Vcc
BOOT
HSG
Supply Voltage for the signal part of the IC and for the drivers.
High-side gate-drive floating supply Voltage. The bootstrap capacitor connected between this pin and pin 13 (OUT) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. This patented structure normally replaces the external diode.
High Side Driver Output. This pin must be connected to the gate of the half bridge high side power MOSFET . A resistor connected between this pin and the power MOS gate can be used to reduce the peak current.
An internal 20K
Ω resistor toward OUT pin avoids spurious and undesired
MOSFET turn-on
The totem pole output stage is able to drive the power MOS with a peak current of 120mA source and 120mA sink.
OUT
High-side gate-drive floating ground. Current return for the high-side gate-drive current. Layout carefully the connection of this pin to avoid too large spikes below ground.
N.C.
Not connected
HVSU
High-voltage start-up. The current flowing into this pin charges the capacitor connected between pin Vcc and GND to start up the IC. Whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. When the chip works in operating mode the generator is shut down and it is re-enabled when the Vcc voltage falls below the UVLO threshold.
According to the required V
REF
pin current, this pin can be connected to the rectified mains voltage either directly or through a resistor.
N.C.
HEG
CSO
CSI
VREF
High-voltage spacer. The pin is not connected internally to isolate the highvoltage pin and comply with safety regulations (creepage distance) on the
PCB.
Output for the HEI block; this driver can be used to drive the MOS employed in isolated filaments preheating. An internal 20K
Ω resistor toward ground avoids spurious and undesired MOSFET turn-on.
Output of current sense comparator, compatible with 5V CMOS logic; during
operating mode, the pin is forced low whereas whenever the OC comparator is triggered (CSI> 0.55 typ.) the pin latches high.
Input of current sense comparator, it is enabled only during operating mode; when the pin voltage exceeds the internal threshold, the CSO pin is forced high and the half bridge drivers are disabled. It exits from this condition by either cycling the Vcc below the UVLO or with LGI=HGI=low simultaneously.
Voltage reference. During operating mode an internal generator provides an accurate voltage reference that can be used to supply up to 30mA to an external circuit. A small film capacitor (0.22
µF min.), connected between this pin and GND is recommended to ensure the stability of the generator and to prevent noise from affecting the reference.
5/21
Maximum ratings L6382D5
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol Pin Parameter
10 IC supply voltage (ICC = 20mA) V
CC
V
HVSU
V
BOOT
V
OUT
I
TPR(RMS)
I
TPR(PK)
V
TPR
15 High voltage start-up generator voltage range
11 Floating supply voltage
13 Floating ground voltage
7 Maximum TPR RMS current
7 Maximum TPR peak current
Tstg
Tj
7
Maximum TPR voltage
(1)
19 CSI input voltage
1, 2,
3, 4
Logic input voltage
9, 12,
17
Operating frequency
5 Operating frequency
Storage Temperature
Ambient Temperature operating range
1.
Excluding operating mode
Value
Self-limited
-0.3 to 600
-1 to V
HVSU
+V
CC
-1 to 600
±200
±600
14
-0.3 to 7
-0.3 to 7
Unit
V
V
V mA mA
V
V
V
15 to 400
15 to 600
-40 to +150
-40 to +125
KHz
KHz
°C
°C
Table 3. Thermal data
Symbol
R thJA
Parameter
Maximum thermal resistance junction-ambient
Value
120
Unit
°C/W
6/21
L6382D5 Electrical characteristics
Table 4. Electrical characteristcs (T
J
= 25°C, V
CC unless otherwise specified)
= 13V, C
DRIVER
= 1nF
Symbol Pin Parameter Test Min Typ
Supply voltage
V ccON
V ccOFF
V ccSM
VSMhys
V
REF(OFF)
IvccON
IvccSM
10
10
10
10
10
10
10
Turn-on voltage
Turn-off voltage
Save mode voltage
Save mode hysteresys
Reference turn-off
Start-up current
Save Mode current consumption
(1)
190
Max Unit
13
8.5
14
9
15
9.5
12.75
13.8
14.85
V
V
V
0.12
0.16
6 6.4
0.2
6.8
160
220
250
V
V
µA
µA
µA
Ivcc 10
Vz 10
High voltage start-up
Quiescent current in operating mode
V
CC
=13V;
LGI = HGI = high; no load on VREF.
Internal Zener
IMSS
ILSS
15
15
Maximum current
V
HVSU
> 50V
Leakage current off state
V
HVSU
= 600V
Two point regulator (TPR) protection
TPR
TPR
TPR st
(ON)
(OFF)
10
10
10
7
7
7
Vcc Protection level
Operating mode
Vcc Turn-on level
Operating mode; after the first falling edge on
LSG
Vcc Turn-off level
Operating mode; after the first falling edge on
LSG
Output voltage on state
Forward voltage drop Diode
I
TPR
= 200mA
@ 600mA forward current.
Leakage current off state
V
TPR
= 13V
16.5
20
12.5
17
13
2.1
18
40
14.0
14.5
15.0
13.5
12.45
12.95
13.48
V
2
2.3
5 mA
V mA
µA
V
V
V
V
µA
7/21
Electrical characteristics L6382D5
Table 4. Electrical characteristcs (T
J
= 25°C, V
CC unless otherwise specified)
(continued)
= 13V, C
DRIVER
= 1nF
Symbol Pin Parameter Test Min Typ
LSG, HEG & PFG drivers
V
V
OH(LS
OL(LS)
)
5, 9
17
5, 9
17
HIGH Output
Voltage
LOW Output
Voltage
Source Current
Capability
Sink Current
Capability
ILSG = IPFG = 10mA
IHEG = 2.5mA
ILSG = IPFG = 10mA
IHEG = 2.5mA
LSG and PFG
HEG
LSG
HEG
PFG
T
T
RISE
FALL
17
5,
9
17
5
9 Rise time
Fall time
Cload = 1nF
Cload = 1nF
T
DELAY
R
B
LSG; high to low and low to high
Propagation delay
(input to output)
HEG; high to low and low to high
PFG; high to low
PFG; low to high
LSG
Pull down Resistor HEG
PFG
HSG driver (voltages referred to OUT)
V
V
OH(HS)
T
OL(HS)
RISE
12
12
12
12
12
HIGH Output
Voltage
LOW Output
Voltage
Sink Current
Capability
Source Current
Capability
Rise time
IHSG = 10 mA
IHSG = 10 mA
Cload = 1nF
120
50
120
70
250
120
120
12.5
0.5
20
50
10
12.5
0.5
115
80
300
60
60
110
40
Max Unit
300
V
V mA mA mA ns ns ns
200
250
200 ns ns ns
K
Ω
K
Ω
K
Ω
V
V mA mA ns
8/21
L6382D5 Electrical characteristics
Table 4. Electrical characteristcs (T
J
= 25°C, V
CC unless otherwise specified)
(continued)
= 13V, C
DRIVER
= 1nF
Symbol Pin Parameter Test Min Typ
T
FALL
12 Fall time Cload = 1nF 75
T
DELAY
12
Propagation delay
(LGI to LSG) high to low and low to high
R
B
12 Pull down Resistor to OUT 20
High-side floating gate-driver supply
Max Unit
ns
300 ns
K
Ω
I
I
LKBOOT
R
LKOUT
DS(on)
11
13
V
BOOT
pin leakage current
V
BOOT
= 580V
OUT pin leakage current
Synchronous bootstrap diode onresistance
Forward Voltage
Drop
V
V
OUT
LVG
= 562V
= HIGH at 10 mA forward current
Forward Current at 5V forward voltage drop
V
REF
V
REF
20
20
20
20
20
Reference voltage 15mA load.
Load regulation
Voltage change
IRef = -3 to +30 mA
15mA load; Vcc = 9V to
15V
V
REF
latched protection
V
REF
Clamp
@3mA
V
CC
from 0 to V
CCON during start-up; Vcc from
V
REF(OFF)
to 0 during shut-down; V
REF
< 2V
I
REF
20
Current Drive
Capability
Save mode
Overcurrent buffer stage
V
CSI
I
CSI
19
19
Comparator Level
Input Bias Current
Propagation delay CSO turn off to LSG low
20
4.9
-20
-3
-3
150
2.4
5
1.2
5
5
5.1
2
15
3.2
1.8
+30
+10
0.52
0.54
0.56
500
200
µA
µA
Ω
V mA
V mV mV
V
V mA mA
V nA ns
9/21
Electrical characteristics L6382D5
Table 4. Electrical characteristcs (T
J
= 25°C, V
CC unless otherwise specified)
(continued)
= 13V, C
DRIVER
= 1nF
Symbol Pin Parameter Test Min Typ
18 High output voltage I
CSO
= 200
µA
V
REF
-
0.5V
18 Low output voltage I
CSO
= -150
µA
DIM
T
ED
Normal Mode Time
Out
Vref enabling drivers
Time enabling drivers
65 100
4.6
10
Logic input
Max Unit
0.5
135
V
µs
V
µs
1 to 4
Low Level Logic
Input Voltage
1.3
V
1 to 4
High Level Logic
Input Voltage
3.7
V
LGI Pull down resistor 100
K
Ω
1.
Specification over the -40°C to +125°C junction temperature range are ensured by design, characterization and statistical correlation.
10/21
L6382D5 Application information
The L6382D5 has two stable states (save mode and operating mode) and two additional states that manage the Start-up and fault conditions: the Over Current Protection is a parallel asynchronous process enabled when in operating mode
Following paragraphs will describe each mode and the condition necessary to shift between them.
Figure 4.
State diagram
START-UP
V
CC
<V
REF(OFF)
V
CC
>V
CC(ON)
V
CC
<V
REF(OFF)
SAVE MODE
V
REF
>4.6V
T
DE
&
>10
µs
OPERATING
MODE
LGI low for more than 100
µs
V
CC
<V
CC(ON)
SHUT DOWN
V
CC
< V
CC(OFF) or
V
REF
<3.2V
With reference to the timing diagram of figure 6, when power is first applied to the converter, the voltage on the bulk capacitor (Vin) builds up and the HV generator is enabled to operate drawing about 10mA. This current, diminished by the IC consumption (less than 150µA), charges the bypass capacitor connected between pin Vcc and ground and makes its voltage rise almost linear.
During this phase, all IC's functions are disabled except for:
● the current sinking circuit on V
REF
pin that maintains low the voltage by keeping disabled the microcontroller connected to this pin;
● the High-Voltage Start-Up (HVSU) that is ON (conductive) to charge the external capacitor on pin Vcc.
As the Vcc voltage reaches the start-up threshold (14V typ.) the chip starts operating and the HV generator is switched off.
11/21
Application information
Summarizing:
– The high-voltage start-up generator is active;
– V
REF
is disabled with additional sinking circuit on pin V
REF enabled;
– TPR is disabled;
– OCP is disabled;
– The drivers are disabled.
L6382D5
This mode is entered after the V
CC
voltage reaches the turn-on threshold; the VREF is enabled in low current source mode to supply the
µC connected to it, whose wake-up required current must be less than 10mA: if no switching activity is detected at LGI input, the high voltage start-up generator cycles ON-OFF keeping the Vcc voltage between VccON and V ccSM
.
Summarizing:
– The high-voltage start-up generator is cycling;
– V
REF
is enabled in low source current capability (I
REF
≤ 10mA);
– TPR circuit is disabled;
– OCP is disabled;
– The drivers are disabled.
If the V
CC
voltage falls below the V
REF(OFF)
threshold, the device enters the start-up mode.
After 10
µs in save mode and only if the votage at V
REF
is higher than 4.6V, on the falling edge on the HGI input, the driver are enabled as well as all the IC's functions; this is the mode correspondent to the proper lamp behaviour.
Summarizing:
– HVSU is OFF
– V
REF
is enabled in high source current mode (I
REF
< 30mA)
– TPR circuit is enabled
– OCP is enabled
– The drivers are enabled
If there is no switching activity on LGI for more than 100
µs, the IC returns in save mode.
This state permits to manage the fault conditions in operating mode and it is entered by the occurrence on one of the following conditions:
1. V
CC
< V ccOff
(Under Voltage fault on Supply),
2. V
REF
< 3.2V (Under Voltage fault on V
REF
)
12/21
L6382D5 Application information
In this state the functions are:
– The HVSU generator is ON
– V
REF
is enabled in low source current mode (I
REF
< 10mA)
– TPR is disabled
– OCP is disabled
– The drivers are disabled
In this state if Vcc reaches V
V
CC
< V
REF(OFF) ccOn
, the device enters the save mode otherwise, if
, also the
µC is turned off and the device will be ready to execute the Startup sequence.
Figure 5.
Timing Sequences, TPR behavior
13/21
Application information
Figure 6.
Timing Sequences, save mode and operating mode
L6382D5
14/21
L6382D5 Block description
6.2
●
●
●
µPUVLO ( Power Under Voltage Lock Out): This block controls the power management of the L6382D5 ensuring the right current consumption in each operating state, the correct V
REF
current capability, the driver enabling and the high-voltage startup generator switching.
During Start-up the device sinks the current necessary to charge the external capacitor on pin V
CC
from the high voltage bus; in this state the other IC's functions are disabled and the current consumption of the whole IC is less than 150
µA.
When the voltage on V
CC
pin reaches VccON, the IC enters the save mode where the
µPUVLO block controls Vcc between VccON and VccSM by switching ON/OFF the high voltage start-up generator.
HVSU (High-Voltage Start-Up generator): a 600V internal MOS transistor structure controls the Vcc supply voltage during START UP and SAVE MODE conditions and it reduces the power losses during operating MODE by switching off the MOS transistor.
The transistor has a source current capability of up to 30mA.
TPR (Two Point Regulator) & PWS: during operating mode, the TPR block controls the PSW switch in order to regulate the IC supply voltage (V
CC
) to a value in the range between TPR(ON) and TPR(OFF) by switching ON and OFF the PSW transistor.
– Vcc > TPRst: the PSW is switched ON immediately;
– TPR(ON) < Vcc < TPRst: the PSW is switched ON at the following falling edge of
LGI;
– Vcc < TPR(OFF): the PSW is switched OFF at the following falling edge on LGI.
When the PSW switch is OFF, the diodes build a charge pump structure so that, connecting the TPR pin to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip without adding any further external component. The diodes and the switch are designed to withstand a peak current of at least 200mA
RMS
.
5V reference voltage
This block is used to supply the microcontroller; this source is able to supply 10mA in save mode and 30mA in normal mode; moreover, during start-up when V
REF
is not yet available, an additional circuit is ensures that, even sinking 3mA, the pin voltage doesn't exceed 1.2V.
The reference is available until Vcc is above V
REF(OFF) additional sinking circuit is enabled again.
; below that it turns off and the
15/21
Block description L6382D5
6.3 Drivers
●
●
●
●
●
LSD (Low Side Driver): it consists of a level shifter from 5V logic signal (LSI) to Vcc
MOS driving level; conceived for the half-bridge low-side power MOS, it is able to source and sink 120mA (min).
HSD (Level Shifter and High Side Driver): it consists of a level shifter from 5V logic signal (HSI) to the high side gate driver input up to 600V. Conceived for the half-bridge high-side power MOS, the HSD is able to source and sink 120mA.
PFD (Power Factor Driver): it consists of a level shifter from 5V logic signal (PFI) to Vcc
MOS driving level: the driver is able to source 120mA from V
CC
to PFG (turn-on) and to sink 250mA to GND (turn-off); it is suitable to drive the MOS of the PFC pre-regulator stage.
HED (Heat Driver): it consists of a level shifter from 5V logic signal (HEI) to Vcc MOS driving level; the driver is able to source 30mA from Vcc to HEG and to sink 75mA to
GND and it is suitable for the filament heating when they are supplied by independent winding.
Bootstrap Circuit: it generates the supply voltage for the high side Driver (HSD). This circuit sources current from V
CC
to PIN HSB when LSG in ON. A patented integrated bootstrap section replaces an external bootstrap diode. This section together with a bootstrap capacitor provides the bootstrap voltage to drive the high side power
MOSFET. This function is achieved using a high voltage DMOS driver which is driven synchronously with the low side external power MOSFET. For a safe operation, current flow between BOOT pin and Vcc is always inhibited, even though ZVS operation may not be ensured.
6.4 Internal logic, over current protection (OCP) and interlocking function
The DIM (Digital Input Monitor) block manages the input signals delivered to the drivers ensuring that they are low during the described start-up procedure; the DIM block controls the L6382D5 behaviour during both save and operating modes.
When the voltage on pin CSI overcomes the internal reference of 0.54V (typ.) the block latches the fault condition: in this state the OCP block forces low both HSG and LSG signals while CSO will be forced high. This condition remains latched until LSI and HSI are simultaneously low and CSI is below 0.54V.
This function is suitable to implement an over current protection or hard-switching detection by using an external sense resistor.
As the voltage on pin CSI can go negative, the current must be limited below 2mA by external components.
Another feature of the DIM block is the internal interlocking that avoids cross-conduction in the half-bridge FET's: if by chance both HSI and LSI input's are brought high at the same time, then LSG and HSG are forced low as long as this critical condition persists.
16/21
L6382D5
7 Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
17/21
Package mechanical data
Table 5. SO-20 Mechanical data mm.
Dim.
Min Typ
A 2.35
A1 0.10
B 0.33
C 0.23
D
(1)
Max Min
E 7.40 e 1.27
H 10.0 h 0.25
L 0.40 k 0° (min.), 8° (max.)
Figure 7.
Package dimensions
L6382D5 inch
Typ Max
0.104
0.012
0.200
0.013
0.299
0.050
0.419
0.030
0.050
18/21
L6382D5
Table 6. Order codes
Part number
L6382D5
L6382D5TR
Package
SO-20
SO-20
Order codes
Packaging
Tube
Tape & Reel
19/21
Revision history
Table 7. Revision history
Date Revision
15-Jan-2004 1
17-May-2006
22-Mar-2007
2
3
First Issue
Document reformatted
Typo on
Changes
L6382D5
20/21
L6382D5
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