STMicroelectronics STR755FR2 Datasheet
Reklama
Reklama
STR750Fxx STR751Fxx
STR752Fxx STR755Fxx
ARM7TDMI-S™ 32-bit MCU with Flash, SMI, 3 std 16-bit timers,
PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
Features
■
■
■
■
■
■
Core
– ARM7TDMI-S 32-bit RISC CPU
– 54 DMIPS @ 60 MHz
Memories
– Up to 256 KB Flash program memory (10k
W/E cycles, retention 20 yrs @ 85°C)
– 16 KB Read-While-Write Flash for data
(100k W/E cycles, retention 20 yrs@ 85°C)
– Flash Data Readout and Write Protection
– 16KBytes embedded high speed SRAM
– Memory mapped interface (SMI) to ext.
Serial Flash (64 MB) w. boot capability
Clock, reset and supply management
– Single supply 3.3V ±10% or 5V ±10%
– Embedded 1.8V Voltage Regulators
– Int. RC for fast start-up and backup clock
– Up to 60 MHz operation using internal PLL with 4 or 8 MHz crystal/ceramic osc.
– Smart Low Power Modes: SLOW, WFI,
STOP and STANDBY with backup registers
– Real-time Clock, driven by low power internal RC or 32.768 kHz dedicated osc, for clock-calendar and Auto Wake-up
Nested interrupt controller
– Fast interrupt handling with 32 vectors
– 16 IRQ priorities, 2 maskable FIQ sources
– 16 external interrupt / wake-up lines
DMA
– 4-channel DMA controller
– Circular buffer management
– Support for UART, SSP, Timers, ADC
6 Timers
– 16-bit watchdog timer (WDG)
– 16-bit timer for system timebase functions
– 3 synchronizable timers each with up to 2 input captures and 2 output compare/PWMs.
LQFP64 10x10 mm LQFP100 14 x 14 mm
LFBGA64
8 x 8 x 1.7 mm
LFBGA100
10 x 10 x 1.7 mm
■
■
■
– 16-bit 6-ch. synchronizable PWM timer
– Dead time generation, edge/center-aligned waveforms and emergency stop
– Ideal for induction/brushless DC motors
8 Communications interfaces
– 1 I
2
C interface
– 3 HiSpeed UARTs w. Modem/LIN capability
– 2 SSP interfaces (SPI or SSI) up to 16 Mb/s
– 1 CAN interface (2.0B Active)
– 1 USB full-speed 12 Mb/s interface with 8 configurable endpoint sizes
10-bit A/D converter
– 16/11 chan. with prog. Scan Mode & FIFO
– Programmable Analog Watchdog feature
– Conversion time: min. 3.75 µs
– Start conversion can be triggered by timers
Up to 72/38 I/O ports
– 72/38 GPIOs with High Sink capabilities
– Atomic bit SET and RES operations
Table 1.
Reference
Device summary
Part number
STR750Fxx STR750FV0, STR750FV1, STR750FV2
STR751Fxx STR751FR0, STR751FR1, STR751FR2
STR752Fxx STR752FR0, STR752FR1, STR752FR2
STR755Fxx
STR755FR0, STR755FR1, STR755FR2
STR755FV0, STR755FV1, STR755FV2
February 2009 Rev 5 1/84
www.st.com
1
Contents
Contents
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
I/O characteristics versus the various power schemes (3.3V or 5.0V) . 29
Current consumption measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 35
Embedded voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Contents
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
TB and TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 80
3/84
Description
1 Description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
●
●
●
●
The STR750 family of 32-bit microcontrollers combines the industry-standard ARM7TDMI®
32-bit RISC core, featuring high performance, very low power, and very dense code, with a comprehensive set of peripherals and ST's latest 0.18µ embedded Flash technology. The
STR750 family comprises a range of devices integrating a common set of peripherals as well as USB, CAN and some key innovations like clock failure detection and an advanced motor control timer. It supports both 3.3V and 5V, and it is also available in an extended temperature range (-40 to +105°C). This makes it a genuine general purpose microcontroller family, suitable for a wide range of applications:
Appliances, brushless motor drives
USB peripherals, UPS, alarm systems
Programmable logic controllers, circuit breakers, inverters
Medical and portable equipment
Table 2.
Device overview
Features
Flash - Bank 0 (bytes)
Flash - Bank 1 (bytes)
RAM (bytes)
Operating
Temperature.
Common Peripherals
USB/CAN peripherals
Operating Voltage
Packages (x)
STR755FR0
STR755FR1
STR755FR2
STR751FR0/
STR751FR1/
STR751FR2
STR752FR0/
STR752FR1/
STR752FR2
STR755FV0
STR755FV1/
STR755FV2
STR750FV0/
STR750FV1/
STR750FV2
64K/128K/256K
16K RWW
16K
Ambient temp.:-40 to +85°C / -40 to +105°C (see
)
Junction temp. -40 to + 125 °C (see
3 UARTs, 2 SSPs, 1 I2C, 3 timers 1 PWM timer,
38 I/Os 13 Wake-up lines, 11 A/D Channels
3 UARTs, 2 SSPs, 1 I
2
C,
3 timers 1 PWM timer, 72
I/Os 15 Wake-up lines, 16 A/D Channels
None USB CAN None USB+CAN
3.3V or 5V 3.3V
T=LQFP64 10x10, H=LFBGA64
3.3V or 5V
T=LQFP100 14x14, H=LFBGA100
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
3 Introduction
Introduction
This Datasheet contains the description of the STR750F family features, pinout, Electrical
Characteristics, Mechanical Data and Ordering information.
For complete information on the Microcontroller memory, registers and peripherals. Please refer to the STR750F Reference Manual.
For information on the ARM7TDMI-S core please refer to the ARM7TDMI-S Technical
Reference Manual available from Arm Ltd.
For information on programming, erasing and protection of the internal Flash memory please refer to the STR7 Flash Programming Reference Manual
For information on third-party development tools, please refer to the http://www.st.com/mcu website.
The STR750F family includes devices in 2 package sizes: 64-pin and 100-pin. Both types have the following common features:
ARM7TDMI-S
TM
core with embedded Flash & RAM
STR750F family has an embedded ARM core and is therefore compatible with all ARM tools and software. It combines the high performance ARM7TDMI-S
TM
CPU with an extensive range of peripheral functions and enhanced I/O capabilities. All devices have on-chip highspeed single voltage FLASH memory and high-speed RAM.
shows the general block diagram of the device family.
Embedded Flash memory
Up to 256 KBytes of embedded Flash is available in Bank 0 for storing programs and data.
An additional Bank 1 provides 16 Kbytes of RWW (Read While Write) memory allowing it to be erased/programmed on-the-fly. This partitioning feature is ideal for storing application parameters.
●
When configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states for sequential accesses and 1 wait state for random access
(maximum 60 MHz).
● When not configured in burst mode, access to Flash memory is performed at CPU clock speed with 0 wait states (maximum 32 MHz)
Embedded SRAM
16 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states.
Enhanced interrupt controller (EIC)
In addition to the standard ARM interrupt controller, the STR750F embeds a nested interrupt controller able to handle up to 32 vectors and 16 priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency.
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Introduction STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Serial memory interface (SMI)
The Serial Memory interface is directly able to access up to 4 serial FLASH devices. It can be used to access data, execute code directly or boot the application from external memory.
The memory is addressed as 4 banks of up to 16 Mbytes each.
Clocks and start-up
After RESET or when exiting from Low Power Mode, the CPU is clocked immediately by an internal RC oscillator (FREEOSC) at a frequency centered around 5 MHz, so the application code can start executing without delay. In parallel, the 4/8 MHz Oscillator is enabled and its stabilization time is monitored using a dedicated counter.
An oscillator failure detection is implemented: when the clock disappears on the XT1 pin, the circuit automatically switches to the FREEOSC oscillator and an interrupt is generated.
In Run mode, the AHB and APB clock speeds can be set at a large number of different frequencies thanks to the PLL and various prescalers: up to 60 MHz for AHB and up to 32
MHz for APB when fetching from Flash (64 MHz and 32 MHz when fetching from SRAM).
In SLOW mode, the AHB clock can be significantly decreased to reduce power consumption.
The built-in Clock Controller also provides the 48 MHz USB clock directly without any extra oscillators or PLL. For instance, starting from the 4 MHz crystal source, it is possible to obtain in parallel 60 MHz for the AHB clock, 48 MHz for the USB clock and 30 MHz for the
APB peripherals.
Boot modes
●
●
●
●
At start-up, boot pins are used to select one of five boot options:
Boot from internal flash
Boot from external serial Flash memory
Boot from internal boot loader
Boot from internal SRAM
Booting from SMI memory allows booting from a serial flash. This way, a specific boot monitor can be implemented. Alternatively, the STR750F can boot from the internal boot loader that implements a boot from UART.
Power supply schemes
You can connect the device in any of the following ways depending on your application.
● Power Scheme 1: Single external 3.3V power source. In this configuration the
V
CORE supply required for the internal logic is generated internally by the main voltage regulator and the V
BACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 3.3V power source.
●
Power Scheme 2: Dual external 3.3V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off by forcing the VREG_DIS pin to high level. V
CORE is provided externally through the V
18 and V
18REG power pins and
V
BACKUP
through the V
18_BKP
pin. This scheme is intended to save power consumption for applications which already provide an 1.8V power supply.
●
Power Scheme 3: Single external 5.0V power source. In this configuration the
V
CORE supply required for the internal logic is generated internally by the main voltage
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Introduction
● regulator and the V
BACKUP supply is generated internally by the low power voltage regulator. This scheme has the advantage of requiring only one 5.0V power source.
Power Scheme 4: Dual external 5.0V and 1.8V power sources. In this configuration, the internal voltage regulators are switched off, by forcing the VREG_DIS pin to high level. V
CORE is provided externally through the V
18 and V
18REG power pins and
V
BACKUP
through the V
18_BKP
pin. This scheme is intended to provide 5V I/O capability.
Caution:
When powered by 5.0V, the USB peripheral cannot operate.
Low power modes
The STR750F supports 5 low power modes, SLOW, PCG, WFI, STOP and STANDBY.
●
SLOW MODE: the system clock speed is reduced. Alternatively, the PLL and the main oscillator can be stopped and the device is driven by a low power clock (f
RTC
). The clock is either an external 32.768 kHz oscillator or the internal low power RC oscillator.
● PCG MODE (Peripheral Clock Gating MODE): When the peripherals are not used, their
APB clocks are gated to optimize the power consumption.
●
●
WFI MODE (Wait For Interrupts): only the CPU clock is stopped, all peripherals continue to work and can wake-up the CPU when IRQs occur.
STOP MODE: all clocks/peripherals are disabled. It is also possible to disable the oscillators and the Main Voltage Regulator (In this case the V
CORE
is entirely powered by V
18_BKP
). This mode is intended to achieve the lowest power consumption with
SRAM and registers contents retained. The system can be woken up by any of the external interrupts / wake-up lines or by the RTC timer which can optionally be kept running. The RTC can be clocked either by the 32.768 kHz Crystal or the Low Power
RC Oscillator.
Alternatively, STOP mode gives flexibility to keep the either main oscillator, or the Flash or the Main Voltage Regulator enabled when a fast start after wake-up is preferred (at the cost of some extra power consumption).
●
STANDBY MODE: This mode (only available in single supply power schemes) is intended to achieve the lowest power consumption even when the temperature is increasing. The digital power supply (V
CORE
) is completely removed (no leakage even at high ambient temperature). SRAM and all register contents are lost. Only the RTC remains powered by V
18_BKP
. The STR750F can be switched back from STANDBY to
RUN mode by a trigger event on the WKP_STDBY pin or an alarm timeout on the RTC counter.
Caution:
It is important to bear in mind that it is forbidden to remove power from the V
DD_IO
power supply in any of the Low Power Modes (even in STANDBY MODE).
DMA
The flexible 4-channel general-purpose DMA is able to manage memory to memory, peripheral to memory and memory to peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.
The DMA can be used with the main peripherals: UART0, SSP0, Motor control PWM timer
(PWM), standard timer TIM0 and ADC.
RTC (real-time clock)
The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a
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Introduction STR750Fxx STR751Fxx STR752Fxx STR755Fxx
periodic interrupt. It is clocked by an external 32.768 kHz oscillator or the internal low power
RC oscillator. The RC has a typical frequency of 300 kHz and can be calibrated.
WDG (watchdog timer)
The watchdog timer is based on a 16-bit downcounter and 8-bit prescaler. It can be used as watchdog to reset the device when a problem occurs, or as free running timer for application time out management.
Timebase timer (TB)
The timebase timer is based on a 16-bit auto-reload counter and not connected to the I/O pins. It can be used for software triggering, or to implement the scheduler of a real-time operating system.
Synchronizable standard timers (TIM2:0)
The three standard timers are based on a 16-bit auto-reload counter and feature up to 2 input captures and 2 output compares (for external triggering or time base / time out management). They can work together with the PWM timer via the Timer Link feature for synchronization or event chaining. In reset state, timer Alternate Function I/Os are connected to the same
I/O ports in both 64-pin and 100-pin devices. To optimize timer functions in 64-pin devices, timer Alternate Function I/Os can be connected, or “remapped”, to other I/O ports as
. This remapping is done by the application via a control register.
Table 3. Standard timer alternate function I/Os
Number of alternate function I/Os
Standard timer functions
TIM 0
TIM 1
TIM 2
Input Capture
Output Compare/PWM
Input Capture
Output Compare/PWM
Input Capture
Output Compare/PWM
100-pin package
2
2
2
2
2
2
64-pin package
Default mapping
1
2
1
1
1
1
Remapped
1
2
2
2
2
1
Any of the standard timers can be used to generate PWM outputs. One timer (TIM0) is mapped to a DMA channel.
Motor control PWM timer (PWM)
The Motor Control PWM Timer (PWM) can be seen as a three-phase PWM multiplexed on 6 channels. The 16-bit PWM generator has full modulation capability (0...100%), edge or centre-aligned patterns and supports dead-time insertion. It has many features in common with the standard TIM timers which has the same architecture and it can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.The PWM timer is mapped to a DMA channel.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Introduction
I²C bus
The I²C bus interface can operate in multi-master and slave mode. It can support standard and fast modes (up to 400KHz).
High speed universal asynch. receiver transmitter (UART)
The three UART interfaces are able to communicate at speeds of up to 2 Mbit/s. They provide hardware management of the CTS and RTS signals and have LIN Master capability.
To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 16 bytes each have been implemented.
One UART can be served by the DMA controller (UART0).
Synchronous serial peripheral (SSP)
The two SSPs are able to communicate up to 8 Mbit/s (SSP1) or up to 16 Mbit/s (SSP0) in standard full duplex 4-pin interface mode as a master device or up to 2.66 Mbit/s as a slave device. To optimize the data transfer between the processor and the peripheral, two FIFOs
(receive/transmit) of 8 x 16 bit words have been implemented. The SSPs support the
Motorola SPI or TI SSI protocols.
One SSP can be served by the DMA controller (SSP0).
Controller area network (CAN)
The CAN is compliant with the specification 2.0 part B (active) with a bit rate up to 1Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Up to 32 message objects are handled through an internal RAM buffer. In LQFP64 devices, CAN and USB cannot be connected simultaneously.
Universal serial bus (USB)
The STR750F embeds a USB device peripheral compatible with the USB Full speed 12Mbs.
The USB interface implements a full speed (12 Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock source is generated from the internal main PLL. V
DD
USB operation.
must be in the range 3.3V±10% for
ADC (analog to digital converter)
The 10-bit Analog to Digital Converter, converts up to 16 external channels (11 channels in
64-pin devices) in single-shot or scan modes. In scan mode, continuous conversion is performed on a selected group of analog inputs. The minimum conversion time is 3.75 µs
(including the sampling time).
The ADC can be served by the DMA controller.
An analog watchdog feature allows you to very precisely monitor the converted voltage of up to four channels. An IRQ is generated when the converted voltage is outside the programmed thresholds.
The events generated by TIM0, TIM2 and PWM timers can be internally connected to the
ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers.
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Introduction STR750Fxx STR751Fxx STR752Fxx STR755Fxx
GPIOs (general purpose input/output)
Each of the 72 GPIO pins (38 GPIOs in 64-pin devices) can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as
Peripheral Alternate Function. Port 1.15 is an exception, it can be used as general-purpose input only or wake-up from STANDBY mode (WKP_STDBY). Most of the GPIO pins are shared with digital or analog alternate functions.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Introduction
Figure 1.
STR750 block diagram
BOOT1,
BOOT0
as AF
TEST
NJTRST
JTDI
JTCK
JTMS
JTDO as AF
ARM7TDMI-S
CPU
60MHz
AHB
JTAG & ICE-RT
GP DMA
4 streams
AHB
Arbiter
SCLK, MOSI
MISO as AF
4 CS as AF
SERIAL MEMORY
INTERFACE
APB
BRIDGE
HRESETN
PRESETN
SRAM 16KB
FLASH 256KB
+16KB (RWW)
NESTED
INTERRUPT CTL
V
DD_IO
V
CORE
V
BACKUP
V
DDA_PLL
V
DDA_ADC
32xIRQ
2xFIQ
RESET &
POWER
DC-DC
3.3V TO 1.8V
MAIN
LOW POWER
CK_RTC
LP
OSC
OSC
32K
CK_SYS
HCLK
PCLK
CLOCK
MANAGE-
MENT
PLL
FREE
OSC
OSC
4M
CK_USB
USB Full Speed
NRSTIN
NRSTOUT
V
DD_IO
V
18
V
18BKP
V
SS
RTC_XT1
RTC_XT2
XT1
XT2
V
DDA_PLL
V
SSA_PLL
USBDP
USBDM
15AF
P0[31:0]
P1[19:0]
P2[19:0]
16AF
VDDA_ADC
VSSA_ADC
2xICAP, 2xOCMP as AF
2xICAP, 2xOCMP as AF
2xICAP, 2xOCMP as AF
PWM1, PWM1N
PWM2, PWM2N
PWM3, PWM3N
PWM_EMERGENCY as AF
EXT.IT
WAKEUP
GPIO PORT 0
GPIO PORT 1
GPIO PORT 2
10-bit ADC
WATCHDOG
RTC
TB TIMER
TIM0 TIMER
TIM1 TIMER
TIM2 TIMER
PWM TIMER
APB (up to 32 MHz)
CAN 2.0B
FIFO
2x(16x8bit)
UART0
FIFO
2x(16x8bit)
UART1
FIFO
2x(16x8bit)
UART2
FIFO
2x(8x16bit)
SSP0
FIFO
2x(8x16bit)
SSP1
I2C
RX,TX as AF
RX,TX,CTS,
RTS as AF
RX,TX,CTS,
RTS as AF
RX,TX,CTS,
RTS as AF
MOSI,MISO,
SCK,NSS as AF
MOSI,MISO,
SCK,NSS as AF
SCL,SDA as AF
AF: alternate function on I/O port pin
Note: I/Os shown for 100 pin devices. 64-pin devices have the I/O set shown in
11/84
Pin description
Figure 2.
LQFP100 pinout
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
ADC_IN13 / P1.12
ADC_IN0 / TIM2_OC1/ P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
TIM1_TI2 / P0.31
TIM1_OC2 / P0.30
ADC_IN8 / TIM1_TI1 / P0.29
TIM1_OC1 / P0.28
TEST
V
SS_IO
ADC_IN6 / UART1_RTS / P0.23
TIM2_OC1/ P2.04
UART1_RTS / P2.03
P2.02
ADC_IN5 / UART1_CTS / P0.22
UART1_TX / P0.21
UART1_RX / P0.20
JTMS / P1.19
JTCK / P1.18
JTDO / P1.17
JTDI / P1.16
NJTRST
P2.01
P2.00
UART0_RTS / RTCK / P0.13
12
13
14
15
8
9
10
11
6
7
4
5
1
2
3
20
21
22
23
16
17
18
19
24
25
LQFP100
V
18BKP
I/Os
64
63
62
61
68
67
66
65
75
74
73
72
71
70
69
56
55
54
53
60
59
58
57
52
51
VREG_DIS
V
SS_IO
V
SSA_ADC
P2.10
P2.11
V
DDA_ADC
V
DD_IO
P1.02 / TIM2_OC2
P1.03 / TIM2_TI2
USB_DP
USB_DN
P0.14 / CAN_RX
P0.15 / CAN_TX
P2.12
P2.13
P1.15 / WKP_STDBY
NRSTIN
NRSTOUT
XRTC2
XRTC1
V
18BKP
V
SSBKP
V
SS18
V
18REG
P2.14
= 16 A/D input channels
= 15 External interrupts / Wake-up Lines
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 3.
LQFP64 pinout
Pin description
ADC_IN13 / P1.12
ADC_IN0 / TIM2_OC1 / P0.02
MCO / TIM0_TI1 / P0.01
BOOT0 / TIM0_OC1 / P0.00
ADC_IN8 / TIM1_TI1 / P0.29
TIM1_OC1 / P0.28
TEST
V
SS_IO_4
UART1_TX / P0.21
UART1_RX / P0.20
JTMS / P1.19
JTCK / P1.18
JTDO / P1.17
JTDI / P1.16
NJTRST
UART2_TX / UART0_RTS / RTCK / P0.13
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
LQFP64
9
40
10
39
11
38
12
V
18BKP
I/Os
37
13
36
14
35
15
34
16
17 18 19 20 21 22 23 24 25 26 27 28
33
29 30 31 32
V
REG_DIS
V
SS_IO_2
V
SSA_ADC
V
DDA_ADC
V
DD_IO_2
P1.03 / TIM2_TI2
P0.14 / CAN_RX or USB_DP
P0.15 / CAN_TX or USB_DN
NRSTIN
NRSTOUT
XRTC2
XRTC1
V
18BKP
V
SSBKP
V
SS18
V
18REG
= 11 A/D input channels
= 13 External interrupts / Wake-up Lines
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Pin description STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 4.
1
LFBGA100 ball connections
2 3 4 5 6 7
A
P0.03
P1.13
P1.14
P1.04
P1.06 P1.08
P0.05
8
P0.06
9
P0.07
10
P1.02
B
P1.12
P0.02
P0.01
P1.05
P1.07 P1.09
P0.04
K
P0.10
P0.09
P0.08
P0.18
P0.17 P0.16
XT1
P2.13
P1.03
P2.10
C
P0.31
P0.00 V
DD_IO
V
18
P1.10 P2.09
V
SS_IO
V
SSA_ADC
P2.11
USB_DP
D
P0.29
P0.30 V
SS_IO
V
SS18
P1.01 P1.15
V
DD_IO
V
DDA_ADC
P2.12
USB_DN
E
P0.28
P0.23
P0.22
V
SS_IO
TEST P1.00 NRSTOUT VREG_DIS NRSTIN P0.14
F
P2.03
P0.21
P0.20
P2.02
P2.04 P2.05
P2.06
G
H
NJTRST P1.18
P0.13
P1.16
P1.19
P1.17
P2.01
P2.19
P2.00 P2.07
P2.18 P2.17
2.08
P0.24
V
SS18
V
18REG
V
SSBKP
P0.15
V
18BKP
XRTC2
P2.14
P2.16
XRTC1
J
P0.11
P0.12
P1.11
P0.27
P0.19 P0.26
P0.25
P2.15
XT2
V
DD_IO
V
SS_IO
V
DDA_PLL
V
SSA_PLL
Table 5.
A
F
G
D
E
B
C
H
LFBGA64 ball connections
1 2 3 4
P0.29
P1.18
P0.28
P1.19
TEST
P0.20
P0.13
NJTRST P1.16
P0.11
P0.12
P1.11
5
P1.08
6
P0.05
7
P0.06
8
P0.07
P0.03
P1.12
P0.01
P0.10
V
SS_IO
V
DD_IO
P0.02
P0.09
P1.04
P1.05
P0.00
P0.08
P1.06
P1.07
P1.09
P0.04
P1.10
P1.03
V
18
V
SS18
V
DD_IO
V
SS_IO
P0.14
V
SS_IO
VREG_DIS V
DDA_ADC
V
SSA_ADC
P0.15
P0.21
NRSTOUT NRSTIN V
18BKP
XRTC2
P1.17
P0.19
P0.17
V
18REG
V
DD_IO
P0.18
V
SS18
V
SSBKP
XRTC1
V
SS_IO
V
DDA_PLL
V
SSA_PLL
P0.16
XT2 XT1
14/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
4.1
Pin description
Pin description table
Legend / abbreviations for
Table 6
:
Type:
Input levels:
Inputs:
I = input, O = output, S = supply,
All Inputs are LVTTL at V
DD_IO at V
DD_IO
= 5V
= 3.3V+/-0.3V or TTL
±
0.5V. In both cases, T
T means
V
ILmax
=0.8V V
IHmin
=2.0V
All inputs can be configured as floating or with internal weak pull-up or pull down (pu/pd)
Outputs:
All Outputs can be configured as Open Drain (OD) or
Push-Pull (PP) (see also note 6 below
Table 6
There are 3 different types of Output with different drives and speed characteristics:
– O8: f max
= 40 MHz on C
L
=50pF and 8 mA static drive capability for V
OL
=0.4V and up to 20 mA for
V
OL
Output driving current on page 55
– O4: f max
= 20 MHz on C
L
=50pF and 4 mA static drive capability for V
OL
=0.4V (see
Output driving current on page 55
– O2: f max
= 10 MHz on C
L
=50pF and 2 mA static drive capability of for V
OL
=0.4V (see
Output driving current on page 55
External interrupts/wake-up lines:
EITx
15/84
Pin description STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Port reset state
The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13 which are configured as JTAG alternate functions:
● The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready to accept JTAG sequences.
●
●
The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is configured in output push-pull only when serial JTAG data must be output.
The JTAG output RTCK is always configured as output push-pull. It outputs '0' level during the reset phase and then outputs the JTCK input signal resynchronized 3 times by the internal AHB clock.
●
●
The GPIO_PCx registers do not control JTAG AF selection, so the reset values of
GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO section of the STR750 Reference Manual for the register description and reset values.
P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first word of user code at address 0000 0000h.
●
When booting from SMI (and only in this case), the reset state of the following GPIOs is
"SMI alternate function output enabled":
– P0.07 (SMI_DOUT)
– P0.05 (SMI_CLK)
– P0.04 (SMI_CS0)
– P0.06 (SMI_DIN)
Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected.
To avoid excess power consumption, unused I/O ports must be tied to ground.
Table 6.
Pin n°
STR750F pin description
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Alternate function
1
2
B1 1 B1
P1.12 /
ADC_IN13
B2 2 C2
P0.02 /
TIM2_OC1 /
ADC_IN0
I/O T
I/O T
T
T
X
X
X
X
3 B3 3 C1
P0.01 / TIM0_TI1
/ MCO
I/O T
T
X
X
EIT12
EIT0
O8
O8
O8
X
X
X
X
X
X
4 C2 4 C3
P0.00 /
TIM0_OC1 /
BOOT0
I/O T
T
X
X O8 X X
5 C1
6 D2
P0.31 / TIM1_TI2 I/O T
T
X
P0.30 /
TIM1_OC2
I/O T
T
X
X
X
O2 X X
O2 X X
Port 1.12
Port 0.02
ADC: Analog input 13
TIM2: Output
Compare 1
ADC: Analog input 0
Port 0.01
TIM0: Input
Capture / trigger
/ external clock 1
Main Clock
Output
Port 0.00 /
Boot mode selection input 0
TIM0: Output Compare 1
Port 0.31
TIM1: Input Capture / trigger / external clock 2
Port 0.30
TIM1: Output Compare 2
16/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
Pin n°
STR750F pin description (continued)
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Pin description
Alternate function
7 D1 5 D1
P0.29 / TIM1_TI1
/ ADC_IN8
I/O T
T
8 E1 6 D2
P0.28 /
TIM1_OC1
E5 7 D3 TEST 9
10 E4 8 D4 VSS_IO
11 E2
P0.23 /
UART1_RTS /
ADC_IN6
12 F5
P2.04 /
TIM2_OC1
I/O
I
S
I/O
I/O
T
T
T
T
T
T
X
X
X
X
13 F1
P2.03 /
UART1_RTS
I/O T
T
X
X
X
X
X
X
14
15
F4
E3
P2.02 I/O T
T
P0.22 /
UART1_CTS /
ADC_IN5
I/O T
T
16 F2 9 E4
P0.21 /
UART1_TX
17 F3 10 E3
P0.20 /
UART1_RX
I/O
I/O
T
T
T
T
X
X
X
X
X
X
X
X
18 G3 11 E2 P1.19 / JTMS I/O T
T
X X
19 G2 12 E1 P1.18 / JTCK
20 H3 13 F4 P1.17 / JTDO
21 H2 14 F3 P1.16 / JTDI
22 G1 15 F2 NJTRST
23 G4 P2.01
24 G5 P2.00
I/O T
T
X X
I/O T
T
X X
I/O T
T
X
I T
T
I/O T
T
I/O T
T
X
X
X
X
X
25 H1 16 F1
P0.13 / RTCK /
UART0_RTS
UART2_TX
I/O T
T
X X
O2 X X
O2 X X
O2 X X
O2 X X
O2 X X
O2 X X
O2 X X
O2 X X
O2 X X
O8 X X
O2 X X
O2
O2
O2
O2
X
X
X
X
X
X
X
X
O8 X X
Port 0.29
TIM1: Input
Capture 1
ADC: Analog input 8
Port 0.28
Port 0.22
TIM1: Output Compare 1
Reserved, must be tied to ground
Ground Voltage for digital I/Os
Port 0.23
UART1: Ready
To Send output
(4)
ADC analog input
6
Port 2.04
Port 2.03
TIM2: Output
Compare 1
UART1: Ready
To Send output
Port 2.02
UART1: Clear To
Send input
ADC: Analog input 5
Port 0.21
Port 0.20
UART1: Transmit data output
(remappable to P0.15)
UART1: Receive data input
(remappable to P0.14)
JTAG mode selection
Port 1.19
JTAG clock
Port 1.18
JTAG data
Port 1.17
JTAG data
Port 1.16
JTAG reset input
(5)
Port 2.01
Port 2.00
Port 0.13
JTAG return clock output
(6)
UART0: Ready
To Send output
UART2: Transmit
Data output
(when
17/84
Pin description STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
Pin n°
STR750F pin description (continued)
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Alternate function
26 J2 17 G2
P0.12 /
UART2_RX /
UART0_CTS /
ADC_IN2 /
SMI_CS1
40 K4 24 H5
41 K5 25 H4
42 K6 26 H6
P0.18 /
SSP1_MOSI
P0.17 /
SSP1_MISO /
ADC_IN3
P0.16 /
SSP1_SCLK
I/O T
T
X
X
I/O T
T
I/O T
T
I/O T
T
X
X
X
X
X
X
O4
27 J1 18 G1
P0.11 /
UART0_TX /
BOOT1 /
SMI_CS2
I/O T
T
X
X O4
28 K1 19 H1
P0.10 /
UART0_RX /
SMI_CS3
I/O T
T
29 K2 20 H2 P0.09 / I2C_SDA I/O T
T
30 K3 21 H3 P0.08 / I2C_SCL I/O T
T
31 H4 P2.19
I/O T
T
32 H5 P2.18
I/O T
T
33 H6
P2.17 /
UART2_RTS
I/O T
T
34 J3 22 G3
P1.11
/UART0_RTS
ADC_IN12
35 J4
P0.27 /
UART2_RTS /
ADC_IN7
I/O
I/O
T
T
T
T
36
37
38
J6
J7
H7
P0.26 /
UART2_CTS
P0.25 /
UART2_TX
P0.24 /
UART2_RX
I/O
I/O
I/O
T
T
T
T
T
T
X
X
X
X
X
X
X
X
X
X
X
X
X
X EIT3
X
X
X
EIT4 O2
X EIT11 O8
X
X
X
X
O2
O2
O2
O2
O4
O4
O2
O2
O2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
39 J5 23 G4
P0.19 / USB_CK /
SSP1_NSS /
ADC_IN4
I/O T
T
X
X EIT6 O2 X X
O2
X
X
O2 X
O2 X
X
X
X
X
Port 0.12
Port 0.10
Port 0.09
Port 0.08
Port 2.19
Port 2.18
UART0: Clear To
Send input
ADC: Analog input 2
Serial Memory
Interface: chip select output 1
UART2: Receive
Data input (when
Port
0.11/Boot mode selection input 1
UART0: Transmit data output
Serial Memory
Interface: chip select output 2
UART0: Receive
Data input
Serial Memory
Interface: chip select output 3
I2C: Serial Data
I2C: Serial clock
Port 2.17
UART2: Ready To Send output
Port 1.11
Port 0.27
UART0: Ready
To Send output
UART2: Ready
To Send output
ADC: Analog input 12
ADC: Analog input 7
Port 0.26
Port 0.25
Port 0.24
Port 0.19
Port 0.18
Port 0.17
Port 0.16
UART2: Clear To Send input
UART2: Transmit data output
(remappable to P0.13)
UART2: Receive data input
(remappable to P0.12)
SSP1: Slave select input
(remappable to
P0.11)
ADC: Analog input 4
USB:
48 MHz Clock input
SSP1: Master out/slave in data
(remappable to P0.10)
SSP1: Master in/slave out data
(remappable to
P0.09)
ADC: Analog input 3
SSP1: serial clock (remappable to
P0.08)
18/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
Pin n°
STR750F pin description (continued)
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Pin description
Alternate function
43 H9 P2.16
44 J9 27 G5 VDD_IO
45 K9 28 G7 VDDA_PLL
46 K8 29 H7 XT2
47 K7 30 H8 XT1
48
49
50
51
52
53
54
55
J10
K10
J8
H8
G8
F8
F9
G9
31
32
33
34
35
36
G6 VSS_IO
G8 VSSA_PLL
F5
F6
F7
E7
P2.15
P2.14
V18REG
VSS18
VSSBKP
V18BKP
I/O T
T
S
S
S
S
I/O T
T
I/O T
T
S
S
S
S
56 H10 37 F8 XRTC1
57 G10 38 E8 XRTC2
58 E7 39 E5 NRSTOUT
59 E9 40 E6 NRSTIN
60 D6
P1.15 /
WKP_STDBY
61 B8
62 D9
P2.13
P2.12
63 F10
41
(7)
D8
P0.15 / CAN_TX
O
I
I
I/O
T
T
T
I/O T
T
T
T
T
X
I/O T
T
X
64 E10
42
C8
P0.14 / CAN_RX I/O T
T
X
X
X
65 D10
41
D8
USB_DN
66 C10
42
C8
USB_DP
I/O
I/O
X
X
X
X
EIT15
EIT5
O2
O2
O2
O2 X
X
X
X
X
67 B9 43 B8 P1.03 / TIM2_TI2 I/O T
T
X
X
X
X
X
X
X
X
O2
O2
O2
O2
X
X
X
X
X
X
Port 2.16
Supply voltage for digital I/Os
Supply voltage for PLL
4 MHz main oscillator
X
X
X
X
X
Ground voltage for digital I/Os
Ground voltage for PLL
Port 2.15
Port 2.14
Stabilization for main voltage regulator. Requires external capacitors of at least 10µF between
To be connected to the 1.8V external power supply when embedded regulators are not used,
Ground Voltage for the main voltage regulator
Stabilization for low power voltage regulator.
Ground Voltage for the low power voltage regulator.
Requires external capacitors of at least 1µF between V18BKP and VSSBKP. See
To be connected to the 1.8V external power supply when embedded regulators are not used,
X
32 kHz oscillator for Realtime Clock
X
X Reset output
X Reset input
X
Port 1.15
Wake-up from STANDBY input pin
Port 2.13
Port 2.12
Port 0.15
CAN: Transmit data output
Port 0.14
CAN: Receive data input
USB: bidirectional data (data -)
USB: bidirectional data (data +)
Port 1.03
TIM2: Input Capture / trigger / external clock 2 (remappable to
P0.07)
(8)
19/84
Pin description STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
Pin n°
STR750F pin description (continued)
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Alternate function
68 A10
P1.02 /
TIM2_OC2
69 D7 44 C6 VDD_IO
70 D8 45 D6 VDDA_ADC
71 C9
72 B10
P2.11
P2.10
73 C8 46 D7 VSSA_ADC
74 C7 47 C7 VSS_IO
75 E8 48 D5 VREG_DIS
76 A9 49 A8
P0.07 /
SMI_DOUT /
SSP0_MOSI
I/O T
T
S
S
I/O T
T
I/O T
T
S
S
I T
T
I/O T
T
X
X
X
X
X
X
X
X EIT2
O2
O2
O2
O4
77 A8 50 A7
P0.06 / SMI_DIN
/ SSP0_MISO
I/O T
T
X
78 A7 51 A6
P0.05 /
SSP0_SCLK /
SMI_CK
I/O T
T
X
X
X EIT1
O4
O4
79 B7 52 B6
P0.04 / SMI_CS0
/ SSP0_NSS
I/O T
T
X
X O4
80 C5 53 B7
P1.10
PWM_EMERGE
NCY
81 B6 54 B5 P1.09 / PWM1
82 C6 P2.09 / PWM1N
83
84
85
86
G7
G6
F7
F6
P2.08 / PWM2
P2.07 / PWM2N
P2.06 / PWM3
P2.05 / PWM3N
I/O T
T
X
X EIT10 O2
I/O T
T
X
I/O T
T
X
I/O T
T
X
I/O T
T
X
I/O T
T
X
I/O T
T
X
X
X
X
X
X
X
EIT9 O4
O2
O2
O2
O2
O2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
87 A6 55 A5
P1.08 / PWM1N /
ADC_IN11
I/O T
T
X
X O4
88 B5 56 B4 P1.07 / PWM2 I/O T
T
X
89 A5 57 A4
P1.06 / PWM2N /
ADC_IN10
I/O T
T
X
90 B4 58 B3 P1.05 / PWM3 I/O T
T
X
X
X
X
EIT8
EIT7
O4
O4
O4
X
X
X
X
X
X
X
X
Port 1.02
TIM2: Output compare 2
(remappable to P0.06)
Supply Voltage for digital I/Os
Supply Voltage for A/D converter
Port 2.11
Port 2.10
Ground Voltage for A/D converter
Ground Voltage for digital I/Os
Voltage Regulator Disable input
Port 0.07
Serial Memory
Interface: data output
SSP0: Master out
Slave in data
Port 0.06
Serial Memory
Interface: data input
SSP0: Master in
Slave out data
Port 0.05
SSP0: Serial clock
Serial Memory
Interface: Serial clock output
Port 0.04
Serial Memory
Interface: chip select output 0
SSP0: Slave select input
Port 1.10
PWM: Emergency input
Port 1.09
Port 2.09
Port 2.08
Port 2.07
Port 2.06
Port 2.05
Port 1.08
Port 1.07
Port 1.06
Port 1.05
PWM: PWM1 output
PWM: PWM1 complementary output
PWM: PWM2 output
PWM: PWM2 complementary output
PWM: PWM3 output
PWM: PWM3 complementary output
PWM: PWM1 complementary output
ADC: analog input 11
PWM: PWM2 output
PWM: PWM2 complementary output
ADC: analog input 10
PWM: PWM3 output
20/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
Pin n°
STR750F pin description (continued)
Input Output
Pin name
OD
(3)
PP
Main function
(after reset)
Pin description
Alternate function
91 A4 59 A3
P1.04 / PWM3N /
ADC_IN9
I/O T
T
X
X O4 X X
Port 1.04
PWM: PWM3 complementary output
ADC: analog input 9
92 A3
93 A2
P1.14 /
ADC_IN15
P1.13 /
ADC_IN14
I/O T
T
I/O T
T
X
X
X O8
X EIT13 O8
X
X
X
X
Port 1.14
Port 1.13
ADC: analog input 15
ADC: analog input 14
94 D5
95 E6
P1.01 / TIM0_TI2 I/O T
T
P1.00 /
TIM0_OC2
96 C4 60 C4 V18
97 D4 61 C5 VSS18
98 D3 62 A2 VSS_IO
99 C3 63 B2 VDD_IO
I/O T
T
S
S
S
S
100 A1 64 A1
P0.03 / TIM2_TI1
/ ADC_IN1
I/O T
T
X
X
X
X
X
X
O2
O2
O2
X
X
X
X
X
X
Port 1.01
Port 1.00
TIM0: Input Capture / trigger / external clock 2 (remappable to
P0.05)
TIM0: Output compare 2
(remappable to P0.04)
Stabilization for main voltage regulator. Requires external capacitors 33nF between V18 and VSS18.
.
To be connected to the 1.8V external power supply when embedded regulators are not used.
Ground Voltage for the main voltage regulator.
Ground Voltage for digital I/Os
Supply Voltage for digital I/Os
Port 0.03
TIM2: Input
Capture / trigger
/ external clock 1
ADC: analog input 1
1.
For STR755FVx part numbers, the USB pins must be left unconnected.
2.
The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level.
3.
None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O pin and VDD_IO.
4.
In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where these functions are listed in the table.
5.
It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to
NRSTOUT pin (if available) or NRSTIN.
6.
After reset, these pins are enabled as JTAG alternate function see (
general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case, debugging these I/Os via JTAG is not possible).
7.
There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX.
8.
For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
21/84
Pin description STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 4.
Required external capacitors when regulators are used
33 nF
33 nF
97
V
SS18
96
V
18
V
18BKP
55
V
SSBKP 54
1µF
61
V
SS18
60
V
18
V
18BKP
36
V
SSBKP 35
LQFP100
V
SS18 53
V
18REG 52
V
DD_IO
44
10 µF
LQFP64
V
SS18 34
V
18REG
V
DD_IO
27
33
1 µF
1 µF
33 nF
33 nF
D4
V
SS18
C4
V
18
V
18BKP
G9
V
SSBKP F9
LFBGA100
V
SS18
F8
V
18REG G8
V
DD_IO
J9
1 µF
1µF
10 µF
C5
V
SS18
C4
V
18
V
18BKP
E7
V
SSBKP F7
LFBGA64
V
SS18 F6
V
18REG
V
DD_IO
G5
F5
1 µF
1µF
10 µF
1µF
10 µF
22/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Memory map
Figure 5.
Memory map
Addressable Memory Space
4 Gbytes
0xFFFF FFFF
APB TO ARM7
BRIDGE
0xFFFF 8000
32K
7
0xE000 0000
0xDFFF FFFF
6
0xC000 0000
0xBFFF FFFF
FLASH Memory Space
128/256 Kbytes
0x2010 DFFF
0x2010 C000
0x2010 0017
0x2010 0000
SystemMemory
8K
Flash registers
24B
5
0xA000 0000
0x9FFF FFFF
0x200C 4000
0x200C 3FFF
0x200C 2000
0x200C 1FFF
0x200C 0000
B1F1
B1F0
8K
8K
4
0x9000 0013
0x9000 0000
SMI Registers 20B
0x83FF FFFF
0x8000 0000
0x7FFF FFFF
SMI Ext. Memory
4 x 16M
3
0x6000 0047
0x6000 0000
0x5FFF FFFF
CONF + MRCC 1K
0x2003 FFFF
B0F7
(2) 64K
2
0x4000 3FFF
0x4000 0000
0x3FFF FFFF
Internal SRAM
16K
0x2003 0000
0x2002 FFFF
0x2002 0000
0x2001 FFFF
1
0x2010 0017
0x2000 0000
0x1FFF FFFF
Internal Flash 128K/256K+16K+32B
0x2001 0000
0x2000 FFFF
0
0x0000 0000
Boot Memory
(1)
128K/256K
0x2000 8000
0x2000 7FFF
0x2000 6000
0x2000 5FFF
0x2000 4000
0x2000 3FFF
0x2000 2000
0x2000 1FFF
0x2000 0000
B0F6
(2)
B0F5
B0F4
B0F3
B0F2
B0F1
B0F0
64K
64K
(1) In internal Flash Boot Mode, internal FLASH is aliased at 0x0000 0000h
(2) Only available in STR750Fx2
Reserved
32K
8K
8K
8K
8K
Peripheral Memory Space
32 Kbytes
0xFFFF FFFF
Reserved
0xFFFF FC00
0xFFFF FBFF
EIC
0xFFFF F800
0xFFFF F7FF
EXTIT
0xFFFF F400
0xFFFF F3FF
RTC
0xFFFF F000
0xFFFF EFFF
DMA
0xFFFF EC00
0xFFFF EBFF
Reserved
0xFFFF E800
0xFFFF E7FF
GPIO I/O Ports
0xFFFF E400
0xFFFF E3FF
Reserved
0xFFFF E000
0xFFFF DFFF
UART2
0xFFFF DC00
0xFFFF DBFF
UART1
0xFFFF D800
0xFFFF D7FF
UART0
0xFFFF D400
0xFFFF D3FF
Reserved
0xFFFF D000
0xFFFF CFFF
I2C
0xFFFF CC00
0xFFFF CBFF
Reserved
0xFFFF C800
0xFFFF C7FF
CAN
0xFFFF C400
0xFFFF C3FF
Reserved
0xFFFF C000
0xFFFF BFFF
SSP1
0xFFFF BC00
0xFFFF BBFF
SSP0
0xFFFF B800
0xFFFF B7FF
Reserved
0xFFFF B400
0xFFFF B3FF
WDG
0xFFFF B000
0xFFFF AFFF
Reserved
0xFFFF AC00
0xFFFF ABFF
USB Registers
0xFFFF A800
0xFFFF A7FF
Reserved
0xFFFF A400
0xFFFF A3FF
0xFFFF A200
0xFFFF A000
0xFFFF 9FFF
USB RAM 256 x16-bit
Reserved
0xFFFF 9C00
0xFFFF 9BFF
PWM
0xFFFF 9800
0xFFFF 97FF
TIM2
0xFFFF 9400
0xFFFF 93FF
TIM1
0xFFFF 9000
0xFFFF 8FFF
TIM0
0xFFFF 8C00
0xFFFF 8BFF
TB Timer
0xFFFF 8800
0xFFFF 87FF
ADC
0xFFFF 8400
0xFFFF 83FF
Reserved
0xFFFF 8000
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
23/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.1.1
Unless otherwise specified, all voltages are referred to V
SS
.
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at T
A max (given by the selected temperature range).
Data based on product characterisation, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3
Σ).
Unless otherwise specified, typical data are based on T
A
=25° C, V
DD_IO
=3.3 V (for the
3.0 V
≤V
DD_IO
≤3.6 V voltage range) and V
18
=1.8 V. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2
Σ)
.
Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
24/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
The loading conditions used for pin parameter measurement are shown in
.
Figure 6.
Pin loading conditions
STR7 PIN
C
L
=50pF
6.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in
Figure 7.
Pin input voltage
STR7 PIN
V
IN
25/84
Electrical parameters
6.1.6
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply schemes
When mentioned, some electrical parameters can refer to a dedicated power scheme among the four possibilities. The four different power schemes are described below.
Power supply scheme 1: Single external 3.3 V power source
Figure 8.
Power supply scheme 1
V
18_BKP
1µF
V
SS_BKP
VREG_DIS
33nF
10µF
V
18
V
SS18
V
18REG
V
SS18
3.3V
+/-0.3V
V
DD_IO
1µF
V
SS_IO
LOW POWER
VOLTAGE
REGULATOR
V
LPVREG
~1.4V
V
18
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
MAIN
VOLTAGE
REGULATOR
V
MVREG
= 1.8V
NORMAL
MODE
POWER
SWITCH
V
BACKUP
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
V
CORE
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
V
IO
=3.3V
OUT
GP I/Os I/O LOGIC
IN
V
DD_PLL
V
SS_PLL
3.3V
PLL
V
DD_ADC
3.3V
ADC
V
SS_ADC
ADC
IN
26/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Power supply scheme 2: Dual external 1.8V and 3.3V supply
Figure 9.
Power supply scheme 2
V
18_BKP
V
SS_BKP
V
DD_IO
VREG_DIS
V
18
V
18REG
1.8V
V
SS18
V
DD_IO
3.3V
+/-0.3V
V
SS_IO
OFF
LOW POWER
VOLTAGE
REGULATOR
V
LPVREG
GP I/Os
OFF
MAIN
VOLTAGE
REGULATOR
V
MVREG
V
IO
=3.3V
OUT
I/O LOGIC
IN
V
DD_PLL
V
SS_PLL
3.3V
PLL
POWER
SWITCH
V
BACKUP
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
V
CORE
KERNEL
(CORE &
DIGITAL &
MEMORIES)
V
DD_ADC
3.3V
ADC
V
SS_ADC
ADC
IN
NOTE : THE EXTERNAL 3.3 V POWER SUPPLY MUST ALWAYS BE KEPT ON
27/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply scheme 3: Single external 5 V power source
Figure 10.
Power supply scheme 3
V
18_BKP
1µF
V
SS_BKP
VREG_DIS
33nF
10µF
V
18
V
SS18
V
18REG
V
SS18
5.0V
+/-0.5V
V
DD_IO
1µF
V
SS_IO
V
LOW POWER
VOLTAGE
REGULATOR
18
V
LPVREG
IN STANDBY MODE THIS BLOCK IS KEPT POWERED ON
~1.4V
GP I/Os
MAIN
VOLTAGE
REGULATOR
V
MVREG
= 1.8V
V
IO
=5.0V
OUT
I/O LOGIC
IN
V
DD_PLL
V
SS_PLL
5.0V
PLL
NORMAL
MODE
V
BACKUP
BACKUP
CIRCUITRY
OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
POWER
SWITCH
V
CORE
KERNEL LOGIC
(CPU &
DIGITAL &
MEMORIES)
V
DD_ADC
5.0V
ADC
V
SS_ADC
ADC
IN
28/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Power supply scheme 4: Dual external 1.8 V and 5.0 V supply
Figure 11.
Power supply scheme 4
V
18_BKP
V
SS_BKP
V
DD_IO
VREG_DIS
V
18
V
18REG
1.8V
V
SS18
V
DD_IO
5.0V
+/-0.5V
V
SS_IO
OFF
LOW POWER
VOLTAGE
REGULATOR
V
LPVREG
OFF
MAIN
VOLTAGE
REGULATOR
V
MVREG
POWER
SWITCH
V
BACKUP
BACKUP
CIRCUITRY
(OSC32K, RTC
WAKEUP LOGIC,
BACKUP REGISTERS)
V
CORE
KERNEL
(CORE &
DIGITAL &
MEMORIES)
V
IO
=5.0V
OUT
GP I/Os
I/O LOGIC
IN
V
DD_PLL
V
SS_PLL
5.0V
PLL
V
DD_ADC
5.0V
ADC
V
SS_ADC
ADC
IN
NOTE : THE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS BE KEPT ON
6.1.7 I/O characteristics versus the various power schemes (3.3V or 5.0V)
Unless otherwise mentioned, all the I/O characteristics are valid for both
●
●
V
V
DD_IO
DD_IO
=3.0 V to 3.6 V with bit EN33=1
=4.5 V to 5.5 V with bit EN33=0
When V
DD_IO
=3.0 V to 3.6 V, I/Os are not 5V tolerant.
All the current consumption measurements mentioned below refer to Power scheme 1 and 2
29/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 12.
Power consumption measurements in power scheme 1 (regulators enabled)
V
DDA_ADC pins
V
DDA_PLL pins
I
DDA_ADC
ADC load
I
DDA_PLL
PLL load
V
DD_IO pins
I
DD
3.3V
Supply ballast regulator transistor
I
33
3.3V
internal load
V
18 pins (including V
18BKP
)
I
18
1.8V
internal load
I
DD
is measured, which corresponds to the total current consumption :
I
DD
= I
DDA_PLL
+ I
DDA_ADC
+ I
33
+ I
18
Figure 13.
Power consumption measurements in power scheme 2 (regulators disabled)
I
DD_v33
V
DDA_ADC pins
V
DDA_PLL pins
I
DDA_PLL
V
DD_IO pins
PLL load
I
DDA_ADC
ADC load
3.3V
Supply
V
18 pins (including V
18BKP
)
I
33
3.3V
internal load
1.8V
Supply
I
DD_v18
I
DD_v33
and I
DD_v18 are measured which correspond to:
I
DD_v33
= I
DDA_PLL
+ I
DDA_ADC
+ I
33
I
DD_v18
= I
18
I
18
1.8V
internal load
30/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Figure 14.
Power consumption measurements in power scheme 3 (regulators enabled)
V
DDA_ADC pins
V
DDA_PLL pins
I
DDA_ADC
ADC load
I
DDA_PLL
PLL load
V
DD_IO pins
I
DD
5.0V
Supply ballast regulator transistor
I
50
5.0V
internal load
V
18 pins (including V
18BKP
)
I
18
1.8V
internal load
I
DD
is measured, which corresponds to the total current consumption :
I
DD
= I
DDA_PLL
+ I
DDA_ADC
+ I
50
+ I
18
Figure 15.
Power consumption measurements in power scheme 4 (regulators disabled)
I
DD_v50
V
DDA_ADC pins
V
DDA_PLL pins
I
DDA_PLL
V
DD_IO pins
PLL load
I
DDA_ADC
ADC load
5.0V
Supply
V
18 pins (including V
18BKP
)
I
50
5.0V
internal load
1.8V
Supply
I
DD_v18
I
DD_v50
and I
DD_v18 are measured which correspond to:
I
DD_v50
= I
DDA_PLL
+ I
DDA_ADC
+ I
50
I
DD_v18
= I
18
I
18
1.8V
internal load
31/84
Electrical parameters
6.2
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Absolute maximum ratings
Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Table 7.
Voltage characteristics
Symbol Ratings
V
DD_x
- V
SS_X
(1)
Including V
DDA_ADC
and V
DDA_PLL
V
18
- V
SS18
Digital 1.8 V Supply voltage on all V
18 power pins (when 1.8 V is provided externally)
V
IN
|
ΔV
DDx
|
|
ΔV
18x
|
|V
SSX
- V
SS
|
V
ESD(HBM)
V
ESD(MM)
Min
-0.3
-0.3
Max
6.5
2.0
Input voltage on any pin
(2)
V
SS
-0.3 to
V
DD_IO
+0.3
V
SS
-0.3 to
V
DD_IO
+0.3
Variations between different 3.3 V or
5.0 V power pins
Variations between different 1.8 V power pins
(3)
Variations between all the different ground pins
50
25
50
Electro-static discharge voltage (Human
Body Model)
Electro-static discharge voltage (Machine
Model)
(electrical sensitivity) on page 52
(electrical sensitivity) on page 52
Unit
V mV
1.
All 3.3 V or 5.0 V power (V
DD_IO
, V
DDA_ADC
, V
DDA_PLL
) and ground (V
SS_IO
, V
SSA_ADC
, V
DDA_ADC
) pins must always be connected to the external 3.3V or 5.0V supply. When powered by 3.3V, I/Os are not 5V tolerant.
2.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V injection is induced by V
IN
>V
DD there is no positive injection current, and the corresponding V
IN
maximum is respected. If V cannot be respected, the injection current must be limited externally to the I
INJ(PIN)
while a negative injection is induced by V
IN
IN
<V
SS
IN
maximum
value. A positive
. For true open-drain pads,
maximum must always be respected
3.
Only when using external 1.8 V power supply. All the power (V
18
V
SSBKP
, V
18REG
, V
18BKP
) and ground (V
SS18
,
) pins must always be connected to the external 1.8 V supply.
32/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 8.
Current characteristics
Symbol Ratings
Maximum value
Unit
I
I
VDD_IO
(1)
VSS_IO
Total current into V
DD_IO
power lines (source)
(2)
Total current out of V
SS
Output current sunk by any I/O and control pin
150
150
25
I
IO
Output current source by any I/Os and control pin - 25 mA
Injected current on NRSTIN pin ± 5
I
INJ(PIN)
(3) & (4)
Injected current on XT1 and XT2 pins ± 5
ΣI
INJ(PIN)
Injected current on any other pin
(5)
Total injected current (sum of all I/O and control pins)
± 5
± 25
1.
The user can use GPIOs to source or sink high current (up to 20 mA for O8 type High Sink I/Os). In this case, the user must ensure that these absolute max. values are not exceeded (taking into account the
RUN power consumption) and must follow the rules described in
Section 6.3.8: I/O port pin characteristics on page 54
.
2.
All 3.3 V or 5.0 V power (V
DD_IO
, V
DDA_ADC
, V
DDA_PLL
) and ground (V must always be connected to the external 3.3V or 5.0V supply.
SS_IO
, V
SSA_ADC
, V
DDA_ADC
) pins
3.
I
INJ(PIN)
must never be exceeded. This is implicitly insured if V cannot be respected, the injection current must be limited externally to the I
INJ(PIN) injection is induced by V
IN
IN
maximum is respected. If V
>V
DD
while a negative injection is induced by V
IN
<V
SS
IN
maximum
value. A positive
. Data based on T
A
=25°C.
4.
Negative injection disturbs the analog performance of the device. See note in
Section 6.3.12: 10-bit ADC characteristics on page 72
.
5.
When several inputs are submitted to a current injection, the maximum
ΣI
INJ(PIN)
is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with
ΣI
INJ(PIN)
maximum current injection on four I/O port pins of the device.
Table 9.
Symbol
Thermal characteristics
Ratings
T
STG
T
J
Storage temperature range
Maximum junction temperature
Value
-65 to +150
150
Unit
°C
°C
33/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.1 General operating conditions
Subject to general operating conditions for V
DD_IO
, and T
A unless otherwise specified.
Table 10.
General operating conditions
Symbol Parameter Conditions Min Max Unit
V f f
HCLK
PCLK
DD_IO
V
P
T
18
D
A
Internal AHB Clock frequency
Internal APB Clock frequency
Standard Operating Voltage
Power Scheme 1 & 2
Accessing SRAM with 0 wait states
Accessing Flash in burst mode, T
A
≤85° C
Accessing Flash in burst mode
T
A
>85° C
Accessing Flash with 0 wait states
Write access to Flash registers
(1)
Accessing Flash in RWW mode
0 64
0
0
0
0
0
3.0
Standard Operating Voltage
Power Scheme 3 & 4
Standard Operating Voltage
Power Scheme 2 & 4
4.5
1.65
LQFP100
Power dissipation at T
A
= 85° C for suffix 6 or T
A
= 105° C for suffix 7
(2)
LQFP64
LFBGA100
LFBGA64
Ambient temperature for 6 suffix version
Maximum power dissipation -40
Low power dissipation
(3)
-40
Ambient temperature for 7 suffix version
Maximum power dissipation -40
Low power dissipation
-40
60
56
32
30
16
32
3.6
5.5
1.95
434
444
487
344
85
105
105
125
MHz
MHz
V mW
T
J
Junction temperature range
6 Suffix Version
7 Suffix Version
-40
-40
105
125
1.
Write access to Flash registers is either a program, erase, set protection or un-set protection operation.
2.
If T
A
is lower, higher PD values are allowed as long as T
Thermal characteristics on page 79
J does not exceed T
Jmax
3.
In low power dissipation state, T
A
can be extended to this range as long as T
Section 7.2: Thermal characteristics on page 79
).
J does not exceed T
Jmax
(see
°C
°C
°C
°C
°C
°C
34/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Subject to general operating conditions for T
A
.
Table 11.
Operating conditions at power-up / power-down
Symbol Parameter Conditions Min
(1)
20 t
VDD_IO
V
DD_IO
rise time rate t
V18
V
18
rise time rate
When 1.8 V power is supplied externally
1.
Data guaranteed by characterization, not tested in production.
20
Typ Max
20
20
Unit
μs/V ms/V
μs/V ms/V
Subject to general operating conditions for V
DD_IO
, and T
A
Table 12.
Embedded voltage regulators
Symbol Parameter Conditions Min Typ Max Unit
V
MVREG
MVREG power supply
(1)
load <150 mA 1.65
1.80
1.95
V
LPVREG
LPVREG power supply
(2)
load <10 mA 1.30
1.40
1.50
t
Voltage Regulators start-up time (to reach 90% of final V value) at V
DD_IO
power-up
(3)
18
V
DD_IO
rise slope = 20 µs/V
V
DD_IO
rise slope = 20 ms/V
80
35
1.
V
MVREG
is observed on the V
18
, V
18REG and V
18BKP
pins except in the following case:
- In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2.
- In STANDBY mode. See note 2.
2.
In STANDBY mode, V
LPVREG
is observed on the V
18BKP
pin
In STOP mode, V
LPVREG
is observed on the V
18
, V
18REG and V
18BKP
pins.
3.
Once V
DD_IO
has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET during this start-up time.
V
V
µs ms
35/84
Electrical parameters
6.3.4
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Supply current characteristics
The current consumption is measured as described in
and
.
Subject to general operating conditions for V
DD_IO
, and T
A
Maximum power consumption
●
●
●
, the MCU is placed under the following conditions:
All I/O pins are configured in output push-pull 0
All peripherals are disabled except if explicitly mentioned.
Embedded Regulators are used to provide 1.8 V (except if explicitly mentioned).
Table 13.
Maximum power consumption in RUN and WFI modes
Symbol Parameter Conditions
(1)
Typ
(2)
Max
(3)
Unit
I
DD
Supply current in
RUN mode
External Clock with PLL multiplication, code running from
RAM, all peripherals enabled in the
MRCC_PLCKEN register: f
HCLK
=60
MHz, f
PCLK
=30 MHz
3.3V and 5V range
Supply current in
WFI mode
External Clock, code running from
RAM: f
HCLK
=60 MHz, f
PCLK
=30 MHz
Single supply scheme see
Parameter setting BURST=1,
WFI_FLASHEN=1
3.3V and 5V range
80
62
90
67
1.
The conditions for these consumption measurements are described at the beginning of
2.
Typical data are based on T
A
=25°C, V
DD_IO
=3.3V or 5.0V and V
18
=1.8V unless otherwise specified.
3.
Data based on product characterisation, tested in production at V
DD_IO max and V supply mode or regulator output value in single supply mode) and T
A
max.
18
max (1.95V in dual mA mA
36/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 14.
Maximum power consumption in STOP and STANDBY modes
Symbol Parameter Conditions
(1)
Typ
(2)
T
A
25°C
Max
(3)
T
A
85°C
T
A
105°C
Unit
I
DD
Supply current in
STOP mode
Supply current in
STANDBY mode
LP_PARAM bits: ALL OFF
(4)
.
LP_PARAM bits: ALL OFF
.
LP_PARAM bits: ALL OFF
3.3V range
I
DD_V18
I
DD_V33
5V range
RTC OFF
I
DD_V18
I
DD_V50
3.3 V range
5V range
12
5
<1
15
5
3
10
15
16
8
3
22
8
6
20
25
117
60
20
160
60
50
25
30
250
110
26
310
110
65
28
33
1.
The conditions for these consumption measurements are described at the beginning of
.
2.
Typical data are based on T
A
=25°C, V
DD_IO
=3.3V or 5.0V and V
18
=1.8V unless otherwise specified.
3.
Data based on product characterisation, tested in production at V regulator output value in single supply mode).
DD_IO max and V
18
max (1.95V in dual supply mode or
4.
In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4V, which significantly reduces the leakage currents.
μA
μA
μA
μA
37/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 16.
Power consumption in STOP mode in Single supply scheme (3.3 V range)
Figure 17.
Power consumption in STOP mode
Single supply scheme (5 V range)
300
250
200
150
100
50
0
TYP (3.3V)
MAX (3.6V)
-40 25 45 55
Temp (°C)
75 95 105
350
300
250
200
150
100
50
0
TYP (5.0V)
MAX (5.5V)
-40 25 45 55
Temp (°C)
75 95 105
Figure 18.
Power consumption in STANDBY mode (3.3 V range)
Figure 19.
Power consumption in STANDBY mode (5 V range)
30
25
20
15
10
5
0
TYP (3.3V)
MAX (3.6V)
35
30
25
20
15
10
5
0
TYP (5.0V)
MAX (5.5V)
-40 25
Temp (°C)
105 -40 25
Temp (°C)
105
38/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Typical power consumption
The following measurement conditions apply to
.
●
●
●
In RUN mode:
● Program is executed from Flash (except if especially mentioned). The program consists of an infinite loop. When f
HCLK
> 32 MHz, burst mode is activated.
A standard 4 MHz crystal source is used.
In all cases the PLL is used to multiply the frequency.
All measurements are done in the single supply scheme with internal regulators used
)
In WFI Mode:
● In WFI Mode the measurement conditions are similar to RUN mode (OSC4M and PLL enabled). In addition, the Flash can be disabled depending on burst mode activation:
– For AHB frequencies greater than 32 MHz, burst mode is activated and the Flash is kept enabled by setting the WFI_FLASH_EN bit (this bit cannot be reset when burst mode is activated).
– For AHB frequencies less than or equal to 32 MHz, burst mode is deactivated,
WFI_FLASH_EN is reset and the LP_PARAM14 bit is set (Flash is disabled in WFI mode).
In SLOW mode:
●
The same program as in RUN mode is executed from Flash. The CPU is clocked by the
FREEOSC, OSC4M, LPOSC or OSC32K. Only EXTIT peripheral is enabled in the
MRCC_PCLKEN register.
In SLOW-WFI mode:
● In SLOW-WFI, the measurement conditions are similar to SLOW mode (CPU clocked by a low frequency clock). In addition, the LP_PARAM14 bit is set (FLASH is OFF). The
WFI routine itself is executed from SRAM (it is not allowed to execute a WFI from the internal FLASH)
In STOP mode:
●
Several measurements are given: in the single supply scheme with internal regulators used (see
): and in the dual supply scheme (see
In STANDBY mode:
● Three measurements are given:
– The RTC is disabled, only the consumption of the LPVREG and RSM remain
(almost no leakage currents)
– The RTC is running, clocked by a standard 32.768 kHz crystal.
●
– The RTC is running, clocked by the internal Low Power RC oscillator (LPOSC)
STANDBY mode is only supported in the single supply scheme (see
39/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Subject to general operating conditions for V
DD_IO
, and T
A
Table 15.
Single supply typical power consumption in Run, WFI, Slow and Slow-WFI modes
Symbol Para meter Conditions
3.3V typ
(1)
5V typ
(2)
Unit
I
DD
(3)
Supply current in
RUN mode
(4)
Clocked by OSC4M with PLL multiplication, all peripherals enabled in the MRCC_PLCKEN register: f
HCLK
=60 MHz, f
PCLK
=30 MHz f
HCLK
=56 MHz, f
PCLK
=28 MHz f
HCLK
=48 MHz, f
PCLK
=24 MHz f
HCLK
=32 MHz, f
PCLK
=32 MHz f
HCLK
=16 MHz, f
PCLK
=16 MHz f
HCLK
=8 MHz, f
PCLK
=8 MHz
Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: f
HCLK
=60 MHz, f
PCLK
=30 MHz f
HCLK
=56 MHz, f
PCLK
=28 MHz f
HCLK
=48 MHz, f
PCLK
=24 MHz f
HCLK
=32 MHz, f
PCLK
=32 MHz f
HCLK
=16 MHz, f
PCLK
=16 MHz f
HCLK
=8 MHz, f
PCLK
=8 MHz
Supply current in
Clocked by OSC4M with PLL multiplication, only EXTIT peripheral enabled in the MRCC_PLCKEN register: f f f f
HCLK
=60 MHz, f
PCLK f
HCLK
=56 MHz, f
PCLK
HCLK
=48 MHz, f
PCLK f
HCLK
=32 MHz, f
PCLK
HCLK
HCLK
=16 MHz, f
= 8 MHz, f
PCLK
PCLK
=30 MHz
(5)
=32 MHz
(6)
= 16 MHz
= 8 MHz
Supply current in
Clocked by FREEOSC: f
HCLK
=f
PCLK
=~5 MHz,
Clocked by OSC4M: f
HCLK
=f
PCLK
=4 MHz
Clocked by LPOSC: f
HCLK
=f
PCLK
=~300 kHz
Clocked by OSC32K: f
HCLK
=f
PCLK
=32.768 kHz
Supply current in
SLOW-WFI
Clocked by FREEOSC: f
HCLK
=f
PCLK
=~5 MHz
Clocked by OSC4M: f
HCLK
=f
PCLK
=4 MHz
Clocked by LPOSC: f
HCLK
=f
PCLK
=~300 kHz
Clocked by OSC32K: f
HCLK
=f
PCLK
=32.768 kHz
80
75
65
59
34
20
65
60
54
42
22
16
62
59
53
22
13
10
9
8
3.65
3.5
3.5
3.1
1.15
0.98
1.
Typical data based on T
A
=25° C and V
DD_IO
=3.3V.
2.
Typical data based on T
A
=25° C and V
DD_IO
=5.0V.
3.
The conditions for these consumption measurements are described at the beginning of
4.
Single supply scheme see
.
5.
Parameter setting BURST=1, WFI_FLASHEN=1
6.
Parameter setting BURST=0, WFI_FLASHEN=0
7.
Parameter setting WFI_FLASHEN=0, OSC4MOFF=1
67
62
55
44
24
18
82
77
67
61
37
22
10
9
3.9
4.2
4.0
3.75
1.65
1.5
63
60
54
23
15
11 mA mA mA mA mA
40/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 16.
Dual supply supply typical power consumption in Run, WFI, Slow and
Slow-WFI modes
To calculate the power consumption in Dual supply mode, refer to the values given in
consider that this consumption is split as follows:
I
DD(single supply)
~I
DD(dual supply)
= I
DD_V18
+ I
DD(VDD_IO)
For 3.3V range: I
DD(VDD_IO)
~ 1 to 2 mA
For 5V range: I
DD(VDD_IO)
~ 2 to 3 mA
Therefore most of the consumption is sunk on the V
18 power supply
This formula does not apply in STOP and STANDBY modes, refer to
.
Subject to general operating conditions for V
DD_IO
, and T
A
Table 17.
Typical power consumption in STOP and STANDBY modes
Symbol Parameter Conditions
3.3V
Typ
(1)
5V
Typ
(2)
Unit
I
DD
(3)
Supply current in STOP mode
(4)
Supply current in STOP mode
(7)
LP_PARAM bits: ALL OFF
(5)
LP_PARAM bits : MVREG ON, OSC4M OFF, FLASH
OFF
(6)
LP_PARAM bits: MVREG ON, OSC4M ON , FLASH
LP_PARAM bits: MVREG ON, OSC4M OFF, FLASH ON
LP_PARAM bits: MVREG ON, OSC4M ON, FLASH ON
LPPARAM bits: ALL OFF, with V
18
=1.8 V
LP_PARAM bits: OSC4M ON, FLASH OFF
LP_PARAM bits: OSC4M OFF, FLASH ON
LP_PARAM bits: OSC4M ON, FLASH ON
I
DD_V18
I
DD_V33
I
DD_V18
I
DD_V33
I
DD_V18
I
DD_V33
I
DD_V18
I
DD_V33
RTC OFF
12
130
1950
630
2435
5
<1
410
1475
550
<1
910
1475
11
15
135
1930
Supply current in STANDBY
RTC ON clocked by OSC32K 14 18
1.
Typical data are based on T
A
=25°C, V
DD_IO
=3.3 V and V
18
=1.8 V unless otherwise indicated in the table.
2.
Typical data are based on T
A
=25°C, V
DD_IO
=5.0 V and V
18
=1.8 V unless otherwise indicated in the table.
3.
The conditions for these consumption measurements are described at the beginning of
4.
Single supply scheme see
.
5.
In this mode, the whole digital circuitry is powered internally by the LPVREG at approximately 1.4 V, which significantly reduces the leakage currents.
6.
In this mode, the whole digital circuitry is powered internally by the MVREG at 1.8 V.
7.
635
2425
5
<1
410
1435
550
1
910
1445
14
μA
μA
μA
41/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Supply and clock manager power consumption
Table 18.
Supply and clock manager
power consumption
Symbol Parameter Conditions
(1)
3.3V
Typ
5V
Typ
I
DD(OSC4M)
I
DD(FLASH)
Supply current of resonator oscillator in STOP or WFI mode (LP_PARAM bit: OSC4M ON)
FLASH static current consumption in
STOP or WFI mode (LP_PARAM bit
FLASH ON)
External components specified in
4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2) on page 46
I
DD(MVREG)
Main Voltage Regulator static current consumption in STOP mode
(LP_PARAM bit: MVREG ON)
I
DD(LPVREG)
Low Power Voltage Regulator + RSM current static current consumption
STOP mode includes leakage where V
18
is internally set to 1.4 V
STANDBY mode where
V
18BKP
and V
18 are internally set to
1.4 V and 0 V respectively
1.
Measurements performed in 3.3V single supply mode see
1815 1795
515
130
12
11
515
135
15
14
Unit
μA
42/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
On-Chip peripheral power consumption
Conditions:
– V
DD_IO
=V
DDA_ADC
=V
DDA_PLL
=3.3 V or 5 V ±10% unless otherwise specified.
– T
A
= 25° C
– Clocked by OSC4M with PLL multiplication, f
CK_SYS
=64 MHz, f
HCLK
=32 MHz, f
PCLK
=32 MHz
.
Table 19.
On-Chip peripherals
Symbol Parameter
Typ
(3.3V and 5.0V)
Unit
I
DD(TIM)
I
DD(PWM)
I
DD(SSP)
I
DD(UART)
TIM Timer supply current
SSP supply current
(3)
(1)
PWM Timer supply current
(2)
0.7
1
1.3
I
I
I
DD(I2C)
DD(ADC)
DD(USB)
UART supply current
(4)
I2C supply current
(5)
ADC supply current when converting
(6)
USB supply current
(7)
Note: V
DD_IO
must be 3.3 V ±10%
CAN supply current
(8)
1.6
0.3
1.2
0.90
mA
I
DD(CAN)
2.8
1.
Data based on a differential I
DD
measurement between reset configuration and timer counter running at 32
MHz. No IC/OC programmed (no I/O pads toggling)
2.
Data based on a differential I
DD
measurement between reset configuration and PWM running at 32 MHz.
This measurement does not include PWM pads toggling consumption.
3.
Data based on a differential I
DD
measurement between reset configuration and permanent SPI master communication at maximum speed 16 MHz. The data sent is 55h. This measurement does not include the pad toggling consumption.
4.
Data based on a differential I
DD
measurement between reset configuration and a permanent UART data transmit sequence at 1Mbauds. This measurement does not include the pad toggling consumption.
5.
Data based on a differential I
DD
measurement between reset configuration (I2C disabled) and a permanent
I2C master communication at 100kHz (data sent equal to 55h). This measurement includes the pad toggling consumption but not the external 10kOhm external pull-up on clock and data lines.
6.
Data based on a differential I
DD
measurement between reset configuration and continuous A/D conversions at 8 MHz in scan mode on 16 inputs configured as AIN.
7.
Data based on a differential I application.
DD
measurement between reset configuration and a running generic HID
8.
Data based on a differential IDD measurement between reset configuration (CAN disabled) and a permanent CAN data transmit sequence in loopback mode at 1MHz. This measurement does not include the pad toggling consumption.
43/84
Electrical parameters
6.3.5
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Clock and timing characteristics
XT1 external clock source
Subject to general operating conditions for V
DD_IO
, and T
A
.
Table 20.
XT1 external clock source
Symbol Parameter Conditions
(1) (2)
Min Typ Max Unit
V f
XT1
XT1H
External clock source frequency
XT1 input pin high level voltage
0.7xV
DD_IO
4
V
60
DD_IO
MHz
V
XT1L
V
SS
0.3xV
DD_IO
V
XT1 input pin low level voltage
t w(XT1H) t w(XT1L) t r(XT1) t f(XT1)
XT1 high or low time
XT1 rise or fall time
(3)
6
20 ns
I
L
XTx Input leakage current
V
SS
≤ V
IN
≤
V
DD_IO
±1
μA
C
IN(XT1)
DuCy
(XT1)
Duty cycle
45
5
55
1.
Data based on typical application software.
2.
Time measured between interrupt event and interrupt vector fetch.
Δt c(INST) needed to finish the current instruction execution.
is the number of t
CPU
cycles
3.
Data based on design simulation and/or technology characteristics, not tested in production.
pF
%
44/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
XRTC1 external clock source
Subject to general operating conditions for V
DD_IO
, and T
A
.
Table 21.
XRTC1 external clock source
Symbol Parameter Conditions
(1)
Min Typ Max Unit
V
V f
XRTC1
XRTC1H
XRTC1L t w(XRTC1H) t w(XRTC1L) t r(XRTC1) t f(XRTC1)
External clock source frequency
XRTC1 input pin high level voltage
XRTC1 input pin low level voltage
XRTC1 high or low time
(2)
C
I
L
IN(RTC1)
XRTCx Input leakage current
XRTC1 input
V
SS
≤V
IN
≤V
DD_I
O
0.7xV
DD_IO
V
SS
900
32.768
5
V
500
DD_IO
0.3xV
DD_IO
50
±1
DuCy
(RTC1)
Duty cycle 30
1.
Data based on typical application software.
2.
Data based on design simulation and/or technology characteristics, not tested in production.
70 kHz
V ns
μA pF
%
Figure 20.
Typical application with an external clock source
90%
V
XT1H
10%
V
XT1L t r(XT1)
T
XT1 t f(XT1) t w(XT1H) t w(XT1L)
EXTERNAL
CLOCK SOURCE hi-Z
XT2
XT1
I
L f
OSC4M
STR750
45/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)
The STR750 system clock or the input of the PLL can be supplied by a OSC4M which is a 4
MHz clock generated from a 4 MHz or 8 MHz crystal or ceramic resonator. If using an 8 MHz oscillator, software set the XTDIV bit to enable a divider by 2 and generate a 4 MHz OSC4M clock. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Table 22.
4/8 MHz crystal / ceramic resonator oscillator (XT1/XT2)
(1)
Symbol Parameter Conditions Min Typ Max Unit
f
OSC4M
Oscillator frequency
4 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=0 or
8 MHz Crystal/Resonator Oscillator connected on XT1/XT2 XTDIV=1
4 MHz
R
F
Feedback resistor
C
C
L1
(2)
L2 i
2 t
SU(OSC4M)
(4)
Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R
S
)
(3)
R
S
=200
Ω
XT2 driving current V
DD_IO
=3.3 V or 5.0 V
Startup time at V
DD_IO
power-up
200 240
425
1
270
60 k pF
μA ms
1.
Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2.
For C
L1
and C
L2 it is recommended to use high-quality ceramic capacitors in the 5-pF to 25-pF range (typ.) designed for high-frequency applications and selected to match the requirements of the crystal or resonator. C
L1
and C
L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C
L1
PCB and MCU pin capacitance must be included when sizing C combined pin and board capacitance).
L1
and C
L2
and C
L2
(10 pF can be used as a rough estimate of the
.
3.
The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions.
4.
t
SU(OSC4M)
is the typical start-up time measured from the moment V to 3.3V (<50
DD_IO
is powered (with a quick V
DD_IO
ramp-up from 0
μs) to a stabilized 4MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer.
Ω
Figure 21.
Typical application with a 4 or 8 MHz crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS
C
L1
C
L2
XT1
RESONATOR
XT2
XTDIV
LINEAR
AMPLIFIER
R
F
V
DD
Ref
/2 i
2
/2
FEEDBACK
LOOP f
OSC4M
STR75X
46/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
OSC32K crystal / ceramic resonator oscillator
The STR7 RTC clock can be supplied with a 32.768 kHz Crystal/Ceramic resonator oscillator. All the information given in this paragraph are based on product characterisation with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time. Refer to the crystal/ceramic resonator manufacturer for more details (frequency, package, accuracy...).
Table 23.
OSC32K crystal / ceramic resonator oscillator
Symbol Parameter Conditions Min Typ Max Unit
f
OSC32K
R
F
Oscillator Frequency
Feedback resistor V
DD_IO
=3.3 V or 5.0 V 270
32.768
310 370 kHz k
Ω
C
C
L1
L2
Recommended load capacitance versus equivalent serial resistance of the crystal or ceramic resonator (R
S
)
(1)
R
S
=40K
Ω
12.5
15 pF i
2
XT2 driving current t
SU(OSC32K)
(2)
Startup time
V
DD_IO
=3.3 V or 5.0 V
V
IN
=V
SS
V
DD_IO
is stabilized
1
2.5
5
1.
The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R
S
Refer to crystal/ceramic resonator manufacturer for more details
value.
2.
t
SU(OSC32K)
is the start-up time measured from the moment it is enabled (by software) to a stabilized 32 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal/ceramic resonator manufacturer
μA s
Figure 22.
Typical application with a 32.768 kHz crystal or ceramic resonator
WHEN RESONATOR WITH
INTEGRATED CAPACITORS i
2
FEEDBACK
LOOP
C
L1
XRTC1 f
OSC32K
C
L2
32 kHz
RESONATOR
XRTC2
R
F
STR750
PLL characteristics
PLL Jitter Terminology
●
Self-referred single period jitter (period jitter)
Period Jitter is defined as the difference of the maximum period (T max
) and minimum period (T min
) at the output of the PLL where T max
is the maximum time difference between 2 consecutive clock rising edges and T min
is the minimum time difference between 2 consecutive clock rising edges.
See
●
Self-referred long term jitter (N period jitter)
Self-referred long term Jitter is defined as the difference of the maximum period (T max
) and minimum period (T min
) at the output of the PLL where T max
is the maximum time
47/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
● difference between N+1 consecutive clock rising edges and T min
is the minimum time difference between N+1 consecutive clock rising edges.
N should be kept sufficiently large to have a long term jitter (ex: thousands).
For N=1, this becomes the single period jitter.
See
Cycle-to-cycle jitter (N period jitter)
This corresponds to the time variation between adjacent cycles over a random sample of adjacent clock cycles pairs. Jitter(cycle-to-cycle) = Max(Tcycle n- Tcycle n-1) for n=1 to N.
See
Figure 23.
Self-referred jitter (single and long term)
n n+1
---
IDEAL
CK_PLL
T n+N
ACTUAL
CK_PLL trigger point single period jitter
Figure 24.
Cycle-to-cycle jitter
n
IDEAL
CK_PLL
T n+1
ACTUAL
CK_PLL
Tcycle 1 Tcycle 2 n+2 --long term jitter
Tcycle N-1 n+N
48/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
PLL characteristics
Subject to general operating conditions for V
DD_IO
, and T
A
.
Table 24.
PLL characteristics
Symbol Parameter Test Conditions
Value
Min Typ Max
(1)
Unit
f
PLL_IN
PLL input clock
PLL input clock duty cycle 40
4.0
60
MHz
% f
PLL_OUT f
VCO
PLL multiplier output clock
VCO frequency range f
PLL_IN x 24
When PLL operates (locked)
336
165
960
MHz
MHz t
LOCK
Δt
JITTER1
(2)(3)
Δt
Δt
PLL lock time
Single period jitter (+/-3 to peak)
Long term jitter (+/-3 peak)
Σ peak
Σ peak to
Cycle to cycle jitter (+/-3
Σ peak to peak) f
PLL_IN
= 4 MHz
(4)
V
DD_IO
is stable f
PLL_IN
V
DD_IO
is stable f
PLL_IN
V
DD_IO
is stable
300
+/-250
+/-2.5
+/-500
1.
Data based on product characterisation, not tested in production.
2.
Refer to jitter terminology in
: PLL characteristics on page 47
for details on how jitter is specified.
3.
The jitter specification holds true only up to 50mV (peak-to-peak) noise on V
DDA_PLL
and V
18
supplies.
Jitter will increase if the noise is more than 50mV. In addition, it assumes that the input clock has no jitter.
4.
The PLL parameters (MX1, MX0, PRESC1, PRESC2) must respect the constraints described in
: PLL characteristics on page 47
.
μs ps ns ps
Internal RC oscillators (FREEOSC & LPOSC)
Subject to general operating conditions for V
DD_IO
, and T
A
.
Table 25.
Internal RC oscillators (FREEOSC & LPOSC)
Symbol Parameter Conditions Min
f
CK_FREEOSC f
CK_LPOSC
FREEOSC Oscillator Frequency
LPOSC Oscillator Frequency
3
150
Typ
5
300
Max
8
500
Unit
MHz kHz
49/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Flash memory
Subject to general operating conditions for V
DD_IO
and V
18 otherwise specified.
, T
A
= -40 to 105 °C unless
Table 26.
Flash memory characteristics
Symbol Parameter Test Conditions
t
PW t
PDW
Word Program
Double Word Program t t
PB0
PB1
Bank 0 Program (256K)
Bank 1 Program (16K)
Single Word programming of a checker-board pattern
Single Word programming of a checker-board pattern t t t t
ES
ES
ES
ES
Sector Erase (64K)
Sector Erase (8K)
Bank 0 Erase (256K)
Bank 1 Erase (16K)
Not preprogrammed (all 1)
Preprogrammed (all 0)
Not preprogrammed (all 1)
Preprogrammed (all 0)
Not preprogrammed (all 1)
Preprogrammed (all 0)
Not preprogrammed (all 1)
Preprogrammed (all 0) t
RPD t
PSL t
ESL
Recovery when disabled
Program Suspend Latency
Erase Suspend Latency
1.
Data based on characterisation not tested in production
2.
10K program/erase cycles.
Table 27.
Flash memory endurance and data retention
Value
Typ Max
(1)
35
60
2
125
4.9
(2)
224
1.54
1.176
392
343
8.0
6.6
0.9
0.8
2.94
2.38
560
532
13.7
11.2
1.5
1.3
20
10
300
Value
Symbol Parameter Conditions
N
END_B0
Endurance (Bank 0 sectors)
N
END_B1
Endurance (Bank 1 sectors)
Y
RET
Data Retention t
ESR
Erase Suspend Rate
T
A
=85° C
Min time from Erase
Resume to next Erase
Suspend
1.
Data based on characterisation not tested in production.
Min
(1)
10
100
20
20
Typ Max
Unit
μs
μs s ms s ms s s
μs
μs
μs
Unit
kcycles kcycles
Years ms
50/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electro magnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the
LEDs).
●
ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 1000-4-2 standard.
● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V
DD
and
V
SS
through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.
Software recommendations:
The software flowchart must include the management of runaway conditions such as:
●
●
●
Corrupted program counter
Unexpected reset
Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the RESET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 28.
EMC characteristics
Symbol Parameter Conditions
Level/
Class
V
FESD
V
EFTB
Voltage limits to be applied on any I/O pin to induce a functional disturbance
V
T
DD_IO
A
=3.3 V or 5 V,
=+25° C, f
CK_SYS
=32 MHz conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied through 100pF on V
DD
and V
SS pins to induce a functional disturbance
V
T
DD_IO
A
=3.3 V or 5 V,
=+25° C, f
CK_SYS
=32 MHz conforms to IEC 1000-4-4
Class A
Class A
51/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electro magnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin.
Table 29.
EMI characteristics
Symbo l
S
EMI
Parameter Conditions
Monitored
Frequency Band
Peak level
Flash devices:
V
T
DD_IO
A
=3.3 V or 5 V,
=+25° C,
LQFP64 package conforming to SAE J
1752/3
0.1 MHz to 30 MHz
30 MHz to 130 MHz
130 MHz to 1 GHz
SAE EMI Level
Max vs. [f
OSC4M
/f
HCLK
]
4/32MHz 4/60MHz
22
31
19
>4
26
26
23
>4
Unit
dB
μV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electro-Static discharge (ESD)
Electro-Static Discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models can be simulated: Human Body Model and Machine Model. This test conforms to the
JESD22-A114A/A115A standard.
Table 30.
Absolute maximum ratings
Symbol Ratings Conditions
Maximum value
(1)
Unit
V
ESD(HBM)
Electro-static discharge voltage
(Human Body Model)
V
ESD(MM)
Electro-static discharge voltage
(Machine Model)
V
ESD(CDM)
Electro-static discharge voltage
(Charge Device Model)
T
A
=+25° C
1.
Data based on product characterisation, not tested in production.
2000
200
750
V
52/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Static and dynamic latch-up
●
●
LU: 3 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
DLU: Electro-Static Discharges (one positive then one negative test) are applied to each pin of 3 samples when the micro is running to assess the latch-up performance in dynamic mode. Power supplies are set to the typical values, the oscillator is connected as near as possible to the pins of the micro and the component is put in reset mode.
This test conforms to the IEC1000-4-2 and SAEJ1752/3 standards. For more details, refer to the application note AN1181.
Table 31.
Electrical sensitivities
Symbol Parameter Conditions Class
(1)
LU
DLU
Static latch-up class
Dynamic latch-up class
T
A
T
A
T
A
=+25° C
=+85° C
=+105° C f
V
DD
= 5.5 V, f
OSC4M
CK_SYS
=32 MHz, T
=4 MHz,
A
=+25° C
Class A
Class A
1.
Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B
Class strictly covers all the JEDEC criteria (international standard).
53/84
Electrical parameters
6.3.8
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
I/O port pin characteristics
General characteristics
Subject to general operating conditions for V
DD_IO
and T
A
unless otherwise specified.
Table 32.
General characteristics
I/O static characteristics
Symbol Parameter Conditions Min Typ Max Unit
V
V
V
IL
IH hys
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
(1)
TTL ports
2
400
0.8
V mV
I
INJ(PIN)
ΣI
INJ(PIN
(2)
Injected Current on any I/O pin
Total injected current (sum of all
I/O and control pins)
± 4
± 25 mA
I lkg
Input leakage current on robust pins
Input leakage current
(3)
R
R
I
S
PU
PD
Static current consumption
Weak pull-up equivalent resistor
(5)
Weak pull-down equivalent
(4)
V
SS
≤
V
IN
≤
V
DD_IO
Floating input mode
V
V
IN
=
IN
=
V
V
SS
DD_IO
±1
μA
200
V
DD_IO
=3.3 V 50 95 200 k
Ω
V
DD_IO
=5 V 20 58 150 k
Ω
V
DD_IO
=3.3 V 25 80 180 k
Ω
V
DD_IO
=5 V 20 50 120 k
Ω
5 pF C
IO
I/O pin capacitance t w(IT)in
External interrupt/wake-up lines pulse time
(6)
2
1.
Hysteresis voltage between Schmitt trigger switching levels.
2.
When the current limitation is not possible, the V
IN
absolute maximum rating must be respected, otherwise refer to I
INJ(PIN) induced by V
IN
specification. A positive injection is induced by V
IN
>V
DD_IO
<V
SS
. Refer to
while a negative injection is
3.
Leakage could be higher than max. if negative current is injected on adjacent pins.
4.
Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor (see
). Data based on design simulation and/or technology characteristics, not tested in production.
5.
The R
PU
pull-up and R
PD
pull-down equivalent resistor are based on a resistive transistor.
6.
To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external interrupt source.
T
AP
B
54/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 25.
Connecting unused I/O pins
V
DD
10k
Ω
STR7XXX
UNUSED I/O PORT
Electrical parameters
10k
Ω
UNUSED I/O PORT
STR7XXX
Output driving current
●
●
●
The GP I/Os have different drive capabilities:
O2 outputs can sink or source up to +/-2 mA.
O4 outputs can sink or source up to +/-4 mA. outputs can sink or source up to +/-8 mA or can sink +20 mA (with a relaxed V
OL
).
In the application, the user must limit the number of I/O pins which can drive current to respect the absolute maximum rating specified in
:
●
●
The sum of the current sourced by all the I/Os on V
DD_IO, plus the maximum RUN consumption of the MCU sourced on V
DD_IO, can not exceed the absolute maximum rating IV
DD_IO
.
The sum of the current sunk by all the I/Os on V
SS_IO
plus the maximum RUN consumption of the MCU sunk on V
SS_IO
can not exceed the absolute maximum rating
IV
SS_IO
.
Subject to general operating conditions for V
DD_IO and T
A
unless otherwise specified.
55/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 33.
Output driving current
I/O Output drive characteristics for
V
DD_IO
= 3.0 to 3.6 V and EN33 bit =1 or V
DD_IO
= 4.5 to 5.5 V and EN33 bit =0
I/O
Type
Symbol Parameter Conditions Min Max Unit
O2
O4
O8
V
V
V
V
V
V
OL
(1)
OH
(2)
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same time
I
IO
=+2 mA
Output high level voltage for an I/O pin when 4 pins are sourced at same time
I
IO
=-2 mA
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same time
I
IO
=+4 mA
Output high level voltage for an I/O pin when 4 pins are sourced at same time
I
IO
=-4 mA
Output low level voltage for a standard
I/O pin when 8 pins are sunk at same time
I
IO
=+8 mA
Output low level voltage for a high sink
I/O pin when 4 pins are sunk at same time
I
IO
=+20 mA,
T
A
T
A
≤85°C
≥85°C
I
IO
=+8 mA
Output high level voltage for an I/O pin when 4 pins are sourced at same time
I
IO
=-8 mA
V
V
V
DD_IO
DD_IO
DD_IO
-0.8
-0.8
-0.8
0.4
0.4
0.4
1.3
1.5
0.4
1.
The I
IO
current sunk must always respect the absolute maximum rating specified in
sum of I
IO
(I/O ports and control pins) must not exceed I
VSS_IO
.
2.
The I
IO
current sourced must always respect the absolute maximum rating specified in
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VDD_IO
.
V
56/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Output speed
Subject to general operating conditions for V
DD_IO
and T
A
unless otherwise specified.
Table 34.
Output speed
I/O dynamic characteristics for
V
DD_IO
= 3.0 to 3.6V and EN33 bit =1 or V
DD_IO
= 4.5 to 5.5V and EN33 bit =0
I/O
Type
Symbol Parameter Conditions
f max(IO)out
Maximum Frequency
(1) t f(IO)out
Output high to low level fall time
(2)
C
L
=50 pF
O2
C
L
=50 pF
Between 10% and 90% t r(IO)out f max(IO)out
Output low to high level rise time
t f(IO)out
Output high to low level fall time
C
L
=50 pF
O4
C
L
=50 pF
Between 10% and 90% t r(IO)out f max(IO)out
Output low to high level rise time
t f(IO)out
Output high to low level fall time
C
L
=50pF
O8
C
L
=50 pF
Between 10% and 90% t r(IO)out
Output low to high level rise time
1.
The maximum frequency is defined as described in
2.
Data based on product characterisation, not tested in production.
Min Typ Max Unit
10
30
33
25
12
14
40
6
6
MHz ns
MHz ns
MHz ns
Figure 26.
I/O output speed definition
90%
50%
10%
10%
50%
90%
EXTERNAL
OUTPUT
ON 50pF t r(IO)out
T t r(IO)out
Maximum frequency is achieved if (t r
+ t f
)
≤
(2/3)T and if the duty cycle is (45-55%) when loaded by 50pF
57/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
NRSTIN and NRSTOUT pins
NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present which is the same as R
PU
: General characteristics on page 54
)
NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the same as R
PU
(see
: General characteristics on page 54
Subject to general operating conditions for V
DD_IO
and T
A
unless otherwise specified.
Table 35.
NRSTIN and NRSTOUT pins
Symbol Parameter Conditions Min Typ
1)
Max Unit
V
V
IL(NRSTIN)
IH(NRSTIN)
NRSTIN Input low level voltage
(1)
NRSTIN Input high level
V hys(NRSTIN)
NRSTIN Schmitt trigger voltage hysteresis
(2)
V
R t
OL(NRSTIN)
PU(NRSTIN) w(RSTL)out t t h(RSTL)in g(RSTL)in
2
NRSTOUT Output low level voltage
(3)
I
IO
=+2 mA
NRSTIN Weak pull-up equivalent resistor
(4)
V
IN
=
V
SS
V
DD_IO
=3.3 V
V
DD_IO
=5 V
Generated reset pulse duration (visible at NRSTOUT pin)
(5)
Internal reset source
External reset pulse hold time at NRSTIN pin
(6)
At V
DD_IO
power-up
When V
DD_IO established
is
25
20
15
20
1 maximum negative spike duration filtered at NRSTIN pin
(7)
The time between two spikes must be higher than 1/2 of the spike duration.
400
50
31
20
150
0.8
0.4
100
100 mV k k
V
Ω
Ω
μs
μs
μs ns
1.
Data based on product characterisation, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels.
3.
The I
IO
current sunk must always respect the absolute maximum rating specified in
sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
4.
The R
PU
pull-up equivalent resistor are based on a resistive transistor
5.
To guarantee the reset of the device, a minimum pulse of 15 µs has to be applied to the internal reset. At
V
DD_IO
power-up, the built-in reset stretcher may not generate the 15 µs pulse duration while once V
DD_IO is established, an external reset pulse will be internally stretched up to 15 µs thanks to the reset pulse stretcher.
6.
The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy environments.
7.
In fact the filter is made to ignore all incoming pulses with short duration:
- all negative spikes with a duration less than 150 ns are filtered
- all trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum duration of 150 ns with minimum interval between spikes of 75 ns are filtered.
Data guaranteed by design, not tested in production.
V
58/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 27.
Recommended NRSTIN pin protection
V
DD_IO
R
PU
Filter
TO RESET
OTHER CHIPS
NRSTOUT
PULSE
GENERATOR
EXTERNAL
RESET
CIRCUIT
V
DD_IO
NRSTIN
R
PU
Filter
0.01
μF
Electrical parameters
INTERNAL RESET
WATCHDOG RESET
SOFTWARE RESET
RSM RESET
STR7X
1.
The user must ensure that the level on the NRSTIN pin can go below the V
IL(NRSTIN)
max. level specified in
NRSTIN and NRSTOUT pins on page 58
. Otherwise the reset will not be taken into account internally.
59/84
Electrical parameters
6.3.9
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
TB and TIM timer characteristics
Subject to general operating conditions for V
DD_IO
, f specified.
CK_SYS
, and T
A
unless otherwise
Refer to
Section 6.3.8: I/O port pin characteristics on page 54
input/output alternate function characteristics (output compare, input capture, external clock,
PWM output...).
Table 36.
TB and TIM timers
Symbol Parameter Conditions Min Typ Max Unit
t w(ICAP)in
Input capture pulse time
TIM0,1,2 t res(TIM) f
EXT
Res
TIM
TB f
CK_TIM(MAX)
= f
CK_SYS f
CK_TIM
= f
CK_SYS
60 MHz
=
Timer resolution time
(1)
Timer external clock
TIM0,1,2 frequency on
TI1 or TI2 f
CK_TIM(MAX)
= f
CK_SYS f
CK_TIM
= f
CK_SYS
60 MHz
=
Timer resolution f
CK_TIM(MAX)
= f
CK_SYS
TIM0,1,2 f
CK_TIM
= f
CK_SYS
60MHz
=
2
1
16.6
1
16.6
0
0
f
CK_TIM
15
16
/4 t t t
CK_TIM
CK_TIM ns
CK_TIM ns
MHz
MHz bit t
COUNTER
16-bit
Counter clock
TB period when internal clock is selected
(16-bit
Prescaler)
TIM0,1,2 f
CK_TIM
= f
CK_SYS
=
60 MHz f
CK_TIM
= f
CK_SYS
60 MHz
=
1
0.0166
1
0.0166
65536
1092
65536
1092 t t
CK_TIM
µs
CK_TIM
µs
65536x65536 t
CK_TIM
TB f
CK_TIM
60 MHz
= f
CK_SYS
=
Maximum t
MAX_COUNT
Possible
Count
71.58
65536x65536 t s
CK_TIM
TIM0,1,2 f
CK_TIM
= f
CK_SYS
60 MHz
=
71.58
s
1.
Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to I/O pin, described in
60/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 37.
PWM Timer (PWM)
Symbol Parameter Conditions Min Typ Max Unit
t t res(PWM)
Res
V
PWM
OS
(1)
COUNTER
PWM resolution time f
CK_TIM(MAX)
= f
CK_SYS f
CK_TIM
= f
CK_SYS
=
60 MHz
1
PWM resolution
PWM/DAC output step voltage
V
DD_IO
=3.3 V, Res=16-bits
V
DD_IO
=5.0 V, Res=16-bits
Timer clock period when internal clock is selected f
CK_TIM
=60 MHz
1
0.0166
50
76
16 t
CK_TIM ns bit
µV
µV
65536 t
CK_TIM
1087 µs
65536x
65536 t
CK_TIM t
MAX_COUNT
Maximum Possible
Count f
CK_TIM
= f
CK_SYS
=
60 MHz
71.58
s
1.
Take into account the frequency limitation due to the I/O speed capability when outputting the PWM to an
.
61/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.10 Communication interface characteristics
SSP synchronous serial peripheral in master mode (SPI or TI mode)
General operating conditions: V
33
, 3.0V to 3.3V, V18 =1.8V, C
L
≈
45 pF.
Table 38.
SSP master mode characteristics
(1)
Symbol Parameter Conditions Min Max Unit
t t t t
SCKNSSH t t t t f
SCK r(SCK) f(SCK) w(SCKH) w(SCKL)
NSSLQV
SCKQV
SCKQX t t su h
SPI clock frequency
SPI clock rise time
SPI clock fall time
(2)
SCK high and low time
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
NSS low to Data Output
MOSI valid time
SSP0
SSP1
SCK last edge to NSS high
CPHA = 0
SSP0
SSP1
CPHA = 1
SSP0
SSP1
SCK trigger edge to data output MOSI valid time
SCK trigger edge to data output MOSI invalid time
SSP0
SSP1
SSP0
SSP1
SSP0 Data input (MISO) setup time w.r.t SCK sampling edge
SSP1
Data input (MISO) hold time w.r.t SCK sampling edge
SSP0
SSP1
0
0
25
25
0
0
1.
Data based on characterisation results, not tested in production.
2.
Max frequency for the 2 SSPs is f
PCLK
/2; f
PCLK
max = 32 MHz. This takes into account the frequency limitation due to I/O speed capability. SSP0 uses IO4 type while SSP1 uses IO2 type I/Os.
33
11
30
19
30
16
8
14
0.5t
SCK
+15ns
0.5t
SCK
+30ns
0.5t
SCK
+15ns
0.5t
SCK
+30ns t
SCK
+15ns t
SCK
+30ns
15
30
MHz ns
62/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Figure 28.
SPI configuration - master mode, single transfer
NSS
OUTPUT t c(SCK) sample edge trigger edge
CPHA=0
CPOL=0
CPHA=0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1 trigger edge sample edge trigger edge sample edge sample edge t w(SCKH) t w(SCKL) t r(SCK) t f(SCK) t su(MISO) t h(MISO)
MISO
INPUT
MSB IN BIT IN DONT CARE t
NSSLQV t
SCKNSSH (CPHA=0) trigger edge t
SCKNSSH (CPHA=1)
LSB IN
DONT
CARE t
SCKQX
MOSI
OUTPUT t
SCKQV
1 OR 0 MSB OUT BIT OUT LSB OUT t
SCKQX
1 OR 0
Figure 29.
SPI configuration - master mode, continuous transfer, CPHA=0
t c(SCK)
1.5*t c(SCK)
NSS
OUTPUT sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
CPOL=0
CPOL=1 t
NSSLQV t
NSSLQV
1 OR 0
MOSI
OUTPUT
MISO
INPUT
DONT CARE
MSB OUT
MSB IN
LSB OUT
LSB IN
MSB OUT
DONT CARE MSB IN
FRAME 1 FRAME 2
Figure 30.
SPI configuration - master mode, continuous transfer, CPHA=1
t c(SCK)
NSS
OUTPUT trigger sample trigger sample trigger sample trigger samlpe trigger sample trigger sample trigger sample trigger sample trigger
CPOL=0
CPOL=1
1 OR 0
MOSI
OUTPUT
MISO
INPUT
DONT CARE
MSB OUT
MSB IN
FRAME 1
LSB OUT MSB OUT
LSB IN MSB IN
FRAME 2
63/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 31.
TI configuration - master mode, single transfer
NSS
OUTPUT
SCK
OUTPUT
MISO
INPUT
DONT CARE t c(SCK) trigger edge sample edge trigger edge sample edge trigger edge sample edge t w(SCKH) t w(SCKL) t f(SCK) t su(MISO) t h(MISO) t r(SCK)
MSB IN LSB IN t
SCKQV t
SCKQX
MOSI
OUTPUT
1 OR 0
MSB OUT LSB OUT
DONT CARE
Figure 32.
TI configuration - master mode, continuous transfer
t c(SCK) t c(SCK)
NSS
OUTPUT trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
SCK
OUTPUT
MOSI
OUTPUT
1 OR 0
MSB OUT
MISO
INPUT
DONT CARE MSB IN
LSB OUT MSB OUT
LSB IN MSB IN
LSB OUT
LSB IN DONT CARE
FRAME 1
FRAME 2
64/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
SSP synchronous serial peripheral in slave mode (SPI or TI mode)
Subject to general operating conditions with C
L
≈
45 pF
Table 39.
SSP slave mode characteristics
(1)
Symbol Parameter Conditions Min Max
MISO
OUTPUT MSB OUT BIT OUT LSB OUT
Unit
t t t t t t t t f
SCK su(NSS) h(NSS)
NSSLQV
NSSLQZ
SCKQV
SCKQX su(MOSI) h(MOSI)
SPI clock frequency
NSS input setup time w.r.t
SCK first edge
NSS input hold time w.r.t
SCK last edge
NSS low to Data Output
MISO valid time
NSS low to Data Output
MISO invalid time
SCK trigger edge to data output MISO valid time
SCK trigger edge to data output MISO invalid time
MOSI setup time w.r.t SCK sampling edge
MOSI hold time w.r.t SCK sampling edge
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
1.
Data based on characterisation results, not tested in production.
0
0 t
PCLK
+15ns t
PCLK
+15ns
2t
PCLK
2t
PCLK
2t
PCLK
2t
PCLK
2t
PCLK
2t
PCLK
0
0
3t
PCLK
+15 ns
3t
PCLK
+15 ns
2.66 MHz
(f
PLCK
/12)
3t
PCLK
+30 ns
3t
PCLK
+30 ns
3t
PCLK
+15 ns
3t
PCLK
+15 ns
15
30
Figure 33.
SPI configuration, slave mode with CPHA=0, single transfer
NSS
INPUT t su(NSS) t h(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1 sample edge trigger edge t c(SCK) sample edge trigger edge t
NSSLQV t w(SCKH) t w(SCKL) t
SCKQV(MISO) t r(SCK) t f(SCK) t
SCKQX(MISO)
MHz ns t
NSSHQZ z z t su(SI) t h(SI)
MOSI
INPUT
DONT CARE MSB IN BIT1 IN LSB IN DONT CARE
65/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 34.
SPI configuration - slave mode with CPHA=0, continuous transfer
1.5*t c(SCK) t c(SCK)
1.5*t c(SCK)
NSS
INPUT sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
CPOL=0
CPOL=1
MISO
OUTPUT z t
NSSLQV
MSB OUT LSB OUT t
NSHQZ t
NSSLQV z
MSB OUT
DONT CARE MSB IN LSB IN DONT CARE MSB IN
MOSI
INPUT
FRAME 1 FRAME 2
Figure 35.
SPI configuration, slave mode with CPHA=1, single transfer
NSS
INPUT t su(NSS) t h(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1 trigger edge sample edge t c(SCK) trigger edge sample edge t w(SCKH) t w(SCKL) t r(SCK) t f(SCK) t
NSSLQV t
SCKQV(MISO) t
SCKQX(MISO)
MISO
OUTPUT z
MSB OUT
BIT OUT LSB OUT t
NSSHQX t
NSSHQZ z
MOSI
INPUT
DONT CARE t su(SI)
MSB IN t h(SI)
BIT1 IN LSB IN
DONT
CARE
Figure 36.
SPI configuration - slave mode with CPHA=1, continuous transfer
t c(SCK)
NSS
OUTPUT trigger sample trigger sample trigger sample trigger samlpe trigger sample trigger sample trigger sample trigger sample trigger
CPOL=0
CPOL=1
1 OR 0 MSB OUT
MOSI
OUTPUT
MISO
INPUT
DONT CARE MSB IN
FRAME 1
LSB OUT MSB OUT
LSB IN MSB IN
FRAME 2
66/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Figure 37.
TI configuration - slave mode, single transfer
NSS
INPUT
SCK
INPUT
MOSI
INPUT
MISO
OUTPUT t su(NSS) t c(SCK)
/2 t c(SCK) trigger edge sample edge trigger edge sample edge trigger edge sample edge
DONT CARE t w(SCKH) t f(SCK) t su(MOSI) t w(SCKL) t h(MOSI) t r(SCK)
MSB IN LSB IN t
SCKQV t
SCKQX t t
SCKQZ c(SCK)
/2
DONT CARE z
1 OR 0 MSB OUT LSB OUT z
Figure 38.
TI configuration - slave mode, continuous transfer
t su(NSS) t c(SCK) t h(NSS) t c(SCK)
NSS
OUTPUT trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
SCK
OUTPUT
MOSI
INPUT
DONT CARE MSB IN
MISO
OUTPUT
1 OR 0 MSB OUT
FRAME 1
LSB IN MSB IN LSB IN DONT CARE
LSB OUT MSB OUT
FRAME 2
LSB OUT
67/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
SMI - serial memory interface
Subject to general operating conditions with C
L
≈
30 pF.
Table 40.
SMI characteristics
(1)
Symbol Parameter
f
SMI_CK
SMI clock frequency
Min
t r(SMI_CK) t f(SMI_CK) t v(SMI_DOUT) t h(SMI_DOUT) t v(SMI_CSSx) t h(SMI_CSSx) t su(SMI_DIN) t h(SMI_DIN)
SMI clock rise time
SMI clock fall time
Data output valid time
Data output hold time
CSS output valid time
CSS output hold time
Data input setup time
Data input hold time
1.
Data based on characterisation results, not tested in production.
2.
Max. frequency = f
PCLK
/2 = 64/2 = 32 MHz.
3.
Valid for all temperature ranges: -40 to 105 °C, with 30 pF load capacitance.
4.
Valid up to 60 °C, with 10 pF load capacitance.
Figure 39.
SMI timing diagram
t c(SMI_CK)
SMI_CK
OUTPUT t w(SMI_CKH) t w(SMI_CKL)
0
5 t r(SMI_CK) t f(SMI_CK) t su(SMI_DIN) t h(SMI_DIN)
SMI_DIN
INPUT BIT6 IN LSB IN t v(SMI_DOUT)
MSB IN t h(SMI_DOUT)
Max
32
(2)(3)
48
(4)
10
8
10
0
10
0
SMI_DOUT
OUTPUT t v(SMI_CSS)
MSB OUT t h(SMI_CSS)
BIT6 OUT LSB OUT
SMI_CSSX
OUTPUT
Unit
MHz ns
I
2
C - Inter IC control interface
Subject to general operating conditions for V
DD_IO
, f
PCLK
, and T
A
unless otherwise specified.
The I
2
C interface meets the requirements of the Standard I
2
C communication protocol described in the following table with the restriction mentioned below:
Restriction: The I/O pins which SDA and SCL are mapped to are not “True” Open-
Drain: when configured as open-drain, the PMOS connected between the I/O pin and
V
DD_IO
is disabled, but it is still present. Also, there is a protection diode between the
I/O pin and V
DD_IO
. Consequently, when using this I
2
C in a multi-master network, it is
68/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
not possible to power off the STR7x while some another I
2
C master node remains powered on: otherwise, the STR7x will be powered by the protection diode.
Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).
Table 41.
SDA and SCL characteristics
Symbol Parameter
Standard mode
I
2
C
Fast mode I
2
C
(1)
Unit
Min
(2)
t w(SCLL) t w(SCLH) t su(SDA) t h(SDA) t r(SDA) t r(SCL) t f(SDA) t f(SCL)
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
SDA and SCL rise time
SDA and SCL fall time
4.7
4.0
250
0
(3)
1000
300
1.3
0.6
100
0
(4)
20+0.1C
20+0.1C
b b
300
300
μs ns t h(STA) t su(STA) t su(STO) t w(STO:STA)
START condition hold time
Repeated START condition setup time
STOP condition setup time
STOP to START condition time (bus free)
4.0
4.7
4.0
4.7
0.6
0.6
0.6
1.3
μs
μs
μs
C b
Capacitive load for each bus line 400 400
1.
f
PCLK
, must be at least 8 MHz to achieve max fast I
2
C speed (400 kHz).
2.
Data based on standard I
2
C protocol requirement, not tested in production.
3.
The maximum hold time t h(SDA)
is not applicable
4.
The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
pF
Figure 40.
Typical application with I
2
C bus and timing diagram
V
DD
V
DD
4.7k
Ω
4.7k
Ω
100
Ω
SDA
I
2
C BUS
100
Ω
SCL
STRT75X
REPEATED START
START t su(STA) t w(STO:STA)
START
SDA t f(SDA) t r(SDA) t su(SDA) t h(SDA)
SCL t h(STA) t w(SCKH) t w(SCKL) t r(SCK) t f(SCK)
1.
Measurement points are done at CMOS levels: 0.3xV
DD
and 0.7xV
DD
.
t su(STO)
STOP
69/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
The USB interface is USB-IF certified (Full Speed).
Table 42.
USB startup time
Symbol Parameter Conditions Max
1
Unit
µs t
STARTUP
USB transceiver startup time
Table 43.
USB characteristics
USB DC Electrical Characteristics
Symbol Parameter Conditions Min.
(1)(2)
Unit
V
DI
V
CM
Differential Input Sensitivity
Differential Common Mode
Range
Input Levels
I(DP, DM)
Includes V
DI range
0.2
0.8
2.5
V
SE
Single Ended Receiver
Threshold
1.3
2.0
V
OL
V
OH
Static Output Level Low
Static Output Level High
Output Levels
R
L
of 1.5 k
R
L
of 15 k
Ω
to 3.6V
Ω
to V
SS
(3)
2.8
0.3
3.6
1.
All the voltages are measured from the local ground potential.
2.
It is important to be aware that the DP/DM pins are not 5 V tolerant. As a consequence, in case of a a shortcut with Vbus (typ: 5.0V), the protection diodes of the DP/DM pins will be direct biased . This will not damage the device if not more than 50 mA is sunk for longer than 24 hours but the reliability may be affected.
3.
R
L
is the load connected on the USB drivers
V
Figure 41.
USB: data signal rise and fall time
V
Differential
Data Lines
V
CRS
Crossover points
V
SS t f t r
Table 44.
Symbol
t t f r
USB: Full speed electrical characteristics
Parameter Conditions
Rise time
Fall Time
(1)
1)
Driver characteristics:
C
L
=50 pF
C
L
=50 pF
Min
4
4
Max
20
20
Unit
ns ns
70/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 44.
Symbol
USB: Full speed electrical characteristics
Parameter Conditions Min Max Unit
t rfm
V
CRS
Rise/ Fall Time matching
Output signal Crossover Voltage t r
/t f
90
1.3
110
2.0
1.
Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
%
V
71/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Subject to general operating conditions for V
DDA_ADC
, f
PCLK
, and T
A
unless otherwise specified.
Table 45.
10-bit ADC characteristics
Symbol Parameter Conditions Min Typ
(1)
Max Unit
f
ADC
V
AIN
R
AIN
ADC clock frequency
Conversion voltage range
External input impedance
(2)
(3)(4)
V
0.4
SSA_ADC
V
8
DDA_ADC
10
MHz k
V
Ω
C
AIN
External capacitor on analog input
6.8
pF
I lkg
Induced input leakage current
+400 µA injected on any pin
-400 µA injected on any pin except specific adjacent pins in
-400µA injected on specific adjacent pins in
40
1
1
μA
μA
μA
C
ADC
Internal sample and hold capacitor
3.5
pF t t
CAL
CONV
Calibration Time
Total Conversion time
(including sampling time)
f
f
CK_ADC
CK_ADC
=8 MHz
=8 MHz
725.25
5802
3.75
30 (11 for sampling + 19 for
Successive Approximation)
1/f
μs
1/f
ADC
μs
ADC
I
ADC
Sunk on
V
DDA_ADC
3.7
mA
1.
Unless otherwise specified, typical data are based on T
A and are not tested.
=25°C. They are given only as design guidelines
2.
Calibration is needed once after each power-up.
3.
C
PARASITIC
represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus f the pad capacitance (3 pF). A high C
PARASITIC
ADC
should be reduced.
value will downgrade conversion accuracy. To remedy this,
4.
Depending on the input signal variation (f
AIN
), C
AIN
can be increased for stabilization time and reduced to allow the use of a larger serial resistor (R
AIN
). It is valid for all f
ADC
frequencies
≤ 8 MHz.
72/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
ADC accuracy vs. negative injection current
Injecting negative current on specific pins listed in
(generally adjacent to the analog input pin being converted) should be avoided as this significantly reduces the accuracy of the conversion being performed. It is recommended to add a Schottky diode (pin to ground) to pins which may potentially inject negative current.
Table 46.
List of adjacent pins
Analog input
a
AIN1/P0.03
AIN2/P0.12
AIN3/P0.17
AIN4/P0.19
AIN5/P0.22
AIN6/P0.23
AIN7/P0.27
AIN8/P0.29
AIN9/P1.04
AIN10/P1.06
AIN11/P1.08
AIN12/P1.11
AIN13/P1.12
AIN14/P1.13
AIN15/P1.14
None
None
P0.11
P0.18 and P0.16
P0.24
None
P2.04
P1.11 and P0.26
P0.30 and P0.28
None
P1.05
P1.04 and P1.13
P2.17 and P0.27
None
P1.14 and P1.01
None
Related adjacent pins
Figure 42.
Typical application with ADC
V
DD
STR75XX
V
T
0.6V
V
AIN
R
AIN
C
AIN
AINx
V
T
0.6V
2k
Ω(max)
10-Bit A/D
Conversion
I
L
±1
μA
C
ADC
3.2pF
Analog power supply and reference pins
The V
DDA_ADC
and V
SSA_ADC pins are the analog power supply of the A/D converter cell.
Separation of the digital and analog power pins allow board designers to improve A/D performance. Conversion accuracy can be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines (see
: General PCB design guidelines on page 74
73/84
Electrical parameters STR750Fxx STR751Fxx STR752Fxx STR755Fxx
General PCB design guidelines
To obtain best results, some general design and layout rules should be followed when designing the application PCB to shield the noise-sensitive, analog physical interface from noise-generating CMOS logic signals.
● Use separate digital and analog planes. The analog ground plane should be connected to the digital ground plane via a single point on the PCB.
●
●
Filter power to the analog power planes. It is recommended to connect capacitors, with good high frequency characteristics, between the power and ground lines, placing
0.1 µF and optionally, if needed 10 pF capacitors as close as possible to the STR7 power supply pins and a 1 to 10 µF capacitor close to the power source (see
).
The analog and digital power supplies should be connected in a star network. Do not use a resistor, as V
DDA_ADC
is used as a reference voltage by the A/D converter and any resistance would cause a voltage drop and a loss of accuracy.
●
Properly place components and route the signal traces on the PCB to shield the analog inputs. Analog signals paths should run over the analog ground plane and be as short as possible. Isolate analog signals from digital signals that may switch while the analog inputs are being sampled by the A/D converter. Do not toggle digital outputs near the
A/D input being converted.
Software filtering of spurious conversion results
For EMC performance reasons, it is recommended to filter A/D conversion outliers using software filtering techniques.
Figure 43.
Power supply filtering
1 to 10
μF
STR7
DIGITAL NOISE
FILTERING
V
DD
0.1
μF
V
SS
V
DD_IO
STR75XX
POWER
SUPPLY
SOURCE
(3.3V or 5.0V)
0.1
μF
V
DDA_ADC
EXTERNAL
NOISE
FILTERING
V
SSA_ADC
74/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters
Table 47.
ADC accuracy
ADC accuracy with f
CK_SYS
= 20 MHz, f
ADC
=8 MHz, R
AIN
< 10 k
Ω
This assumes that the ADC is calibrated
(1)
Symbol Parameter Conditions Typ Max Unit
|E
|E
E
|E
|E
T
O
G
D
L
|
|
|
|
Total unadjusted error
Offset error
Gain Error
Integral linearity error
(2) (3)
V
DDA_ADC
=3.3 V
V
DDA_ADC
=5.0 V
V
DDA_ADC
=3.3 V
V
DDA_ADC
=5.0 V
V
DDA_ADC
=3.3 V
V
DDA_ADC
=5.0 V
V
DDA_ADC
=3.3 V
V
DDA_ADC
=5.0 V
V
DDA_ADC
=3.3 V
V
DDA_ADC
=5.0 V
1
1
0.15
0.15
-0.8
-0.8
0.7
0.7
0.6
0.6
1.2
1.2
0.5
0.5
-0.2
-0.2
0.9
0.9
0.8
0.8
LSB
1.
Calibration is needed once after each power-up.
2.
ADC accuracy vs. negative injection current on page 73
3.
ADC Accuracy vs. MCO (Main Clock Output): the ADC accuracy can be significantly degraded when activating the MCO on pin P0.01 while converting an analog channel (especially those which are close to the MCO pin). To avoid this, when an ADC conversion is launched, it is strongly recommended to disable the MCO.
Figure 44.
ADC accuracy characteristics
Digital Result ADCDR
1023
1022
1021
1LSB
IDEAL
=
V
DDA
– V
1024
(2)
E
T
(3)
7
6
5
4
3
2
1
E
O
E
L
1 LSB
IDEAL
E
D
(1)
E
G
0
V
SSA
1 2 3 4 5 6 7 1021 1022 1023 1024
V
DDA
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
E
T
=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves.
E
O
=Offset Error: deviation between the first actual transition and the first ideal one.
E
G
=Gain Error: deviation between the last ideal transition and the last actual one.
E
D
=Differential Linearity Error: maximum deviation between actual steps and the ideal one.
E
L
=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line.
Vin
75/84
Package characteristics STR750Fxx STR751Fxx STR752Fxx STR755Fxx
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at:
www.st.com
.
ECOPACK
®
is an ST trademark.
7.1 Package mechanical data
Figure 45.
64-pin low profile quad flat package (10x10)
D
D1
D3
0.10mm
.004
seating plane
M x 45°
PIN 1
IDENTIFICATION
E3 E1 E
L1
L
B e
A
A2
A1 c
K
L
L1
D1
E
E1 e
Dim.
mm
Min Typ Max Min inches
(1)
Typ Max
A
A1
0.05
1.60
0.15 0.0020
0.0630
0.0059
A2
1.35
1.40
1.45 0.0531 0.0551 0.0571
b
0.17
0.22
0.27 0.0067 0.0087 0.0106
C
D
0.09
12.00
0.20 0.0035
0.4724
0.0079
N
0°
10.00
12.00
10.00
0.50
3.5° 7°
64
0°
0.3937
0.4724
0.3937
0.0197
3.5° 7°
0.45
0.60
0.75 0.0177 0.0236 0.0295
1.00
0.0394
Number of pins
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
K
76/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Package characteristics
Figure 46.
100-pin low profile flat package (14x14)
D
D1
E1 E
L1
L b e
A1
A
A2
θ c
mm inches
(1)
Dim.
Min Typ Max Min Typ Max
A
A1
0.05
1.60
0.15 0.0020
0.0630
0.0059
A2
1.35
1.40
1.45 0.0531 0.0551 0.0571
b
0.17
0.22
0.27 0.0067 0.0087 0.0106
C
0.09
D
0.20 0.0035
16.00
0.6299
0.0079
D1
E
14.00
16.00
0.5512
0.6299
E1
14.00
0.5512
e
θ
0°
0.50
3.5° 7° 0°
0.0197
3.5° 7°
L
0.45
0.60
0.75 0.0177 0.0236 0.0295
L1
1.00
N
0.0394
Number of Pins
100
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 47.
64-ball low profile fine pitch ball grid array package mm inches
(1)
Dim.
Min Typ Max Min Typ Max
A
1.210
A1 0.270
1.700 0.0476
0.0106
0.0669
A2
1.120
0.0441
b
0.450 0.500 0.550 0.0177 0.0197 0.0217
D
7.750 8.000 8.150 0.3051 0.3150 0.3209
D1
5.600
0.2205
E
7.750 8.000 8.150 0.3051 0.3150 0.3209
E1
5.600
0.2205
e
0.720 0.800 0.880 0.0283 0.0315 0.0346
f
1.050 1.200 1.350 0.0413 0.0472 0.0531
ddd
0.120
Number of Pins
0.0047
N
64
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
77/84
Package characteristics STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 48.
100-ball low profile fine pitch ball grid array package mm inches
(1)
Dim.
E
E1 e
F ddd eee fff
A4 b
D
D1
A
A1
A2
A3
Min Typ Max Min Typ Max
1.700
0.0669
0.270
0.0106
1.085
0.30
0.0427
0.0118
0.80
0.0315
0.55
0.0177 0.0197 0.0217
0.45
0.50
9.85
10.00
10.15
0.3878 0.3937 0.3996
7.20
0.2835
9.85
10.00
10.15
0.3878 0.3937 0.3996
7.20
0.2835
0.80
1.40
0.0315
0.055
0.12
0.15
0.08
Number of Balls
100
0.005
0.006
0.003
N
1.
Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 49.
Recommended PCB design rules (0.80/0.75mm pitch BGA)
Dpad
Dsm
0.37 mm
0.52 mm typ. (depends on solder mask registration tolerance
Solder paste 0.37 mm aperture diameter
– Non solder mask defined pads are recommended
– 4 to 6 mils screen print
Dpad
Dsm
78/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Package characteristics
The maximum chip junction temperature (T
Jmax
) must never exceed the values given in
Table 10: General operating conditions on page 34
.
The maximum chip-junction temperature, T
Jmax
, in degrees Celsius, may be calculated using the following equation:
T
Jmax
= T
Amax
+ (P
Dmax
x
Θ
JA
)
Where:
– T
Amax
is the maximum Ambient Temperature in
°C,
–
Θ
JA
is the Package Junction-to-Ambient Thermal Resistance, in
° C/W,
– P
Dmax
is the sum of P
INTmax
and P
I/Omax
(P
Dmax
= P
INTmax
+ P
I/Omax
),
– P
INTmax
is the product of I
DD and V
DD
, expressed in Watts. This is the maximum chip internal power.
– P
I/Omax
represents the maximum Power Dissipation on Output Pins.
Where:
P
I/Omax
=
Σ (V
OL
*I
OL
) +
Σ((V
DD
-V
OH
)*I
OH
), taking into account the actual V level in the application.
OL
/ I
OL and V
OH
/ I
OH
of the I/Os at low and high
Table 48.
Thermal characteristics
(1)
Symbol Parameter Value
Θ
Θ
Θ
Θ
JA
JA
JA
JA
Thermal Resistance Junction-Ambient
LQFP 100 - 14 x 14 mm / 0.5 mm pitch
Thermal Resistance Junction-Ambient
LQFP 64 - 10 x 10 mm / 0.5 mm pitch
Thermal Resistance Junction-Ambient
LFBGA 64 - 8 x 8 x 1.7mm
Thermal Resistance Junction-Ambient
LFBGA 100 - 10 x 10 x 1.7mm
46
45
58
41
1.
Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment.
Unit
°C/W
°C/W
°C/W
°C/W
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
79/84
Package characteristics STR750Fxx STR751Fxx STR752Fxx STR755Fxx
When ordering the microcontroller, the temperature range is specified in the order code
Table 49: Order codes on page 81
.
The following example shows how to calculate the temperature range needed for a given application.
Assuming the following application conditions:
I
Maximum ambient temperature T
Amax
= 82 °C (measured according to JESD51-2),
DDmax
=8 mA, V
DD
= 5 V, maximum 20 I/Os used at the same time in output at low level with I
OL
= 8 mA, V
OL
= 0.4 V
P
INTmax
= 8 mA x 5 V= 400 mW
P
IOmax
= 20 x 8 mA x 0.4V = 64 mW
This gives: P
INTmax
= 400 mW and P
IOmax
64 mW:
P
Dmax
= 400 mW + 64 mW
Thus: P
Dmax
= 464 mW
Using the values obtained in
T
Jmax
is calculated as follows:
– For LQFP100, 46°C/W
T
Jmax
= 82° C + (46° C/W x 464 mW) = 82°C + 21°C = 103° C
This is within the range of the suffix 6 version parts (-40 < T
J
< 105° C).
In this case, parts must be ordered at least with the temperature range suffix 6
Table 49: Order codes on page 81
).
– For BGA64, 58°C/W
T
Jmax
= 82° C + (58° C/W x 464 mW) = 82°C + 27°C = 109° C
This is within the range of the suffix 7 version parts (-40 < T
J
< 125° C).
In this case, parts must be ordered at least with the temperature range suffix 7
Table 49: Order codes on page 81
).
Figure 50.
LQFP100 P
Dmax
vs T
A
700
600
500
400
300
200
100
0
75 85 95
105 115 125
T
A
(° C)
Suffix 6
Suffix 7
80/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Order codes
Table 49.
Order codes
Order code
Flash Prog.
Memory
(Bank 0)
Kbytes
STR750FV0T6
STR750FV1T6
STR750FV2T6
STR750FV0H6
STR750FV1H6
STR750FV2H6
STR751FR0T6
STR751FR1T6
STR751FR2T6
STR751FR0H6
STR751FR1H6
STR751FR2H6
STR752FR0T6
STR752FR1T6
STR752FR2T6
STR752FR0H6
STR752FR1H6
STR752FR2H6
STR752FR0T7
STR752FR1T7
STR752FR2T7
STR752FR0H7
STR752FR1H7
STR752FR2H7
STR755FR0T6
STR755FR1T6
STR755FR2T6
STR755FR0H6
STR755FR1H6
STR755FR2H6
64
128
256
64
128
256
64
128
256
64
128
256
64
128
256
64
128
256
128
256
64
128
256
64
128
256
64
64
128
256
Package
LQFP100 14x14
LFBGA100 10x10
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
LQFP64 10x10
LFBGA64 8x8
CAN
Periph
USB
Periph
Nominal
Temp. Range
(T
A
)
Yes
-
Yes
Yes
-
Yes
Yes
-
-
-
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +105°C
-40 to +85°C
81/84
Order codes STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 49.
Order codes (continued)
Order code
Flash Prog.
Memory
(Bank 0)
Kbytes
STR755FV0T6
STR755FV1T6
STR755FV2T6
STR755FV0H6
STR755FV1H6
STR755FV2H6
64
128
256
64
128
256
Package
LQFP100 14x14
LFBGA100 10x10
CAN
Periph
USB
Periph
Nominal
Temp. Range
(T
A
)
-40 to +85°C
82/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Revision history
Table 50.
Document revision history
Date Revision
25-Sep-2006
30-Oct-2006
04-Jul-2007
23-Oct-2007
17-Feb-2009
1
2
3
4
5
Description of Changes
Initial release
Added power consumption data for 5V operation in
Changed datasheet title from STR750F to STR750FXX STR751Fxx
STR752Fxx STR755xx.
Added
Table 1: Device summary on page 1
Added note 1 to
Added STOP mode IDD max. values in
Updated XT2 driving current in
Updated RPD in
Table 21: XRTC1 external clock source on page 45
Table 34: Output speed on page 57
Added characteristics for
SSP synchronous serial peripheral in master mode (SPI or TI mode) on page 62
SSP synchronous serial peripheral in slave mode (SPI or TI mode) on page 65
Added characteristics for
SMI - serial memory interface on page 68
Added
Table 42: USB startup time on page 70
Section 6.2.3: Thermal characteristics on page 33
Updated P
D
, T
J
and T
A
in
Section 6.3: Operating conditions on page 34
Table 20: XT1 external clock source on page 44
Table 21: XRTC1 external clock source on page 45
Section 7: Package characteristics on page 76
(inches rounded to 4 decimal digits instead of 3)
Section 8: Order codes on page 81
Table 8: Current characteristics on page 33
Added AHB clock frequency for write access to Flash registers in
Table 10: General operating conditions on page 34
Table 41: SDA and SCL characteristics on page 69
83/84
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
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