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DATASHEET
4A Low Quiescent Current High Efficiency Synchronous
Buck Regulator
ISL78214
The ISL78214 is a high efficiency, monolithic, synchronous step-down DC/DC converter that can deliver up to 4A continuous output current from a 2.8V to 5.5V input supply. It uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability.
The ISL78214 integrates a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 400mV dropout voltage at 4A output current. High 1MHz Pulse-width Modulation (PWM) switching frequency, that can be synchronization up to 4MHz with an external clock, allows the use of small external components and SYNC input enables multiple ICs to synchronize out of phase to reduce ripple and eliminate beat frequencies.
The ISL78214 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference while discontinuous mode provides high efficiency by reducing switching losses at light loads.
Fault protection is provided by internal hiccup mode current limiting during short circuit and overcurrent conditions, an output overvoltage comparator and over-temperature monitor circuit. A power-good output voltage monitor indicates when the output is in regulation.
The ISL78214 is offered in a space saving 4x4 QFN lead free package with exposed pad lead frames for low thermal.
The ISL78214 offers a 1ms Power-good (PG) timer at power-up. When shutdown, ISL78214 discharges the output capacitor. Other features include internal soft-start, internal compensation, overcurrent protection and thermal shutdown.
Features
• High efficiency synchronous buck regulator with up to 97% efficiency
• Power-good (PG) output with a 1ms delay
• 2.8V to 5.5V supply voltage
• 2% output accuracy over-temperature/load/line
• 4A output current
• Pin compatible to ISL78213
• Start-up with prebiased output
• Internal soft-start - 1ms
• Soft-stop output discharge during disable
• 35µA quiescent supply current in PFM mode
• Selectable forced PWM mode and PFM mode
• External synchronization up to 4MHz
• Less than 1µA logic controlled shutdown current
• 100% maximum duty cycle
• Internal current mode compensation
• Peak current limiting and hiccup mode short circuit protection
• Over-temperature protection
• Small 16 Ld 4mmx4mm QFN
• Pb-free (RoHS compliant)
• AEC-Q100 qualified
Applications
• Automotive power
• DC/DC POL modules
• µC/µP, FPGA and DSP power
The ISL78214 is offered in a 16 Ld 4mmx4mm QFN package with 1mm maximum height. The complete converter occupies less than 0.4in
2
area.
The ISL78214 is AEC-Q100 qualified. The ISL78214 is rated for the automotive temperature range -40°C to +105°C.
Related Literature
• AN1366 , “ISL8014AEVAL2Z: 4A Low Quiescent Current
1MHz High Efficiency Synchronous Buck Regulator”
May 12, 2015
FN7551.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
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ISL78214
Ordering Information
PART NUMBER
(
)
ISL78214ARZ
PART
MARKING
782 14ARZ
TEMP. RANGE
(°C)
-40 to +105
PACKAGE
(RoHS Compliant)
16 Ld 4x4 QFN
PKG.
DWG. #
L16.4x4
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78214 . For more information on MSL please see techbrief TB363 .
Pin Configuration
ISL78214
(16 LD QFN)
TOP VIEW
VIN 1
VIN 2
VDD 3
SYNCH 4
16 15 14 13
PD
12 PGND
11 PGND
10 SGND
9 SGND
5 6 7 8
Pin Descriptions
PIN NUMBER
1, 2
3
5
PIN NAME
VIN
VDD
EN
7
4
PG
SYNCH
14, 15
11, 12
9, 10
8
6, 13, 16
PD
LX
PGND
SGND
VFB
NC
Exposed Pad
Refer to Application Note AN1366 for more layout suggestions.
DESCRIPTION
Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
Input supply voltage for the analog circuitry. Connect to VIN pin.
Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do not leave this pin floating.
1ms timer output. At power-up or EN HI, this output is a 1ms delayed power-good signal for the output voltage.
Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the negative edge trigger. Do not leave this pin floating.
Switching node connection. Connect to one terminal of the inductor.
Power ground
Signal ground
Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage. For 0.8V output voltage, connect this pin to the output.
No connect
The exposed pad must be connected to the SGND pin for proper electrical performance. Place as much vias as possible under the pad connecting to SGND plane for optimal thermal performance.
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FN7551.3
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ISL78214
Typical Application
INPUT 2.8V TO 5.5V
C
1
2 x 22µF
R
1
100k
VIN
VDD
ISL78214
LX
PGND
L
1.5µH
C
2
2 x 22µF
R
2
124k
OUTPUT
1.8V
C
3
47pF
EN
VFB
PG
R
3
100k
SYNCH SGND
FIGURE 1. TYPICAL APPLICATION DIAGRAM
Block Diagram
EN
SOFT
START
SHUTDOWN
BANDGAP
0.8V
-
+
EAMP
-
3pF
+
SYNCH
SHUTDOWN 27pF
390k
-
+
COMP
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
VFB
6k
SLOPE
COMP
CSA
-
+
OCP
-
1.4V
0.736V
-
+
+
SKIP
-
PG
SGND
1ms
DELAY
0.5V
ZERO-CROSS
SENSING
0.2V
-
SCP
+
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
VIN
LX
PGND
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ISL78214
Absolute Maximum Ratings
(Reference to GND)
VIN, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
LX . . . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6.5V (DC) or 7V (20ms)
VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.8V
ESD Ratings
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . 3000V
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . 2000V
Machine Model (Tested per AEC-Q100-003). . . . . . . . . . . . . . . . . . . 250V
Latch-up (Tested per AEC-Q100-004, ClassII, Level A). . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
16 Ld QFN Package ( Notes 4 , 5 ) . . . . . . . .
JA
(°C/W)
JC
39
(°C/W)
3
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 4A
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -40
°
C to +105
°
C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 .
5.
JC
, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions unless otherwise noted: T
A at T
A
= -40°C to +105°C, V
= +25°C. Boldface limits apply across the operating temperature range, -40°C to +105°C.
IN
= 3.6V, EN = VDD. Typical values are
PARAMETER SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
V
DD
Undervoltage Lockout Threshold V
UVLO
Quiescent Supply Current
Shutdown Supply Current
I
VIN
I
SD
Rising, no load
Falling, no load
SYNCH = GND, no load at the output
SYNCH = GND, no load at the output and no switches switching
SYNCH = VDD, F
S
= 1MHz, no load at the output
V
IN
= 5.5V, EN = low, T
A
= +85°C
V
IN
= 5.5V, EN = low, T
A
= +105°C
-
-
-
-
2.15
-
-
2.6
2.35
35
30
6.5
0.1
0.1
10
4
10
2.8
-
-
45 mA
µA
µA
V
V
µA
µA
OUTPUT REGULATION
Reference Voltage
VFB Bias Current
Line Regulation
Soft-start Ramp Time Cycle
OVERCURRENT PROTECTION
Current Limit Blanking Time
Overcurrent and Auto Restart Period
Switch Current Limit
Peak Skip Limit
COMPENSATION
Error Amplifier Transconductance
Transresistance
V
REF
I
VFB t
OCON t
OCOFF
I
LIMIT
I
SKIP
RT
VFB = 0.75V
V
IN
= V
O
+ 0.5V to 5.5V (minimal 2.8V)
(
(
0.790
-
-
-
-
-
4.9
-
-
0.17
0.8
0.1
0.2
1
17
4
6.0
1.3
20
0.20
0.810
-
-
-
-
-
7.1
-
-
0.23
V
µA
%/V ms
Clock pulses
SS cycle
A
A
µA/V
Ω
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FN7551.3
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ISL78214
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions unless otherwise noted: T
A at T
A
= -40°C to +105°C, V
= +25°C. Boldface limits apply across the operating temperature range, -40°C to +105°C. (Continued)
IN
= 3.6V, EN = VDD. Typical values are
PARAMETER SYMBOL TEST CONDITIONS
MIN
( Note 7 ) TYP
MAX
( Note 7 ) UNIT
LX
P-Channel MOSFET ON-resistance
N-Channel MOSFET ON-resistance
LX Maximum Duty Cycle
PWM Switching Frequency
LX Minimum On-time
PG f
S
V
V
V
V
IN
= 5V, I
IN
= 5V, I
O
= 200mA
IN
= 2.8V, I
O
= 200mA
O
= 200mA
IN
= 2.8V, I
O
= 200mA
SYNCH = High
-
-
-
-
-
0.80
-
50
70
50
70
100
1.0
-
75
100
75
100
-
1.20
140 mΩ mΩ mΩ mΩ
MHz ns
Output Low Voltage
Delay Time (Rising Edge)
PG Pin Leakage Current
PGOOD Rising Threshold
Sinking 1mA
PG = V
IN
= 3.6V
Percentage of regulation voltage
Percentage of regulation voltage
-
0.65
-
89
-
1
0.01
92
0.3
1.35
2
95
V ms
µA
%
PGOOD Falling Threshold
PGOOD Delay Time (Falling Edge)
EN, SYNCH
Logic Input Low
Logic Input High
Synch Logic Input Leakage Current
Enable Logic Input Leakage Current
Thermal Shutdown
I
SYNCH
I
EN
Pulled up to 5.5V
85
-
-
-
-
-
1.4
88
15
-
-
0.1
0.1
140
91
-
0.4
-
4
4
-
%
µs
V
V
µA
µA
°C
Thermal Shutdown Hysteresis 25 °C
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
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ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A.
A
= +25°C, V
VIN
= 2.5V to 5.5V,
100 100
90
90
80
70
60
2.5V
OUT-PWM
1.8V
OUT-PWM
1.5V
OUT-PWM
1.2V
OUT-PWM
80
70
60
2.5V
OUT-PFM
1.8V
OUT-PFM
1.5V
OUT-PFM
1.2V
OUT-PFM
50
50
40
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 V
IN
PWM)
4.0
40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 V
IN
PFM)
100
90
80
70
60
2.5V
OUT-PWM
1.8V
OUT-PWM
3.3V
OUT-PWM
1.5V
OUT-PWM
1.2V
OUT-PWM
50
40
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5V
IN
PWM)
4.0
100
90
80
70
60
2.5V
OUT-PFM
3.3V
OUT-PFM
1.2V
OUT-PFM
1.5V
OUT-PFM
1.8V
OUT-PFM
50
40
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
OUTPUT LOAD (A)
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5V
IN
PFM)
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
5V
IN-PWM
3.3V
IN-PFM
5V
IN-PFM
3.3V
IN-PWM
0.00
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
4.0
FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, V
OUT
= 1.8V)
125
100
75
50
25
0
2.0
2.5
3.0
3.5
V
IN
(V)
4.0
4.5
5.0
FIGURE 8. POWER DISSIPATION WITH NO LOAD vs V
IN
V
OUT
= 1.8V)
(PWM
5.5
Submit Document Feedback 6
FN7551.3
May 12, 2015
ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
A
= +25°C, V
VIN
= 2.5V to 5.5V,
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A. (Continued)
0.25
1.24
0.20
0.15
0.10
0.05
1.23
1.22
3.3V
IN-PFM
1.21
1.20
1.19
1.18
1.17
5V
IN-PFM
5V
IN-PWM
3.3V
IN-PWM
0
2.0
2.5
3.0
3.5
4.0
V
IN
(V)
4.5
5.0
FIGURE 9. POWER DISSIPATION WITH NO LOAD vs V
IN
(PFM V
OUT
= 1.8V)
5.5
1.16
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 10. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 1.2V)
4.0
1.55
1.54
1.53
1.52
1.51
1.50
1.49
3.3V
IN-PFM
5V
IN-PFM
5V
IN-PWM
3.3V
IN-PWM
1.48
1.47
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 11. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 1.5V)
4.0
1.83
1.82
3.3V
IN-PFM
1.81
1.80
1.79
1.78
1.77
1.76
5V
IN-PFM
5V
IN-PWM
3.3V
IN-PWM
1.75
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 12. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 1.8V)
4.0
2.52
2.51
2.50
3.3V
IN-PFM
2.49
2.48
3.3V
IN-PWM
2.47
5V
IN-PWM
2.46
2.45
5V
IN-PFM
2.44
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 13. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 2.5V)
4.0
3.36
3.35
3.34
3.33
3.32
5V
IN-PWM
4.5V
IN-PWM
3.31
3.30
5V
IN-PFM
4.5V
IN-PFM
3.29
3.28
0.0
0.5
1.0
1.5
2.0
2.5
OUTPUT LOAD (A)
3.0
3.5
FIGURE 14. V
OUT
REGULATION vs LOAD (1MHz, V
OUT
= 3.3V)
4.0
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ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
A
= +25°C, V
VIN
= 2.5V to 5.5V,
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A. (Continued)
1.83
1.83
1.82
1.82
1.81
1.80
4A LOAD PWM
0A LOAD PWM
1.81
1.80
4A LOAD
0A LOAD
1.79
1.78
1.77
1.79
1.78
1.77
1.76
1.76
1.75
2.0
2.5
3.0
3.5
4.0
INPUT VOLTAGE (V)
4.5
FIGURE 15. OUTPUT VOLTAGE REGULATION vs V
IN
(PWM V
OUT =
1.8)
5.0
5.5
1.75
2.0
2.5
3.0
3.5
4.0
INPUT VOLTAGE (V)
4.5
FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN
(PFM V
OUT
= 1.8V)
5.0
5.5
LX 2V/DIV
V
OUT
RIPPLE 20mV/DIV
IL 0.5A/DIV
FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM)
LX 2V/DIV
IL 2A/DIV
V
OUT
RIPPLE 20mV/DIV
FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD
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LX 2V/DIV
V
OUT
RIPPLE 20mV/DIV
IL 0.5A/DIV
FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM)
LX 2V/DIV
V
OUT
RIPPLE 50mV/DIV
IL 1A/DIV
FIGURE 20. MODE TRANSITION CCM TO DCM
FN7551.3
May 12, 2015
ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
A
= +25°C, V
VIN
= 2.5V to 5.5V,
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A. (Continued)
LX 2V/DIV
V
OUT
RIPPLE 50mV/DIV
V
OUT
RIPPLE 50mV/DIV
IL 1A/DIV
FIGURE 21. MODE TRANSITION DCM TO CCM
LX 2V/DIV
IL 1A/DIV
FIGURE 22. LOAD TRANSIENT (PWM)
EN 5V/DIV
EN 5V/DIV
V
OUT
RIPPLE 50mV/DIV
IL 1A/DIV
FIGURE 23. LOAD TRANSIENT (PFM)
V
OUT
0.5V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT NO LOAD (PFM)
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V
OUT
0.5V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 24. SOFT-START WITH NO LOAD (PWM)
EN 5V/DIV
V
OUT
0.5V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 26. SOFT-START WITH PREBIASED 1V
FN7551.3
May 12, 2015
ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
A
= +25°C, V
VIN
= 2.5V to 5.5V,
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A. (Continued)
EN 2V/DIV
EN 5V/DIV
V
OUT
0.5V/DIV
IL 2A/DIV
PG 5V/DIV
FIGURE 27. SOFT-START AT FULL LOAD
V
OUT
0.5V/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 28. SOFT-DISCHARGE SHUTDOWN
LX 2V/DIV
SYNCH 2V/DIV
V
OUT
RIPPLE 20mV/DIV
IL 1A/DIV
FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 2MHz
LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
V
OUT
RIPPLE 20mV/DIV
FIGURE 30. STEADY STATE OPERATION AT FULL LOAD WITH
FREQUENCY = 2MHz
LX 2V/DIV
SYNCH 2V/DIV
V
OUT
RIPPLE 20mV/DIV
IL 0.5A/DIV
FIGURE 31. STEADY STATE OPERATION AT NO LOAD WITH
FREQUENCY = 4MHz
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LX 2V/DIV
IL 1A/DIV
SYNCH 2V/DIV
V
OUT
RIPPLE 20mV/DIV
FIGURE 32. STEADY STATE OPERATION AT FULL LOAD (PWM)
WITH FREQUENCY = 4MHz
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ISL78214
Typical Operating Performance
Unless otherwise noted, operating conditions are: T
A
= +25°C, V
VIN
= 2.5V to 5.5V,
EN = V
IN
, SYNCH = 0V, L = 1.5µH, C
1
= 2x22µF, C
2
= 2x22µF, I
OUT
= 0A to 4A. (Continued)
LX 2V/DIV
LX 2V/DIV
IL 2A/DIV
V
OUT
0.5V/DIV
V
OUT
1V/DIV
PG 5V/DIV
PG 5V/DIV
IL 2A/DIV
FIGURE 33. OUTPUT SHORT CIRCUIT
FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY
5.500
5.375
5.250
5.125
5.000
4.875
4.750
OCP_3.3V
IN
OCP_5V
IN
4.625
4.500
-50 -25 0 25 50
TEMPERATURE (°C)
75
FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE
100
Theory of Operation
The ISL78214 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at
1MHz fixed switching frequency under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 35µA. The supply current is typically only 0.1µA when the regulator is shut down.
PWM Control Scheme
Pulling the SYNCH pin HI (>2.5V) forces the converter into PWM mode, regardless of output current. The ISL78214 employs the current-mode Pulse-width Modulation (PWM) control scheme for
oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The gain for the current sensing circuit is typically 200mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the oscillator.
The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation
(237mV/µs) reaches the control reference of the current loop, the
PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and turn on the N-Channel MOSFET. The
N-MOSFET stays on until the end of the PWM cycle. Figure 36
shows the typical operating waveforms during the PWM operation.
The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the V
EAMP
voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage loop. The feedback signal comes from the
VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error signal to a current output. The voltage loop is internally compensated
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with the 27pF and 390kΩ RC network. The maximum EAMP voltage output is precisely clamped to 1.6V.
V
EAMP
V
CSA
DUTY
CYCLE
I
L
V
OUT
ISL78214
FIGURE 36. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCH pin LO (<0.4V) forces the converter into PFM mode. The ISL78214 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching
frequency. Figure 37 illustrates the skip-mode operation. A
zero-cross sensing circuit shown in
N-MOSFET current for zero crossing. When 8 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. During the eight detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero.
Once the skip mode is entered, the pulse modulation starts being
controlled by the SKIP comparator shown in Figure 2 . Each pulse
cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak Skip current limit value. Then the inductor current is discharging to 0A and stays at zero. The internal clock is disabled and the output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the rising edge of the internal clock as it repeats the previous operations.
The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage.
PWM
Synchronization Control
The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNCH pin. The falling edge on the
SYNCH triggers the rising edge of the LX pulse. Make sure that the minimum ON time of the LX node is greater than 140ns.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA output
with the OCP comparator, as shown in Figure 2
. The current sensing circuit has a gain of 200mV/A, from the P-MOSFET current to the
CSA output. When the CSA output reaches 1.4V, which is equivalent to 5.7A for the switch current, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are
17 sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of four soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away during the delay of four soft-start periods, the output will resume back into regulation point after hiccup mode expires.
Short-circuit Protection
The Short-circuit Protection (SCP) comparator monitors the VFB pin voltage for output short-circuit protection. When the VFB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event.
PG
During power-up, the open-drain power-good output holds low for about 1ms after V
OUT
reaches the regulation voltage. The PG output also serves as a 1ms delayed power-good signal when the pull-up resistor R
1
is installed.
PFM
CLOCK
I
L
0
V
OUT
8 CYCLES
NOMINAL +1.5%
PFM CURRENT LIMIT
LOAD CURRENT
NOMINAL
FIGURE 37. SKIP MODE OPERATION WAVEFORMS
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ISL78214
UVLO Thermal Shutdown
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Soft Start-up
The ISL78214 has built-in thermal protection. When the internal temperature reaches +140°C, the regulator is completely shut down. As the temperature drops to +115°C, the ISL78214 resumes operation by stepping through the soft-start.
The soft start-up reduces the inrush current during the start-up.
The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. When VFB is less than 0.2V at the beginning of the soft-start, the switching frequency is reduced to
1/3 of the nominal value so that the output can start up smoothly at light load condition. During soft-start, the IC operates in the SKIP mode to support prebiased output condition.
Enable
Applications Information
Output Inductor and Capacitor Selection
To consider steady state and transient operations, ISL78214 typically uses a 1.5µH output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V applications, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased.
It is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in
The enable (EN) input allows the user to control turning on or off the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference and then the soft start-up begins.
Discharge Mode (Soft-stop)
I
=
V
O
1 –
V
---------
IN
L f
S
(EQ. 1)
When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100Ω switch.
The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL78214 protects the typical peak current 6A. The saturation current needs be over 7A for maximum output current application.
Power MOSFETs
The power MOSFETs are optimized for best efficiency. The
ON-resistance for the P-MOSFET is typically 50mΩ and the
ON-resistance for the N-MOSFET is typically 50mΩ.
ISL78214 uses internal an compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended X5R or X7R minimum output capacitor values are shown in
100% Duty Cycle
The ISL78214 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the
ISL78214 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum
In
Table 1 , the minimum output capacitor value is given for the
different output voltage to make sure that the whole converter system is stable. Additional output capacitance should be added dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the
P-MOSFET. for better performances in applications where high load transient or low output ripple is required. It is recommended to check the system level performance along with the simulation model.
TABLE 1. OUTPUT CAPACITOR VALUE vs V
OUT
1.5
1.8
2.5
3.3
3.6
V
OUT
(V)
0.8
1.2
C
OUT
(µF)
2 x 22
2 x 22
2 x 22
2 x 22
2 x 22
2 x 22
2 x 22
L
(µH)
1.0~2.2
1.0~2.2
1.5~3.3
1.5~3.3
1.5~3.3
2.2~4.7
2.2~4.7
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ISL78214
Output Voltage Selection
The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the
inverting input of the error amplifier. Refer to Figure 1 on page 3 .
The output voltage programming resistor, R
3
, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 10kΩ and 100kΩ
R
3
=
V
R
OUT
0.8V
–
0.8V
(EQ. 2)
If the output voltage desired is 0.8V, then R
3 and R
2
is left unpopulated
is shorted. There is a leakage current from VIN to LX. It is recommended to preload the output with 10µA minimum. For better performance, add 47pF in parallel with R
2
(100kΩ
Input Capacitor Selection
The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. Two 22µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev.
DATE
May 12, 2015
December 4, 2013
March 8, 2010
REVISION
FN7551.2
FN7551.1
FN7551.0
CHANGE
-Added “Tested per AEC...” information to ESD ratings.
-Updated Latch-up information from Jedec to AEC spec and results.
-Added Shutdown Supply Current max for +105°C of “10µA”.
Updated About Intersil verbiage.
Updated to newest template
Page 1 - updated copyright information
Page 22 - 2nd line of the disclaimer changed from:
“Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted” to:
“Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted”.
Initial release.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com
.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask .
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil Automotive Qualified products are manufactured, assembled and tested utilizing TS16949 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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Package Outline Drawing
L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 6, 02/08
4.00
A
B
ISL78214
6
PIN 1
INDEX AREA
12
13
4X 1.95
12X
0.65
16
1
6
PIN #1 INDEX AREA
2 . 10 ± 0 . 15
9
(4X)
0.15
( 3 . 6 TYP )
( 2 . 10 )
TOP VIEW
16X 0 . 60
+0.15
-0.10
1.00 MAX
( 12X 0 . 65 )
4
8
BOTTOM VIEW
5
4
0.10
M C A B
0.28 +0.07 / -0.05
SEE DETAIL "X"
0.10 C
BASE PLANE
C
SEATING PLANE
0.08 C
SIDE VIEW
TYPICAL RECOMMENDED LAND PATTERN
( 16X 0 . 28 )
( 16 X 0 . 8 )
C 0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
5
NOTES:
1.
2.
3.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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