STMicroelectronics SPC563M60L5 Datasheet

Yes

Class 2+

Yes

4 channels

Yes

LQFP144

LQFP176

Yes

364

Figure 1 shows a top-level block diagram of the SPC563Mxx series.

Calibration package only.

The 176-pin package has 34 input channels; 144-pin package has 32 input channels; 100-pin package has 23 input channels.

One FlexCAN module has 64 message buffers; the other has 32 message buffers.

165 interrupt channels are reserved for compatibility with future devices. This device has 191 peripheral interrupt sources plus 8 software interrupts available to the user.

10/128



Operating Parameters

– Fully static operation, 0 MHz – 80 MHz (plus 2 % frequency modulation - 82 MHz)

– –40

C to 150 C junction temperature operating range

– Low power design

– Less than 400 mW power dissipation (nominal)

– Designed for dynamic power management of core and peripherals

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SPC563M64x, SPC563M60x Overview

– Software controlled clock gating of peripherals

– Low power stop mode, with all clocks stopped

– Fabricated in 90 nm process

– 1.2 V internal logic

– Single power supply with 5.0 V

5 % (4.5 V to 5.25 V) with internal regulator to provide 3.3 V and 1.2 V for the core

– Input and output pins with 5.0 V

5% (4.5 V to 5.25 V) range

35 %/65 % V

DDE

CMOS switch levels (with hysteresis)

– Selectable hysteresis

– Selectable slew rate control

– Nexus pins powered by 3.3 V supply

– Designed with EMI reduction techniques

– Phase-locked loop

– Frequency modulation of system clock frequency

– On-chip bypass capacitance

– Selectable slew rate and drive strength



High performance e200z335 core processor

– 32-bit Power Architecture Book E programmer’s model

– Variable Length Encoding Enhancements

– Allows Power Architecture instruction set to be optionally encoded in a mixed

16 and 32-bit instructions

– Results in smaller code size

– Single issue, 32-bit Power Architecture technology compliant CPU

– In-order execution and retirement

– Precise exception handling

– Branch processing unit

– Dedicated branch address calculation adder

– Branch acceleration using Branch Lookahead Instruction Buffer

– Load/store unit

– One-cycle load latency

– Fully pipelined

– Big and Little Endian support

– Misaligned access support

– Zero load-to-use pipeline bubbles

– Thirty-two 64-bit general purpose registers (GPRs)

– Memory management unit (MMU) with 16-entry fully-associative translation lookaside buffer (TLB)

– Separate instruction bus and load/store bus

– Vectored interrupt support

– Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to execution of first instruction of interrupt exception handler)

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Overview SPC563M64x, SPC563M60x

– Non-maskable interrupt (NMI) input for handling external events that must produce an immediate response, e.g., power down detection. On this device, the

NMI input is connected to the Critical Interrupt Input. (May not be recoverable)

– Critical Interrupt input. For external interrupt sources that are higher priority than provided by the Interrupt Controller. (Always recoverable)

– New ‘Wait for Interrupt’ instruction, to be used with new low power modes

– Reservation instructions for implementing read-modify-write accesses

– Signal processing extension (SPE) APU

– Operating on all 32 GPRs that are all extended to 64 bits wide

– Provides a full compliment of vector and scalar integer and floating point arithmetic operations (including integer vector MAC and MUL operations)

(SIMD)

– Provides rich array of extended 64-bit loads and stores to/from extended

GPRs

– Fully code compatible with e200z6 core

– Floating point (FPU)

– IEEE 754 compatible with software wrapper

– Scalar single precision in hardware, double precision with software library

– Conversion instructions between single precision floating point and fixed point

– Fully code compatible with e200z6 core

– Long cycle time instructions, except for guarded loads, do not increase interrupt latency

– Extensive system development support through Nexus debug port



Advanced microcontroller bus architecture (AMBA) crossbar switch (XBAR)

– Three master ports, four slave ports

– Masters: CPU Instruction bus; CPU Load/store bus (Nexus); eDMA

– Slave: Flash; SRAM; Peripheral Bridge; calibration EBI

– 32-bit internal address bus, 64-bit internal data bus



Enhanced direct memory access (eDMA) controller

– 32 channels support independent 8-bit, 16-bit, or 32-bit single value or block transfers

– Supports variable sized queues and circular queues

– Source and destination address registers are independently configured to postincrement or remain constant

– Each transfer is initiated by a peripheral, CPU, or eDMA channel request

– Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single value or block transfer



Interrupt controller (INTC)

– 191 peripheral interrupt request sources

– 8 software setable interrupt request sources

– 9-bit vector

– Unique vector for each interrupt request source

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– Provided by hardware connection to processor or read from register

– Each interrupt source can be programmed to one of 16 priorities

– Preemption

– Preemptive prioritized interrupt requests to processor

– ISR at a higher priority preempts ISRs or tasks at lower priorities

– Automatic pushing or popping of preempted priority to or from a LIFO

– Ability to modify the ISR or task priority. Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing shared resources.

– Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor



Frequency Modulating Phase-locked loop (FMPLL)

– Reference clock pre-divider (PREDIV) for finer frequency synthesis resolution

– Reduced frequency divider (RFD) for reducing the FMPLL output clock frequency without forcing the FMPLL to re-lock

– System clock divider (SYSDIV) for reducing the system clock frequency in normal or bypass mode

– Input clock frequency range from 4 MHz to 20 MHz before the pre-divider, and from 4 MHz to 16 MHz at the FMPLL input

– Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

– VCO free-running frequency range from 25 MHz to 125 MHz

– Four bypass modes: crystal or external reference with PLL on or off

– Two normal modes: crystal or external reference

– Programmable frequency modulation

– Triangle wave modulation

– Register programmable modulation frequency and depth

– Lock detect circuitry reports when the FMPLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions

– User-selectable ability to generate an interrupt request upon loss of lock

– User-selectable ability to generate a system reset upon loss of lock

– Clock quality monitor (CQM) module provides loss-of-clock detection for the

FMPLL reference and output clocks

– User-selectable ability to generate an interrupt request upon loss of clock

– User-selectable ability to generate a system reset upon loss of clock

– Backup clock (reference clock or FMPLL free-running) can be applied to the system in case of loss of clock



Calibration bus interface (EBI)

– Available only in the calibration package (496 CSP package)

– 1.8 V to 3.3 V ± 10% I/O (1.6 V to 3.6 V)

– Memory controller with support for various memory types

– 16-bit data bus, up to 22-bit address bus

– Selectable drive strength

– Configurable bus speed modes

– Bus monitor

– Configurable wait states

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Overview SPC563M64x, SPC563M60x



System integration unit (SIU)

– Centralized GPIO control of 80 I/O pins

– Centralized pad control on a per-pin basis

– Pin function selection

– Configurable weak pull-up or pull-down

– Drive strength

– Slew rate

– Hysteresis

– System reset monitoring and generation

– External interrupt inputs, filtering and control

– Critical Interrupt control

– Non-Maskable Interrupt control

– Internal multiplexer subblock (IMUX)

– Allows flexible selection of eQADC trigger inputs (eTPU, eMIOS and external signals)

– Allows selection of interrupt requests between external pins and DSPI



Error correction status module (ECSM)

– Configurable error-correcting codes (ECC) reporting

– Single-bit error correction reporting



On-chip flash memory

– Up to 1.5 MB flash memory, accessed via a 64-bit wide bus interface

– 16 KB shadow block

– Fetch Accelerator

– Provide single cycle flash access at 80 MHz

– Quadruple 128-bit wide prefetch/burst buffers

– Prefetch buffers can be configured to prefetch code or data or both

– Censorship protection scheme to prevent flash content visibility

– Flash divided into two independent arrays, allowing reading from one array while erasing/programming the other array (used for EEPROM emulation)

– Memory block:

– For SPC563M64: 18 blocks (4

16 KB, 2 32 KB, 2 64 KB, 10 128 KB)

– For SPC563M60: 14 blocks (4

16 KB, 2 32 KB, 2 64 KB, 6 128 KB)

– Hardware programming state machine



On-chip static RAM

– For SPC563M64: 94 KB general purpose RAM of which 32 KB are on standby power supply

– For SPC563M60: 64 KB general purpose RAM of which 32 KB are on standby power supply



Boot assist module (BAM)

– Enables and manages the transition of MCU from reset to user code execution in the following configurations:

– Execution from internal flash memory

– Execution from external memory on the calibration bus

– Download and execution of code via FlexCAN or eSCI

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

Periodic interrupt timer (PIT)

– 32-bit wide down counter with automatic reload

– Four channels clocked by system clock

– One channel clocked by crystal clock

– Each channel can produce periodic software interrupt

– Each channel can produce periodic triggers for eQADC queue triggering

– One channel out of the five can be used as wake-up timer to wake device from low power stop mode



System timer module (STM)

– 32-bit up counter with 8-bit prescaler

– Clocked from system clock

– Four-channel timer compare hardware

– Each channel can generate a unique interrupt request

– Designed to address AUTOSAR task monitor function



Software watchdog timer (SWT)

– 32-bit timer

– Clock by system clock or crystal clock

– Can generate either system reset or non-maskable interrupt followed by system reset

– Enabled out of reset



Enhanced modular I/O system (eMIOS)

– 16 timer channels (up to 14 channels in LQFP144)

– 24-bit timer resolution

– 3 selectable time bases plus shared time or angle counter bus from eTPU2

– DMA and interrupt request support

– Motor control capability



Second-generation enhanced time processor unit (eTPU2)

– Object-code compatible with eTPU—no changes are required to hardware or software if only eTPU features are used

– Intelligent co-processor designed for timing control

– High level tools, assembler and compiler available

– 32 channels (each channel has dedicated I/O pin in all packages)

– 24-bit timer resolution

– 14 KB code memory and 3 KB data memory

– Double match and capture on all channels

– Angle clock hardware support

– Shared time or angle counter bus with eMIOS

– DMA and interrupt request support

– Nexus Class 1 debug support

– eTPU2 enhancements

– Counters and channels can run at full system clock speed

– Software watchdog

– Real-time performance monitor

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Overview SPC563M64x, SPC563M60x

– Instruction set enhancements for smaller more flexible code generation

– Programmable channel mode for customization of channel operation



Enhanced queued A/D converter (eQADC)

– Two independent on-chip redundant signed digit (RSD) cyclic ADCs

8-, 10-, and 12-bit resolution

– Differential conversions

– Targets up to 10-bit accuracy at 500 KSample/s (ADC_CLK = 7.5 MHz) and

8-bit accuracy at 1 MSample/s (ADC_CLK = 15 MHz) for differential conversions

– Differential channels include variable gain amplifier (VGA) for improved dynamic range (

1; 2; 4)

– Differential channels include programmable pull-up and pull-down resistors for biasing and sensor diagnostics (200 k

; 100 k; low value of 5 k)

– Single-ended signal range from 0 to 5 V

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

– Provides time stamp information when requested

– Parallel interface to eQADC command FIFOs (CFIFOs) and result FIFOs

(RFIFOs)

– Supports both right-justified unsigned and signed formats for conversion results

– Temperature sensor to enable measurement of die temperature

– Ability to measure all power supply pins directly

– Automatic application of ADC calibration constants

– Provision of reference voltages (25% VREF and 75% VREF) for ADC calibration purposes

– Up to 34

(b)

input channels available to the two on-chip ADCs

– Four pairs of differential analog input channels

– Full duplex synchronous serial interface to an external device

– Has a free-running clock for use by the external device

– Supports a 26-bit message length

– Transmits a null message when there are no triggered CFIFOs with commands bound for external CBuffers, or when there are triggered CFIFOs with commands bound for external CBuffers but the external CBuffers are full

– Parallel Side Interface to communicate with an on-chip companion module

– Zero jitter triggering for queue 0. (Queue 0 trigger causes current conversion to be aborted and the queued conversions in the CBUFFER to be bypassed. Delay from

Trigger to start of conversion is 13 system clocks + 1 ADC clock.)

– eQADC Result Streaming. Generation of a continuous stream of ADC conversion results from a single eQADC command word. Controlled by two different trigger signals; one to define the rate at which results are generated and the other to define the beginning and ending of the stream. Used to digitize waveforms during specific time/angle windows, e.g., engine knock sensor sampling.

16/128 b.

176-pin package has 34 input channels; 144-pin package has 32 input channels; 100-pin package has 23 input channels.

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– Angular Decimation. The ability of the eQADC to sample an analog waveform in the time domain, perform Finite Impulse Response (FIR) or Infinite Impulse

Response (IIR) filtering also in the time domain, but to down sample the results in the angle domain. Resulting in a time domain filtered result at a given engine angle.

– Priority Based CFIFOs

– Supports six CFIFOs with fixed priority. The lower the CFIFO number, the higher its priority. When commands of distinct CFIFOs are bound for the same CBuffer, the higher priority CFIFO is always served first.

– Supports software and several hardware trigger modes to arm a particular

CFIFO

– Generates interrupt when command coherency is not achieved

– External Hardware Triggers

– Supports rising edge, falling edge, high level and low level triggers

– Supports configurable digital filter

– Supports four external 8-to-1 muxes which can expand the input channel number from 34

(c)

to 59



Two deserial serial peripheral interface modules (DSPI)

– SPI

– Full duplex communication ports with interrupt and DMA request support

– Support for queues in RAM

– 6 chip selects, expandable to 64 with external demultiplexers

– Programmable frame size, baud rate, clock delay and clock phase on a per frame basis

– Modified SPI mode for interfacing to peripherals with longer setup time requirements

– LVDS option for output clock and data to allow higher speed communication

– Deserial serial interface (DSI)

– Pin reduction by hardware serialization and deserialization of eTPU, eMIOS channels and GPIO

– 32 bits per DSPI module

– Triggered transfer control and change in data transfer control (for reduced

EMI)

– Compatible with Microsecond Channel Version 1.0 downstream



Two enhanced serial communication interface (eSCI) modules

– UART mode provides NRZ format and half or full duplex interface

– eSCI bit rate up to 1 Mbps

– Advanced error detection, and optional parity generation and detection

– Word length programmable as 8, 9, 12 or 13 bits

– Separately enabled transmitter and receiver

– LIN support

– DMA support

– Interrupt request support c.176-pin package.

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Overview SPC563M64x, SPC563M60x

– Programmable clock source: system clock or oscillator clock

– Support Microsecond Channel (Timed Serial Bus - TSB) upstream Version 1.0



Two FlexCAN

– One with 32 message buffers; the second with 64 message buffers

– Full implementation of the CAN protocol specification, Version 2.0B

– Programmable acceptance filters

– Short latency time for high priority transmit messages

– Arbitration scheme according to message ID or message buffer number

– Listen only mode capabilities

– Programmable clock source: system clock or oscillator clock

– Message buffers may be configured as mailboxes or as FIFO



Nexus port controller (NPC)

– Per IEEE-ISTO 5001-2003

– Real time development support for Power Architecture core and eTPU engine through Nexus class 2/1

– Read and write access (Nexus class 3 feature that is supported on this device)

– Run-time access of entire memory map

– Calibration

– Support for data value breakpoints / watchpoints

– Run-time access of entire memory map

– Calibration

– Table constants calibrated using MMU and internal and external RAM

– Scalar constants calibrated using cache line locking

– Configured via the IEEE 1149.1 (JTAG) port



IEEE 1149.1 JTAG controller (JTAGC)

– IEEE 1149.1-2001 Test Access Port (TAP) interface

– 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions

– 5-bit instruction register that supports additional public instructions

– Three test data registers: a bypass register, a boundary scan register, and a device identification register

– Censorship disable register. By writing the 64-bit serial boot password to this register, Censorship may be disabled until the next reset

– TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry



On-chip Voltage Regulator for single 5 V supply operation

– On-chip regulator 5 V to 3.3 V for internal supplies

– On-chip regulator controller 5 V to 1.2 V (with external bypass transistor) for core logic



Low-power modes

– SLOW Mode. Allows device to be run at very low speed (approximately 1 MHz), with modules (including the PLL) selectively disabled in software

– STOP Mode. System clock stopped to all modules including the CPU. Wake-up timer used to restart the system clock after a predetermined time

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2.3 SPC563Mxx feature details

Overview

The e200z335 processor utilizes a four stage pipeline for instruction execution. The

Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address

Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions.

The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation

Unit (CRU), a Count-Leading-Zeros unit (CLZ), a 32

32 Hardware Multiplier array, result feed-forward hardware, and support hardware for division.

Most arithmetic and logical operations are executed in a single cycle with the exception of the divide instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The

Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six instructions.

Branches can also be decoded at the instruction buffer and branch target addresses calculated prior to the branch reaching the instruction decode stage, allowing the branch target to be prefetched early. When a branch is detected at the instruction buffer, a prediction may be made on whether the branch is taken or not. If the branch is predicted to be taken, a target fetch is initiated and its target instructions are placed in the instruction buffer following the branch instruction. Many branches take zero cycle to execute by using branch folding. Branches are folded out from the instruction execution pipe whenever possible. These include unconditional branches and conditional branches with condition codes that can be resolved early.

Conditional branches which are not taken and not folded execute in a single clock.

Branches with successful target prefetching which are not folded have an effective execution time of one clock. All other taken branches have an execution time of two clocks.

Memory load and store operations are provided for byte, halfword, and word (32-bit) data with automatic zero or sign extension of byte and halfword load data as well as optional byte reversal of data. These instructions can be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow low overhead context save and restore operations. The load/store unit contains a dedicated effective address adder to allow effective address generation to be optimized. Also, a load-to-use dependency does not incur any pipeline bubbles for most cases.

The Condition Register unit supports the condition register (CR) and condition register operations defined by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.

The hardware floating-point unit utilizes the IEEE-754 single-precision floating-point format and supports single-precision floating-point operations in a pipelined fashion. The general purpose register file is used for source and destination operands, thus there is a unified

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Overview SPC563M64x, SPC563M60x storage model for single-precision floating-point data types of 32 bits and the normal integer type. Single-cycle floating-point add, subtract, multiply, compare, and conversion operations are provided. Divide instructions are multi-cycle and are not pipelined.

The Signal Processing Extension (SPE) Auxiliary Processing Unit (APU) provides hardware

SIMD operations and supports a full complement of dual integer arithmetic operation including Multiply Accumulate (MAC) and dual integer multiply (MUL) in a pipelined fashion.

The general purpose register file is enhanced such that all 32 of the GPRs are extended to

64 bits wide and are used for source and destination operands, thus there is a unified storage model for 32

32 MAC operations which generate greater than 32-bit results.

The majority of both scalar and vector operations (including MAC and MUL) are executed in a single clock cycle. Both scalar and vector divides take multiple clocks. The SPE APU also provides extended load and store operations to support the transfer of data to and from the extended 64-bit GPRs.

The CPU includes support for Variable Length Encoding (VLE) instruction enhancements.

This enables the classic Power Architecture instruction set to be represented by a modified instruction set made up from a mixture of 16- and 32-bit instructions. This results in a significantly smaller code size footprint without noticeably affecting performance. The Power

Architecture instruction set and VLE instruction set are available concurrently. Regions of the memory map are designated as PPC or VLE using an additional configuration bit in each of Table Look-aside Buffers (TLB) entries in the MMU.

The CPU core is enhanced by the addition of two additional interrupt sources; Non-

Maskable Interrupt and Critical Interrupt. These two sources are routed directly from package pins, via edge detection logic in the SIU to the CPU, bypassing completely the

Interrupt Controller. Once the edge detection logic is programmed, it cannot be disabled, except by reset. The non-maskable Interrupt is, as the name suggests, completely unmaskable and when asserted will always result in the immediate execution of the respective interrupt service routine. The non-maskable interrupt is not guaranteed to be recoverable.

The Critical Interrupt is very similar to the non-maskable interrupt, but it can be masked by other exceptional interrupts in the CPU and is guaranteed to be recoverable (code execution may be resumed from where it stopped).

The CPU core has an additional ‘Wait for Interrupt’ instruction that is used in conjunction with low power STOP mode. When Low Power Stop mode is selected, this instruction is executed to allow the system clock to be stopped. An external interrupt source or the system wake-up timer is used to restart the system clock and allow the CPU to service the interrupt.

2.3.2 Crossbar

The XBAR multi-port crossbar switch supports simultaneous connections between three master ports and four slave ports. The crossbar supports a 32-bit address bus width and a

64-bit data bus width.

The crossbar allows three concurrent transactions to occur from the master ports to any slave port; but each master must access a different slave. If a slave port is simultaneously requested by more than one master port, arbitration logic selects the higher priority master and grants it ownership of the slave port. All other masters requesting that slave port are stalled until the higher priority master completes its transactions. Requesting masters are treated with equal priority and are granted access to a slave port in round-robin fashion,

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

3 master ports:

– e200z335 core complex Instruction port

– e200z335 core complex Load/Store port

– eDMA



4 slave ports

– FLASH

– Calibration bus

– SRAM

– Peripheral bridge A/B (eTPU2, eMIOS, SIU, DSPI, eSCI, FlexCAN, eQADC, BAM, decimation filter, PIT, STM and SWT)



32-bit internal address, 64-bit internal data paths

2.3.3 eDMA

The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data movements via 32 programmable channels, with minimal intervention from the host processor. The hardware micro architecture includes a

DMA engine which performs source and destination address calculations, and the actual data movement operations, along with an SRAM-based memory containing the transfer control descriptors (TCD) for the channels. This implementation is utilized to minimize the overall block size. The eDMA module provides the following features:



All data movement via dual-address transfers: read from source, write to destination



Programmable source and destination addresses, transfer size, plus support for enhanced addressing modes



Transfer control descriptor organized to support two-deep, nested transfer operations



An inner data transfer loop defined by a “minor” byte transfer count



An outer data transfer loop defined by a “major” iteration count



Channel activation via one of three methods:

– Explicit software initiation

– Initiation via a channel-to-channel linking mechanism for continuous transfers

– Peripheral-paced hardware requests (one per channel)



Support for fixed-priority and round-robin channel arbitration



Channel completion reported via optional interrupt requests



1 interrupt per channel, optionally asserted at completion of major iteration count



Error termination interrupts are optionally enabled



Support for scatter/gather DMA processing



Channel transfers can be suspended by a higher priority channel

The INTC (interrupt controller) provides priority-based preemptive scheduling of interrupt requests, suitable for statically scheduled hard real-time systems. The INTC allows interrupt request servicing from up to 191 peripheral interrupt request sources, plus 165 sources reserved for compatibility with other family members).

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Overview SPC563M64x, SPC563M60x

For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC provides a unique vector for each interrupt request source for quick determination of which ISR needs to be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request, the priority of each interrupt request is software configurable.

When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other.

Multiple processors can assert interrupt requests to each other through software setable interrupt requests. These same software setable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priority portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software setable interrupt request to finish the servicing in a lower priority

ISR. Therefore these software setable interrupt requests can be used instead of the peripheral ISR scheduling a task through the RTOS.

The INTC provides the following features:



356 peripheral interrupt request sources



8 software setable interrupt request sources



9-bit vector addresses



Unique vector for each interrupt request source



Hardware connection to processor or read from register



Each interrupt source can be programmed to one of 16 priorities



Preemptive prioritized interrupt requests to processor



ISR at a higher priority preempts executing ISRs or tasks at lower priorities



Automatic pushing or popping of preempted priority to or from a LIFO



Ability to modify the ISR or task priority to implement the priority ceiling protocol for accessing shared resources



Low latency—three clocks from receipt of interrupt request from peripheral to interrupt request to processor

This device also includes a Non-Maskable Interrupt (NMI) pin that bypasses the INTC and multiplexing logic.

2.3.5 FMPLL

The FMPLL allows the user to generate high speed system clocks from a 4 MHz to 20 MHz crystal oscillator or external clock generator. Further, the FMPLL supports programmable frequency modulation of the system clock. The PLL multiplication factor, output clock divider ratio are all software configurable. The PLL has the following major features:



Input clock frequency from 4 MHz to 20 MHz



Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz, resulting in system clock frequencies from 16 MHz to 80 MHz with granularity of 4 MHz or better



Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

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

3 modes of operation

– Bypass mode with PLL off

– Bypass mode with PLL running (default mode out of reset)

– PLL normal mode



Each of the three modes may be run with a crystal oscillator or an external clock reference



Programmable frequency modulation

– Modulation enabled/disabled through software

– Triangle wave modulation up to 100 kHz modulation frequency

– Programmable modulation depth (0% to 2% modulation depth)

– Programmable modulation frequency dependent on reference frequency



Lock detect circuitry reports when the PLL has achieved frequency lock and continuously monitors lock status to report loss of lock conditions



Clock Quality Module

– detects the quality of the crystal clock and cause interrupt request or system reset if error is detected

– detects the quality of the PLL output clock. If an error is detected, causes a system reset or switches the system clock to the crystal clock and causes an interrupt request



Programmable interrupt request or system reset on loss of lock

Note:

The Calibration EBI controls data transfer across the crossbar switch to/from memories or peripherals attached to the calibration tool connector in the calibration address space. The

Calibration EBI is only available in the calibration tool. The Calibration EBI includes a memory controller that generates interface signals to support a variety of external memories. The Calibration EBI memory controller supports legacy flash, SRAM, and asynchronous memories. In addition, the calibration EBI supports up to three regions via chip selects (two chip selects are multiplexed with two address bits), along with programmed region-specific attributes. The calibration EBI supports the following features:



22-bit address bus (two most significant signals multiplexed with two chip selects)



16-bit data bus



Multiplexed mode with addresses and data signals present on the data lines

The calibration EBI must be configured in multiplexed mode when the extended Nexus trace is used on the calibration tool. This is because Nexus signals and address lines of the calibration bus share the same balls in the calibration package.



Memory controller with support for various memory types:

– Asynchronous/legacy flash and SRAM



Bus monitor

– User selectable

– Programmable timeout period (with 8 external bus clock resolution)



Configurable wait states (via chip selects)



3 chip-select (Cal_CS[0], Cal_CS[2:3]) signals (Multiplexed with 2 most significant address signals)

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

2 write/byte enable (WE[0:1]/BE[0:1]) signals



Configurable bus speed modes

– system frequency

– 1/2 of system frequency

– 1/4 of system frequency



Optional automatic CLKOUT gating to save power and reduce EMI



Selectable drive strengths; 10 pF, 20 pF, 30 pF, 50 pF

2.3.7 SIU

The SPC563Mxx SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation. The reset configuration block contains the external pin boot configuration logic.

The pad configuration block controls the static electrical characteristics of I/O pins. The

GPIO block provides uniform and discrete input/output control of the I/O pins of the MCU.

The reset controller performs reset monitoring of internal and external reset sources, and drives the RSTOUT pin. Communication between the SIU and the e200z335 CPU core is via the crossbar switch. The SIU provides the following features:



System configuration

– MCU reset configuration via external pins

– Pad configuration control for each pad

– Pad configuration control for virtual I/O via DSPI serialization



System reset monitoring and generation

– Power-on reset support

– Reset status register provides last reset source to software

– Glitch detection on reset input

– Software controlled reset assertion



External interrupt

– 11 interrupt requests

– Rising or falling edge event detection

– Programmable digital filter for glitch rejection

– Critical Interrupt request

– Non-Maskable Interrupt request



GPIO

– GPIO function on 80 I/O pins

– Virtual GPIO on 64 I/O pins via DSPI serialization (requires external deserialization device)

– Dedicated input and output registers for setting each GPIO and Virtual GPIO pin



Internal multiplexing

– Allows serial and parallel chaining of DSPIs

– Allows flexible selection of eQADC trigger inputs

– Allows selection of interrupt requests between external pins and DSPI

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2.3.8 ECSM

The error correction status module provides status information regarding platform memory errors reported by error-correcting codes.

2.3.9 Flash

Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.

The flash module includes a Fetch Accelerator, that optimizes the performance of the flash array to match the CPU architecture and provides single cycle random access to the Flash

@ 80 MHz. The Flash module interfaces the system bus to a dedicated Flash memory array controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit data bus width at the system bus port, and a 128-bit read data interface to Flash memory.

The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which prefetches sequential lines of data from the Flash array into the buffer. Prefetch buffer hits allow no-wait responses. Normal Flash array accesses are registered and are forwarded to the system bus on the following cycle, incurring three wait-states. Prefetch operations may be automatically controlled, and are restricted to instruction fetch.

The Flash memory provides the following features:



Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte, halfword, word and doubleword reads are supported. Only aligned word and doubleword writes are supported.



Fetch Accelerator

– Architected to optimize the performance of the Flash with the CPU to provide single cycle random access to the Flash up to 80 MHz system clock speed

– Configurable read buffering and line prefetch support

– Four line read buffers (128 bits wide) and a prefetch controller



Hardware and software configurable read and write access protections on a per-master basis



Interface to the Flash array controller is pipelined with a depth of one, allowing overlapped accesses to proceed in parallel for interleaved or pipelined flash array designs



Configurable access timing allowing use in a wide range of system frequencies



Multiple-mapping support and mapping-based block access timing (0-31 additional cycles) allowing use for emulation of other memory types



Software programmable block program/erase restriction control



Erase of selected block(s)



Read page size of 128 bits (four words)



ECC with single-bit correction, double-bit detection



Program page size of 64 bits (two words)



ECC single-bit error corrections are visible to software



Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address, due to ECC



Embedded hardware program and erase algorithm



Erase suspend

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

Shadow information stored in non-volatile shadow block



Independent program/erase of the shadow block

2.3.10 SRAM

The SPC563Mxx SRAM module provides a general-purpose up to 94 KB memory block.

The SRAM controller includes these features:



Supports read/write accesses mapped to the SRAM memory from any master



32 KB block powered by separate supply for standby operation



Byte, halfword, word and double word addressable



ECC performs single-bit correction, double-bit detection on 32-bit data element

2.3.11 BAM

The BAM (Boot Assist Module) is a block of read-only memory that is programmed once by

ST and is identical for all SPC563Mxx MCUs. The BAM program is executed every time the

MCU is powered-on or reset in normal mode. The BAM supports different modes of booting.

They are:



Booting from internal flash memory



Serial boot loading (A program is downloaded into RAM via eSCI or the FlexCAN and then executed)



Booting from external memory on calibration bus

The BAM also reads the reset configuration half word (RCHW) from internal flash memory and configures the SPC563Mxx hardware accordingly. The BAM provides the following features:



Sets up MMU to cover all resources and mapping all physical address to logical addresses with minimum address translation



Sets up the MMU to allow user boot code to execute as either Power Architecture code

(default) or as VLE code



Detection of user boot code



Automatic switch to serial boot mode if internal flash is blank or invalid



Supports user programmable 64-bit password protection for serial boot mode



Supports serial bootloading via FlexCAN bus and eSCI using fixed baudrate protocol



Supports serial bootloading via FlexCAN bus and eSCI with auto baud rate sensing



Supports serial bootloading of either Power Architecture code (default) or VLE code



Supports booting from calibration bus interface



Supports censorship protection for internal flash memory



Provides an option to enable the core watchdog timer



Provides an option to disable the software watchdog timer

2.3.12 eMIOS

The eMIOS (Enhanced Modular Input Output System) module provides the functionality to generate or measure time events. The channels on this module provide a range of operating modes including the capability to perform dual input capture or dual output compare as well as PWM output.

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The eMIOS provides the following features:



16 channels (24-bit timer resolution)



For compatibility with other family members selected channels and timebases are implemented:

– Channels 0 to 6, 8 to 15, and 23

– Timebases A, B and C



Channels 1, 3, 5 and 6 support modes:

– General Purpose Input/Output (GPIO)

– Single Action Input Capture (SAIC)

– Single Action Output Compare (SAOC)



Channels 2, 4, 11 and 13 support all the modes above plus:

– Output Pulse Width Modulation Buffered (OPWMB)



Channels 0, 8, 9, 10, 12, 14, 15, 23 support all the modes above plus:

– Input Period Measurement (IPM)

– Input Pulse Width Measurement (IPWM)

– Double Action Output Compare (set flag on both matches) (DAOC)

– Modulus Counter Buffered (MCB)

– Output Pulse Width and Frequency Modulation Buffered (OPWFMB)



Three 24-bit wide counter buses

– Counter bus A can be driven by channel 23 or by the eTPU2 and all channels can use it as a reference

– Counter bus B is driven by channel 0 and channels 0 to 6 can use it as a reference

– Counter bus C is driven by channel 8 and channels 8 to 15 can use it as a reference



Shared time bases with the eTPU2 through the counter buses



Synchronization among internal and external time bases

2.3.13 eTPU2

The eTPU2 is an enhanced co-processor designed for timing control. Operating in parallel with the host CPU, eTPU2 processes instructions and real-time input events, performs output waveform generation, and accesses shared data without host intervention.

Consequently, for each timer event, the host CPU setup and service times are minimized or eliminated. A powerful timer subsystem is formed by combining the eTPU2 with its own instruction and data RAM. High-level assembler/compiler and documentation allows customers to develop their own functions on the eTPU2.

The eTPU2 includes these distinctive features:



The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.



Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and

TDL2) can now be independently negated by microcode.

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

A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.



Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction.



Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.



Channel digital filters can be bypassed.



The Timer Counter (TCR1), channel logic and digital filters (both channel and the external timer clock input [TCRCLK]) now have an option to run at full system clock speed or system clock / 2.



Channels support unordered transitions: transition 2 can now be detected before transition 1. Related to this enhancement, the transition detection latches (TDL1 and

TDL2) can now be independently negated by microcode.



A new User Programmable Channel Mode has been added: the blocking, enabling, service request and capture characteristics of this channel mode can be programmed via microcode.



Microinstructions now provide an option to issue Interrupt and Data Transfer requests selected by channel. They can also be requested simultaneously at the same instruction.



Channel Flags 0 and 1 can now be tested for branching, in addition to selecting the entry point.



Channel digital filters can be bypassed.



32 channels, each channel is associated with one input and one output signal

– Enhanced input digital filters on the input pins for improved noise immunity.

– Identical, orthogonal channels: each channel can perform any time function. Each time function can be assigned to more than one channel at a given time, so each signal can have any functionality.

– Each channel has an event mechanism which supports single and double action functionality in various combinations. It includes two 24-bit capture registers, two

24-bit match registers, 24-bit greater-equal and equal-only comparators

– Input and output signal states visible from the host



2 independent 24-bit time bases for channel synchronization:

– First time base clocked by system clock with programmable prescale division from

2 to 512 (in steps of 2), or by output of second time base prescaler

– Second time base counter can work as a continuous angle counter, enabling angle based applications to match angle instead of time

– Both time bases can be exported to the eMIOS timer module

– Both time bases visible from the host



Event-triggered microengine:

– Fixed-length instruction execution in two-system-clock microcycle

– 14 KB of code memory (SCM)

– 3 KB of parameter (data) RAM (SPRAM)

– Parallel execution of data memory, ALU, channel control and flow control subinstructions in selected combinations

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– 32-bit microengine registers and 24-bit wide ALU, with 1 microcycle addition and subtraction, absolute value, bitwise logical operations on 24-bit, 16-bit, or byte operands, single-bit manipulation, shift operations, sign extension and conditional execution

– Additional 24-bit Multiply/MAC/Divide unit which supports all signed/unsigned

Multiply/MAC combinations, and unsigned 24-bit divide. The MAC/Divide unit works in parallel with the regular microcode commands



Resource sharing features support channel use of common channel registers, memory and micro engine time:

– Hardware scheduler works as a “task management” unit, dispatching event service routines by predefined, host-configured priority

– Automatic channel context switch when a “task switch” occurs, i.e., one function thread ends and another begins to service a request from other channel: channelspecific registers, flags and parameter base address are automatically loaded for the next serviced channel

– SPRAM shared between host CPU and eTPU2, supporting communication either between channels and host or inter-channel

– Dual-parameter coherency hardware support allows atomic access to two parameters by host



Test and development support features:

– Nexus Class 1 debug, supporting single-step execution, arbitrary microinstruction execution, hardware breakpoints and watchpoints on several conditions

– Software breakpoints

– SCM continuous signature-check built-in self test (MISC — multiple input signature calculator), runs concurrently with eTPU2 normal operation



System enhancements

– Software watchdog with programmable timeout

– Real-time performance information



Channel enhancements

– Channels 1 and 2 can optionally drive angle clock hardware



Programming enhancements

– Engine relative addressing mode

2.3.14 eQADC

The enhanced queued analog to digital converter (eQADC) block provides accurate and fast conversions for a wide range of applications. The eQADC provides a parallel interface to two on-chip analog to digital converters (ADC), and a single master to single slave serial interface to an off-chip external device. Both on-chip ADCs have access to all the analog channels.

The eQADC prioritizes and transfers commands from six command conversion command

‘queues’ to the on-chip ADCs or to the external device. The block can also receive data from the on-chip ADCs or from an off-chip external device into the six result queues, in parallel, independently of the command queues. The six command queues are prioritized with

Queue_0 having the highest priority and Queue_5 the lowest. Queue_0 also has the added ability to bypass all buffering and queuing and abort a currently running conversion on either

ADC and start a Queue_0 conversion. This means that Queue_0 will always have a deterministic time from trigger to start of conversion, irrespective of what tasks the ADCs

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The ADCs also support features designed to allow the direct connection of high impedance acoustic sensors that might be used in a system for detecting engine knock. These features include differential inputs; integrated variable gain amplifiers for increasing the dynamic range; programmable pull-up and pull-down resistors for biasing and sensor diagnostics.

The eQADC also integrates a programmable decimation filter capable of taking in ADC conversion results at a high rate, passing them through a hardware low pass filter, then down-sampling the output of the filter and feeding the lower sample rate results to the result

FIFOs. This allows the ADCs to sample the sensor at a rate high enough to avoid aliasing of out-of-band noise; while providing a reduced sample rate output to minimize the amount

DSP processing bandwidth required to fully process the digitized waveform.

The eQADC provides the following features:



Dual on-chip ADCs

– 2

 12-bit ADC resolution

– Programmable resolution for increased conversion speed (12 bit, 10 bit, 8 bit)

12-bit conversion time – 1

s (1M sample/sec)

10-bit conversion time – 867 ns (1.2M sample/second)

8-bit conversion time – 733 ns (1.4M sample/second)

– Up to 10-bit accuracy at 500 KSample/s and 9-bit accuracy at 1 MSample/s

– Differential conversions

– Single-ended signal range from 0 to 5 V

– Variable gain amplifiers on differential inputs (

1, 2, 4)

– Sample times of 2 (default), 8, 64 or 128 ADC clock cycles

– Provides time stamp information when requested

– Parallel interface to eQADC CFIFOs and RFIFOs

– Supports both right-justified unsigned and signed formats for conversion results



Up to 34

(d)

input channels (accessible by both ADCs)



23 additional internal channels for measuring control and monitoring voltages inside the device

– Including Core voltage, I/O voltage, LVI voltages, etc.



An internal bandgap reference to allow absolute voltage measurements



4 pairs of differential analog input channels

– Programmable pull-up/pull-down resistors on each differential input for biasing and sensor diagnostic (200 k

, 100 k, 5 k)



Silicon die temperature sensor

– provides temperature of silicon as an analog value

– read using an internal ADC analog channel

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– may be read with either ADC



Decimation Filter

– Programmable decimation factor (2 to 16)

– Selectable IIR or FIR filter

– Up to 4th order IIR or 8th order FIR

– Programmable coefficients

– Saturated or non-saturated modes

– Programmable Rounding (Convergent; Two’s Complement; Truncated)

– Pre-fill mode to pre-condition the filter before the sample window opens



Full duplex synchronous serial interface to an external device

– Free-running clock for use by an external device

– Supports a 26-bit message length



Priority based Queues

– Supports six Queues with fixed priority. When commands of distinct Queues are bound for the same ADC, the higher priority Queue is always served first

– Queue_0 can bypass all prioritization, buffering and abort current conversions to start a Queue_0 conversion a deterministic time after the queue trigger

– Streaming mode operation of Queue_0 to execute some commands several times

– Supports software and hardware trigger modes to arm a particular Queue

– Generates interrupt when command coherency is not achieved



External hardware triggers

– Supports rising edge, falling edge, high level and low level triggers

– Supports configurable digital filter



Supports four external 8-to-1 muxes which can expand the input channels to 56 channels total

2.3.15 DSPI

The Deserial Serial Peripheral Interface (DSPI) block provides a synchronous serial interface for communication between the SPC563Mxx MCU and external devices. The

DSPI supports pin count reduction through serialization and deserialization of eTPU and eMIOS channels and memory-mapped registers. The channels and register content are transmitted using a SPI-like protocol. This SPI-like protocol is completely configurable for baud rate, polarity and phase, frame length, chip select assertion, etc. Each bit in the frame may be configured to serialize either eTPU channels, eMIOS channels or GPIO signals. The

DSPI can be configured to serialize data to an external device that supports the

Microsecond Channel protocol. There are two identical DSPI blocks on the SPC563Mxx

MCU. The DSPI output pins support 5 V logic levels or Low Voltage Differential Signalling

(LVDS) according to the Microsecond Channel specification.

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The DSPIs have three configurations:



Serial peripheral interface (SPI) configuration where the DSPI operates as an up to 16bit SPI with support for queues



Enhanced Deserial Serial Interface (DSI) configuration where DSPI serializes up to 32 bits with three possible sources per bit

– eTPU, eMIOS, new virtual GPIO registers as possible bit source

– Programmable inter-frame gap in continuous mode

– Bit source selection allows microsecond channel downstream with command or data frames up to 32 bits

– Microsecond channel dual receiver mode



Combined serial interface (CSI) configuration where the DSPI operates in both SPI and

DSI configurations interleaving DSI frames with SPI frames, giving priority to SPI frames

For queued operations, the SPI queues reside in system memory external to the DSPI. Data transfers between the memory and the DSPI FIFOs are accomplished through the use of the eDMA controller or through host software.

The DSPI supports these SPI features:



Full-duplex, synchronous transfers



Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins



Master and Slave Mode



Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries



Buffered receive operation using the RX FIFO with parameterized depth of 4 entries



TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues



Visibility into the TX and RX FIFOs for ease of debugging



FIFO Bypass Mode for low-latency updates to SPI queues



Programmable transfer attributes on a per-frame basis:

– Parameterized number of transfer attribute registers (from two to eight)

– Serial clock with programmable polarity and phase

– Various programmable delays:

PCS to SCK delay

SCK to PCS delay

Delay between frames

– Programmable serial frame size of 4 to 16 bits, expandable with software control

– Continuously held chip select capability



6 Peripheral Chip Selects, expandable to 64 with external demultiplexer



Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer



DMA support for adding entries to TX FIFO and removing entries from RX FIFO:

– TX FIFO is not full (TFFF)

– RX FIFO is not empty (RFDF)

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

6 Interrupt conditions:

– End of queue reached (EOQF)

– TX FIFO is not full (TFFF)

– Transfer of current frame complete (TCF)

– Attempt to transmit with an empty Transmit FIFO (TFUF)

– RX FIFO is not empty (RFDF)

– FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when the TxFIFO is empty)

– FIFO Overrun (serial frame received while RX FIFO is full)



Modified transfer formats for communication with slower peripheral devices



Continuous Serial Communications Clock (SCK)



Power savings via support for Stop Mode



Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration, supporting the Microsecond Channel downstream frame format

The DSPIs also support these features unique to the DSI and CSI configurations:



2 sources of the serialized data:

– eTPU_A and eMIOS output channels

– Memory-mapped register in the DSPI



Destinations for the deserialized data:

– eTPU_A and eMIOS input channels

– SIU External Interrupt Request inputs

– Memory-mapped register in the DSPI



Deserialized data is provided as Parallel Output signals and as bits in a memorymapped register



Transfer initiation conditions:

– Continuous

– Edge sensitive hardware trigger

– Change in data



Pin serialization/deserialization with interleaved SPI frames for control and diagnostics



Continuous serial communications clock



Support for parallel and serial chaining of up to four DSPI blocks

2.3.16 eSCI

The enhanced serial communications interface (eSCI) allows asynchronous serial communications with peripheral devices and other MCUs. It includes special support to interface to Local Interconnect Network (LIN) slave devices. The eSCI block provides the following features:



Full-duplex operation



Standard mark/space non-return-to-zero (NRZ) format



13-bit baud rate selection



Programmable 8-bit or 9-bit, data format



Programmable 12-bit or 13-bit data format for Timed Serial Bus (TSB) configuration to support the Microsecond Channel upstream

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

Automatic parity generation



LIN support

– Autonomous transmission of entire frames

– Configurable to support all revisions of the LIN standard

– Automatic parity bit generation

– Double stop bit after bit error

– 10- or 13-bit break support



Separately enabled transmitter and receiver



Programmable transmitter output parity



2 receiver wake up methods:

– Idle line wake-up

– Address mark wake-up



Interrupt-driven operation with flags



Receiver framing error detection



Hardware parity checking



1/16 bit-time noise detection



DMA support for both transmit and receive data

– Global error bit stored with receive data in system RAM to allow post processing of errors

2.3.17 FlexCAN

The SPC563Mxx MCU contains two controller area network (FlexCAN) blocks. The

FlexCAN module is a communication controller implementing the CAN protocol according to

Bosch Specification version 2.0B. The CAN protocol was designed to be used primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness and required bandwidth. FlexCAN module ‘A’ contains 64 message buffers (MB); FlexCAN module ‘C’ contains 32 message buffers.

The FlexCAN module provides the following features:



Full Implementation of the CAN protocol specification, Version 2.0B

– Standard data and remote frames

– Extended data and remote frames

– Zero to eight bytes data length

– Programmable bit rate up to 1 Mbit/s



Content-related addressing



64 / 32 message buffers of zero to eight bytes data length



Individual Rx Mask Register per message buffer



Each message buffer configurable as Rx or Tx, all supporting standard and extended messages



Includes 1056 / 544 bytes of embedded memory for message buffer storage



Includes a 256-byte and a 128-byte memories for storing individual Rx mask registers



Full featured Rx FIFO with storage capacity for six frames and internal pointer handling

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

Powerful Rx FIFO ID filtering, capable of matching incoming IDs against 8 extended,

16 standard or 32 partial (8 bits) IDs, with individual masking capability



Selectable backwards compatibility with previous FlexCAN versions



Programmable clock source to the CAN Protocol Interface, either system clock or oscillator clock



Listen only mode capability



Programmable loop-back mode supporting self-test operation



3 programmable Mask Registers



Programmable transmit-first scheme: lowest ID, lowest buffer number or highest priority



Time Stamp based on 16-bit free-running timer



Global network time, synchronized by a specific message



Maskable interrupts



Warning interrupts when the Rx and Tx Error Counters reach 96



Independent of the transmission medium (an external transceiver is assumed)



Multi master concept



High immunity to EMI



Short latency time due to an arbitration scheme for high-priority messages



Low power mode, with programmable wake-up on bus activity

The system timers provide two distinct types of system timer:



Periodic interrupts/triggers using the Periodic Interrupt Timer (PIT)



Operating system task monitors using the System Timer Module (STM)

2.3.18.1 Periodic Interrupt Timer (PIT)

The PIT provides five independent timer channels, capable of producing periodic interrupts and periodic triggers. The PIT has no external input or output pins and is intended to be used to provide system ‘tick’ signals to the operating system, as well as periodic triggers for eQADC queues. Of the five channels in the PIT, four are clocked by the system clock, one is clocked by the crystal clock. This one channel is also referred to as Real Time Interrupt

(RTI) and is used to wakeup the device from low power stop mode.

The following features are implemented in the PIT:



5 independent timer channels



Each channel includes 32-bit wide down counter with automatic reload



4 channels clocked from system clock



1 channel clocked from crystal clock (wake-up timer)



Wake-up timer remains active when System STOP mode is entered. Used to restart system clock after predefined timeout period



Each channel can optionally generate an interrupt request or a trigger event (to trigger eQADC queues) when the timer reaches zero

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Overview SPC563M64x, SPC563M60x

2.3.18.2 System Timer Module (STM)

The System Timer Module (STM) is designed to implement the software task monitor as defined by AUTOSAR (see autosar.org web site). It consists of a single 32-bit counter, clocked by the system clock, and four independent timer comparators. These comparators produce a CPU interrupt when the timer exceeds the programmed value.

The following features are implemented in the STM:



One 32-bit up counter with 8-bit prescaler



Four 32-bit compare channels



Independent interrupt source for each channel



Counter can be stopped in debug mode

2.3.19 Software Watchdog Timer (SWT)

The Software Watchdog Timer (SWT) is a second watchdog module to complement the standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit modulus counter, clocked by the system clock or the crystal clock, that can provide a system reset or interrupt request when the correct software key is not written within the required time window.

The following features are implemented:



32-bit modulus counter



Clocked by system clock or crystal clock



Optional programmable watchdog window mode



Can optionally cause system reset or interrupt request on timeout



Reset by writing a software key to memory mapped register



Enabled out of reset



Configuration is protected by a software key or a write-once register

2.3.20.1 Nexus port controller

The NPC (Nexus Port Controller) block provides real-time development support capabilities for the SPC563Mxx Power Architecture-based MCU in compliance with the IEEE-ISTO

5001-2003 standard. This development support is supplied for MCUs without requiring external address and data pins for internal visibility. The NPC block is an integration of several individual Nexus blocks that are selected to provide the development support interface for SPC563Mxx. The NPC block interfaces to the host processor (e200z335), eTPU, and internal buses to provide development support as per the IEEE-ISTO 5001-2003 standard. The development support provided includes program trace and run-time access to the MCUs internal memory map and access to the Power Architecture and eTPU internal registers during halt. The Nexus interface also supports a JTAG only mode using only the

JTAG pins. SPC563Mxx in the production LQFP144 supports a 3.3 V reduced (4-bit wide)

Auxiliary port. These Nexus port pins can also be used as 5 V I/O signals to increase usable

I/O count of the device. When using this Nexus port as IO, Nexus trace is still possible using calibration tool calibration. In the calibration tool calibration package, the full 12-bit Auxiliary port is available.

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Note:

Overview

In the calibration tool package, the full Nexus Auxiliary port shares balls with the addresses of the calibration bus. Therefore multiplexed address/data bus mode must be used for the calibration bus when using full width Nexus trace in calibration tool assembly.

The following features are implemented:



5-pin JTAG port (JCOMP, TDI, TDO, TMS, and TCK)

– Always available in production package

– Supports both JTAG Boundary Scan and debug modes

– 3.3 V interface

– Supports Nexus class 1 features

– Supports Nexus class 3 read/write feature



9-pin Reduced Port interface in LQFP144 production package

– Alternate function as IO

– 5 V (in GPIO or alternate function mode), 3.3 V (in Nexus mode) interface

– Auxiliary Output port

– 1 MCKO (message clock out) pin

– 4 MDO (message data out) pins

– 2 MSEO (message start/end out) pins

– 1 EVTO (event out) pin

– Auxiliary input port

– 1 EVTI (event in) pin



17-pin Full Port interface in calibration package used on calibration tool boards

– 3.3 V interface

– Auxiliary Output port

– 1 MCKO (message clock out) pin

– 4 (reduced port mode) or 12 (full port mode) MDO (message data out) pins;

8 extra full port pins shared with calibration bus

– 2 MSEO (message start/end out) pins

– 1 EVTO (event out) pin

– Auxiliary input port

– 1 EVTI (event in) pin



Host processor (e200) development support features

– IEEE-ISTO 5001-2003 standard class 2 compliant

– Program trace via branch trace messaging (BTM). Branch trace messaging displays program flow discontinuities (direct branches, indirect branches, exceptions, etc.), allowing the development tool to interpolate what transpires between the discontinuities. Thus, static code may be traced.

– Watchpoint trigger enable of program trace messaging

– Data Value Breakpoints (JTAG feature of the e200z335 core): allows CPU to be halted when the CPU writes a specific value to a memory location

– 4 data value breakpoints

– CPU only

– Detects ‘equal’ and ‘not equal’

– Byte, half word, word (naturally aligned)

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Overview SPC563M64x, SPC563M60x

Note: This feature is imprecise due to CPU pipelining.

– Subset of Power Architecture software debug facilities with OnCE block (Nexus class 1 features)

 eTPU development support features

– IEEE-ISTO 5001-2003 standard class 1 compliant for the eTPU

– Nexus based breakpoint configuration and single step support (JTAG feature of the eTPU)



Run-time access to the on-chip memory map via the Nexus read/write access protocol.

This feature supports accesses for run-time internal visibility, calibration variable acquisition, calibration constant tuning, and external rapid prototyping for powertrain automotive development systems.



All features are independently configurable and controllable via the IEEE 1149.1 I/O port



Power-on-reset status indication during reset via MDO[0] in disabled and reset modes

2.3.20.2 JTAG

The JTAGC (JTAG Controller) block provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC block is communicated in serial format. The

JTAGC block is compliant with the IEEE 1149.1-2001 standard and supports the following features:



IEEE 1149.1-2001 Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, and TDO)



A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:

– BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD, HIGHZ, CLAMP



A 5-bit instruction register that supports the additional following public instructions:

– ACCESS_AUX_TAP_NPC

– ACCESS_AUX_TAP_ONCE

– ACCESS_AUX_TAP_eTPU

– ACCESS_CENSOR



3 test data registers to support JTAG Boundary Scan mode

– Bypass register

– Boundary scan register

– Device identification register



A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry



Censorship Inhibit Register

– 64-bit Censorship password register

– If the external tool writes a 64-bit password that matches the Serial Boot password stored in the internal flash shadow row, Censorship is disabled until the next system reset.

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2.4 SPC563Mxx series architecture

Overview

Figure 1. SPC563Mxx series block diagram

JTAG

JTAG Port

Nexus Port

NMI

Clocks

PLL

Nexus eTPU e200z335

Instructions

M S

SPE

NMI

SIU critical

MMU

Nexus 2+

Data

CQM

STM

Interrupt

Requests from

Peripheral

Blocks & eDMA eDMA

Interrupt

Controller

(INTC)

SWT PIT

DMA

Requests from

Peripheral

Blocks eDMA, FLASH, Bridge B, crossbar, SRAM

Configuration

Calibration

Bus

Interface

Flash

1.5 MB

SRAM

62 KB

Voltage

Regulator

(1.2V, 3.3V,

STB RAM)

BAM

V stby

Interrupt

Request

SIU

Reset Control

External

Interrupt

Request

IMUX

GPIO &

Pad Control

Peripheral Bridge

Nexus eTPU

NEXUS 1

32 Ch.+

Engine

RAM

14 KB/3 KB

16 Ch.

eMIOS

DSPIs

2x eSCIs

CANs eQADC

ADCI

Serial

Analog IF

ADC ADC

AMUX

Decimation

Filter

Analog

Temp. Sensor

I/O

. . .

Table 3 summarizes the functions of the blocks present on the SPC563Mxx series

microcontrollers.

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Overview SPC563M64x, SPC563M60x

Block e200z3 core

Flash memory

RAM (random-access memory)

Calibration bus

DMA (Direct Memory Access)

Table 3. SPC563Mxx series block summary

Function

DSPI (Deserial Serial Peripheral Interface)

Executes programs and interrupt handlers.

Provides storage for program code, constants, and variables

Transfers data across the crossbar switch to/from peripherals attached to the VertiCal connector

Performs complex data movements with minimal intervention from the core

Provides a synchronous serial interface for communication with external devices eMIOS (enhanced Modular Input-output

System) eQADC (enhanced Queued Analog-todigital Converter)

Provides the functionality to generate or measure events eSCI (Serial Communication Interface) eTPU (enhanced Time Processor Unit)

FlexCAN (Controller Area Network)

FMPLL (Frequency-modulated Phaselocked Loop)

INTC (Interrupt Controller)

JTAG controller

NPC (Nexus Port Controller)

PIT (Peripheral Interrupt Timer)

Temperature sensor

SWT (Software Watchdog Timer)

STM (System Timer Module)

Provides accurate and fast conversions for a wide range of applications

Allows asynchronous serial communications with peripheral devices and other microcontroller units

Processes real-time input events, performs output waveform generation, and accesses shared data without host intervention

Supports the standard CAN communications protocol

Generates high-speed system clocks and supports the programmable frequency modulation of these clocks

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode

Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard

Produces periodic interrupts and triggers

Provides the temperature of the device as an analog value

Provides protection from runaway code

Timer providing a set of output compare events to support AutoSAR and operating system tasks

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SPC563M64x, SPC563M60x

3 Pinout and signal description

Pinout and signal description

This section contains the pinouts for all production packages for the SPC563Mxx family of devices. Please note the following:



Pins labeled “NC” are to be left unconnected. Any connection to an external circuit or voltage may cause unpredictable device behavior or damage.



Pins labeled “NIC” have no internal connection.

Figure 2 shows the pinout for the 144-pin LQFP.

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Pinout and signal description SPC563M64x, SPC563M60x

Figure 2. 144-pin LQFP pinout (top view)

AN[18]

AN[17]

AN[16]

AN[11] / ANZ

AN[9] / ANX

VDDA

VSSA

AN[39] / AN[10] / ANY

AN[38] / AN[8] / ANW

VDDREG

VRCCTL

VSTBY

VRC33

(see signal details, pin 14)

(see signal details, pin 15) eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143] eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142]

(see signal details, pin 18)

(see signal details, pin 19)

(see signal details, pin 20)

(see signal details, pin 21)

VSS

(see signal details, pin 23)

VDDEH1A

(see signal details, pin 25)

VDD eTPU_A[21] / IRQ[9] / GPIO[135] eTPU_A[20] / IRQ[8] / GPIO[134] eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130] eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129]

VDDEH1B

(see signal details, pin 35)

VSS

144-Pin

LQFP signal details: pin 14: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145] pin 15: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144] pin 18: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT /

GPIO[141] pin 19: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140] pin 20: eTPU_A[25] / IRQ[13] / SCK_C_LVDS+ / GPIO[139] pin 21: eTPU_A[24] / IRQ[12] / SCK_C_LVDS– / GPIO[138] pin 23: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137] pin 25: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136] pin 35: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]

100

108

107

106

105

104

103

102

101

TMS

TDI / eMIOS[5] / GPIO[232]

EVTO / eTPU_A[4] / GPIO[227]

TCK

VSS

EVTI / eTPU_A[2] / GPIO[231]

VDDEH7

MSEO[1] / eTPU_A[29] / GPIO[225]

TDO / eMIOS[6] / GPIO[228]

MCKO / GPIO[219]

JCOMP

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

DSPI_B_PCS[0] / GPIO[105]

VDDEH6B

DSPI_B_PCS[1] / GPIO[106]

VSS

DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

VDD

RSTOUT

CAN_C_TX / GPIO[87]

SCI_A_TX / eMIOS[13] / GPIO[89]

SCI_A_RX / eMIOS[15] / GPIO[90]

CAN_C_RX / GPIO[88]

RESET

VSS

VDDEH6A

VSSPLL

XTAL

EXTAL / EXTCLK

VDDPLL

VSS

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SPC563M64x, SPC563M60x Pinout and signal description

Figure 3 shows the pinout for the 176-pin LQFP.

Figure 3. 176-pin LQFP pinout (top view)

AN[18]

AN[17]

AN[16]

AN[11] / ANZ

AN[9] / ANX

VDDA

VSSA

AN[39] / AN[10] / ANY

AN[38] / AN[8] / ANW

VDDREG

VRCCTL

VSTBY

VRC33

ALT_MCKO

VSS

VDDE12

ALT_MDO[0]

ALT_MDO[1]

ALT_MDO[2]

ALT_MDO[3]

(see signal details, pin 21)

(see signal details, pin 22)

(see signal details, pin 23)

(see signal details, pin 24)

(see signal details, pin 25)

(see signal details, pin 26)

(see signal details, pin 27)

(see signal details, pin 28)

VSS

(see signal details, pin 30)

VDDEH1A

(see signal details, pin 32)

VDD eTPU_A[21] / IRQ[9] / GPIO[135] eTPU_A[20] / IRQ[8] / GPIO[134] eTPU_A[19] / GPIO[133] eTPU_A[18] / GPIO[132] eTPU_A[17] / GPIO[131] eTPU_A[16] / GPIO[130]

(see signal details, pin 40)

VDDEH1B

(see signal details, pin 42)

VSS

NIC

176 - Pin

LQFP signal details: pin 21: eTPU_A[31] / DSPI_C_PCS[4] / eTPU_A[13] / GPIO[145] pin 22: eTPU_A[30] / DSPI_C_PCS[3] / eTPU_A[11] / GPIO[144] pin 23: eTPU_A[29] / DSPI_C_PCS[2] / GPIO[143] pin 24: eTPU_A[28] / DSPI_C_PCS[1] / GPIO[142] pin 25: eTPU_A[27] / IRQ[15] / DSPI_C_SOUT_LVDS+ / DSPI_B_SOUT / GPIO[141] pin 26: eTPU_A[26] / IRQ[14] / DSPI_C_SOUT_LVDS– / GPIO[140] pin 27: eTPU_A[25] / IRQ[13] / DSPI_C_SCK_LVDS+ / GPIO[139] pin 28: eTPU_A[24] / IRQ[12] / DSPI_C_SCK_LVDS– / GPIO[138] pin 30: eTPU_A[23] / IRQ[11] / eTPU_A[21] / GPIO[137] pin 32: eTPU_A[22] / IRQ[10] / eTPU_A[17] / GPIO[136] pin 40: eTPU_A[15] / DSPI_B_PCS[5] / GPIO[129] pin 42: eTPU_A[14] / DSPI_B_PCS[4] / eTPU_A[9] / GPIO[128]

105

104

103

102

101

100

117

116

115

114

113

112

111

110

109

108

107

106

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

NIC

TMS

TDI / eMIOS[5] / GPIO[232] eTPU_A[4] / GPIO[227]

TCK

VSS eTPU_A[2] / GPIO[231]

VDDEH7 eTPU_A[29] / GPIO[225]

TDO / eMIOS[6] / GPIO[228]

GPIO[219]

JCOMP

ALT_EVTO

VDDE12

ALT_MSEO[0]

ALT_MSEO[1]

ALT_EVTI

VSS

DSPI_B_PCS[3] / DSPI_C_SIN / GPIO[108]

DSPI_B_SOUT / DSPI_C_PCS[5] / GPIO[104]

DSPI_B_SIN / DSPI_C_PCS[2] / GPIO[103]

DSPI_B_PCS[0] / GPIO[105]

VDDEH6B

DSPI_B_PCS[1] / GPIO[106]

VSS

DSPI_B_PCS[2] / DSPI_C_SOUT / GPIO[107]

DSPI_B_SCK / DSPI_C_PCS[1] / GPIO[102]

DSPI_B_PCS[4] / DSPI_C_SCK / GPIO[109]

DSPI_B_PCS[5] / DSPI_C_PCS[0] / GPIO[110]

VDD

RSTOUT

CAN_C_TX / GPIO[87]

SCI_A_TX / eMIOS[13] / GPIO[89]

SCI_A_RX / eMIOS[15] / GPIO[90]

CAN_C_RX / GPIO[88]

RESET

VSS

VDDEH6A

VSSPLL

XTAL

EXTAL / EXTCLK

VDDPLL

VSS

NIC

Note: Pins marked “NIC” have no internal connection.

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127

GPIO[98]

GPIO[99]

GPIO[206]

(7)

GPIO[207]

(7)

RESET

RSTOUT

PLLREF

IRQ[4]

ETRIG[2]

GPIO[208]

BOOTCFG1

IRQ[3]

ETRIG[3]

GPIO[212]

Name

GPIO

Function

(1)

External Reset Input

External Reset Output

FMPLL Mode Selection

External Interrupt Request eQADC Trigger Input

GPIO

Boot Config. Input

External Interrupt Request eQADC Trigger Input

GPIO

Table 4. SPC563Mx signal properties

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Dedicated GPIO

PCR[98]

PCR[99]

PCR[206]

PCR[207]

—

I/O

VDDEH7

Slow

VDDEH7

Slow

VDDEH7

Slow

VDDEH7

Slow

Reset / Configuration

—

PCR[230]

—

VDDEH6a

Slow

VDDEH6a

Slow

PCR[208]

PCR[212]

011

010

100

000

011

010

100

000

I/O

VDDEH6a

Slow

VDDEH6a

Slow

Reset

State

(5)

– / Up

I / Up

RSTOUT/

Low

PLLREF / Up

BOOTCFG1 /

Down

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

GPIO[98]/Up

GPIO[99]/Up

GPIO[206]/Up

GPIO[207]/Up

RESET /

RSTOUT/

High

– / Up

– / Down

—

141

142

143

144

102

Name

WKPCFG

NMI

DSPI_B_SOUT

GPIO[213]

CAL_ADDR[12:15]

(9)

CAL_ADDR[16]

ALT_MDO[0]

(10)

ALT_MDO[1]

ALT_MDO[2]

ALT_MDO[3]

CAL_ADDR[20:27]

ALT_MDO[4:11]

ALT_MSEO[0]

ALT_MSEO[1]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

Weak Pull Config. Input

Non-Maskable Interrupt

DSPI_B Data Output

GPIO

PCR[213]

Calibration

(8)

I/O

VDDEH6a

Slow

WKPCFG /

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / Up 71 86

Calibration Address Bus

Nexus Msg Data Out

PCR[340]

PCR[345]

—

VDDE12

Fast

VDDE12

(11)

Fast

O / Low

(12)

—

Calibration Address Bus

Nexus Msg Data Out

Calibration Address Bus

Nexus Msg Data Out

Calibration Address Bus

Nexus Msg Data Out

Calibration Address Bus

Nexus Msg Data Out

Calibration Address Bus

Nexus Msg Start/End Out

Calibration Address Bus

Nexus Msg Start/End Out

PCR[345]

—

Fast

Fast

Fast

Fast

Fast

Fast

O / Low

(14)

O / Low

CAL_ADDR /

Low

MDO /

ALT_ADDR

Low

ALT_MDO /

CAL_ADDR

Low

ALT_MDO /

CAL_ADDR

Low

ALT_MDO /

CAL_ADDR

Low

ALT_MDO /

CAL_ADDR

(13)

Low

Low

Low

—

118

117

Name

ALT_EVTO

ALT_MCKO

NEXUSCFG

CAL_CS[0]

CAL_CS[2]

CAL_ADDR[10]

CAL_CS[3]

CAL_ADDR[11]

CAL_DATA[0:9]

CAL_DATA[10:15]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Calibration Address Bus

Nexus Event In

Nexus Event Out

Nexus Msg Clock Out

Nexus/Calibration bus selector

Calibration Chip Selects

Calibration Address Bus

Calibration Chip Selects

Calibration Address Bus

Calibration Data Bus

Calibration Output Enable

Calibration Read/Write

Calibration Transfer Start

Address Latch Enable

Calibration Write Enable

Byte Enable

PCR[345]

PCR[344]

—

PCR[336]

PCR[338]

PCR[339]

PCR[341]

PCR[342]

PCR[343]

PCR[342]

—

TS=0b1

ALE=0b0

—

I/O

Fast

Fast

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

VDDE12

Fast

Reset

State

(5)

—

(15)

O / Low

I / Down

O / High

– / Up

O / High

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

ALT_EVTI /

CAL_ADDR

(16)

ALT_EVTO /

High

ALT_MCKO /

Enabled

NEXUSCFG /

Down

—

116

120

—

CAL_CS / High — —

CAL_CS / High

– / Up

CAL_OE / High

CAL_RD_WR

/High

CAL_TS / High

CAL_WE /

High

—

EVTI

(18) eTPU_A[2]

GPIO[231]

EVTO

eTPU_A[4]

GPIO[227]

MCKO

GPIO[219]

MDO[0]

eTPU_A[13]

GPIO[220]

MDO[1]

eTPU_A[19]

GPIO[221]

MDO[2]

eTPU_A[21]

GPIO[222]

MDO[3]

eTPU_A[25]

GPIO[223]

MSEO[0]

eTPU_A[27]

GPIO[224]

Name

Nexus Event In eTPU A Ch.

GPIO

Nexus Event Out eTPU A Ch.

GPIO

Nexus Msg Clock Out

GPIO

Nexus Msg Data Out eTPU A Ch.

GPIO

Nexus Msg Data Out eTPU A Ch.

GPIO

Nexus Msg Data Out eTPU A Ch.

GPIO

Nexus Msg Data Out eTPU A Ch.

GPIO

Nexus Msg Start/End Out eTPU A Ch.

GPIO

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

PCR[231]

PCR[227]

PCR[219]

PCR[220]

PCR[221]

PCR[222]

PCR[223]

PCR[224]

NEXUS

(17)

(19)

N/A

(19)

I/O

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

VDDEH7

Multi-V

– / –

I / Up

– / –

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / –

I / Up

– / –

103

106

110

111

112

114

109

126

129

122

135

136

137

139

134

Name

MSEO[1]

eTPU_A[29]

GPIO[225]

TCK

TDI

(20) eMIOS[5]

GPIO[232]

TDO

(20)

eMIOS[6]

GPIO[228]

TMS

JCOMP

CAN_A_TX

SCI_A_TX

GPIO[83]

CAN_A_RX

SCI_A_RX

GPIO[84]

CAN_C_TX

GPIO[87]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Nexus Msg Start/End Out eTPU A Ch.

GPIO

PCR[225]

(19)

I/O

VDDEH7

Multi-V

Reset

State

(5)

– / –

JTAG / TEST

JTAG Test Clock Input — — I

VDDEH7

Multi-V

TCK / Down

JTAG Test Data Input eMIOS Ch.

GPIO

JTAG Test Data Output eMIOS Ch.

GPIO

PCR[232]

PCR[228]

(21)

I/O

VDDEH7

Multi-V

VDDEH7

Multi-V

– / –

JTAG Test Mode Select Input

JTAG TAP Controller Enable

—

— I

VDDEH7

Multi-V

VDDEH7

Multi-V

TMS / Up

JCOMP /

Down

CAN_A Transmit eSCI_A Transmit

GPIO

CAN_A Receive eSCI_A Receive

GPIO

CAN_C Transmit

GPIO

PCR[83]

PCR[84]

PCR[87]

CAN

I/O

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Medium

– / Up

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / –

TCK / Down

– / –

TMS / Up

JCOMP / Down

– / Up

(22)

– / Up

101

105

107

100

108

124

128

130

123

131

121

101

Name

CAN_C_RX

GPIO[88]

SCI_A_TX eMIOS[13]

GPIO[89]

SCI_A_RX

(23) eMIOS[15]

GPIO[90]

SCI_B_TX

GPIO[91]

SCI_B_RX

GPIO[92]

DSPI_B_SCK

DSPI_C_PCS[1]

GPIO[102]

DSPI_B_SIN

DSPI_C_PCS[2]

GPIO[103]

DSPI_B_SOUT

DSPI_C_PCS[5]

GPIO[104]

DSPI_B_PCS[0]

GPIO[105]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

CAN_C Receive

GPIO

PCR[88]

I/O

VDDEH6a

Slow

– / Up eSCI_A Transmit eMIOS Ch.

GPIO eSCI_A Receive eMIOS Ch.

GPIO eSCI_B Transmit

GPIO eSCI_B Receive

GPIO

DSPI_B Clock

DSPI_C Periph Chip Select

GPIO

DSPI_B Data Input

DSPI_C Periph Chip Select

GPIO

DSPI_B Data Output

DSPI_C Periph Chip Select

GPIO

DSPI_B Periph Chip Select

GPIO

PCR[89]

PCR[90]

PCR[91]

PCR[92]

PCR[102]

PCR[103]

PCR[104]

PCR[105]

00 eSCI

DSPI

I/O

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6b

Medium

VDDEH6b

Medium

VDDEH6b

Medium

VDDEH6b

Medium

– / Up

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / Up 81 98

– / Up

100

106

112

113

111

Name

AN[0]

(24)

DAN0+

AN[1]

DAN0-

AN[2]

DAN1+

AN[3]

DAN1-

AN[4]

DAN2+

DSPI_B_PCS[1]

GPIO[106]

DSPI_B_PCS[2]

DSPI_C_SOUT

GPIO[107]

DSPI_B_PCS[3]

DSPI_C_SIN

GPIO[108]

DSPI_B_PCS[4]

DSPI_C_SCK

GPIO[109]

DSPI_B_PCS[5]

DSPI_C_PCS[0]

GPIO[110]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

DSPI_B Periph Chip Select

GPIO

DSPI_B Periph Chip Select

DSPI_C Data Output

GPIO

DSPI_B Periph Chip Select

DSPI_C Data Input

GPIO

DSPI_B Periph Chip Select

DSPI_C Clock

GPIO

DSPI_B Periph Chip Select

DSPI_C Periph Chip Select

GPIO

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

PCR[106]

PCR[107]

PCR[108]

PCR[109]

PCR[110]

—

00 eQADC

I/O

—

VDDEH6b

Medium

VDDEH6b

Medium

VDDEH6b

Medium

VDDEH6b

Medium

VDDEH6b

Medium

VDDA

– / Up

I / –

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / Up 92 109

– / Up

AN[0] / –

AN[1] / –

AN[2] / –

AN[3] / –

AN[4] / –

143

142

141

140

139

107

114

105

104

172

171

170

169

168

Name

AN[5]

DAN2-

AN[6]

DAN3+

AN[7]

DAN3-

AN[8]

AN[9]

ANX

AN[10]

AN[11]

ANZ

AN[12]

MA[0]

ETPU_A[19]

SDS

AN[13]

MA[1]

ETPU_A[21]

SDO

AN[14]

MA[2]

ETPU_A[27]

SDI

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

Single Ended Analog Input

Negative Terminal Diff. Input

Single Ended Analog Input

Positive Terminal Diff. Input

Single Ended Analog Input

Negative Terminal Diff. Input

See AN[38]-AN[8]-ANW

Single Ended Analog Input

External Multiplexed Analog

Input

See AN[39]-AN[10]-ANY

Single Ended Analog Input

External Multiplexed Analog

Input

Single Ended Analog Input

Mux Address

ETPU_A Ch.

eQADC Serial Data Strobe

Single Ended Analog Input

Mux Address

ETPU_A Ch.

eQADC Serial Data Out

Single Ended Analog Input

Mux Address

ETPU_A Ch.

eQADC Serial Data In

—

PCR[215]

PCR[216]

PCR[217]

—

011

010

100

000

011

010

100

000

011

010

100

000

VDDA

VDDEH7

I / –

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

AN[5] / – 138 167

AN[6] / –

AN[7] / –

AN[9] / –

AN[11] / –

AN[12] / –

AN[13] / –

AN[14] / –

137

136

166

165

119 148

118 147

117 146

Name

AN[24]

AN[25]

AN[27]

AN[28]

AN[30]

AN[31]

AN[32]

AN[33]

AN[15]

FCK

ETPU_A[29]

AN[16]

AN[17]

AN[18]

AN[21]

AN[22]

AN[23]

AN[34]

AN[35]

AN[36]

AN[37]

AN[38]-AN[8]-

ANW

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

Single Ended Analog Input eQADC Free Running Clock

ETPU_A Ch.

Single Ended Analog Input

Multiplexed Analog Input

PCR[218]

—

011

010

000

—

VDDA

VDDEH7

VDDA

I / –

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

AN[15] / –

AN[x] / –

AN[38] / –

116 145

124

123

122

121

128

127

126

125

—

132

131

130

129

144

153

152

151

150

157

156

155

154

174

175

161

160

159

158

173

Name

AN[39]-AN[10]-

ANY

VRH

VRL

REFBYPC eTPU_A[0] eTPU_A[12] eTPU_A[19]

GPIO[114] eTPU_A[1] eTPU_A[13]

GPIO[115] eTPU_A[2] eTPU_A[14]

GPIO[116] eTPU_A[3] eTPU_A[15]

GPIO[117] eTPU_A[4] eTPU_A[16]

GPIO[118] eTPU_A[5] eTPU_A[17]

DSPI_B_SCK_LVDS-

GPIO[119]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

Single Ended Analog Input

Multiplexed Analog Input

Voltage Reference High

Voltage Reference Low

Bypass Capacitor Input

—

— I VDDA

VDDA

VSSA0

VRL

I / –

– / –

– / – eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

DSPI_B CLOCK LVDS-

GPIO

PCR[114]

PCR[115]

PCR[116]

PCR[117]

PCR[118]

PCR[119]

—

— eTPU2

011

010

100

000

001

010

100

000

I/O

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

AN[39] / –

VRH

VRL

REFBYPC

– / WKPCFG – / WKPCFG

134

133

135

163

162

164

Name eTPU_A[6] eTPU_A[18]

DSPI_B_SCK_LVDS+

GPIO[120] eTPU_A[7] eTPU_A[19]

DSPI_B_SOUT_LVDSeTPU_A[6]

GPIO[121] eTPU_A[8] eTPU_A[20]

DSPI_B_SOUT_LVDS+

GPIO[122] eTPU_A[9] eTPU_A[21]

GPIO[123] eTPU_A[10] eTPU_A[22]

GPIO[124] eTPU_A[11] eTPU_A[23]

GPIO[125] eTPU_A[12]

DSPI_B_PCS[1]

GPIO[126]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eTPU_A Ch.

eTPU_A Ch.

DSPI_B Clock LVDS+

GPIO eTPU_A Ch.

eTPU_A Ch.

DSPI_B Data Output LVDSeTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

DSPI_B Data Output LVDS+

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

eTPU_A Ch.

GPIO eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO

PCR[120]

PCR[121]

PCR[122]

PCR[123]

PCR[124]

PCR[125]

PCR[126]

001

010

100

000

001

010

100

000

0001

0010

0100

1000

0000

I/O

VDDEH1b

Medium

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Medium

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

Name eTPU_A[13]

DSPI_B_PCS[3]

GPIO[127] eTPU_A[14]

DSPI_B_PCS[4] eTPU_A[9]

GPIO[128] eTPU_A[15]

DSPI_B_PCS[5]

GPIO[129] eTPU_A[16]

GPIO[130] eTPU_A[17]

GPIO[131] eTPU_A[18]

GPIO[132] eTPU_A[19]

GPIO[133] eTPU_A[20]

IRQ[8]

GPIO[134] eTPU_A[21]

IRQ[9]

GPIO[135]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO eTPU_A Ch.

DSPI_B Periph Chip Select eTPU_A Ch.

GPIO eTPU_A Ch.

DSPI_B Periph Chip Select

GPIO eTPU_A Ch.

External Interrupt Request

GPIO eTPU_A Ch.

External Interrupt Request

GPIO

PCR[127]

PCR[128]

PCR[129]

PCR[130]

PCR[131]

PCR[132]

PCR[133]

PCR[134]

PCR[135]

001

010

100

000

I/O

VDDEH1b

Medium

VDDEH1b

Medium

VDDEH1b

Medium

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1a

Slow

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

Name Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eTPU_A[22]

IRQ[10] eTPU_A[17]

GPIO[136] eTPU_A[23]

IRQ[11] eTPU_A[21]

GPIO[137] eTPU_A[24]

(25)

IRQ[12]

DSPI_C_SCK_LVDS-

GPIO[138]

eTPU_A[25]

IRQ[13]

DSPI_C_SCK_LVDS+

GPIO[139]

eTPU_A[26]

IRQ[14]

DSPI_C_SOUT_LVDS-

GPIO[140]

eTPU_A[27]

IRQ[15]

DSPI_C_SOUT_LVDS+

DSPI_B_SOUT

GPIO[141] eTPU_A Ch.

External Interrupt Request eTPU_A Ch. External

GPIO eTPU_A Ch.

External Interrupt Request eTPU_A Ch. External

GPIO eTPU_A Ch.

External Interrupt Request

DSPI_C Clock LVDS-

GPIO eTPU_A Ch.

External Interrupt Request

DSPI _C Clock LVDS+

GPIO eTPU_A Ch.

External Interrupt Request

DSPI_C Data Output LVDS-

GPIO eTPU_A Ch.

External Interrupt Request

DSPI_C Data Output LVDS+

DSPI_B Data Output

GPIO

PCR[136]

PCR[137]

PCR[138]

PCR[139]

PCR[140]

PCR[141]

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

0001

0010

0100

1000

0000

I/O

VDDEH1a

Slow

VDDEH1a

Slow

VDDEH1a

Slow

VDDEH1a

Medium

VDDEH1a

Slow

VDDEH1a

Slow

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

Name

eTPU_A[28]

DSPI_C_PCS[1]

GPIO[142]

eTPU_A[29]

contains details on the multiplexed signals that appear in Table 4 .

DSPI_C_PCS[2]

GPIO[143] eTPU_A[30]

DSPI_C_PCS[3] eTPU_A[11]

GPIO[144] eTPU_A[31]

DSPI_C_PCS[4] eTPU_A[13]

GPIO[145] eMIOS[0] eTPU_A[0] eTPU_A[25]

(26)

GPIO[179] eMIOS[1] eTPU_A[1]

GPIO[180] eMIOS[2] eTPU_A[2]

GPIO[181] eMIOS Ch.

eTPU_A Ch.

GPIO eMIOS Ch.

eTPU_A Ch.

GPIO eMIOS Ch.

eTPU_A Ch.

GPIO

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eTPU_A Ch. (Input and

Output)

DSPI_C Periph Chip Select

GPIO eTPU_A Ch. (Input and

Output)

DSPI_C Periph Chip Select

GPIO eTPU_A Ch.

DSPI_C Periph Chip Select eTPU_A Ch.

GPIO eTPU_A Ch.

DSPI_C Periph Chip Select eTPU_A Ch.

GPIO

PCR[142]

PCR[143]

PCR[144]

PCR[145]

PCR[179]

PCR[180]

PCR[181]

I/O

011

010

001

000

011

010

001

000 eMIOS

001

010

100

000

I/O

VDDEH1a

Medium

VDDEH1a

Medium

VDDEH1a

Medium

VDDEH1a

Medium

VDDEH1b

Slow

VDDEH1b

Slow

VDDEH1b

Slow

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

—

Name eMIOS[4] eTPU_A[4]

GPIO[183] eMIOS[8] eTPU_A[8]

(27)

SCI_B_TX

GPIO[187] eMIOS[9] eTPU_A[9]

(27)

SCI_B_RX

GPIO[188] eMIOS[10]

GPIO[189] eMIOS[11]

GPIO[190] eMIOS[12]

DSPI_C_SOUT eTPU_A[27]

GPIO[191] eMIOS[13]

GPIO[192] eMIOS[14]

IRQ[0] eTPU_A[29]

GPIO[193]

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eMIOS Ch.

eTPU_A Ch.

GPIO eMIOS Ch.

eTPU_A Ch.

eSCI_B Transmit

GPIO eMIOS Ch.

eTPU_A Ch.

eSCI_B Receive

GPIO eMIOS Ch.

DSPI C Data Output eTPU_A Ch.

GPIO eMIOS Ch.

External Interrupt Request eTPU_A Ch.

GPIO

PCR[183]

PCR[187]

PCR[188]

PCR[189]

PCR[190]

PCR[191]

PCR[192]

PCR[193]

001

010

100

000

001

010

100

000

001

010

100

000

001

010

100

000

I/O

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a

Medium

VDDEH6a – / WKPCFG – / WKPCFG

VDDEH6a

Slow

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

—

VDDPLL

VSSPLL

(30)

VSTBY

VRC33

VRCCTL

VDDA

(31)

VDDA0

VSSA0

Name eMIOS[15]

IRQ[1]

GPIO[194] eMIOS[23]

GPIO[202]

XTAL

EXTAL

EXTCLK

Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5) eMIOS Ch.

External Interrupt Request

GPIO eMIOS Ch.

GPIO

PCR[194]

PCR[202]

—

I/O

Clock Synthesizer

— O

VDDEH6a

Slow

VDDEH6a

Slow

VDDEH6a O / –

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

– / WKPCFG – / WKPCFG

XTAL

(28)

/ –

—

93 Crystal Oscillator Output

Crystal Oscillator Input

External Clock Input

— — I VDDEH6a I / – EXTAL

(29)

/ – 75 92

Power / Ground

PLL Supply Voltage —

—

— I

VDDPLL

(1.2V)

VSSPLL

I / –

—

94 PLL Ground

Power Supply for Standby

RAM

3.3V Voltage Regulator

Bypass Capacitor

Voltage Regulator Control

Output

Analog Power Input for eQADC

Analog Ground Input for eQADC

—

VSTBY

VRC33

VDDA (5.0 V)

VDDA

VSSA

I / –

O / –

I / –

—

Name Function

(1)

Table 4. SPC563Mx signal properties (continued)

Pad

Config.

Register

(PCR)

(2)

PCR PA

Field

(3)

I/O

Type

Voltage

(4)

Pad Type

Reset

State

(5)

Pin No.

Function / State

After Reset

(6) LQFP

144

LQFP

176

VDDA1

VSSA1

VSSA

(32)

Analog Power Input for eQADC

Analog Ground Input for eQADC

—

— I

I VDDA

VSSA

I / –

—

VDDREG Voltage Regulator Supply — — I

VDDREG

(5.0 V)

I / – — 10 10

VDD

VSS

VDDEH1A

VDDEH1B

VDDEH6a

VDDEH6b

(33)

(35),(36)

(36)

Internal Logic Supply Input

Ground

I/O Supply Input

—

–

VDD (1.2 V)

VSS0

VDDEH1

(34)

(3.3V – 5.0V)

VDDEH6

(3.3V – 5.0V)

I / –

—

26, 53,

86,

120

33, 62,

103,

149

22, 36,

48, 59,

73, 79,

91,

104,

115

15, 29,

43, 57,

72, 90,

96,

108,

115,

127,

133,

140

24, 34,

31, 41

78, 93,

95,

110,

VDDEH6

VDDEH7

I/O Supply Input

—

— I

I VDDEH6

VDDEH7

(37)

(3.3V – 5.0V)

I / –

—

102,

113

For each pin in the table, each line in the Function column is a separate function of the pin. For all I/O pins the selection of primary pin function or secondary function or

GPIO is done in the SIU except where explicitly noted.

—

125,

138

Values in this column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number. For example, PCR[190] refers to the SIU register named SIU_PCR190.

The Pad Configuration Register (PCR) PA field is used by software to select pin function.

The VDDE and VDDEH supply inputs are broken into segments. Each segment of slow I/O pins (VDDEH) may have a separate supply in the 3.3 V to 5.0 V range (–

10 %/+5 %). Each segment of fast I/O (VDDE) may have a separate supply in the 1.8 V to 3.3 V range (+/– 10 %).

Terminology is O — output, I — input, Up — weak pull up enabled, Down — weak pull down enabled, Low — output driven low, High — output driven high. A dash for the function in this column denotes that both the input and output buffer are turned off.

Function after reset of GPI is general purpose input. A dash for the function in this column denotes that both the input and output buffer are turned off.

The GPIO functions on GPIO[206] and GPIO[207] can be selected as trigger functions in the SIU for the ADC by making the proper selections in the SIU_ETISR and

SIU_ISEL3 registers in the SIU.

Some signals in this section are available only on calibration package.

These pins are only available in the calibration package.

10. On the calibration package, the Nexus function on this pin is enabled when the NEXUSCFG pin is high and Nexus is configured to full port mode. On the 176-pin package, the Nexus function on this pin is enabled permanently. Do not connect the Nexus MDO or MSEO pins directly to a power supply or ground.

11. In the calibration package, the I/O segment containing this pin is called VDDE12.

12. When configured as Nexus (calibration package with NEXUSCFG=1), and JCOMP is asserted during reset, MDO[0] is driven high until the crystal oscillator becomes stable, at which time it is then negated.

13. The function of this pin is Nexus when NEXUSCFG is high.

14. High when the pin is configured to Nexus, low otherwise.

15. O/Low for the calibration with NEXUSCFG=0; I/Up otherwise.

16. ALT_ADDR/Low for the calibration package with NEXUSCFG=0; EVTI/Up otherwise.

17. In 176-pin package, the Nexus function is disabled and the pin/ball has the secondary function

18. This signal is not available in the 176-pin package.

19. The primary function is not selected via the PA field when the pin is a Nexus signal. Instead, it is activated by the Nexus controller.

20. TDI and TDO are required for JTAG operation.

21. The primary function is not selected via the PA field when the pin is a JTAG signal. Instead, it is activated by the JTAG controller.

22. The function and state of the CAN_A and eSCI_A pins after execution of the BAM program is determined by the BOOTCFG1 pin.

23. Connect an external 10K pull-up resistor to the SCI_A_RX pin to ensure that the pin is driven high during CAN serial boot.

24. For pins AN[0:7], during and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock propagates through the device.

25. ETPUA[24:29] are input and output. The input muxing is controlled by SIU_ISEL8 register.

26. eTPU_A[25] is an output only function.

27. Only the output channels of eTPU[8:9] are connected to pins.

28. The function after reset of the XTAL pin is determined by the value of the signal on the PLLCFG[1] pin. When bypass mode is chosen XTAL has no function and should be grounded.

29. The function after reset of the EXTAL_EXTCLK pin is determined by the value of the signal on the PLLCFG[1] pin. If the EXTCLK function is chosen, the valid operating voltage for the pin is 1.62 V to 3.6 V. If the EXTAL function is chosen, the valid operating voltage is 3.3 V.

30. VSSPLL and VSSREG are connected to the same pin.

31. This pin is shared by two pads: VDDA_AN, using pad_vdde_hv, and VDDA_DIG, using pad_vdde_int_hv.

32. This pin is shared by two pads: VSSA_AN, using pad_vsse_hv, and VSSA_DIG, using pad_vsse_int_hv.

33. VDDEH1A, VDDEH1B, and VDDEH1AB are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

34. LVDS pins will not work at 3.3 V.

35. The VDDEH6 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.

36. VDDEH6A and VDDEH6B are shorted together in all production packages. The separation of the signal names is present to support legacy naming, however they should be considered as the same signal in this document.

37. If using JTAG or Nexus, the I/O segment that contains the JTAG and Nexus pins must be powered by a 5 V supply. The 3.3 V Nexus/JTAG signals are derived from the 5 volt power supply.

SPC563M64x, SPC563M60x

Pad Type

Slow

Medium

Fast

MultiV

Analog

LVDS

Pinout and signal description

Name

Table 5. Pad types

Supply Voltage pad_ssr_hv pad_msr_hv pad_fc pad_multv_hv

3.0 V – 5.25 V

3.0 V – 3.6 V

3.0 V – 5.25 V (high swing mode)

4.5 V – 5.25 V (low swing mode) pad_ae_hv 0.0 – 5.25 V pad_lo_lv —

EXTAL

EXTCLK

PLLREF

Table 6

CLKOUT

Signal

XTAL

SCK_B_LVDS–

SCK_B_LVDS+

SOUT_B_LVDS–

SOUT_B_LVDS+

SCK_C_LVDS–

SCK_C_LVDS+

SOUT_C_LVDS–

SOUT_C_LVDS+

PCS_B[0]

PCS_C[0]

PCS_B[1:5]

PCS_C[1:5]

SCK_B

SCK_C

SIN_B

SIN_C

Clock Generation

Table 6. Signal details

Module or Function Description

SPC563Mxx clock output for the calibration bus interface

Input pin for an external crystal oscillator or an external clock source based on the value driven on the PLLREF pin at reset.

External clock input

PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset. PLLREF=0 selects external reference mode.

Crystal oscillator input

DSPI

DSPI_B – DSPI_C

LVDS pair used for DSPI_B TSB mode transmission

LVDS pair used for DSPI_C TSB mode transmission

Peripheral chip select when device is in master mode—slave select when used in slave mode

Peripheral chip select when device is in master mode—not used in slave mode

DSPI clock—output when device is in master mode; input when in slave mode

DSPI data in

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CAL_EVTO

CAL_MCKO

NEXUSCFG eMIOS[0:23]

AN[0:39]

FCK

MA[0:2]

REFBYPC

SDI

SDO

SDS

VRH

VRL

SCI_A_RX

SCI_B_RX

SCI_A_TX

SCI_B_TX

ETPU_A[0:31]

CAN_A_TX

CAN_C_TX

Pinout and signal description

SOUT_B

SOUT_C

Signal

CAL_ADDR[12:30]

CAL_CS[0:3]

CAL_DATA[0:15]

CAL_OE

CAL_RD_WR

CAL_TS_ALE

SPC563M64x, SPC563M60x

Table 6. Signal details (continued)

Module or Function Description

DSPI_B – DSPI_C DSPI data out

Calibration Bus

The CAL_ADDR[12:30] signals specify the physical address of the bus transaction.

CSx is asserted by the master to indicate that this transaction is targeted for a particular memory bank on the Primary external bus.

The CAL_DATA[0:15] signals contain the data to be transferred for the current transaction.

OE is used to indicate when an external memory is permitted to drive back read data. External memories must have their data output buffers off when OE is negated. OE is only asserted for chip-select accesses.

RD_WR indicates whether the current transaction is a read access or a write access.

The Transfer Start signal (TS) is asserted by the SPC563Mxx to indicate the start of a transfer.

The Address Latch Enable (ALE) signal is used to demultiplex the address from the data bus.

Calibration Bus

Nexus Event Out

Nexus Message Clock Out

Nexus/Calibration Bus Nexus/Calibration Bus selector eMIOS eQADC eQADC eQADC eMIOS I/O channels

Single-ended analog inputs for analog-to-digital converter eQADC free running clock for eQADC SSI.

These three control bits are output to enable the selection for an external Analog Mux for expansion channels.

Bypass capacitor input eQADC eQADC eQADC eQADC eQADC eQADC

Serial data in

Serial data out

Serial data select

Voltage reference high input

Voltage reference low input eSCI_A – eSCI_B eSCI receive eSCI_A – eSCI_B eTPU

FlexCAN_A –

FlexCAN_C eSCI transmit eTPU I/O channel

FlexCAN transmit

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Signal

CAN_A_RX

CAN_C_RX

JCOMP

TCK

TDI

TDO

TMS

EVTI

EVTO

MCKO

MDO[3:0]

MSEO[1:0]

BOOTCFG[1]

WKPCFG

ETRIG[2:3]

IRQ[0:15]

Pinout and signal description

Table 6. Signal details (continued)

Module or Function Description

FlexCAN_A –

FlexCAN_C

FlexCAN receive

JTAG

Nexus

Enables the JTAG TAP controller.

Clock input for the on-chip test and debug logic.

Serial test instruction and data input for the on-chip test and debug logic.

Serial test data output for the on-chip test logic.

Controls test mode operations for the on-chip test and debug logic.

EVTI is an input that is read on the negation of RESET to enable or disable the Nexus Debug port. After reset, the EVTI pin is used to initiate program synchronization messages or generate a breakpoint.

Nexus

Output that provides timing to a development tool for a single watchpoint or breakpoint occurrence.

MCKO is a free running clock output to the development tools which is used for timing of the MDO and MSEO signals.

Trace message output to development tools. This pin also indicates the status of the crystal oscillator clock following a power-on reset, when MDO[0] is driven high until the crystal oscillator clock achieves stability and is then negated.

Output pin—Indicates the start or end of the variable length message on the MDO pins

SIU – Configuration

The BOOTCFG1 pin is sampled during the assertion of the

RSTOUT signal, and the value is used to update the RSR and the BAM boot mode

The following values are for BOOTCFG[0:1}:

0 Boot from internal Flash memory

1 FlexCAN/eSCI boot

The WKPCFG pin is applied at the assertion of the internal reset signal (assertion of RSTOUT), and is sampled 4 clock cycles before the negation of the RSTOUT pin.

The value is used to configure whether the eTPU and eMIOS pins are connected to internal weak pull up or weak pull down devices after reset. The value latched on the WKPCFG pin at reset is stored in the Reset Status Register (RSR), and is updated for all reset sources except the Debug Port Reset and

Software External Reset.

0: Weak pulldown applied to eTPU and eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS pins at reset.

SIU – eQADC Triggers External signal eTRIGx triggers eQADC CFIFOx

SIU – External

Interrupts

The IRQ[0:15] pins connect to the SIU IRQ inputs. IMUX Select

IRQs.

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Pinout and signal description

NMI

GPIO[n]

RESET

RSTOUT

Signal

SPC563M64x, SPC563M60x

Table 6. Signal details (continued)

Module or Function Description

SIU – External

Interrupts

Non-Maskable Interrupt

SIU – GPIO

SIU – Reset

Configurable general purpose I/O pins. Each GPIO input and output is separately controlled by an 8-bit input (GPDI) or output (GPDO) register. Additionally, each GPIO pins is configured using a dedicated SIU_PCR register.

The GPIO pins are generally multiplexed with other I/O pin functions.

The RESET pin is an active low input. The RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over.

The RESET pin has a glitch detector which detects spikes greater than two clock cycles in duration that fall below the switch point of the input buffer logic of the VDDEH input pins.

The switch point lies between the maximum VIL and minimum

VIH specifications for the VDDEH input pins.

The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the

MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the

RSTOUT pin.

Power

Segment

VDDA0

Table 7 gives the power/ground segmentation of the SPC563Mx MCU. Each segment

provides the power and ground for the given set of I/O pins, and can be powered by any of the allowed voltages regardless of the power on the other segments.

VDDEH1 (a, b)

Table 7. SPC563Mx Power/Ground Segmentation

144-LQFP Pin

Number

176-LQFP Pin

Number

Voltage

Range

(1)

I/O Pins Powered by Segment

24, 34

31, 41

5.0 V

3.3 V – 5.0 V

AN[0:7], AN[9], AN[11], AN[16:18],

AN[21:25], AN[27:28], AN[30:37], AN38,

AN39, VRL, REFBYPC,

VRH

PCKCFG[2], eTPU_A[0:31], eMIOS[0:2]

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Power

Segment

Table 7. SPC563Mx Power/Ground Segmentation (continued)

144-LQFP Pin

Number

176-LQFP Pin

Number

Voltage

Range

(1)

I/O Pins Powered by Segment

VDDEH6 (a, b)

VDDEH7

VDDE12

(2)

(3)

78, 93

102, 113

—

95, 110

125, 138

16, 119

3.3 V – 5.0 V

1.8 V – 3.3 V

RESET, RSTOUT, WKPCFG,

BOOTCFG1, PLLREF, SCK_B,

PCKCFG[0],

CAN_A_TX, CAN_A_RX, CAN_C_TX,

CAN_C_RX,

SCI_A_TX, SCI_A_RX, SCI_B_TX,

SCI_B_RX,

SCK_B, SIN_B, SOUT_B,

DSPI_B_PCS_B[0:5], eMIOS[4], eMIOS[8:15], eMIOS[23],

XTAL, EXTAL

PCKCFG[1],

MDO[0:3], EVTI, EVTO, MCKO,

MSEO[0:1], TDO, TDI, TMS, TCK,

JCOMP, AN[12:15]

(GPIO[98:99],

GPIO[206:207])

CAL_ADDR[12:30], CAL_DATA[0:15],

CAL_CS[0], CAL_CS[2:3],

CAL_RD_WR, CAL_WE[0:1], CAL_OE,

CAL_TS, ALT_MCKO, ALT_EVTO,

NEXUSCFG

These are nominal voltages. All VDDE and VDDEH voltages are –5 %, +10 % (VDDE 1.62 V to 3.6 V, VDDEH 3.0 V to

5.5 V). VDDA is +5 %, –10 %.

The VDDEH7 segment may be powered from 3.0 V to 5.0 V for mux address or SSI functions, but must meet the VDDA specifications of 4.5 V to 5.25 V for analog input function.

In the calibration package this signal is named VDDE12.

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Electrical characteristics SPC563M64x, SPC563M60x

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications for the SPC563Mxx series of MCUs.In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement is included in the

Symbol column.

The electrical parameters shown in this document are guaranteed by various methods. To

provide a better understanding, the classifications listed in Table 8 are used and the

parameters are tagged accordingly in the tables. Note that only Controller Characteristics

(“CC”) are classified. System Requirements (“SR”) are operating conditions that must be provided to ensure normal device operation.

Classification tag

Table 8. Parameter classifications

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category.

Those parameters are derived mainly from simulations.

Note: The classification is shown in the column labeled “C” in the parameter tables where appropriate.

FLASH

STBY

DDPLL

RC33

(5)

Symbol

Table 9. Absolute maximum ratings

(1)

Parameter

SR 1.2 V core supply voltage

(2)

SR Flash core voltage

(3)

SR SRAM standby voltage

(4)

SR Clock synthesizer voltage

Voltage regulator control input voltage

Conditions min

– 0.3

Value max

1.32

5.5

1.32

3.6

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SPC563M64x, SPC563M60x Electrical characteristics

Table 9. Absolute maximum ratings

(1)

(continued)

Value

Symbol Parameter Conditions Unit min max

DDA

DDE

DDEH

– V

SSPLL

DDREG

– V

STG

SDR

SSA

– V

MAXD

MAXA

Analog supply voltage

SR I/O supply voltage

(6)

I/O supply voltage

Reference to V

SSA

SR DC input voltage

(7)

DDEH

powered I/O pads

DDE

powered I/O pads

DDA

powered I/O pads

Voltage regulator supply

voltage

(6)

Analog reference high voltage

SR V

differential voltage

SR V

REF

differential voltage

(6)

VRL to V

SSA

differential voltage

SSPLL

to V

differential voltage

Maximum DC digital input current

(11)

Reference to VRL

Per pin, applies to all digital pins

Maximum DC analog input current

(12)

Per pin, applies to all analog pins

Maximum operating temperature range

(13)

– die junction temperature

SR Storage temperature range

Maximum solder temperature

(14)

SR Moisture sensitivity level

(15)

– 0.3

–1.0

D Junction-to-Ambient, Natural Convection

–1.0

– 0.3

– 0.1

– 0.3

– 0.1

– 3

—

– 40.0

– 55.0

—

(8)

DDEH

DDE

DDA

5.5

3.6

5.5

+ 0.3 V

(10)

+ 0.3 V

5.5

0.1

5.5

0.3

0.1

150.0

260.0

(9)

V mA mA o o o

MSL — 3 —

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or cause permanent damage to the device.

Allowed 2 V for 10 hours cumulative time, remaining time at 1.2 V +10%.

The V

FLASH

supply is connected to V

DDEH1

Allowed 6.8 V for 10 hours cumulative time, remaining time at 5 V +10%.

The pin named as V

RC33

is internally connected to the pads V

FLASH

and V apply when the internal regulator is disabled and V

RC33

in the LQFP144 package. These limits

power is supplied externally.

All functional non-supply I/O pins are clamped to V

SS and V

DDE

, or V

DDEH

AC signal overshoot and undershoot of up to 2.0 V of the input voltages is permitted for an accumulative duration of 60 hours over the complete lifetime of the device (injection current not limited for this duration).

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Electrical characteristics SPC563M64x, SPC563M60x

Internal structures hold the voltage greater than –1.0 V if the injection current limit of 2 mA is met.

Internal structures hold the input voltage less than the maximum voltage on all pads powered by V maximum injection current specification is met (2 mA for all pins) and V

DDEH

supplies, if the

DDEH

is within the operating voltage specifications.

10. Internal structures hold the input voltage less than the maximum voltage on all pads powered by V

DDE maximum injection current specification is met (2 mA for all pins) and V

DDE

supplies, if the

is within the operating voltage specifications.

11. Total injection current for all pins (including both digital and analog) must not exceed 25 mA.

12. Total injection current for all analog input pins must not exceed 15 mA.

13. Lifetime operation at these specification limits is not guaranteed.

14. Solder profile per CDF-AEC-Q100.

15. Moisture sensitivity per JEDEC test method A112.

Table 10. Thermal characteristics for 144-pin LQFP

JA

R JA

R JMA

R JB

R JCtop

Symbol C Parameter

CC D Junction-to-Ambient, Natural Convection

(1)

D Junction-to-Ambient (@200 ft/min)

D Junction-to-Ambient (@200 ft/min)

D Junction-to-Ambient, Natural Convection

CC D Junction-to-Board

(2)

CC D Junction-to-Case (Top)

(3)

Conditions

Single layer board – 1s

Four layer board – 2s2p

Single layer board –1s

Four layer board – 2s2p



CC D

Junction-to-Package Top, Natural

Convection

(4)

Value

Unit

°C/W

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

°C/W

Table 11. Thermal characteristics for 176-pin LQFP

Symbol

JA

C Parameter

CC D Junction-to-Ambient, Natural Convection

(1)

D Junction-to-Moving-Air, Ambient

Conditions

Single layer board - 1s

Four layer board - 2s2p

R JMA CC

D Junction-to-Moving-Air, Ambient

@200 ft./min., single layer board - 1s

R JMA CC

@200 ft./min., four layer board - 2s2p

R JB CC D Junction-to-Board

(2)

Value

Unit

°C/W

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Table 11. Thermal characteristics for 176-pin LQFP (continued)

Symbol

JCtop

C Parameter

CC D Junction-to-Case

(3)



CC D

Junction-to-Package Top, Natural

Convection

(4)

Conditions Value

Unit

°C/W

Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test board meets

JEDEC specification for this package.

Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification for the specified package.

4.3.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T

, can be obtained from the equation:

Equation 1 T

= T

+ (R JA * P

) where:

= ambient temperature for the package ( o

R JA = junction-to-ambient thermal resistance ( o

C/W)

= power dissipation in the package (W)

The thermal resistance values used are based on the JEDEC JESD51 series of standards to provide consistent values for estimations and comparisons. The difference between the values determined for the single-layer (1s) board compared to a four-layer board that has two signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal resistance is not a constant. The thermal resistance depends on the:



Construction of the application board (number of planes)



Effective size of the board which cools the component



Quality of the thermal and electrical connections to the planes



Power dissipated by adjacent components

Connect all the ground and power balls to the respective planes with one via per ball. Using fewer vias to connect the package to the planes reduces the thermal performance. Thinner planes also reduce the thermal performance. When the clearance between the vias leave the planes virtually disconnected, the thermal performance is also greatly reduced.

As a general rule, the value obtained on a single-layer board is within the normal range for the tightly packed printed circuit board. The value obtained on a board with the internal planes is usually within the normal range if the application board has:



One oz. (35 micron nominal thickness) internal planes



Components are well separated



Overall power dissipation on the board is less than 0.02 W/cm2

The thermal performance of any component depends on the power dissipation of the surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board

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Electrical characteristics SPC563M64x, SPC563M60x temperature at the perimeter (edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

Equation 2 T

= T

+ (R JB * P

) where:

= board temperature for the package perimeter ( o

R JB = junction-to-board thermal resistance ( o

C/W) per JESD51-8S

= power dissipation in the package (W)

When the heat loss from the package case to the air does not factor into the calculation, an acceptable value for the junction temperature is predictable. Ensure the application board is similar to the thermal test condition, with the component soldered to a board with internal planes.

The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus a case-to-ambient thermal resistance:

Equation 3 R

JA

= R

JC

+ R

CA where:

R JA = junction-to-ambient thermal resistance ( o

C/W)

JC

= junction-to-case thermal resistance ( o

C/W)

R CA = case to ambient thermal resistance ( o

C/W)

R JC is device related and is not affected by other factors. The thermal environment can be controlled to change the case-to-ambient thermal resistance, R CA . For example, change the air flow around the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. This description is most useful for packages with heat sinks where

90% of the heat flow is through the case to heat sink to ambient. For most packages, a better model is required.

A more accurate two-resistor thermal model can be constructed from the junction-to-board thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal resistance describes when using a heat sink or where a substantial amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance describes the thermal performance when most of the heat is conducted to the printed circuit board. This model can be used to generate simple estimations and for computational fluid dynamics (CFD) thermal models.

To determine the junction temperature of the device in the application on a prototype board, use the thermal characterization parameter (



) to determine the junction temperature by measuring the temperature at the top center of the package case using the following equation:

Equation 4 T

= T

+ (



x P

)

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

= thermocouple temperature on top of the package ( o

= thermal characterization parameter ( o

= power dissipation in the package (W)

C/W)

The thermal characterization parameter is measured in compliance with the JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. Position the thermocouple so that the thermocouple junction rests on the package. Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire extending from the junction. Place the thermocouple wire flat against the package case to avoid measurement errors caused by the cooling effects of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

USA

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering

Documents at 800-854-7179 or 303-397-7956.

JEDEC specifications are available on the jedec.org web site.



C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.



G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled

Applications”, Electronic Packaging and Production, pp. 53-58, March 1998.



B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal

Resistance and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San

Diego, 1999, pp. 212-220.

DocID14642 Rev 12 73/128

127

Electrical characteristics SPC563M64x, SPC563M60x

Table 12. EMI testing specifications

(1)

Symbol Parameter Conditions f

OSC

BUS

Frequency

Radiated

Emissions

EME

Device

Configuration, test conditions and EM testing per standard

IEC61967-2;

Supply Voltage =

5.0V DC, Ambient

Temperature =

25 °C, Worst-case

Orientation

Oscillator

Frequency = 8

MHz;

System Bus

Frequency = 80

MHz;

No PLL

Frequency

Modulation

150 kHz – 50

MHz

50–150 MHz

150–500 MHz

500–1000 MHz

IEC Level

Oscillator

Frequency = 8

MHz;

System Bus

Frequency = 80

MHz;

1% PLL

Frequency

Modulation

150 kHz – 50

MHz

50–150 MHz

150–500 MHz

500–1000 MHz

IEC Level

IEC Classification Level: L = 24 dBµV; K = 30 dBµV.

Level

(Typ)

Unit dB

V

— dB

V

—

Table 13. ESD ratings

(1),(2)

Parameter Conditions Symbol Value Unit

—

SR ESD for Human Body Model (HBM)

HBM circuit description

ESD for field induced charge Model

(FCDM)

Number of pulses per pin

—

All pins

Corner pins

Positive pulses (HBM)

Negative pulses (HBM)

—

2000

1500

100

500

750

1 — SR Number of pulses

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.

Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.”

 pF

—

74/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

(POR) electrical specifications

Table 14. PMC Operating conditions and external regulators supply voltage

Name C Parameter Min Typ Max ID

Jtemp SR — Junction temperature

Vddreg SR — PMC 5 V supply voltage VDDREG

Vdd SR —

Core supply voltage 1.2 V VDD when external regulator is used without disabling the internal regulator (PMC unit turned on, LVI monitor active)

(2)

—

Ivdd

SR —

Core supply voltage 1.2 V VDD when external regulator is used with a disabled internal regulator (PMC unit turned-off, LVI monitor disabled)

SR —

Voltage regulator core supply maximum DC output current

(4)

Vdd33 SR —

Regulated 3.3 V supply voltage when external regulator is used without disabling the internal regulator (PMC unit turned-on, internal 3.3V regulator enabled, LVI monitor active)

(5)

— SR —

Regulated 3.3 V supply voltage when external regulator is used with a disabled internal regulator (PMC unit turned-off, LVI monitor disabled)

–40

4.75

1.26

400

3.3

(1)

(3)

1.14

1.3

1.2

—

3.45

3.3

6 — SR —

Voltage regulator 3.3 V supply maximum required DC output current

80 —

During start up operation the minimum required voltage to come out of reset state is 4.6 V.

An internal regulator controller can be used to regulate core supply.

The minimum supply required for the part to exit reset and enter in normal run mode is 1.28 V.

The on chip regulator can support a minimum of 400 ma although the worst case core current is 180 ma.

An internal regulator can be used to regulate 3.3 V supply.

150

5.25

1.32

—

3.6

—

Unit

°C

V mA

Vbg

—

Name C

Table 15. PMC electrical characteristics

Parameter

CC C

Nominal bandgap voltage reference

CC P

Untrimmed bandgap reference voltage

CC P

Trimmed bandgap reference voltage (5 V,

27 °C)

CC C

Bandgap reference temperature variation

Min

—

Vbg–7%

Typ Max

Vbg–10mV Vbg Vbg+10mV V

—

1.219

Vbg

100

—

Vbg+6%

—

Unit

V ppm

/°C

Notes

DocID14642 Rev 12 75/128

127

Electrical characteristics SPC563M64x, SPC563M60x

ID Name C

Table 15. PMC electrical characteristics (continued)

Parameter Min Typ Max Unit

—

Vdd

—

Ivrcctl

CC C

Bandgap reference supply voltage variation

CC C

Nominal VDD core supply internal regulator target DC output voltage

(1)

—

CC P

Nominal VDD core supply internal regulator target DC output voltage variation at power-on reset

Vdd – 6%

CC P

Nominal VDD core supply internal regulator target DC output voltage variation after power-on reset

Vdd – 10

(2)

— CC C Trimming step Vdd

CC C

Voltage regulator controller for core supply maximum

DC output current

3000

1.28

Vdd

—

Vdd + 10%

Vdd + 3%

—

— ppm

V mV mA

Lvi1p2 CC C

Nominal LVI for rising core supply

(3),(4)

— CC C

Variation of LVI for rising core supply at power-on reset

(4),(5)

—

1.120

1.160

1.200

—

1.280

CC C

Variation of LVI for rising core supply after power-on reset

(4),(5)

Lvi1p2–3% Lvi1p2 Lvi1p2+3% V

CC C

Trimming step LVI core supply

— 20 — mV

3d Lvi1p2_h CC C

LVI core supply

hysteresis

4 Por1.2V_r CC C POR 1.2 V rising

— 40 — mV

— CC

Por1.2V_f CC

C POR 1.2 V rising variation

C POR 1.2 V falling

— 0.709

— V

Por1.2V_r–

35%

Por1.2V_

Por1.2V_r+

35%

— 0.638

—

— CC C POR 1.2 V falling variation

Por1.2V_f–

35%

Por1.2V_

Por1.2V_f+

35%

Vdd33 CC C

Nominal 3.3 V supply internal regulator DC output voltage

— CC P

Nominal 3.3 V supply internal regulator DC output voltage variation at power-

on reset

—

Vdd33 –

8.5%

3.39

Vdd33

—

Vdd3 + 7%

Notes

76/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

ID Name C

Table 15. PMC electrical characteristics (continued)

Parameter Min Typ Max Unit Notes

—

CC P

Nominal 3.3 V supply internal regulator DC output voltage variation after power-on reset

CC D

Voltage regulator 3.3 V output impedance at maximum DC load

Vdd33 –

7.5%

—

Idd3p3 CC P

Voltage regulator 3.3 V maximum DC output current

Vdd33

ILim

(5)

CC C

Voltage regulator 3.3 V DC current limit

—

Vdd33

—

130

Vdd33 +

—

 mA mA

With internal load up to Idd3p3

6 Lvi3p3 CC C

Nominal LVI for rising 3.3 V supply

— 3.090

— V

The Lvi3p3 specs are also valid for the Vddeh LVI

6a — CC C

Variation of LVI for rising

3.3 V supply at power-on reset

Lvi3p3–6% Lvi3p3 Lvi3p3+6% V See note

(6)

—

Variation of LVI for rising

3.3 V supply after power-on reset

Lvi3p3–3% Lvi3p3 Lvi3p3+3% V See note

(6)

C Trimming step LVI 3.3 V

6d Lvi3p3_h CC

C LVI 3.3 V hysteresis

—

— mV mV

7 Por3.3V_r CC C

Nominal POR for rising

3.3 V supply

— 2.07

— V

The 3.3V POR specs are also valid for the Vddeh

POR

7a — CC C

Variation of POR for rising

3.3 V supply

Por3.3V_r–

35%

Por3.3V_

Por3.3V_r+

35%

7b Por3.3V_f CC C

Nominal POR for falling

3.3 V supply

7c — CC C

Variation of POR for falling

3.3 V supply

Por3.3V_f–

35%

Por3.3V_

Por3.3V_f+

35%

Lvi5p0 CC C

Nominal LVI for rising 5 V

VDDREG supply

— CC C

Variation of LVI for rising

5 V VDDREG supply at power-on reset

—

Variation of LVI for rising

5 V VDDREG supply power-on reset

C Trimming step LVI 5 V

8d Lvi5p0_h CC

C LVI 5 V hysteresis

Table 19 show the required component values for the three different

—

Lvi5p0–6%

Lvi5p0–3%

—

4.290

Lvi5p0

—

Lvi5p0+6%

Lvi5p0+3%

—

V mV mV

9 Por5V_r CC C

Nominal POR for rising 5 V

VDDREG supply

—

1.95

2.67

—

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127

Electrical characteristics SPC563M64x, SPC563M60x

ID Name C

Table 15. PMC electrical characteristics (continued)

Parameter Min Typ Max Unit Notes

9a — CC C

Variation of POR for rising

5 V VDDREG supply

9b Por5V_f CC C

Nominal POR for falling 5 V

VDDREG supply

Por5V_r –

35%

Por5V_r

— 2.47

9c — CC C

Variation of POR for falling

5 V VDDREG supply

Por5V_f –

35%

Por5V_r +

50%

—

Por5V_f

Por5V_f +

50%

Using external ballast transistor.

Min range is extended to 10% since Lvi1p2 is reprogrammed from 1.2 V to 1.16 V after power-on reset.

LVI for falling supply is calculated as LVI rising - LVI hysteresis.

The internal voltage regulator can be disabled by tying the VDDREG pin to ground. When the internal voltage regulator is disabled, the LVI specifications are not applicable because all LVI monitors are disabled. POR specifications remain valid when the internal voltage regulator is disabled as long as VDDEH and VDD33 supplies are within the required ranges.

This parameter is the “inrush” current of the internal 3.3V regulator when it is turned on. This spec. is the current at which the regulator will go into current limit mode.

Lvi3p3 tracks DC target variation of internal Vdd33 regulator. Minimum and maximum Lvi3p3 correspond to minimum and maximum Vdd33 DC target respectively.

Figure 4. Core voltage regulator controller external components preferred configuration

5V from power supply

Keep inductance from 5V supply to the transistor collector and

VDDREG below 1

H if not using R

REG

DDREG

Required only if R

is used

Keep inductance below 20 nH

RCCTL

MCU

78/128

There are three options for the bypassing and compensation networks for the 1.2V regulator controller. The component values in the following table are the same for all PMC network requirements.

DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Component

Table 16. Required external PMC component values

Symbol Minimum Typical Maximum Units Comment

Pass Transistor T1

NJD2873 or

BCP68

VDDREG capacitor C

REG

Pass transistor Collector bypass capacitor

Collector resistor

(1)

1.1

—

13.3

5.6

µF



X7R, -50%/+35%

The collector resistor may not be required. It depends on the allowable power dissipation of the pass transistor (T1).

Table 17 , Table 18 and

options.

Component

Table 17. Network 1 component values

Symbol Minimum Typical Maximum

4 x 2.35

1 x 5

4 x 4.7

1 x 10

4 x 6.35

1 x 13.5

Transistor emitter bypass capacitance

ESR

MCU decoupling capacitor

Base “snubber” capacitor

Base “snubber” resistor R

4 x 50

1.1

6.12

4 x 100

2.2

6.8

4 x 135

2.97

7.48

Emitter resistor R

0 0 0

Units

µF

µF m

 nF

µF



Comment

X7R, -50%/+35%

Equivalent ESR of

capacitors

X7R, -50%/+35%

±10%

Not required

(short)

Component

Table 18. Network 2 component values

Symbol Minimum Typical Maximum

3 x 2.35

1 x 5

3 x 4.7

1 x 10

3 x 6.35

1 x 13.5

Transistor emitter bypass capacitance

ESR

MCU decoupling capacitor

Base “snubber” capacitor

Base “snubber” resistor R

Emitter resistor R

4 x 50

1.1

0.252

4 x 100

2.2

0.280

4 x 135

2.97

0.308

Units

µF

µF m

 nF

Comment

X7R, -50%/+35%

Equivalent ESR of

capacitors

X7R, -50%/+35%

µF



X7R, -50%/+35%

±10%

Not required

(short)

DocID14642 Rev 12 79/128

127

Electrical characteristics SPC563M64x, SPC563M60x

The following component configuration is acceptable when using the BCP68 transistor, however, is not recommended for new designs. Either option 1 or option 2 should be used for new designs. This option should not be used with the NJD2873 transistor.

Component

Table 19. Network 3 component values

Symbol Minimum Typical Maximum

4 x 3.4

4 x 6.8

4 x 9.18

Transistor emitter bypass capacitance

ESR

MCU decoupling capacitor

Base “snubber” capacitor

Base “snubber” resistor R

4 x 110

1.1

13.5

4 x 220

2.2

4 x 297

2.97

16.5

Emitter resistor R

0 0 0

Units

µF m

 nF

µF



Comment

X7R, -50%/+35%

Equivalent ESR of

capacitors

X7R, -50%/+35%

±10%

Not required

(short)

4.6.2 Recommended power transistors

The following NPN transistors are recommended for use with the on-chip voltage regulator controller: ON Semiconductor

BCP68T1 or NJD2873 as well as Philips Semiconductor

BCP68. The collector of the external transistor is preferably connected to the same voltage supply source as the output stage of the regulator.

Symbol h

(

)

Table 20. Recommended operating characteristics

Parameter Value

DC current gain (Beta)

Absolute minimum power dissipation

CMaxDC

VCE

SAT

Minimum peak collector current

Collector-to-emitter saturation voltage

Base-to-emitter voltage

Adjust resistor at bipolar transistor collector for 3.3 V/5.0 V to avoid VCE < VCE

SAT

60 – 550

>1.0

(1.5 preferred)

1.0

200–600

(1)

0.4–1.0

Unit

—

A mV

80/128

There is no power sequencing required among power sources during power up and power down, in order to operate within specification but use of the following sequence is strongly recommended when the internal regulator is bypassed:

5 V

 3.3 V and 1.2 V

This is also the normal sequence when the internal regulator is enabled.

Although there are no power up/down sequencing requirements to prevent issues like latchup, excessive current spikes, etc., the state of the I/O pins during power up/down varies

DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

according to table Table 21 for all pins with fast pads and Table 22

for all pins with medium, slow and multi-voltage pads

(e)

DDE

LOW

DDE

Table 21. Power sequence pin states for fast pads

RC33

Fast (pad_fc)

LOW

RC33

LOW

HIGH

HIGH IMPEDANCE

FUNCTIONAL

Table 22. Power sequence pin states for medium, slow and multi-voltage pads

DDEH

Medium (pad_msr_hv)

Slow (pad_ssr_hv)

Multi-voltage (pad_multv_hv)

LOW

DDEH

LOW

HIGH IMPEDANCE

FUNCTIONAL

4.8

Symbol

DDE

DDEH

RC33

DDA

INDC

– V

SSA

– V

SSA

DC electrical specifications



Table 23. DC electrical specifications

C Parameter

SR — Core supply voltage

SR — I/O supply voltage

SR —

3.3 V external voltage

(2)

SR — Analog supply voltage

SR — Analog input voltage

(4)

SR — V

differential voltage

SR —

Analog reference low voltage

SR — V

differential voltage

Conditions

—

Min

1.14

1.62

3.0

4.75

(3)

SSA

– 0.3

–100

SSA

–100

—

Value

Typ

—

Max

1.32

3.6

(1)

5.25

3.6

5.25

DDA

+0.3

100

SSA

+0.1

100

Unit

V mV

V e.

If an external 3.3 V external regulator is used to supply current to the 1.2 V pass transistor and this supply also supplies current for the other 3.3 V supplies, then the 5 V supply must always be greater than or equal to the external 3.3 V supply.

DocID14642 Rev 12 81/128

127

Electrical characteristics SPC563M64x, SPC563M60x

Symbol

– V

DDF

FLASH

(6)

STBY

DDREG

DDPLL

SSPLL

– V

IL_S

IL_F

IL_LS

IL_HS

IH_S

IH_F

Table 23. DC electrical specifications (continued)

Value

Parameter Conditions

Min Typ

SR —

Analog reference high voltage

SR —

REF

differential voltage

SR —

Flash operating voltage

(5)

—

SR — Flash read voltage —

Unregulated mode

SR — SRAM standby voltage

Regulated mode

SR —

Voltage regulator supply voltage

(7)

SR —

Clock synthesizer operating voltage

—

SR —

SSPLL

to V

SS differential voltage

—

Slow/medium pad I/O input low voltage

Hysteresis enabled hysteresis disabled

Fast pad I/O input low voltage

Hysteresis enabled hysteresis disabled

C Multi-voltage pad I/O

P input low voltage in low-swing

mode

(8),(9),(10),(11)

C Multi-voltage pad I/O input low voltage in high-swing mode

Hysteresis enabled

Hysteresis disabled

Hysteresis enabled

Hysteresis disabled

Slow/medium pad I/O input high voltage

Hysteresis enabled hysteresis disabled

Hysteresis enabled

Fast pad I/O input high voltage hysteresis disabled

DDA

– 0.1

4.75

1.14

4.75

0.95

2.0

4.75

1.14

–100

–0.3

0.65 V

DDEH

0.55 V

DDEH

0.65 V

DDE

0.55 V

DDE

—

Max

DDA

5.25

1.32

5.25

1.2

5.5

5.25

1.32

100

0.35*V

DDEH

0.40*V

DDEH

0.35*V

DDE

0.40*V

DDE

0.8

1.1

0.35 V

DDEH

0.4 V

DDEH

+0.3

DDEH

+0.3

DDE

+0.3

DDE

+0.3

Unit

V mV

82/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Symbol

IH_LS

IH_HS

OL_S

OL_F

OL_LS

OL_HS

OH_S

OH_F

OH_LS

OH_HS

HYS_S

HYS_F

HYS_LS

Table 23. DC electrical specifications (continued)

Value

Parameter Conditions

Min Typ

C Multi-voltage pad I/O

P input high voltage in low-swing mode

(8),(9),(10),(11)

C Multi-voltage pad I/O

P input high voltage in high-swing mode

(12)

Hysteresis enabled

Hysteresis disabled

Hysteresis enabled

Hysteresis disabled

CC P

Slow/medium multivoltage pad I/O output low voltage

(15),(13)

CC P

Fast pad I/O output low voltage

(14),(15)

CC P

Multi-voltage pad I/O output low voltage in low-swing

mode

(8),(9),(10),(11),(14)

CC P

Multi-voltage pad I/O output low voltage in

high-swing mode

CC P

Slow/medium pad I/O output high voltage

(15),(13)

CC P

Fast pad I/O output high voltage

(14),(15)

—

= 2 mA

—

CC P

Multi-voltage pad I/O output high voltage in low-swing

mode

(8),(9),(10),(11),(14)

OH_LS

0.5 mA

Min V

DDEH

4.75 V

CC P

Multi-voltage pad I/O output high voltage in

high-swing mode

CC C

Slow/medium/multivoltage I/O input hysteresis

—

CC C

Fast I/O input hysteresis

—

CC C

Low-Swing-Mode

Multi-Voltage I/O Input

Hysteresis hysteresis enabled

2.5

2.2

0.65 V

0.55 V

—

0.8 V

DDEH

0.8 V

DDEH

DDE

2.1

0.8 V

DDEH

0.1 * V

DDEH

0.1 * V

0.25

DDE

—

Max

DDEH

+0.3

DDEH

+0.3

DDEH

+0.3

DDEH

+0.3

0.2*V

DDEH

0.2*V

DDE

0.6

0.2 V

DDEH

—

3.7

—

Unit

DocID14642 Rev 12 83/128

127

Electrical characteristics SPC563M64x, SPC563M60x

Symbol

DDPLL

(16)

DDSTBY

DDSTBY150

DDSLOW

DDSTOP

DD33

DDA

REF

DDREG

DDH1

DDH6

DDH7

DDH9

DD12

ACT_S

ACT_F

ACT_MV_PU

Table 23. DC electrical specifications (continued)

Value

Parameter Conditions

Min Typ

CC P

Operating current

1.2 V supplies

= 1.32 V,

80 MHz

= 1.32 V,

64 MHz

Operating current 1 V supplies

P Operating current

= 1.32 V,

40 MHz

= 25 o

= 55 o

=150 o

Slow mode

(17)

P V

low-power mode operating current @

1.32 V

Stop mode

(18)

CC T

Operating current

3.3 V supplies @

80 MHz

Operating current

5.0 V supplies @

80 MHz

Operating current

DDE

(20)

supplies @

80 MHz

C Slow/medium I/O

P weak pull up/down

current

(21)

Fast I/O weak pull up/down current

(21)

RC33

DDA

(19)

Analog reference supply current

DDREG

DDEH1

DDEH6

DDEH7

DDEH9

DDE12

3.0 V – 3.6 V

4.75 V – 5.25 V

C Multi-voltage pad

P weak pullup current

1.62 V – 1.98 V

2.25 V – 2.75 V

3.0 V – 3.6 V

DDEH



3.0–3.6 V

 pad_multv_hv,

 all process corners,

 high swing mode only

4.75 V – 5.25 V

—

Max

195

135

200

120

139

158

100

700

1.0

See note

(20)

200

Unit mA

µA

A mA mA mA mA

A

84/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Symbol

ACT_MV_PD

INACT_D

INACT_A

IN_A

IN_M

PUPD200K

PUPDMATCH

PUPD100K

PUPDMATCH

Table 23. DC electrical specifications (continued)

Value

Parameter Conditions

Min Typ

C Multivoltage pad weak pulldown current

DDEH



3.0–3.6 V

particular I/O segment, and the voltage of the I/O segment. See Table 24 for values to calculate power dissipation for

 pad_multv_hv,

 all process corners,

 high swing mode only

P 4.75 V – 5.25 V

—

CC P

I/O input leakage current

(22)

CC T

DC injection current

(per pin)

Analog input current, channel off, AN[0:7],

AN38, AN39

(23)

Analog input current, channel off, all other analog pins (ANx)

(23)

—

DSC(PCR[8:9])

= 0b00

DSC(PCR[8:9])

= 0b01

Load capacitance (fast

I/O)

(24)

DSC(PCR[8:9])

= 0b10

DSC(PCR[8:9])

= 0b11

CC D

Input capacitance

(digital pins)

CC D

Input capacitance

(analog pins)

CC D

Input capacitance

(digital and analog pins

(25)

)

CC P

Weak Pull-Up/Down

Resistance

(26),(27)

200 k

 Option

CC C 200K

 Option

CC P

Weak Pull-Up/Down

Resistance

(26),(27)

100 k

 Option

CC C 100K

 Option

—

–2.5

–1.0

–250

–150

—

130

–2.5

—

Max

280

2.5

140

2.5

200

2.5

1.0

250

150

Unit

A

A mA nA pF k



% k



% pF pF pF

DocID14642 Rev 12 85/128

127

Electrical characteristics SPC563M64x, SPC563M60x

Symbol C

Table 23. DC electrical specifications (continued)

Value

Parameter Conditions

Min Typ

Unit

Max

PUPD5K

CC D

Weak Pull-Up/Down

Resistance

(26)

5 k

 Option

to T

) SR —

Operating temperature range - ambient

(packaged)

5 V ± 5% supply

—

— SR —

Slew rate on power supply pins

—

1.4

–40.0

—

7.5

125.0

50 k



V/ms

DDE

must be lower than V

RC33

, otherwise there is additional leakage on pins supplied by V

DDE

These specifications apply when V

RC33

is supplied externally, after disabling the internal regulator (V

DDREG

= 0).

ADC is functional with 4 V

V

DDA

 4.75 V but with derated accuracy. This means the ADC will continue to function at full speed with no bad behavior, but the accuracy will be degraded.

Internal structures hold the input voltage less than V

DDA

+ 1.0 V on all pads powered by V

DDA

supplies, if the maximum injection current specification is met (3 mA for all pins) and V

DDA

is within the operating voltage specifications.

The V

DDF only.

supply is connected to V

in the package substrate. This specification applies to calibration package devices

FLASH

is only available in the calibration package.

Regulator is functional, with derated performance, with supply voltage down to 4.0 V.

Multi-voltage pads (type pad_multv_hv) must be supplied with a power supply between 4.75 V and 5.25 V.

The slew rate (SRC) setting must be 0b11 when in low-swing mode.

10. While in low-swing mode there are no restrictions in transitioning to high-swing mode.

11. Pin in low-swing mode can accept a 5 V input.

12. Pin in low-swing mode can accept a 5 V input.

13. Characterization based capability:



IOH_S = {6, 11.6} mA and IOL_S = {9.2, 17.7} mA for {slow, medium} I/O with VDDEH=4.5 V;



IOH_S = {2.8, 5.4} mA and IOL_S = {4.2, 8.1} mA for {slow, medium} I/O with VDDEH=3.0 V

14. Characterization based capability:



IOH_F = {12, 20, 30, 40} mA and IOL_F = {24, 40, 50, 65} mA for {00, 01,10, 11} drive mode with VDDE=3.0 V;



IOH_F = {7, 13, 18, 25} mA and IOL_F = {18, 30, 35, 50} mA for {00, 01, 10, 11} drive mode with VDDE=2.25 V;



IOH_F = {3, 7, 10, 15} mA and IOL_F = {12, 20, 27, 35} mA for {00, 01, 10, 11} drive mode with VDDE=1.62 V

15. All VOL/VOH values 100 % tested with ± 2 mA load.

16. Run mode as follows:



System clock = 40/60/80 MHz + FM 2 %



Code executed from Flash memory



ADC0 at 16 MHz with DMA enabled



ADC1 at 8 MHz

 eMIOS pads toggle in PWM mode with a rate between 100 kHz and 500 kHz

 eTPU pads toggle in PWM mode with a rate between 10 kHz and 500 kHz



CAN configured for a bit rate of 500 kHz



DSPI configured in master mode with a bit rate of 2 MHz

 eSCI transmission configured with a bit rate of 100 kHz

17. Bypass mode, system clock at 1 MHz (using system clock divider), PLL shut down, CPU running simple executive code,

4 x ADC conversion every 10 ms, 2 × PWM channels at 1 kHz, all other modules stopped.

18. Bypass mode, system clock at 1 MHz (using system clock divider), CPU stopped, PIT running, all other modules stopped.

19. When using the internal regulator only, a bypass capacitor should be connected to this pin. External circuits should not be powered by the internal regulator. The internal regulator can be used as a reference for an external debugger.

20. Power requirements for each I/O segment are dependent on the frequency of operation and load of the I/O pins on a

specific operation. The total power consumption of an I/O segment is the sum of the individual power consumptions for each pin on the segment.

21. Absolute value of current, measured at V

and V



86/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

22. Weak pull up/down inactive. Measured at V

DDE

= 3.6 V and V

DDEH

= 5.25 V. Applies to pad types: fast (pad_fc).

23. Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each 8 to 12 o

C, in the ambient temperature range of 50 to 125 o

C. Applies to pad types: pad_a and pad_ae.

24. Applies to CLKOUT, external bus pins, and Nexus pins.

25. Applies to the FCK, SDI, SDO, and SDS pins.

26. This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics.

27. When the pull-up and pull-down of the same nominal 200 K

 or 100 K value are both enabled, assuming no interference from external devices, the resulting pad voltage will be 0.5*V

DDE

± 2.5%

4.9

Note:

I/O Pad current specifications

SPC563Mxx devices use two sets of I/O pads (5 V and 3.3 V). See Table 4

and Table 5 in

Section 3.3: Signal summary , for the pad type associated with each signal.

The power consumption of an I/O segment depends on the usage of the pins on a particular segment. The power consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from

Table 24 based on the voltage,

frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 24 .

Pad Type

Slow

Medium

Fast

Symbol

Table 24. I/O pad average I

DDE

specifications

(1)

Period

(ns)

Load

(2)

(pF)

DDE

(V)

Drive/Slew

Rate Select

DRV_SSR_HV

DRV_MSR_HV

DRV_FC

5.25

3.6

5.25

3.6

1.98

200

317

425

130

650

840

CC D

DDE

Avg

(mA)

(3)

5.3

1.1

22.7

12.1

2.5

0.5

1.5

8.3

4.44

12.5

7.3

5.42

2.84

DDE

RMS

(mA)

—

68.3

41.1

—

27.7

14.3

18.6

12.6

6.4

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127

Electrical characteristics SPC563M64x, SPC563M60x

Pad Type

MultiV

(High

Swing

Mode)

Table 24. I/O pad average I

DDE

specifications

(1)

(continued)

Symbol C

Period

(ns)

Load

(2)

(pF)

DDE

(V)

Drive/Slew

Rate Select

DDE

Avg

(mA)

(3)

DRV_MULTV_HV

CC D

300

200

5.25

21.2

(4)

—

(5)

20.2

(6)

DRV_MULTV_HV

CC D 30 30 5.25

11 NA

MultiV

(Low

Swing

Mode)

Numbers from simulations at best case process, 150 °C.

All loads are lumped.

Average current is for pad configured as output only.

Ratio from 5.5 V pad spec to 5.25 V data sheet.

Not specified.

Low swing mode is not a strong function of V

DDE

DDE

RMS

(mA)

—

4.9.1 I/O current specifications

The power consumption of the VRC33 supply is dependent on the usage of the pins on all

I/O segments. The power consumption is the sum of all output pin V

RC33

currents for all I/O segments. The output pin V

RC33

current can be calculated from

Table 25 based on the

voltage, frequency, and load on all medium, slow, and multv_hv pins. The output pin VRC33 current can be calculated from

Table 26 based on the voltage, frequency, and load on all

fast pins. Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 25

and Table 26

Pad Type

Slow

Medium

Table 25. I/O pad V

RC33

average I

DDE

specifications

(1)

Symbol C

Period

(ns)

Load

(2)

(pF)

Slew Rate

Select

DD33

Avg

(µA)

DRV_SSR_HV

DRV_MSR_HV

CC D

100

200

800

100

500

200

0.8

0.04

0.06

0.009

2.75

0.11

0.02

0.01

DD33

RMS

(µA)

235.7

87.4

47.4

258

76.5

56.2

88/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Pad Type

Table 25. I/O pad V

RC33

average I

DDE

specifications

(1)

(continued)

Symbol C

Period

(ns)

Load

(2)

(pF)

Slew Rate

Select

DD33

Avg

(µA)

MultiV

(3)

(High

Swing Mode)

MultiV

(4)

(Low

Swing Mode)

DRV_MULTV_HV

CC D

100

500

100

500

200

2.75

0.11

0.02

0.01

2.75

0.11

0.02

0.01

These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.

All loads are lumped.

Average current is for pad configured as output only.

In low swing mode, multi-voltage pads (pad_multv_hv) must operate in highest slew rate setting.

DD33

RMS

(µA)

258

76.5

56.2

258

76.5

56.2

Pad

Type

Symbol

Table 26. V

RC33

pad average DC current

(1)

Period

(ns)

Load

(2)

(pF)

RC33

(V)

DDE

(V)

Drive

Select

DD33

Avg

(µA)

DD33

RMS

(µA)

Fast I

DRV_FC

CC D

3.6

1.98

2.35

1.75

1.41

1.06

1.75

1.32

1.14

0.95

These are typical values that are estimated from simulation and not tested. Currents apply to output pins only.

All loads are lumped.

6.12

4.3

3.43

2.9

4.56

3.44

2.95

2.62

4.9.2 LVDS pad specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol which is an enhanced feature of the DSPI module. The LVDS pads are compliant with LVDS specifications and support data rates up to 50 MHz.

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127

Electrical characteristics SPC563M64x, SPC563M60x

# Characteristic

Table 27. DSPI LVDS pad specification

(1)

Symbol C Condition

Min.

Value

4 Data Frequency F

LVDSCLK

Data Rate

CC D

Driver Specs

5 Differential output voltage V

SRC=0b00 or

0b11

150

P SRC=0b01

P SRC=0b10

155

Common mode voltage

(LVDS), V

7 Rise/Fall time

Propagation delay (Low to

High)

PLH

Propagation delay (High to

Low)

PHL

10 Delay (H/L), sync Mode t

PDSYNC

11 Delay, Z to Normal (High/Low) T

Diff Skew Itphla-tplhbI or

Itplhb-tphlaI

SKEW

Termination

13 Trans. Line (differential Zo)

14 Temperature

These are typical values that are estimated from simulation.

0.8

–40

Typ.

Value

1.2

500

100

Max.

Value

430

340

480

1.6

0.5

105

150

Unit

MHz mV

C ns ns ns ns

V ns ns

Table 28. PLLMRFM electrical specifications (V

DDPLL

=1.14 V to 1.32 V, V

= V

SSPLL

= 0 V, T

= T to T

)

Value

Symbol C Parameter Conditions Unit

Min Max f ref_crystal f ref_ext f pll_in f vco f sys

PLL reference frequency range

(1)

CC P

Phase detector input frequency range

(after pre-divider)

CC P VCO frequency range

(2)

CC C On-chip PLL frequency

(1)

Crystal reference

External reference

—

256

512

MHz

90/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Table 28. PLLMRFM electrical specifications (V

DDPLL

=1.14 V to 1.32 V, V

= V

SSPLL

= 0 V, T

= T to T

) (continued)

Value

Symbol C Parameter Conditions Unit

Min Max f sys

System frequency in bypass mode

(3)

Crystal reference

External reference t

CYC

CC D System clock period — f f

LORL

LORH

Loss of reference frequency window

(4)

Lower limit

CC P Self-clocked mode frequency

(5),(6)

Upper limit

— f

SCM

JITTER

CLKOUT period jitter

(7),(8),(9),

(10)

Peak-to-peak (clock edge to clock edge)

Long-term jitter (avg. over 2 ms interval) f

SYS

maximum t cst

CC T Crystal

IHEXT

ILEXT

EXTAL input high voltage

EXTAL input low voltage

—

Crystal Mode

(13)

0.8

Vxtal 1.5V



External

Reference

(13),(14)

Crystal Mode

(13)



0.65

Vxtal1.25V

External

Reference

(13),(14)

4 MHz

—

1.6

1.2

–5

–6

—

Vxtal +

0.4

RC33

+ 0.4

—

1 / f

— sys

3.7

RC33

Vxtal –

0.4

RC33

– 0.4

MHz ns

MHz

% f

CLK

OUT ns ms

8 MHz 5 26

— CC T

XTAL load capacitance

(11)

12 MHz

16 MHz

19 pF

20 MHz 5 16 t lpll t dc f

LCK f

CC T Duty cycle of reference

PLL lock time

(11),(15)

Frequency LOCK range

Frequency un-LOCK range

—

–6

–18

200

s

% f sys

% f sys f f

CC Modulation Depth

CC D Modulation frequency

(16)

Center spread

Down Spread

±0.25

–0.5

±4.0

–8.0

%f sys f

MOD

— — 100 kHz

Considering operation with PLL not bypassed.

VCO

is calculated as follows:

— In Legacy Mode f

VCO

= (f crystal

/ (PREDIV + 1)) * (4 * (MFD + 4))

— In Enhanced Mode fvco = (f crystal

/ (EPREDIV + 1)) * (EMFD + 4)

All internal registers retain data at 0 Hz.

“Loss of Reference Frequency” window is the reference frequency range outside of which the PLL is in self clocked mode.

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127

Electrical characteristics SPC563M64x, SPC563M60x

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls outside the f

LOR window.

VCO

self clock range is 20–150 MHz. f mode.

SCM

represents f

SYS

after PLL output divider (ERFD) of 2 through 16 in enhanced

This value is determined by the crystal manufacturer and board design.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

SYS

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the PLL circuitry via V

DDPLL percentage for a given interval.

and V

SSPLL

and variation in crystal oscillator frequency increase the C

JITTER

Proper PC board layout procedures must be followed to achieve specifications.

10. Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

JITTER f

or f

(depending on whether center spread or down spread modulation is enabled).

and either

11. This value is determined by the crystal manufacturer and board design. For 4 MHz to 20 MHz crystals specified for this

PLL, load capacitors should not exceed these limits. For a 20 MHz crystal the maximum load should be 17 pF.

12. Proper PC board layout procedures must be followed to achieve specifications.

13. This parameter is guaranteed by design rather than 100% tested.

14. V

IHEXT

cannot exceed V

RC33

in external reference mode.

15. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the synthesizer control register (SYNCR).

16. Modulation depth will be attenuated from depth setting when operating at modulation frequencies above 50 kHz.

Symbol

—

Table 29. Temperature sensor electrical characteristics

Value

Parameter Conditions

Min Typical Max

CC C

Temperature monitoring range

CC C Sensitivity

CC P Accuracy T

= –40 to 150 °C

–40

—

–20

—

6.3

—

150

—

Unit

°C mV/°C

°C

Note: ADC performance is affected by several environmental elements, such as quality of the input signal source, presence of noise sources and quality of the PCB layout.

The DC or Static parameters (DNL, INL, OFFSET, GAIN, and TUE) are measured using methods that provide a very accurate evaluation using averaging.

The AC or Dynamic parameters (SNR, THD, SFDR, SINAD) are determined using a full scale peak-peak sine wave of 1kHz frequency at the input of the ADC.

92/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics f

ADCLK

Symbol C

Table 30. eQADC conversion specifications (operating)

Value

Parameter min max

SR — ADC clock (ADCLK) frequency 2 16

CC 2 + 13 128 + 14

—

OFFNC

OFFWC

GAINNC

GAINWC

INJ

TUE8

TUE16

SNR

THD

SFDR

SINAD

ENOB

GAINVGA1

GAINVGA2

GAINVGA4

CC D Conversion cycles

CC C Stop mode recovery time

(1)

CC D Resolution

(2)

CC C Offset error without calibration

CC C Offset error with calibration

CC C Full scale gain error without calibration

CC C Full scale gain error with calibration

CC T Disruptive input injection current

(3), (4), (5), (6)

CC T

Incremental error due to injection current

(6),(7),(8)

CC C Total unadjusted error (TUE) at 8 MHz

(9)

CC C Total unadjusted error at 16 MHz

(10)

CC T Signal to Noise Ratio

(11)

CC T Total Harmonic Distorsion

CC T Spurious Free Dynamic Range

CC T Signal to Noise and Distorsion

CC T Effective Number of Bits

CC – Variable gain amplifier accuracy (gain=1)

(12)

CC C 8 MHz ADC

INL

CC C 16 MHz ADC

CC C 8 MHz ADC

DNL

CC C 16 MHz ADC

CC –

Variable gain amplifier accuracy (gain=2)

(12)

CC D

INL

8 MHz ADC

16 MHz ADC

CC D 8 MHz ADC

DNL

CC D 16 MHz ADC

CC –

Variable gain amplifier accuracy (gain=4)

(12)

CC D

INL

DNL

8 MHz ADC

16 MHz ADC

8 MHz ADC

16 MHz ADC

–4

–8

55.2

70.0

65.0

55.0

8.8

—

1.25

–4

–160

–4

–3

–4

–7

–8

–4

–5

–8

–3

–4

–8

–3

(14)

–3

—

160

Unit

Counts

(13)

Counts

Counts dB dB dB dB

Counts

MHz

ADCLK cycles

s mV

Counts

Counts mA

Counts

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127

Electrical characteristics SPC563M64x, SPC563M60x

Symbol

Table 30. eQADC conversion specifications (operating) (continued)

Value

C Parameter min max

Unit

DIFF

DIFF max max2 max4

CC C

Maximum differential voltage

(DANx+ - DANx-) or (DANx- -

DANx+)

PREGAIN set to 1X setting

PREGAIN set to 2X setting

PREGAIN set to 4X setting

–

(VRH -

VRL)/2

(VRH -

VRL)/4

(VRH -

VRL)/8

(VRH -

VRL)/2 +

DIFF cmv

CC C

Differential input Common mode voltage (DANx- + DANx+)/2

(15)

(VRH -

VRL)/2 -

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that the ADC is ready to perform conversions.Delay from power up to full accuracy = 8 ms.

At V

– V

= 5.12 V, one count = 1.25 mV. Without using pregain.

Below disruptive current conditions, the channel being stressed has conversion values of 0x3FF for analog inputs greater then V

and 0x0 for values less then V

. Other channels are not affected by non-disruptive conditions.

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values using V

POSCLAMP

= V

DDA

+ 0.5 V and V

NEGCLAMP

= – 0.3 V, then use the larger of the calculated values.

Condition applies to two adjacent pins at injection limits.

Performance expected with production silicon.

All channels have same 10 k

 < Rs < 100 k; Channel under test has Rs=10 k; I

INJ

INJMAX

INJMIN.

TUE is tested by averaging 10 samples.

10. TUE is tested by averaging three samples.

11. These values can be significantly improved by using three samples of averaging. Input frequency of 1 kHz was used as the reference for the Signal to Noise Ratio.

12. Variable gain is controlled by setting the PRE_GAIN bits in the ADC_ACR1-8 registers to select a gain factor of

1, 2, or

4. Settings are for differential input only. Tested at 1 gain. Values for other settings are guaranteed by as indicated.

13. At V

– V

= 5.12 V, one LSB = 1.25 mV.

14. Guaranteed 10-bit monotonicity.

15. Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode voltage of the differential signal violates the Differential Input common mode voltage specification.

4.13 Platform Flash controller electrical characteristics

Table 31. APC, RWSC, WWSC settings vs. frequency of operation

(1)

Target Max Frequency

(2)

(MHz)

APC

(3)

RWSC

(3)

WWSC

000

001

64 010

80 011

All 111

Illegal combinations exist, all entries must be taken from the same row.

000

001

010

011

111

94/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Maximum Frequency includes FM modulation.

APC must be equal to RWSC.

4.14 Flash memory electrical characteristics

Table 32. Program and erase specifications

Symbol Parameter

Min

Value

Typical

Value

(1)

Initial

Max

(2)

Max

(3)

Unit

T dwprogram

P Double Word (64 bits) Program Time

(4)

16kpperase

P 16 KB Block Pre-program and Erase Time

32kpperase

P 32 KB Block Pre-program and Erase Time

64kpperase

P 64 KB Block Pre-program and Erase Time

128kpperase

P 128 KB Block Pre-program and Erase Time

—

300

400

600

800

500

600

900

1300

500

5000

7500 ms ms ms ms

Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change pending device characterization.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program & erase times occur after the specified number of program/erase cycles. These maximum values are characterized but not guaranteed.

Actual hardware programming times. This does not include software overhead.

s

Table 33. Flash module life

Value

Symbol Parameter Conditions Unit

Min Typ

P/E

Number of program/erase cycles per block for 16 Kbyte blocks over the operating temperature range (T

)

Number of program/erase cycles per block for 32 and 64 Kbyte blocks over operating temperature range (T

)

Number of program/erase cycles per block for 128 Kbyte blocks over the operating temperature range (T

)

—

Retention C

Minimum data retention at 85 °C average ambient temperature

(1)

Blocks with 0 – 1,000

P/E cycles

Blocks with 10,000 P/E cycles

Blocks with 100,000 P/E cycles

100,000

10,000

1,000

—

— cycles cycles cycles years years years

Ambient temperature averaged over duration of application, not to exceed recommended product operating temperature range.

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127

Electrical characteristics SPC563M64x, SPC563M60x

Name

Table 34. Pad AC specifications (5.0 V)

(1)

Output Delay

(ns)

(2),(3)

Low-to-High/Highto-Low

Rise/Fall Edge

(3)

(4)

Drive Load

(pF)

SRC/DSC

Min Max Min Max MSB,LSB

Medium

Slow

(5),(6),(7)

(7),(10)

MultiV

(11)

(High Swing Mode)

4.6/3.7

13/10

CC D

12/13

23/23

CC D

69/71

95/90

CC D 7.3/5.7

CC D 24/19

12/12

32/32

28/34

52/59

152/165

205/220

19/18

58/58

2.2/2.2

9/9

N/A

5.6/6

11/14

34/35

44/51

4.4/4.3

CC D 26/27 61/69

CC D 49/45 115/115

CC D 137/142 320/330

CC D 182/172 420/420

17/15

N/A

13/13

27/23

72/74

90/85

CC D 4.1/3.6

10.3/8.9

3.28/2.98

CC D 10.4/10.2

24.2/23.6

12.7/11.54

N/A

CC D 8.38/6.11

16/12.9

CC D 15.9/13.6

31/28.5

5.48/4.81

14.6/13.1

CC D 61.7/10.4

92.2/24.3

42.0/12.2

CC D 85.5/37.3

132.6/

78.9

57.7/46.4

7/7

22/22

15/15

31/31

74/74

96/96

14/14

42/42

34/34

61/61

164/164

200/200

8/8

29/29

11/11

31/31

63/63

85/85

200

(8)

(9)

MultiV

(Low Swing Mode)

Fast

(12) pad_i_hv

(13) pull_hv

CC D 2.31/2.34

CC D 0.5/0.5

CC D NA

7.62/6.33

1.9/1.9

6000

1.26/1.67

0.3/0.3

—

N/A

7/7 30

1.5/1.5

5000/5000

0.5

Output delay is shown in Figure 5

N/A

These are worst case values that are estimated from simulation and not tested. Values in the table are simulated at f

SYS

80 MHz, V

= 1.14 V to 1.32 V, V

DDE

= 1.62 V to 1.98 V, V

DDEH

= 4.5 V to 5.25 V, T

= T

to T

This parameter is supplied for reference and is not guaranteed by design and not tested.

96/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad V

and V

values are the same as those of the slew controlled output pads

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.

. Add a maximum of one system clock to the output delay for delay with respect to system clock.

Can be used on the tester.

This drive select value is not supported. If selected, it will be approximately equal to 11.

10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.

11. Selectable high/low swing IO pad with selectable slew in high swing mode only.

12. Fast pads are 3.3 V pads.

13. Stand alone input buffer. Also has weak pull-up/pull-down.

Pad Type

Medium

(5),(6),(7)

Slow

(7),(10)

MultiV

(7),(11)

(High Swing Mode)

Table 35. Pad AC specifications (3.3 V)

(1)

Output Delay

(ns)

(2),(3)

Low-to-High/Highto-Low

Rise/Fall Edge (ns)

(3),(4)

Drive Load

(pF)

SRC/DSC

Min

CC D 5.8/4.4

CC D 16/13

Max

18/17

46/49

CC D

14/16

27/27

83/86

37/45

69/82

200/210

CC D 113/109 270/285

CC D 9.2/6.9

27/28

CC D 30/23 81/87

CC D

31/31

58/52

80/90

144/155

CC D 162/168 415/415

CC D 216/205 533/540

CC D

3.7/3.1

46/49

Min

2.7/2.1

11.2/8.6

N/A

6.5/6.7

15/13

38/38

53/46

5.5/4.1

21/16

N/A

15.4/15.4

32/26

80/82

106/95

Max

10/10

34/34

19/19

43/43

86/86

120/120

20/20

63/63

42/42

82/85

190/190

250/250

10/10

37/37

200

MSB,LSB

(8)

(9)

N/A 10

Output delay is shown in Figure 5

CC D

210

295

15/15

46/46

100/100

134/134

200

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127

Electrical characteristics SPC563M64x, SPC563M60x

Pad Type

Table 35. Pad AC specifications (3.3 V)

(1)

(continued)

Output Delay

(ns)

(2),(3)

Low-to-High/Highto-Low

Rise/Fall Edge (ns)

(3),(4)

Drive Load

(pF)

SRC/DSC

Min Max Min Max MSB,LSB

Fast

CC D

CC D 0.5/0.5

CC D NA

2.5/2.5

3/3

6000

1.2/1.2

1.5/1.5

5000/5000

0.5

50 pad_i_hv

(12) pull_hv

0.4/0.4

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at f

SYS

= 80 MHz, V

= 1.14 V to 1.32 V, V

DDE

= 3 V to 3.6 V, V

DDEH

= 3 V to 3.6 V, T

= T

to T

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

In high swing mode, high/low swing pad Vol and Voh values are the same as those of the slew controlled output pads.

Medium Slew-Rate Controlled Output buffer. Contains an input buffer and weak pullup/pulldown.

. Add a maximum of one system clock to the output delay for delay with respect to system clock.

Can be used on the tester.

This drive select value is not supported. If selected, it will be approximately equal to 11.

10. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.

11. Slow Slew-Rate Controlled Output buffer. Contains an input buffer and weak pull-up/pull-down.

12. Stand alone input buffer. Also has weak pull-up/pull-down.

scan only. See Table 38 for functional specifications.

N/A

Pad Type

Table 36. Pad AC specifications (1.8 V)

Output Delay

(ns)

(1),(2)

Low-to-High / Highto-Low

Rise/Fall Edge (ns)

(3)

Min Max Min Max

Fast

CC D

3.0/3.0

2.0/1.5

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Can be used on the tester.

Drive Load

(pF)

SRC/DSC

MSB,LSB

(4)

98/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x

Figure 5. Pad output delay

Electrical characteristics

Pad

Data Input

Pad

Output

Rising

Edge

Output

Delay

Falling

Edge

Output

Delay

DDE

4.16.1 IEEE 1149.1 interface timing

13 t

JCYC t

JDC t

TCKRISE t

TMSS, t

TDIS t

TMSH, t

TDIH t

TDOV t

TDOI t

TDOHZ t

JCMPPW t

JCMPS t

BSDV

Symbol t

BSDVZ t

BSDHZ

Table 37. JTAG pin AC electrical characteristics

(1)

C Characteristic

Min.

Value

CC D TCK Cycle Time

CC D TCK Clock Pulse Width

CC D TCK Rise and Fall Times (40% – 70%)

CC D TMS, TDI Data Setup Time

CC D TMS, TDI Data Hold Time

CC D TCK Low to TDO Data Valid

CC D TCK Low to TDO Data Invalid

CC D TCK Low to TDO High Impedance

CC D JCOMP Assertion Time

CC D JCOMP Setup Time to TCK Low

CC D TCK Falling Edge to Output Valid

CC D

TCK Falling Edge to Output Valid out of High

Impedance

CC D TCK Falling Edge to Output High Impedance

100

—

100

—

Unit ns ns ns ns ns ns ns ns ns ns ns ns ns

Max.

Value

—

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Electrical characteristics SPC563M64x, SPC563M60x

Table 37. JTAG pin AC electrical characteristics

(1)

(continued)

Symbol C Characteristic

Min.

Value

Max.

Value

Unit

15 t t

BSDST

BSDHT

CC D

Boundary Scan Input Valid to TCK Rising

Edge

TCK Rising Edge to Boundary Scan Input

Invalid

—

— ns ns

JTAG timing specified at V

Swing mode, T

= T

to T

= 1.14 V to 1.32 V, V

and C

DDEH

= 4.5 V to 5.25 V with multi-voltage pads programmed to Low-

= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary

Figure 6. JTAG test clock input timing

TCK

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SPC563M64x, SPC563M60x Electrical characteristics

Figure 7. JTAG test access port timing

TCK

TMS, TDI

7 8

TDO

Figure 8. JTAG JCOMP timing

TCK

JCOMP

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Electrical characteristics SPC563M64x, SPC563M60x

Figure 9. JTAG boundary scan timing

TCK

11 13

Output

Signals

Output

Signals

Input

Signals

7 t

MCYC t

MDC t

MDOV t

MSEOV t

EVTOV t

EVTIPW

8 t

EVTOPW

9 t

TCYC

Symbol C

Table 38. Nexus debug port timing

(1)

Characteristic

CC D MCKO Cycle Time

CC D Absolute Minimum MCKO Cycle Time

CC D MCKO Duty Cycle

CC D MCKO Low to MDO Data Valid

(5)

CC D MCKO Low to MSEO Data Valid

CC D MCKO Low to EVTO Data Valid

CC D EVTI Pulse Width

CC D EVTO Pulse Width

CC D TCK Cycle Time

Min. Value Max. Value

(2),(3)

100

(4)

– 0.1

—

0.2

0.1

– 0.1

0.2

— 4.0

(6),(7)

—

Unit t

CYC ns

% t

MCYC t

TCYC t

MCYC t

CYC

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SPC563M64x, SPC563M60x Electrical characteristics

Table 38. Nexus debug port timing

(1)

(continued)

# Symbol C Characteristic Min. Value Max. Value Unit

15 t

TCYC t

TDC t

NTDIS t

NTDIH t

NTMSS t

NTMSH t

JOV

Absolute Minimum TCK Cycle Time

TCK Duty Cycle

TDI Data Setup Time

TDI Data Hold Time

TMS Data Setup Time

TMS Data Hold Time

TCK Low to TDO Data Valid

100

(8)

—

20 ns

% ns ns ns ns ns

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified at V

= 1.14 V to 1.32 V, V

DDEH

= 4.5 V to 5.25 V with multi-voltage pads programmed to Low-Swing mode, T

= TL to TH, and CL = 30 pF with DSC = 0b10.

Achieving the absolute minimum MCKO cycle time may require setting the MCKO divider to more than its minimum setting

(NPC_PCR[MCKO_DIV] depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum MCKO period specification.

This may require setting the MCKO divider to more than its minimum setting (NPC_PCR[MCKO_DIV]) depending on the actual system frequency being used.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

This is a functionally allowable feature. However, this may be limited by the maximum frequency specified by the Absolute minimum TCK period specification.

This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the design (system frequency / 4) depending on the actual system frequency being used.

Figure 10. Nexus output timing

MCKO

MDO

MSEO

EVTO

Output Data Valid

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Electrical characteristics SPC563M64x, SPC563M60x

Figure 11. Nexus event trigger and test clock timings

TCK

EVTI

EVTO

9 7

Figure 12. Nexus TDI, TMS, TDO timing

TCK

TMS, TDI

TDO

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4.16.3 Calibration bus interface timing

# Symbol C

Table 39. Calibration bus operation timing

(1)

66 MHz (ext. bus)

(2)

Characteristic

Min Max

Unit

1 T

CC P CLKOUT Period

2 t

CDC

3 t

CRT

4 t

CFT

CC D CLKOUT duty cycle

CC D CLKOUT rise time

CC D CLKOUT fall time

CLKOUT Posedge to Output Signal

Invalid or High Z(Hold Time)

15.2

45%

—

55%

(3)

Notes ns

Signals are measured at 50%

DDE

C ns ns

5 t

COH

CC D

ADDR[8:31]

CS[0:3]

DATA[0:31]

RD_WR

WE[0:3]/BE[0:3]

CLKOUT Posedge to Output Signal

Valid (Output Delay)

1.0

(4)

/1.5

— ns

Hold time selectable via

SIU_ECCR[EBTS] bit:

EBTS=0: 1.0ns

EBTS=1: 1.5ns

6 t

COV

8 t t

CIS

CIH

CC D

ADDR[8:31]

CS[0:3]

DATA[0:31]

RD_WR

WE[0:3]/BE[0:3]

Input Signal Valid to CLKOUT Posedge

(Setup Time)

CC D

DATA[0:31]

CLKOUT Posedge to Input Signal

Invalid

(Hold Time)

—

5.0

1.0

6.0

/7.0

—

— ns ns

Output valid time selectable via

SIU_ECCR[EBTS] bit:

EBTS=0: 5.5ns

EBTS=1: 6.5ns

9 t

APW

10 t

AAI

CC D

DATA[0:31]

CC D ALE Pulse Width

(5)

ALE Negated to Address Invalid

Refer to Fast Pad timing in Table 35

6.5

—

— ns ns

Calibration bus timing specified at f

SYS

= T

to T

, and C

= 80 MHz, V

= 1.14 V to 1.32 V, V

DDE

= 1.62 V to 3.6 V (unless stated otherwise),

= 30 pF with DSC = 0b10.

The external bus is limited to half the speed of the internal bus. The maximum external bus frequency is 66 MHz.

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127

Electrical characteristics SPC563M64x, SPC563M60x

and

Table 36

(different values for 3.3 V vs. 1.8 V).

The EBTS=0 timings are only valid/ tested at V

DDE

=2.25–3.6 V, whereas EBTS=1 timings are valid/tested at 1.6–3.6 V.

Measured at 50% of ALE.

Figure 13. CLKOUT timing

Voh_f

VDDE/2

Vol_f

CLKOUT

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CLKOUT

Electrical characteristics

Figure 14. Synchronous output timing

VDDE/2

OUTPUT

BUS

VDDE/2

OUTPUT

SIGNAL

VDDE/2

OUTPUT

SIGNAL VDDE/2

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Electrical characteristics

CLKOUT

SPC563M64x, SPC563M60x

Figure 15. Synchronous input timing

VDDE/2

INPUT

BUS

VDDE/2

INPUT

SIGNAL VDDE/2

Figure 16. ALE signal timing ipg_clk

CLKOUT

ALE

A/D

ADDR

9 10

DATA

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Table 40. eMIOS timing

(1)

# Symbol C Characteristic

Min.

Value

Max.

Value

Unit

2 t

MIPW t

MOPW

D eMIOS Input Pulse Width eMIOS Output Pulse Width

—

— t t

CYC

eMIOS timing specified at f with SRC = 0b00.

SYS

= 80 MHz, V

= 1.14 V to 1.32 V, V

DDEH

= 4.5 V to 5.25 V, T

= T

to T

, and C

= 50 pF

Symbol t

SCK t

CSC t

ASC t

SDC

Table 41. DSPI timing

(1)(2)

40 MHz

Characteristic

Min Max

64 MHz

Min Max

80 MHz

Min Max

CC D SCK Cycle Time

(3),(4)

CC D PCS to SCK Delay

(5)

CC D After SCK Delay

(6)

48.8 ns 5.8 ms 28.4 ns 3.5 ms 24.4 ns 2.9 ms

46 — 26 — 22 —

CC D SCK Duty Cycle

( ½ t

)

– 2

—

( ½ t

)

+ 2

( ½ t

)

– 2

—

( ½ t

)

+ 2

( ½ t

)

– 2

—

( ½ t

)

+ 2 t

A t

DIS

7 t

PCSC

8 t

PASC

9 t

SUI

CC D

Slave Access Time

(SS active to SOUT driven)

CC D

Slave SOUT Disable

Time

(SS inactive to SOUT

High-Z or invalid)

CC D PCSx to PCSS time

CC D PCSS to PCSx time

D Master (MTFE = 0)

D Slave

Master (MTFE = 1,

CPHA = 0)

(7)

Master (MTFE = 1,

CPHA = 1)

—

–4

—

Data Setup Time for Inputs

—

Unit

— ns ns ns ns ns ns ns ns

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Electrical characteristics SPC563M64x, SPC563M60x

# Symbol C

Table 41. DSPI timing

(1)(2)

(continued)

40 MHz 64 MHz

Characteristic

Min Max Min Max

80 MHz

Unit

Min Max

10 t

D Master (MTFE = 0)

D Slave

Master (MTFE = 1,

CPHA = 0)

(7)

Master (MTFE = 1,

CPHA = 1)

–4

Data Hold Time for Inputs

— –4

—

–4

—

–4

—

— ns

11 t

SUO

D Master (MTFE = 0)

D Slave

Master (MTFE = 1,

CPHA=0)

Master (MTFE = 1,

CPHA=1)

—

Data Valid (after SCK edge)

—

6 ns

12 t

D Master (MTFE = 0)

D Slave

Master (MTFE = 1,

CPHA = 0)

Master (MTFE = 1,

CPHA = 1)

–5

5.5

–5

Data Hold Time for Outputs

—

–5

5.5

–5

—

–5

5.5

–5

—

— ns

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of

S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to TH, and CL = 50 pF with SRC = 0b11.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation

(FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 66 MHz parts allow for a 64 MHz system clock + 2% FM, and

82 MHz parts allow for 80 MHz system clock + 2% FM.

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated based on two SPC563Mxx devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

110/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Figure 17. DSPI classic SPI timing – master, CPHA = 0

These numbers reference

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

First Data

SOUT First Data

Data

Last Data

PCSx

Figure 18. DSPI classic SPI timing – master, CPHA = 1

These numbers reference

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

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Electrical characteristics

SPC563M64x, SPC563M60x

Figure 19. DSPI classic SPI timing – slave, CPHA = 0

3 These numbers reference

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

Figure 20. DSPI classic SPI timing – slave, CPHA = 1

These numbers reference

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

SOUT

SIN

First Data

Data

Last Data

112/128 DocID14642 Rev 12

SPC563M64x, SPC563M60x Electrical characteristics

Figure 21. DSPI modified transfer format timing – master, CPHA = 0

These numbers reference

Table 41

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data Last Data

Data

Last Data

PCSx

Figure 22. DSPI modified transfer format timing – master, CPHA = 1

These numbers reference

Table 41

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

SIN

SOUT

First Data

Data

Last Data

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Electrical characteristics

SPC563M64x, SPC563M60x

Figure 23. DSPI modified transfer format timing – slave, CPHA =0

These numbers reference

SCK Input

(CPOL=0)

SCK Input

(CPOL=1)

11 12

SOUT

SIN

First Data

Data

Last Data

Figure 24. DSPI modified transfer format timing – slave, CPHA =1

These numbers reference