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Arria 10 UHD Video Reference
Design
AN-776
2016-08-01
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Contents
Contents
1.2.1 Arria 10 UHD Video Reference Design Hardware and Software Requirements...... 4
1.2.2 Downloading and Installing the Arria 10 UHD Reference Design ....................... 4
1.2.3 Connecting up the Arria 10 UHD Reference Design Hardware............................ 7
1.2.4 Compiling the Arria 10 UHD Reference Design................................................ 9
1.2.5 Running the Arria 10 UHD Video Reference Design on the Hardware.................. 9
1.2.6 Compiling the Arria 10 UHD Reference Design Software................................. 10
1.3.1 Arria 10 UHD Video Reference Design Parameters......................................... 16
1.3.2 Arria 10 UHD Video Reference Design Clocks................................................ 19
Arria 10 UHD Video Reference Design
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1 Arria 10 UHD Video Reference Design
1 Arria 10 UHD Video Reference Design
The Arria ® 10 ultra-high-definition (UHD) video reference design demonstrates Altera
HDMI 2.0 video connectivity IP core with a video processing pipeline based on IP cores from the Altera Video and Image Processing Suite.
The design delivers high-quality up-, down-, and cross-conversion (UDX) highdefinition and UHD video streams. The design is highly software and hardware configurable, enabling rapid system configuration and redesign. The reference design targets Arria 10 devices and uses the latest 4K ready IP cores from the Video and
Image Processing Suite in the Altera Complete Design Suite v16.0.
Related Links
Altera High-Definition Multimedia Interface (HDMI) IP Core User Guide
1.1 Arria 10 UHD Video Reference Design Features
• Files for targeting Arria 10 GX FPGA Development Kit
• Input: HDMI 2.0 connectivity supporting 1080p or 2160p resolution at any frame rate up to and including 60 fps.
• Output: HDMI 2.0 connectivity selectable for either 1080p or 2160p resolution at
60 fps.
• Input and output hot-plugging support.
• Single 10-bit RGB processing pipeline with software configurable up and down scaling.
— 12x12 tap down-scaler
— 16x16 phase, 4x4 tap up-scaler
• Triple buffer video frame buffer to provide frame rate conversion from a variable input frame rate to the fixed output rate of 60 fps.
• Mixer with alpha-blending allowing OSD icon overlay.
This reference design does not support audio.
Related Links
• Avalon Interface Specifications
Information about Avalon-MM and Avalon-ST interfaces
• Video and Image Processing Suite User Guide
Information about Avalon-ST video interface
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2008
Registered
1 Arria 10 UHD Video Reference Design
1.2 Arria 10 UHD Reference Design Getting Started
Arria 10 UHD Video Reference Design Hardware and Software Requirements on page
4
Downloading and Installing the Arria 10 UHD Reference Design
on page 4
Connecting up the Arria 10 UHD Reference Design Hardware on page 7
Compiling the Arria 10 UHD Reference Design on page 9
Running the Arria 10 UHD Video Reference Design on the Hardware
on page 9
Compiling the Arria 10 UHD Reference Design Software on page 10
1.2.1 Arria 10 UHD Video Reference Design Hardware and Software
Requirements
The reference design requires the following hardware:
• Arria 10 GX FPGA Development Kit
• DDR4 Hilo Daughter Card fitted to an Arria 10 GX FPGA development board.
• Bitec HDMI 2.0 FMC daughter card
• HDMI 2.0 source that produces up to 3840x2160p60 RGB video
• HDMI 2.0 sink that displays up to 3840x2160p60 RGB video
The reference design requires the following software:
• Windows or Linux OS
• The Altera Complete Design Suite v16.0 that includes:
— The Quartus Prime software
— Qsys
— Nios II EDS
— IP Library (including the Video and Image Processing Suite)
Related Links
• Arria 10 GX FPGA Development Kit
• Bitec HDMI FMC Daughter Card
1.2.2 Downloading and Installing the Arria 10 UHD Reference Design
1. Download the project file
udx10.par
from the Altera Design Store.
2. Install the template from the command line: a. Open the Quartus Prime software.
b. Click File > New Project Wizard.
c. Enter a working directory and project name, for example top.
d. Click Next.
e. On the Project page, select Project Template.
f.
Click Next.
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1 Arria 10 UHD Video Reference Design
Figure 1.
g. On the New Project Wizard Design Templates page, click 2. Install the
Design Template.
New Project Wizard
Figure 2.
h. Specify the installation directory.
Design template Installation i.
Click OK.
When the installation completes, the software creates the Quartus Prime
top.qsf
and
top.qpf
files and all other files for the design.
Related Links
Altera Design Store
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1 Arria 10 UHD Video Reference Design
1.2.2.1 Arria 10 UHD Reference Design Installation Files
Table 1.
Files and Directories
File or Directory Name build_ip.tcl
edid_ram.qsys
EDID.hex
edid_ram
PLL_SYS.qsys
qsys_vip_pipeline.qsys
Description
NOT USED. This file shows the flow to build the design from the original Qsys files.
The HDMI sink’s EDID table interface and contents files. The design builds the Qsys system in to the edid_ram
directory.
qsys_vip_pipeline.sopcinfo
top.qpf and top.qsf
udx10.v
clock_control edid_ram gxb hdmi_rx hdmi_tx
PLL_SYS i2c_master
The PLL that generates the system clocks for the top-level design.
The Qsys system containing the video processing pipeline for the reference design along with the Nios II processor and its associated components.
The information file for the qsys_vip_pipline Qsys system and the Nios II software project in Eclipse.
The Quartus Prime project and settings files for the reference design.
The top-level HDL file for this reference design.
Directories containing the generated IP blocks that make up the reference design.
i2c_slave non_acds_ip.ipx
non_acds_ip/debounce.v
non_acds_ip/alt_vip_icon_generate
Directory containing the I2C interface from the HDMI source. You can access this
Avalon-MM slave interface from the Nios II processor.
Directory containing the I2C interface associated with the HDMI Rx core. The I2C slave has interfaces to the EDID RAM and the SCDC interface on the HDMI Rx core.
Non-IP library cores that the reference design uses. Including the debounce block to connect to the pushbuttons.
master_image master_image/udx10.sof
A pre-built .sof image of the reference design. Can be used to test the design without having to compile and build it first.
sdc sdc/mr.sdc
sdc/udx10.sdc
The
.sdc
constraints file for the HDMI’s multi-rate reconfiguration circuitry.
The
.sdc
constraints file for the top-level design. Defines the top-level clocks in the design and sets timing and false paths to and from the top-level connections.
software software/vip_control_src.zip
software/vip_control/mem_init
A
.zip
file containing the software source tree.
Directory containing the pre-built RAM contents for the Nios II processor.
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1.2.3 Connecting up the Arria 10 UHD Reference Design Hardware
Figure 3.
Arria 10 UHD Reference Design Hardware
The photo does not shows the Arria 10 FPGA development board blue heatsink to allow you to see the Hilo daughter card position
1. Fit the DDR4 Hilo card to the Arria 10 GX FPGA development board.
2. Fit the Bitec HDMI 2.0 FMC card to the Arria 10 GX FPGA development board using
FMC Port B.
3. Ensure the power switch (SW1) is turned off, then connect the power connector.
4. Connect a USB-Blaster II download cable to your computer and to the MicroUSB
Connector (J3) on the Arria 10 GX FPGA development board.
5. Attach a HDMI 2.0 cable between the HDMI source and the Rx port of the Bitec
HDMI 2.0 FMC card and ensure the source is active.
6. Attach a HDMI 2.0 cable between the HDMI display and the Tx port of the Bitec
HDMI 2.0 FMC card and ensure the display is active.
7. Turn on board using SW1.
1 Board Status Lights and Pushbuttons
The Arria 10 GX FPGA Development board has eight status lights, each of which contains both red and green LEDs, and three push-buttons that the Arria 10 UHD
Reference Design uses.
Arria 10 UHD Video Reference Design
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Figure 4.
Board Status Lights and Pushbuttons Location
1 Arria 10 UHD Video Reference Design
5
6
3
4
7
0
1
2
Reset
PB
0
PB
1
PB
2
FMC
Card
LCD
Arria10 GX FPGA board
Table 2.
3
4
5
6
1
2
LED
Green LEDs
0
0
1
7
Red LEDs
Status Lights
While the reference design is running on the Arria 10 GX FPGA development board, the board’s status lights display the current status of the system. Each status light position contains a combined red and green LED.
Description
HDMI Rx – IO Pll Locked
HDMI Rx – Rx Ready
HDMI Rx – Locked
HDMI Rx – Oversampling
HDMI Tx – IO Pll Locked
HDMI Tx – Rx Ready
HDMI Tx – Locked
HDMI Tx – Oversampling
DDR4 EMIF Calibration not completed
DDR4 EMIF Calibration fail
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1 Arria 10 UHD Video Reference Design
Table 3.
PB0
PB1
PB2
Push Buttons
While the reference design runs on the Arria 10 GX FPGA development board, use the push-buttons to control the operation of the design. The push-buttons are next to the FMC daughter card and the LCD display.
Pushbutton Description
Change scaling mode
Change output resolution
Toggle the Icon display on/off
The design software operates in any one of three scaling modes that serve to demonstrate the scaling required to transfer from the current input resolution to the current output resolution. The scaling modes are passthrough, upscaling/clip and downscaling. PB0 can be used to cycle through the scaling modes in turn.
The design can generate either 1920x1080p60 or 3840x2160p60 output resolutions.
Use PB1 to toggle between these resolutions.
The design displays an Icon in the top-right corner of the screen by default. Use PB2 to switch this Icon display on and off as required.
1.2.4 Compiling the Arria 10 UHD Reference Design
Altera also provides a precompiled
udx10.sof
file as part of the project file in the
master_image
directory.
Download and install the reference design.
1. In the Quartus Prime software, open the project file
top.qpf
, which the installation generates.
2. Click Processing ➤ Start Compilation.
The compilation creates the
top.sof
file in the
output_files
directory.
Related Links
Downloading and Installing the Arria 10 UHD Reference Design
1.2.5 Running the Arria 10 UHD Video Reference Design on the Hardware
1. Download the
Programmer.
.sof
image, in the Quartus Prime software, click Tools ➤
2. In the Programmer window, click Add File, then: a. To use the precompiled
.sof
included with the design, select the
.sof
in the
master_image
directory.
b. To use your compiled
.sof
, select the
.sof
in the
output_files
directory.
3. Start the Nios II terminal to display status messages during its operation, by typing this command on the command line:
nios2-terminal
When the .sof loads and the terminal program is running, examine the status lights. If you see any red status lights, the DDR4 memory configuration has a failure, so check the seating of the DDR4 card in the Hilo socket.
An image appears on the display.
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1 Arria 10 UHD Video Reference Design
Figure 5.
Example Image
This figure shows an example image with the output resolution set to 1080p and shows the alpha blended logo in the top-right corner of the screen. For this example image the input is a black and white sawtooth test pattern.
1.2.6 Compiling the Arria 10 UHD Reference Design Software
The example code for the design is in the
vip_control_src.zip
file in the
project\software
directory.
Install the reference design
1. Ensure the
qsys_vip_pipeline.sopcinfo
file, which the software build process requires, is in the Quartus project directory.
If you cannot find the file, ensure you installed the reference design.
2. Navigate to the Quartus project directory.
3. Start Nios II software Build Tools for Eclipse: in the Quartus Prime software, click
Tools ➤ Nios II software Build Tools for Eclipse.
4. Select the
software
directory as the workspace folder and click OK to create a new workspace.
5. Click File ➤ New ➤ Nios II Application and BSP from Template.
The Nios II Application and BSP from Template dialog box appears.
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1 Arria 10 UHD Video Reference Design
Figure 6.
Nios II Application and BSP from Template
6. In the SOPC Information File box, select the
qsys_vip_pipeline.sopcinfo
file.
The Nios II SBT for Eclipse fills in the CPU name with the processor name from the
.sopcinfo
file..
7. In the Project name box, type
vip_control
.
8. Select Blank Project from the Templates list and then click Next.
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1 Arria 10 UHD Video Reference Design
9. Select Create a new BSP project based on the application project template with the project name vip_control_bsp and turn on Use default location.
10. Click Finish to create the application and the BSP based on the
.sopcinfo
file.
After the BSP generates, the vip_control and vip_control_bsp projects appear in the Project Explorer tab.
11. In windows Explorer, in the
software
directory, unzip the
vip_software_src.zip
file to generate a
vip_software_src
directory with all of the necessary software files.
12. Copy all these software files and the
vip
directory from the
vip_control_src
directory and in the Eclipse Project Explorer tab on the vip_control folder rightclick and select Paste.
Do not click on vip_control_bsp.
13. In the Project Explorer window, right-click vip_control_bsp and select Nios II
➤
BSP Editor.
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Figure 7.
BSP Editor
14. Turn on enable_small_c_library and enable_reduced_device_drivers, click
Generate then Exit.
15. Select Project > Build All to generate the file
vip_control.elf
in the
software/vip_control
directory.
16. To build the
mem_init
file for the the Quartus Prime compilation, right click on
vip_control in the Project Explorer window and select Make Targets >
Build…, then select mem_init_generate and click on Build.
The quartus Prime software generates the
qsys_vip_pipeline_cpu_ram.hex
file in the
software/vip_control/mem_init
directory.
Related Links
Downloading and Installing the Arria 10 UHD Reference Design
1.3 Arria 10 UHD Video Reference Design Functional Description
A Qsys system,
Nios ®
qsys_vip_pipeline.qsys
, contains the video pipeline IP and the
II processor components. The design associates the remaining components at the top-level with the HDMI Rx and HDMI Tx IP cores and support logic.
The design comprises a single video processing path between the HDMI input and the
HDMI output.
Arria 10 UHD Video Reference Design
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1 Arria 10 UHD Video Reference Design
Figure 8.
Block Diagram
The diagram shows the incoming video from the HDMI source on the left. The design processes the video through the video pipeline from left to right before passing the video out to the HDMI sink on the right.
DDR4
From
FMC
Card
Quartus Prime Project (HDL)
Qsys System
EDID
I 2 C
Nios II
Processor
Processing Pipeline Is 10-bit RGB. Two pixels In parallel at 300 MHz.
HDMI
RX
Clocked
Video Input
Stream
Cleaner
Clipper
Scaler
(Downscale)
DDR and
EMIF
Frame
Buffer
Scaler
(Upscale)
Icon
Mixer
I 2 C
Clocked
Video Output
HDMI
TX
To
FMC
Card
GPIO
Frame Rate
Conversion
GPIO
Reconfiguration
Master
Transceiver
Reconfiguration
Arbitration
HDMI Source to HDMI Rx
The Bitec HDMI FMC card provides a buffer for the HDMI 2.0 signal from the HDMI source then the HDMI Rx IP core processes the signal. The HDMI Rx IP processes the incoming HDMI signal without any software intervention. The resulting video signal from the HDMI Rx IP is in a clocked video interface format.
The reference design configures the HDMI Rx for 8-bit output. Logic between the
HDMI Rx and CVI bit extends each color plane to 10-bit.
Clocked Video Input
The clocked video input processes the clocked video interface signal from the HDMI Rx
IP core and converts it to Altera proprietary Avalon-ST Video signal format. This signal format strips all horizontal and vertical blanking information from the video leaving only active picture data. The Avalon-ST Video stream through the processing pipe is two pixels in parallel with three symbols per pixel. The clocked video input provides clock crossing for the conversion from the variable rate clocked video signal from the
HDMI Rx core to the fixed clock rate for the video IP pipeline.
Stream Cleaner
The stream cleaner ensures that the Avalon-ST Video signal passing to the processing pipeline is error free. Hot-plugging of the HDMI source can cause the design to present incomplete frames of data to the clocked video input core, which can generate errors in the resulting Avalon-ST Video stream.
Clipper
The clipper selects an active area from the incoming video stream and discards the software control defines the region to select.
Scaler (Downscale)
The first scaler in the pipeline downscales. The downscaler precedes the frame buffer in the processing pipeline. When performing a downscale operation (rather than just passthrough), the scaler does not continuously generate pixels. The scaler should not pass downscaled video stream directly to a mixer because the mixer requires the
Arria 10 UHD Video Reference Design
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1 Arria 10 UHD Video Reference Design pixels to be generated continuously at its inputs. The frame buffer provides a buffer for the pixels generated by the downscaler and gives them to the mixer in an acceptable, continuous stream.
Frame Buffer
The frame buffer uses the DDR4 memory to perform triple buffering that allows the video and image processing pipeline to perform frame rate conversion between the incoming and outgoing frame rates. The output frame rate is fixed at 60 fps, but the design can use any input frame rate up to 60 fps.
Scaler (Upscale)
The second scaler in the pipeline upscales. You should insert a frame buffer between the clipper and the upscaler, when performing vertical clip and an upscale operation.
The frame buffer regulates the flow of video data between bursts of clipper output data and the bursts of backpressure from the upscaler input. In this system configuration, the clipper cannot operate with irregular backpressure. The frame buffer provides a buffer of the video stream so that the clipper can generate a stream of continuous pixels. Also the upscaler is providing backpressure to the input stream from the frame buffer.
Mixer
The mixer generates a fixed size black background image that the Nios II processor programs to match the size of the current output image. The mixer has two inputs.
The first input connects to the upscaler to allow the design to show the output from the current video pipeline. The second input connects to the Icon generator block. The design only enables the mixer's first input when it detects active, stable video at the clocked video input. Thus, the design maintains a stable output image at the output while hot-plugging at the input. The design alpha blends the second input to the mixer, connected to the Icon generator, over both the background and video pipeline images with 50% transparency.
Clocked Video Output
The clocked video output converts the Avalon-ST Video stream to the clocked video format. The design passes the clocked video format to the HDMI transmit IP core. The clocked video output adds horizontal and vertical blanking and synchronisation timing information to the video. The Nios II processor programs the relevant settings in the clocked video output depending on the output resolution. The clocked video output converts the clock crossing from the fixed clock to the variable rate of the clock video output.
HDMI Tx
The reference design configures the HDMI Tx for 8-bit output. Logic between the CVO and HDMI Tx removes the two LSBs from each 10-bit color plane output from the
CVO.
Transceiver Reconfiguration Arbitration
The transceiver reconfiguration arbitration controls the sequence of the transmit and receive reconfiguration accesses in a first come first served basis and merges accesses to the same native PHY.
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Reconfiguration Master
The reconfiguration master allows the Nios II processor to reconfigure the HDMI Tx to the required output resolution. The software file
xcvr_gpll_rcfg.c
in the
software/vip_control_src
directory includes software routines to control the reconfiguration process. The main software source file (
main.cpp
) sets the required output resolution using the
set_output_resolution
function. Setting a new output resolution requires you reprogram the CVO with the relevant timing parameters before reconfiguring the HDMI Tx.
System Peripherals
The system contains the following components to provide information about the status of the design and to support run-time user input:
• A JTAG UART (part of the Qsys System) to display software printf output.
• LEDs to display system status.
• Push-button switches to allow switching between video output resolutions and to allow control of the software running on the Nios II Processor.
Related Links
• Altera High-Definition Multimedia Interface (HDMI) IP Core User Guide
• Video and Image Processing Suite User Guide
Information about Avalon-ST video interface
1.3.1 Arria 10 UHD Video Reference Design Parameters
You can change the default parameters of the video pipeline components to change the operation of the design.
Table 4.
Clocked Video Input Parameters
Parameter
Bits per pixel per color plane
Number of color planes
Number of pixels in parallel
Use control port
10
3
2
On
Value
Table 5.
Stream Cleaner Parameters
Parameter
Bits per pixel per color plane
Number of color planes
Number of pixels transmitted in 1 clock cycle
Maximum frame width
Maximum frame height
Enable control slave port
How user packets are handled
Value
10
3
2
3840
2160
On
Discard all user packets received
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1 Arria 10 UHD Video Reference Design
Table 6.
Clipper Parameters
Parameter
Maximum input frame width
Maximum input frame height
Number of pixels transmitted in 1 clock cycle
Run-time control
Add extra pipelining registers
How user packets are handled
Table 7.
Scaler (Down) Parameters
Parameter
Number of pixels in parallel
Bits per symbol
Symbols in parallel
Enable runtime control of output frame size and edge/blur thresholds
Maximum input frame width
Maximum input frame height
Maximum output frame width
Maximum output frame height
Scaling algorithm
Vertical filter taps
Horizontal filter taps
Load scaler coefficients at runtime
Add extra pipelining registers
Reduced control slave register readback
How user packets are handled
Table 8.
Frame Buffer Parameters
Parameter
Maximum frame width
Maximum frame height
Number of color planes
Bits per pixel per color plane
Pixels in parallel
Frame dropping
Frame repeating
Drop invalid frames
Value
3840
2160
2
On
On
No user packets allowed
Value
2
10
3
On
3840
2160
3840
2160
POLYPHASE
12
12
On
On
On
No user packets allowed
2
On
On
On
3840
2160
3
10
Value
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1 Arria 10 UHD Video Reference Design
Table 9.
Scaler (Up) Parameters
Parameter
Number of pixels in parallel
Bits per symbol
Symbols in parallel
Enable runtime control of output frame size and edge/blur thresholds
Maximum input frame width
Maximum input frame height
Maximum output frame width
Maximum output frame height
Scaling algorithm
Vertical filter taps
Horizontal filter taps
Add extra pipelining registers
How user packets are handled
Table 10.
Stream Cleaner Parameters
Parameter
Bits per pixel per color plane
Number of color planes
Number of pixels transmitted in 1 clock cycle
Maximum frame width
Maximum frame height
Enable control slave port
How user packets are handled
Table 11.
Mixer Parameters
Parameter
Number of inputs
Alpha Blending Enable
Register Avalon-ST ready signals
Colorspace (used for background layer)
Pattern
Maximum output frame width
Maximum output frame height
Value
10
3
2
3840
2160
On
Discard all user packets received
2
On
On
RGB
Uniform background
3840
2160
Value
Value
2
10
3
On
3840
2160
3840
2160
POLYPHASE
4
4
On
No user packets allowed continued...
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1 Arria 10 UHD Video Reference Design
Parameter
Bits per pixel per color plane
Number of pixels transmitted in 1 clock cycle
How user packets are handled
Value
10
2
Discard all user packets received
Table 12.
Clocked Video Output Parameters
Parameter
Image width / Active pixels
Image height / Active lines
Bits per pixel per color plane
Number of color planes
Number of pixels in parallel
Pixel fifo size
Fifo level at which to start output
Use control port
3840
2160
10
3
2
2048
2047
On
Value
1.3.2 Arria 10 UHD Video Reference Design Clocks
Table 13.
Name
Clocks clk_fpga_b3_p
VIP_CLK
Source
On board PLL 100
Frequency
(MHz)
PLL.qsys
300
CPU_CLK ddr4_pll_ref_clk On board PLL 133 refclk_sdi_p On board PLL 148.5
hdmi_rx_ls_clk hdmi_tx_ls_clk
PLL.qsy
hdmi_rx_vid_clk HDMI Rx IP
HDMI Rx IP hdmi_tx_vid_clk HDMI Tx IP
HDMI Tx IP
100
<= 297
<= 297
<= 297
<= 297
Usage
Source clock for PLL.qsys
All of the Video IP blocks within the Qsys design qsys_vip_pipeline use this clock.
CPU subsystem within the qsys_vip_pipeline Qsys system and the management clock interfaces within the HDMI reconfiguration logic.
DDR4 EMIF reference clock.
The HDMI Tx reference clock (refclk_sdi_p is the name of the signal on the board for the Arria 10 GX FPGA Development Kit)
The video rate clock generated by the HDMI Rx IP core. Clocks the clocked video interface to the CVI core in the video pipeline.
The link speed clock generated by the HDMI Rx IP core. Clocks the auxiliary data interface out of the core: audio, general control packet, AVI, VSI etc.
The video rate clock generated by the HDMI Tx IP core. Clocks the clocked video interface from the CVO core in the video pipeline into the HDMI Tx IP core.
The link speed clock generated by the HDMI Tx IP core. Clocks the auxiliary data interfaces in to the core: audio, general control packet, AVI, VSI etc.
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1 Arria 10 UHD Video Reference Design Software Operation
The software determines the current input resolution and input status automatically from the clocked video input.
The software running on the Nios II processor:
• Initializes the video IP cores
• Processes the following events:
— HDMI transmit hot-plug
— Output resolution changes because of push-button control
— Stable input video availability
— Scaling mode control via push-button control
Use the push-button switches on the Arria 10 GX FPGA development board to control the scaling operations that the video processing pipeline performs and to set the output video resolution. The mixer provides a stable output image using its software programmable size background image. When the design detects a stable input stream from the clock video input block, the design enables the processing pipeline up to the mixer and the design overlays it for the mixer to show. The design overlays the OSD
Icon over both the background and processed video image. Press push-button PB2 to turn off the OSD Icon. The video processing pipeline converts the input image size and output image size depending on the scaling. You control the scaling using the pushbuttons.
Related Links
Board Status Lights and Pushbuttons on page 7
1.4 Arria 10 UHD Video Reference Design Resource Utilization
ALMs
28,000 59,000
Total Registers
345
RAM Blocks
112
DSP Blocks
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