Arria 10 UHD Video Reference Design

1 Arria 10 UHD Video Reference Design

Parameter

Bits per pixel per color plane

Number of pixels transmitted in 1 clock cycle

How user packets are handled

Value

10

2

Discard all user packets received

Table 12.

Clocked Video Output Parameters

Parameter

Image width / Active pixels

Image height / Active lines

Bits per pixel per color plane

Number of color planes

Number of pixels in parallel

Pixel fifo size

Fifo level at which to start output

Use control port

3840

2160

10

3

2

2048

2047

On

Value

1.3.2 Arria 10 UHD Video Reference Design Clocks

Table 13.

Name

Clocks clk_fpga_b3_p

VIP_CLK

Source

On board PLL 100

Frequency

(MHz)

PLL.qsys

300

CPU_CLK ddr4_pll_ref_clk On board PLL 133 refclk_sdi_p On board PLL 148.5

hdmi_rx_ls_clk hdmi_tx_ls_clk

PLL.qsy

hdmi_rx_vid_clk HDMI Rx IP

HDMI Rx IP hdmi_tx_vid_clk HDMI Tx IP

HDMI Tx IP

100

<= 297

<= 297

<= 297

<= 297

Usage

Source clock for PLL.qsys

All of the Video IP blocks within the Qsys design qsys_vip_pipeline use this clock.

CPU subsystem within the qsys_vip_pipeline Qsys system and the management clock interfaces within the HDMI reconfiguration logic.

DDR4 EMIF reference clock.

The HDMI Tx reference clock (refclk_sdi_p is the name of the signal on the board for the Arria 10 GX FPGA Development Kit)

The video rate clock generated by the HDMI Rx IP core. Clocks the clocked video interface to the CVI core in the video pipeline.

The link speed clock generated by the HDMI Rx IP core. Clocks the auxiliary data interface out of the core: audio, general control packet, AVI, VSI etc.

The video rate clock generated by the HDMI Tx IP core. Clocks the clocked video interface from the CVO core in the video pipeline into the HDMI Tx IP core.

The link speed clock generated by the HDMI Tx IP core. Clocks the auxiliary data interfaces in to the core: audio, general control packet, AVI, VSI etc.

Arria 10 UHD Video Reference Design

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