Microsemi SmartTime software, SmartFusion, IGLOO, ProSAIC3, Fusion SoC User's Guide

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Figure 73 · Set Input Delay Dialog Box

2. In the Show by field, select External Setup/Hold.

3. Click the Browse button in the Input Port field to select the ports for the external setup constraints.

The Select Ports for Input Ports dialog box appears and displays the input ports in the design (as shown below).

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Adding an Input Delay Constraint

Figure 74 · Select Ports for Input Delay Dialog Box

4. Select the ports Enable and Aclr, and then click Add to move the pins from the Available Pins list to the Assigned Pins list. Click OK to close the Select Ports for Input Delay dialog box.

5. Enter the following values in the Set Input Delay Constraint dialog box:

• Clock Port: Select Clock from the Clock Port drop-down list.

• Hold Delay: 1 ns

• Setup Delay: 8 ns

6. Click OK to close the

Set Input Delay Constraint

Continue to add an output delay constraint .

The Input Delay constraints appear in the SmartTime Constraint Editor. Note that the Timing

Constraints Editor View displays both the external setup/hold requirement and the Maximum Delay and Minimum Delay (as shown below).

Figure 75 · SmartTime Constraints Editor with Input Delay Constraint

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Adding an Output Delay Constraint

To add an output delay constraint:

1. Click the Add Output Delay Constraint icon

Constraint

in the SmartTime toolbar. The

Set Output Delay

Figure 76 · Set Output Delay Constraint Dialog Box

2. In the Show by field, select Clock-to-Output.

3. Click the Browse button in the Output Port field to select the ports for the output delay constraint. The

Select Ports for Output Delay dialog box appears and displays the output ports in the design (as shown below).

4. Click Add All to select all the output ports. SmartTime moves the output pins from the Available Pins list to the Assigned Pins list.

5. Click OK to close the Select Ports for Output Delay dialog box.

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Adding an Output Delay Constraint

Figure 77 · Select Ports for Output Delay Dialog Box

6. Select Clock from the Clock Port drop-down list.

7. Enter 10 in the Maximum Delay field and 8 in the Minimum Delay field.

8. Click OK to close the

Set Output Delay Constraint

dialog box. After the dialog box closes, the clk-to-

out delay constraints appear in the SmartTime Constraint Editor (as shown below).

Figure 78 · SmartTime Constraints Editor with Output Delay Constraint

You must commit your changes in SmartTime before you can analyze timing in your design. Click the

Commit icon in the SmartTime toolbar to save your constraints.

You are ready to analyze your design .

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Analyzing the Maximum Operating Frequency

The Maximum Delay Analysis View indicates the maximum operating frequency for a design and displays any setup violations.

To perform the Maximum Delay Analysis:

Click the Timing Analyzer icon in the Designer interface to open the SmartTime Timing Analyzer. The

Maximum Delay Analysis View appears. A green flag next to the name of the clock indicates there are no timing violations for that clock domain (as shown below).

The SmartTime Maximum Delay Analysis View displays the maximum operating frequency for a design and any setup violations.

Figure 79 · SmartTime Maximum Delay Analysis View

The Summary in the Maximum Delay Analysis View displays the maximum operating frequency for the design, the required frequency if any, the external setup and hold requirements, and the maximum and minimum clock-to-out times. In this example, the maximum clock frequency for CLK is 143.988 MHz.

You can now View Register-to-Register paths as part of the Maximum Delay Analysis.

See Also

Analyzing the design (SmartTime)

Viewing Register-to-Register Paths

To view register to register paths:

1. Click the + next to Clock to expand the clock domain in the Domain Browser and display the Register to Register, External Setup, and Clock to output path sets.

2. Click Register to Register to display the register to register paths in the Paths List. It displays a list of register-to-register paths at the top of the Path List and detailed timing analysis for the selected path in the Path Details. Note that all the slack values are positive, indicating that no setup time violations exist (as shown in the figure below).

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Viewing Register-to-Register Paths

Figure 80 · SmartTime Register to Register Paths List

3. Double-click a path row to open the Expanded Path View (see figure below). The top of the view shows a calculation of the required and arrival times. A schematic of the path is shown at the bottom of the view.

Figure 81 · SmartTime Expanded Paths View

Tip: Right-click and drag the mouse to zoom in or out in the schematic window.

Close the Expanded Paths View.

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Viewing External Setup Paths

To view External Setup paths, click External Setup in the Domain Browser to display the external setup timing (as shown below). Note that the slack is positive in the tutorial example, indicating there are no timing violations.

Figure 82 · SmartTime External Setup Path List

Viewing Clock-to-Output Paths

To view Clock-to-output paths, click Clock to Output in the Domain Browser to display the register to output timing. Again, the slack is positive in the tutorial example, indicating there are no timing violations.

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Viewing Clock-to-Output Paths

Figure 83 · SmartTime Clock to Output Paths List

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SmartTime Constraints Editor

Components of the SmartTime Constraints Editor

SmartTime Constraints Editor is a tool in the Designer software that enables you to create, view, and edit timing constraints of the selected scenario for use with SmartTime timing analysis and timing-driven optimization tools. This editor includes powerful visual dialogs that guide you toward capturing your timing requirements and timing exceptions quickly and correctly. In addition, it is closely connected to the

SmartTime Timing Analysis View, which enables you to analyze the impact of constraint changes.

Figure 84 · SmartTime Constraints Editor View

Constraint Hierarchy Browser

The SmartTime Constraints Editor window is divided into a Constraint Browser and a Constraint List. The

Constraint Browser categorizes constraints based on requirements and exceptions, while the Constraint List provides details about each constraint and enables the user to add, edit and delete constraints.

You can perform the following tasks in the SmartTime Constraints View:

• Select a constraint type from the Constraint Browser and create or edit the constraint.

• Add a new constraint and check the syntax.

• Click or double-click a constraint in the Constraint List to edit and check the syntax of the selected constraint.

• Select a row and right-click to display the shortcut menu, which you can use to edit, delete, or copy the selected constraint to a spreadsheet.

• Select the entire spreadsheet and copy it to another spreadsheet.

See Also

Editable Grid and Quick Adder

SmartTime scenarios

Editable Constraints Grid

The Constraints Editor allows you to add, edit and delete constraints directly from the Constraints Editor

View.

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Constraint Wizard

Figure 85 · Constraints Editor View

To add a new constraint:

1. Select a constraint type from the constraint browser.

2. Enter the constraint values in the first row and click the green check mark to apply your changes. To cancel the changes press the red cancel mark.

3. The new constraint is added to the Constraint List. The green syntax flag indicates that the constraint was successfully checked.

To edit a constraint:

1. Select a constraint type from the constraint browser.

2. Select the constraint, edit the values and click the green check mark to apply your changes. To cancel the changes press the red cancel mark. The green syntax flag indicates that the constraint was successfully checked.

To delete a constraint:

1. Select a constraint type from the constraint browser.

2. Select the constraint you want to delete and from the right-click menu, select Delete Constraint.

Constraint Wizard

The SmartTime Constraint Wizard enables you to quickly and easily create clock and timing I/O constraints for your design.

To open the Constraint Wizard (shown below) from the SmartTime Tool menu, choose Constraint Wizard.

This window can be resized.

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Constraint Wizard

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Figure 86 · Constraint Wizard

This window provides information about the Constraint Wizard and how to use it. Check the Don’t show

this introduction again box to skip this window next time you use this wizard.

Press Next to continue to the next step in the wizard.

Note: All steps in this Wizard are optional and you can exit the wizard by clicking the Finish button.

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Overall Clock Constraint

Constraint Wizard

Figure 87 · Constraint Wizard – Overall Clock Requirements

In this window you can set a default required period or frequency for all explicit clocks in your design. Clocks that already have a constraint will not be affected.

To set a constraint for all explicit clocks, enter the Period or the Frequency, and click Next to go to the next step or Finish to exit the wizard.

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Overall I/O Constraint

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Figure 88 · Constraint Wizard – Overall I/O Constraint

In this window you can set a default constraint for all I/Os in the design. Constraints will be applied with respect to clocks related to the I/Os. This constraint will not override existing I/O constraints.

Show I/O constraints enables you to display I/O constraints as I/O delays (minimum and maximum delays for input and output) or external setup/clock-to-out.

To set a constraint for all I/Os:

1. Enter the Maximum and/or Minimum delays for the Input and/or Output.

2. Click Next to go to the next step or Finish to exit the wizard.

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Specific Clock Constraints

Constraint Wizard

Figure 89 · Constraint Wizard – Specific Clock Constraints

In this window you can set a period and I/O timing constraints for a specific clock domain. All I/Os within the domain will be affected by the I/O timing constraints. You can modify the constraints from the grid.

To add a constraint for a potential clock:

1. Click the first row in the grid, enter the constraint information, and click the green check mark.

2. Click Next to go to the next step or Finish to exit the wizard.

Note: This option is available only when there is a potential clock in your design.

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Generated Clock Constraints

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Figure 90 · Constraint Wizard – Generated Clock Constraints

In this window you can set a period and I/O timing constraints for a specific generated clock domain. You can modify the constraints from the grid.

To add a constraint for a generated clock:

1. Click the first row in the grid, enter the constraint information, and click the green check mark.

2. Click Next to go to the next step or Finish to exit the wizard.

Note: This option is available only when there is a generated clock in your design.

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Specific Input Constraints

Constraint Wizard

Figure 91 · Constraint Wizard – Specific Input Constraints

In this window you can set constraints for specific input pins. You can modify the constraints from the grid.

To set a constraint for an input pin:

1. Set the maximum and/or minimum input delay for selected pin in the grid.

2. Click Next to go to the next step or Finish to exit the wizard.

Note: This option is available only when there is an input pin in your design.

Double-click the Port Name or Clock header in the table to change the sorting order by input port name or clock name.

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Specific Output Constraints

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Figure 92 · Constraint Wizard – Specific Output Constraints

In this window you can set constraints for specific output pins. You can modify the constraints from the grid.

To set a constraint for an output pin:

1. Set the maximum and/or minimum output delay for selected pin in the grid.

2. Click Next to go to the next step or Finish to exit the wizard.

Note: This option is available only when there is an output pin in your design.

Double-click the Port Name or Clock header in the table to change the sorting order by output port name or clock name.

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Summary

Using Clock Types

Figure 93 · Constraint Wizard – Summary

This window summarizes the requirements specified in the wizard and information about all clock and I/O constraints in the design.

Click Finish to create the constraints.

See Also

Editable Grid and Quick Adder

Using Clock Types

Clock constraints enable you to specify your clock sources and clock requirements, such as the frequency and duty cycle. SmartTime detects possible clocks by tracing back the design from the clock pins of all sequential components until it finds an input port, the output of another sequential element, or the output of a

PLL. SmartTime classifies clock sources into three types:

•

Explicit clocks

•

Potential clocks

•

Clock network

Grouping clocks into these three types helps you manage clock domains efficiently when you add a new clock domain for analysis or when you create a new clock constraint using the Select Source Pins for Clock

Constraint dialog box (as shown below).

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Figure 94 · Select Source Pins for Clock Constraint Dialog Box

Understanding explicit clocks

Understanding potential clocks

Choose the Clock Source dialog box

Understanding Explicit Clocks

Explicit clocks are pins or ports connected to the clock pin of one or more sequential component, and where each clock is one of the following:

• The output of a PLL

• An input port that does not get gated between the source and the clock pins it drives

• The output pin of a sequential element that does not get gated between the source and the clock pins it drives

• Any pin or port on which a clock constraint was specified

By default, SmartTime displays domains with explicit clocks in the Timing Analysis View. You can browse these domains in the Domain Browser of the Timing Analysis View.

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Understanding Potential Clocks

Figure 95 · Explicit Clocks

See Also

Using clock types

Understanding potential clocks

Choose the Clock Source dialog box

Figure 96 ·

Understanding Potential Clocks

Potential clocks are the clock sources that could be either enabled sources or clock sources. This type of clock is generally associated with the use of gated clocks. When associated with gated clocks, SmartTime cannot differentiate between the enabled sources and clock sources. Both sources appear in the potential clocks list and not the explicit clocks list.

See Also

Using clock types

Understanding explicit clocks

Choose the Clock Source dialog box

Understanding Clock Networks

Clock networks are internal clock network pins used as a clock source. With this network type, you can set the clock constraint on any pin in the clock network. You may want to do this to eliminate clock network pessimism by short-cutting a reconvergent combinational logic on the clock network (as shown below).

Clock network pessimism triggers an overestimation of the clock skew, making the timing analysis inaccurate.

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Figure 97 · Source Being Set Within a Clock Network

See Also

Using clock types

Understanding potential clocks

1. Add the constraint in the editable constraints grid

Specifying Clock Constraints

Specifying clock constraints is the most effective way to constrain and verify the timing behavior of a sequential design. Use clock constraints to meet your performance goals.

To specify a clock constraint:

2. Select the pin to use as the clock source. You can click the Browse button to display the

Create Clock Constraint

dialog box

using one of the following methods:

•

From the Actions menu, choose Constraints > Clock.

•

Click the icon.

•

Right-click the Clock in the Constraint Browser.

•

Double-click any field in the Generated Clock Constraints grid.

The Create Clock Constraint dialog box appears (as shown below).

Figure 98 · Create Clock Constraint Dialog Box

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Specifying Generated Clock Constraints

Select

Source Pins for Clock Constraint

dialog box (as shown below).

Note: Do not select a source pin when you specify a virtual clock. Virtual clocks can be used to define a clock outside the FPGA that it is used to synchronize I/Os.

Use the Choose the Clock Source Pin dialog box to display a list of source pins from which you can choose. By default, it displays the explicit clock sources of the design. To choose other pins in the design as clock source pins, select Filter available objects - Pin Type as Explicit clocks, Potential clocks,

Input ports, All Pins, All Nets, Pins on clock network,or Nets in clock network. To display a subset of the displayed clock source pins, you can create and apply a filter.

Multiple source pins can be specified for the same clock when a single clock is entering the FPGA using multiple inputs with different delays.

Click OK to save these dialog box settings.

3. Specify the Period in nanoseconds (ns) or Frequency in megahertz (MHz).

4. Modify the Clock Name. The name of the first clock source is provided as default.

5. Modify the Duty cycle, if needed.

6. Modify the Offset of the clock, if needed.

7. Modify the first edge direction of the clock, if needed.

7. Click OK. The new constraint appears in the Constraints List.

Note: When you choose File > Commit, SmartTime saves the newly created constraint in the database.

Figure 99 · SmartTime Timing Constraint View

See Also

Clock definition

Create a clock

Create clock constraint dialog box

Specifying Generated Clock Constraints

Specifying a generated clock constraint enables you to define an internally generated clock for your design

and verify its timing behavior. Use generated clock constraints and clock constraints to meet your

performance goals.

To specify a generated clock constraint:

1. Add the constraint in the editable constraints grid

source pins, click the Browse button. The

dialog box using one of the following methods:

•

From the Actions menu, choose Constraints > Generated Clock.

•

Click the icon.

•

Right-click the GeneratedClock in the Constraint Browser.

•

Double-click any field in the Generated Clock Constraints grid.

The Create Generated Clock Constraint dialog box appears (as shown below).

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Figure 100 · Create Generated Clock Constraint

2. Select a Clock Pin to use as the generated clock source. To display a list of available generated clock

Select Generated Clock Source

dialog box appears (as

shown below).

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Using Automatically Generated Clock Constraints

Figure 101 · Select Generated Clock Source Dialog Box

3. Modify the Clock Name if necessary.

4. Click OK to save these dialog box settings.

5. Specify a Clock Reference. To display a list of available clock reference pins, click the Browse

button. The

Select Generated Clock Reference

Create clock constraint dialog box

5. Click OK to save this dialog box settings.

6. Specify the values to calculate the generated frequency: a multiplication factor and/or a division factor

(both positive integers).

7. Specify the first edge of the generated waveform either same as or inverted with respect to the reference waveform.

8. Click OK. The new constraint appears in the Constraints List.

Tip: From the File menu, choose Commit to save the newly created constraint in the database.

See Also

Design Constraint Guide: Clock definition

Design Constraint Guide: Create a clock

Using Automatically Generated Clock Constraints

The automatically generated clock constraints is only available for SmartFusion2, IGLOO2, SmartFusion,

IGLOO, ProASIC3, Fusion families.

If your design uses a static PLL, SmartTime automatically generates the required frequency at the output of the PLL, provided you have supplied the input frequency. When you start SmartTime, a generated clock constraint appears in the Constraints List with the multiplication and division factor extracted from the PLL configuration. The File column specifies this constraint as auto-generated (as shown below).

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Figure 102 · Constraints Editor

Note: SmartTime does not automatically create a Generated Clock constraint if you have already set a constraint on the PLL output.

If you delete the automatically generated clock constraint, SmartTime does not regenerate it the next time you open the design. However, you can easily create it again by using the following steps:

1. Open the

dialog box (as shown below).

Figure 103 · Create Generated Clock Constraint

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Specifying an Input Delay Constraint

2. Select the PLL output as the Clock Pin source for the generated clock.

3. Select the PLL input clock as the Clock Reference for the generated clock.

4. Click Get Pre-Computed Factors. SmartTime retrieves the factor from the static PLL configuration.

5. Click OK.

See Also

Create Generated Clock Constraint (SDC)

Specifying an Input Delay Constraint

Use the input delay constraint to define the arrival time of an input relative to a clock.

To specify an input timing delay constraint:

1. Add the constraint in the editable constraints grid or open the Set Input Delay Constraint dialog box

using one of the following methods:

•

From the SmartTime Actions menu, choose Constraints > Input Delay.

•

Click the icon.

•

Right-click the Input Delay in the Constraint Browser.

•

Double-click any field in the Input Delay Constraints grid.

The Set Input Delay Constraint dialog box appears (as shown below).

Figure 104 · Set Input Delay Dialog Box

2. Select either External Setup/Hold or Input Delay.

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•

External Setup/Hold enables you to enter an input delay constraint by specifying the timing budget inside the FPGA using the external setup and hold time. This is the default selection.

Note: The external hold information is currently used for analysis only and not by the optimization tools.

For the basic timing analysis flow of a simple design, select External Setup/Hold.

•

Input Delay enables you to enter an input delay constraint by specifying the timing budget outside the FPGA. You can enter the Maximum Delay, the Minimum Delay, or both.

Note: The Minimum Delay is currently used for analysis only and not by the optimization tools.

When you change values in one view, SmartTime automatically updates the other view.

3. Specify the Input Port or click the Browse button to display the Select Ports for Input Delay dialog box.

Figure 105 · Select Ports for Input Delay Dialog Box

3. Select the name of the input pin(s) from the Available Pins list. Choose the Pin Type from the dropdown list. You can use the filter to narrow the pin list. You can select multiple ports in this window.

4. Click Add or Add All to move the input pin(s) from the Available Pins list to the Assigned Pins list.

5. Click OK.

The Set Input Delay Constraint dialog box displays the updated Input Port information.

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Specifying an Output Delay Constraint

Figure 106 · Updated Set Input Delay Constraint Dialog Box

4. Select a clock from the Clock Port drop-down list.

5. If you selected Show by: External Setup/Hold, specifythe External Setup.

If you selected Show by: Input Delay, specify the Maximum Delay value.

6. If you selected Show by External Setup/Hold, specify the External Hold. If you selected Show by:

Input Delay, specify the Minimum Delay value.

7. Click OK.

SmartTime adds this constraint to the Constraints List in the SmartTime Constraints Editor.

See Also

Set Input Delay Constraint dialog box

Select Source or Destination Pins for Constraint dialog box

Specifying an Output Delay Constraint

Use the output delay constraints to define the output delay of an output relative to a clock.

To specify an output delay constraint:

1. Add the constraint in the editable constraints grid or open the Set Output Delay Constraint dialog box

using one of the following methods:

•

From the SmartTime Actions menu, choose Constraints > Output Delay.

•

Click the icon.

•

Right-click the Output Delay in the Constraint Browser.

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•

Double-click any field in the Output Delay Constraints grid.

The Set Output Delay Constraint dialog box appears.

Figure 107 · Set Output Delay Constraint Dialog Box

Specify either Clock-to-Output or Output Delay.

•

Clock-to-Output enables you to enter an output delay constraint by specifying the timing budget inside the FPGA. This is the default selection.

•

Note: The Minimum Delay value is currently used for analysis only and not by the optimization tool.

•

Output Delay enables you to enter an output delay constraint by specifying the timing budget outside the FPGA. You can enter either the Maximum Delay, the Minimum Delay, or both.

Note: The Minimum Delay is currently used for analysis only and not by the optimization tools.

When you change values in one view, SmartTime automatically updates the values in the other view.

3. Enter the name of the Output Port or click the Browse button to display the Select Ports for Output

Delay dialog box.

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Specifying an Output Delay Constraint

Figure 108 · Select Ports for Output Delay Dialog Box

4. Select the output pin(s) from the Available Pin list. Choose the Pin Type from the drop-down list. You can use the filter to narrow the pin list. You can select multiple ports in this dialog box.

5. Click Add or Add All to move the output pin(s) from the Available Pins list to the Assigned Pins list.

6. Click OK. The Set Output Delay Constraint dialog box displays the updated representation of the

Output Port graphic.

7. Select a clock port from the Clock Port drop-down list.

8. Enter the Maximum Delay value.

9. Enter the Minimum Delay value.

10. Click OK. SmartTime adds this constraint to the Constraints List in the Constraints Editor.

See Also

Set Output Delay Constraint dialog box

Select Source or Destination Pins for Constraint dialog box

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SmartTime Timing Analyzer

Components of the SmartTime Timing Analyzer

Use the SmartTime Timing Analyzer to visualize and identify timing issues in your design for the selected scenario. In this view, you can evaluate how far you are from meeting your timing requirements, create custom sets to track, set timing exceptions to obtain timing closure, and cross-probe paths with other tools.

The timing analysis view includes:

• Domain Browser: Enables you to perform your timing analysis on a per domain basis.

• Path List: Displays paths in a specific set in a given domain sorted by slack.

• Path Details: Displays detailed timing analysis of a selected path in the paths list.

• Analysis View Filter: Enables you to filter the content of the paths list.

• Path Slack Histogram: When a set is selected in the Domain Browser, the Path Slack Histogram displays a distribution of the path slacks for that set. Selecting one or multiple bars in the Path Slack

Histogram filters the paths displayed in the Path List.

You can copy, change the resolution and the number of bars of the chart from the right-click menu.

Figure 109 · SmartTime Timing Analyzer Components

See Also

SmartTime scenarios

SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion

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Analyzing Your Design

Analyzing Your Design

The timing engine uses the following priorities when analyzing paths and calculating slack:

1. False path

2. Max/Min delay

3. Multi-cycle path

4. Clock

If multiple constraints of the same priority apply to a path, the timing engine uses the tightest constraint.

You can perform two types of timing analysis: Maximum Delay Analysis and Minimum Delay Analysis.

To perform the basic timing analysis:

1. Open the Timing Analysis View using one of the following methods:

•

In the Design Flow window, click the Timing Analyzer icon to display the SmartTime Timing

Analyzer.

•

From the SmartTime Tools menu, choose Timing Analyzer > Maximum Delay Analysis or

Minimum Delay Analysis.

•

Click the icon for Maximum Delay Analysis or the from the SmartTime window.

icon for Minimum Delay Analysis

Note: When you open the Timing Analyzer from Designer, the Maximum Delay Analysis window is displayed by default.

Figure 110 · Maximum Delay Analysis View

2. In the Domain Browser, select the clock domain. Clock domains with a indicate that the timing requirements in these domains were met. Clock domains with an x indicate that there are violations within these domains. The Paths List displays the timing paths sorted by slack. The path with the lowest slack (biggest violation) is at the top of the list.

3. Select the path to view. The Path Details below the Paths List displays detailed information on how the slack was computed by detailing the arrival time and required time calculation. When a path is violated, the slack is negative and is displayed in red color.

4. Double-click the path to display a separate view that includes the path details and schematic.

Note: In cases where the minimum pulse width of one element on the critical path limits the maximum frequency for the clock, SmartTime displays an icon for the clock name in the Summary List.

Click on the icon to display the name of the pin that limits the clock frequency.

5. Repeat the above steps as required.

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Performing a Bottleneck Analysis - SmartFusion, IGLOO,

ProASIC3, and Fusion

To perform a bottleneck analysis

1. From the SmartTime Tools menu, select Timing Analyzer > Bottleneck Analysis. The

Timing

Bottleneck Analysis Options dialog box

appears.

2. Select the options you wish to display and click OK.

The Bottleneck Analysis View appears in a separate window (see image below).

Figure 111 · Bottleneck Analysis View

A bottleneck is a point in the design that contributes to multiple timing violations. The Bottleneck Analysis

View contains two sections

• Device Description

• Bottleneck Description

Device Description

The device section contains general information about the design and the parameters that define the bottleneck computation:

• Design name

• Family

• Die

• Package

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Managing Clock Domains

• Design state

• Data source

• Set selection type

• Max paths

• Bottleneck instances

• Analysis type

• Analysis max case

• Voltage

• Temperature

• Speed grade

• Cost type

• Max parallel paths

• Slack threshold

Bottleneck Description

This section displays a graphic representation of the bottleneck analysis and lists the core of the bottleneck information for the bar selected in the chart above. If no bar is selected, the grid lists all bottleneck information.

Click the controls on the right to zoom in or out the contents in the chart.

Right-click the chart to export the chart or to copy the chart to the clipboard.

The list is divided into two columns:

• Instance name: refers to the output pin name of the instance. Click the pin name to select the cell and the corresponding instance is selected in MultiView Navigator (MVN).

• Bottleneck cost: displays the pin's cost given the chosen cost type. Pin names are listed in decreasing order of their cost type.

Managing Clock Domains

In SmartTime, timing paths are organized by clock domains. By default, SmartTime displays domains with explicit clocks. Each clock domain includes at least three path sets:

• Register to Register

• External Setup (in the Maximum Analysis View) or External Hold (in the Minimum Analysis View)

• Clock to Out

You must select a path set to display a list of paths in that specific set.

To manage the clock domains:

1. Right-click anywhere in the Domain Browser, and choose Manage Clock Domains. The

Manage

Clock Domains

dialog box appears (as shown below).

Tip: You can click the dialog box.

icon in the SmartTime window bar to display the

Manage Clock Domains

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Figure 112 · Manage Clock Domains Dialog Box

2. To add a new domain, select a clock domain from the Available clock domains list, and click either

Add or New Clock to add a non-explicit clock domain.

3. To remove a displayed domain, select a clock domain from the Show the clock domain in this order list, and click Remove.

4. To change the display order in the Domain Browser, select a clock domain from the Show the clock

domain in this order list, and then use the Move Up or Move Down to change the order in the list.

5. Click OK. SmartTime updates the Domain Browser based on your specifications. If you have added a new clock domain, then it will include at least the three path sets as mentioned above.

See Also

Manage Clock Domain dialog box

Managing Path Sets

You can create and manage custom path sets for timing analysis and tracking purposes. Path sets are displayed under the Custom Path Sets at the bottom of the Domain Browser.

To add a new path set:

1. Right-click anywhere in the Domain Browser, and choose Add Set. The

Add Path Analysis Set

dialog box appears (as shown below).

Tip: You can click the dialog box.

icon in the SmartTime window bar to display the

Add Path Analysis Set

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Managing Path Sets

Figure 113 · Add Path Analysis Set Dialog Box

2. Enter a name for the path set.

3. Select the source and sink pins. You can use the filters to control the type of pins displayed.

4. Click OK. The new path set appears under Custom Path Sets in the Domain Browser (as shown below).

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Figure 114 · Updated Domain Browser with User Sets

To remove an existing path set:

1. Select the path set from the User Sets in the Domain Browser.

2. Right-click the set to delete, and then choose Delete Set from the right-click menu.

To rename an existing path set:

1. Select the path set from User Set in the Domain Browser.

2. Right-click the set to rename, and then choose Rename Set from the right-click menu.

3. Edit the name directly in the Domain Browser.

See Also

Add Path Analysis Set dialog box

dialog box appears (as shown below).

Exporting Files

Displaying Path List Timing Information

The Path List in the Timing Analysis View displays the timing information required to verify the timing requirements and identify violating paths. The Path List is organized in a grid where each row represents a timing path with the corresponding timing information displayed in columns. Timing information is customizable; you can add or remove columns for each type of set.

By default, each type of set displays a subset of columns as follows:

• Register to Register: Source Pin, Sink Pin, Delay, Slack, Arrival, Required, Setup, Minimum Period, and Skew.

• External Setup: Source Pin, Sink Pin, Delay, Slack, Arrival, Required, Setup, and External Setup.

• Clock to Out: Source Pin, Sink Pin, Delay, Slack, Arrival, Required, and Clock to Out.

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Displaying Expanded Path Timing Information

• Input to Output: Source Pin, Sink Pin, Delay, and Slack.

• Custom Path Sets: Source Pin, Sink Pin, Delay, and Slack.

You can add the following columns for each type of set:

• Register to Register: Clock, Source Clock Edge, Destination Clock Edge, Logic Stage Count, Max

Fanout, Clock Constraint, Maximum Delay Constraint, and Multicycle Constraint.

• External Setup: Clock, Destination Clock Edge, Logic Stage Count, Max Fanout, Clock Constraint,

Input Delay Constraint, Required External Setup, Maximum Delay Constraint, and Multicycle

Constraint.

• Clock to Out: Clock, Source Clock Edge, Logic Stage Count, Max Fanout, Clock Constraint, Output

Delay Constraint, Required Maximum Clock to Out, Maximum Delay Constraint, and Multicycle

Constraint.

• Input to Output: Arrival, Required, Setup, Hold, Logic Stage Count, and Max Fanout.

• Custom Path Sets.

To customize the set of timing information in the Path List:

1. Select the set to customize.

2. Select the whole Paths List by clicking in the upper-left corner.

3. Right-click anywhere on the column headings, and then choose Customize table from the right-click

menu. The

Customize Analysis View

Figure 115 · Customize Analysis View Dialog Box

4. To add one or more columns, select the fields to add from the Available fields list, and click Add.

5. To remove one or more columns, select the fields to remove from the Show these fields in this order list, and click Remove.

6. Click OK to add or remove the selected columns. SmartTime updates the Timing Analysis View.

See Also

Customize Analysis View

Displaying Expanded Path Timing Information

SmartTime displays the list of paths and the path details for all parallel paths.

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Figure 116 · Expanded Path View

The Path List displays all parallel paths in your design. The Path Details grid displays the path details for all parallel paths.

To display the Expanded Path View:

From the Path List: double-click the path, or right-click a path and select expand selected paths.

From the Expanded Path View: double-click the path, or right-click the path and select expand path.

Figure 117 · Expanded Path View

The Expanded Path Summary provides a summary of all parallel paths for the selected path. The Path

Profile chart displays the percentage of time taken by cells and nets for the selected path. If no parallel path

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Using Filters

is selected in this view, the Path Profile shows the percentage for all paths. By default, SmartTime only

shows one path for each Expanded Path. You can change this default in the SmartTime Options dialog box.

The Expanded Path View also includes a schematic of the path and a path profile chart for the paths selected in the Expanded Path Summary.

Using Filters

You can use filters in SmartTime to limit the Path List content (that is, create a filtered list on the source and sink pin names). The filtering options appear on the top of the Timing Analysis View. You can save these filters one level below the set under which it has been created.

To use the filter:

1. Select a set in the Domain Browser to display a given number of paths, depending on your

SmartTime

Options settings (100 paths by default).

2. Enter the filter criteria in both the From and To fields and click Apply Filter. This limits the display to the paths that match your filter criteria.

Figure 118 · Maximum Delay Analysis View

3. Click Store Filter to save your filter criteria with a special name. The

Store Filter as Analysis Set

dialog

box appears (as shown below).

Figure 119 · Store Filter as Analysis Set Dialog Box

4. Enter a name for the filter such as MyFilter01, and click OK. Your new filter name appears below the set under which it was created.

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100

Figure 120 · Updated Maximum Delay Analysis View

Repeat the above steps and cascade as many sets as you need using the filtering mechanism.

To remove a set created with filters:

1. Select the set that uses filters.

2. Right-click the set, and choose Delete Set from the shortcut menu.

To rename a set created with filters:

1. Select the set that uses filters.

2. Right-click the set, and choose Rename Set from the shortcut menu.

3. Edit the name directly in the Domain Browser.

To edit a specific filter in the set:

1. Select the filter to edit.

2. Right-click the filter, and choose Edit Set from the shortcut menu.

See Also

SmartTime Options

Store Filter as Analysis Set

Edit Set dialog box

Exporting Files

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Using Filters

Cross-probing between ChipPlanner and SmartTime

Use ChipPlanner with SmartTime to identify the signal path or individual instances in ChipPlanner.

To identify paths in ChipPlanner:

1. In the Design Flow window, click ChipPlanner to display the chip view, and then click Timing

Analyzer to display the SmartTime Timing Analyzer.

2. In the SmartTimeTiming Analyzer, select the clock domain in the Domain Browser.

3. Select a set in the Path list (as shown below) and the paths within that set are displayed in the Path

Details (lower table). The Paths List displays timing information for various categories.

Figure 121 · Path Details of Selected Path Highlighted

4. Select the path to cross-probe.

5. Right-click the selected path, and choose Cross-probe selected paths from the right-click menu. All objects in the selected path appear highlighted in ChipPlanner (as shown below).

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102

Figure 122 · Objects in Selected Path Appear Highlighted in ChipPlanner

Note: Logic must be either placed or placed-and-routed before you can cross-probe paths.

Tip: From the

Edit

menu, choose

Unhighlight All

to remove the highlighting from the cross-probed paths in ChipPlanner.

To cross-probe an object with ChipPlanner:

1. In the Design Flow window, click ChipPlanner to display the chip view, and then click Timing

Analyzer to display the SmartTime Timing Analyzer.

2. In the SmartTimeTiming Analyzer, select the clock domain in the Domain Browser.

3. Select a path in the Paths List, right-click it, and choose Expand selected paths from the right-click menu.

4. Select any instance in the SmartTime Expanded Path View. The instance appears highlighted in both

SmartTime and ChipPlanner.

5. To cross-probe the path of the selected object, right-click the instance, and choose Cross-probe Path from the right-click menu. All objects in the selected path appear highlighted in ChipPlanner.

When you cross-probe a path in ChipPlanner, the default view is the Ratsnest view, shown in the following example.

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Using Filters

Figure 123 · Ratsnest view in ChipPlanner showing cross-probed path

Tip: To select multiple instances, hold down the Shift key as you click each instance.

The critical cross-probed path appears highlighted in ChipPlanner as a solid line with arrows indicating the direction of the path. The color of the line is the color you selected for the highlight color.

You can right-click a selected cross-probed path, choose Properties to display the Path Properties dialog box, and do one of the following:

• Rename the cross-probed path

• Assign a different color to the cross-probed path

You can create more than one cross-probed path in ChipPlanner, building one path on top of another.

ChipPlanner does not delete paths you have cross-probed. When you save your design, the cross-probed paths are also saved in your design (.ADB) file.

Tip: In SmartTime, you can select several paths at one time by clicking the top-left corner square in the

Maximum Delay Analysis View window.

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Cross-probing Between NetlistViewer and SmartTime

Use NetlistViewer with SmartTime to view and trace entire Timing paths and to cross-probe one or more objects.

Note: Your design must be compiled to start NetlistViewer. If it is not compiled, Designer prompts you to compile your design. After you compile it, NetlistViewer opens and displays the netlist.

To cross-probe an object using NetlistViewer and SmartTime:

1. In the Design Flow window, click NetlistViewer to display your netlist, and then click Timing

Analyzer to display the SmartTime Timing Analyzer.

2. In the SmartTimeTiming Analyzer, select the clock domain in the Domain Browser.

3. Select a path in the Paths List, right-click it, and choose Expand selected paths from the right-click menu.

4. Select any instance in the SmartTime Expanded Path View. The instance appears highlighted in both

SmartTime and NetlistViewer as shown in the following example.

Tip: To select multiple instances, hold down the Shift key as you click each instance.

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Figure 124 · Selected Instance Appears Highlighted in Both SmartTime and NetlistViewer

5. To cross-probe a path, right-click the path, and choose Cross-probe Path from the right-click menu

(as shown in the following example).

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Using Filters

Figure 125 · Cross-probe Path Using Right-click Menu

All objects in the selected path appear highlighted in NetlistViewer as shown below.

Figure 126 · All Objects in the Cross-probed Path Appear Highlighted in NetlistViewer

Tip: Changing the highlight color does not change the color of all cross-probed paths in NetlistViewer. To change the color of a cross-probed path, from the Edit menu, choose Highlight Color and select a different color. Then cross-probe the path again in SmartTime. The cross-probed path will appear in the new highlight color.

See Also

Identifying Paths

Cross-probing between NetlistViewer and ChipPlanner

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Advanced Timing Analysis

Understanding Inter-Clock Domain Analysis

When functional paths exist across two clock domains (the register launching the data and the one capturing it are clocked by two different clock sources), you must provide accurate specification of both clocks to allow a valid inter-clock domain timing check. This is important especially when the clocks are specified with different waveforms and frequencies.

When you specify multiple clocks in your design, the first step is to consider whether the inter-clock domain paths are false or functional. If these paths are functional, then you must perform setup and hold checks between the clock domains in SmartTime. Unless specified otherwise, SmartTime considers the inter-clock domain as false, and therefore does not perform setup or hold checks between the clock domains.

If you have several clock domains that are subset of a single clock (such as if you want to measure clock tree delay from an input clock to a generated clock), you must configure Generated Clock Constraints for each of the clock domains in order for SmartTime to do execute the calculation and show timing for each of the inter-clock-domain paths.

Once you include the inter-clock domains for timing analysis, SmartTime analyzes for each inter-clock domain the relationship between all the active clock edges over a common period equal to the least common multiple of the two clock periods. The new common period represents a full repeating cycle (or pattern) of the two clock waveforms (as shown below).

For setup check, SmartTime considers the tightest relation launch-capture to ensure that the data arrives before the capture edge. The hold check verifies that a setup relationship is not overwritten by a following data launch.

106

Figure 127 · Example Showing Inter-Clock Domains

See Also

Activating inter-clock domain analysis

Deactivating a specific inter-clock domain

Displaying inter-clock domain paths

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Activating Inter-Clock Domain Analysis

Activating Inter-Clock Domain Analysis

To activate the inter-clock domain checking:

1. In SmartTime, from the Tools menu choose Options. The

SmartTime Options

dialog box appears

(as shown below).

2. In the general category, check the Include inter-clock domains in calculations for timing analysis.

Figure 128 · SmartTime Options Dialog Box

3. Click OK to save the dialog box settings.

Deactivating a specific inter-clock domain

Displaying inter-clock domain paths

SmartTime Options dialog box

Displaying Inter-Clock Domain Paths

Once you activate the inter-clock domain checking for a given clock domain CK1, SmartTime automatically

detects all other domains CKn with paths ending at CK1. SmartTime creates inter-clock domain sets CKn to

CK1 under the domain CK1. Each of these sets enables you to display the inter-clock domain paths between a given clock domain and CK1.

To display an inter-clock domain set:

1. Expand the receiving clock domain of the inter-clock domain in the Domain Browser to display its related sets. For the inter-clock domain CK1 to CK2, expand clock domain CK2.

2. Select the inter-clock domain that you want to see expanded from these sets. Once selected, all paths between the related two domains are displayed in Paths List in the same way as any register to register set.

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Figure 129 · Maximum Delay Analysis View

Activating inter-clock domain analysis

Deactivating a specific inter-clock domain

Deactivating a Specific Inter-Clock Domain

To deactivate the inter-clock domain checking for the specific clock domains clk2->clk1, without disabling this option for the other clock domains:

1. From the Tools menu, choose Constraints Editor > Primary Scenario to open the Constraints Editor

View.

2. In the Constraints Browser, double-click False Path under Exceptions. The "

Set False Path

Constraint

3. Click the Browse button to the right of the From text box. The Select Source Pins for False Path

Constraint dialog box appears.

4. For Specify pins, select by keyword and wildcard.

5. For Pin Type, select Registers by clock names from the Pin Type drop-down list.

6. Type the inter-clock domain name, for example Clk2 in the filter box and click Filter.

7. Click OK to begin filtering the pins by your criteria. In this example, [get_clocks {Clk2}] appears in the

From text box in the

Set False Path Constraint

8. Repeat steps 3 to 7 for the To option in the

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Timing Exceptions Overview

Set False Path Constraint dialog box, and type Clk2 in the

filter box.

9. Click OK to validate the new false path and display it in the Paths List of the Constraints Editor.

10. Click the Recalculate All icon

in the toolbar.

11. Select the inter-clock domain set clk2 -> clk1 in the Domain Browser (as shown below).

12. Verify that the set does not contain any paths.

Figure 130 · Maximum Delay Analysis View

Activating inter-clock domain analysis

Displaying inter-clock domain paths

Select Source or Destination Pins for Constraint dialog box

Set False Path Constraint dialog box

Timing Exceptions Overview

Use timing exceptions to overwrite the default behavior of the design path. Timing exceptions include:

• Setting multicycle constraint to specify paths that (by design) will take more than one cycle.

• Setting a false path constraint to identify paths that must not be included in the timing analysis or the optimization flow.

• Setting a maximum delay constraint on specific paths to relax or to tighten the original clock constraint requirement.

See Also

Specifying maximum delay constraint

Specifying multiple path constraint

Changing output port capacitance

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Specifying a Maximum Delay Constraint

You set options in the

Maximum Delay Constraint dialog

box to relax or to tighten the original clock

constraint requirement on specific paths.

To specify Max delay constraints:

1. Add the constraint in the editable constraints grid

Timing exceptions overview

Set Maximum Delay Constraint

dialog

box using one of the following methods:

•

From the SmartTime Actions menu, choose Constraints > Max delay.

•

Click the icon.

•

Right-click Max delay in the Constraint Browser.

•

Double-click any field in the Maximum Delay Constraints grid.

The Set Maximum Delay Constraint dialog box appears (as shown below).

110

Figure 131 · Set Maximum Delay Constraint Dialog Box

2. Specify the delay in the Maximum delay field.

3. Specify the From pin(s). Click the Browse button next to From to open the Select Source Pins for

Max Delay Constraint dialog box (as shown below).

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Specifying a Maximum Delay Constraint

Figure 132 · Select Source Pins for Max Delay Constraint

4. Select by explicit list. (Alternatively, you can select by keyword and wildcard.)

5. Select the input pin(s) from the Available Pins list. You can also use Filter available objects to narrow the pin list. You can select multiple ports in this window.

6. Click Add or Add All. The input pin(s) move from the Available Pins list to the Assigned Pins list.

7. Click OK.The Set Maximum Delay Constraint dialog box displays the updated From pin(s) list.

8. Click the Browse button for Through and To and add the appropriate pin(s). The displayed list shows the pins reachable from the previously selected pin(s) list.

9. Enter comments in the Comment section.

10. Click OK.

SmartTime adds the maximum delay constraints to the Constraints List in the SmartTime Constraints Editor.

See Also

Set Maximum Delay Constraint dialog box

Specifying maximum delay constraint

Specifying multicycle constraint

Changing output port capacitance

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Specifying a Minimum Delay Constraint

You set options in the

Minimum Delay Constraint dialog

box to relax or to tighten the original clock

constraint requirement on specific paths.

To specify Min delay constraints:

1. Add the constraint in the editable constraints grid

Timing exceptions overview

Set Minimum Delay Constraint

dialog

box using one of the following methods:

•

From the SmartTime Actions menu, choose Constraints > Min delay.

•

Click the icon.

•

Right-click Min delay in the Constraint Browser.

•

Double-click any field in the Minimum Delay Constraints grid.

The Set Minimum Delay Constraint dialog box appears (as shown below).

112

Figure 133 · Set Minimum Delay Constraint Dialog Box

2. Specify the delay in the Minimum delay field.

3. Specify the From pin(s). Click the Browse button next to From to open the Select Source Pins for

Min Delay Constraint dialog box (as shown below).

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Specifying a Multicycle Constraint

Figure 134 · Select Source Pins for Max Delay Constraint

4. Select by explicit list. (Alternatively, you can select by keyword and wildcard.)

5. Select the input pin(s) from the Available Pins list. You can also use Filter available objects to narrow the pin list. You can select multiple ports in this window.

6. Click Add or Add All. The input pin(s) move from the Available Pins list to the Assigned Pins list.

7. Click OK. The Set Minimum Delay Constraint dialog box displays the updated From pin(s) list.

8. Click the Browse button for Through and To and add the appropriate pin(s). The displayed list shows the pins reachable from the previously selected pin(s) list.

9. Enter comments in the Comment section.

10. Click OK.

SmartTime adds the minimum delay constraints to the Constraints List in the SmartTime Constraints Editor.

See Also

Set Minimum Delay Constraint dialog box

Specifying multicycle constraint

Changing output port capacitance

Specifying a Multicycle Constraint

You set options in the

Set Multicycle Constraint

dialog box to specify paths that take multiple clock cycles

in the current design.

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To specify multicycle constraints:

1. Add the constraint in the editable constraints grid

3. Specify the From pin(s). Click the browse button (...) next to From to open the

Set Multicycle Constraint

dialog box

using one of the following methods:

•

From the SmartTime Actions menu, choose Constraint > MultiCycle.

•

Click the icon.

•

Right-click the Multicycle option in the Constraint Browser.

The Set Multicycle Constraint dialog appears (as shown below).

114

Figure 135 · Set Multicycle Constraint Dialog Box

2. Specify the number of cycles in the Setup Path Multiplier.

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Specifying a Multicycle Constraint

Select Source Pins for

Multicycle Constraint

dialog box (as shown below).

Figure 136 · Select Source Pins for Multicycle Constraint

4. Select by explicit list. (Alternatively, you can select by keyword and wildcard. For details, refer to

Select Source or Destination Pins for Constraint .)

5. Select the input pin(s) from the Available Pin list. You can use Filter available objects to narrow the pin list. You can select multiple ports in this window.

6. Click Add or Add All to move theinput pin(s) move from the Available pins list to the Assigned Pins list.

7. Click OK.

The Set Multicycle Constraint dialog box displays the updated representation of the From pin(s) (as shown below).

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116

Figure 137 · Set Multicycle Constraint Dialog Box

8. Click the browse button for Through and To and add the appropriate pins. The displayed list shows the pins reachable from the previously selected pin(s) list.

9. Enter comments in the Comment section.

10. Click OK. SmartTime adds the multicycle constraints to the Constraints List in the SmartTime

Constraints Editor.

See Also

Set Multicycle Constraint dialog box

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Specifying a False Path Constraint

Select Source Pins for Multicycle Constraint dialog box

Specifying a False Path Constraint

You set options in the Set False Path Constraint dialog box to define specific timing paths as false.

To specify False Path constraints:

1. Add the constraint in the

Editable Constraints Grid or open the Set False Path Constraint dialog box.

You can do this by using one of the following methods:

•

From the SmartTime Constraints menu, choose False Path.

•

Click the icon.

•

Right-click False Path in the Constraint Browser.

•

Double-click any field in the False Path Constraints grid.

The Set False Path Constraint dialog box appears (as shown below).

Figure 138 · Set False Path Constraint Dialog Box

2. Specify the From pin(s). Click the Browse button next to From to open the Select Source Pins for

False Path Constraint dialog box (as shown below).

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Figure 139 · Select Source Pins for False Path Constraint Dialog Box

3. Select by explicit list. (Alternatively, you can select by keyword and wildcard. For details, refer to

Select Source or Destination Pins for Constraint .)

4. Select the input pin(s) from the Available Pin list. You can use Filter available objects to narrow the pin list. You can select multiple ports in this window.

5. Click Add or Add All. The input pin(s) move from the Available Pins list to the Assigned Pins list.

6. Click OK.

The

Set False Constraint

dialog box displays the updated representation of the From pin(s).

7. Click the Browse button for Through and To and add the appropriate pin(s). The displayed list shows the pins reachable from the previously selected pin(s) list.

8. Enter comments in the Comment section.

9. Click OK.

SmartTime adds the False Path constraints to the Constraints List in the SmartTime Constraints Editor.

See Also

Set False Constraint dialog box

Select Source Pins for False Path Constraint dialog box.

Changing Output Port Capacitance

Output propagation delay is affected by both the capacitive loading on the board and the I/O standard. The

I/O Attribute Editor in ChipPlanner provides a mechanism for setting the expected capacitance to improve the propagation delay model. SmartTime automatically uses the modified delay model for delay calculations.

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Specifying Clock Source Latency

To change the output port capacitance and view the effect of this change in SmartTime Timing Analyzer, refer to the following example. The figure below shows the delay from FF3 to output port OUT2. It shows a delay of 6.603 ns based on the default loading of 35 pF.

Figure 140 · Maximum Delay Analysis View

If your board has output capacitance of 75pf on OUT2, you must perform the following steps to update the timing number:

1. Open the I/O Attribute Editor and change the output load to 75pf.

Figure 141 · I/O Attribute Editor View

2. Select File > Commit.

3. Select File > Close.

4. Open the SmartTime Timing Analyzer.

You can see that the Clock to Output delay changed to 7.723 ns.

Specifying Clock Source Latency

Use clock source latency to specify the delay from the clock generation point to the clock definition point in the design.

Clock source latency defines the delay between an external clock source and the definition pin of a clock within SmartTime. It behaves much like an input delay constraint.

You can specify both an "early" delay and a "late" delay for this latency, providing an uncertainty which

SmartTime propagates through its calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

To specify the clock source latency:

1. Add the constraint in the editable constraints grid or open the Set Clock Source Latency dialog box

using one of the following methods:

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•

From the SmartTime Actions menu, choose Constraints > Clock Source Latency.

•

Click the icon.

•

Right-click Clock Source Latency in the Constraint Browser.

•

Double-click any field in the Clock Source Latency grid.

2. Select a clock pin on which to set the source latency. You can only specify a clock source latency on a clock pin that has a clock constraint. Additionally, you may apply only one clock source latency constraint to each constrained clock pin.

3. Enter the Late Rise, Early Rise, Late Fall, and Early Fall values as required for your design.

Note: An ‘early’ value larger than a ‘late’ value can result in optimistic timing analysis.

4. Select the Falling Same As Rising check box to indicate that falling clock edges have the same latency as rising clock edges.

5. Select the Early Same As Late check box to use a single value for the clock latency, rather than a range, by clicking the checkbox.

6. Enter any comments to be attached to the constraint.

7. Click OK. The new constraint appears in the constraints list.

Note: When you choose Commit from the File menu, SmartTime saves the newly-created constraint in the database.

See Also

Set Clock Source Latency dialog box

Specifying Disable Timing Constraint

Use disable timing constraint to specify the timing arcs being disabled.

To specify the disable timing constraint:

1. Add the constraint in the editable constraints grid

or open the Set Constraint to Disable Timing Arcs dialog box using one of the following methods:

•

From the SmartTime Actions menu, choose Constraints > Disable Timing.

•

Click the icon.

•

Right-click Disable Timing in the Constraint Browser.

•

Double-click any field in the Disable Timing grid.

2. Select an instance from your design.

3. Select whether you want to exclude all timing arcs in the instance or if you want to specify the timing arc to exclude. If you selected specify timing arc to exclude, select a from and to port for the timing arc.

4. Enter any comments to be attached to the constraint.

5. Click OK. The new constraint appears in the constraints list.

Note: When you choose Commit from the File menu, SmartTime saves the newly-created constraint in the database.

Specifying Clock-to-Clock Uncertainty Constraint

Use the clock-to-clock uncertainty constraint to model tracking jitter between two clocks in your design.

To specify the clock-to-clock uncertainty constraint:

1. Add the constraint in the editable constraints grid

or open the Set Clock-to-Clock Uncertainty

Constraint dialog box using one of the following methods:

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Specifying Clock-to-Clock Uncertainty Constraint

•

From the SmartTime Actions menu, choose Constraints > Clock-to-Clock Uncertainty

Constraint.

•

Click the icon.

•

Right-click Clock-to-Clock Uncertainty Constraint in the Constraint Browser.

•

Double-click any field in the Clock-to-Clock Uncertainty Constraint grid.

2. Specify the from and to clocks and specify the uncertainty in ns.

4. Enter any comments to be attached to the constraint.

5. Click OK. The new constraint appears in the constraints list.

Note: When you choose Commit from the File menu, SmartTime saves the newly-created constraint in the database.

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Generating Timing Reports

Types of Reports

Using SmartTime you can generate the following types of reports:

• Timing report – This report displays the timing information organized by clock domain.

• Timing violations report – This flat slack report provides information about constraint violations.

• Datasheet report – This report describes the characteristics of the pins, I/O technologies, and timing properties in the design.

• Bottleneck report – This report displays the points in the design that contribute to the most timing violations.

• Constraints coverage report – This report displays the overall coverage of the timing constraints set on the current design.

• Combinational loop report – This report displays loops found during initialization.

See Also

Generating timing report

Generating timing violation report

Generating a datasheet report

Generating a bottleneck report

Generating a constraints coverage report

Generating a Combinational Loop Report

Generating a Timing Report

The timing report enables you to quickly determine if any timing problems exist in your design. The timing report lists the following information about your design:

• Maximum delay from input I/O to output I/O

• Maximum delay from input I/O to internal registers

• Maximum delay from internal registers to output I/O

• Maximum delays for each clock network

• Maximum delays for interactions between clock networks

To generate a timing report:

1. From the Designer Tools menu, choose Reports > Timing > Timer. The

Timing Report Options dialog box appears.

2. Select the options you want to include in the report, and then click OK.

The timing report appears in a separate window.

You can also generate the timing report from within SmartTime. From the Tools menu, choose Reports >

Report Paths.

See Also

Understanding timing report

Timing Report Options dialog box

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Understanding Timing Reports

Understanding Timing Reports

The timing report contains the following sections:

Header

The header lists:

• The report type

• The version of Designer used to generate the report

• The date and time the report was generated

• General design information (name, family, etc.)

Summary

The summary section reports the timing information for each clock domain.

By default, the clock domains reported are the explicit clock domains that are shown in SmartTime. You can

filter the domains and get only specific sections in the report (see Timing Report Options ).

Path Sections

The paths section lists the timing information for different types of paths in the design. This section is

reported by default. You can deselect this option in the Timing Report Options dialog box.

By default, the number of paths displayed per set is 5.

You can filter the domains using the Timing Report Options dialog box.

You can also view the stored filter sets in the generated report using the timing report options (see Timing

Report Options ). The filter sets are listed by name in their appropriate section, and the number of paths

reported for the filter set is the same as for the main sets.

By default, the filter sets are not reported.

Clock domains

The paths are organized by clock domain.

Register to Register set

This set reports the paths from the registers clock pins to the registers data pins in the current clock domain.

Input to register set

This set reports the paths from the top level design input ports to the registers in the current clock domain.

Register to output set

This set reports the paths from the registers clock pins to the top level design output ports in the current clock domain.

Inter-clock domain

This set reports the paths from the registers clock pins of the specified clock domain to the registers data pins in the current clock domain. Inter-domain paths are not reported by default.

Pin to pin

This set lists input to output paths and user sets. Input to output paths are reported by default. To see the

user-defined sets, use the Timing Report Options dialog box.

Input to output set

This set reports the paths from the top level design input ports to top level design output ports.

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Expanded Paths

Expanded paths can be reported for each set. By default, the number of expanded paths to report is set to 1.

You can select and change the number when you specify Timing Report Options .

124

Figure 142 · Timing Report

See Also

Generating timing report

Timing Report Options dialog box

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Generating a Timing Violation Report

Generating a Timing Violation Report

The timing violations report provides a flat slack report centered around constraint violations.

To generate a timing violation report

1. From the Designer Tools menu, choose Reports > Timing > Timing Violations. The

Timing Violation

Report Options dialog box appears.

2. Select the options you want to include in the report, and then click OK. The timing violations report appears in a separate window.

You can also generate the timing violations report from within SmartTime. From the Tools menu, choose

Reports > Report Violations.

See Also

Understanding timing violation report

Timing Violations Report Options dialog box

Understanding Timing Violation Reports

The timing violation report contains the following sections:

Header

The header lists:

• The report type

• The version of Designer used to generate the report

• The date and time the report was generated

• General design information (name, family, etc.)

Paths

The paths section lists the timing information for the violated paths in the design.

The number of paths displayed is controlled by two parameters:

• A maximum slack threshold to report

• A maximum number or path to report

By default, the slack threshold is 0 and the number of paths is limited. The default maximum number of paths reported is 100.

All clocks domains are mixed in this report. The paths are listed by decreasing slack.

You can also choose to expand one or more paths. By default, no paths are expanded. For details, see the timing violation report options.

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Figure 143 · Timing Violations Report

Timing Violations Report Options dialog box (SmartTime)

Generating a Constraints Coverage Report

The constraints coverage report contains information about the constraints in the design.

To generate a constraints coverage report, from the Designer Tools menu, select Reports > Timing >

Constraints Coverage. The report appears in a separate window.

You can also generate the constraints coverage report from within SmartTime. From the Tools menu, choose Reports > Constraints Coverage.

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Understanding Constraints Coverage Reports

Understanding Constraints Coverage Reports

The constraint coverage displays the overall coverage of the timing constraints set on the current design.

You can generate this report either from within Designer or within SmartTime Analyzer. The report contains two sections:

• Coverage Summary

• Enhancement Suggestions

• Results by Clock Domain

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Figure 144 · Constraints Coverage Report

Coverage Summary

The coverage summary gives statistical information on the timing constraint in the design. For each type of timing checks (Setup, Recovery, Output, Hold and Removal), it specifies how many are met (there is a constraint and it is satisfied), violated (there is a constraint and it is not satisfied), or untested (no constraint was found).

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Generating a Bottleneck Report

Clock Domain

This section provides a coverage summary for each clock domain.

Enhancement Suggestions

The enhancement suggestion reports, per clock domain, a list of constraints that can be added to the design to improve the coverage. It also reports if some options impacting the coverage can be changed.

Detailed Stats

This section provides detailed suggestions regarding specific clocks or I/O ports that may require to be constrained for every pin/port that requires checks.

See Also

Clock

Input delay

Output delay

Setting SmartTime Options

Generating a Bottleneck Report

The bottleneck report provides a list of the bottlenecks in the design.

To generate a bottleneck report, from the Designer Tools menu, select Reports > Timing > Bottleneck.

The report appears in a separate window.

You can also generate the bottleneck report from within SmartTime. From the Tools menu, choose Reports

> Report Bottlenecks.

See Also

Understanding the bottleneck report

Timing Bottleneck Report Options dialog box

Understanding Bottleneck Reports - SmartFusion, IGLOO,

ProASIC3, and Fusion

A bottleneck is a point in the design that contributes to multiple timing violations. The purpose of the bottleneck report is to provide a list of the bottlenecks in the design. You can generate this report either from within Designer or within SmartTime Analyzer. It contains two sections

• Device Description

• Bottleneck Description

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Figure 145 · Bottleneck Report

The bottleneck can only be computed if and only a cost type is defined. There are two options available:

• Path count: This cost type associates the severity of the bottleneck to the count of violating/critical paths that traverse the instance.

• Path cost: This cost type associates the severity of the bottleneck to the sum of the timing violations for the violating/critical paths that traverse the instance.

Device Description

The device section contains general information about the design, including:

• Design name

• Family

• Die

• Package

• Software version

Bottleneck Description

This section lists the core of the bottleneck information. It is divided into two columns:

• Instance name: refers to the output pin name of the instance.

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Generating a Datasheet Report

• Bottleneck cost: displays the pin's cost given the chosen cost type. Pin names are listed in decreasing order of their cost type.

See Also

Generating a bottleneck report

Timing Bottleneck Report Options dialog box

Generating a Datasheet Report

The datasheet reports information about the external characteristics of the design.

To generate a datasheet report, from the Designer Tools menu, select Reports > Timing > Datasheet. The report appears in a separate window.

You can also generate the datasheet report from within SmartTime. From the Tools menu, choose Reports

> Datasheet.

See Also

Understanding the datasheet report

Timing Datasheet Report Options dialog box

Understanding Datasheet Reports

The datasheet report displays the external characteristics of the design. You can generate this report either from within Designer or within SmartTime Analyzer. It contains three tables:

• Pin Description

• DC Electrical Characteristics

• AC Electrical Characteristics

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Figure 146 · Datasheet Report

Pin Description

Provides the port name in the netlist, location on the package, type of port, and I/O technology assigned to it. Types can be input, output, inout, or clock. Clock ports are ports shown as "clock" in the Clock domain browser.

DC Electrical Characteristics

Provides the parameters of the different I/O technologies used in the design. The number of parameters displayed depends on the family for which you have created the design.

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Generating a Combinational Loop Report

AC Electrical Characteristics

Provides the timing properties of the ports of the design. For each clock, this section includes the maximum frequency. For each input, it includes the external setup, external hold, external recovery, and external removal for every clock where it applies. For each output, it includes the clock-to-out propagation time. This section also displays the input-to-output propagation time for combinational paths.

See Also

Generating a datasheet report

Timing Datasheet Report Options dialog box

Generating a Combinational Loop Report

The combinational loop report displays all loops found during initialization and reports pins associated with the loop(s), and the location where the loop is broken.

To generate a combinational loop report, from the Designer Tools menu, select Reports > Timing >

Combinational Loop. The report appears in a separate window.

You can also generate the combinational loop report from within SmartTime. From the Tools menu, choose

Reports > Combinational Loop.

The combinational loop report displays all loops found during initialization and reports pins associated with the loop(s), and the location where the loop is broken.

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134

Figure 147 · Combinational Loop Report

To view a graphical representation of the broken loop, open MultiView Navigator, find each pin and add them as a logical cone. For more information on how to find each pin and how to set up the logical cones, refer to What is a LogicalCone .

See Also

Generating a Combinational Loop Report

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Static Timing Analysis Versus Dynamic Simulation

Timing Concepts

Static Timing Analysis Versus Dynamic Simulation

Static timing analysis (STA) offers an efficient technique for identifying timing violations in your design and ensuring that it meets all your timing requirements. You can communicate timing requirements and timing exceptions to the system by setting timing constraints. A static timing analysis tool will then check and report setup and hold violations as well as violations on specific path requirements.

STA is particularly well suited for traditional synchronous designs. The main advantage of STA is that unlike dynamic simulation, it does not require input vectors. It covers all possible paths in the design and does all the above with relatively low run-time requirements. The major disadvantage of STA is that the STA tools do not automatically detect false paths in their algorithms.

Delay Models

The first step in timing analysis is the computation of single component delays. These components could be either a combinational gate or block or a single interconnect connecting two components.

Gates that are part of the library are pre-characterized with delays under different parameters, such as inputslew rates or capacitive loads. Traditional models provide delays between each pair of I/Os of the gate and between rising and falling edges.

The accuracy with which interconnect delays are computed depends on the design phase. These can be estimated using a simple Wire Load Model (WLM) at the pre-layout phase, or a more complex Resistor and

Capacitor (RC) tree solver at the post-layout phase.

Timing Path Types

Path delays are computed by adding delay values across a chain of gates and interconnects. SmartTime uses this information to check for timing violations. Traditionally, timing paths are presented by static timing analysis tools in four categories or "sets":

• Paths between sequential components internal to the design. SmartTime displays this category under the Register to Register set of each displayed clock domain.

• Paths that start at input ports and end at sequential components internal to the design. SmartTime displays this category under the External Setup and External Hold sets of each displayed clock domain.

• Paths that start at sequential components internal to the design and end at output ports. SmartTime displays this category under the Clock to Out set of each displayed clock domain.

• Paths that start at input ports and end at output ports. SmartTime displays this category under the

Input to Output set.

Maximum Clock Frequency

Generally, you set clock constraints on clocks for which you have a specified requirement. The absence of violations indicates that this clock will be able to run at least at the specified frequency. However, in the absence of such requirements, you may still be interested in computing the maximum frequency of a specific clock domain.

To obtain the maximum clock frequency, a static timing analysis tool computes the minimum period for each path between two sequential elements. To compute the minimum period, the tool evaluates the maximum data path delay and the minimum skew between the two elements, as well as the setup on the receiving sequential element. It also considers the polarity of each sequential element. The maximum frequency is the

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Setup Check

The setup and hold check ensures that the design functions as specified at the required clock frequency.

Setup check specifies when data is required to be present at the input of a sequential component in order for the clock to capture this data effectively into the component. Timing analyzers evaluate the setup check as a maximum timing budget allowed between adjacent sequential elements. For more details on how setup

check is processed, refer to Arrival time, required time, and slack .

See Also

Static timing analysis

Arrival time, required time, and slack

Arrival Time, Required Time, and Slack

You can use arrival time and required time to verify timing requirements in the presence of constraints.

Below is a simple example applied to verifying the clock requirement for setup between sequential elements in the design.

The arrival time represents the time at which the data arrives at the input of the receiving sequential element. In this example, the arrival time is considered from the setup launch edge at CK, taken as a time reference (instant zero). It follows the clock network along the blue line until the clock pin on FF1 (delay d1).

Then it continues along the data path always following the blue line until the data pin D on FF2. Therefore,

Arrival_Time

FF2:D

= d1 + d2

The required time represents when the data is required to be present at the same pin FF2:D. Assume in this example that in the presence of an FF with the same polarity, the capturing edge is simply one cycle following the launch edge. Using the period T provided to the tool through the clock constraint, the event gets propagated through the clock network along the red line until the clock pin of FF2 (delay d3). Taking into account FF2 setup (delay d4), this means that the clock constraint requires the data to be present d4 time before the capturing clock edge on FF2. Therefore, the required time is:

Required_Time

FF2:D

= T + d3 - d4

The slack is simply the difference between the required time and arrival time:

Slack

FF2:D

= Required_Time

FF2:D

- Arrival_TimeFF2:D

If the slack is negative, the path is violating the setup relationship between the two sequential elements.

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Figure 148 · Arrival Time and Required Time for Setup Check

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Timing Exceptions

Timing Exceptions

Design requirements are often imported using clock, input delay, and output delay constraints. By default, most static timing analyzers assume that all paths are sensitizable. They also assume that the design is operating in a single-cycle mode (that is, only one clock cycle is allowed for the data to transfer from one sequential stage to another).

If any paths in your design exhibit a different behavior, you must use timing exceptions to overwrite the default behavior. Timing exceptions include:

• Setting a false path constraint to identify non sensitizable paths that should not be included in the analysis or the optimization flow.

• Setting a maximum delay constraint on specific paths to relax or tighten the original clock constraint requirement on them.

• Setting a multicycle constraint to specify paths that by design will take more than one cycle to exchange data between sequential components.

SmartTime supports all these exceptions.

See Also

set_false_path (SDC)

Set False Path Constraint dialog box

set_max_delay (SDC)

Set Maximum Delay Constraint dialog box

set_multicycle_path (SDC)

Set Multicycle Constraint dialog box

Clock Skew

The clock skew between two different sequential components is the difference between the insertion delays from the clock source to the clock pins of these components. SmartTime calculates the arrival time at the clock pin of each sequential component. Then it subtracts the arrival time at the receiving component from the arrival time at the launching component to obtain an accurate clock skew.

Both setup and hold checks must account for clock skew. However, for setup check, SmartTime looks for the smallest skew. This skew is computed by using the maximum insertion delay to the launching sequential component and the shortest insertion delay to the receiving component.

For hold check, SmartTime looks for the largest skew. This skew is computed by using the shortest insertion delay to the launching sequential component and the largest insertion delay to the receiving component.

SmartTime makes this distinction automatically.

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Dialog Boxes

Add Path Analysis Set Dialog Box

Use this dialog box to specify a custom path analysis set.

Note: The Analysis menu is available only in Maximum or Minimum Delay Analysis view.

To open the Add Path Analysis Set dialog box (shown below) from the SmartTime Timing Analyzer, choose Actions > Analysis > Path Set.

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Figure 149 · Add Path Analysis Set Dialog Box

Name

Enter the name of your path set.

Trace from

Select whether you want to trace connected pins from Source to sink or from Sink to source. By default, the pins are traced Source to sink.

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Analysis Set Properties Dialog Box

Source Pins

Displays a list of available and valid source pins. You can select multiple pins. To select all source pins, click the Select All button beneath the Source Pins list.

Select All

Selects all the pins in the Source Pins list to include in the path analysis set.

Filter Source Pins

Enables you to specify thesource Pin Type and the Filter. The default pin type is Registers by pin name.

You can specify any string value for the Filter. If you change the pin type, the Source Pins shows the updated list of available source pins.

Sink Pins

Displays list of available and valid pins. You can select multiple pins. To select all source pins, click the

Select All button beneath the Sink Pins list.

Select All

Selects all the pins in the Sink Pins list to include in the path analysis set.

Filter Sink Pins

Enables you to specify thesink Pin Type and the Filter. The default pin type is Registers (by pin). You can specify any string value for the Filter. If you change the pin type, the Sink Pins shows the updated list of available sink pins.

Analysis Set Properties Dialog Box

Use this dialog box to view information about the user created set.

To open the Analysis Set Properties dialog box (shown below) from the Timing Analysis View, right-click any user-created set in the Domain Browser, and choose Properties from the shortcut menu.

Figure 150 · Analysis Set Properties Dialog Box

Name

Specifies the name of the user-created path set.

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Parent Set

Specifies the name of the parent path set to which the user-created path set belongs.

Creation filter

From

Specifies a list of source pins in the user-created path set.

Specifies a list of sink pins in the user-created path set.

See Also

Edit Filter Set Dialog Box

Use this dialog box to specify a filter.

To open the Edit Filter Set dialog box (shown below) from the SmartTime Timing Analyzer, select an existing filter set in the clock domain browser, and then choose Edit Set from the shortcut menu.

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Figure 151 · Edit Filter Set Dialog Box

Name

Specifies the name of the filtered set you want to edit.

Parent Set

Specifies the name of the filtered set to which the filter you want to edit belongs.

Creation filter

From - Specifies a list of source pins in the user-created path set.

To - Specifies a list of sink pins in the user-created path set.

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Select Source Pins for Clock Constraint Dialog Box

See Also

Constraints Editor, click the Browse button to the right of the Clock source field in the

Select Source Pins for Clock Constraint Dialog Box

Use this dialog box to find and choose the clock source from the list of available pins.

To open the Select Source Pins for the Clock Constraint dialog box (shown below) from the SmartTime

Create Clock

Constraint

Specifying clock constraints

Figure 152 · Choose the Clock Source Pin Dialog Box

Select a Pin

Displays all available pins.

Filter Available Objects

Explicit clock pins for the design is the default value. To identify any other pins in the design as clock pins, select Filter available objects - Pin Type as Explicit clocks, Potential clocks, Input ports, All Pins, All

Nets, Pins on clock network,or Nets in clock network. You can also use the Filter to filter the clock source pin name in the displayed list.

See Also

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Create Clock Constraint Dialog Box

Use this dialog box to enter a clock constraint setting.

It displays a typical clock waveform with its associated clock information. You can enter or modify this information, and save the final settings as long as the constraint information is consistent and defines the clock waveform completely. The tool displays errors and warnings if information is missing or incorrect.

To open the Create Clock Constraint dialog box (shown below) from the Actions menu, choose

Constraints > Clock.

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Figure 153 · Create Clock Constraint Dialog Box

Clock Source

Enables you to choose a pin from your design to use as the clock source.

The drop-down list is populated with all explicit clocks. You can also select the Browse button to access all

potential clocks. The Browse button displays the

Select Source Pins for Clock Constraint

Specifying clock constraint

Name

Specifies the name of the clock constraint. This field is required for virtual clocks when no clock source is provided.

T(zero) Label

Instant zero used as a common starting time to all clock constraints.

Period

When you edit the period, the tool automatically updates the frequency value.

The period must be a positive real number. Accuracy is up to 3 decimal places.

Frequency

When you edit the frequency, the tool automatically updates the period value.

The frequency must be a positive real number. Accuracy is up to 3 decimal places.

Starting Edge Selector

Enables you to switch between rising and falling edges and updates the clock waveform.

If the current setting of starting edge is rising, you can change the starting edge from rising to falling.

If the current setting of starting edge is falling, you can change the starting edge from falling to rising.

Duty Cycle

This number specifies the percentage of the overall period that the clock pulse is high.

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Create Generated Clock Constraint Dialog Box

The duty cycle must be a positive real number. Accuracy is up to 4 decimal places. Default value is 50%.

Offset

The offset must be a positive real number. Accuracy is up to 2 decimal places. Default value is 0.

Comment

Enables you to save a single line of text that describes the clock constraints purpose.

See Also

create_clock (SDC)

Clock definition

Create Generated Clock Constraint Dialog Box

Use this dialog box to specify generated clock constraint settings.

It displays a relationship between the clock source and its reference clock. You can enter or modify this information, and save the final settings as long as the constraint information is consistent. The tool displays errors and warnings if the information is missing or incorrect.

To open the Create Generated Clock Constraint dialog box (shown below) from the SmartTime

Constraints Editor, choose Actions > Constraints > Generated Clock.

Figure 154 · Create Generated Clock Constraint

Clock Pin

Enables you to choose a pin from your design to use as a generated clock source.

The drop-down list is populated with all unconstrained explicit clocks. You can also select the Browse button

to access all potential clocks and pins from the clock network. The Browse button displays the

Select

Generated Clock Source

create_generated_clock (SDC)

Clock Reference

Enables you to choose a pin from your design to use as a generated reference pin.

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Generated Clock Name

Specifies the name of the clock constraint. This field is required for virtual clocks when no clock source is provided.

Generated Frequency

The generated frequency is a factor of reference frequency defined with a multiplication element and/or a division element.

Generated Waveform

The generated waveform could be either the same as or inverted w.r.t. the reference waveform.

Comment

Enables you to save a single line of text that describes the generated clock constraints purpose.

See Also

Specifying generated clock constraint

Select Generated Clock Source

Customize Analysis View Dialog Box

Use this dialog box to customize the timing analysis grid.

To open the Customize Analysis View dialog box (shown below) from the SmartTime Timing Analyzer, choose View > Table: > Customize Analysis Grid.

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Figure 155 · Customize Analysis View Dialog Box

Available Fields

Displays a list of all the available fields in the timing analysis grid.

Show These Fields in This Order

Shows the list of fields you want to see in the timing analysis grid. Use Add or Remove to move selected items from Available fields to Show these fields in this order or vice versa. You can change the order in which these fields are displayed by using Move Up or Move Down.

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Manage Clock Domain Dialog Box

Restore Defaults

Resets all the options in the General panel to their default values.

Manage Clock Domain Dialog Box

Use this dialog box to specify the clock pins you want to see in the Expanded Path view.

To open the Manage Clock Domain dialog box (shown below) from the SmartTime Timing Analyzer, choose Actions > Analysis > Clock Domain.

Figure 156 · Manage Clock Domains Dialog Box

Available Clock Domains

Displays alphanumerically sorted list of available clock pins. The first clock pin is selected by default.

Show the Clock Domains in this Order

Shows the clock pins you want to see in the Expanded Path view. Use Add or Remove to move selected items from Available clock domains to Show the clock domains in this order or vice versa. You can change the order in which these clock pins are displayed by using Move Up or Move Down.

New Clock

Invokes the Choose the Clock Source Pin dialog box. The new clock gets added at the end of the Show the

clock domains in this order list box.

See Also

Managing clock domains

Select Generated Clock Source Dialog Box

Use this dialog box to find and choose the generated clock source from the list of available pins.

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To open the Select Generated Clock Source dialog box (shown below) from the SmartTime Constraints

Editor, open

dialog box and click the Browse button for the Clock

Pin.

Figure 157 · Select Generated Clock Source Dialog Box

Select a Pin

Displays all available pins.

Filter Available Objects

Explicit clock pins for the design is the default value. To identify any other pins in the design as the generated clock source pins, select Filter available objects - Pin Type as Explicit clocks, Potential

clocks, Input ports, All Pins, All Nets, Pins on clock network,or Nets in clock network . You can also use the Filter to filter the generated clock source pin name in the displayed list.

Select Generated Clock Reference Dialog Box

Use this dialog box to find and choose the generated clock reference pin from the list of available pins.

To open the Select Generated Clock Reference dialog box (shown below) from the SmartTime Constraints

Editor, open

dialog box and click the Browse button for the Clock

Reference.

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Select Source or Destination Pins for Constraint Dialog Box

Figure 158 · Select Generated Clock Reference Dialog Box

Select a Pin

Displays all available pins.

Filter Available Objects

To identify any other pins in the design as the generated master pin, select Filter available objects - Type as Clock Network. You can also use the Filter to filter the generated reference clock pin name in the displayed list.

Select Source or Destination Pins for Constraint Dialog Box

Use this dialog box to select pins or ports:

• By explicit list

• By keyword and wildcard

To open the Select Source or Destination Pins for Constraint dialog box from the SmartTime Constraints

Editor, choose Constraint > Constraint Name dialog box. Click the Browse button to select the source.

By Explicit List

This is the default. This mode stores the actual pin names. The following figure shows an example dialog box for Select Source Pins for Multicycle Constraint > by explicit list.

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Figure 159 · Select Source Pins for Multicycle (Specify pins by explicit list) Dialog Box

Available Objects

The list box displays the available valid objects. If you change the filter value, the list box shows the available objects based on the filter.

Use Add, Add All, Remove, Remove All to add or delete pins from the Assigned Pins list.

Filter Available Objects

Pin type – Specifies the filter on the available object. This can be by Explicit clocks, Potential clocks,

Input ports, All Pins, All Nets, Pins on clock network,or Nets in clock network

Filter

Specifies the filter based on which the Available Pins list shows the pin names. The default is *. You can specify any string value.

By Keyword and Wildcard

This mode stores the filter only. It does not store the actual pin names. The constraints created using this mode get exported with the SDC accessors (get_ports, get_pins, etc.).The following figure shows an example dialog box for Select Source Pins for Multicycle Constraint > by keyword and wildcard.

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Set False Path Constraint Dialog Box

Figure 160 · Select Source Pins for Multicycle (Specify pins by keyword and wildcard) Dialog Box

Pin Type

Specifies the filter on the available pins. This can be Registers by pin names, Registers by clock names,

Input Ports, or Output Ports. The default pin type is Registers by pin names.

Filter

Specifies the filter based on which the Available Pins list shows the pin names. The default is *. You can specify any string value.

Resulting Pins

Displays pins from the available pins based on the filter.

Set False Path Constraint Dialog Box

Use this dialog box to define specific timing paths as being false.

This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis. The path starting points are the input ports or register clock pins and path ending points are the register data pins or output ports. This constraint disables setup and hold checking for the specified paths.

Note: The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints.

To open the Set False Path Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > False Path.

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Figure 161 · Set False Path Constraint Dialog Box

From

Specifies the starting points for false path. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

Through

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

Specifies the ending points for false path. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Comment

Enables you to provide comments for this constraint.

See Also

first create a clock constraint . From the Actions menu, choose Constraint > Latency.

Set Clock Source Latency Dialog Box

Use this dialog box to define the delay between an external clock source and the definition pin of a clock within SmartTime.

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Set Clock Source Latency Dialog Box

To open the Set Clock Source Latency dialog box (shown below) from the Timing Analysis View, you must

Figure 162 · Set Clock Source Latency Dialog Box

Clock Port or Pin

Displays a list of clock ports or pins that do not already have a clock source latency specified. Select the clock port or pin for which you are specifying the clock source latency.

Late Rise

Specifies the largest possible latency, in nanoseconds, of the rising clock edge at the clock port or pin selected, with respect to its source. Negative values are acceptable, but may lead to overly optimistic analysis.

Early Rise

Specifies the smallest possible latency, in nanoseconds, of the rising clock edge at the clock port or pin selected, with respect to its source. Negative values are acceptable, but may lead to overly optimistic analysis.

Late Fall

Specifies the largest possible latency, in nanoseconds, of the falling clock edge at the clock port or pin selected, with respect to its source. Negative values are acceptable, but may lead to overly optimistic analysis.

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Early Fall

Specifies the smallest possible latency, in nanoseconds, of the falling clock edge at the clock port or pin selected, with respect to its source. Negative values are acceptable, but may lead to overly optimistic analysis.

Clock Edges

Select the latency for the rising and falling edges:

Falling same as rising: Specifies that Rising and Falling clock edges have the same latency.

Early same as late : Specifies that the clock source latency should be considered as a single value, not a range from "early" to ‘"late".

Comment

Enables you to save a single line of text that describes the clock source latency.

See Also

Specifying clock constraints

Set Constraint to Disable Timing Arcs Dialog Box

Use this dialog box to specify the timing arcs being disabled to fix the combinational loops in the design.

To open the Set Constraint to Disable Timing Arcs dialog box (shown below) from the Timing Analysis

View. From the Actions menu, choose Constraint > Disable Timing.

152

Figure 163 · Set Constraint to Disable Timing Arcs Dialog Box

Instance Name

Specifies the instance name for which the disable timing arc constraint will be created.

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Set Clock-to-Clock Uncertainty Constraint Dialog Box

Exclude All Timing Arcs in the Instance

This option enables you to exclude all timing arcs in the specified instance.

Specify Timing Arc to Exclude

This option enables you to specify the timing arc to exclude. In this case, you need to specify the from and to ports:

From Port

Specifies the starting point for the timing arc.

To Port

Specifies the ending point for the timing arc.

Comment

Enables you to save a single line of text that describes the disable timing arc.

See Also

Specifying Disable Timing Constraint

Set Clock-to-Clock Uncertainty Constraint Dialog Box

Use this dialog box to model tracking jitter between two clocks in your design.

To open the Set Clock-to-Clock Uncertainty Constraint dialog box (shown below), from the Actions menu, choose Constraint > Clock-to-Clock Uncertainty Constraint.

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154

Figure 164 · Clock-to-Clock Uncertainty Constraint Dialog Box

From Clock

Specifies clock name as the uncertainty source.

Edge

This option enables you to select if the clock-to-clock uncertainty applies to rising, falling, or both edges.

To Clock

Specifies clock name as the uncertainty destination.

Edge

This option enables you to select if the clock-to-clock uncertainty applies to rising, falling, or both edges.

Uncertainty

Enter the time in ns that represents the amount of variation between two clock edges.

Use Uncertainty For

This option enables you select whether the uncertainty constraint applies to setup, hold, or all checks.

Comment

Enables you to save a single line of text that describes this constraint.

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Set Input Delay Constraint Dialog Box

See Also

Specifying Disable Timing Constraint

Set Input Delay Constraint Dialog Box

Use this dialog box to apply input delay constraints or external setup/hold constraints. This constraint defines the arrival time of an input relative to a clock.

To open the Set Input Delay Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > Input Delay.

External Setup/hold

Figure 165 · Set Input Delay Constraint (Show by: External Setup/Hold) Dialog Box

Input Port

Specifies a list of input ports in the current design to which the constraint is assigned. You can apply more than one port.

Clock Port

Specifies the clock reference to which the specified External Setup/Hold is related.

External Hold

Specifies the external hold time requirement for the specified input ports.

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Input Delay

External Setup

Specifies the external setup time requirement for the specified input ports.

Comment

Enables you to provide comments for this constraint.

156

Figure 166 · Set Input Delay Constraint (Show by: Input Delay) Dialog Box

Input Port

Specifies a list of input ports in the current design to which the constraint is assigned. You can apply more than one port.

Clock Port

Specifies the clock reference to which the specified input delay is related.

Clock edge

Indicates the launching edge of the clock.

Use max delay for both min and max

Specifies that the minimum input delay uses the same value as the maximum input delay.

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Set Maximum Delay Constraint Dialog Box

Maximum Delay

Specifies that the delay refers to the longest path arriving at the specified input.

Minimum Delay

Specifies that the delay refers to the shortest path arriving at the specified input.

Comment

Enables you to provide comments for this constraint.

Set Maximum Delay Constraint Dialog Box

Use this dialog box to specify the required maximum delay for timing paths in the current design.

SmartTime automatically derives the individual maximum delay targets from clock waveforms and port input or output delays. So the maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multiple cycle path constraint.

To open the Set Maximum Delay Constraint dialog box (shown below) from the SmartTime Constraints

Editor, choose Actions > Constraints > Max Delay.

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158

Figure 167 · Set Maximum Delay Constraint Dialog Box

Maximum Delay

Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.

If the path starting point is on a sequential device, SmartTime includes clock skew in the computed delay.

If the path starting point has an input delay specified, SmartTime adds that delay value to the path delay.

If the path ending point is on a sequential device, SmartTime includes clock skew and library setup time in the computed delay.

If the ending point has an output delay specified, SmartTime adds that delay to the path delay.

From

Specifies the starting points for max delay constraint. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

Through

Specifies the through points for the multiple cycle constraint.

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Set Minimum Delay Constraint Dialog Box

Specifies the ending points for maximum delay constraint. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Comment

Enables you to provide comments for this constraint.

See Also

Specifying maximum delay constraint

Set Minimum Delay Constraint Dialog Box

Use this dialog box to specify the required minimum delay for timing paths in the current design.

SmartTime automatically derives the individual minimum delay targets from clock waveforms and port input or output delays. So the minimum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multiple cycle path constraint.

To open the Set Minimum Delay Constraint dialog box (shown below) from the SmartTime Constraints

Editor, choose Actions > Constraints > Min Delay.

Figure 168 · Set Minimum Delay Constraint Dialog Box

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Minimum Delay

Specifies a floating point number in nanoseconds that represents the required minimum delay value for specified paths.

If the path starting point is on a sequential device, SmartTime includes clock skew in the computed delay.

If the path starting point has an input delay specified, SmartTime adds that delay value to the path delay.

If the path ending point is on a sequential device, SmartTime includes clock skew and library setup time in the computed delay.

If the ending point has an output delay specified, SmartTime adds that delay to the path delay.

From

Specifies the starting points for minimum delay constraint. A valid timing starting point is a clock, a primary input, an input port, or a clock pin of a sequential cell.

Through

Specifies the through points for the multiple cycle constraint.

Specifies the ending points for minimum delay constraint. A valid timing ending point is a clock, a primary output, an input port, or a data pin of a sequential cell.

Comment

Enables you to provide comments for this constraint.

See Also

Specifying minimum delay constraint

Set Multicycle Constraint Dialog Box

Use this dialog box to specify the paths that take multiple clock cycles in the current design.

Setting the multiple-cycle paths constraint overrides the single-cycle timing relationships between sequential elements by specifying the number of cycles that the data path must have for setup or hold checks.

Note: The false path information always takes precedence over multiple cycle path information. A specific maximum delay constraint overrides a general multiple cycle path constraint.

To open the Set Multicycle Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraint> Multicycle.

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Set Multicycle Constraint Dialog Box

Figure 169 · Set Multicycle Constraint Dialog Box

Setup Path Multiplier

Specifies an integer value that represents a number of cycles the data path must have for a setup check. No hold check will be performed.

From

Specifies the starting points for the multiple cycle constraint. A valid timing starting point is a clock, a primary input, an inout port, or the clock pin of a sequential cell.

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Through

Specifies the through points for the multiple cycle constraint.

Specifies the ending points for the multiple cycle constraint. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Comment

Enables you to provide comments for this constraint.

When you select the Setup and Hold Checks option, an additional field appears in this dialog box: Hold

Path Multiplier.

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Set Multicycle Constraint Dialog Box

Figure 170 · Set Multicycle Constraint Dialog Box with Setup and Hold Checks Selected

Hold Path Multiplier

Specifies an integer value that represents a number of cycles the data path must have for a hold check, starting from one cycle before the setup check edge.

See Also

Specifying multicycle constraint

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Set Output Delay Constraint Dialog Box

Use this dialog box to apply output delay constraints. This constraint defines the output delay of an output relative to a clock.

To open the Set Output Delay Constraint dialog box (shown below) from the SmartTime Constraints

Editor, choose Actions > Constraints > Output Delay.

Clock-to-Output

164

Figure 171 · Set Output Delay (Show By: Clock-to-Output) Dialog Box

Output Port

Specifies a list of output ports in the current design to which the constraint is assigned. You can apply more than one port.

Clock Port

Specifies the clock reference to which the specified Clock-to-Output is related.

Clock edge

Indicates the clock edge of the launched edge.

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Set Output Delay Constraint Dialog Box

Maximum Delay

Specifies the delay for the longest path from the clock port to the output port. This constraint includes the combinational path delay from output of the launched edge to the output port.

Minimum Delay

Specifies the delay for the shortest path from the clock port to the output port. This constraint includes the combinational path delay from output of the launched edge to the output port.

Comment

Enables you to provide comments for this constraint.

Output Delay

Figure 172 · Set Output Delay (Show By: Output Delay) Dialog Box

Output Port

Specifies a list of output ports in the current design to which the constraint is assigned. You can apply more than one port.

Clock Port

Specifies the clock reference to which the specified output delay is related.

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Clock edge

Indicates the launching edge of the clock.

Maximum Delay

Specifies the delay for the longest path from the specified output to the captured edge. This represents a combinational path delay to a register outside the current design plus the library setup time.

Minimum Delay

Specifies the delay for the shortest path from the specified output to the captured edge. This represents a combinational path delay to a register outside the current design plus the library hold time.

Comment

Enables you to provide comments for this constraint.

SmartTime Options Dialog Box

Use this dialog box to specify the SmartTime options to perform timing analysis.

This interface includes the following categories:

• General

• Analysis View

• Advanced

To open the SmartTime Options dialog box (shown below) from the SmartTime tool, choose Tools >

Options.

General

166

Figure 173 · SmartTime Options - General Dialog Box

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SmartTime Options Dialog Box

Operating Conditions

Allows you to perform maximum or minimum delay analysis based on the Best, Typical, or Worst case. By default, maximum delay analysis is based on WORST case and minimum delay analysis is based on BEST case.

Clock Domains

• Include inter-clock domains in calculations for timing analysis: Enables you to specify if

SmartTime must use inter-clock domains in calculations for timing analysis. By default, this option is unchecked.

• Enable recovery and removal checks: Enables SmartTime to check removal and recovery time on asynchronous signals. Additional sets are created in each clock domain in Analysis View to report the corresponding paths.

Restore Defaults

Resets all the options in the General panel to their default values.

Analysis View

Figure 174 · SmartTime Options - Analysis View Dialog Box

Display of Paths

Limits the number of paths shown in a path set for timing analysis. The default value is 100. You must specify a number greater than 1.

Filter the paths by slack value

Specifies the slack range between minimum slack and maximum slack. This option is unchecked by default.

Show clock network details in expanded path

Displays the clock network details as well as the data path details in the Expanded Path views.

Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime displays. The default number of parallel paths is 1.

Restore Defaults

Resets all the options in the Analysis View panel to their default values.

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Advanced

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Figure 175 · SmartTime Options - Advanced Dialog Box

Special Situations

Enables you to specify if you need to use loopback in bi-directional buffers (bibufs) and/or break paths at asynchronous pins.

Scenarios

Enables you to select the scenario to use for timing analysis and for timing-driven place-and-route.

Restore Defaults

Resets all the options in the Analysis View panel to their default values.

Store Filter as Analysis Set Dialog Box

Use this dialog box to specify a filter.

To open the Store Filter as Analysis Set dialog box (shown below) from the SmartTime Timing Analyzer, select a path and click the Store Filter button in the Analysis View Filter.

168

Figure 176 · Store Filter as Analysis Set Dialog Box

Name

Specifies the name of the filtered set.

See Also

Performing a bottleneck analysis

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Timing Bottleneck Analysis Options Dialog Box

Timing Bottleneck Analysis Options Dialog Box

Use this dialog box to customize the timing bottleneck report.

You can set report bottleneck options for the following categories:

•

General pane

•

Bottleneck pane

•

Sets pane

To open the Timing Bottleneck Analysis Options dialog box (shown below) from the SmartTime tool, choose Tools > Timing Analyzer > Bottleneck Analysis.

General Pane

Figure 177 · Timing Bottleneck Report - General Pane Dialog Box

Analysis

Lets you specify what type of analysis will be reported in the report. By default, the report includes

Maximum Delay Analysis.

Slack

Lets you specify whether the reported paths will be filtered by threshold, and if so what will be the maximum slack to report. By default the paths are filtered by slack, and the slack threshold is 0.

Restore Defaults

Resets all the options in the General pane to their default values.

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Bottleneck Pane

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Figure 178 · Timing Bottleneck Report - Bottleneck Pane Dialog Box

Bottleneck Options

Cost Type: Select the cost type that SmartTime will include in the bottleneck report. By default, path count is selected.

Limit the number of reported paths per section to: Specify the maximum number of paths per set type that SmartTime will include per section in the report. The default maximum number of paths reported is

100.

Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime will include in the report. Only cells that lie on these violating paths are reported. The default number of parallel paths is 1.

Limit the number of reported instances: Specify the maximum number of cells that SmartTime will include per section in the report. The default number of cells is 10.

Restore Defaults

Resets all the options in the Bottleneck panel to their default values.

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Timing Bottleneck Analysis Options Dialog Box

Sets Pane

Value

Figure 179 · Timing Bottleneck Report - Sets Pane Dialog Box

This pane has three mutually exclusive options:

• Entire Design

• Clock Domain

• Use existing user set

Entire Design: Select this option to display the bottleneck information for the entire design.

Clock Domain: Select this option to display the bottleneck information for the selected clock domain. You can specify the following options:

• Clock: Allows pruning based on a given clock domains. Only cells that lie on these violating paths are reported.

• Type: This option can only be used in conjunction with -clock. The acceptable values are:

Description

Asynchronous to Register

Paths between registers in the design

Paths from asynchronous pins to registers

External Recovery

External Removal

Paths from registers to asynchronous pins

The set of paths from inputs to asynchronous pins

External Setup

External Hold

Clock to Output

Paths from input ports to register

Paths from registers to output ports

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Use existing user set: Displays the bottleneck information for the existing user set selected. Only paths that lie within the name set are will be considered towards the bottleneck report.

Filter: Allows you to filter the bottleneck report by the following options:

• From: Reports only cells that lie on violating paths that start at locations specified by this option.

• To: Reports only cells that lie on violating paths that end at locations specified by this option.

Filter defaults to all outputs.

Restore Defaults

Resets all the options in the Paths panel to their default values.

See Also

Timing Bottleneck Report Options Dialog Box

Use this dialog box to customize the timing bottleneck report.

You can set report bottleneck options for the following categories:

•

General pane

•

Bottleneck pane

•

Sets pane

To open the Timing Bottleneck Report Options dialog box (shown below) from the SmartTime tool, choose Tools > Report > Report Bottlenecks.

General Pane

172

Figure 180 · Timing Bottleneck Report - General Pane Dialog Box

Format

Specifies whether or not the report will be exported as a Comma Separated Value (CSV) file or a plain text file. By default, the Plain Text option is selected.

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Timing Bottleneck Report Options Dialog Box

Analysis

Lets you specify what type of analysis will be reported in the report. By default, the report includes

Maximum Delay Analysis.

Slack

Restore Defaults

Resets all the options in the General pane to their default values.

Bottleneck Pane

Figure 181 · Timing Bottleneck Report - Bottleneck Pane Dialog Box

Bottleneck Options

Cost Type: Select the cost type that SmartTime will include in the bottleneck report. By default, path count is selected.

100.

Limit the number of reported instances: Specify the maximum number of cells that SmartTime will include per section in the report. The default number of cells is 10.

Restore Defaults

Resets all the options in the Bottleneck panel to their default values.

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Sets Pane

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Value

Figure 182 · Timing Bottleneck Report - Sets Pane Dialog Box

This pane has three mutually exclusive options:

• Entire Design

• Clock Domain

• Use existing user set

Entire Design: Select this option to display the bottleneck information for the entire design.

Clock Domain: Select this option to display the bottleneck information for the selected clock domain. You can specify the following options:

• Clock: Allows pruning based on a given clock domains. Only cells that lie on these violating paths are reported.

• Type: This option can only be used in conjunction with -clock. The acceptable values are:

Description

Asynchronous to Register

External Recovery

External Removal

External Setup

External Hold

Paths from asynchronous pins to registers

Paths from registers to asynchronous pins

The set of paths from inputs to asynchronous pins

Paths from input ports to register

Clock to Output Paths from registers to output ports

Use existing user set: Displays the bottleneck information for the existing user set selected. Only paths that lie within the name set are will be considered towards the bottleneck report.

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Timing Datasheet Report Options Dialog Box

Filter: Allows you to filter the bottleneck report by the following options:

• From: Reports only cells that lie on violating paths that start at locations specified by this option.

• To: Reports only cells that lie on violating paths that end at locations specified by this option.

Filter defaults to all outputs.

Restore Defaults

Resets all the options in the Paths panel to their default values.

See Also

Generating a bottleneck report

Understanding bottleneck report

report (bottleneck) using SmartTime

Timing Datasheet Report Options Dialog Box

Use this dialog box to select the output format for your timing datasheet report.

To open the Timing Datasheet Report Options dialog box (shown below) from the SmartTime tool, choose

Tools > Report > Report Datasheet.

You can generate your report in one of two formats:

Plain Text

Select this option to save your report to disk in plain ASCII text format.

Comma Separated Values

Select this option to save your report to disk in comma-separated value format (.CSV) format, which you can import into a spreadsheet

Restore Defaults

Resets the option to its default value, which is Plain Text.

See Also

Generating a datasheet report

Understanding datasheet reports

report (Datasheet) using SmartTime

Timing Report Options Dialog Box

Use this dialog box to customize the timing report.

You can set report options for the following categories:

•

•

•

•

To open the Timing Report Options dialog box (shown below) from the SmartTime tool, choose Tools >

Report > Report Paths.

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General

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176

Figure 183 · Timing Report Options - General Dialog Box

Format

Specifies whether or not the report will be exported as a Comma Separated Value (CSV) file or a plain text file. By default, the Plain Text option is selected.

Summary

Specifies whether or not the summary section will be included in the report. By default, this option is selected.

Analysis

Specifies the type of analysis to be included in the timing report. It can be either a Maximum Delay Analysis report or Minimum Delay Analysis report. By default, the Maximum Delay Analysis report is included in the timing report.

Slack

Specifies whether the reported paths will be filtered by threshold, and if so what will be the maximum slack to report. By default, the paths are not filtered by slack.

Restore Defaults

Resets all the options in the General panel to their default values.

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Paths

Timing Report Options Dialog Box

Figure 184 · Timing Report Options - Paths Dialog Box

Display of Paths

Include detailed path information in this report: Check this box to include the detailed path information in the timing report.

Limit the number of reported paths per section to: Specify the maximum number of paths that

SmartTime will include per section in the report.

Limit the number of expanded paths per section to: Specify the maximum number of expanded paths that SmartTime will include per section in the report.

Limit the number of parallel paths in expanded path to: For each expanded path, specify the maximum number of parallel paths that SmartTime will include in the report. The default number of parallel paths is 1.

Restore Defaults

Resets all the options in the Paths panel to their default values.

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Sets

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Figure 185 · Timing Report Options - Sets Dialog Box

Display of Sets

Specifies whether or not the user sets will be included in the timing report.

User sets are either filters that you have created and stored on the default paths sets (Register to Register,

Inputs to Register, etc.) or Pin to Pin user sets. By default, the paths for these sets are not reported.

In addition, specify whether the Inputs to Output sets will be included in the report. By default, the Input to

Output sets are reported.

Restore Defaults

Resets both options in the Sets panel to their default values.

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Timing Violations Report Options Dialog Box

Clock Domains

Figure 186 · Timing Report Options - Clock Domains Dialog Box

Display of Clock Domains

Lets you specify what clock domains will be included in the report. By default, the current clock domains used by the timing engine will be reported.

Include Clock Domains

Enables you to include or exclude clock domains in the report. Click the checkbox to include clock domains.

Limit reporting on clock domains to specified domains

Lets you include one or more of the clock domain names in the box, or include additional clock domain names using Select Domains.

Restore Defaults

Resets all options in the Clock Domains panel to their default values.

See Also

Generating timing report

Understanding timing report

report (Timing) using SmartTime

Timing Violations Report Options Dialog Box

Use this dialog box to customize the timing violation report.

You can set report violation options for the following categories:

• General

• Paths

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General

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To open the Timing Report Options dialog box (shown below) from the SmartTime tool, choose Tools >

Report > Report Violations.

180

Figure 187 · Timing Violations Report - General Dialog Box

Format

Specifies whether or not the report will be exported as a Comma Separated Value (CSV) file or a plain text file. By default, the Plain Text option is selected.

Analysis

Lets you specify what type of analysis will be reported in the report. By default, the report includes Maximum

Delay Analysis.

Slack

Restore Defaults

Resets all the options in the General panel to their default values.

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Timing Violations Report Options Dialog Box

Paths

Figure 188 · Timing Violations Report - Paths Dialog Box

Display of paths

Limit the number of reported paths: Check this box to limit the number of paths in the report. By default, the number of paths is limited.

Limit the number of reported paths per section to: Specify the maximum number of paths that

SmartTime will include per section in the report. The default maximum number of paths reported is 100.

Limit the number of expanded paths per section to: Specify the maximum number of expanded paths that SmartTime will include per section in the report. The default number of expanded paths is 0.

Restore Defaults

Resets all the options in the Paths panel to their default values.

See Also

Generating timing violation report

Understanding timing violation report

report (Timing violations) using SmartTime

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Menus, Tools, and Shortcut Keys

File Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Icon Shortcut Function

Commit CTRL +

Saves changes to the working design for this Designer session only. Note: To save changes to disk, you

must also save your file in Designer.

Displays the active design in a Preview window Print

Preview

Exit

CTRL +

Displays the Print dialog box from which you can print your active design

Closes SmartTime

Edit Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Icon Shortcut Function

Undo

Redo

Cut

Copy

CTRL + Z Reverses your last action

CTRL + Y Reverses the action of your last Undo command

CTRL + X Removes the selection from your design

CTRL +

Copies the selection to the Clipboard

Paste

Modify

CTRL + V Pastes the selection from the Clipboard

Displays appropriate dialog box to edit the current constraint

Delete

Select All

Del Deletes the selected constraint

CTRL + A Selects all logic in your design

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View Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Icon Shortcut Function

Recalculates all the generated values Recalculate

All

Table: Name

Toolbars >

Status Bar

Scenarios

Provides option for customizing the table in the Timing

Analysis View

Hides or displays groups of toolbar buttons

Shows or hides the status bar at the bottom of the window

Shows or hides the scenarios panel

View > Table

Command Icon Shortcut

Customize

Current Table

Function

Enables you to select columns and the order of the columns for the Paths List in the Timing Analysis

View

View > Toolbars

Command Icon Shortcut

Standard

Constraints

Analysis

Function

Shows or hides the standard toolbar

Show or hides the constraints toolbar

Shows or hides the analysis toolbar

View Menu

Actions Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Icon Shortcut Function

Constraints > Provides options to create new constraints

Analysis > Provides options to perform timing analysis

Actions > Constraints

Command Icon Shortcut Function

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Command

Clock

Generated Clock

Input Delay

Output Delay

Max Delay

Min Delay

False Path

Multicycle

Latency

Disable Timing

Clock to Clock

Uncertainty

Icon Shortcut Function

Displays the Create Clock Constraint dialog box

Displays the Create Generated Clock

Constraint dialog box

Displays the Set Input Delay Constraint dialog box

Displays the Set Output Delay Constraint dialog box

Displays the Set Maximum Delay Constraint dialog box

Displays the Set Minimum Delay Constraint dialog box

Displays the Set False Path Constraint dialog box

Displays the Set Mulitcycle Constraint dialog box

Displays the Set Clock Source Latency dialog box

Displays the Set Constraint to Disable Timing

Arcs dialog box

Displays the Set Clock-to-Clock Uncertainty dialog box

Actions > Analysis

Command Icon Shortcut

Clock Domain

Function

Displays Manage Clock Domain dialog box

Path Set Displays Add Path Analysis Set dialog box

Tools Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Icon Shortcut Function

Constraints

Editor >

Provides options for constraints scenarios

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Command

Constraint

Wizard >

Timing Analyzer

Icon Shortcut Function

Opens the Constraint Wizard for creating clock and I/O constraints

Provides options for timing analysis

Constraint

Checker

Reports >

Options

Verifies if all timing constraints are valid

Provides options to generate reports

Displays the SmartTime Options dialog box

Tools > Constraints Editor

Command Icon Shortcut

1. Primary Scenario (and all other available scenarios)

Scenarios

Function

Displays the primary set of timing constraints for the selected scenario

Opens the scenario panel, which lists all available scenarios

New scenario Creates a new scenario

Tools > Timing Analyzer

Command Icon Shortcut

Maximum Delay

Analysis

Function

Displays the Maximum Delay Analysis

View

Displays the Minimum Delay Analysis View Minimum Delay Analysis

Bottleneck Analysis Displays the Bottleneck Analysis View

Tools > Reports

Command Icon Shortcut

Report Paths

Function

Displays the Timing Report Options dialog box

Report Violations

Report Datasheet

Displays the Timing Violations Report

Options dialog box

Displays the Datasheet Report Options dialog box

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Tools Menu

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Command

Report Constraints

Coverage

Report Combinational

Loop

Icon Shortcut Function

Displays the Constraints Coverage Report

Options dialog box

Displays the Combinational Loop report

Window Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Function

New Window Opens another window for the currently active tool Note: Use these

windows to view different parts of the design at the same time.

Cascade Arranges windows so you can see the title bar of each window

Tile Horizontally Arranges windows side-by-side in a horizontal pattern

Tile Vertically Arranges windows side-by-side in a vertical pattern

Minimize All

Windows

Minimizes all active windows

Arrange Icons Arranges minimized windows left-to-right across the bottom of the

Tool window

Close All

Windows

Closes all tool views

Help Menu

This menu is available in both Timing Constraint Editor View and Timing Analysis View.

Command Function

Help Topics Displays the first Help topic for the SmartTime tool

Displays the SmartTime User's Guide SmartTime

User's Guide

About

SmartTime

Data Change

History

Displays the current version number and copyright information for the

SmartTime tool

Displays features and enhancements, bug fixes and known issues for the current software release that may impact timing data of the current design

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SmartTime Toolbar

SmartTime Toolbar

The SmartTime toolbar contains commands for constraining or analyzing designs. Tool tips are available for each button.

Table 2 · SmartTime Toolbar

Icon Description

Commits the changes

Prints the contents of the constraints editor

Copies data to the clipboard

Pastes data from the clipboard

Modifies the selected object from the constraints editor

Deletes the selected object from the constraints editor

Undoes previous changes

Redoes previous changes

Opens the maximum delay analysis view

Opens the minimum delay analysis view

Opens the manage clock domains manager

Opens the path set manager

Recalculates all

Opens the constraints editor

Opens the add clock constraint dialog box

Opens the add generated clock constraint dialog box

Opens the set input delay clock constraint dialog box

Opens the set output delay clock constraint dialog box

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Icon Description

Opens the set false path constraint dialog box

Opens the set maximum delay constraint dialog box

Opens the set minimum delay constraint dialog box

Opens the set multicycle constraint dialog box

Opens the set clock source latency dialog box

Opens the set constraint to disable timing arcs dialog box

Opens the set clock-to-clock uncertainty constraint dialog box

Checks timing constraints

Opens the constraint wizard

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SmartTime Toolbar

Data Change History - SmartTime

The data change history lists features, enhancements and bug fixes for the current software release that may impact timing data of the current design.

To generate a data change history, from the Help menu, choose Data Change History. This opens a data change history in text format.

Figure 189 · SmartTime Data Change History Report

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Tcl Commands

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all_registers

Tcl command; returns an object representing register pins or cells in the current scenario based on the given parameters. all_registers [-clock

clock_name

]

[-async_pins][-output_pins][-data_pins][-clock_pins]

Arguments

-clock

clock_name

Specifies the name of the clock domain to which the registers belong. If no clock is specified, all registers in the design will be targeted.

-async_pins

Lists all register pins that are async pins for the specified clock (or all registers asynchronous pins in the design).

-output_pins

Lists all register pins that are output pins for the specified clock (or all registers output pins in the design).

-data_pins

Lists all register pins that are data pins for the specified clock (or all registers data pins in the design).

-clock_pins

Lists all register pins that are data pins for the specified clock (or all registers clock pins in the design).

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Exceptions

You can only use this command as part of a –from, -to, or –through argument in the following Tcl

commands: set_min_delay ,

set_max_delay ,

, and set_false_path .

Examples

set_max_delay 2.000 -from { ff_m:CLK ff_s2:CLK } -to [all_registers -clock_pins -clock { ff_m:Q }]

See Also

Tcl documentation conventions

Designer Tcl Command Reference

check_timing_constraints

Tcl command; checks all timing constraints in the current timing scenario for validity. check_timing_constraints

Arguments

None

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clone_scenario

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

check_timing_constraints

See Also

Tcl documentation conventions

Designer Tcl Command Reference

clone_scenario

Tcl command; creates a new timing scenario by duplicating an existing one. You must provide a unique name (that is, it cannot already be used by another timing scenario). clone_scenario

name

-source

origin

Arguments

name

Specifies the name of the new timing scenario to create.

-source

origin

Specifies the source of the timing scenario to clone (copy). The source must be a valid, existing timing scenario.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command creates a timing scenario with the specified name, which includes a copy of all constraints in the original scenario (specified with the -source parameter). The new scenario is then added to the list of scenarios.

Example

clone_scenario scenario_A –source {Primary}

See Also

create_scenario

delete_scenario

Tcl documentation conventions

Designer Tcl Command Reference

create_clock

Tcl command; creates a clock constraint on the specified ports/pins, or a virtual clock if no source other than a name is specified. create_clock -period

period_value

[-name

clock_name

]

[-waveform>

edge_list

][

source_objects

]

Arguments

-period

period_value

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Specifies the clock period in nanoseconds. The value you specify is the minimum time over which the clock waveform repeats. The period_value must be greater than zero.

-name

clock_name

Specifies the name of the clock constraint. You must specify either a clock name or a source.

-waveform

edge_list

Specifies the rise and fall times of the clock waveform in ns over a complete clock period. There must be exactly two transitions in the list, a rising transition followed by a falling transition. You can define a clock starting with a falling edge by providing an edge list where fall time is less than rise time. If you do not specify -waveform option, the tool creates a default waveform, with a rising edge at instant 0.0 ns and a falling edge at instant (period_value/2)ns.

source_objects

Specifies the source of the clock constraint. The source can be ports, pins, or nets in the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing one. You must specify either a source or a clock name.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Creates a clock in the current design at the declared source and defines its period and waveform. The static timing analysis tool uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source.

The clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Examples

The following example creates two clocks on ports CK1 and CK2 with a period of 6, a rising edge at 0, and a falling edge at 3: create_clock -name {my_user_clock} -period 6 CK1 create_clock -name {my_other_user_clock} –period 6 –waveform {0 3} {CK2}

The following example creates a clock on port CK3 with a period of 7, a rising edge at 2, and a falling edge at 4: create_clock –period 7 –waveform {2 4} [get_ports {CK3}]

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

create_generated_clock

Tcl command; creates an internally generated clock constraint on the ports/pins and defines its characteristics. create_generated_clock [-name

name

] -source

reference_pin

[-divide_by

divide_factor

] [multiply_by

multiply_factor

] [-invert]

source

Arguments

-name

name

Specifies the name of the clock constraint.

-source

reference_pin

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create_scenario

Specifies the reference pin in the design from which the clock waveform is to be derived.

-divide_by

divide_factor

Specifies the frequency division factor. For instance if the divide_factor is equal to 2, the generated clock period is twice the reference clock period.

-multiply_by

multiply_factor

Specifies the frequency multiplication factor. For instance if the multiply_factor is equal to 2, the generated clock period is half the reference clock period.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock. source

Specifies the source of the clock constraint on internal pins of the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing clock. Only one source is accepted.

Wildcards are accepted as long as the resolution shows one pin.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.

The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Examples

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK. create_generated_clock -name {my_user_clock} –divide_by 2 –source [get_ports

{CLK}] U1/reg1:Q

The following example creates a generated clock at the primary output of myPLL with a period ¾ of the period at the reference pin clk. create_generated_clock –divide_by 3 –multiply_by 4 -source clk [get_pins {myPLL:CLK1}]

See Also

command as part of a –from, -to, or –through argument in the following Tcl commands: set_max delay ,

Tcl Command Documentation Conventions

Designer Tcl Command Reference

create_scenario

Tcl command; creates a new timing scenario with the specified name. You must provide a unique name

(that is, it cannot already be used by another timing scenario). create_scenario

name

Arguments

name

Specifies the name of the new timing scenario.

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Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

A timing scenario is a set of timing constraints used with a design. Scenarios enable you to easily refine the set of timing constraints used for Timing-Driven Place-and-Route, so as to achieve timing closure more rapidly.

This command creates an empty timing scenario with the specified name and adds it to the list of scenarios.

Example

create_scenario scenario_A

See Also

clone_scenario

Tcl Command Documentation Conventions

Designer Tcl Command Reference

delete_scenario

Tcl command; deletes the specified timing scenario. delete_scenario

name

Arguments

name

Specifies the name of the timing scenario to delete.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command deletes the specified timing scenario and all the constraints it contains.

Exceptions

• At least one timing scenario must always be available. If the current scenario is the only one that exists, you cannot delete it.

• Scenarios that are linked to the timing analysis or layout cannot be deleted.

Example

delete_scenario scenario_A

See Also

create_scenario

Tcl Command Documentation Conventions

Designer Tcl Command Reference

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get_cells

get_cells

Tcl command; returns an object representing the cells (instances) that match those specified in the pattern argument. get_cells pattern

Arguments

pattern

Specifies the pattern to match the instances to return. For example, "get_cells U18*" returns all instances starting with the characters "U18", where “*” is a wildcard that represents any character string.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command returns a collection of instances matching the pattern you specify. You can only use this

• If this command is used as a –from argument in either the set maximum ( set_max_delay ), or set

, and set_false_path .

Examples

set_max_delay 2 -from [get_cells {reg*}] -to [get_ports {out}] set_false_path –through [get_cells {Rblock/muxA}]

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

get_clocks

Tcl command; returns an object representing the clock(s) that match those specified in the pattern argument in the current timing scenario. get_clocks

pattern

Arguments

pattern

Specifies the pattern to use to match the clocks set in SmartTime or Timer.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

minimum delay ( set_min_delay

), false path ( set_false_path ), and multicycle constraints

( set_multicycle_path ), the clock pins of all the registers related to this clock are used as path start

points.

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• If this command is used as a –to argument in either the set maximum ( set_max_delay ), or set

minimum delay ( set_min_delay

), false path ( set_false_path ), and multicycle constraints

( set_multicycle_path ), the synchronous pins of all the registers related to this clock are used as path

endpoints.

Example

set_max_delay -from [get_ports datal] -to \

[get_clocks ck1]

See Also

command as source objects in create clock ( create_clock ) or create generated clock

Tcl Command Documentation Conventions

Designer Tcl Command Reference

get_current_scenario

Tcl command; returns the name of the current timing scenario. get_current_scenario

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

get_current_scenario

See Also

set_current_scenario

Tcl documentation conventions

Designer Tcl Command Reference

get_nets

Tcl command; returns an object representing the nets that match those specified in the pattern argument. get_nets

pattern

Arguments

pattern

Specifies the pattern to match the names of the nets to return. For example, "get_nets N_255*" returns all nets starting with the characters "N_255", where “*” is a wildcard that represents any character string.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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get_pins

Description

This command returns a collection of nets matching the pattern you specify. You can only use this

( create_generated_clock ) constraints and as -through arguments in the set false path, set minimum

delay, set maximum delay, and set multicycle path constraints.

Examples

set_max_delay 2 -from [get_ports RDATA1] -through [get_nets {net_chkp1 net_chkqi}] set_false_path –through [get_nets {Tblk/rm/n*}] create_clock -name mainCLK -period 2.5 [get_nets {cknet}]

See Also

Tcl documentation conventions

Designer Tcl Command Reference

get_pins

Tcl command; returns an object representing the pin(s) that match those specified in the pattern argument. get_pins

pattern

Arguments

pattern

Specifies the pattern to match the pins to return. For example, "get_pins clock_gen*" returns all pins starting with the characters "clock_gen", where “*” is a wildcard that represents any character string.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Example

create_clock -period 10 [get_pins clock_gen/reg2:Q]

See Also

Tcl documentation conventions

Designer Tcl Command Reference

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get_ports

Tcl command; returns an object representing the port(s) that match those specified in the pattern argument. get_ports

pattern

Argument

pattern

Specifies the pattern to match the ports.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Example

create_clock -period 10 [get_ports CK1]

See Also

Tcl documentation conventions

Designer Tcl Command Reference

list_clock_latencies

Tcl command; returns details about all of the clock latencies in the current timing constraint scenario. list_clock_latencies

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_clock_latencies]

See Also

set_clock_latency

remove_clock_latency

Tcl documentation conventions

Designer Tcl Command Reference

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list_clock_uncertainties

list_clock_uncertainties

Tcl command; returns details about all of the clock uncertainties in the current timing constraint scenario. list_clock_uncertainties

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

list_clock_uncertainties

See Also

remove_clock_uncertainty

Designer Tcl Command Reference

list_clocks

Tcl command; returns details about all of the clock constraints in the current timing constraint scenario. list_clocks

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_clocks]

See Also

remove_clock

Tcl documentation conventions

Designer Tcl Command Reference

list_disable_timings

Tcl command; returns the list of disable timing constraints for the current scenario. list_disable_timings

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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Example

list_disable_timings

See Also

Designer Tcl Command Reference

list_false_paths

Tcl command; returns details about all of the false paths in the current timing constraint scenario. list_false_paths

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_false_paths]

See Also

set_false_path

remove_false_path

Tcl documentation conventions

Designer Tcl Command Reference

list_generated_clocks

Tcl command; returns details about all of the generated clock constraints in the current timing constraint scenario. list_generated_clocks

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_generated_clocks]

See Also

remove_generated_clock

Tcl documentation conventions

Designer Tcl Command Reference

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list_input_delays

list_input_delays

Tcl command; returns details about all of the input delay constraints in the current timing constraint scenario. list_input_delays

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_input_delays]

See Also

remove_input_delay

Tcl documentation conventions

Designer Tcl Command Reference

list_max_delays

Tcl command; returns details about all of the maximum delay constraints in the current timing constraint scenario. list_max_delays

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_max_delays]

See Also

remove_max_delay

Tcl documentation conventions

Designer Tcl Command Reference

list_min_delays

Tcl command; returns details about all of the minimum delay constraints in the current timing constraint scenario. list_min_delays

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Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_min_delays]

See Also

remove_min_delay

Tcl documentation conventions

Designer Tcl Command Reference

list_multicycle_paths

Tcl command; returns details about all of the multicycle paths in the current timing constraint scenario. list_multicycle_paths

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_multicycle_paths]

See Also

remove_multicycle_path

Tcl documentation conventions

Designer Tcl Command Reference

list_objects

Tcl command; returns a list of object matching the parameter. Objects can be nets, pins, ports, clocks or instances. list_objects <object>

Arguments

Any timing constraint parameter.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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list_output_delays

Example

The following example lists all the inputs in your design: list_objects [all_inputs]

You can also use wildcards to filter your list, as in the following command: list_objects [get_ports a*]

See Also

Tcl documentation conventions

Designer Tcl Command Reference

list_output_delays

Tcl command; returns details about all of the output delay constraints in the current timing constraint scenario. list_output_delays

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

puts [list_output_delays]

See Also

remove_output_delay

Tcl documentation conventions

Designer Tcl Command Reference

list_scenarios

Tcl command; returns a list of names of all of the available timing scenarios. list_scenarios

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

list_scenarios

See Also

get_current_scenario

Tcl documentation conventions

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Designer Tcl Command Reference

remove_clock

Tcl command; removes the specified clock constraint from the current timing scenario. remove_clock -name

clock_name

| -id

constraint_ID

Arguments

-name

clock_name

Specifies the name of the clock constraint to remove from the current scenario. You must specify either a clock name or an ID.

-id

constraint_ID

Specifies the ID of the clock constraint to remove from the current scenario. You must specify either an

ID or a clock name that exists in the current scenario.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes the specified clock constraint from the current scenario. If the specified name does not match a clock constraint in the current scenario, or if the specified ID does not refer to a clock constraint, this command fails.

Do not specify both the name and the ID.

Exceptions

You cannot use wildcards when specifying a clock name.

Examples

The following example removes the clock constraint named "my_user_clock": remove_clock -name my_user_clock

The following example removes the clock constraint using its ID: set clockId [create_clock –name my_user_clock –period 2] remove_clock –id $clockId

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_clock_latency

Tcl command; removes a clock source latency from the specified clock and from all edges of the clock. remove_clock_latency {-source

clock_name_or_source

|-id

constraint_ID

}

Arguments

-source

clock_name_or_source

Specifies either the clock name or source name of the clock constraint from which to remove the clock source latency. You must specify either a clock or source name or its constraint ID.

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remove_clock_uncertainty

-id

constraint_ID

Specifies the ID of the clock constraint to remove from the current scenario. You must specify either a clock or source name or its constraint ID.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes a clock source latency from the specified clock in the current scenario. If the specified source does not match a clock with a latency constraint in the current scenario, or if the specified ID does not refer to a clock with a latency constraint, this command fails.

Do not specify both the source and the ID.

Exceptions

You cannot use wildcards when specifying a clock name.

Examples

The following example removes the clock source latency from the specified clock. remove_clock_latency -source my_clock

See Also

set_clock_latency

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_clock_uncertainty

Tcl command; removes a clock-to-clock uncertainty from the current timing scenario by specifying either its exact arguments or its ID. remove_clock_uncertainty -from | -rise_from | -fall_from

from_clock_list

-to | -rise_to| fall_to

to_clock_list

-setup {

value

} -hold {

value

} remove_clock_uncertainty -id

constraint_ID

Arguments

-from

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the source clock list. Only one of the -from, -rise_from, or -fall_from arguments can be specified for the constraint to be valid.

-rise_from

Specifies that the clock-to-clock uncertainty applies only to rising edges of the source clock list. Only one of the -from, -rise_from, or -fall_from arguments can be specified for the constraint to be valid.

-fall_from

Specifies that the clock-to-clock uncertainty applies only to falling edges of the source clock list. Only one of the -from, -rise_from, or -fall_from arguments can be specified for the constraint to be valid.

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the destination clock list. Only one of the -to, -rise_to , or -fall_to arguments can be specified for the constraint to be valid.

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Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes a clock-to-clock uncertainty from the specified clock in the current scenario. If the specified arguments do not match clocks with an uncertainty constraint in the current scenario, or if the specified ID does not refer to a clock-to-clock uncertainty constraint, this command fails.

Do not specify both the exact arguments and the ID.

Examples

-rise_to

Specifies that the clock-to-clock uncertainty applies only to rising edges of the destination clock list. Only one of the -to, -rise_to , or -fall_to arguments can be specified for the constraint to be valid.

-fall_to

Specifies that the clock-to-clock uncertainty applies only to falling edges of the destination clock list. Only one of the -to, -rise_to , or -fall_to arguments can be specified for the constraint to be valid.

to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-id

constraint_ID

Specifies the ID of the clock constraint to remove from the current scenario. You must specify either the exact parameters to set the constraint or its constraint ID. remove_clock_uncertainty -from Clk1 -to Clk2 remove_clock_uncertainty -from Clk1 -fall_to { Clk2 Clk3 } -setup remove_clock_uncertainty 4.3 -fall_from { Clk1 Clk2 } -rise_to * remove_clock_uncertainty 0.1 -rise_from [ get_clocks { Clk1 Clk2 } ] -fall_to { Clk3

Clk4 } -setup remove_clock_uncertainty 5 -rise_from Clk1 -to [ get_clocks {*} ] remove_clock_uncertainty -id $clockId

See Also

remove_clock

remove_generated_clock

Designer Tcl Command Reference

remove_disable_timing

Tcl command; removes a disable timing constraint by specifying its arguments, or its ID. If the arguments do not match a disable timing constraint, or if the ID does not refer to a disable timing constraint, the command fails. remove_disable_timing -from

value

-to

value name

-id

name

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remove_false_path

Arguments

-from

from_port

Specifies the starting port. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

-to

to_port

Specifies the ending port. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

name

Specifies the cell name where the disable timing constraint will be removed. It is an error to supply both a cell name and a constraint ID, as they are mutually exclusive. No wildcards are allowed when specifying a clock name, either alone or in an accessor command1.

-id

name

Specifies the constraint name where the disable timing constraint will be removed. It is an error to supply both a cell name and a constraint ID, as they are mutually exclusive. No wildcards are allowed when specifying a clock name, either alone or in an accessor command1.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Example

remove_disable_timing -from port1 -to port2 -id new_constraint

Designer Tcl Command Reference

remove_false_path

Tcl command; removes a false path from the current timing scenario by specifying either its exact arguments or its ID. remove_false_path [-from

from_list

] [-to

to_list

] [-through

through_list

] [-id

constraint_ID

] remove_false_path -id

constraint_ID

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-id

constraint_ID

Specifies the ID of the false path constraint to remove from the current scenario. You must specify either the exact false path to remove or the constraint ID that refers to the false path constraint to remove.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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Description

Removes a false path from the specified clock in the current scenario. If the arguments do not match a false path constraint in the current scenario, or if the specified ID does not refer to a false path constraint, this command fails.

Do not specify both the false path arguments and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an Accessor command such as get_pins or get_ports.

Examples

The following example specifies all false paths to remove: remove_false_path -through U0/U1:Y

The following example removes the false path constraint using its id: set fpId [set_false_path –from [get_clocks c*] –through {topx/reg/*} –to [get_ports out15] ] remove_false_path –id $fpId

See Also

set_false_path

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_generated_clock

Tcl command; removes the specified generated clock constraint from the current scenario. remove_generated_clock {-name

clock_name

| -id

constraint_ID

}

Arguments

-name

clock_name

Specifies the name of the generated clock constraint to remove from the current scenario. You must specify either a clock name or an ID.

-id

constraint_ID

Specifies the ID of the generated clock constraint to remove from the current scenario. You must specify either an ID or a clock name that exists in the current scenario.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes the specified generated clock constraint from the current scenario. If the specified name does not match a generated clock constraint in the current scenario, or if the specified ID does not refer to a generated clock constraint, this command fails.

Do not specify both the name and the ID.

Exceptions

You cannot use wildcards when specifying a generated clock name.

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remove_input_delay

Examples

The following example removes the generated clock constraint named "my_user_clock": remove_generated_clock -name my_user_clock

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_input_delay

Tcl command; removes an input delay a clock on a port by specifying both the clocks and port names or the ID of the input_delay constraint to remove. remove_input_delay -clock

clock_name port_pin_list

remove_input_delay -id

constraint_ID

Arguments

-clock

clock_name

Specifies the clock name to which the specified input delay value is assigned.

port_pin_list

Specifies the port names to which the specified input delay value is assigned.

-id

constraint_ID

Specifies the ID of the clock with the input_delay value to remove from the current scenario. You must specify either both a clock name and list of port names or the input_delay constraint ID .

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes an input delay from the specified clocks and port in the current scenario. If the clocks and port names do not match an input delay constraint in the current scenario, or if the specified ID does not refer to an input delay constraint, this command fails.

Do not specify both the clock and port names and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an accessor command.

Examples

The following example removes the input delay from CLK1 on port data1: remove_input_delay -clock [get_clocks CLK1] [get_ports data1]

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

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remove_max_delay

Tcl command; removes a maximum delay constraint from the current timing scenario by specifying either its exact arguments or its ID. remove_max_delay [-from

from_list

] [-to

to_list

] [-through

through_list

] remove_max_delay -id

constraint_ID

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-id

constraint_ID

Specifies the ID of the maximum delay constraint to remove from the current scenario. You must specify either the exact maximum delay arguments to remove or the constraint ID that refers to the maximum delay constraint to remove.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes a maximum delay value from the specified clock in the current scenario. If the arguments do not match a maximum delay constraint in the current scenario, or if the specified ID does not refer to a maximum delay constraint, this command fails.

Do not specify both the maximum delay arguments and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an Accessor command.

Examples

The following example specifies a range of maximum delay constraints to remove: remove_max_delay -through U0/U1:Y

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_min_delay

Tcl command; removes a minimum delay constraint in the current timing scenario by specifying either its exact arguments or its ID. remove_min_delay [-from

from_list

] [-to

to_list

] [-through

through_list

] remove_min_delay -id

constraint_ID

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remove_multicycle_path

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-id

constraint_ID

Specifies the ID of the minimum delay constraint to remove from the current scenario. You must specify either the exact minimum delay arguments to remove or the constraint ID that refers to the minimum delay constraint to remove.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes a minimum delay value from the specified clock in the current scenario. If the arguments do not match a minimum delay constraint in the current scenario, or if the specified ID does not refer to a minimum delay constraint, this command fails.

Do not specify both the minimum delay arguments and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an accessor command.

Examples

The following example specifies a range of minimum delay constraints to remove: remove_min_delay -through U0/U1:Y

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_multicycle_path

Tcl command; removes a multicycle path constraint in the current timing scenario by specifying either its exact arguments or its ID. remove_multicycle_path [-from

from_list

] [-to

to_list

] [-through

through_list

] remove multicycle_path -id

constraint_ID

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to

to_list

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Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-id

constraint_ID

Specifies the ID of the multicycle path constraint to remove from the current scenario. You must specify either the exact multicycle path arguments to remove or the constraint ID that refers to the multicycle path constraint to remove.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Removes a multicycle path from the specified clock in the current scenario. If the arguments do not match a multicycle path constraint in the current scenario, or if the specified ID does not refer to a multicycle path constraint, this command fails.

Do not specify both the multicycle path arguments and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an accessor command.

Examples

The following example removes all paths between reg1 and reg2 to 3 cycles for setup check. remove_multicycle_path -from [get_pins {reg1}] –to [get_pins {reg2}]

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

remove_output_delay

Tcl command; removes an ouput delay by specifying both the clocks and port names or the ID of the output_delay constraint to remove. remove_output_delay -clock

clock_name port_pin_list

remove_output_delay -id

constraint_ID

Arguments

-clock

clock_name

Specifies the clock name to which the specified output delay value is assigned.

port_pin_list

Specifies the port names to which the specified output delay value is assigned.

-id

constraint_ID

Specifies the ID of the clock with the output_delay value to remove from the current scenario. You must specify either both a clock name and list of port names or the output_delay constraint ID .

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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rename_scenario

Description

Removes an output delay from the specified clocks and port in the current scenario. If the clocks and port names do not match an output delay constraint in the current scenario, or if the specified ID does not refer to an output delay constraint, this command fails.

Do not specify both the clock and port names and the constraint ID.

Exceptions

You cannot use wildcards when specifying a clock name, either alone or in an accessor command.

Examples

The following example removes the output delay from CLK1 on port out1: remove_output_delay -clock [get_clocks CLK1] [get_ports out1]

See Also

report (Timing) for SmartFusion2, SmartFusion, IGLOO, ProASIC3, Fusion families

Tcl Command Documentation Conventions

Designer Tcl Command Reference

rename_scenario

Tcl command; renames the specified timing scenario with the new name provided. You must provide a unique new name (that is, it cannot already be used by another timing scenario). rename_scenario

oldname

-new

newname

Arguments

oldname

Specifies the current name of the timing scenario.

-new

newname

Specifies the new name to give to the timing scenario.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command changes the name of the timing scenario in the list of scenarios.

Example

rename_scenario scenario_A -new scenario_B

See Also

create_scenario

delete_scenario

Tcl documentation conventions

Designer Tcl Command Reference

report

The report command provides you with frequently-used information in a convenient format.

You can generate several different types of reports using this command, including:

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• report (Status)

•

•

report (Timing violations) for SmartFusion2, SmartFusion, IGLOO, ProASIC3, Fusion families

• report (Pin)

• report (Flip-flop)

• report (I/O Bank)

• report (Global Usage)

• report (Power)

set_clock_latency

Tcl command; defines the delay between an external clock source and the definition pin of a clock within

SmartTime. set_clock_latency -source [-rise][-fall][-early][-late]

delay clock

Arguments

-source

Specifies the source latency on a clock pin, potentially only on certain edges of the clock.

-rise

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-fall

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock.

-late

Optional. Specifies that the latency is late bound on the latency. The appropriate bound is used to provide the most pessimistic timing scenario. However, if the value of "-late" is less than the value of "-early", optimistic timing takes place which could result in incorrect analysis. If neither or both "-early" and "-late" are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.

-early

Optional. Specifies that the latency is early bound on the latency. The appropriate bound is used to provide the most pessimistic timing scenario. However, if the value of "-late" is less than the value of "early", optimistic timing takes place which could result in incorrect analysis. If neither or both "-early" and

"-late" are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.

delay

Specifies the latency value for the constraint.

clock

Specifies the clock to which the constraint is applied. This clock must be constrained.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

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set_clock_to_output

calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

Examples

The following example sets an early clock source latency of 0.4 on the rising edge of main_clock. It also sets a clock source latency of 1.2, for both the early and late values of the falling edge of main_clock. The late value for the clock source latency for the falling edge of main_clock remains undefined. set_clock_latency –source –rise –early 0.4 { main_clock } set_clock_latency –source –fall 1.2 { main_clock }

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_clock_to_output

SDC command; defines the timing budget available inside the FPGA for an output relative to a clock. set_clock_to_output

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

output_list

Arguments

delay_value

Specifies the clock to output delay in nanoseconds. This time represents the amount of time available inside the FPGA between the active clock edge and the data change at the output port.

-clock

clock_ref

Specifies the reference clock to which the specified clock to output is related. This is a mandatory argument.

-max

Specifies that

delay_value

refers to the maximum clock to output at the specified output. If you do not specify –max or –min options, the tool assumes maximum and minimum clock to output delays to be equal.

-min

Specifies that

delay_value

refers to the minimum clock to output at the specified output. If you do not specify –max or –min options, the tool assumes maximum and minimum clock to output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the reference clock. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

set_clock_uncertainty

Tcl command; specifies a clock-to-clock uncertainty between two clocks (from and to) and returns the ID of the created constraint if the command succeeded.

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uncertainty

-from | -rise_from | -fall_from

from_clock_list

-to | rise_to | -fall_to

to_clock_list

-setup {

value

} -hold {

value

}

Arguments

uncertainty

Specifies the time in nanoseconds that represents the amount of variation between two clock edges.

-from

-rise_from

-fall_from

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

-rise_to

-fall_to

to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

The set_clock_uncertainty command sets the timing uncertainty between two clock waveforms or maximum clock skew. Timing between clocks have no uncertainty unless you specify it.

Examples

set_clock_uncertainty 10 -from Clk1 -to Clk2 set_clock_uncertainty 0 -from Clk1 -fall_to { Clk2 Clk3 } -setup set_clock_uncertainty 4.3 -fall_from { Clk1 Clk2 } -rise_to * set_clock_uncertainty 0.1 -rise_from [ get_clocks { Clk1 Clk2 } ] -fall_to { Clk3 Clk4 }

-setup

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set_current_scenario

set_clock_uncertainty 5 -rise_from Clk1 -to [ get_clocks {*} ]

See Also

remove_clock_uncertainty

Designer Tcl Command Reference

set_current_scenario

Tcl command; specifies the timing scenario for the Timing Analyzer to use. All commands that follow this command will apply to the specified timing scenario. set_current_scenario

name

Arguments

name

Specifies the name of the timing scenario to which to apply all commands from this point on.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

A timing scenario is a set of timing constraints used with a design. If the specified scenario is already the current one, this command has no effect.

After setting the current scenario, constraints can be listed, added, or removed, the checker can be invoked on the set of constraints, and so on.

This command uses the specified timing scenario to compute timing analysis.

Example

set_current_scenario scenario_A

See Also

get_current_scenario

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_disable_timing

Tcl command; disables timing arcs within a cell and returns the ID of the created constraint if the command succeeded. set_disable_timing -from

value

-to

value name

Arguments

-from

from_port

Specifies the starting port. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

-to

to_port

Specifies the ending port. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

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name

Specifies the cell name where the timing arcs will be disabled.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Example

set_disable_timing -from A -to Y a2

See Also

Tcl documentation conventions

Designer Tcl Command Reference

set_external_check

SDC command; defines the external setup and hold delays for an input relative to a clock. set_external_check

delay_value

-clock

clock_ref

[–setup] [–hold] [–clock_fall]

input_list

Arguments

delay_value

Specifies the external setup or external hold delay in nanoseconds. This time represents the amount of time available inside the FPGA for the specified input after a clock edge.

-clock

clock_ref

Specifies the reference clock to which the specified external check is related. This is a mandatory argument.

-setup

Specifies that

delay_value

refers to the setup check at the specified input. This is a mandatory argument if –hold is not used. You must specify either the -setup or -hold option.

-clock_fall

Specifies that the delay is relative to the falling edge of the reference clock. The default is the rising edge.

input_list

Provides a list of input ports in the current design to which

delay_value

is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

set_false_path

Tcl command; identifies paths that are considered false and excluded from the timing analysis in the current timing scenario. set_false_path [-from

from_list

] [-through

through_list

] [-to

to_list

]

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

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set_input_delay

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

The set_false_path command identifies specific timing paths as being false. The false timing paths are paths that do not propagate logic level changes. This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis. The path starting points are the input ports or register clock pins, and the path ending points are the register data pins or output ports.

This constraint disables setup and hold checking for the specified paths.

The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints. If more than one object is specified within one -through option, the path can pass through any objects.

You must specify at least one of the –from, -to, or –through arguments for this constraint to be valid.

Examples

The following example specifies all paths from clock pins of the registers in clock domain clk1 to data pins of a specific register in clock domain clk2 as false paths: set_false_path –from [get_clocks {clk1}] –to reg_2:D

The following example specifies all paths through the pin U0/U1:Y to be false: set_false_path -through U0/U1:Y

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_input_delay

Tcl command; creates an input delay on a port list by defining the arrival time of an input relative to a clock in the current scenario. set_input_delay

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

input_list

Arguments

delay_value

Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge.

-clock

clock_ref

Specifies the clock reference to which the specified input delay is related. This is a mandatory argument.

If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path arriving at the specified input. If you do not specify max or -min options, the tool assumes maximum and minimum input delays to be equal.

-min

Specifies that delay_value refers to the shortest path arriving at the specified input. If you do not specify max or -min options, the tool assumes maximum and minimum input delays to be equal.

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-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

input_list

Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.and IGLOOe, except ProASIC3 nano and ProASIC3L

Description

The set_input_delay command sets input path delays on input ports relative to a clock edge. This usually represents a combinational path delay from the clock pin of a register external to the current design. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds input delay to path delay for paths starting at primary inputs.

A clock is a singleton that represents the name of a defined clock constraint. This can be:

• a single port name used as source for a clock constraint

• a single pin name used as source for a clock constraint; for instance reg1:CLK. This name can be hierarchical (for instance toplevel/block1/reg2:CLK)

• an object accessor that will refer to one clock: [get_clocks {clk}]

Examples

The following example sets an input delay of 1.2ns for port data1 relative to the rising edge of CLK1: set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports data1]

The following example sets a different maximum and minimum input delay for port IN1 relative to the falling edge of CLK2: set_input_delay 1.0 -clock_fall -clock CLK2 –min {IN1} set_input_delay 1.4 -clock_fall -clock CLK2 –max {IN1}

See Also

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_max_delay

Tcl command; specifies the maximum delay for the timing paths in the current scenario. set_max_delay

delay_value

[-from

from_list

] [-to

to_list

] [-through

through_list

]

Arguments

delay_value

Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.

•

If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.

•

If the path starting point has an input delay specified, the tool adds that delay value to the path delay.

•

If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.

•

If the ending point has an output delay specified, the tool adds that delay to the path delay.

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set_min_delay

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the timing paths must pass.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command specifies the required maximum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The timing engine automatically derives the individual maximum delay targets from clock waveforms and port input or output delays.

The maximum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multicycle path constraint.

You must specify at least one of the –from, -to, or –through arguments for this constraint to be valid.

Examples

The following example sets a maximum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns: set_max_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a maximum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns: set_max_delay 3.8 -to [get_ports out*]

See Also

remove_max_delay

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_min_delay

Tcl command; specifies the minimum delay for the timing paths in the current scenario. set_min_delay

delay_value

[-from

from_list

] [-to

to_list

] [-through

through_list

]

Arguments

delay_value

Specifies a floating point number in nanoseconds that represents the required minimum delay value for specified paths.

• If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.

• If the path starting point has an input delay specified, the tool adds that delay value to the path delay.

• If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.

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• If the ending point has an output delay specified, the tool adds that delay to the path delay.

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the timing paths must pass.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command specifies the required minimum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The timing engine automatically derives the individual minimum delay targets from clock waveforms and port input or output delays.

The minimum delay constraint is a timing exception. This constraint overrides the default single cycle timing relationship for one or more timing paths. This constraint also overrides a multicycle path constraint.

You must specify at least one of the –from, -to, or –through arguments for this constraint to be valid.

Examples

The following example sets a minimum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns: set_min_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a minimum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns: set_min_delay 3.8 -to [get_ports out*]

See Also

remove_min_delay

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_multicycle_path

Tcl command; defines a path that takes multiple clock cycles in the current scenario. set_multicycle_path

ncycles

[-setup] [-hold] [-from

from_list

[–through

through_list

[-to

to_list

Arguments

ncycles

Specifies an integer value that represents a number of cycles the data path must have for setup or hold check. The value is relative to the starting point or ending point clock, before data is required at the ending point.

-setup

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set_output_delay

Optional. Applies the cycle value for the setup check only. This option does not affect the hold check. The default hold check will be applied unless you have specified another set_multicycle_path command for the hold value.

-hold

Optional. Applies the cycle value for the hold check only. This option does not affect the setup check.

Note: If you do not specify "-setup" or "-hold", the cycle value is applied to the setup check and the default hold check is performed (ncycles -1).

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins or ports through which the multiple cycle paths must pass.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

Setting multiple cycle paths constraint overrides the single cycle timing relationships between sequential elements by specifying the number of cycles that the data path must have for setup or hold checks. If you change the multiplier, it affects both the setup and hold checks.

False path information always takes precedence over multiple cycle path information. A specific maximum delay constraint overrides a general multiple cycle path constraint.

If you specify more than one object within one -through option, the path passes through any of the objects.

You must specify at least one of the –from, -to, or –through arguments for this constraint to be valid.

Exceptions

Multiple priority management is not supported in Microsemi SoC designs. All multiple cycle path constraints are handled with the same priority.

Examples

The following example sets all paths between reg1 and reg2 to 3 cycles for setup check. Hold check is measured at the previous edge of the clock at reg2. set_multicycle_path 3 -from [get_pins {reg1}] –to [get_pins {reg2}]

The following example specifies that four cycles are needed for setup check on all paths starting at the registers in the clock domain ck1. Hold check is further specified with two cycles instead of the three cycles that would have been applied otherwise. set_multicycle_path 4 -setup -from [get_clocks {ck1}] set_multicycle_path 2 -hold -from [get_clocks {ck1}]

See Also

remove_multicycle_path

Tcl Command Documentation Conventions

Designer Tcl Command Reference

set_output_delay

Tcl command; defines the output delay of an output relative to a clock in the current scenario.

SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion 223

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

output_list

Arguments

delay_value

Specifies the amount of time before a clock edge for which the signal is required. This represents a combinational path delay to a register outside the current design plus the library setup time (for maximum output delay) or hold time (for minimum output delay).

-clock

clock_ref

Specifies the clock reference to which the specified output delay is related. This is a mandatory argument.

If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-min

Specifies that delay_value refers to the shortest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

The set_output_delay command sets output path delays on output ports relative to a clock edge. Output ports have no output delay unless you specify it. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds output delay to path delay for paths ending at primary outputs.

Examples

The following example sets an output delay of 1.2ns for port OUT1 relative to the rising edge of CLK1: set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports OUT1]

The following example sets a different maximum and minimum output delay for port OUT1 relative to the falling edge of CLK2: set_output_delay 1.0 -clock_fall -clock CLK2 –min {OUT1} set_output_delay 1.4 -clock_fall -clock CLK2 –max {OUT1}

See Also

remove_output_delay

Tcl Command Documentation Conventions

Designer Tcl Command Reference

st_commit

Tcl command; saves the changes made in SmartTime to the design (.adb) file

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st_create_set

st_commit

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_commit

See Also

st_restore

Tcl documentation conventions

Designer Tcl Command Reference

st_create_set

Tcl command; creates a set of paths to be analyzed. Use the arguments to specify which paths to include.

To create a set that is a subset of a clock domain, specify it with -clock and -type. To create a set that is a subset of an inter-clock domain set, specify it with -source_clock and -sink_clock. To create a set that is a subset (filter) of an existing named set, specify the set to be filtered with -from_set.

To create a set that is not derived from an existing set, you must provide both the -source

pin_list

and -sink

pin_list

derived. Otherwise, the -source and -sink arguments act as filters on the pins from the parent set. You must give each new set a unique name in the design. st_create_set -name

name

[-parent_set

name

]

[-clock

clock_id

-type

value

]

[-in_to_out]

[-source_clock

clock_id

-sink_clock

clock_id

]

[-source

pin_list

] -sink

pin_list

]

Arguments

-name

name

Specifies a unique name for the newly create path set.

-parent_set

name

Specifies the name of the set to filter.

-clock

clock_id

Specifies that the set is to be a subset of the given clock domain. This argument is valid only if you also specify the -type argument.

-type

value

Specifies the predefined set type on which to base the new path set. You can only use this argument with the -clock argument, not by itself.

Value Description

reg_to_reg Paths between registers in the design async_to_reg Paths from asynchronous pins to registers

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Value

reg_to_async external_recovery

Description

Paths from registers to asynchronous pins

The set of paths from inputs to asynchronous pins external_removal external_setup

The set of paths from inputs to asynchronous pins

Paths from input ports to registers external_hold Paths from input ports to registers clock_to_out Paths from registers to output ports

-in_to_out

Specifies that the set is based on the “Input to Output” set, which includes paths that start at input ports and end at output ports.

-source_clock

clock_id

Specifies that the set will be a subset of an inter-clock domain set with the given source clock.

You can only use this option with the -sink_clock option, not by itself.

-sink_clock

clock_id

Specifies that the set will be a subset of an inter-clock domain set with the given sink clock.

You can only use this option with the -source_clock option, not by itself.

-source

pin_list

Specifies a filter on the source pins of the parent set. If you do not specify a parent set, this option filters all pins in the current design.

-sink

pin_list

Specifies a filter on the sink pins of the parent set. If you do not specify a parent set, this option filters all pins in the current design.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_create_set –name { my_user_set } –source { C* } –sink { D* } st_create_set –name { my_other_user_set } –from_set { my_user_set } –source { CL* } st_create_set –name { adder } –clock { ALU_CLOCK } –type { REG_TO_REG } -sink { ADDER*

} st_create_set –name { another_set } –source_clock { EXTERN_CLOCK } –sink_clock {

MY_GEN_CLOCK } st_create_set –name { some_p2p } –pin2pin –to { T* }

See Also

Designer Tcl Command Reference

Tcl documentation conventions

st_remove_set

st_edit_set

Tcl command; modifies the paths in a user set.

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st_expand_path

st_edit_set -name

name

[-source

pin_list

] [-sink

pin_list

]

[-rename_to

name

]

Arguments

-name

name

Specifies the name of the set to modify.

-source

pin_list

If the set is a subset of another set, specifies a filter on the source pins from the parent set. Otherwise, this option specifies the source pins of the set.

-sink

pin_list

If the set is a subset of another set, specifies a filter on the sink pins from the parent set. Otherwise, this option specifies the sink pins of the set.

-rename_to

name

Specifies a new name for the set.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_edit_set –name { my_user_set} –rename_to { my_critical_pins } st_edit_set –name { adder } –sink { ADD* }

See Also

Designer Tcl Command Reference

Tcl documentation conventions

st_create_set

st_remove_set

st_expand_path

Tcl command; displays expanded path information (path details) for paths. The paths to be expanded are identified by the parameters required to display these paths with st_list_paths. For example, to expand the first path listed with st_list_paths -clock {MYCLOCK} -type {register_to_register}, use the command st_expand_path -clock {MYCLOCK} -type {register_to_register}. Path details contain the pin name, type, net name, cell name, operation, delay, total delay, and edge as well as the arrival time, required time, and slack. These details are the same as details available in the SmartTime Expanded Path window. st_expand_path [-set

name

]

[-clock

clock_id

-type

value

]

[-in_to_out]

[-source_clock

clock_id

-sink_clock

clock_id

]

[-source

pin_list

] [-sink

pin_list

]

[-analysis

value

]

[-index

list_of_indices

]

[-format

value

]

Arguments

-set

name

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Displays a list of paths from the named set. You can either use the -set option to specify a set name, or use both -clock and -type to specify a set. A list of valid set names includes "in_to_out", as well as any user set names.

-clock

clock_id

Displays the set of paths belonging to the specified clock domain. You can either use this option along with -type to specify a set or use the -set option to specify the name of the set to display.

-in_to_out

Specifies that the paths should be from the set "Input to Output, which includes paths that start at input ports and end at output ports.

-type

value

Specifies the type of paths in the clock domain to display in a list. You can only use this option with the clock option, not by itself. You can either use this option along with -clock to specify a set or use the -set option to specify a set name.

Value Description

reg_to_reg async_to_reg reg_to_asyn

Paths between registers in the design

Paths from asynchronous pins to registers

Paths from registers to asynchronous pins external_recovery external_removal external_setup

The set of paths from inputs to asynchronous pins

Paths from input ports to registers

Paths from input ports to registers clock_to_out Paths from registers to output ports

-source_clock

clock_id

Displays a list of timing paths for an inter-clock domain set belonging to the source clock specified. You can only use this option with the -sink_clock option, not by itself.

-sink_clock

clock_id

Displays a list of timing paths for an inter-clock domain set belonging to the sink clock specified. You can only use this option with the -source_clock option, not by itself.

-source

pin_list

Specifies a filter on the source pins of the paths to be listed.

-sink

pin_list

Specifies a filter on the sink pins of the paths to be listed.

-analysis

name

Specifies the analysis type for the paths to be listed. The following table shows the acceptable values for this argument:

Value Description

maxdelay Maximum delay analysis mindelay Minimum delay analysis

-index

list_of_indices

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st_list_paths

text

Specifies which paths to display. The index starts at 1 and defaults to 1. Only values lower than the max_paths option will be expanded.

-format

value

Specifies the file format of the output. The following table shows the acceptable values for this argument:

Value Description

ASCII text format csv Comma separated value fie format

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

Note: The following example returns a list of five paths: st_expand_path –clock { myclock } –type {reg_to_reg } st_expand_path –clock {myclock} –type {reg_to_reg} –index { 1 2 3 } –format text

See Also

Designer Tcl Command Reference

Tcl documentation conventions

st_list_paths

Tcl command; displays the list of paths in the same tabular format shown in SmartTime. st_list_paths [-set

name

]

[-clock

clock_id

-type

value

]

[-in_to_out]

[-source_clock

clock_id

-sink_clock

clock_id

]

[-source

pin_list

] [-sink

pin_list

]

[-analysis

value

]

[-format

value

]

Arguments

-set

name

Displays a list of paths from the named set. You can either use the –set option to specify a set name, or use both –clock and –type to specify a set. A list of valid set names includes “in_to_out”, as well as any user set names.

-clock

clock_id

Displays the set of paths belonging to the specified clock domain. You can either use this option along with -type to specify a set or use the -set option to specify the name of the set to display.

-in_to_out

Specifies that the paths should be from the set “Input to Output”, which includes paths that start at input ports and end at output ports.

-type

value

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Value

reg_to_reg async_to_reg

Description

Paths between registers in the design

Paths from asynchronous pins to registers reg_to_asyn external_recovery external_removal external_setup

Paths from registers to asynchronous pins

The set of paths from inputs to asynchronous pins

Paths from input ports to registers

Paths from input ports to registers clock_to_out Paths from registers to output ports

-source_clock clock_id

Displays a list of timing paths for an inter-clock domain set belonging to the source clock specified. You can only use this option with the -sink_clock option, not by itself.

-sink_clock clock_id

Displays a list of timing paths for an inter-clock domain set belonging to the sink clock specified. You can only use this option with the -source_clock option, not by itself.

-source pin_list

Specifies a filter on the source pins of the paths to be listed.

-sink pin_list

Specifies a filter on the sink pins of the paths to be listed.

-analysis

name

Specifies the analysis type for the paths to be listed. The following table shows the acceptable values for this argument:

Value Description

maxdelay Maximum delay analysis mindelay Minimum delay analysis

-format

value

Specifies the file format of the output. The following table shows the acceptable values for this argument:

Value Description

text csv

ASCII text format

Comma separated value fie format

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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st_remove_all_constraints

Examples

st_list_paths –set { myset } st_list_paths –analysis mindelay –clock { myclock } –type { reg_to_reg } –format csv

The list of paths can be written to a file with the following Tcl commands: set outfile [ open “pathlisting.csv” w] puts $outfile [ st_list_paths –format csv –set { myset} ] close $outfile

See Also

Designer Tcl Command Reference

Tcl documentation conventions

st_expand_path

st_remove_all_constraints

Tcl command; removes all timing constraints from analysis st_remove_all_constraints

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Example

st_remove_all_constraints

st_remove_set

Tcl command; deletes a user set from the design. st_remove_set -name

name

Arguments

-name

name

Specifies the name of the set to delete.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_remove_set { clockset1 }

See Also

Designer Tcl Command Reference

Tcl documentation conventions

st_create_set

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st_restore

Tcl command; restores constraints previously committed in SmartTime. st_restore

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_restore

See Also

st_commit

Tcl documentation conventions

Designer Tcl Command Reference

st_set_options

Tcl command; sets options for timing analysis. With no parameters given, it will display the current settings of the options. For SmartFusion, IGLOO, ProASIC3, Fusion families, these options also affect timing-driven place-and-route. st_set_options [-max_opcond

value

]

[-min_opcond

value

]

[-interclockdomain_analysis

value

]

[-use_bibuf_loopbacks

value

]

[-enable_recovery_removal_checks

value

]

[-break_at_async

value

]

[-filter_when_slack_below

value

]

[-filter_when_slack_above

value

]

[-remove_slack_filters]

[-limit_max_paths

value

]

[-expand_clock_network

value

]

[-expand_parallel_paths

value

]

[-analysis_scenario

value

]

[-tdpr_scenario

value

]

[-reset]

Arguments

worst typ best

-max_opcond

value

Sets the operating condition to use for Maximum Delay Analysis. The following table shows the acceptable values for this argument:

Value Description

Use Worst Case conditions for Maximum Delay Analysis

Use Typical conditions for Maximum Delay Analysis

Use Best Case conditions for Maximum Delay Analysis

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st_set_options

-min_opcond

value

Sets the operating condition to use for Minimum Delay Analysis. The following table shows the acceptable values for this argument:

Value Description

best typ

Use Best Case conditions for Minimum Delay Analysis

Use Typical conditions for Minimum Delay Analysis worst Use Worst Case conditions for Minimum Delay Analysis

-interclockdomain_analysis

value

Enables or disables inter-clock domain analysis.

Value Description

yes Enables inter-clock domain analysis no Disables inter-clock domain analysis

-use_bibuf_loopbacks

value

Enables or disables loopback in bibufs.

Value Description

yes Enables loopback in bibufs no Disables loopback in bibufs

-enable_recovery_removal_checks

value

Enables or disables recovery and removal checks.

Value Description

yes Enables recovery and removal checks no Disables recovery and removal checks

-break_at_async

value

Enables or disables breaking paths at asynchronous ports.

Value Description

yes Enables breaking paths at asynchronous ports no Disables breaking paths at asynchronous ports

-filter_when_slack_below

value

Do not show paths with slack below x.

-filter_when_slack_above

value

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Do not show paths with slack above y.

-remove_slack_filters

Remove all existing slack filters.

-limit_max_paths

value

Limit path reporting commands to a maximum of <n> paths, where n is a value of 0 or higher.

-expand_clock_network

value

Enables or disables expanded clock network information in expanded paths.

Value Description

yes Enables expanded clock network information in paths no Disables expanded clock network information in paths

-expand_parallel_paths

value

Expand a maximum of <n> parallel paths, where n is a value of 0 or higher. If n is 0 or 1, only one path will be expanded when viewing expanded paths.

-analysis_scenario

value

Set the timing constraints scenario to be used for both maximum delay and minimum delay analysis. The argument must be a valid scenario name.

Note: This option does not affect the timing scenario used for TDPR.

-tdpr_scenario

value

Set the timing constraints scenario to be used by the place and route engine. The argument must be a valid scenario name.

Note: This option does not affect the timing scenario used for analysis.

-reset

Reset all options to their default values, except for scenarios used for analysis and TDPR that remain unchanged.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

st_set_options –max_opcond worst

-min_opcond best

-interclockdomain_analysis true

-enable_removal_recovery_checks true st_set_options –limit_max_paths 50 –remove_slack_filters

–filter_when_slack_above 3

See Also

Tcl documentation conventions

Designer Tcl Command Reference

timer_get_clock_actuals

Tcl command; displays the actual clock frequency in the Log window, when the timing analysis tool is initiated. timer_get_clock_actuals -clock

clock_name

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timer_get_clock_constraints

Arguments

-clock

clock_name

Specifies the name of the clock with the frequency (or period) to display.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

This example displays the actual clock frequency of clock clk1 in the Log window: timer_get_clock_actuals -clock clk1

See Also

timer_get_clock_constraints

Tcl documentation conventions

Designer Tcl Command Reference

timer_get_clock_constraints

Tcl command; returns the constraints (period, frequency, and duty cycle) on the specified clock. timer_get_clock_constraints -clock

clock_name

Arguments

-clock

clock_name

Specifies the name of the clock with the constraint to display.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example displays the clock constraints on the clock clk in the Log window: timer_get_clock_constraints -clock clk

See Also

timer_get_clock_actuals

Tcl documentation conventions

Designer Tcl Command Reference

timer_get_maxdelay

Tcl command; displays the maximum delay constraint between two pins in a path in the Log window. timer_get_maxdelay -from

source_pin

-to

destination_pin

Arguments

-from

source_pin

Specifies the name of the source pin in the path.

-to

destination_pin

Specifies the name of the destination pin in the path.

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Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example displays the maximum delay constraint from the pin clk166 to the pin reg_q_a_9_/U0:CLK in the Log window: timer_get_maxdelay -from {clk166} -to {reg_q_a_9_/U0:CLK}

See Also

timer_set_maxdelay

Tcl documentation conventions

Designer Tcl Command Reference

timer_get_path

Tcl command; displays the path between the specified pins in the Log window. timer_get_path -from

source_pin

-to

destination_pin

[-exp

value

[-sort

value

[-order

value

[-case

value

[-maxpath

maximum_paths

[-maxexpath

maximum_paths_to_expand

[-mindelay

minimum_delay

[-maxdelay

maximum_delay

[-breakatclk

value

[-breakatclr

value

]

Arguments

actual slack

-from

source_pin

Specifies the name of the source pin for the path.

-to

destination_pin

Specifies the name of the destination pin for the path.

-exp

value

Specifies whether to expand the path. The following table shows the acceptable values for this argument:

Value Description

yes Expands the path no Does not expand the path

-sort

value

Specifies whether to sort the path by either the actual delay or slack value. The following table shows the acceptable values for this argument:

Value Description

Sorts the path by the actual delay value

Sorts the path by the slack value

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timer_get_path

long

-order

value

Specifies whether the list is based on maximum or minimum delay analysis. The following table shows the acceptable values for this argument:

Value Description

The paths are listed based on the maximum delay analysis short The paths are listed based on the minimum delay analysis

-case

value

Specifies whether the report will include the worst, typical, or best case timing numbers. The following table shows the acceptable values for this argument:

Value Description

worst Includes worst case timing numbers typ Includes typical case timing numbers best Includes best case timing numbers

-maxpath

maximum_paths

Specifies the maximum number of paths to display.

-maxexpath

maximum_paths_to_expand

Specifies the maximum number of paths to expand.

-mindelay

minimum_delay

Specifies the path delay in the minimum delay analysis mode.

-maxdelay

maximum_delay

Specifies the path delay in the maximum delay analysis mode.

-breakatclk

value

Specifies whether to break the paths at the register clock pins. The following table shows the acceptable values for this argument:

Value Description

yes Breaks the paths at the register clock pins no Does not break the paths at the register clock pins

-breakatclr

value

Specifies whether to break the paths at the register clear pins. The following table shows the acceptable values for this argument:

Value Description

yes no

Breaks the paths at the register clear pins

Does not break the paths at the register clear pins

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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Examples

The following example returns the paths from input port headdr_dat<31> to the input pin of register u0_headdr_data1_reg/data_out_t_31 under typical conditions. timer_get_path -from "headdr_dat<31>" \

-to "u0_headdr_data1_reg/data_out_t_31/U0:D" \

-case typ \

-exp "yes" \

-maxpath "100" \

-maxexpapth "10"

The following example returns the paths from the clock pin of register gearbox_inst/bits64_out_reg<55> to the output port pma_tx_data_64bit[55] timer_get_path -from "gearbox_inst/bits64_out_reg<55>/U0:CLK" \

-to {pma_tx_data_64bit[55]} \

-exp "yes"

See Also

Tcl documentation conventions

Designer Tcl Command Reference

timer_get_path_constraints

Tcl command; displays the path constraints that were set as the maximum delay constraint in the timing analysis tool. timer_get_path_constraints

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

This command lists the paths constrained by maximum delay values. The information is displayed in the

Log window. If no maximum delay constraints are set, this command does not report anything.

Examples

Invoking timer_get_path_constraints displays the following paths and their delay constraints in the Log window: max_delay -from [all_inputs] -to [all_outputs] = 12 ns max_delay -from p_f_testwdata0 p_f_testwdata1 -to p_f_dacuwdata0 p_f_dacuwdata1 r_f_dacuwdata0 r_f_dacuwdata1 = 8 ns

See Also

Tcl documentation conventions

Designer Tcl Command Reference

timer_remove_all_constraints

Tcl command; removes all timing constraints in the current design.

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timer_remove_stop

timer_remove_all_constraints

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example removes all of the constraints from the design and then commits the changes: timer_remove_all_constraints timer_commit

See Also

Tcl documentation conventions

Designer Tcl Command Reference

timer_remove_stop

Tcl command; removes the previously entered path stop constraint on the specified pin. timer_remove_stop -pin

pin_name

Arguments

-pin

pin_name

Specifies the name of the pin from which to remove the path stop constraint.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Description

If you remove a path stop constraint using the Timer GUI, and then export a script using File > Export >

Script files, the resulting script will contain timer_remove_pass -pin

pin_name

instead of timer_remove_stop -pin

pin_name

Exceptions

• For the SmartFusion2, SmartFusion, IGLOO, ProASIC3, Fusion families, best practice is to use the following flow:

1. Open SmartTime >

Set False Path Constraint dialog box

2. Look for the pin name in the Through: list (Note: You must not have any entry selected in the

From or To lists).

3. Delete this pin.

Examples

The following example removes the path stop constraint on the clear pin reg_q_a_0_:CLR: timer_remove_stop -pin {reg_q_a_0_:CLR}

See Also

Tcl documentation conventions

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Set False Path Constraint dialog box

Designer Tcl Command Reference

timer_restore

Tcl command; restores constraints previously committed in Timer. timer_restore

Arguments

None

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

timer_restore

See Also

Tcl documentation conventions

Designer Tcl Command Reference

report (Timing) using SmartTime

Tcl command; creates a timing report. report -type timing \

[−print_summary

value

[−analysis

value

[−use_slack_threshold

value

[−slack_threshold

value

[−print_paths

value

[−max_paths

value

[−max_expanded_paths

value

[−include_user_sets

value

[−include_pin_to_pin

value

[-include_clock_domains

value

[−select_clock_domains

value

[−clock_domain clock_domain_list]

[−format

value

]

filename

Arguments

-type timing

Specifies the type of report to generate.

−print_summary

value

Specifies whether to print the summary section in the timing report.

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Value Description

yes Includes summary section in the timing report (the default value). no Excludes summary section in the timing report

−analysis

value

Specifies whether the report will consider minimum analysis or maximum analysis.

Value Description

min Timing report considers minimum analysis max Timing report considers maximum analysis (the default value)

−use_slack_threshold

value

Specifies whether the report will consider slack threshold.

Value Description

yes Includes slack threshold in the timing report. no Excludes slack threshold in the timing report (the default value)

−slack_threshold

value

Specifies the threshold to consider when reporting path slacks. This is a floating-point number in nanoseconds (ns). By default, there is no threshold (all slacks are reported).

−print_paths

value

Specifies whether the path section (clock domains and in-to-out paths) will be printed in the timing report.

Value Description

yes Includes path section in the timing report (the default value) no Excludes path sections from the timing report

−max_paths

value

Defines the maximum number of paths to display for each set. This is a positive integer value greater than zero. The default is 5.

−max_expanded_paths

value

Defines the number of paths to expand per set. This is a positive integer value greater than zero. The default is 1.

−include_user_sets

value

Defines whether to include the user defined sets in the timing report.

Value Description

yes Includes user defined sets in the timing report (the default value)

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Value Description

no Excludes user defined sets from the timing report

−include_pin_to_pin

value

Specifies whether to show pin-to-pin paths in the timing report.

Value Description

yes Includes pin-to-pin paths in the timing report (the default value). no Excludes pin-to-pin paths from the timing report

−include_clock_domains

value

Defines whether to include clock domains in the timing report.

Value Description

yes Includes clock domains no Excludes clock domains from the timing report

−select_clock_domains

value

Specifies whether to show the clock domain list in the timing report.

Value Description

yes Includes the clock domain list in the timing report no Excludes the clock domain list from the timing report (the default value)

−clock_domain clock_domain_list

Defines the clock domain to be considered in the clock domain section. The domain list is a series of strings with domain names separated by spaces. Both the summary and the path sections in the timing report display only the listed clock domains.

−format

value

Specifies the output format of the generated the report.

Value Description

text Generates a text report; text is the default value csv Generates the report in a comma-separated value format which you can import into a spreadsheet

filename

Specifies the name and destination of the timing report.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

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Examples

The following example generates a timing report named timing_report.txt. The report does not print the summary section. It includes a max-delay analysis and only reports paths with a slack value less than

0.50 ns. It reports a maximum of 3 paths per section and does not report any expanded paths. It only reports timing information for the clock domains count8_clock and count2_clk. report -type timing -print_summary no \

-analysis max \

-use_slack_threshold yes \

-slack_threshold 0.50 \

-print_paths yes -max_paths 3 \

-max_expanded_paths 0 \

-include_user_sets yes \

-include_pin_to_pin yes \

-select_clock_domains yes \

-clock_domain {count8_clock count2_clk} \ timing_report.txt

See Also

Tcl documentation conventions

report (Timing violations) using SmartTime

report (Datasheet) using SmartTime

Designer Tcl Command Reference

report (Timing violations) using SmartTime

Tcl command; creates a timing violations report. report -type timing_violations \

[−analysis

value

[−use_slack_threshold

value

[−slack_threshold

value

[–limit_max_paths

value

[−max_paths

value

[−max_expanded_paths

value

] \

[−format

value

]

filename

Arguments

-type timing_violations

Specifies the type of report to generate.

−analysis

value

Specifies whether to consider minimum analysis or maximum analysis in the timing violations report.

Value Description

min Timing report considers minimum analysis max Timing report considers maximum analysis (the default value)

−use_slack_threshold

value

Specifies whether to consider the slack threshold in the timing violations report.

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Value Description

yes Includes slack threshold in the timing violations report no Excludes slack threshold in the timing violations report (the default value)

−slack_threshold

value

Specifies the threshold to consider when reporting path slacks. This value is a floating-point number in nanoseconds (ns). By default, there is no threshold (all slacks reported).

–limit_max_paths

value

Specifies if the paths are limited by the number of paths.

Value Description

yes Limits the maximum number of paths to report no Specifies that there is no limit to the number of paths to report (the default value)

−max_paths

value

Specifies the maximum number of paths to display for each set. This value is a positive integer value greater than zero. Default is 100.

−max_expanded_paths

value

Specifies the number of paths to expand per set. This value is a positive integer value greater than zero. The default is 0.

−format

value

Specifies the output format of the generated report.

Value Description

text csv

Generates a text report; text is the default value

Generates the report in a comma-separated value format which you can import into a spreadsheet

filename

Specifies the name and destination of the timing violations report.

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example generates a timing violations report named timg_viol.txt. The report considers an analysis using maximum delays and does not filter paths based on slack threshold. It reports 2 paths per section and 1 expanded path per section. report -type timing_violations \

-analysis max -use_slack_threshold no \

-limit_max_paths -yes \

-max_paths 2 \

-max_expanded_paths 1 \

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report (Datasheet) using SmartTime

timg_viol.txt

See Also

Tcl documentation conventions

report (Timing) using SmartTime

report (Datasheet) using SmartTime

Designer Tcl Command Reference

report (Datasheet) using SmartTime

Tcl command; creates a datasheet report. report -type datasheet

filename \

[−format

value

]

Arguments

text csv filename

Specifies the name and destination of the datasheet report.

−format

value

Specifies the output format of the generated the report.

Value Description

Generates a text report; text is the default value

Generates the report in a comma-separated value format which you can import into a spreadsheet

Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example generates a datasheet report named datasheet.txt. report -type datasheet -format Text datasheet.txt

See Also

Tcl documentation conventions

report (Timing) using SmartTime

report (Timing violations) using SmartTime

Designer Tcl Command Reference

report (Bottleneck) using SmartTime

Tcl command; creates a bottleneck report. report -type bottleneck

[-cost_type {

value

} ]

[-use_slack_threshold{

value

} ]

[-slack_threshold {

value

} ]

[-set_name {

value

} ]

[-clock

clock_id

-set_type

value

]

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[-source_clock

clock_id

-sink_clock

clock_id

]

[-source {

pin_list

} ]

[-sink {

pin_list

} ]

[-max_instances {

value

} ]

[-max_paths {

value

} ]

[-max_parallel_paths {

value

} ]

[-analysis {

value

} ]

{

filename

} \

[−format

value

]

Arguments

-cost_type

value

Specifies the type of bottleneck cost. The default option is path_count.

Value Description

path_count Instances with the greatest number of path violations will have the highest bottleneck cost path_cost Instances with the largest combined timing violations will have the highest bottleneck cost

-use_slack_threshold

value

Specifies whether to consider the slack threshold when computing the bottlenecks in the report.

Value Description

yes Includes slack threshold in the bottleneck report no Excludes slack threshold in the bottleneck report

-slack_threshold

value

Specifies that paths whose slack is larger than this given threshold will be considered. Only instances that lie on these violating paths are reported. The default option is 0.

-set_name

value

Displays the bottleneck information for the named set. You can either use this option or use both –clock and –type. This option allows pruning based on a given set. Only paths that lie within the named set will be considered towards bottleneck.

-clock

value

This option allows pruning based on a given clock domain. Only instances that lie on these violating paths are reported.

-set_type

value

This option can only be used in combination with the –clock option, and not by itself. The options allow to filter which type of paths should be considered towards the bottleneck.

Value Description

reg_to_reg Paths between registers in the design async_to_reg reg_to_async external_recovery

Paths from asynchronous pins to registers

Paths from registers to asynchronous pins

The set of paths from inputs to asynchronous pins

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report (Bottleneck) using SmartTime

Value

external_removal external_setup

Description

The set of paths from inputs to asynchronous pins

Paths from input ports to registers external_hold Paths from input ports to registers clock_to_out Paths from registers to output ports

-source_clock

clock_id

Reports only bottleneck instances that lie on violating timing paths of the inter-clock domain that starts at the source clock specified by this option. This option can only be used in combination with -sink_clock, and not by itself.

-sink_clock

clock_id

Reports only bottleneck instances that lie on violating timing paths of the inter-clock domain that ends at the sink clock specified by this option. This option can only be used in combination with -source_clock, and not by itself.

-source

value

Reports only instances that lie on violating paths that start at locations specified by this option.

-sink

value

Reports only instances that lie on violating paths that end at locations specified by this option.

-max_instances

value

Specifies the maximum number of instances to be reported. Defaults to 10.

-max_paths

value

Specifies the maximum number of paths to be considered per path set type. Allowed values are 1 to

2000000. Defaults to 100.

-max_parallel_paths

value

Specifies the maximum number of paths allowed per end point pair. Only instances that lie on these violating paths are reported. Defaults to 1 (No parallel paths).

-analysis

value

Specifies the analysis types (max or min) under which the violations are reported. Defaults to max analysis.

Value Description

max Sets the analysis type to maximum delay min Sets the analysis type to minimum delay

−format

value

Specifies the output format of the generated report.

Value Description

text Generates a text report; text is the default value csv Generates the report in a comma-separated value format that you can import into a spreadsheet

filename

Specifies the name and destination of the bottleneck report.

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Supported Families

See the Tcl Commands and Supported Families table for the list of families that support this command.

Examples

The following example generates a bottleneck report named bottleneck.txt. report -type bottleneck -cost_type path_count -slack_threshold 0 -set_name set1 max_paths 10 -max_parallel_paths 10 -analysis max -format text bottleneck.txt

See Also

Tcl documentation conventions

Designer Tcl Command Reference

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Constraints by File Format - SDC Command

Reference

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About Synopsys Design Constraints (SDC) Files

Synopsys Design Constraints (SDC) is a Tcl-based format used by Synopsys tools to specify the design intent, including the timing and area constraints for a design. Microsemi tools use a subset of the SDC format to capture supported timing constraints. Any timing constraint that you can enter using Designer tools can also be specified in an SDC file.

Use the SDC-based flow to share timing constraint information between Microsemi tools and third-party EDA tools.

Command Action

Creates a clock and defines its characteristics

remove_clock_uncertainty Removes a clock-to-clock uncertainty from the current

Creates an internally generated clock and defines its characteristics

timing scenario.

set_clock_latency

Defines the delay between an external clock source and the definition pin of a clock within SmartTime

set_false_path

Defines the timing uncertainty between two clock waveforms or maximum skew

Identifies paths that are to be considered false and excluded from the timing analysis

set_load

Defines the arrival time of an input relative to a clock

Sets the load to a specified value on a specified port

Specifies the maximum delay for the timing paths

Specifies the minimum delay for the timing paths

Defines a path that takes multiple clock cycles

Defines the output delay of an output relative to a clock

See Also

Constraint Entry

Importing Constraint Files

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SDC Syntax Conventions

The following table shows the typographical conventions that are used for the SDC command syntax.

Syntax

Notation

Description

command argument

Commands and arguments appear in Courier New typeface.

variable

[-argument

value

]

Variables appear in blue, italic

Courier New

typeface. You must substitute an appropriate value for the variable.

Optional arguments begin and end with a square bracket.

Note: SDC commands and arguments are case sensitive.

Example

The following example shows syntax for the create_clock command and a sample command: create_clock -period

period_value

[-waveform

edge_list

] source create_clock –period 7 –waveform {2 4}{CLK1}

Wildcard Characters

You can use the following wildcard characters in names used in the SDC commands:

Wildcard What it does

Interprets the next character literally

Matches any string

Note: The matching function requires that you add a backslash (\) before each slash in the pin names in case the slash does not denote the hierarchy in your design.

Special Characters ([ ], { }, and \)

Square brackets ([ ]) are part of the command syntax to access ports, pins and clocks. In cases where these netlist objects names themselves contain square brackets (for example, buses), you must either enclose the names with curly brackets ({}) or precede the open and closed square brackets ([ ]) characters with a backslash (\). If you do not do this, the tool displays an error message.

For example: create_clock -period 3 clk\[0\] set_max_delay 1.5 -from [get_pins ff1\[5\]:CLK] -to [get_clocks {clk[0]}]

Although not necessary, Microsemi recommends the use of curly brackets around the names, as shown in the following example: set_false_path –from {data1} –to [get_pins {reg1:D}]

In any case, the use of the curly bracket is mandatory when you have to provide more than one name.

For example: set_false_path –from {data3 data4} –to [get_pins {reg2:D reg5:D}]

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Entering Arguments on Separate Lines

If a command needs to be split on multiple lines, each line except the last must end with a backslash (\) character as shown in the following example: set_multicycle_path 2 –from \

[get_pins {reg1*}] \

-to {reg2:D}

See Also

About SDC Files

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create_clock

SDC command; creates a clock and defines its characteristics. create_clock -name

name

-period

period_value

[-waveform

edge_list

]

source

Arguments

-name

name

Specifies the name of the clock constraint. This parameter is required for virtual clocks when no clock source is provided.

-period

period_value

Specifies the clock period in nanoseconds. The value you specify is the minimum time over which the clock waveform repeats. The period_value must be greater than zero.

-waveform

edge_list

source

Specifies the source of the clock constraint. The source can be ports or pins in the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing one. Only one source is accepted. Wildcards are accepted as long as the resolution shows one port or pin.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

The clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Exceptions

• None

Examples

The following example creates a clock on port CK3 with a period of 7, a rising edge at 2, and a falling edge at 4: create_clock –period 7 –waveform {2 4} [get_ports {CK3}]

Microsemi Implementation Specifics

• The -waveform in SDC accepts waveforms with multiple edges within a period. In Microsemi design implementation, only two waveforms are accepted.

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• SDC accepts defining a clock on many sources using a single command. In Microsemi design implementation, only one source is accepted.

• The source argument in SDC create_clock command is optional. This is in conjunction with the -name argument in SDC to support the concept of virtual clocks. In Microsemi implementation, source is a mandatory argument as -name and virtual clocks concept is not supported.

• The -domain argument in the SDC create_clock command is not supported.

See Also

Constraint Support by Family

Constraint Entry Table

Create a New Clock Constraint

Clock Definition

Create Clock

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create_generated_clock

SDC command; creates an internally generated clock and defines its characteristics. create_generated_clock -name {

name

-source

reference_pin

[-divide_by

divide_factor

] [multiply_by

multiply_factor

] [-invert] source -pll_output

pll_feedback_clock

-pll_feedback

pll_feedback_input

Arguments

-name

name

Specifies the name of the clock constraint. This parameter is required for virtual clocks when no clock source is provided.

-source

reference_pin

Specifies the reference pin in the design from which the clock waveform is to be derived.

-divide_by

divide_factor

Specifies the frequency division factor. For instance if the divide_factor is equal to 2, the generated clock period is twice the reference clock period.

-multiply_by

multiply_factor

Specifies the frequency multiplication factor. For instance if the multiply_factor is equal to 2, the generated clock period is half the reference clock period.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock. source

Wildcards are accepted as long as the resolution shows one pin.

-pll_output

pll_feedback_clock

Specifies the output pin of the PLL which is used as the external feedback clock. This pin must drive the feedback input pin of the PLL specified using the –pll_feedback option. The PLL will align the rising edge of the reference input clock to the feedback clock. This is a mandatory argument if the PLL is operating in external feedback mode.

-pll_feedback

pll_feedback_input

Specifies the feedback input pin of the PLL. This pin must be driven by the output pin of the PLL specified using the –pll_output option. The PLL will align the rising edge of the reference input clock to the external feedback clock. This is a mandatory argument if the PLL is operating in external feedback mode.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Examples

The following example creates a generated clock on pin U1/reg1:Q with a period twice as long as the period at the reference port CLK.

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{CLK}] U1/reg1:Q

The following example creates a generated clock named system_clk on the GL2 output pin of FCCC_0 with a period equal to half the period of the source clock. The constraint also identifies GL2 output pin as the external feedback clock source and CLK2 as the feedback input pin for FCCC_0. create_generated_clock -name { system_clk } \

-multiply_by 2 \

-source { FCCC_0/CCC_INST/INST_CCC_IP:CLK3_PAD } \

-pll_output { FCCC_0/CCC_INST/INST_CCC_IP:GL2 } \

-pll_feedback { FCCC_0/CCC_INST/INST_CCC_IP:CLK2 } \

{ FCCC_0/CCC_INST/INST_CCC_IP:GL2 }

Microsemi Implementation Specifics

• SDC accepts either –multiply_by or –divide_by option. In Microsemi design implementation, both are accepted to accurately model the PLL behavior.

• SDC accepts defining a generated clock on many sources using a single command. In Microsemi design implementation, only one source is accepted.

• The -duty_cycle ,-edges and –edge_shift options in the SDC create_generated_clock command are not supported in Microsemi design implementation.

See Also

Constraint Support by Family

Constraint Entry Table

Create Generated Clock Constraint (SDC)

remove_clock_uncertainty

SDC command; Removes a clock-to-clock uncertainty from the current timing scenario. remove_clock_uncertainty -from | -rise_from | -fall_from

from_clock_list

-to | -rise_to| fall_to

to_clock_list

-setup {

value

} -hold {

value

} remove_clock_uncertainty -id

constraint_ID

Arguments

-from

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

-rise_from

Specifies that the clock-to-clock uncertainty applies only to rising edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

-fall_from

Specifies that the clock-to-clock uncertainty applies only to falling edges of the source clock list. You can specify only one of the -from, -rise_from, or -fall_from arguments for the constraint to be valid.

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

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remove_clock_uncertainty

Specifies that the clock-to-clock uncertainty applies to both rising and falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-rise_to

Specifies that the clock-to-clock uncertainty applies only to rising edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

-fall_to

Specifies that the clock-to-clock uncertainty applies only to falling edges of the destination clock list. You can specify only one of the -to, -rise_to , or -fall_to arguments for the constraint to be valid.

to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If none or both -setup and -hold are present, the uncertainty applies to both setup and hold checks.

-id

constraint_ID

Specifies the ID of the clock constraint to remove from the current scenario. You must specify either the exact parameters to set the constraint or its constraint ID.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

Do not specify both the exact arguments and the ID.

Exceptions

None

Examples

remove_clock_uncertainty -from Clk1 -to Clk2 remove_clock_uncertainty -from Clk1 -fall_to { Clk2 Clk3 } -setup remove_clock_uncertainty 4.3 -fall_from { Clk1 Clk2 } -rise_to * remove_clock_uncertainty 0.1 -rise_from [ get_clocks { Clk1 Clk2 } ] -fall_to { Clk3

Clk4 } -setup remove_clock_uncertainty 5 -rise_from Clk1 -to [ get_clocks {*} ] remove_clock_uncertainty -id $clockId

See Also

Constraint Support by Family

Constraint Entry Table

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set_clock_latency

SDC command; defines the delay between an external clock source and the definition pin of a clock within SmartTime. set_clock_latency -source [-rise][-fall][-early][-late

] delay clock

Arguments

-source

Specifies a clock source latency on a clock pin.

-rise

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-fall

Specifies the edge for which this constraint will apply. If neither or both rise are passed, the same latency is applied to both edges.

-invert

Specifies that the generated clock waveform is inverted with respect to the reference clock.

-late

-early

"-late" are provided, the same latency is used for both bounds, which results in the latency having no effect for single clock domain setup and hold checks.

delay

Specifies the latency value for the constraint.

clock

Specifies the clock to which the constraint is applied. This clock must be constrained.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

Clock source latency defines the delay between an external clock source and the definition pin of a clock within SmartTime. It behaves much like an input delay constraint. You can specify both an "early" delay and a"late" delay for this latency, providing an uncertainty which SmartTime propagates through its calculations. Rising and falling edges of the same clock can have different latencies. If only one value is provided for the clock source latency, it is taken as the exact latency value, for both rising and falling edges.

Exceptions

None

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set_clock_to_output

Examples

Microsemi Implementation Specifics

SDC accepts a list of clocks to -set_clock_latency. In Microsemi design implementation, only one clock pin can have its source latency specified per command.

See Also

Constraint Support by Family

Constraint Entry Table

set_clock_to_output

SDC command; defines the timing budget available inside the FPGA for an output relative to a clock. set_clock_to_output

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

output_list

Arguments

delay_value

Specifies the clock to output delay in nanoseconds. This time represents the amount of time available inside the FPGA between the active clock edge and the data change at the output port.

-clock

clock_ref

Specifies the reference clock to which the specified clock to output is related. This is a mandatory argument.

-max

Specifies that delay_value refers to the maximum clock to output at the specified output. If you do not specify –max or –min options, the tool assumes maximum and minimum clock to output delays to be equal.

-min

Specifies that delay_value refers to the minimum clock to output at the specified output. If you do not specify –max or –min options, the tool assumes maximum and minimum clock to output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the reference clock. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

The set_clock_to_output command specifies the clock to output maximum and minimum delays on output ports relative to a clock edge. This usually represents a combinational path delay from a register internal to

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A clock is a singleton that represents the name of a defined clock constraint. This can be an object accessor that will refer to one clock. For example:

[get_clocks {system_clk}]

[get_clocks {sys*_clk}]

Examples

The following example sets a maximum clock to output delay of 12 ns and a minimum clock to output delay of 6 ns for port data_out relative to the rising edge of CLK1: set_clock_to_output 12 -clock [get_clocks CLK1] -max [get_ports data_out] set_clock_to_output 6 -clock [get_clocks CLK1] -min [get_ports data_out]

See Also

Constraint Support by Family

Constraint Entry Table

set_clock_uncertainty

SDC command; defines the timing uncertainty between two clock waveforms or maximum skew. set_clock_uncertainty

uncertainty

(-from | -rise_from | -fall_from)

from_clock_list

(-to | rise_to | -fall_to)

to_clock_list

[-setup | -hold]

Arguments

uncertainty

Specifies the time in nanoseconds that represents the amount of variation between two clock edges. The value must be a positive floating point number.

-from

-rise_from

-fall_from

from_clock_list

Specifies the list of clock names as the uncertainty source.

-to

-rise_to

-fall_to

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set_disable_timing to_clock_list

Specifies the list of clock names as the uncertainty destination.

-setup

Specifies that the uncertainty applies only to setup checks. If you do not specify either option (-setup or

-hold

) or if you specify both options, the uncertainty applies to both setup and hold checks.

-hold

Specifies that the uncertainty applies only to hold checks. If you do not specify either option (-setup or hold

) or if you specify both options, the uncertainty applies to both setup and hold checks.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

Clock uncertainty defines the timing between an two clock waveforms or maximum clock skew.

Exceptions

None

Examples

The following example defines two clocks and sets the uncertainty constraints, which analyzes the interclock domain between clk1 and clk2. create_clock –period 10 clk1 create_generated_clock –name clk2 -source clk1 -multiply_by 2 sclk1 set_clock_uncertainty 0.4 -rise_from clk1 -rise_to clk2

Microsemi Implementation Specifics

• SDC accepts a list of clocks to -set_clock_uncertainty.

See Also

Constraint Support by Family

Constraint Entry Table

create_generated_clock (SDC)

create_clock (SDC)

remove_clock_uncertainty

set_disable_timing

SDC command; disables timing arcs within the specified cell and returns the ID of the created constraint if the command succeeded.

set_disable_timing [-from

from_port

] [-to

to_port

]

cell_name

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Arguments

-from

from_port

Specifies the starting port.

-to

to_port

Specifies the ending port.

cell_name

Specifies the name of the cell in which timing arcs will be disabled.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command disables the timing arcs in the specified cell, and returns the ID of the created constraint if the command succeeded. The –from and –to arguments must either both be present or both omitted for the constraint to be valid.

Examples

The following example disables the arc between a2:A and a2:Y. set_disable_timing -from port1 -to port2 cellname

This command ensures that the arc is disabled within a cell instead of between cells.

Microsemi Implementation Specifics

• None

See Also

Constraint Support by Family

Constraint Entry Table

set_external_check

SDC command; defines the external setup and hold delays for an input relative to a clock. set_external_check

delay_value

-clock

clock_ref

[–setup] [–hold] [–clock_fall]

input_list

Arguments

delay_value

Specifies the external setup or external hold delay in nanoseconds. This time represents the amount of time available inside the FPGA for the specified input after a clock edge.

-clock

clock_ref

Specifies the reference clock to which the specified external check is related. This is a mandatory argument.

-setup

Specifies that delay_value refers to the setup check at the specified input. This is a mandatory argument if

–hold is not used. You must specify either -setup or -hold option.

-clock_fall

Specifies that the delay is relative to the falling edge of the reference clock. The default is the rising edge.

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set_external_check input_list

Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

The set_external_check command specifies the external setup and hold times on input ports relative to a clock edge. This usually represents a combinational path delay from the input port to the clock pin of a register internal to the current design. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool uses external setup and external hold times for paths starting at primary inputs.

A clock is a singleton that represents the name of a defined clock constraint. This can be an object accessor that will refer to one clock. For example:

[get_clocks {system_clk}]

[get_clocks {sys*_clk}]

Examples

The following example sets an external setup check of 12 ns and an external hold check of 6 ns for port data_in relative to the rising edge of CLK1: set_external_check 12 -clock [get_clocks CLK1] -setup [get_ports data_in] set_external_check 6 -clock [get_clocks CLK1] -hold [get_ports data_in]

See Also

Constraint Support by Family

Constraint Entry Table

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set_false_path

SDC command; identifies paths that are considered false and excluded from the timing analysis. set_false_path [-from

from_list

] [-through

through_list

] [-to

to_list

]

Arguments

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.

-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This constraint disables setup and hold checking for the specified paths.

Examples

The following example specifies all paths through the pin U0/U1:Y to be false: set_false_path -through U0/U1:Y

Microsemi Implementation Specifics

SDC accepts multiple -through options in a single constraint to specify paths that traverse multiple points in the design. In Microsemi design implementation, only one –through option is accepted.

See Also

Constraint Support by Family

Constraint Entry Table

Set False Path Constraint

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set_external_check

set_input_delay

SDC command; defines the arrival time of an input relative to a clock. set_input_delay

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

input_list

Arguments

delay_value

Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge.

-clock clock_ref

Specifies the clock reference to which the specified input delay is related. This is a mandatory argument.

If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path arriving at the specified input. If you do not specify max or -min options, the tool assumes maximum and minimum input delays to be equal.

-min

Specifies that delay_value refers to the shortest path arriving at the specified input. If you do not specify max or -min options, the tool assumes maximum and minimum input delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge. input_list

Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion and IGLOOe, except ProASIC3 nano and ProASIC3L

Description

A clock is a singleton that represents the name of a defined clock constraint. This can be:

• a single port name used as source for a clock constraint

• a single pin name used as source for a clock constraint; for instance reg1:CLK. This name can be hierarchical (for instance toplevel/block1/reg2:CLK)

• an object accessor that will refer to one clock: [get_clocks {clk}]

Examples

The following example sets an input delay of 1.2ns for port data1 relative to the rising edge of CLK1: set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports data1]

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Microsemi Implementation Specifics

In SDC, the -clock is an optional argument that allows you to set input delay for combinational designs.

Microsemi Implementation currently requires this argument.

See Also

Constraint Support by Family

Constraint Entry Table

Set Input Delay

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set_external_check

set_load

SDC command; sets the load to a specified value on a specified port. set_load

capacitance port_list

Arguments

capacitance

Specifies the capacitance value that must be set on the specified ports.

port_list

Specifies a list of ports in the current design on which the capacitance is to be set.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

The load constraint enables the Designer software to account for external capacitance at a specified port.

You cannot set load constraint on the nets. When you specify this constraint on the output ports, it impacts the delay calculation on the specified ports.

Examples

The following examples show how to set output capacitance on different output ports: set_load 35 out_p set_load 40 {O1 02} set_load 25 [get_ports out]

Microsemi Implementation Specifics

• In SDC, you can use the set_load command to specify capacitance value on nets. Microsemi

Implementation only supports output ports.

See Also

Constraint Support by Family

Constraint Entry Table

or output delays. For more information, refer to the create_clock ,

Set Load on Port

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set_max_delay (SDC)

SDC command; specifies the maximum delay for the timing paths. set_max_delay

delay_value

[-from

from_list

] [-to

to_list

]

Arguments

delay_value

Specifies a floating point number in nanoseconds that represents the required maximum delay value for specified paths.

•

If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.

•

If the path starting point has an input delay specified, the tool adds that delay value to the path delay.

•

If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.

•

If the ending point has an output delay specified, the tool adds that delay to the path delay.

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command specifies the required maximum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The tool automatically derives the individual maximum delay targets from clock waveforms and port input

, and set_output_delay

commands.

Examples

The following example sets a maximum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns: set_max_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a maximum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns: set_max_delay 3.8 -to [get_ports out*]

Microsemi Implementation Specifics

The –through option in the set_max_delay SDC command is not supported.

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See Also

Constraint Support by Family

Constraint Entry Table

or output delays. For more information, refer to the create_clock ,

Set Max Delay

set_external_check

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set_min_delay

SDC command; specifies the minimum delay for the timing paths. set_min_delay

delay_value

[-from

from_list

] [-to

to_list

]

Arguments

delay_value

Specifies a floating point number in nanoseconds that represents the required minimum delay value for specified paths.

•

If the path starting point is on a sequential device, the tool includes clock skew in the computed delay.

•

If the path starting point has an input delay specified, the tool adds that delay value to the path delay.

•

If the path ending point is on a sequential device, the tool includes clock skew and library setup time in the computed delay.

•

If the ending point has an output delay specified, the tool adds that delay to the path delay.

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command specifies the required minimum delay for timing paths in the current design. The path length for any startpoint in from_list to any endpoint in to_list must be less than delay_value.

The tool automatically derives the individual minimum delay targets from clock waveforms and port input

, and set_output_delay

commands.

Examples

The following example sets a minimum delay by constraining all paths from ff1a:CLK or ff1b:CLK to ff2e:D with a delay less than 5 ns: set_min_delay 5 -from {ff1a:CLK ff1b:CLK} -to {ff2e:D}

The following example sets a minimum delay by constraining all paths to output ports whose names start by “out” with a delay less than 3.8 ns: set_min_delay 3.8 -to [get_ports out*]

Microsemi Implementation Specifics

The –through option in the set_min_delay SDC command is not supported.

See Also

Constraint Support by Family

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Constraint Entry Table

set_external_check

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set_multicycle_path

SDC command; defines a path that takes multiple clock cycles. set_multicycle_path

ncycles

[-setup] [-hold] [-from

from_list

] [–through

through_list

] [-to

to_list

]

Arguments

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

False path information always takes precedence over multiple cycle path information. A specific maximum delay constraint overrides a general multiple cycle path constraint.

If you specify more than one object within one -through option, the path passes through any of the objects.

Examples

ncycles

-setup

-hold

Optional. Applies the cycle value for the hold check only. This option does not affect the setup check.

Note: If you do not specify "-setup" or "-hold", the cycle value is applied to the setup check and the default hold check is performed (

ncycles

-1).

-from

from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.

-through

through_list

Specifies a list of pins or ports through which the multiple cycle paths must pass.

-to

to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

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set_external_check

set_multicycle_path 2 -hold -from [get_clocks {ck1}]

Microsemi Implementation Specifics

• SDC allows multiple priority management on the multiple cycle path constraint depending on the scope of the object accessors. In Microsemi design implementation, such priority management is not supported. All multiple cycle path constraints are handled with the same priority.

See Also

Constraint Support by Family

Constraint Entry Table

Set Multicycle Path

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set_output_delay

SDC command; defines the output delay of an output relative to a clock. set_output_delay

delay_value

-clock

clock_ref

[–max] [–min] [–clock_fall]

output_list

Arguments

delay_value

-clock

clock_ref

Specifies the clock reference to which the specified output delay is related. This is a mandatory argument.

If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-min

Specifies that delay_value refers to the shortest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

Examples

The following example sets an output delay of 1.2ns for port OUT1 relative to the rising edge of CLK1: set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports OUT1]

Microsemi Implementation Specifics

• In SDC, the -clock is an optional argument that allows you to set the output delay for combinational designs. Microsemi Implementation currently requires this option.

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See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns all the input or inout ports of the design.

Set Output Delay

set_external_check

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Design Object Access Commands

Design object access commands are SDC commands. Most SDC constraint commands require one of these commands as command arguments.

Microsemi software supports the following SDC access commands:

Design Object Access Command

Cell

Clock

Net

get_cells

get_nets

get_clocks

Port

Input ports

Output ports

Registers

See Also

About SDC Files

get_ports

get_pins

all_inputs all_outputs

all_registers

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all_inputs

all_inputs

Arguments

• None

Supported Families

SmartFusion2, IGLOO2, SmartFusion, IGLOO, ProASIC3, Fusion

Exceptions

• None

Example

set_max_delay -from [all_inputs] -to [get_clocks ck1]

Microsemi Implementation Specifics

• None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns all the output or inout ports of the design.

set_external_check

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all_outputs

all_outputs

Arguments

• None

Supported Families

SmartFusion2, IGLOO2, SmartFusion, IGLOO, ProASIC3, Fusion

Exceptions

• None

Example

set_max_delay -from [all_inputs] -to [all_outputs]

Microsemi Implementation Specifics

None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns either a collection of register cells or register pins, whichever you

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set_external_check

all_registers

specify. all_registers [-clock

clock_name

] [-cells] [-data_pins ]

[-clock_pins] [-async_pins] [-output_pins]

Arguments

-clock

clock_name

Creates a collection of register cells or register pins in the specified clock domain.

-cells

Creates a collection of register cells. This is the default. This option cannot be used in combination with any other option.

-data_pins

Creates a collection of register data pins.

-clock_pins

Creates a collection of register clock pins.

-async_pins

Creates a collection of register asynchronous pins.

-output_pins

Creates a collection of register output pins.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command creates either a collection of register cells (default) or register pins, whichever is specified.

If you do not specify an option, this command creates a collection of register cells.

Exceptions

• None

Examples

set_max_delay 2 -from [all_registers] -to [get_ports {out}] set_max_delay 3 –to [all_registers –async_pins] set_false_path –from [all_registers –clock clk150] set_multicycle_path –to [all_registers –clock c* -data_pins

–clock_pins]

Microsemi Implementation Specifics

• None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns the cells (instances) specified by the pattern argument.

SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion 279

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get_cells

get_cells

pattern

Arguments

pattern

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command returns a collection of instances matching the pattern you specify. You can only use this command as part of a –from, -to, or –through argument for the following constraint exceptions: set_max delay, set_multicycle_path, and set_false_path design constraints.

Exceptions

None

Examples

set_max_delay 2 -from [get_cells {reg*}] -to [get_ports {out}] set_false_path –through [get_cells {Rblock/muxA}]

Microsemi Implementation Specifics

• None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns the specified clock.

280 SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion

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set_external_check

get_clocks

get_clocks

pattern

Arguments

pattern

Specifies the pattern to match to the SmartTime on which a clock constraint has been set.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

• If this command is used as a –from argument in maximum delay (set_max_path_delay), false path

( set_false_path

), and multicycle constraints ( set_multicycle_path ), the clock pins of all the registers

related to this clock are used as path start points.

• If this command is used as a –to argument in maximum delay (set_max_path_delay), false path

( set_false_path

), and multicycle constraints ( set_multicycle_path ), the synchronous pins of all the

registers related to this clock are used as path endpoints.

Exceptions

• None

Example

set_max_delay -from [get_ports datal] -to \

[get_clocks ck1]

Microsemi Implementation Specifics

None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns the specified pins.

SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion 281

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get_pins

get_pins

pattern

Arguments

pattern

Specifies the pattern to match the pins.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Exceptions

None

Example

create_clock -period 10 [get_pins clock_gen/reg2:Q]

Microsemi Implementation Specifics

• None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns the named nets specified by the pattern argument.

282 SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion

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set_external_check

get_nets

get_nets

pattern

Arguments

pattern

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Description

This command returns a collection of nets matching the pattern you specify. You can only use this

command as source objects in create clock ( create_clock ) or create generated clock

( create_generated_clock

) constraints and as -through arguments in set false path ( set_false_path ), set

minimum delay (set_min_delay), set maximum delay ( set_max_delay ), and set multicycle path

( set_multicycle_path ) constraints.

Exceptions

None

Examples

set_max_delay 2 -from [get_ports RDATA1] -through [get_nets {net_chkp1 net_chkqi}] set_false_path –through [get_nets {Tblk/rm/n*}] create_clcok -name mainCLK -per 2.5 [get_nets {cknet}]

Microsemi Implementation Specifics

None

See Also

Constraint Support by Family

Constraint Entry Table

Design object access command ; returns the specified ports.

SmartTime User's Guide - SmartFusion, IGLOO, ProSAIC3, and Fusion 283

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get_ports

get_ports

pattern

Argument

pattern

Specifies the pattern to match the ports. This is equivalent to the macros $in()[<pattern>] when used as – from argument and $out()[<pattern>] when used as –to argument or $ports()[<pattern>] when used as a – through argument.

Supported Families

SmartFusion2, IGLOO2, RTG4, SmartFusion, IGLOO, ProASIC3, Fusion

Exceptions

None

Example

create_clock -period 10[get_ports CK1]

Microsemi Implementation Specifics

None

See Also

Constraint Support by Family

Constraint Entry Table