A31 Datasheet

A31
Datasheet
Version 1.00
November 6, 2012
A31
Datasheet
REVISION HISTORY
Version
Date
1.00
Nov.6, 2012
Author
Description
Initial version
DECLARATION
THIS A31 DATASHEET IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER
TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE
WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE
COPYRIGHT OWNER.
THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE.
ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR
SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY
RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR
OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS
GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF
ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND,
INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION.
THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED
THIRD PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR
ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL
HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE.
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 1 / 43
A31
Datasheet
TABLE OF CONTENTS
REVISION HISTORY .............................................................................................................................1
DECLARATION ......................................................................................................................................1
TABLE OF CONTENTS .........................................................................................................................2
CHAPTER 1 OVERVIEW ....................................................................................................................3
CHAPTER 2 FEATURES ....................................................................................................................4
CHAPTER 3 BLOCK DIAGRAM ......................................................................................................10
CHAPTER 4 PIN ASSIGNMENT ...................................................................................................... 11
4.1.
BALL MAP.............................................................................................................................. 11
4.2.
PIN DIMENSION....................................................................................................................15
CHAPTER 5 PIN DESCRIPTION......................................................................................................16
5.1.
PIN CHARACTERISTICS ......................................................................................................16
5.2.
GPIO MULTIPLEXING FUNCTIONS ....................................................................................25
5.3.
DETAILED PIN/SIGNAL DESCRIPTION ..............................................................................30
5.4.
POWER/GND SIGNAL DESCRIPTION ................................................................................37
CHAPTER 6 ELECTRICAL CHARACTERISTICS ...........................................................................39
6.1.
ABSOLUTE MAXIMUM RATINGS ........................................................................................39
6.2.
RECOMMENDED OPERATING CONDITIONS ....................................................................39
6.3.
DC ELECTRICAL CHARACTERISTICS ...............................................................................40
6.4.
OSCILLATOR ELECTRICAL CHARACTERISTICS ..............................................................40
6.5.
POWER ON AND POWER OFF SEQUENCE ......................................................................41
A31 Datasheet V1.0
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PAGE 2 / 43
A31
Datasheet
1
OVERVIEW
A31 is a highly integrated mobile application processor designed to provide high performance solutions for
tablets, handsets, and smart TVs, etc.
It comes with a Quad-core Cortex-A7 CPU architecture that allows outstanding computing capability with
less power consumption, a powerful SGX544 MP2 GPU with eight logic cores, and a robust multimedia
processing system that capable of 4Kx2K video decoding, Blu-ray 3D and perfect compatibility for stream
media, etc.
A31 also features dual-channel 32bitx2 DRAM bus to provide wider bandwidth, and dual-channel NAND
flash to speed up Read/Write operations.
Besides, A31 provides a board range of peripheral interfaces. For example, it comes with display interfaces
such as HDMI, LCD RGB, MIPI DSI, and LVDS, image input interfaces such as CSI and MIPI CSI, and data
interfaces such as USB OTG, USB EHCI/OHCI, GB Ethernet, SDC, SDIO, etc.
When it comes to power efficiency, A31 features smart Power Consumption Management System to
dynamically adjust CPU frequency and voltage, DRAM Dynamic Frequency Scaling technology to
dynamically adjust DRAM frequency based on bandwidth requirements, and also supports Super Standby
Mode to lower the power consumption during system standby.
A31 Datasheet V1.0
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PAGE 3 / 43
A31
Datasheet
2
FEATURES
SYSTEM RESOURCES
QUAD CPU
 Quad
Cortex-A7 Subsystem
- ARM Version 7 ISA
TM
 Timer
Standard ARM instruction
set plus ThumbR2, JazellerR RCT
- 32KB instruction and 32KB data L1 cache for
each CPU
- Neon
TM
- 6 timers: clock source can be switched over
24M/32K for all timers, and external signals can
function as clock source for timer4/5
- 33-bit AVS counter
SIMD Coprocessor and VFPV4 for each
- 4 watchdogs to generate reset signal or
interrupts
CPU
 GIC
- TrustZone security technology
- Hardware Virtualization support
- Support 16 SGIs, 16 PPIs, and 128 SPIs
- Large Physical Address Extensions(LPAE)
- Support ARM architecture security extensions
- Debug and trace features
- Support ARM architecture virtualization
- One general timer for each CPU
 Shared
extensions
- Uni-processor and multiprocessor environments
1MB L2 cache
 HS-Timer
GRAPHIC ENGINE
- 4 channels
 3D
- Clock source fixed to AHB, and pre-scale
- POWER VR SGX 544 GPU
ranges from 1 to 16
- Support Open GL ES 2.0 /Open VG 1.1 / Open
CL 1.1 / DX 9.3 standard
- 56-bit counter, can be separated to 24-bit Hi-reg
and 32-bit Low-reg
 DMA
 2D
- 16 channels
- Support BLT / ROP2/3/4, scaling function with
4x4 taps and 32 phases
- Support burst length of 1/4/8
- Support 90/180/270 rotation degree,
mirror/alpha (plane and pixel alpha)/ color key
- Any format conversion：ARGB 8888/4444/1555,
RGB565, Mono 1/2/4/8 bpp, Palette 1/2/4/8 bpp
(input only), YUV 444/422/420
- Support data width of 8/16/32 bits
- Support linrear and IO address modes
- Configure information can be stored in
SRAM/external DRAM as command queue
- DMA channels can be paused during data
transfer if necessary
- Support command queue
A31 Datasheet V1.0
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PAGE 4 / 43
A31
Datasheet
MEMORY SUBSYSTEM
IMAGE SIGNAL PROCESSOR
 Internal
 Support
image mirror flip and rotation
- 32K in size
 Support
thumb image generation
- Support system boot from 8-bit NAND Flash,
 Support
two channels output
SPI Nor Flash (SPI0) and SD /TF /8-bit eMMC
 Support
valid picture size up to 4096x4096
(SDC0/2)
 Support
speed up to 250Mpixel/s
Boot ROM
- Support system code download via USB OTG
(USB0)
 ISP
for YCbCr input
- YCbCr gain and offset control
- DRC(dynamic range compression)
 Internal
SRAM
- Anti-flick detection statistics
- 32KB SRAM for CPU0 boot
- Histogram statistics
- 64KB SRAM for secure access only
 ISP
for RAW RGB input
- Black clamp with horizontal/vertical offset
 RTC
compensation
- Real time registers for second, minute, hour, day,
month and year
- Window capture
- Static/dynamic defect pixel correction
- Two alarms based on seconds and weeks
- Super lens shading correction
- 16 general purpose registers
- Super lens flare correction
- Color dependent gain and offset control
 CCU
- Anisotropic non-linear bayer interpolation with
- 11 programmable PLLs
false color suppression
- Programmable color correction
 External
SDRAM
- Programmable gamma correction
- Comply to LPDDR1/2, DDR2, DDR3 SDRAM
jedec specification
- DRC(dynamic range compression)
- RGB2YCbCr
- Support memory device power of
1.2v/1.35v/1.5v /1.8v
- Non-linear 2D sharpening
- Advanced contrast enhancement
- Support memory capacity up to 16G bits
- Advanced spatial (2D) de-noise filter
- Support two chip select signals (CS) for each
- Zone-based AE/AF/AWB statistics
channel
- Anti-flick detection statistics
- Support up to 2GB and 8 banks per channel
- Histogram statistics
- Support two SDRAM controllers
- Support LPDDR1/2, DDR2, DDR3 SDRAM
- Support 8/16/32 bits bus width per DRAM chip
VIDEO INPUT
 Support
4 lanes MIPI CSI, 1G bps per lane
(up to 12M pixels still image or 1080p@60fps
video)
 Support
A31 Datasheet V1.0
parallel 12bits CSI
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PAGE 5 / 43
A31
Datasheet
VIDEO ENGINE
DISPLAY ENGINE
 Decoder
 Support
 Video
and encoder can work at the same time
decoding
dual display paths
- Each path supports 4 movable and
- Picture size up to 4096x2304
size-adjustable layers
- Decoding speed up to 1920x1080@60fps
- Support multiple video formats: Mpeg1, Mpeg2,
- Layer size up to 8192x8192 pixels
 Ultra-scaling
Engine
Mpeg4 SP/ASP GMC, XVID, H.263 including
- 8 taps in horizontal and 4 taps in vertical
Sorenson Spark, H.264 BP/MP/HP, WMV7/8,
- Source image size from 8x4 to 8192x8192
WMV9/VC1 BP/MP/AP, VP6/8, AVS jizun,
- Destination image size from 8x4 to 8192x8192
JPEG/MJPEG
 Support
- Support tiled/YUV/YUV output format
 Video
Encoding
multiple image input formats
- Mono 1/2/4/8 bpp
- Palette 1/2/4/8 bpp
- H.264 HP: picture size up to 3840x2160
- 16/24/32 bpp color
- H.264 HP: speed up to 1920x1080@60fps
- YUV444/420/422/411
- H.264 HP: cyclic intra refresh
 Support
- H.264 HP: ROI windows
alpha blending, color key, gamma,
hardware cursor
- JPEG baseline: picture size up to 8192x8192
 Support
powerful video post processing
- Alpha blending
- De-interlacing
- Thumb generation
- Detail enhancement
- 4x2 scaling ratio: from 1/16 to 64 arbitrary
- Dynamic range control
non-integer ratio
- Color management
 3D
ANALOG AUDIO INPUT
 Support
display (with HDMI)
two audio ADC channels
- 96dBA SNR for ADC recording
DISPLAY OUTPUT
- 8KHz~ 48KHz ADC sample rate
 Analog
low-power loop from line-in/mic-in/ phone-in
to headphone/speaker/ earpiece outputs
 Accessory
 Five
content input/output format conversion and
button press detection
analog audio inputs
 Support
channel, resolution up to 4096x2160 @30fps
 Dual
flexible sync RGB/CPU/LVDS LCD interface,
up to 1080p@60fps
 Support
- Three differential microphone inputs
- Differential phone-in input
HDMI 1.4, speed up to 3G bps per
4 lanes MIPI DSI, 1G bps per lane,
resolution up to 1920x1200/1080p@60fps
 Support
dual display devices processing
- Stereo line-in input
 Support
low-noise digital MIC interface
 Excellent
digital audio process for ADC
- High pass filter and low latency decimation filter
for class voice
- Automatic gain control (AGC)
A31 Datasheet V1.0
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A31
Datasheet
ANALOG AUDIO OUTPUT
GPADC
 Two
 Support
audio DAC channels
 Stereo
capless headphone drivers
 Conversion
- Up to 100dBA SNR for DAC playback
 Low
- 8KHz~192KHz DAC sample rate
 3V
 Support
 Two
analog/digital volume control
low-noise analog microphone bias
 Dedicated
headphone/speaker/earpiece outputs,
single-ended or differential
differential phone-out
 Support
two mixers for different applications
- Output mixer for LINEINL/R, PHONEP/N,
MIC1P/N, MIC2P/N and stereo DAC output
- ADC record mixer for LINEINL/R, PHONEP/N,
MIC1P/N, MIC2P/N, MIC3P/N, stereo DAC output
 Excellent
digital audio process for DAC
- Pop suppression control
- Individual high pass filter/De-emphasis filter
- Support EQ equalization
- Soft volume control and soft mute
NAND FLASH
 Comply
to ONFI 2.3 & toggle 1.0
 Support
up to 2 channels
 Support
64 bits ECC per 512 bytes or 1024 bytes
 Support
8bits/16bits data bus width
 Support
1.8V/3.3V signal voltage
 Support
1K/2K/4K/8K/16K page size
 Support
up to 4 CE and 2 RB
 Support
hardware randomize engine
 Support
system boot from NAND flash
 Support
SLC/MLC/TLC NAND and EF-NAND
 Support
SDR/DDR NAND interface
 Two
rate up to 1MSPS
power consumption
power supply
 Analog
input range: 0V~3V
 On-chip
 Single
sample-and-hold function
or multiple input channel select mode
 Median
 Support
12-bit resolution
and averaging filter to reduce noise
SD/MMC
 Comply
to eMMC standard specification v4.5
 Comply
to SD physical layer specification v3.0
 Comply
to SDIO card specification v2.0
 Support
1/4/8bits bus width
 Support
HS/DS/SDR12/SDR25/SDR50 /HS200/
DDR50 bus mode
 Support
1.8V/3.3V adjustable power for signals
 Support
eMMC mandatory and alternative boot
operations
 Support
transmit clock up to100MHz
 Support
four independent SD/MMC/SDIO
controllers
 Support
SDSC/SDHC/SDXC/UHS-I/MMC/
RS-MMC Card
 Support
eMMC/iNand Flash
 Support
1GB/2GB/4GB/8GB/16GB/32GB/ 64GB
/128GB SD/MMC card
 Support
SDIO interrupt detection
 Support
build-in 64-byte FIFO for buffered read or
write operations
 Support
descriptor-based internal DMA controller
for efficient scatter and gather operations
256x32bits RAM for pipeline procession
 Support
internal DMA controller for data transfer
 Support
ECC corrected error bit information
report
 Support
NAND interrupt
A31 Datasheet V1.0
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A31
Datasheet
CONNECTIVITY
 USB2.0
 Transport
OTG
- Support High-Speed (HS, 480-Mbps),
Stream
- Support both SPI and SSI
Full-Speed (FS, 12-Mbps), and Low-Speed (LS,
- Support 64 channels PID filter
1.5-Mbps) in Host mode
- Support hardware PCR packet detection
- Support High-Speed (HS, 480-Mbps),
Full-Speed (FS, 12-Mbps) in Device mode
- Speed up to 150Mbps for both SPI and SSI
interface
- 8K SRAM for EP Buffer
- Support up to 10 user-configurable endpoints for
 GMAC
bulk , isochronous, control and interrupt
- Comply to IEEE 802.3-2002 standard
bi-directional transfers
- Support both full-duplex and half-duplex
operations
 USB
- Automatic CRC and pad generation controllable
EHCI/OHCI
- Two EHCI/OHCI-compliant Hosts
on a per-frame basis
- Options for automatic Pad/CRC stripping on
- One OHCI only FS Host
receive frames
- Programmable frame length to support standard
 LRADC
- Support sample rate up to 250Hz
or Jumbo Ethernet frames with size up to 16KB
- Support 6-bit resolution
- Support multiple flexible address filtering modes
- Support 0V ~2V voltage input
- Support 10/100/1000-Mbps transfer rates
- IEEE 802.3-compliant GMII/MII interface to
 Digital
communicate with an external Gigabit/Fast
Audio Interface
- Comply to industry standard I2S/PCM
Ethernet PHY
- Support 10/100/1000-Mbps data transfer rates
specification
- Two sets I2S/PCM interfaces for baseband and
RGMII interface to communicate with an
external Giga bit PHY
Bluetooth
- Support Master/Slave mode and full-duplex
- Optimization for packet-oriented DMA transfer
with frame delimiters
operation
- Support 8KHz ~192KHz audio sample rate
- DMA’s descriptor architecture (ring or chained),
- Support MCLK output for CODEC chips
allowing large blocks of data transfer with
- Support standard I2S, left-justified, right-justified,
minimum CPU intervention
8/16-bit linear sample, 8-bit u-law and a-law
- 4KB transmit FIFO for transmission packets
companded sample
- 16KB receive FIFO for reception packets
 CIR
 PWM
- A flexible receiver for IR remote controller
- 4 PWM outputs
- Support cycle mode and pulse mode
- The pre-scale ranges from 1 to 64
A31 Datasheet V1.0
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PAGE 8 / 43
A31
Datasheet
 UART
SECURITY SYSTEM
- Comply to industry-standard 16450/16550
UARTS specification
 Support AES,
 Support
- Support fully AMBA APB CPU interface
programmable operation
DES, 3DES, SHA-1, MD5
ECB, CBC, CNT modes for
AES/DES/3DES 128-bit, 192-bit and 256-bit key
size for AES
- Support 16-bit programmable baud rate and
dynamic modification
 160-bit
hardware PRNG with 192-bit seed
 Security
JTAG
- Support 2-wire serial communication
- Support 4-wire auto data flow communication
- Support 8-wire modem(data carrier equipment,
DCE) or data set
- Support up to 6 UART controllers
POWER MANAGEMENT
 Flexible
PLL clock generator and 32768Hz OSC
 Flexible
clock gate and module reset
 Support
DVFS for CPU frequency and voltage
adjustment
 SPI
 Support
- Master/Slave configurable
- Up to 4 independent SPI controllers, SPI0 with
only one CS signal for system boot, and
dynamic frequency adjustment for
external DRAM controller
 Support
standby mode
SPI1/2/3 with two CS signals
- Support dual-input and dual-output operation
PROCESS & PACKAGE
 FBGA
 TWI
- Up to 5 TWIs compliant with I2C protocol
 P2WI
18 x 18 x 1.4-mm
 40nm
- Support SCCB protocol
609 balls, 0.65mm ball pitch,
LP process
(Push-Pull TWI)
- Support speed up to 2MHz
 One
Wire Interface
- Support both standard One Wire protocol and
simple HDQ protocol
A31 Datasheet V1.0
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PAGE 9 / 43
A31
Datasheet
3
BLOCK DIAGRAM
Power
DVFS
32K I-Cache*4
User Interface
32K D-Cache*4
Core0
Core1
FPU
Keypad
IR
1MB L2 Cache
Core2
Core3
NEON SIMD
LRADC
RTP
System
GPU
CPU
Quad-Core
Thumb-2 Tech
Processing
Enhancement
Engine
Audio Codec
Video Engine
Display Engine
Memory
Security
Display Interface
USB OTG/2USB HOST
2-CH DDR3/LPDDR2
Security System
2-CH RGB LCD
GMAC/TS/4SD/MMC
2-CH DDR3L
S-JTAG
2-CH LVDS
4 SPI/5 TWI
2-CH Raw NAND
Camera Interface
HDMI 1.4
6 UART/2 PCM/2 I2S
eMMC NAND
ITU601
MIPI DSI
Interrupt Controller
SE0
SE1
RTC/Timer/HS-Timer
SE2
SE3
Clock System
SE4
SE5
16-CH DMA
SE6
SE7
Connectivity
MIPI CSI
Figure 3-1. A31 Block Diagram
A31 Datasheet V1.0
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PAGE 10 / 43
A31
Datasheet
4
PIN ASSIGNMENT
4.1.
BALL MAP
1
2
3
4
5
6
7
8
9
10
11
12
13
A
PC10
PC11
PC12
PC13
PC17
PC21
PC26
PH3
PH7
PH15
PH19
UBOOT
PE7
B
PC6
PC7
PC8
PC9
PC16
PC20
PC25
PH2
PH6
PH14
PH18
PH30
PE3
C
PF4
PF5
PC2
PC5
PC4
PC19
PC23
PH1
PH5
PH17
PH13
PE0
PE5
D
PF3
PC0
PC15
PC1
PC3
PC18
PC22
PH0
PH4
PH8
PH16
PH20
PE1
E
PF2
PF0
PF1
PC14
F
S0DQ8
S0DQ14
S0DQ2
S0DQ6
PC27
PC24
PH10
PH9
PH24
PH26
PH28
PH22
G
S0DQ12
S0DQ10
S0DQ0
S0DQ4
VCC-PF
VCC-PC
VCC-PC
PH11
PH12
PH23
PH21
PH25
H
S0DQS1B
S0DQS1
S0DQS0
S0DQS0B
S0ZQ
VCC-DRAM
J
S0DQ15
S0DQ13
S0DQ1
S0DQ7
S0ODT1
VCC-DRAM
VDD-GPU
VDD-GPU
VDD-GPU
GND
GND
K
S0DQ9
S0DQ11
S0DQ5
S0DQ3
S0CS1
VCC-DRAM
VDD-GPU
VDD-GPU
VDD-GPU
GND
GND
L
S0ODT
S0DQM1
S0DQM0
S0RAS
S0CKE1
VCC-DRAM
VDD-GPU
VDD-GPU
VDD-GPU
GND
GND
M
S0WE
S0BA0
S0CS
S0CAS
VCC-DRAM
VCC-DRAM
VDD-GPU
VDD-GPU
VDD-GPU
GND
GND
N
S0A5
S0A0
S0BA2
S0A3
VCC-DRAM
VCC-DRAM
GND
GND
GND
GND
GND
Figure 4-1
A31 Datasheet V1.0
A31 Ball Map (Upper Left)）
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PAGE 11 / 43
A31
Datasheet
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PE8
PE12
PE14
PG3
PG7
PG9
PG15
PG18
PB2
PA1
PA2
PA6
PA10
PA14
A
PE4
PE11
PE15
PG2
PG6
PG10
PG16
PB0
PB3
PB6
PA3
PA7
PA11
PA15
B
PE6
PE10
PE16
PG1
PG4
PG12
PG14
PB1
PB4
PA0
PA5
PA9
PA12
PA16
C
PE2
PE9
PE13
PG0
PG5
PG11
PG13
PG17
PB5
PB7
PA4
PA8
PA13
PA17
D
PA18
PA19
PA20
PA21
E
PA25
PA22
PA23
PA24
F
PA26
PA27
G
PH29
TEST
BOOTSEL0 JTAGSEL0
VCC-PE
PG8
VCC-PA
CPU-VDDF
B
GND
PH27
VCC-PH
BOOTSEL1 JTAGSEL1
VCC-PG
VCC-PB
VCC-PA
VCC-HP
TPX1
HPCOM HPCOMFB
CPU-VDDS
W
VRP
HPOUTL
HPOUTR
LINEINL
LINEINR
H
TPY2
VRA2
PHINP
PHINN
MIC1N
MIC1P
J
MIC2P
MIC2N
MBIAS
HBIAS
K
VCC-PH
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
AGND
GND
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU VDD-CPU
PM2
VRA1
GND
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU VDD-CPU
TPY1
AVCC
GND
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU VDD-CPU
MIC3P
GND
VDD-CPU
VDD-CPU
VDD-CPU
VDD-CPU
MIC3N
HPBP
Figure 4-2
A31 Datasheet V1.0
LINEOUT
LINEOUTL PHOUTP PHOUTN
R
L
PM3
LRADC1
LRADC0
PM0
PM1
M
TPX2
PM4
PM5
PM6
PM7
N
A31 Ball Map (Upper Right)）
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PAGE 12 / 43
A31
Datasheet
P
S0CK
S0A2
S0A7
S0A9
VCC-DRAM
VCC-DRAM
GND
GND
GND
GND
GND
R
S0CKB
S0CKE
S0A13
S0RST
S0VREF
VCC-DRAM
GND
GND
GND
GND
GND
T
S0BA1
S0A10
S0A12
S0A15
S0ADBG
VCC-DRAM
GND-DRAM GND-DRAM
GND
GND
VDD-SYS
U
S0A6
S0A11
S0A4
S0A1
S0DDBG0
VCC-DRAM
GND-DRAM GND-DRAM
GND
GND
VDD-SYS
V
S0DQ30
S0DQ26
S0A8
S0A14
S0DDBG1
GND-DRAM
VDD-DLL
GND-DRAM
GND
GND
VDD-SYS
W
S0DQ24
S0DQ28
S0DQ20
S0DQ18
GND-DRAM GND-DRAM
VDD-DLL
GND-DRAM
GND
GND
VDD-SYS
Y
S0DQS3 S0DQS3B
S0DQ22
S0DQ16
GND-DRAM GND-DRAM
AA
S0DQ29
S0DQ31
AB
S0DQ27
S0DQ25
S0DQ21
S0DQ23
AC
S0DQM3 S0DQM2
S0DQ19
S0DQ17
S0DQS2B S0DQS2
GND-DRAM GND-DRAM VCC-DRAM VCC-DRAM VCC-DRAM VCC-DRAM VCC-DRAM VCC-DRAM
S1VREF
S1ZQ
S1ODT1
S1CS1
S1CKE1
S1ADBG
S1DDBG0
S1DDBG1
AD
S1DQ6
S1DQ4
S1DQS0B
S1DQ5
S1DQ3
S1RAS
S1CAS
S1BA2
S1A2
S1RST
S1A10
S1A1
S1A14
AE
S1DQ2
S1DQ0
S1DQS0
S1DQ7
S1DQ1
S1DQM0
S1CS
S1BA0
S1A7
S1A13
S1A11
S1A6
S1A4
AF
S1DQ14
S1DQ10
S1DQS1
S1DQ11 S1DQ13
S1ODT
S1WE
S1A0
S1A9
S1CKE
S1A15
S1A8
S1DQ28
AG
S1DQ12
S1DQ8
S1DQ9
S1DQM1
S1A3
S1A5
S1CK
S1CKB
S1A12
S1BA1
S1DQ30
1
2
5
6
7
8
9
10
11
12
13
S1DQS1B S1DQ15
3
4
Figure 4-3
A31 Datasheet V1.0
A31 Ball Map (Lower Left)
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 13 / 43
A31
Datasheet
NMI
RESET
X32KI
PL0
P
PL3
PL2
PL1
PL4
X32KO
R
PL5
PL8
PD0
PD1
USB-DM0 USB-DP0
T
GND
PL6
PL7
PD2
PD3
USB-DM1 USB-DP1
U
VCC-PLL
VCC-PD
VCC-USB
PD4
PD5
USB-DM2 USB-DP2
V
VCC-HDMI
VCC-PD
VCC-PD
PD6
PD7
PD10
PD11
W
GND
GND
PD8
PD9
PD12
PD13
Y
GND
GND
GND
GND
GND
VDDQE
GND
GND
GND
GND
GND
VCC-PM
VCC-RTC
VDD-SYS
VDD-SYS
GND
GND
GND
VIO-RTC
VDD-SYS
VDD-SYS
GND
GND
GND
VDD-SYS
VDD-SYS
GND
VDD-SYS
VDD-SYS
VCC-MIPI
PLL-TEST GND-PLL
PLL-VRE
G
PLL-DV
VDD-CPUS VDD-CPUS
VCC-DRAM GND-DRAM GND-DRAM
GND-DRA
M
GND
GND
GND
GND
GND
PD21
PD20
PD14
PD15
AA
GND-DRAM GND-DRAM GND-DRAM
GND-DRA
M
GND
GND
GND
HSCL
HHPD
PD23
PD22
PD16
PD17
AB
PD24
HSDA
PD18
PD19
AC
S1DQ18
S1DQ16
S1DQS2
S1DQ17
S1DQ21
DSI-D0N
DSI_D1N
DSI-CKN
DSI-D2N
DSI-D3N
GND
PD27
PD26
PD25
AD
S1DQ22
S1DQ20
S1DQS2B
S1DQ23
S1DQ19
DSI-D0P
DSI-D1P
DSI-CKP
DSI-D2P
DSI-D3P
GND
GND
HTX2N
HTX2P
AE
S1DQ24
S1DQS3B
S1DQ31
S1DQ25
S1DQM2
CSI2-D0N CSI2_D1N CSI2-CKN CSI2-D2N CSI2-D3N X24MO HTXCP
HTX0P
HTX1P
AF
S1DQ26
S1DQS3
S1DQ29
S1DQ27
S1DQM3
CSI2-D0P CSI2-D1P CSI2-CKP CSI2-D2P CSI2-D3P
AG
14
15
16
17
18
19
Figure 4-4
A31 Datasheet V1.0
20
21
22
23
X24MI
HTXCN
HTX0N
HTX1N
24
25
26
27
A31 Ball Map (Lower Right)）
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 14 / 43
A31
Datasheet
4.2.
PIN DIMENSION
Figure 4-5. A31 Pin Dimension
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 15 / 43
A31
Datasheet
5
PIN DESCRIPTION
5.1.
PIN CHARACTERISTICS
Table 5-1 lists the characteristics of A31 609 Pins.
NOTES
1) Pin Name defines the names of pins. Note that a group of pins with similar meaning may be expressed in the form of [x:0],
and their corresponding ball is given in BALL# column in increasing order, for example, for pin group S0DQ[31:0], G3 is the
ball# of S0DQ0, J3 is the ball# of S0DQ1, F3 is the ball# of S0DQ2, etc;
2) Default Function defines the default function of each pin;
3) Type defines the signal direction: I (Input), O (Output), I/O(Input / Output), A (Analog), P (Power), G (Ground);
4) Default IO State defines the default IO state of each pin: DIS means disable;
5) Default Pull Up/Down defines the presence of an internal pull up or pull down resister. Unless otherwise specified, the pin
is default to be floating, and can be configured as pull up or pull down; Note that the NMI and RESET pins require no
additional pull-up resistors;
6) Buffer Strength defines drive strength of the associated output buffer. It is tested in the condition that VCC= 3.3V,
strength=MAX;
7) P[A:M] in Table 5-1 stands for GPIO [A:M]. For detailed auxiliary functions of each GPIO, please go to Section 5.2 GPIO
Multiplexing Functions section.
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
-
DRAM
I/O
DIS
Z
-
S0DQSB[3:0]
DRAM
I/O
DIS
Z
-
L3,L2,AC2,AC1
S0DQM[3:0]
DRAM
O
DIS
Z
-
P1
S0CK
DRAM
O
DIS
Z
-
R1
S0CKB
DRAM
O
DIS
Z
-
Ball#
Pin Name○1
Default
Function○2
G3,J3,F3,K4,G4,K3,F4,J4,
F1,K1,G2,K2,G1,J2,F2,J1,
Y4,AC4,W4,AC3,W3,AB3,
Y3,AB4,W1,AB2,V2,ABI,W
2,AA1,V1,AA2
S0DQ[31:0]
DRAM
H3,H2,AA4,Y1
S0DQS[3:0]
H4,H1,AA3,Y2
Type
3
○
Power Supply
DRAM
R2,L6
S0CKE[1:0]
DRAM
O
DIS
Z
-
N2,U4,P2,N4,U3,N1,U1,P3
,V3,P4,T2,U2,T3,R3,V4,T4
S0A[15:0]
DRAM
O
DIS
Z
-
M1
S0WE
DRAM
O
DIS
Z
-
M4
S0CAS
DRAM
O
DIS
Z
-
L4
S0RAS
DRAM
O
DIS
Z
-
M3,K6
S0CS[1:0]
DRAM
O
DIS
Z
-
M2,T1,N3
S0BA[2:0]
DRAM
O
DIS
Z
-
L1,J6
S0ODT[1:0]
DRAM
O
DIS
Z
-
R4
S0RST
DRAM
O
DIS
Z
-
H6
S0ZQ
DRAM
A
-
-
-
R6
S0VREF
DRAM
P
-
-
-
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
VCC_DRAM
PAGE 16 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
P
-
-
-
DRAM
G
-
-
-
VDD-DLL
DRAM
P
-
-
-
T6
S0ADBG
DRAM
A
-
-
-
U6
S0DDBG0
DRAM
A
-
-
-
Pin Name○1
Default
Function○2
VCC-DRAM
(20)
DRAM
GND-DRAM
(20)
V9,W9
Ball#
H7,J7,K7,L7,M6,M7,N6,N7
,P6,P7,R7,T7,U7,AA8,AA9
,AA10,AA11,AA12,AA13,A
A14
T9,T10,U9,U10,V7,V10,W
6,W7,W10,Y6,Y7,AA6,AA7
,AA15,AA16,AA17,AB14,A
B15,AB16,AB17
Type
3
○
V6
S0DDBG1
DRAM
A
-
-
-
AE2,AE5,AE1,AD5,AD2,A
D4,AD1,AE4,AG2,AG5,AF
2,AF4,AG1,AF5,AF1,AG4,
AD15,AD17,AD14,AE18,A
E15,AD18,AE14,AE17,AF1
4,AF17,AG14,AG17,AF13,
AG16,AG13,AF16
S1DQ[31:0]
DRAM
I/O
DIS
Z
-
AE3,AF3,AD16,AG15
S1DQS[3:0]
DRAM
I/O
DIS
Z
-
AD3,AG3,AE16,AF15
S1DQSB[3:0]
DRAM
I/O
DIS
Z
-
AE6,AG6,AF18,AG18
S1DQM[3:0]
DRAM
O
DIS
Z
-
AG9
S1CK
DRAM
O
DIS
Z
AG10
S1CKB
DRAM
O
DIS
Z
-
AF10,AB10
S1CKE[1:0]
DRAM
O
DIS
Z
-
AF8,AD12,AD9,AG7,AE13,
AG8,AE12,AE9,AF12,AF9,
AD11,AE11,AG11,AE10,A
D13,AE11
S1A[15:0]
DRAM
O
DIS
Z
-
AF7
S1WE
DRAM
O
DIS
Z
-
AD7
S1CAS
DRAM
O
DIS
Z
-
AD6
S1RAS
DRAM
O
DIS
Z
-
AE7,AB9
S1CS[1:0]
DRAM
O
DIS
Z
-
AE8,AG12,AD8
S1BA[2:0]
DRAM
O
DIS
Z
-
AF6,AB8
S1ODT[1:0]
DRAM
O
DIS
Z
-
AD10
S1RST
DRAM
O
DIS
Z
-
AB7
S1ZQ
DRAM
A
-
-
-
AB6
S1VREF
DRAM
P
-
-
-
AB11
S1ADGB
DRAM
A
-
-
-
AB12
S1DDBG0
DRAM
A
-
-
-
AB13
S1DDBG1
DRAM
A
-
-
-
C23
PA0
GPIO
I/O
DIS
Z
20
A23
PA1
GPIO
I/O
DIS
Z
20
A24
PA2
GPIO
I/O
DIS
Z
20
B24
PA3
GPIO
I/O
DIS
Z
20
D24
PA4
GPIO
I/O
DIS
Z
20
C24
PA5
GPIO
I/O
DIS
Z
20
A25
PA6
GPIO
I/O
DIS
Z
20
B25
PA7
GPIO
I/O
DIS
Z
20
Power Supply
VCC-DRAM
7
○
GPIO A
VCC-PA
A31 Datasheet V1.0
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PAGE 17 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
20
GPIO
I/O
DIS
Z
20
PA10
GPIO
I/O
DIS
Z
20
B26
PA11
GPIO
I/O
DIS
Z
20
C26
PA12
GPIO
I/O
DIS
Z
20
D26
PA13
GPIO
I/O
DIS
Z
20
A27
PA14
GPIO
I/O
DIS
Z
20
B27
PA15
GPIO
I/O
DIS
Z
20
C27
PA16
GPIO
I/O
DIS
Z
20
D27
PA17
GPIO
I/O
DIS
Z
20
E24
PA18
GPIO
I/O
DIS
Z
20
E25
PA19
GPIO
I/O
DIS
Z
20
E26
PA20
GPIO
I/O
DIS
Z
20
E27
PA21
GPIO
I/O
DIS
Z
20
F25
PA22
GPIO
I/O
DIS
Z
20
F26
PA23
GPIO
I/O
DIS
Z
20
F27
PA24
GPIO
I/O
DIS
Z
20
F24
PA25
GPIO
I/O
DIS
Z
20
G26
PA26
GPIO
I/O
DIS
Z
20
G27
PA27
GPIO
I/O
DIS
Z
20
F20,G20
VCC-PA
POWER
P
-
-
-
B21
PB0
GPIO
I/O
DIS
Z
20
C21
PB1
GPIO
I/O
DIS
Z
20
A22
PB2
GPIO
I/O
DIS
Z
20
B22
PB3
GPIO
I/O
DIS
Z
20
C22
PB4
GPIO
I/O
DIS
Z
20
Ball#
Pin Name○1
Default
Function○2
D25
PA8
GPIO
C25
PA9
A26
Type
3
○
Power Supply
7
○
GPIO B
D22
PB5
GPIO
I/O
DIS
Z
20
B23
PB6
GPIO
I/O
DIS
Z
20
D23
PB7
GPIO
I/O
DIS
Z
20
G19
VCC-PB
POWER
P
-
-
-
D2
PC0
GPIO
I/O
DIS
Z
20
D4
PC1
GPIO
I/O
DIS
Z
20
C3
PC2
GPIO
I/O
DIS
Z
20
D5
PC3
GPIO
I/O
DIS
Pull-up
20
C5
PC4
GPIO
I/O
DIS
Pull-up
20
VCC-PB
7
○
GPIO C
C4
PC5
GPIO
I/O
DIS
Z
20
B1
PC6
GPIO
I/O
DIS
Pull-up
20
B2
PC7
GPIO
I/O
DIS
Pull-up
20
B3
PC8
GPIO
I/O
DIS
Z
20
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
VCC-PC
PAGE 18 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
20
GPIO
I/O
DIS
Z
20
PC11
GPIO
I/O
DIS
Z
20
A3
PC12
GPIO
I/O
DIS
Z
20
A4
PC13
GPIO
I/O
DIS
Z
20
E4
PC14
GPIO
I/O
DIS
Z
20
D3
PC15
GPIO
I/O
DIS
Z
20
B5
PC16
GPIO
I/O
DIS
Z
20
A5
PC17
GPIO
I/O
DIS
Z
20
D6
PC18
GPIO
I/O
DIS
Z
20
C6
PC19
GPIO
I/O
DIS
Z
20
B6
PC20
GPIO
I/O
DIS
Z
20
A6
PC21
GPIO
I/O
DIS
Z
20
D7
PC22
GPIO
I/O
DIS
Z
20
C7
PC23
GPIO
I/O
DIS
Z
20
F7
PC24
GPIO
I/O
DIS
Z
20
B7
PC25
GPIO
I/O
DIS
Pull-up
20
A7
PC26
GPIO
I/O
DIS
Pull-up
20
F6
PC27
GPIO
I/O
DIS
Pull-up
20
G7,G8
VCC-PC
POWER
P
-
-
-
T24
PD0
GPIO
I/O
DIS
Z
20
T25
PD1
GPIO
I/O
DIS
Z
20
U24
PD2
GPIO
I/O
DIS
Z
20
U25
PD3
GPIO
I/O
DIS
Z
20
V24
PD4
GPIO
I/O
DIS
Z
20
V25
PD5
GPIO
I/O
DIS
Z
20
W24
PD6
GPIO
I/O
DIS
Z
20
W25
PD7
GPIO
I/O
DIS
Z
20
Y24
PD8
GPIO
I/O
DIS
Z
20
Y25
PD9
GPIO
I/O
DIS
Z
20
W26
PD10
GPIO
I/O
DIS
Z
20
W27
PD11
GPIO
I/O
DIS
Z
20
Y26
PD12
GPIO
I/O
DIS
Z
20
Y27
PD13
GPIO
I/O
DIS
Z
20
AA26
PD14
GPIO
I/O
DIS
Z
20
AA27
PD15
GPIO
I/O
DIS
Z
20
AB26
PD16
GPIO
I/O
DIS
Z
20
AB27
PD17
GPIO
I/O
DIS
Z
20
AC26
PD18
GPIO
I/O
DIS
Z
20
AC27
PD19
GPIO
I/O
DIS
Z
20
Ball#
Pin Name○1
Default
Function○2
B4
PC9
GPIO
A1
PC10
A2
Type
3
○
Power Supply
7
○
GPIO D
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
VCC-PD
PAGE 19 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
20
GPIO
I/O
DIS
Z
20
PD22
GPIO
I/O
DIS
Z
20
AB24
PD23
GPIO
I/O
DIS
Z
20
AC24
PD24
GPIO
I/O
DIS
Z
20
AD27
PD25
GPIO
I/O
DIS
Z
20
AD26
PD26
GPIO
I/O
DIS
Z
20
AD25
PD27
GPIO
I/O
DIS
Z
20
V21,W21,W22
VCC-PD
POWER
P
-
-
-
C12
PE0
GPIO
I/O
DIS
Z
20
D13
PE1
GPIO
I/O
DIS
Z
20
D14
PE2
GPIO
I/O
DIS
Z
20
B13
PE3
GPIO
I/O
DIS
Z
20
B14
PE4
GPIO
I/O
DIS
Z
20
C13
PE5
GPIO
I/O
DIS
Z
20
C14
PE6
GPIO
I/O
DIS
Z
20
A13
PE7
GPIO
I/O
DIS
Z
20
A14
PE8
GPIO
I/O
DIS
Z
20
D15
PE9
GPIO
I/O
DIS
Z
20
C15
PE10
GPIO
I/O
DIS
Z
20
B15
PE11
GPIO
I/O
DIS
Z
20
A15
PE12
GPIO
I/O
DIS
Z
20
D16
PE13
GPIO
I/O
DIS
Z
20
A16
PE14
GPIO
I/O
DIS
Z
20
B16
PE15
GPIO
I/O
DIS
Z
20
C16
PE16
GPIO
I/O
DIS
Z
20
F18
VCC-PE
POWER
P
-
-
-
E2
PF0
GPIO
I/O
DIS
Z
20
E3
PF1
GPIO
I/O
DIS
Z
20
E1
PF2
GPIO
I/O
DIS
Z
20
D1
PF3
GPIO
I/O
DIS
Z
20
Ball#
Pin Name○1
Default
Function○2
AA25
PD20
GPIO
AA24
PD21
AB25
Type
3
○
Power Supply
7
○
GPIO E
VCC-PE
7
○
GPIO F
C1
PF4
GPIO
I/O
DIS
Z
20
C2
PF5
GPIO
I/O
DIS
Z
20
G6
VCC-PF
POWER
P
-
-
-
D17
PG0
GPIO
I/O
DIS
Z
20
C17
PG1
GPIO
I/O
DIS
Z
20
B17
PG2
GPIO
I/O
DIS
Z
20
A17
PG3
GPIO
I/O
DIS
Z
20
VCC-PF
7
○
GPIO G
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
VCC-PG
PAGE 20 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
20
GPIO
I/O
DIS
Z
20
PG6
GPIO
I/O
DIS
Z
20
A18
PG7
GPIO
I/O
DIS
Z
20
F19
PG8
GPIO
I/O
DIS
Z
20
A19
PG9
GPIO
I/O
DIS
Z
20
B19
PG10
GPIO
I/O
DIS
Z
20
D19
PG11
GPIO
I/O
DIS
Z
20
C19
PG12
GPIO
I/O
DIS
Z
20
D20
PG13
GPIO
I/O
DIS
Z
20
C20
PG14
GPIO
I/O
DIS
Z
20
A20
PG15
GPIO
I/O
DIS
Z
20
B20
PG16
GPIO
I/O
DIS
Z
20
D21
PG17
GPIO
I/O
DIS
Z
20
A21
PG18
GPIO
I/O
DIS
Z
20
G18
VCC-PG
POWER
P
-
-
-
D8
PH0
GPIO
I/O
DIS
Z
20
C8
PH1
GPIO
I/O
DIS
Z
20
B8
PH2
GPIO
I/O
DIS
Z
20
A8
PH3
GPIO
I/O
DIS
Pull-up
20
D9
PH4
GPIO
I/O
DIS
Pull-up
20
C9
PH5
GPIO
I/O
DIS
Z
20
B9
PH6
GPIO
I/O
DIS
Pull-up
20
A9
PH7
GPIO
I/O
DIS
Pull-up
20
D10
PH8
GPIO
I/O
DIS
Z
20
F9
PH9
GPIO
I/O
DIS
Z
20
F8
PH10
GPIO
I/O
DIS
Z
20
G9
PH11
GPIO
I/O
DIS
Z
20
G10
PH12
GPIO
I/O
DIS
Z
20
C11
PH13
GPIO
I/O
DIS
Z
20
B10
PH14
GPIO
I/O
DIS
Z
20
A10
PH15
GPIO
I/O
DIS
Z
20
D11
PH16
GPIO
I/O
DIS
Z
20
C10
PH17
GPIO
I/O
DIS
Z
20
B11
PH18
GPIO
I/O
DIS
Z
20
A11
PH19
GPIO
I/O
DIS
Z
20
D12
PH20
GPIO
I/O
DIS
Z
20
G12
PH21
GPIO
I/O
DIS
Z
20
F13
PH22
GPIO
I/O
DIS
Z
20
G11
PH23
GPIO
I/O
DIS
Z
20
Ball#
Pin Name○1
Default
Function○2
C18
PG4
GPIO
D18
PG5
B18
Type
3
○
Power Supply
7
○
GPIO H
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
VCC-PH
PAGE 21 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
I/O
DIS
Z
20
GPIO
I/O
DIS
Z
20
PH26
GPIO
I/O
DIS
Z
20
G14
PH27
GPIO
I/O
DIS
Z
20
F12
PH28
GPIO
I/O
DIS
Z
20
F14
PH29
GPIO
I/O
DIS
Pull-up
20
B12
PH30
GPIO
I/O
DIS
Pull-up
20
G15，J14
VCC-PH
POWER
P
-
-
-
P27
PL0
GPIO
I/O
DIS
Pull-up
20
R25
PL1
GPIO
I/O
DIS
Pull-up
20
R24
PL2
GPIO
I/O
DIS
Z
20
R22
PL3
GPIO
I/O
DIS
Z
20
R26
PL4
GPIO
I/O
DIS
Z
20
T21
PL5
GPIO
I/O
DIS
Z
20
U21
PL6
GPIO
I/O
DIS
Z
20
U22
PL7
GPIO
I/O
DIS
Z
20
T22
PL8
GPIO
I/O
DIS
Z
20
M26
PM0
GPIO
I/O
DIS
Z
20
M27
PM1
GPIO
I/O
DIS
Z
20
K21
PM2
GPIO
I/O
DIS
Z
20
M22
PM3
GPIO
I/O
DIS
Z
20
N24
PM4
GPIO
I/O
DIS
Z
20
Ball#
Pin Name○1
Default
Function○2
F10
PH24
GPIO
G13
PH25
F11
Type
3
○
Power Supply
7
○
GPIO L
VCC-RTC
7
○
GPIO M
VCC-PM
N25
PM5
GPIO
I/O
DIS
Z
20
N26
PM6
GPIO
I/O
DIS
Z
20
N27
PM7
GPIO
I/O
DIS
Z
20
R19
VCC-PM
POWER
P
-
-
-
A12
UBOOT
-
I
-
Pull-up
-
VCC_PH
F17，G17
JTAG_SEL
-
I
-
Pull-up
-
VCC_PH
F16，G16
BOOT_SEL
-
I
-
Pull-up
-
VCC_PH
F15
TEST
-
I
-
Pull-down
-
VCC_PH
P19
VDDQE
-
P
-
-
-
P24
NMI
-
I/O
I
Z
-
VCC_RTC
P25
RESET
-
I
I
Z
-
VCC_RTC
AF26
HTX0P
-
A
-
-
-
AG26
HTX0N
-
A
-
-
-
AF27
HTX1P
-
A
-
-
-
AG27
HTX1N
-
A
-
-
-
System Control
HDMI
VCC-HDMI
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 22 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
A
-
-
-
-
A
-
-
-
HTXCP
-
A
-
-
-
AG25
HTXCN
-
A
-
-
-
W19
VCC-HDMI
-
P
-
-
-
AB21
HSCL
-
A
-
-
-
AC25
HSDA
-
A
-
-
-
AB22
HHPD
-
A
-
-
-
T26
USB_DM0
-
A
-
-
-
T27
USB_DP0
-
A
-
-
-
U26
USB_DM1
-
A
-
-
-
U27
USB_DP1
-
A
-
-
-
V22
VCC-USB
-
P
-
-
-
V26
USB_DM2
-
A
-
-
-
V27
USB_DP2
-
A
-
-
-
G22
TPX1
-
A
-
-
-
N22
TPX2
-
A
-
-
-
L21
TPY1
-
A
-
-
-
J21
TPY2
-
A
-
-
-
L27
PHOUTN
-
A
-
-
-
L26
PHOUTP
-
A
-
-
-
J24
PHINP
-
A
-
-
-
J25
PHINN
-
A
-
-
-
K27
HBIAS
-
A
-
-
-
K26
MBIAS
-
A
-
-
-
N21
MIC3N
-
A
-
-
-
M21
MIC3P
-
A
-
-
-
K25
MIC2N
-
A
-
-
-
K24
MIC2P
-
A
-
-
-
J26
MIC1N
-
A
-
-
-
J27
MIC1P
-
A
-
-
-
K22
VRA1
-
A
-
-
-
J22
VRA2
-
A
-
-
-
L22
AVCC
-
P
-
-
-
H22
VRP
-
P
-
-
-
L24
LINEOUTR
-
A
-
-
-
L25
LINEOUTL
-
A
-
-
-
H27
LINEINR
-
A
-
-
-
Ball#
Pin Name○1
Default
Function○2
AE27
HTX2P
-
AE26
HTX2N
AF25
Type
3
○
Power Supply
USB
VCC-USB
Touch Panel
AVCC
Audio Codec
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
AVCC
PAGE 23 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
A
-
-
-
-
G
-
-
-
HPOUTR
-
A
-
-
-
G25
HPCOMFB
-
A
-
-
-
G24
HPCOM
-
A
-
-
-
N19
HPBP
-
A
-
-
-
G21
VCC-HP
-
A
-
-
-
H24
HPOUTL
-
A
-
-
-
M25
LRADC0
-
A
-
-
-
M24
LRADC1
-
A
-
-
-
AD19
DSI-D0N
-
A
-
-
-
AE19
DSI-D0P
-
A
-
-
-
AD20
DSI-D1N
-
A
-
-
-
AE20
DSI-D1P
-
A
-
-
-
AD22
DSI-D2N
-
A
-
-
-
AE22
DSI-D2P
-
A
-
-
-
AD23
DSI-D3N
-
A
-
-
-
AE23
DSI-D3P
-
A
-
-
-
AD21
DSI-CKN
-
A
-
-
-
AE21
DSI-CKP
-
A
-
-
-
AF19
CSI-D0N
-
A
-
-
-
AG19
CSI-D0P
-
A
-
-
-
AF20
CSI-D1N
-
A
-
-
-
AG20
CSI-D1P
-
A
-
-
-
AF22
CSI-D2N
-
A
-
-
-
AG22
CSI-D2P
-
A
-
-
-
AF23
CSI-D3N
-
A
-
-
-
AG23
CSI-D3P
-
A
-
-
-
AF21
CSI-CKN
-
A
-
-
-
AG21
CSI-CKP
-
A
-
-
-
W17
VCC-MIPI
-
P
-
-
-
AG24
X24MI
-
A
-
-
-
AF24
X24MO
-
A
-
-
-
T19
RTC-VIO
-
P
-
-
-
R21
VCC-RTC
-
P
-
-
-
P26
X32KI
-
A
-
-
-
R27
X32KO
-
A
-
-
-
Ball#
Pin Name○1
Default
Function○2
H26
LINEINL
-
J19
AGND
H25
Type
3
○
Power Supply
LRADC
AVCC
MIPI DSI/CSI
VCC-MIPI
RTC
VCC-RTC
Clock
VCC-PLL
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 24 / 43
A31
Datasheet
Default
IO State○4
Default
Pull
Up/Down○5
Buffer
6
○
Strength
(mA)
A
-
-
-
-
P
-
-
-
PLL-VREG
-
P
-
-
-
V19
VCC-PLL
-
P
-
-
-
V18
GND-PLL
-
G
-
-
-
Ball#
Pin Name○1
Default
Function○2
V17
PLLTEST
-
W18
PLLDV
W17
Type
3
○
Power Supply
Power
P21，P22
VDD-CPUS
-
P
-
-
-
-
J15,J16,J17,J18,K15,K16,
K17,K18,K19,L15,L16,L17,
L18,L19,M15,M16,M17,M1
8,M19,N15,N16,N17,N18
VDD-CPU
(23)
-
P
-
-
-
-
F21
CPU-VDDFB
-
-
-
-
-
H21
CPU-VDDSW
-
-
-
-
-
J9,J10,J11,K9,K10,K11,L9,
L10,L11,M9,M10,M11
T13,T14,T15,U13,U14,U15
,V13,V14,V15,W13,W14,W
15
F22,J12,J13,K12,K13,K14,
L12,L13,L14,M12,M13,M1
4,N9,N10,N11,N12,N13,N1
4,P9,P10,P11,P12,P13,P1
4,P15,P16,P17,P18,R9,R1
0,R11,R12,R13,R14,R15,R
16,R17,R18,T11,T12,T16,
T17,T18,U11,U12,U16,U1
7,U18,U19,V11,V12,V16,
W11,W12,Y21,Y22,AA18,
AA19,AA20,AA21,AA22,A
B18,AB19,AB20,AD24,AE
24,AE25
VDD-GPU
(12)
-
P
-
-
-
-
VDD-SYS
(12)
-
P
-
-
-
-
GND(67)
-
G
-
-
-
-
Table 5-1 Pin Characteristics
5.2.
GPIO MULTIPLEXING FUNCTIONS
The following table provides a description of the A31 GPIO multiplexing functions.
Pin
Name
IO
Type
Default
IO State
PA0
I/O
DIS
PA1
I/O
DIS
PA2
I/O
DIS
PA3
I/O
DIS
PA4
I/O
DIS
PA5
I/O
DIS
I/O
DIS
PA7
I/O
DIS
PA8
I/O
DIS
PA9
I/O
DIS
PA10
I/O
PA11
I/O
DIS
PA12
I/O
DIS
PA6
Default
Function
GPIO
A31 Datasheet V1.0
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
ETXD0
LCD1_D0
UART1_DTR
-
ETXD1
LCD1_D1
UART1_DSR
-
ETXD2
LCD1_D2
UART1_DCD
-
ETXD3
LCD1_D3
UART1_RING
-
ETXD4
LCD1_D4
UART1_TX
-
ETXD5
LCD1_D5
UART1_RX
-
ETXD6
LCD1_D6
UART1_RTS
-
ETXD7
LCD1_D7
UART1_CTS
-
ETXCLK
LCD1_D8
ECLK_IN0
-
ETXEN
LCD1_D9
SDC3_CMD
SDC2_CMD
Z
EGTXCLK
LCD1_D10
SDC3_CLK
SDC2_CLK
Z
ERXD0
LCD1_D11
SDC3_D0
SDC2_D0
Z
ERXD1
LCD1_D12
SDC3_D1
SDC2_D1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Copyright © 2012 Allwinner Technology. All Rights Reserved.
Function 6
PA_EINT0
PA_EINT1
PA_EINT2
PA_EINT3
PA_EINT4
PA_EINT5
PA_EINT6
PA_EINT7
PA_EINT8
PA_EINT9
PA_EINT10
PA_EINT11
PA_EINT12
PAGE 25 / 43
A31
Datasheet
Pin
Name
Default
Function
IO
Type
Default
IO State
PA13
I/O
DIS
PA14
I/O
DIS
PA15
I/O
DIS
PA16
I/O
DIS
PA17
I/O
DIS
PA18
I/O
DIS
PA19
I/O
DIS
PA20
I/O
DIS
PA21
I/O
DIS
PA22
I/O
DIS
PA23
I/O
DIS
PA24
I/O
DIS
PA25
I/O
DIS
PA26
I/O
DIS
PA27
I/O
DIS
PB0
I/O
PB1
I/O
PB2
I/O
PB3
I/O
GPIO
PB4
I/O
PB5
I/O
PB6
I/O
PB7
I/O
PC0
I/O
PC1
I/O
PC2
I/O
PC3
I/O
PC4
I/O
PC5
I/O
PC6
I/O
PC7
I/O
PC8
I/O
GPIO
PC9
I/O
PC10
I/O
PC11
I/O
PC12
I/O
PC13
I/O
PC14
I/O
PC15
I/O
PC16
I/O
PC17
I/O
A31 Datasheet V1.0
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Z
ERXD2
Z
ERXD3
Z
ERXD4
Z
ERXD5
Z
ERXD6
Z
ERXD7
Z
ERXDV
Z
ERXCLK
Z
ETXERR
Z
ERXERR
Z
ECOL
Z
ECRS
Z
ECLKIN
Z
EMDC
Function 3
Function 4
Function 5
LCD1_D13
SDC3_D2
SDC2_D2
LCD1_D14
SDC3_D3
SDC2_D3
LCD1_D15
CLKA_OUT
LCD1_D16
DMIC_CLK
LCD1_D17
DMIC_DIN
LCD1_D18
CLKB_OUT
LCD1_D19
PWM3_P
LCD1_D20
PWM3_N
LCD1_D21
SPI3_CS0
LCD1_D22
SPI3_CLK
LCD1_D23
SPI3_MOSI
LCD1_CLK
SPI3_MISO
LCD1_DE
SPI3_CS1
Function 6
PA_EINT13
PA_EINT14
-
PA_EINT15
-
PA_EINT16
-
PA_EINT17
-
PA_EINT18
-
PA_EINT19
-
PA_EINT20
-
PA_EINT21
-
PA_EINT22
-
PA_EINT23
-
PA_EINT24
-
PA_EINT25
-
PA_EINT26
-
PA_EINT27
LCD1_HSYNC
CLKC_OUT
EMDIO
LCD1_VSYNC
ECLK_IN1
Z
I2S0_MCLK
UART3_CTS
MCS_MCLK1
-
PB_EINT0
Z
I2S0_BCLK
-
-
-
PB_EINT1
Z
I2S0_LRCK
-
-
-
PB_EINT2
Z
I2S0_DO0
-
-
-
PB_EINT3
Z
I2S0_DO1
UART3_RTS
-
-
PB_EINT4
Z
I2S0_DO2
UART3_TX
TWI3_SCK
-
PB_EINT5
Z
I2S0_DO3
UART3_RX
TWI3_SDA
-
PB_EINT6
Z
I2S0_DI
-
-
-
PB_EINT7
Z
NAND0_WE
SPI0_MOSI
-
-
-
Z
NAND0_ALE
SPI0_MISO
-
-
-
Z
NAND0_CLE
SPI0_CLK
-
-
-
Pull-up
NAND0_CE1
-
-
-
-
Pull-up
NAND0_CE0
-
-
-
-
Z
NAND0_RE
-
-
-
-
Pull-up
NAND0_RB0
SDC2_CMD
SDC3_CMD
-
-
Pull-up
NAND0_RB1
SDC2_CLK
SDC3_CLK
-
-
Z
NAND0_DQ0
SDC2_D0
SDC3_D0
-
-
Z
NAND0_DQ1
SDC2_D1
SDC3_D1
-
-
Z
NAND0_DQ2
SDC2_D2
SDC3_D2
-
-
Z
NAND0_DQ3
SDC2_D3
SDC3_D3
-
-
Z
NAND0_DQ4
SDC2_D4
SDC3_D4
-
-
Z
NAND0_DQ5
SDC2_D5
SDC3_D5
-
-
Z
NAND0_DQ6
SDC2_D6
SDC3_D6
-
-
Z
NAND0_DQ7
SDC2_D7
SDC3_D7
-
-
Z
NAND0_DQ8
NAND1_DQ0
-
-
Z
NAND0_DQ9
NAND1_DQ1
TRACE_DOUT
0
TRACE_DOUT
1
-
-
Z
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 26 / 43
A31
Datasheet
Pin
Name
Default
Function
IO
Type
PC18
I/O
PC19
I/O
PC20
I/O
PC21
I/O
PC22
I/O
PC23
I/O
PC24
I/O
PC25
I/O
PC26
I/O
PC27
I/O
PD0
I/O
PD1
I/O
PD2
I/O
PD3
I/O
PD4
I/O
PD5
I/O
PD6
I/O
PD7
I/O
PD8
I/O
PD9
I/O
PD10
I/O
PD11
I/O
PD12
I/O
PD13
I/O
GPIO
PD14
I/O
PD15
I/O
PD16
I/O
PD17
I/O
PD18
I/O
PD19
I/O
PD20
I/O
PD21
I/O
PD22
I/O
PD23
I/O
PD24
I/O
PD25
I/O
PD26
I/O
PD27
I/O
PE0
I/O
PE1
GPIO
PE2
A31 Datasheet V1.0
I/O
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Z
NAND0_DQ10
NAND1_DQ2
Z
NAND0_DQ11
NAND1_DQ3
Z
NAND0_DQ12
NAND1_DQ4
Z
NAND0_DQ13
NAND1_DQ5
Z
NAND0_DQ14
NAND1_DQ6
Z
NAND0_DQ15
NAND1_DQ7
Z
NAND0_DQS
Pull-up
Function 4
Function 5
Function 6
TRACE_DOUT
2
TRACE_DOUT
3
TRACE_DOUT
4
TRACE_DOUT
5
TRACE_DOUT
6
TRACE_DOUT
7
-
-
-
-
-
-
-
-
-
-
-
-
SDC2_RST
SDC3_RST
-
-
NAND0_CE2
-
-
-
-
Pull-up
NAND0_CE3
-
-
-
-
Pull-up
-
SPI0_CS0
-
-
-
Z
LCD0_D0
LVDS0_VP0
-
-
-
Z
LCD0_D1
LVDS0_VN0
-
-
-
Z
LCD0_D2
LVDS0_VP1
-
-
-
Z
LCD0_D3
LVDS0_VN1
-
-
-
Z
LCD0_D4
LVDS0_VP2
-
-
-
Z
LCD0_D5
LVDS0_VN2
-
-
-
Z
LCD0_D6
LVDS0_VPC
-
-
-
Z
LCD0_D7
LVDS0_VNC
-
-
-
Z
LCD0_D8
LVDS0_VP3
-
-
-
Z
LCD0_D9
LVDS0_VN3
-
-
-
Z
LCD0_D10
LVDS1_VP0
-
-
-
Z
LCD0_D11
LVDS1_VN0
-
-
-
Z
LCD0_D12
LVDS1_VP1
-
-
-
Z
LCD0_D13
LVDS1_VN1
-
-
-
Z
LCD0_D14
LVDS1_VP2
-
-
-
Z
LCD0_D15
LVDS1_VN2
-
-
-
Z
LCD0_D16
LVDS1_VPC
-
-
-
Z
LCD0_D17
LVDS1_VNC
-
-
-
Z
LCD0_D18
LVDS1_VP3
-
-
-
Z
LCD0_D19
LVDS1_VN3
-
-
-
Z
LCD0_D20
-
-
-
-
Z
LCD0_D21
-
-
-
-
Z
LCD0_D22
-
-
-
-
Z
LCD0_D23
-
-
-
-
Z
LCD0_CLK
-
-
-
-
Z
LCD0_DE
-
-
-
-
Z
LCD0_HSYNC
-
-
-
-
Z
LCD0_VSYNC
-
-
-
-
Z
CSI_PCLK
TS_CLK
-
-
PE_EINT0
Z
CSI_MCLK
TS_ERR
-
-
PE_EINT1
Z
CSI_HSYNC
TS_SYNC
-
-
PE_EINT2
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 27 / 43
A31
Datasheet
Pin
Name
Default
Function
IO
Type
PE3
I/O
PE4
I/O
PE5
I/O
PE6
I/O
PE7
I/O
PE8
I/O
PE9
I/O
PE10
I/O
PE11
I/O
PE12
I/O
PE13
I/O
PE14
I/O
PE15
I/O
PE16
I/O
PF0
I/O
PF1
I/O
PF2
I/O
GPIO
PF3
I/O
PF4
I/O
PF5
I/O
PG0
I/O
PG1
I/O
PG2
I/O
PG3
I/O
PG4
I/O
PG5
I/O
PG6
I/O
PG7
I/O
PG8
I/O
PG9
GPIO
I/O
PG10
I/O
PG11
I/O
PG12
I/O
PG13
I/O
PG14
I/O
PG15
I/O
PG16
I/O
PG17
I/O
PG18
I/O
PH0
I/O
GPIO
PH1
A31 Datasheet V1.0
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
Function 6
Z
CSI_VSYNC
TS_DVLD
-
-
PE_EINT3
Z
CSI_D0
UART5_TX
-
-
PE_EINT4
Z
CSI_D1
UART5_RX
-
-
PE_EINT5
Z
CSI_D2
UART5_RTS
-
PE_EINT6
Z
CSI_D3
UART5_CTS
-
-
PE_EINT7
Z
CSI_D4
TS_D0
-
-
PE_EINT8
Z
CSI_D5
TS_D1
-
-
PE_EINT9
Z
CSI_D6
TS_D2
-
-
PE_EINT10
Z
CSI_D7
TS_D3
-
-
PE_EINT11
Z
CSI_D8
TS_D4
-
-
PE_EINT12
Z
CSI_D9
TS_D5
-
-
PE_EINT13
Z
CSI_D10
TS_D6
-
-
PE_EINT14
Z
CSI_D11
TS_D7
-
-
PE_EINT15
Z
MCS_MCLK1
-
-
-
PE_EINT16
Z
SDC0_D1
-
JTAG_MS1
-
-
Z
SDC0_D0
-
JTAG_DI1
-
-
Z
SDC0_CLK
-
UART0_TX
-
-
Z
SDC0_CMD
-
JTAG_DO1
-
-
Z
SDC0_D3
-
UART0_RX
-
-
Z
SDC0_D2
-
JTAG_CK1
-
-
Z
SDC1_CLK
-
-
-
PG_EINT0
Z
SDC1_CMD
-
-
-
PG_EINT1
Z
SDC1_D0
-
-
-
PG_EINT2
Z
SDC1_D1
-
-
-
PG_EINT3
Z
SDC1_D2
-
-
-
PG_EINT4
Z
SDC1_D3
-
-
-
PG_EINT5
Z
UART2_TX
-
-
-
PG_EINT6
Z
UART2_RX
-
-
-
PG_EINT7
Z
UART2_RTS
-
-
-
PG_EINT8
Z
UART2_CTS
-
-
-
PG_EINT9
Z
TWI3_SCK
USB_DP3
-
-
PG_EINT10
Z
TWI3_SDA
USB_DM3
-
-
PG_EINT11
Z
SPI1_CS1
I2S1_MCLK
-
-
PG_EINT12
Z
SPI1_CS0
I2S1_BCLK
-
-
PG_EINT13
Z
SPI1_CLK
I2S1_LRCK
-
-
PG_EINT14
Z
SPI1_MOSI
I2S1_DIN
-
-
PG_EINT15
Z
SPI1_MISO
I2S1_DOUT
-
-
PG_EINT16
Z
UART4_TX
-
-
-
PG_EINT17
Z
UART4_RX
-
-
-
PG_EINT18
Z
NAND1_WE
-
-
-
Z
NAND1_ALE
-
-
-
Copyright © 2012 Allwinner Technology. All Rights Reserved.
TRACE_DOUT
8
TRACE_DOUT
9
PAGE 28 / 43
A31
Datasheet
Pin
Name
Default
Function
IO
Type
PH2
I/O
PH3
I/O
PH4
I/O
PH5
I/O
PH6
I/O
PH7
I/O
PH8
I/O
PH9
I/O
PH10
I/O
PH11
I/O
PH12
I/O
PH13
I/O
PH14
I/O
PH15
I/O
PH16
I/O
PH17
I/O
PH18
I/O
PH19
I/O
PH20
I/O
PH21
I/O
PH22
I/O
PH23
I/O
PH24
I/O
PH25
I/O
PH26
I/O
PH27
I/O
PH28
I/O
PH29
I/O
PH30
I/O
PL0
I/O
PL1
I/O
PL2
I/O
PL3
I/O
PL4
GPIO
I/O
PL5
I/O
PL6
I/O
PL7
I/O
PL8
I/O
PM0
I/O
PM1
GPIO
PM2
A31 Datasheet V1.0
I/O
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Z
NAND1_CLE
-
Pull-up
NAND1_CE1
-
Pull-up
NAND1_CE0
-
Z
NAND1_RE
-
Pull-up
NAND1_RB0
-
Pull-up
NAND1_RB1
-
Z
NAND1_DQS
-
Z
SPI2_CS0
Z
Function 5
Function 6
-
-
-
-
-
-
-
-
-
-
-
-
TRACE_CLK
-
-
JTAG_MS0
PWM1_P
-
-
SPI2_CLK
JTAG_CK0
PWM1_N
-
-
Z
SPI2_MOSI
JTAG_DO0
PWM2_P
-
-
Z
SPI2_MISO
JTAG_DI0
PWM2_N
-
-
Z
PWM0
-
-
-
-
Z
TWI0_SCK
-
-
-
-
Z
TWI0_SDA
-
-
-
-
Z
TWI1_SCK
-
-
-
-
Z
TWI1_SDA
-
-
-
-
Z
TWI2_SCK
-
-
-
-
Z
TWI2_SDA
-
-
-
-
Z
UART0_TX
-
-
-
-
Z
UART0_RX
-
-
-
-
Z
-
-
-
-
-
Z
-
-
-
-
-
Z
-
-
-
-
-
Z
-
-
-
-
-
Z
-
-
-
-
-
Z
-
-
-
-
-
Z
-
-
TRACE_CTL
-
-
Pull-up
NAND1_CE2
-
-
-
-
Pull-up
NAND1_CE3
-
-
-
-
Pull-up
S_TWI_SCK
S_P2WI_SCK
-
-
-
Pull-up
S_TWI_SDA
S_P2WI_SDA
-
-
-
Z
S_UART_TX
-
-
-
-
Z
S_UART_RX
-
-
-
-
Z
S_IR_RX
-
-
-
-
Z
S_PL_EINT0
S_JTAG_MS
-
-
-
Z
S_PL_EINT1
S_JTAG_CK
-
-
-
Z
S_PL_EINT2
S_JTAG_DO
-
-
-
Z
S_PL_EINT3
S_JTAG_DI
-
-
-
Z
S_PM_EINT0
-
-
-
-
Z
S_PM_EINT1
-
-
-
-
Z
S_PM_EINT2
1WIRE
-
-
-
Copyright © 2012 Allwinner Technology. All Rights Reserved.
Function 4
TRACE_DOUT
10
TRACE_DOUT
11
TRACE_DOUT
12
TRACE_DOUT
13
TRACE_DOUT
14
TRACE_DOUT
15
PAGE 29 / 43
A31
Datasheet
Pin
Name
Default
Function
IO
Type
PM3
I/O
PM4
I/O
PM5
I/O
PM6
I/O
PM7
I/O
Default
IO State
DIS
DIS
DIS
DIS
DIS
Default
Pull-up/
down
Function2
Function 3
Function 4
Function 5
Function 6
Z
S_PM_EINT3
-
-
-
-
Z
S_PM_EINT4
-
-
-
-
Z
S_PM_EINT5
-
-
-
-
Z
S_PM_EINT6
-
-
-
-
Z
S_PM_EINT7
RTC_CLKO
-
-
-
Table 5-2 Multiplexing Functions
5.3.
DETAILED PIN/SIGNAL DESCRIPTION
Following table describes the 609 pins of A31.
Pin/Signal Name
Description
Type
DRAM
S0DQ[31:0]
DRAM0 DQ[31:0]
I/O
S0DQS[3:0]
DRAM0 Data Strobe DQS[3:0]
I/O
S0DQSB[3:0]
DRAM0 DQSB[3:0]
I/O
S0DQM[3:0]
DRAM0 DQ Mask [3:0]
O
S0CK
DRAM0 Clock
O
S0CKB
DRAM0 CKB
O
S0CKE[1:0]
DRAM0 Clock Enable [1:0]
O
S0A[15:0]
DRAM0 data Address [15:0]
O
S0WE
DRAM0 Write Enable
O
S0CAS
DRAM0 Column Address Strobe
O
S0RAS
DRAM0 Row Address Strobe
O
S0CS[1:0]
DRAM0 Chip Select [1:0]
O
S0BA[2:0]
DRAM0 Bank Address [2:0]
O
S0ODT[1:0]
DRAM0 ODT Control [1:0]
O
S0RST
DRAM0 Reset
O
S0ZQ
DRAM0 ZQ Calibration
A
S0VREF
DRAM0 Reference Input
P
VCC-DRAM
DRAM Power Supply
P
GND-DRAM
DRAM Ground
G
VDD-DLL
DLL Power Supply
P
S0ADBG
DRAM0 Analog Debug
A
S0DDBG0
DRAM0 Digital DBG0
A
S0DDBG1
DRAM0 Digital DBG1
A
S1DQ[31:0]
DRAM1 DQ[31:0]
I/O
S1DQS[3:0]
DRAM1 Data Strobe DQS[3:0]
I/O
S1DQSB[3:0]
DRAM1 DQSB[3:0]
I/O
S1DQM[3:0]
DRAM1 DQ Mask [3:0]
O
S1CK
DRAM1 Clock
O
S1CKB
DRAM1 CKB
O
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 30 / 43
A31
Datasheet
Pin/Signal Name
Description
Type
S1CKE[1:0]
DRAM1 Clock Enable
O
S1A[15:0]
DRAM1 Address[15:0]
O
S1WE
DRAM1 Write Enable
O
S1CAS
DRAM1 Column Address Strobe
O
S1RAS
DRAM1 Row Address Strobe
O
S1CS[1:0]
DRAM1 Chip Select[1:0]
O
S1BA[2:0]
DRAM1 Bank Address[2:0]
O
S1ODT[1:0]
DRAM1 ODT control[1:0]
O
S1RST
DRAM1 Reset
O
S1ZQ
DRAM1 ZQ Calibration
A
S1VREF
DRAM1 Reference Input
P
S1ADGB
DRAM1 Analog Debug
A
S1DDBG0
DRAM1 Digital Debug0
A
S1DDBG1
DRAM1 Digital Debug1
A
GPIO
PA[27:0]
GPIO A Bit [27:0]
I/O
VCC-PA
GPIO A Power Supply
PB[7:0]
GPIO B Bit [7:0]
VCC-PB
GPIO B Power Supply
PC[27:0]
GPIO C Bit [27:0]
VCC-PC
GPIO C Power Supply
PD[27:0]
GPIO D Bit [27:0]
VCC-PD
GPIO D Power Supply
PE[16:0]
GPIO E Bit [16:0]
VCC-PE
GPIO E Power Supply
PF[5:0]
GPIO F Bit [5:0]
VCC-PF
GPIO F Power Supply
PG[18:0]
GPIO G Bit [18:0]
VCC-PG
GPIO G Power Supply
PH[30:0]
GPIO H Bit[30:0]
VCC-PH
GPIO H Power Supply
PL[8:0]
GPIO L Bit [8:0]
I/O
PM[7:0]
GPIO M Bit [7:0]
I/O
VCC-PM
GPIO M Power Supply
P
UBOOT
UBOOT
I
JTAG_SEL
JTAG Mode Select
I
BOOT_SEL
BOOT Mode Select
I
TEST
TEST Signal
I
VDDQE
eFUSE Power Supply
P
NMI
Non-Maskable Interrupt
RESET
RESET Signal
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
I/O
P
System Control
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
I/O
I
PAGE 31 / 43
A31
Datasheet
Pin/Signal Name
Description
Type
HDMI
HTX0P
TMSD Data 0 Positive
A
HTX0N
TMSD Data 0 Negative
A
HTX1P
TMSD Data 1 Positive
A
HTX1N
TMSD Data 1 Negative
A
HTX2P
TMSD Data 2 Positive
A
HTX2N
TMSD Data 2 Negative
A
HTXCP
TMSD Clock Positive
A
HTXCN
TMSD Clock Negative
A
VCC-HDMI
HDMI Power Supply
P
HSCL
HDMI DDC Clock
A
HSDA
HDMI DDC Data
A
HHPD
HDMI Hot Plug Detection signal
A
USB_DM0
USB DM0 Signal
A
USB_DP0
USB DP0 Signal
A
USB_DM1
USB DM1 Signal
A
USB_DP1
USB DP1 Signal
A
VCC-USB
USB Power Supply
P
USB_DM2
USB DM2 Signal
A
USB_DP2
USB DP2 Signal
A
USB_DP3
USB DP3 Signal
I/O
USB_DM3
USB DM3 Signal
I/O
USB
TP
TPX1
Touch Panel ADC Input
A
TPX2
Touch Panel ADC Input
A
TPY1
Touch Panel ADC Input
A
TPY2
Touch Panel ADC Input
A
PHOUTN
Phone Negative Output
A
PHOUTP
Phone Positive Output
A
PHINP
Phone Positive Input
A
PHINN
Phone Negative Input
A
HBIAS
Headphone Microphone Bias
A
MBIAS
Master Analog Microphone Bias
A
MIC3N
MIC Negative Input 3
A
MIC3P
MIC Positive Input 3
A
MIC2N
MIC Negative Input 2
A
MIC2P
MIC Positive Input 2
A
MIC1N
MIC Negative Input 1
A
MIC1P
MIC Positive Input 1
A
VRA1
Reference (1.5 V)
A
Audio Codec
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 32 / 43
A31
Datasheet
Pin/Signal Name
Description
Type
VRA2
Reference (1.5 V)
A
AVCC
Analog Power Supply
P
VRP
Reference (3.0 V)
P
LINEOUTR
LINE-OUT Right Channel Output
A
LINEOUTL
LINE-OUT Left Channel Output
A
LINEINR
LINE-IN Right Channel Input
A
LINEINL
LINE-IN Left Channel Input
A
AGND
Analog Ground
G
HPOUTR
Headphone Right Channel Output
A
HPCOMFB
Headphone Common Reference Feedback
A
HPCOM
Headphone Common Reference
A
HPBP
Headphone Bypass Output
A
VCC-HP
Headphone Power Supply
A
HPOUTL
Headphone Left Channel Output
A
LRADC0
LRADC input0
A
LRADC1
LRADC input1
A
DSI_D0N
MIPI DSI Data 0 Negative
A
DSI_D0P
MIPI DSI Data 0 Positive
A
DSI_D1N
MIPI DSI Data 1 Negative
A
DSI_D1P
MIPI DSI Data 1 Positive
A
DSI_D2N
MIPI DSI Data 2 Negative
A
DSI_D2P
MIPI DSI Data 2 Positive
A
DSI_D3N
MIPI DSI Data 3 Negative
A
DSI_D3P
MIPI DSI Data 3 Positive
A
DSI-CKN
MIPI DSI Clock Negative
A
DSI-CKP
MIPI DSI Clock Positive
A
CSI_DN0
MIPI CSI Data 0 Negative
A
CSI_DP0
MIPI CSI Data 0 Positive
A
CSI_DN1
MIPI CSI Data 1 Negative
A
CSI_DP1
MIPI CSI Data 1 Positive
A
CSI_DN2
MIPI CSI Data 2 Negative
A
CSI_DP2
MIPI CSI Data 2 Positive
A
CSI_DN3
MIPI CSI Data 3 Negative
A
CSI_DP3
MIPI CSI Data 3 Positive
A
CSI-CKN
MIPI CSI Clock Negative
A
CSI-CKP
MIPI CSI Clock Positive
A
VCC-MIPI
MIPI Power Supply
P
RTC-VIO
RTC Power
P
VCC-RTC
RTC Power Supply
P
LRADC
MIPI DSI/CSI
RTC
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 33 / 43
A31
Datasheet
Pin/Signal Name
Description
Type
Clock
X24MI
Clock Input Of 24MHz Crystal
A
X24MO
Clock Output Of 24MHz Crystal
A
X32KI
Clock Input Of 32768Hz Crystal
A
X32KO
Clock Output Of 32768Hz Crystal
A
PLLTEST
PLL Test Signal
A
PLLDV
PLL Power
P
PLL-VREG
PLL Power
P
VCC-PLL
PLL Power Supply
P
GND-PLL
PLL Ground
G
SDCx_CMD
SDx/MMCx/SDIOx Command Signal
I/O
SDCx_CLK
SDx/MMCx/SDIOx Clock
I/O
SDC0_D[3:0]
SD0/MMC0/SDIO0 Data [3:0]
I/O
SDC1_D[3:0]
SD1/MMC1/SDIO1 Data [3:0]
I/O
SDC2_D[7:0]
SD2/MMC2/SDIO2 Data [7:0]
I/O
SDC3_D[7:0]
SD3/MMC3/SDIO3 Data [7:0]
I/O
SDC2_RST
SD2/MMC2/SDIO2 Reset Signal
I/O
SDC3_RST
SD3/MMC3/SDIO3 Reset Signal
I/O
NAND0_DQ[15:0]
NAND Flash0 Data Bit [15:0]
I/O
NAND1_DQ[7:0]
NAND Flash1 Data Bit [7:0]
I/O
NANDx_DQS
NADN Flash Data Strobe
I/O
NANDx_WE
NAND Flash Write Enable
I/O
NANDx_RE
NAND Flash chip Read Enable
I/O
NANDx_ALE
NAND Flash Address Latch Enable
I/O
NANDx_CLE
NAND Command Latch Enable
I/O
NANDx_CE[3:0]
NAND Flash Chip Select [3:0]
I/O
NANDx_RB[1:0]
NAND Flash Ready/Busy Bit
I/O
S_JTAG_MS
N/A
I/O
S_JTAG_CK
N/A
I/O
S_JTAG_DO
N/A
I/O
S_JTAG_DI
N/A
I/O
JTAG_MS[1:0]
N/A
I/O
JTAG_CK[1:0]
N/A
I/O
JTAG_DO[1:0]
N/A
I/O
JTAG_DI[1:0]
N/A
I/O
TRACE_DOUT[15:0]
ETM TRACE Port Data Output
I/O
TRACE_CLK
ETM TRACE Port Clock
I/O
TRACE_CTL
ETM TRACE Port Control
I/O
SD (x=[3:0])
NAND (x=[1:0])
JTAG
ETM TRACE
A31 Datasheet V1.0
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A31
Datasheet
Pin/Signal Name
Description
Type
Interrupt
PA_EINT[27:0]
GPIO A Interrupt
I/O
PB_EINT[7:0]
GPIO B Interrupt
I/O
PE_EINT[16:0]
GPIO E Interrupt
I/O
S_PL_EINT[3:0]
GPIO L Interrupt
I/O
S_PM_EINT[7:0]
GPIO M Interrupt
I/O
PWMx_P
PWM Output Positive
I/O
PWMx_N
PWM Output Negative
I/O
PWM0
PWM 0
I/O
IR Data Receive
I/O
LCD0_D[23:0]
LCD0 Data Bit [23:0]
I/O
LCD1_D[23:0]
LCD1 Data Bit [23:0]
I/O
LCDx_CLK
LCD Clock signal
I/O
LCDx_DE
LCD Data Enable
I/O
LCDx_HSYNC
LCD Horizontal SYNC
I/O
LCDx_VSYNC
LCD Vertical SYNC
I/O
PWM (x=[3:1])
IR
S_IR_RX
LCD (x=[1:0])
LVDS
LVDS0_VP[3:0]
LVDS Channel 0 Data Positive Signal Output[3:0]
A
LVDS0_VN[3:0]
LVDS Channel 0 Data Negative Signal Output[3:0]
A
LVDS0_VPC
LVDS Channel 0 Clock Positive Signal Output
A
LVDS0_VNC
LVDS Channel 0 Clock Negative Signal Output
A
LVDS1_VP[3:0]
LVDS Channel 1 Data Positive Signal Output[3:0]
A
LVDS1_VN[3:0]
LVDS Channel 1 Data Negative Signal Output[3:0]
A
LVDS1_VPC
LVDS Channel 1 Clock Positive Signal Output
A
LVDS1_VNC
LVDS Channel 1 Clock Negative Signal Output
A
I2S (x=[1:0])
I2Sx_MCLK
I2S Master Clock (system clock)
I/O
I2Sx_BCLK
I2S Bit Clock
I/O
I2Sx_LRCK
I2S Left/Right Channel Select Clock
I/O
I2S1_DIN
I2S1 Data Input
I/O
I2S1_DOUT
I2S1 Data Output
I/O
I2S0_DO[3:0]
I2S0 Data Output
I/O
I2S0_DI
I2S0 Data Input
I/O
CSI_PCLK
CSI Pixel Clock
I/O
CSI_MCLK
CSI Master Clock
I/O
CSI_HSYNC
CSI Horizontal SYNC
I/O
CSI_VSYNC
CSI Vertical SYNC
I/O
CSI_D[11:0]
CSI Data bit [11:0]
I/O
CSI
A31 Datasheet V1.0
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A31
Datasheet
Pin/Signal Name
MCS_MCLK1
Description
Type
Master Clock for MIPI CSI
I/O
TS_CLK
Transport Stream Clock
I/O
TS_ERR
Transport Stream Error Indicate
I/O
TS_SYNC
Transport Stream SYNC
I/O
TS_DVLD
Transport Stream Valid Signal
I/O
TS_D[7:0]
Transport Stream Data
I/O
ETXD[7:0]
EMAC MII Transmit Data Nibble Data Bit[7:0]
I/O
ETXCLK
EMAC MII Transmit Clock
I/O
ETXEN
EMAC MII Transmit Enable
I/O
EGTXCLK
GMAC TCLK signal
I/O
ERXD[7:0]
EMAC MII Receive Data Nibble Data Bit[7:0]
I/O
ERXDV
EMAC MII Receive Data Valid
I/O
ERXCLK
EMAC MII Receive Clock
I/O
ETXERR
EMAC MII Transmit Error
I/O
ERXERR
EMAC MII Receive Error
I/O
ECOL
EMAC MII Collision Detect
I/O
ECRS
EMAC MII Carrier Sense
I/O
ECLKIN
EMAC Clock Input
I/O
EMDC
EMAC MII Management Data Clock
I/O
EMDIO
EMAC MII Management Data Input/Output
I/O
ECLK_IN0
EMAC Clock Input
I/O
ECLK-IN
EMAC Clock Input
I/O
SPI0_CS0
SPI0 Chip Select signal 0
SPI1_CS[1:0]
SPI1 Chip Select signal[1:0]
I/O
I/O
SPI2_CS0
SPI2 Chip Select signal 0
SPI3_CS[1:0]
SPI3 Chip Select signal [1:0]
SPIx_CLK
SPI Clock signal
I/O
SPIx_MOSI
SPI Master data Out, Slave data In
I/O
SPIx_MISO
SPI Master data In, Slave data Out
I/O
UART1_DTR
UART Data Terminal Ready
I/O
UART1_DSR
UART Data Set Ready
I/O
UART1_DCD
UART Data Carrier Detect
I/O
UART1_RING
UART RING indicator
I/O
UARTx_CTS
UART Data Clear To Send
I/O
UARTx_RTS
UART Data Request To Send
I/O
UARTx_TX[5:0]
UART Data Transmit
I/O
UARTx_RX[5:0]
UART Data Receive
I/O
S_UART_TX
UART Data Transmit
I/O
TS
EMAC
SPI (x=[3:0])
I/O
I/O
UART (x=[5:0])
A31 Datasheet V1.0
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A31
Datasheet
Pin/Signal Name
S_UART_RX
Description
Type
UART Data Receive
I/O
TWIx_SCK
TWI Serial Clock Signal
I/O
TWIx_SDA
TWI Serial Data Signal
I/O
S_TWI_SCK
TWI Serial Clock Signal
I/O
S_TWI_SDA
TWI Serial Data Signal
I/O
S_P2WI_SCK
P2WI Serial Clock Signal
I/O
S_P2WI_SDA
P2WI Serial Data Signal
I/O
CLKA_OUT
CLOCK OUT A
I/O
CLKB_OUT
CLOCK OUT B
I/O
CLKC_OUT
CLOCK OUT C
I/O
CK32KO
32K Crystal Clock Output
I/O
RTC_CLKO
RTC Clock Output
I/O
1WIRE
One WIRE signal
Table 5-3 Detailed Pin Description
I/O
TWI (x=[3:0])
Others
5.4.
POWER/GND SIGNAL DESCRIPTION
Note
1) VRP/VRA1/VRA2 are output type, and are not for third party development use.
Signal Name
Description
Ball#
HDMI
VCC-HDMI
HDMI Power Supply
(2.7V~3.3V)
W19
USB Power
VCC-USB
USB Power Supply
(2.7V~3.3V)
V22
Clock
VCC-PLL
PLL Power Supply (2.7V~3.3V)
V19
GND-PLL
PLL Ground
V18
MIPI
VCC-MIPI
MIPI Power Supply
(2.7V~3.3V)
W17
IO Power
VCC-PA
Power Supply for GPIO A (1.8V-3.3V)
VCC-PB
Power Supply for GPIO B
(1.8V-3.3V)
F20,G20
G19
VCC-PC
Power Supply for GPIO C
(1.8V-3.3V)
G7,G8
VCC-PD
Power Supply for GPIO D
(1.8V-3.3V)
V21,W21,W22
VCC-PE
Power Supply for GPIO E
(1.8V-3.3V)
F18
VCC-PF
Power Supply for GPIO F
(1.8V-3.3V)
G6
VCC-PG
Power Supply for GPIO G
(1.8V-3.3V)
G18
VCC-PH
Power Supply for GPIO H
(1.8V-3.3V)
G15，J14
VCC-PM
Power Supply for GPIO M (1.8V-3.3V)
R19
RTC Power Supply
R21
RTC
VCC_RTC
(3.0V)
DRAM Power
A31 Datasheet V1.0
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A31
Datasheet
Signal Name
Description
VCC-DRAM
DRAM Power Supply
VDD-DLL
DLL Power Supply
GND-DRAM
DRAM Ground
(1.2V-2.5V)
(1.1V)
Ball#
H7,J7,K7,L7,M6,M7,N6,N7,P6,P
7,R7,T7,U7,AA8,AA9,AA10,AA1
1,AA12,AA13,AA14
V9,W9
T9,T10,U9,U10,V7,V10,W6,W7,
W10,Y6,Y7,AA6,AA7,AA15,AA1
6,AA17,AB14,AB15,AB16,AB17
Audio Codec
AVCC
Analog Power Supply (3.0V)
L22
AGND
Analog Ground
J19
1
VRP○
VRP=3.0V, output;
H22
1
VRA1○
VRA1=1.5V,output;
K22
1
VRA2○
VRA2=1.5V,output;
J22
VCC-HP
Headphone Power Supply (3.3V)
G21
CPU&GPU
VDD-CPU
Power Supply for CPU (1.1V)
VDD-GPU
Power Supply for GPU
(1.1V)
J15,J16,J17,J18,K15,K16,K17,K
18,K19,L15,L16,L17,L18,L19,M
15,M16,M17,M18,M19,N15,N16,
N17,N18
J9,J10,J11,K9,K10,K11,L9,L10,
L11,M9,M10,M11
System
VDD-SYS
Power Supply for the system (1.1V)
VDD-CPUS
Power Supply for the system (1.1V)
T13,T14,T15,U13,U14,U15,V13,
V14,V15,W13,W14,W15
P21，P22
eFUSE
VDDQE
eFuse Power Supply
P19
Ground
GND
Ground
F22,J12,J13,K12,K13,K14,L12,L
13,L14,M12,M13,M14,N9,N10,N
11,N12,N13,N14,P9,P10,P11,P
12,P13,P14,P15,P16,P17,P18,R
9,R10,R11,R12,R13,R14,R15,R
16,R17,R18,T11,T12,T16,T17,T
18,U11,U12,U16,U17,U18,U19,
V11,V12,V16,W11,W12,Y21,Y2
2,AA18,AA19,AA20,AA21,AA22,
AB18,AB19,AB20,AD24,AE24,A
E25
Table 5-4 A31 Power/Ground Signal Description
A31 Datasheet V1.0
Copyright © 2012 Allwinner Technology. All Rights Reserved.
PAGE 38 / 43
A31
Datasheet
6
ELECTRICAL CHARACTERISTICS
6.1.
ABSOLUTE MAXIMUM RATINGS
Prolonged exposure to absolute maximum ratings (as shown in Table 6-1) may reduce device reliability.
Functional operation at these maximum ratings is not implied.
Symbol
II/O
Parameter
Min
Max
Unit
/
/
mA
In/Out current for input and output
/
/
VESD
N/A
N/A
N/A
Power supply for I/O
/
3.6
V
Power supply for Internal Digital Logic
/
1.32
V
VESD
ESD stress voltage
VCC
VDD
HBM(human body mode)
CDM(charged device mode)
AVCC
Power supply for Analog Part
3.0
3.0
V
VCC-DRAM
Power supply for DRAM Part
1.2
2.5
V
VCC-USB
/
3.3
V
Power supply for LRADC
3.0
3.0
V
VCC-HP
Power supply for Headphone
3.3
3.3
V
VDD-DLL
Power supply for DLL
1.1
1.1
V
VCC-PLL
Power supply for PLL
2.7
3.3
V
VDD-CPU
Power Supply for CPU
0.7
1.32
V
VDD-GPU
Power Supply for GPU
0.7
1.32
V
/
125
°C
VCC-LRADC
Tg
Power supply for USB PHY
Storage Temperature
Table 6-1
6.2.
Absolute Maximum Ratings
RECOMMENDED OPERATING CONDITIONS
All A31 modules are used under the operating Conditions contained in Table 6-2.
Symbol
Ta
VCC
AVCC
VCC-DRAM
VCC-USB
VCC-LRADC
Parameter
Ambient Operating Temperature
Min
Typ
Max
Unit
(Commercial)
-20
/
+70
°C
(Extended)
N/A
N/A
N/A
°C
Power Supply for the IO
/
3.3
/
V
Power Supply For Analog Part
/
3.0
/
V
Power Supply For DRAMC
1.2
1.5/1.8
2.5
V
Power Supply For USB PHY
2.8
3.3
3.3
V
Power Supply for LRADC
3.0
3.0
3.0
V
VCC-HP
Power Supply For Headphone
3.3
3.3
3.3
V
VDD-DLL
Power Supply For DLL
1.1
1.1
1.1
V
VCC-PLL
Power supply for OSC24M/PLLs
/
3.0
/
V
VCC-RTC
Power Supply For RTCLDO/LOSC/RCOSC
2.8
3.0
3.3
V
A31 Datasheet V1.0
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PAGE 39 / 43
A31
Datasheet
VDD-RTC
Power Supply For RTC/Alarm
0.7
1.1
1.32
V
VDD-SYS
Power supply for VDD_SYS
0.7
1.1
1.32
V
VDD-CPU
Power Supply for CPU
0.7
1.1
1.32
V
VDD-GPU
Power supply for GPU
0.7
1.1
1.32
V
0
0
0
V
Min
Typ
Max
Unit
VCC = 3.3V
2.1
3.3
3.6
V
VCC = 1.8V
1.2
1.8
3.6
V
VCC = 3.3V
-0.3
0
0.7
V
GND
Ground
Table 6-2
6.3.
Recommended Operating Conditions
DC ELECTRICAL CHARACTERISTICS
Table 6-3 summarizes the DC electrical characteristics of A31.
Symbol
Parameter
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
IIH
High-Level Input Current
IIL
Low-Level Input Current
Test Conditions
VCC = 1.8V
-0.3
0
0.6
V
VCC = 3.3V, VI = 3.3V
TBD
TBD
TBD
uA
VCC = 1.8V, VI = 1.8V
TBD
TBD
TBD
uA
VCC = 3.3V, VI = 0V
TBD
TBD
TBD
uA
VCC = 1.8V, VI = 0V
TBD
TBD
TBD
uA
VCC = 3.3V
2.7
3.3
N/A
V
VCC = 1.8V
1.5
1.8
N/A
V
VCC = 3.3V
N/A
0
0.4
V
VCC = 1.8V
N/A
0
0.3
V
VCC = 3.3V
TBD
TBD
TBD
uA
VCC = 1.8V
TBD
TBD
TBD
uA
VOH
High-Level Output Voltage
VOL
Low-Level Output Voltage
IOZ
Tri-State Output Leakage Current
CIN
Input Capacitance
N/A
N/A
5
pF
Output Capacitance
N/A
N/A
5
pF
COUT
Table 6-3
6.4.
DC Electrical Characteristics
OSCILLATOR ELECTRICAL CHARACTERISTICS
The A31 clock control module includes 11PLLs, a main oscillator, an on-chip RC oscillator of 466.9KHz
~867.1KHz, and a 32768Hz low power oscillator.
The 24.000MHz frequency is used to generate the main source clock for PLL and the main digital blocks, and
the 32768Hz oscillator is used only to provide a low power accurate reference for RTC.
24MHz Oscillator Characteristics
Table 6-4 lists the 24MHz crystal specifications.
Symbol
1/(tCPMAIN)
tST
PON
CL
A31 Datasheet V1.0
Parameter
Min
Crystal Oscillator Frequency Range
-
Typ
Max
24.000
-
Unit
MHz
Startup Time
–
–
Frequency Tolerance at 25 °C
-40
–
Oscillation Mode
Fundamental
Maximum change over temperature range
-50
–
+50
ppm
Drive level
–
–
50
uW
Equivalent Load capacitance
–
–
pF
Copyright © 2012 Allwinner Technology. All Rights Reserved.
ms
+40
ppm
–
PAGE 40 / 43
A31
Datasheet
CL1,CL2
RS
CM
CSHUT
RBIAS
Internal Load capacitance(CL1=CL2)
–
–
pF
Series Resistance(ESR)
–
–
Ω
Duty Cycle
30
50
70
%
Motional capacitance
–
–
pF
Shunt capacitance
–
–
pF
MΩ
Internal bias resistor
Table 6-4 24MHz Oscillator Characteristics
32768Hz Oscillator Characteristics
The 32768Hz crystal is connected between the LOSCI (amplifier input) and LOSCO (amplifier output). Table
6-5 lists the 32768Hz crystal specifications.
Symbol
1/(tCPMAIN)
tST
Parameter
Min
Typ
Crystal Oscillator Frequency Range
Startup Time
Frequency Tolerance at 25 °C
Max
32.768
–
–
-40
–
Oscillation Mode
Unit
kHz
ms
+40
ppm
–
Fundamental
-50
–
+50
ppm
Drive level
–
–
50
uW
Equivalent Load capacitance
–
–
pF
Internal Load capacitance(CL1=CL2)
–
–
pF
Series Resistance(ESR)
–
–
Ω
Duty Cycle
30
50
70
%
Motional capacitance
–
–
pF
CSHUT
Shunt capacitance
–
–
pF
RBIAS
Internal bias resistor
Maximum change over temperature range
PON
CL
CL1,CL2
RS
CM
MΩ
Table 6-5 32768Hz Oscillator Characteristics
6.5.
POWER UP AND POWER DOWN SEQUENCE
A31 supports four working modes: active mode, idle mode, super standby mode, and power-off mode.
Power Up Sequence
When the system is powered on for the first time, CPU0 will run Boot Rom to scan external storage interface;
when the system is powered on from super standby mode, CPU0 will run Boot Rom to check the super
standby flag and then jump to internal SRAM.
Following Figure 6-1 illustrates the power on sequence:
A31 Datasheet V1.0
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A31
Datasheet
PS
RTC-VCC
VCC-3V3
VDD-CPU
VDD-GPU
VDD-SYS
VDD-DRAM
AVCC-AP
AP-RESET#
128ms
64ms
Figure 6-1 ON
A31 Power
Up Sequence
POWER
SEQUENCE
Power Down Sequence
Figure 6-2 illustrates the power off sequence:
PS
RTC-VCC
VCC-3V3
VDD-CPU
VDD-GPU
VDD-SYS
VDD-DRAM
AVCC-AP
AP-RESET#
Figure 6-2 A31 Power Down Sequence
POWER OFF SEQUENCE
A31 Datasheet V1.0
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PAGE 42 / 43