Series

Technical Manual

NOTICE

No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.

Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control

Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency.

© Seiko Epson corporation 1998 All right reserved.

i8088 and i8086 are registered trademarks of Intel Corporation.

Z80 is registered trademark of Zilog Corporation.

V20 and V30 are registered trademarks of Nippon Electric Corporation.

CONTENTS

Selection Guide

1. SED1510 Series

2. SED1520 Series

3. SED152A Series

4. SED1526 Series

5. SED1530 Series

6. SED1540 Series

7. SED1560 Series

8. SED1565 Series

9. SED1570 Series

SED1500 Series

Selection Guide

■

LCD drivers with RAM for smalland medium-sized displays

Ultra-low power consumption and on-chip RAM make this series ideal for compact

LCD-based equipment.

SED1500 series

Part number

Supply voltage range (V)

LCD voltage range (V)

SED1510D

0C

SED1510D

0B

SED1510F

0C

SED1510F

0E

SED1511D

0A

SED1520D

0A

SED1520D

0B

SED1520F

0A

SED1520F 0C

SED1520T

0A

SED1520D

AA

SED1520D

AB

SED1520F

AA

SED1520F

AC

SED1520T

AA

#

SED1521D

0A

SED1521D

0B

SED1521F

0A

SED1521F

0C

SED1521T

0A

#

SED1521D AA

SED1521D

AB

SED1521F

AA

SED1521F

AC

SED1521T

AA

#

SED152AD

0A

SED1522D

0A

SED1522D

0B

SED1522F

0A

SED1522F

0C

SED1522T 0A

#

SED1522D

AA

SED1522D

AB

SED1522F

AA

SED1522F

AC

SED1522T

AA

#

SED1540D

0A

SED1540D

0B

SED1540F

0A

0.9–6.0

2.4–7.0

1.8–6.0

3.5–13

3.5–11

Duty

1/4

1/16,1/32

1/8–1/32

1/8,1/16

1/3,1/4

Segment Common

Display

RAM (bits)

Microprocessor interface

Frequency

(KHz)

32

61

80

69

73

4

16

–

8

3, 4

Package

Application/additional features

128 Serial

2,560 8-bit parallel

18 (internal)

18

(internal, external)

2

(external)

18

(external)

2

(external)

18

(internal, external)

2

(external)

18 (internal)

4 (external)

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

Al pad chip

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

AI pad chip

Au bump chip

QFP5-100pin

AI pad chip

Au bump chip

QFP12-48pin

QFP6-60pin

AI pad chip

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

AI pad chip

Au bump chip

QFP5-100pin

QFP15-100pin

TCP

Small segment-type LCD display. Command and data interface

Small segment-type LCD dislays. Data only interface

Dot-matrix LCD displays

Extension driver is the

SED1521.

Extension driver for the

SED1520 and SED1522

P-substrate version of SED1521

Dot-matrix LCD displays

Extension driver is the

SED1521.

Segment-type displays

# : Planning TCP : Tape Carrier Package

Part number

Supply voltage range (V)

LCD voltage range (V)

SED1562T QA

SED1565D

0B

SED1565D

1B

*

SED1565D

2B

SED1565T

0A

SED1565T

0B

SED1565T

0C

SED1566D

0B

SED1566D

1B

*

SED1566D

2B

SED1566T 0A

SED1567D

0B

SED1567D

1B

*

SED1567D

2B

SED1567T

0B

SED1567T

0C

SED1568D

0B

SED1569D

0B

SED1569T

**

SED1570D

0A

SED1570D

0B

SED1526D

*A

SED1526D *B

SED1526F

*A

SED1526T

*A

SED1528D

*A

SED1528D

*B

SED1528F

*A

SED1528T

*A

SED1560D

0A

SED1560D

AA

SED1560D

0B

SED1560D

AB

SED1560T

0B

SED1560T

QA

SED1561D 0A

SED1561D

AA

SED1561D

0B

SED1561D

AB

SED1561T

0B

SED1561T

AB

SED1561T

QA

SED1562D

0A

SED1562D

0B

SED1562T

0B

2.4–6.0

1.8–5.5

2.7–5.5

2.4–6.0

6.0–16.0

4.5–16.0

8.0–20.0

3.5–

Supply

×

3 voltage

Duty

1/48, 1/49

1/64, 1/65

1/24, 1/25

1/32, 1/33

1/16, 1/17

(1/5bias)

1/65

(1/7, 1/9 bias)

1/49

(1/6, 1/8 bias)

1/33

(1/5, 1/6 bias)

1/55 (1/6, 1/8 bias)

1/53

(1/6, 1/8 bias)

1/64–1/200

1/8, 1/9

1/16, 1/17

1/32, 1/33

Segment Common

Display

RAM (bits)

Microprocessor interface

Frequency

(KHz)

102

134

150

132

80

64

65

33

17

65

49

33

55

53

–

17

33

166

80

× bits

132 bits

200

×

×

× bits

33 bits

65

65

80

8-bit parallel or Serial

4-bit parallel

8-bit parallel or Serial

18

33

–

20

Package

Application/additional features

Au bump chip

TCP

QTCP

Au bump chip

Au bump chip

Au bump chip

TCP

TCP

TCP

Au bump chip

Au bump chip

Au bump chip

TCP

Au bump chip

Au bump chip

Au bump chip

TCP

TCP

Au bump chip

Au bump chip

TCP

Al pad chip

Au bump chip

Al pad chip

Au bump chip

QFP5-128pin

TCP

Al pad chip

Au bump chip

QFP5-128pin

TCP

Al pad chip

Al pad chip

Au bump chip

Au bump chip

TCP

QTCP

Al pad chip

Al pad chip

Au bump chip

Au bump chip

TCP

TCP

QTCP

Al pad chip

Built-in power circuit for LCD

(voltage tripler)

SED1560 ✽

0B

(1/9 bias)

SED1560 ✽

AB

(1/7 bias)

SED1561 ✽

0B

(1/7 bias)

SED1561 ✽

AB

(1/5 bias)

Built-in power circuit for LCD

(DC/DC

×

4)

Built-in self-refreshing function

Built-in power circuit for LCD

(voltage tripler)

SED1526 ✽

0 ✽

(V

REG

)

SED1526 ✽

E ✽

(no V

REG

)

SED1526 ✽

A ✽

(redistribution of COMS)

SED1528 ✽

0 ✽

(V

REG

)

SED1528 ✽

E ✽

(no V

REG

)

Part number

Supply voltage range (V)

LCD voltage range (V)

SED1530D

0A

SED1530D

AA

SED1530D

0B

SED1530D

AB

SED1530T

AA

SED1531D

0A

SED1531D 0B

SED1531T

0A

SED1532D

0A

SED1532D

BA

SED1532D

0B

SED1532D

BA

SED1532T

0A

SED1532T

BA

SED1535D

0B

*

2.4–6.0

4.5–16.0

Duty

1/32, 1/33

1/64, 1/65

1/35

Segment Common

Display

RAM (bits)

Microprocessor interface

Frequency

(KHz)

100

132

100

98

33

–

33

35

132

× bits

65 8-bit parallel or Serial

–

Package

Application/additional features

Al pad chip

Al pad chip

Au bump chip

Au bump chip

TCP

Al pad chip

Au bump chip

TCP

Al pad chip

Al pad chip

Au bump chip

Au bump chip

TCP

TCP

Au bump chip

Built-in power circuit for LCD

(voltage quadrupler)

SED153 ✽✽

0 ✽

(Common: Right side)

SED153 ✽✽

A ✽

(Common: Both side)

SED153 ✽✽

B ✽

(Common: Left side)

SED153 ✽✽

F ✽

(no V

REG

)

TCP : Tape Carrier Package

2. SED1520 Series

SED1520 Series

Contents

OVERVIEW .......................................................................................................................................................... 2-1

FEATURES ........................................................................................................................................................... 2-1

BLOCK DIAGRAM ................................................................................................................................................ 2-2

PACKAGE OUTLINE ............................................................................................................................................ 2-3

PAD ...................................................................................................................................................................... 2-4

Pad Arrangement ......................................................................................................................................... 2-4

PAD ARRANGEMENT ......................................................................................................................................... 2-5

PIN DESCRIPTION .............................................................................................................................................. 2-6

(1) Power Pins ............................................................................................................................................. 2-6

(2) System Bus Connection Pins ................................................................................................................. 2-6

(3) LCD Drive Circuit Signals ....................................................................................................................... 2-7

BLOCK DESCRIPTION ........................................................................................................................................ 2-8

System Bus .................................................................................................................................................. 2-8

Display Start Line and Line Count Registers ............................................................................................... 2-9

Column Address Counter ............................................................................................................................. 2-9

Page Register .............................................................................................................................................. 2-9

Display Data RAM ........................................................................................................................................ 2-9

Common Timing Generator Circuit ............................................................................................................ 2-10

Display Data Latch Circuit .......................................................................................................................... 2-10

LCD Driver Circuit ...................................................................................................................................... 2-10

Display Timing Generator .......................................................................................................................... 2-10

Oscillator Circuit (SED1520 *

0A

Only) ........................................................................................................ 2-11

Reset Circuit .............................................................................................................................................. 2-11

COMMANDS ...................................................................................................................................................... 2-14

Summary .................................................................................................................................................... 2-14

Command Description ............................................................................................................................... 2-15

SPECIFICATIONS .............................................................................................................................................. 2-20

Absolute Maximum Ratings ....................................................................................................................... 2-20

Electrical Specifications ............................................................................................................................. 2-20

APPLICATION NOTES ....................................................................................................................................... 2-26

MPU Interface Configuration ...................................................................................................................... 2-26

LCD Drive Interface Configuration ............................................................................................................. 2-27

LCD Panel Wiring Example ....................................................................................................................... 2-29

Package Dimensions ................................................................................................................................. 2-30

– i –

SED1520 Series

OVERVIEW

The SED1520 family of dot matrix LCD drivers are designed for the display of characters and graphics. The drivers generate LCD drive signals derived from bit mapped data stored in an internal RAM.

The drivers are available in two configurations

The SED1520 family drivers incorporate innovative circuit design strategies to achieve very low power dissipation at a wide range of operating voltages.

These features give the designer a flexible means of implementing small to medium size LCD displays for compact, low power systems.

• The SED1520 which is able to drive two lines of twelve characters each.

• The SED1521 which is able to drive 80 segments for extention.

• The SED1522 which is able to drive one line of thirteen characters each.

FEATURES

• Fast 8-bit MPU interface compatible with 80- and 68family microcomputers

• Many command set

• Total 80 (segment + common) drive sets

• Low power — 30

µ

W at 2 kHz external clock

• Wide range of supply voltages

V DD – V SS : –2.4 to –7.0 V

V DD – V5: –3.5 to –13.0 V

• Low-power CMOS

Line-up

Product

Name

Clock Frequency

Applicable Driver

Number Number of SEG of CMOS

SED1520 * 0 *

On-Chip External

18 kHz 18 kHz SED1520 * 0 *

, SED1521 * 0 *

Drivers Drivers

61

SED1521 * 0 *

— 18 kHz SED1520 * 0 *

, SED1522 * 0 *

80

SED1522 * 0 *

18 kHz 18 kHz SED1522 * 0 *

, SED1521 * 0 *

69

SED1520 * A *

— 2 kHz SED1520 * A *

, SED1521 * A *

61

SED1521 * A *

— 2 kHz SED1520 * A *

, SED1522 * A *

80

SED1522 * A *

— 2 kHz SED1522 * A *

, SED1521 * A *

69

16

0

8

16

0

8

Duty

1/16, 1/32

1/8 to 1/32

1/8, 1/16

1/16, 1/32

1/8 to 1/32

1/8, 1/16

• Package code (For example SED1520)

SED1520T

SED1520F ** : PKG

SED1520D ** : Chip

SED1520F * A

SED1520F * C

SED1520D * A

SED1520D * B

(QFP5-100pin)

(QFP15-100pin)

(Al-pad)

(Au-bump)

EPSON 2–1

SED1520 Series

BLOCK DIAGRAM

An example of SED1520 * AA:

LCD drive circuit

Common counter Display data latch circuit

Display data RAM

(2560-bit)

CL

FR

Display timing generator circuit

Command decoder

Column address decoder

Column address counter

Column address register

Status

MPU interface

2–2 EPSON

PACKAGE OUTLINE

QFP5

SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 A0 CS(OSC1) CL(OSC2) R/W(WR) V CS0 CS1

CS2

CS3

CS4

CS5

CS6

CS7

V DD

RES

F2

V5

V1

V2

M/S

V4

V1

COM0

COM1

COM2

COM3

COM4

85

90

95

100

Index

45

40

35

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SED1520 Series

COM5 COM6 COM7 COM8 COM9

COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42

QFP15

RES

F R

V5

V3

V2

M/S

V4

V1

COM 0

COM 1

COM 2

COM 3

COM 4

COM 5

COM 6

V SS

D30

D31

D32

D33

D34

D35

D36

D37

V DD 85

90

95

Index

50

45

40

35

30

SEG20

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

SEG41

SEG42

SEG43

SEG44

Note: This is an example of SED1520F pin assignment. The modified pin names are given below.

Product

Name

SED1520F

SED1521F

SED1522F

SED1520F

SED1521F

SED1522F

0A

0A

0A

AA

AA

AA

74

OSC1

CS

OSC1

CS

CS

CS

75

OSC2

CL

Pin/Pad Number

96 to 100, 1 to 11

COM0 to COM15*

SEG76 to SEG61

OSC2 COM0 to 7, SEG68 to 61

93

M/S

SEG79

M/S

CL

CL

CL

COM0 to COM15*

SEG76 to SEG61

COM0 to 7, SEG68 to 61

M/S

SEG79

M/S

94

V4

SEG78

V4

V4

SEG78

V4

95

V1

SEG77

V1

V1

SEG77

V1

SED1520: Common outputs COM0 to COM15 of the master LSI correspond to COM31 to COM16 of the slave LSI.

SED1522: Common outputs COM0 to COM15 of the master LSI correspond to COM15 to COM8 of the slave LSI.

EPSON 2–3

SED1520 Series

PAD

Pad Arrangement

Chip specifications of AL pad package

Chip size: 4.80

×

7.04

×

0.400 mm

Pad pitch: 100

×

100

µ m

Chip specifications of gold bump package

Chip size: 4.80

×

7.04

×

0.525 mm

Bump pitch: 199

µ m (Min.)

Bump height: 22.5

µ m (Typ.)

Bump size: 132

×

111

µ m (

±

20

µ m) for mushroom model

116

×

92

µ m (

±

4

µ m) for vertical model

1

100

5

95 90 85

80

75

10

Y

(0, 0)

70

15

20

X

65

60

25

30

35 40

4.80 mm

45

55

50

Note: An example of SED1520D AA die numbers is given. These numbers are the same as the bump package.

2–4 EPSON

SED1520 Series

PAD ARRANGEMENT

An example of SED1520D A * asterisk ( * ) can be A for AL pad package or B for gold bump package.

pin names is given. The

SED1520D AB Pad Center Coordinates

Pad

No.

29

30

31

32

25

26

27

28

33

34

21

22

23

24

17

18

19

20

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

Pin

Name

X Y

COM5 159 6507

COM6 159 6308

COM7 159 6108

COM8 159 5909

COM9 159 5709

COM10 159 5510

COM11 159 5310

COM12 159 5111

COM13 159 4911

COM14 159 4712

COM15 159 4512

SEG60 159 4169

SEG59 159 3969

SEG58 159 3770

SEG57 159 3570

SEG56 159 3371

SEG55 159 3075

SEG54 159 2876

SEG53 159 2676

SEG52 159 2477

SEG51 159 2277

SEG50 159 2078

SEG49 159 1878

SEG48 159 1679

SEG47 159 1479

SEG46 159 1280

SEG45 159 1080

SEG44 159 881

SEG43 159 681

SEG42 159 482

SEG41 504 159

SEG40 704 159

SEG39 903 159

SEG38 1103 159

Pad

No.

63

64

65

66

59

60

61

62

67

68

55

56

57

58

51

52

53

54

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

Pin

Name

X Y

SEG37 1302 159

SEG36 1502 159

SEG35 1701 159

SEG34 1901 159

SEG33 2100 159

SEG32 2300 159

SEG31 2499 159

SEG30 2699 159

SEG29 2898 159

SEG28 3098 159

SEG27 3297 159

SEG26 3497 159

SEG25 3696 159

SEG24 3896 159

SEG23 4095 159

SEG22 4295 159

SEG21 4641 482

SEG20 4641 681

SEG19 4641 881

SEG18 4641 1080

SEG17 4641 1280

SEG16 4641 1479

SEG15 4641 1679

SEG14 4641 1878

SEG13 4641 2078

SEG12 4641 2277

SEG11 4641 2477

SEG10 4641 2676

SEG9 4641 2876

SEG8 4641 3075

SEG7 4641 3275

SEG6 4641 3474

SEG5 4641 3674

SEG4 4641 3948

Pad

No.

Pin

Name

X Y

73

74

75

76

69

70

71

72

SEG3 4641 4148

SEG2 4641 4347

SEG1 4641 4547

SEG0 4641 4789

A0

CS

4641 5048

4641 5247

CL 4641 5447

E (RD) 4641 5646

81

82

83

84

77 R/W (WR) 4641 5846

78 V SS 4641 6107

79

80

DB0

DB1

4641 6307

4641 6506

DB2

DB3

DB4

DB5

4295 6884

4095 6884

3896 6884

3696 6884

89

90

91

92

85

86

87

88

DB6 3497 6884

DB7 3297 6884

V DD 3098 6884

RES 2898 6884

FR

V 5

V 3

V 2

2699 6884

2499 6884

2300 6884

2100 6884

93

94

95

96

M/S 1901 6884

V 4 1701 6884

V 1 1502 6884

COM0 1302 6884

97

98

COM1 1103 6884

COM2 903 6884

99 COM3 704 6884

100 COM4 504 6884

The other SED1520 series packages have the different pin names as shown.

Package/Pad No.

SED1520D 0*

SED1522D

0*

SED1522D

A*

SED1521D

0*

SED1521D

A*

74

OSC1

OSC1

OSC1

CS

CS

75

OSC2

OSC2

OSC2

CL

CL

96 to 100, 1 to 11

COM0 to COM15 *

COM0 to 7, SEG68 to 61

COM0 to 7, SEG68 to 61

SEG76 to SEG61

SEG76 to SEG61

93

M/S

M/S

M/S

94

V

V

V

4

4

4

95

V

V

V

1

1

1

SEG79 SEG78 SEG77

SEG79 SEG78 SEG77

EPSON 2–5

SED1520 Series

PIN DESCRIPTION

(1) Power Pins

Name

V DD

Description

Connected to the +5Vdc power. Common to the V CC MPU power pin.

V SS 0 Vdc pin connected to the system ground.

V 1 , V 2 , V 3 , V

4

, V

5

Multi-level power supplies for LCD driving. The voltage determined for each liquid crystal cell is divided by resistance or it is converted in impedance by the op amp, and supplied. These voltages must satisfy the following:

V

DD

≥

V

1

≥

V

2

≥

V

3

≥

V

4

≥

V

5

(2) System Bus Connection Pins

D7 to D0

A0

RES

CS

E (RD)

R/W (WR)

Three-state I/O.

The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU data buses.

Input.

Usually connected to the low-order bit of the MPU address bus and used to identify the data or a command.

A0=0: D0 to D7 are display control data.

A0=1: D0 to D7 are display data.

Input.

When the RES signal goes the 68-series MPU is initialized, and when it goes , the 80-series MPU is initialized. The system is reset during edge sense of the RES signal. The interface type to the 68-series or 80-series MPU is selected by the level input as follows:

High level: 68-series MPU interface

Low level: 80-series MPU interface

Input. Active low. Effective for an external clock operation model only.

An address bus signal is usually decoded by use of chip select signal, and it is entered. If the system has a built-in oscillator, this is used as an input pin to the oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,

WR and E signals must be ORed with the CS signals and entered.

• If the 68-series MPU is connected:

Input. Active high.

Used as an enable clock input of the 68-series MPU.

• If the 80-series MPU is connected:

Input. Active low.

The RD signal of the 80-series MPU is entered in this pin. When this signal is kept low, the SED1520 data bus is in the output status.

• If the 68-series MPU is connected:

Input.

Used as an input pin of read control signals (if R/W is high) or write control signals (if low).

• If the 80-series MPU is connected:

Input. Active low.

The WR signal of the 80-series MPU is entered in this pin. A signal on the data bus is fetched at the rising edge of WR signal.

2–6 EPSON

SED1520 Series

(3) LCD Drive Circuit Signals

Name

CL

FR

SEGn

Description

Input. Effective for an external clock operation model only.

This is a display data latch signal to count up the line counter and common counter at each signal falling and rising edges. If the system has a built-in oscillator, this is used as an output pin of the oscillator amp and an Rf oscillator resistor is connected to it.

Input/output.

This is an I/P pin of LCD AC signals, and connected to the M terminal of common driver.

I/O selection

• Common oscillator built-in model: Output if M/S is 1;

• Dedicate segment model:

Input if M/S is 0.

Input

Output.

The output pin for LCD column (segment) driving. A single level of V DD , V 2 , V 3 and

V

5

is selected by the combination of display RAM contents and RF signal.

COMn

1 0

FR signal

1 0 1 0

Data

V

DD

V2 V5 V3

Output level

Output.

The output pin for LCD common (low) driving. A single level of V DD , V 1 , V 4 and V 5 is selected by the combination of common counter output and RF signal. The slave LSI has the reverse common output scan sequence than the master LSI.

FR signal

Counter output

Output level

1 0

1

V5

0

V1

1 0

V

DD

V4

M/S Input.

The master or slave LSI operation select pin for the SED1520 or SED1522.

Connected to V DD (to select the master LSI operation mode) or V SS (to select the slave LSI operation mode).

When this M/S pin is set, the functions of FR, COM0 to COM15, OSC1 (CS), and

OSC2 (CL) pins are changed.

SED1520F

SED1522F

0A

0A

M/S

V DD

V SS

V DD

V SS

FR COM output

Output COM0 to COM15

Input

Output

Input

COM31 to COM16

COM0 to COM7

COM15 to COM8

OSC1

Input

NC

Input

NC

OSC2

Output

Input

Output

Input

* The slave driver has the reverse common output scan sequence than the master driver.

EPSON 2–7

SED1520 Series

BLOCK DESCRIPTION

System Bus

MPU interface

1. Selecting an interface type

The SED1520 series transfers data via 8-bit bidirectional data buses (D0 to D7). As its Reset pin has the

MPU interface select function, the 80-series MPU or the 68-series MPU can directly be connected to the

MPU bus by the selection of high or low RES signal

RES signal input level

Active low

Active high

MPU type

68-series

80-series level after reset (see Table 1).

When the CS signal is high, the SED1520 series is disconnected from the MPU bus and set to stand by.

However, the reset signal is entered regardless of the internal setup status.

Table 1

A0

↑

↑

E

↑

RD

R/W

↑

WR

CS

↑

↑

D0 to D7

↑

↑

Data transfer

The SED1520 and SED1521 drivers use the A0, E (or

RD) and R/W (or WR) signals to transfer data between the system MPU and internal registers. The combinations used are given in the table blow.

In order to match the timing requirements of the MPU with those of the display data RAM and control registers all data is latched into and out of the driver. This introduces a one cycle delay between a read request for data and the data arriving. For example when the MPU

Common

A0

0

0

1

1

68 MPU

R/W

1

0

1

0

RD

0

1

0

1

80 MPU

WR

1

0

1

0 executes a read cycle to access display RAM the current contents of the latch are placed on the system data bus while the desired contents of the display RAM are moved into the latch.

This means that a dummy read cycle has to be executed at the start of every series of reads. See Figure 1.

No dummy cycle is required at the start of a series of writes as data is transferred automatically from the input latch to its destination.

Function

Read display data

Write display data

Read status

Write to internal register (command)

2–8 EPSON

SED1520 Series

WRITE

MPU

Internal timing

READ

MPU

WR

RD

DATA

WR

DATA

Bus hold

WR

WR

Internal timing

RD

Column address

Bus hold

N

N

N

Address set at N

N + 1

N + 1

N

Dummy read

N + 2 n

Data read at N

N + 2

N + 3

N + 3 n + 1

Data read at N + 1

N N + 1

N n

Figure 1 Bus Buffer Delay n + 1

N + 2 n + 2

Busy flag

When the Busy flag is logical 1, the SED1520 series is executing its internal operations. Any command other than Status Read is rejected during this time. The Busy flag is output at pin D7 by the Status Read command. If an appropriate cycle time (tcyc) is given, this flag needs not be checked at the beginning of each command and, therefore, the MPU processing capacity can greatly be enhanced.

Display Start Line and Line Count

Registers

The contents of this register form a pointer to a line of data in display data RAM corresponding to the first line of the display (COM0), and are set by the Display Start

Line command. See section 3.

The contents of the display start line register are copied into the line count register at the start of every frame, that is on each edge of FR. The line count register is incremented by the CL clock once for every display line, thus generating a pointer to the current line of data, in display data RAM, being transferred to the segment driver circuits.

Column Address Counter

The column address counter is a 7-bit presettable counter that supplies the column address for MPU access to the display data RAM. See Figure 2. The counter is incremented by one every time the driver receives a Read or Write Display Data command. Addresses above 50H are invalid, and the counter will not increment past this value. The contents of the column address counter are set with the Set Column Address command.

Page Register

The page resiter is a 2-bit register that supplies the page address for MPU access to the display data RAM. See

Figure 2. The contents of the page register are set by the

Set Page Register command.

Display Data RAM

The display data RAM stores the LCD display data, on a

1-bit per pixel basis. The relation-ship between display data, display address and the display is shown in Figure

2.

EPSON 2–9

SED1520 Series

Common Timing Generator Circuit

Generates common timing signals and FR frame signals from the CL basic clock. The 1/16 or 1/32 duty (for

SED1520) or 1/8 or 1/16 duty (for SED1522) can be selected by the Duty Select command. If the 1/32 duty is selected for the SED1520 and 1/16 duty is selected for the

SED1522, the 1/32 and 1/16 duties are provided by two chips consisting of the master and slave chips in the common multi-chip mode.

SED1520

FR signal

(Master output)

Master Common

Slave Common

SED1522

FR signal

(Master output)

Master Common

Slave Common

0 1 2 14 15

16 17

0 1 2 6 7

8 9

30 31

0 1

14 15

0 1

15

16 17

7

8 9

31

15

Display Data Latch Circuit

This latch stores one line of display data for use by the

LCD driver interface circuitry. The output of this latch is controlled by the Display ON/OFF and Static Drive

ON/OFF commands.

LCD Driver Circuit

The LCD driver circuitry generates the 80 4-level signals used to drive the LCD panel, using output from the display data latch and the common timing generator circuitry.

Display Timing Generator

This circuit generates the internal display timing signal using the basic clock, CL, and the frame signals, FR.

FR is used to generate the dual frame AC-drive waveform (type B drive) and to lock the line counter and common timing generator to the system frame rate.

CL is used to lock the line counter to the system line scan rate. If a system uses both SED1520s or SED1522 and

SED1521s they must have the same CL frequency rating.

2–10 EPSON

SED1520 Series

Oscillator Circuit (SED1520 * 0A

Only)

A low power-consumption CR oscillator for adjusting the oscillation frequency using Rf oscillation resistor only. This circuit generates a display timing signal.

Some of SED1520 and SED1522 series models have a built-in oscillator and others use an external clock. This difference must be checked before use.

Connect the Rf oscillation resistor as follows. To suppress the built-in oscillator circuit and drive the MPU using an external clock, enter the clock having the same phase as the OSC2 of mater chip into OSC2 of the slave chip.

• MPU having a built-in oscillator

V

DD

Master chip

M/S

(CS)

OSC1

(CL)

OSC2

Slave chip

M/S

(CS)

OSC1

(CL)

OSC2

V

SS

Rf

*2

Open

*1

*1 If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower frequency. Therefore, the Rf oscillation frequency must be reduced below the specified level.

*2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips.

• MPU driven with an external clock

Y driver

CL2

SED1521F

AA

CL

Reset Circuit

Detects a rising or falling edge of an RES input and initializes the MPU during power-on.

• Initialization status

1. Display is off.

2. Display start line register is set to line 1.

3. Static drive is turned off.

4. Column address counter is set to address 0.

5. Page address register is set to page 3.

6. 1/32 duty (SED1520) or 1/16 duty (SED1522) is selected.

7. Forward ADC is selected (ADC command D0 is

1 and ADC status flag is 1).

8. Read-modify-write is turned off.

EPSON

The input signal level at RES pin is sensed, and an

MPU interface mode is selected as shown on Table 1.

For the 80-series MPU, the RES input is passed through the inverter and the active high reset signal must be entered. For the 68-series MPU, the active low reset signal must be entered.

As shown for the MPU interface (reference example), the RES pin must be connected to the Reset pin and reset at the same time as the MPU initialization.

If the MPU is not initialized by the use of RES pin during power-on, an unrecoverable MPU failure may occur.

When the Reset command is issued, initialization

2–11

SED1520 Series

Column address

ADC

SEG pin D

0

= "1" D

0

= "0"

SEG 0 4F

H

00

H

1

2

3

4

5

6

4E

4D

4C

4B

4A

49

01

02

03

04

05

06

7 48 07

77

78

79

02

01

00

4D

4E

4F

Display area

2–12

Figure 2 Display Data RAM Addressing

EPSON

COM8

COM9

COM10

COM11

COM12

COM13

COM14

COM15

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

1/5 bias, 1/16 duty

1/6 bias, 1/32 duty

SED1520 Series

FR

0 1 2 3

0 1 2 3

COM0

15 0

31 0

1

1

2

2

3

3

COM1

COM2

SEG0

SEG1

COM0—SEG0

COM0—SEG1

15

31

V5

V4

V3

V2

V1

V

DD

-V1

-V2

-V3

-V4

-V5

V5

V4

V3

V2

V1

V

DD

-V1

-V2

-V3

-V4

-V5

V

DD

V1

V2

V3

V4

V5

V

DD

V1

V2

V3

V4

V5

V2

V3

V4

V5

V

DD

V

SS

V

DD

V1

V

DD

V1

V2

V3

V4

V5

V

DD

V1

V2

V3

V4

V5

Figure 4 LCD drive waveforms example

EPSON 2–13

SED1520 Series

COMMANDS

Summary

Command

A0 RD WR D

7

D

6

Code

D

5

D

4

D

3

D

2

D

1

D

0

Function

Display On/OFF

Display start line

Set page address

Set column

(segment) address

Read status

Write display data

Read display data

Select ADC

Statis drive

ON/OFF

Select duty

Read-Modify-Write

End

Reset

0

0

0

0

0

1

1

0

0

0

0

0

0

1

1

1

1

0

1

0

1

1

1

1

1

1

0

0

0

0

1

0

1

0

0

0

0

0

0

1

1

1

0

Busy

1

1

1

1

1

1

0

1

0

ADC ON/OFF Reset

0

0

0

1

1

1

1

0

1

1

1

1

1

1

1

0 1 1 1 0/1

Display start address (0 to 31)

1 1 0 Page (0 to 3)

Column address (0 to 79)

Write data

Read data

0

0

0

0

0

0

0

0

0

1

0

1

0

0

1

0

0

1

0

0 0

0

0

0

0

1

1

0

0/1

0/1

0/1

0

0

0

Turns display on or off.

1: ON, 0: OFF

Specifies RAM line corresponding to top line of display.

Sets display RAM page in page address register.

Sets display RAM column address in column address register.

Reads the following status:

BUSY 1: Busy

ADC

0: Ready

1: CW output

0: CCW output

ON/OFF 1: Display off

RESET

0: Display on

1: Being reset

0: Normal

Writes data from data bus into display RAM.

Reads data from display RAM onto data bus.

0: CW output, 1: CCW output

Selects static driving operation.

1: Static drive, 0: Normal driving

Selets LCD duty cycle

1: 1/32, 0: 1/16

Read-modify-write ON

Read-modify-write OFF

Software reset

2–14 EPSON

SED1520 Series

Command Description

Table 3 is the command table. The SED1520 series identifies a data bus using a combination of A0 and R/W (RD or WR) signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed is very high. The busy check is usually not required.

Display ON/OFF

A

0

0

RD

1

R/W

WR

0

D

1

7

This command turns the display on and off.

• D=1: Display ON

• D=0: Display OFF

D

6

0

D

1

5

D

0

4

D

1

3

D

1

2

D

1

1

D

D

0

AEH, AFH

Display Start Line

This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COM0. The display area begins at the specified line address and continues in the line address increment direction. This area having the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command, the vertical smooth scrolling and paging can be used.

A 0

R/W

RD WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

0 1 0 1 1 0 A 4 A 3 A 2 A 1 A 0 C0H to DFH

This command loads the display start line register.

A 4 A 3 A 2 A 1 A 0 Line Address

0 0 0 0 0

0 0 0 0 1

:

:

1 1 1 1 1

0

1

:

:

31

See Figure 2.

Set Page Address

This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.

The display status is not changed even when the page address is changed.

A 0

R/W

RD WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

0 1 0 1 0 1 1 1 0 A 1 A 0 B8H to BBH

This command loads the page address register.

A 1 A 0 Page

0 0

0 1

1 0

1 1

0

1

2

3

See Figure 2.

EPSON 2–15

SED1520 Series

Set Column Address

This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU can access to data continuously. The column address stops to be incremented at address 80, and the page address is not changed continuously.

A 0

R/W

RD WR D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0

0 1 0 0 A 6 A 5 A 4 A 3 A 2 A 1 A 0 00H to 4FH

This command loads the column address register.

A 6 A 5 A 4 A 3 A 2 A 1 A 0 Column Address

0 0 0 0 0 0 0

0 0 0 0 0 0 1

:

:

1 0 0 1 1 1 1

0

1

:

:

79

Read Status

A

0

0

RD

0

R/W

WR D

7

D

6

D

5

D

4

D

3

1 BUSY ADC ON/OFF RESET 0

D

0

2

D

0

1

D

0

0

Reading the command I/O register (A0=0) yields system status information.

• The busy bit indicates whether the driver will accept a command or not.

Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.

Busy=0: The driver will accept a new command.

• The ADC bit indicates the way column addresses are assigned to segment drivers.

ADC=1: Normal. Column address n

→

segment driver n.

ADC=0: Inverted. Column address 79-u

→

segment driver u.

• The ON/OFF bit indicates the current status of the display.

It is the inverse of the polarity of the display ON/OFF command.

ON/OFF=1: Display OFF

ON/OFF=0: Display ON

• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.

RESET=1: Currently executing reset command.

RESET=0: Normal operation

Write Display Data

A 0

1

RD

1

R/W

WR

0

D 7 D 6 D 5 D 4 D 3

Write data

D 2 D 1 D 0

Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page address registers and then increments the column address register by one.

2–16 EPSON

SED1520 Series

Read Display Data

A

1

0

R/W

RD WR D 7

0 1

D 6 D 5 D 4 D 3

Read data

D 2 D 1 D 0

Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data

RAM location specified by the contents of the column address and page address registers and then increments the column address register.

After loading a new address into the column address register one dummy read is required before valid data is obtained.

Select ADC

A

0

0

R/W

RD WR D 7

1 0 1

D

0

6 D

1

5 D

0

4 D

0

3 D

0

2 D

0

1 D

D

0

A0H, A1H

This command selects the relationship between display data RAM column addresses and segment drivers.

D=1: SEG0

←

column address 4FH, … (inverted)

D=0: SEG0

←

column address 00H, … (normal)

This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit board design. See Figure 2 for a table of segments and column addresses for the two values of D.

Static Drive ON/OFF

A

0

0

R/W

RD WR D 7

1 0 1

D

0

6 D

1

5 D

0

4 D

0

3 D

1

2 D

0

1 D

D

0

A4H, A5H

Forces display on and all common outputs to be selected.

D=1: Static drive on

D=0: Static drive off

Select Duty

A

0

0

R/W

RD WR D 7

1 0 1

D

0

6 D

1

5 D 4

0

D

1

3 D

0

2 D

0

1 D

D

0

A8H, A9H

This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F. It is invalid for the SED1521F which performs passive operation. The duty cycle of the SED1521F is determined by the externally generated FR signal.

SED1520 SED1522

D=1: 1/32 duty cycle 1/16 duty cycle

D=0: 1/16 duty cycle 1/8 duty cycle

When using the SED1520F 0A , SED1522F 0A (having a built-in oscillator) and the SED1521F 0A continuously, set the duty as follows:

SED1520F

SED1522F

0A

0A

1/32

1/16

1/16

1/8

SED1521F 0A

1/32

1/16

1/32

1/16

EPSON 2–17

SED1520 Series

Read-Modify-Write

A

0

0

R/W

RD WR D 7

1 0 1

D 6

1

D 5

1

D 4

0

D 3

0

D 2

0

D 1

0

D

0

0

E0H

This command defeats column address register auto-increment after data reads. The current conetents of the column address register are saved. This mode remains active until an End command is received.

• Operation sequence during cursor display

When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write command. This function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor blinking).

* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column

Address Set command cannot be used.

Set Page Address

Set Column Address

Read-Modify-Write

Dummy Read

Read Data

Write Data

No

Completed?

Yes

End

End

A

0

0

RD

1

R/W

WR

0

D

1

7

D

1

6

D

1

5

D

0

4

D

1

3

D

1

2

D

1

1

D

0

0

EEH

This command cancels read-modify-write mode and restores the contents of the column address register to their value prior to the receipt of the Read-Modify-Write command.

2–18

Column address N N+1 N+2 N+3

Read-Modify-Write mode is selected.

N+m

Return

N

End

EPSON

SED1520 Series

Reset

A 0

0

R/W

RD WR D 7

1 0 1

D 6

1

D 5

1

D 4

0

D 3

0

D 2

0

D 1

1

D

0

0

E2H

This command clears

• the display start line register.

• and set page address register to 3 page.

It does not affect the contents of the display data RAM.

When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead of this Reset signal.

Power Save (Combination command)

The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can be reduced to almost the static current level. In the Power Save mode:

(a) The LCD drive is stopped, and the segment and common driver outputs are set to the V DD level.

(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.

(c) The display and operation modes are kept.

The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the

Power Save signal.

V

DD

V

DD

V

1

V

2

V

3

V

4

V

5

SED1520

SED1522

Power Save signal

V

SSH

If the LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected and reduce the power consumption using the divider resistor.

EPSON 2–19

SED1520 Series

SPECIFICATIONS

Absolute Maximum Ratings

Input voltage

Output voltage

Parameter

Supply voltage (1)

Supply voltage (2)

Supply voltage (3)

Power dissipation

Operating temperature

Symbol

V

SS

V 5

V

1

, V

4

, V

2

, V

3

V IN

V

O

P D

T opr

V

V

SS

SS

Rating

–8.0 to +0.3

–16.5 to +0.3

V5 to +0.3

–0.3 to +0.3

–0.3 to +0.3

250

–40 to +85

Unit

V

V

V

V

V mW deg. C

Storage temperature

Soldering temperature time at lead

T

T stg sol

–65 to +150

260, 10 deg. C deg. C, sec

Notes: 1. All voltages are specified relative to V DD = 0 V.

2. The following relation must be always hold

V DD

≥

V 1

≥

V 2

≥

V 3

≥

V 4

≥

V 5

3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional operation under these conditions is not implied.

4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to avoid thermally stressing the package during board assembly.

Electrical Specifications

DC Characteristics

Ta = –20 to 75 deg. C, V DD = 0 V unless stated otherwise

Parameter

Operating Recommended voltage (1)

See note 1. Allowable

Recommended

Operating Allowable voltage (2) Allowable

Allowable

High-level input voltage

Low-level input voltage

High-level output voltage

Symbol Condition

Min.

–5.5

V SS

–7.0

V 5

V 1 , V 2

V 3 , V 4

V IHT

V IHC

V IHT V SS = –3 V

V IHC V SS = –3 V

V ILT

V ILC

V ILT V SS = –3 V

V ILC V SS = –3 V

V OHT I OH = –3.0 mA

V OHC1 I OH = –2.0 mA

V OHC2 I OH = –120

µ

A

V OHT V SS = –3 V

V OHC1 V SS = –3 V

V OHC2 V SS = –3 V

–13.0

–13.0

0.6

×

V 5

V 5

V SS +2.0

0.2

×

V SS

0.2

×

V SS

0.2

×

V SS

V SS

V SS

V SS

V SS

V SS +2.4

V SS +2.4

0.2

×

V SS

I OH = –2 mA 0.2

×

V SS

I OH = –2 mA 0.2

×

V SS

I OH = –50

µ

A 0.2

×

V SS

Rating

Typ.

–5.0

—

—

—

—

—

—

—

—

—

—

—

—

Max.

–4.5

–2.4

–3.5

—

V DD

0.4

×

V 5

V DD

V DD

V DD

V DD

V SS +0.8

0.8

×

V SS

0.85

×

V SS

0.8

×

V SS

—

—

—

Unit Applicable Pin

V

V

V

V

V

V SS

V 5

See note 10.

V V 1 , V 2

V V 3 , V 4

See note 2 & 3.

See note 2 & 3.

See note 2 & 3.

See note 2 & 3.

OSC2

See note 4 & 5.

See note 4 & 5.

OSC2

(continued)

2–20 EPSON

SED1520 Series

DC Characteristics (Cont’d)

Ta = –20 to 75 deg. C, V DD = 0 V unless stated otherwise

Parameter

Low-level output voltage

Input leakage current

Output leakage current

LCD driver ON resistance

Symbol Condition

V OLT I OL = 3.0 mA

V OLC1 I OL = 2.0 mA

V OLC2 I OL = 120

µ

A

V OLT V SS = –3 V

V OLC1 V SS = –3 V

V OLC2 V SS = –3 V

I LI

I LO

I OL = 2 mA

I OL = 2 mA

I OL = 50

µ

A

R ON Ta = 25 deg. C

V 5 = –5.0 V

V 5 = –3.5 V

Min.

—

—

—

–1.0

–3.0

—

—

Rating

Typ.

Unit Applicable Pin

Max.

—

—

V SS +0.4

V SS +0.4

V

— 0.8

×

V SS

0.8

×

V SS

0.8

×

V SS V

0.8

×

V SS

—

—

1.0

3.0

OSC2

See note 4 & 5.

See note 4 & 5.

OSC2

µ

A See note 6.

µ

A See note 7.

5.0

7.5

10.0

0.05

2.0

9.5

5.0

50.0

1.0

5.0

15.0

10.0

SEG0 to 79, k

Ω

COM0 to 15,

See note 11

µ

A V DD

V DD

µ

A See note 12,

13 & 14.

Static current dissipation

Dynamic current dissipation

I DDQ CS = CL = V DD

During display

V 5 = –5.0 V

— f CL = 2 kHz

R f = 1 M

Ω

—

— f CL = 18 kHz —

I DD (1)

During display f CL = 2 kHz

V 5 = –5 V

V SS = –3 V Rf = 1 M

Ω

1.5

6.0

4.5

12.0

µ

A

V DD

See note 12 & 13.

Input pin capacitance

Oscillation frequency

During access t cyc = 200 kHz —

I DD (2) V SS = –3V,

During access t cyc = 200 kHz f

C IN Ta = 25 deg. C, f = 1 MHz

R f = 1.0 M

Ω ±

2%,

OSC

V SS = –5.0 V

R f = 1.0 M

Ω ±

2%,

V SS = –3.0 V

—

15

11

300

150

5.0

18

16

500

300

8.0

21

21

µ

A See note 8.

pF All input pins kHz See note 9.

Reset time t R 1.0

—

µ

S

RES

See note 15.

Notes: 1. Operation over the specified voltage range is guaranteed, except where the supply voltage changes suddenly during CPU access.

2. A0, D0 to D7, E (or RD), R/W (or WR) and CS

3. CL, FR, M/S and RES

4. D0 to D7

5. FR

6. A0, E (or RD), R/W (or WR), CS, CL, M/S and RES

7. When D0 to D7 and FR are high impedance.

8. During continual write acess at a frequency of t cyc . Current consumption during access is effectively proportional to the access frequency.

9. See figure below for details

10. See figure below for details

11. For a voltage differential of 0.1 V between input (V 1 , …, V 4 ) and output (COM, SEG) pins. All voltages within specified operating voltage range.

12. SED1520 *

A * and SED1521 *

A * and SED1522 *

A * only. Does not include transient currents due to stray and panel capacitances.

13. SED1520 *

0 * and SED1522 *

0 * only. Does not include transient currents due to stray and panel capacitances.

14. SED1521 *

0 * only. Does not include transient currents due to stray and panel capacitances.

15. t R (Reset time) represents the time from the RES signal edge to the completion of reset of the internal circuit. Therefore, the SED1520 series enters the normal operation status after this t R .

EPSON 2–21

SED1520 Series

Relationship between f OSC , f FR and R f , and operating bounds on V SS and V5

*9 • Relationship between oscillation frequency, frames and Rf

(SED1520F 0A ), (SED1522F 0A )

Rf

OSC1

OSC2

Same for 1/16 and 1/32 duties

40 200

30

SED1522

20 100

SED1520

10

0 0.5

Rf

1.0

1.5

Figure 5 (a)

2.0

2.5

• Relationship between external clocks (f CL ) and frames

(SED1520F AA ) , (SED1522F AA )

0 0.5

Rf

1.0

1.5

Figure 5 (b)

2.0

2.5

200 duty1/32 duty1/16 duty1/8

100

0 1 f CL

Figure 5 (c)

2

[kHz]

*10 • Operating voltage range of V SS and V5 systems

–15

–10

Operating voltage range

–5

3

2–22

0 –2 –4

V

SS

Figure 6

EPSON

–6

(V)

–8

SED1520 Series

AC Characteristics

• MPU Bus Read/Write I (80-family MPU)

A0,CS

WR,RD t AW8 t f

D0 to D7

(WRITE) t ACC8

D0 to D7

(READ) t CC t CYC8 t DS8 t r t DH8 t AH8 t OH8

Ta = –20 to 75 deg. C, V SS = –5.0 V

±

10% unless stated otherwise

Condition Parameter

Address hold time

Address setup time

System cycle time

Control pulsewidth

Data setup time

Data hold time

RD access time

Output disable time

Rise and fall time

Symbol t

AH8 t

AW8 t

CYC8 t

CC t

DS8 t

DH8 t

ACC8 t

CH8 t r

, t f

C

L

= 100 pF

—

Min.

Rating

Max.

10

20

—

—

1000

200

80

10

—

—

—

—

—

10

—

90

60

15

(V SS = –2.7 to –4.5 V, Ta = –20 to +75

°

C)

Parameter

Address hold time

Address setup time

System cycle time

Control pulse width

Data setup time

Data hold time

RD access time

Output disable time

Rise and fall time

Symbol t AH8 t AW8 t CYC8 t CC t DS8 t DH8 t ACC8 t CH8 t r , t f

Condition

C L

—

—

—

= 100 pF

—

Min.

Rating

Max.

20

40

2000

400

160

20

—

20

—

—

—

—

—

—

—

180

120

15

Unit ns ns ns ns ns ns ns ns ns

Signal

A0, CS

WR, RD

D0 to D7

—

Unit ns ns ns ns ns ns ns ns ns

Signal

A0, CS

WR, RD

D0 to D7

—

EPSON 2–23

SED1520 Series

• MPU Bus Read/Write II (68-family MPU) t CYC6

E t AW6 t r t EW t DS6 t f

R/W t AH6

A0,CS t

DH6

D0 to D7

(WRITE) t ACC6

D0 to D7

(READ)

Ta = –20 to 75 deg. C, V SS = –5 V

±

10 unless stated otherwise

Condition Parameter

System cycle time

Address setup time

Address hold time

Data setup time

Data hold time

Output disable time

Access time

Enable pulsewidth

Read

Write

Rise and fall time

Symbol t CYC6 t AW6 t AH6 t DS6 t DH6 t OH6 t ACC6 t EW tr, tf

C L = 100 pF

—

Min.

Rating

Max.

1000

20

—

—

10

80

10

10

—

—

—

60

—

100

80

—

90

—

—

15

(V SS = –2.7 to – 4.5 V, Ta = –20 to +75

°

C)

Parameter Symbol Condition

System cycle time *1

Address setup time

Address hold time

Data setup time

Data hold time

Output disable time

Access time

Enable Read pulse width Write

Rise and fall time t t t t t t t

CYC6

AW6

AH6

DS6

DH6

OH6

ACC6 t EW t r

, t f

C L

—

—

—

= 100 pF

—

—

Notes: 1. t CYC6 is the cycle time of CS. E = H, not the cycle time of E.

Min.

Rating

Max.

2000

40

—

—

20

160

20

20

—

—

—

120

—

200

160

—

180

—

—

15

2–24 EPSON t OH6

Unit ns ns ns ns ns ns ns ns ns ns

Signal

A0, CS, R/W

D0 to D7

E

—

Unit ns ns ns ns ns ns ns ns ns ns

Signal

A0, CS, R/W

D0 to D7

E

—

SED1520 Series

• Display Control Signal Timing

CL t

WLCL t

DFR

FR t

WHCL t f t r

Input

Ta = –20 to 75 deg. C, V SS = –5.0 V

±

10% unless stated otherwise

Parameter

Low-level pulsewidth

High-level pulsewidth

Rise time

Fall time

FR delay time

Symbol t t t

WLCL

WHCL t t r f

DFR

V SS = –2.7 to –4.5 V, Ta = –20 to +75

°

C

Condition

Rating

Min.

Typ.

Max.

35

35

—

—

—

—

—

—

–2.0

30

30

0.2

150

150

2.0

Parameter

Low-level pulse width

High-level pulse width

Rise time

Fall time

FR delay time

Symbol t t

WHCL t

WLCL t t r f

DFR

Condition

—

—

—

—

—

Rating

Min.

Typ.

Max.

70

70

—

—

–4.0

—

—

60

60

0.4

—

—

300

300

4.0

Unit

µ s

µ s ns ns

µ s

Note: The listed input t DFR applies to the SED1520 and SED1521 and SED1522 in slave mode.

Unit

µ s

µ s ns ns

µ s

Output

Ta = –20 to 75 deg. C, V

SS

= –5.0 V

±

10% unless stated otherwise

Parameter Symbol Condition

C L = 100 pF

Rating

Min.

Typ.

Max.

— 0.2

0.4

FR delay time t DFR

V

SS

= –2.7 to –4.5 V, Ta = –20 to +75

°

C

Parameter

FR delay time

Symbol t DFR

Condition

C L = 100 pF

Rating

Min.

Typ.

Max.

— 0.4

0.8

Notes: 1. The listed output t DFR applies to the SED1520 and SED1522 in master mode.

Unit

µ s

Unit

µ s

Signal

CL

FR

Signal

CL

FR

Signal

FR

Signal

FR

EPSON 2–25

SED1520 Series

APPLICATION NOTES

MPU Interface Configuration

80 Family MPU

V

CC

A0

MPU

A1 to A7

IOQR

D0 to D7

RD

WR

GND

RES

Decoder

RESET

V

DD

A0

CS

SED1520F

AA

D0 to D7

RD

WR

RES

V

SS

V

5

2–26 EPSON

SED1520 Series

LCD Drive Interface Configuration

SED1520F 0A –SED1520F 0A

SED1522F 0A –SED1522F 0A

To LCD SEG

To LCD COM

V

DD

SED1520F 0A

M/S

OSC1

Master

OSC2 FR

R f

SED1520F AA –SED1520F AA

SED1522F AA –SED1522F AA

To LCD SEG

To LCD COM

V

DD

M/S

SED1520F AA

Master

CL FR

External clock

SED1520F 0A

SED1522F 0A

) –SED1521F 0A (See note 1)

To LCD SEG

To LCD COM

V

DD

SED1520F 0A

M/S

OSC1

Master

OSC2 FR

R f

*2

EPSON

To LCD SEG

SED1520F 0A

Slave

OSC1 OSC2

M/S

FR

To LCD COM

V

SS

To LCD SEG

SED1520F AA

Slave

CL

M/S

FR

To LCD COM

V

SS

To LCD SEG

SED1521F 0A

OSC1

Slave

OSC2 FR

2–27

SED1520 Series

SED1520F AA –SED1521F AA

To LCD COM

V

DD

M/S

To LCD SEG

SED1520F AA

CL FR

External clock

Notes: 1. The duty cycle of the slave must be the same as that for the master.

2. If a system has two or more slave drivers a CMOS buffer will be required.

To LCD SEG

SED1521F AA

CL FR

2–28 EPSON

SED1520 Series

LCD Panel Wiring Example (The full-dot LCD panel displays a character in 6

×××××

8 dots.)

1/16 duty:

• 10 characters

×

2 lines

1

16 1

LCD 16

×

61

61

SEG

COM

SED1520F

1/16 duty:

• 23 characters

×

2 lines

1

16 1

SEG

COM

SED1520F

LCD 16

×

141

61 62

SEG

SED1521F

141

1/32 duty:

• 33 characters

×

4 lines

1

16

1

SEG

61 62

LCD 32

×

202

141 142

SEG SEG

17

202 32

COM

SED1520F SED1521F

*

SED1520F

COM

* The SED1521F can be omitted (the 32

×

122-dot display mode is selected).

Note: A combination of AB or AA type chip (that uses internal clocks) and 0B or 0A type chip (that uses external clocks) is NOT allowed.

EPSON 2–29

SED1520 Series

Package Dimensions

• Plastic QFP5–100 pin

Dimensions: inches (mm)

80

1.008

±

0.016

(25.6

±

0.4

)

0.787

±

0.004

(20

±

0.1

)

51

81

50

• Plastic QFP15–100 pin

Index

100

1 0.026

(0.65

±

0.004

±

0.1

)

31

30

0.012

±

0.004

(0.30

±

0.1

)

0.110

(2.8)

0~12

°

0.059

(1.5

±

±

0.012

0.3

)

76

75

0.630

±

0.016

(16.0

±

0.4

)

0.551

±

0.004

(14.0

±

0.1

)

51

50

2–30

100

Index

1

0.020

(0.5

±

0.004

±

0.1

)

0.007

(0.18

±

0.004

±

0.1

)

25

26

0~12

°

0.020

±

0.004

(0.5

±

0.2

)

0.039(1.0)

EPSON

SED1520 Series

(Mold, marking area)

EPSON 2–31