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TDA7461
Car radio signal processor
Not For New Design
Features
■
■
■
■
■
■
High performance signal processor for car radio systems
Device includes audio processor, stereo decoder, noise blanker and multipath detector
No external components required
Fully programmable via I
2
C bus
Low distortion
Low noise
SO-28
Description
The TDA7461 is a high performance signal processor specifically designed for car radio applications.
The device includes a complete audioprocessor and a stereo decoder with noise blanker, stereo blend and all signal processing functions necessary for state-of-the-art as well as future car radio systems.
Switched-capacitors design technique allows to obtain all these features without external components or adjustments. This means that higher quality and reliability walks alongside an overall cost saving. The CSP is fully programmable by I
2
C bus interface allowing to customize key device parameters and especially filter characteristics.
The BiCMOS process combined with the optimized signal processing assure low noise and low distortion performances.
Table 1.
Device summary
Order code Package
TDA7461ND SO-28
TDA7461NDTR
E-TDA7461ND
(1)
SO-28
SO-28
SO-28
1.
Device in ECOPACK® package, see Chapter 7: Package information on page 46
.
Packing
Tube
Tape and reel
Tube
Tape and reel
January 2009 Rev 7
This is information on a product still in production but not recommended for new designs.
1/48 www.st.com
1
Contents
Contents
TDA7461
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Audio processor part feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Audio processor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Description of the audio processor part . . . . . . . . . . . . . . . . . . . . . . . . 13
Programmable input matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
How to find the right input configuration . . . . . . . . . . . . . . . . . . . . . . . . 14
2/48
TDA7461
Contents
Stereo decoder electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20
Description of stereo decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stereo decoder mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
De-emphasis and high cut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PLL and pilot tone detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
FUnctional description of the noise blanker . . . . . . . . . . . . . . . . . . . . . . . 29
Automatic noise controlled threshold adjustment (ATC) . . . . . . . . . . . . 30
Automatic threshold control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Over deviation detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Functional description of the multipath detector . . . . . . . . . . . . . . . . . . . . 31
C bus interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3/48
List of tables
List of tables
TDA7461
4/48
TDA7461
List of figures
List of figures
Relation between internal and external LEVEL voltage and setup of Stereo blend . . . . . . 29
5/48
Block diagram and pin description
1 Block diagram and pin description
TDA7461
Figure 1.
Block diagram
AM
10
CASS R
CASS L
PHONE
3
4
9
7
CDL CDG CDR
6 5
INPUT
MULTIPLEXER
+
AUTO ZERO
PHONE
MIXING
STAGE
BEEP
PH GND
8
LOUDNESS
MPX
11
80KHz
LP
PILOT
CANCELLATION
VOLUME
DEMODULATOR
+ STEREO ADJUST
+ STEREO BLEND
SMUTE
17
SOFT
MUTE
25KHz
LP
TREBLE
DIGITAL CONTROL
BASS
28
S & H
27 1 2
OUT LR
OUT LF
OUT RR
OUT RF
23
25
22
24
OUT LR
OUT LF
OUT RR
OUT RF
I
2
C BUS
18
19
SCL
SDA
16
15
MUX R
MUX L
HIGH
CUT
CONTROL
VS
21
SUPPLY
GND
20 26
CREF
PLL
PIL
DET
13
MPIN
MULTIPATH-
DETECTOR
14
MPOUT
NOISE
BLANKER
PULSE
FORMER
D
A
12
LEVEL D97AU646A
6/48
Figure 2.
Pin connection (top view)
ACINL
ACINR
CASSR
CASSL
CDR
CDGND
CDL
PH GND
PHONE
AM
MPX
LEVEL
MPIN
MPOUT
5
6
7
8
9
3
4
1
2
10
11
12
13
14
D97AU647
24
23
22
21
20
28
27
26
25
19
18
17
16
15
ACOUTL
ACOUTR
CREF
OUTLF
OUTRF
OUTLR
OUTRR
VS
GND
SDA
SCL
SMUTE
MUXR
MUXL
TDA7461 Block diagram and pin description
Table 2.
N.
Pin description
Name Function
12
13
14
10
11
8
9
6
7
4
5
1
2
3
15
16
25
26
27
28
22
23
24
17
18
19
20
21
ACINL Speaker stage input left
ACINR Speaker stage input right
CASSR Cassette input right
CASSL Cassette input left
CDR CD right channel input
CDGND Ground reference CD
CDL CD left channel input
PHGND Phone ground
PHONE Phone input
AM AM input
MPX FM input (MPX)
LEVEL Level input stereo decoder
MPIN Multipath detector input
MPOUT Multipath detector output
MUXL
MUXR
Multiplexer output left channel (stereo decoder output left selectable
(1)
Multiplexer output right channel (stereo decoder output right
SMUTE Soft mute drive
SCL I
2
C clock line
SDA I
2
C data line
GND Supply ground
VS Supply voltage
OUTRR Right rear speaker output
OUTLR Left rear speaker output
OUTRF Right front speaker output
OUTLF Left front speaker output
CREF Reference capacitor pin
ACOUTR Pre-speaker AC output right channel
ACOUTL Pre-speaker AC output left channel
1.
See data byte specification - speaker attenuator
Pin type:
I = Input
O = Output
I/O = Input/Output
S = Supply
Type
I
I
O
I
I
I
I
I
I
I
I
I
I
I
O
O
O
S
O
O
O
O
O
I
I/O
I/O
S
S
7/48
Electrical specification TDA7461
2.1 Absolute maximum ratings
Table 3.
Symbol
V
S
T amb
T stg
Absolute maximum ratings
Parameter
Operating supply voltage
Operating ambient temperature range
Storage temperature range
Value
10.5
-40 to 85
-55 to 150
Unit
V
°C
°C
2.2 Supply
Table 4.
Symbol
Supply
Parameter
V
S
I
S
SVRR
Test condition
Supply voltage
Supply current
Ripple rejection @ 1 kHz
V
S
= 9V
Audioprocessor (all filters flat)
Stereo decoder + Audioprocessor
Min.
Typ.
Max.
Unit
7.5
25
9
30
60
45
10
35
V mA dB dB
2.3 ESD
All pins are protected against ESD according to the MIL883 standard.
Table 5.
Symbol
R th j-pins
Thermal data
Parameter
Thermal resistance junction to pins max
Value
85
Unit
°C/W
8/48
TDA7461
2.5 Audio processor part feature
Electrical specification
●
●
●
●
●
●
●
●
●
●
Fully differential or quasi-differential CD and cassette stereo input
AM mono or stereo input
Phone differential or single ended input
Internal beep with 2 frequencies (selectable)
Mixable phone and beep signals
Loudness
Second order frequency response
Programmable center frequency and quality factor
15 x 1 dB steps
Selectable flat-mode (constant attenuation)
●
●
●
●
1 dB attenuator
Max. gain 20 dB
Max. attenuation 79 dB
Soft-step gain control
●
●
●
●
2 nd
order frequency response
Center frequency programmable in 4 (5) steps
DC gain programmable
7 x 2 dB steps
●
●
●
2 nd
order frequency response
Center frequency programmable in 4 steps
7 x 2 dB steps
4 independent speaker controls (1 dB steps control range 50 dB)
●
●
Direct mute
Digitally controlled softmute with 4 programmable time constants
9/48
Electrical specification TDA7461
2.6 Audio processor electrical characteristics
Table 6.
Audio processor electrical characteristics
(V
S
= 9 V; T amb
= 25 °C; R
L
= 10 k
Ω; all gains = 0 dB; f = 1 kHz; unless otherwise specified).
Parameter Test condition Min.
Typ.
Max.
Unit Symbol
Input selector
R in
V
CL
S
IN
G
IN MIN
G
IN MAX
G
STEP
Input resistance
Clipping level
Input separation
Min. input gain
Max. input gain
Step resolution all inputs except phone
V
DC
DC Steps
Adjacent gain step
G
MIN
to G
MAX
Differential CD stereo input
R in
Input resistance
CMRR Common mode rejection ratio
Differential
Common mode
V
CM
= 1 V
RMS
@ 1 kHz
V
CM
= 1 V
RMS
@ 10 kHz e
N
Output noise @ speaker output
Differential phone input
20 Hz to 20 kHz flat; all stages 0dB
R in
Input resistance
CMRR Common mode rejection ratio
Differential
Common mode
V
CM
= 1 V
RMS
@ 1 kHz
V
CM
= 1 V
RMS
@ 10 kHz
Beep control
V
RMS f
BMIN f
BMAX
Beep level
Lower beep frequency
Higher beep frequency
Mixing control
M
LEVEL
Mixing level
Source
Source
Source
Beep/Phone
Volume control
G
MAX
A
MAX
Max gain
Max attenuation
250
570
1.15
19
-83
70
20
45
45
10
20
45
45
-1
-5
-10
-1
13
1
-5
-5
70
2.2
80
-1
14
2
0
1
100
2.6
100
0
100
30
70
60
9
15
30
70
60
350
600
1.2
0
-6
-12
0
20
-79
130
130
40
15
20
40
500
630
1.25
1
-7
-14
1
1
15
3
+5
+5
21
-75 dB dB dB dB
K
Ω
K
Ω dB dB mV
Hz
KHz dB dB dB dB mV mV
K
Ω
V
RMS dB dB
K
Ω
K
Ω dB dB
μV
10/48
TDA7461 Electrical specification
Table 6.
Symbol
A
STEP
E
A
E
T
V
DC
LOudness control
A
STEP
A
MAX f
CMIN f
CMAX
Soft mute
A
MUTE
Step resolution
Max. attenuation
Lower center frequency
Higher center frequency
Mute attenuation
T
D
Audio processor electrical characteristics (continued)
(V
S
= 9 V; T amb
= 25 °C; R
L
= 10 k
Ω; all gains = 0 dB; f = 1 kHz; unless otherwise specified).
Parameter Test condition Min.
Typ.
Max.
Unit
Step resolution
Attenuation set error
Tracking error
DC steps
G = -20 to 20 dB
G = -60 to 20 dB
Adjacent attenuation steps
From 0 dB to GMIN
0.5
-1.25
-4
-3
-7
1
0
0
0.1
0.5
1.5
1.25
3
2
3
+7 dB dB dB dB mV mV
Delay time
V
THlow
V
THhigh
R
PU
V
PU
Soft step
Low threshold for SM pin
High threshold for SM pin
Internal pull-up resistor
Pull-up voltage
T
SW
Bass control
Switch time
C
RANGE
A
STEP
Control range
Step resolution
(1)
T1
T2
T3
T4
0.5
-16
180
360
60
20
200
2.5
70
5
100
0.48
0.96
40.4
324
1
-15
200
400
100
4.7
10
1
2
60
600
1
1.5
-14
220
440
130
15 ms
V
V
K
Ω
V dB ms ms ms dB dB
Hz
Hz ms f
C
Q
BASS
Center frequency
Quality factor
Q
1
Q
2
Q
3
Q
4 f
C1 f
C2 f
C3 f
C4
72
90
0.9
1.1
±13
1
54
63
1.3
1.8
±14
2
60
70
80
100
(2)
1
1.25
1.5
2
88
110
1.1
1.4
±15
3
66
77
1.7
2.2
dB dB
Hz
Hz
Hz
Hz
11/48
Electrical specification TDA7461
Table 6.
Audio processor electrical characteristics (continued)
(V
S
= 9 V; T amb
= 25 °C; R
L
= 10 k
Ω; all gains = 0 dB; f = 1 kHz; unless otherwise specified).
Parameter Test condition Min.
Typ.
Max.
Unit Symbol
DC
GAIN
Bass-DC-gain
DC = off
DC = on
Treble control
C
RANGE
A
STEP
Control range
Step resolution f
C
Center frequency f
C1 f
C2 f
C3 f
C4
Speaker attenuator
C
RANGE
A
STEP
A
MUTE
E
E
V
DC
Control range
Step resolution
Output mute attenuation
Attenuation set error
DC steps
Audio outputs
V
CLIP
R
L
C
L
R
OUT
V
DC
General
Clipping level
Output load resistance
Output load capacitance
Output Impedance
DC voltage level e
NO
Output noise
BW = 20 Hz to 20 kHz output muted all gain = 0 dB
BW = 20 Hz to 20 kHz
S/N d
Signal to noise ratio
Distortion all gain = 0 dB flat; V
O
= 2 V
RMS bass treble at 12 dB; V
O
= 2.6V
RMS
V
IN
= 1 V
RMS
; all stages 0 dB
V
IN
= 1 V
RMS
; bass & treble = 12 dB
S
C
Channel separation left/right
E
T
Total tracking error
A
V
= 0 to -20 dB
A
V
= -20 to -60 dB
1.
The SM pin is active low (Mute = 0)
2.
See description of audioprocessor part - bass & treble filter characteristics programming
-1
4
±13
1
8
10
12
14
2.2
2
3.6
-53
0.5
80
-2
80
-1
-2
0
4.4
±14
2
10
12.5
15
17.5
-50
1
90
0.1
2.6
30
3.8
3
6.5
+1
6
-47
2
2
5
10
100
4.0
15
15
106
100
0.002
0.1
0.05
0.1
100
0
0
1
2
±15
3
12
15
18
21 dB dB dB dB
KHz
KHz
KHz
KHz
V
RMS
K
Ω nF
W
V dB dB dB dB mV
μV
μV dB dB dB dB dB
%
%
12/48
TDA7461
3
Description of the audio processor part
Description of the audio processor part
●
●
●
●
●
The programmable input matrix of the TDA7461 offers several possibilities to adapt the audioprocessor to the desired application. In to the standard application we have:
CD quasi differential
Cassette stereo
Phone differential
AM mono
Stereo decoder input.
The input matrix can be configured by only 2 bits: bits 3 and 4 of subaddress 0. Basically the bit of subaddress 13 is fixed by the application and has to be programmed only once at the startup of the IC.
For many configurations the two bits are also fixed during one application (e.g. the standard application) and a change of the input source can be done by loading the first three bits of subaddress 0.
In other configurations for some sources a programming of bit 3 and 4 of subaddress 0 is necessary in addition to the three source selection bits. In every case only the subaddress 0 has to be changed to switch from one source to another.
The following picture shows the input and source programming flow:
Figure 3.
Input configuration tree
TDA7461
CD QD CD FD
APPL. 1 APPL. 2 APPL. 3 APPL. 4 APPL. 5 APPL. 6
CD QD
CASSETTE
FM STD
AM MONO
PHONE (D)
CD QD
CASSETTE
FM STD
AM STEREO
PHONE (SE)
CD QD
CASSETTE
FM STD
AM STD
PHONE (D)
CD FD
CASSETTE
FM STD
AM MONO
PHONE (SE)
CD FD
CASSETTE
FM STD
AM STEREO
CD FD
CASSETTE
FM STD
AM STD
PHONE (SE)
D97AU632B
1.
In AMSTD configuration the AM mono signal is lead through the FM stereo decoder part to use its additional filters.
13/48
Description of the audio processor part
3.1.1
TDA7461
Table 7.
Input and source programming
Pin number
Appl. N# Programming
(1)
6 8 9 10
1
2
3
4
5
6
CD
CD
CD
CDR
GND
GND
GND
CDR
CDR
GND
GND
GND
Phone
Phone
Phone
CDL
CDL
CDL
GND
GND
GND
GND
GND
GND
Phone
AMRIGHT
Phone
Phone
AMRIGHT
Phone
AM
AM
AMSTD
AM
AM
MONO
LEFT
MONO
AM
LEFT
STD
Startup
Startup
FM
AM
Phone
Startup
FM
AM
Phone
Startup
Startup
FM
AM
Startup
FM
AM
Phone
1.
Syntax 0/xxx11100 means: SUBADDRESS = 0 - DATA BYTE = xxx11100 (x - don’t care).
0/xxx11xxx
0/xxxx1xxx
0/xxx11100
0/xxx01011
0/xxx11010
0/xxxx1xxx
0/xxx11100
0/xxx01100
0/xxx11010
0/xxxx0xxx
0/xxxx0xxx
0/xxx10100
0/xxx00011
0/xxxx0xxx
0/xxx10100
0/xxx00100
0/xxx10010
How to find the right input configuration
The best way to come to the desired configuration may be to go through the application tree from the top to the bottom while making the specific decisions.
This way will lead to one of the six possible applications. Then take the number of the application and go into the pinning table. Here you will find the special pinout as well as the special programming codes for selecting sources.
For example in Appl. 6 the TDA7461 has to be configured while startup with the data byte
0/xxxx0xxx.
To select the FM, AM or phone source the last five significant bits of subaddress 0 have to be changed, for any other source the last three bits are sufficient (see data byte specification).
14/48
Most of the input circuits are the same as in previous ST audio processors with exception of
). In the meantime there are some CD players in the market having a significant high source impedance which affects strongly the common mode rejection of the normal differential input stage. The additional buffer of the CD input avoids this drawback and offers the full common mode rejection even with those CD players.
TDA7461 Description of the audio processor part
The TDA7461 can be configured with an additional input; if the AC coupling before the speaker stage is not used (bit 7 in subaddress 5 set to "1") ACINL and ACINR pins can be used as an additional stereo input.
Figure 4.
Input stages
15K 15K
CD
100K
15K
-
+
15K
CDGND
15K 15K
PHONE
15K
-
+
15K IN GAIN
PH_GND
CASSETTE
100K
AM
100K
STEREODECODER
MPX
100K
D97AU633A
3.1.3 AutoZero
In order to reduce the number of pins there is no AC coupling between the In-Gain and the following stage, so that any offset generated by or before the In-Gain stage would be transferred or even amplified to the output. To avoid that effect a special offset cancellation stage called AutoZero is implemented.
To avoid audible clicks the audioprocessor is muted before the loudness stage during this time. In some cases, for example if the
μP is executing a refresh cycle of the I 2
C bus programming, it is not useful to start a new AutoZero action because no new source is selected and an undesired mute would appear at the outputs. For such applications the
TDA7461 could be switched in the "Auto Zero Remain" mode (Bit 6 of the subaddress byte).
If this bit is set to high, the DATABYTE 0 could be loaded without invoking the AutoZero and the old adjustment value remains.
The MUX_L and MUX_R outputs can provide selectively the output of the input multiplexer
(Speaker RF register, Byte 8, bit 6=1) or the output of the stereo decoder (Speaker RF register Byte 8 bit 6=0).
If bit D3 byte 10 (Stdec Register) is set to 1, then the stdec signal is automatically muted, when another source is selected at the input multiplexer.
15/48
Description of the audio processor part TDA7461
If bit D3 byte 10 (Stdec Register) is set to 0, then the stdec signal will be always available at the Mux out pins, no matter which is the selected source.
The selection of the stereodecoder input, via a special procedure, is recommended.
1. Soft Mute or Mute the signal path
2. Temporary deselect the stereodec
3. Wait 100-200 ms to allow the stdec internal filters to settle
4. Select sterodec input (with automatic autozero)
This procedure guarantees an optimum offsetcancellation, avoiding big DC offsets due to the autozero circuitry, which otherwise could try to compensate the signal sourced at the
MPX input instead of the stereodecoder intrinsic offset.
This stage offers the possibility to mix the internal beep or the phone signal to any other source.
Due to the fact that the mixing stage is also located behind the In-Gain stage fine adjustments of the main source level can be done in this way.
3.3.1 Loudness
●
●
●
●
There are four parameters programmable in the loudness stage (see
):
Attenuation
Center frequency
Loudness Q
Flat Mode: in this mode the loudness stage works as a 0 - 15dB attenuator.
Figure 5.
Loudness attenuation @ fc = 400 Hz
(second order)
Figure 6.
Loudness center frequency @
Atten. = 15 dB (second order)
16/48
TDA7461 Description of the audio processor part
Figure 7.
Loudness attenuation = 15 dB @ fc = 400 Hz
D98AU844
(dB)
-5
-10
-15
-20
10 100 1,000 Hz
3.3.2 Softmute
The digitally controlled softmute stage allows muting/demuting the signal with a I
2
C bus
I programmable slope. The mute process can either be activated by the softmute pin or by the
2
C bus. The slope is realized in a special S shaped curve to mute slow in the critical regions
). For timing purposes the Bit 3 of the I
2
C bus output register is set to 1 from the start of muting until the end of demuting.
Figure 8.
Softmute timing
EXT.
MUTE
1
+SIGNAL
REF
-SIGNAL
1
I
2
C BUS
OUT
D97AU634
Time
1.
Please notice that a started Mute action is always terminated and could not be interrupted by a change of the mute signal.
When volume level is changed often an audible click appears at the output. The root cause of those clicks could be either a DC offset before the volume stage or the sudden change of the envelope of the audio signal. With the Soft step feature both kinds of clicks could be reduced to a minimum and are no more audible (see
).
17/48
Description of the audio processor part TDA7461
Figure 9.
Soft step timing
VOUT
2dB
1dB
Time
10ms
-1dB
-2dB
D97AU635
1.
For steps more than 1dB the soft step mode should be deactivated because it could generate a 1dB error during the blend-time.
3.3.4 Bass
There are three parameters programmable in the bass stage (see Figure 10 , 11 , 12 , 13 ):
●
●
●
Attenuation
Center Frequency (60, 70, 80 and 100 Hz)
Quality Factors (1, 1.25, 1.5 and 2)
In this mode the DC gain is increased by 4.4 dB. In addition the programmed center frequency and quality factor is decreased by 25 % which can be used to reach alternative center frequencies or quality factors.
3.3.6 Treble
There are two parameters programmable in the treble stage (see
,
):
●
●
Attenuation
Center frequency (10, 12.5, 15 and 17.5 kHz).
Due to practical aspects the steps in the speaker attenuator are not linear over the full range. At attenuations more than 24 dB the steps increase from 1.5 dB to 10 dB (please see data byte specification).
18/48
TDA7461 Description of the audio processor part
Figure 10.
Bass control @ fc = 80 Hz, Q = 1 Figure 11.
Bass center @ Gain = 14 dB, Q = 1
Figure 12.
Bass quality factors @
Gain = 14 dB, fc = 80 Hz
Figure 13.
Bass normal and DC mode @
Gain = 14 dB, fc = 80 Hz
(1)
Figure 14.
Treble control @ fc = 17.5 kHz) Figure 15.
Treble center frequencies @
Gain = 14 dB
(1) In general the center frequency, Q and DC-mode can be set independently. The exception from this rule is the mode (5/xx1111xx) where the center frequency is set to 150Hz instead of 100 Hz.
19/48
Stereo decoder part
4 Stereo decoder part
TDA7461
4.1 Stereo decoder feature
●
●
●
●
●
●
●
●
●
●
No external components necessary
PLL with adjustment free fully integrated VCO
Automatic pilot dependent mono/stereo switching
Very high suppression of intermodulation and interference
Programmable roll-off compensation
Dedicated RDS Softmute
High cut and stereo blend characteristics programmable in a wide range
Internal Noise blanker with threshold controls
Multipath detector with programmable internal/external influence
I
2
C bus control of all necessary functions
4.2 Stereo decoder electrical characteristics
Table 8.
Symbol
.
Stereo decoder electrical characteristics
(V
S
= 9 V; de-emphasis time constant = 50
μs, V
MPX
= 500 mV, 75 kHz deviation, f = 1 kHz.
G
I
= 6 dB, T amb
= 25 °C; unless otherwise specified)
Parameter Test condition Min.
Typ.
Max.
Unit
V
IN
R in
G min
G max
G
STEP
SVRR a
THD
MPX input level
Input resistance
Minimum input gain
Max input gain
Input gain = 3.5 dB
Step resolution
Supply voltage ripple rejection V ripple
= 100 mV, f = 1 kHz
Max channel separation
Total harmonic distortion
70
1.5
8.5
1.75
30
2.5
55
50
0.02
0.5
100
3.5
11
1.25
130
4.5
12.5
3.25
0.3
dB dB dB
%
V
RMS
K
Ω dB dB
S +
N
N
Signal plus noise to noise ratio S = 2 V rms
80 91 dB
Mono/stereo switch
PLL
V
PTHST1
V
PTHST0
V
PTHMO1
V
PTHMO0
Δf/f
Pilot threshold voltage
Pilot threshold voltage
Pilot threshold voltage
Pilot threshold voltage
Capture range for Stereo, PTH = 1 for Stereo, PTH = 0 for Mono, PTH = 1 for Stereo, PTH = 0
10
15
7
10
0.5
15
25
12
19
25
35
17
25 mV mV mV mV
%
20/48
TDA7461 Stereo decoder part
Table 8.
Symbol
Stereo decoder electrical characteristics (continued)
(V
S
= 9 V; de-emphasis time constant = 50
μs, V
MPX
= 500 mV, 75 kHz deviation, f = 1 kHz.
G
I
= 6 dB, T amb
= 25 °C; unless otherwise specified)
Parameter Test condition Min.
Typ.
Max.
Unit
De-emphasis and high cut
(1)
τ
HC50
τ
HC75
τ
HC50
τ
HC75
De-emphasis time constant
De-emphasis time constant
High cut time constant
High cut time constant
Bit = 7, Subadr. 10 = 0
V
LEVEL
>> V
HCH
Bit = 7, Subadr. 10 = 1
V
LEVEL
>> V
HCH
Bit = 7, Subadr. 10 = 0
V
LEVEL
>> V
HCL
Bit = 7, Subadr. 10 = 1
V
LEVEL
>> V
HCL
Stereo blend and high cut-control
REF5V Internal reference voltage
TC
REF5V
L
Gmin
L
Gmax
L
Gstep
V
SBLmin
V
SBLmax
V
SBLstep
VHCH min
VHCH max
VHCH step
VHCL min
VHCL max
Temperature coefficient
Min. level gain
Max. level gain
Level gain step resolution
Min. voltage for mono
Max. voltage for mono
Step resolution
Min.voltage for no high cut
Max. voltage for no high cut
Step resolution
Min. voltage for full high cut
Max. voltage for full high cut
Carrier and harmonic suppression at the output
α19
α38
α57
α76
Pilot signal
Sub carrier
Sub carrier
Sub carrier
Intermodulation
(2)
) f = 19 kHz f = 38 kHz f = 57 kHz f = 76 kHz
α2
α3
Pilot signal f mod
= 10 kHz f spur
= 1 kHz; f mod
= 13 kHz; f spur
= 1 kHz;
25
50
100
150
4.7
12
46
70
12
21
37
+1
12
1.0
37
62
8.4
42
66
8.4
17
33
5
3300
0
10
0.67
33
58
5.0
36
62
5
13
29
-1
8
0.3
29
54
40
50
75
150
225
50
75
62
90
65
75
75
100
200
300
5.3
μs
μs
μs
μs dB dB dB dB dB dB
V ppm dB dB dB
%REF5V
%REF5V
%REF5V
%REF5V
%REF5V
%REF5V
%VHCH
%VHCH
21/48
Stereo decoder part TDA7461
Table 8.
Symbol
Stereo decoder electrical characteristics (continued)
(V
S
= 9 V; de-emphasis time constant = 50
μs, V
MPX
= 500 mV, 75 kHz deviation, f = 1 kHz.
G
I
= 6 dB, T amb
= 25 °C; unless otherwise specified)
Parameter Test condition Min.
Typ.
Max.
Unit
Traffic radio
(3)
α57
Signal f = 57 kHz
SCA - Subsidiary communications authorization
(4)
α67
Signal
ACI - Adjacent channel interference
(5) f = 67 kHz
70
75 dB dB
α114
α190
Signal
Signal f = 114 kHz f = 190 kHz
95
84 dB dB
1.
By design/characterization but functionally guaranteed through dedicated test mode structure
2.
Intermodulation Suppression: measured with: 91% pilot signal; fm = 10kHz or 13kHz.
3.
Traffic radio (V.F.) suppression: measured with: 91 % stereo signal; 9 % pilot signal; fm=1 kHz; 5% sub carrier (f = 57 kHz, fm = 23 Hz AM, m = 60 %)
4.
SCA (subsidiary communications authorization) measured with: 81% mono signal; 9% pilot signal; fm = 1 kHz; 1 0% SCA sub carrier (fs = 6 7 kHz, unmodulated).
5.
ACI (adjacent channel interference) measured with: 90% mono signal; 9% pilot signal; fm = 1 kHz; 1% spurious signal
(fs = 110 kHz or 186 kHz, unmodulated).
22/48
TDA7461 Stereo decoder part
4.3
●
●
●
●
●
Noise blanker part
internal 2 nd
order 140 kHz high pass filter programmable trigger threshold additional circuits for trigger adjustment (deviation, field-strength) very low offset current during hold time four selectable pulse suppression times
Table 9.
Symbol
Noise blanker electrical characteristics
Parameter Test condition Min.
Typ.
V
TR
Trigger threshold
(1), (2) meas. with V
PEAK
= 0.9V
NBT = 111
NBT = 110
NBT = 101
NBT = 100
NBT = 011
NBT = 010
NBT = 001
NBT = 000
V
TRNOISE
Noise Controlled
Trigger Threshold
(3) meas. with V
PEAK
= 1.5V
NCT = 00
NCT = 01
NCT = 10
260
220
180
V
RECT
Rectifier Voltage
V
MPX
= 0mV
V
MPX
= 50mV; f = 150KHz
V
MPX
= 100mV; f = 150KHz
NCT = 11
0.5
1.5
140
0.9
1.7
OVD = 11
2.2
0.5
2.5
0.9(off)
V
RECT DEV
Deviation dependent
(4) rectifier voltage means. with
V
MPX
= 800mV
(75KHz dev.)
OVD = 10
OVD = 01
OVD = 00
0.9
1.7
2.5
1.2
2.0
2.8
FSC = 11 0.5
V
RECT FS
Fieldstrength controlled
(5) rectifier voltage means. with
V
MPX
= 0mV
V
LEVEL
<< V
SBL
(fully mono)
FSC = 10
FSC = 01
1.0
1.5
FSC = 00 2.0
1.
All thresholds are measured using a pulse with T
R
= 2
μs, T
HIGH
= 2
μs and T
F
= 10
μs.
2.
NBT represents the Noise blanker-Byte bits D2; D0 for the noise blanker trigger threshold
3.
NAT represents the Noise blanker-Byte bit pair D4,D3 for the noise controlled trigger adjustment
4.
OVD represents the Noise blanker-Byte bit pair D7,D6 for the over deviation detector
5.
FSC represents the Fieldstrength-Byte bit pair D1,D0 for the fieldstrength control
0.9(off)
1.3
1.8
2.3
30
35
40
45
50
55
60
65
Max.
1.3
2.1
2.9
1.3
1.5
2.3
3.1
1.3
1.6
2.1
2.6
Unit mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP mV
OP
V
V
V mV
OP mV
OP mV
OP mV
OP
V
V
V
V
23/48
Stereo decoder part
Figure 16.
Noise blanker diagram
VIN
VOP
DC
D97AU636 TR THIGH
Figure 17.
Trigger threshold vs. V
PEAK
VTH
TF
Time
260mV(00)
220mV(01)
180mV(10)
140mV(11)
MIN. TRIG. THRESHOLD
8 STEPS
65mV
30mV
0.9V
D97AU648
Figure 18.
Deviation controlled trigger adjustment
VPEAK
(V
OP
)
1.5V
NOISE CONTROLLED
TRIG. THRESHOLD
VPEAK(V)
00
2.8
2.0
1.2
0.9
01
10
DETECTOR OFF (11)
DEVIATION(KHz)
D97AU649 20 32.5
45 75
TDA7461
24/48
TDA7461 Stereo decoder part
Figure 19.
Fieldstrength controlled trigger adjustment
VPEAK
MONO STEREO
»3V
NOISE
2.3V(00)
1.8V(01)
1.3V(10)
ATC_SB OFF (11) noisy signal
D98AU863 good signal
0.9V
E'
●
●
●
●
Internal 19 kHz bandpass filter
Programmable bandpass and rectifier gain
Two pin solution fully independent usable for external programming
Selectable internal influence on Stereo blend
Table 10.
Multipath detector electrical characteristics
Symbol Parameter Test condition f
CMP
G
BPMP
G
RECTMP
Center frequency of multipath- bandpass
Bandpass gain
Rectifier gain stereo decoder locked on pilot tone bits D
2
, D
1
configuration byte = 00 bits D
2
, D
1
configuration byte = 01 bits D
2
, D
1
configuration byte = 10 bits D
2
, D
1
configuration byte = 11 bits D
7
, D
6
configuration byte = 00 bits D
7
, D
6
configuration byte = 01 bits D
7
, D
6
configuration byte = 10
I
CHMP
I
DISMP
Rectifier charge current
Rectifier discharge current
Min.
Typ.
Max.
Unit
19
7.6
4.6
0
1
1.5
6
16
12
18
KHz dB dB dB
μA mA dB dB dB dB
25/48
Stereo decoder part TDA7461
4.5 Description of stereo decoder
The stereo decoder part of the TDA7461 (see Figure 20
) contains all functions necessary to demodulate the MPX signal like pilot tone dependent mono/stereo switching as well as
“stereo blend” and “high cut” functions. Adaptations like programmable input gain, roll-off compensation, selectable de-emphasis time constant and a programmable fieldstrength input allow to use different IF devices.
Figure 20.
Block diagram of the stereo decoder
MPX
INGAIN
3.5 ... 11dB
STEP 2.5dB
INFILTER
LP 80KHz
4.th ORDER
DEMODULATOR
- PLOT CANC
- ROLL-OFF COMP.
- LP 25KHz
DEEMPHASIS
+ HIGHCUT t=50 or 75 μs
FM_L
FM_R
100K
PLL +
PILOT-DET.
F19
F38
STEREO
NOISE BLANKER
HOLDN
SB CONTROL
REF 5V
VSBL
HC
CONTROL
D
A
-
MPINFL
LEVEL INTERN
MULTIPATH
DETECTOR
VHCCH
VHCCL
LEVEL INPUT
LP 2.2KHZ
1.th ORDER
GAIN 0..10dB
LEVEL
MPIN
MPOUT
D97AU762
The TDA7461 has a fast and easy to control RDS mute function which is a combination of the audioprocessor softmute and the high-ohmic mute of the stereo decoder. If the stereo decoder is selected and a softmute command is sent (or activated through the SM pin) the stereo decoder will be set automatically to the high-ohmic mute condition after the audio signal has been soft muted.
Hence a checking of alternate frequencies could be performed. To release the system from the mute condition simply the unmute command must be sent: the stereo decoder is
unmuted immediately and the audioprocessor is softly unmuted. Figure 21 shows the output
signal V
O
as well as the internal stereo decoder mute signal. This influence of Softmute on the stereo decoder mute can be switched off by setting bit 3 of the Softmute byte to "0". A stereo decoder mute command (bit 0, stereo decoder byte set to "1") will set the stereo decoder in any case independently to the high-ohmic mute state.
If any other source than the stereo decoder is selected the decoder remains muted and the
MPX pin is connected to Vref to avoid any discharge of the coupling capacitor through leakage currents.
26/48
The In gain stage allows to adjust the MPX signal to a magnitude of about 1Vrms internally which is the recommended value. The 4 th
order input filter has a corner frequency of 80 kHz and is used to attenuate spikes and noise and acts as an anti aliasing filter for the following switch capacitor filters.
TDA7461 Stereo decoder part
4.5.3 Demodulator
In the demodulator block the left and the right channel are separated from the MPX signal.
In this stage also the 19 kHz pilot tone is cancelled. For reaching a high channel separation the TDA7461 offers an I
2
C bus programmable roll off adjustment which is able to compensate the lowpass behavior of the tuner section.
If the tuner attenuation at 38 kHz is in a range from 20.2 % to 31 % the TDA7461 needs no external network before the MPX pin. Within this range an adjustment to obtain at least
40 dB channel separation is possible. The bits for this adjustment are located together with the fieldstrength adjustment in one byte. This gives the possibility to perform an optimization step during the production of the carradio where the channel separation and the fieldstrength control are trimmed.
Figure 21.
Signals during stereo decoder’s soft mute
SOFTMUTE
COMMAND t
STD MUTE t
V
O
4.5.4
4.5.5
D97AU638 t
De-emphasis and high cut
The lowpass filter for the de-emphasis allows to choose between a time constant of 50
μs and 75
μs (bit D7, Stereo decoder byte).
The high cut control range will be in both cases t
HC
= 2 * t
Deemp
. Inside the high cut control range (between VHCH and VHCL) the LEVEL signal is converted into a 5 bit word which controls the lowpass time constant between t
Deemp
...3 × t
Deemp
.
There by the resolution will remain always 5 bits independently of the absolute voltage
I range between the VHCH and VHCL values. The high cut function can be switched off by
2
C bus (bit D7, Fieldstrength byte set to "0").
PLL and pilot tone detector
The PLL has the task to lock on the 19 kHz pilotone during a stereo transmission to allow a correct demodulation. The included detector enables the demodulation if the pilot tone reaches the selected pilottone threshold VPTHST. Two different thresholds are available.
The detector output (signal stereo, see block diagram) can be checked by reading the status byte of the TDA7461 via I
2
C bus.
27/48
Stereo decoder part TDA7461
4.5.7
The fieldstrength input is used to control the high cut and the stereo blend function. In addition the signal can be also used to control the noise blanker thresholds.
Level input and gain
To suppress undesired high frequency modulation on the high cut and stereo blend function the LEVEL signal is lowpass filtered firstly. The filter is a combination of a 1 st
order RC lowpass at 53 kHz (working as anti-aliasing filter) and a 1storder switched capacitor lowpass at 2.2 kHz. The second stage is a programmable gain stage to adapt the LEVEL signal internally to different IF.
The gain is widely programmable in 16 steps from 0 dB to 10 dB (step = 0.67 dB). These 4 bits are located together with the Roll-Off bits in the “Stereo decoder Adjustment” byte to simplify a possible adaptation during the production of the carradio.
Figure 22.
Internal stereo blend characteristics
4.5.8 Stereo blend control
The stereo blend control block converts the internal LEVEL voltage (LEVEL INTERN) into an demodulator compatible analog signal which is used to control the channel separation between 0dB and the maximum separation. Internally this control range has a fixed upper limit which is the internal reference voltage REF5V. The lower limit can be programmed to be 33%, 42%, 50% or 58% of REF5V (see
).
To adjust the external LEVEL voltage to the internal range two values must be defined: the
LEVEL gain L
G
and VSBL. To adjust the voltage where the full channel separation is reached (VST) the LEVEL gain LG has to be defined. The following equation can be used to estimate the gain:
L
G
=
]
The gain can be programmed through 4 bits in the "Stereo decoder-Adjustment" byte.
The MONO voltage VMO (0 dB channel separation) can be chosen selecting 33, 42, 50 or
58 % of REF5V.
28/48
TDA7461 Stereo decoder part
All necessary internal reference voltages like REF5V are derived from a band gap circuit.
Therefore they have a temperature coefficient near zero. This is useful if the fieldstrength signal is also temperature compensated.
But most IF devices apply a LEVEL voltage with a TC of 3300 ppm. The TDA7461 offers this
TC for the reference voltages, too. The TC is selectable with bit D7 of the “stereo decoder adjustment" byte.
Figure 23.
Relation between internal and external LEVEL voltage and setup of
Stereo blend
INTERNAL
VOLTAGES
REF 5V
VSBL
SETUP OF VST
LEVEL
LEVEL INTERN
INTERNAL
VOLTAGES
REF 5V
VSBL
58%
50%
42%
33%
SETUP OF VMO
LEVEL INTERN
4.5.9
VMO VST t
FIELDSTRENGHT VOLTAGE
D97AU639
VMO
VST t
FIELDSTRENGHT VOLTAGE
High cut control
The high cut control setup is similar to the stereo blend control setup: the starting point
VHCH can be set with 2 bits to be 42, 50, 58 or 66% of REF5V whereas the range can be set to be 17 or 33% of VHCH (see
).
Figure 24.
High cut characteristics
LOWPASS
TIME CONSTANT
3 • τ
Deemp
4.6
τ
Deemp
VHCL
D97AU640
VHCH FIELDSTRENGHT
FUnctional description of the noise blanker
In the automotive environment the MPX signal is disturbed by spikes produced by the ignition and for example the wiper motor. The aim of the noise blanker part is to cancel the audible influence of the spikes. Therefore the output of the stereo decoder is held at the actual voltage for 40 µs.
In a first stage the spikes must be detected but to avoid a wrong triggering on high frequency (white) noise a complex trigger control is implemented. Behind the trigger stage a pulse former generates the "blanking" pulse. To avoid any crosstalk to the signal path the noise blanker is supplied by his own biasing circuit.
29/48
Stereo decoder part TDA7461
The incoming MPX signal is highpass filtered, amplified and rectified. This second order highpass-filter has a corner frequency of 140 kHz. The rectified signal, RECT, is lowpass filtered to generate a signal called PEAK. Also noise with a frequency 140 kHz increases the
PEAK voltage. The PEAK voltage is fed to a threshold generator, which adds to the PEAK voltage a DC dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a comparator which triggers a re-triggerable monoflop. The monoflop’s output activates the sample-and-hold circuits in the signalpath for 40 µs.
The block diagram of the noiseblanker is given in Figure 25 .
There are mainly two independent possibilities for programming the trigger threshold: the low threshold in 8 steps (bits D0 to D2 of the noiseblanker byte) the noise adjusted threshold in 4 steps (bits D3 and D4 of the noiseblanker byte, see fig.
18).
The low threshold is active in combination with a good MPX signal without any noise; the
PEAK voltage is less than 1V. The sensitivity in this operation is high.
If the MPX signal is noisy the PEAK voltage increases due to the higher noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold increases, too. This particular gain is programmable in 4 steps (see
).
Figure 25.
Block diagram of the noiseblankert
MPX HIGH PASS
RECTIFIER
LOWPASS
RECT
+
+
-
VTH
PEAK
+
MONOFLOP
THRESHOLD
GENERATOR
ADDITIONAL
THRESHOLD
CONTROL
D98AU861
HOLDN
4.6.3 Automatic threshold control
Besides the noise controlled threshold adjustment there is an additional possibility for influencing the trigger threshold. It is depending on the stereo blend control.
The point where the MPX signal starts to become noisy is fixed by the RF part. Therefore also the starting point of the normal noise-controlled trigger adjustment is fixed (
).
In some cases the behavior of the noise blanker can be improved by increasing the threshold even in a region of higher fieldstrength. Sometimes a wrong triggering occurs for the MPX signal often shows distortion in this range which can be avoided even if using a low threshold.
30/48
TDA7461
4.6.4
Stereo decoder part
Because of the overlap of this range and the range of the stereo/mono transition it can be controlled by stereo blend. This threshold increase is programmable in 3 steps or switched off with bits D0 and D1 of the fieldstrength control byte.
Over deviation detector
If the system is tuned to stations with a high deviation the noise blanker can trigger on the higher frequencies of the modulation. To avoid this wrong behavior, which causes noise in the output signal, the noise blanker offers a deviation dependent threshold adjustment. By rectifying the MPX signal a further signal representing the actual deviation is obtained. It is used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3 steps with the bits D6 and D7 of the stereo decoder byte (the first step turns off the detector,
Using the internal detector the audible effects of a multipath condition can be minimized. A multipath condition is detected by rectifying the 19 kHz spectrum in the fieldstrength signal.
Selecting the "internal influence" in the configuration byte, the channel separation is automatically reduced during a multipath condition according to the voltage appearing at the
MPOUT pin.
To obtain a optimal performance an adaptation is necessary. Therefore the gain of the
19 kHz bandpass is programmable in four steps as well as the rectifier gain. The attack and decay times can be set by the external capacitor value.
During the test mode which can be activated by setting bit D0 of the testing byte and bit D5 of the subaddress byte to "1" several internal signals are available at the CASSR pin. During this mode the input resistance of 100 k
Ω is disconnected from the pin. The internal signals available are shown in the software specification.
Figure 26.
Block diagram of the multipath detector to SB
LEVEL -
VDD
DC=1
μA int. INFLUENCE
MPIN
BANDPASS
19KHz
RECTIFIER
GAIN
2 BITS
GAIN
2 BITS
MPOUT
220nF
D97AU880
31/48
Stereo decoder part TDA7461
Figure 27.
Application example 1
SOUND
EFFECTS
ACOUTR ACINR ACOUTL
V
S
=
+V
CC
9V
100nF
CASS R
CASS L
CDR
CDG
CDL
PHGND
PHONE
100nF
CASS R
100nF
CASS L
100nF
CDR
22 μF
CDG
100nF
CDL
220nF
PHONE_GND
220nF
PHONE
TDA7461
MPIN MPOUT MUXR
UNWEIGHTED
LEVEL
220nF
Note: Bit D7 of "Bass and Treble Filter characteristics" set to 1
Figure 28.
Application example 2
PRE-SPEAKER
OUTPUT
ACOUTL
V
S
ADDITIONAL
INPUT
100nF
ACOUTR ACINR
100nF
ACINL
CREF
=
+V
CC
9V
100nF OUTLF
OUTRF
CASS R
CASS L
CDR
CDG
CDL
PHGND
PHONE
100nF
CASS R
100nF
CASS L
100nF
CDR
22
μF
CDG
100nF
CDL
220nF
PHONE_GND
220nF
PHONE
TDA7461
OUTLR
OUTRR
MPX
AM
SDA
SCL
SMUTE
LEVEL
GND
MUXL
MPIN MPOUT
MUXR
UNWEIGHTED
LEVEL
220nF
Note: Bit D7 of "Bass and Treble Filter characteristics" set to 0
ACINL
CREF
OUTLF
OUTRF
OUTLR
OUTRR
MPX
AM
SDA
SCL
SMUTE
LEVEL
GND
MUXL
10
μF
220nF
220nF
10 μF
220nF
220nF
D97AU763A
D97AU764
OUTLF
OUTRF
OUTLR
OUTRR
MPX
AM
SDA
SCL
SMUTE
LEVEL
OUTLF
OUTRF
OUTLR
OUTRR
MPX
AM
SDA
SCL
SMUTE
LEVEL
32/48
TDA7461
5 I
2
C bus interface description
I
2
C bus interface description
The interface protocol comprises:
●
●
●
●
● a start condition (S) a chip address byte (the LSB bit determines read/ write transmission) a subaddress byte a sequence of data (N-bytes + acknowledge) a stop condition (P)
Figure 29.
Interface protocol diagram
CHIP ADDRESS SUBADDRESS
MSB LSB
S 1 0 0 0 1 1 0 R/W ACK
MSB
X AZ T
D97AU627
I
LSB
A3 A2 A1 A0 ACK
MSB
DATA 1 to DATA n
DATA
LSB
ACK P
S = Start
ACK = Acknowledge
AZ = AutoZero-Remain
T = Testing
I = Auto increment
P = Stop
Max. clock speed: 500 kbits/s
The transmitted data is automatically updated after each ACK.
Transmission can be repeated without new chip address.
If bit I in the subaddress byte is set to "1", the auto increment of the subaddress is enabled.
Table 11.
Transmitted data (send mode)
MSB
X X X X
SM = Soft mute activated
ST = Stereo
X = Not used
ST SM X
LSB
X
33/48
I
2
C bus interface description TDA7461
Table 12.
Subaddress (receive mode)
MSB
X AZ T I A3
0
0
0
0
1
0
0
0
0
A2
1
1
1
1
0
0
0
0
0
A1
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
1
1
1
1
0
T = Testmode
I = Auto increment
AZ = Auto Zero Remain
X = not used
LSB
FUNCTION
A0
0 Input selector
1 Loudness / Auto-Zero
0 Volume
1 Softmute / Beep
0 Bass / Treble Attenuator
1 Bass / Treble Configuration
0 Speaker attenuator LF
1 Speaker attenuator LR
0 Speaker attenuator RF
1
Speaker attenuator RR / Blank time adjust
0 Stereo decoder
1 Noise blanker
0 Fieldstrength Control
1 Configuration
0 Stereo decoder Adjustment
1 Testing
34/48
TDA7461
6 Data byte specification
Data byte specification
Table 13.
Input selector
MSB
D7 D6 D5 D4
1
0
0
1
D3
0
1
D2
0
0
0
0
1
1
1
1
0
0
1
1
D1
0
0
1
1
0
0
1
1
0
0
1
1
LSB
D0
0
0
1
1
0
1
0
1
0
1
0
1
In-gain
14 dB
12 dB
:
2 dB
0 dB
Function
Source selector
CD
Cassette
Phone
AM
Stereo Decoder
Input FM
Mute
AC inputs
CD mode
CD Full-differential
CD Quasi-diff
AM/FM mode
AM mono
AM stereo
AM through Stereo decoder
FM- Stereo decoder
0
0
:
1
1
0
0
:
1
1
0
1
:
0
1
For example to select the CD input in quasi-differential mode with gain of 8 dB the Data Byte is: 0/01111000
35/48
Data byte specification TDA7461
Table 14.
Loudness
MSB
D7 D6
0
1
D5
0
1
D4
0
1
D3
0
0
:
1
1
D2
0
0
:
1
1
D1
0
0
:
1
1
LSB
D0
Function
0
1
:
0
1
Attenuation
0 dB
-1 dB
:
-14 dB
-15 dB
Filter on off (flat)
Center frequency
200 Hz
400 Hz
Loudness Q low (1 s t order) normal (2 nd
order) must be "1” 1
Note: The attenuation is specified at high frequencies. Around the center frequency the value is different depending on the programmed attenuation (see Loudness frequency response).
36/48
TDA7461 Data byte specification
Table 15.
Mute, Beep and Mixing
MSB
D7 D6 D5
0
1
D4
0
1
D3
0
1
D2
0
0
1
1
D1
0
1
0
1
LSB
D0
0
1
Full Mix Signal
Source -12 dB + Mix-Signal -2.5 dB
Source -6 dB + Mix-Signal -6 dB
Full Source
Function
Mute
Enable Softmute
Disable Softmute
Mute time =0.48 ms
Mute time =0.96 ms
Mute time =40.4 ms
Mute time =324 ms
Stereo decoder softmute influence = off
Stereo decoder softmute influence = on
Beep
Beep Frequency = 600 Hz
Beep Frequency = 1.2 kHz
Mixing
Mix-Source = Beep
Mix-Source = Phone
1
1
0
0
0
1
0
1
Note: for more information to the Stereo decoder-Softmute-Influence please refer to the stereo decoder description.
37/48
Data byte specification TDA7461
Table 16.
Volume
MSB
D7
0
1
D6
0
0
:
0
0
0
:
0
0
0
:
1
1
D5
0
0
:
0
0
0
:
0
1
1
:
1
1
D4
0
0
:
0
0
0
:
1
0
0
:
0
0
D3
0
0
:
1
1
1
:
1
0
0
:
1
1
D2
0
0
:
1
1
1
:
1
0
0
:
1
1
D1
0
0
:
0
0
1
:
1
1
1
0
0
:
LSB
D0
0
1
:
0
1
0
:
1
0
1
0
1
:
Soft step
Function
Gain/Attenuation
+32 dB
+31 dB
:
+20 dB
+19 dB
:
+18 dB
+1 dB
:
0 dB
- 1 dB
-78 dB
-79 dB
Soft step volume = off
Soft step volume = on
Note: It is not recommended to use a gain more than 20dB for system performance reason. In general, the max. gain should be limited by software to the maximum value, which is needed for the system.
38/48
TDA7461 Data byte specification
Table 17.
Bass and treble attenuation
MSB
D7 D6 D5 D4 D3
0
0
:
0
0
1
1
:
1
1
D2
0
0
:
1
1
1
1
:
0
0
D1
0
0
:
1
1
1
1
:
0
0
LSB
D0
1
0
:
1
0
0
1
:
0
1
1
1
:
0
0
1
1
0
0
:
0
0
:
1
1
1
1
:
0
0
0
0
:
1
1
1
1
:
0
0
0
1
:
0
1
1
0
:
1
0
For example 12dB Treble and -8dB Bass give the following data byte: 0 0 1 1 1 0 0 1.
Treble steps
-14 dB
-12 dB
:
-2 dB
0 dB
:
0 dB
+2 dB
+12 dB
+14 dB
Bass steps
-14 dB
-12 dB
:
-2 dB
0 dB
:
0 dB
+2 dB
+12 dB
+14 dB
Function
39/48
Data byte specification TDA7461
Table 18.
Bass and treble filter characteristics
MSB LSB
Function
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
1
0
1
0
1
Treble
Center Frequency = 10 kHz
Center Frequency = 12.5 kHz
Center Frequency = 15 kHz
Center Frequency = 17.5 kHz
0
1
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1.
For deeper information see application examples
Bass
Center Frequency = 60 Hz
Center Frequency = 70 Hz
Center Frequency = 80 Hz
Center Frequency = 100 Hz
Center Frequency = 150 Hz
Quality factor = 1
Quality factor = 1.25
Quality factor = 1.5
Quality factor = 2
DC-Gain = 0 dB
DC-Gain = ±4.4 dB
AC Coupling
(1)
For External Connection
Internally Connection
For example Treble center frequency = 15kHz, Bass center frequency = 100Hz, Bass Q = 1 and DC = 0dB give the following DATA BYTE: 1 0 0 0 1 1 1 0
40/48
TDA7461 Data byte specification
)
Table 19.
Speaker attenuation (LF, LR, RF, RR)
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
1
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
1
1
0
0
:
1
0
1
1
1
1
0
0
0
0
0
:
1
0
1
1
1
1
1
1
1
0
0
:
0
1
1
1
1
1
1
1
1
0
0
:
1
1
0
0
0
0
0
1
0
0
0
0
0
0
:
Function
0
1
0
1
1
0
1
0
1
:
1
0
Attenuation
0 dB
:
-1 dB
-23 dB
-24.5 dB
-26 dB
-28 dB
-30 dB
-32 dB
-35 dB
-40 dB
-50 dB
Speaker Mute
Must be "1" (except RF, RR speaker; see below)
Blank Time adj. (subaddress speaker
RR)
38
μs
25.5
μs
32
μs
22
μs
Output selector for pins 15 and 16.
subaddress speaker RF)
Stereo decoder output selected
Input multiplexer output selected
41/48
Data byte specification TDA7461
Table 20.
Stereo decoder
MSB
D7 D6 D5 D4 D3 D2
1
1
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
0
1
Table 21.
Noise blanker
MSB
D7 D6 D5 D4 D3
0
1
0
1
D2
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
D1
LSB
D0
0
1
Function
STD unmuted
STD muted
IN-Gain 11 dB
IN-Gain 8.5 dB
IN-Gain 6 dB
IN-Gain 3.5 dB
Stereo decoder Unmuted with Stdec
Input selected and automatically
Muted at the selection of any other source.
Stereo decoder Unmuted whichever is the selected source.
Forced mono
Mono/stereo switch automatically
Pilot threshold high
Pilot threshold low
De-emphasis 50
μs
De-emphasis 75
μs
D1
0
0
1
1
1
1
0
0
LSB
D0
0
1
0
0
1
1
0
1
Function
Low threshold 65 mV
Low threshold 60 mV
Low threshold 55 mV
Low threshold 50 mV
Low threshold 45 mV
Low threshold 40 mV
Low threshold 35 mV
Low threshold 30 mV
Noise controlled threshold 320 mV
Noise controlled threshold 260 mV
Noise controlled threshold 200 mV
Noise controlled threshold 140 mV
Noise blanker off
Noise blanker on
Over deviation adjust 2.8 V
Over deviation adjust 2.0 V
Over deviation adjust 1.2 V
Over deviation detector off
42/48
TDA7461 Data byte specification
l
Table 22.
Field strength control
MSB
D7 D6 D5 D4 D3 D2
0
0
1
1
1
0
0
1
Table 23.
Configuration
MSB
D7 D6 D5 D4
0
1
0
1
D3
0
0
1
1
0
1
0
1
D2
D1
0
0
1
1
LSB
D0
0
1
0
1
Function
Noise blanker Field strength Adj 2.3 V
Noise blanker Field strength Adj 1.8 V
Noise blanker Field strength Adj 1.3 V
Noise blanker Field strength Adj Off
VSBL at 33 % REF 5 V
VSBL at 42 % REF 5 V
VSBL at 50 % REF 5 V
VSBL at 58 % REF 5 V
VHCH at 42 % REF 5 V
VHCH at 50 % REF 5 V
VHCH at 58 % REF 5 V
VHCH at 66 % REF 5 V
VHCL at 17 % VHCH
VHCL at 33 % VHCH
High cut OFF
High cut ON
0
0
1
1
0
1
0
1
1
0
1
1
1
0
0
0
1
0
1
0
0
1
1
D1
LSB
D0
Function
0
1
0
1
Noise rectifier discharge resistor
R = infinite
R = 56 k
Ω
R = 33 k
Ω
R =18 k
Ω
Multipath detector bandpass gain
6 dB
16 dB
12 dB
18 dB
Multipath detector internal influence
On
Off
Mute be “1”
Multipath detector reflection gain
Gain = 7.6 dB
Gain = 4.6 dB
Gain = 0 dB
Off
43/48
Data byte specification TDA7461
Table 24.
Stereo decoder adjustment
MSB
D7 D6 D5 D4 D3 D2 D1
0
1
0
0
0
:
1
0
0
0
:
1
0
0
1
:
1
0
1
0
:
1
:
1
:
1
0
0
0
:
1
:
0
0
0
1
LSB
D0
Function
0
:
0
:
1
0
1
Roll-off compensation not allowed
20.2%
:
21.9%
25.5%
:
31.0%
Level gain
0dB
0.66 dB
:
1.33 dB
10 dB
Temperature compensation at level input
TC = 0
TC = 16.7 mV/K (3300 ppm)
44/48
TDA7461 Data byte specification
Table 25.
Testing
MSB
D7 D6
0
1
D5
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D4
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D3
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
D2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D1
0
1
LSB
D0
0
1
Only if bit D5 of the subaddress (test mode bit) is set to "1"
Off
Function
Stereo decoder test signals
OFF
Test signals enabled if bit D5 of the subaddress (test mode bit) is set to
"1", too
External Clock
Internal Clock
Test signals at CASS_R
VHCCH
Level intern
Pilot magnitude
VCOCON; VCO Control Voltage
Pilot threshold
HOLDN
NB threshold
F228
VHCCL
VSBL not used not used
PEAK not used
REF5V not used
VCO
Off
On
Audio processor test mode
0
1
Note: This byte is used for testing or evaluation purposes only and must not be set to other values than the default "11111110" in the application!
45/48
Package information TDA7461
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
Figure 30. SO-28 mechanical data and package dimensions e e3
D
E
F
A a1 b b1
C c1
DIM.
mm inch
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
0.1
0.35
0.23
2.65
0.3
0.004
0.49
0.014
0.32
0.009
0.5
0.020
0.104
0.012
0.019
0.013
17.7
10
45 ° (typ.)
18.1
0.697
10.65
0.394
0.713
0.419
1.27
16.51
7.6
0.291
0.050
0.65
7.4
0.4
0.299
0.050
L
S
1.27
0.016
8 ° (max.)
OUTLINE AND
MECHANICAL DATA
SO-28
46/48
TDA7461 Revision history
Table 26.
Document revision history
Date Revision
20-Oct-2003
13-Jan-2009
6
7
Changes
Initial release.
Document reformatted.
Document status changed from datasheet to “not for new design”.
Removed all refences to DIP28 package.
Added
Table 1: Device summary on page 1
.
Updated
Section 7: Package information on page 46 .
47/48
TDA7461
Please Read Carefully:
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