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CP690HS
Active PMC Carrier Board for CompactPCI Applications
Doc. ID: 20955, Rev. 05
July 16, 2009
If it’s embedded, it’s Kontron.
Preface CP690HS
Revision History
Rev.
Publication Title: CP690HS: Active PMC Carrier Board for CompactPCI Applications
Doc. ID: 20955
Brief Description of Changes Board Index Date of Issue
0100 Initial issue
02 Added support signals for 66 MHz operation
03
04
05
Addition of Configuration chapter
General update, product name changed from CP690 to CP690HS, Appendix A, “CP-RIO6-90” added
General update
0000/0000
0000
0000
2102
5000
Jan. 00
Oct. 02
May 03
23-Jun-2005
16-Jul-2009
Imprint
Kontron Modular Computers GmbH may be contacted via the following:
MAILING ADDRESS TELEPHONE AND E-MAIL
Kontron Modular Computers GmbH
Sudetenstraße 7
D - 87600 Kaufbeuren Germany
+49 (0) 800-SALESKONTRON [email protected]
For further information about other Kontron products, please visit our Internet web site: www.kontron.com.
Disclaimer
Copyright © 2009 Kontron AG. All rights reserved. All data is for information purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Kontron and the Kontron logo and all other trademarks or registered trademarks are the property of their respective owners and are recognized. Specifications are subject to change without notice.
Page ii ID 20955, Rev. 05
CP690HS Preface
Table of Contents
Introduction ............................................................................. 1 - 3
CP-RIO6-90 Dual PIM Rear I/O Transition Module ........................ 1 - 4
System Relevant Information .................................................................. 1 - 4
PMC Connectors Pinout ....................................................... 2 - 4
CompactPCI Bus Connector ........................................................... 2 - 7
CompactPCI Connector Keying ............................................. 2 - 7
Hot Swap Support .................................................................. 2 - 7
CompactPCI Connectors J1 and J2 Pinouts .......................... 2 - 8
ID 20955, Rev. 05 Page iii
Preface CP690HS
CompactPCI Rear I/O Connectors J3 and J5 and Pinouts ...2 - 10
CP690HS Initial Installation Procedures ..................................................3 - 4
Standard Removal Procedures ................................................................3 - 5
Installation of CP690HS Peripheral Devices ...........................................3 - 6
PMC Module Installation .................................................................3 - 6
CompactPCI Signaling Voltage ...............................................3 - 7
PMC Signaling Voltage ...........................................................3 - 7
Technical Background of CompactPCI Hot Swap ....................................5 - 3
Hot Swap System ............................................................................5 - 3
The Hot Swap Backplane .......................................................5 - 4
The System Host (System Controller) ....................................5 - 5
The Hot Swap Board ..............................................................5 - 5
Software and Operating System .............................................5 - 5
Design Implementation on CP690HS ......................................................5 - 6
Power Ramping ...............................................................................5 - 6
Handle Switch .................................................................................5 - 6
ENUM# Interrupt .............................................................................5 - 6
Hot Swap Control and Status Register/Statemachine ....................5 - 6
Programming the GPIOs .................................................................5 - 8
GPIO: Output Enable Control Register - Offset 66h ...............5 - 8
GPIO Input Data Register - Offset 67h ...................................5 - 9
GPIO Output Data Register - Offset 65h ..............................5 - 10
CP690HS Voltage Ranges ......................................................................6 - 3
Voltage Ramp ..................................................................................6 - 5
Voltage Sequencing Requirements .................................................6 - 5
Rise Time Diagram .........................................................................6 - 5
Recommended Operating Conditions .............................................6 - 6
Supply Voltage Regulation ..............................................................6 - 6
Page iv ID 20955, Rev. 05
CP690HS Preface
Power Consumption of the CP690HS ..................................................... 6 - 7
Maximum Allowable Power Consumption of PMC Modules ................... 6 - 7
CompactPCI Rear I/O Interface on the CP-RIO6-90 Module .........A - 8
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Preface
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CP690HS
Page vi ID 20955, Rev. 05
CP690HS Preface
List of Tables
System Relevant Information .................................................................... 1 - 4
2-1 PMC1 and PMC2 Connectors Jn1 and Jn2 Pinouts .................................. 2 - 4
2-2 PMC1 and PMC2 Connector Jn3 Pinout ................................................... 2 - 5
2-3 PMC1 and PMC2 Connector Jn4 Rear I/O Pinouts ................................... 2 - 6
2-4 CompactPCI Bus Connector J1 Pinout ...................................................... 2 - 8
2-5 CompactPCI Bus Connector J2 Pinout ...................................................... 2 - 9
2-6 CompactPCI Rear I/O Connector J3 Pinout ............................................ 2 - 10
2-7 CompactPCI Rear I/O Connector J5 Pinout ............................................ 2 - 11
5-1 Hot Swap Control and Status Register / Statemachine ............................. 5 - 6
5-3 GPIO Output Enable Control Register - Offset 66h ................................... 5 - 9
5-5 GPIO Output Data Register - Offset 65h ................................................. 5 - 10
6-2 DC Operational Input Voltage Ranges ...................................................... 6 - 3
6-4 Power Consumption CP690HS without PMC/PIM Module ....................... 6 - 7
6-5 Maximum Allowable Power Consumption of Both PMC Modules ............. 6 - 7
A-1 PIM1 Connectors Jn0 (J10) and Jn4 (J14) Pinouts ................................... A - 6
A-2 PIM2 Connectors Jn0 (J20) and Jn4 (J24) Pinouts ................................... A - 7
A-3 CompactPCI Rear I/O Connector J3 Pinout .............................................. A - 9
A-4 CompactPCI Rear I/O Connector J5 Pinout ............................................ A - 10
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Preface
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CP690HS
Page viii ID 20955, Rev. 05
CP690HS Preface
List of Figures
2-2 CompactPCI Connectors J1, J2, J3, and J5 ........................................... 2 - 7
5-1 Illustration of Staggered Pinning on the Hot Swap Backplane .............. 5 - 4
6-1 Voltage Ramp of the CP3-SVE180 AC Power Supply ............................. 6 - 5
A-1 CP-RIO6-90 Functional Block Diagram ................................................... A - 3
A-4 CompactPCI Rear I/O Connectors J3 and J5 .......................................... A - 8
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CP690HS
Page x ID 20955, Rev. 05
CP690HS Preface
Proprietary Note
This document contains information proprietary to Kontron. It may not be copied or transmitted by any means, disclosed to others, or stored in any retrieval system or media without the prior written consent of Kontron or one of its authorized agents.
The information contained in this document is, to the best of our knowledge, entirely correct.
However, Kontron cannot accept liability for any inaccuracies or the consequences thereof, or for any liability arising from the use or application of any circuit, product, or example shown in this document.
Kontron reserves the right to change, modify, or improve this document or the product described herein, as seen fit by Kontron without further notice.
Trademarks
This document may include names, company logos and trademarks, which are registered trademarks and, therefore, proprietary to their respective owners.
Environmental Protection Statement
This product has been manufactured to satisfy environmental protection requirements where possible. Many of the components used (structural parts, printed circuit boards, connectors, batteries, etc.) are capable of being recycled.
Final disposition of this product after its service life must be accomplished in accordance with applicable country, state, or local laws or regulations.
ID 20955, Rev. 05 Page xi
Preface CP690HS
Explanation of Symbols
Caution, Electric Shock!
This symbol and title warn of hazards due to electrical shocks (> 60V) when touching products or parts of them. Failure to observe the precautions indicated and/or prescribed by the law may endanger your life/health and/or result in damage to your material.
Please refer also to the section “High Voltage Safety Instructions” on the following page.
Warning, ESD Sensitive Device!
This symbol and title inform that electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.
Please read also the section “Special Handling and Unpacking
Instructions” on the following page.
Warning!
This symbol and title emphasize points which, if not fully understood and taken into consideration by the reader, may endanger your health and/or result in damage to your material.
Note ...
This symbol and title emphasize aspects the reader should read through carefully for his or her own advantage.
Page xii ID 20955, Rev. 05
CP690HS Preface
For Your Safety
Your new Kontron product was developed and tested carefully to provide all features necessary to ensure its compliance with electrical safety requirements. It was also designed for a long fault-free life. However, the life expectancy of your product can be drastically reduced by improper treatment during unpacking and installation. Therefore, in the interest of your own safety and of the correct operation of your new Kontron product, you are requested to conform with the following guidelines.
High Voltage Safety Instructions
Warning!
All operations on this device must be carried out by sufficiently skilled personnel only.
Caution, Electric Shock!
Before installing a not hot-swappable Kontron product into a system always ensure that your mains power is switched off. This applies also to the installation of piggybacks.
Serious electrical shock hazards can exist during all installation, repair and maintenance operations with this product. Therefore, always unplug the power cable and any other cables which provide external voltages before performing work.
Special Handling and Unpacking Instructions
ESD Sensitive Device!
Electronic boards and their components are sensitive to static electricity. Therefore, care must be taken during all handling operations and inspections of this product, in order to ensure product integrity at all times.
Do not handle this product out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected.
Whenever possible, unpack or pack this product only at EOS/ESD safe work stations. Where a safe work station is not guaranteed, it is important for the user to be electrically discharged before touching the product with his/her hands or tools. This is most easily done by touching a metal part of your system housing.
It is particularly important to observe standard anti-static precautions when changing piggybacks, ROM devices, jumper settings etc. If the product contains batteries for RTC or memory backup, ensure that the board is not placed on conductive surfaces, including anti-static plastics or sponges. They can cause short circuits and damage the batteries or conductive circuits on the board.
ID 20955, Rev. 05 Page xiii
Preface CP690HS
General Instructions on Usage
In order to maintain Kontron’s product warranty, this product must not be altered or modified in any way. Changes or modifications to the device, which are not explicitly approved by Kontron and described in this manual or received from Kontron’s Technical Support as a special handling instruction, will void your warranty.
This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmental requirements. This applies also to the operational temperature range of the specific board version, which must not be exceeded. If batteries are present, their temperature restrictions must be taken into account.
In performing all necessary installation and application operations, please follow only the instructions supplied by the present manual.
Keep all the original packaging material for future storage or warranty shipments. If it is necessary to store or ship the board, please re-pack it as nearly as possible in the manner in which it was delivered.
Special care is necessary when handling or unpacking the product. Please consult the special handling and unpacking instruction on the previous page of this manual.
Page xiv ID 20955, Rev. 05
CP690HS Preface
Two Year Warranty
Kontron grants the original purchaser of Kontron’s products a
TWO YEAR LIMITED HARDWARE
WARRANTY
as described in the following. However, no other warranties that may be granted or implied by anyone on behalf of Kontron are valid unless the consumer has the express written consent of Kontron.
Kontron warrants their own products, excluding software, to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase. This warranty is not transferable nor extendible to cover any other users or long-term storage of the product.
It does not cover products which have been modified, altered or repaired by any other party than Kontron or their authorized agents. Furthermore, any product which has been, or is suspected of being damaged as a result of negligence, improper use, incorrect handling, servicing or maintenance, or which has been damaged as a result of excessive current/voltage or temperature, or which has had its serial number(s), any other markings or parts thereof altered, defaced or removed will also be excluded from this warranty.
If the customer’s eligibility for warranty has not been voided, in the event of any claim, he may return the product at the earliest possible convenience to the original place of purchase, together with a copy of the original document of purchase, a full description of the application the product is used on and a description of the defect. Pack the product in such a way as to ensure safe transportation (see our safety instructions).
Kontron provides for repair or replacement of any part, assembly or sub-assembly at their own discretion, or to refund the original cost of purchase, if appropriate. In the event of repair, refunding or replacement of any part, the ownership of the removed or replaced parts reverts to
Kontron, and the remaining part of the original guarantee, or any new guarantee to cover the repaired or replaced items, will be transferred to cover the new or repaired items. Any extensions to the original guarantee are considered gestures of goodwill, and will be defined in the
“Repair Report” issued by Kontron with the repaired or replaced item.
Kontron will not accept liability for any further claims resulting directly or indirectly from any warranty claim, other than the above specified repair, replacement or refunding. In particular, all claims for damage to any system or process in which the product was employed, or any loss incurred as a result of the product not functioning at any given time, are excluded. The extent of Kontron liability to the customer shall not exceed the original purchase price of the item for which the claim exists.
Kontron issues no warranty or representation, either explicit or implicit, with respect to its products’ reliability, fitness, quality, marketability or ability to fulfil any particular application or purpose. As a result, the products are sold “as is,” and the responsibility to ensure their suitability for any given task remains that of the purchaser. In no event will Kontron be liable for direct, indirect or consequential damages resulting from the use of our hardware or software products, or documentation, even if Kontron were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase.
Please remember that no Kontron employee, dealer or agent is authorized to make any modification or addition to the above specified terms, either verbally or in any other form, written or electronically transmitted, without the company’s consent.
ID 20955, Rev. 05 Page xv
Preface
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CP690HS
Page xvi ID 20955, Rev. 05
CP690HS Introduction
Chapter
1
Introduction
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Introduction CP690HS
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Page 1 - 2 ID 20955, Rev. 05
CP690HS Introduction
1.
Introduction
1.1
Overview
PMC modules are renowned for their flexibility and versatility of use. They afford the user wideranging system-independent solutions by means of easily interchanged or upgraded mezzanine add-on modules. The CP690HS has been designed to maximize the advantages provided by PMC modules in a 6U environment. Flexibility, versatility, convenience and ease of use have been keynotes throughout the design process. The result is a board which, although essentially a carrier for PMC modules, also includes a wide range of important features such as a PCI-to-
PCI bridge, rear I/O capability, and the ability to hot swap. Use of the hot swap feature means, of course, that all PMC modules employed on the board are effectively hot-swappable.
The CP690HS is a 6U non-intelligent, active CompactPCI carrier board with two single-size
PMC slots.
Some of the outstanding features of the CP690HS are:
• Active carrier with PCI-to-PCI bridge
• 32/64-bit, 33/66 MHz PCI bus on the CompactPCI (primary) and on the PMC (secondary) side with the following configurations:
• 32-bit/33 MHz CompactPCI bus with 32-bit and 33 MHz PMC bus
• 64-bit/66 MHz CompactPCI bus with 32/64-bit and 33/66 MHz PMC bus
• It supports the interrupts INTA, INTB, INTC, and INTD
• Software transparence: a specific software driver is required for using the hot swap feature
• It may be configured either for 3.3V or 5V signalling on the secondary PCI bus (PMC side)
• It supports all the signals of the PCI bus on its connectors Jn1 (J11/J21), Jn2 (J12/J22) and Jn3 (J13/J23)
• The two Jn4 connectors J14 and J24 provide the possibility to implement rear I/O through the CompactPCI connectors J3 and J5.
• The connectors which connect the mezzanine board with the carrier include all the signals of a 66 /33 MHz, 64/32-bit, multi-master PCI bus, the power rails for 3.3V, 5V, +12V,
-12V, V(I/O) and other specialized signals for board detection.
• A PCI-to-PCI bridge provides for coupling of the PMC side to the CompactPCI side, so that two independent PCI busses exist. The PCI-to-PCI bridge is the Pericom
PI7C8154B. It is software transparent and consequently a software driver is not required to manage data transfer between the PMC module and the CompactPCI bus.
• The CP690HS has been designed to function with all Kontron CompactPCI backplanes.
The fact that the J4 connector is not present on the CP690HS means that this carrier board can also be used in systems employing an H110 backplane.
Kontron’s PMC modules are operable in both CompactPCI and VME systems. They offer all the key benefits of PC I/O technology, namely:
• Low-cost solutions
• High performance
• A processor-independent local I/O bus
• A broad range of I/O peripheral devices
Customers who additionally require the functionality of the CP690HS in the smaller 3U form factor are referred to Kontron’s single-height PMC Module carrier board, the CP390.
ID 20955, Rev. 05 Page 1 - 3
Introduction CP690HS
1.2
Optional Modules
1.2.1
CP-RIO6-90 Dual PIM Rear I/O Transition Module
The CP-RIO6-90 rear I/O transition module has been designed for use only with the CP690HS
6U CompactPCI board from Kontron and enables the user to connect up to two PIM modules to the CP690HS.
For further information on this rear I/O transition module, refer to Appendix A, “CP-RIO6-90”.
1.3
System Relevant Information
The following system relevant information is general in nature but should still be considered when developing applications using the CP690HS.
Table 1-1: System Relevant Information
SUBJECT INFORMATION
Master/Slave Functionality
Hot Swap Compatibility
The CP690HS can operate only as a slave board.
Board Location in the System The CP690HS board must be installed in a peripheral slot of a CompactPCI backplane.
The CP690HS is hot swap capable in compliance with the PICMG 2.1 R1.0 Hot
Swap specification.
Hardware Requirements The CP690HS can be installed in any CompactPCI 6U rack.
Page 1 - 4 ID 20955, Rev. 05
CP690HS
1.4
Functional Block Diagram
Figure 1-1: Functional Block Diagram
Introduction
PMC 2
Module
J21 J22
J23 J24
J5 P5 rP5
PMC 1
Module
J11 J12
J13 J14
J3
J2
PCI-to-PCI
Bridge
Power
Controller
(Hot Swap)
CP690HS
J1
P3 rP3
P2
P1
Backplane
ID 20955, Rev. 05 Page 1 - 5
Introduction
1.5
Front Panel
Figure 1-2: Front Panel
CP 690HS
CP690HS
Page 1 - 6
HS
ID 20955, Rev. 05
CP690HS
1.6
Board Layout
Figure 1-3: Board Layout
ID 20955, Rev. 05
Introduction
PMC2
R71
5V
R72
3.3V
1 2 1 2
J5
A
63 64
1 2
B
63 64
1 2
PMC1
63 64
1 2
63 64
1 2
A
63 64
1 2
B
63 64
1 2
J3
63 64 63 64 J2
Power
Controller
Logic
PMC Coding Key Function
PMC coding key A: 3.3V
PMC coding key B: 5V
PCI-to-PCI
Bridge
J1
Page 1 - 7
Introduction CP690HS
1.7
Technical Specifications
Table 1-2: CP690HS Main Specifications
CP690HS
PCI-to-PCI Bridge
CompactPCI
Rear I/O
Hot Swap Compatible
PMC
Front Panel
Onboard Connectors
Mechanical
Power Consumption
Temperature Range
Climatic Humidity
Dimensions
Board Weight
LED
SPECIFICATIONS
•
Pericom PI7C8154B P2P bridge controller
Compliant with CompactPCI Specification PICMG
®
2.0 R 2.1
•
Peripheral operation
•
32/64-bit at 33/66 MHz master interface
•
Universal signaling support
The desired CompactPCI bus speed must be stated on the order.
•
PMC rear I/O
The CP690HS is hot swap capable in compliance with the PICMG 2.1 R1.0
Hot Swap specification.
CMC / PMC P1386 / Draft 2.4a compliant mezzanine interface
•
Jn1, Jn2, Jn3 and Jn4 PCI mezzanine connectors for standard single-size
PMC modules
•
64/32-bit, 66/ 33 MHz PCI interface
•
User-selectable configuration to 3.3 V or 5 V (default configuration 3.3 V)
•
Rear I/O supported through the CompactPCI connectors J3 and J5
•
Two PMC front panels
•
PMC interface (connectors Jn1, Jn2, Jn3, and Jn4)
•
CompactPCI connectors J1, J2, J3, and J5
6U, 4HP, CompactPCI-compliant form factor max. 3.9 W
See Chapter 6 for further details.
Operational: 0°C to 60°C Standard
-25°C to 75°C E1
Storage: -55°C to 85°C
93% RH at 40 °C, non-condensing (acc. to IEC 60068-2-78)
233.35 mm x 160 mm
275 g
System status:
• HS (blue): Hot swap control
Page 1 - 8 ID 20955, Rev. 05
CP690HS Introduction
1.8
Standards
This product complies with the requirements of the following standards:
Table 1-3: Standards
COMPLIANCE
CE
Mechanical
Environmental and Health
Aspects
Emission
TYPE
Immission
Electrical Safety
STANDARD
EN55022
EN61000-6-3
EN55024
EN61000-6-2
EN60950
Mechanical Dimensions IEEE 1101.10
Vibration (Sinusoidal) IEC60068-2-6
--
--
--
--
TEST LEVEL
Shock
Bump
Vibration, broad-band random (digital control) and guidance
Climatic Humidity
WEEE
RoHS
IEC60068-2-27
IEC60068-2-29
IEC 60068-2-64
IEC60068-2-78
Directive 2002/96/EC
Directive 2002/95/EC
10-300 [Hz]
2 [g]
1 [oct/min]
10 cycles/axis
3 axes
30 [g]
9 [ms]
3 shocks per direction
6 directions
5 [s] recovery time
15 [g]
11 [ms]
500 bumps per direction
6 directions
1 [s] recovery time
20-500Hz, 0.05[g²]
500-2000Hz, 0.005[g²]
3.5 [g RMS]
30 [min] test time/axis
3 axes
93% RH at 40 °C, non-condensing
Waste electrical and electronic equipment
Restriction of the use of certain hazardous substances in electrical and electronic equipment
ID 20955, Rev. 05 Page 1 - 9
Introduction CP690HS
1.9
Related Publications
The following publications contain information relating to this product.
Table 1-4: Related Publications
PRODUCT
CompactPCI Systems and
Boards
PMC / PIM
PUBLICATION
CompactPCI Specification 2.0, Rev. 3.0
CompactPCI Hot Swap Specification PICMG 2.1 Rev. 1.0
Draft Standard for a Common Mezzanine Card Family, P1386/Draft 2.0
Draft Standard Physical and Environment Layers for PCI Mezzanine Cards,
P1386.1/Draft 2.0
PMC I/O Module Standard VITA 36 - 199X, Draft 0.1, July 19, 1999
Page 1 - 10 ID 20955, Rev. 05
CP690HS Functional Description
Chapter
2
Functional Description
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Functional Description CP690HS
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CP690HS Functional Description
2.
Functional Description
2.1
Board Interfaces
2.1.1
PMC Slots
The two single-size PMC slots on the CP690HS provide an easy way to extend a CompactPCI system via the wide array of interfaces and functions which are available from all PMC vendors.
The secondary (PMC) side of the PCI-to-PCI bridge provides a 32/64-bit wide PCI data path with a speed of up to 66 MHz which is routed to the onboard connectors Jn1, Jn2 and Jn3.
These connectors also provide the power supply for the PMC module. The PMC slots have been designed to comply with the IEEE 1386.1 specification, which defines a PCI electrical interface for the CMC (Common Mezzanine Card) form factor.
The CP690HS has been designed to comply with the CompactPCI hot swap specification PIC-
MG 2.1 R1.0, which means that the power supply of the PMC modules will be ramped up and a reset generated whenever the board is plugged into a running system. The CP690HS provides 3.3V (default) and 5V PMC PCI signaling environment.
Figure 2-1: PMC Connectors Functions
The top two of each set of four PMC connectors are for connection to a 32-bit PCI bus.
R71
5V
R72
3.3V
1 2 1 2
PMC2
A
63
1
64
2
B
63
1
64
2
J5
63
1
64
2
63
1
64
2
1 2 1 2
Note:
The upper and lower sets of four connectors are identical in function.
A
63 64
1 2
B
63 64
1 2
PMC1
A
63
1
64
2
B
63
1
64
2
J3
For use only with Rear I/O
63 64 63 64
J2
63 64 63 64
PMC coding key A: 3.3V
PMC coding key B: 5V
This connector raises the signal capacity to 64-bit PCI bus.
Warning!
The PMC coding key must be set according to the chosen PMC voltage.
Care must be taken to ensure correct voltage configuration. Using an incorrect signalling voltage may damage the PMC module.
ID 20955, Rev. 05 Page 2 - 3
Functional Description CP690HS
2.1.1.1
PMC Connectors Pinout
Table 2-1: PMC1 and PMC2 Connectors Jn1 and Jn2 Pinouts
SIGNAL
AD[12]
AD[09]
Ground
AD[06]
AD[04]
V(I/O)
AD[02]
AD[00]
Ground
V(I/O)
FRAME#
Ground
DEVSEL#
Ground
SDONE#
PAR
V(I/O)
Ground
REQ#
V(I/O)
AD[28]
AD[25]
Ground
AD[22]
AD[19]
TCK
Ground
INTB#
BUSMODE1#
INTD#
Ground
CLK
SIGNAL
AD[11]
+5V
C/BE[0]#
AD[05]
Ground
AD[03]
AD[01]
+5V
REQ64#
AD[17]
Ground
IRDY#
+5V
LOCK#
SBO#
Ground
AD[15]
-12V
INTA#
INTC#
+5V
PCI-RSVD*
PCI-RSVD*
Ground
GNT#
+5V
AD[31]
AD[27]
Ground
C/BE[3]#
AD[21]
+5V
Jn1 (J11 / J21)
PIN PIN
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
11
13
7
9
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
SIGNAL
AD[16]
Ground
TRDY#
Ground
PERR#
+3.3V
C/BE[1]#
AD[14]
M66EN
AD[08]
AD[07]
+3.3V
PMC-RSVD
PMC-RSVD
Ground
ACK64#
Ground
+12V
TMS
TDI
Ground
PCI-RSVD*
BUSMODE2#
RST#
3.3V
PCI-RSVD*
AD[30]
Ground
AD[24]
IDSEL
+3.3V
AD[18]
Jn2 (J12 / J22)
PIN PIN
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
11
13
7
9
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
SIGNAL
C/BE[2]#
PMC-RSVD
+3.3V
STOP#
Ground
SERR#
Ground
AD[13]
AD[10]
+3.3V
PMC-RSVD
PMC-RSVD
Ground
PMC-RSVD
PMC-RSVD
+3.3V
PMC-RSVD
TRST#
TDO
Ground
PCI-RSVD*
PCI-RSVD*
+3.3V
BUSMODE3#
BUSMODE4#
Ground
AD[29]
AD[26]
+3.3V
AD[23]
AD[20]
Ground
Page 2 - 4 ID 20955, Rev. 05
CP690HS
SIGNAL
V(I/O)
AD[55]
AD[53]
Ground
AD[51]
AD[49]
Ground
AD[47]
AD[45]
V(I/O)
AD[43]
AD[41]
Ground
AD[39]
PCI-RSVD
Ground
C/BE[6]#
C/BE[4]#
V(I/O)
AD[63]
AD[61]
Ground
AD[59]
AD[57]
AD[37]
Ground
AD[35]
AD[33]
V(I/O)
PCI-RSVD
PCI-RSVD
Ground
Table 2-2: PMC1 and PMC2 Connector Jn3 Pinout
Jn3 (J13 / J23)
PIN PIN
39
41
43
33
35
37
45
47
27
29
31
21
23
25
55
57
59
49
51
53
61
63
15
17
19
9
11
13
5
7
1
3
40
42
44
34
36
38
46
48
28
30
32
22
24
26
56
58
60
50
52
54
62
64
16
18
20
10
12
14
6
8
2
4
SIGNAL
AD[56]
AD[54]
Ground
AD[52]
AD[50]
Ground
AD[48]
AD[46]
Ground
AD[44]
AD[42]
Ground
AD[40]
AD[38]
Ground
C/BE[7]#
C/BE[5]#
Ground
PAR64
AD[62]
Ground
AD[60]
AD[58]
Ground
Ground
AD[36]
AD[34]
Ground
AD[32]
PCI-RSVD
Ground
PCI-RSVD
Functional Description
ID 20955, Rev. 05 Page 2 - 5
Functional Description CP690HS
Table 2-3: PMC1 and PMC2 Connector Jn4 Rear I/O Pinouts
SIGNAL
PMC1IO31
PMC1IO33
PMC1IO35
PMC1IO37
PMC1IO39
PMC1IO41
PMC1IO43
PMC1IO45
PMC1IO47
PMC1IO49
PMC1IO51
PMC1IO53
PMC1IO55
PMC1IO57
PMC1IO59
PMC1IO61
PMC1IO63
PMC1IO1
PMC1IO3
PMC1IO5
PMC1IO7
PMC1IO9
PMC1IO11
PMC1IO13
PMC1IO15
PMC1IO17
PMC1IO19
PMC1IO21
PMC1IO23
PMC1IO25
PMC1IO27
PMC1IO29
SIGNAL
PMC1IO32
PMC1IO34
PMC1IO36
PMC1IO38
PMC1IO40
PMC1IO42
PMC1IO44
PMC1IO46
PMC1IO48
PMC1IO50
PMC1IO52
PMC1IO54
PMC1IO56
PMC1IO58
PMC1IO60
PMC1IO62
PMC1IO64
PMC1IO2
PMC1IO4
PMC1IO6
PMC1IO8
PMC1IO10
PMC1IO12
PMC1IO14
PMC1IO16
PMC1IO18
PMC1IO20
PMC1IO22
PMC1IO24
PMC1IO26
PMC1IO28
PMC1IO30
Jn4 (J14)
PIN PIN
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
11
13
7
9
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
SIGNAL
Jn4 (J24)
PIN PIN
55
57
59
61
63
47
49
51
53
39
41
43
45
31
33
35
37
23
25
27
29
15
17
19
21
11
13
7
9
1
3
5
56
58
60
62
64
48
50
52
54
40
42
44
46
32
34
36
38
24
26
28
30
16
18
20
22
8
10
12
14
2
4
6
PMC2IO31
PMC2IO33
PMC2IO35
PMC2IO37
PMC2IO39
PMC2IO41
PMC2IO43
PMC2IO45
PMC2IO47
PMC2IO49
PMC2IO51
PMC2IO53
PMC2IO55
PMC2IO57
PMC2IO59
PMC2IO61
PMC2IO63
PMC2IO1
PMC2IO3
PMC2IO5
PMC2IO7
PMC2IO9
PMC2IO11
PMC2IO13
PMC2IO15
PMC2IO17
PMC2IO19
PMC2IO21
PMC2IO23
PMC2IO25
PMC2IO27
PMC2IO29
SIGNAL
PMC2IO32
PMC2IO34
PMC2IO36
PMC2IO38
PMC2IO40
PMC2IO42
PMC2IO44
PMC2IO46
PMC2IO48
PMC2IO50
PMC2IO52
PMC2IO54
PMC2IO56
PMC2IO58
PMC2IO60
PMC2IO62
PMC2IO64
PMC2IO2
PMC2IO4
PMC2IO6
PMC2IO8
PMC2IO10
PMC2IO12
PMC2IO14
PMC2IO16
PMC2IO18
PMC2IO20
PMC2IO22
PMC2IO24
PMC2IO26
PMC2IO28
PMC2IO30
Note ...
The PMC rear I/O signals from Jn4 (J14 and J24) are routed to CompactPCI connectors J3 and J5, whose pinout is described later in this chapter.
Page 2 - 6 ID 20955, Rev. 05
CP690HS Functional Description
2.1.2
CompactPCI Bus Connector
Figure 2-2: CompactPCI Connectors J1, J2, J3, and J5
The CompactPCI interface provides all the necessary signals for data transfer as defined by the PCI Specification Rev. 2.1.
The CP690HS is connected to the CompactPCI backplane using the Pericom
PI7C8154B PCI-to-PCI bridge, which interfaces the board with a data path width of 32 or 64-bit and a speed up to 33/66MHz. All bus signals are provided on the
CompactPCI connectors J1 and J2 (64-bit extension). In addition to meeting the requirements of the interface definition of the CompactPCI Specification PICMG 2.0
R2.1, the CP690HS is designed to comply with the CompactPCI Hot Swap specification PICMG 2.1 R1.0, a consequence of which is that the CompactPCI interface of the board will be precharged when the board is plugged into a running system.
The complete CompactPCI connector configuration comprises four connectors named J1, J2, J3, and J5. Their functions are as follows:
• J1 and J2: 32/64-bit CompactPCI interface with PCI bus signals, arbitration, clock and power
• J3 and J5 have rear I/O interface functionality from the PMC module
The CP690HS is designed for a CompactPCI bus architecture. The CompactPCI standard is electrically identical to the PCI local bus. However, these systems are enhanced to operate in rugged industrial environments and to support multiple slots.
J5
J3
22
19
1
2.1.2.1
CompactPCI Connector Keying
The CompactPCI connectors support guide lugs to ensure a correct polarized mating.
The CP690HS supports universal CompactPCI VI/O signaling voltages with one common termination resistor configuration and includes a CompactPCI
VI/O voltage detection circuit. If the CompactPCI VI/O voltage is 5 V, the maximum supported CompactPCI frequency is 33 MHz.
J2
1
22
2.1.2.2
Hot Swap Support
To ensure that a board may be removed and replaced in a working bus without disturbing the system, the following additional features are required:
• Power ramping
• Precharge
• Hot swap control and status register bits
• Automatic interrupt generation whenever a board is about to be removed or replaced
• An LED to indicate that the board may be safely removed
For further information regarding the hot swap capability of the CP690HS, refer to Chapter 5.2, “Design Implementation on CP690HS”.
J1
1
25
1
F D B Z
E C A
Note:
Pinrows F and Z are GND pins.
ID 20955, Rev. 05 Page 2 - 7
Functional Description CP690HS
2.1.2.3
CompactPCI Connectors J1 and J2 Pinouts
The CP690HS is provided with two 2 mm x 2 mm pitch female CompactPCI bus connectors,
J1 and J2. The different pin lengths are related to the hot swap functionality. For further information on the hot swap functionality, refer to section 5.1.1.1, “The Hot Swap Backplane”.
Table 2-4: CompactPCI Bus Connector J1 Pinout
9
8
7
6
15
14 - 12
11
10
3
2
1
5
4
19
18
17
16
25
24
23
22
21
20
PIN ROW Z ROW A
GND 5V
GND AD[1]
GND 3.3V
GND AD[7]
GND 3.3V
GND AD[12]
GND 3V
GND SERR#
GND 3.3V
GND DEVSEL#
GND 3.3V
GND AD[18]
GND AD[21]
GND C/BE[3]#
GND AD[26]
GND AD[30]
GND REQ#
GND NC
GND NC
GND INTA#
GND NC
GND 5V
ROW B
REQ64#
5V
AD[4]
GND
AD[9]
GND
AD[15]
GND
NC
PCIXCAP
FRAME#
AD[17]
GND
IDSEL
GND
AD[29]
GND
NC
HEALTHY#
INTB#
5V
-12V
ROW C
ENUM#
V(I/O)
AD[3]
3.3V
AD[8]
V(I/O)
AD[14]
3.3V
NC
V(I/O)
IRDY#
Key Area
AD[16]
3.3V
AD[23]
V(I/O)
AD[28]
3.3V
PCI_RST#
V(I/O)
INTC#
NC
NC
GND
NC
5V
TDO
+12V
GND
AD[20]
GND
AD[25]
GND
CLK
ROW D ROW E
3.3V
AD[0]
5V
AD[6]
M66EN
AD[11]
5V
ACK64#
AD[2]
AD[5]
C/BE[0]#
AD[10]
GND
PAR
AD[13]
C/BE[1]#
GND
STOP#
PERR#
LOCK#
BD_SEL# TRDY#
GNT#
NC
INTD#
TDI
5V
C/BE[2]#
AD[19]
AD[22]
AD[24]
AD[27]
AD[31]
ROW F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND long pins (early power signals) short pins (control signals) medium-length pins
All signal names indicated in the table below refer to medium-length pins.
Page 2 - 8 ID 20955, Rev. 05
CP690HS Functional Description
Table 2-5: CompactPCI Bus Connector J2 Pinout
8
7
10
9
14
13
12
11
18
17
16
15
22
21
20
19
6
5
4
3
2
1
PIN ROW Z
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ROW A
AD35#
AD38#
AD42#
AD45#
AD49#
AD52#
AD56#
AD59#
NC
NC
NC
NC
NC
NC
NC
GND
AD63#
C/BE5
V(I/O)
NC
NC
NC
ROW B
AD34#
GND
AD41#
GND
AD48#
GND
AD55#
GND
NC
GND
NC
GND
NC
GND
GND
GND
AD62#
64EN#
NC
GND
NC
GND
ROW C
AD33#
V(I/O)
AD40#
V(I/O)
AD47#
V(I/O)
AD54#
V(I/O)
NC
NC
NC
NC
NC
NC
NC
NC
AD61#
V(I/O)
C/BE7#
NC
NC
NC medium-length pins
ROW D
GND
AD37#
GND
AD44#
GND
AD51#
GND
AD58#
GND
NC
GND
NC
NC
NC
GND
NC
GND
C/BE4#
GND
NC
NC
NC
ROW E
AD32#
AD36#
AD39#
AD43#
AD46#
AD50#
AD53#
AD57#
NC
NC
NC
NC
NC
NC
NC
NC
AD60#
PAR64
C/BE6#
NC
NC
NC
ROW F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ID 20955, Rev. 05 Page 2 - 9
Functional Description CP690HS
2.1.2.4
CompactPCI Rear I/O Connectors J3 and J5 and Pinouts
The CP690HS conducts all PMC signals through the rear I/O connectors J3 and J5. The
CP690HS board provides optional rear I/O connectivity for peripherals.
For the rear I/O feature, a suitable backplane is necessary which must be compliant with the
CompactPCI Specification PICMG 2.0 R3.0, October 1999. The pinout of the CompactPCI rear
I/O connectors J3 and J5 is compatible with all standard 6U CompactPCI passive backplanes with rear I/O support.
Table 2-6: CompactPCI Rear I/O Connector J3 Pinout
PIN ROW Z
7
6
5
4
11
10
9
8
3
2
1
15
14
13
12
19
18
17
16
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ROW D
NC
NC
NC
NC
NC
RIO_5V
PMC1IO2
PMC1IO7
PMC1IO12
PMC1IO17
PMC1IO22
PMC1IO27
PMC1IO32
PMC1IO37
PMC1IO42
PMC1IO47
PMC1IO52
PMC1IO57
PMC1IO62
ROW C
NC
NC
NC
NC
NC
RIO_3.3V
PMC1IO3
PMC1IO8
PMC1IO13
PMC1IO18
PMC1IO23
PMC1IO28
PMC1IO33
PMC1IO38
PMC1IO43
PMC1IO48
PMC1IO53
PMC1IO58
PMC1IO63
ROW B
NC
NC
NC
NC
NC
RIO_3.3V
PMC1IO4
PMC1IO9
PMC1IO14
PMC1IO19
PMC1IO24
PMC1IO29
PMC1IO34
PMC1IO39
PMC1IO44
PMC1IO49
PMC1IO54
PMC1IO59
PMC1IO64
ROW A
NC
NC
NC
NC
NC
RIO_3.3V
PMC1IO5
PMC1IO10
PMC1IO15
PMC1IO20
PMC1IO25
PMC1IO30
PMC1IO35
PMC1IO40
PMC1IO45
PMC1IO50
PMC1IO55
PMC1IO60
RIO_V(I/O)
ROW E
NC
NC
NC
NC
NC
RIO_5V
PMC1IO1
PMC1IO6
PMC1IO11
PMC1IO16
PMC1IO21
PMC1IO26
PMC1IO31
PMC1IO36
PMC1IO41
PMC1IO46
PMC1IO51
PMC1IO56
PMC1IO61
ROW F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Warning!
The RIO_XXX signals are power supply OUTPUTS to supply the rear I/O module with power. These pins MUST NOT be connected to any other power source, either within the backplane itself or within a rear I/O module.
Failure to comply with the above will result in damage to your board.
Page 2 - 10 ID 20955, Rev. 05
CP690HS Functional Description
Table 2-7: CompactPCI Rear I/O Connector J5 Pinout
PIN
ROW Z ROW A
8
7
10
9
14
13
12
11
18
17
16
15
22
21
20
19
4
3
6
5
2
1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
NC
PMC2IO5
PMC2IO10
PMC2IO15
PMC2IO20
PMC2IO25
PMC2IO30
PMC2IO35
NC
NC
NC
NC
NC
NC
NC
NC
PMC2IO40
PMC2IO45
PMC2IO50
PMC2IO55
PMC2IO60
RIO_V(I/O)
ROW B
NC
PMC2IO4
PMC2IO9
PMC2IO14
PMC2IO19
PMC2IO24
PMC2IO29
PMC2IO34
NC
NC
NC
NC
NC
NC
NC
NC
PMC2IO39
PMC2IO44
PMC2IO49
PMC2IO54
PMC2IO59
PMC2IO64
ROW C
NC
PMC2IO3
PMC2IO8
PMC2IO13
PMC2IO18
PMC2IO23
PMC2IO28
PMC2IO33
NC
NC
NC
NC
NC
NC
NC
NC
PMC2IO38
PMC2IO43
PMC2IO48
PMC2IO53
PMC2IO58
PMC2IO63
ROW D
NC
PMC2IO2
PMC2IO7
PMC2IO12
PMC2IO17
PMC2IO22
PMC2IO27
PMC2IO32
NC
NC
NC
NC
NC
NC
NC
NC
PMC2IO37
PMC2IO42
PMC2IO47
PMC2IO52
PMC2IO57
PMC2IO62
ROW E ROW F
NC
PMC2IO1
PMC2IO6
PMC2IO11
PMC2IO16
PMC2IO21
PMC2IO26
PMC2IO31
NC
NC
NC
NC
NC
NC
NC
NC
PMC2IO36
PMC2IO41
PMC2IO46
PMC2IO51
PMC2IO56
PMC2IO61
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Warning!
The RIO_XXX signals are power supply OUTPUTS to supply the rear I/O module with power. These pins MUST NOT be connected to any other power source, either within the backplane itself or within a rear I/O module.
Failure to comply with the above will result in damage to your board.
ID 20955, Rev. 05 Page 2 - 11
Functional Description CP690HS
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Page 2 - 12 ID 20955, Rev. 05
CP690HS Installation
Chapter
3
Installation
ID 20955, Rev. 05 Page 3 - 1
Installation CP690HS
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Page 3 - 2 ID 20955, Rev. 05
CP690HS Installation
3.
Installation
The CP690HS has been designed for easy installation. However, the following standard precautions, installation procedures, and general information must be observed to ensure proper installation and to preclude damage to the board, other system components, or injury to personnel.
3.1
Safety Requirements
The following safety precautions must be observed when installing or operating the CP690HS.
Kontron assumes no responsibility for any damage resulting from failure to comply with these requirements.
Caution!
If your board type is not specifically qualified as being hot swap capable, switch off the CompactPCI system power before installing the board in a free
CompactPCI slot. Failure to do so could endanger your life or health and may damage your board or system.
Note ...
Certain CompactPCI boards require bus master and/or rear I/O capability. If you are in doubt whether such features are required for the board you intend to install, please check your specific board and/or system documentation to make sure that your system is provided with an appropriate free slot in which to insert the board.
ESD Equipment!
Your carrier board and PMC module contain electrostatically sensitive devices.
Please observe the necessary precautions to avoid damage to your board:
• Discharge your clothing before touching the assembly. Tools must be discharged before use.
• Do not touch components, connector-pins or traces.
• If working at an anti-static workbench with professional discharging equipment, please do not omit to use it.
ID 20955, Rev. 05 Page 3 - 3
Installation CP690HS
3.2
CP690HS Initial Installation Procedures
The following procedures are applicable only for the initial installation of the CP690HS in a system. Procedures for standard removal are found in their respective chapters.
To perform an initial installation of the CP690HS in a system proceed as follows:
1. Ensure that the safety requirements indicated Chapter 3.1 are observed.
Warning!
Failure to comply with the instruction below may cause damage to the board or result in improper system operation.
2. Ensure that the board is properly configured for operation in accordance with application requirements before installing. For information regarding the configuration of the
CP690HS refer to Chapter 4. For the installation of CP690HS-specific peripheral devices and rear I/O devices, refer to the documentation provided with the device itself.
Warning!
Care must be taken when applying the procedures below to ensure that neither the CP690HS nor other system boards are physically damaged by the application of these procedures.
3. To install the CP690HS perform the following:
1. Carefully insert the board into the slot designated by the application requirements for the board until it makes contact with the backplane connectors.
2. Using the ejector handle, engage the board with the backplane. When the ejector handle is locked, the board is engaged.
3. Fasten the front panel retaining screws.
4. Connect all external interfacing cables to the board as required.
5. Ensure that the board and all required interfacing cables are properly secured.
4. The CP690HS is now ready for operation. For operation of the CP690HS, refer to appropriate CP690HS-specific software, application, and system documentation.
Page 3 - 4 ID 20955, Rev. 05
CP690HS Installation
3.3
Standard Removal Procedures
To remove the board proceed as follows:
1. Ensure that the safety requirements indicated in Chapter 3.1 are observed.
Warning!
Care must be taken when applying the procedures below to ensure that neither the CP690HS nor system boards are physically damaged by the application of these procedures.
2. Disconnect any interfacing cables that may be connected to the board.
3. Unscrew the front panel retaining screws.
4. Disengage the board from the backplane by first unlocking the board ejection handles and then by pressing the handles as required until the board is disengaged.
5. After disengaging the board from the backplane, pull the board out of the slot.
6. Dispose of the board as required.
ID 20955, Rev. 05 Page 3 - 5
Installation CP690HS
3.4
Installation of CP690HS Peripheral Devices
The CP690HS is designed to accommodate a variety of peripheral devices whose installation varies considerably. The following chapters provide information regarding installation aspects and not detailed procedures.
3.4.1
PMC Module Installation
1. Place the EMC gasket on the bezel of your PMC module.
2. Push the PMC bezel into the window of the front panel of the CP690HS and plug the connectors together.
3. Use four screws (M2.5 x 6mm) to fix the board.
Figure 3-1: Installation Diagram
PMC module
CP690HS Front Panel
1
2
CP690HS
PMC bezel
10mm stand-off
Page 3 - 6
3
4 *M2.5 *6mm screws
Note ...
Only one key is present on each carrier board, either 3.3V or 5V, depending on the signaling used. The two PMC modules must both be set to the same voltage, i.e. either both 3.3V or both 5V.
ID 20955, Rev. 05
CP690HS Installation
3.4.1.1
CompactPCI Signaling Voltage
The primary side of the PCI-to-PCI bridge, i.e. the CompactPCI side, has buffers either for 3.3V
or 5V signaling and is not selectable by the user.
3.4.1.2
PMC Signaling Voltage
The secondary (PMC) side of the PCI-to-PCI bridge may be configured either for a 3.3V or a
5V signaling environment. Please refer to Chapter 4, “Configuration” for jumper settings.
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Installation CP690HS
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CP690HS Configuration
Chapter
4
Configuration
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Configuration CP690HS
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CP690HS Configuration
4.
Configuration
4.1
Jumper Settings
The secondary side of the PCI-to-PCI bridge (the PMC side) may be configured either for a
3.3V or a 5V signalling environment. Configuration is effected by setting the jumpers (zero ohm resistors) R72 or R71.
Figure 4-1: Jumpers on the CP690HS
R71
5V
1 2
R72
3.3V
1 2
J5
64
1 2
63 64
1 2
Table 4-1: Jumpers Settings
R72
Closed
Open
R71
Open
Closed
DESCRIPTION
3.3V signalling
5V signalling
The default setting is indicated by using italic bold.
Warning!
No other jumper settings are permitted as serious damage or misoperation will result.
Warning!
The PMC coding key must be set according to the chosen PMC voltage.
Care must be taken to ensure correct voltage configuration. Using an incorrect signalling voltage may damage the PMC module.
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Configuration CP690HS
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CP690HS Hot Swap
Chapter
5
Hot Swap
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Hot Swap CP690HS
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CP690HS Hot Swap
5.
Hot Swap
5.1
Technical Background of CompactPCI Hot Swap
In many modern application systems downtime is costly and/or unacceptable. Server applications, telecommunications networks and automated systems requiring continuous monitoring call for a system design in which a single card can be inserted or extracted without affecting the rest of the system. The ease with which a board may be removed and replaced is dependent on the mechanical design (form factor), the possibility of deactivating the software drivers for the board (operating system) and the possibility of removing and inserting the board without disturbing the signal quality on the bus.
CompactPCI hot swap is currently the most effective way to meet this need. Staggered pins on the backplane guarantee controlled power sequencing of the board, while the signals ENUM,
BDSEL, HEALTHY and the hot swap control and status register bits may be used to control board access from the software side.
5.1.1
Hot Swap System
A hot swap system consists of a hot swap platform which comprises a hot swap backplane, the system host (CPU) with hot swap features, cooling, power supplies etc. plus the boards to be hot swapped. Hot swapping is not possible unless the operating system has the capability to enable and disable the board-specific driver during normal operation.
ID 20955, Rev. 05 Page 5 - 3
Hot Swap CP690HS
5.1.1.1
The Hot Swap Backplane
The hot swap backplane has staggered pins to ensure defined power sequencing.
Figure 5-1: Illustration of Staggered Pinning on the Hot Swap Backplane
BACKPLANE BOARD
Step 3
Step 2
Step 1
EARLY POWER *
BACK END POWER *
PCI SIGNALS
ENUM#
HEALTHY# *
BD_SEL#
ID_SEL
EXPLANATORY KEY
*EARLY POWER: a part of 5V, 3.3V, V(I/O) and GND
*BACK END POWER: the main part of 5V,
3.3V, V(I/O), +/-12V and GND
*HEALTHY: only for high availability
Note ...
Some special signals (e.g. ENUM, HEALTHY, BDSEL, etc.) have particular routing requirements.
Page 5 - 4 ID 20955, Rev. 05
CP690HS Hot Swap
5.1.1.2
The System Host (System Controller)
The System Controller must have the possibility to utilize the special signals defined by the
CompactPCI hot swap specification. If a high-availability system is used, it must additionally be able to control the hardware connection with the peripheral boards (Hardware Connection Control).
5.1.1.3
The Hot Swap Board
To ensure that a board may be removed and replaced in a working bus without disturbing the system it requires the following additional features:
• Precharge
• Power ramping
• Hot swap control and status register bits
• Automatic interrupt generation whenever a board is about to be removed or replaced.
• An LED to indicate that the board may be safely removed.
5.1.1.4
Software and Operating System
In a hot swap environment the software driver and the operating system have the following additional requirements:
• The OS must provide the possibility to initialize PCI devices during normal operation whenever required (allocate resources).
• The OS must provide the possibility to load or unload software drivers during normal operation whenever required.
ID 20955, Rev. 05 Page 5 - 5
Hot Swap CP690HS
5.2
Design Implementation on CP690HS
5.2.1
Power Ramping
On the CP690HS, a special hot swap controller is used to ramp up the supply voltage of the
PMC modules (Back-End Power). This is done to avoid transients on the 3.3V and the 5V power supplies from the hot swap system. When the power supply is stable, the hot swap controller generates a reset on the PMC slots to put the devices into a definite state.
5.2.2
Precharge
Precharge is provided on the CP690HS by a resistor on each signal line (PCI bus), connected to a 1V reference voltage.
5.2.3
Handle Switch
A microswitch is situated in the extractor handle. Opening the handle initiates the generation of the ENUM interrupt (produced by the onboard logic).
5.2.4
ENUM# Interrupt
The onboard logic generates a low active interrupt signal to indicate that the board is about to be extracted from the system or inserted into the system.
5.2.5
Hot Swap Control and Status Register/Statemachine
All hot swap peripheral boards provide a Hot Swap Control and Status Register which provides information on the current state of the board. The defined bits in this register set are named, as follows:
Table 5-1: Hot Swap Control and Status Register / Statemachine
BIT
EXT
INS
LOO
EIM
FUNCTION
Indication of extraction process
Indication of insertion process
Led on
ENUM mask bit
These bits are implemented into the onboard logic. Since on-chip registers handle read and write accesses in the same way, it is necessary to exercise care when configuring the
PCI-to-PCI GPIOs (General Purpose I/Os).
Page 5 - 6 ID 20955, Rev. 05
CP690HS Hot Swap
Table 5-2: Hot Swap Register Bits
BIT
EXT
INS
LOO
EIM
SIGNAL ON
PERICOM PI7C8154B
GPIO[2]
GPIO[3]
GPIO[0]
GPIO[1]
Warning!
GPIO[2:3] have to be configured as inputs. A different configuration may damage your bridge device.
ID 20955, Rev. 05 Page 5 - 7
Hot Swap CP690HS
Figure 5-2: Hot Swap State Machine
Power on Slot empty
EXT: 0
INS: 0
ENUM#: 1
DISCONNECT#: 1
LED#: 1
HANDLE: closed
EIM: 0
LOO: 0
FFs valid: 0
Insertion
EXT: 0
INS: 0
ENUM#: 1
DISCONNECT#: 1
LED#: 1
Handle: open
EIM: 0
LOO: 0
FFs valid: 0
Toggle
EIM and LOO
EXT: 0
INS: 0
ENUM#: 1
DISCONNECT#: 1
LED#: 1
Handle: closed
EIM: 0
LOO: 0
FFs valid: 1
#: low active signal
Toggle
EIM and LOO
Extraction armed
EXT: 0
INS: 1
ENUM#: 0
DISCONNECT#: 1
LED#: 1
Handle: closed
EIM: 0
LOO: 0
FFs valid: 1
Extraction
Close Handle
Physical
Extraction:
Handle is open
Physical
Insertion:
Power
Ramping,
Handle is open
Disconnected
EXT: 0
INS: 0
ENUM#: 1
DISCONNECT#: 0
LED#: 0
Handle: open
EIM: 0
LOO: 1
FFs valid: 1
Open Handle
FFs valid: PLD-internal Flip-Flops are valid.
EXT: 1
INS: 0
ENUM#: 0
DISCONNECT#: 1
LED#: 1
Handle: open
EIM: 0
LOO: 0
FFs valid: 1
Toggle
EIM and LOO followed by
Setting LOO
5.2.6
Programming the GPIOs
This sub-chapter provides information for programming the GPIOs (General Purpose I/Os) of the PCI-to-PCI bridge.
5.2.6.1
GPIO: Output Enable Control Register - Offset 66h
This section describes the GPIO for the Output Enable Control Register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = x0xxb
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CP690HS Hot Swap
Table 5-3: GPIO Output Enable Control Register - Offset 66h
Dword BIT
19:16
NAME
GPIO output enable write-1-to-clear
R/W
R/W1TC
DESCRIPTION
The gpio<3:0> output enable control write-1-to-clear. Writing 1 to any of these bits configures the corresponding gpio<3:0> pin as an input only; that is, the output driver is tristated.
Writing 0 to this register has no effect.
When read, reflects the last value written.
23:20 GPIO output enable write-1-to-set
R/W1TS
Reset value: 0 (all pins are input only).
The gpio<3:0> output enable control write-1-to-set. Writing 1 to any of these bits configures the corresponding gpio<3:0> pin as bidirectional, that is, enables the output driver and drives the value set in the output data register (65h).
Writing 0 to this register has no effect.
When read, reflects the last value written.
Reset value: 0 (all pins are input only).
5.2.6.2
GPIO Input Data Register - Offset 67h
This section describes the GPIO input data register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = 0xxxb
Table 5-4: GPIO Input Data Register - Offset 67h
Dword BIT
27:24
31:28
NAME
Reserved
GPIO input
R/W
R
R
DESCRIPTION
Reserved. Returns 0 when read.
This read-only register reads the state of the gpio<3:0> pins.
This state is updated on the
PCI clock cycle following a change in the gpio pins.
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Hot Swap CP690HS
5.2.6.3
GPIO Output Data Register - Offset 65h
This section describes the GPIO output data register.
Dword address = 64h
Byte enable p_cbe_1<3:0> = xx0xb
Table 5-5: GPIO Output Data Register - Offset 65h
Dword BIT
11:8
NAME
GPIO output enable write-1-to-clear
R/W
R/W1TC
DESCRIPTION
The gpio<3:0> pin output data write-1-to-clear. Writing 1 to any of these bits drives the corresponding bit low on the gpio<3:0> bus if it is programmed as bi-directional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to gpio pins that are programmed as input only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
15:12 GPIO output enable write-1-to-set
R/W1TS
Reset value: 0.
The gpio<3:0> pin output data write-1- to-set. Writing 1 to any of these bits drives the corresponding bit high on the gpio<3:0> bus if it is programmed as bi-directional. Data is driven on the PCI clock cycle following completion of the configuration write to this register. Bit positions corresponding to gpio pins that are programmed as input only are not driven.
Writing 0 to these bits has no effect.
When read, reflects the last value written.
Reset value: 0.
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CP690HS Power Considerations
Chapter
6
Power Considerations
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Power Considerations CP690HS
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CP690HS Power Considerations
6.
Power Considerations
6.1
System Power
The considerations presented in the ensuing sections must be taken into account by system integrators when specifying the CP690HS system environment.
6.2
CP690HS Voltage Ranges
The CP690HS board itself has been designed for optimal power input and distribution. Still it is necessary to observe certain criteria essential for application stability and reliability.
The table below indicates the absolute maximum input voltage ratings that must not be exceeded. Power supplies to be used with the CP690HS should be carefully tested to ensure compliance with these ratings.
Table 6-1: Absolute Maximum Ratings
SUPPLY VOLTAGE
3.3 V
5 V
+12 V
-12 V
ABSOLUTE MAXIMUM RATINGS
3.6 V
5.5 V
+14.0 V
-14.0 V
Warning!
The maximum permitted voltage indicated in the table above must not be exceeded. Failure to comply with the above may result in damage to your board.
The following table specifies the ranges for the different input power voltages within which the board is functional. The CP690HS is not guaranteed to function if the board is not operated within the prescribed limits.
Table 6-2: DC Operational Input Voltage Ranges
INPUT SUPPLY
VOLTAGE
3.3 V
5 V
+12 V
-12 V
ABSOLUTE
RANGE
3.2 V min. to 3.47 V max.
4.85 V min. to 5.25 V max.
11.4 V min. to 12.6 V max.
-11.4 V min. to -12.6 V max.
RECOMMENDED
RANGE
3.3 V min. to 3.47 V max.
5.0 V min. to 5.25 V max.
12 V min. to 12.6 V max.
-12 V min. to -12.6 V max.
REMARKS
Main voltage
Main voltage
Not required
Not required
ID 20955, Rev. 05 Page 6 - 3
Power Considerations CP690HS
6.3
Backplane Requirements
Backplanes to be used with the CP690HS must be adequately specified. The backplane must provide optimal power distribution for the 3.3 V, 5 V, +12 V and -12V power inputs. It is recommended to use only backplanes which have two power planes for the 3.3 V and 5 V voltages.
Input power connections to the backplane itself should be carefully specified to ensure a minimum of power loss and to guarantee operational stability. Long input lines, under-dimensioned cabling or bridges, high-resistance connections, etc. must be avoided. It is recommended to use POSITRONIC or M-type connector backplanes and power supplies where possible.
6.4
Power Supply Units
Power supplies for the CP690HS must be specified with enough reserve for the remaining system consumption. In order to guarantee a stable functionality of the system, it is recommended to provide more power than the system requires. An industrial power supply unit should be able to provide at least twice as much power as the entire system requires. An ATX power supply unit should be able to provide at least three times as much power as the entire system requires.
As the design of the CP690HS has been optimized for minimal power consumption, the power supply unit shall be stable even without minimum load.
Where possible, power supplies which support voltage sensing should be used. Depending on the system configuration this may require an appropriate backplane. The power supply should be sufficient to allow for die resistance variations.
Note ...
Non-industrial ATX PSUs require a greater minimum load than a single
CP690HS is capable of creating. When a PSU of this type is used, it will not power up correctly and the CP690HS may hang up. The solution is to use an industrial PSU or to add more load to the system.
If DC/DC power supplies are used, please ensure that the external main supply provides sufficient power in order to start-up the system properly. The external main supply should provide at least as much power as the system power supply is able to provide taking into consideration the inrush current.
Warning!
An under-dimensioned power supply may cause damage to system components.
The start-up behavior of CompactPCI and PCI (ATX) power supplies is critical for all new CompactPCI boards. These boards require a defined power of sequence and start-up behavior of the power supply. For information on the required behavior refer to the power supply specifications on the formfactors.org web site and to the CompactPCI (PICMG) specification on the picmgeu.org web site.
Page 6 - 4 ID 20955, Rev. 05
CP690HS Power Considerations
6.4.1
Voltage Ramp
Power supplies must comply with the following guidelines, in order to be used with the
CP690HS.
• Beginning at 10% of the nominal output voltage, the voltage must rise within
> 0.1 ms to < 20 ms to the specified regulation range of the voltage. Typically:
> 5 ms to < 15 ms.
• There must be a smooth and continuous ramp of each DC output voltage from
10% to 90% of the regulation band.
• The slope of the turn-on waveform shall be a positive, almost linear voltage increase and have a value from 0 V to nominal Vout.
6.4.2
Voltage Sequencing Requirements
The 5 VDC output level must always be equal to or higher than the 3.3 VDC output during power-up and normal operation.
6.4.3
Rise Time Diagram
The following figure illustrates an example of the recommended voltage ramp of a CompactPCI power supply for all Kontron boards delivered up to now.
Figure 6-1: Voltage Ramp of the CP3-SVE180 AC Power Supply
ID 20955, Rev. 05 Page 6 - 5
Power Considerations CP690HS
6.4.4
Recommended Operating Conditions
The tolerance of the voltage lines is described in the CompactPCI specification (PICMG 2.0
R3.0).The recommended measurement point for the voltage is the CompactPCI connector on the CP690HS.
The output voltage overshoot generated during the application (load changes) or during the removal of the input voltage must be less than 5% of the nominal value. No voltage of reverse polarity may be present on any output during turn-on or turn-off.
The following table provides information regarding the required characteristics for each board input voltage.
Table 6-3: Input Voltage Characteristics
VOLTAGE
5 V
3.3 V
+12 V
-12 V
VI/O
(PCI signaling voltage)
GND
NOMINAL VALUE
5.0 VDC
3.3 VDC
+12 VDC
-12 VDC
3.3 VDC or 5 VDC
TOLERANCE
+5%/-3%
+5%/-3%
+5%/-5%
+5%/-5%
+5%/-3%
Ground, not directly connected to protective earth (PE)
MAX. RIPPLE (p-p)
50 mV
50 mV
240 mV
240 mV
50 mV
6.4.5
Supply Voltage Regulation
The power supply shall be unconditionally stable under line, load, unload and transient load conditions including capacitive loads. The operation of the power supply must be consistent even without the minimum load on all output lines.
Note ...
Non-industrial ATX PSUs require a greater minimum load than a single
CP690HS is capable of creating. When a PSU of this type is used, it will not power up correctly and the CP690HS may hang up. The solution is to use an industrial PSU or to add more load to the system.
Note ...
If the main power input is switched off, the supply voltages will not go to 0V instantly. It will take a couple of seconds until capacitors are discharged. If the voltage rises again before it has gone below a certain level, the circuits may enter a latch-up state where even a hard RESET will not help any more. The system must be switched off for at least 3 seconds before it may be switched on again. If problems still occur, turn off the main power for 30 seconds before turning it on again.
Page 6 - 6 ID 20955, Rev. 05
CP690HS Power Considerations
6.5
Power Consumption of the CP690HS
The goal of this description is to provide a method to calculate the power consumption for the
CP690HS and additional PMC/PIM modules.
Table 6-4: Power Consumption CP690HS without PMC/PIM Module
POWER
5 V
3.3 V
CP690HS WITHOUT PMC / PIM MODULE
max. 1.2 W max. 2.7 W
For further information on the power consumption of the CP690HS, please contact Kontron.
6.6
Maximum Allowable Power Consumption of PMC Modules
The following table indicates the total power consumption of both PMC modules that is permitted in order to be used on the CP690HS. Overcurrent security for the PMC modules is provided by the power controller.
Table 6-5: Maximum Allowable Power Consumption of Both PMC Modules
POWER
5 V
3.3 V
POWER CONSUMPTION OF BOTH PMC MODULES
MAX. POWER CONSUMPTION
RANGE
4.0 A - 6.0 A
4.0 A - 6.0 A
TYPICAL
POWER CONSUMPTION
5.0 A
5.0 A
Note ...
An extremely high inrush current of the PMC modules can lead to system instability or improper operation.
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Chapter
7
System Considerations
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CP690HS System Considerations
7.
System Considerations
It is the responsibility of the system integrator to ensure that sufficient air flow or cooling is provided for proper operation of the CP690HS and associated PMC modules.
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System Considerations CP690HS
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CP690HS CP-RIO6-90
CP-RIO6-90
ID 20955, Rev. 05 Page A - 1
CP-RIO6-90 CP690HS
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CP690HS CP-RIO6-90
A.
CP-RIO6-90
A.1
Introduction
The CP-RIO6-90 rear I/O transition module has been designed for use only with the CP690HS
6U CompactPCI board from Kontron and enables the user to connect up to two PIM modules to the CP690HS.
The CP-RIO6-90 is plugged in from the back of the system into the backplane connectors rP3 and rP5 in line with the CP690HS.
Note ...
The CP-RIO6-90 can be used only with the CP690HS hardware index 01 or higher (new rear I/O pinout), it cannot be used with the hardware index 00.
A.2
Functional Block Diagram
Figure A-1: CP-RIO6-90 Functional Block Diagram
J21 J22
PMC 2
Module
J23 J24
J5 P5 rP5 J5
J20
J24
PIM 2
Module
J11 J12
PMC 1
Module
J13 J14
J3
J2
P3 rP3
J3
P2
CP690HS
J1 P1
Backplane
J10
J14
PIM 1
Module
CP-RIO6-90
ID 20955, Rev. 05 Page A - 3
CP-RIO6-90
A.3
CP-RIO6-90 Front Panel
Figure A-2: CP-RIO6-90 Front Panel
CP690HS
Page A - 4 ID 20955, Rev. 05
CP690HS
A.4
CP-RIO6-90 Board Layout
Figure A-3: CP-RIO6-90 Board Layout
J5
1 2
63 64
1 2
PIM 2
63 64
1 2
J3
63 64
1 2
PIM 1
63 64
CP-RIO6-90
ID 20955, Rev. 05 Page A - 5
CP-RIO6-90 CP690HS
A.5
Module Interfaces
A.5.1
PIM Interfaces
Up to two PIM modules can be connected to the CP-RIO6-90 via the four 64-pin, female connectors J10, J14, J20, J24. The following tables indicate the pinouts of the PIM connectors.
Table A-1: PIM1 Connectors Jn0 (J10) and Jn4 (J14) Pinouts
SIGNAL
NC
NC
NC
NC
NC
NC
RIO_5V
NC
NC
RIO_5V
NC
NC
NC
GND
NC
NC
RIO_5V
NC
NC
NC
GND
NC
NC
NC
NC
NC
GND
NC
NC
NC
RIO_5V
NC
SIGNAL SIGNAL
PIM1[17]
PIM1[19]
PIM1[21]
PIM1[23]
PIM1[25]
PIM1[27]
PIM1[29]
PIM1[31]
PIM1[33]
PIM1[35]
PIM1[37]
PIM1[39]
PIM1[41]
PIM1[43]
PIM1[01]
PIM1[03]
PIM1[05]
PIM1[07]
PIM1[09]
PIM1[11]
PIM1[13]
PIM1[15]
PIM1[45]
PIM1[47]
PIM1[49]
PIM1[51]
PIM1[53]
PIM1[55]
PIM1[57]
PIM1[59]
PIM1[61]
PIM1[63]
NC
NC
NC
NC
RIO_3.3V
NC
NC
NC
GND
NC
NC
NC
RIO_3.3V
NC
NC
NC
GND
NC
NC
NC
RIO_3.3V
NC
NC
NC
GND
NC
NC
NC
RIO_3.3V
NC
NC
NC
Jn0 (J10)
PIN PIN
39
41
43
31
33
35
37
25
27
29
17
19
21
23
9
11
5
7
13
15
1
3
45
47
49
51
53
55
57
59
61
63
40
42
44
32
34
36
38
26
28
30
18
20
22
24
10
12
6
8
14
16
2
4
46
48
50
52
54
56
58
60
62
64
SIGNAL
PIM1[18]
PIM1[20]
PIM1[22]
PIM1[24]
PIM1[26]
PIM1[28]
PIM1[30]
PIM1[32]
PIM1[34]
PIM1[36]
PIM1[38]
PIM1[40]
PIM1[42]
PIM1[44]
PIM1[02]
PIM1[04]
PIM1[06]
PIM1[08]
PIM1[10]
PIM1[12]
PIM1[14]
PIM1[16]
PIM1[46]
PIM1[48]
PIM1[50]
PIM1[52]
PIM1[54]
PIM1[56]
PIM1[58]
PIM1[60]
PIM1[62]
PIM1[64]
Jn4 (J14)
PIN PIN
39
41
43
31
33
35
37
25
27
29
17
19
21
23
9
11
5
7
13
15
1
3
45
47
49
51
53
55
57
59
61
63
40
42
44
32
34
36
38
26
28
30
18
20
22
24
10
12
6
8
14
16
2
4
46
48
50
52
54
56
58
60
62
64
Page A - 6 ID 20955, Rev. 05
CP690HS CP-RIO6-90
Table A-2: PIM2 Connectors Jn0 (J20) and Jn4 (J24) Pinouts
SIGNAL
RIO_5V
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
NC
NC
NC
RIO_5V
NC
NC
NC
NC
RIO_5V
NC
NC
NC
GND
NC
NC
NC
RIO_RIO_
SIGNAL
NC
RIO_RIO_
NC
NC
NC
GND
NC
NC
NC
RIO_3.3V
NC
NC
NC
GND
NC
NC
NC
GND
NC
NC
NC
NC
NC
NC
RIO_3.3V
NC
NC
NC
RIO_3.3V
NC
NC
NC
Jn0 (J20)
PIN PIN
43
45
47
49
37
39
41
31
33
35
23
25
27
29
57
59
61
51
53
55
63
17
19
21
11
13
15
1
7
9
3
5
44
46
48
50
38
40
42
32
34
36
24
26
28
30
58
60
62
52
54
56
64
18
20
22
12
14
16
2
8
10
4
6
SIGNAL
PIM2[24]
PIM2[26]
PIM2[28]
PIM2[30]
PIM2[32]
PIM2[34]
PIM2[36]
PIM2[38]
PIM2[40]
PIM2[42]
PIM2[44]
PIM2[46]
PIM2[48]
PIM2[50]
PIM2[02]
PIM2[04]
PIM2[06]
PIM2[08]
PIM2[10]
PIM2[12]
PIM2[14]
PIM2[16]
PIM2[18]
PIM2[20]
PIM2[22]
PIM2[52]
PIM2[54]
PIM2[56]
PIM2[58]
PIM2[60]
PIM2[62]
PIM2[64]
Warning!
The RIO_XXX signals indicated in tables A-1 and A-2 are power supply
INPUTS to supply the rear I/O module with power. These pins MUST NOT be connected to any other power source, either within the backplane itself or within a rear I/O module.
Failure to comply with the above will result in damage to your board.
Jn4 (J24)
PIN PIN
43
45
47
49
37
39
41
31
33
35
23
25
27
29
57
59
61
51
53
55
63
17
19
21
11
13
15
1
7
9
3
5
44
46
48
50
38
40
42
32
34
36
24
26
28
30
58
60
62
52
54
56
64
18
20
22
12
14
16
2
8
10
4
6
SIGNAL
PIM2[23]
PIM2[25]
PIM2[27]
PIM2[29]
PIM2[31]
PIM2[33]
PIM2[35]
PIM2[37]
PIM2[39]
PIM2[41]
PIM2[43]
PIM2[45]
PIM2[47]
PIM2[49]
PIM2[01]
PIM2[03]
PIM2[05]
PIM2[07]
PIM2[09]
PIM2[11]
PIM2[13]
PIM2[15]
PIM2[17]
PIM2[19]
PIM2[21]
PIM2[51]
PIM2[53]
PIM2[55]
PIM2[57]
PIM2[59]
PIM2[61]
PIM2[63]
ID 20955, Rev. 05 Page A - 7
CP-RIO6-90 CP690HS
A.5.2
CompactPCI Rear I/O Interface on the CP-RIO6-90 Module
The CP-RIO6-90 is equipped with two female CompactPCI rear I/O connectors, J3 and J5.
Figure A-4: CompactPCI Rear I/O Connectors J3 and J5
22
J5
1
Page A - 8
J3
19
1
Note:
Pinrow F: GND
Pinrow Z: NC
A B C D E
Z F
ID 20955, Rev. 05
CP690HS CP-RIO6-90
The following tables provide the pinouts of the CompactPCI rear I/O connectors, J3 and J5. The same pinouts apply to the matching rear I/O connectors rP3 and rP5 located on the backplane.
Table A-3: CompactPCI Rear I/O Connector J3 Pinout
Z
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PIN
5
4
7
6
9
8
11
10
3
2
1
15
14
13
12
19
18
17
16
A B C D E F
RIO_5V
NC
NC
NC
RIO_5V
NC
NC
NC
RIO_3.3V
GND
GND
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
RIO_3.3V
NC
RIO_3.3V
GND
RIO_3.3V
NC
RIO_5V
NC-
NC
GND
NC
PMC1_IO[05] PMC1_IO[04] PMC1_IO[03] PMC1_IO[02] PMC1_IO[01] GND
PMC1_IO[10] PMC1_IO[09] PMC1_IO[08] PMC1_IO[07] PMC1_IO[06] NC
GND
NC
GND
NC
PMC1_IO[15] PMC1_IO[14] PMC1_IO[13] PMC1_IO[12] PMC1_IO[11] GND
PMC1_IO[20] PMC1_IO[19] PMC1_IO[18] PMC1_IO[17] PMC1_IO[16]
PMC1_IO[25] PMC1_IO[24] PMC1_IO[23] PMC1_IO[22] PMC1_IO[21]
NC
GND
PMC1_IO[30] PMC1_IO[29] PMC1_IO[28] PMC1_IO[27] PMC1_IO[26]
NC
PMC1_IO[35] PMC1_IO[34] PMC1_IO[33] PMC1_IO[32] PMC1_IO[31]
GND
PMC1_IO[40] PMC1_IO[39] PMC1_IO[38] PMC1_IO[37] PMC1_IO[36] NC
PMC1_IO[45] PMC1_IO[44] PMC1_IO[43] PMC1_IO[42] PMC1_IO[41] GND
PMC1_IO[50] PMC1_IO[49] PMC1_IO[48] PMC1_IO[47] PMC1_IO[46] NC
PMC1_IO[55] PMC1_IO[54] PMC1_IO[53] PMC1_IO[52] PMC1_IO[51] GND
PMC1_IO[60] PMC1_IO[59] PMC1_IO[58] PMC1_IO[57] PMC1_IO[56]
NC PMC1_IO[64] PMC1_IO[63] PMC1_IO[62] PMC1_IO[61]
NC
GND
Warning!
The RIO_XXX signals are power supply INPUTS to supply the rear I/O module with power. These pins MUST NOT be connected to any other power source, either within the backplane itself or within a rear I/O module.
Failure to comply with the above will result in damage to your board.
ID 20955, Rev. 05 Page A - 9
CP-RIO6-90 CP690HS
Table A-4: CompactPCI Rear I/O Connector J5 Pinout
PIN
8
7
10
9
14
13
12
11
18
17
16
15
22
21
20
19
4
3
6
5
2
1
Z
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
NC
NC
NC
NC
NC
NC
NC
NC
NC
PMC2_IO[05]
PMC2_IO[10]
PMC2_IO[15]
PMC2_IO[20]
PMC2_IO[25]
PMC2_IO[30]
PMC2_IO[35]
PMC2_IO[40]
PMC2_IO[45]
PMC2_IO[50]
PMC2_IO[55]
PMC2_IO[60]
NC
B
NC
NC
NC
NC
NC
NC
NC
NC
NC
PMC2_IO[04]
PMC2_IO[09]
PMC2_IO[14]
PMC2_IO[19]
PMC2_IO[24]
PMC2_IO[29]
PMC2_IO[34]
PMC2_IO[39]
PMC2_IO[44]
PMC2_IO[49]
PMC2_IO[54]
PMC2_IO[59]
PMC2_IO[64]
C D E F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
PMC2_IO[03] PMC2_IO[02] PMC2_IO[01] GND
NC
GND
NC
GND
PMC2_IO[08] PMC2_IO[07] PMC2_IO[06] NC
PMC2_IO[13] PMC2_IO[12] PMC2_IO[11] GND
PMC2_IO[18] PMC2_IO[17] PMC2_IO[16]
PMC2_IO[23] PMC2_IO[22] PMC2_IO[21]
NC
GND
PMC2_IO[28] PMC2_IO[27] PMC2_IO[26]
PMC2_IO[33] PMC2_IO[32] PMC2_IO[31]
NC
GND
PMC2_IO[38] PMC2_IO[37] PMC2_IO[36] NC
PMC2_IO[43] PMC2_IO[42] PMC2_IO[41] GND
PMC2_IO[48] PMC2_IO[47] PMC2_IO[46] NC
PMC2_IO[53] PMC2_IO[52] PMC2_IO[51] GND
PMC2_IO[58] PMC2_IO[57] PMC2_IO[56] NC
PMC2_IO[63] PMC2_IO[62] PMC2_IO[61] GND
Page A - 10 ID 20955, Rev. 05
CP690HS CP-RIO6-90
A.6
Technical Specifications
Table A-5: CP-RIO6-90 Main Specifications
CP-RIO6-90
ce CompactPCI Rear I/O
Interfaces
SPECIFICATIONS
Two CompactPCI rear I/O connectors, J3 and J5
PIM Interface
Power Consumption
Temperature Range
Climatic Humidity
Dimensions
Module Weight
Four onboard, 64-pin, female PIM connectors:
•
PIM1: J10 and J14
•
PIM2: J20 and J24
3.3 V and 5.0 V: ≤ 100 mW (without PIM module)
Operating temp.: 0°C to +75°C
93% RH at 40°C, non-condensing (acc. to IEC 60068-2-78)
233.35 mm x 80 mm (6U rear I/O card size)
200 grams (without PIM module)
ID 20955, Rev. 05 Page A - 11
CP-RIO6-90 CP690HS
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Page A - 12 ID 20955, Rev. 05
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