INTEGRATED CIRCUITS

DATA SHEET

UDA1334BT

Low power audio DAC

Product specification 2002 May 22

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

CONTENTS

9

10

11

12

6

7

8

8.1

8.2

8.3

8.4

8.5

8.6

8.6.1

8.6.2

8.6.3

8.6.4

4

5

2

3

1

1.1

1.2

1.3

1.4

FEATURES

General

Multiple format data interface

DAC digital sound processing

Advanced audio configuration

APPLICATIONS

GENERAL DESCRIPTION

ORDERING INFORMATION

QUICK REFERENCE DATA

BLOCK DIAGRAM

PINNING

FUNCTIONAL DESCRIPTION

System clock

Interpolation filter

Noise shaper

Filter stream DAC

Power-on reset

Feature settings

Digital interface format select

Mute control

De-emphasis control

Power control and sampling frequency select

LIMITING VALUES

HANDLING

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

18

19

20

13

14

14.1

14.2

14.3

15

16

17

17.1

17.2

17.3

17.4

17.5

DC CHARACTERISTICS

AC CHARACTERISTICS

2.0 V supply voltage

3.0 V supply voltage

Timing

APPLICATION INFORMATION

PACKAGE OUTLINE

SOLDERING

Introduction to soldering surface mount packages

Reflow soldering

Wave soldering

Manual soldering

Suitability of surface mount IC packages for wave and reflow soldering methods

DATA SHEET STATUS

DEFINITIONS

DISCLAIMERS

2002 May 22 2

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

1 FEATURES

1.1

General

•

1.8 to 3.6 V power supply voltage

•

Integrated digital filter plus DAC

•

Supports sample frequencies from 8 to 100 kHz

•

Automatic system clock versus sample rate detection

•

Low power consumption

•

No analog post filtering required for DAC

•

Slave mode only applications

•

Easy application

•

SO16 package.

1.2

Multiple format data interface

•

I 2 S-bus and LSB-justified format compatible

•

1f s

input data rate.

1.3

DAC digital sound processing

•

Digital de-emphasis for 44.1 kHz sampling rate

•

Mute function.

1.4

Advanced audio configuration

•

High linearity, wide dynamic range and low distortion

•

Standby or Sleep mode in which the DAC is powered down.

2

This audio DAC is excellently suitable for digital audio portable application, such as portable MD, MP3 and

DVD players.

3

APPLICATIONS

GENERAL DESCRIPTION

The UDA1334BT supports the I 2 S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits.

The UDA1334BT has basic features such as de-emphasis

(at 44.1 kHz sampling rate) and mute.

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1334BT

NAME

SO16

PACKAGE

DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm

VERSION

SOT109-1

2002 May 22 3

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

Supplies

I

V

DDA

V

DDD

I

DDA

DDD

DAC analog supply voltage digital supply voltage

DAC analog supply current digital supply current normal operating mode

Sleep mode normal operating mode

Sleep mode clock running no clock running

1.8

T amb ambient temperature

Digital-to-analog converter (V

DDA

= V

DDD

= 2.0 V)

V

α o(rms) output voltage (RMS value)

(THD + N)/S total harmonic

S/N cs distortion-plus-noise to signal ratio signal-to-noise ratio channel separation f f f f f f at 0 dB (FS) digital input; note 1 s s s s

= 44.1 kHz; at 0 dB

= 44.1 kHz; at

−

60 dB; A-weighted

−

= 96 kHz; at 0 dB

−

= 96 kHz; at

−

60 dB; A-weighted

−

− s

= 44.1 kHz; code = 0; A-weighted

−

− s

= 96 kHz; code = 0; A-weighted

−

−

Digital-to-analog converter (V

DDA

= V

DDD

= 3.0 V)

V

α o(rms) output voltage (RMS value)

(THD + N)/S total harmonic

S/N cs distortion-plus-noise to signal ratio signal-to-noise ratio channel separation f f f f f f at 0 dB (FS) digital input; note 1 s s s s

= 44.1 kHz; at 0 dB

= 44.1 kHz; at

−

60 dB; A-weighted

−

= 96 kHz; at 0 dB

−

= 96 kHz; at

−

60 dB; A-weighted

−

− s

= 44.1 kHz; code = 0; A-weighted

−

− s

= 96 kHz; code = 0; A-weighted

−

−

−

−

1.8

−

2.0

2.0

2.3

125

1.4

600

−

−

−

−

80

37

75

35

97

95

100

−

900

−

−

90

−

−

40

−

−

85

−

−

37

−

100

−

98

3.6

3.6

−

−

−

−

−

−

40

−

250

−

20

−

+85

µ

µ

°

A

A

C

−

−

−

−

−

−

−

−

100

− dB dB dB mV dB dB dB dB dB dB dB mV dB dB dB dB

V

V mA

µ

A mA

Power dissipation (at f s

= 44.1 kHz)

P power dissipation playback mode at 2.0 V supply voltage at 3.0 V supply voltage

Sleep mode; at 2.0 V supply voltage clock running no clock running

−

−

−

−

7.4

17

0.75

0.3

−

−

−

− mW mW mW mW

Note

1. The DAC output voltage scales proportionally to the power supply voltage.

2002 May 22 4

Philips Semiconductors

Low power audio DAC

6 BLOCK DIAGRAM handbook, full pagewidth

VDDD

4

BCK

WS

DATAI

1

2

3

SYSCLK

MUTE

DEEM

PCS

6

8

9

10

UDA1334BT

DIGITAL INTERFACE

DE-EMPHASIS

INTERPOLATION FILTER

VSSD

5

NOISE SHAPER

VOUTL

14

13

VDDA

DAC

15

VSSA

DAC

7

11

SFOR1

SFOR0

16

VOUTR

12

Vref(DAC)

MGU676

Fig.1 Block diagram.

Product specification

UDA1334BT

2002 May 22 5

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

7 PINNING

SYMBOL

BCK

WS

DATAI

V

DDD

V

SSD

SYSCLK

SFOR1

MUTE

DEEM

PCS

SFOR0

V ref(DAC)

V

DDA

VOUTL

V

SSA

VOUTR

PIN

1

8

9

6

7

10

4

5

2

3

11

12

13

14

15

16

PAD TYPE

5 V tolerant digital input pad; note 1

5 V tolerant digital input pad; note 1

5 V tolerant digital input pad; note 1 digital supply pad digital ground pad

5 V tolerant digital input pad; note 1

5 V tolerant digital input pad; note 1

5 V tolerant digital input pad; note 1

5 V tolerant digital input pad; note 1

3-level input pad; note 2 digital input pad; note 2 analog pad analog supply pad analog output pad analog ground pad analog output pad

DESCRIPTION bit clock input word select input serial data input digital supply voltage digital ground system clock input serial format select 1 mute control de-emphasis control power control and sampling frequency select serial format select 0

DAC reference voltage

DAC analog supply voltage

DAC output left

DAC analog ground

DAC output right

Notes

1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages this is maximum 3.3 V tolerant.

2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a maximum of 0.5 V above that level.

2002 May 22 handbook, halfpage

BCK 1

WS 2

DATAI 3

16 VOUTR

15 VSSA

14 VOUTL

VDDD 4

VSSD 5

SYSCLK 6

UDA1334BT

13 VDDA

12 Vref(DAC)

11 SFOR0

SFOR1 7

MUTE 8

10 PCS

9 DEEM

MGU675

Fig.2 Pin configuration.

6

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

8 FUNCTIONAL DESCRIPTION

8.1

System clock

The UDA1334BT operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals

(BCK and WS).

The system clock must be locked in frequency to the digital interface signals.

The UDA1334BT automatically detects the ratio between the SYSCLK and WS frequencies.

The BCK clock can be up to 64f s

, or in other words the

BCK frequency is 64 times the Word Select (WS) frequency or less: f

BCK

≤

64

× f

WS

.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O data interface

2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%.

The modes which are supported are given in Table 1.

Table 1 Supported sampling ranges

CLOCK MODE

768f s

512f s

384f s

256f s

192f s

128f s

SAMPLING RANGE

8 to 55 kHz

8 to 100 kHz

8 to 100 kHz

8 to 100 kHz

8 to 100 kHz (1)(2)

8 to 100 kHz (2)

Notes

1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in

192f s mode the sampling frequency should be limited to 55 kHz.

2. Not supported in the low sampling frequency mode.

Table 2 Example using a 12.228 MHz system clock

CLOCK MODE

128f s

192f s

256f s

384f s

512f s

768f s

SAMPLING FREQUENCY

96 kHz

64 kHz (1)

48 kHz

32 kHz

24 kHz

16 kHz

Note

1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192f s mode the sampling frequency should be limited to

55 kHz.

8.2

Interpolation filter

The interpolation digital filter interpolates from 1f s by cascading FIR filters (see Table 3).

to 64f s

Table 3 Interpolation filter characteristics

ITEM

Pass-band ripple

Stop band

Dynamic range

CONDITION

0 to 0.45f

s

>0.55f

s

0 to 0.45f

s

VALUE (dB)

±

0.02

−

50

>114

8.3

Noise shaper

The 5th-order noise shaper operates at 64f s

. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a

Filter Stream DAC (FSDAC).

An example is given in Table 2 for a 12.228 MHz system clock input.

2002 May 22 7

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

8.4

Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally with the power supply voltage.

8.5

Power-on reset

The UDA1334BT has an internal Power-on reset circuit

(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external capacitor which is connected between pin V ref(DAC) ground. The reset time should be at least 1

µ s for

and

V ref(DAC)

< 1.25 V. When V

DDA will be reset again for V ref(DAC)

is switched off, the device

< 0.75 V.

During the reset time the system clock should be running.

handbook, halfpage

3.0 V

VDDA

13

50 k

Ω

Vref(DAC)

12

C1

>

10

µ

F

RESET

CIRCUIT

50 k

Ω

UDA1334BT

MGU678

Fig.3 Power-on reset circuit.

3.0

handbook, halfpage

VDDD

(V)

1.5

0

3.0

VDDA

(V)

1.5

t

0

3.0

Vref(DAC)

(V)

1.5

1.25

0.75

0 t

>

1

µ s

Fig.4 Power-on reset timing.

t

MGL984

2002 May 22 8

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

8.6

Feature settings

The features of the UDA1334BT can be set by control pins SFOR1, SFOR0, MUTE, DEEM and PCS.

8.6.1

D IGITAL INTERFACE FORMAT SELECT

The digital audio interface formats (see Fig.5) can be selected via the pins SFOR1 and SFOR0 as shown in

Table 4.

Table 4 Data format selection

SFOR1

LOW

LOW

HIGH

HIGH

SFOR0

LOW

HIGH

LOW

HIGH

INPUT FORMAT

I 2 S-bus input

LSB-justified 16 bits input

LSB-justified 20 bits input

LSB-justified 24 bits input

8.6.2

M UTE CONTROL

The output signal can be soft muted by setting pin MUTE to HIGH level as shown in Table 5.

Table 5 Mute control

MUTE

LOW

HIGH mute off mute on

FUNCTION

8.6.3

D E EMPHASIS CONTROL

De-emphasis can be switched on for f s

= 44.1 kHz by setting pin DEEM at HIGH level. The function description of pin DEEM is given in Table 6.

Table 6 De-emphasis control

DEEM

LOW

HIGH

FUNCTION de-emphasis off de-emphasis on

8.6.4

P OWER CONTROL AND SAMPLING FREQUENCY

SELECT

Pin PCS is a 3-level pin and is used to set the mode of the

UDA1334BT. The definition is given in Table 7.

Table 7 PCS function definition

PCS

LOW

MID

HIGH

FUNCTION normal operating mode low sampling frequency mode

Power-down or Sleep mode

The low sampling frequency mode is required to have a higher oversampling rate in the noise shaper in order to improve the signal-to-noise ratio. In this mode the oversampling ratio of the noise shaper will be 128f s of 64f s

.

instead

Remark: the de-emphasis function in only supported in the normal operating mode, not in the low sampling frequency mode.

2002 May 22 9

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WS

BCK

DATA

1 2 3

MSB B2

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

LEFT

>

= 8 1 2 3

RIGHT

MSB B2

I

2

S-BUS FORMAT

LEFT

16 15

>

= 8

2 1

MSB

RIGHT

16 15

MSB B2 B15 LSB

LSB-JUSTIFIED FORMAT 16 BITS

LEFT

20 19 18 17 16 15 2 1

MSB B2

RIGHT

20 19 18 17 16 15

MSB B2 B3 B4 B5 B6 B19 LSB

LSB-JUSTIFIED FORMAT 20 BITS

24 23 22 21

LEFT

20 19 18 17 16 15 2 1

MSB B2 B3 B4 B5 B6

24 23 22 21

RIGHT

20 19 18 17 16 15

MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB

LSB-JUSTIFIED FORMAT 24 BITS

MSB B2 B3 B4 B5 B6 B7 B8 B9 B10

2 1

B15 LSB

2 1

B19 LSB

2 1

B23 LSB

MGS752

Fig.5 Digital audio formats

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

CONDITIONS SYMBOL

V

DD

T xtal(max)

T stg

T amb

V es

PARAMETER supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage note 1

I sc(DAC) short-circuit current of DAC human body model machine model note 2 output short-circuited to V

SSA output short-circuited to V

DDA

−

−

−

65

−

40

−

2000

−

200

−

−

MIN.

MAX.

4.0

150

+125

+85

+2000 V

V

°

C

°

C

°

C

+200

450

300

V

Note

1. All supply connections must be made to the same power supply.

2. Short-circuit test at T amb

= 0

°

C and V

DDA

= 3 V. DAC operation after short-circuiting cannot be warranted.

UNIT mA mA

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices.

11 THERMAL CHARACTERISTICS

SYMBOL

R th(j-a)

PARAMETER CONDITIONS thermal resistance from junction to ambient in free air

12 QUALITY SPECIFICATION

In accordance with “SNW-FQ-611-D”.

VALUE

145

UNIT

K/W

13 DC CHARACTERISTICS

V

DDD

= V

DDA

= 2.0 V; T amb

= 25

°

C; R

L otherwise specified.

= 5 k

Ω

; all voltages with respect to ground (pins V

SSA

and V

SSD

); unless

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

Supplies

V

DDA

V

DDD

I

DDA

DAC analog supply voltage note 1 digital supply voltage note 1

1.8

1.8

DAC analog supply current normal operating mode at 2.0 V supply voltage

− at 3.0 V supply voltage

−

Sleep mode at 2.0 V supply voltage

− at 3.0 V supply voltage

−

2.0

2.0

2.3

3.5

125

175

3.6

3.6

−

−

−

−

V

V mA mA

µ

µ

A

A

2002 May 22 11

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

I

SYMBOL

DDD

PARAMETER digital supply current

CONDITIONS normal operating mode at 2.0 V supply voltage

− at 3.0 V supply voltage

−

Sleep mode; at 2.0 V supply voltage clock running no clock running

−

−

Sleep mode; at 3.0 V supply voltage clock running no clock running

−

−

MIN.

1.4

2.1

250

20

375

30

TYP.

−

−

−

−

−

−

MAX.

mA mA

µ

µ

UNIT

A

A

µ

A

µ

A

Digital input pins; note 2

V

V

IH

IL

HIGH-level input voltage

LOW-level input voltage



I

LI



C i input leakage current input capacitance

3-level input: pin PCS

V

IH

V

IM

V

IL

DAC

HIGH-level input voltage

MID-level input voltage

LOW-level input voltage at 2.0 V supply voltage at 3.0 V supply voltage at 2.0 V supply voltage at 3.0 V supply voltage

1.3

2.0

−

−

−

0.5

−

0.5

0.9V

0.4V

DDD

−

0.5

DDD

−

−

−

−

−

−

−

−

−

3.3

5.0

+0.5

+0.8

1

10

V

DDD

0.6V

+0.5

V

V

V

V

µ

A pF

+ 0.5

V

DDD

V

V

V

R ref(DAC) o(ref) reference voltage output resistance on pin V ref(DAC) maximum output current with respect to V

SSA

0.45V

−

DDA

0.5V

25

DDA

0.55V

−

DDA

V k

Ω

I o(max)

(THD + N)/S < 0.1%;

R

L

= 800

Ω

−

1.6

− mA

R

L

C

L load resistance load capacitance note 3

3

−

−

−

−

50 k

Ω pF

Notes

1. All supply connections must be made to the same external power supply unit.

2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be accepted, but levels from 3.3 V domain can be applied to the pins.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100

Ω

must be used to prevent oscillations in the output operational amplifier.

2002 May 22 12

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

14 AC CHARACTERISTICS

14.1

2.0 V supply voltage

V

DDD

= V

DDA

= 2.0 V; f i

= 1 kHz; T unless otherwise specified.

amb

= 25

°

C; R

L

= 5 k

Ω

.; all voltages with respect to ground (pins V

SSA

and V

SSD

);

SYMBOL PARAMETER CONDITIONS

DAC

V o(rms)

∆

V o

S/N

α cs

PSRR output voltage (RMS value) unbalance between channels

(THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB (FS) digital input f s

= 44.1 kHz; at 0 dB f s

= 44.1 kHz; at

A-weighted

−

60 dB; signal-to-noise ratio channel separation power supply rejection ratio f f f f s f s

= 96 kHz; at 0 dB

−

= 96 kHz; at

−

60 dB; A-weighted

− s s

= 44.1 kHz; code = 0; A-weighted

−

= 96 kHz; code = 0; A-weighted

− ripple

= 1 kHz; V ripple

−

= 30 mV (p-p)

−

−

−

−

−

MIN.

TYP.

MAX.

UNIT

600

0.1

−

80

−

37

−

75

−

35

97

95

100

60

−

−

−

−

−

−

−

−

−

− mV dB dB dB dB dB dB dB dB dB

14.2

3.0 V supply voltage

V

DDD

= V

DDA

= 3.0 V; f i

= 1 kHz; T unless otherwise specified.

amb

= 25

°

C; R

L

= 5 k

Ω

; all voltages with respect to ground (pins V

SSA

and V

SSD

);

SYMBOL PARAMETER CONDITIONS

DAC

V o(rms)

∆

V o

S/N

α cs

PSRR output voltage (RMS value) unbalance between channels

(THD + N)/S total harmonic distortion-plus-noise to signal ratio at 0 dB (FS) digital input f s

= 44.1 kHz; at 0 dB f s

= 44.1 kHz; at

A-weighted

−

60 dB; signal-to-noise ratio channel separation f f f s f s

= 96 kHz; at 0 dB

−

= 96 kHz; at

−

60 dB; A-weighted

− s s

= 44.1 kHz; code = 0; A-weighted

−

= 96 kHz; code = 0; A-weighted

−

− power supply rejection ratio f ripple

= 1 kHz; V ripple

= 30 mV (p-p)

−

−

−

−

−

MIN.

TYP.

MAX.

UNIT

900

0.1

−

90

−

40

−

85

−

37

100

98

100

60

−

−

−

−

−

−

−

−

−

− mV dB dB dB dB dB dB dB dB dB

2002 May 22 13

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

14.3

Timing

V

DDD

= V

DDA

= 1.8 to 3.6 V; T amb

= unless otherwise specified; note 1.

−

20 to +85

°

C; R

L

= 5 k

Ω

; all voltages with respect to ground (pins V

SSA and V

SSD

);

SYMBOL PARAMETER CONDITIONS MIN.

TYP.

MAX.

UNIT

System clock timing (see Fig.6)

T sys system clock cycle time t t

CWH

CWL system clock HIGH time system clock LOW time f sys

= 256f s f sys

= 384f s f sys

= 512f s f f sys

< 19.2 MHz sys

≥

19.2 MHz f f sys

< 19.2 MHz sys

≥

19.2 MHz

35

23

17

0.3T

sys

0.4T

sys

0.3T

sys

0.4T

sys

88

59

−

−

−

44

−

780

520

390

0.7T

sys

0.6T

sys

0.7T

sys

0.6T

sys ns ns ns ns ns ns ns

Reset timing t reset reset time

Serial interface timing (see Fig.7) f

BCK t

BCKH t

BCKL t r t f t su(DATAI) t h(DATAI) t su(WS) t h(WS) bit clock frequency bit clock HIGH time bit clock LOW time rise time fall time set-up time data input hold time data input set-up time word select hold time word select

1

−

50

50

−

−

20

0

20

10

−

−

−

−

−

−

−

−

−

−

−

64f s

−

−

20

20

−

−

−

−

µ s ns ns ns ns

Hz ns ns ns ns

Note

1. The typical value of the timing is specified at f s

= 44.1 kHz (sampling frequency).

2002 May 22 14

Philips Semiconductors

Low power audio DAC handbook, full pagewidth tCWH

Tsys tCWL

Fig.6 System clock timing.

MGR984

Product specification

UDA1334BT handbook, full pagewidth

WS

BCK tr tBCKH tf

Tcy(BCK) tBCKL th(WS) tsu(WS)

DATAI tsu(DATAI) th(DATAI)

MGL880

Fig.7 Serial interface timing.

2002 May 22 15

Philips Semiconductors

Low power audio DAC

15 APPLICATION INFORMATION

Product specification

UDA1334BT handbook, full pagewidth system clock analog supply voltage digital supply voltage

R7

1

Ω

C5

47

µ

F

(16 V)

C6

R6

1

Ω

C9

47

µ

F

(16 V)

C10

R5

47

Ω

SYSCLK

6

BCK

1

WS

2

DATAI

SFOR1

SFOR0

3

7

11

100 nF

(63 V)

15

VSSA

13

VDDA

UDA1334BT

5

100 nF

(63 V)

VSSD

4

VDDD

14

VOUTL

C3

47

µ

F

(16 V)

16

VOUTR

C4

47

µ

F

(16 V)

R3

100

Ω

R1

220 k

Ω C1

R4

100

Ω

R2

220 k

Ω C2

MUTE

8

DEEM

9

PCS

10

12

Vref(DAC)

C8

100 nF

(63 V)

C7

47

µ

F

(16 V)

10 nF

(63 V)

10 nF

(63 V)

MGU677 left output right output

Fig.8 Typical application diagram.

2002 May 22 16

Philips Semiconductors

Low power audio DAC

16 PACKAGE OUTLINE

SO16: plastic small outline package; 16 leads; body width 3.9 mm

Product specification

UDA1334BT

SOT109-1

16

Z y

1 pin 1 index e

D E A

X c

H

E

9 b p

8 w M

A

2

A

1

L

L p detail X

Q

θ

A v M A

0 2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT

A max.

A

1

A

2

A

3 b p c D

(1)

E

(1) e H

E mm inches

1.75

0.069

0.25

0.10

0.010

0.004

1.45

1.25

0.057

0.049

0.25

0.01

0.49

0.36

0.25

0.19

0.019

0.014

0.0100

0.0075

10.0

9.8

0.39

0.38

4.0

3.8

0.16

0.15

1.27

0.050

6.2

5.8

L

1.05

0.244

0.228

0.041

L p

Q

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.020

v

0.25

0.01

w y Z

(1)

0.25

0.01

0.1

0.004

0.7

0.3

0.028

0.012

θ

8 o

0 o

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE

VERSION

SOT109-1

IEC

076E07

REFERENCES

JEDEC EIAJ

MS-012

EUROPEAN

PROJECTION

ISSUE DATE

97-05-22

99-12-27

2002 May 22 17

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

17 SOLDERING

17.1

Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch

SMDs. In these situations reflow soldering is recommended.

17.2

Reflow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from

215 to 250

°

C. The top-surface temperature of the packages should preferable be kept below 220

°

C for thick/large packages, and below 235

°

C for small/thin packages.

17.3

Wave soldering

Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

•

Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

•

For packages with leads on four sides, the footprint must be placed at a 45

° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250

°

C.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

17.4

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300

°

C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between

270 and 320

°

C.

2002 May 22 18

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

17.5

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE (1)

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA

HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

PLCC (4) , SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO not suitable not suitable

SOLDERING METHOD

WAVE

(3)

REFLOW (2) suitable suitable suitable suitable not recommended (4)(5) suitable not recommended (6) suitable

Notes

1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

4. If wave soldering is considered, then the package must be placed at a 45

°

angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2002 May 22 19

Philips Semiconductors

Low power audio DAC

Product specification

UDA1334BT

18 DATA SHEET STATUS

DATA SHEET STATUS (1)

Objective data

Preliminary data

Product data

PRODUCT

STATUS (2)

DEFINITIONS

Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice.

Qualification This data sheet contains data from the preliminary specification.

Supplementary data will be published at a later date. Philips

Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product.

Production This data sheet contains data from the product specification. Philips

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change

Notification (CPCN) procedure SNW-SQ-650A.

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

19 DEFINITIONS

Short-form specification



The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition



Limiting values given are in accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any other conditions above those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may affect device reliability.

Application information



Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

20 DISCLAIMERS

Life support applications



These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips

Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes



Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2002 May 22 20

Philips Semiconductors

Low power audio DAC

NOTES

Product specification

UDA1334BT

2002 May 22 21

Philips Semiconductors

Low power audio DAC

NOTES

Product specification

UDA1334BT

2002 May 22 22

Philips Semiconductors

Low power audio DAC

NOTES

Product specification

UDA1334BT

2002 May 22 23