STMicroelectronics VS6663CD Datasheet
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VS6663CD
Features
• 1280 x 960 1.3 Mpixel resolution sensor
• Compact size:
6.5 mm x 6.5 mm x 4.1 mm
• Short focus distance: 15 cm
• MIPI CSI-2 (a)
(D-PHY v1.0) and CCP2 Video data interface
• Ultra low power standby mode (<15uW)
• Binning 2x2 mode
• Defect correction
• 4-channel lens shading correction
1.3 megapixel camera module
Datasheet
-
production data
Description
The VS6663CD is a compact camera module designed for imaging and machine vision applications which require a short focus distance.
It is designed to be used for high quality still camera function and also supports video modes.
The camera silicon device is capable of generating raw Bayer 1.3 Mpixel images up to
30 fps. The VS6663CD supports the CCI control and CCP2 and CSI-2 data interfaces.
The module design is optimized for both footprint and height.
A separate hardware accelerator can be incorporated in the phone system to run the algorithms in hardware. The specification of these devices are contained in a separate document.
Table 1. Device summary
Order code Package Packing
VS6663CDQ05I/1 SMIA65 Tape and reel a.
Copyright
2005 MIPI Alliance, Inc. Standard for
Camera Serial Interface 2 (CSI-2) version 1.01, limited to 1 Gbps per lane
September 2015
This is information on a product in full production.
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Contents
Contents
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VS6663CD
VS6663CD use in system with hardware coprocessor . . . . . . . . . . . . . . . 8
VS6663CD use in a system with software image processing . . . . . . . . . . 9
Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Power-up procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-down procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Dark calibration algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Camera control interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
General status registers [0x0000 to 0x001F] . . . . . . . . . . . . . . . . . . . . . 23
Frame format description registers [0x0040 to 0x007F] . . . . . . . . . . . . 24
Analog gain description registers [0x0080 to 0x0093] . . . . . . . . . . . . . . 24
Data format description registers [0x00C0 to 0x00C7] . . . . . . . . . . . . . 25
Setup registers [0x0100 to 0x01FF] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Integration time and gain registers [0x0200 to 0x02FF] . . . . . . . . . . . . 27
Video timing registers [0x0300 to 0x03FF] . . . . . . . . . . . . . . . . . . . . . . 28
Image compression registers [0x0500 to 0x0501] . . . . . . . . . . . . . . . . . 29
Test pattern registers [0x0600 to 0x0611] . . . . . . . . . . . . . . . . . . . . . . . 29
Binning registers [0x0900 to 0x0902] . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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VS6663CD
Contents
Integration time and gain parameter limit registers [0x1000 to 0x10FF] 31
Video timing parameter limit registers [0x1100 to 0x11FF] . . . . . . . . . . 32
Binning capability registers [0x1700 to 0x1713] . . . . . . . . . . . . . . . . . . 35
Exposure and gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Integration and gain parameter retiming . . . . . . . . . . . . . . . . . . . . . . . . 46
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power supply - VDIG, VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
System clock - EXTCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power down control - XSHUTDOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCI interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
CCI interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
CCP2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CCP2 interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 52
CSI-2 interface - DC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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Contents
VS6663CD
CSI-2 interface - AC specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
On-chip image optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Mapped couplet correction (Bruce filter) . . . . . . . . . . . . . . . . . . . . . . . . . 56
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List of tables
List of tables
Power-down sequence timing constraints for CSI2 communications . . . . . . . . . . . . . . . . . 18
External clock frequency examples - 1.3 Mpixel resolution Raw10 30 fps . . . . . . . . . . . . . 43
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List of figures
List of figures
VS6663CD
VS6663CD module pinout (viewed from bottom of camera module) . . . . . . . . . . . . . . . . . 11
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VS6663CD
1 Overview
Overview
The VS6663CD 1.3 Mpixel image sensor produces raw digital video data at up to 30 fps. It has both CCP2 and MIPI CSI-2 video data interfaces selectable over the camera control interface (CCI).
The image data is digitized using an internal 10-bit column ADC. The resulting 10-bit pixel data is output as 8-bit, 10-bit or 10-8 bit compressed data and includes checksums and embedded codes for synchronization. The interface conforms to both the CCP2 and MIPI
CSI-2 interface standards. The sensor is fully configurable through a CCI serial interface.
The module is available in a SMOP type package measuring 6.5 mm x 6.5 mm x 4.1 mm. It is designed to be used with a board mounted socket or flex.
Feature
Sensor technology
Pixel size
Analogue gain
Dynamic range
Signal to noise
SNR10 value
Supply voltage
Table 2. Technical specification
Detail
IMG140 ST’s 65 nm based
CMOS imaging process
1.75 µm x 1.75 µm
24 dB (max)
60 dB (typical)
38 dB (typical)
50 lux
Analogue: 2.6 V to 2.9 V
Digital: 1.68 V to 1.92 V
Average power consumption
30 fps
Lens
TV distortion
System attach
150 mW (typical)
51° HFOV F/2.8
<1%
Socket or flex
Figure 1. VS6663CD camera module
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Overview
1.1
VS6663CD
VS6663CD use in system with hardware coprocessor
The VS6663CD as an image sensor can be paired with an STMicroelectronics hardware accelerator. The coprocessor and the sensor together form a complete imaging system.
Figure 2 illustrates a typical system using VS6663CD.
Figure 2. VS6663CD in system with processor
Video Engine
4 Ch AV
Dig Filters
Dark Cal
Output Data I/F
CCP2 / CSI-2
CCP2 / CSI-2
Input Data I/F
CCP2 / CSI-2 Rx
CCP2 / CSI-2 Rx
MUX
Bayer
Reconstruction
CCI CCI
Master
Scaler
Video Timing
Col ADC
Power
Pixel
Array
CCI
Test Ctrl
Sys Ctrl
Clk Mngt
VS6663CD
PLL
XSHUT
DOWN
House
Keeper
Color
Engine
Color
Engine
CCI
Slave Output coder
EXTCLK CCI
XSHUT
DOWN
Mobile Base Band
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VS6663CD Overview
The module's main function is to convert the viewed scene into a data stream. The companion processor’s function is to manage the sensor included in the module in order to produce the best possible pictures given the module's optics and the scene itself. The companion processor processes the data stream into a form which is easily handled by up stream mobile baseband or multimedia processor (MMP) chipsets.
The sensor supplies high-speed clock signal to the coprocessor and provides the embedded control sequences which allow the coprocessor to synchronize with the frame and line level timings. The coprocessor then performs the color processing on the raw image data from the sensor before supplying the final image data to the host.
In a coprocessor architecture, a low speed clock (external clock) is sent by the host to both the VS6663CD and the coprocessor. This is used by the sensor in all phases of operation and by the coprocessor during the initial stages of system boot up.
During streaming phase, the VS6663CD supplies the high-speed data qualification clock for the coprocessor. The high-speed clock is generated using the VS6663CD embedded PLL and is provided as the continuous data qualification clock.
1.2 VS6663CD use in a system with software image processing
The VS6663CD image sensor can also be directly connected to a baseband or multimedia processor. No dedicated coprocessor is used in this configuration. The image processing is done in software within the baseband processor.
Figure 3. VS6663CD in a system with software image processing
4 Ch AV
Dig filters
Dark cal
Output data I/F
CCP2 / CSI-2
Mobile baseband processor
Video timing
CCI
Test ctrl
Sys ctrl
Clk mngt
Col ADC
Power
Pixel array
VS6663CD
PLL
XSHUTDOWN
EXTCLK
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Overview VS6663CD
Table 3. Reference documents
Title
MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2) v1.0
MIPI Alliance D-PHY Specification (v1.00.00)
Date
29-Nov-2005
14-May-2009
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VS6663CD Device pinout
Figure 4 shows the position of the pins on the module and Table 4 provides the signal
descriptions.
Figure 4. VS6663CD module pinout (viewed from bottom of camera module)
12 11 10 9 8 7
TP TP
TP TP
TP TP
TP TP
1 2 3 4 5 6
Pad number Pad name
3
4
Power supplies
1
7
2
10
System
VCAP
GND
VANA
VDIG
XSHUTDOWN
EXTCLK
Control
5 SCL
Table 4. Pin description
I/O type
I
I
I
PWR
PWR
PWR
PWR
Description
Do not connect
(1)
Ground (combined)
Analog power
Digital power
Power down control
(2)
System clock input
Serial communication clock
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Device pinout
6
Pad number
Data
8
9
11
12
ST test
SDA
Table 4. Pin description (continued)
Pad name I/O type Description
CLK-
CLK+
DATA-
DATA+
I/O
SubLVDS output
Serial communication data
SubLVDS output Output qualifying clock
SubLVDS output Serial output data
SubLVDS output
TP ST test pins
1.
No connection should be made to VCAP.
2.
Signal is active low.
3.
Test pins are not floating.
Output qualifying clock
Serial output data
Do not connect
(3)
VS6663CD
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VS6663CD Functional description
3.1.1 Clock input type
The external clock provided by the host to the VS6663CD must be a DC coupled square wave and may also be RC-filtered.
Figure 5. Clock input types
Host processor
Host processor pwrdn pwrdn
Pad
Pad
Pad extclk
Pad extclk
Camera module
Extclk pwrdn
1st option
DC-coupled
Camera module
Extclk pwrdn
2nd option
DC-coupled and filtered
3.1.2 PLL and clock input
The VS6663CD has an embedded PLL block. This block generates all necessary internal
clocks from an input range defined in Table 5 .
Table 5. System input clock frequency range
Minimum (MHz) Maximum (MHz)
6 27
The value of the external clock frequency must be written to register 0x0136
(extclk_frequency_mhz).
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Functional description VS6663CD
The mode changes in VS6663CD are shown in Figure 6
. Further details are provided in the following sections.
Figure 6. System state diagram
POWER-OFF
CSI-2
Power supplies OFF Power supplies ON Power supplies OFF
HW-STANDBY
CSI-2
XSHUTDOWN is low XSHUTDOWN is high XSHUTDOWN is low
SW-STANDBY
CSI-2
CCI
CCI
STREAMING
CSI-2
CCI
CCI
SW-STANDBY
CCP2
CCI
CCI
STREAMING
CCP2
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VS6663CD Functional description
The digital and analog supply voltages can be powered up in any order, for example, VDIG then VANA or VANA then VDIG.
On power-up the on-chip power-on reset cell ensures that the CCI register values are initialized correctly to their default values.
The EXTCLK clock can either be initially low and then enabled during software standby mode or EXTCLK can be a free running clock.
The power-up sequence timing constraints are shown in
.
Symbol t0
Table 6. Power-up sequence timing constraints
Parameter
VANA rising – VDIG rising
Min.
Max.
t1 t2
VDIG rising – VANA rising
VDIG / VANA rising –
XSHUTDOWN rising
VANA and VDIG may rise in any order. The rising separation can vary from 0 ns to indefinite.
XSHUTDOWN must rise later than or coincident with the later rising supply (VDIG or VANA) t3 t4 t5 t6 t7
XSHUTDOWN – First I
2
C transaction
Minimum number of EXTCLK cycles prior to the first I
2
C transaction
PLL start up/lock time
Entering streaming mode – First frame start sequence (fixed part)
Entering streaming mode – First frame start sequence (variable part)
= Integration time
2400
2400
-
-
-
-
1
The delay is the coarse integration time value.
Units ns ns
µs
EXTCLK cycles
EXTCLK cycles ms ms
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Functional description
Figure 7. VS6663CD power-up sequence for CCP2
VDIG t0 t1
This is an example of VANA rising after VDIG
VANA t2
XSHUTDOWN t3
EXTCLK (Free running)
EXTCLK (Gated)
EXTCLCK may be free running or gated t4
VS6663CD
CCI
CLK+/-
DATA+/-
Frame count register
16/64
Read
Device
ID
Configure
Device
Enter
Streaming t5
0xFF
LP00 (CSI-2 mode)
High Z (tri-state)
Mode changed to CCP2 t6 t7
0x01
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VS6663CD Functional description
Figure 8. VS6663CD power-up sequence for CSI-2 mode
VDIG t0 t1
This is an example of
VANA rising after VDIG
VANA t2
XSHUTDOWN t3
EXTCLK (Free running)
EXTCLK may be free running or gated
EXTCLK (Gated) t4
CCI
CLK+/-
DATA+/-
Frame count register
0xFF
Read device
ID
Configure device
Enter streaming t5
LP11 LP01
High-Speed
TX t6
0x01 t7
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Functional description VS6663CD
The power-down sequence timing constraints are shown in
.
Table 7. Power-down sequence timing constraints for CSI2 communications
Symbol t8 t9
Parameter
Last I
2
C transaction to software standby
Last I
2
C transaction or MIPI frame end to XSHUTDOWN falling
Minimum
-
512
Maximum
1 frame
-
Units clock cycles t10 t11
XSHUTDOWN to VANA/VDIG falling
VANA to VDIG or VDIG to VANA falling
XSHUTDOWN must fall at the same time as, or earlier than, both power supplies (VDIG and VANA)
VANA and VDIG may fall in any order, the rising separation can vary from 0 ns to indefinite
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VS6663CD Functional description
Figure 9. VS6663CD power-down sequence for CSI-2 mode
VDIG
This is an example of
VANA falling after VDIG t11
VANA t10 t9
XSHUTDOWN
EXTCLK (Free running)
EXTCLK may be free running or gated
EXTCLK (Gated)
CCI
Configure device
Stop streaming
High-Speed
TX
High-Speed
TX t8
LP11
LP11
CLK+/-
CSI output is disabled after XSHUTDOWN=0 or clock is stopped
DATA+/-
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Functional description
3.2.3
VS6663CD
Internal power-on reset (POR)
The VS6663CD internally performs a power-on reset (POR) when the digital supply rises through the trigger level, Vtrig_rising. Similarly, if the digital power supply falls through the trigger level, Vtrig_falling, then the power-on reset will also trigger.
Figure 10. POR timing
Burst < t4 Burst > t2 Burst > t5
Digital
Power
Supply,
VDIG
V trig_rising
V trig_falling t1 t3 t1
POR Cell Output
Symbol
Table 8. POR cell characteristics
Constraint Minimum Typical Maximum Units t1 t2 t3
(1) t4 t5
Vtrig_rising
Vtrig_falling
VDIG rising crossing Vtrig_rising – Internal reset being released.
Minimum VDIG spike width below Vtrig_falling which is considered to be a reset when POR cell output high.
VDIG falling crossing Vtrig_falling - Internal reset active.
Minimum VDIG spike width below Vtrig_falling which is considered to be a reset when POR cell output low.
Minimum VDIG spike width above Vtrig_rising which is considered to be a supply is stable when
POR cell output low. While the POR cell output is low, all VDIG spikes above Vtrig_rising which are less than t5 must be ignored.
VDIG rising trigger voltage.
VDIG falling trigger voltage.
20.7
1.25
1.25
1.5
20.7
429
401
30.7
2.1
2.1
2.1
30.7
755
725
50.7
6.9
6.9
6.9
50.7
944
904
µs
µs
µs
µs ns mV mV
1.
The device could be reset by any VDIG voltage excursion falling below Vtrig_falling and will always be reset by a VDIG voltage excursion below Vtrig_falling of > 0.5 µs
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VS6663CD Functional description
3.2.4 Power-off
The power-off state is defined as either or both of the digital and analog supplies not present.
This is the lowest power consumption mode. CCI communications are not supported in this mode. The PLL and the video blocks are powered down. This state is entered by pulling the control pin XSHUTDOWN down (active low). All registers are returned to their default values
Note:
Software standby mode preserves the contents of the CCI register map. CCI communications are supported in this mode. The software standby mode is selected using a serial interface command. If this state is entered from hardware standby the data pads remain high impedance. If this state is entered from streaming then the data pads go high impedance at the end of the current frame. The internal video timing is reset to the start of a video frame in preparation for the enabling of active video. The values of the serial interface registers like exposure and gain are preserved. The system clock must remain active when communicating with the sensor.
This state is entered by releasing the device from hard reset by setting XSHUTDOWN high, writing 0x00 to the mode control register (0x0100) or commanding a soft reset by writing
0x01 to the software reset register (0x0103).
After a soft reset or the transition of XSHUTDOWN to high, all registers are returned to their default values.
3.2.7 Streaming
The VS6663CD streams live video. This mode is entered by writing 0x01 to the mode control register (0x0100).
VS6663CD runs an automatic dark calibration algorithm on the raw image data to control the video offsets caused by dark current. This ensures that a high quality image is output over a range of operating conditions. First frame dark level is correctly calibrated, for subsequent frames the adjustment of the dark level is damped by a leaky integrator function to avoid possible frame to frame flicker.
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Camera control interface (CCI)
4 Camera control interface (CCI)
VS6663CD
This chapter specifies the camera control interface (CCI). The I
2
C-type interface uses 1.8 V
I/O with two signals: serial data line (SDA) and serial clock line (SCL). CCI is used for control data transfer. Clock signal (SCL) generation is performed by the master device (the camera module is a slave device). The master device initiates data transfer. The CCI bus on the camera module has a maximum speed of 400 Kbits/s and has a software switchable device address.
Any internal register that can be written to, can also be read from. There are also read only registers that contain device status information, (for example, design revision details). A read instruction from an un-used register location will return the value 0x00. A read instruction from the manufacturers specific registers may return any value. A write instruction to a reserved or unused register location is illegal and the effect of such a write is undefined. It is the responsibility of the host system to only write to register locations which have been defined.
4.1 Valid register data types
The contents of the registers can represent a number of different data types (see Table 9
).
The register map uses this coding to help with the interpretation of the contents of each register.
Data type
8UI
8SI
16UI
16SI
Name
Table 9. Valid register data types
8-bit unsigned integer
8-bit signed integer
16-bit unsigned integer
16-bit signed integer
Range
0 to 255
-128 to 127
0 to 65535
-32768 to 32767
16UR
16SR
32SF
16-bit unsigned iReal
16-bit signed iReal
32-bit IEEE floating-point number
8C or 16C 8-bit or 16-bit Coded
8B or 16B 8 or 16 Bits -
-
0 to 255.99609375
-128 to 127.9960375
As per IEEE 754
Description
-
-
Two’s complement notation
Two’s complement notation
08.08 fixed point number. 8 integer bits (MS Byte), 8 fractional bits (LS Byte)
Two’s complement notation, 8 fractional bits
As per IEEE 754. 1 sign bit,
8 exponent bits, 23 fractional bits
This indicates that the value is decoded to select one of several functions or modes.
Each bit represents a specific function or mode.
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0x0005
0x0006
Index Byte
0x0000 Hi
0x0001 Lo
0x0002
0x0003
0x0004
Table 10. General status registers [0x0000 to 0x001F]
Register name model_id revision_number_major manufacturer_id smia_version frame_count pixel_order
Data type Default Type
16UI
8UI
8C
8C
8UI
8C
02.97
04
01
0A
FF
00
Comment
RO
Camera model identification
0x0297 = 663
10
RO Revision identifier of the camera
RO Manufacturer ID: ST Micro
RO 0x0A: SMIA 1.0
RO
RO
Frame count increments from 1 to
254 when streaming.
When moving from video to sleep the frame count is reset to 255.
The frame count is also reset to 255 after a soft reset (register 0x0103).
Color pixel readout order.
Defines the order of the color pixel readout. Changes with mirror and flip (register 0x0101).
0x00 - GR/BG - normal
0x01 - RG/GB - horizontal mirror
0x02 - BG/GR - vertical flip
0x03 - GB/RG - vertical flip and horizontal mirror
0x0008 Hi
0x0009 Lo data_pedestal 16UI 00.40
RO The video data is offset by 64
0x000C pixel_depth 8UI 0A RO
Pixel data resolution. For
VS6663CD the pixel depth is 10 bits.
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Camera control interface (CCI) VS6663CD
For a full description of the frame format description refer to
Chapter 5: Video data interface on page 36 .
0x0040
0x0041
0x0042 Hi
0x0043 Lo
0x0044 Hi
0x0045 Lo
0x0046 Hi
0x0047 Lo
Index Byte
Table 11. Frame format description registers [0x0040 to 0x007F]
Register name Data type Default Type Comment frame_format_model_type frame_format_model_subtype frame_format_descriptor_0 frame_format_descriptor_1 frame_format_descriptor_2
8C
8C
16C
16C
16C
01
12
RO
RO
55.10
RO
10.02
RO
53.D0
RO
Generic frame format.
0x01: 2-byte data format.
Contains the number of 2-byte data format descriptors used.
Upper nibble defines the number of column descriptors (1).
The lower nibble defines the number of row descriptors (2)
Pixel data code: 5 (Visible Columns)
Number of pixels : readout dependent
(Maximum of 1296)
Number of pixels: 1296
Pixel data code: 1 (Embedded data lines)
Number of status lines:2
Pixel data code: 5 (Visible Lines) number of pixels: readout dependent
(Maximum of 976)
Number of pixels: 976
For a full description of the analog gain description registers refer to
Chapter 6: Video timing on page 39 .
Index Byte
Table 12. Analog gain description [0x0080 to 0x0093]
Register name Data type Default Type Comment
0x0080 Hi analogue_gain_capability
0x0081 Lo
0x0084 Hi
0x0085 Lo
0x0086 Hi
0x0087 Lo
0x0088 Hi
0x0089 Lo analogue_gain_code_min analogue_gain_code_max analogue_gain_code_step
16B
16UI
16UI
16UI
00.00
RO
Analog gain capability
0 – single global analog gain only
00.00
RO
Minimum recommended analog gain code, that is, 0 (x1 gain)
00.F0
RO
Maximum recommended analog gain code, that is, 240 (x16 gain)
00.10
RO Analog gain code step size
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Index Byte
0x008A Hi
0x008B Lo
0x008C Hi
0x008D Lo
0x008E Hi
0x008F Lo
0x0090 Hi
0x0091 Lo
0x0092 Hi
0x0093 Lo
Table 12. Analog gain description [0x0080 to 0x0093] (continued)
Register name analogue_gain_type analogue_gain_m0 analogue_gain_c0 analogue_gain_m1 analogue_gain_c1
Data type Default Type
16UI
16SI
16SI
16SI
16SI
00.00
RO Analog gain type
00.00
RO
01.00
RO
FF.FF
RO
01.00
RO
Comment
Analog gain m0 constant.
m0 = 0
Analog gain c0 constant.
c0 = 256
Analog gain m1 constant.
m1 =-1
Analog gain c1 constant c1 = 256
0x00C0
Index Byte
Table 13. Data format description registers [0x00C0 to 0x00C7]
Register name Data type Default Type Comment data_format_model_type 8UI
8UI
01
03
RO
2-byte generic data format model.
Always 0x01
RO Number of descriptors, that is, 3 0x00C1
0x00C2 Hi
0x00C3 Lo
0x00C4 Hi
0x00C5 Lo
0x00C6 Hi data_format_model_subtype data_format_descriptor_0 data_format_descriptor_1
0x00C7 Lo data_format_descriptor_2
16UI
16UI
16UI
08.08
RO
0A.0A
RO
0A.08
RO
Top 8-bits of internal pixel data transmitted as RAW8.
Top 10-bits of internal pixel data transmitted as RAW 10.
Compress top 10-bits of internal pixel data to 8. Transmitted as RAW
8 mode.
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Camera control interface (CCI) VS6663CD
4.2.5 Setup registers [0x0100 to 0x01FF]
0x0100
0x0101
0x0103
0x0104
0x0105
0x0110
0x0111
Index Byte
Table 14. Setup registers [0x0100 to 0x01FF]
Register name mode_select image_orientation software_reset grouped_parameter_hold mask_corrupted_frames csi_channel_identifier csi_signalling_mode
Data type Default Type
8UI
8B
8UI
8UI
8UI
8UI
8UI
00
00
00
00
00
00
02
RW
RW
RW
RW
RW
RW
RW
Comment
Mode select
0x00 - Software standby
0x01 - Streaming
Refer to
Section 3.2: Device operating modes on page 14
Image orientation, that is, horizontal mirror and vertical flip.
Bit 0: 0 - no mirror, 1 - horizontal mirror enable
Bit 1: 0 - no flip, 1 - vertical flip enable
Software reset. Setting this register to 1 resets the sensor to its power up defaults. The value of this bit is also reset
0x00 - normal
0x01 - soft reset
Refer to
Section 3.2: Device operating modes on page 14
The grouped parameter hold register disables the consumption of integration, gain and video timing parameters
0x00 - consume parameters as normal
0x01 - hold parameters
Refer to
Section 6.3.3: Integration and gain parameter retiming on page 46
Setting this register to 1 prevents the sensor outputing frames that have been corrupted by video timing parameter changes.
0x00 - normal
0x01 - mask corrupted frames
The DMA (CCP2) or Virtual (CSI2) channel identifier
Valid range: 0-7 for CCP2
Valid range: 0-3 for CSI-2
0x00 - CCP2 Data/clock signalling:
0x01 - CCP2 Data/strobe signalling:
0x02 - CSI-2:
This register should not be changed while the device is streaming data.
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Index Byte
0x0112 Hi
0x0113 Lo
0x0114
0x0115
0x0120
Table 14. Setup registers [0x0100 to 0x01FF] (continued)
Register name Data type Default Type Comment csi_data_format csi_lane_mode csi2_10_to_8_dt gain_mode
16UI
8UI
8UI
8UI
0A.0A
RW
00
30
00
RW
RW
RO
The MSB contains the bit width of the uncompressed pixel data.
The LSB contains the bit width of the compressed pixel data.
0A.0A - RAW10 mode
0A.08 - 10-8 compressed mode
08.08 - RAW8 mode
Number of data lanes in use
00 - 1-lane
CSI-2 data type for 10-8 compression
0x00 – Global analog gain.
VS6663CD supports only global gain modes.
0x0136 Hi
0x0137 Lo extclk_frequency_mhz 8.8UR
06.00
RW Frequency of external crystal
4.2.6 Integration time and gain registers [0x0200 to 0x02FF]
These registers are used to control the image exposure. See
Section 6.3: Exposure and gain control on page 45
for more information.
0x0200 Hi
0x0201 Lo
0x0202 Hi
0x0203 Lo
0x0204 Hi
Index Byte
Table 15. Integration time and gain registers [0x0200 to 0x02FF]
Register name fine_integration_time coarse_integration_time
Data type Default Type
16UI
16UI
Comment
01.4C
RW Fine integration time (pixels)
00.00
RW coarse integration time (lines).
0x0205 Lo analogue_gain_code_global 16UI 00.00
RW
Global analog gain parameter
(coded). See Section 6.3.1: Gain model on page 45
for details of how to use this parameter.
0x020E Hi
0x020F Lo
0x0210 Hi
0x0211 Lo
0x0212 Hi
0x0213 Lo
0x0214 Hi
0x0215 Lo digital_gain_greenr digital_gain_red digital_gain_blue digital_gain_greenb
16UR
16UR
16UR
16UR
01.00
RW Gain code for greenr channel
01.00
RW Gain code for red channel
01.00
RW Gain code for blue channel
01.00
RW Gain code for greenb channel
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Camera control interface (CCI) VS6663CD
For a full description of the video timing registers refer to Chapter 6: Video timing on page 39 .
Index Byte
0x0300 Hi
0x0301 Lo
0x0302 Hi
0x0303 Lo
0x0304 Hi
0x0305 Lo
0x0306 Hi
0x0307 Lo
0x0340 Hi
Table 16. Video timing registers [0x0300 to 0x03FF]
Register name vt_pix_clk_div vt_sys_clk_div pre_pll_clk_div pll_multiplier
Data type Default Type
16UI
16UI
16UI
16UI
Comment
00.0A
RW
Video timing clock divider
Value: 10
00.01
RW
Video timing clock divider
Value: 1
00.01
RW
Pre PLL clock divider value
Value: 1
00.85
RW
PLL multiplier value
Value: 133
0x0341 Lo
0x0342 Hi
0x0343 Lo
0x0344 Hi
0x0345 Lo
0x0346 Hi
0x0347 Lo
0x0348 Hi
0x0349 Lo
0x034A Hi
0x034B Lo
0x034C Hi
0x034D Lo frame_length_lines line_length_pck x_addr_start y_addr_start x_addr_end y_addr_end x_output_size
16UI
16UI
16UI
16UI
16UI
16UI
16UI
03.F0
RW
0A.50 RW
00.00
RW
00.00
RW
05.0F
RW
03.CF
RW
05.10
RW
Frame length
Units: Lines
Value: 1008
Line length
Units: Pixel clocks
Value: 2640
X-address of the top left corner of the visible pixel data
Units: Pixels
Value: 0
Y-address of the top left corner of the visible pixel data.
Must be modulo 4 for correct operation of device.
Units: Lines
Value: 0
X-address of the bottom right corner of the visible pixel data
Units: Pixels
Value: 1295
Y-address of the bottom right corner of the visible pixel data
Units: Lines
Value = 975
Width of image data output from the sensor module
Units: Pixels
Value: 1296
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Index Byte
0x034E Hi
0x034F Lo
Table 16. Video timing registers [0x0300 to 0x03FF] (continued)
Register name Data type Default Type Comment y_output_size 16UI 03.D0
RW
Height of image data output from the sensor module
Units: Lines
Value: 976
0x0380 Hi x_even_inc
0x0381 Lo
0x0382 Hi
0x0383 Lo x_odd_inc
0x0384 Hi y_even_inc
0x0385 Lo
0x0386 Hi y_odd_inc
0x0387 Lo
16UI
16UI
16UI
16UI
00.01
RW
Increment for even pixels
Units: Pixels
00.01
RW
Increment for odd pixels
Units: Pixels
00.01
RW
Increment for even pixels
Units: Pixels
00.01
RW
Increment for odd pixels
Units: Pixels
4.2.8 Image compression registers [0x0500 to 0x0501]
Index Byte
Table 17. Image compression registers [0x0500 to 0x0501]
Register name Data type Default Type Comment
0x0500 Hi
0x0501 Lo compression_mode 16UI 00.01
RO
1 – DPCM/PCM compression
(simple predictor)
4.2.9 Test pattern registers [0x0600 to 0x0611]
0x0601 Lo
Index Byte
0x0600 Hi
Table 18. Test pattern registers [0x0600 to 0x0611]
Register name test_pattern_mode
Data type Default Type
16C 00.00
RW
Comment
0 – normal operation (default)
1 – solid color bars
2 – 100% color bars
3 – fade to grey’ color bars
4 - PN9
5 to 255 - reserved
256 to 65535 - manufacturer specific
0x0602 Hi
0x0603 Lo
0x0604 Hi test_data_red 16UI 00.00
RW
The test data used to replace red pixel data. Range 0 to 1023.
(1)
0x0605 Lo test_data_greenR 16UI 00.00
RW
The test data used to replace green pixel data on rows that also have red pixels. Valid range 0 to 1023.
(1)
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Camera control interface (CCI) VS6663CD
Index Byte
Table 18. Test pattern registers [0x0600 to 0x0611] (continued)
Register name Data type Default Type Comment
0x0606 Hi
0x0607 Lo
0x0608 Hi test_data_blue 16UI 00.00
RW
The test data used to replace blue pixel data. Range 0 to 1023.
(1)
0x0609 Lo test_data_greenB 16UI 00.00
RW
The test data used to replace green pixel data on rows that also have blue pixels. Range 0 to 1023.
(1)
0x060A Hi
0x060B Lo
0x060C Hi
0x060D Lo
0x060E Hi
0x060F Lo
0x0610 Hi horizontal_cursor_width horizontal_cursor_position vertical_cursor_width
16UI
16UI
16UI
00.00
00.00
00.00
RW
RW
RW
Defines the width of the horizontal cursor (in pixels).
Defines the top edge of the horizontal cursor.
Defines the width of the vertical cursor (in pixels).
0x0611 Lo vertical_cursor_ position 16UI 00.00
RW
Defines the left hand edge of the vertical cursor. Maximum value =
0xFFFF
A value of 0xFFFF switches the vertical cursor into automatic mode where it automatically advances every frame.
1.
Some clipping of these values may occur to prevent false sync codes being generated
Index Byte
0x0900
Table 19. Binning registers [0x0900 to 0x0902]
Register name Data type Default Type binning_mode 8UI 00 RW
Binning mode
0 - Disable
1 - Enable
Comment
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4.2.11 Integration time and gain parameter limit registers [0x1000 to 0x10FF]
These registers are used to define exposure limits for the integration control registers
(0x200 - 0x203). See
Section 6.3: Exposure and gain control on page 45 for more
information.
Table 20. Integration time and gain parameter limit registers [0x1000 to 0x10FF]
Index Byte Register name Data type Default Type Comment
0x1000 Hi
0x1001 Lo
0x1004 Hi
0x1005 Lo
0x1006 Hi integration_time_capability coarse_integration_time_ min
0x1007 Lo coarse_integration_time_ max_margin
0x1008 Hi
0x1009 Lo
0x100A Hi fine_integration_time_min
0x100B Lo fine_integration_time_ max_margin
16UI
16UI
16UI
16UI
16UI
00.01
RO
This device supports coarse and fine integration.
00.00
RO
Minimum coarse integration time.
Line periods.
00.07
RO
Current frame length – current max coarse exposure.
Line periods.
01.4C
RO
Minimum fine integration time.
332 pixel periods.
06.DF
RO
Current line length - current max fine exposure.
1759 pixel periods.
0x1080 Hi
0x1081 Lo
0x1084 Hi
0x1085 Lo
0x1086 Hi
0x1087 Lo
0x1088 Hi
0x1089 Lo digital_gain_capability digital_gain_min digital_gain_max digital_gain_step_size
16UI
16UR
16UR
16UR
00.01
RO VS6663CD supports digital gain
00.01
RO 0.0039 minimum
01.FF
RO 1.996 maximum
00.01
RO 0.0039 step size
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Camera control interface (CCI) VS6663CD
4.2.12 Video timing parameter limit registers [0x1100 to 0x11FF]
Index Byte
Table 21. Video timing parameter limit registers [0x1100 to 0x11FF]
Register name Data type Default Type Comment
0x1100 Hi
0x1101 3rd
0x1102 2nd
0x1103 Lo min_ext_clk_freq_mhz
0x1104 Hi
0x1105 3rd
0x1106 2nd
0x1107 Lo
0x1108 Hi
0x1109 Lo
0x110A Hi
0x110B Lo max_ext_clk_freq_mhz min_pre_pll_clk_div max_pre_pll_clk_div
0x110C Hi
0x110D 3rd
0x110E 2nd
0x110F Lo
0x1110 Hi
0x1111 3rd min_pll_ip_freq_mhz max_pll_ip_freq_mhz
0x1112 2nd
0x1113 Lo
0x1114 Hi min_pll_multiplier
0x1115 Lo
0x1116 Hi
0x1117 Lo
0x1118 Hi
0x1119 3rd max_pll_multiplier min_pll_op_freq_mhz
0x111A 2nd
0x111B Lo
32SF
32SF
16UI
16UI
32SF
32SF
16UI
16UI
32SF
40.C0
00.00
41.D8
00.00
43.96
00.00
RO
Minimum external clock frequency
Units: MHz
Value: 6.0
RO
Maximum external clock frequency
Units: MHz
Value: 27.0
00.01
RO
Minimum Pre PLL divider value
Value: 1
00.04
RO
Maximum Pre PLL divider value
Value: 4
40.C0
00.00
41.40
00.00
RO
Minimum PLL input clock frequency
Units: MHz
Value: 6.0
RO
Maximum PLL input clock frequency
Units: MHz
Value: 12.0
00.19
RO
Minimum PLL multiplier
Value: 25
00.85
RO
Maximum PLL multiplier
Value: 133
RO
Minimum PLL output clock frequency
Units: MHz
Value: 300.0
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Table 21. Video timing parameter limit registers [0x1100 to 0x11FF] (continued)
Index Byte Register name Data type Default Type Comment
0x111C Hi
0x111D 3rd
0x111E 2nd max_pll_op_freq_mhz
0x111F Lo
0x1120 Hi min_vt_sys_clk_div
0x1121 Lo
32SF
16UI
44.48
00.00
RO
00.01
RO
Maximum PLL output clock frequency
Units: MHz
Value: 800.0
0x1122 Hi
0x1123 Lo
0x1124 Hi
0x1125 3rd
0x1126 2nd min_vt_sys_clk_freq_mhz
0x1127 Lo
0x1128 Hi
0x1129 3rd
0x112A 2nd max_vt_sys_clk_freq_mhz
0x112B Lo max_vt_sys_clk_div 16UI
32SF
32SF
00.04
RO
42.96
00.00
44.48
00.00
RO
RO
Minimum video-timing system clock divider value
Value: 1
Maximum video-timing system clock divider value
Value: 4
Minimum video-timing system clock frequency
Units: MHz
Value: 75.0
This value is 80 MHz in CSI2 mode.
Maximum video-timing system clock frequency
Units: MHz
Value: 800.0
The maximum value is 640 MHz in
CCP mode.
0x112C Hi
0x112D 3rd
0x112E 2nd
0x112F Lo
0x1130 Hi min_vt_pix_clk_freq_mhz
0x1131 3rd
0x1132 2nd
0x1133 Lo max_vt_pix_clk_freq_mhz
32SF
32SF
40.F0
00.00
42.A0
00.00
RO
RO
Minimum video-timing pixel clock frequency
Units: MHz
Value: 7.5
Maximum video-timing pixel clock frequency
Units: MHz
Value: 80.0
0x1134 Hi
0x1135 Lo min_vt_pix_clk_div 16UI 00.08
RO
Minimum video-timing pixel clock divider
Value: 8
0x1136 Hi max_vt_pix_clk_div
0x1137 Lo
16UI 00.0A
RO
Maximum video-timing pixel clock divider
Value: 10
0x1140 Hi min_frame_length_lines
0x1141 Lo
16UI 00.D0
RO
Minimum frame length allowed.
Value = 208
Units: Lines
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Camera control interface (CCI) VS6663CD
Table 21. Video timing parameter limit registers [0x1100 to 0x11FF] (continued)
Index Byte Register name Data type Default Type Comment
0x1142 Hi
0x1143 Lo max_frame_length_lines 16UI FF.FF
RO
Maximum possible number of lines per frame.
Value = 65535
Units: Lines
0x1144 Hi min_line_length_pck
0x1145 Lo
0x1146 Hi max_line_length_pck
0x1147 Lo
0x1148 Hi
0x1149 Lo min_line_blanking_pck
0x114A Hi
0x114B Lo
0x114C Hi
0x114D Lo min_frame_blanking_lines min_linelength_pck_step_size
16UI
16UI
16UI
16UI
16UI
0A.50
RO
Minimum line length allowed.
Value = 2640
Units: Pixel clocks
3F.FF
RO
05.30
RO
Maximum possible number of pixel clocks per line.
Value = 16383
Units: Pixel clocks
Minimum line blanking time in pixel clocks
Value = 1328
Units: Pixel clocks
00.0E
RO
Minimum frame blanking in video lines = 14
00.01
RO Minimum step size of line length pck
0x1180 Hi x_addr_min
0x1181 Lo
0x1182 Hi y_addr_min
0x1183 Lo
0x1184 Hi
0x1185 Lo x_addr_max
0x1186 Hi
0x1187 Lo y_addr_max
0x1188 Hi
0x1189 Lo
0x118A Hi
0x118B Lo
0x118C Hi
0x118D Lo
0x118E Hi
0x118F Lo min_x_output_size min_y_output_size max_x_output_size max_y_output_size
16UI
16UI
16UI
16UI
16UI
16UI
16UI
16UI
00.00
RO
Minimum X-address of the addressable pixel array
Value: Always 0
00.00
RO
05.0F
RO
03.CF
RO
01.00
RO
Minimum Y-address of the addressable pixel array
Value: Always 0
Maximum X-address of the addressable pixel array
Value = 1295
Maximum Y-address of the addressable pixel array
Value = 975
Minimum x output size in pixels.
Value: 256
00.C0
RO
Minimum y output size in pixels.
Value: 192
05.10
RO
Maximum x output size in pixels.
Value: 1296
03.D0
RO
Maximum y output size in pixels:
Value: 976
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Table 21. Video timing parameter limit registers [0x1100 to 0x11FF] (continued)
Index Byte Register name Data type Default Type Comment
0x11C0 Hi
0x11C1 Lo
0x11C2 Hi
0x11C3 Lo
0x11C4 Hi
0x11C5 Lo
0x11C6 Hi
0x11C7 Lo min_even_inc max_even_inc min_odd_inc max_odd_inc
16UI
16UI
16UI
16UI
00.01
RO Minimum Increment for even pixels
00.01
RO Maximum increment for even pixels
00.01
RO Minimum Increment for odd pixels
00.01
RO Maximum Increment for odd pixels
0x1700 Hi
0x1701 Lo
0x1702 Hi
0x1703 Lo
0x1704 Hi
0x1705 Lo
0x1706 Hi
0x1707 Lo
0x1708 Hi
0x1709 Lo
0x170A Hi
0x170B Lo
0x170c Hi
0x170d Lo
Index Byte
Table 22. Binning capability registers [0x1700 to 0x1713]
Register name Data type Default Type Comment min_frame_length_lines_bin max_frame_length_lines_bin min_line_length_pck_bin max_line_length_pck_bin min_line_blanking_pck_bin fine_integration_time_min_bin fine_integration_time_max_ margin_bin
16UI
16UI
16UI
16UI
16UI
16UI
16UI
00.D0
RO
Minimum frame length allowed in binning mode.
Units: Lines
FF.FF
3F.FF
05.30
01.24
RO
0A.50
RO
RO
RO
RO
07.EA
RO
Maximum possible number of lines per frame allowed in binning mode.
Value = 65535
Units: Lines
Minimum line length allowed in binning mode.
Value = 2640
Units: Pixel clocks
Maximum possible number of pixel clocks per line allowed in binning mode.
Units: Pixel clocks
Minimum line blanking time in pixel clocks allowed in binning mode.
Value = 1328
Units: Pixel clocks
Minimum fine integration time.
Pixel periods allowed in binning mode.
Current line length – current max fine exposure allowed in binning mode.
Pixel periods.
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Video data interface
5 Video data interface
VS6663CD
The video stream which is output from the VS6663CD through the compact camera port
(CCP) or camera serial interface (CSI) contains both video data and other auxiliary information. This chapter describes the frame formats.
The VS6663CD is MIPI CSI-2 version 1.00 and D-PHY 1.0 compliant.
The selection of the video data format is controlled using the register
CSI_SIGNALLING_MODE (0x0111):
0 - CCP2 Data/Clock
1 - CCP2 Data/Strobe
2 - CSI-2 (default)
Changing the video data format must be performed when the sensor is in software standby.
• The CSI-2 link supports the transmission of raw Bayer data at 1.3 Mpixel resolution up to 30 frame/s at 10-bit resolution.
• The CCP link supports the transmission of raw Bayer data at 1.3 Mpixel resolution up to 30 frame/s using10-8bit compressed data or 24 frame/s at 10-bit resolution.
• The VS6663CD has one CSI-2 data lane capable of transmitting at 800 Mbps.
• The VS6663CD CCP lane is capable of transmitting at 640 Mbps.
• The CSI-2 data lane transmitter supports:
– unidirectional master
– HS-TX
– LP-TX (ULPS)
– CIL-MUYN function
• The CSI-2 clock lane transmitter supports:
– unidirectional master
– HS-TX
– LP-TX (ULPS)
– CIL-MCNN function
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The frame format for the VS6663CD is described by the frame format description registers in
Table 11 on page 24 . For CCP2 this results in a frame as shown in
and for CSI-
2 it results in a frame as shown in Figure 12 .
Figure 11. VS6663CD CCP2 frame format
FS
2 embedded data lines
Frame start code
Bayer pixel data
FE
Interframe padding
Figure 12. VS6663CD CSI-2 frame format
FS Embedded data
Frame start packet
Bayer pixel data
Line blanking
Frame end code
FE
Frame end packet
Frame blanking
Embedded data lines
The embedded data lines provide a mechanism to embed non-image data such as sensor configuration details within the output data stream. The number of embedded data lines at the start and end of the frame is specified as part of the frame format description.
VS6663CD has two embedded data lines.
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Video data interface VS6663CD
Dummy pixel data
This is invalid pixel data. The receiver should always ignore dummy pixel data. The
VS6663CD has 0 dummy columns.
Visible pixel data
The visible pixels contain valid image data.The correct integration time and analog gain for the visible pixels is specified in the blank lines at the start of the frame.The number of visible pixels can be varied with the requested frame size.
Dark pixel data (light shielded pixels)
The VS6663CD has 0 dark pixels.
Black pixel data (zero integration time)
The VS6663CD has 0 black pixels.
Manufacturer specific pixel data
The VS6663CD has 0 manufacturer specific pixels.
Interline padding/line blanking
During interline padding all bits in the data stream in a CCP2 frame are set to 1.
In a CSI-2 frame there is no concept of line blanking being transmitted, the sensor will simply spend a longer time in the LP state between active line data.
Interframe padding / frame blanking
During interframe padding all bits in the data stream in a CCP2 frame are set to 1.
In a CSI-2 frame there is no concept of frame blanking being transmitted, the sensor will simply spend a longer time in the LP state at the end of the active data for a frame.
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Note:
The VS6663CD has the following methods available to achieve the required output size, these can be used independently or in conjunction with any other:
• analog crop, see
• binning, see
•
output crop, see Section 6.1.3
The VS6663CD does not support subsampling.
The programmable image size and output size are independent functions. It is the responsibility of the host to ensure that these functions are programmed correctly for the intended application.
Figure 13. Data flow
Imaging array
Analog crop
Binning
Output crop
The native size for the VS6663CD is 1280x 960, the maximum addressable array is 1296 x
976 which gives eight border pixels for the color reconstruction algorithms to use at the edges of the array.
By programming the x_addr_start, y_addr_start, x_addr_end and y_addr_end registers it is possible to use the full size of the array as you would do for a native size output or you can select a “window of interest”. The addressed region of the array is used in any subsequent binning operation.
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Video timing
Figure 14. Analog crop x_addr_min, y_addr_min x_addr_start, y_addr_start
Addressed pixel array region
VS6663CD x_addr_min = 0 y_addr_min = 0 x_addr_max = 1295 y_addr_max = 975 x_addr_end, y_addr_end x_addr_max, y_addr_max
The host must ensure the following rules are kept:
• the end address must be greater than the start address
• the x and y start addresses are restricted to even numbers only, and the x and y end addresses are restricted to odd numbers only, to ensure that there is always a even number of pixels read-out
6.1.2 Binning
The VS6663CD also has a binning mode that offers a reduced size full field of view image.
The binning mode averages row and column pixel data.
The binning mode results in a reduced number of lines and so can be used to give a higher image frame rate. Compared to subsampling, binning makes use of the light gathered from the whole pixel array and it results in higher image quality.
The binning mode will scale by 2x2 in the X and Y direction. Entering and exiting binning mode may or may not be performed when the sensor is in software standby.
Table 23 summarizes the register setting for enabling binning mode. (The x/y_odd_inc
registers are automatically set and do not require to be set by the user.)
Register binning_mode
Table 23. Binning register settings
Address Normal
0x0900 0
Binning 2x2
1
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The x_output_size and y_output_size registers are not intended as the primary cropping controls.
They are intended to define the position of the LE/FE codes in the CCP2 data frame so that the sensor does not need to calculate this based on analog crop or binning settings. It should be expected that the host will set the output sizes to exactly enclose the output image data. If the host should not do this, the VS6663CD treats the output size as being calculated from the top left hand corner of the output array. So in the case where output sizes are smaller than the output data, the data shall be cropped from its right-hand and lower limits. In the case where larger than the output data, the lines shall be padded out to the defined output size with undefined data.
Figure 15. Output size within a CCP2 data frame
CCP2 output active line length
FS
2 embedded data lines x_output_size
Output data
Interframe padding
FE
The number of pixels between the line start and the line end sync codes for:
•
RAW8 is a multiple of 4 pixels
• RAW10 is a multiple of 4 pixels for CSI-2 and a multiple of 16 pixels for CCP2
The host must control the x_output_size to ensure that the above criteria is met.
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Video timing VS6663CD
This section specifies the timing for the image data that is readout from the pixel array and the output image data. These are not necessarily the same size.
The application of all of the video timing read/write parameters must be re-timed to the start of frame boundary to ensure that the parameters are consistent within a frame. The video stream which is output from the VS6663CD contains both video data and other auxiliary information.
The VS6663CD contains a phase locked loop (PLL) block, which generates all the necessary internal clocks from the external clock input. Changes to the PLL settings on the
VS6663CD will only be consumed on the software standby to streaming mode transition.
shows the internal functional blocks, which define the relationship between the external input clock frequency and the pixel clock frequency.
The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is clocked by the external input clock.
Figure 16. Clock relationship
External input clock ext_clk_freq_mhz
PLL input clock pll_ip_clk_freq_mhz
PLL output clock pll_op_clk_freq_mhz
Video timing system clock vt_sys_clk_freq_mhz
Video timing pixel clock vt_pix_clk_freq_mhz
Max.
27 MHz pre_pll_ clk_div
Max.
12 MHz pll_multiplier
Max.
800 MHz vt_sys_clk
_div
Max.
800 MHz
(2) vt_pix_clk
_div
Max.
80 MHz
Ext. input clock
Min.
6 MHz
Range
1, 2, 4
Min.
6 MHz
Min.
25
Max.
133
Min.
300 MHz
Range
1, 2, 4
Min.
75 MHz
(1)
Min.
8
Max.
10
Min.
7.5 MHz
1. The minimum vt_sys_clk_freq_mhz is 80 MHz in CSI-2 mode.
2. The maximum vt_sys_clk_freq_mhx is 640 MHz in CCP mode.
The equation relating the input clock frequency to pixel clock frequencies is: vt_pix_clk_freq_mhz = ext_clk_freq_mhz
-------------------------------------------------------------------------------------------------------------------------------pre_pll_clk_div ×
× pll_multiplier vt_sys_clk_div × vt_pix_clk_div
6.2.2 Framerate
The framerate of the array readout and therefore the output framerate is governed by the line length, frame length and the video timing pixel clock frequency.
• line length is specified as a number of pixel clocks, line_length_pck
• frame length is specified as a number of lines, frame_length_lines
• video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz
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VS6663CD Video timing
The equation relating the framerate to the line length, frame length and the video timing pixel clock frequency is:
Framerate = vt_pix_clk_freq_mhz
----------------------------------------------------------------------------------------------line_length_pck × frame_length_line
Table 24 provides examples of frame timing for Raw10 CSI-2 mode for 30 fps at a variety of
external clock frequencies.
Table 24. External clock frequency examples - 1.3 Mpixel resolution Raw10 30 fps
Ext clk freq
Pre-PLL clk div
PLL multiplier
VT sys clk div
VT pixel clk div
VT pixel clk freq
Line length
Frame length
MHz
9.60
12.00
13.00
Integer
1
2
2
Integer
(Dec)
83
133
123
Integer
1
1
1
Integer
10
10
10
MHz
79.68
79.80
79.95
Pixel clks
2640
2640
2640
Lines
(Dec)
1006
1007
1009
The three color (Red, Green, Blue) filters are arranged over the pixel array in a repeated 2x2 arrangement known as the Bayer Pattern. When the sensor array is read, the output order of red, green, blue depends on the settings of vertical flip and horizontal mirror.
shows the read-out order for the default settings of vertical flip and horizontal mirror turned off. Vertical flip changes the first line to be output from a green/red line to a blue/green line and horizontal mirror changes the sequence within a line, for example, green/red to red/green.
As shown in
, the first pixel to be readout from the imaging array will be green followed by red.
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Video timing
Figure 17. Bayer pattern
0 1 2 3 4 5 6 7
0
Green Red Green Red Green Red Green Red
1
Blue Green Blue Green Blue Green Blue Green
2
Green Red Green Red Green Red Green Red
3
Blue Green Blue Green Blue Green Blue Green
4
Green Red Green Red Green Red Green Red
5 Blue Green Blue Green Blue Green Blue Green
1296 ACTIVE COLUMNS
976 ACTIVE ROWS
VS6663CD
Green Red Green Red Green Red Green Red
Green Red Green Red Green Red Green Red
970
Blue Green Blue Green Blue Green Blue Green
971
972
Blue Green Blue Green Blue Green Blue Green 973
Green Red Green Red Green Red Green Red 974
Blue Green Blue Green Blue Green Blue Green 975
1288 1289 1290 1291 1292 1293 1294 1295
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VS6663CD
6.3
Video timing
Exposure and gain control
VS6663CD does not contain any form of automatic exposure control. To produce a correctly exposed image the integration period and analog gain for the pixels must be calculated by an exposure control algorithm implemented externally. The parameters are then written to the VS6663CD through the CCI interface.
The exposure control parameters available on VS6663CD are:
• fine integration time
• coarse integration time
• analog gain
• digital gain
The exposure control parameter registers are defined in
Section 4.2.6: Integration time and gain registers [0x0200 to 0x02FF] on page 27
.
Integration time and analog gain capability registers should be used to determine the exposure control parameter limits for a given video timing configuration.
VS6663CD only supports the single global analog gain mode.The gain is monotonic to avoid instabilities in the exposure loop VS6663CD has a 16-bit register (0x0204 and
0x0205) to control analog gain.
shows how the analog gain bits are used for VS6663CD.
Figure 18. Analog gain register format
A15 A14 A13 A12 A11 A10 A9
Not used
A8 A7 A6 A5 A4
Coarse gain
A3 A2
Not used
A1 A0
Not used
The following generic equation describes VS6663CD gain behavior specified by the analog gain description registers 0x008A to 0x0093: gain = c0
⁄ m
⋅
+ c1
) where: m
1
= -1 c
0
= 256 c
1
= 256
Table 25 specifies the valid analog gain values for VS6663CD.
Gain value (0x0204/0x0205)
Table 25. Analog gain control
Coarse gain code [A7:A4]
0x0000
0x0010
0x0020
0x0030
0000
0001
0010
0011
Coarse analog gain
0.00 dB (x1.00)
0.6 dB (x 1.07)
1.1 dB (x1.14)
1.8 dB (x1.23)
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Video timing VS6663CD
Table 25. Analog gain control (continued)
Gain value (0x0204/0x0205) Coarse gain code [A7:A4] Coarse analog gain
0x0040
0x0050
0x0060
0x0070
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x00D0
0x00E0
0x00F0
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2.5 dB (x1.33)
3.2 dB (x1.45)
4.1 dB (x1.60)
5.0 dB (x1.78)
6.0 dB(x2.00)
7.2 dB (x2.29)
8.5 dB (x2.66)
10.1 dB (x3.20)
12.0 dB (x4.00)
14.5 dB (x5.33)
18.1 dB (x8.00)
24.1 dB (x16.00)
6.3.3
To help compensate for the relatively coarse analogue gain steps, VS6663CD contains a digital multiplier to “fill” in the missing steps. By mixing analogue and digital gain it is possible to implement 3% gain steps across the full 1x to 16x gain range
The details of the digital gain implementation are listed below:
• four individual 16-bit digital channel gains - one per Bayer channel
– digital_gain_greenR (0x020E and 0x020F)
– digital_gain_red (0x0210 and 0x0211)
– digital_gain_blue (0x0212 and 0x0213)
– digital_gain_greenB (0x0214 and 0x0215)
• The digital gain range for each channel is 0.0039 to 1.996 in steps of 0.0039 (1/256)
– digital_gain_min {0x1084:0x1085} = 0x0001 (0.0039)
– digital_gain_max {0x1086:0x1087} = 0x01FF (1.996)
– digital_gain_step {0x1088:0x1089} = 0x0001 (0.0039)
Integration and gain parameter retiming
The modification of exposure parameter (coarse integration time or gain) register values does not take effect immediately.
The exact time at which changes to certain parameters take effect is controlled both to ensure that each frame of image data produced has consistent settings and that changes in groups of related parameters can be synchronized.
To eliminate the possibility of the sensor array seeing only part of the new exposure and gain setting, if the serial interface communications extends over a frame boundary, the internal retiming of exposure and gain data is disabled while writing data to the serial interface register map. Therefore if the 4 bytes of exposure and gain data is sent as an auto-
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VS6663CD Video timing increment CCI sequence, it is not possible for the sensor to consume only part of the new exposure and gain data.
However if it is not possible for the host to use auto-increment CCI register accesses and only discrete register accesses are possible then the VS6663CD has a mechanism to temporarily suspend the automatic application of updated exposure register values.
A group of parameter changes is marked by the host using a dedicated Boolean control parameter, grouped_parameter_hold (register 0x0104). Any changes made to ‘retimed’ parameters while the grouped_parameter_hold signal is in the ‘hold’ state will be considered part of the same group. Only when the grouped_parameter_hold control signal is moved back to the default ‘no-hold’ state will the group of changes be executed by VS6663CD.
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Electrical characteristics VS6663CD
All parameter values quoted in this outline product specification are design targets and will be confirmed by evaluation of initial samples and device characterization.
Typical values quoted for nominal voltage, process and temperature. Maximum values are quoted for worst case conditions (process, voltage and functional temperature) unless otherwise specified.
7.1 Absolute maximum ratings
Symbol
Table 26. Absolute maximum ratings
Parameter Minimum Maximum Unit
V
DIGMAX
V
V
T
ANAMAX
IP(DIG)
STO
Digital power supply
Analog power supply
Digital input voltage
(1)
Storage temperature
Electrostatic discharge model
Human body model
(3)
Charge device model
(4)
-0.3
-0.3
-0.3
-40
V
2.2
3.2
ANA
+ 0.3
+ 85
(2) o
V
V
V
C
V
ESD
-2
-500
2
500
1.
Digital input: EXTCLK, XSHUTDOWN, SCL, SDA
2.
This is a maximum long term standard storage temperature, see soldering profile for short term high temperature tolerance
3.
HBM tests are performed in compliance with JESD22-A114F
MM test is performed in compliance with JESD22-A115A Class B if HBM pass level is less than 1000V.
4.
CDM ESD tests are performed in compliance with JESD22-C101D
KV
V
Caution: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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VS6663CD Electrical characteristics
7.3
Symbol
Table 27. Operating conditions
Parameter Minimum Typical Maximum
Voltage
VDIG
VANA
Digital power supply
Analog power supply
1.68
2.6
Temperature
T
AS
T
AF
T
AN
T
AO
T
AT
Temperature (storage
Temperature (test
(6)
)
(1)
)
Temperature (functional operating
(2)
Temperature (normal operating
(3)
Temperature (optimal operating
(4)
)
)
(5)
)
1.
Camera has no permanent degradation.
2.
Camera is electrically functional.
3.
Camera produces “acceptable” images.
4.
Camera produces optimal optical performance.
5.
Camera surface temperature.
6.
100% tested parameters are measured at this temperature.
-40
-30 -
-25
+5
+21
-
-
-
-
1.8
2.8
1.92
2.9
+85
+70
+55
+40
+25
Unit
V
V
°C
°C
°C
°C
°C
Power supply - VDIG, VANA
Table 28. Power supplies VDIG, VANA
Digital Analogue
Parameter
Hardware standby
Streaming
(1)
1.
Full resolution, 10-10data, 30 fps, CSI-2
Typical Maximum Typical Maximum
2
18
20
50
2
40
10
55
Unit
µA mA
The peak current consumption of the sensor module is defined as any current pulse
>=10 μs. Peak current is assumed to be <1.33 x maximum average current for the stated operating mode and worst case conditions. The duty cycle of the peak to the low part of the current profile is 33% with a worst-case period of 500 μs.
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Electrical characteristics
7.4 System clock - EXTCLK
Symbol
Table 29. System clock - EXTCK
Parameter
Clock frequency input
Minimum
6.0 - 1%
(1) f
EXTCLK
Leakage current 4
(2)
1.
Nominal frequencies are 6.0 to 27 MHz with a 1% centre frequency tolerance.
2.
With DC coupled square wave clock.
3.
With DC VDIG applied.
Maximum
27 + 1%
(1)
30
(3)
VS6663CD
Unit
MHz
μA
7.5 Power down control - XSHUTDOWN
Symbol
V
IL
V
IH
Table 30. Power down control - XSHUTDOWN
Parameter Minimum Typical Maximum
Low level input voltage
High level input voltage
0
0.7 VDIG -
0.3 VDIG
VANA
Unit
V
V
7.6 CCI interface - SDA, SCL
Symbol
Table 31. CCI interface - DC specification
Parameter Minimum
V
IL
V
IH
V
OL
I
IL
Low level input voltage
High level input voltage
Low level output voltage
Low level input current
(1)
I
IH
High level input current
1.
V
OH
not valid for CCI. 3mA drive strength
0
0.7 * VDIG
0
-
-
Maximum
0.3 * VDIG
VDIG
0.2 * VDIG
-10
10
Unit
V
V
V
µA
µA
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VS6663CD Electrical characteristics
SDA
Symbol
Table 32. CCI interface - timing characteristics
Parameter t t t t
SCL
LOW
HIGH
SP
SCL clock frequency
Clock pulse width low
Clock pulse width high
Pulse width of spikes which are suppressed by the input filter t
BUF t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
R t
F t
SU.STO
Ci/o
Bus free time between transmissions
Start hold time
Start set-up time
Data in hold time
Data in set-up time
SCL/SDA rise time
SCL/SDA fall time
Stop set-up time
Input/output capacitance (SDA)
Cin Input capacitance (SCL)
1.
Cb = total capacitance of one bus line in pF
Minimum
0
1.3
0.6
0
1.3
0.6
0.6
0
100
20+0.1 Cb
(1)
20+0.1 Cb
(1)
0.6
-
-
Typical
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Maximum Unit
400
-
kHz
μs
μs
50 ns
-
-
-
0.9
-
μs
μs
μs
μs ns
300 ns
300
-
8
6 ns
μs pF pF stop start
Figure 19. CCI AC characteristics
...
0.7 VDIG
0.3 VDIG start stop
SCL t
BUF
0.7 VDIG
0.3 VDIG t
LOW t
R t
F
...
t
HD.STA
t
HD.DAT
t
HIGH t
SU.DAT
All timings are measured from either 0.3 VDIG or 0.7 VDIG.
t
SU.STA
t
HD.STA
t
SU.STO
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Electrical characteristics VS6663CD
7.7.2
Symbol
Table 33. CCP2 interface - DC specification
Parameter
Differential voltage swing
(1)
Minimum
100
Typical Maximum
150 200
Unit
I
V
OD
V
R
CM
O
DR
Common mode voltage (self biasing)
Output Impedance
Drive current range
(internally set by bias circuit)
0.8
40
0.5
0.9
1.5
1.0
140
2 mV
V
Ω mA
0 - 100MHz 30 dB
PSRR
(2)
100 - 1000MHz 10 dB
1.
Measured over a 100
Ω load
2.
Nominal value for the interference at V
CM
voltage through digital supply relative to the interference at digital supply over the 0-1 GHz operating range. PSRR = 20*log10 (V interference (peak-to-peak))
DIG
interference (peak-to-peak) / V
CM
CCP2 interface - timing characteristics
The parameters in
Table 34 are measured across a terminated 100
Ω transmission line, in data/strobe mode.
Symbol
Table 34. CCP2 interface - timing characteristics
Parameter
F p
T p
T jitter
(1) t stable
Average data frequency
Average data period
Data period Jitter
Both data and clock at the stable level
T rise
Rise time of DATA+/DATA-
,CLK+/CLK-
T fall
Fall time of DATA+/DATA-,
CLK+/CLK-
T skew
(2) t
PWR
Total skew between signals
Power up/down time
1.
T
Pmax
-T
Pmin
2.
T skew
=T cmpskew
+ T chcskew
Min.
-
1.56
-
780
300
300
-
-
Max.
640
-
200
-
400
400
225
20
Unit
Mbits/s ns ps ps ps ps ps
μs
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VS6663CD
DATA+/
DATA-
CLK+/
CLK-
T cmpskew
T chcskew
Figure 20. SubLVDS AC timing
Electrical characteristics
80%
0.9V
20%
T stable
T fall
80%
0.9V
20%
T
Pmin
T
Pmax
T rise
Symbol
Table 35. CSI-2 interface - high speed mode - DC specification
Parameter Minimum Typical Maximum
V
CMTX
HS transmit static common mode voltage
150 200 250
V
OD
V
OHHS
HS transmit differential voltage
(1)
140 200
Z
OS
Single Ended Output Impedance 40 50
1.
Value when driving into load impedance anywhere in the Z
ID
range (80-125
Ω
).
270
HS output high voltage
(1)
360
62.5
Symbol
V
OH
V
OL
Z
OLP
Table 36. CSI-2 interface - low power mode - DC specification
Parameter Minimum Typical Maximum
Output high level
Output low level
Output impedance of LP transmitter
1.1
-50
110
1.2
1.3
50
Unit
V mV
Ω
Unit mV mV mV
Ω
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Electrical characteristics VS6663CD
Note:
Symbol
Table 37. CSI-2 interface - high speed mode - AC specification
Parameter Minimum Typical Maximum Unit t r
and t f t skew
Data rate
20% - 80% rise time and fall time
Data to clock skew
80
150
-0.15UI
-
-
800
0.3UI
(1)
0.15UI
Mbits/s ps ps
1.
UI is equal to 1/(2*fh) where fh is the fundamental frequency of the transmission for a certain bit rate. For example, for 800 Mbps, fh is 400 MHz.
Symbol t r
and t f
Table 38. CSI-2 interface - low power mode - AC specification
Parameter
15% - 85% rise time and fall time
Minimum Typical Maximum
25
Unit ns
For further information on the D-PHY please refer to the following specification document:
MIPI Alliance Standard for D_PHY version 1.00.
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VS6663CD Optical specification
Table 39. Lens design characteristics for first source lens supplier
Parameter Value
2-element plastic lens
F/number
Effective focal length
Horizontal FOV
Nominal focusing distance
Stray-light
-
2.8
2.31mm (paraxial)
50.7
°
15 cm
No undesirable stray-light artefact's to be present in image at contrast of:
1:10
5
out of scene
1:10
4
in scene
Spectral weighting:
Wavelength (nm)
Weight
656.28
151
Lateral chromatic aberration from blue
( λ=435nm) to red (λ=640nm)
< |3.8 um|
587.56
318
546.07
312
486.13
157
435.84
49
404.66
13
Coating reflectance - All surfaces are coated. At least 50% of all surfaces must fulfil this specification.
< 400 nm
400 - 670 nm
>670 nm
No limitation
≤ 1.0% absolute, 0.35% avg
Straight line with a slope of < 3% /
100nm
Maximum chief ray angle 29 °
As is common with many CMOS image modules the camera should not be pointed at bright static objects for long periods of time as permanent damage to the sensor may occur.
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On-chip image optimization
9 On-chip image optimization
9.1
VS6663CD
Mapped couplet correction (Bruce filter)
The mapped couplet defect correction filter is designed to intelligently correct the first defect in a couplet thereby changing a couplet into a single pixel defect. Single pixel correction is achieved either by the median filter or by the host (coprocessor, MMP or baseband). The mapped couplet correction filter operates in both full resolution, and in binned mode.
The mapped couplet correction filter requires exact coordinate information for each of the couplets to be repaired. The couplet coordinates are stored in non-volatile-memory (NVM) during production test.
The mapped couplet correction is controlled by register 0x0B05:
0 - Disable
1 - Enable
9.3
This is a simple 1-D median filter defect correction which replaces every pixel value by the median of itself, its predecessor and its successor (respecting the color pattern). The median filter operates in both full resolution, and in binned mode. It is suggested that this filter is only used for viewfinder images or other non stored images. (Note that the median filter will not correct any defective pixels which occur in either the first two or the last two columns).
The selection of the median filter is controlled using register (0x0B06)
0 - Disable
1 - Enable
Lens shading correction
The VS6663CD has an adaptive (four color temperature) lens shading correction function which can be used to reduce the effect of roll off in the optical system. Correction is carried out individually for all four color planes, each gain is calculated based on the distance from the image centre to the pixel in question using a two factor polynomial (R
2
and R
4
). The lens shading filter operates in both full resolution, and in binned mode. The correction applied is
75%.
In order to optimize the AV algorithm, the coefficients for each device are calculated under
D65 (Fluorescent Philips Graphica Pro 965) lighting conditions and programmed in the NVM memory at production test. (The coefficients from the NVM can be overwritten).
Settings for three other color temperatures (Cool White, U30, and Horizon) are calculated from characterization data and these are stored in the NVM memory.
The calculation of the color temperature is performed by the sensor using the white balance gains. The white balance gains can either be calculated internally by the sensor or they can be calculated by the host and written back to the sensor.
provides an example of lens shading correction.
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Figure 21. Lens shading images
Original image Corrected image
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Mechanical
10 Mechanical
Figure 22. VS6663CD outline drawing - 1 of 3 - All dimensions in mm
VS6663CD
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VS6663CD
Figure 23. VS6663CD outline drawing - 2of 3 - All dimensions in mm
Mechanical
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Mechanical
Figure 24. VS6663CD outline drawing - 3 of 3 - All dimensions in mm
VS6663CD
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VS6663CD
11 Application
11.1 Schematic
Figure 25. Mobile camera application
Application
External clock
1.8V
2.8V
VCAP
VS6663CD
220nF
220nF
.
.
VDIG
VANA
3.6V
CHARGE
PUMP
EXTCLK
DATA+
DATA-
CLK+
CLK-
XSHUTDOWN
470nF
VCORE
SCL
SDA
GND
100R
100R
SubLVDS data
SubLVDS clock
Power down signal
4.7k
1.8V
CCI control lines
Notes:
No connection should be made to VCAP.
CCCP2 100R termination may be internal to subLVDS receiver. For CSI-2, the receiver is mandated to have an internal termination which is dynamically switched in and out depending on whether the link is in HIGH SPEED or
LOW POWER mode. This transition occurs every line.
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ECOPACK
®
12 ECOPACK
®
VS6663CD
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
® specifications, grade definitions and product status are available at: www.st.com
.
ECOPACK
®
is an ST trademark.
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VS6663CD
Date
19-Jan-2015
09-Sep-2015
Table 40. Document revision history
Revision Changes
1
2
Initial release.
Updated disclaimer
Revision history
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VS6663CD
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