STMicroelectronics High performance 3 A ULDO linear regulator Datasheet
Reklamë
Reklamë
L6935
High performance 3 A ULDO linear regulator
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
Up to 5 V input voltage range
60 m
Ω max R
DS(on)
35
µA shut-down current
3 A maximum output current
Split bias and power supplies
Adjustable output voltage: 0.5 V to 3.0 V
Excellent load and line regulation: 1 % accuracy (over temperature)
MLCC supported
Programmable soft-start
Short-circuit protection
3.5 A overcurrent protection
Thermal shut-down
VFQFPN20 4 x 4 x 1.0 mm package
Applications
■
■
■
■
■
■
Motherboard
Mobile PC
Hand-held instruments
PCMCIA cards
Processors I/O
Chipset and RAM supply
Table 1.
Device summary
Order codes
L6935
L6935
TR
VFQFPN20
(4.0 x 4.0 x 1.0 mm)
Description
L6935 is an ultra low drop output linear regulator operating up to 5 V input and is able to support output current up to 3 A. Designed with an internal low-R
DS(on)
N-channel MOSFET, it can be used for on-board DC-DC conversions saving in real estate, list of components and power dissipation.
Bias input and power input are split to allow linear conversion from buses lower than 1.2 V minimizing power losses.
L6935 provides the application with an adjustable voltage from 0.5 V to 3.0 V with a voltage regulation accuracy of 1 %. soft-start is available to program the output voltage rise-time according to the external capacitor connected.
Enable and Power Good functions make L6935 suitable for complex systems and programmable start-up sequencing.
The current limit at 3 A protects the system during a short circuit. The current is sensed in the power
DMOS in order to limit the power dissipation.
Thermal shut down limits the internal temperature at 150 °C with a hysteresis of 20 °C.
Package
VFQFPN20
Packing
Tube
Tape and reel
May 2008 Rev 1 1/20
www.st.com
20
Contents
Contents
L6935
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VIN, VBIAS and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VFQFPN20 mechanical data and package dimensions . . . . . . . . . . . . 18
2/20
Typical application circuit and block diagram
1 Typical application circuit and block diagram
L6935
Figure 1.
Typical application circuit - VIN
=
VBIAS
V
IN
EN C
IN
C
SS
VBIAS
VIN VOUT
L6935
R
1
EN ADJ
SS GND PAD PGOOD
R
2
V
OUT
= 0.5V to 3.0V
C
OUT
PGOOD
L6935 Reference Schematic
Figure 2.
Typical application circuit - VIN
≠
VBIAS
V
BIAS
V
IN
= 0.75V to V
BIAS
EN
C
IN
C
SS
VBIAS
VIN VOUT
EN
L6935
R
1
ADJ
SS GND PAD PGOOD
R
2
V
OUT
> 0.5V (*)
C
OUT
PGOOD
L6935 Reference Schematic
(*) Vin may decrease until the minimum drop is reached. Conversely, Vout can rise untile the minimum drop is reached.
3/20
Typical application circuit and block diagram
Figure 3.
Block diagram
VIN
VBIAS
SS
CHARGE
PUMP
CURRENT
LIMIT
REFERENCE
0.500V
VREF
+
-
ERROR
AMPLIFIER
DRIVER
EN ENABLE
THERMAL
SENSOR
GND
0.9 VREF
+
-
L6935
VOUT
ADJ
PGOOD
4/20
Pins description and connection diagrams
2 Pins description and connection diagrams
Figure 4.
Pins connection (top view)
L6935
N.C.
N.C.
N.C.
N.C.
N.C.
11
10 9 8 7
12
6
5
4
13
14
L6935
3
2
15
16 17 18 19 20
1
PGOOD
N.C.
N.C.
GND
N.C.
5/20
Table 2.
Pin #
1
2
3, 4
5
6
7
8 to 10
11 to15
16 to 18
Pins descriptions
Name
N.C.
GND
N.C.
PGOOD
VBIAS
EN
VIN
N.C.
VOUT
Function
Not internally connected.
Ground connection. Connect to PCB ground plane.
Not internally connected.
Power Good output flag: the pin is open drain and it is forced low if the output voltage is lower than 90 % of the programmed voltage. If not used, it can be left floating.
Input bias supply. This pin supplies the internal logic to drive the power
N-channel MOSFET that realize the voltage conversion. Connect directly to
V
IN
or to a different supply ranging from V
IN
to 5 V.
The voltage connected to this pin MUST always be higher or equal that V
IN
.
Enables the device if a voltage higher than 1 V is applied.
When pulled low, the device is in low-power consumption: everything inside the controller is kept OFF.
See
for details about EN signal and power sequencing.
Power supply voltage. This pin is connected to the drain of the internal
N-channel MOSFET.
Filter to GND with capacitor larger than the one used for V
OUT
.
Not internally connected.
Regulated output voltage. This pin is connected to the source of the internal N-mos. MLCC capacitor are supported. Filter to GND with capacitor smaller than the one used for V
IN
.
Pins description and connection diagrams L6935
Table 2.
Pin #
19
20
PAD
Pins descriptions (continued)
Name
ADJ
SS
GND
Function
Feedback for the IC regulation.
Connecting this pin through a voltage divider to V
OUT
, it is possible to program the output voltage between 0.5 V and 3.0 V.
Soft-start pin. The soft-start time is programmed connecting an external capacitor C
SS
from this pin to GND.
In steady state regulation, the voltage at this pin is 3.3 V.
Ground connection. Connect to PCB GND Plane with enough VIAs to improve thermal conductivity.
6/20
Electrical specifications L6935
3.1 Absolute maximum ratings
Table 3.
Absolute maximum ratings
Symbol Parameter
VIN to GND
VBIAS, EN, PGOOD to GND
SS, VOUT
ADJ to GND to GND
Maximum withstanding voltage range test condition:
CDF-AEC-Q100-002 “human body model” acceptance criteria: “normal performance”
Value
5.5
6
-0.3 to 3.3
-0.3 to 1
±1000
Unit
V
V
V
V
V
Table 4.
Symbol
Thermal data
Parameter Value Unit
R thJA
T
MAX
T
STG
Thermal resistance junction to ambient
Maximum junction temperature
Storage temperature range
(1)
55
150
-50 to 150
°C/W
°C
°C
T
J
Junction temperature range -25 to 150 °C
1.
Measured with the component mounted on demonstration board in free air (22 x 28.5 mm - 2 layer 70
µm copper).
7/20
Electrical specifications L6935
Table 5.
Electrical characteristics
(V
IN
= 5 V, V
BIAS
= 5 V; T
A
= 25
°C unless otherwise specified).
Parameter Test conditions Min Symbol Typ Max
Recommended operating conditions
VIN Operating supply voltage
VBIAS UVLO
I
IN
Quiescent current
Shut-down current
V
IN
= V
BIAS
V
BIAS
< 5 V
V
BIAS
rising
Iout = 0 A
V
IN
= V
BIAS
= 3.3 V
V
IN
= V
BIAS
= 5.0 V
2.3
Voltage regulation
VOUT Output voltage
Line regulation
Io = 0.1 A; V
IN
= 3.3 V; ADJ = OUT 0.496
0.500
0.504
Vin = 3.30 V +/- 10 %; Io = 10 mA
Vin = 4.50 V +/- 10 %; Io = 10 mA
2.5
2.5
ADJ
Load regulation Vin = 3.3 V; Io = 100 mA to 3 A
Ripple rejection
(1)
F = 100...120 Hz; Io = 10 mA
Vin = 3 V;
∆Vin = 2 Vpp; Vout = 1 V
Drain-to-source resistance Io = 3 A R
DS(on)
Enable, SS and protections
45
30
7
60
3.15
77
3.50
3.85
85
I
OCP
PGOOD
Current limiting
Power Good threshold
Hysteresis
Voltage low
Vo = 1.8 V
V
ADJ
falling, wrt Ref.
EN
SS
OT
Enable threshold
Soft start current
Thermal shut-down
I = -1 mA
EN rising
Vss = 0 V
Temperature rising
(1)
Hysteresis
(1)
1.
Parameter guaranteed by design, not tested in production
10
1.0
150
20
0.4
1.05
5.0
V
BIAS
1.275
3
25
40
Unit
A
%
%
V
V
µA
°C
°C
V
V mA
µA
V mV mV dB m
Ω
8/20
Typical performances L6935
Figure 5.
Output voltage and OC threshold vs junction temperature
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40 -20 0 20 40 60
Temperature [°C]
80 100 120 140
4.0
3.8
3.6
3.4
3.2
3.0
-40 -20 0 20 40 60
Temperature [°C]
80 100 120 140
Figure 6.
Quiescent and shutdown current vs junction temperature
4.0
3.8
3.6
3.4
3.2
3.0
-40 -20 0 20 40 60
Temperature [°C]
80 100 120 140
40
35
30
25
20
5 VIN
15
10
5
0
-40
3 VIN
-20 0 20 40 60
Temperature [°C]
80 100 120 140
Figure 7.
Line regulation
0.2%
VBIAS = VIN, VOUT = 0.5V
0.1%
0.0%
-0.1%
-0.2%
1.0
1.5
2.0
2.5
3.0
V
IN
[V]
3.5
4.0
4.5
5.0
0.2%
0.1%
0.0%
-0.1%
VBIAS = 1.4V, VOUT = 2V
-0.2%
2.0
2.5
3.0
3.5
V
IN
[V]
4.0
4.5
5.0
9/20
Typical performances
Figure 8.
Load regulation
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
0.0
VBIAS = 1.4V, VIN = 2.6V, VOUT = 2V
0.5
1.0
1.5
Output Current [A]
2.0
2.5
L6935
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
0.0
VBIAS = VIN = 1.4V, VOUT = 0.5V
0.5
1.0
1.5
Output Current [A]
2.0
2.5
10/20
Device description L6935
5.1 Soft-start
L6935 implements a soft-start feature to smoothly charge the output filter avoiding high inrush currents to be required to the input power supply.
The soft-start process begins as soon as V
A constant current I
SS
BIAS
reaches UVLO and ENABLE is asserted.
= 1.0
µA is sourced through the SS pin: connecting an external capacitor (C
SS
) to this pin a voltage ramp is implemented; the voltage ramp internally clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the voltage on C
SS
reaches the V
REF
value the internal clamp is released.
In this way, the soft-start process lasts for:
T
SS
= C
SS
⋅
V
--------------
I
SS
=
⋅
5
⋅
C
SS where C
SS
is the external capacitor [F] and T
SS
is the soft-start time [sec.].
If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped to GND for a fixed time of about 50
µs. in order to discharge the residual charge present on
C
SS
: in this way, the device will be ready for a new SS process as ENABLE is asserted again.
describes a typical soft-start process.
Figure 9.
Soft start process diagram (left) and measured (right)
Vbias
>1.1V
ENABLE
>0.7V
ADJ
0.5V
Vout
Programmed Vout
~50
µsec
Programmed Tss
11/20
Device description L6935
L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft start procedure, and is left free when V
OUT
reaches 90 % of the programmed value.
An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise
shows the PGOOD commutations.
Figure 10.
Power good window
5.3 V
IN
vs V
BIAS
L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than the power input (VIN). The aim of this feature is to provide low-drop regulation still having the supply voltage to correctly drive the internal power mosfet so optimizing the conversion.
VIN drives only the drain of the power DMOS and it can be kept as low as possible
(V
IN
> V
OUT
+ V
DROPmin
), while V
BIAS higher than V
IN
.
drives the control section. V
BIAS
must be typically
5.4 Protections
L6935 is equipped with a set of protections in order to protect both the load and the device from electrical overstress. Each protection does not latch the device, that returns to work properly as the perturbation disappear.
An over current protection is provided: if the current that flows through the power DMOS is greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep constant the delivered current (I
OUT
PGOOD to be set low.
). Anyhow the output may drop also causing the
show the way the OCP intervention: as the threshold value is reached by I
OUT
, the device forces a lower output current (~3.5 A).
12/20
Device description
Figure 11.
Over-current protection
L6935
The device constantly monitors its internal temperature. As the silicon reaches a 150 °C, the control circuit turns off the power DMOS, and stays off until a safe temperature of
150° - 20° = 130 °C.
shows how the over-temperature protection intervention.
Figure 12.
Over-temperature protection
13/20
Application information L6935
L6935 is the best choice in smart linear regulator applications, due to its own small size, high power delivered and high regulation accuracy. Furthermore thermal shut-down and
OCP guarantee the highest reliability for each application.
V
IN
can be separated by V
BIAS
: in this way the device can regulate the output voltage even if
V
IN
< V
BIAS
, resulting in a better performance. In fact, the power dissipated decreases as
V
IN
get lower, according to the relationship P
DISS
= (V
IN
- V
OUT
) x I
OUT
.
The choice of the input capacitor value depends on the several factor such as load transient requirements, input source (battery or DC/DC converter) and its distance from the input capacitor. Generally speaking, a capacitor with the lowest ESR possible should be chosen: a value within the range [10
µF; 100 µF] can be sufficient in many cases.
The choice of the output capacitor value basically depends on the load transient requirement. Output capacitor must be sized according to the dynamic requests of the load.
A too small capacitor may exhibit huge voltage drop after a load transient is applied: a value greater than 10
µF should be used.
In order to guarantee a good reliability, at least X5R type should be used as I/O capacitors.
Different kinds of input/output capacitors can be used:
shows a few tested examples.
Table 6.
Input/output capacitor selection guide
Manufacturer
Murata - GRM31CR61ExxxK
Panasonic - ECJ3YB1AxxxM
(1)
Type
MLCC, SMD1206, X5R
MLCC, SMD1206, X5R
I/O cap. value Rated voltage
10...100
µF
10...100
µF
6.3 - 25 V
10 - 25 V
Panasonic - EEFFD0HxxxR
SPCap - SMD7343
28 m
Ω ESR
10...100
µF
Sanyo - 8TPE100MPC2
POSCAP, SMD6032
25 m
Ω ESR
10...100
µF
TDK - C3216X5R0JxxxMT MLCC, SMD1210, X5R 10...100
µF
1. xxx in the part numbers stands for 106 (10
µF), 226 (22 µF)... 105 (100 µF)
4 - 8 V
6.3 - 25 V
6.3 V
14/20
Application information
6.2
L6935
VIN, VBIAS and sequencing
Different configurations for VIN and VBIAS are possibleand the power sequencing must consider the different timings in which the power suppliesbecomes available. In order to properly drive the device internal logic, it is reccomendedto control the sequence between
EN signal and the VIN / VBIAS application: the device need to result being disabled when
VBIAS crosses the UVLO threshols. Furthermore, in case of VIN <> VBIAS, the EN signal needs to be driven by the last-coming between the two supplies.
It is reccomended to drive the EN pin with a resistor divider connected as reported into
and
Figure 13.
Recommended circuit for VBIAS = VIN
VIN VOUT = 0.5V to 3.0V
C
IN
R
EH
VIN
EN
SS
VBIAS
VOUT
L6935
PGOOD
GND PAD ADJ
R
1
R
PG
C
OUT
PGOOD
EN
(OpenDrain Toggle **)
R
EL
C
SS
R
2
** Drive EN with external Open-Drain Signal.
Figure 14.
Reccomended circuit for VBIAS
≠
VIN
VBIAS
VIN (< VBIAS)
C
IN
EN
(OpenDrain Toggle **)
VIN
EN
SS
VBIAS
VOUT
L6935
PGOOD
GND PAD ADJ
R
1
R
EL
C
SS
R
2
VOUT = 0.5V to 3.0V
R
PG
C
OUT
PGOOD
* EN Divider (R
EH
) needs to be connected to the Last-Coming rail between VCC and VIN.
** Drive EN with external Open-Drain Signal.
15/20
Demonstration board description L6935
and
show the schematic and the layout of the demonstration board
designed for L6935. V
IN
and V
BIAS
may be different and, in this case, R4 must not be mounted. C3 defines the Soft-Start timer, according to the relationship described in the
The value of the output divider R
1
/ R
2
have to be designed in order to program the desired
V
OUT
value, according to the following equation:
V
OUT
=
0.5
⋅
⎛
⎝
1
+
R
-------
R
2
⎠
⎞
Figure 15.
Demonstration board schematic
V
BIAS
PGOOD
R
4
C
2
R
5
V
IN
EN
C
4
C
1
6
VBIAS
L6935
16,17,18
VOUT
R
3
SS GND PAD
C
3
20 2
ADJ
C
6
R
1
R
2
C
5
V
OUT
GND
Figure 16.
Demonstration board layout
16/20
Demonstration board description L6935
Different values for R
1
are available in order to program the value of V
OUT
(R
2
= 10 k
Ω)
V
OUT
= 0.50 V
DC
@ R
1
= 0
Ω
V
OUT
= 0.75 V
DC
@ R
1
= 5 k
Ω
V
OUT
= 1.00 V
DC
@ R
1
= 10 k
Ω
V
OUT
= 1.25 V
DC
@ R
1
= 15 k
Ω
V
OUT
= 1.50 V
DC
@ R
1
= 20 k
Ω
V
OUT
= 3.00 V
DC
@ R
1
= 50 k
Ω
Table 7.
L6935 demonstration board bill of material
Reference Description
C1, C2, c3
C4
C5
C6
R1
R2
R3, R5
R4
Chip capacitor 100 nF - 6.3 V - X5R
Murata chip capacitor (GRM31CR60J226K) 1206, X5R, 6.3-25V, 22
µF
Murata chip capacitor (GRM31CR61E106K) 1206, X5R, 6.3-25V, 10
µF
Not mounted
Chip resistor 15 k
Ω
+/-0.1% - 1/16 W
Chip resistor 10 k
Ω
+/-0.1% - 1/16 W
Chip resistor 10 k
Ω
+/-5% - 1/16 W
Chip resistor 0
Ω
17/20
VFQFPN20 mechanical data and package dimensions
8
L6935
VFQFPN20 mechanical data and package dimensions
In order to meet environmental requirements, ST offers these devices in ECOPACK
® packages. These packages have a lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
.
Figure 17.
VFQFPN20 mechanical data and package dimensions
REF.
DIMENSIONS mm mils
MIN.
TYP. MAX. MIN.
TYP.
MAX.
A 0.80
0.90
1.00
31.496 35.433 39.370
PACKAGE AND
PACKING INFORMATION
A1
A2
A3 b
0.02
0.05
0.787 1.969
0.65
0.25
1.00
25.591 39.370
9.843
0.18
0.23
0.30
7.087 9.055 11.811
3.85
4.00
4.15
151.57 157.48 163.39
D
D2
E
E2 e
L ddd
2.70
2.80
2.90
106.30 110.24 114.17
3.85
4.00
4.15
151.57 157.48 163.39
2.70
2.80
2.90
106.30 110.24 114.17
0.45
0.3
0.50
0.4
0.55
17.717 19.685 21.654
0.5
11.811 15.748 19.685
0.08
3.150
Very Fine Quad Flat
Package No lead
Weight: not available
VFQFPN20 (4x4x1.00mm)
18/20
Revision history
Table 8.
Date
Document revision history
Revision
20-May-2008 1 Initial release
Changes
L6935
19/20
L6935
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