100Gb/s QSFP28 LR4 (Ethernet) Optical Transceiver TR

TR- FC13R-N00 Rev1.1

100Gb/s QSFP28 LR4 (Ethernet) Optical Transceiver

TR-FC13R-N00

Product Specification

Features



Hot pluggable QSFP28 MSA form factor



Compliant to IEEE 802.3ba 100GBASE-LR4



Supports 103.1Gb/s aggregate bit rate



Up to 10km reach for G.652 SMF



Single +3.3V power supply



Operating case temperature: 0~70 o

C



Transmitter: cooled 4x25Gb/s LAN WDM DFB

TOSA (1295.56, 1300.05, 1304.58, 1309.14nm)



Receiver: 4x25Gb/s PIN ROSA



4x25G electrical interface (OIF CEI-28G-VSR)



Maximum power consumption 4.0W



Duplex LC receptacle



RoHS-6 compliant

Module picture shown above is that of InnoLight standard part and is for reference.

Applications



100GBASE-LR4 Ethernet Links



Infiniband QDR and DDR interconnects



Datacenter and Enterprise networking

Part Number Ordering Information

TR-FC13R-N00 QSFP28 LR4 (Ethernet) 10km optical transceiver with full real-time digital diagnostic monitoring and pull tab

Page 1

TR- FC13R-N00 Rev1.1

1. General Description

This product is a 100Gb/s transceiver module designed for optical communication applications compliant to 100GBASE-LR4 of the IEEE 802.3ba standard. The module converts 4 input channels of

25Gb/s electrical data to 4 channels of LAN WDM optical signals and then multiplexes them into a single channel for 100Gb/s optical transmission. Reversely on the receiver side, the module demultiplexes a 100Gb/s optical input into 4 channels of LAN WDM optical signals and then converts them to 4 output channels of electrical data.

The central wavelengths of the 4 LAN WDM channels are 1295.56, 1300.05, 1304.58 and 1309.14 nm as members of the LAN WDM wavelength grid defined in IEEE 802.3ba. The high performance cooled LAN WDM DFB transmitters and high sensitivity PIN receivers provide superior performance for 100Gigabit Ethernet applications up to 10km links and compliant to optical interface with

100GBASE-LR4 requirements specified in IEEE 802.3ba Clause 88.

The product is designed with form factor, optical/electrical connection and digital diagnostic interface according to the QSFP+ Multi-Source Agreement (MSA). It has been designed to meet the harshest external operating conditions including temperature, humidity and EMI interference.

2. Functional Description

The transceiver module receives 4 channels of 25Gb/s electrical data, which are processed by a 4channel Clock and Data Recovery (CDR) IC that reshapes and reduces the jitter of each electrical signal. Subsequently, DFB laser driver IC converts each one of the 4 channels of electrical signals to an optical signal that is transmitted from one of the 4 cooled DFB lasers which are packaged in the

Transmitter Optical Sub-Assembly (TOSA). Each laser launches the optical signal in specific wavelength specified in IEEE 802.3ba 100GBASE-LR4 requirements. These 4-lane optical signals will be optically multiplexed into a single fiber by a 4-to-1 optical WDM MUX. The optical output power of each channel is maintained constant by an automatic power control (APC) circuit. The transmitter output can be turned off by TX_DIS hardware signal and/or 2-wire serial interface.

The receiver receives 4-lane LAN WDM optical signals. The optical signals are de-multiplexed by a

1-to-4 optical DEMUX and each of the resulting 4 channels of optical signals is fed into one of the 4 receivers that are packaged into the Receiver Optical Sub-Assembly (ROSA). Each receiver converts the optical signal to an electrical signal. The regenerated electrical signals are retimed and de-jittered and amplified by the RX portion of the 4-channel CDR. The retimed 4-lane output electrical signals are compliant with IEEE CAUI-4 interface requirements. In addition, each received optical signal is monitored by the DOM section. The monitored value is reported through the 2-wire serial interface. If one or more received optical signal is weaker than the threshold level, RX_LOS hardware alarm will be triggered.

A single +3.3V power supply is required to power up this product. Both power supply pins VccTx and

Page 2

TR- FC13R-N00 Rev1.1

VccRx are internally connected and should be applied concurrently. As per MSA specifications the module offers 7 low speed hardware control pins (including the 2-wire serial interface): ModSelL,

SCL, SDA, ResetL, LPMode, ModPrsL and IntL.

Module Select (ModSelL) is an input pin. When held low by the host, this product responds to 2-wire serial communication commands. The ModSelL allows the use of this product on a single 2-wire interface bus – individual ModSelL lines must be used.

Serial Clock (SCL) and Serial Data (SDA) are required for the 2-wire serial bus communication interface and enable the host to access the QSFP28 memory map.

The ResetL pin enables a complete reset, returning the settings to their default state, when a low level on the ResetL pin is held for longer than the minimum pulse length. During the execution of a reset the host shall disregard all status bits until it indicates a completion of the reset interrupt. The product indicates this by posting an IntL (Interrupt) signal with the Data_Not_Ready bit negated in the memory map. Note that on power up (including hot insertion) the module should post this completion of reset interrupt without requiring a reset.

Low Power Mode (LPMode) pin is used to set the maximum power consumption for the product in order to protect hosts that are not capable of cooling higher power modules, should such modules be accidentally inserted.

Module Present (ModPrsL) is a signal local to the host board which, in the absence of a product, is normally pulled up to the host Vcc. When the product is inserted into the connector, it completes the path to ground through a resistor on the host board and asserts the signal. ModPrsL then indicates its present by setting ModPrsL to a “Low” state.

Interrupt (IntL) is an output pin. “Low” indicates a possible operational fault or a status critical to the host system. The host identifies the source of the interrupt using the 2-wire serial interface. The IntL pin is an open collector output and must be pulled to the Host Vcc voltage on the Host board.

Page 3

3. Transceiver Block Diagram

TR- FC13R-N00 Rev1.1

Figure 1. QSFP28 LR4 (Ethernet) Transceiver Block Diagram

4. Pin Assignment and Description

Figure 2. MSA compliant Connector

Page 4

TR- FC13R-N00 Rev1.1

Pin Definition

PIN Logic

1

2 CML-I

3 CML-I

4

5 CML-I

6 CML-I

7

8

9

10

LVTLL-I

LVTLL-I

Symbol

GND

Tx2n

Tx2p

GND

Tx4n

Tx4p

GND

ModSelL

ResetL

VccRx

11 LVCMOS-I/O SCL

12 LVCMOS-I/O SDA

13

14 CML-O

15 CML-O

16

GND

Rx3p

Rx3n

GND

17 CML-O

18 CML-O

19

20

Rx1p

Rx1n

GND

GND

21 CML-O

22 CML-O

23

24 CML-O

25 CML-O

26

27 LVTTL-O

28 LVTTL-O

29

30

31 LVTTL-I

Rx2n

Rx2p

GND

Rx4n

Rx4p

GND

ModPrsL

IntL

VccTx

Vcc1

LPMode

Name/Description

Ground

Transmitter Inverted Data Input

Transmitter Non-Inverted Data output

Ground

Transmitter Inverted Data Input

Transmitter Non-Inverted Data output

Ground

Module Select

Module Reset

+3.3V Power Supply Receiver

2-Wire Serial Interface Clock

2-Wire Serial Interface Data

Ground

Receiver Non-Inverted Data Output

Receiver Inverted Data Output

Ground

Receiver Non-Inverted Data Output

Receiver Inverted Data Output

Ground

Ground

Receiver Inverted Data Output

Receiver Non-Inverted Data Output

Ground

Receiver Inverted Data Output

Receiver Non-Inverted Data Output

Ground

Module Present

Interrupt

+3.3 V Power Supply transmitter

+3.3 V Power Supply

Low Power Mode

Notes

1

1

1

2

1

1

1

2

2

1

1

1

Page 5

TR- FC13R-N00 Rev1.1

32

33 CML-I

34 CML-I

35

36 CML-I

37 CML-I

38

GND

Tx3p

Tx3n

GND

Tx1p

Tx1n

GND

Ground

Transmitter Non-Inverted Data Input

Transmitter Inverted Data Output

Ground

Transmitter Non-Inverted Data Input

Transmitter Inverted Data Output

Ground

1

1

1

Notes:

1.

GND is the symbol for signal and supply (power) common for the QSFP28 module. All are common within the module and all module voltages are referenced to this potential unless otherwise noted. Connect these directly to the host board signal common ground plane.

2.

VccRx, Vcc1 and VccTx are the receiving and transmission power suppliers and shall be applied concurrently. Recommended host board power supply filtering is shown in Figure 3 below. Vcc

Rx, Vcc1 and Vcc Tx may be internally connected within the module in any combination. The connector pins are each rated for a maximum current of 1000mA.

5. Recommended Power Supply Filter

Figure 3. Recommended Power Supply Filter

Page 6

TR- FC13R-N00 Rev1.1

6. Absolute Maximum Ratings

It has to be noted that the operation in excess of any individual absolute maximum ratings might cause permanent damage to this module.

Parameter

Storage Temperature

Operating Case Temperature

Power Supply Voltage

Relative Humidity (non-condensation)

Damage Threshold, each Lane

Symbol

T

S

T

OP

V

CC

RH

TH d

Min

-40

0

-0.5

0

5.5

Max

85

70

3.6

85

Units Notes

degC degC

V

% dBm

7. Recommended Operating Conditions and Power Supply Requirements

Typical Parameter

Operating Case Temperature

Power Supply Voltage

Data Rate, each Lane

Data Rate Accuracy

Control Input Voltage High

Control Input Voltage Low

Link Distance with G.652

Symbol

T

OP

V

CC

D

Min

0

3.135

-100

2

0

0.002

3.3

25.78125

Max

70

3.465

100

Vcc

0.8

10

Units

degC

V

Gb/s ppm

V

V km

8. Electrical Characteristics

The following electrical characteristics are defined over the Recommended Operating Environment unless otherwise specified.

Parameter

Test

Point

Min Typical Max Units Notes

Power Consumption 4.0 W

Supply Current Icc

Transmitter (each Lane)

1.21 A

Overload Differential Voltage pk-pk

TP1a

900 mV

Common Mode Voltage (Vcm)

TP1

-350 2850 mV 1

Differential Termination

Resistance Mismatch

Differential Return Loss

(SDD11)

TP1

TP1

10

See CEI-

28G-VSR

% dB

At 1MHz

Page 7

TR- FC13R-N00 Rev1.1

Common Mode to Differential conversion and Differential to

Common Mode conversion

(SDC11, SCD11)

TP1

Equation

13-19

See CEI-

28G-VSR

Equation

13-20 dB

Stressed Input Test

Differential Voltage, pk-pk

Common Mode Voltage (Vcm)

Common Mode Noise, RMS

Differential Termination

Resistance Mismatch

TP1a

See CEI-

28G-VSR

Section

13.3.11.2.1

TP4

Receiver (each Lane)

TP4

TP4

TP4

-350

900

2850

17.5

10 mV mV mV

%

Differential Return Loss

(SDD22)

TP4

See CEI-

28G-VSR

Equation

13-19 dB

Common Mode to Differential conversion and Differential to

Common Mode conversion

(SDC22, SCD22)

TP4

See CEI-

28G-VSR

Equation

13-21 dB

Common Mode Return Loss

TP4

-2 dB

(SCC22)

Transition Time, 20 to 80%

TP4

9.5 ps

Vertical Eye Closure (VEC)

Eye Width at 10

-15

probability

TP4

5.5

TP4

0.57

(EW15)

Eye Height at 10

-15

probability

TP4

228

(EH15)

Notes:

1.

Vcm is generated by the host. Specification includes effects of ground offset voltage.

2.

From 250MHz to 30GHz.

dB

UI mV

1

At 1MHz

2

Page 8

TR- FC13R-N00 Rev1.1

9. Optical Characteristics

Parameter

Lane Wavelength

Side Mode Suppression Ratio

Total Average Launch Power

Average Launch Power, each Lane

OMA, each Lane

Launch Power in OMA minus

Transmitter and Dispersion Penalty

(TDP), each Lane

TDP, each Lane

Extinction Ratio

Difference in Launch Power between any Two Lanes (OMA)

RIN

20

OMA

Optical Return Loss Tolerance

Transmitter Reflectance

Average Launch Power OFF

Transmitter, each Lane

Eye Mask{X1, X2, X3, Y1, Y2, Y3}

Receiver

Damage Threshold, each Lane

Average Receive Power, each Lane

QSFP28 100GBASE-LR4

Symbol

L0

L1

L2

L3

Min

1294.53 1295.56 1296.59

1299.02

Typical

1300.05

Max

1301.09

1303.54 1304.58 1305.63

1308.09 1309.14 1310.19

Transmitter

SMSR 30

P

T

10.5

P

P

AVG

OMA

TDP

ER

Ptx,diff

RIN

TOL

R

T

TH d

Poff

-4.3

-1.3

-2.3

4

5.5

-10.6

4.5

4.5

2.2

5

-130

20

-12

-30

{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}

4.5

4.5

Units Notes

nm nm nm nm dB dBm dBm dBm dBm dB dB dB dB/Hz dB dB dBm dBm dBm dBm

1

2

3

Receive Power (OMA), each Lane

Receiver Sensitivity (OMA), each

Lane

Stressed Receiver Sensitivity

(OMA), each Lane

SEN -8.6

-6.8

dBm dBm 4

Page 9

TR- FC13R-N00 Rev1.1

Receiver Reflectance

R

R

-26

Difference in Receive Power

Prx,diff 5.5 between any Two Lanes (OMA)

LOS Assert

LOSA -30

LOS Deassert

LOSD -13

LOS Hysteresis

LOSH 0.5

Receiver Electrical 3 dB upper

Fc 31

Cutoff Frequency, each Lane

Conditions of Stress Receiver Sensitivity Test

(Note 5)

Vertical Eye Closure Penalty, each

Lane

1.8

Stressed Eye J2 Jitter, each Lane

Stressed Eye J9 Jitter, each Lane

0.3

0.47 dB dB dBm dBm dB

GHz dB

UI

UI

Notes:

1.

Even if the TDP < 1 dB, the OMA min must exceed the minimum value specified here.

2.

Hit ratio 5x10

-5

.

3.

The receiver shall be able to tolerate, without damage, continuous exposure to a modulated optical input signal having this power level on one lane. The receiver does not have to operate correctly at this input power.

4.

Measured with conformance test signal at receiver input for BER = 1x10

-12

.

5.

Vertical eye closure penalty, stressed eye J2 jitter, and stressed eye J9 jitter are test conditions for measuring stressed receiver sensitivity. They are not characteristics of the receiver.

Page 10

TR- FC13R-N00 Rev1.1

10. Digital Diagnostic Functions

The following digital diagnostic characteristics are defined over the normal operating conditions unless otherwise specified.

Parameter

Temperature monitor absolute error

Symbol

DMI_Temp

Min

-3

Max

+3

Units

degC

Notes

Over operating temperature range

Supply voltage monitor absolute error

DMI _VCC -0.1

0.1 V

Over full operating range

Channel RX power monitor absolute error

DMI_RX_Ch -2 2 dB 1

Channel Bias current monitor

Channel TX power monitor absolute error

DMI_Ibias_Ch

DMI_TX_Ch

-10%

-2

10%

2 mA dB 1

Notes:

1. Due to measurement accuracy of different single mode fibers, there could be an additional +/-1 dB fluctuation, or a +/- 3 dB total accuracy.

11. Mechanical Dimensions

Figure 4. Mechanical Outline

Page 11

TR- FC13R-N00 Rev1.1

12. ESD

This transceiver is specified as ESD threshold 1KV for high speed data pins and 2KV for all others electrical input pins, tested per MIL-STD-883, Method 3015.4 /JESD22-A114-A (HBM). However, normal ESD precautions are still required during the handling of this module. This transceiver is shipped in ESD protective packaging. It should be removed from the packaging and handled only in an ESD protected environment.

13. Laser Safety

This is a Class 1 Laser Product according to EN 60825-1:2014. This product complies with 21 CFR

1040.10 and 1040.11 except for deviations pursuant to Laser Notice No. 50, dated (June 24, 2007).

Caution: Use of controls or adjustments or performance of procedures other than those specified herein may result in hazardous radiation exposure.

Contact Information

Vitex LLC

105 Challenger Road, Suite 401

Ridgefield Park, NJ 07760

USA

Ph: 201-296-0145

Email: [email protected]

www.vitextech.com

December 26, 2016 InnoLight Technology Confidential Page 12