NXP MSC8156 High-Performance Six-Core DSP Reference Manual

MSC8156 Reference Manual
Six Core Digital Signal Processor
MSC8156RM
Rev 2, June 2011
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MSC8156RM
Rev. 2
6/2011
Overview
1
SC3850 Core Overview
2
External Signals
3
Chip-Level Arbitration and Switching System (CLASS)
4
Reset
5
Boot Program
6
Clocks
7
General Configuration Registers
8
Memory Map
9
MSC8154 SC3850 DSP Subsystem
10
Internal Memory Subsystem
11
DDR-SDRAM Controller
12
Interrupt Handling
13
Direct Memory Access (DMA) Controller
14
High Speed Serial Interface (HSSI)
15
Serial RapidIO Controller
16
PCI Express Controller
17
QUICC Engine Subsystem
18
TDM Interface
19
UART
20
Timers
21
GPIO
22
Hardware Semaphores
23
I2C
24
Debugging, Profiling, and Performance Monitoring
25
Multi Accelerator Platform Engine, Baseband (MAPLE-B)
26
1
Overview
2
SC3850 Core Overview
3
External Signals
4
Chip-Level Arbitration and Switching System (CLASS)
5
Reset
6
Boot Program
7
Clocks
8
General Configuration Registers
9
Memory Map
10
MSC8154 SC3850 DSP Subsystem
11
Internal Memory Subsystem
12
DDR-SDRAM Controller
13
Interrupt Handling
14
Direct Memory Access (DMA) Controller
15
High Speed Serial Interface (HSSI)
16
Serial RapidIO Controller
17
PCI Express Controller
18
QUICC Engine Subsystem
19
TDM Interface
20
UART
21
Timers
22
GPIO
23
Hardware Semaphores
24
I2C
25
Debugging, Profiling, and Performance Monitoring
26
Multi Accelerator Platform Engine, Baseband (MAPLE-B)
Contents
About This Book
Before Using This Manual—Important Note . . . . . . . . . . . . . . . . . . . . . . . . . . . xlii
Audience and Helpful Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlii
Notational Conventions and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xliii
Conventions for Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xliv
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xliv
Other MSC8156 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlvii
Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlvii
Document Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xlviii
1
Overview
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.11.1
1.11.1.1
1.11.1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
StarCore SC3850 DSP Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
StarCore SC3850 DSP Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
L1 Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
L1 Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
L2 Unified Cache/M2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Debug and Profiling Unit (DPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Extended Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
MAPLE-B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Chip-Level Arbitration and Switching System (CLASS) . . . . . . . . . . . . . . . . . 1-20
M3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
DDR Controllers (DDRC1 and DDRC2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
High Speed System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Serial RapidIO Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Serial RapidIO and Host Interactions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-24
RapidIO Messaging Unit (RMU) Operation . . . . . . . . . . . . . . . . . . . . . . . . 1-25
MSC8156 Reference Manual, Rev. 2
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Contents
1.11.2
1.11.3
1.11.4
1.11.5
1.11.6
1.12
1.12.1
1.12.2
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.23.1
1.23.2
1.24
1.24.1
1.24.2
1.24.3
1.24.4
1.24.5
1.24.6
1.24.7
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCN-DMA Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCN Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRIO Port Controller Modules (SRIOn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SerDes PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QUICC Engine Subsystem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Semaphores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Virtual Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Developer Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Application Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 1: 3G-LTE Basic System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 2: 3G-LTE System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 3: 3G-LTE System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 4: TD-SCDMA System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 5: WiMAX Basic System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 6: WiMAX System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Use Case 7: WCDMA Basic System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
SC3850 Core Overview
2.1
2.2
Core Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
StarCore SC3850 Core Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
3
External Signals
3.1
3.2
3.3
3.4
3.5
1-26
1-27
1-27
1-27
1-27
1-28
1-29
1-30
1-30
1-31
1-31
1-31
1-31
1-32
1-32
1-32
1-32
1-33
1-34
1-34
1-35
1-35
1-35
1-36
1-36
1-37
1-37
1-38
1-38
Power Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Reset and Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Memory Controller 1 and 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
SerDes Multiplexed Signals for the Serial RapidIO, PCI Express, and
SGMII Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
MSC8156 Reference Manual, Rev. 2
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Contents
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
TDM and Ethernet Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) Signal Summary . . . . . . . . . . . . . . . . . . . . . .
GPIO/Maskable Interrupt Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External DMA Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Interrupt Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCE Event and JTAG Test Access Port Signals . . . . . . . . . . . . . . . . . . . . . . . .
3-16
3-20
3-20
3-25
3-26
3-26
3-27
3-28
3-29
4
Chip-Level Arbitration and Switching System (CLASS)
4.1
4.2
4.2.1
4.2.2
4.2.2.1
4.2.2.1.1
4.2.2.1.2
4.2.2.1.3
4.2.2.1.4
4.2.2.2
4.2.3
4.2.4
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.6
4.6.1
4.6.2
4.7
4.8
4.8.1
4.8.2
4.8.3
4.8.4
4.8.5
4.8.6
CLASS Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Expander Module and Transaction Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Multiplexer and Arbiter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
CLASS Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
Weighted Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Late Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Priority Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Auto Priority Upgrade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
CLASS Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Normalizer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CLASS Control Interface (CCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
MSC8156 Initiator CLASS Access Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
CLASS Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
CLASS Debug Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Watch Point Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Event Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Debug and Profiling Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
CLASS Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Hard Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
CLASS Priority Mapping Registers (C0PMRx) . . . . . . . . . . . . . . . . . . . . . . . 4-16
CLASS Priority Auto Upgrade Value Registers (C0PAVRx) . . . . . . . . . . . . 4-18
CLASS Priority Auto Upgrade Control Registers (C0PACRx) . . . . . . . . . . . 4-19
CLASS Error Address Registers (C0EARx) . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
CLASS Error Extended Address Registers (C0EEARx) . . . . . . . . . . . . . . . . 4-21
CLASS Initiator Profiling Configuration Registers (C0IPCRx) . . . . . . . . . . 4-23
MSC8156 Reference Manual, Rev. 2
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Contents
4.8.7
4.8.8
4.8.9
4.8.10
4.8.11
4.8.12
4.8.13
4.8.14
4.8.15
4.8.16
4.8.17
4.8.18
4.8.19
4.8.20
4.8.21
4.8.22
4.8.23
4.8.24
4.8.25
4.8.26
CLASS Initiator Watch Point Control Registers (C0IWPCRx) . . . . . . . . . . .
CLASS Arbitration Weight Registers (C0AWRx) . . . . . . . . . . . . . . . . . . . . .
CLASS0 Start Address Decoder x (C0SADx) . . . . . . . . . . . . . . . . . . . . . . . .
CLASS End Address Decoder x (C0EADx). . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS Attributes Decoder x (C0ATDx) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS IRQ Status Register (C0ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS IRQ Enable Register (C0IER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS Target Profiling Configuration Register (C0TPCR) . . . . . . . . . . . . .
CLASS Profiling Control Register (C0PCR) . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS Watch Point Control Registers (C0WPCR) . . . . . . . . . . . . . . . . . . .
CLASS Watch Point Access Configuration Register (C0WPACR) . . . . . . .
CLASS Watch Point Extended Access Configuration Register
(C0WPEACR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CLASS Watch Point Address Mask Registers (C0WPAMR) . . . . . . . . . . . .
CLASS Profiling Time-Out Registers (C0PTOR) . . . . . . . . . . . . . . . . . . . . .
CLASS Target Watch Point Control Registers (C0TWPCR) . . . . . . . . . . . .
CLASS Profiling IRQ Status Register (C0PISR) . . . . . . . . . . . . . . . . . . . . . .
CLASS Profiling IRQ Enable Register (C0PIER) . . . . . . . . . . . . . . . . . . . . .
CLASS Profiling Reference Counter Register (C0PRCR) . . . . . . . . . . . . . . .
CLASS Profiling General Counter Registers (C0PGCRx) . . . . . . . . . . . . . . .
CLASS Arbitration Control Register (C0ACR) . . . . . . . . . . . . . . . . . . . . . . .
4-25
4-26
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-42
4-43
4-44
5
Reset
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.5.1
5.2.5.1.1
5.2.5.1.2
5.2.5.1.3
5.2.5.1.4
Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Reset Actions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Power-On Reset Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Detailed Power-On Reset Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
HRESET Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
SRESET Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Reset Configuration Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Reset Configuration Words Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
Reset Configuration Input Signal Selection and Reset Sequence Duration . . . 5-9
Reset Configuration Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Loading The Reset Configuration Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Loading From an I2C EEPROM (RCW_SRC[0–2] = 001 or 010) . . . . . . . 5-10
Using The Boot Sequencer For Reset Configuration . . . . . . . . . . . . . . . . . . 5-10
EEPROM Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
EEPROM Data Format In Reset Configuration Mode. . . . . . . . . . . . . . . . . 5-10
Single Device Loading From I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . 5-11
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5.2.5.1.5
5.2.5.2
5.2.5.3
5.2.5.3.1
5.2.5.3.2
5.2.5.4
5.2.5.4.1
5.2.5.4.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Loading Multiple Devices From a Single I2C EEPROM. . . . . . . . . . . . . . .
Loading Multiplexed RCW from External Pins (RCW_SRC[0–2] = 000) .
Loading Reduced RCW From External Pins (RCW_SRC[0–2] = 011) . . .
Reduced External Reset Configuration Word Low Field Values . . . . . . . .
Reduced External Reset Configuration Word High Field Values . . . . . . . .
Default Reset Configuration Words (RCW_SRC[0–2] = 100 or 101). . . . .
Hard Coded Reset Configuration Word Low Field Values . . . . . . . . . . . . .
Hard Coded Reset Configuration Word High Field Values . . . . . . . . . . . . .
Reset Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Configuration Word Low Register (RCWLR) . . . . . . . . . . . . . . . . . . .
Reset Configuration Word High Register (RCWHR). . . . . . . . . . . . . . . . . . .
Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Protection Register (RPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Control Register (RCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Control Enable Register (RCER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Boot Program
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.2.1
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.3
6.2.3.1
6.2.3.2
6.2.3.3
6.2.4
6.2.4.1
6.2.4.2
6.2.5
6.3
6.4
6.5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Private Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Shared Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3
Patch Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Multi Device Support for the I2C Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4
Example Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
I2C EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9
Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-13
DHCP Client. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
TFTP Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Boot File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Simple Ethernet Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Simple Ethernet Boot Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Simple Ethernet Boot Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19
Boot File Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Serial RapidIO Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Serial RapidIO Without I2C Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Serial RapidIO Interface with I2C Support . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Jump to User Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
System after Boot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Boot Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
5-11
5-13
5-14
5-14
5-15
5-15
5-15
5-16
5-17
5-17
5-19
5-22
5-24
5-25
5-26
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7
Clocks
7.1
7.2
7.2.1
7.2.2
Clock Generation Components and Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock Control Register (SCCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock General Purpose Register 0 (CLK_GPR0) . . . . . . . . . . . . . . . . . . . . . . .
8
General Configuration Registers
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.2.11
8.2.12
8.2.13
8.2.14
8.2.15
8.2.16
8.2.17
8.2.18
8.2.19
8.2.20
8.2.21
8.2.22
8.2.23
8.2.24
8.2.25
8.2.26
8.2.27
8.2.28
8.2.29
8.2.30
8.2.31
8.2.32
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Detailed Register Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
General Configuration Register 1 (GCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
General Configuration Register 2 (GCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3
General Status Register 1 (GSR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
High Speed Serial Interface Status Register (HSSI_SR) . . . . . . . . . . . . . . . . . 8-7
DDR General Control Register (DDR_GCR) . . . . . . . . . . . . . . . . . . . . . . . . . 8-10
High Speed Serial Interface Control Register 1 (HSSI_CR1) . . . . . . . . . . . . 8-12
High Speed Serial Interface Control Register 2 (HSSI_CR2) . . . . . . . . . . . . 8-15
QUICC Engine Control Register (QECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
GPIO Pull-Up Enable Register (GPUER). . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
GPIO Input Enable Register (GIER). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18
System Part and Revision ID Register (SPRIDR) . . . . . . . . . . . . . . . . . . . . . 8-19
General Control Register 4 (GCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20
General Control Register 5 (GCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22
General Status Register 2 (GSR2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Core Subsystem Slave Port Priority Control Register (TSPPCR) . . . . . . . . . 8-26
QUICC Engine First External Request Multiplex Register (CPCE1R) . . . . . 8-27
QUICC Engine Second External Request Multiplex Register (CPCE2R) . . . 8-28
QUICC Engine Third External Request Multiplex Register (CPCE3R) . . . . 8-29
QUICC Engine Fourth External Request Multiplex Register (CPCE4R). . . . 8-30
General Control Register 10 (GCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-31
General Interrupt Register 1 (GIR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-32
General Interrupt Enable Register 1 (GIER1_x). . . . . . . . . . . . . . . . . . . . . . . 8-35
General Interrupt Register 3 (GIR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-37
General Interrupt Enable Register 3 for Cores 0–3 (GIER3_x) . . . . . . . . . . . 8-39
General Interrupt Register 5 (GIR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-40
General Interrupt Enable Register 5 (GIER5_x). . . . . . . . . . . . . . . . . . . . . . . 8-42
General Control Register 11 (GCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-43
General Control Register 12 (GCR12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-44
DMA Request0 Control Register (GCR_DREQ0) . . . . . . . . . . . . . . . . . . . . . 8-46
DMA Request1 Control Register (GCR_DREQ1) . . . . . . . . . . . . . . . . . . . . . 8-50
DMA Done Control Register (GCR_DDONE) . . . . . . . . . . . . . . . . . . . . . . . 8-54
DDR1 General Configuration Register (DDR1_GCR). . . . . . . . . . . . . . . . . . 8-57
7-2
7-4
7-4
7-5
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8.2.33
8.2.34
DDR2 General Configuration Register (DDR2_GCR). . . . . . . . . . . . . . . . . . 8-58
Core Subsystem Slave Port General Configuration Register
(CORE_SLV_GCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-59
9
Memory Map
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.6
Shared Memory Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shared SC3850 DSP Core Subsystem M2/L2 Memories . . . . . . . . . . . . . . . . . .
SC3850 DSP Core Subsystem Internal Address Space . . . . . . . . . . . . . . . . . . . .
CCSR Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiators Views of the System Address Space . . . . . . . . . . . . . . . . . . . . . . . . . .
SC3850 (Data) View of the System Address Space . . . . . . . . . . . . . . . . . . . . .
Peripherals View of the System Address Space . . . . . . . . . . . . . . . . . . . . . . . .
Detailed System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
MSC8156 SC3850 DSP Subsystem
10.1
10.2
10.3
10.3.1
10.3.2
10.4
10.4.1
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.5
10.6
10.7
10.8
10.9
10.10
10.10.1
10.10.2
10.11
10.11.1
10.11.2
10.11.2.1
10.11.2.2
SC3850 DSP Core Subsystem Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2
SC3850 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3
Instruction Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4
Instruction Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Data Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Data Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Data Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
Write-Back Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Write-Through Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Data Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Write Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8
L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9
On-Chip Emulator and Debug and Profiling Unit . . . . . . . . . . . . . . . . . . . . . 10-10
Extended Programmable Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
QBus to MBus Interface Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
MBus to DMA Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11
Entering and Exiting Wait and Stop States Safely. . . . . . . . . . . . . . . . . . . . . . 10-12
Wait State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Stop State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12
Procedure for Entering DSP Subsystem Stop State Safely . . . . . . . . . . . . 10-12
Procedure for Exiting the Stop State Safely . . . . . . . . . . . . . . . . . . . . . . . . 10-13
9-1
9-2
9-3
9-4
9-5
9-5
9-6
9-6
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11
Internal Memory Subsystem
11.1
11.2
11.3
11.4
11.5
11.6
Memory Management Unit (MMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Instruction Channel (ICache and IFU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Data Channel and Write Queue (DCache) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5
L2 Unified Cache/M2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
M3 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Internal Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
12
DDR SDRAM Memory Controller
12.1
12.2
12.2.1
12.2.2
12.2.3
12.3
12.4
12.4.1
12.4.2
12.4.3
12.4.4
12.4.5
12.4.5.1
12.4.5.2
12.4.6
12.4.7
12.5
12.6
12.7
12.7.1
12.7.2
12.8
12.8.1
12.8.2
12.8.3
12.8.4
12.8.5
12.8.6
12.8.7
12.8.8
12.8.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3
DDR SDRAM Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7
DDR SDRAM Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-8
DDR SDRAM Address Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10
JEDEC Standard DDR SDRAM Interface Commands . . . . . . . . . . . . . . . . . . 12-15
DDR SDRAM Clocking and Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 12-20
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-24
DDR SDRAM Mode-Set Command Timing . . . . . . . . . . . . . . . . . . . . . . . . 12-25
DDR SDRAM Registered DIMM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-25
DDR SDRAM Write Timing Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . 12-26
DDR SDRAM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
DDR SDRAM Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-28
DDR SDRAM Refresh and Power-Saving Modes. . . . . . . . . . . . . . . . . . . 12-29
DDR Data Beat Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-31
Page Mode and Logical Bank Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
Error Checking and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-32
Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-35
Set-Up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-36
Programming Differences Between Memory Types. . . . . . . . . . . . . . . . . . . 12-40
DDR SDRAM Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
Memory Controller Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-44
Chip-Select Bounds (MnCSx_BNDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-46
Chip-Select x Configuration Register (MnCSx_CONFIG) . . . . . . . . . . . . . 12-47
Chip-Select x Configuration Register 2 (MnCSx_CONFIG_2) . . . . . . . . . . 12-49
DDR SDRAM Timing Configuration 3 (MnTIMING_CFG_3). . . . . . . . . . 12-50
DDR SDRAM Timing Configuration Register 0 (MnTIMING_CFG_0) . . 12-52
DDR SDRAM Timing Configuration Register 1 (MnTIMING_CFG_1) . . 12-55
DDR SDRAM Timing Configuration Register 2 (MnTIMING_CFG_2) . . 12-60
DDR SDRAM Control Configuration Register (MnDDR_SDRAM_CFG). 12-65
DDR SDRAM Control Configuration Register 2
(MnDDR_SDRAM_CFG_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-67
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12.8.10
12.8.11
12.8.12
12.8.13
12.8.14
12.8.15
12.8.16
12.8.17
12.8.18
12.8.19
12.8.20
12.8.21
12.8.22
12.8.23
12.8.24
12.8.25
12.8.26
12.8.27
12.8.28
12.8.29
12.8.30
12.8.31
12.8.32
12.8.33
12.8.34
12.8.35
12.8.36
12.8.37
12.8.38
12.8.39
12.8.40
12.8.41
DDR SDRAM Mode Configuration Register (MnDDR_SDRAM_MODE) 12-70
DDR SDRAM Mode Configuration 2 Register
(MnDDR_SDRAM_MODE_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-71
DDR SDRAM Mode Control Register (MnDDR_SDRAM_MD_CNTL). . 12-71
DDR SDRAM Interval Configuration Register
(MnDDR_SDRAM_INTERVAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-74
DDR SDRAM Data Initialization Register (MnDDR_DATA_INIT) . . . . . 12-75
DDR SDRAM Clock Control Configuration Register
(MnDDR_SDRAM_CLK_CNTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-75
DDR SDRAM Initialization Address Register (MnDDR_INIT_ADDR) . . 12-76
DDR Initialization Enable (MnDDR_INIT_EN) . . . . . . . . . . . . . . . . . . . . . 12-77
DDR SDRAM Timing Configuration 4 (MnTIMING_CFG_4). . . . . . . . . . 12-78
DDR SDRAM Timing Configuration 5 (MnTIMING_CFG_5). . . . . . . . . . 12-80
DDR ZQ Calibration Control (MnDDR_ZQ_CNTL) . . . . . . . . . . . . . . . . . 12-82
DDR Write Leveling Control (MnDDR_WRLVL_CNTL) . . . . . . . . . . . . . 12-84
DDR Write Leveling Control 2 (MnDDR_WRLVL_CNTL_2). . . . . . . . . . 12-87
DDR Write Leveling Control 3 (MnDDR_WRLVL_CNTL_3). . . . . . . . . . 12-90
DDR Pre-Drive Conditioning Control (MnDDR_PD_CNTL) . . . . . . . . . . . 12-93
DDR Self Refresh Counter (MnDDR_SR_CNTR) . . . . . . . . . . . . . . . . . . . 12-96
DDR SDRAM Register Control Words 1 (MnDDR_SDRAM_RCW_1) . . 12-97
DDR SDRAM Register Control Words 2 (MnDDR_SDRAM_RCW_2) . . 12-98
DDR Debug Status Register 1 (MnDDRDSR_1) . . . . . . . . . . . . . . . . . . . . . 12-99
DDR Debug Status Register 2 (MnDDRDSR_2) . . . . . . . . . . . . . . . . . . . . 12-100
DDR Control Driver Register 1 (MnDDRCDR_1). . . . . . . . . . . . . . . . . . . 12-100
DDR Control Driver Register 2 (MnDDRCDR_2). . . . . . . . . . . . . . . . . . . 12-104
DDR SDRAM IP Block Revision 1 Register (MnDDR_IP_REV1) . . . . . 12-105
DDR SDRAM IP Block Revision 2 Register (MnDDR_IP_REV2) . . . . . 12-105
DDR SDRAM Memory Data Path Error Injection Mask High Register
(MnDATA_ERR_INJECT_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106
DDR SDRAM Memory Data Path Error Injection Mask Low Register
(MnDATA_ERR_INJECT_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-106
DDR SDRAM Memory Data Path Error Injection Mask ECC Register
(MnERR_INJECT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-107
DDR SDRAM Memory Data Path Read Capture Data High Register
(MnCAPTURE_DATA_HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-108
DDR SDRAM Memory Data Path Read Capture Data Low Register
(MnCAPTURE_DATA_LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-108
DDR SDRAM Memory Data Path Read Capture ECC Register
(MnCAPTURE_ECC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-109
DDR SDRAM Memory Error Detect Register (MnERR_DETECT) . . . . . 12-109
DDR SDRAM Memory Error Disable Register (MnERR_DISABLE) . . . 12-110
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12.8.42
12.8.43
12.8.44
12.8.45
12.8.46
DDR SDRAM Memory Error Interrupt Enable Register
(MnERR_INT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAM Memory Error Attributes Capture Register
(MnCAPTURE_ATTRIBUTES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAM Memory Error Address Capture Register
(MnCAPTURE_ADDRESS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAM Single-Bit ECC Memory Error Management Register
(MnERR_SBE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Register 2 (MnDEBUG_2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12-112
12-113
12-114
12-114
12-115
13
Interrupt Handling
13.1
13.2
13.2.1
13.2.2
13.2.3
13.3
13.4
13.5
13.5.1
13.5.1.1
13.5.1.2
13.5.2
13.5.3
Global Interrupt Controller (GIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2
General Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Interrupt Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5
Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6
Core Interrupt Mesh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-22
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
Global Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-23
Virtual Interrupt Generation Register (VIGR) . . . . . . . . . . . . . . . . . . . . . . 13-23
Virtual Interrupt Status Register (VISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 13-24
General Interrupt Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
Programming Restrictions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-26
14
Direct Memory Access (DMA) Controller
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.2.7
14.2.8
14.2.9
14.2.10
14.2.11
14.3
14.3.1
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-2
One-Dimensional Simple Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
One-Dimensional Cyclic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5
One-Dimensional Chained Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
One-Dimensional Incremental Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-7
One-Dimensional Complex Buffers With Dual Cyclic Buffers . . . . . . . . . . . 14-8
Two-Dimensional Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-9
Three-Dimensional Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-11
Four-Dimensional Simple Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-12
Multi-Dimensional Chained Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-15
Two-Dimensional Cyclic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17
Three-Dimensional Cyclic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18
Arbitration Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
Round-Robin Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19
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14.3.2
14.3.2.1
14.3.2.2
14.3.2.3
14.4
14.4.1
14.4.2
14.5
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1
14.6.3.2
14.6.3.3
14.6.4
14.7
14.7.1
14.7.2
14.7.3
14.7.4
14.7.5
14.7.6
14.7.7
14.7.8
14.7.9
14.7.10
14.7.11
14.7.12
14.7.13
14.7.14
14.7.15
14.7.16
14.7.17
14.7.18
14.7.19
14.7.20
14.7.21
14.7.22
14.7.22.1
14.7.22.2
EDF Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Issuing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Source to the Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration and Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Request Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Done Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the DMA Peripheral Interface Block . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Buffer Descriptor Base Registers x (DMABDBRx). . . . . . . . . . . . . .
DMA Controller Channel Configuration Registers x (DMACHCRx) . . . . .
DMA Controller Global Configuration Register (DMAGCR) . . . . . . . . . . .
DMA Channel Enable Register (DMACHER) . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Disable Register (DMACHDR) . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Freeze Register (DMACHFR) . . . . . . . . . . . . . . . . . . . . . . .
DMA Channel Defrost Register (DMACHDFR).. . . . . . . . . . . . . . . . . . . . .
DMA Time-To-Dead Line Registers x (DMAEDFTDLx) . . . . . . . . . . . . . .
DMA EDF Control Register (DMAEDFCTRL). . . . . . . . . . . . . . . . . . . . . .
DMA EDF Mask Register (DMAEDFMR) . . . . . . . . . . . . . . . . . . . . . . . . .
DMA EDF Mask Update Register (DMAEDFMUR). . . . . . . . . . . . . . . . . .
DMA EDF Status Register (DMAEDFSTR) . . . . . . . . . . . . . . . . . . . . . . . .
DMA Mask Register (DMAMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Mask Update Register (DMAMUR). . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Status Register (DMASTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Error Register (DMAERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Debug Event Status Register (DMADESR) . . . . . . . . . . . . . . . . . . . .
DMA Local Profiling Configuration Register (DMALPCR) . . . . . . . . . . . .
DMA Round-Robin Priority Group Update Register (DMARRPGUR) . . .
DMA Channel Active Status Register (DMACHASTR) . . . . . . . . . . . . . . .
DMA Channel Freeze Status Register (DMACHFSTR) . . . . . . . . . . . . . . .
DMA Channel Buffer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Attributes (BD_ATTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Dimensional Buffer Attributes (BD_MD_ATTR) . . . . . . . . . . . . . .
14-20
14-21
14-21
14-22
14-22
14-22
14-22
14-23
14-23
14-23
14-24
14-25
14-25
14-25
14-25
14-26
14-27
14-28
14-29
14-31
14-31
14-32
14-33
14-33
14-34
14-35
14-35
14-36
14-38
14-38
14-39
14-40
14-41
14-43
14-43
14-44
14-45
14-45
14-45
14-49
14-52
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15
High Speed Serial Interface (HSSI) Subsystem
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
15.4
15.4.1
15.4.1.1
15.4.1.2
15.4.1.2.1
15.4.1.2.2
15.4.1.2.3
15.4.1.2.4
15.4.1.2.5
15.4.1.3
15.4.1.3.1
15.4.1.3.2
15.4.1.4
15.4.1.5
15.4.1.6
15.4.1.7
15.4.2
15.4.3
15.4.4
15.4.5
15.4.6
15.5
15.6
15.7
15.8
15.8.1
15.8.2
15.8.3
15.8.4
15.8.5
15.8.6
15.8.7
15.8.8
15.8.9
HSSI Subsystem Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2
OCN Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3
DMA Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
DMA Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7
Source/Destination Transaction Size Calculations. . . . . . . . . . . . . . . . . . . . 15-7
Basic DMA Mode Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Basic Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9
Basic Direct Single-Write Start Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Basic Chaining Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10
Basic Chaining Single-Write Start Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11
Extended DMA Mode Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12
Channel Continue Mode for Cascading Transfer Chains. . . . . . . . . . . . . . 15-13
Basic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Extended Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Channel Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14
Bandwidth Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Channel State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15
Illustration of Stride Size and Stride Distance . . . . . . . . . . . . . . . . . . . . . . 15-15
DMA Transfer Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
DMA Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16
DMA Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17
Local Access ATMU Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
Limitations and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-19
OCN-to-MBus (O2M) Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
SRIO Port Controller Modules (SRIOn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
SerDes PHY Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
HSSI Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-21
Mode Registers 0–3 (DnMR[0–3]). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-24
Status Registers (DnSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-27
Current Link Descriptor Extended Address Registers (DnECLNDARn). . . 15-29
Current Link Descriptor Address Registers (DnCLNDARn): . . . . . . . . . . . 15-30
Source Attributes Registers (DnSATRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-31
Source Address Registers (DnSARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-32
Destination Attributes Registers (DnDATRn). . . . . . . . . . . . . . . . . . . . . . . . 15-33
Destination Address Registers (DnDARn) . . . . . . . . . . . . . . . . . . . . . . . . . . 15-34
Byte Count Registers (DnBCRn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-35
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15.8.10
15.8.11
15.8.12
15.8.13
15.8.14
15.8.15
15.8.16
15.8.17
15.8.18
15.8.19
15.8.20
15.8.21
15.8.22
15.8.23
15.8.24
15.8.25
15.8.26
15.8.27
15.8.28
15.8.29
15.8.30
15.8.31
15.8.32
15.8.33
Extended Next Link Descriptor Address Registers (DnENLNDARn) . . . . .
Next Link Descriptor Address Registers (DnNLNDARn) . . . . . . . . . . . . . .
Extended Current List Descriptor Address Registers (DnECLSDARn). . . .
Current List Descriptor Address Registers (DnCLSDARn) . . . . . . . . . . . . .
Extended Next List Descriptor Address Registers (DnENLSDARn) . . . . . .
Next List Descriptor Address Registers (DnNLSDARn) . . . . . . . . . . . . . . .
Source Stride Registers (DnSSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Destination Stride Registers (DnDSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA General Status Register (DnDGSR)) . . . . . . . . . . . . . . . . . . . . . . . . .
Local Access Window Base Address Registers 0–9 (DnLAWBAR[0–9]) .
Local Access Window Attributes Registers 0–9 (DnLAWAR[0–9]) . . . . . .
OCN-to-MBus Configuration Registers (O2MCR[0–1]) . . . . . . . . . . . . . . .
OCN-to-MBus Error Attribute Registers (O2MEAR[0–1]) . . . . . . . . . . . . .
OCN-to-MBus Error Address Registers (O2MEADR[0–1]) . . . . . . . . . . . .
OCN-to-MBus Error Status Registers (O2MESR[0–1]). . . . . . . . . . . . . . . .
OCN-to-MBus Interrupt Enable Registers (O2MIER[0–1]). . . . . . . . . . . . .
OCN-to-MBus Error Capture Enable Registers (O2MECER[0–1]). . . . . . .
SRDS Control Register 0 (SRDSnCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 1 (SRDSnCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 2 (SRDSnCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 3 (SRDSnCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 4 (SRDSnCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 5 (SRDSnCR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SRDS Control Register 6 (SRDSnCR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15-36
15-37
15-38
15-39
15-40
15-41
15-42
15-43
15-44
15-46
15-47
15-49
15-50
15-52
15-53
15-54
15-55
15-56
15-59
15-62
15-63
15-65
15-67
15-68
16
Serial RapidIO Controller
16.1
16.1.1
16.1.2
16.1.3
16.1.4
16.1.4.1
16.1.4.2
16.2
16.2.1
16.2.2
16.2.3
16.2.4
16.2.4.1
16.2.4.2
16.2.4.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
1x/4x LP-Serial Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
RapidIO Interface Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Initialization for Booting the MSC8156 DSP . . . . . . . . . . . . . . . . . . . . . . . 16-6
Initialization for Non-Boot Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
RapidIO Interface Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
RapidIO Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7
RapidIO Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8
RapidIO Control Symbol Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9
Accessing Configuration Registers via RapidIO Packets . . . . . . . . . . . . . . . 16-11
Inbound Maintenance Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11
RapidIO Non-Maintenance Accesses Using LCSBA1CSR. . . . . . . . . . . . 16-12
RapidIO Maintenance Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
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Contents
16.2.4.3.1
16.2.4.3.2
16.2.5
16.2.5.1
16.2.5.2
16.2.5.3
16.2.5.3.1
16.2.5.3.2
16.2.5.4
16.2.5.4.1
16.2.5.4.2
16.2.6
16.2.7
16.2.8
16.2.9
16.2.10
16.2.10.1
16.2.10.2
16.2.10.3
16.3
16.3.1
16.3.2
16.3.2.1
16.3.2.2
16.3.2.3
16.3.2.4
16.3.2.5
16.3.2.5.1
16.3.2.5.2
16.3.2.5.3
16.3.2.5.4
16.3.2.5.5
16.3.2.6
16.3.2.7
16.3.2.8
16.3.3
16.3.3.1
16.3.3.2
16.3.3.3
16.3.3.4
16.3.3.5
Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
Outbound Maintenance Accesses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12
RapidIO ATMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
RapidIO Outbound ATMU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13
Outbound Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-15
Window Size and Segmented Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . 16-16
Valid Hits to Multiple ATMU Windows . . . . . . . . . . . . . . . . . . . . . . . . . . 16-40
Window Boundary Crossing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-41
RapidIO Inbound ATMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-42
Hits to Multiple ATMU Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44
Window Boundary Crossing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-44
Generating Link-Request/Reset-Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-45
Outbound Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-46
Input Port Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-47
Software Assisted Error Recovery Register Support . . . . . . . . . . . . . . . . . . 16-47
Errors and Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48
RapidIO Error Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-48
Physical Layer RapidIO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-50
Logical Layer RapidIO Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-53
RapidIO Message Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-79
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-79
Outbound Message Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-80
Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-80
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-83
Disabling and Enabling the Message Controller . . . . . . . . . . . . . . . . . . . . 16-84
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-84
Chaining Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-88
Changing Descriptor Queues in Chaining Mode . . . . . . . . . . . . . . . . . . . . 16-91
Preventing Queue Overflow in Chaining Mode . . . . . . . . . . . . . . . . . . . . . 16-91
Switching Between Direct and Chaining Modes . . . . . . . . . . . . . . . . . . . . 16-91
Chaining Mode Descriptor Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-92
Chaining Mode Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-93
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-94
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-95
Outbound Message Controller Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . 16-96
Inbound Message Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-97
Inbound Message Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 16-98
Inbound Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-98
Message Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-100
Retry Response Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-100
Inbound Message Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 16-100
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16.3.3.6
16.3.3.7
16.3.3.8
16.3.3.9
16.3.4
16.4
16.4.1
16.4.2
16.4.3
16.4.3.1
16.4.3.2
16.4.3.3
16.4.3.4
16.4.4
16.4.4.1
16.4.4.2
16.4.4.3
16.4.4.4
16.4.4.5
16.4.4.6
16.4.4.7
16.4.4.8
16.4.4.9
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.5.7
16.5.8
16.5.9
16.6
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
16.6.6
16.6.7
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disabling and Enabling the Inbound Message Controller . . . . . . . . . . . .
RapidIO Message Passing Logical Specification Register Bits . . . . . . . . .
RapidIO Doorbell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Doorbell Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outbound Doorbell Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inbound Doorbell Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Doorbell Queue Entry Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Retry Response Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Doorbell Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disabling and Enabling the Doorbell Controller . . . . . . . . . . . . . . . . . . .
RapidIO Message Passing Logical Specification Registers . . . . . . . . . . .
Port-Write Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port-Write Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port-Write Controller Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port-Write Controller Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discarding Port-Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transaction Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disabling and Enabling the Port-Write Controller . . . . . . . . . . . . . . . . . . .
RapidIO Message Passing Logical Specification Registers . . . . . . . . . . . .
RapidIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Identity Capability Register (DIDCAR) . . . . . . . . . . . . . . . . . . . . .
Device Information Capability Register (DICAR) . . . . . . . . . . . . . . . . . . .
Assembly Identity Capability Register (AIDCAR) . . . . . . . . . . . . . . . . . .
Assembly Information Capability Register (AICAR). . . . . . . . . . . . . . . . .
Processing Element Features Capability Register (PEFCAR) . . . . . . . . . .
Source Operations Capability Register (SOCAR) . . . . . . . . . . . . . . . . . . .
Destination Operations Capability Register (DOCAR) . . . . . . . . . . . . . . .
16-101
16-102
16-107
16-107
16-108
16-108
16-108
16-109
16-110
16-111
16-111
16-112
16-114
16-115
16-116
16-117
16-117
16-118
16-118
16-118
16-121
16-122
16-122
16-123
16-123
16-124
16-124
16-125
16-125
16-125
16-125
16-128
16-129
16-129
16-133
16-133
16-134
16-134
16-135
16-136
16-138
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Contents
16.6.8
16.6.9
16.6.10
16.6.11
16.6.12
16.6.13
16.6.14
16.6.15
16.6.16
16.6.17
16.6.18
16.6.19
16.6.20
16.6.21
16.6.22
16.6.23
16.6.24
16.6.25
16.6.26
16.6.27
16.6.28
16.6.29
16.6.30
16.6.31
16.6.32
16.6.33
16.6.34
Mailbox Command and Status Register (MCSR) . . . . . . . . . . . . . . . . . . . . 16-139
Port Write and Doorbell Command and Status Register (PWDCSR) . . . . 16-141
Processing Element Logical Layer Control Command and Status Register
(PELLCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-142
Local Configuration Space Base Address 1 Command and Status
Register (LCSBA1CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-143
Base Device ID Command and Status Register (BDIDCSR) . . . . . . . . . . . 16-144
Host Base Device ID Lock Command and Status Register
(HBDIDLCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-145
Component Tag Command and Status Register (CTCSR) . . . . . . . . . . . . . 16-146
Port Maintenance Block Header 0 (PMBH0) . . . . . . . . . . . . . . . . . . . . . . . 16-147
Port Link Time-Out Control Command and Status Register (PLTOCCSR)16-148
Port Response Time-Out Control Command and Status Register
(PRTOCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-149
Port General Control Command and Status Register (PGCCSR). . . . . . . . 16-150
Port 0–1 Link Maintenance Request Command and Status Register
(PnLMREQCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-151
Port 0–1 Link Maintenance Response Command and Status Register
(PnLMRESPCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-152
Port 0–1 Local ackID Command and Status Register (PnLASCR) . . . . . . 16-153
Port 0–1 Error and Status Command and Status Register (PnESCSR). . . . 16-154
Port 0–1 Control Command and Status Register (PnCCSR) . . . . . . . . . . . 16-156
Error Reporting Block Header (ERBH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-158
Logical/Transport Layer Error Detect Command and Status Register
(LTLEDCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-158
Logical/Transport Layer Error Enable Command and Status Register
(LTLEECSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-160
Logical/Transport Layer Address Capture Command and Status Register
(LTLACCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-161
Logical/Transport Layer Device ID Capture Command and Status Register
(LTLDIDCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-162
Logical/Transport Layer Control Capture Command and Status Register
(LTLCCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-163
Port 0–1 Error Detect Command and Status Register (PnEDCSR) . . . . . . 16-164
Port 0–1 Error Rate Enable Command and Status Register (PnERECSR). 16-165
Port 0–1 Error Capture Attributes Command and Status Register
(PnECACSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-166
Port 0–1 Packet/Control Symbol Error Capture Command and Status Register
(PnPCSECCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-168
Port 0–1 Packet Error Capture Command and Status Register 1
(PnPECCSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-169
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Contents
16.6.35
16.6.36
16.6.37
16.6.38
16.6.39
16.6.40
16.6.41
16.6.42
16.6.43
16.6.44
16.6.45
16.6.46
16.6.47
16.6.48
16.6.49
16.6.50
16.6.51
16.6.52
16.6.53
16.6.54
16.6.55
16.6.56
16.6.57
16.6.58
16.6.59
16.6.60
16.6.61
16.6.62
Port 0–1 Packet Error Capture Command and Status Register 2
(PnPECCSR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-170
Port 0–1 Packet Error Capture Command and Status Register 3
(PnPECCSR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-171
Port 0–1 Error Rate Command and Status Register (PnERCSR) . . . . . . . . 16-172
Port 0–1 Error Rate Threshold Command and Status Register
(PnERTCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-173
Logical Layer Configuration Register (LLCR). . . . . . . . . . . . . . . . . . . . . . 16-174
Error/Port-Write Status Register (EPWISR). . . . . . . . . . . . . . . . . . . . . . . . 16-175
Logical Retry Error Threshold Configuration Register (LRETCR) . . . . . . 16-176
Physical Retry Error Threshold Configuration Register (PRETCR) . . . . . 16-177
Port 0–1 Alternate Device ID Command and Status Register
(PnADIDCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-178
Port 0–1 Pass-Through Accept-All Configuration Register (PnPTAACR) 16-179
Port 0–1 Logical Outbound Packet Time-to-Live Configuration Register
(PnLOPTTLCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-180
Port 0–1 Implementation Error Command and Status Register (PnIECSR) 16-181
Port 0–1 Serial Link Command and Status Register (PnSLCSR). . . . . . . . 16-182
Port 0–1 Serial Link Error Injection Configuration Register (PnSLEICR) 16-183
IP Block Revision Register 1 (IPBRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-184
IP Block Revision Register 2 (IPBRR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-184
Port 0–1 RapidIO Outbound Window Translation Address Registers x
(PnROWTARx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-185
Port 0–1 RapidIO Outbound Window Translation Extended Address Registers x
(PnROWTEARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-186
Port 0–1 RapidIO Outbound Window Base Address Registers x
(PnROWBARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-187
Port 0–1 RapidIO Outbound Window Attributes Registers x
(PnROWARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-188
Port 0–1 RapidIO Outbound Window Segment 1–3 Registers 1–8
(PnROWSxRy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-190
Port 0–1 RapidIO Inbound Window Translation Address Registers x
(PnRIWTARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-191
Port 0–1 RapidIO Inbound Window Base Address Registers x
(PnRIWBARx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-192
Port 0–1 RapidIO Inbound Window Attributes Registers x (PnRIWARx) 16-193
Outbound Message x Mode Registers (OMxMR) . . . . . . . . . . . . . . . . . . . 16-194
Outbound Message x Status Registers (OMxSR) . . . . . . . . . . . . . . . . . . . . 16-196
Outbound Message x Descriptor Queue Dequeue Pointer Address Registers
(DMxDQDPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-198
Outbound Message x Source Address Registers (OMxSAR) . . . . . . . . . . . 16-199
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Contents
16.6.63
16.6.64
16.6.65
16.6.66
16.6.67
16.6.68
16.6.69
16.6.70
16.6.71
16.6.72
16.6.73
16.6.74
16.6.75
16.6.76
16.6.77
16.6.78
16.6.79
16.6.80
16.6.81
16.6.82
16.6.83
16.6.84
16.6.85
16.6.86
16.6.87
Outbound Message x Destination Port Register (OMxDPR) . . . . . . . . . . . 16-200
Outbound Message x Destination Attributes Register (OMxDATR) . . . . . 16-201
Outbound Message x Double-Word Count Register (DMxDCR) . . . . . . . 16-202
Outbound Message x Descriptor Queue Enqueue Pointer Address Registers
(OMxDQEPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-203
Outbound Message x Retry Error Threshold Configuration Register
(OMxRETCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-204
Outbound Message x Multicast Group Registers (OMxMGR) . . . . . . . . . 16-205
Outbound Message x Multicast List Registers (OMxMLR) . . . . . . . . . . . . 16-206
Inbound Message x Mode Registers (IMxMR). . . . . . . . . . . . . . . . . . . . . . 16-207
Inbound Message x Status Registers (IMxSR) . . . . . . . . . . . . . . . . . . . . . . 16-209
Inbound Message x Frame Queue Dequeue Pointer Address Registers
(IMxFQDPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-211
Inbound Message x Frame Queue Enqueue Pointer Address Registers
(IMxFQEPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-212
Inbound Message x Maximum Interrupt Report Interval Registers
(IMxMIRIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-213
Outbound Doorbell Mode Register (ODMR) . . . . . . . . . . . . . . . . . . . . . . . 16-214
Outbound Doorbell Status Register (ODSR) . . . . . . . . . . . . . . . . . . . . . . . 16-215
Outbound Doorbell Destination Port Register (ODDPR) . . . . . . . . . . . . . . 16-216
Outbound Doorbell Destination Attributes Register (ODDATR). . . . . . . . 16-217
Outbound Doorbell Retry Error Threshold Configuration Register
(ODRETCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-218
Inbound Doorbell Mode Registers (IDMR) . . . . . . . . . . . . . . . . . . . . . . . . 16-219
Inbound Doorbell Status Register (IDSR) . . . . . . . . . . . . . . . . . . . . . . . . . 16-221
Inbound Doorbell Queue Dequeue Pointer Address Register (IDQDPAR) 16-222
Inbound Doorbell Queue Enqueue Pointer Address Registers
(IDQEPAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-223
Inbound Doorbell Maximum Interrupt Report Interval Register
(IDMIRIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-224
Inbound Port-Write Mode Register (IPWMR) . . . . . . . . . . . . . . . . . . . . . . 16-225
Inbound Port-Write Status Register (IPWSR) . . . . . . . . . . . . . . . . . . . . . . 16-226
Inbound Port-Write Queue Base Address Register (IPWQBAR). . . . . . . . 16-227
17
PCI Express Controller
17.1
17.1.1
17.1.2
17.2
17.3
17.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outbound Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inbound Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-1
17-2
17-3
17-4
17-5
17-6
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Contents
17.3.2
17.3.2.1
17.3.2.2
17.3.2.3
17.3.2.4
17.3.2.5
17.3.2.6
17.3.2.7
17.3.3
17.3.3.1
17.3.3.2
17.3.4
17.3.4.1
17.3.4.2
17.3.4.3
17.3.5
17.3.6
17.3.7
17.3.8
17.3.9
17.3.10
17.3.11
17.4
17.4.1
17.4.1.1
17.4.1.1.1
17.4.1.1.2
17.4.1.1.3
17.4.1.1.4
17.4.1.1.5
17.4.1.2
17.4.1.2.1
17.4.1.2.2
17.4.1.2.3
17.4.1.2.4
17.4.1.2.5
17.4.1.2.6
PCI Express Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-6
Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7
Byte Order for Configuration Transactions . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Transaction Ordering Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9
Memory Space Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
I/O Space Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10
Configuration Space Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
Serialization of Configuration and I/O Writes . . . . . . . . . . . . . . . . . . . . . . 17-11
Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-11
Outbound ATMU Message Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12
Inbound Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13
Error Handling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
PCI Express Error Logging and Signaling . . . . . . . . . . . . . . . . . . . . . . . . . 17-15
PCI Express Controller Internal Interrupt Sources. . . . . . . . . . . . . . . . . . . 17-17
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21
Initial Credit Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22
L2/L3 Ready Link State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
Hot Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23
Link Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24
PCI Express Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25
PCI Express Configuration Access Registers. . . . . . . . . . . . . . . . . . . . . . . 17-27
PCI Express Configuration Address Register (PEX_CONFIG_ADDR) . . 17-27
PCI Express Configuration Data Register (PEX_CONFIG_DATA). . . . . 17-28
PCI Express Outbound Completion Timeout Register
(PEX_OTB_CPL_TOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-29
PCI Express Configuration Retry Timeout Register
(PEX_CONF_RTY_TOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30
PCI Express Configuration Register (PEX_CONFIG) . . . . . . . . . . . . . . . 17-30
PCI Express Power Management Event and Message Registers . . . . . . . . 17-31
PCI Express PME and Message Detect Register (PEX_PME_MES_DR) 17-31
PCI Express PME and Message Disable Register
(PEX_PME_MES_DISR)17-33
PCI Express PME and Message Interrupt Enable Register
(PEX_PME_MES_IER)17-34
PCI Express Power Management Command Register (PEX_PMCR). . . . 17-36
PCI Express Link Width Control Register (PEX_LWCR) . . . . . . . . . . . . 17-37
PCI Express Link Width Status Register (PEX_LWSR) . . . . . . . . . . . . . 17-38
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Contents
17.4.1.2.7
17.4.1.2.8
17.4.1.3
17.4.1.3.1
17.4.1.3.2
17.4.1.4
17.4.1.4.1
17.4.1.4.2
17.4.1.4.3
17.4.1.4.4
17.4.1.4.5
17.4.1.4.6
17.4.1.4.7
17.4.1.4.8
17.4.1.4.9
17.4.1.4.10
17.4.1.4.11
17.4.1.4.12
17.4.1.4.13
17.4.1.5
17.4.1.5.1
17.4.1.5.2
17.4.1.5.3
17.4.1.5.4
17.4.1.5.5
17.4.1.5.6
17.4.1.5.7
17.4.1.5.8
17.4.1.6
17.4.1.6.1
17.4.1.6.2
17.4.1.6.3
17.4.1.6.4
17.4.1.7
17.4.1.7.1
17.4.1.7.2
17.4.1.7.3
17.4.1.7.4
PCI Express Link Speed Control Register (PEX_LSCR) . . . . . . . . . . . . .
PCI Express Link Speed Status Register (PEX_LSSR) . . . . . . . . . . . . . . .
PCI Express IP Block Revision Registers . . . . . . . . . . . . . . . . . . . . . . . . .
IP Block Revision Register 1 (PEX_IP_BLK_REV1). . . . . . . . . . . . . . . .
IP Block Revision Register 2 (PEX_IP_BLK_REV2). . . . . . . . . . . . . . . .
PCI Express ATMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Outbound ATMU Registers. . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Outbound Translation Address Registers (PEXOTARn) . . .
PCI Express Outbound Translation Extended Address Registers
(PEXOTEARn). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Outbound Window Base Address Registers
(PEXOWBARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Outbound Window Attributes Registers (PEXOWARn) . . .
PCI Express Inbound ATMU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
EP Inbound ATMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC Inbound ATMU Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Inbound Translation Address Registers (PEXITARn) . . . . .
PCI Express Inbound Window Base Address Register 1 (PEXIWBAR1)
PCI Express Inbound Window Base Address Registers (PEXIWBARn) .
PCI Express Inbound Window Base Extended Address Registers
(PEXIWBEARn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Inbound Window Attributes Registers (PEXIWARn) . . . . .
PCI Express Error Management Registers . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Error Detect Register (PEX_ERR_DR) . . . . . . . . . . . . . . . .
PCI Express Error Interrupt Enable Register (PEX_ERR_EN) . . . . . . . . .
PCI Express Error Disable Register (PEX_ERR_DISR) . . . . . . . . . . . . . .
PCI Express Error Capture Status Register (PEX_ERR_CAP_STAT) . . .
PCI Express Error Capture Register 0 (PEX_ERR_CAP_R0) . . . . . . . . .
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1) . . . . . . . . .
PCI Express Error Capture Register 2 (PEX_ERR_CAP_R2) . . . . . . . . .
PCI Express Error Capture Register 3 (PEX_ERR_CAP_R3) . . . . . . . . .
PCI Express Configuration Space Access . . . . . . . . . . . . . . . . . . . . . . . . .
RC Configuration Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Configuration Access Register Mechanism . . . . . . . . . . . . .
Outbound ATMU Configuration Mechanism (RC-Only) . . . . . . . . . . . . .
EP Configuration Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Compatible Configuration Headers. . . . . . . . . . . . . . . . . . . . . . . . . . .
Common PCI Compatible Configuration Header Registers . . . . . . . . . . .
PCI Express Vendor ID Register—Offset 0x00. . . . . . . . . . . . . . . . . . . . .
PCI Express Device ID Register—Offset 0x02 . . . . . . . . . . . . . . . . . . . . .
PCI Express Command Register—Offset 0x04 . . . . . . . . . . . . . . . . . . . . .
17-39
17-40
17-41
17-41
17-41
17-42
17-42
17-42
17-43
17-44
17-45
17-47
17-47
17-47
17-48
17-49
17-50
17-51
17-52
17-54
17-54
17-56
17-58
17-59
17-60
17-61
17-63
17-64
17-65
17-65
17-66
17-66
17-67
17-67
17-67
17-68
17-68
17-68
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Contents
17.4.1.7.5
17.4.1.7.6
17.4.1.7.7
17.4.1.7.8
17.4.1.7.9
17.4.1.7.10
17.4.1.7.11
17.4.1.7.12
17.4.1.7.13
17.4.1.7.14
17.4.1.7.15
17.4.1.7.16
17.4.1.7.17
17.4.1.7.18
17.4.1.7.19
17.4.1.7.20
17.4.1.7.21
17.4.1.7.22
17.4.1.7.23
17.4.1.7.24
17.4.1.7.25
17.4.1.7.26
17.4.1.7.27
17.4.1.7.28
17.4.1.7.29
17.4.1.7.30
17.4.1.7.31
17.4.1.7.32
17.4.1.7.33
17.4.1.7.34
17.4.1.7.35
17.4.1.7.36
17.4.1.7.37
17.4.1.7.38
17.4.1.7.39
17.4.1.7.40
17.4.1.7.41
17.4.1.8
17.4.1.8.1
17.4.1.8.2
17.4.1.8.3
PCI Express Status Register—Offset 0x06 . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Revision ID Register—Offset 0x08 . . . . . . . . . . . . . . . . . . .
PCI Express Class Code Register—Offset 0x09 . . . . . . . . . . . . . . . . . . . .
PCI Express Cache Line Size Register—Offset 0x0C . . . . . . . . . . . . . . . .
PCI Express Latency Timer Register—0x0D . . . . . . . . . . . . . . . . . . . . . .
PCI Express Header Type Register—0x0E . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express BIST Register—0x0F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Type 0 Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Base Address Registers—0x10–0x27 . . . . . . . . . . . . . . . . . .
PCI Express Subsystem Vendor ID Register (EP-Mode Only)—0x2C. . .
PCI Express Subsystem ID Register (EP-Mode Only)—0x2E . . . . . . . . .
Capabilities Pointer Register—0x34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Interrupt Line Register (EP-Mode Only)—0x3C . . . . . . . . .
PCI Express Interrupt Pin Register—0x3D . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Minimum Grant Register (EP-Mode Only)—0x3E . . . . . . .
PCI Express Maximum Latency Register (EP-Mode Only)—0x3F . . . . .
Type 1 Configuration Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Base Address Register 0—0x10 . . . . . . . . . . . . . . . . . . . . . .
PCI Express Primary Bus Number Register—Offset 0x18 . . . . . . . . . . . .
PCI Express Secondary Bus Number Register—Offset 0x19 . . . . . . . . . .
PCI Express Subordinate Bus Number Register—Offset 0x1A . . . . . . . .
PCI Express Secondary Latency Timer Register—0x1B. . . . . . . . . . . . . .
PCI Express I/O Base Register—0x1C . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express I/O Limit Register—0x1D. . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Secondary Status Register—0x1E. . . . . . . . . . . . . . . . . . . . .
PCI Express Memory Base Register—0x20 . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Memory Limit Register—0x22 . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Prefetchable Memory Base Register—0x24 . . . . . . . . . . . . .
PCI Express Prefetchable Memory Limit Register—0x26 . . . . . . . . . . . .
PCI Express Prefetchable Base Upper 32 Bits Register—0x28. . . . . . . . .
PCI Express Prefetchable Limit Upper 32 Bits Register—0x2C . . . . . . . .
PCI Express I/O Base Upper 16 Bits Register—0x30 . . . . . . . . . . . . . . . .
PCI Express I/O Limit Upper 16 Bits Register—0x32 . . . . . . . . . . . . . . .
Capabilities Pointer Register—0x34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Interrupt Line Register—0x3C . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Interrupt Pin Register—0x3D . . . . . . . . . . . . . . . . . . . . . . . .
PCI Express Bridge Control Register—0x3E . . . . . . . . . . . . . . . . . . . . . .
PCI Compatible Device-Specific Configuration Space . . . . . . . . . . . . . . .
PCI Express Power Management Capability ID Register—0x44 . . . . . . .
PCI Express Power Management Capabilities Register—0x46. . . . . . . . .
PCI Express Power Management Status and Control Register—0x48 . . .
17-70
17-71
17-71
17-72
17-72
17-73
17-73
17-73
17-74
17-76
17-77
17-77
17-78
17-78
17-78
17-79
17-79
17-80
17-80
17-81
17-81
17-81
17-82
17-82
17-83
17-84
17-84
17-85
17-85
17-86
17-86
17-87
17-87
17-88
17-88
17-88
17-89
17-90
17-91
17-91
17-92
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Contents
17.4.1.8.4
17.4.1.8.5
17.4.1.8.6
17.4.1.8.7
17.4.1.8.8
17.4.1.8.9
17.4.1.8.10
17.4.1.8.11
17.4.1.8.12
17.4.1.8.13
17.4.1.8.14
17.4.1.8.15
17.4.1.8.16
17.4.1.8.17
17.4.1.8.18
17.4.1.8.19
17.4.1.8.20
17.4.1.8.21
17.4.1.8.22
17.4.1.9
17.4.1.9.1
17.4.1.9.2
17.4.1.9.3
17.4.1.9.4
17.4.1.9.5
17.4.1.9.6
17.4.1.9.7
17.4.1.9.8
17.4.1.9.9
17.4.1.9.10
17.4.1.9.11
17.4.1.9.12
17.4.1.9.13
17.4.1.9.14
17.4.1.9.15
17.4.1.9.16
17.4.1.9.17
17.4.1.9.18
PCI Express Power Management Data Register—0x4B . . . . . . . . . . . . . . 17-92
PCI Express Capability ID Register—0x4C . . . . . . . . . . . . . . . . . . . . . . . 17-93
PCI Express Capabilities Register—0x4E . . . . . . . . . . . . . . . . . . . . . . . . . 17-93
PCI Express Device Capabilities Register—0x50 . . . . . . . . . . . . . . . . . . . 17-94
PCI Express Device Control Register—0x54 . . . . . . . . . . . . . . . . . . . . . . 17-95
PCI Express Device Status Register—0x56. . . . . . . . . . . . . . . . . . . . . . . . 17-95
PCI Express Link Capabilities Register—0x58 . . . . . . . . . . . . . . . . . . . . . 17-96
PCI Express Link Control Register—0x5C . . . . . . . . . . . . . . . . . . . . . . . . 17-96
PCI Express Link Status Register—0x5E . . . . . . . . . . . . . . . . . . . . . . . . . 17-97
PCI Express Slot Capabilities Register—0x60 . . . . . . . . . . . . . . . . . . . . . 17-97
PCI Express Slot Control Register—0x64 . . . . . . . . . . . . . . . . . . . . . . . . . 17-98
PCI Express Slot Status Register—0x66 . . . . . . . . . . . . . . . . . . . . . . . . . . 17-99
PCI Express Root Control Register (RC Mode Only)—0x68 . . . . . . . . . . 17-99
PCI Express Root Status Register (RC Mode Only)—0x6C . . . . . . . . . . 17-100
PCI Express MSI Message Capability ID Register
(EP Mode Only)—0x70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-100
PCI Express MSI Message Control Register (EP Mode Only)—0x72 . . 17-101
PCI Express MSI Message Address Register (EP Mode Only)—0x74 . . 17-101
PCI Express MSI Message Upper Address Register
(EP Mode Only)—0x78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-102
PCI Express MSI Message Data Register (EP Mode Only)—0x7C . . . . 17-102
PCI Express Extended Configuration Space . . . . . . . . . . . . . . . . . . . . . . 17-103
PCI Express Advanced Error Reporting Capability ID Register—0x100 17-104
PCI Express Uncorrectable Error Status Register—0x104 . . . . . . . . . . . 17-104
PCI Express Uncorrectable Error Mask Register—0x108 . . . . . . . . . . . . 17-105
PCI Express Uncorrectable Error Severity Register—0x10C . . . . . . . . . 17-106
PCI Express Correctable Error Status Register—0x110 . . . . . . . . . . . . . 17-107
PCI Express Correctable Error Mask Register—0x114 . . . . . . . . . . . . . . 17-108
PCI Express Advanced Error Capabilities and Control Register—0x118 17-109
PCI Express Header Log Register—0x11C–0x12B. . . . . . . . . . . . . . . . . 17-110
PCI Express Root Error Command Register—0x12C . . . . . . . . . . . . . . . 17-111
PCI Express Root Error Status Register—0x130 . . . . . . . . . . . . . . . . . . . 17-111
PCI Express Correctable Error Source ID Register—0x134 . . . . . . . . . . 17-112
PCI Express Error Source ID Register—0x136 . . . . . . . . . . . . . . . . . . . . 17-112
LTSSM State Control Register—0x400. . . . . . . . . . . . . . . . . . . . . . . . . . 17-113
LTSSM State Status Register—0x404 . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-114
PCI Express ACK Replay Timeout Register
(PEX_ACK_REPLAY_TIMEOUT)—0x434 . . . . . . . . . . . . . . . . . . . . . 17-116
PCI Express Controller Core Clock Ratio Register—0x440 . . . . . . . . . . 17-117
PCI Express Power Management Timer Register—0x450 . . . . . . . . . . . 17-117
PCI Express PME Time-Out Register (EP-Mode Only)—0x454 . . . . . . 17-118
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Contents
17.4.1.9.19
17.4.1.9.20
17.4.1.9.21
17.4.1.9.22
17.4.1.9.23
PCI Express Subsystem Vendor ID Update Register
(EP Mode Only)—0x478 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Ready Register—0x4B0 . . . . . . . . . . . . . . . . . . . . . . . . . .
PME_To_Ack Timeout Register (RC-Mode Only)—0x590 . . . . . . . . . .
Secondary Status Interrupt Mask Register (RC-Mode Only)—0x5A0 . .
Gen2 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17-119
17-119
17-120
17-121
17-122
18
QUICC Engine Subsystem
18.1
18.2
18.2.1
18.2.2
18.2.3
18.2.4
18.2.5
18.2.6
18.2.7
18.3
18.3.1
18.3.2
18.3.2.1
18.3.2.2
18.3.3
18.3.4
18.3.5
18.4
18.4.1
18.4.2
18.5
18.6
18.7
18.7.1
18.7.1.1
18.7.1.2
18.7.2
18.7.2.1
18.7.2.1.1
18.7.2.1.2
18.7.2.2
18.7.2.2.1
18.7.2.2.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2
RISC Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
SC3850 Core Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3
Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Parameter RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4
Buffer Descriptors (BDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5
Multithreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6
Serial Numbers (SNUMs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7
IRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
Serial DMA Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
Data Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-8
SDMA and Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Simple Recovery from Bus Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-9
Selective Peripheral Recovery Procedure . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
SDMA and Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
MBus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10
SDMA Internal Resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
Multiplexer Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-11
Baud-Rate Generators (BRGs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
UCCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-14
Ethernet Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18
RGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18
SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18
Ethernet Physical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18
Reduced Gigabit Media-Independent Interface (RGMII) Signals . . . . . . . 18-19
RGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-19
RGMII Signal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20
Serial Gigabit Media-Independent Interface (SGMII) Signals . . . . . . . . . 18-20
SGMII Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
SGMII Signal Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21
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Contents
18.7.3
18.7.4
18.8
18.8.1
18.8.1.1
18.8.1.2
18.8.2
18.8.3
18.8.4
18.9
Controlling PHY Links (Management Interface) . . . . . . . . . . . . . . . . . . . . .
Ethernet Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI as a Master Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI as a Slave Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI in Multi-Master Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Signal Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Transmission and Reception Process . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18-22
18-22
18-23
18-24
18-24
18-26
18-26
18-28
18-28
18-29
19
TDM Interface
19.1
19.2
19.2.1
19.2.2
19.2.3
19.2.4
19.2.4.1
19.2.4.2
19.2.4.3
19.2.4.4
19.2.5
19.2.6
19.2.6.1
19.2.6.2
19.2.6.3
19.2.6.4
19.2.7
19.3
19.4
19.5
19.6
19.7
19.7.1
19.7.1.1
19.7.1.2
19.7.1.3
19.7.1.4
19.7.1.5
19.7.1.6
Typical Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5
TDM Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6
Common Signals for the TDM Modules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8
Receiver and Transmitter Independent or Shared Operation . . . . . . . . . . . . 19-10
TDM Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
Sync Out Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15
Sync In Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16
Serial Interface Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-18
Reverse Data Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20
TDM Local Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-22
Buffers Mapped on System Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23
Data Buffer Size and A/m-law Channels . . . . . . . . . . . . . . . . . . . . . . . . . . 19-23
Data Buffer Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-24
Threshold Pointers and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26
Unified Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-28
Adaptation Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-30
TDM Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
Channel Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-31
Loopback Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-32
TDM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-33
TDM Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-34
Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-36
TDMx General Interface Register (TDMxGIR). . . . . . . . . . . . . . . . . . . . . 19-36
TDMx Receive Interface Register (TDMxRIR). . . . . . . . . . . . . . . . . . . . . 19-43
TDMx Transmit Interface Register (TDMxTIR) . . . . . . . . . . . . . . . . . . . . 19-45
TDMx Receive Frame Parameters (TDMxRFP) . . . . . . . . . . . . . . . . . . . . 19-47
TDMx Transmit Frame Parameters (TDMxTFP) . . . . . . . . . . . . . . . . . . . 19-50
TDMx Receive Data Buffer Size (TDMxRDBS) . . . . . . . . . . . . . . . . . . . 19-52
MSC8156 Reference Manual, Rev. 2
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Contents
19.7.1.7
19.7.1.8
19.7.1.9
19.7.1.10
19.7.1.11
19.7.1.12
19.7.2
19.7.2.1
19.7.2.2
19.7.2.3
19.7.2.4
19.7.2.5
19.7.2.6
19.7.2.7
19.7.2.8
19.7.2.9
19.7.2.10
19.7.2.11
19.7.3
19.7.3.1
19.7.3.2
19.7.3.3
19.7.3.4
19.7.3.5
19.7.3.6
19.7.3.7
19.7.3.8
19.7.3.9
19.7.3.10
19.7.3.11
TDMx Transmit Data Buffer Size (TDMxTDBS) . . . . . . . . . . . . . . . . . . .
TDMx Receive Global Base Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Global Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Force Register (TDMxTFR) . . . . . . . . . . . . . . . . . . . . . .
TDMx Receive Force Register (TDMxRFR). . . . . . . . . . . . . . . . . . . . . . .
TDMx Parity Control Register (TDMxPCR) . . . . . . . . . . . . . . . . . . . . . . .
Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Adaptation Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Receive Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Control Register (TDMxTCR) . . . . . . . . . . . . . . . . . . . .
TDMx Receive Data Buffer First Threshold (TDMxRDBFT) . . . . . . . . .
TDMx Transmit Data Buffer First Threshold . . . . . . . . . . . . . . . . . . . . . .
TDMx Receive Data Buffer Second Threshold . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Data Buffer Second Threshold . . . . . . . . . . . . . . . . . . . .
TDMx Receive Channel Parameter Register n . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Channel Parameter Register n . . . . . . . . . . . . . . . . . . . . .
TDMx Receive Interrupt Enable Register (TDMXRIER) . . . . . . . . . . . . .
TDMx Transmit Interrupt Enable Register (TDMxTIER) . . . . . . . . . . . . .
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TDMx Adaptation Sync Distance Register (TDMxASDR) . . . . . . . . . . . .
TDMx Receive Data Buffers Displacement Register (TDMxRDBDR) . .
TDMx Transmit Data Buffer Displacement Register (TDMxTDBDR) . .
TDMx Receive Number of Buffers (TDMxRNB) . . . . . . . . . . . . . . . . . . .
TDMx Transmitter Number of Buffers (TDMxTNB) . . . . . . . . . . . . . . . .
TDMx Receive Event Register (TDMxRER) . . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Event Register (TDMxTER) . . . . . . . . . . . . . . . . . . . . . .
TDMx Adaptation Status Register (TDMxASR) . . . . . . . . . . . . . . . . . . . .
TDMx Receive Status Register (TDMxRSR) . . . . . . . . . . . . . . . . . . . . . .
TDMx Transmit Status Register (TDMxTSR). . . . . . . . . . . . . . . . . . . . . .
TDMx Parity Error Register (TDMxPER) . . . . . . . . . . . . . . . . . . . . . . . . .
19-53
19-53
19-54
19-54
19-55
19-56
19-56
19-56
19-57
19-58
19-58
19-59
19-60
19-60
19-61
19-62
19-63
19-64
19-65
19-65
19-66
19-66
19-67
19-68
19-68
19-69
19-70
19-71
19-72
19-73
20
UART
20.1
20.1.1
20.1.2
20.1.3
20.1.4
20.2
20.2.1
20.2.2
20.2.3
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6
Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Parity Bit Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11
Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12
Framing Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17
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20.2.4
20.2.5
20.2.6
20.2.6.1
20.2.6.2
20.2.7
20.2.7.1
20.2.7.2
20.3
20.4
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
20.5
20.6
20.6.1
20.6.2
20.6.3
20.6.4
20.6.5
Parity Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud-Rate Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Data Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Input Line Wake-Up (WAKE = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Mark Wake-Up (WAKE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI Baud-Rate Register (SCIBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI Control Register (SCICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI Status Register (SCISR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI Data Register (SCIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SCI Data Direction Register (SCIDDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-18
20-18
20-18
20-19
20-20
20-20
20-21
20-21
20-21
20-22
20-22
20-22
20-23
20-23
20-23
20-24
20-24
20-25
20-26
20-29
20-31
20-32
21
Timers
21.1
21.1.1
21.1.2
21.1.3
21.1.3.1
21.1.3.2
21.1.4
21.1.4.1
21.1.4.2
21.1.4.3
21.1.4.4
21.1.5
21.1.5.1
21.1.5.2
21.1.5.3
21.1.6
21.1.6.1
Device-Level Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
Timer Module Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2
Setting Up Counters for Cascaded Operation . . . . . . . . . . . . . . . . . . . . . . . . . 21-3
Operation of the Cascaded Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Cascading Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5
One-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
Pulse Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
Fixed Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7
Variable Frequency PWM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8
Timer Compare Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10
Compare Preload Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
Capture Register Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-11
Broadcast from an Initiator Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
Timer Compare Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12
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Contents
21.1.6.2
21.1.6.3
21.2
21.3
21.3.1
21.3.2
21.3.3
21.4
21.4.1
21.4.1.1
21.4.1.2
21.4.1.3
21.4.1.4
21.4.1.5
21.4.1.6
21.4.1.7
21.4.1.8
21.4.1.9
21.4.1.10
21.4.1.11
21.4.2
21.4.3
21.4.3.1
21.4.3.2
21.4.3.3
Timer Overflow Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Input Edge Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SC3850 DSP Core Subsystem Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Watchdog Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software WDT Servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timers Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device-Level Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Channel Control Registers (TMRnCTLx) . . . . . . . . . . . . . . . . . . . .
Timer Channel Status and Control Registers (TMRnSCTLx) . . . . . . . . . .
Timer Channel Compare 1 Registers (TMRnCMP1x). . . . . . . . . . . . . . . .
Timer Channel Compare 2 Registers (TMRnCMP2x). . . . . . . . . . . . . . . .
Timer Channel Compare Load 1 Registers (TMRnCMPLD1x) . . . . . . . .
Timer Channel Compare Load 2 Registers (TMRnCMPLD2x) . . . . . . . .
Timer Channel Comparator Status and Control Registers
(TMRnCOMSCx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Channel Capture Registers (TMRnCAPx) . . . . . . . . . . . . . . . . . . .
Timer Channel Load Registers (TMRnLOADx) . . . . . . . . . . . . . . . . . . . .
Timer Channel Hold Registers (TMRnHOLDx) . . . . . . . . . . . . . . . . . . . .
Timer Channel Counter Registers (TMRnCNTRx) . . . . . . . . . . . . . . . . . .
SC3850 DSP Core Subsystem Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Watchdog Timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Watchdog Control Register 0–7 (SWCRR[0–7]) . . . . . . . . . . . . .
System Watchdog Count Register 0–7 (SWCNR[0–7]) . . . . . . . . . . . . . .
System Watchdog Service Register 0–7 (SWSRR[0–7]). . . . . . . . . . . . . .
21-13
21-13
21-13
21-13
21-14
21-14
21-15
21-16
21-16
21-17
21-19
21-21
21-21
21-22
21-22
22
GPIO
22.1
22.2
22.3
22.4
22.4.1
22.4.2
22.4.3
22.4.4
22.4.5
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
GPIO Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2
GPIO Connection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3
GPIO Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5
Pin Open-Drain Register (PODR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6
Pin Data Register (PDAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7
Pin Data Direction Register (PDIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8
Pin Assignment Register (PAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-9
Pin Special Options Register (PSOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10
21-22
21-23
21-24
21-24
21-24
21-24
21-25
21-26
21-27
21-27
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23
24
24.1
24.2
24.3
24.3.1
24.3.2
24.3.3
24.3.4
24.3.5
24.3.6
24.3.7
24.3.8
24.4
24.4.1
24.4.2
24.4.3
24.4.4
24.4.5
24.4.6
24.4.7
24.4.8
24.5
24.5.1
24.5.2
24.5.3
24.5.4
24.5.5
24.5.6
24.5.7
24.5.8
24.5.9
24.5.10
24.6
24.6.1
24.6.2
24.6.3
24.6.4
24.6.5
24.6.6
Hardware Semaphores
I2C
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
I2C Module Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
Input Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
Digital Input Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
Transaction Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Arbitration Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
Transfer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
In/Out Data Shift Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
Address Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
Target Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
Repeated START Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
STOP Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-10
Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
Generation of I2C_SCL When I2C_SDA Low. . . . . . . . . . . . . . . . . . . . . . . 24-11
Target Mode Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
Target Transmitter and Received Acknowledge . . . . . . . . . . . . . . . . . . . . . . 24-12
Loss of Arbitration and Forcing of Target Mode . . . . . . . . . . . . . . . . . . . . . 24-12
Interrupt Service Routine Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
I2C Address Register (I2CADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
I2C Frequency Divider Register (I2CFDR) . . . . . . . . . . . . . . . . . . . . . . . . . 24-15
I2C Control Register (I2CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-16
I2C Status Register (I2CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-17
I2C Data Register (I2CDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-19
Digital Filter Sampling Rate Register (I2CDFSRR). . . . . . . . . . . . . . . . . . . 24-19
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25
Debugging, Profiling, and Performance Monitoring
25.1
25.1.1
25.1.2
25.1.3
25.1.4
25.1.5
25.1.6
25.1.7
25.1.8
25.1.9
25.1.10
25.1.11
25.1.12
25.1.13
25.1.14
25.1.15
25.1.15.1
25.1.15.2
25.1.15.3
25.1.15.4
25.1.15.5
25.2
25.2.1
25.2.2
25.2.3
25.2.4
25.2.5
25.2.6
25.2.6.1
25.2.6.2
25.2.7
25.2.7.1
25.2.7.2
25.2.8
25.2.8.1
25.2.8.2
25.2.9
25.2.9.1
25.2.9.2
25.2.10
TAP, Boundary Scan, and OCE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-5
Instruction Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6
Multi-Core JTAG and OCE Module Concept. . . . . . . . . . . . . . . . . . . . . . . . 25-10
Enabling the OCE Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10
DEBUG_REQUEST and ENABLE_ONCE Commands . . . . . . . . . . . . . . . 25-11
RD_STATUS Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12
Reading/Writing OCE Registers Through JTAG . . . . . . . . . . . . . . . . . . . . . 25-12
Signalling a Debug Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13
EE_CTRL Modifications for the MSC8156 . . . . . . . . . . . . . . . . . . . . . . . . . 25-14
ESEL_DM and EDCA_CTRL Register Programming. . . . . . . . . . . . . . . . . 25-15
Real-Time Debug Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15
Exiting Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-16
General JTAG Mode Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
JTAG and OCE Module Programming Model . . . . . . . . . . . . . . . . . . . . . . . 25-17
Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17
Boundary Scan Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-18
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20
Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21
Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22
Entering Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23
Exiting Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23
SC3850 Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
L1 ICache and DCache Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . 25-24
DMA Controller Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
Debug Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-24
Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
CLASS Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
CLASS Debug Profiling Unit (CDPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-25
QUICC Engine Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27
TDM Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
TDM Loopback Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
RapidIO Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28
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25.2.10.1
25.2.10.2
25.2.11
25.2.12
25.2.13
25.2.13.1
25.2.13.2
25.2.13.3
25.2.13.4
25.2.13.5
25.2.13.6
25.2.13.7
25.2.13.8
25.2.13.9
25.2.13.10
25.2.13.11
25.2.13.12
25.2.13.13
25.2.13.14
25.2.13.15
25.2.13.16
25.2.13.17
25.2.13.18
25.2.13.19
25.2.13.20
25.2.13.21
25.2.13.22
25.2.13.23
25.2.13.24
25.2.13.25
25.3
25.3.1
25.3.1.1
25.3.1.2
25.3.1.3
25.3.1.4
25.3.1.5
25.3.1.6
25.3.2
25.3.2.1
25.3.2.2
Debug Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Profiling Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE-B Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Watchdog (SWT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Profiling Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPU Control Register (DP_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPU Status Register (DP_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPU Monitor Register (DP_MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPU PID Detection Reference Value Register (DP_RPID) . . . . . . . . . . .
DPU DID Detection Reference Value Register (DP_RDID) . . . . . . . . . .
DPU Counter Triad A Control Register (DP_TAC) . . . . . . . . . . . . . . . . .
DPU Counter Triad B Control Register (DP_TBC) . . . . . . . . . . . . . . . . .
DPU Counter A0 Control Register (DP_CA0C) . . . . . . . . . . . . . . . . . . . .
DPU Counter A0 Value Register (DP_CA0V) . . . . . . . . . . . . . . . . . . . . .
DPU Counter A1 Control Register (DP_CA1C) . . . . . . . . . . . . . . . . . . . .
DPU Counter A1 Value Registers (DP_CA1V) . . . . . . . . . . . . . . . . . . . .
DPU Counter A2 Control Register (DP_CA2C) . . . . . . . . . . . . . . . . . . . .
DPU Counter A2 Value Registers (DP_CA2V) . . . . . . . . . . . . . . . . . . . .
DPU Counter B0 Control Register (DP_CB0C) . . . . . . . . . . . . . . . . . . . .
DPU Counter B0 Value Registers (DP_CB0V) . . . . . . . . . . . . . . . . . . . .
DPU Counter B1 Control Register (DP_CB1C) . . . . . . . . . . . . . . . . . . . .
DPU Counter B1 Value Registers (DP_CB1V) . . . . . . . . . . . . . . . . . . . .
DPU Counter B2 Control Register (DP_CB2C) . . . . . . . . . . . . . . . . . . .
DPU Counter B2 Value Registers (DP_CB2V) . . . . . . . . . . . . . . . . . . . .
DPU Trace Control Register (DP_TC) . . . . . . . . . . . . . . . . . . . . . . . . . . .
DPU VTB Start Address Register (DP_TSA) . . . . . . . . . . . . . . . . . . . . .
DPU VTB End Address Register (DP_TEA) . . . . . . . . . . . . . . . . . . . . . .
DPU Trace Event Request Register (DP_TER) . . . . . . . . . . . . . . . . . . . .
DPU Trace Write Pointer Register (DP_TW) . . . . . . . . . . . . . . . . . . . . .
DPU Trace Data Register (DP_TD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Event Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threshold Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Programming Model . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Global Control Register (PMGC) . . . . . . . . . . . . . .
Performance Monitor Local Control A0 Register (PMLCA0). . . . . . . . . .
25-28
25-29
25-29
25-29
25-29
25-31
25-33
25-34
25-35
25-36
25-36
25-40
25-42
25-44
25-45
25-47
25-47
25-50
25-50
25-53
25-53
25-56
25-56
25-59
25-59
25-63
25-64
25-65
25-66
25-67
25-67
25-69
25-69
25-69
25-70
25-70
25-71
25-77
25-79
25-80
25-81
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25.3.2.3
25.3.2.4
25.3.2.5
25.3.2.6
26
26.1
26.2
26.2.1
26.2.2
26.2.3
26.2.4
26.3
26.3.1
26.3.1.1
26.3.1.2
26.3.1.3
26.3.1.4
26.3.1.4.1
26.3.1.4.2
26.3.1.4.3
26.3.1.4.4
26.3.1.4.5
26.3.1.4.6
26.3.1.4.7
26.3.1.4.8
26.3.1.4.9
26.3.1.4.10
26.3.1.4.11
26.3.2
26.3.2.1
26.3.2.1.1
26.3.2.1.2
26.3.2.1.3
26.3.2.1.4
26.3.2.1.5
26.3.2.2
26.3.2.2.1
26.3.2.2.2
26.3.2.2.3
Performance Monitor Local Control A[1–8] (PMLCA[1–8]) . . . . . . . . . .
Performance Monitor Local Control B[1–8] (PMLCB[1–8]) . . . . . . . . . .
Performance Monitor Counter 0 (PMC0). . . . . . . . . . . . . . . . . . . . . . . . . .
Performance Monitor Counter 1–8 (PMC[1–8]) . . . . . . . . . . . . . . . . . . . .
25-82
25-83
25-84
25-85
Multi Accelerator Platform Engine, Baseband (MAPLE-B)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
3GLTE Standard Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
WiMAX Standard Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-5
3GPP Standard Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
3GPP2 Standard Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
Buffer Descriptors (BDs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
BD Rings Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-6
BD Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-8
BDs Data Coherency Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10
Turbo/Viterbi Decoding Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
Turbo Standard Parameter Assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . 26-11
TVPE Buffer-Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-12
Buffer Descriptor Special Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24
TVPE Input Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-24
Input Sample Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-25
Direct Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-26
Separate Vectors Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-36
Periodically Punctured Configurable Mix Stream (PPCMS) Data Structure. 2639
Rate-Matched Fixed Mix Stream Data Structure . . . . . . . . . . . . . . . . . . . . 26-44
Sub-Block Interleaved Vectors Data Structure . . . . . . . . . . . . . . . . . . . . . 26-49
Supported Input Data Structures for Different Standards . . . . . . . . . . . . . 26-52
PE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-55
Turbo/Viterbi PE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-55
Turbo Decoding Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-55
Viterbi Decoding Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-64
TVPE Output Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-73
Output Data Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-77
TVPE Debug and Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-78
FFT/iFFT/DFT/iDFT Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80
FTPE Buffer-Descriptor Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-80
FTPE Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-90
FTPE Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-95
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26.3.2.2.4
26.3.2.2.5
26.3.2.2.6
26.3.2.3
26.3.2.3.1
26.3.2.3.2
26.3.2.3.3
26.3.2.3.4
26.3.2.3.5
26.3.3
26.3.3.1
26.3.3.2
26.3.3.2.1
26.3.3.2.2
26.3.3.2.3
26.3.3.3
26.3.3.3.1
26.3.3.3.2
26.3.3.4
26.3.3.5
26.3.3.6
26.3.3.7
26.3.3.7.1
26.3.3.7.2
26.3.4
26.4
26.4.1
26.4.1.1
26.4.1.2
26.4.1.3
26.4.1.4
26.4.2
26.4.2.1
26.4.2.1.1
26.4.2.1.2
26.4.2.1.3
26.4.2.1.4
26.4.2.1.5
FTPE Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using the DFTPE as FFTPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FTPE Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Buffer-Descriptor Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Descriptors Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Input Data Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CRC Processing Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
:System Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Correction Code (ECC) Memory Support . . . . . . . . . . . . . . . . . . .
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BD Rings Done Indication Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Error Event Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECC Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Masters Support Using Serial RapidIO Doorbell . . . . . . . . . . .
Serial RapidIO Doorbell Parameters Configuration. . . . . . . . . . . . . . . . .
Serial RapidIO Configuration Information . . . . . . . . . . . . . . . . . . . . . . .
Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE-B Internal Task Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Hard/Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE-B Parameter RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFTPE Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFTPE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Detailed Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Buffer Descriptors (BD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE BD Rings Configuration Parameter (MBDRCP). . . . . . . . . . . .
MAPLE UCode Version Parameter (MUCVP) . . . . . . . . . . . . . . . . . . . .
MAPLE Timer Period Parameter (MP_TPP). . . . . . . . . . . . . . . . . . . . . .
MAPLE TVPE BD Ring High Priority A <x> Parameter
(MTVBRHPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE TVPE BD Ring High Priority B <x> Parameter
(MTVBRHPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
26-105
26-105
26-106
26-107
26-107
26-111
26-111
26-113
26-114
26-115
26-115
26-116
26-116
26-117
26-117
26-118
26-118
26-119
26-120
26-121
26-122
26-122
26-122
26-123
26-123
26-124
26-125
26-125
26-128
26-129
26-129
26-130
26-130
26-130
26-132
26-133
26-134
26-135
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Contents
26.4.2.1.6
26.4.2.1.7
26.4.2.1.8
26.4.2.1.9
26.4.2.1.10
26.4.2.1.11
26.4.2.1.12
26.4.2.1.13
26.4.2.1.14
26.4.2.1.15
26.4.2.1.16
26.4.2.1.17
26.4.2.1.18
26.4.2.1.19
26.4.2.2
26.4.2.2.1
26.4.2.2.2
26.4.2.2.3
26.4.2.2.4
26.4.2.2.5
26.4.2.2.6
26.4.2.3
MAPLE TVPE BD Ring Low Priority A <x> Parameter
(MTVBRLPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-136
MAPLE TVPE BD Ring Low Priority B <x> Parameter
(MTVBRLPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-137
MAPLE FFTPE BD Ring High Priority A <x> Parameter
(MFFBRHPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-139
MAPLE FFTPE BD Ring High Priority B <x> Parameter
(MFFBRHPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-140
MAPLE FFTPE BD Ring Low Priority A <x> Parameter
(MFFBRLPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-141
MAPLE FFTPE BD Ring Low Priority B <x> Parameter
(MFFBRLPBxP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-142
MAPLE DFTPE BD Ring High Priority A <x> Parameter
(MDFBRHPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-143
MAPLE DFTPE BD Ring High Priority B <x> Parameter
(MDFBRHPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-145
MAPLE DFTPE BD Ring Low Priority A <x> Parameter
(MDFBRLPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-146
MAPLE DFTPE BD Ring Low Priority B <x> Parameter
(MDFBRLPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-147
MAPLE CRCPE BD Ring High Priority A <x> Parameter
(MCRCBRHPAxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-148
MAPLE CRCPE BD Ring High Priority B <x> Parameter
(MCRCBRHPBxP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-149
MAPLE CRCPE BD Ring Low Priority A <x> Parameter
(MCRCBRLPAxP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-151
MAPLE CRCPE BD Ring Low Priority B <x> Parameter
(MCRCBRLPBxP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-152
MAPLE Operating Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-153
MAPLE- Turbo Stop Criteria Configuration Parameter(MTSCCP) . . . . 26-153
MAPLE Turbo Viterbi Puncturing Vector x High Configuration Parameter
(MTVPVxHCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-154
MAPLE Turbo Viterbi Puncturing Vector x Low Configuration Parameter
(MTVPVxLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-155
MAPLE Turbo Viterbi Puncturing Period Configuration y Parameter
(MTVPPCyP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-156
MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 0 Parameter
(MTVPVSxC0P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-157
MAPLE Turbo Viterbi Polynomial Vector Set x Configuration 1 Parameter
(MTVPVSxC1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-158
Profiling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-159
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Contents
26.4.2.3.1
26.4.2.3.2
26.4.2.3.3
26.4.2.3.4
26.4.2.3.5
26.4.2.3.6
26.4.2.3.7
26.4.2.3.8
26.4.2.3.9
26.4.2.4
26.4.2.4.1
26.4.2.4.2
26.4.2.4.3
26.4.2.4.4
26.4.3
26.4.3.1
26.4.3.2
26.4.3.3
26.4.3.4
26.4.3.5
26.4.4
26.4.4.1
26.4.4.1.1
26.4.4.1.2
26.4.4.1.3
26.4.4.1.4
26.4.4.1.5
26.4.4.1.6
26.4.4.1.7
26.4.4.1.8
26.4.4.2
26.4.4.2.1
26.4.4.2.2
26.4.4.2.3
26.4.4.2.4
26.4.4.2.5
MAPLE-B Turbo Total Performance Parameter (MTTPP) . . . . . . . . . . .
MAPLE-B Viterbi Total Performance Parameter (MVTPP) . . . . . . . . . .
MAPLE-B Total BLER Parameter (MTBP) . . . . . . . . . . . . . . . . . . . . . .
MAPLE-B TVPE BDs Counter Parameter (MTBDCP) . . . . . . . . . . . . .
MAPLE-B FFT Total Performance Parameter (MFTPP) . . . . . . . . . . . .
MAPLE-B FFTPE BDs Counter Parameter (MFBDCP) . . . . . . . . . . . . .
MAPLE-B DFT Total Performance Parameter (MDTPP) . . . . . . . . . . . .
MAPLE-B DFTPE BDs Counter Parameter (MDBDCP) . . . . . . . . . . . .
MAPLE-B Profiling Enable Parameter (MPEP) . . . . . . . . . . . . . . . . . . .
Serial RapidIO Doorbell Support Attributes Parameters . . . . . . . . . . . . .
Serial RapidIO Outbound RapidIO Doorbell Base Address Parameter
(SORDP0BAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Semaphore Base Address Parameter (HSP0BAP) . . . . . . . . .
MAPLE-B Doorbell Hardware Semaphore ID Configuration Parameter
(MDHSIDCP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAPLE-B Doorbell General Configuration Parameter (MDGCP) . . . . .
PSIF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSIF Command Register (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSIF PIC Event Register (PSPICER). . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSIF PIC Edge/Level Register(PSPICELR) . . . . . . . . . . . . . . . . . . . . . .
PSIF PIC Mask Register(PSPICMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PSIF PIC Interrupts Assertion Clocks Register (PSPICIACR) . . . . . . . .
Processing Engine Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Configuration 0 Register (TVPEC0R) . . . . . . . . . . . . . . . . . . . . .
TVPE Symbol Identification 0 Configuration Register (TVSI0CR) . . . .
TVPE Symbol Identification 1 Configuration Register (TVSI1CR) . . . .
TVPE Turbo Tail Symbol Identification x Configuration Register
(TVTTSIxCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Aposteriori Quality Configuration Register (TVAQCR) . . . . . . .
TVPE Viterbi Polynomial Vector Generation 0 Configuration Register
(TVVPVG0CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Viterbi Polynomial Vector Generation 1 Configuration Register
(TVVPVG1CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TVPE Decoder Status Register (TVPESR) . . . . . . . . . . . . . . . . . . . . . . .
FFTPE Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFTPE Data Size Register 0 (FFTPEDSR0) . . . . . . . . . . . . . . . . . . . . . .
FFTPE Data Size Register 1 (FFTPEDSR1) . . . . . . . . . . . . . . . . . . . . . .
FFTPE Data Size Register 2 (FFTPEDSR2) . . . . . . . . . . . . . . . . . . . . . .
FFTPE Status Register (FFTPESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FFTPE Scaling Status Register (FFTPESCLSTR). . . . . . . . . . . . . . . . . .
26-159
26-159
26-160
26-161
26-161
26-162
26-163
26-163
26-164
26-165
26-165
26-166
26-167
26-168
26-169
26-169
26-170
26-171
26-172
26-173
26-174
26-174
26-174
26-175
26-178
26-179
26-181
26-182
26-183
26-184
26-185
26-185
26-186
26-187
26-188
26-189
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Contents
26.4.4.2.6
26.4.4.2.7
26.4.4.2.8
26.4.4.2.9
26.4.4.3
26.4.4.3.1
26.4.4.3.2
26.4.4.3.3
26.4.4.4
26.4.4.4.1
26.4.4.4.2
26.4.4.4.3
26.4.4.4.4
26.4.4.4.5
26.4.4.4.6
FFTPE Saturation Status Register 0 (FFTPESSTR0) . . . . . . . . . . . . . . .
FFTPE Saturation Status Register 1 (FFTPESSTR1) . . . . . . . . . . . . . . .
FFTPE Saturation Status Register 2 (FFTPESSTR2) . . . . . . . . . . . . . . .
FFTPE Saturation Status Register 3 (FFTPESSTR3) . . . . . . . . . . . . . . .
DFTPE Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFTPE Data Size Register 0 (DFTPEDSR0) . . . . . . . . . . . . . . . . . . . . .
DFTPE Data Size Register 1 (DFTPEDSR1) . . . . . . . . . . . . . . . . . . . . .
DFTPE Data Size Register 2 (DFTPEDSR2) . . . . . . . . . . . . . . . . . . . . .
DFTPE Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFTPE Status Register (DFTPESTR) . . . . . . . . . . . . . . . . . . . . . . . . . . .
DFTPE Scaling Status Register (DFTPESCLSTR) . . . . . . . . . . . . . . . . .
DFTPE Saturation Status Register 0 (DFTPESSTR0) . . . . . . . . . . . . . . .
DFTPE Saturation Status Register 1 (DFTPESSTR1) . . . . . . . . . . . . . . .
DFTPE Saturation Status Register 2 (DFTPESSTR2) . . . . . . . . . . . . . . .
DFTPE Saturation Status Register 3(DFTPESSTR3) . . . . . . . . . . . . . . .
26-190
26-191
26-192
26-193
26-194
26-194
26-195
26-196
26-197
26-197
26-198
26-199
26-200
26-201
26-202
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Contents
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
About This Book
The MSC8156 device is the fourth generation of Freescale high-end multicore DSP devices. It
builds upon the proven success of the previous multicore DSPs and is designed to bolster the
rapidly changing and expanding wireless markets, such as 3GPP, TD-SCDMA, 3G-LTE, and
WiMAX. Its tool suite provides a full-featured development environment for C/C++ and
assembly languages as well as ease of integration with third-party software, such as off-the-shelf
libraries and a real-time operating system. The MSC8156 device includes six DSP core
subsystems, a large internal memory subsystem and DDR memory controller for external
memory, and a variety of communication processors and interfaces.
HSSI
SerDes Interfaces
TDM
UART
I2C
Timers
StarCore
SC3850
Core Subsystem
1056 KB M3
Memory
512 KB
L2 Cache/
M2 Memory
MAPLE
PCI Express
Serial RapidIO
Serial RapidIO
QUICC
Engine
Module
32 KB
32 KB
L1
L1
ICache DCache
Ethernet
Ethernet
SPI
DDR
Memory
Controller
DDR Interfaces
Per Core Subsystem
Six DSP Core Subsystems
Memory Subsystem
Each DSP core subsystem includes an
SC3850 DSP core, a 32 KB 8-way level
1 ICache, a 32 KB 8-way level 1
DCache, 512 KB level 2 cache
configurable as M2 memory, a memory
management unit, an embedded
programmable interrupt controller (EPIC)
with up to 256 interrupts and 32 priority
levels, two general-purpose 32-bit
timers, an on-chip emulator (OCE), a
debug and profiling unit (DPU), a JTAG
test access port (TAP), and two lowpower operating modes (Wait and Stop).
Interface from the cores to the memories
and external interfaces is through a chiplevel arbitration and switching system
(CLASS).
The memory subsystem includes 1056
KB of shared M3 memory, two DDRSDRAM controller to access up to 0.5
GB of DDR2/3 external memory, and a
32-channel direct memory access (DMA)
controller optimized for DDR-SDRAM.
MAPLE-B
The multi-accelerator platform engine
(MAPLE-B) provides Turbo decoding,
Viterbi decoding, FFT and DFT
acceleration.
Communications
Processors and Interfaces
Includes a PCI Express interface, two
serial RapidIO® interfaces, four 512channel (256 transmit and 256 receive)
TDM interfaces, a UART interface, an
I2C interface, eight timer input/outputs,
and a QUICC Engine module with two
1000Base-T Ethernet controllers and an
SPI. In addition, the global interrupt
controller (GIC) consolidates all chipmaskable and non-maskable interrupts
and routes them to NMI_OUT, INT_OUT,
and to the cores. The hardware
semaphores allow initiators to protect
and reserve the system hardware
resources.
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Before Using This Manual—Important Note
This manual describes the structure and function of the MSC8156 device. The information in this
manual is subject to change without notice, as described in the disclaimers on the title page of this
manual. As with any technical documentation, it is your responsibility as the reader to ensure that
you are using the most recent version of the documentation. For more information, contact your
sales representative.
Before using this manual, determine whether it is the latest revision and whether there are errata
or addenda. To locate any published errata or updates associated with this manual or this product,
refer to the Freescale web site. The address for the web site is listed on the back cover of this
manual.
Audience and Helpful Hints
This manual is intended for software and hardware developers and applications programmers
who want to develop products with the MSC8156. It is assumed that you have a working
knowledge of DSP technology and that you may be familiar with Freescale products based on
StarCore technology.
For your convenience, the chapters of this manual are organized to make the information flow as
predictably as possible. When feasible, the information in each chapter follows this general
sequence:
„ General description, block diagram, features, and architecture
„ Functional description with operating modes and example applications and programming
„ Programming Model (registers)
In chapters that include a Programming Model section, this section is the last one in the chapter,
or module subsection for those chapters that include multiple modules, and describes all registers
for the module discussed. The Programming Model section begins with a bulleted overview of
the registers that includes the page number where the description of each register begins.
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Notational Conventions and Definitions
This manual uses the following notational conventions:
mnemonics
Instruction mnemonics appear in lowercase bold.
COMMAND
Command names are set in small caps, as follows: GRACEFUL STOP TRANSMIT
or ENTER HUNT MODE.
names
italics
Book titles in text are set in italics, as are cross-referenced section titles. Also,
italics are used for emphasis and to highlight the main items in bulleted lists.
0x
Prefix to denote a hexadecimal number.
0b
Prefix to denote a binary number.
REG[FIELD]
Abbreviations or acronyms for registers or buffer descriptors appear in
uppercase text. Specific bits, fields, or numeric ranges appear in brackets. For
example, ICR[INIT] refers to the Force Initialization bit in the host Interface
Control Register.
ACTIVE HIGH
SIGNALS
Names of active high signals appear in sans serif capital letters, as follows:
TT[04], TSIZ[0–3], and DP[0–7].
ACTIVE LOW
SIGNALS
Signal names of active low signals appear in sans serif capital letters with an
overbar, as follows: DBG, AACK, and EXT_BG[2].
x
A lowercase italicized x in a register or signal name indicates that there are
multiple registers or signals with this name. For example, BRCGx refers to
BRCG[1–8], and MxMR refers to the MAMR/MBMR/MCMR registers.
On the MSC8156 device, the SC3850 cores are 16-bit DSP processors. The following table
shows the SC3850 assembly language data types. For details, see the StarCore SC3850 DSP
Core Reference Manual.
Name
SC3850
Byte/Octet
Half Word
Word
Long/Long Word/2 Words
Quad Word/4 Words
8 bits
8 bits
16 bits
32 bits
64 bits
The following table lists the SC3850 C language data types recognized by the StarCore C
compiler. For details, see the StarCore SC100 C Compiler User’s Manual (MNSC100CC/D).
Name
Size
char/unsigned char
short/unsigned short
int/unsigned int
8 bits
16 bits
16 bits
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Name
Size
fractional short
long/unsigned long
fractional long
pointer
16 bits
32 bits
32 bits
32 bits
Conventions for Registers
The Programming Model section of each chapter includes a register bit table for each register in
that module, as well as a table describing each bit in the register. The register bit table not only
shows the names and positions of the bits/bit fields but also their reset value, value after boot, and
their type (Read/Write). For registers that are not changed by the system boot, no boot line is
listed. The register address is shown with the register name and mnemonic. Reserved bits/fields
are indicated with a long dash (—). In the RSR shown below, all of the bits are read/write (R/W).
Other registers may include read-only (R) and write-only (W) bits. Notice that the least
significant bit (LSB) is 0, or big-endian order.
RSR
Bit
Reset Status Register
31
30
29
28
27
RSTSRC
26
25
24
Type
Reset
0
0
0
0
0
0
0
RIO
R/W
0
0
Bit
15
14
13
12
11
10
9
8
—
JPO
JH
JS
—
Type
Reset
—
23
SWSR SWHR
7
22
21
20
SW1
SW2
SW3
0
0
0
0
0
0
0
6
5
4
3
2
1
0
SW
–
SRS
HRS
0
0
1
1
—
19
18
17
—
16
BSF
R/W
0
0
0
0
0
0
0
0
0
0
0
0
Organization
Following is a summary and a brief description of the chapters of this manual:
„ Chapter 1, Overview. Features, descriptive overview of main modules, configurations,
and application examples.
„ Chapter 2, SC3850 Core Overview. Target markets, features, overview of development
tools, descriptive overview of main modules.
„ Chapter 3, External Signals. Identifies the external signals, lists signal groupings,
including the number of signal connections in each group, and describes each signal
within a functional group.
„ Chapter 4, Chip-Level Arbitration and Switching System (CLASS). Describes the
system switch fabric that allows multi-initiator access to the internal memory and devices
and enables high-bandwidth internal data transfers with few bottlenecks.
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„ Chapter 5, Reset. Covers reset sources, causes, and configurations; gives examples of
different reset configuration scenarios, including systems with multiple MSC8156
devices.
„ Chapter 6, Boot Program. Describes the bootloader program that loads and executes
source code to initialize the MSC8156 after it completes a reset sequence and programs its
registers for the required mode of operation. This chapter covers selection of bootloader
modes, normal sequence of events for bootloading a source program, and booting in a
multi-processor environment.
„ Chapter 7, Clocks. Contains an overview of the MSC8156 clock modules.
„ Chapter 8, General Configuration Registers. Contains a detailed description of the
general configuration registers.
„ Chapter 9, Memory Map. Defines the address spaces for all MSC8156 modules; includes
cross references to all registers discussed.
„ Chapter 10, MSC8156 SC3850 DSP Subsystem. Describes the structure of the DSP core
subsystem, which includes the SC3850 core, the instruction cache (ICache), the data cache
(DCache), L2/M2 memory, memory management unit (MMU), two 32-bit timers, the
embedded programmable interrupt controller (EPIC), and the on-chip emulator (OCE).
„ Chapter 11, Internal Memory Subsystem. Describes the structure and operation of the
L1 ICache, L1 DCache, L2/M2 memory, and M3 memory.
„ Chapter 12, DDR SDRAM Memory Controller. Describes the how the memory
controller interface works and how to program it. This interface increases the efficiency of
accesses through the DDR memory controller to external DDR memory.
„ Chapter 13, Interrupt Handling. Discusses the interrupt controllers that provide
maximum flexibility in handling MSC8156 interrupts, enabling interrupts to be handled
by the SC3850 cores internally, by an external host, or by a combination of the two; also
discusses source priority schemes.
„ Chapter 14, Direct Memory Access (DMA) Controller. Describes the different DMA
operating modes, transfer types, and buffer types. The chapter also gives procedures for
programming different types of transfers. The multi-channel DMA controller includes
hardware support for up to 16 time-multiplexed channels including buffer alignment. The
DMA controller supports flyby transactions on either bus. and enables hot swaps between
channels, by using time-multiplexed channels that impose no cost in clock cycles.
„ Chapter 15, High Speed Serial Interface (HSSI) Subsystem. Describes subsystem that
supports and multiplexes the Serial RapidIO, PCI Express, and SGMII signals across the
dual SerDes PHY ports and how the dedicated DMA controllers support the serial
RapidIO interfaces and PCI Express interface and how to program them.
„ Chapter 16, Serial RapidIO Controller. Describes the how the serial RapidIO interfaces
work and how to program them.
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„ Chapter 17, PCI Express Controller. Describes the how the PCI Express interface works
and how to program it.
„ Chapter 18, QUICC Engine Subsystem. Describes the QUICC Engine module, the
Ethernet controllers, and the serial peripheral interface (SPI). Detailed information is
referenced in the QUICC Engine™ Block Reference Manual with Protocol Interworking
(QEIWRM).
„ Chapter 19, TDM Interface. Describes the four TDM interfaces. Each can handle up to
256 bidirectional channels. The interfaces support the serial bus rate and format for most
standard TDM buses, including T1 and E1 highways, pulse-code modulation (PCM)
highway, and the ISDN buses in both basic and primary rates.
„ Chapter 20, UART. Describes the UART interface, which is a full-duplex serial port
used to communicate with other devices.
„ Chapter 21, Timers. Discusses the 32 identical 16-bit general-purpose timers residing in
two timer modules (A and B) that each have their set of configuration registers.
„ Chapter 22, GPIO. Discusses the thirty-two GPIO signals. Sixteen of the signals can be
configured as external interrupt inputs. Each pin is multiplexed with other signals and can
be configured as a general-purpose input, general-purpose output, or a dedicated
peripheral pin.
„ Chapter 23, Hardware Semaphores. Describes the function and programming of the
hardware semaphores, which control resource sharing.
„ Chapter 24, I2C. Describes the I2C interface. which allows the MSC8156 to boot from a
serial EEPROM device.
„ Chapter 25, Debugging, Profiling, and Performance Monitoring. Includes aspects of
the JTAG implementation that are specific to the SC3850 core and should be used with the
supporting IEEE® Std. 1149.1™ documentation. The discussion covers the items that the
standard requires to be defined and provides additional information specific to the
MSC8156 implementation. Also includes debugging resources available in the SC3850
DSP core subsystem, including the OCE modules, and L2 ICache module.
„ Chapter 26, Multi Accelerator Platform Engine, Baseband (MAPLE-B). Describes the
architecture, function, and register and memory structures used by the multi-accelerator
platform engine (MAPLE-B) for Turbo decoding, Viterbi decoding, Fast Fourier
Transform and Discrete Fourier Transform acceleration.
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Other MSC8156 Documentation
You can find the following documents on the Freescale Semiconductor web site listed on the
back cover of this manual.
„ MSC8156 Technical Data Sheet (MSC8156). Details the signals, AC/DC characteristics,
clock signal characteristics, package and pinout, and electrical design considerations of
the MSC8156 device.
„ QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM).
Describes all functional blocks supported by the QUICC Engine technology, provides
detailed programming registers and guidelines, and indicates which QUICC Engine
blocks and functionality are supported by specified Freescale products.
„ Application Notes. Cover various programming topics related to the StarCore DSP core
and the MSC8156 device.
Further Reading
The following documents are available with a signed non-disclosure agreement (see your
Freescale representative or distributor for details):
„ SC3850 DSP Core Reference Manual. Covers the SC3850 core architecture, control
registers, clock registers, program control, on-chip emulator (OCE), and instruction set.
„ SC3850 DSP Core Subsystem Reference Manual. Covers the SC3850 DSP core subsystem
which includes an SC3850 DSP core, a memory management unit (MMU), and instruction
channel with L1 ICache, a data channel with L1 DCache, an embedded programmable
interrupt controller (EPIC), real-time debug support with the core OCE and a JTAG
interface and a debug and profiling unit (DPU), and a dual timer.
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Document Change History
Revision
Date
Change Description
0
Sep 2010
Initial public release
1
Nov 2010
• Chapter 4, Chip-Level Arbitration and Switching System (CLASS).
– Removed all references to CLASS MBus Target Configuration Registers (C0MTCRn), CLASS
Start Address Decoder 7 (C0SAD7), CLASS End Address Decoder 7 (C0EAD7), and CLASS
Attributes Decoder 7 (C0ATD7).
– Added 4.3, MSC8151 Initiator CLASS Access Priorities.
• Chapter 6, Boot Program
–
–
–
–
Updated Figure 6-1.
Updated Steps 10 and 11 in Section 6.1.4, Multi Device Support for the I2C Bus, on page 6-4.
Updated Section 6.2.4.1, Serial RapidIO Without I2C Support, on page 6-21.
Updated Figure 6-10.
• Chapter 7, Clocks
– Added Clock Mode 19 to Table 7-1 and Table 7-2.
– Fixed RPTE field in figure layout in Section 7.2.2, Clock General Purpose Register 0
(CLK_GPR0), on page 7-5.
• Chapter 9, Memory Map
– Deleted C0MTCRn, C0SAD7, C0EAD7, C0ATD7, P0PCR, and P1PCR from Table 9-7.
• Chapter 13, Interrupt Handling
– Changed core mesh interrupts from level-only to level or edge in Table 13-6.
• Chapter 16, Serial RapidIO Controller
– Converted list of registers to Table 16-44.
– Removed references to Port [0–1] Physical Configuration Registers (PnPCR).
• Chapter 17, PCI Express Controller
– Added new section Section 17.4.1.9.15, PCI Express ACK Replay Timeout Register
(PEX_ACK_REPLAY_TIMEOUT)—0x434, on page 17-116.
• Chapter 25, Debugging, Profiling, and Performance Monitoring
– Removed references to trigger mode including PMLCB0.
– Updated the settings values for DP_TC[CSS] in Table 25-32.
– Updated the list of performance monitor events in Table 25-38.
2
Jun 2011
• Chapter 4, Chip-Level Arbitration and Switching System (CLASS)
– Remove the reference to Target Switch events from Table 4-2
• Chapter 8, General Configuration Registers
– Corrected PARTID value in System Part and Revision ID Register (SPRIDR).
• Chapter 12, DDR SDRAM Memory Controller
– Updated Figure 12-4 to change length of arrows between banks and total size of each bank
(from 64 Mbytes to 256 Mbytes).
– Changed heading of fourth and fifth columns in Table 12-3 from 32-bit to 64-bit.
• Chapter 15, High Speed Serial Interface (HSSI) Subsystem
– Added OCN-toMBus control registers in Section 15.8, HSSI Programming Model.
• Chapter 16, Serial RapidIO Controller
– Corrected DI value in DIDCAR..
• Chapter 26, Multi Accelerator Platform Engine, Baseband (MAPLE-B)
– Corrected the values and meanings of the DOSBY and DOSBI bits in Section 26.3.2.1.4,
Output Data Structure.
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1
Overview
The MSC8156 device is the fourth generation of Freescale high-end multicore DSP devices that
target the communications infrastructure and delivers the industry’s highest level of performance
and integration. It builds upon the proven success of the previous multicore DSPs and is designed
to bolster the rapidly changing and expanding wireless markets, such as 3GPP, TD-SCDMA,
3G-LTE, and WiMAX. The MSC8156 is carefully optimized for minimal cost, power, and area
per channel. The highly flexible, fully-programmable and powerful MSC8156 broadband
wireless access DSP offers tremendous processing power while maintaining a competitive price
and high performance.
The highly integrated MSC8156 DSP device includes the following:
„ Six StarCore® SC3850 DSP subsystems each running at up to 1 GHz with an architecture
optimized for wireless applications.
„ Two DDR2/3 memory controllers high-speed industry-standard memory interface.
„ Multi-Accelerator Platform Engine for Baseband (MAPLE-B) supports hardware
acceleration for Turbo decoding, Viterbi decoding, Fast Fourier Transform and Discrete
Fourier Transform algorithm processing.
„ High-Speed Serial Interface (HSSI) subsystem that supports
— Two serial RapidIO interfaces
— Two Gigabit serial Ethernet interfaces
— One PCI-Express controller
„ QUICC Engine RISC-based subsystem to guarantee reliable data transport over packet
networks while significantly off loading such processing from the DSP cores that
supports:
— Two gigabit Ethernet controllers with RGMII and SGMII support
— One SPI
„ Four 256-channel time-division multiplexing (TDM) interfaces
„ 16 bidirectional channels DMA controller
„ UART interface
„ I2C interface
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Overview
1.1
Features
The MSC8156 includes the following features:
„ StarCore DSP subsystem. The DSP subsystem includes:
— StarCore SC3850 core
• Running at up to 1 GHz
• Up to 8000 16-bit MMACS. A MAC operation includes a multiply-accumulate
command with the associated data moves and a pointer update.
• Backwards binary compatible with the SC140 and SC3400 architectures.
• Data Arithmetic and Logic Unit (DALU) containing 4 ALUs, each capable of
performing 2 16 × 16 multiply accumulate operations, effectively doubling the
performance of convolution-based kernels relative to the SC3400 core
• New instructions double the performance of complex and extended precision
multiplication.
• Address Generating Unit (AGU) containing 2 Address Arithmetic Units (AAU)
• Up to six instructions executed in a single clock cycle: 4 DALU and 2 AGU
instructions
• Variable-length Execution Set (VLES) execution model.
• 16 data registers, 40 bits each; 27 address registers, 32 bits each.
• Hardware support for fractional and integer data types.
• Four hardware loops with near-zero cycle overhead
• Very rich 16-bit wide orthogonal instruction set.
• Application specific instructions for Viterbi and Multimedia.
• Special SIMD (Single instruction, multiple data) instructions working on 2-word or
4-byte operands packed in a register, enabling to perform 2 to 4 operations per
instruction (8 to 16 operations per VLES)
• New dedicated instructions accelerate FFTs enabling a 40% cycle count reduction
and improved SNR
• User and Supervisor privilege levels, supporting a protected SW model
• New instructions and features to improve control code performance
• Precise exceptions for memory accesses enabling good RTOS support and Soft
Error corrections
• Branch Target Buffer (BTB) for acceleration of change of flow operations
— L1 ICache:
• 32 Kbytes
• 8 ways with 16 lines of 256 bytes per line
• Multi-task support
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Features
• Real-time support through locking flexible boundaries
• Line pre-fetch capability
• Software coherency support
• Software pre-fetch support by core instructions
— L1 DCache:
• 32 Kbytes
• 8 ways with 16 lines of 256 bytes per line
• Capable of serving two data accesses in parallel (XA, XB)
• Multi-task support
• Real-time support through locking flexible boundaries
• Software coherency support
• Writing policy programmable per memory segment as either write-back or
write-through
• 0.25 Kbytes Write-back Buffer (WBB)
• Six 64-bit entry WTB
• Line pre-fetch capability
• Software pre-fetch, synchronize, and flush support by core instructions
— Unified L2 Cache/M2 Memory:
• 512 Kbyte
• 8 ways with 1024 indexes and a 64 byte line
• Physically addressed
• Dynamically configured as a DMA accessible M2 Memory
• Maximum user flexibility for real time support through address partitioning of the
cache
• Support various write policies and methods to reduce cache inclusiveness
• Multi-channel, two dimensional software pre-fetch support
• Software coherency support with seamless transition from L1 cache coherency
operation.
— Memory management unit (MMU):
• Highly flexible memory mapping capability
• Provides virtual to physical address translation
• Provides task protection
• Supports multi-tasking
• Supports precise interrupts. Enabling to have an open RTOS.
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Overview
— Debug and Profiling Unit (DPU) block:
• Supports the debugging and profiling of the platform in cooperation with the OCE
Block
• Supports various breakpoint and event counting options
• Supports real-time tracing to the main memory with the Trace Write Buffer (TWB)
— Extended programmable interrupt controller (EPIC)
• 256 interrupts
• 32 priority levels with NMI support
— Two general-purpose 32-bit timers
— Low-power design with the following modes of operation:
• Wait processing state for peripheral operation
• Stop processing state
— ECC/EDC support.
„ Multi Accelerator Platform Engine for Baseband (MAPLE-B)
— Programmable System Interface
• Software friendly buffer descriptor based handshake and task assignment.
• Support for high priority and low priority tasks via multiple descriptor rings.
• Processing elements management and scheduling.
• Two master buses for data transfers from/to the system memory at total throughput
up to 50 Gbps.
• One slave bus for accessing MAPLE-B internal memories and registers.
• Multi-Core Aware.
• Interrupt or RapidIO Door Bell generation and/or status bit indication on job or
multiple jobs completion.
• System memory utilized only for input/output data, all the internal calculations are
performed using MAPLE-B memories.
— Turbo Decoding
• Scalable architecture with 1, 2 or 4 Radix 4 dual-recursion engines.
• Supports 3GPP-R6 turbo decoding as specified in 3GPP TS 25.212, section 4.2.3.2.
• Supports 3GPP2 turbo decoding as specified in 3GPP2 C.S002, section 2.1.3.1.4.2.
• Supports Wimax OFDMA turbo decoding as specified in IEEE® 802.16™-2004
standard and corrigendum IEEE P802.16-2004/Cor2/D2 standard, section
8.4.9.2.3.
• Supports 3GLTE (Evolved UTRA) turbo decoding as specified in 3GPP TS 36.212,
section 5.1.2.2.
• Programmable Number of Iterations
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Features
•
Multiple stop conditions, including built in CRC check and A-Posteriori Quality
Indication.
• Programmable de-puncturing schemes including support for rate-de-matching in
3GPP (and 3G LTE).
• Binary and Duo-Binary turbo codes.
• Support for trellis termination bits and tail biting.
• Decoding techniques using: Max Log Map or Linear Log Map (MAX*) including
extrinsic factorization.
• 8-bit soft symbol inputs with Hard or Soft decision outputs.
— Viterbi Decoding
• Supports 3GPP-R6 viterbi decoding as specified in 3GPP TS 25.212, section
4.2.3.1.
• Supports 3GPP2 viterbi decoding as specified in 3GPP2 C.S002, section
2.1.3.1.4.1.
• Supports Wimax OFDMA channel decoding as specified in IEEE 802.16-2004 and
corrigendum IEEE P802.16-2004/Cor2/D2, section 8.4.9.2.1.
• Supports 3GLTE (Evolved UTRA) channel decoding as specified in 3GPP TS
36.212, section 5.1.2.1.
• Fully programmable polynomials
• Programmable schemes for supporting various rates/puncturing cases (e.g. 1/2,
1/3).
• Support for zero tailing.
• Support for tail-bitting with multiple-iteration or WAVA* approaches.
• 8-bit soft symbol inputs with Hard or Soft decision outputs.
— FFT/iFFT and DFT/iDFT processing
• Variable lengths FFT/iFFT processing of lengths 128, 256, 512, 1024 and 2048.
• Variable lengths DFT/iDFT processing of the form 2k·3m·5n·12, up to 1536 points.
• Mixed radix implementation using R2, R3, R4, R5 and R8 building blocks.
• 16-bit I, 16-bit Q input, output and twiddles resolutions.
• Input and output I/Q samples are interleaved in memory.
• Internal twiddles memory.
— CRC processing with the following features:
• Four possible polynomials
• CRC check or CRC calculation for block sizes of up to 128 Kb
• Optional byte reverse CRC processing
• CRC processing with throughput of up to 12 Gbps at 450 MHz
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Overview
„
„
„
„
— When it is not required, the MAPLE-B power can be disabled internally to reduce
overall device power consumption.
Chip-level arbitration and switching system (CLASS)
— A full fabric that arbitrates between the DSP cores and other CLASS masters to the
core M2 memory, shared M3 memory, DDR SDRAM controllers, MAPLE-B, and the
device configuration control and status registers (CCSRs).
— High bandwidth.
— Non-blocking allows parallel accesses from multiple initiators to multiple targets.
— Fully pipelined.
— Low latency.
— Per target arbitration highly optimized to the target characteristics using prioritized
round-robin arbitration.
— Reduces data flow bottlenecks and enables high-bandwidth internal data transfers.
Internal memory. The 4608 Kbyte internal memory space includes:
— 32 Kbyte L1 ICache per core.
— 32 Kbyte L1 DCache per core.
— 512 Kbyte unified L2 Cache / M2 Memory per core.
— 1056 Kbyte shared M3 memory. 1024 Kbyte of M3 memory can be turned off to save
power, if necessary, which reduces the M3 memory size to 32 Kbyte.
— 96 Kbyte boot ROM accessible from the cores.
Clocks
— Three input clocks:
• Input clock.
• Two differential input clocks (one per each serial RapidIO PLL).
— Five PLLs:
• Three system PLLs
• Two Serial RapidIO PLLs.
— Clock ratios selected during reset via reset configuration pins.
— Clock modes user-configurable after reset.
Two DDR Controllers, each supporting:
— Up to 400 MHz clock rate (800 MHz data rate).
— Supports both DDR2 and DDR3 devices
— Programmable timing supporting both DDR2 and DDR3 SDRAM (but not
simultaneously)
— Support for a 64-bit data interface (72 bits including ECC), up to 800 MHz data rate,
for DDR2 and DDR3
— Support for a 32-bit data interface (40 bits including ECC), up to 800 MHz data rate,
for DDR2 and DDR3
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Features
— Full ECC support for single-bit error correction and multi-bit error detection up to the
maximum specified data rates for DDR2 and DDR3
— Two banks of memory via two chip selects. Each chip select supports up to 512
Mbytes, but the sum of the memory cannot exceed 512 Mbyte total (1 Gbyte total for
the two controllers).
— DRAM chip configurations from 64 Mbits to 4 Gbits with x8/x16 data ports
— Support burst lengths of 4 beats for DDR2 devices
— Support burst lengths of 4 (burst chop) and 8 beats for DDR3 devices
— Sleep mode support for self-refresh SDRAM
— On-die termination support
— Supports auto refreshing
— Support for both Unbuffered and Registered DIMMs
„ DMA Controller
— 32 unidirectional channels, providing up to 16 memory-to-memory channels.
— Buffer descriptor programing model.
— Up to 1024 buffer descriptors per channel direction provide a total of 32 Kbyte buffer
descriptors. Buffer descriptors can reside in M2 or DDR memories.
— Priority-based time-multiplexing between channels, using four internal priority groups
with round-robin arbitration between channels on equal priority group.
— Earliest deadline first (EDF) priority scheme that assures task completion on time.
— Flexible channel configuration with all channels supporting all features.
— A flexible buffer configuration, including:
• Simple buffers
• Cyclic buffers
• Single address buffers (I/O device).
• Incremental address buffers
• Chained buffers
• 1D to 4D buffers, optimized for video applications
• 1D or 2–4D complex buffers, a combination of buffer types
— Two external DMA request (DREQ) and two DONE signal lines that allow an external
device to trigger DMA transfers.
— High bandwidth
— Optimized for DDR SDRAM
„ High-Speed Serial Interface (HSSI)
— Serial RapidIO® Subsystem
• Two serial RapidIO ports supporting x1/x4 operation up to 3.125 Gbaud with a
RapidIO messaging unit and two RapidIO DMA units.
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1-7
Overview
•
Each x1/x4 serial RapidIO endpoint operates at 1.25/2.5/3.125 Gbaud and complies
with the following parts of Specification 1.2 of the RapidIO trade association
interconnect specification:
— Part I (input and output logical specifications)
— Part II (message passing logical specification)
— Part III (common transport specification)
— Part VI (physical layer x1 LP-serial specification)
— Part VIII (error management extension specification)
•
Each serial RapidIO port supports read, write, messages, doorbells, and
maintenance accesses:
— Small and large transport information field only
— All priorities flow
— Pass-through between the two ports that allows cascading devices using the
serial RapidIO and enabling message/data path between the two serial RapidIO
ports without core intervention. A message/data that is not designated for the
specific device passes through it to the next device.
•
RapidIO Messaging Unit supports:
— Two outbound message queues
— Two inbound message queues
— One outbound doorbell queue
— One inbound doorbell queue
— One inbound port-write queue
•
Each RapidIO DMA unit supports:
— Four high-speed/high-bandwidth channels accessible by local and remote
masters
— Basic DMA operation modes (direct, simple chaining)
— Extended DMA operation modes (advanced chaining and stride capability)
— Programmable bandwidth control between channels
— Up to 256 bytes for DMA sub-block transfers to maximize performance over
the RapidIO interface
— Three priority levels supported for source and destination transactions
— PCI-Express Controller
• Complies with the PCI Express™ Base Specification, Revision 1.0a
• Supports root complex (RC) and endpoint (EP) configurations
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Features
•
•
•
32- and 64-bit address support
x4, x2, and x1 link support
Supports accesses to all PCI Express memory and I/O address spaces (requestor
only)
• Supports posting of processor-to-PCI Express and PCI Express-to-memory write
• Supports strong and relaxed transaction ordering rules
• PCI Express configuration registers (type 0 in EP mode, type 1 in RC mode)
• Baseline and advanced error reporting support
• One virtual channel (VC0)
• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)
• Supports three inbound general-purpose translation windows and one configuration
window
• Supports four outbound translation windows and one default window
• Supports eight non-posted and four posted PCI Express transactions
• Supports up to six priority 0 internal platform reads and eight priority 0 to 2 internal
platform writes. (The maximum number of outstanding transactions at any given
time is eight.)
• Credit-based flow control management
• Supports PCI Express messages and interrupts
— Dual x4 SerDes Ports:
• Port 1 supports x4 serial RapidIO interface or x1 serial RapidIO interface and two
SGMII ports
• Port 2 supports x1/x4 serial RapidIO interface or x1/x2/x4 PCI Express interface
and two SGMII ports
„ The QUICC Engine subsystem includes dual RISC processors and 48-Kbyte multi-master
RAM to handle the Ethernet and SPI interfaces, thus off loading the tasks from the cores.
The three communication controllers support:
— Two Ethernet Controllers
• Two Ethernet physical interfaces:
— 1000 Mbps SGMII protocol using a 4-pin SerDes interface multiplexed through
the HSSI SerDes port.
— 1000 Mbps RGMII protocol
•
•
•
•
•
MAC-to-MAC connection in all modes
Full-duplex operations
Full-duplex flow control feature (IEEE Std. 802.3x™)
Receive flow control frames
Detection of all erroneous frames as defined by IEEE Std. 802.3®-2002
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Overview
•
•
•
•
•
•
•
•
•
•
•
•
•
Multi-buffer data structure
Diagnostic modes: Internal and external loopback mode and echo mode
Serial management interface MDC/MDIO
Transmitter network management and diagnostics
Receiver network management and diagnostics
VLAN Support
IEEE Std. 802.1p/Q™ QoS
Eight Tx/Rx queues
Queuing decision for IP/MAC/UDP filtering based on MAC destination addresses,
IP destination address, and UDP destination port
Programmable maximum frame length
Enhanced MIB statistics
Optional shift of data buffer by two bytes for L3 header alignments
Extended features
— IP header checksum verification and calculation
— Parsing of frame headers and adding a frame control block at the frame head,
containing L3 and L4 information for CPU acceleration
— Serial peripheral interface (SPI)
• Four-signal interface (SPIMOSI, SPIMISO, SPICLK and SPISEL)
• Full-duplex operation
• Works with 32-bit data characters, or with a range from 4-bit to 16-bit data
characters•Supports back-to-back character transmission and reception
• Supports master or slave SPI mode
• Supports multiple-master environment
• Continuous transfer mode for automatic scanning of a peripheral
• Maximum clock rate is (QUICC Engine clock)/8 in master mode and (QUICC
Engine clock)/4 in slave mode (not in back-to-back operation)
• Independent programmable baud rate generator
• Programmable clock phase and polarity
• Local loopback capability for testing
• Open-drain outputs support multimaster configuration
• Communication with Ethernet PHY for configuration and status (MIIMCOM-MII
management communication protocol)
• Multi-MIIMCOM environment with up to 32 PHYs
• Programmable clock gap between two characters in master mode
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Features
•
Controlled by the DSP cores and the QUICC Engine RISC processors according to
user configuration.
„ TDM
— Backward-compatible with the MSC8102/MSC812x/MSC814x TDM interface
— All the four TDM modules together support up to 1K time-slots for receive and 1K
time-slots for transmit
— Up to four independent TDM modules:
• Independent receive and transmit mode. Independent transmitter and receiver.
Transmitter input clock, output data, and frame sync can be configured as either
input or output. Up to 256 transmit channels and up to 256 receive channels.
Receiver input clock, input data, and input frame sync.
• Shared sync and clock mode. Two receive and two transmit links share the same
clock and frame sync. The sync can be configured as either input or output. Up to
128 transmit channels and 128 receive channels.
• Shared data link. Up to four full-duplex data links can operate as either transmit or
receive. All links have the same clock and frame sync. Each link supports up to 128
channels.
— Word size of 2, 4, 8, or 16-bit. All the channels share the same size.
— Hardware A-law/μ-law conversion
— Up to 62.5 Mbps data rate for all TDM modules
— Up to 16 Mbyte per channel buffer (granularity 8 bytes), where A/μ law buffer size has
double size (16-byte granularity)
— Separate or shared interrupts for receive and transmit with two programmable receive
and two programmable transmit thresholds for double buffering
— Each channel can be programmed as active or inactive
— Support either 0.5 ms (4 frames) or 1 ms (8 frames) latency
— Glueless interface to E1/T1 framers
„ I/O Interrupt Concentrator consolidates all chip maskable interrupt and non-maskable
interrupt sources and routes them to INT_OUT, NMI_OUT, and the cores.
„ UART
— Bit rate up to 6.25 Mbps
— Two signals for transmit data and receive data
— Full-duplex operation
— Standard mark/space non-return-to-zero (NRZ) format
— 13-bit baud rate selection
— Programmable 8-bit or 9-bit data format
— Separately enabled transmitter and receiver
— Programmable transmitter output polarity
— Separate receiver and transmitter interrupt requests
— Receiver framing error detection
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Overview
„
„
„
„
„
— Hardware parity checking
— 1/16 bit-time noise detection
— Single-wire and loop operations
Timers
— Two general-purpose 32-bit timers for RTOS support per SC3850 core
— Four TMR modules, each with the following features:
• Four 16-bit timers
• Cascadable timers
• Count up/down
• Programmable count modulo
• Count once or repeatedly
• Counters are preload able
• Compare registers can be preloaded
• Counters can share available inputs
• Separate prescaler for each counter
• Each counter has capture and compare capability
• Can use one of the following clock sources: system clock, TDM clock input, or
external clock input
— Eight software watchdog timer (SWT) modules
Eight programmable hardware semaphores, locked by simple write access without need
for read-modify-write operation by the DSP core.
Virtual interrupts
— Generation of 32 virtual interrupts by a simple write access
— Generation of virtual NMI by a simple write access
I2C interface
— Two-wire interface
— Multi-master operational
— Calling address identification interrupt
— START and STOP signal generation/detection
— Acknowledge bit generation/detection
— Bus busy detection
— Programmable clock frequency
— On-chip filtering for spikes on the bus
General-purpose input/output (GPIO) ports:
— 32 GPIO ports
— Each GPIO port can either serve the on-device peripherals or act as a programmable
I/O pin
— Sixteen GPIO pins can be configured as external interrupt inputs
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Block Diagram
— All ports are bidirectional
— All ports are set as GPIO inputs at system reset
— All port values can be read while the pin is connected to an internal peripheral
— All ports have open-drain output capability
„ Boot interface options:
— Ethernet
— Serial RapidIO interface
— I 2C
— SPI
„ JTAG. Test Access Port (TAP) and Boundary Scan Architecture designed to comply with
IEEE Std. 1149.1™.
„ Reduced power dissipation
— Very low power CMOS design
— Low-power standby modes
— Optimized power management circuitry (instruction-dependent, peripheral-dependent,
and mode-dependent)
— Technology: The MSC8156 device is manufactured using CMOS 45 nm SOI
technology.
1.2
Block Diagram
A block diagram of the MSC8156 is shown in Figure 1-1.
DDR Interface 64/32-bit
JTAG
DDR Interface 64/32-bit
DDR
Controller
DDR
Controller
I/O-Interrupt
Concentrator
M3 Memory
1056 Kbyte
UART
Clocks
Timers
CLASS
Reset
High-Speed Serial Interface
DFT/
IDFT
FFT/
IFFT
DMA
MAPLE-B
32 Kbyte 32 Kbyte
L1
L1
ICache DCache
Turbo/
Viterbi
4 TDMs
SC3850
DSP Core
QUICC Engine
Subsystem
DMA
RMU
Dual RISC Processors
SGMII
SPI Ethernet Ethernet
DMA
Serial Serial
PCI
RapidIO RapidIO Expr
x2
512 Kbyte
L2 Cache / M2 Memory
SerDes 1
Six DSP Cores at 1 GHz
Four TDMs 256-Channels each
SPI RGMII RGMII
Note: The arrow direction indicates master or slave.
SerDes 2
Semaphores
Virtual
Interrupts
Boot ROM
I2C
Other
Modules
x4 3.125 Gbaud
PCI-EX x1/x2/x4
Two SGMII
x4 3.125 Gbaud
Two SGMII
Figure 1-1. MSC8156 Block Diagram
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Overview
1.3
Architecture
The MSC8156 architecture is carefully optimized to achieve the maximum channel density for a
given device area, power, and cost. Also, the MSC8156 is a derivative of the same system
internal platform Freescale uses to implement new DSPs. Therefore, Freescale can swiftly spin
off DSP devices from the same platform and provide the customer with familiar modules and
programming models.
1.4
StarCore SC3850 DSP Subsystem
Figure 1-2 shows the block diagram of the StarCore SC3850 DSP subsystem, which contains
the SC3850 core, the ICache, the DCache, the MMU for task and memory protection and address
translation and two write buffers. In addition, there is an interrupt controller, two timers, a debug
and profiling unit, and a trace write buffer. The SC3850 core fetches instructions through a
128-bit wide program bus (P-bus), and it fetches data through two 64-bit wide data buses (Xa-bus
and Xb-bus). After a brief overview of the DSP platform, this section presents a subsection on
each part of the platform.
128 bits master
bus to CLASS
128 bits slave
bus from CLASS
Interrupts
512 Kbyte L2 Cache / M2 Memory
IQBus
EPIC
Timer
DQBus
TWB
Task
Protection
Debug Support
OCE30 DPU
SC3850
Core
32 Kbyte
Instruction
Cache
WriteThrough
Buffer
(WTB)
32 Kbyte
Data
Cache
WriteBack
Buffer
Address
Translation
(WBB)
MMU
P-bus
Xa-bus
Xb-bus
Figure 1-2. StarCore SC3850 DSP Subsystem Block Diagram
Instruction/data read accesses are performed as follows:
„ Non-cacheable instructions/data are read from the target memory (for example, M2
memory).
„ Cacheable instructions/data are read from the ICache/DCache. If they do not reside in the
cache (a miss), they are first fetched directly from the target memory.
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StarCore SC3850 DSP Subsystem
There are three write policies when writing data outside the core:
„ Cacheable write-back. Information is written only to the cache. The modified cache lines
are written to main memory only when they are replaced. The subsequent write-back
buffer is combined with the write-allocate write-miss policy in which the required lines
are loaded to the cache whenever a write-miss occurs.
„ Cacheable write-through. Both the cache and the higher-level memory are updated during
every write operation. In the StarCore SC3850 DSP subsystem, the write-through buffer is
a non-write allocate buffer. Therefore, a cacheable write-through access does not update
the cache unless there is a hit.
„ Non-cacheable. The write is direct to memory and is not written to the cache. A hazard
mechanism ensures that read accesses read updated data.
The DSP subsystem supports a Real-Time Operating System (RTOS) as follows:
„
„
„
„
Virtual-to-physical address translation in the MMU.
Two privilege levels: user and supervisor.
Memory protection.
Precise exceptions upon an MMU violation enabling dynamic memory management.
The embedded programmable interrupt controller (EPIC) handles up to 256 interrupts with 32
priorities, 222 of which are external platform inputs.
1.4.1 Enhancements
Table 1-1 summarizes the major improvements and benefits of the SC3850 DSP core and
subsystem. For enhancement details, see the SC3850 DSP Core Reference Manual.
Table 1-1. SC3850 DSP Core and Subsystem Major Benefits
No.
Feature
Type
DSP/Control
Highlights
Benefit
• Eight 16 × 16 multiplications per
cycle
• Complex operations
• Mixed/Double precision
multiplications support
Double the throughput of convolution
based kernels, complex arithmetics,
and mixed/double precision
multiplications
• Parallel condition computation
Accelerate decision making in control
code
Both
•
•
•
•
HW loop stall removal
BTB enlargement
Deeper speculation depth
Misc. stall reductions
Significant control cycle improvements
and a friendlier compiler target
Both
• Low latency
• Unified program and data
Significant out-of-the-box improvement
1
Dual Multiply
ALU
DSP
3
Condition
Handling
instruction set
architecture
Control
4
Microarchitecture
core stall
reduction
5
Private L2 cache
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Overview
Table 1-1. SC3850 DSP Core and Subsystem Major Benefits (Continued)
Type
DSP/Control
No.
Feature
Highlights
Benefit
6
Cache instruction
set architecture
Both
• Cache fetch
• Cache flush/sync
• Cache allocation
Significant increase in core utilization
Simplified cache coherency
management
7
Microarchitecture
cache stall
reduction
Both
• Write stall hiding
• Read contention buffer
Significant increase in core utilization
1.4.2 StarCore SC3850 DSP Core
The SC3850 core is a flexible, programmable DSP core that handles compute-intensive
communications applications, providing high performance, low power, and high code density. It
is fully binary-backward compatible with the MSC8101, MSC8102, MSC8103, MSC8112,
MSC8113, MSC8122, MSC8126, MSC8144, and MSC8144E DSPs, and it introduces many new
features and enhancements.
The SC3850 core includes a data arithmetic logic unit (DALU) that contains four arithmetic logic
units (ALUs). The core also includes an address generation unit (AGU) that contains two address
arithmetic units. The SC3850 efficiently deploys the variable-length execution set (VLES)
execution model, allowing grouping of up to 4 DALU and 2 AGU instructions in a single clock
cycle without sacrificing code size for unused execution slots.
Each ALU has two 16-bit × 16-bit multipliers and a 40-bit accumulation capability, a 40-bit
parallel barrel shifter and a 40-bit adder/subtractor. Each ALU performs one MAC operation per
clock cycle, so a single core running at 1 GHz can perform up to 8 GMACS. Each AAU in the
AGU can perform one address calculation and drive one data memory access per cycle. Data
access widths are flexible from 8 to 64 bits. The AGU can support a throughput of up to 128
Gbps between the core and the memory.
Arithmetic operations use both fractional and integer data types, enabling the user to choose an
individual style of code development or to use coding techniques derived from an
application-specific standard. Parts of many algorithms use data with reduced width such as 8 or
16 bits. For better efficiency, the SC3850 core also supports single-instruction multiple-data
(SIMD) instructions working on 2-word or 4-byte operands packed in a register. This packing
allows the core to perform 2 to 4 operations per instruction (a maximum of 10 to 18 operation per
VLES including AGU operations).
A new dual 20-bit packed data format enables you to accumulate two multiplication results from
the dual multiply ALU into a single register with guard bits. Alternatively, accumulation of both
multiplies can be combined into a single 40-bit accumulator (dot product). In addition, the
SC3850 supports special instructions to support special operations, such as Viterbi and video
applications.
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StarCore SC3850 DSP Subsystem
Although the SC3850 is a DSP, the rich instruction set also gives special attention to control
code, making the SC3850 core ideal for applications that embed DSP and communications
operations as general control code. Among the features that support control code are the
interlocked pipeline that solves dependency hazards. The powerful SC3850 compiler translates
code written in C/C++ into parallel fetch sets and maintains high code density and/or high
performance by taking advantage of these features and the compiler-friendly instruction set. Even
compiled pure control code yields results with high code density.
The SC3850 core supports general micro-controller capabilities, making it a suitable target for
advanced operating systems. These capabilities include support for user and supervisor privilege
levels that enable (with the off-core MMU) a protected software model implementation. Precise
exceptions for memory accesses allow implementation of advanced memory management
schemes and soft error correction.
The SC3850 core includes a dynamic branch prediction mechanism that contains a 48-entry
branch target buffer (BTB) to improve performance by reducing the change of flow latency.
1.4.3 L1 Instruction Cache
The instruction channel, which comprises the instruction cache (ICache) and the instruction fetch
unit (IFU), provides the core with instructions that are stored in higher-level memory. The ICache
operates at core speed and stores recently accessed instructions. Whenever an addressed
instruction (from the cacheable memory area) is found in the array, it is immediately made
available to the core (ICache hit). When the required address is not found in the array, it is loaded
to the ICache from the external (off-subsystem) memory by the IFU (ICache miss). The IFU
operates in parallel with the core to implement a HW line prefetching algorithm that loads the
ICache with information that has a high probability of being needed soon. This action reduces the
number of cache misses. When an instruction is addressed from a non-cacheable area, the IFU
fetches it directly to the XP bus of the core without writing it to the cache.
1.4.4 L1 Data Cache
The data channel comprises the data cache (DCache), the data fetch unit (DFU), the data control
unit (DCU), the write-back buffer (WBB), and the write-through buffer (WTB). This two-way
channel reads and writes information from the core to/from higher-level memory (M2 or L2) and
control memory (internal blocks and external peripherals) spaces.
The DCache, which operates at core speed, keeps the recently accessed data. When addressed
data (from a cacheable memory area) is found in the array, it is immediately made available to the
core (DCache hit) in a read and updated if written to. When the required address is not found in
the array, a DCache miss occurs, and the DFU loads the data to the DCache from the external
(off-subsystem) memory and drives it to the core. The DFU operates in parallel with the core and
implements a HW line prefetch algorithm that loads the DCache with information that has a high
probability of being needed soon, thus reducing the number of data cache misses.
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Overview
The channel differentiates between cacheable and non-cacheable addresses. For cacheable
addresses, it supports the write-back allocate and write-through writing policies. The selection is
made on an address segment basis, as programmed in the MMU. The data channel supports the
arrangement of data in big-endian formats. Core data types can be byte, word, long (4 bytes), or 2
long (8 bytes) wide.
1.4.5 L2 Unified Cache/M2 Memory
The L2 cache processes data and program accesses to the external M3/DDR memory. Caching
the accesses requested by the L1 subsystem reduces the average penalty of accessing the high
latency M3. The L2 cache includes a slave arbitration and tag unit, cache logic and arrays, along
with a write buffer for write back and write through accesses, fetch logic to fetch data from the
off platform memory upon a miss or a non-cacheable access, and a master arbiter that arbitrates
between the different internal units.
1.4.6 Memory Management Unit (MMU)
The MMU performs three main functions:
„ Memory hardware protection for instruction and data access with two privilege levels
(user and supervisor).
„ High-speed address translation from virtual to physical address to support memory
relocation.
„ Cache and bus controls for advanced memory management
Memory protection increases the reliability of the system so that errant tasks cannot ruin the
privileged state and the state of other tasks. Program and data accesses from the core can occur at
either the user or supervisor level. The MMU checks each access to determine whether it matches
the permissions defined for this task in the memory attributes and translation table (MATT). If it
does not, the access is killed and a memory exception is generated.
1.4.7 Debug and Profiling Unit (DPU)
The on-chip emulator (OCE) and the debug and profiling unit (DPU) are hardware blocks for
debugging and profiling. The OCE performs the following tasks:
„ Communicates with the host debugger through the SoC JTAG test access port (TAP)
controller
„ Enables the SC3850 core to enter the debug processing state upon a varied set of
conditions to:
— Single step
— Execute core commands inserted from the host debugger to upload and download
memory and core registers.
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MAPLE-B
„ Sets up to six address-related breakpoints on either PC or a data address
„ Sets a data breakpoint on a data value, optionally combined with a data address
„ Generates the PC tracing flow, optionally filtered to a subset of events such as only
jumps/returns from subroutine, interrupts, and so on.
The DPU has the following characteristics:
„ Enables parallel counting of subsystem events in six dedicated counters, from more than
40 events
„ Filters, processes, and adds task ID and profiling information on the OCE PC trace
information
1.4.8 Extended Programmable Interrupt Controller
The internal extended programmable interrupt controller (EPIC) manages internal and external
interrupts. The EPIC handles up to 256 interrupts, 222 of which are external subsystem inputs.
The rest of the interrupts serve internal subsystem conditions. The external interrupts can be
configured as either maskable interrupts or non-maskable interrupts (NMIs). The EPIC can
handle 33 levels of interrupt priorities, of which 32 levels are maskable at the core and 1 level is
NMI.
1.4.9 Timer
The timer block includes two 32-bit general-purpose counters with pre-loading capability. It
counts clocks at the core frequency. It is intended mainly for operating system use.
1.5
MAPLE-B
The MAPLE-B is a baseband algorithm accelerator for Turbo, Viterbi, FFT/iFFT, and DFT/iDFT
algorithms The MAPLE-B consists of a programmable-system-interface (PSIF) that is a
programmable controller with DMA capabilities and three accelerators attached to it using an
internal interface:
„
„
„
„
Turbo/Viterbi Processing-Element (TVPE)
FFT Processing-Element (FFTPE)
DFT Processing-Element (DFTPE)
CRC Processing-Element (CRCPE)
The PSIF has two 64-bit wide MBus master ports used to transfer input and output data to and
from system memory and a 64-bit MBus Slave port that allows any core to access its internal
memories. Through this port, the cores can perform any of the following functions:
„ Place buffer-descriptors in the PSIF internal memory.
„ Access the MAPLE-B parameter RAM.
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Overview
„ Access the PSIF internal registers using the SBus.
„ Access the process element (PE) configuration registers.
1.6
Chip-Level Arbitration and Switching System (CLASS)
The CLASS is the central internal interconnect system for the MSC8156 device. The CLASS is a
non-blocking, full-fabric interconnect that allows any initiator to access any target in parallel
with another initiator-target couple. The CLASS uses a fully pipelined low latency design. The
CLASS demonstrates per-target prioritized round-robin arbitration, highly optimized to the target
characteristics. The CLASS operates at 500 MHz, and is separate from the SC3850 core
frequency to provide an optimized trade-off between power dissipation, memory technology, and
miss latency. Controlling the intradevice data flow, the CLASS reduces bottle necks and permits
high bandwidth fully pipe-lined traffic.
The CLASS initiators are:
„
„
„
„
„
Six SC3850 DSP subsystems
Two MAPLE-B ports
HSSI
Peripheral group (TDM, QUICC Engine subsystem, and JTAG)
Two DMA ports
The CLASS targets are:
„
„
„
„
„
1.7
Configuration control and status registers (CCSRs)
MAPLE-B
Three core ports (each shared by two cores)
Two DDR controllers
M3 memory
M3 Memory
The 1056 KB M3 memory can be used for both program and data and eliminates the need for an
external memory in a variety of applications, thus reducing board space, power dissipation, and
cost. The M3 memory has a 128-bit wide port and runs at 500 MHz using dense memory
technology. The M3 memory supports partial, full, and burst accesses. The M3 memory includes
hidden refresh with a low probability of conflict with core accesses, and it supports burstable
accesses. If the full M3 memory is not required, power can be turned off to 1024 MB to reduce
power consumption.
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Clocks
1.8
Clocks
The MSC8156 device has three input clocks:
„ A shared input clock.
„ Two differential input clock for HSSI dual-SerDes port interface.
The MSC8156 device includes five PLLs:
„ Three system PLLs to support the different internal system clock requirements required by
the peripherals and interfaces.
„ Two SerDes PLLs.
The ratios between the system clocks are selected during reset via reset configuration pins. The
clock ratios are selected from a fixed table called clock modes table. The clock modes can be
changed by the user after reset.
1.9
DDR Controllers (DDRC1 and DDRC2)
The DDR SDRAM interface is useful when the channel storage size is relatively big (as for a
modem) and also when more channels are required to supplement the internal memory. When the
MSC8156 device works with channel data stored in the DDR SDRAM, the DMA controller can
swap the data to and from the M2 memory, thus enabling the L1 DCache to fetch from M2
memory instead of accessing the DDR SDRAM memory directly. Fetch latency is thus reduced,
significantly improving the average clock cycles required per task. The M2 and M3 memories are
large enough to accommodate the number of channels processed by the DSP subsystems for a
variety of packet telephony and wireless transcoding application, such as basic G.711 voice
coding, G.729 or G.723 premium voice coding, AMR, and EFR. However, it is not large enough
for such memory-consuming applications as a V.90 modem, especially when high channel
densities are required. For these applications, the MSC8156 can interface with JEDEC-compliant
DDR2 or DDR3 SDRAM devices. A DDR SDRAM can be used not only as an extension for the
M2 and M3 memories but also to store code. In a typical application, infrequently used code is
either swapped into M2/M3 memory when needed or executed directly from an external DDR
SDRAM. The DDR SDRAM interface frequency is decoupled from the DSP subsystem
frequency, and it has a separate PLL to deliver the required frequency according to the bandwidth
requirements. It is 16/32 bits wide and can interface with up to two 16-bit wide devices, or four
8-bit wide devices. It has a separate strobe per byte. Two logical banks (chip select) are
supported, each with logical programmable bank start and end addresses. A bank size of up to
128 MB is supported. Programmable parameters allow for a variety of SDRAM organizations
and timings. Using data mask bits, the SDRAM controller enables partial write operations to
bytes in a word or words in a burst. Optional ECC protection is provided for the DDR SDRAM
data bus. Using ECC, the memory controller detects all two-bit errors and corrects all single-bit
errors within the 32-bit data bus. For ECC, an additional ECC DDR SDRAM device is usually
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Overview
needed. Both the data DDR SDRAM and the ECC DDR SDRAM should have the same CAS
latency. There is page retention for up to four simultaneous open pages, and the number of clocks
for which the pages are kept open is programmable. Pages are replaced using a pseudo-LRU
replacement algorithm.
1.10
DMA Controller
The DMA controller enables data movement and rearrangement while the DSP cores work
independently. The DMA controller transfers blocks of data to and from the M2 memory, M3
memory, and the DDR SDRAM controller. It has 16 high-speed bidirectional channels and can
be commanded from each of the DSP subsystems, as well as from an off-device initiator through
the RapidIO or PCI using BDs. All channels are capable of complex data movement and
advanced transaction chaining. Operations such as descriptor fetches and block transfers are
initiated by each of the sixteen channels. Full duplex operation allows the DMA controller to read
data from one target and store it in its internal memory while concurrently writing another buffer
to another a target. This capability can be used extensively when data is read from the M3
memory and written into the M2 memory. The bidirectional DMA controller reads from one of
the CLASS target ports while writing to the second one. The DMA controller supports smart
arbitration algorithms such as round robin, bandwidth control, and a timer-based mechanism
using an earliest deadline first (EDF) algorithm.
1.11
High Speed System Interface
The High Speed Serial Interface (HSSI) is a 8-port (two x4 SerDes PHYs) serial communications
subsystem that supports the following multiplexed serial interface combinations:
„
„
„
„
Two x1/x4 Serial RapidIO ports
One x1/x4 Serial RapidIO ports, one x1 Serial RapidIO port, and two SGMII ports
One x1/x4 Serial RapidIO port and a PCI Express port
One x1 Serial RapidIO port, two SGMII ports, and a PCI Express port
To support these interfaces, the HSSI includes the following blocks:
„ One RapidIO controller with two ports and one RapidIO Messaging Unit (RMU)
„ One PCI Express controller with a bridge to the OCN fabric.
„ One 8-port OCN fabric with two DMA controllers to connect between the RapidIO and
PCI Express controllers and the system CLASS module
„ Two SRIO port controllers to link the RMU and OCN fabric to the SerDes ports.
„ Two SerDes interfaces to connect to the external signal interface.
These communication interfaces allow the cores to execute the data processing code and be
relieved from the data transfer and handling overhead for processing serial data flow.
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High Speed System Interface
Figure 1-3 shows a block diagram of the HSSI.
HSSI to MBus Bridge
HSSI
OCNDMA0
DMA to OCN
Bridge
OCN to MBus
Bridge
DMA to OCN
Bridge
Port 2
Port 3
Port 6
Port 7
Port 1
OCN Fabric
Port 0
Port 4
Port 5
PCI Express
to OCN Bridge
RMU
SerDes 1
SRIO0
PHY1
PCI Express
SRIO1
SerDes 2
Serial RapidIO x4 Interface at 3.125 Gbaud
or two SGMII
PHY2
QUICC Engine Subsystem
QUICC Engine Subsystem
OCN to MBus
Bridge
OCNDMA1
Serial RapidIO x4 Interface at 3.125 Gbaud
or PCI-Express
Figure 1-3. HSSI Block Diagram
1.11.1 Serial RapidIO Subsystem
RapidIO is a high-performance, point-to-point, low-pin-count, packet-switched system-level
interconnect that can be used in a variety of applications as an open standard. The RapidIO
architecture provides a rich variety of features including high data bandwidth, low-latency
capability, and support for high-performance I/O devices, as well as providing message-passing
and software-managed programming models. The Serial RapidIO subsystem consists of a Serial
RapidIO controller supporting two ports and a RapidIO Message Unit (RMU). The MSC8156
device can either connect directly to a host or to a Serial RapidIO switch. Each port in the switch
is point-to-point connected to the MSC8156 device through a serial RapidIO link. This link
typically carries packets in both directions. Packets ready for processing are transported from the
host to the MSC8156, and the processed packets are transported from the MSC8156 back to the
host.
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Overview
1.11.1.1 Serial RapidIO and Host Interactions
The Serial RapidIO controller directs the traffic flow between a host processor and the MSC8156
device through the RMU. The host and the MSC8156 communicate as follows:
„ The host may send messages to the destination MSC8156 device, which are sent back to
the host after processing along with a short doorbell interrupt to indicate that the packets
have been processed.
„ Messages eliminate the latency of read accesses. The host writes to the MSC8156 and the
MSC8156 writes to the host. In addition, messages can be used in applications where the
host does not know the internal memory structure of the target DSP.
„ The host may directly access the data in the MSC8156 memory for both reads and writes.
It handshakes with the software running on a DSP core through a ring of descriptors in
MSC8156 memory.
„ The host may access the data in MSC8156 memory for both reads and writes, but instead
of maintaining a ring of descriptors in the MSC8156 memory, it uses buffer descriptors
(BDs) that are messaged from the DSP core to the host.
„ The host may put all the data buffers into its memory and have the MSC8156 access the
data.
„ Any initiator on the RapidIO system can access any internal memory space as well as the
DDR SDRAM using NREAD, NWRITE, MESSAGE, and DOORBELLS. In addition, it
can configure the RapidIO messaging and configuration unit using MAINTENANCE
packets.
In the receive path, the following steps occur:
1.
The clock is recovered using a dedicated PLL.
2.
The data is deserialized, 8b/10b decoded, checked for the correct CRC, and passed to
the higher-level protocol logic.
3.
The control symbols are stripped and used to interface with the other peers without core
intervention.
4.
NWRITE packets are written to the destination memory.
5.
MESSAGES are directed to the RapidIO messaging unit from which they are forwarded
to their destination queue/memory location.
6.
RESPONSE messages are associated with their respective NREAD and go back to the
internal initiator that initiated the transaction.
On the transmit path, packets are buffered. The CRC is calculated and arbitration is performed
between packet data and control symbols. The data stream then passes through the 8b/10b
encoder and the serializer and transmitted on the RapidIO link. The RapidIO endpoints support
link initialization and training according to the RapidIO specification. The buffers in the RapidIO
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Freescale Semiconductor
High Speed System Interface
endpoints support packets of up to 256 bytes and four priority levels for both the receive and the
transmit.
1.11.1.2 RapidIO Messaging Unit (RMU) Operation
The messaging unit is divided into five parts:
„
„
„
„
„
Inbound message controllers.
Outbound message controllers.
Inbound doorbell controllers.
Outbound doorbell controller.
Inbound maintenance controller.
The message receiver performs the following steps:
1.
Filters the received packets into multiple queues (controllers) based on selected
(programmable) fields in the RapidIO message header (for example, mailbox number
and letter number). This filtering mechanism can be used for filtering the messages to
the different SC3850 cores or filtering the messages according to their size to the right
queue.
2.
Writes the message to a receive buffer pre-allocated by the SC3850 core.
3.
Post-increments the buffer write pointer.
4.
Optionally interrupts the SC3850 core. The core can then read the buffer, process the
message data, and update the read pointer of the buffer by writing it to the messaging
controller.
The doorbell receiver functions in much the same way except for filtering according to a selected
field in the header only.
The message transmitter performs the following steps:
1.
The SC3850 core sets the registers in the controller with the message parameters (read
pointer, message length, destination, buffer size, available messages.)
— Optionally, the SC3850 core initiates only a pointer to a BD queue.
— The messaging controller reads the BD that includes the message parameters.
2. The controller reads data from memory according to predefined parameters.
3.
The controller encapsulates the message and transfer it to a RapidIO endpoint.
4.
The RapidIO endpoint sends the message.
5.
Acknowledges are transferred from the RapidIO endpoint to the RMU.
6.
Upon completion of a message the controller can:
— Send an interrupt to the core, waiting for a new sets of parameters.
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1-25
Overview
— Proceed to the next message in queue according to the previous parameters.
— Proceed to the next BD in queue.
The doorbell transmitter performs the following steps:
1.
The SC3850 core sets the registers in the controller with the doorbell parameters
(doorbell data, destination)
2.
The controller encapsulates the doorbell and transfers it to the RapidIO endpoint.
3.
The RapidIO endpoint sends the message.
4.
Acknowledges are transferred from the RapidIO endpoint to the RMU.
5.
Upon completion of a message the controller can send an interrupt to the SC3850 core
and wait for a new sets of parameters.
1.11.2 PCI Express
The PCI Express controller connects to a 2.5-GHz serial interface configurable for up to a x4
interface. As both an initiator and a target device, the PCI Express interface is capable of
high-bandwidth data transfer and is designed to support next generation I/O devices. When
selected and enabled by the device configuration, the PCI Express interface performs link width
negotiation and exchanges flow control credits with its link partner after it completes its reset
sequence. Once link autonegotiation is successful, the controller is available to transfer data.
The PCI Express controller can be configured to operate as either a PCI Express root complex
(RC) or an endpoint (EP) device. An RC device connects the core processor/memory subsystem
to I/O devices while an EP device typically denotes a peripheral or I/O device. In RC mode, a
PCI Express type 1 configuration header is used; in EP mode, a PCI Express type 0 configuration
header is used.
As an initiator, the PCI Express controller supports memory read and write operations with a
maximum transaction size of 256 bytes. In RC mode, the controller also supports configuration
and I/O transactions. As a target interface, the PCI Express controller accepts read and write
operations to local memory space. When configured as an EP device, the PCI Express controller
accepts configuration transactions to the internal PCI Express configuration registers. Message
generation and acceptance are supported in both RC and EP modes. Locked transactions and
inbound I/O transactions are not supported.
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Freescale Semiconductor
High Speed System Interface
1.11.3 OCN-DMA Controllers
The MSC8156 includes two dedicated DMA controllers that transfer blocks of data between the serial
RapidIO controller and the PCI Express controller and the local address space independent of the DSP
cores. This offloads the data management processing from the cores. Each dedicated DMA
controller offers the following features:
„
„
„
„
„
„
„
„
„
Four high-speed/high-bandwidth channels accessible by local and remote masters
Basic DMA operation modes (direct, simple chaining)
Extended DMA operation modes (advanced chaining and stride capability)
Cascading descriptor chains
Misaligned transfers
Programmable bandwidth control between channels
Three priority levels supported for source and destination transactions
Interrupt on error and completed segment, list, or link
An Address Translation Management Unit (ATMU) with 10 local access address
windows. The ATMU translates a request address into a logical device source/destination.
1.11.4 OCN Fabric
The On-Chip Network (OCN) fabric is a non-blocking high speed interconnect used for
embedded system devices. The MSC8156 DSP HSSI uses an 8-port OCN to connect between the
Serial RapidIO Controller, the PCI Express controller, the two supporting DMA controllers and
the dual SerDes PHYs. The OCN requires no programming and provides a seamless interface for
the HSSI.
1.11.5 SRIO Port Controller Modules (SRIOn)
The SRIO0 and SRIO1 modules provide an interface bridge between the RMU and the two
SerDes PHYs. The units require no programming, but transfers through the SRIO modules can be
tracked by the performance monitor.
1.11.6 SerDes PHY Interfaces
The HSSI includes two 4-port SerDes interfaces that are multiplexed between the two Serial
RapidIO ports, the PCI Express port, and the two SGMII ports from the QUICC Engine
subsystem. Multiplexing configuration is done using the HSSI general configuration registers.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
1-27
Overview
1.12
QUICC Engine Subsystem
The MSC8156 QUICC Engine module is a versatile communications engine based on a subset of
the MPC83XX QUICC Engine subsystem that integrates several communications peripheral
controllers. The QUICC Engine module combines interface hardware and RISC firmware to
support multimedia packet operations. The QUICC Engine module includes control registers and
an interrupt controller to allow the DSP cores to control and monitor operations. These registers
configure certain global options and create specific commands related to the communication
protocols. The cores issue commands by writing to the QUICC Engine module Command
Register (QECMDR). These commands are used to initialize the RISC processors and each
specific communications controller while the RISC engines are running. The QUICC Engine
module includes various blocks to provide the system with an efficient way to handle data
communication tasks, including:
„ Two RISC processors, each of which provide:
— One instruction per clock
— Code execution from internal ROM or multi-port RAM
— 32-bit RISC architecture
— Up to sixteen internal software timers maintained in the multi-port RAM
— Interface with the core processors through a 48-KB dual-port RAM and virtual DMA
channels for each interface controller
— Ability to handle serial protocols and virtual DMA
„
„
„
„
Multi-initiator 48-KB multi-port RAM
48-KB instruction RAM (IRAM)
Serial DMA channel
Three full-duplex communications controllers:
— Communications controllers 1 and 3 support IEEE 802.3/Fast Ethernet controllers
„ Interrupt controller
„ Multiplexer and timers logic
„ Baud-rate generators
The internal clocks (RCLK/TCLK) for each communications controller can be programmed to
use either an external or internal source. The rate of these clocks can be up to one-half of the
QUICC Engine module clock frequency. However, the ability of an interface to support a
sustained bit stream depends on the protocol settings and other factors.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
QUICC Engine Subsystem
Figure 1-4 shows the MSC8156 QUICC Engine module block diagram.
CLASS
32-Bit
RISC
Processor
ROM
32-Bit
RISC
Processor
SDMAs
Multi-Initiator
RAM 48 KB
ROM
IRAM
Peripheral Bus
Ethernet
Controller
Ethernet
Controller
RGMII/SGMII
RGMII/SGMII
Figure 1-4. QUICC Engine Module Block Diagram
1.12.1 Ethernet Controllers
The two identical gigabit Ethernet controllers are based on the enhanced PowerQUICC II™
Ethernet controller with network statistics. The Ethernet controllers support two standard
MAC-PHY interfaces to connect to an external Ethernet transceiver:
„ 1000 Mbps SGMII with SerDes support
„ 1000 Mbps RGMII (full duplex only)
The Ethernet transmitter requires little core intervention. After the software driver initializes the
system, the Ethernet controller activates its transmit scheduler. As a result, the controller starts
polling the first transmit buffer descriptor (TxBD) in one of the eight transmit queues as chosen
by the scheduler. The TxBD ring is polled every 512 transmit clocks. If TxBD[R] bit is set, the
Ethernet controller begins moving transmit buffers from memory to the Tx virtual FIFO. The
Ethernet MAC transmitter takes data from Tx virtual FIFO and transmits the data through the
appropriate interface (RGMII/SGMII) to the physical media. The transmitter, once initialized,
runs until the end-of-frame (EOF) condition is detected, unless a collision within the collision
window occurs (in half-duplex mode) or an abort condition is encountered. The Ethernet
Controller receiver can perform pattern matching, data extraction, Ethernet type recognition,
CRC checking, VLAN detection, short frame checking, and maximum frame-length checking.
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Freescale Semiconductor
1-29
Overview
1.12.2 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the exchange of data with other devices containing an
SPI. The SPI also communicates with peripheral devices such as EEPROMs, real-time clocks,
A/D converters, and ISDN devices. The SPI is a full-duplex, synchronous, character-oriented
channel that supports a four-wire interface (receive, transmit, clock, and slave select). The SPI
block consists of transmitter and receiver sections, an independent baud-rate generator, and a
control unit. The transmitter and receiver sections use the same clock, which is derived from the
SPI baud rate generator in master mode and generated externally in slave mode. During an SPI
transfer, data is sent and received simultaneously.
1.13
TDM
The TDM interface connects gluelessly to common telecommunication framers, such as T1 and
E1. It can interface with multiple buses, such as H-MVIP/H.110 devices, TSI, and codecs such as
AC-97. It provides a total 4096 channels that are timing compliant with their clock, sync and data
signals. The TDM is composed of eight identical and independent modules. Each TDM module
can be configured in one of the following modes:
„ Independent receive and transmit mode. The transmitter has an input clock, output data
and a frame sync that can be configured as either input or output. There are up to 256
transmit channels and up to 256 receive channels. The receiver has an input clock, input
data, and an input frame sync.
„ Shared sync and clock mode. Two receive and two transmit links share the same clock and
the frame sync: The sync can be configured as either input or output. Each of the two
transmit and receive links supports up to 128 channels.
„ Shared data link mode. Up to four full-duplex data links, which operate as either transmit
or receive, have the same clock and frame sync. Each link supports up to 128 channels.
If all are used, the TDM modules can support up to 500 Mbps (250 Mbps Tx and 250 Mbps Rx)
with a clock frequency up to 62.5 MHz (62.5 Mbps × 4 TDMs in each direction). Each channel
can be 2, 4, 8, or 16 bits wide. All the channels share the same width during the TDM operation.
When the slot size is 8 bits wide, the selected channels can be defined as A-law/µ-law. These
channels are converted to 13/14 bits, which are padded into 16 bits and stored in memory. Each
receive and transmit channel can be active or not. An active channel has a configurable buffer
located in either in M2, M3, or DDR memory. The TDMs support either 0.5 ms (4 frames) or 1
ms (8 frames) latency. The buffers of one TDM interface are the same size and are filled/emptied
at the same rate. A-law/u-law buffers are filled at twice the rate, so their buffer size is twice that
of the transparent channels. For receive, the buffers of specific TDM interface fill at the same rate
and therefore share the same write pointer relative to the beginning of the buffer. When the write
pointer reaches a predetermined threshold, an interrupt to the SC3850 core is generated. The
SC3850 core empties the buffers while the TDM continues to fill the buffers until a second
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Freescale Semiconductor
Global Interrupt Controller (GIC)
threshold line is reached and then an additional interrupt is generated to the SC3850 core. The
SC3850 core empties the data between the first and the second threshold lines. Both the first and
the second threshold lines are programmable. Using these threshold lines, the SC3850 core and
the TDM can perform a double-buffer handshake. For transmit, the SC3850 core fills all the
buffers of a TDM interface, and the TDM empties them. A similar method employing two
threshold line interrupts is used for a double-buffer handshake between the SC3850 core and the
TDM. You can program the interrupt as either shared for receive and transmit or separated.
1.14
Global Interrupt Controller (GIC)
The GIC receives the external and internal NMI and maskable interrupt sources and routes them to
the SC3850 cores, to the INT_OUT lines, or to the NMI_OUT lines.
1.15
UART
The UART is used mainly for debugging. It provides a full-duplex port for serial
communications by transmit data (TXD) and receive data (RXD) lines. During reception, the
UART generates an interrupt request when a new character is available to the UART data
register. During transmission, the UART generates an interrupt request when its data register can
be written with new character. When accepting an interrupt request, an SC3850 core or external
host should read the UART status register to identify the interrupt source and service it
accordingly.
1.16
Timers
The MSC8156 device contains 16 identical 16-bit timers divided into four groups. Each group
(TMR) contains four identical 16-bit timers, each with a prescaler, a counter, a load register, a
hold register, a capture register, two compare registers, two status registers, and a control register.
In addition, each SC3850 subsystem includes two general purpose 32-bit timers. The MSC8156
device also includes 8 software watchdog timers. Each of the software watchdog timers can be
used by any of the cores within MSC8156 as well as by an external host.
1.17
Hardware Semaphores
There are eight coded hardware semaphores. Each semaphore is an 8-bit register with a selective
write protection mechanism. When the register value is zero, it is writable to any new value.
When the register value is not zero, it is writable only to zero. Each SC3850 core/host/task has a
unique predefined lock number (8-bit code). When trying to lock the semaphore, the SC3850
core writes its lock number to the semaphore and then reads it. If the read value equals its lock
number, the semaphore belongs to that host and is essentially locked. An SC3850 core/host/task
releases the semaphore by writing a 0 to it.
MSC8156 Reference Manual, Rev. 2
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1-31
Overview
1.18
Virtual Interrupts
The global interrupt controller generates 26 virtual interrupts including 16 maskable interrupts, 8
VNMIs, and 2 interrupts for external interrupt and NMI outputs (INT_OUT and NMI_OUT,
respectively). A virtual interrupt/VNMI is generated via a write access to the Virtual Interrupt
Generation Register (VIGR) by one of the SC3850 cores or an external host CPU.
1.19
I2C Interface
The inter-integrated circuit (I2C) controller enables the MSC8156 to exchange data with other
I2C devices, such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and
LCD displays. The I2C controller uses a synchronous, multi-initiator bus that can connect several
integrated circuits on a board. Two signals, serial data (SDA) and serial clock (SCL), carry
information between the integrated circuits connected to it.
1.20
GPIOs
The MSC8156 has 32 general-purpose I/O (GPIO) ports that are multiplexed as either GPIO
ports or dedicated peripheral interface ports. As GPIOs, each port is configured as an input or
output (with a register for data output that is read or written at any time) by GPIO configuration
registers. These registers also select the alternate functions and enable the open-drain function
when ports are configured as outputs. In addition to the GPIO configuration registers, two general
configuration registers (GPUER and GIER) also control the functionality when the ports are
configured as inputs. The default configuration out of reset selects the primary GPIO input
function with internal pull-ups. However, the ports are also disabled. GIER is used to enable the
individual input ports and GPUER can disable the pull-ups for each port. Sixteen of the GPIs can
also be configured as IRQ inputs. If configured as output, the GPIO ports can also be configured
as open-drain (that is, configured in an active low wired-OR configuration on the board). In this
mode, an output drives a zero voltage but goes to tri-state when driving a high voltage. The
dedicated MSC8156 peripheral functions multiplexed with the GPIO ports are grouped to
maximize the usefulness of the ports in the greatest number of MSC8156 applications.
1.21
Boot Options
The boot program in the internal boot ROM initializes the MSC8156 after it completes a reset
sequence. The MSC8156 device can boot from an external host through the serial RapidIO
interface or download a user boot program through the I2C, SPI, or Ethernet ports.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
JTAG
1.22
JTAG
The dedicated user-accessible test access port (TAP) is fully compatible with IEEE Std. 1149.1.
The MSC8156 device supports circuit-board test strategies based on this standard. For details on
the standard, refer to the standard documentation.
MSC8156 Reference Manual, Rev. 2
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1-33
Overview
1.23
Developer Environment
Freescale supplies a complete set of DSP development tools for the MSC8156 device. The tools
provide easier and more robust ways for designers to develop optimized DSP systems. Whether
the application targets a 3G-LTE, TD-SCDMA, or WiMAX system, the development
environment gives the designers everything they need to exploit the advanced capabilities of the
MSC8156 architecture.
1.23.1 Tools
The MSC8156 tool components include the following:
„ Integrated development environment (IDE). Easy-to-use graphical user interface and
project manager for configuring and managing multiple build configurations.
„ C compiler with in-line assembly. The developer can generate highly optimized DSP code
by exploiting the StarCore multiple-ALU architecture, with parallel fetch sets and high
code density.
„ Librarian. The developer can create application-specific DSP libraries for modularity.
„ Linker. The developer can efficiently produce executables from object code and partition
memory according to the application architecture; the linker supports code overlay.
„ Multi-Core Debugger. Seamlessly integrated real-time, non-intrusive, multi-mode,
multi-core, and multi-DSP debugger handles highly optimized DSP algorithms. The
developer can choose to debug in source code, assembly code, or mixed mode. Supports
RTOS-aware debugger.
„ Royalty-free RTOS. Included with package and includes a graphical user interface (GUI)
called Kernel Aware that shows task information, interrupts, and other processing
elements.
„ Software Simulator. Full chip simulation (FCS) that allows the developer to design an
application and run it on the simulator before running it on the silicon. FCS is integrated
under integrator developer environment (IDE), the simulator provides customers with
tools to create projects and debug them as they would on silicon (high speed simultaneous
transfers). In addition, there is an SC3850 subsystem performance accurate (PACC)
simulator that is approximately 95% cycle accurate.
„ Profiler. The developer can analyze and identify program design inefficiencies.
„ High Speed Run Control. USB TAP high speed host-target interface allows users to
program in Flash memory, ROM, and cache.
„ Host Platform Support. Microsoft Windows and Solaris.
„ Development Board. The application development system (ADS).
„ Kit for MSC8156. A complete system for developing and debugging real-time hardware
and software.
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Freescale Semiconductor
Example Applications
1.23.2 Application Software
Freescale offers a broad range of DSP applications through its third-party application software
partners; these applications target IP telephony, telephony modem, wireless and multimedia
transcoding, and wireless base stations. Applications and software modules are listed in Table
1-2.
Table 1-2. Application Software Modules
Application
Baseband
Modules
WiMAX solution supporting Wave 1 features with future extension to Wave 2 and beyond.
3G-LTE evolving kernels library.
Optimized FFT kernels, including matrix multiplication, and so forth.
Device Drivers and
Example Code
MAPLE-B driver, DMA driver, serial RapidIO driver, TDM driver, Ethernet driver, UART driver,
memory allocation, and interrupt handling.
StarCore Libraries
Rich set of StarCore software libraries, including: Math (Part 1 and 2), Signal, Complex vector,
Control function, Frequency domain, Filter, Common, Image Processing, Communication, and Matrix.
.
1.24
Example Applications
This section describes seven use cases.
1.24.1 Use Case 1: 3G-LTE Basic System
The system shown in Figure 1-5 can be used as a 10 MHz FDD LTE system supporting 2 × 2 UL
MIMO, 2 × 2 DL MIMO, 50 Mbps DL, 25 Mbps UL.
MPC8526
GigE
x1
Serial
RapidIO
RLC, MAC
MSC8156
x1
Serial
RapidIO
x4
Serial
RapidIO
RF
Uplink, Downlink
Figure 1-5. Use Case 1: 3G-LTE Basic System
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
1-35
Overview
1.24.2 Use Case 2: 3G-LTE System
The system shown in Figure 1-6 can be used as an LTE 10 MHz FDD, 2 × 4 UL MIMO, 4 × 2
DL MIMO, 50 Mbit/s DL, 25 Mbps UL, 3 sectors.
MPC8526
Serial
RapidIO
Switch
x1
Serial
RapidIO
GigE
RF
x4 Serial
RapidIO
x4 Serial
RapidIO
x4 Serial
RapidIO
MSC8156
MSC8156
MSC8156
DDR
DDR
DDR
Figure 1-6. Use Case 2: 3G-LTE System
1.24.3 Use Case 3: 3G-LTE System
The system shown in Figure 1-7 can be used as an LTE 20 MHz FDD, 2 × 2 DL MIMO, 2 × 2
UL MIMO, 100 Mbit/s DL, 50 Mbps UL, 1 sector.
MPC85xx
GigE
x1
Serial
RapidIO
DDR
DDR
MSC8156
MSC8156
x1
Serial
RapidIO
x4
Serial
RapidIO
x4
Serial
RapidIO
x4
Serial
RapidIO
RF
Figure 1-7. Use Case 3: 3G-LTE System
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
Example Applications
1.24.4 Use Case 4: TD-SCDMA System
The system shown in Figure 1-8 can be used as a TD-SCDMA 1.6 MHz TDD, 8 × 8 no MIMO,
6 carriers.
MPC85xx
GigE
x1
Serial
RapidIO
Bridge
Serial
RapidIO
Switch
x4
Serial
RapidIO
x4 Serial
RapidIO
x4 Serial
RapidIO
MSC8156
MSC8156
DDR
DDR
RF
CPRI
Note: Two devices may be required to support 6 carriers supporting chip-rate and symbol rate,
depending on the system configuration.
Figure 1-8. Use Case 4: TD-SCDMA System
1.24.5 Use Case 5: WiMAX Basic System
The system shown in Figure 1-9 can be used as a WiMAX 10 MHz TDD, 2 × 2 MIMO, 1 sector.
DDR
MPC8526
MSC8156
Bridge
GigE
x1
Serial
RapidIO
RLC, MAC, MAC-hs
x4
Serial
RapidIO
x4
Serial
RapidIO
x4
Serial
RapidIO
CPRI
RF
Uplink, Downlink
Figure 1-9. Use Case 5: WiMAX Basic System
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Freescale Semiconductor
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Overview
1.24.6 Use Case 6: WiMAX System
The system shown in Figure 1-10 can be used as a WiMAX 10 MHz TDD, 4 × 4 MIMO, 4
sectors.
MSC8156
MPC8572
x1
Serial
RapidIO
MSC8156
x1
Serial
RapidIO
DDR
GigE
x4
Serial
RapidIO
Serial
RapidIO
Switch
MPC8572
DDR
GigE
x4
Serial
RapidIO
Bridge
x4 Serial
RapidIO
CPRI
RF
x4 Serial
RapidIO
Figure 1-10. Use Case 6: WiMAX System
1.24.7 Use Case 7: WCDMA Basic System
The system shown in Figure 1-11 can be used as a WCDMA 5 MHz FDD, 2 × 1, no MIMO, 3
sectors.
DDR
MPC8526
MSC8156
FPGA
GigE
x1
Serial
RapidIO
RLC, MAC
x4
Serial
RapidIO
x4
Serial
RapidIO
Uplink, Downlink
x4
Serial
RapidIO
CPRI
RF
IF, Routing, Spread/Despread,
DUC/DDC
Figure 1-11. Use Case 7: WiMAX System
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
SC3850 Core Overview
2
The SC3850 digital signal processing (DSP) core features an innovative architecture that
addresses the key market needs of DSP applications, especially in the fields of wireline and
wireless infrastructure, subscriber communication, and multimedia packet transfer. This flexible
DSP core supports compute-intensive applications by providing high performance, low power,
efficient compile, and high code density. Each high-performance core is binary compatible with
the SC140 core used in the MSC81xx DSP family, the SC1400 core, and the SC3400 core used in
the MSC8144 family and delivers up to 8000 16-bit MMACS using an internal 1 GHz clock at 1
V. A MAC operation includes a multiply-accumulate command with the associated data moves
and a pointer update.
The StarCore SC3850 DSP core and subsystem is an evolution of the StarCore® SC3400 DSP
core and subsystem that enhances many of the original core and subsystem components and
optimizes overall performance and memory hierarchy to target future application needs.
Optimizations target:
„ Improved control/compiled code performance
„ Better operation of DSP intensive kernels
„ Minimizing memory system stalls to increase core use.
Note:
See the SC3850 DSP Core Reference Manual for a detailed description of core
functionality and instruction set. The manual is only available with a signed
non-disclosure agreement. Contact your local Freescale sales office or representative
for details.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
2-1
SC3850 Core Overview
2.1 Core Architecture Features
Key features of the SC3850 DSP core include the following:
• Main core resources
— 4 Data ALU execution units
— 2 integer and address generation units
— Sixteen 40-bit data registers with 8 guard bits, freely accessible by Data ALU instructions
— Sixteen 32-bit address registers, freely accessible by Address generation instructions
• Instruction set
— 16-bit instruction set, expandable to 32 and 48 instructions
— High orthogonality of operands
— Rich instruction set for DSP and control features
— A very good compiler target
• Very high execution parallelism
— Up to six instructions executed in a single clock cycle, statically scheduled
— Variable Length Execution Set (VLES) execution model
— Up to 4 Data ALU instructions and 2 Memory access/integer instructions per cycle
• Data type support
— Byte (8-bit), word (16-bit) and long (32-bit) data widths, supported by instructions and memory
moves
— Both Integer (signed and unsigned) and fractional data types
— Packed fractional complex data type
— Several packed data types (2 to 4 objects on the same register) for SIMD operations
• Very high numerical throughput for DSP operations
— Each Data ALU can perform two 16x16 multiplications per cycle (total of 8 multiplications for
all ALUs), which can be used for:
– Dot product acceleration (40 + (16x16) + (16x16))
– SIMD2 multiplication and accumulation into two 20-bit register portions
– Acceleration of Complex multiplication
– Acceleration of extended precision multiplication
— Some performance summary metrics are listed in Table 2-1:
Table 2-1. Multiplication Throughput Summary Figures for the SC3850
Operation
Precision
Instructions per Operation
Result Throughput (4 ALUs)
Real multiply
16 × 16
0.5
8
16 × 32
1
4
32 × 32
2
2
16 × 16
2
2
16 × 32
4
1
Complex
multiply
MSC8156 Reference Manual, Rev. 2
2-2
Freescale Semiconductor
Core Architecture Features
•
•
•
•
•
•
•
•
Application specific instructions for acceleration the following algorithms
— FFT
— Video processing
— Viterbi
— Baseband operations
High throughput memory interface
— Unified, 32-bit byte addressable memory space
— Dual Harvard architecture that permits one 128-bit program access and two 64-bit data
accesses per cycle
— Core to data memory throughput of up to 16 Giga Bytes per second, at 1 GHz core frequency
— Support of Big Endian, Little Endian and Mixed endian memory policies
Powerful address generation model
— Zero overhead modulo arithmetic support for address pointers
— Several
Advanced pipeline
— 12 stage, fully interlocked pipeline
— No stalls for memory load to register, MAC operation, and result storage to memory
— Speculation of conditionally executed instructions and change of flow execution paths
Control features
— Zero-overhead hardware loops with up to four levels of nesting
— A Branch Target Buffer (BTB) for accelerating execution of change of flow instructions
OS support
— Precise memory exception support, for advanced OS
— User and Supervisor privilege levels, supporting a protected, task oriented execution model
— Full support for memory protection and address translation in the off-core MMU
— Exception and Normal stack pointer for software stack support
— Low task switch overhead using wide stack save and restore instructions
Rich set of real-time debug capabilities through an On-Chip Emulator (OCE)
— Real-time PC, data address and data breakpoint capabilities
— Up to six hardware breakpoint channels, and unlimited debugger-enabled SW breakpoints
— Single stepping
— Externally forced instructions in debug mode by the host processor
— Precise detection of PC breakpoints
— PC tracing with filtering and compression options
— Support for Nexus IEEE-ISTO 5001-2003 standard with off-core ready modules
Low Power Design
— Low-power Wait and Stop instructions
— A very low power design
— Fully static logic
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
2-3
SC3850 Core Overview
2.2 StarCore SC3850 Core Architecture
The SC3850 core contains a Data Arithmetic and Logic Unit (DALU) with four ALUs, and an
Address Generation Unit (AGU) that includes two Address Arithmetic Units (AAU). The
SC3850 efficiently deploys the variable-length execution set (VLES) execution model, allowing
to group up to 4 DALU and 2 AGU instructions in a single clock cycle without sacrificing code
size for execution slots that are not used. Figure 2-1 shows a block diagram of the SC3850 DSP
core.
Data and Program Memory
Program
Sequencer
64
XAD
AGU
Register File
64
XBD
32
XBA
XAA
32
DALU
Register File
Internal
bus
OCE
128
XPD
XPA
32
BTB
2 AAUs
PSEQ
4 ALUs
(2 16 × 16 MAC each)
BMU
AGU
DALU
Instruction bus
Resource Stall Unit (RSU)
SC3850 DSP Core
Figure 2-1. SC3850 DSP Core Block Diagram
The SC3850 uses dual-multiply ALUs supporting two 16-bit × 16-bit multipliers that can
accumulate results into 40-bit wide destination data registers. In addition, it has a 40-bit parallel
barrel shifter. Each ALU performs two MAC operations per clock cycle, so that a single core
running at up to 1 GHz can perform 8 billion multiply-accumulates per second (GMACS). This
rate is for both 16-bit operands, 8-bit operands, or mixed 8-bit and 16-bit operands.
Each AAU in the AGU can perform one address calculation and drive one data memory access
per cycle. Data access widths are flexible and can be between 8 to 64 bits wide. The AGU can
support a throughput of up to 128 Gbps between the core and the memory.
The program sequencer manages the instruction fetching from the program memory, dispatching
the VLES to the execution units, performing change of flow (COF) and HW loop management
MSC8156 Reference Manual, Rev. 2
2-4
Freescale Semiconductor
StarCore SC3850 Core Architecture
and exception processing. It includes a 48-entry branch target buffer which is used to accelerate
the execution of COF operation.
The Resource Stall Unit (RSU) detects dependency hazards and resource requirements as defined
by the code semantics. It then activates the internal operand bypass logic or inserts stalls as
needed.
The SC3850 supports general microcontroller capabilities that make it a suitable target for
advanced operating systems, including support for user and supervisor privilege levels that, with
the MMU, enable implementation of a protected software model. The SC3850 supports precise
exceptions for program and data accesses, allowing designs to implement advanced memory
management schemes and soft error correction. The SC3850 also includes a 48-entry Branch
Target Buffer (BTB) that improves performance by reducing the change of flow latency.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
2-5
SC3850 Core Overview
MSC8156 Reference Manual, Rev. 2
2-6
Freescale Semiconductor
3
External Signals
The MSC8156 external signals are organized into functional groups. Table 3-1 lists the
functional groups and references the table that gives a detailed listing of signals within each
group.
Table 3-1. MSC8156 Functional Signal Groupings
Functional Group
Detailed Description
Power and ground
Table 3-3 on page 3-4
Clock
Table 3-4 on page 3-6
Reset and Configuration
Table 3-5 on page 3-6
DDR Memory Controllers
Table 3-6 on page 3-10
SerDes Multiplexers (Serial RapidIO controllers, PCI Express interface, and SGMII signals)
Table 3-7 on page 3-11
TDM and Ethernet
Table 3-8 on page 3-16
Serial peripheral interface (SPI)
Table 3-9 on page 3-20
GPIOs and maskable Interrupts
Table 3-10 on page 3-20
Timers
Table 3-11 on page 3-25
UART
Table 3-12 on page 3-26
I2C
Table 3-13 on page 3-26
External DMA Interface
Table 3-14 on page 3-27
NMI/INT_OUT/NMI_OUT
Table 3-15 on page 3-28
OCE module and JTAG Test Access Port
Table 3-16 on page 3-29
Some signals are only sampled during the power-on reset sequence; most of these signal lines are
are used by other modules and subsystems during normal operation. Signal multiplexing is
determined at the following three levels:
„ I/O Multiplexing. TDM channels and RGMII channels sharing. Selected during power-on
reset by the GE1/GE2 bits in the high part of the Reset Configuration Word (see Chapter
5, Reset for details). Ethernet selections (RGMII/SGMII) are configured by the Ethernet
registers (see the QUICC Engine Block Reference Manual with Protocol Interworking for
details).
„ SerDes Multiplexing. Serial RapidIO interfaces, PCI Express interface, and SGMII
sharing on the 8-lane SerDes interface. Configured by the Reset Configuration Word (see
Chapter 5, Reset for details).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-1
External Signals
„ GPIO Multiplexing. GPIOs, IRQs, I2C, SPI, DMA external request interface, Timers, and
UART sharing. Configured by GPIO configuration registers (see Chapter 22, GPIO for
details).
The values of the GE1/GE2 RCW bits determine the sharing of signal lines between the TDM
interfaces and the RGMII signals for Ethernet controllers 1 and 2. Table 3-2 lists the signal
groups supported by each of the available multiplexing modes.
Table 3-2. Ethernet/TDM Multiplexing by GE1/GE2 Bit Values
RCW[GE1]
Value
RCW[GE2]
Value
0
Interfaces
TDM0
TDM1
TDM2
TDM3
GE1 RGMII
GE2 RGMII
0
Available
Available
Available
Available
Unavailable
Unavailable
0
1
Unavailable
Unavailable
Available
Available
Unavailable
Available
1
0
Available
Available
Unavailable
Unavailable
Available
Unavailable
1
1
Unavailable
Unavailable
Unavailable
Unavailable
Available
Available
The PCI Express, serial RapidIO interfaces, and the Ethernet SGMIIs share the two SerDes
interfaces. Access to the SerDes interface blocks is configured via the RCW bits (see Chapter 5,
Reset for details).
The thirty-two GPIO ports have configurable functionality. Sixteen of the GPIO lines can be
configured as IRQ inputs through the GPIO configuration registers; four of these lines can also be
configured as the DMA external interface. Fifteen of the other sixteen GPIO lines are
multiplexed with other interface units including the SPI, timers, UART, and I2C signals. The
specific function is selected through configuration of the GPIO registers (see Chapter 22, GPIO
for details).
Figure 3-1 summarizes the various MSC8156 external signal multiplexing options.
MSC8156 Reference Manual, Rev. 2
3-2
Freescale Semiconductor
MSC8156 Device
1.0 V
1.5 V
1.8 V
2.5 V
M1VREF, M2VREF
GND
GNDRIOPLL
CLKIN
CLKOUT
→
→
→
→
→
→
→
→
←
PORESET
HRESET
SRESET
STOP_BS
→
↔
↔
→
INT_OUT ←
NMI →
NMI_OUT ←
I/O Mode 1
I/O Mode 0
Power and
Ground
DDR Memory
Controllers
Clocks
Resets
Interrupts
GE2_RD2
GE2_TD2
GE2_RD3
GE2_GTX_CLK
GE2_RD0
GE2_TD3
TDM0RCK
TDM0RSN
TDM0RDT
TDM0TCK
TDM0TSN
TDM0TDT
↔
↔
↔
↔
↔
↔
TDM0/
Ethernet
Controller 2
GE2_RD1
GE2_RX_CTL
GE2_TX_CLK
GE2_RX_CLK
GE2_TD1
GE2_TD0
TDM1RCK
TDM1RSN
TDM1RDT
TDM1TCK
TDM1TSN
TDM1TDT
↔
↔
↔
→
↔
↔
TDM1/
Ethernet
Controller 2
GE1_TD0
GE1_TD2
GE1_TD1
GE1_TD3
TDM2RCK
TDM2RSN
TDM2RDT
TDM2TCK
↔
↔
↔
→
TDM2TSN ↔
TDM2TDT ↔
TDM2/
Ethernet
Controller 1
TDM3RCK
TDM3RSN
TDM3RDT
TDM3TCK
TDM3TSN
TDM3TDT
↔
↔
↔
→
↔
↔
TDM3/
Ethernet
Controller 1
GPIO17/SPI_SCK
GPIO18/SPI_MOSI
GPIO19/SPI_MISO
GPIO20/SPI_SL
GPIO30/I2C_SCL
GPIO31/I2C_SDA
TCK
TMS
TDI
TDO
TRST
EE0
EE1
←
→
←
↔
↔
↔
↔
↔
↔
↔
→
→
→
←
→
→
←
GE1_TX_CTL
GE1_TX_CLK
GE1_GTX_CLK
GE1_RD1
GE1_RD0
GE1_RD2
GE1_RX_CLK
GE1_RD3
GE2_TX_CTL
GE1_RX_CTL
GE_MDC
GE_MDIO
SerDes
Multiplexers
Serial RapidIO
Controllers/PCI
Express/Serial
Ethernet
GPIO
Dedicated
Ethernet
SPI
I2C
Timers
JTAG/Debug
UART
DDR Controller 1
→
→
↔
→
↔
↔
→
→
→
→
→
→
→
↔
↔
→
→
←
M1A[15–0]
M1BA[2–0]
M1DQ[63–0]
M1DM[8–0]
M1DQS[8–0]
M1DQS[8–0]
M1CK[0–2]
M1CK[0–2]
M1CKE[0–1]
M1RAS
M1CAS
M1WE
M1CS[0–1]
M1ECC[0–7]
M1MDIC[0–1]
M1ODT[0–1]
M1APAR_OUT
M1APAR_IN
←
←
←
←
←
←
→
→
←
←
→
→
←
←
→
→
←
←
→
→
SR1_REF_CLK
SR1_REF_CLK
SR1_IMP_CAL_RX
SR1_IMP_CAL_TX
SR1_RXD0
SR1_RXD0
SR1_TXD0
SR1_TXD0
SR1_RXD1
SR1_RXD1
SR1_TXD1
SR1_TXD1
SR1_RXD2/SG1_RX
SR1_RXD2/SG1_RX
SR1_TXD2/SG1_TX
SR1_TXD2/SG1_TX
SR1_RXD3/SG2_RX
SR1_RXD3/SG2_RX
SR1_TXD3/SG2_TX
SR1_TXD3/SG2_TX
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
GPIO0/IRQ0
GPIO1/IRQ1
GPIO2/IRQ2
GPIO3/IRQ3/DRQ1
GPIO4/IRQ4/DDN1
GPIO5/IRQ5
GPIO6/IRQ6
GPIO7/IRQ7
GPIO8/IRQ8
GPIO9/IRQ9
GPIO10/IRQ10
GPIO11/IRQ11
GPIO12/IRQ12
GPIO13/IRQ13
GPIO14/IRQ14/DRQ0
GPIO15/IRQ15/DDN0
GPIO16
GPIO21
GPIO22
GPIO23/TMR0
GPIO24/TMR1
GPIO25/TMR2
GPIO26/TMR3
GPIO27/TMR4
GPIO28/UART_RXD
GPIO29/UART_TXD
SerDes Multiplexer 1
Note: See the individual signal description tables for details about individual power supplies and grounds.
DDR Controller 2
M2A[15–0]
M2BA[2–0]
M2DQ[63–0]
M2DM[8–0]
M2DQS[8–0]
M2DQS[8–0]
M2CK[0–2]
M2CK[0–2]
M2CKE[0–1]
M2RAS
M2CAS
M2WE
M2CS[0–1]
M2ECC[0–7]
M2MDIC[0–1]
M2ODT[0–1]
M2APAR_OUT
M2APAR_IN
SerDes Multiplexer 2
SR2_REF_CLK
SR2_REF_CLK
SR2_IMP_CAL_RX
SR2_IMP_CAL_TX
SR2_RXD0/PE_RXD0
SR2_RXD0/PE_RXD0
SR2_TXD0/PE_TXD0
SR2_TXD0/PE_TXD0
SR2_RXD1/PE_RXD1
SR2_RXD1/PE_RXD1
SR2_TXD1/PE_TXD1
SR2_TXD1/PE_TXD1
SR2_RXD2/PE_RXD2/SG1_RX
SR2_RXD2/PE_RXD2/SG1_RX
SR2_TXD2/PE_TXD2/SG1_TX
SR2_TXD2/PE_TXD2/SG1_TX
SR2_RXD3/PE_RXD3/SG2_RX
SR2_RXD3/PE_RXD3/SG2_RX
SR2_TXD3/PE_TXD3/SG2_TX
SR2_TXD3/PE_TXD3/SG2_TX
Sampled at PORESET deassertion
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RCW_SRC2
RCW_SRC1
RCW_SRC0
Dedicated signals:
RC17/RCW_LSEL0, RC18/RCW_LSEL1,
RC19/RCW_LSEL2, RC20/RCW_LSEL3,
RC21
Figure 3-1. MSC8156 External Signals
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-3
External Signals
3.1
Power Signals
Table 3-3. Power and Ground Inputs
Nominal
Voltage
Signal Name
Symbol
VDD
VDD
M3VDD
VDDM3
MVDD
VDDM
PLL0_AVDD
VDDPLL1
PLL1_AVDD
VDDPLL1
PLL2_AVDD
VDDPLL1
SXPVDD1
VDDSXP1
SXPVDD2
VDDSXP2
SXCVDD1
VDDSXC1
SXCVDD2
VDDSXC2
SR1_PLL_AVDD
VDDPLL1
SR2_PLL_AVDD
VDDPLL1
1.0 V
1.0 V
(Differential)
Description
Power for Core Subsystems 0–5
A dedicated well-regulated power source for core subsystems
0–5. Provide an extremely low impedance path to the VDD power
rail and adequate external decoupling capacitors.
Power for M3 Memory
A dedicated well-regulated power source for 1 Mbyte of the M3
memory. Provide an extremely low impedance path to the VDD
power rail and adequate external decoupling capacitors. This
input can be disabled when not used to reduce system power
requirements. When this input is disabled, 32 Kbyte of M3
memory remains active.
Power for MAPLE-B Subsystem
A dedicated well-regulated power source for the MAPLE-B
subsystem. Provide an extremely low impedance path to the VDD
power rail and adequate external decoupling capacitors. This
input can be disabled when not used to reduce system power
requirements.
System PLL 0 Power
A dedicated well-regulated power for the system Phase Lock
Loops (PLLs).
System PLL 1 Power
A dedicated well-regulated power for the system Phase Lock
Loops (PLLs).
System PLL 2 Power
A dedicated well-regulated power for the system Phase Lock
Loops (PLLs).
Serial RapidIO Interface 1 Pad Power
A dedicated well-regulated power for the Serial RapidIO interface
1 pad circuitry.
Serial RapidIO Interface 2 Pad Power
A dedicated well-regulated power for the Serial RapidIO interface
2 pad circuitry.
Serial RapidIO Interface 1 Core Power
A dedicated well-regulated power for the Serial RapidIO interface
1 core circuitry.
Serial RapidIO Interface 2 Core Power
A dedicated well-regulated power for the Serial RapidIO interface
2 core circuitry.
Serial RapidIO PLL 1 Power
A dedicated well-regulated power for the system Phase Lock
Loops (PLLs).
Serial RapidIO PLL 2 Power
A dedicated well-regulated power for the system Phase Lock
Loops (PLLs).
MSC8156 Reference Manual, Rev. 2
3-4
Freescale Semiconductor
Power Signals
Table 3-3. Power and Ground Inputs (Continued)
Nominal
Voltage
Signal Name
1.5 V or 1.8 V
GVDD1
VDDDDR1
GVDD2
VDDDDR2
M1VREF
M1VREF
M2VREF
M2VREF
NVDD
VDDIO
QVDD
VDDPLL0
VSS
GND
SR1_PLL_AGND
GNDRIO1PLL
SR2_PLL_AGND
GNDRIO2PLL
SXCVSS1
GNDSXC1
SXCVSS2
GNDSXC2
SXPVSS1
GNDSXP1
SXPVSS2
GNDSXP2
GVDD1 × 0.5 V
GVDD2 × 0.5 V
2.5 V
Symbol
0 V (GND)
Note:
Description
SSTL IO Driver Power (1.5 V or 1.8 V)
A dedicated power source for the DDR controller 1 DRAM
interface buffers. Provide adequate external decoupling
capacitors. The external decoupling capacitors recommendations
are listed in the MSC8156 Technical Data Sheet.
SSTL IO Driver Power (1.5 V or 1.8 V)
A dedicated power source for the DDR controller 2 DRAM
interface buffers. Provide adequate external decoupling
capacitors. The external decoupling capacitors recommendations
are listed in the MSC8156 Technical Data Sheet.
SSTL Reference Power
A reference power level for the DDR controller 1 memory
interface.
SSTL Reference Power
A reference power level for the DDR controller 2 memory
interface.
Input/Output Power
The power source for the external I/O signal lines. Provide
adequate external decoupling capacitors. The external
decoupling capacitors recommendations are listed in the
MSC8156 Technical Data Sheet.
Input/Output Power
The power source for the external clock, reset, OCE, and JTAG
signal lines. Provide adequate external decoupling capacitors.
The external decoupling capacitors recommendations are listed in
the MSC8156 Technical Data Sheet.
System Ground
An isolated ground for the internal processing logic and I/O
buffers. This connection must be tied externally to all chip ground
connections, except GNDSXC and GNDSXP.
RapidIO Interface 1 PLL Ground
Ground dedicated for RapidIO Interface 1 PLL use. The
connection should be provided with an extremely low-impedance
path to ground.
RapidIO Interface 2 PLL Ground
Ground dedicated for RapidIO interface 2 PLL use. The
connection should be provided with an extremely low-impedance
path to ground.
RapidIO Interface 1 Core Ground
A ground for the RapidIO port 1 Core circuitry.
RapidIO Interface 2 Core Ground
A ground for the RapidIO port 2 Core circuitry.
RapidIO Interface 1 Pad Ground
A ground for the RapidIO port 1 Pad circuitry.
RapidIO Interface 2 Pad Ground
A ground for the RapidIO port 2 Pad circuitry.
The external decoupling capacitors recommendations are listed in the MSC8156
Technical Data Sheet.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-5
External Signals
3.2
Clock Signals
Table 3-4. Clock Signals
Signal Name
CLKIN
Input
CLKOUT
3.3
Type
Signal Description
Clock In
Primary clock input to the MSC8156 PLLs.
Output Clock Out
The bus clock output.
Reset and Configuration Signals
Table 3-5. Reset and Configuration Signals
Signal Name
Type
Signal Description
Input
Power-On Reset
When asserted, this line causes the MSC8156 to enter power-on reset state.
Internally, this signal also resets the TAP and debugging modules. The power-on
reset flow resets the MSC8156 device, configures various device attributes
including its clock modes, and drives HRESET and SRESET as open-drain outputs.
HRESET
Input/
Output
Hard Reset
When asserted as an input, this signal causes the MSC8156 to abort all current
internal and external transactions, set most registers to their default state, and enter
the hard reset state. This signal must be asserted for at least 32 CLKIN cycles.
While the device is in the hard reset state, it drives HRESET and SRESET as
open-drain outputs. This signal requires an external pull-up resistor. The signal is
tri-stated after the hard reset flow is complete.
SRESET
Input/
Output
Soft Reset
When asserted as an input, this signal causes the MSC8156 to enter the soft reset
state, about all current internal transactions, configure most registers with their
default values, and cause the cores to enter their reset state. The signal does not
affect I/O signal functionality or direction or memory controller operations. While the
device is in the soft reset state, it drives the SRESET as an open-drain output. This
signal requires an external pull-up resistor. The signal is tri-stated after the soft reset
flow is complete.
Input
Stop Boot Sequencer
This signal is valid only when the reset configuration words are being loaded from
an I2C EEPROM using the boot sequencer and is asserted only for a reset target
device to prevent the loading of the reset configuration words until allowed by the
Boot ROM. The signal level must be asserted as long as HRESET is asserted. For
the reset master or a single device reading from I2C EEPROM, you must drive this
low during the reset sequence. For details, see Chapter 5, Reset. This signal is also
used for booting after reset (for details, see Chapter 6, Boot Program).
PORESET
STOP_BS
MSC8156 Reference Manual, Rev. 2
3-6
Freescale Semiconductor
Reset and Configuration Signals
Table 3-5. Reset and Configuration Signals (Continued)
Signal Name
RCW_SRC0
Type
Signal Description
Input
Reset Configuration Word Source 0
Along with the RCW_SRC[1–2], this signal is sampled at the deassertion of
PORESET to identify the source of the reset configuration word. The required signal
level must be maintained as long as HRESET is asserted.
GPIO27
Input/
Output
General-Purpose Input Output 27
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details,
see Chapter 22, GPIO.
TMR4
Input/
Output
Timer 4
Configured as input to the counter or output from the counter. Selected through the
GPIO configuration. For details, see Chapter 22, GPIO. For functional details, see
Chapter 21, Timers.
Input
Reset Configuration Word Source 1
Along with the RCW_SRC[0, 2], this signal is sampled at the deassertion of
PORESET to identify the source of the reset configuration word. The required signal
level must be maintained as long as HRESET is asserted.
RCW_SRC1
GPIO25
Input/
Output
General-Purpose Input Output 25
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details,
see Chapter 22, GPIO.
TMR2
Input/
Output
Timer 2
Configured as input to the counter or output from the counter. Selected through the
GPIO configuration. For details, see Chapter 22, GPIO. For functional details, see
Chapter 21, Timers.
Input
Reset Configuration Word Source 2
Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of
PORESET to identify the source of the reset configuration word. The required signal
level must be maintained as long as HRESET is asserted.
RCW_SRC2
GPIO24
Input/
Output
General-Purpose Input Output 24
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details,
see Chapter 22, GPIO.
TMR1
Input/
Output
Timer 1
Configured as input to the counter or output from the counter. Selected through the
GPIO configuration. For details, see Chapter 22, GPIO. For functional details, see
Chapter 21, Timers.
RC[0–2]
GPIO[0–2]
IRQ[0–2]
Input
Input/
Output
Input
Reset Configuration Word Bit 0–2
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 0–2
Three of the 32 GPIO pins used as GPIO or as a dedicated input or output. For
details, see Chapter 22, GPIO.
Interrupt Request 0–2
External lines that can request a service routine via the internal interrupt controller.
Selected through GPIO configuration. For details, see Chapter 22, GPIO. For
functional details, see Chapter 13, Interrupt Handling.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-7
External Signals
Table 3-5. Reset and Configuration Signals (Continued)
Signal Name
RC3
GPIO3
Type
Input
Input/
Output
Signal Description
Reset Configuration Word Bit 3
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 3
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ3
Input
Interrupt Request 3
External line that can request a service routine via the internal interrupt controller.
For details, see Chapter 13, Interrupt Handling.
DRQ1
Input
DMA External Request 1
When enabled by GPIO multiplexing, asserting this input triggers external DMA
request 1. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
RC4
Input
Reset Configuration Word Bit 4
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
GPIO4
Input/
Output
General-Purpose Input Output 4
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ4
Input
Interrupt Request 4
External line that can request a service routine via the internal interrupt controller.
For details, see Chapter 13, Interrupt Handling.
DDN1
Output
DMA External DONE Indication 1
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA
request 1 is done. For details, see Chapter 14, Direct Memory Access (DMA)
Controller,
RC[5–13]
GPIO[5–13]
Input
Reset Configuration Word Bit 5–13
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
Input/
Output
General-Purpose Input Output 5–13
Nine of the 32 GPIO pins used as GPIO or as a dedicated input or output. For
details, see Chapter 22, GPIO.
IRQ[5–13]
Input
Interrupt Request 5–13
External lines that can request a service routine via the internal interrupt controller.
Selected through GPIO configuration. For details, see Chapter 22, GPIO. For
functional details, see Chapter 13, Interrupt Handling.
RC14
Input
Reset Configuration Word Bit 14
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
GPIO14
Input/
Output
General-Purpose Input Output 14
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ14
Input
Interrupt Request 14
External line that can request a service routine via the internal interrupt controller.
For details, see Chapter 13, Interrupt Handling.
DRQ0
Input
DMA External Request 0
When enabled by GPIO multiplexing, asserting this input triggers external DMA
request 0. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
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Reset and Configuration Signals
Table 3-5. Reset and Configuration Signals (Continued)
Signal Name
RC15
GPIO15
Type
Input
Input/
Output
Signal Description
Reset Configuration Word Bit 15
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 15
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ15
Input
Interrupt Request 15
External line that can request a service routine via the internal interrupt controller.
For details, see Chapter 13, Interrupt Handling.
DDN0
Output
DMA External DONE Indication 0
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA
request 0 is done. For details, see Chapter 14, Direct Memory Access (DMA)
Controller,
RC16
Input
GPIO16
RC17
RCW_LSEL0
RC18
RCW_LSEL1
RC19
RCW_LSEL2
RC20
RCW_LSEL3
Input/
Output
Input
Output
Input
Output
Input
Output
Input
Output
Reset Configuration Word Bit 16
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 16
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details,
see Chapter 22, GPIO.
Reset Configuration Word Bit 17
If RCW_SRC[0–2] equals 011, this input is sampled during the assertion of
PORESET to set part of the bits of the Reset Configuration Word Registers.
Reset Configuration Word Lane 0 Select
If RCW_SRC[0–2] equals 000, this signal is used to enable loading of Lane 0
(RCWLR bits 15–0) of the RCW via RC[15–0] when asserted. See Chapter 5,
Reset for details.
Reset Configuration Word Bit 18
If RCW_SRC[0–2] equals 011, this input is sampled during the assertion of
PORESET to set part of the bits of the Reset Configuration Word Registers.
Reset Configuration Word Lane 1 Select
If RCW_SRC[0–2] equals 000, this signal is used to enable loading of Lane 1
(RCWLR bits 31–16) of the RCW via RC[15–0] when asserted. See Chapter 5,
Reset for details.
Reset Configuration Word Bit 19
If RCW_SRC[0–2] equals 011, this input is sampled during the assertion of
PORESET to set part of the bits of the Reset Configuration Word Registers.
Reset Configuration Word Lane 2 Select
If RCW_SRC[0–2] equals 000, this signal is used to enable loading of Lane 2
(RCWHR bits 15–0) of the RCW via RC[15–0] when asserted. See Chapter 5,
Reset for details.
Reset Configuration Word Bit 20
If RCW_SRC[0–2] equals 011, this input is sampled during the assertion of
PORESET to set part of the bits of the Reset Configuration Word Registers.
Reset Configuration Word Lane 3 Select
If RCW_SRC[0–2] equals 000, this signal is used to enable loading of Lane 3
(RCWHR bits 31–16) of the RCW via RC[15–0] when asserted. See Chapter 5,
Reset for details.
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External Signals
Table 3-5. Reset and Configuration Signals (Continued)
Signal Name
RC21
Note:
Type
Input
Signal Description
Reset Configuration Word Bit 21
If RCW_SRC[0–2] equals 011, this input is sampled during the assertion of
PORESET to set part of the bits of the Reset Configuration Word Registers. If
RCW_SRC[0–2] does not equal 011, this input is ignored.
When RCW_SRC[0–2] equals 011, RC[0–21] are valid only for driving a reduced external reset configuration word
value. The signals are sampled during the assertion of PORESET to set part of the bits of the Reset Configuration
Word Registers. The required signal levels must be maintained as long as HRESET is asserted. All other signal
drivers connected to these inputs must be tri-stated while HRESET is asserted. When RCW_SRC[0–2] equals 000,
the device loads all 64 bits of the RCW via RC[0–15] in four beats. In this case, RC[17–20] function as
RCW_LSEL[0–3] outputs that are asserted to load the RCW 16 bits at a time and RC21 is ignored. See Chapter 5,
Reset for details.
3.4
Memory Controller 1 and 2
Refer to Chapter 12, DDR SDRAM Memory Controller for details on configuring these signals.
Table 3-6. Memory Controller Signals
Signal Name
Type
Description
M1A[15–0]
M2A[15–0]
Output
Address Bus
The memory interface address bus used to connect to external memory
devices. MA0 is the lsb of the address driven by the DDR controller.
M1BA[2–0]
M2BA[2–0]
Output
Bank Address
Selects the DDR DRAM bank. Each DDR SDRAM can support four or
eight logically addressable sub-banks. MBA0 must connect to bit zero of
the SDRAM input bank address. This line is asserted during the mode
register set command to specify the extended mode register.
M1DQ[63–0]
M2DQ[63–0]
Input/
Output
Data Bus
The MSC8156 device drives the bus during write cycles and the external
memory drives the bus during read cycles.
M1DM[8–0]
M2DM[8–0]
Output
DDR SDRAM Data Output Mask
Masks unwanted data bytes transferred during a burst write. These signals
are used to support sub-burst-size transactions (such as single-byte
writes) on SDRAM in which all transactions occur in multi-byte bursts.
MDM0 corresponds to the MSB and MDM7 corresponds to the LSB.
MDM8 acts as the ECC data mask.
M1DQS[8–0]
M2DQS[8–0]
Input/Output
DDR SDRAM DQS
Strobe for byte-lane data capture. The signals are inputs driven by the
DDR SRAM with read data and outputs driven by the DDR controller with
write data. The data strobes may be single-ended or differential. Bit 8 is
used as the ECC data mask.
M1DQS[8–0]
M2DQS[8–0]
Input/Output
DDR SDRAM DQS Complement
Complement strobe for byte-lane data capture. The signals are inputs
driven by the DDR SRAM with read data and outputs driven by the DDR
controller with write data. The data strobes may be single-ended or
differential.
M1ECC[7–0]
M2ECC[7–0]
Input/Output
DDR Error Checking and Correcting Codes
As normal mode outputs the ECC signals represent the state of ECC
driven by the DDR controller on writes.
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SerDes Multiplexed Signals for the Serial RapidIO, PCI Express, and SGMII Interfaces
Table 3-6. Memory Controller Signals (Continued)
Signal Name
Type
Description
M1CK[2–0]
M2CK[2–0]
Output
DDR Clock Out
The DDR clock output. Each signal is part of a differential pair.
M1CK[2–0]
M2CK[2–0]
Output
DDR Clock Out Inverted
The inverted DDR clock. Each signal is part of a differential pair.
M1CKE[1–0]
M2CKE[1–0]
Output
Clock Enable
When asserted, this signal enables the DDR clock for the DDR DRAM.
M1RAS
M2RAS
Output
Row Address Strobe
Connects to DDR DRAM RAS input. This line is asserted for activate
commands and is used for mode register set and refresh commands.
M1CAS
M2CAS
Output
Column Address Strobe
Connects to DDR DRAM CAS input. This line is asserted for read or write
transactions and for mode register set, refresh, and precharge commands.
M1WE
M2WE
Output
Write Enable
Connects to DDR DRAM WE input.
M1CS[0–1]
M2CS[0–1]
Output
Chip Select 0–1
Enables specific memory devices or peripherals connected to the bus.
M1MDIC[0–1]
M2MDIC[0–1]
Input/Output
M1ODT[0–1]
M2ODT[0–1]
Output
On-Die Termination
Memory controller outputs for the ODT to the SDRAM. Each signal
represents the corresponding chip select.
M1APAR_OUT
M2APAR_OUT
Output
Parity Output
If enabled, drives the parity bit for the bus.
M1APAR_IN
M2APAR_IN
3.5
Input
Driver Impedance Calibration
These lines are used for automatic calibration of the DDR I/O.
Parity Input
Receives the error indication from an open-drain parity error signal.
SerDes Multiplexed Signals for the Serial RapidIO, PCI
Express, and SGMII Interfaces
Refer to Chapter 5, Reset, Chapter 16, Serial RapidIO Controller, Chapter 16, Serial RapidIO
Controller, and the QUICC Engine Block Reference Manual with Protocol Interworking for
configuration information.
Table 3-7. SerDes Multiplexed Signals
Signal Name
Type
Description
SR1_IMP_CAL_RX
Input
Serial RapidIO Controller 1 Receiver Impedance Control Signal
Receiver impedance calibration control signal.
SR1_IMP_CAL_TX
Input
Serial RapidIO Controller 1 Transmitter Impedance Control Signal
Transmitter impedance calibration control signal.
SR1_RXD0
Input
Serial RapidIO Controller 1 Receive Data 0
Serial data input for a x1 or x4 link. Each signal is part of a differential pair.
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External Signals
Table 3-7. SerDes Multiplexed Signals (Continued)
Signal Name
Type
Description
SR1_RXD0
Input
Serial RapidIO Controller 1 Receive Data 0 Inverted
Inverted serial data input for a x1 or x4 link. Each signal is part of a differential
pair.
SR1_RXD1
Input
Serial RapidIO Controller 1 Receive Data 1
Serial data input for a x4 link. Each signal is part of a differential pair.
SR1_RXD1
Input
Serial RapidIO Controller 1 Receive Data 1 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
SR1_RXD2
Input
Serial RapidIO Controller 1 Receive Data 2
Serial data input for a x4 link. Each signal is part of a differential pair.
SG1_RX
Input
Ethernet 1 SGMII Receive Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_RXD2
Input
Serial RapidIO Controller 1 Receive Data 2 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
SG1_RX
Input
Ethernet 1 SGMII Receive Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_RXD3
Input
Serial RapidIO Controller 1 Receive Data 3
Serial data input for a x4 link. Each signal is part of a differential pair.
SG2_RX
Input
Ethernet 2 SGMII Receive Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_RXD3
Input
Serial RapidIO Controller 1 Receive Data 3 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
SG2_RX
Input
Ethernet 2 SGMII Receive Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_TXD0
Output
Serial RapidIO Controller 1 Transmit Data 0
Serial data output for a x1 or x4 link. Each signal is part of a differential pair.
SR1_TXD0
Output
Serial RapidIO Controller 1 Transmit Data 0 Inverted
Inverted serial data output for a x1 or x4 link. Each signal is part of a differential
pair.
SR1_TXD1
Output
Serial RapidIO Controller 1 Transmit Data 1
Serial data output for a x4 link. Each signal is part of a differential pair.
SR1_TXD1
Output
Serial RapidIO Controller 1 Transmit Data 1 Inverted
Inverted serial data output for a x4 link. Each signal is part of a differential pair.
SR1_TXD2
Output
Serial RapidIO Controller 1 Transmit Data 2
Serial data output for a x4 link. Each signal is part of a differential pair.
SG1_TX
Output
Ethernet 1 SGMII Transmit Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
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SerDes Multiplexed Signals for the Serial RapidIO, PCI Express, and SGMII Interfaces
Table 3-7. SerDes Multiplexed Signals (Continued)
Signal Name
Type
Description
SR1_TXD2
Output
Serial RapidIO Controller 1 Transmit Data 2 Inverted
Inverted serial data output for a x4 link. Each signal is part of a differential pair.
SG1_TX
Output
Ethernet 1 SGMII Transmit Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_TXD3
Output
Serial RapidIO Controller 1 Transmit Data 3
Serial data output for a x4 link. Each signal is part of a differential pair.
SG2_TX
Output
Ethernet 2 SGMII Transmit Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_TXD3
Output
Serial RapidIO Controller 1 Transmit Data 3 Inverted
Inverted serial data output for a x4 link. Each signal is part of a differential pair.
SG2_TX
Output
Ethernet 2 SGMII Transmit Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR1_REF_CLK
Input
Serial RapidIO Controller 1 Reference Clock
Reference clock signal. Each signal is part of a differential pair. For SGMII
operation, this provides the input clock.
SR1_REF_CLK
Input
Serial RapidIO Controller 1 Reference Clock Inverted
Inverted reference clock signal. Each signal is part of a differential pair. For
SGMII operation, this provides the input clock.
SR2_IMP_CAL_RX
Input
Serial RapidIO Controller 2 Receiver Impedance Control Signal
Receiver impedance calibration control signal.
SR2_IMP_CAL_TX
Input
Serial RapidIO Controller 2 Transmitter Impedance Control Signal
Transmitter impedance calibration control signal.
SR2_RXD0
Input
Serial RapidIO Controller 2 Receive Data 0
Serial data input for a x1 or x4 link. Each signal is part of a differential pair.
PE_RXD0
Input
PCI Express Receive Data 0
Serial data input. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SR2_RXD0
Input
Serial RapidIO Controller 2 Receive Data 0 Inverted
Inverted serial data input for a x1 or x4 link. Each signal is part of a differential
pair.
PE_RXD0
Input
PCI Express Receive Data 0 Inverted
Inverted serial data input. Each signal is part of a differential pair. For details,
see Chapter 17, PCI Express Controller.
SR2_RXD1
Input
Serial RapidIO Controller 2 Receive Data 1
Serial data input for a x4 link. Each signal is part of a differential pair.
PE_RXD1
Input
PCI Express Receive Data 1
Serial data input. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SG2_RX
Input
Ethernet 2 SGMII Receive Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
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3-13
External Signals
Table 3-7. SerDes Multiplexed Signals (Continued)
Signal Name
Type
Description
SR2_RXD1
Input
Serial RapidIO Controller 2 Receive Data 1 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
PE_RXD1
Input
PCI Express Receive Data 1 Inverted
Inverted serial data input. Each signal is part of a differential pair. For details,
see Chapter 17, PCI Express Controller.
SG2_RX
Input
Ethernet 2 SGMII Receive Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_RXD2
Input
Serial RapidIO Controller 2 Receive Data 2
Serial data input for a x4 link. Each signal is part of a differential pair.
PE_RXD2
Input
PCI Express Receive Data 2
Serial data input. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SG1_RX
Input
Ethernet 1 SGMII Receive Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_RXD2
Input
Serial RapidIO Controller 2 Receive Data 2 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
PE_RXD2
Input
PCI Express Receive Data 2 Inverted
Inverted serial data input. Each signal is part of a differential pair. For details,
see Chapter 17, PCI Express Controller.
SG1_RX
Input
Ethernet 1 SGMII Receive Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_RXD3
Input
Serial RapidIO Controller 2 Receive Data 3
Serial data input for a x4 link. Each signal is part of a differential pair.
PE_RXD3
Input
PCI Express Receive Data 3
Serial data input. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SR2_RXD3
Input
Serial RapidIO Controller 2 Receive Data 3 Inverted
Inverted serial data input for a x4 link. Each signal is part of a differential pair.
PEI_RXD0
Input
PCI Express Receive Data 1 Inverted
Inverted serial data input. Each signal is part of a differential pair. For details,
see Chapter 17, PCI Express Controller.
SR2_TXD0
Output
Serial RapidIO Controller 2 Transmit Data 0
Serial data output for a x1 or x4 link. Each signal is part of a differential pair.
PE_TXD0
Output
PCI Express Transmit Data 0
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
MSC8156 Reference Manual, Rev. 2
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SerDes Multiplexed Signals for the Serial RapidIO, PCI Express, and SGMII Interfaces
Table 3-7. SerDes Multiplexed Signals (Continued)
Signal Name
Type
Description
SR2_TXD0
Output
Serial RapidIO Controller 2 Transmit Data 0 Inverted
Inverted serial data output for a x1 or x4 link. Each signal is part of a differential
pair.
PE_TXD0
Output
PCI Express Transmit Data 0 Inverted
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SR2_TXD1
Output
Serial RapidIO Controller 2 Transmit Data 1
Serial data output for a x1 or x4 link. Each signal is part of a differential pair.
PE_TXD1
Output
PCI Express Transmit Data 1
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SG2_TX
Output
Ethernet 2 SGMII Transmit Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_TXD1
Output
Serial RapidIO Controller 2 Transmit Data 1 Inverted
Inverted serial data output for a x1 or x4 link. Each signal is part of a differential
pair.
PE_TXD1
Output
PCI Express Transmit Data 1 Inverted
Inverted serial data output. Each signal is part of a differential pair. For details,
see Chapter 17, PCI Express Controller.
SG2_TX
Output
Ethernet 2 SGMII Transmit Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_TXD2
Output
Serial RapidIO Controller 2 Transmit Data 2
Serial data output for a x1 or x4 link. Each signal is part of a differential pair.
PE_TXD2
Output
PCI Express Transmit Data 2
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SG1_TX
Output
Ethernet 1 SGMII Transmit Data
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
SR2_TXD2
Output
Serial RapidIO Controller 2 Transmit Data 2 Inverted
Inverted serial data output for a x1 or x4 link. Each signal is part of a differential
pair.
PE_TXD2
Output
PCI Express Transmit Data 2 Inverted
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SG1_TX
Output
Ethernet 1 SGMII Transmit Data Inverted
Part of the Ethernet signals. For details, see the QUICC Engine Block
Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
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External Signals
Table 3-7. SerDes Multiplexed Signals (Continued)
Signal Name
Type
Description
SR2_TXD3
Output
Serial RapidIO Controller 2 Transmit Data 3
Serial data output for a x4 link. Each signal is part of a differential pair.
PE_TXD3
Output
PCI Express Transmit Data 3
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SR2_TXD3
Output
Serial RapidIO Controller 2 Transmit Data 3 Inverted
Inverted serial data output for a x1 or x4 link. Each signal is part of a differential
pair.
PE_TXD3
Output
PCI Express Transmit Data 3 Inverted
Serial data output. Each signal is part of a differential pair. For details, see
Chapter 17, PCI Express Controller.
SR2_REF_CLK
Input
Serial RapidIO Controller 2 Reference Clock
Reference clock signal. Each signal is part of a differential pair. For SGMII
operation, this provides the input clock.
SR2_REF_CLK
Input
Serial RapidIO Controller 2 Reference Clock Inverted
Inverted reference clock signal. Each signal is part of a differential pair. For
SGMII operation, this provides the input clock.
Note:
For proper definition of serial RapidIO modes (x1/x4), PCI Express, and SGMII, configure the interfaces using the
Reset Configuration Word settings. For details, see Chapter 5, Reset.
3.6
TDM and Ethernet Signals
The TDM and RGMII signals are listed together because they are multiplexed using the same
signal lines. The GE1 and GE2 bits in the RCW control the selection between the TDM signals
and the RGMII signals. See Table 3-2 on page 3-2 for a detailed description of the multiplexing
options. Table 3-8 describes the signals in this group.
Table 3-8. TDM and Ethernet Signals
Signal Name
TDM3TDT
Type
Description
Input/ TDM3 Serial Transmitter Data
Output The serial transmit data signal for TDM 3. For configuration details, see Chapter 19, TDM
Interface.
GE1_RD3
Input
Ethernet 1 Receive Data 3
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM3TCK
Input
TDM3 Transmit Clock
Transmit Clock for TDM 3. For configuration details, see Chapter 19, TDM Interface.
GE1_RD2
Input
Ethernet 1 Receive Data 2
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM3TSN
GE1_RX_CLK
Input/ TDM3 Transmit Frame Sync
Output Transmit frame sync for TDM 3. See Chapter 19, TDM Interface.
Input
Ethernet 1 Receive Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
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TDM and Ethernet Signals
Table 3-8. TDM and Ethernet Signals (Continued)
Signal Name
TDM3RDT
GE1_RD0
Type
Description
Input/ TDM3 Serial Receiver Data
Output The receive data signal for TDM 3. For configuration details, see Chapter 19, TDM Interface.
Input
Ethernet 1 Receive Data 0
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM3RCK
Input/ TDM3 Receive Clock
Output The receive clock signal for TDM 3. For configuration details, see Chapter 19, TDM Interface.
GE1_GTX_CLK
Output Ethernet 1 Output Transmit Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM3RSN
Input/ TDM3 Receive Frame Sync
Output The receive sync signal for TDM 3. For configuration details, see Chapter 19, TDM Interface.
GE1_RD1
TDM2TDT
Input
Ethernet 1 Receive Data 1
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
Input/ TDM2 Serial Transmitter Data
Output The transmit data signal for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TX_CLK
Input
Ethernet 1 Transmit Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM2TCK
Input
TDM 2 Transmit Clock
Transmit clock for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TD3
Output Ethernet 1 Transmit Data 3
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM2TSN
Input/ TDM2 Transmit frame Sync
Output Transmit frame sync for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TX_CTL
Output Ethernet 1 Transmit Control
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM2RDT
Input/ TDM2 Serial Receiver Data
Output The receive data signal for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TD1
Output Ethernet 1 Transmit Data 1
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM2RCK
Input/ TDM2 Receive Clock
Output The receive clock signal for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TD0
Output Ethernet 1 Transmit Data 0
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM2RSN
Input/ TDM2 Receive Frame Sync
Output The receive sync signal for TDM 2. For configuration details, see Chapter 19, TDM Interface.
GE1_TD2
Output Ethernet 1 Transmit Data 2
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM1TDT
Input/ TDM1 Serial Transmitter Data
Output The transmit data signal for TDM 1. For configuration details, see Chapter 19, TDM Interface.
GE2_TD0
Output Ethernet 2 Transmit Data 0
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
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External Signals
Table 3-8. TDM and Ethernet Signals (Continued)
Signal Name
Type
Description
TDM1TCK
Input
TDM1 Transmit Clock
Transmit clock for TDM 1. For configuration details, see Chapter 19, TDM Interface.
GE2_RX_CLK
Input
Ethernet 2 Receive Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM1TSN
Input/ TDM1 Transmit Frame Sync
Output Transmit frame sync for TDM 1. For configuration details, see Chapter 19, TDM Interface.
GE2_TD1
Output Ethernet 2 Transmit Data 1
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM1RDT
Input/ TDM1 Serial Receiver Data
Output The receive data signal for TDM 1. For configuration details, see Chapter 19, TDM Interface.
GE2_TX_CLK
TDM1RCK
GE2_RD1
TDM1RSN
GE2_RX_CTL
Input
Ethernet 2 Transmit Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
Input/ TDM1 Receive Clock
Output The receive clock signal for TDM 1. For configuration details, see Chapter 19, TDM Interface.
Input
Ethernet 2 Receive Data 1
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
Input/ TDM1 Receive Frame Sync
Output The receive sync signal for TDM 1. For configuration details, see Chapter 19, TDM Interface.
Input
Ethernet 2 Receive Control
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM0TDT
Input/ TDM0 Serial Transmitter Data
Output The transmit data signal for TDM 0. For configuration details, see Chapter 19, TDM Interface.
GE2_TD3
Output Ethernet 2 Transmit Data 3
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM0TCK
Input
TDM 0 Transmit Clock
Transmit Clock for TDM 0. For configuration details, see Chapter 19, TDM Interface.
GE2_GTX_CLK
Output Ethernet 2 Output Transmit Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
TDM0TSN
Input/ TDM0 Transmit Frame Sync
Output Transmit Frame Sync for TDM 0. For configuration details, see Chapter 19, TDM Interface.
GE2_RD0
TDM0RDT
GE2_RD3
TDM0RCK
GE2_RD2
Input
Ethernet 2 Receive Data 0
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
Input/ TDM0 Serial Receiver Data
Output The receive data signal for TDM 0. For configuration details, see Chapter 19, TDM Interface.
Input
Ethernet 2 Receive Data 3
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
Input/ TDM0 Receive Clock
Output The receive clock signal for TDM 0. For configuration details, see Chapter 19, TDM Interface.
Input
Ethernet 2 Receive Data 2
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
TDM and Ethernet Signals
Table 3-8. TDM and Ethernet Signals (Continued)
Signal Name
Type
Description
TDM0RSN
Input/ TDM0 Receive Frame Sync
Output The receive sync signal for TDM 0. For configuration details, see Chapter 19, TDM Interface.
GE2_TD2
Output Ethernet 2 Transmit Data 2
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
GE2_TX_CTL
Output Ethernet 2 Transmit Control
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
GE1_RX_CTL
Input
Ethernet 1 Receive Control
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
GE_MDC
Output Ethernet Management Data Clock
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
GE_MDIO
Input/ Ethernet Management Data Input/Output
Output For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-19
External Signals
3.7
Serial Peripheral Interface (SPI) Signal Summary
Table 3-9 summarizes the Serial Peripheral Interface (SPI) signal lines, which are available in all modes.
Table 3-9. SPI Signals
Signal Name
Type
Signal Description
Input/ General-Purpose Input Output 20
Output One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes.
GPIO20
Input
SPI_SL
SPI Select
Enable input to the SPI slave in single master mode. In multi-master environment, SPI_SL
detects an error when more one master is operating. Assertion of an SPI_SL, while it is master,
causes an error.
GPIO19
Input/ General-Purpose Input Output 19
Output One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes
SPI_MISO
Input/ SPI Master Input Slave Output
Output When the SPI is a master, SPI_SCK is the clock input signal that shifts received data in from
SPI_MOSI and transmitted data out through SPI_MISO.
GPIO18
Input/ General-Purpose Input Output 18
Output One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes.
SPI_MOSI
Input/ SPI Master Output Slave Input
Output When the SPI is a master, SPI_SCK is the clock input signal that shifts received data in from
SPI_MOSI and transmitted data out through SPI_MISO.
GPIO17
Input/ General-Purpose Input Output 17
Output One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes.
SPI_SCK
Input/ SPI Clock
Output Gated clock, active only during data transfers. Four combinations of SPI_SCK phase and
polarity can be configured. When the SPI is a master, SPI_SCK is the clock output signal that
shifts received data in from SPI_MOSI and transmitted data out through SPI_MISO.
3.8
GPIO/Maskable Interrupt Signal Summary
Some of the GPIO and interrupt lines are multiplexed with other interfaces. Some of the lines are
independent. In addition to the hardware interrupt inputs, there are also several signal lines used
to reroute interrupts between the cores and an external host processor. Table 3-16 summarizes
the GPIO and interrupt signal lines.
Table 3-10. GPIO and Maskable Interrupt Summary
Signal Name
Type
Description
GPIO31
Input/
Output
General-Purpose Input Output 31
One of 32 GPIOs. For details, see Chapter 22, GPIO.
I2C_SDA
Input/
Output
I2C-Bus Data Line
This is the data line for the I2C bus. For details, see Chapter 24, I2C.
MSC8156 Reference Manual, Rev. 2
3-20
Freescale Semiconductor
GPIO/Maskable Interrupt Signal Summary
Table 3-10. GPIO and Maskable Interrupt Summary (Continued)
Signal Name
Type
Description
GPIO30
Input/
Output
General-Purpose Input Output 30
One of 32 GPIOs. For details, see Chapter 22, GPIO.
I2C_SCL
Input/
Output
I2C-Bus Clock Line
This the clock line for the I2C bus. For details, see Chapter 24, I2C.
GPIO29
Input/
Output
General-Purpose Input Output 29
One of 32 GPIOs. For details, see Chapter 22, GPIO.
UART_TXD
Output
UART Transmit Data
For details, see Chapter 20, UART.
GPIO28
Input/
Output
General-Purpose Input Output 28
One of 32 GPIOs. For details, see Chapter 22, GPIO.
UART_RXD
Input/
Output
UART Receive Data
For details, see Chapter 20, UART.
GPIO27
Input/
Output
General-Purpose Input Output 27
One of 32 GPIOs. For details, see Chapter 22, GPIO.
TMR4
Input/
Output
Timer 4
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
Input
Reset Configuration Word Source 0
Along with the RCW_SRC[1–2], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
GPIO26
Input/
Output
TMR3
Input/
Output
General-Purpose Input/Output 26
One of 32 GPIOs. For details, see Chapter 22, GPIO.
.
Timer 3
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO25
Input/
Output
General-Purpose Input Output 25
One of 32 GPIOs. For details, see Chapter 22, GPIO.
TMR2
Input/
Output
Timer 2
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
Input
Reset Configuration Word Source 1
Along with the RCW_SRC[0,2], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
RCW_SRC0
RCW_SRC1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-21
External Signals
Table 3-10. GPIO and Maskable Interrupt Summary (Continued)
Signal Name
Type
Description
GPIO24
Input/
Output
General-Purpose Input Output 24
One of 32 GPIOs. For details, see Chapter 22, GPIO.
TMR1
Input/
Output
Timer 1
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
Input
Reset Configuration Word Source 2
Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
RCW_SRC2
GPIO23
Input/
Output
General-Purpose Input Output 23
One of 32 GPIOs. For details, see Chapter 22, GPIO.
TMR0
Input/
Output
Timer 0
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO22
Input/
Output
General-Purpose Input Output 22
One of 32 GPIOs. For details, see Chapter 22, GPIO.
GPIO21
Input/
Output
General-Purpose Input Output 21
One of 32 GPIOs. For details, see Chapter 22, GPIO.
GPIO20
Input/
Output
General-Purpose Input Output 20
One of 32 GPIOs. For details, see Chapter 22, GPIO.
SPI_SL
Input
GPIO19
Input/
Output
General-Purpose Input Output 19
One of 32 GPIOs. For details, see Chapter 22, GPIO.
SPI_MISO
Input/
Output
SPI Master Input Slave Output
When the SPI is a master, SPI_SCK is the clock input signal that shifts received data in
from SPI_MOSI and transmitted data out through SPI_MISO. For details, see the QUICC
Engine Block Reference Manual with Protocol Interworking.
GPIO18
Input/
Output
General-Purpose Input Output 18
One of 32 GPIOs. For details, see Chapter 22, GPIO.
SPI_MOSI
Input/
Output
SPI Master Output Slave Input
When the SPI is a master, SPI_SCK is the clock input signal that shifts received data in
from SPI_MOSI and transmitted data out through SPI_MISO. For details, see the QUICC
Engine Block Reference Manual with Protocol Interworking.
GPIO17
Input/
Output
General-Purpose Input Output 17
One of 32 GPIOs. For details, see Chapter 22, GPIO.
SPI_SCK
Input/
Output
SPI Clock
Gated clock, active only during data transfers. Four combinations of SPI_SCK phase and
polarity can be configured. When the SPI is a master, SPI_SCK is the clock output signal
that shifts received data in from SPI_MOSI and transmitted data out through SPI_MISO.
For details, see the QUICC Engine Block Reference Manual with Protocol Interworking.
SPI Select
Enable input to the SPI slave in single master mode. In multi-master environment,
SPI_SL detects an error when more one master is operating. Assertion of an SPI_SL,
while it is master, causes an error. For details, see the QUICC Engine Block Reference
Manual with Protocol Interworking.
MSC8156 Reference Manual, Rev. 2
3-22
Freescale Semiconductor
GPIO/Maskable Interrupt Signal Summary
Table 3-10. GPIO and Maskable Interrupt Summary (Continued)
Signal Name
GPIO16
RC16
GPIO15
Type
Input/
Output
Input
Input/
Output
IRQ15
Input
DDN0
Output
RC15
Input
GPIO14
Input/
Output
Description
General-Purpose Input Output 16
One of 32 GPIOs. For details, see Chapter 22, GPIO.
Reset Configuration Word Bit 16
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 15
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
Interrupt Request 15
External line that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
DMA External DONE Indication 0
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA request
0 is done. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
Reset Configuration Word Bit 15
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 14
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ14
Input
Interrupt Request 14
External line that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
DRQ0
Input
DMA External Request 0
When enabled by GPIO multiplexing, asserting this input triggers external DMA request 0.
For details, see Chapter 14, Direct Memory Access (DMA) Controller,
RC14
Input
Reset Configuration Word Bit 14
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
GPIO[13–5]
Input/
Output
General-Purpose Input Output 13–5
Nine of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ[13–5]
Input
Interrupt Request 13–5
External lines that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
RC[13–5]
Input
Reset Configuration Word Bit 13–5
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-23
External Signals
Table 3-10. GPIO and Maskable Interrupt Summary (Continued)
Signal Name
GPIO4
Type
Input/
Output
IRQ4
Input
DDN1
Output
RC4
GPIO3
Input
Input/
Output
Description
General-Purpose Input Output 4
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
Interrupt Request 4
External lines that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
DMA External DONE Indication 1
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA request
1 is done. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
Reset Configuration Word Bit 4
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
General-Purpose Input Output 3
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ3
Input
Interrupt Request 3
External line that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
DRQ1
Input
DMA External Request 1
When enabled by GPIO multiplexing, asserting this input triggers external DMA request 1.
For details, see Chapter 14, Direct Memory Access (DMA) Controller,
RC3
Input
Reset Configuration Word Bit 3
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
GPIO[2–0]
Input/
Output
General-Purpose Input Output 2–0
Three of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ[2–0]
Input
Interrupt Request 2–0
External lines that can request a service routine via the internal interrupt controller. For
details, see Chapter 13, Interrupt Handling.
RC[2–0]
Input
Reset Configuration Word Bit 2–0
Sampled during the assertion of PORESET to set part of the bits of the Reset
Configuration Word Registers.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
Timer Signals
3.9
Timer Signals
Table 3-11 describes the signals in this group.
Table 3-11. Timer Signals
Signal Name
Type
Description
TMR4
Input/
Output
Timer 4
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO27
Input/
Output
General-Purpose Input Output 27
One of 32 GPIOs. For details, see Chapter 22, GPIO.
Input
Reset Configuration Word Source 0
Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
TMR3
Input/
Output
Timer 3
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO26
Input/
Output
General-Purpose Input Output 26
One of 32 GPIOs. For details, see Chapter 22, GPIO.
TMR2
Input/
Output
Timer 2
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO25
Input/
Output
General-Purpose Input Output 25
One of 32 GPIOs. For details, see Chapter 22, GPIO.
RCW_SRC0
RCW_SRC1
Input
Reset Configuration Word Source 1
Along with the RCW_SRC[0,2], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
TMR1
Input/
Output
Timer 1
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO24
Input/
Output
General-Purpose Input Output 24
One of 32 GPIOs. For details, see Chapter 22, GPIO.
RCW_SRC2
Input
Reset Configuration Word Source 2
Along with the RCW_SRC[0–1], this signal is sampled at the deassertion of PORESET to
identify the source of the reset configuration word. The required signal level must be
maintained as long as HRESET is asserted.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-25
External Signals
Table 3-11. Timer Signals (Continued)
Signal Name
Type
Description
TMR0
Input/
Output
Timer 0
Configured as input to the counter or output from the counter. Selected through the GPIO
configuration. For details, see Chapter 22, GPIO. For timer functional details, see
Chapter 21, Timers.
GPIO23
Input/
Output
General-Purpose Input Output 23
One of 32 GPIOs. For details, see Chapter 22, GPIO.
3.10
UART Signals
Table 3-12. UART Signals
Signal Name
Type
Description
UART_TXD
Output
UART Transmit Data
Selected through the GPIO configuration. For details, see Chapter 22, GPIO. For functional
details, see Chapter 20, UART.
GPIO29
Input/
Output
General-Purpose Input Output 29
One of 32 GPIOs. For details, see Chapter 22, GPIO.
UART_RXD
Input/
Output
UART Receive Data
Selected through the GPIO configuration. For details, see Chapter 22, GPIO. For functional
details, see Chapter 20, UART.
GPIO28
Input/
Output\
General-Purpose Input Output 28
One of 32 GPIO pins used as GPIO or as a dedicated input or output. For details, see
Chapter 22, GPIO.
3.11
I2C Signals
Table 3-13. I2C Signals
Signal
Name
Type
Description
I2C_SDA
Input/
Output
I2C-Bus Data Line
This is the data line for the I2C bus. Selected through the GPIO configuration. For details, see
Chapter 22, GPIO. For functional details, see Chapter 24, I2C.
GPIO31
Input/
Output
General-Purpose Input Output 31
One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes.
I2C_SCL
Input/
Output
I2C-Bus Clock Line
This the clock line for the I2C bus. Selected through the GPIO configuration. For details, see
Chapter 22, GPIO. For functional details, see Chapter 24, I2C.
GPIO30
Input/
Output
General-Purpose Input/Output 30
One of 32 GPIOs. For details, see Chapter 22, GPIO. Valid in all modes.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
External DMA Signals
3.12
External DMA Signals
Table 3-14. External DMA Signals
Signal
Name
Type
Description
DDN0
Output
DMA External DONE Indication 0
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA request 0 is
done. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
GPIO15
Input/
Output
General-Purpose Input Output 15
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ15
Input
Interrupt Request 15
External line that can request a service routine via the internal interrupt controller. For details, see
Chapter 13, Interrupt Handling.
RC15
Input
Reset Configuration Word Bit 15
Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word
Registers.
DRQ0
Input
DMA External Request 0
When enabled by GPIO multiplexing, asserting this input triggers external DMA request 0. For
details, see Chapter 14, Direct Memory Access (DMA) Controller,
GPIO14
Input/
Output
General-Purpose Input Output 14
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ14
Input
Interrupt Request 14
External line that can request a service routine via the internal interrupt controller. For details, see
Chapter 13, Interrupt Handling.
RC14
Input
Reset Configuration Word Bit 14
Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word
Registers.
DDN1
Output
DMA External DONE Indication 1
When enabled by GPIO multiplexing, this signal is asserted to indicate that DMA request 1 is
done. For details, see Chapter 14, Direct Memory Access (DMA) Controller,
GPIO4
Input/
Output
General-Purpose Input Output 4
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ4
Input
Interrupt Request 4
External lines that can request a service routine via the internal interrupt controller. For details,
see Chapter 13, Interrupt Handling.
RC4
Input
Reset Configuration Word Bit 4
Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word
Registers.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
3-27
External Signals
Table 3-14. External DMA Signals (Continued)
Signal
Name
Type
DRQ1
Input
GPIO3
Input/
Output
Description
DMA External Request 1
When enabled by GPIO multiplexing, asserting this input triggers external DMA request 1. For
details, see Chapter 14, Direct Memory Access (DMA) Controller,
General-Purpose Input Output 3
One of the 32 GPIOs. For details, see Chapter 22, GPIO.
IRQ3
Input
Interrupt Request 3
External line that can request a service routine via the internal interrupt controller. For details, see
Chapter 13, Interrupt Handling.
RC3
Input
Reset Configuration Word Bit 3
Sampled during the assertion of PORESET to set part of the bits of the Reset Configuration Word
Registers.
3.13
Other Interrupt Signals
Table 3-15 summarizes the other interrupt signal lines.
Table 3-15. Other Interrupt Signals
Signal Name
INT_OUT
NMI
NMI_OUT
Type
Description
Output
Interrupt Output
An open-drain output driven from the MSC8156 virtual interrupt 24. Assertion of this output
indicates that an unmasked interrupt is pending in the MSC8156 internal interrupt controller.
Input
Non-Maskable Interrupt
An external device may assert this line to generate a non-maskable interrupt to the MSC8156
device.
Output
Non-Maskable Interrupt Output
An open-drain pin driven from the MSC8156 virtual interrupt 25. Assertion of this output
indicates that a non-maskable interrupt is pending in the MSC8156 internal interrupt controller,
waiting to be handled by an external host.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
OCE Event and JTAG Test Access Port Signals
3.14
OCE Event and JTAG Test Access Port Signals
The MSC8156 uses two sets of debugging signals for the two types of internal debugging
modules: OCE and the JTAG TAP controller. Each internal SC3850 core has an OCE module,
but they are all accessed externally by the same two signals EE0 and EE1. The MSC8156 supports
the standard set of test access port (TAP) signals defined by IEEE® Std. 1149.1™ Test Access
Port and Boundary-Scan Architecture specification and described in Table 3-16.
Table 3-16. JTAG TAP Signals
Signal Name
Type
Signal Description
EE0
Input
OCE Event Bit 0
Used for putting the internal SC3850 cores into Debug mode. Pulling the signal high asserts
the signal and requests that the cores enter Debug mode.
EE1
Output
TCK
Input
Test Clock
A test clock signal for synchronizing JTAG test logic.
TDI
Input
Test Data Input
A test data serial signal for test instructions and data. TDI is sampled on the rising edge of
TCK and has an internal pull-up resistor.
TDO
Output
Test Data Output
A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is
actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of
TCK.
TMS
Input
Test Mode Select
Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has
an internal pull-up resistor.
TRST
Input
Test Reset
Asynchronous JTAG reset input. Initializes the TAP logic. This signal should always be
asserted with PORESET.
OCE Event Bit 1
Indicates that at least one on-chip SC3850 core is in Debug mode. A high output indicates
that at least one SC3850 core is in Debug mode.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
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External Signals
MSC8156 Reference Manual, Rev. 2
3-30
Freescale Semiconductor
Chip-Level Arbitration and Switching
System (CLASS)
4
The Chip Level Arbitration and Switching System (CLASS) is the central internal interconnect
system for the MSC8156 device. The CLASS is a non-blocking, full-fabric interconnect that
allows any initiator to access any target in parallel with another initiator-target couple. The
CLASS uses a fully pipelined low latency design. The CLASS demonstrates per-target
prioritized round-robin arbitration, highly optimized to the target characteristics. The CLASS
operates at 500 MHz, and is separate from the SC3850 core frequency to provide an optimized
trade-off between power dissipation, memory technology, and miss latency. Controlling the
intradevice data flow, the CLASS reduces bottle necks and permits high bandwidth fully
pipe-lined traffic. The CLASS system is ready for use and does not require any special
configuration to perform non-blocking pipelined transactions from any initiator to any memory.
The configurable arbitration features described in this chapter are for fine-tuning the system for
specific application requirements.
The twelve CLASS initiators are:
„ Six SC3850 core subsystems (initiator ports 0–5)
„ Two MAPLE bridges (initiator ports 6–7)
„ SerDes bridge shared by two Serial RapidIO controllers and the PCI Express controller
(initiator port 8)
„ Peripherals bridge shared by the SEC, four TDM interfaces, SPI, RGMII, SGMII, and
JTAG interface (initiator port 9)
„ Two DMA controllers (initiator ports 10–11)
The eight CLASS targets are:
„
„
„
„
„
Configuration Control and Status Registers (CCSR) (target port 0)
MAPLE module (target port 1)
Three core subsystem bridges (two core subsystems per bridge) (target ports 2–4)
Two DDR controllers (target ports 5–6)
M3 memory (target port 7)
Reference Manual, Rev. 2
Freescale Semiconductor
4-1
Chip-Level Arbitration and Switching System (CLASS)
The CLASS initiators and targets are shown in Figure 4-1. The arrows indicate the address
direction from initiator to target.
CCSR
MAPLE
Extended
Core 4–5
Bridge
0
1
2
Target Devices
Extended
Extended
Core 2–3
Core 0–1
Bridge
Bridge
3
DDR
Controller 1
DDR
Controller 2
M3
5
6
7
4
Target Ports
Chip Level Arbitration and Switching System (CLASS)
0
1
2
3
4
Initiator Ports
5
6
Extended Extended Extended Extended Extended Extended
Core4
Core5
Core0
Core1
Core2
Core3
7
MAPLE
8
9
10
11
SerDes Peripherals DMA Controller
Bridge
Bridge
Initiator Devices
Figure 4-1. CLASS Initiators and Targets in the MSC8156 Device
4.1
CLASS Features
The CLASS modules implement the following features:
„
„
„
„
„
„
„
„
„
Non blocking, full fabric interconnect.
Full bandwidth utilization toward each of the targets.
Allows full pipeline when a specific initiator accesses a specific target.
Allows full pipeline when accesses are generated by one or more initiators to specific
targets.
Read transactions can have a maximum pipeline of 16 acknowledged requests before
completing the transaction toward the initiator.
Write transactions can have a maximum pipeline of 3 acknowledged requests before
completing the transaction toward the initiator.
Programmable priority mapping.
Programmable auto priority upgrade.
Address decoding for target selection and multi target demultiplexing:
— Programmable address space start/end registers per target, for flexible address
decoding (resolution of 4 KB). Not supported in the reduced configuration option.
— Fixed priority between address decoding results which allows overlapping address
windows and deduction of address windows.
Reference Manual, Rev. 2
4-2
Freescale Semiconductor
Functional Description
„ Per-target arbitration algorithm:
— 4 level prioritization
— Each level implements pseudo round-robin arbitration algorithm.
— Weighted arbitration
— Optimized data bus utilization mode
„ Programmable masking priority for starvation elimination.
„ Multiplexing the initiator buses according to the arbitration winner.
„ Normalizing mode that splits non-aligned transactions according to the target capabilities
(maximal burst size, power-of-2 burst, burst alignment, full size burst, data-beat
alignment, wrap size)
„ Error detection and handling:
— The CLASS identifies illegal addresses; addresses that do not belong to any of the
address windows or fall inside the negative windows.
— The CLASS stores the illegal address, reports the error, and generates an interrupt.
„ Debug and profiling unit (CDPU) support.
4.2
Functional Description
The CLASS is a non blocking interconnect between up to 16 initiators and up to 16 targets. The
main sub-blocks of the CLASS are: expander, multiplexer and arbiter, normalizer, and the
CLASS control interface (CCI) unit that implements the interface and interrupt lines and the
CLASS register files. The CLASS also implements an inherent debug and profiling unit (CDPU).
To implement the protocol that deals with the point-to-point bus, the CLASS includes an
expander module per initiator that performs address decoding and is used as sampling stage on
the initiator side. Each expander module can detect an error address and generate an interrupt. For
more details about the expander module see Section 4.2.1. From the target side, the CLASS
includes a multiplexer and arbiter module and a normalizer module for each target. The
multiplexer and arbiter module performs a pseudo round-robin (RR) arbitration algorithm
between all the initiators and concentrates them toward one target. For details about multiplexer
and arbiter module see Section 4.2.2. Each multiplexer and arbiter module has a dedicated
normalizer module that is used as the sampling stage on the target side. The normalizer can also
be used for normalizing transactions. For more details about normalizer module see Section
4.2.3.
Reference Manual, Rev. 2
Freescale Semiconductor
4-3
Chip-Level Arbitration and Switching System (CLASS)
4.2.1
Expander Module and Transaction Flow
Each expander module connects to one initiator. The expander module performs address
decoding according to the configuration register settings. Each target is presented by a start
address and an end address that define a window in the memory space. The address decoding is
done by checking whether the transaction address hits one of the active windows. Each expander
module is connected to all of the multiplexer and arbiter blocks in the CLASS to implement a
full-fabric and non-blocking interconnect between any initiator to any target. If the address
decoding hits in more than one window, the CLASS arbiter chooses a window by fixed priority
arbitration (target 0 has the lowest priority). After detecting the requested target and the arbiter
selects the target window, the expander module starts a transaction toward the associated
multiplexer and arbiter module. The CLASS prevents the possibility of simultaneous accessing to
more than one target by the same initiator. If there are accesses from one initiator to different
targets, the expander module start the transactions to other targets only after all the open accesses
to the current target are completed. The expander module is a sampling stage of transaction. For
each request (address + attribute), write data is sampled from the initiator and driven to the
normalizer module through multiplexer and arbiter module in the following clock cycle; read
data is sampled from the normalizer module through multiplexer and arbiter module and driven
to the initiator in the following clock cycle.
4.2.2
Multiplexer and Arbiter Module
The multiplexer and arbiter module connects to all the expander modules on one side and to a
dedicated normalizer module on the other side. The multiplexer and arbiter module block is a
pure logic data path design, that supports up to 16 initiators, performs an arbitration, and
concentrates them towards a specific target normalizer module.
4.2.2.1 CLASS Arbiter
The CLASS arbiter performs weighted arbitration algorithm for requestors simultaneously using
a pseudo round-robin arbitration algorithm for each of the priority levels and chooses the highest
level request. The CLASS arbiter supports four priority levels, where 3 is the highest and 0 is the
lowest. The arbitration operation can be done every clock cycle or delayed according to the
number of datums of acknowledged transaction (Late Arbitration mode). The CLASS arbiter
supports priority upgrade, so the initiator can upgrade the priority level at any clock cycle.
To eliminate starvation for initiators with low priority, the Masking Priority should be enabled.
Starvation can occur when the higher priority initiators access continuously and the lower priority
initiators can not perform any access (no priority upgrade ability by the initiator and auto priority
upgrade in the expander module is disabled). When the Masking Priority is enabled, the arbiter
dedicates slots for lower priority initiator in which the higher priority initiators are masked.
Reference Manual, Rev. 2
4-4
Freescale Semiconductor
Functional Description
4.2.2.1.1 Weighted Arbitration
The CLASS arbiter supports limited weighted arbitration. Weighted arbitration is needed to
apply non-uniform distribution of the bandwidth from all initiators toward each target. Weighted
arbitration is configurable per CLASS target and gives configurable weights to each initiator. The
CLASS arbiter ensures that when a weighted initiator wins the arbitration, it performs Weight + 1
consecutive transactions before transferring control to another initiator with the same or lower
priority level.
4.2.2.1.2 Late Arbitration
In late arbitration mode, the request is initiated by the class arbiters as late as possible. At the end
of a data burst, this can give better or worse performance for the initiators. The performance
depends on the bursty character of the application and the utilization to the target. This mode is
activated/deactivated by the appropriate bit in the C0ACR (see Section 4.8.26, CLASS
Arbitration Control Register (C0ACR)).
4.2.2.1.3 Priority Masking
When C0ACR[PME] is set, the class arbiters are configured to preserve cycle slots for low
priority accesses. They reserve 1/16 of all cycles for priority 0, 2/16 of all cycles for priority 1 or
0, and 2/16 of all cycles for priority 2, 1, or 0. This mode can decrease overall performance. This
is one of two approaches to eliminate starvation. The other is to use auto-priority upgrade.
4.2.2.1.4 Auto Priority Upgrade
This mode is activated by setting the C0PACRx[AUE] bit (see Section 4.8.3, CLASS Priority
Auto Upgrade Control Registers (C0PACRx)). When active, a pending request has its priority
upgraded to the next higher priority after a specified number of cycles specified by
C0PAVRx[AUV] (see Section 4.8.2, CLASS Priority Auto Upgrade Value Registers
(C0PAVRx)). The upgrade level and timing depend on the current priority value assigned, as
follows:
„ For priority 0 requests, the priority is upgraded to priority 1 after AUV cycles.
„ For priority 1 requests, the priority is upgraded to priority 2 after AUV/2 cycles.
„ For priority 2 requests, the priority is upgraded to priority 3 (highest) after AUV/4 cycles.
The upgrade process continues until the request is processed or it reaches priority 3.
4.2.2.2 CLASS Multiplexer
The CLASS multiplexer includes two FIFOs that connect between the appropriate initiator and
the target. The FIFO depth is 16, thus enabling the multiplexer and arbiter module to deal with 16
open transactions, which received their request acknowledge and are waiting for the end-of-data
or end-of-transaction signals. The CLASS multiplexer is pure logic for the data path and does not
cause any latency.
Reference Manual, Rev. 2
Freescale Semiconductor
4-5
Chip-Level Arbitration and Switching System (CLASS)
4.2.3
Normalizer Module
Each normalizer module is connected to the appropriate multiplexer and arbiter module on one
side and to a specific CLASS target interface on the other side. Each normalizer module is used
as a sampler for full pipeline towards the target. The normalizer module is the only module
within the CLASS that can manipulate the transaction (for example, splitting non-aligned
transactions). An internal signal is used to indicate that optimization is needed. Only the last
normalizer module on the way to the target is used for normalization. All the other normalizer
modules should be used only as samplers. The normalizer module supports the fast confirm
mechanism for writes.
4.2.4
CLASS Control Interface (CCI)
The CLASS control interface (CCI) enables access to the CLASS configuration, control, and
status registers. All write accesses to these registers should use supervisor mode. See Section 4.8
for programming details.
4.3
MSC8156 Initiator CLASS Access Priorities
Table 4-1 summarizes the priorities of the CLASS initiators when accessing targets over the
CLASS. The priority listed in this table is the priority of the accesses by the initiator before any
CLASS remapping (that is, C0PMRx = 0x3210). If the CLASS is remapped (using C0PMRx),
this table represents the arrival priority of the initiator to the CLASS and not the new mapped
value. Note that start-up code (for example, the CodeWarrior initialization files) and boot code
can change the value of C0PMRx from its reset value.
Table 4-1. Initiator CLASS Access Priorities
Initiator
Priority 0
Priority 1
Priority 2
Priority 3
“Low” priority (0)
NA
NA
NA
Cores and
subsystems - Read
NA
NA
“High” priority (2)
NA
Cores and
subsystems - Write
“Low” priority (0)
- Normal write
NA
“High” priority (2)
- If the write stalls
the core
NA
(0)
NA
NA
NA
SRIO priority (0)
SRIO priority (1)
SRIO priority (2)
NA
NA
SRIO priority (0),
SRIO priority (1)
SRIO priority (2)
NA
Cores and
subsystems Prefetch
MAPLE
SRIO - Inbound
(IO, Maintenance,
Doorbell)
SRIO - Inbound
(Message)
comments
A core read transaction
reaches the CLASS in
case of L1/L2 miss or
non-cacheable address
SRIO priority (0) and (1)
both result in CLASS
priority 1
Reference Manual, Rev. 2
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Freescale Semiconductor
MSC8156 Initiator CLASS Access Priorities
Table 4-1. Initiator CLASS Access Priorities (Continued)
Initiator
Priority 0
Priority 1
Priority 2
Priority 3
NA
NA
Priority (2)
NA
RMU - DATA Read
(Outbound Doorbell
or Message)
Priority (0),
Priority (1)
Priority (2)
NA
NA
OCNDMA BD Read
(0)
NA
NA
NA
OCNDMA DATA
Read/Write
(0)
NA
NA
NA
System DMA BD
Read
NA
NA
NA
(3)
PP (0)
PP (1)
PP (2)
PP (3)
PCI Express
Inbound
NA
NA
(2)
NA
TDM
NA
Default Priority (1)
NA
Emergency (Defined
by progrmable
threshold of TDM
FIFO fill)
RMU - BD Read
System DMA DATA
Read/Write
QUICC Engine
subsystem
Normal mode (0) Normal mode (1)
Normal mode (2)
comments
Serial RapidIO priority
(0) and (1) both result in
CLASS priority 0
See Section 14.7.22.1,
Buffer Attributes
(BD_ATTR) and
Section 14.7.22.2,
Multi-Dimensional
Buffer Attributes
(BD_MD_ATTR).
Normal/emergency See Section 18.3.4,
mode (3)
MBus Access and the
Serial DMA Mode
Register (SDMR) in the
QUICC Engine Block
Reference Manual with
Interworking Protocol.
Reference Manual, Rev. 2
Freescale Semiconductor
4-7
Chip-Level Arbitration and Switching System (CLASS)
4.4
CLASS Error Interrupts
The CLASS can generate one error interrupt that is common for all initiators. The error interrupt
is created when the CLASS receives a transaction request with an illegal address. Illegal
addresses are defined as any one of the following 2 cases:
1.
An address which does not belong to any of the address space windows of the enabled
address decoders.
2.
An address which falls within any of the address space windows of the enabled error
address decoders.
When an illegal address is identified by the CLASS, the following events occur.
„ The associated AEIx bit in the CISR is set.
„ The address that was identified as illegal is stored in the associated CEARx and
CEEARx. These registers are locked until the associated AEIx bit in the CISR is cleared
either by a hardware reset or by writing 1 to this bit.
Note:
If the associated AEIx bit in the CISR is already set when the illegal address is
identified (due to a prior illegal address), then the new error address is not stored.
„ If the corresponding AEIEx bit in the CIER is set, an IRQ is issued.
„ The CLASS does not initiate a transaction to any target. However, the CLASS will
continue normally on the initiator side until completion, and report the error. In case of a
read transaction, the CLASS delivers invalid data to the initiator.
„ If, at the time of the error transaction, there are open transactions that did not receive the
end-of-transaction, the expander module stalls all new transaction until all prior
transactions receive the end-of-transaction, close the error transaction, report the
end-of-transaction, report the error, and only then continue with subsequent transactions.
„ Any subsequent requests with a legal address are serviced normally.
Note:
The CLASS does not produce an error when a transaction starts inside a target address
window and finishes outside of the window. This situation must be avoided by the user.
If it occurs, the results are unpredictable.
The error interrupt is logically ORed with internal error interrupts. The internal error interrupts
are associated with each initiator. Thus, the CLASS error interrupt is asserted when at least one
internal interrupt is asserted.
Reference Manual, Rev. 2
4-8
Freescale Semiconductor
CLASS Debug Profiling Unit
4.5
CLASS Debug Profiling Unit
The CLASS supports debug and profiling measurements by the CLASS debug and profiling unit
(CDPU).
4.5.1
Profiling
The user can configure the desired measurement in the CIPCRs and CTPCRs.
Note:
For each CLASS module, only one PMM field among all C0IPCRx and C0TPCRx can
be greater than 0 during profiling.
You can activate the CDPU by:
„ Writing a 1 to the CPCR[PE] bit.
„ Configuring a watch point event in CPCR[WPEC] field.
The CDPU is deactivated by:
„
„
„
„
Writing a 0 to the CPCR[PE] bit.
Configuring a watch point event in CPCR[WPEC] field.
Reaching a time-out in the CPTOR when the CPCR[TOE] bit is set.
CPRCR overflow.
After the desired profiling mode has been chosen, activate the CDPU to perform the
measurement. At the beginning of every measurement, the CLASS Profiling Reference Counter
(CPRCR) starts counting the clock cycles. Read the CPISR[OVE] bit to verify that the
measurement is complete and that the profiling counter values are valid. If the CPISR[OVE] is
clear, read the profiling counters CPRCR and CPGCR and analyze the results.
Reference Manual, Rev. 2
Freescale Semiconductor
4-9
Chip-Level Arbitration and Switching System (CLASS)
4.5.2
Watch Point Unit
The CLASS includes a watch point unit (WPU) for each of the initiator interfaces and for each of
the target interfaces. The WPU can compare programmed values to the real transactions and
generate a watch point event when a match occurs.
Note:
For each CLASS module, only one WPEN field can be set among all C0IWPCRx and
C0TWPCRx when snooping watch point events. That is, only one watch point unit can
be active at a time.
Use the following steps to use the watch point unit:
1.
Clear C0PCR.
2.
Clear C0IPCRx and C0TPCR.
3.
For the time-out mechanism, program C0PTOR and set the C0PCR[TOE] bit.
4.
Define the transaction to be monitored by writing the desired configuration to
C0WPCR, C0WPACR, C0WPEACR, and C0WPAMR.
5.
Enable the watch point units through C0IWPCRx and C0TWPCR.
6.
Set the C0WPRCR[CE] bit to enable counting of the watch point events. If you use the
watch point events to enable/disable the profiling unit according to WPCE, clear this bit.
7.
After the measurement are finished check the following registers:
—
—
—
—
Read the C0PISR[OVE] bit.
In time-out mode, read C0PRCR.
If C0PISR[OVE] is set or if C0PRCR is equal to C0PTOR, the results are not valid.
Read C0PGCRx to get the number of watch point events during the measurement.
Reference Manual, Rev. 2
4-10
Freescale Semiconductor
CLASS Debug Profiling Unit
4.5.3
Event Selection
Events are selected using a combination of the CLASS watch point and profiling registers. Table
4-2 lists the measurement modes, the required configuration settings, and the events measured by
the specific CLASS Profiling General Registers for each CLASS module. See Section 4.8 for the
register details.
Table 4-2. C0PGCRx Events Selection
Configuration Settings for Each Mode
Measurement
Mode
None selected
Initiator Priority
and
Auto-Upgrade
Initiator Access
Type
Initiator Stall
C0WPCR
[CE]
C0TPCR
[TT]
C0TPCR
[PMM]
C0IPCRx
[PMM]
0
0
—
—
00
00
00000
00001
Events Measured
C0PGCR0
C0PGCR1
C0PGCR2
C0PGCR3
—
—
—
—
No. of
No. of
No. of
No. of
Initiator
Initiator
Initiator
Initiator
Requests
Requests
Requests
Autowith
with
with
Upgrade
Priority 1
Priority 2
Priority 3
Allows the user to profile a statistical distribution of transaction priorities. This information can be used to
consider whether other arbitration methods (priority mapping, Auto-upgrade, weighted arbitration, priority
mask enable) should be considered
0
—
00
00010
Initiator
No. of
No. of
No. of
Pending
Initiator
Initiator
Initiator
Request
Read
Real Write Fast Write
cycles (not
Requests
Requests
Requests
acknow(not
(not
ledged)
confirmed) confirmed)
Real/Fast confirmation refers to the type of eot for writes that are requested per MBus transaction.
• Real means that for coherency reasons the eot for write should be high only after the data is written to
the target.
• Fast means that for performance reasons the eot can be high even before the data is written to the
target.
Real/Fast confirmation support is initiator dependent and the user cannot change the related settings. A
summary follows below:
• DSP Cores
− Write through uses fast confirmation
− Write through with SYNCIO generate real confirmation
− Last burst in a line write-back is sent with real confirmation
• DMA. Channel transfers come with fast confirm and real confirm on the last data of a transfer.
• Serial RapidIO Inbound Transactions. When the transfer comes with a response (NWRITE_R), the last
data uses real confirmation and fast confirm for the previous transfer. For NWRITE, data is transferred
with fast confirmation
• Serial RapidIO Outbound Transactions. Supports fast confirm on the last data transfer per channel
transfer and fast confirm for the previous transfer.
• QUICC Engine and PCI Express Transactions. Always uses real confirmation
The resulting information can be used to redesign the code to minimize stalls related to real confirmations.
Use of large transactions reduces the number of real confirmations because they are only required for the
last beat of the transfer.
No. of stall
—
No. of stall
0
—
00
00011
No. of
cycles due
Write After cycles due
to WAR
to TS
Read
events
events
(WAR)
events
By managing WAR and target switching, an initiator can enhance the performance for memory accesses
and thus minimize run time.
Note: Stall at the initiator does not mean that the initiator target data phase is idle; it indicates the delay
after which the next access from the initiator starts at the target after a WAR or TS event.
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4-11
Chip-Level Arbitration and Switching System (CLASS)
Table 4-2. C0PGCRx Events Selection (Continued)
Configuration Settings for Each Mode
Measurement
Mode
Initiator Priority
Upgrade
Initiator Priority
Non-Upgrade
Initiator
Supervisor
Initiator
Bandwidth
Initiator-target
Bandwidth
C0WPCR
[CE]
C0TPCR
[TT]
C0TPCR
[PMM]
C0IPCRx
[PMM]
0
—
00
00100
Events Measured
C0PGCR0
C0PGCR1
C0PGCR2
C0PGCR3
Initiator
Initiator
Initiator
—
Sample 0
Sample 1
Sample 2
Upgrade
Upgrade
Upgrade
cycles
cycles
cycles
Initiator Priority Upgrade measurement counts the number of cycles a low-priority transaction is upgraded
because a high-priority transaction was scheduled into the CLASS pipeline. This upgrading mechanism is
necessary to reduce the service latency of newly issued transactions because the CLASS is ordered in
nature and does not do preemption. A high-priority transaction could otherwise be delayed by preceding
lower priority accesses for long periods of time. The upgrade is to the priority level of the high-priority
transaction and it is only possible if the transaction is upgradable. The upgrade attribute of a transaction is
initiator dependent and it is hard-wired. The system DMA is the only initiator issuing non-upgradable
transactions. The counter measurements take place in the early stages of the CLASS pipeline at different
sample locations. Transactions in sample 0 are older than transactions on sample 1, and transactions in
sample 1 are older than the ones in sample 2. Any type of priority upgrade, including auto-upgrade, is
captured by these counters. These counters provide a good view of the starvation dynamics of the system.
0
—
00
00101
Initiator
Initiator
Initiator
—
Sample 0
Sample 1
Sample 2
No
No
No
Upgrade
Upgrade
Upgrade
cycles
cycles
cycles
Initiator Priority No-Upgrade measurement counts the number of cycles an older low-priority transaction is
not upgraded despite the fact that a newer high-priority is scheduled by the same initiator. Compare with
“Initiator Priority Upgrade”. This applies only to System DMA transactions because they are not upgradable
by default. All other initiator transactions can be upgraded. These counts are not very useful for
performance analysis, but they provide a good view of the starvation dynamics of the system.
0
—
00
00110
Request
No. of
No. of non—
pending
supervisor supervisor
cycles
accesses
accesses
Supervisor/user accesses can be used to profile the amount of time the OS spends running and how much
time is left for the users application. Effective for evaluating the core subsystem supervisor/user mode
usage. The implementation depends on the values configured in M_DSDAx[DAPU]/M_DSDAx[DAPS], and
so forth. See the SC3850 Core Subsystem Reference Manual for configuration details.
—
—
No. of
0
—
00
00111
No. of
Initiator
Initiator
Read Data Write Data
AcknowAcknowledges.
ledges
Can be used to profile the number of data reads and writes. The amount of data that passes through the
initiator port = [(NumberOfReadAck + NumberOfWriteAck) × W]. where W is the port width. Note that an
access may be smaller than the port width.
0
—
00
10000 + T
No. of
No. of
—
—
Read Data Write Data
AcknowAcknowledges
ledges
between
between
Initiator
Initiator
and Target and Target
T
T
Can be used to profile the number of data reads and writes. between an initiator and a specific target The
amount of data that passes through the initiator port = [(NumberOfReadAck + NumberOfWriteAck) × W].
where W is the port width. Note that an access may be smaller than the port width.
Reference Manual, Rev. 2
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Freescale Semiconductor
CLASS Debug Profiling Unit
Table 4-2. C0PGCRx Events Selection (Continued)
Configuration Settings for Each Mode
Measurement
Mode
Arbitration
Winner Priority
Target Access
Splitting
Arbitration
Collision
Target
Bandwidth
Target Stall
Watch Point
C0WPCR
[CE]
C0TPCR
[TT]
C0TPCR
[PMM]
C0IPCRx
[PMM]
0
0
01
00000
Events Measured
C0PGCR0
C0PGCR1
C0PGCR2
C0PGCR3
No. of
No. of
No. of
No. of
priority 0
priority 1
priority 2
priority 3
transtranstranstransactions at
actions at
actions at
actions at
Target T
Target T
Target T
Target T
Can be used to see the priority distribution for a target port
0
1
01
00000
No. of
No. of
—
—
M-byte
N-byte
accesses
accesses
toward
toward
target T.
target T.
M=
N=
Initiator
Initiator
requests
requests
(pre
(post
splitting
splitting
accesses)
accesses)
Target access splitting gives statistical information about the ratio between initiator and target accesses
towards every target. It returns the number of accesses in pre and post splitting. For example, say there
are only 2 types of accesses to some target #T: 64-Byte and 16-Byte, and this target only supports 16-Byte
accesses. Then, if the count shows 10000 initiator accesses and 34000 target accesses, this translates to
8000 × (64-Byte accesses) + 2000 × (16-Byte accesses), and they were split into 8000 × (4 × 16-Byte
accesses) + 2000 × (16-Byte access) = 32000 + 2000 = 34000 accesses
0
0
10
00000
Target T
—
—
—
Pending
Request
cycles
This represents the number of cycles with more than one request directed to Target T.
0
1
10
00000
No. of
No. of
—
—
Target T
Target T
Read Data Write Data
AcknowAcknowledges
ledges
Can be used to profile the number of data reads and writes to Target T. The amount of data that passes
through the target port = [(NumberOfReadAck + NumberOfWriteAck) × W] where W is the port width.Note
that an access can be less than the port width
0
—
11
00000
No. of
No. of stall
—
—
Write after cycles due
to WAR
Read
(WAR)
events
events
By managing WAR event, the system designer can enhance memory access performance and thus
minimize run time.
Note: A WAR stall at the target does not mean that the target bus is idle. It indicates the delay after
which the next access from the initiator starts at the target after a WAR event.
1
—
00
00000
No. of
—
—
—
Watch
Point
Event
Watch point event scan be snooped on any initiator and any target. It can be used for debug and also for
triggering profiling counts that are pre-configured, this is non-intrusive (eliminating the need to write to the
registers in the middle of an application)
Reference Manual, Rev. 2
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4-13
Chip-Level Arbitration and Switching System (CLASS)
4.5.4
Debug and Profiling Events
The CLASS generates two event interrupts:
„ Watch point event (WPE)
„ Overflow event (OVE)
4.6
CLASS Reset
The CLASS implements 2 kinds of reset:
„ Synchronous hard reset.
„ Synchronous soft reset.
4.6.1
Soft Reset
This kind of reset has the following effects:
„ All the CLASS state machines return to their idle state.
„ All the CLASS operation FFs return to their idle state.
„ The CLASS configuration registers are reset as described in the table for each register in
Section 4.8, Programming Model.
4.6.2
Hard Reset
This reset brings all states machines to idle state and sets all CLASS registers to the reset values.
4.7
Limitations
„ The CLASS does not support split transaction between targets. A split transaction starts
inside a targets address space but ends outside of this window. The CLASS does not report
an error in this event and the results are unpredictable. You must avoid this situation.
„ The CLASS does not support pipelined transactions between different targets by the same
initiator. The pipeline is stalled until all transaction to one target are closed before issuing
a transaction to a different target.
„ Arbitration Fairness. Requests with the higher priority levels may cause transactions with
lower priority levels not to be acknowledged, resulting in a starvation condition. This
situation can be prevented by using the auto priority upgrade supported by the expander
module and/or by the multiplexer and arbiter module priority mask mechanism.
„ Do not allow the TDM or QUICC Engine interfaces (Ethernet and SPI) to access the
MAPLE-B block.
„ Do not allow MAPLE-B to access itself.
„ Do not allow cores to access each other.
Reference Manual, Rev. 2
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Freescale Semiconductor
Programming Model
4.8
Programming Model
All the CLASS registers are 32-bit registers. All the read and write accesses are executed through the bus.
The CLASS modules use the following registers:
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Note:
CLASS Priority Mapping Registers (see page 4-16)
CLASS Priority Auto Upgrade Value Registers (see page 4-18)
CLASS Priority Auto Upgrade Control Registers (see page 4-19)
CLASS Error Address Registers (see page 4-20)
CLASS Error Extended Address Registers (see page 4-21)
CLASS Initiator Profiling Configuration Registers (see page 4-23)
CLASS Initiator Watch Point Control Registers (see page 4-25)
CLASS Arbitration Weight Registers (see page 4-26)
CLASS Start Address Decoder x (see page 4-27)
CLASS End Address Decoder x (see page 4-28)
CLASS Attributes Decoder x (see page 4-29)
CLASS IRQ Status Register (see page 4-30)
CLASS IRQ Enable Register (see page 4-31)
CLASS Target Profiling Configuration Register (see page 4-32)
CLASS Profiling Control Register (see page 4-33)
CLASS Watch Point Control Register (see page 4-34)
CLASS Watch Point Access Configuration Register (page 4-36)
CLASS Watch Point Extended Access Configuration Register (see page 4-37)
CLASS Watch Point Address Mask Register (see page 4-38)
CLASS Profiling Time Out Register (see page 4-39)
CLASS Target Watch Point Control Register (see page 4-40)
CLASS Profiling IRQ Status Register (see page 4-41)
CLASS Profiling IRQ Enable Register (see page 4-42)
CLASS Profiling Reference Counter Register (see page 4-42)
CLASS Profiling General Counter Registers (see page 4-43)
CLASS Arbitration Control Register (see page 4-44)
The base address for addressing CLASS registers is 0xFFF18000.
Reference Manual, Rev. 2
Freescale Semiconductor
4-15
Chip-Level Arbitration and Switching System (CLASS)
4.8.1
CLASS Priority Mapping Registers (C0PMRx)
C0PMR[0–11]
Bit
31
CLASS Priority Mapping Registers
30
29
28
27
26
25
24
23
22
Offset 0x800 + x*0x04
21
20
19
18
17
16
—
PB
Type
Reset
Boot
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
Boot
PM3
—
PM2
—
PM1
—
PM0
R/W
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
C0PMRx is used as a look-up table for mapping the priority received from the initiator. By
default the input priority is mapped to an identical value on the output. This register also
enables/disables the priority derivation feature.
Note:
You cannot write to this register while there are open CLASS transactions. The boot
overrrides the default reset value for C0PMR[0–5] only.
Table 4-3 lists the C0PMRx bit field descriptions.
Table 4-3. C0PMRx Bit Descriptions
Name
Reset
Description
—
31–17
PB
16
0
Reserved. Write to 0 for future compatibility.
0
Priority Bypass
Enables/disables the priority derivation
mechanism.
—
15–14
PM3
13–12
—
11–10
PM2
9–8
—
7–6
PM1
5–4
0
Reserved. Write to 0 for future compatibility.
11
Priority Mapping 3
Holds the priority value assigned to
transactions that arrive with a value of 3.
0
Reserved. Write to 0 for future compatibility.
10
Priority Mapping 2
Holds the priority value assigned to
transactions that arrive with a value of 2.
0
Reserved. Write to 0 for future compatibility.
01
Priority Mapping 1
Holds the priority value assigned to
transactions that arrive with a value of 1.
Settings
0
1
Filter the mapped priority with the priority
derivation mechanism.
Pass the mapped priority from initiator to target
with no filtering.
00
01
10
11
Priority 0
Priority 1
Priority 2
Priority 3
00
01
10
11
Priority 0
Priority 1
Priority 2
Priority 3
00
01
10
11
Priority 0
Priority 1
Priority 2
Priority 3
Reference Manual, Rev. 2
4-16
Freescale Semiconductor
Programming Model
Table 4-3. C0PMRx Bit Descriptions (Continued)
Name
Reset
Description
—
3–2
PM0
1–0
0
Reserved. Write to 0 for future compatibility.
0
Priority Mapping 0
Holds the priority value assigned to
transactions that arrive with a value of 0.
Settings
00
01
10
11
Priority 0
Priority 1
Priority 2
Priority 3
Reference Manual, Rev. 2
Freescale Semiconductor
4-17
Chip-Level Arbitration and Switching System (CLASS)
4.8.2
CLASS Priority Auto Upgrade Value Registers (C0PAVRx)
C0PAVR[0–11]
Bit
31
30
CLASS Priority Auto Upgrade Value Registers Offset 0x840 + x*0x04
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
Type
Reset
AUV
R/W
1
1
1
1
1
1
1
1
C0PAVRx holds the value loaded to the priority auto-upgrade counter.
Note:
You can write to this register while there are open CLASS transactions. The AUV field
is loaded into the auto-upgrade counter only when you set the AUE bit in C0PACRx.
Therefore, always update the AUV field in the C0PAVRx before you set the AUE bit.
Table 4-4 lists the C0PAVRx bit field descriptions.
Table 4-4. C0PAVRx Bit Descriptions
Name
Reset
—
31–16
0
AUV
15—0
0xFFFF
Description
Reserved. Write to 0 for future compatibility.
Auto-Upgrade Value
The value loaded into the auto-upgrade counter. The priority of the access determines which bits
of this value are used, as follows:
• Priority 0: All 16 bits are loaded into the counter.
• Priority 1: Bits 15–1 are loaded into bit 14–0 of the counter and a 0 into bit 15.
• Priority 2: Bits 15–2 are loaded into bits 13–0 of the counter and 0 into bits 15 and 14.
Reference Manual, Rev. 2
4-18
Freescale Semiconductor
Programming Model
4.8.3
CLASS Priority Auto Upgrade Control Registers (C0PACRx)
C0PACR[0–11]
Bit
31
30
CLASS Priority Auto Upgrade Control Registers Offset 0x880 + x*0x04
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
AUE
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0PACRx controls the priority auto-upgrade mechanism.
Note:
You can write to this register while there are open CLASS transactions.
Table 4-5 lists the C0PACRx bit field descriptions.
Table 4-5. C0PACRx Bit Descriptions
Name
Reset
Description
—
31–1
AUE
0
0
Reserved. Write to 0 for future compatibility.
0
Auto-Upgrade Enable
Enables/disables the auto-upgrade
mechanism.
Note:
Settings
0
1
Auto-upgrade mechanism disabled.
Auto-upgrade mechanism enabled.
This bit can only be cleared by a
hardware reset.
Reference Manual, Rev. 2
Freescale Semiconductor
4-19
Chip-Level Arbitration and Switching System (CLASS)
4.8.4
CLASS Error Address Registers (C0EARx)
C0EAR[0–11]
Bit
31
CLASS Error Address Registers
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
ERR_ADD
R
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
Type
Reset
0
0
0
0
0
0
Offset 0x980 + x*0x04
0
8
7
ERR_ADD
R
0
0
The C0EAR is used to store the address (32 least significant bits) of the internal transaction when
an error has been identified by the CLASS. When an error occurs and an error bit is set in the
C0ISR, the internal transaction address is stored and the C0EARx is locked and does not update
even if another error with a different transactions address occurs. Only when the AEIx bit in the
C0ISR is cleared (either by a hardware reset or by writing a 1 to it) is C0EARx unlocked.
Table 4-6 lists the C0EARx bit field descriptions.
Table 4-6. C0EARx Bit Descriptions
Name
Reset
ERR_ADD
31–0
0
Note:
Description
Error Address
This field stores the 32 lsbs of the address of the internal transaction that caused the error.
The generated interrupts correspond to the following sources:
—
—
—
—
—
—
—
—
—
—
C0EAR0 = Address generated by core 0.
C0EAR1 = Address generated by core 1.
C0EAR2 = Address generated by core 2.
C0EAR3 = Address generated by core 3.
C0EAR4 = Address generated by core 4.
C0EAR5 = Address generated by core 5.
C0EAR6 = Address generated by MAPLE-B port 0.
C0EAR7 = Address generated by MAPLE-B port 1.
C0EAR8 = Address generated by HSSI (serial RapidIO or PCI Express interface).
C0EAR9 = Address generated by SEC, QUICC Engine subsystem (Ethernet or SPI),
Debug system, or TDM.
— C0EAR10 = DMA port 0.
— C0EAR11 = DMA port 1.
Reference Manual, Rev. 2
4-20
Freescale Semiconductor
Programming Model
4.8.5
CLASS Error Extended Address Registers (C0EEARx)
C0EEAR[0–11]
Bit
31
30
CLASS Extended Error Address Registers
29
28
27
26
25
24
23
22
21
Offset 0x9C0 + x*0x04
20
19
18
17
—
16
RW
Type
Reset
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
SA
Type
Reset
—
SRC_ID
ERR_ADD
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The C0EEAR stores the most significant 4 bits of the address of the internal transaction when an
error has been identified by the CLASS. This register also stores the attributes and the source ID
of this transaction. When an error occurs and an error bit is set in the C0ISR, the internal
transaction address is stored and the C0EEAR is locked and is not updated even if another error
with a different transactions address/attributes occurs. Only when the AEI bit in the CISR is
cleared (either by a hardware reset or by writing a 1 to it) is C0EEAR unlocked.
Table 4-7 lists the C0EEARx bit field descriptions.
Table 4-7. C0EEARx Bit Descriptions
Name
Reset
—
31–17
RW
16
0
Reserved. Write to 0 for future compatibility.
0
0
1
Write.
Read.
—
15
SA
14
0
Read/Write
This field indicates whether the transaction that caused the
error was a read or a write.
Reserved. Write to 0 for future compatibility.
0
1
Not supervisor.
Supervisor.
—
13–9
SRC_ID
8–4
0
Supervisor Access
This field indicates whether the transaction that caused the
error was in supervisor mode.
Reserved. Write to 0 for future compatibility.
0
Source ID
Identifies the source ID of the initiator that caused the error.
0x00 Core 0
0x01 Core 1
0x02 Core 2
0x03 Core 3
0x06 MAPLE-B
0x07 MAPLE-B
0x08 DMA Controller
0x09 DMA Controller
0x0B QUICC Engine subsystem
0x0C Serial RapidIO Port 0
0x0D Serial RapidIO Port 1
0x0E TDM
All other values reserved.
ERR_ADD
3–0
0
Error Address
This field stores the 4 msbs of the address of the internal transaction that caused the error.
0
Description
Settings
Reference Manual, Rev. 2
Freescale Semiconductor
4-21
Chip-Level Arbitration and Switching System (CLASS)
Reference Manual, Rev. 2
4-22
Freescale Semiconductor
Programming Model
4.8.6
CLASS Initiator Profiling Configuration Registers (C0IPCRx)
C0IPCR[0–11]
Bit
31
30
CLASS Initiator Profiling Configuration Registers‘Offset 0xA00 + x*0x04
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
—
Type
Reset
PMM
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0IPCRx controls the CLASS initiator profiling measurements. Each initiator has a dedicated
C0IPCR which is numbered according to the initiator number within each CLASS module. The
CLASS can perform only one measurement for a specific module at a time. Select the desired
measurement for the initiator, enter the PMM value in the associated C0IPCR and make sure all
the other C0IPCR and the C0TPCR for that CLASS are cleared.
Note:
Only one PMM field among all C0IPCRx and C0TPCR can be greater than 0 during
profiling.
Table 4-8 lists the C0IPCRx bit field descriptions.
Table 4-8. C0IPCRx Bit Descriptions
Name
Reset
Description
—
31–5
PMM
4–0
0
Reserved. Write to 0 for future compatibility.
0
Profiling Measurement Mode
Determines the profiling measurement
mode for the matching initiator.
Note:
This register can only be cleared
by a hardware reset.
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000–
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000–
11111
No measurement.
Initiator priority and auto-upgrade.
Initiator access type.
Initiator stall.
Initiator priority upgrade.
Initiator priority non-upgrade.
Initiator supervisor.
Initiator bandwidth.
reserved
Target 0 bandwidth.
Target 1 bandwidth.
Target 2 bandwidth.
Target 3 bandwidth.
Target 4 bandwidth.
Target 5 bandwidth.
Target 6 bandwidth.
Target 7 bandwidth.
reserved
Reference Manual, Rev. 2
Freescale Semiconductor
4-23
Chip-Level Arbitration and Switching System (CLASS)
Table 4-9. Initiator Numbers
Initiator
Number
Initiator Module
0
DSP core subsystem 0
1
DSP core subsystem 1
2
DSP core subsystem 2
3
DSP core subsystem 3
4
DSP core subsystem 4
5
DSP core subsystem 5
6
MAPLE port 0
7
MAPLE port 1
8
HSSI
9
SEC, Ethernet, SPI, TDM, or
Debug
10
DMA port 0
11
DMA port 1
Reference Manual, Rev. 2
4-24
Freescale Semiconductor
Programming Model
4.8.7
CLASS Initiator Watch Point Control Registers (C0IWPCRx)
C0IWPCR[0–11]
Bit
31
30
CLASS Initiator Watch Point Control Registers Offset 0xA40 + x*0x04
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
WPEN
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0IWPCRx controls the Watch Point Unit operation for the associated initiator. The Watch Point
Unit monitors a specific access defined by the C0WPCRx, C0WPACRx, C0WPEACRx, and
C0WPAMR. Each initiator can be enabled/disabled to monitor the selected access. You can write
to this register while there are open CLASS transactions.
Note:
Only one WPEN field can be set among all C0IWPCRx and C0TWPCRx when
snooping watch point events.
Table 4-10 lists the C0IWPCRx bit field descriptions.
Table 4-10. C0IWPCRx Bit Descriptions
Name
Reset
Description
—
31–1
WPEN
0
0
Reserved. Write to 0 for future compatibility.
0
Watch Point Enable
Enables/disables the auto-upgrade
mechanism.
Note:
Settings
0
1
The watch point is disabled.
The watch point is enabled.
This bit can only be cleared by a
hardware reset.
Reference Manual, Rev. 2
Freescale Semiconductor
4-25
Chip-Level Arbitration and Switching System (CLASS)
4.8.8
CLASS Arbitration Weight Registers (C0AWRx)
C0AWR[0–11]
Bit
31
30
CLASS Arbitration Weight Registers
29
28
27
26
25
24
Offset 0xA80 + x*0x04
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
WEIGHT
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The value in C0AWRx determines the arbitration weight for the associated initiator. An initiator
with arbitration weight of W is allowed to initiate up to W+1 consecutive transactions.
Note:
When another initiator requests for access with higher priority level, the CLASS Arbiter
chooses the higher priority request instead of the weighted winner.
Table 4-11 lists the C0AWRx bit field descriptions.
Table 4-11. C0AWRx Bit Descriptions
Name
Reset
Description
—
31–4
0
Reserved. Write to 0 for future compatibility.
WEIGHT
3–0
0
Weight
Contains the arbitration weight assigned to
the associated initiator.
Note:
Settings
Recommended Values:
0011
Use for C0AWR0 through C0AWR9
0111
Use for C0AWR10 and C0AWR11
This register can only be cleared
by a hardware reset.
Using the reset values can result in poor initial system performance. Table 4-11 lists the
recommended initial arbitration weight settings to apply after reset to increase initial performance
levels during application development. These are just initial recommendations and can be
changed by the designer according to the application requirements. However, the recommended
settings will yield much higher performance than using the hardware default values. As a general
rule, these recommended settings select a weighted arbitration of 3 for cores, MAPLE-B,
RapidIO controllers, and other peripheral controllers; these are controlled by C0AWR0 through
C0AWR9. Use a weighted arbitration of 7 for DMA transactions, which are controlled by
C0AWR10 and C0AWR11. Also, see Table 4-29 for recommended initial settings for the
CLASS Arbitration Control Register (C0ACR).
Reference Manual, Rev. 2
4-26
Freescale Semiconductor
Programming Model
4.8.9
CLASS0 Start Address Decoder x (C0SADx)
C0SAD5
C0SAD6
Bit
31
CLASS0 Start Address Decoders
30
29
28
27
26
25
24
—
23
22
21
Offset 0xC00 +x*0x04
20
19
18
17
16
SA35 SA34 SA33 SA32 SA31 SA30 SA29 SA28
R/W
Type
Reset
SAD5
SAD6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
SAD5
SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0SADx configure the address decoding of CLASS toward the DDR controllers (C0SAD5 and
C0SAD6). They contain the start address of the window assigned to the specific port.
Note:
To ensure proper operation, never modify the contents of the register while the specific
decoder is enabled. Always clear the associated CATDx[DEN] bit before changing the
contents of C0SADx.
These registers are reset by a hardware reset only. Table 4-25 lists the C0SADx bit field
descriptions.
Table 4-12. C0SADx Bit Descriptions
Name
Reset
—
31–24
0
SA[35–12]
23–0
Port 5 = 0x040000 (DDR1 start)
Port 6 = 0x080000 (DDR2 start)
Note:
Description
Reserved. Write to 0 for future compatibility.
Start Address 35–12
The 24 msb of the start address of the specified port window. The lsbs
are all zeros.
Never write to these registers when there are open transactions being handled by the
CLASS to the specified target controlled by the register.
Reference Manual, Rev. 2
Freescale Semiconductor
4-27
Chip-Level Arbitration and Switching System (CLASS)
4.8.10
CLASS End Address Decoder x (C0EADx)
C0EAD5
C0EAD6
Bit
31
CLASS End Address Decoders
30
29
28
27
26
25
24
—
23
22
Offset 0xC40 + x*0x04
21
20
19
18
17
16
EA35 EA34 EA33 EA32 EA31 EA30 EA29 EA28
R/W
Type
Reset
EAD5
EAD6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Type
Reset
EAD5
EAD6
EA27 EA26 EA25 EA24 EA23 EA22 EA21 EA20 EA19 EA18 EA17 EA16 EA15 EA14 EA13 EA12
R/W
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C0EADx configure the address decoding of CLASS toward the DDR controllers (C0EAD5 and
C0EAD6). They contain the end address of the window assigned to the specific port.
Note:
To ensure proper operation, never modify the contents of the register while the specific
decoder is enabled. Always clear the associated CATDx[DEN] bit before changing the
contents of C0EADx.
These registers are reset by a hardware reset only. Table 4-25 lists the C0EADx bit field
descriptions.
Table 4-13. C0EADx Bit Descriptions
Name
Reset
—
31–24
0
EA[35–12]
23–0
Port 5 = 0x05FFFF (DDR1 end)
Port 6 = 0x09FFFF (DDR2 end)
Note:
Description
Reserved. Write to 0 for future compatibility.
End Address 35–12
The 24 msb of the end address of the specified port window. The lsbs
are all zeros. You must make sure that this value is greater than or
equal to the start address for the same window. If the end address is
equal to the start address, the window size is 4 Kbytes.
Never write to these registers when there are open transactions being handled by the
CLASS to the specified target controlled by the register.
Reference Manual, Rev. 2
4-28
Freescale Semiconductor
Programming Model
4.8.11
CLASS Attributes Decoder x (C0ATDx)
C0ATD5
C0ATD6
Bit
CLASS0 Attributes Decoders
31
30
29
28
27
26
25
24
Offset 0xC80 + X*0x04
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
DEN
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
C0ATDx controls the functionality of each specific decoder for CLASS toward the DDR
controllers (C0ATD5 and C0ATD6). They contain the bit that enables/disables the specific port.
If a decoder is disabled, it never indicates a hit, even if the address corresponds to the decoder
address window. In this case the CLASS treats the space as if it is not assigned to any port.
However, any transaction that was acknowledged up to and including the cycle in which DEN is
cleared continues normally until completed.
Note:
To ensure proper operation, do not enable the specific decoder before the start and end
addresses are specified in the associated C0SADx and C0EADx.
These registers are reset by a hardware reset only. Table 4-25 lists the C0ATDx bit field
descriptions.
Table 4-14. C0ATDx Bit Descriptions
Name
Reset
—
31–1
0
Reserved. Write to 0 for future compatibility.
DEN
0
1
Decoder Enable
Enables/disables the specified decoder.
Note:
Description
Settings
0
1
Disables the decoder.
Enables the decoder.
Never write to these registers when there are open transactions being handled by the
CLASS to the specified target controlled by the register.
Reference Manual, Rev. 2
Freescale Semiconductor
4-29
Chip-Level Arbitration and Switching System (CLASS)
4.8.12
CLASS IRQ Status Register (C0ISR)
C0ISR
Bit
CLASS IRQ Status Register
31
30
29
28
27
26
25
24
Offset 0xD80
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AEI6
AEI5
AEI4
AEI3
AEI2
AEI1
AEI0
0
0
0
0
0
0
0
—
Type
Reset
0
0
AEI11 AEI10 AEI9
0
0
0
0
0
AEI8 AEI7
R/W
0
0
The C0ISR indicates when an event occurs that requires the generation of an interrupt. There is a
dedicated bit for each initiator. An interrupt is generated only when a status bit is set and the
corresponding bit in the IRQ Enable register is set. Bits are cleared by writing ones to them.
Writing a zero has no effect.
Note:
You can write to or read this register at any time. The register is reset by a hard or soft
reset.
Table 4-15 lists the C0ISR bit field descriptions.
Table 4-15. C0ISR Bit Descriptions
Name
Reset
Description
—
31–12
AEI[11–0]
11–0
0
Reserved. Write to 0 for future compatibility.
0
Address Error Interrupt 11–0
A bit is set if for a received transaction
request, it does not belong to any port
address space or falls inside one of the
error areas.
Settings
0
1
No error.
Error detected.
Reference Manual, Rev. 2
4-30
Freescale Semiconductor
Programming Model
4.8.13
CLASS IRQ Enable Register (C0IER)
C0IER
Bit
CLASS IRQ Enable Register
31
30
29
28
27
26
25
24
Offset 0xDC0
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
AEIE11 AEIE10 AEIE9 AEIE8 AEIE7 AEIE6 AEIE5 AEIE4 AEIE3 AEIE2 AEIE1 AEIE0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The C0IER is used to enable/disable the generation of interrupts that have occurred. There is a
dedicated bit for each initiator. If a C0IER bit is cleared the corresponding bit in the C0ISR is
masked. This register is reset by the hardware reset only.
Table 4-16 lists the C0IER bit field descriptions.
Table 4-16. C0IER Bit Descriptions
Name
Reset
Description
—
31–12
AEIE[11–0]
11–0
0
Reserved. Write to 0 for future compatibility.
0
Address Error Interrupt Enable
Used to enable/disable the address error
interrupt for an initiator.
Settings
0
1
Interrupt masked.
Interrupt enabled.
Reference Manual, Rev. 2
Freescale Semiconductor
4-31
Chip-Level Arbitration and Switching System (CLASS)
4.8.14
CLASS Target Profiling Configuration Register (C0TPCR)
C0TPCR
Bit
31
CLASS Target Profiling Configuration Register
30
29
28
27
26
25
24
Offset 0xE00
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TT
—
—
Type
Reset
TN
—
PMM
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0TPCR is used to control the CLASS target profiling measurements. Each CLASS module can
perform only one measurement for a specific module at a time. Use the values of TT and TN to
select the module. Use the PMM value to select the measurement. Only write the PMM value to
this register when all the C0IPCRx are cleared.
Note:
For each CLASS module, you can only monitor one transaction. Therefore, only one
PMM field in C0IPCRx and C0TPCR can be greater than 0 during profiling.
Table 4-17 lists the C0TPCR bit field descriptions.
Table 4-17. C0TPCR Bit Descriptions
Name
Reset
Description
—
31–13
0
Reserved. Write to 0 for future compatibility.
TT
12
0
Target Type
Selects the module used for target
profiling. Used with PMM. See PMM
settings.
—
11
0
Reserved. Write to 0 for future compatibility.
TN
10–8
0
Target Number
Indicates the number of selected target.
Settings
0
1
000
001
010
011
100
101
110
111
Arbiter.
Normalizer.
CCSR
MAPLE
Core 4 and 5 Bridge
Core 2 and 3 Bridge
Core 0 and 1 Bridge
DDR1
DDR2
M3
Reference Manual, Rev. 2
4-32
Freescale Semiconductor
Programming Model
Table 4-17. C0TPCR Bit Descriptions (Continued)
Name
Reset
Description
Settings
—
7–2
0
Reserved. Write to 0 for future compatibility.
PMM
1–0
0
Profiling Measurement Mode
Selects the profiling measurement for the
selected target.
If TT = 0:
00 No profiling measurement.
01 Arbitration winner priority measurement.
10 Collisions measurement.
11 reserved.
If TT = 1:
00 No profiling measurement.
01 Transaction splitting measurement.
10 Bandwidth measurement.
11 Stall measurement.
4.8.15
CLASS Profiling Control Register (C0PCR)
C0PCR
CLASS Profiling Control Register
Bit
31
30
29
28
27
26
25
24
Offset 0xE04
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
WPEC
—
TOE
—
PE
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0PCR controls the CLASS profiling operation. The register is reset only by a hardware reset.
Table 4-18 lists the C0PCR bit field descriptions.
Table 4-18. C0PCR Bit Descriptions
Name
Reset
Description
—
31–10
0
Reserved. Write to 0 for future compatibility.
WPEC
9–8
0
Watch Point Event Configuration
Controls the effects of a Watch Point Unit
event.
—
7–5
0
Reserved. Write to 0 for future compatibility.
TOE
4
0
Time-Out Enable
Enables/disables the time-out mechanism.
—
3–1
0
Reserved. Write to 0 for future compatibility.
PE
0
0
Profiling Enable
Enables/disables the debug profiling unit
operation.
Settings
00
01
10
11
No effect.
Assertion of watch point event sets PE.
Assertion of watch point event clears PE.
Assertion of watch point event toggles PE.
0
1
Time-out function disabled.
Time-out function enabled.
0
1
Profiling unit disabled.
Profiling unit enabled.
Reference Manual, Rev. 2
Freescale Semiconductor
4-33
Chip-Level Arbitration and Switching System (CLASS)
4.8.16
CLASS Watch Point Control Registers (C0WPCR)
C0WPCR
Bit
31
CLASS Watch Point Control Registers
30
29
28
27
26
25
24
23
22
21
Offset 0xE08
20
19
18
17
—
16
UPE
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
SIE
PRE
AE
CE
0
0
0
0
0
WCE EATE
Type
Reset
0
0
BCE ATRE ATAE
R/W
0
0
0
0
—
0
SPVE RWE
0
0
0
0
C0WPCR controls the CLASS watch point unit operation. You can configure this register to
monitor a selected access type and count the number of times it occurs. The register is reset only
by a hardware reset. Table 4-19 lists the C0WPCR bit field descriptions.
Table 4-19. C0WPCR Bit Descriptions
Name
Reset
Description
—
31–17
UPE
16
0
Reserved. Write to 0 for future compatibility.
Settings
0
Upgradeable Compare Enable
Enables/disables the time-out mechanism.
0
1
WCE
15
0
Write-with-Confirm Compare Enable
Enables/disables the write-with-confirm
type comparison.
0
1
EATE
14
0
EOT Attributes Compare Enable
Enables/disables the EOT attributes
comparison.
0
1
—
13
SIE
12
0
Reserved. Write to 0 for future compatibility.
0
0
1
Source ID compare disabled.
Source ID compare with C0WPEACR enabled.
PRE
11
0
Source ID Compare Enable
Enables/disables the source ID
comparison.
Priority Level Compare Enable
Enables/disables the priority level
comparison.
0
1
BCE
10
0
Byte Count Compare Enable
Enables/disables the byte count field
comparison.
0
1
ATRE
9
0
Atomic Result Compare Enable
Enables/disables the atomic result type
comparison.
0
1
ATAE
8
0
Atomic Access Compare Enable
Enables/disables the atomic access type
comparison.
0
1
Priority level compare disabled.
Priority level compare with C0WPEACR
enabled.
Byte count compare disabled.
Byte count compare with the field in
C0WPEACR enabled.
Atomic result type compare disabled.
Atomic result type compare with C0WPACR
enabled.
Atomic access type compare disabled.
Atomic access type compare with C0WPACR
enabled.
—
7–4
SPVE
3
0
Reserved. Write to 0 for future compatibility.
0
Supervisor Access Compare Enable
Enables/disables supervisor access
comparison.
0
1
Upgradeable type compare disabled.
Upgradeable type compare with C0WPEACR
enabled.
Write-with-confirm type compare disabled.
Write-with-confirm type compare with
C0WPEACR enabled.
EOT attributes compare disabled.
EOT attributes compare with C0WPEACR
enabled.
Supervisor type compare disabled.
Supervisor type compare with C0WRACR
enabled.
Reference Manual, Rev. 2
4-34
Freescale Semiconductor
Programming Model
Table 4-19. C0WPCR Bit Descriptions (Continued)
Name
Reset
Description
Settings
RWE
2
0
Read/Write Compare Enable
Enables/disables read/write type
comparison.
0
1
AE
1
0
0
1
CE
0
0
Address Compare Enable
Enables/disables comparison of the
access address.
Count Enable
Enables/disables the counter for watch
point events.
Read/write type compare disabled.
Read/write type compare with C0WPACR
enabled.
Address compare disabled.
Address compare with C0WPACR enabled.
0
1
Counter 1 disabled for watch point events.
Counter 1 enabled for watch point events.
Reference Manual, Rev. 2
Freescale Semiconductor
4-35
Chip-Level Arbitration and Switching System (CLASS)
4.8.17
CLASS Watch Point Access Configuration Register (C0WPACR)
C0WPACR
Bit
CLASS Watch Point Access Configuration Registers
31
30
ATR
ATA
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
0
Type
Reset
0
29
0
28
27
26
—
0
0
25
SPV
0
0
24
23
22
RW
R/W
0
0
21
20
Offset 0xE0C
19
18
17
16
ADDR
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
ADDR
R/W
0
0
0
0
0
0
0
0
0
C0WPACR, along with C0WPEACR, configures the selected access to monitor. The watch point
monitoring occurs only if the respective function is enabled in the C0WPCR. The register is reset
only by a hardware reset. Table 4-20 lists the C0WPACR bit field descriptions.
Table 4-20. C0WPACR Bit Descriptions
Name
Reset
Description
Settings
ATR
31
0
Atomic Result
Defines the atomic result type to monitor.
0
1
Atomic access failed.
Atomic access succeeded.
ATA
30
0
Atomic Access
Defines the atomic access type to monitor.
0
1
Non-atomic access.
Atomic access.
—
29–26
0
Reserved. Write to 0 for future compatibility.
SPV
25
0
Supervisor Access
Defines the supervisor access type to
monitor.
0
1
Non-supervisor access.
Supervisor access.
RW
24
0
Read/Write Access
Defines the access type to monitor.
0
1
Write.
Read.
ADDR
23–0
0
Address[35–12]
This field, along with the ADDM field in
C0WPAWMR, defines the start and range
of the addresses the watch point unit
monitors.
Note: For every bit in
C0WPAMR[ADDM] that is
cleared, make sure the
corresponding bit is cleared in the
ADDR. The bit location in ADDM
(b) corresponds to the b + 12 bit
location in ADDR.
Reference Manual, Rev. 2
4-36
Freescale Semiconductor
Programming Model
4.8.18
CLASS Watch Point Extended Access Configuration Register
(C0WPEACR)
C0WPEACR
Bit
CLASS Watch Point Extended Access Configuration Registers
31
30
29
UP
WC
28
27
—
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
4
3
2
1
0
0
0
0
0
EATTR
Type
Reset
0
0
0
0
0
0
Bit
15
14
13
12
11
10
Offset 0xE10
—
R/W
SI
Type
Reset
0
0
0
0
0
9
8
7
6
5
PR
BC
R/W
0
0
0
0
0
0
0
0
0
0
0
0
C0WPEACR, along with C0WPACR, configures the selected access to monitor. The watch point
monitoring occurs only if the respective function is enabled in the C0WPCR. The register is reset
only by a hardware reset. Table 4-21 lists the C0WPEACR bit field descriptions.
Table 4-21. C0WPEACR Bit Descriptions
Name
Reset
Description
Settings
UP
31
0
Upgradeable Access
Defines the upgradeable access type to
monitor.
0
1
Non-upgradeable access.
Upgradeable access.
WC
30
0
Write-with-Confirm Access
Defines the write-with-confirm access type
to monitor.
0
1
Fast confirm access.
Write-with-confirm access.
—
29–28
0
Reserved. Write to 0 for future compatibility.
EATTR
27–24
0
EOT Attributes
Defines the EOT attributes to monitor.
—
23–16
0
0x0–
0x7
0x8
0x9
0xA
0xB
0xC‘
0xD
0xE
0xF
Reserved
Target port 0 CCSRs
Target port 1 MAPLE-B
Target port 2 Reserved
Target port 3 Cores 2 and 3
Target port 4 Cores 0 and 1
Target port 5 DDRC1 memory
Target port 6 DDRC2 memory
Target port 7 M3 memory
Reserved. Write to 0 for future compatibility.
Reference Manual, Rev. 2
Freescale Semiconductor
4-37
Chip-Level Arbitration and Switching System (CLASS)
Table 4-21. C0WPEACR Bit Descriptions (Continued)
Name
Reset
SI
15–11
0
Source
Defines the source ID to monitor.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
PR
10–9
0
Priority
Defines the priority level to monitor.
00
01
10
11
BC
8–0
0
Byte Count
This field defines the value of the byte
count that the watch point unit monitors.
The byte count to monitor can be from 1 to 511
bytes.
4.8.19
Description
Core0
Core1
Core2
Core3
Core 4
Core 5
MAPLE Port 0
MAPLE Port 1
SerDes Bridge
Peripherals Bridge
DMA Port 0
DMA Port 1
Priority 0 (highest)
Priority 1
Priority 2
Priority 3 (lowest)
CLASS Watch Point Address Mask Registers (C0WPAMR)
C0WPAMR
Bit
Settings
31
CLASS Watch Point Address Mask Registers
30
29
28
27
26
25
24
Offset 0xE14
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
—
Type
Reset
ADDM
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
C0WPAMR controls the address range monitored by the watch point unit. The register is reset
only by a hardware reset. Table 4-22 lists the C0WPAMR bit field descriptions.
Reference Manual, Rev. 2
4-38
Freescale Semiconductor
Programming Model
Table 4-22. C0WPAMR Bit Descriptions
Name
Reset
—
31–8
0
Reserved. Write to 0 for future compatibility.
ADDM
7–0
0
Address Mask
Defines the range and alignment
of the address to monitor if
address monitoring is enabled.
The start address is defined in
C0WPACR[ADDR].
Note: For every bit in ADDM
that is cleared, make
sure the corresponding
bit is cleared in the
C0WPACR.
4.8.20
Description
00000000 Aligned with a range of 1 MB.
10000000 Aligned with a range of 512 KB.
11000000 Aligned with a range of 256 KB.
11100000 Aligned with a range of 128 KB.
11110000 Aligned with a range of 64 KB.
11111000 Aligned with a range of 32 KB.
11111100
Aligned with a range of 16 KB.
11111110
Aligned with a range of 8 KB.
11111111
Aligned with a range of 4 KB.
All other values are reserved.
CLASS Profiling Time-Out Registers (C0PTOR)
C0PTOR
Bit
Settings
31
CLASS Profiling Time-Out Registers
30
29
28
27
26
25
24
Offset 0xE18
23
22
21
20
19
18
17
16
TO
R/W
Type
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
Type
Reset
TO
R/W
1
1
1
1
1
1
1
1
C0PTOR is used to stop the profiling unit operation. When the C0PRCR reaches the value stored
in C0PTOR and C0PCR[TOE] is set, the CLASS clears the C0PCR[PE] bit to disable the
profiling unit. When C0PCR[PE] clears, the CLASS stops all profiling counters. The register is
reset only by a hardware reset. Table 4-23 lists the C0PTOR bit field descriptions.
Table 4-23. C0PTOR Bit Descriptions
Name
Reset
Description
TO
31–0
0xFFFFFFFF
Time-Out
Holds the time-out value used to stop the profiling unit when the time-out function is enabled.
Reference Manual, Rev. 2
Freescale Semiconductor
4-39
Chip-Level Arbitration and Switching System (CLASS)
4.8.21
CLASS Target Watch Point Control Registers (C0TWPCR)
C0TWPCR
Bit
31
CLASS Target Watch Point Control Registers
30
29
28
27
26
25
24
Offset 0xE1C
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
WPEN7 WPEN6 WPEN5 WPEN4 WPEN3 WPEN2 WPEN1 WPEN0
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The C0TWPCR controls the watch point unit operation for CLASS targets. The watch point unit
monitors a specific access defined in C0WPCR, C0WPACR, C0WPEACR, and C0WPAMR.
Each target can be enabled/disabled for monitoring the specified access type. The register is reset
by a hard reset only.
Note:
Only one WPEN field can be set among all the C0IWPCRx and C0TWPCR. That is,
only one watch point unit can be active at a time.
Table 4-15 lists the C0TWPCR bit field descriptions.
Table 4-24. C0TWPCR Bit Descriptions
Name
Reset
Description
—
31–8
WPEN[7–0]
7–0
0
Reserved. Write to 0 for future compatibility.
0
Watch Point Enable 7–0
Each bit enables monitoring of access by
the associated target.
Settings
0
1
The watch point unit for the associated target is
disabled.
The watch point unit for the associated target is
enabled.
Reference Manual, Rev. 2
4-40
Freescale Semiconductor
Programming Model
4.8.22
CLASS Profiling IRQ Status Register (C0PISR)
C0PISR
Bit
31
CLASS Profiling IRQ Status Registers
30
29
28
27
26
25
24
Offset 0xE20
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WPE
OVE
0
0
—
Type
Reset
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0PISR indicates that a watch point event occurred or that the C0PRCR overflowed. An interrupt
is generated if the status bit is set and the corresponding bit in C0PIERx is set to enable the
interrupt. You can write to or read the register at any time. Write a 1 to a bit to clear it; writing a
0 has no effect. The register is reset by a hard or soft reset. Table 4-25 lists the C0PISR bit field
descriptions.
Table 4-25. C0PISR Bit Descriptions
Name
Reset
Description
Settings
—
31–2
0
Reserved. Write to 0 for future compatibility.
WPE
1
0
Watch Point Event
Enables monitoring of access by the
associated target.
0
1
No watch point event occurred.
Watch point event captured.
OVE
0
0
Overflow Event
Enables monitoring of access by the
associated target.
0
1
No overflow occurred.
C0PRCR overflowed (reached 0xFFFFFFFF)
during the last measurement.
Reference Manual, Rev. 2
Freescale Semiconductor
4-41
Chip-Level Arbitration and Switching System (CLASS)
4.8.23
CLASS Profiling IRQ Enable Register (C0PIER)
C0PIER
Bit
31
CLASS Profiling IRQ Enable Registers
30
29
28
27
26
25
24
Offset 0xE24
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
WPEE OVEE
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C0PIER enables/disables the generation of interrupts by the debug profiling unit. You can write
to the register at any time. The register is reset by a hard reset only. Table 4-26 lists the C0PIER
bit field descriptions.
Table 4-26. C0PIER Bit Descriptions
Name
Reset
Description
—
31–2
0
Reserved. Write to 0 for future compatibility.
WPEE
1
0
Watch Point Event Enable
Enables/disables a watch point interrupt.
0
1
Watch point interrupt is masked.
Watch point interrupt is enabled.
OVEE
0
0
Overflow Event Enable
Enables/disables an overflow interrupt.
0
1
Overflow interrupt is masked.
Overflow interrupt is enabled.
4.8.24
CLASS Profiling Reference Counter Register (C0PRCR)
C0PRCR
Bit
Settings
31
CLASS Profiling Reference Counter Registers
30
29
28
27
26
25
24
Offset 0xE40
23
22
21
20
19
18
17
16
C0T
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Type
Reset
CNT
R
0
0
0
0
0
0
0
0
C0PRCR is the reference counter for all profiling measurements. This read-only register counts
the number of cycles occurring during the profiling measurement or during the watch point unit
operation. The counter starts counting from zero when the profiling unit is enabled. The C0PRCR
stops when the profiling unit is disabled, or when the C0PRCR reaches the value stored in
C0PTOR and TOE is set, which causes the CLASS to clear the PE bit to disable the profiling
Reference Manual, Rev. 2
4-42
Freescale Semiconductor
Programming Model
unit. When PE clears, the CLASS stops all profiling counters. The register is reset only by a
hardware reset only. Table 4-27 lists the C0PRCR bit field descriptions.
Table 4-27. C0PRCR Bit Descriptions
Name
Reset
CNT
31–0
0
4.8.25
Description
Counter
Holds the reference counter for the profilers.
CLASS Profiling General Counter Registers (C0PGCRx)
C0PGCR[0–3]
Bit
31
CLASS Profiling General Counter Registers
30
29
28
27
26
25
24
Offset 0xE44 + x*0x04
23
22
21
20
19
18
17
16
CNT
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Type
Reset
CNT
R
0
0
0
0
0
0
0
0
C0PGCRx is used to count profiling unit or watch point unit events. This read-only register
counts the number of cycles occurring during the profiling measurement or during the watch
point unit operation. The counter starts counting from zero when the profiling unit is enabled.
The C0PRCR stops when the profiling unit is disabled, or when the C0PRCR reaches the value
stored in C0PTOR and TOE is set, which causes the CLASS to clear the PE bit to disable the
profiling unit. When PE clears, the CLASS stops all profiling counters. The register is reset only
by a hardware reset. Table 4-28 lists the C0PGCR bit field descriptions.
Table 4-28. C0PGCR Bit Descriptions
Name
Reset
Description
CNT
31–0
0
Counter
Holds the counter value of the selected measurement. Table 4-2 lists the measurements counted
by each counter for each configuration combination.
Reference Manual, Rev. 2
Freescale Semiconductor
4-43
Chip-Level Arbitration and Switching System (CLASS)
4.8.26
CLASS Arbitration Control Register (C0ACR)
C0ACR
Bit
31
CLASS Arbitration Control Registers
30
29
—
28
27
26
25
24
23
22
PME
Offset 0xFC0
21
20
19
18
17
16
—
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LA6
LA5
LA4
LA3
LA2
LA1
LA0
0
LA7
R/W
0
0
0
0
0
0
0
0
0
—
Type
Reset
0
0
0
0
0
0
The C0ACR controls the CLASS arbiters. There is a dedicated bit for each arbiter that controls
the Late Arbitration mode of the associated arbiter. When Late Arbitration mode is enabled, the
arbiter delays the decision according to the size of the last winner access. The arbiter calculates
the number of cycles to allow until a winner decision must be made. This is done to keep the bus
always full, and make the winner decision as late as possible. When Late Arbitration mode is
disabled, the arbiter makes a decision every clock cycle.The register is reset by a hard reset only.
Table 4-29 lists the C0ACR bit field descriptions.
Table 4-29. C0ACR Bit Descriptions
Name
Reset
Description
—
31–29
PME
28
0
Reserved. Write to 0 for future compatibility.
0
Priority mask disabled.
Priority mask enabled.
—
27–8
LA[7–0]
7–0
0
Priority Mask Enable
0
Enables/disables the operation of the
1
priority mask unit for starvation elimination.
Reserved. Write to 0 for future compatibility.
Late Arbitration 7–0
Enables/disables late arbitration mode for
the associated arbiter.
Note: As with the arbitration weight (see
Section 4.8.8, CLASS Arbitration
Weight Registers (C0AWRx), on
page 4-26), the default value for
this field does not yield optimal
performance. Freescale
recommends that after reset,
write a value of 0xFC to this field.
This value assigns late arbitration
to the cores, the M2 memory,
DDR memory, and the M3
memory. This is just an initial
value, and can be changed
according to the application
requirements and system traffic.
Late arbitration disabled.
Late arbitration enabled.
0
Settings
0
1
Reference Manual, Rev. 2
4-44
Freescale Semiconductor
5
Reset
The reset and control signals provide many options for MSC8156 operation by configuring
various modes and features during power-on reset. Most of these features are configured by
loading a reset configuration word to the MSC8156 device that combine with a few direct
configuration inputs sampled during the reset sequence. This section describes the various ways
to reset and configure the MSC8156 device.
5.1 Reset Operations
The MSC8156 has several inputs to the reset logic:
„
„
„
„
„
„
„
„
Power-on reset (PORESET)
External hard reset (HRESET)
External soft reset (SRESET)
Software watchdog reset
JTAG reset
RapidIO reset
Software hard reset
Software soft reset
All of these reset sources are fed into the reset controller and, depending on the source of the
reset, different actions are taken. The reset status register described in Section 5.3.3 indicates the
last sources to cause a reset.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-1
Reset
5.1.1
Reset Sources
Table 5-1 describes reset sources.
Table 5-1. Reset Sources
Name
Description
Power-on reset (PORESET)
Input pin. Asserting this pin initiates the power-on reset flow that resets all the device and
configures various attributes of the device including its clock modes.
Hard reset (HRESET)
This is a bidirectional I/O pin. The MSC8156 can detect an external assertion of
HRESET only if it occurs while the MSC8156 is not asserting reset. During HRESET,
SRESET is asserted. HRESET is an open-drain pin.
Soft reset (SRESET)
Bidirectional I/O pin. The MSC8156 can only detect an external assertion of SRESET if it
occurs while the MSC8156 is not asserting reset. SRESET is an open-drain pin.
Software watchdog reset
After the MSC8156 watchdog timer counts to zero, a software watchdog reset is
generated. The enabled software watchdog event then generates an internal hard reset
sequence.
RapidIO reset
When the RapidIO logic asserts the RapidIO hard reset signal, an internal hard reset
sequence is generated.
JTAG reset
When JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is
generated.
Software hard reset
A hard reset sequence can be initialized by writing to a memory mapped register (RCR)
Software soft reset
A soft reset sequence can be initialized by writing to a memory mapped register (RCR)
5.1.2
Reset Actions
The MSC8156 reset control logic determines the cause of reset, synchronizes it if necessary, and
resets the appropriate internal hardware. Each reset flow has different impact on the device logic.
Power-on reset has the greatest impact, resetting the entire device, including clock logic and error
capture registers. Hard reset resets the entire device excluding clock logic and error capture
registers, while Soft reset initializes the internal logic while maintaining the system
configuration. All reset types generate a reset to the cores. The memory controllers, system
protection logic, interrupt controller, and I/O pins are initialized only on hard reset. Soft reset
initializes the internal logic while maintaining the system configuration. Asserting external
SRESET generates a soft reset to the DSP cores and to the remainder of the device. Table 5-2
identifies reset actions for each reset source.
MSC8156 Reference Manual, Rev. 2
5-2
Freescale Semiconductor
Reset Operations
Table 5-2. Reset Actions for Each Reset Source
Reset Source
Clocks and
PLLs
Reset Logic
Error Capture
Registers
Performance Monitor
HSSI PLLs and Logic
Timers
CLASS (most registers, see
Section 4.8, Programming
Model, on page 4-15 for
details)
Reset
Configuration
Words
Loaded
Other
Internal
Logic
HRESET
Driven
SRESET
and Soft
Reset
Driven to
Cores
• Power-on
reset
Yes
Yes
Yes
Yes
Yes
Yes
• External
hard reset
• Software
watchdog
reset
• RapidIO
reset
• Software
hard reset
No
Yes
No
Yes
Yes
Yes
• External soft
reset
• JTAG soft
reset
• Software soft
reset
No
No
No
Yes
No
Yes
5.1.3
Power-On Reset Flow
Assertion of the external PORESET signal initiates the power-on reset flow. PORESET should be
asserted externally for at least 32 input clock cycles after stable external power is applied to the
MSC8156 device. When PORESET is deasserted, the MSC8156 starts the configuration process.
The MSC8156 asserts HRESET and SRESET throughout the power-on reset sequence, including
during configuration. Configuration time varies according to the configuration source and CLKIN
frequency. Initially, the reset configuration inputs are sampled to determine the configuration
source and the input clock division mode. Next, the MSC8156 starts loading the reset
configuration words. When the clock mode values in the reset configuration word low load, the
PLLs begin to lock, after locking, each PLL distributes clock signals to the device. When all
clocks are locked and the reset configuration words are loaded, HRESET is released. SRESET is
released 21 or 36 clocks later (depending on the reset configuration word source).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-3
Reset
5.1.4
Detailed Power-On Reset Flow
The detailed power-on reset (PORESET) flow for the MSC8156 is as follows:
1.
The user asserts PORESET (and optionally HRESET).
2.
Power is applied to meet the specifications in the MSC8156 Technical Data Sheet.
The user asserts PORESET (and optionally HRESET) causing all registers to be initialized
to their default states and most I/O drivers to be tri-stated (some clock, clock enabled,
and system control signals are active).
4.
The user applies a stable CLKIN signal and stable reset configuration inputs (RCW_SRC,
RC, STOP_BS).
5.
Deassert PORESET after at least 32 stable CLKIN clock cycles; counting the 32 cycles
should only start after VDDIO has reached its nominal value as specified in the MSC8156
Technical Data Sheet.
6.
The device samples the reset configuration input signals to determine the reset
configuration word source.
7.
The device starts loading the reset configuration word. Loading time depends on the
reset configuration word source.
8.
Once Reset Configuration Word Low is loaded, the system PLL begins to lock.
9.
The device keeps driving HRESET low until all PLLs are locked and the reset
configuration words are loaded.
10. Deassert the optional HRESET, if not done earlier.
3.
Note:
The JTAG logic must always be initialized by asserting TRST. There is no need to
assert SRESET when HRESET is asserted.
The internal reset to the cores and the remaining logic is deasserted. I/O drivers are
enabled.
12. After HRESET is deasserted, it can take 41000 OCN cycles for the SerDes block to exit
reset and lock its internal PLL. Read the HSSI_SR[SERDES1_RST_DONE] and
HSSI_SR[SERDES2_RST_DONE] bits to determine when the SerDes reset is
complete. See the High Speed Serial Interface Status Register (HSSI_SR] description in
Chapter 8 General Configuration Registers for details.
13. If enabled, the HSSI complex interfaces are now ready to accept external requests, and
the core boot code fetch can proceed, if enabled. The MSC8156 is now in its ready state.
11.
Figure 5-1 shows a timing diagram of the power-on reset flow.
MSC8156 Reference Manual, Rev. 2
5-4
Freescale Semiconductor
Reset Operations
CLKIN
PORESET
(input)
stable clock
Min. 32
CLKIN
cycles
PLLs are locked (no
external indication)
HRESET
(output)
Device is
ready
SRESET
(output)
TRST
(input)
Reset Configuration
input signals
Reset Configuration
Words loading
Start loading reset
configuration words
End loading reset
configuration words.
Duration depends on source
Figure 5-1. Power-On Reset Flow
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-5
Reset
Figure 5-2 shows a timing diagram of power-on reset flow with RCW_SRC = 000. In this mode,
the external pins RC[15–0] are sampled four times in order to get all the 64 bits RCW.
stable clock
CLKIN
Min. 32
CLKIN
cycles
PORESET
(input)
PLLs are
locked (no
external
indication)
HRESET
(output)
Device is
ready
SRESET
(output)
TRST
(input)
Reset Configuration
input signals
RCWHR[31:16]
RCWHR[15:0]
RCWLR[31:16]
Start loading reset
configuration words
RCWLR[15:0]
RC[15:0]
(input)
End loading reset
configuration words.
RCW_LSEL_0
(output)
RCW_LSEL_1
(output)
RCW_LSEL_2
(output)
RCW_LSEL_3
(output)
Figure 5-2. Power-on Reset Flow for RCW_SRC = 000
MSC8156 Reference Manual, Rev. 2
5-6
Freescale Semiconductor
Reset Operations
5.1.5
HRESET Flow
The HRESET flow may be initiated externally by asserting HRESET or internally when the
MSC8156 detects a reason to assert HRESET. In both cases, the device continues asserting
HRESET and SRESET throughout the HRESET flow. The hard reset sequence time is 1286 CLKIN
cycles. The reset configuration source, the reset configuration word, and the input clock division
mode are not affected by hard reset (they are only affected by a power-on reset), so the MSC8156
immediately configures the device. After the configuration sequence completes, the MSC8156
releases both HRESET and SRESET signals and exits the HRESET flow. Use an external pull-up
resistor to deassert the signals. After deassertion is detected, the device waits for a 16-cycle
period before testing the presence of an external (hard/soft) reset. The HSSI complex logic and
PLL are out of reset after about 41000 OCN cycles. Read the HSSI_SR[SERDES1_RST_DONE]
and HSSI_SR[SERDES2_RST_DONE] bits to determine when the SerDes reset is complete. See
the High Speed Serial Interface Status Register (HSSI_SR] description in Chapter 8 General
Configuration Registers for details.
Note:
Because the MSC8156 does not sample the reset configuration signals (RCW_SRC, RC,
STOP_BS) during a hard reset flow, setting a new value on those pins (different from
the settings during power-on reset) has no effect.
Figure 5-3 shows a timing diagram of the hard reset flow.
CLKIN
stable clock
PORESET
(input)
HRESET
(input or output)
Device is
ready
SRESET
(output)
Reset Configuration
input signals
Figure 5-3. Hard Reset Flow
5.1.6
SRESET Flow
The SRESET flow is initiated externally by asserting SRESET or internally when the MSC8156
detects a cause to assert SRESET. In both cases, the MSC8156 asserts SRESET for 512 CLKIN clock
cycles, after which the MSC8156 releases SRESET and exits the SRESET state. An external pull-up
resistor should be used to deassert SRESET; after deassertion is detected, the device waits for a
16-cycle period before testing for the presence of an external (hard/soft) reset. When SRESET is
asserted, internal hardware is reset, but the hard reset configuration does not change.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-7
Reset
5.2 Reset Configuration
The MSC8156 is initialized using two complementary methods. Initially, a small number of input
signals (RCW_SRC[0–2]) are sampled during the first two CLKIN cycles after the deassertion of
PORESET (during the power-on reset flow). These signals determine whether a reset configuration
word is required and the device source interface from which it is loaded (see Table 5-1). The
RCW_SRC[0–2] signals should remain valid until the deassertion of HRESET. Depending on the
configuration signal values, the MSC8156 may continue with loading the reset configuration
word.
5.2.1
Reset Configuration Signals
Reset configuration input signals are located on device pins that have other functions when the
device is not in the reset state. These input signals sampled values are written into registers
during the assertion of PORESET after a stable clock is supplied (the power-on reset flow). The
inputs must be pulled high or low by external resistors as long as HRESET is asserted. During the
PORESET flow, all other signal drivers connected to these signals must be tri-stated. Refer to the
MSC8156 Technical Data Sheet for the recommended resistor values used to pull reset
configuration signals high or low. The values loaded from these sampled inputs are accessible to
software through memory-mapped registers described in Section 5.3. They are used to configure
the device operation.
5.2.2
Reset Configuration Words Source
The reset configuration word source options permit the MSC8156 to load reset configuration
words from an EEPROM via the I2C interface, a combination of external pins and hard-coded
values, or to use hard-coded default options.
Table 5-3. Reset Configuration Word Sources (Defined by RCW_SRC[0–2])
Value
(Binary)
Meaning
000
Multiplexed external RCW loading. The RCW is driven by external logic on RC[15–0]. The RCW_LSEL[3–0]
selects which bits should be driven on RC[15–0].
001
Reset configuration word is loaded from an I2C EEPROM in 8-bit addressing mode. The internal MSC8156
hardware reads the RCW from EEPROM slave address 1010000 (or 1010111 in case of multi device and
reset slave) with single byte addressing.
010
Reset configuration word is loaded from an I2C EEPROM in 16-bit addressing mode. MSC8156 hardware
reads the RCW from EEPROM slave address 1010000 (or 1010111 in case of multi device and reset slave)
with two byte addressing.
011
Some bits of the reset configuration word are loaded from external pins and others by default.
100
Hard coded option #1. Reset configuration word is loaded from internal hard coded option 1.
101
Hard coded option #2. Reset configuration word is loaded from internal hard coded option 2.
Note:
The value of the reset configuration signals affects the duration of power-on and hard
reset sequences.
MSC8156 Reference Manual, Rev. 2
5-8
Freescale Semiconductor
Reset Configuration
5.2.3
Reset Configuration Input Signal Selection and Reset Sequence
Duration
Table 5-4 shows how to pull down (0) or pull up (1) the reset configuration input signals
(RCW_SRC) for various configurations. The reset sequence duration is measured from the
deassertion of PORESET to the deassertion of HRESET. The SRESET signal is deasserted 21 CLKIN
cycles after the deassertion of HRESET for sources that do not use the I2C interface and 36 CLKIN
cycles for sources that use the I2C interface.
Table 5-4. Selecting Reset Configuration Input Signals
CLKIN
Frequency
RCW_SRC[0–2]
Reset Sequence
Duration in CLKIN
Cycles
Duration in ms
66 MHz
000, 011–101
17426
0.264
66 MHz
001, 010
255156
3.866
100 MHz
000, 011-101
17426
0.174
100 MHz
001, 010
255156
2.552
5.2.4
Reset Configuration Words
Various device functions are initialized by loading the reset configuration words during the
power-on reset flow. All configurable features are reconfigured only during a power-on reset
flow. The MSC8156 decides which interface is used according to reset configuration input
signals, as described in Section 5.2.2.
Section 5.3 describes the functions and modes configured by the reset configuration words. Note
that the reset configuration settings are accessible to software through the following read-only
memory-mapped registers:
„ Reset Configuration Word Low Register (RCWLR). See Section 5.3.1 for details.
„ Reset Configuration Word High Register (RCWHR). See Section 5.3.2 for details.
„ Reset Status Register (RSR). See Section 5.3.3 for details.
5.2.5
Loading The Reset Configuration Words
The MSC8156 loads the reset configuration words from an I2C serial EEPROM, or combination
of default values and external pins, or uses a hard-coded configuration, as selected by the reset
configuration inputs described in Section 5.2.2. The following subsections describe these options
in detail.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-9
Reset
5.2.5.1 Loading From an I2C EEPROM (RCW_SRC[0–2] = 001 or 010)
When a MSC8156 is configured by the reset configuration input signals to load the reset
configuration words from an EEPROM via the I2C interface, it uses the I2C unit boot sequencer
in a special mode. In this mode, the I2C boot sequencer is activated to load the reset configuration
words while the rest of the device remains in the reset state (HRESET is asserted).
5.2.5.1.1 Using The Boot Sequencer For Reset Configuration
Note:
For detailed description about the I2C interface and the boot sequencer, refer to
Chapter 24, I2C.
When used to load the reset configuration words, the I2C module addresses the first EEPROM,
reads the preamble, and then reads the first two data structures. The device latches the reset
configuration words internally and the I2C module enters its reset state until HRESET is
deasserted. There should be no other I2C traffic when the boot sequencer is active. After HRESET
is deasserted, the boot sequencer mode is disabled.
5.2.5.1.2 EEPROM Slave Address
A reset master MSC8156 is selected by holding its STOP_BS signal low during the power-on
reset flow. The reset master uses 0b1010000 for the EEPROM calling address. A reset slave uses
0b1010111 for the EEPROM calling address. The EEPROM to be addressed must contain the
reset configuration information and be programmed to respond to the 0b1010000 address. The
EEPROM device must have address inputs connected to GND in multi device reset applications.
No additional EEPROMs are accessed by the boot sequencer in reset configuration mode. See
also Section 5.2.5.1.5, Loading Multiple Devices From a Single I2C EEPROM, on page 5-11.
5.2.5.1.3 EEPROM Data Format In Reset Configuration Mode
The I2C module expects a specific data format in the EEPROM. The first three bytes should be
the preamble and should contain a value of 0xAA55AA. The I2C module verifies that this
preamble is correctly detected before proceeding further. The two reset configuration words,
should follow the preamble and should use the required format provided in Section 6.2.2.3, Boot
File Format, on page 6-16. Within each configuration word, the first 3 bytes are reserved and
must contain the value 0xFFFFFF. After the first 3 bytes, 4 bytes of data should hold the desired
value of the reset configuration word. The boot sequencer assumes that a big endian address is
stored in the EEPROM.
If a preamble fail or any other I2C bus error is detected, the device stops processing and remains
in a hard reset state with HRESET asserted and most of the I/O drivers are disabled. If reset
configuration word loading from the EEPROM fails, the user must assert the PORESET signal for
at least 100 µs duration to resume operation.
MSC8156 Reference Manual, Rev. 2
5-10
Freescale Semiconductor
Reset Configuration
5.2.5.1.4 Single Device Loading From I2C EEPROM
The MSC8156 can be the only device loading the reset configuration word from the I2C
EEPROM. In this case STOP_BS pin must be driven low during the power on and hard reset
sequences. The hardware connection is shown in Figure 5-4.
RCW_SRC[0–2]
MSC8156E
VDD
I2C EEPROM
3
SRESET
I2C_SCL
I2C_SCL
I2C_SDA
I2C_SDA
HRESET
PORESET
STOP_BS
VDD
Figure 5-4. Single Device I2C Reset Configuration
5.2.5.1.5 Loading Multiple Devices From a Single I2C EEPROM
When the MSC8156 device shares the I2C EEPROM device with other MSC8156 devices to load
the reset configuration words, one device must be a reset master and the rest must be reset slaves.
The definition of reset slave or reset master is latched internally during power-on reset sequence.
In this mode, the RCW_SRC inputs must be the same for all slaves and the master.
The reset configuration implementation involves a software for the reset master and glue logic.
The hardware connection is shown in Figure 5-5. The STOP_BS signal input to the reset master
must be driven low during the power on reset sequence while all the slaves inputs must be driven
high. During the power on reset assertion, the master cannot drive the STOP_BS output bus
because its role as master is not enabled yet. Pull-ups are required; refer to the MSC8156
Technical Data Sheet for appropriate resistor values to pull the slave STOP_BS input signal high.
In the first stage of reset configuration, the reset master reads its own reset configuration words.
It accesses the I2C EEPROM while all other reset slaves are stopped. When PORESET is
deasserted, the STOP_BS is latched in the reset block after few cycles and defines the reset master
and slaves. It also keeps all the reset slave I2C controllers in idle state while the reset master starts
to access the EEPROM slave using address 0b1010000. Then the reset master must exit from
reset and run the internal code.
In the second stage, the reset master reads the slave RCWs and stores the values in its memory.
See Chapter 6, Boot Program for how to determine the number of reset slaves to be configured.
The reset master core reads the slave RCWs from the I2C EEPROM. Then, it configures its I2C
controller to emulate an EEPROM device for each reset slave. The reset master emulates
EEPROM using the slave address 0b1010111.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-11
Reset
In the last stage, the reset master releases the STOP_BS for each slave in a known order. The
released reset slave accesses the I2C bus to read from slave address 0b1010111. The order of
reading the slave RCWs is the order for their connection.
Note:
The STOP_SLV_BS glue logic supports a five pin bus. For up to five reset slaves, the
master drives STOP_SLV_BS directly to the selected slave. For five to fifteen slaves, the
glue logic encodes the signals from the master and selects the slave to drive with
STOP_SLV_BS based on its decoded value.
The external reset logic may reset the system as a unit, or it may be configured to reset individual
devices. Individual resets permit redundancy support during system debugging to allow
problematic devices to be disabled and replaced by a redundant device.
Multi device is described in detail in Section 6.1.4, Multi Device Support for the I2C Bus, on
page 6-4.
VDD
RCW_SRC[0–2]
Reset Logic
MSC8156E
I2C EPROM
3
SRESET
I2C_SCL
A[0–2]
I2C_SDA
I2C_SCL
I2C_SDA
HRESET
GPIO
Decoder
PORESET
VDD
STOP_BS
RCW_SRC[0–2]
SRESET
MSC8156E
I2C_SCL
I2C_SDA
HRESET
VDD
PORESET
STOP_BS
Figure 5-5. Multi Device I2C Reset Configuration Hardware
MSC8156 Reference Manual, Rev. 2
5-12
Freescale Semiconductor
Reset Configuration
5.2.5.2 Loading Multiplexed RCW from External Pins (RCW_SRC[0–2] = 000)
When the MSC8156 device is configured to use the multiplexed loading method, it latches all
bits of the reset configuration word from the external pins. In this case, the sampled RCW bits are
transferred with RCW_LSEL[0–3] glue logic using the hardware shown in Figure 5-6. In this mode,
the 64 bits of the RCW are loaded in four passes using only RC[15–0]. RC16 is not used, and
RC[20–17] are redefined as the lane select signals (RCW_LSEL[0–3], respectively), which provide the
gating signals for each set of 16 bits transferred. .
MSC8156
16
RC
SRESET
4
RCW_LSEL[0–3]
HRESET
RCW_SRC
4
3
PORESET
STOP_BS
Figure 5-6. Multiplexed External Pins Reset Configuration
Figure 5-2 on page 5-6 shows the timing of the gating signals and indicates which RCW bits are loaded by each
lane signal. See Table 3-5 for a detailed description of the lane select signals. The gating summary is as follows:
„
„
„
„
Lane 0 (RCW_LSEL0) gates RC[15–0] to RCWLR bits 15–0
Lane 1 (RCW_LSEL1) gates RC[15–0] to RCWLR bits 31–16
Lane 2 (RCW_LSEL2) gates RC[15–0] to RCWHR bits 15–0
Lane 3 (RCW_LSEL3) gates RC[15–0] to RCWHR bits 31–16
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-13
Reset
5.2.5.3 Loading Reduced RCW From External Pins (RCW_SRC[0–2] = 011)
When the MSC8156 device is configured to use the reduced RCW, the MSC8156 latches some
bits of the reset configuration word from external pins. The other bits of the RCWs are loaded
from default hard coded values. The hardware connection is shown in Figure 5-7.
RCW_SRC[0–2]
MSC8156E
RC[21–0]
3
SRESET
HRESET
PORESET
STOP_BS
Figure 5-7. External Pins Reduced Reset Configuration
5.2.5.3.1 Reduced External Reset Configuration Word Low Field Values
Table 5-5 defines the combined External and Hard Coded Reset Configuration Word Low field
values.
Table 5-5. Combined External and Hard Coded Reset Configuration Word Low Values
Bits
Name
Value
Meaning
31–30
CLKO
00
Select PLL0 divided output clock to be driven on CLKO
29
—
0
Reserved. Should be cleared.
28–24
S2P
0, RC[21–18]
S2P. See Table 5-9 for details.
22–20
S1P
0, RC[17–15]
S1P. See Table 5-9 for details.
19–18
—
00
Reserved. Should be cleared.
17
SCLK2
RC14
SerDes2 (RapidIO interface 2) reference clock. A 0 selects
100 Mhz and a 1 selects 125 MHz. See Table 5-9 for details
and limitations.
16
SCLK1
RC14
SerDes1 (RapidIO interface 1) reference clock. This clock is
identical to SCLK2 in reduced mode and is driven by RC14.
15–6
—
0000000000
5–0
MODCK
00, RC[13–10]
Reserved. Should be cleared.
MODCK[5–4] = 00, MODCK[3–0] = RC[13–10].
MSC8156 Reference Manual, Rev. 2
5-14
Freescale Semiconductor
Reset Configuration
5.2.5.3.2 Reduced External Reset Configuration Word High Field Values
Table 5-6 defines the combined External and Hard Coded Reset Configuration Word High field
values.
Table 5-6. Combined External and Hard Coded Reset Configuration Word High Field Values
Bits
Name
Value
Meaning
31–30
—
00
Reserved. Should be cleared.
29
EWDT
0
Disable Watch Dog Timers.
28
PRDY
0
PCI Express not ready.
27–24
BPRT
0, RC[9–7]
See for details Table 5-10.
23
RIO
1
RapidIO access enabled.
22
RPT
RC6
21
RHE
0
RapidIO host mode disabled.
20–19
—
00
Reserved. Should be cleared.
18
RM
0
Not reset master.
17
BP
0
Boot patch disabled.
16–13
—
00000
12
GE1
RC5
0 - TDM2 and TDM3 are driven on pins.
1 - RGMII of GE1 is driven on pins.
11
GE2
RC4
0 - TDM0 and TDM1 are driven on pins.
1 - RGMII of GE2 is driven on pins.
10
R1A
0
SerDes Port 1 RapidIO interface does not accept all.
9
R2A
0
SerDes Port 2 RapidIO interface does not accept all.
8–3
DEVID
00, RC[3–0]
2
—
0
Reserved. Should be cleared.
1
RMU
0
RMU access local memory on internal port number 0
0
CTLS
1
Common transport type is Large System.
RapidIO pass-through enable bit.
Reserved. Should be cleared.
DEVID[5–4] = 00, DEVID[3–0] = RC[3–0]
5.2.5.4 Default Reset Configuration Words (RCW_SRC[0–2] = 100 or 101)
When the MSC8156 device is configured not to load the RCW from I2C EEPROM or external
pins, it can be initialized using one of the two hard-coded default options listed in Table 5-7 and
Table 5-8.
5.2.5.4.1 Hard Coded Reset Configuration Word Low Field Values
Table 5-7 defines the Hard Coded Reset Configuration Word Low field values.
Table 5-7. Hard Coded Reset Configuration Word Low Field Values
Bits
Name
Value
Meaning
31–30
CLKO
00
Select PLL0 divided output clock to be driven on CLKO
29
—
0
Reserved. Should be cleared.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-15
Reset
Table 5-7. Hard Coded Reset Configuration Word Low Field Values (Continued)
Bits
Name
Value
Meaning
28–24
S2P
01010
SerDes Port 2 PCI Express 1x, SGMII1, SGMII2
23–20
S1P
0011
SerDes Port 1 Serial RapidIO 4x 3.125 GHz
19–18
—
00
Reserved. Should be cleared.
17
SCLK2
1
SerDes2 (RapidIO interface 2) reference clock is 125 MHz
16
SCLK1
1
SerDes1 (RapidIO interface 1) reference clock is 125 MHz
15–6
—
0000000000
5–0
MODCK
000000
000001
Reserved. Should be cleared.
RCW_SRC = 100.
RCW_SRC = 101
5.2.5.4.2 Hard Coded Reset Configuration Word High Field Values
Table 5-8 defines the Hard Coded Reset Configuration Word High field values.
Table 5-8. Hard Coded Reset Configuration Word High Field Values
Bits
Name
Value
Meaning
31–30
—
00
Reserved. Should be cleared
29
EWDT
0
Disable Watch Dog Timers
28
PRDY
0
PCI Express not ready.
27–24
BPRT
0000
23
RIO
1
RapidIO access is enabled.
22
RPT
0
RapidIO pass-through is disabled.
21
RHE
0
RapidIO host mode is disabled.
20-19
—
00
Reserved. Should be cleared
18
RM
0
Not reset master
17
BP
0
Boot patch disabled.
16–13
—
00000
12
GE1
1
RGMII GE1 on GPIO pins
11
GE2
1
RGMII GE2 on GPIO pins
10
R1A
0
SerDes Port 1 RapidIO interface does not accept all
9
R2A
0
SerDes Port 2 RapidIO interface does not accept all
8-3
DEVID
000000
2
—
0
Reserved. Should be cleared
1
RMU
0
RMU access local memory on internal port number 0
0
CTLS
1
Common transport type is Large System.
In Hard Coded RCW, this field is ignored, and the boot port is
Serial RapidIO interface 1
Reserved. Should be cleared
Device ID
MSC8156 Reference Manual, Rev. 2
5-16
Freescale Semiconductor
Reset Programming Model
5.3 Reset Programming Model
This section describes the following reset registers in detail:
„
„
„
„
„
„
Reset Configuration Word Low Register (RCWLR), page 5-17.
Reset Configuration Word High Register (RCWHR), page 5-19.
Reset Status Register (RSR), page 5-22.
Reset Protection Register (RPR), page 5-24.
Reset Control Register (RCR), page 5-25.
Reset Control Enable Register (RCER), page 5-26.
Note:
The Reset register base address is 0xFFF24800.
5.3.1
Reset Configuration Word Low Register (RCWLR)
RCWLR
Bit
Reset Configuration Word Low Register
31
30
29
—
CLKO
Type
Reset
Bit
15
14
13
28
27
26
25
23
22
21
20
19
18
S2P
—
S1P
R
Value depends on the reset configuration word low loaded during reset flow.
12
11
10
9
—
Type
Reset
24
Offset 0x00
8
7
6
PLL1
DIS
—
5
4
3
17
16
SCLK2 SCLK1
2
1
0
MODCK
R
Value depends on the reset configuration word low loaded during reset flow.
The RCWLR is a read-only register set according to the reset configuration word low loaded
during the reset flow. Table 5-9 defines the RCWLR bit fields.
Table 5-9. RCWLR Bit Descriptions
Name
Reset
Description
CLKO
31–30
0
CLKOUT Source
This field selects the source for CLKOUT. See
Chapter 7, Clocks for source clock definitions.
Settings
00 PLL0 divided output clock.
01 PLL1 divided output clock.
10 PLL2 divided output clock.
11 CLKOUT is always low.
—
29
0
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-17
Reset
Table 5-9. RCWLR Bit Descriptions (Continued)
Name
Reset
Description
S2P
28–24
0
SerDes2 Protocol
Selects the SerDes protocol to use.
Note: It is valid to program RCWLR[S1P]
and RCWLR[S2P] to have SGMII1 on
both ports, SGMII2 on both ports, or to
have SGMII1 and SGMII2 on both
ports. An internal multiplexer always
routes only two physical connections
to the QUICC Engine controllers. If the
SGMII interfaces are configured by
S1P and S2P, SGMII1 (if selected by
S1P and S2P) is physically connected
to SerDes Port 1 and SGMII2 (if
selected by S1P and S2P) is
physically connected to SerDes Port 2
S1P
23–20
0
SerDes1 Protocol
Selects the SerDes protocol to use.
Note: It is valid to program RCWLR[S1P]
and RCWLR[S2P] to have SGMII1 on
both ports, SGMII2 on both ports, or to
have SGMII1 and SGMII2 on both
ports. An internal multiplexer always
routes only two physical connections
to the QUICC Engine controllers. If the
SGMII interfaces are configured by
S1P and S2P, SGMII1 (if selected by
S1P and S2P) is physically connected
to SerDes Port 1 and SGMII2 (if
selected by S1P and S2P) is
physically connected to SerDes Port 2
—
19–18
0
Reserved. Write to zero for future compatibility.
SCLK2
17
0
SerDes2 Reference Clock
Selects the SerDes2 reference clock. 100 MHz
clock can work for all protocols and frequencies
except for 3.125 Gbaud RapidIO; 125 MHz
works for all protocols and frequencies with no
exceptions.
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010–
11111
No protocol active.
RapidIO 4x 1.25 GHz
RapidIO 4x 2.5 GHz
RapidIO 4x 3.125 GHz
RapidIO 1x 3.125 GHz
RapidIO 1x 1.25 GHz/SGMII1/SGMII2
RapidIO 1x 2.5 GHz/SGMII1/SGMII2
RapidIO 1x 1.25 GHz/SGMII2
Reserved
Reserved
PCI Express 1x/SGMII1/SGMII2
PCI Express 1x/SGMII2
PCI Express 1x/RapidIO 1x 1.25 GHz
PCI Express 4x
PCI Express 2x/SGMII1/SGMII2
Reserved.
PCI Express 1x/RapidIO 1x 2.5 GHz
PCI Express 1x
RapidIO 1x 1.25 GHz
RapidIO 1x 2.5 GHz
RapidIO 1x 2.5 GHz/SGMII2
Reserved.
PCI Express 2x/SGMII2
PCI Express 2x/RapidIO 1x 1.25 GHz
PCI Express 2x/RapidIO 1x 2.5 GHz
PCI Express 2x
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011–
1111
No protocol active.
RapidIO 4x 1.25 GHz
RapidIO 4x 2.5 GHz
RapidIO 4x 3.125 GHz
RapidIO 1x 3.125 GHz
RapidIO 1x 1.25 GHz/SGMII1/SGMII2
RapidIO 1x 2.5 GHz/SGMII1/SGMII2
RapidIO 1x 1.25 GHz/SGMII1
RapidIO 1x 2.5 GHz/SGMII1
RapidIO 1x 1.25 GHz
RapidIO 1x 2.5 GHz
Reserved
Reserved.
0
SerDes reference clock = 100 MHz.
1
SerDes reference clock = 125 MHz.
MSC8156 Reference Manual, Rev. 2
5-18
Freescale Semiconductor
Reset Programming Model
Table 5-9. RCWLR Bit Descriptions (Continued)
Name
Reset
Description
SCLK1
16
0
SerDes1 Reference Clock
Selects the SerDes1 reference clock. 100 MHz
clock can work for all protocols and frequencies
except for 3.125Gbaud RapidIO; 125 MHz
works for all protocols and frequencies with no
exceptions.
—
15–8
0
Reserved. Write to zero for future compatibility.
PLL1DIS
7
0
Disable PLL1
Setting this bit disables PLL1. When using
clock modes 1 or 37, set this bit to reduce
power consumption.
—
6
0
Reserved. Write to zero for future compatibility.
MODCK
5–0
0
Clock Mode
Defines the clock operating mode.
5.3.2
SerDes reference clock = 100 MHz.
1
SerDes reference clock = 125 MHz.
0
PLL1 enabled.
1
PLL1 disabled.
See Chapter 7, Clocks.
Reset Configuration Word High Register
31
30
—
RC
15
14
29
28
27
26
13
—
Type
Reset
25
24
23
22
21
Offset 0x04
18
17
16
RIO RPT RHE SBETH —
RM
R
Value depends on the reset configuration word high loaded during reset flow.
BP
—
1
0
EWDT PRDY
Type
Reset
Bit
0
Reset Configuration Word High Register (RCWHR)
RCWHR
Bit
Settings
20
19
BPRT
12
11
10
9
GE1
GE2
R1A
R2A
8
7
6
5
4
3
DEVID
2
—
RMU CTLS
R
Value depends on the reset configuration word high loaded during reset flow.
The RCWHR is a read-only register that derives its values from the reset configuration word high
loaded during the reset flow. Table 5-10 defines the RCWHR bit fields.
Table 5-10. RCWHR Bit Descriptions
Name
Description
—
31
Reserved. Write to one for future compatibility.
RC
30
Selects PCI Express RC Mode
When set, selects the PCI Express root complex
(RC) mode of operation. An RC device connects
the core processor/memory subsystem to I/O
devices while an EP device typically denotes a
peripheral or I/O device. See Chapter 17, PCI
Express Controller for details. This field is always 0
in the preconfigured modes (reduced RCW or
hard-coded).
Settings
0
PCI Express end point (EP) mode on the PCI
Express bus.
1
PCI Express root complex (RC) mode on the PCI
Express bus.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-19
Reset
Table 5-10. RCWHR Bit Descriptions (Continued)
Name
Description
EWDT
29
Enable Watchdog Timers
Selects the status of the software watchdog timers
when coming out of reset. The user can override
this value by writing to any of the System
Watchdog Control Registers (SWCRR[SWEN])
during system initialization.
0
Watchdog timers initially disabled.
1
Watchdog timers initially enabled.
PRDY
28
PCI Express Ready
Indicates whether the PCI Express controller is
ready to be configured.
0
PCI Express not ready.
1
PCI Express ready.
BPRT
27–24
Boot Port Select
Defines the boot port interface configuration.
If RapidIO port is selected as boot port, the
RapidIO interface, used for boot port, must be
configured to a valid RapidIO protocol using fields
S1P/S2P in RCWLR.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100–
1111
RIO
23
RapidIO Host Access Enable
Enables RapidIO host access to internal memory
after boot. When this bit is set, host access is
enabled for the following configurations:
• BPRT. Chosen host is SGMII.
• S1P/S2P. One port is configured as SGMII for
boot and the other SerDes does not contain
SGMII.
Note: For both modes, any lane not used for
SGMII closes after boot is disabled. To
use these lanes after boot, the user
should open the lanes as part of the boot
code execution.
0
Host access after boot disabled.
1
Host access after boot enabled.
RPT
22
RapidIO Pass-Through Enable
Selects the reset value of P0PTAACR[PTE] and
P1PTAACR[PTE] which determines whether
pass-through is disabled or enabled.
0
Pass-through disabled. (P0PTAACR[PTE] and
P1PTAACR[PTE] reset value is 0)
1
Pass-through enabled. (P0PTAACR[PTE] and
P1PTAACR[PTE] reset value is 1)
RHE
21
RapidIO Host Enable
Selects whether the RapidIO controller can act as a
host. When enabled as host, it uses the base
device ID (RapidIO register BDIDCSR) taken from
the three least significant bits of the device ID
(RCWHR[DEVID]).
0
RapidIO controller is agent.
1
RapidIO controller is host.
SBETH
20
Simple Boot Over Ethernet
Indicates whether the device uses a simple boot
over Ethernet. See Section 6.2.3, Simple Ethernet
Boot, on page 6-19 for details. This field is always 0
in the preconfigured modes (reduced RCW or
hard-coded).
0
Not simple boot over Ethernet.
1
Simple boot over Ethernet.
—
19
Settings
I2C.
RapidIO interface without I2C
RapidIO interface with I2C
SPI
RGMII1 without I2C
SGMII1 without I2C
RGMII1 with I2C
SGMII1 with I2C
RGMII2 without I2C
SGMII2 without I2C
RGMII2 with I2C
SGMII2 with I2C
Reserved.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
5-20
Freescale Semiconductor
Reset Programming Model
Table 5-10. RCWHR Bit Descriptions (Continued)
Name
Description
Settings
RM
18
Reset Master
This bit should be set when the device is a reset
master or when booting from a dedicated I2C
EEPROM device.
0
Reset slave.
1
Reset master.
BP
17
Boot Patch
This bit enables loading patch code for booting
from I2C.
0
Boot patch disabled.
1
Boot patch enabled.
—
16–13
Reserved. Write to zero for future compatibility.
GE1
12
GE1 Select
Selects the pins multiplexing between GE1 and
TDM[2–3].
0
TDM[2–3] signals are driven on pins.
1
RGMII1 signals are driven on pins.
GE2
11
GE2 Select
Selects the pins multiplexing between GE2 and
TDM[0–1].
0
TDM[0–1] signals are driven on pins.
1
RGMII2 signals are driven on pins.
R1A
10
RapidIO Interface 1 Accept All
Selects the reset value of P0PTAACR[AA]. When
set, RapidIO Interface 1 accepts all device IDs.
0
Do not accept all device IDs. (P0PTAACR[AA] reset
value is 0).
1
Accept all device IDs. (P0PTAACR[AA] reset value
is 1).
RapidIO Interface 2 Accept All
Selects the reset value of P1PTAACR[AA]. When
set, RapidIO Interface 2 accepts all device IDs.
0
Do not accept all device IDs. (P1PTAACR[AA] reset
value is 0).
1
Accept all device IDs. (P1PTAACR[AA] reset value
is 1).
DEVID
8–3
Device ID
Stores the value of the signals sampled during
reset.
000000 Master device/Device 0.
000001–
111111 Slave device number (from 1 to 63).
—
2
Reserved. Write to zero for future compatibility.
R2A
9
RMU
1
CTLS
0
Note:
RapidIO RMU Local Memory Access Internal
Port Select
Selects the internal port, the RMU uses, to access
local memory.
0
Access local memory using internal port 0 [OCN to
MBus Bridge 0 (O2M0)].
1
Access local memory using internal port 1[OCN to
MBus Bridge 1 (O2M1)].
RapidIO Common Transport Large System
This value is written to the RapidIO register
PEFCAR[CTLS]
0
Common transport type is small system
1
Common transport type is large system
The value of fields in the reset configuration word registers (RCWLR and RCWHR)
reflect only their state during the reset flow. Some of these parameters and modes can
be modified by changing their values in other unit memory mapped registers.
Modifying values in other unit memory mapped registers does not affect RCWLR and
RCWHR.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-21
Reset
5.3.3
Reset Status Register (RSR)
RSR
Bit
Reset Status Register
31
30
29
28
27
RCWSRC
25
24
RCW_SRC[0–2]
1
0
0
0
15
12
11
10
9
8
JPO
JH
JS
—
Type
Reset
14
—
23
SW0
R/W
0
0
Type
Reset
Bit
26
13
BSF SWSR SWHR RM
7
Offset 0x10
22
21
20
19
18
17
16
SW1
SW2
SW3
SW4
SW5
SW6
SW7
0
0
0
0
0
0
0
6
5
4
3
2
1
0
SRS
HRS
0
0
—
RIO2 RIO1
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The reset status register captures various reset events in the device. This register fields are sticky
and can be cleared by writing 1, writing 0 has no effect (except RM field which is read-only).
Table 5-11 defines the RSR bit fields.
Table 5-11. RSR Bit Descriptions
Name
Reset
Description
RCWSRC
31–29
0
Reset Configuration Word Source
Stores the value of the RCW_SRC[0–2] signals
sampled during reset. See Section 5.2.2,
Reset Configuration Words Source. Changing
this field has no effect.
—
28–24
10000
SW0
23
0
SW1
22
0
SW2
21
Settings
000
001
010
011
100
101
Multiplexed external RCW loading.
I2C EEPROM in 8-bit addressing mode.
I2C EEPROM in 16-bit addressing mode.
Input pins and default settings.
Hard coded option 1.
Hard coded option 2.
Reserved. Write to 0b10000 for future compatibility.
Software Watchdog Timer 0
Indicates whether watchdog timer 0 expired.
0
Software watchdog timer 0 not expired.
1
Software watchdog timer 0 expired.
Software Watchdog Timer 1
Indicates whether watchdog timer 1 expired.
0
Software watchdog timer 1 not expired.
1
Software watchdog timer 1 expired.
0
Software Watchdog Timer 2
Indicates whether watchdog timer 2 expired.
0
Software watchdog timer 2 not expired.
1
Software watchdog timer 2 expired.
SW3
20
0
Software Watchdog Timer 3
Indicates whether watchdog timer 3 expired.
0
Software watchdog timer 3 not expired.
1
Software watchdog timer 3 expired.
SW4
19
0
Software Watchdog Timer 4
Indicates whether watchdog timer 4 expired.
0
Software watchdog timer 4 not expired.
1
Software watchdog timer 4 expired.
SW5
18
0
Software Watchdog Timer 5
Indicates whether watchdog timer 5 expired.
0
Software watchdog timer 5 not expired.
1
Software watchdog timer 5 expired.
SW6
17
0
Software Watchdog Timer 6
Indicates whether watchdog timer 6 expired.
0
Software watchdog timer 6 not expired.
1
Software watchdog timer 6 expired.
SW7
16
0
Software Watchdog Timer 7
Indicates whether watchdog timer 7 expired.
0
Software watchdog timer 7 not expired.
1
Software watchdog timer 7 expired.
—
15
0
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
5-22
Freescale Semiconductor
Reset Programming Model
Table 5-11. RSR Bit Descriptions (Continued)
Name
Reset
BSF
14
0
SWSR
13
0
SWHR
12
0
RM
11
0
JPO
10
0
JH
9
0
JS
8
0
—
7–4
0
Reserved. Write to zero for future compatibility.
RIO2
3
0
RIO1
2
0
SRS
1
0
HRS
0
0
Note:
Description
Settings
Boot Sequencer Fail
If set, indicates the I2C boot sequencer has
failed while loading the reset configuration
words.
0
No boot sequencer failure.
1
Boot sequencer failure.
Software Soft Reset
Indicates whether a software soft reset has
occurred.
0
No software soft reset.
1
Software soft reset initiated.
Software Hard Reset
Indicates whether a software hard reset has
occurred.
0
No software hard reset.
1
Software hard reset initiated.
Reset Master
Indicates whether the device is the reset
master.
0
Reset slave.
1
Reset master.
JTAG Power-On Reset
Indicates whether a power-on reset request
was received via a JTAG command. When this
bit is set, out of reset, it also sets RSR[HRS]
and RSR[SRS].
0
No JTAG power-on reset request.
1
JTAG power-on reset request received.
JTAG Hard Reset
Indicates whether JTAG hard reset request
was received via a JTAG command.
0
No JTAG hard reset.
1
JTAG hard reset initiated.
JTAG Soft Reset
Indicates whether JTAG soft reset request was
received via a JTAG command.
0
No JTAG reset.
1
JTAG soft reset initiated.
RapidIO Interface 2 Reset Status
Indicates whether the RapidIO interface 2
received a reset request.
0
No reset request received.
1
Reset request received.
RapidIO Interface 1 Reset Status
Indicates whether the RapidIO interface 1
received a reset request.
0
No reset request received.
1
Reset request received.
Soft Reset Status
When an external or internal soft reset event is
detected, SRS is set.
0
No soft reset event.
1
A soft reset event was detected.
Hard Reset Status
When an external or internal hard reset event is
detected, HRS is set.
0
No hard reset event.
1
A hard reset event was detected.
The RSR accumulates reset events. For example, because a software watchdog timer
expiration results in a hard reset that in turn results in a soft reset, RSR[SWSR],
RSR[SRS], and RSR[HRS] are all set after a software watchdog reset. These must be
cleared individually. RSR only returns to its complete reset value when a power-on
reset occurs.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-23
Reset
5.3.4
Reset Protection Register (RPR)
RPR
Bit
Reset Protection Register
31
30
29
28
27
26
Offset 0x18
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
0
RCPW
R/W
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
RCPW
R/W
0
0
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
The RPR enables or disables writing to the reset control register (RCR). The RPR protects
unintended software reset requests due to writes to the reset control register (RCR). To enable the
RPR, write the value 0x52535445 (“RSTE” in ASCII) to the RPR. When enabled, the control
register enable bit in the reset control enable register (RCER[CRE]) is set. Reading the RPR
always returns all zeros. To disable writes to the RCR, write a 1 to the RCER[CRE] bit. Table
5-12 defines the bit fields of RPR.
Table 5-12. RPR Bit Descriptions
Name
Reset
Description
RCPW
31–0
0
Reset Control Protection Word
Protects unintended software reset request caused by writes to the RCR. Write the value
0x52535445 (“RSTE” in ASCII) to the RCPW to enable the RCR. When the RCR is enabled, the
RCER[CRE] bit is set. Reading the RPR always returns all zeros. To disable write to the RCR,
write a 1 to RCER[CRE].
MSC8156 Reference Manual, Rev. 2
5-24
Freescale Semiconductor
Reset Programming Model
5.3.5
Reset Control Register (RCR)
RCR
Bit
Reset Control Register
31
30
29
28
27
26
25
24
Offset 0x1C
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
SRH SWHR SWSR
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The RCR is used by software to initiate a soft or hard reset sequence. To allow writing to this
register, the user must first enable it by writing the value 0x52535445 to the reset protection
register (RPR). Table 5-13 defines the RCR bit fields.
Table 5-13. RCR Bit Descriptions
Name
Reset
Description
—
31–3
0
Reserved. Write to zero for future compatibility.
SHR
2
0
Soft Hard Reset
Setting this bit cause the MSC8156 to convert
all hard reset flows to soft reset flows. This
feature can be used for debug. This bit returns
to its reset state during the reset sequence, so
reading it always returns a 0.
0
Normal hard reset flow.
1
Hard reset flow converted to soft reset flow.
SWHR
1
0
Software Hard Reset
Setting this bit cause the MSC8156 to begin a
hard reset flow. This bit returns to its reset state
during the reset sequence, so reading it always
returns a 0.
0
Normal operation.
1
Initiates a hard reset.
SWSR
0
0
Software Soft Reset
Setting this bit cause the MSC8156 to begin a
soft reset flow. This bit returns to its reset state
during the reset sequence, so reading it always
returns a 0.
0
Normal operation.
1
Initiates a soft reset.
Note:
Settings
When issuing a reset command by accessing the register, the device enters reset mode
immediately. The host transaction does not terminate normally. Always consider the
possible outcome when any host is programmed to issue the software reset command.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
5-25
Reset
5.3.6
Reset Control Enable Register (RCER)
RCER
Bit
Reset Control Enable Register
31
30
29
28
27
26
25
24
Offset 0x20
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
CRE
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The reset control enable register shown in indicates by the CRE field that the reset protection
register (RPR) was accessed with a value that enables the reset control register (RCR). Table
5-14 defines the RCER bit fields.
Table 5-14. RCER Bit Descriptions
Name
Reset
Description
—
31–1
CRE
0
0
Reserved. Write to zero for future compatibility.
0
Control Register Enabled
Indicates the status of the reset control register
(RCR). Writing 1 to this bit disables the RCR
and clears this bit. Writing zero has no effect.
Settings
0
RCR is disabled.
1
The enable value is written to the reset
protection register (RPR) to enable the RCR.
MSC8156 Reference Manual, Rev. 2
5-26
Freescale Semiconductor
6
Boot Program
The boot program initializes the MSC8156 after it completes a reset sequence. The MSC8156
can boot from an external host through the RapidIO interface or download a user boot program
through the I2C, SPI, or Ethernet ports. The default boot code is located in an internal 96 KB
ROM at 0xFEF00000–0xFEF17FFF and is accessible to all cores. For readability, the internal
boot code is written in C and is based on the Freescale SmartDSP OS.
When cores finish the reset sequence, they all jump to the ROM starting address (0xFEF00000),
and run the boot code. Specific tasks may differ based on the core ID.
Note:
Boot data is located in the M3 memory at 0xC0101C00–0xC0107FFF (25 KB). Do not
write to this area during boot loading.
When the cores finish the boot sequence, they all jump to a user-defined address.
Special conditions for boot code operation include the following:
„ The boot code services the watchdog timer if the EWDT bit in the reset configuration
word high register (RCWHR) is set (recommended).
„ If the boot process fails, the core goes into a debug state and writes an indication of the
root error cause to address 0xC0101C04 in M3 memory (see Section 6.5, Boot Errors, on
page 6-23 for details).
„ The boot program does not configure the DDR controller. Therefore, if you want to place
data in the DDR memory, you must first configure the DDR controller to support the type
of DDR memory in the system. To configure the controller, write the configuration data to
the DDR controller memory-mapped registers before writing data to the DDR memory.
See Chapter 12, DDR SDRAM Memory Controller for details.
„ In any reset state other than PORESET, the device does not execute the multi-device
support for using the reset configuration word (RCW) flow with I2C as described in
Section 6.1.4. The rest of the boot flow remains the same as described in this chapter.
„ The boot code is run by all cores. Task differ by core ID.
Note:
Parity error checking is not supported by the boot code because parity errors are
unlikely to occur.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
6-1
Boot Program
6.1 Functional Description
The boot code is divided into four parts shown in Figure 6-1:
„ Private configuration (all cores). Includes general configuration of all cores.
„ Shared configuration (core 0). Includes general configuration of internal CLASS, I2C,
RapidIO interface, and QUICC Engine subsystem.
„ Patch mode. Allows loading patch code for boot from I2C.
„ Boot mode select (core 0). This part includes downloading of code from one of the
MSC8156 bootable ports as defined by the RCWHR[BPRT] field.
„ Boot completion. All cores complete the boot operation and jump to a user-specified
address.
Private
Configuration
No
Core 0?
Yes
Shared
Configuration
No
Boot patch
patch through
through I22C
Boot
HSMPR[0] = 0?
Yes
Boot Mode
Select?
I2C
Code
HSMPR[0] = 0
Ethernet
Code
Serial
RapidIO
Code
Simple
Ethernet
Code
SPI
Code
Core 0 Releases Cores 1–N
by Hardware Semaphore
All Cores Jump To
User Code
Figure 6-1. Boot Sequence Diagram
MSC8156 Reference Manual, Rev. 2
6-2
Freescale Semiconductor
Functional Description
6.1.1 Private Configuration
Private configuration includes the following:
„ VBA register initialization. The value stored in ROM (0xFEF17000) is used to initialize
the Vector Base Address (VBA) register in the SC3850 core. After initialization of the
VBA register, any interrupt places the core in debug mode.
„ The EPIC is programmed to handle all NMIs correctly.
„ The L1 ICache is enabled.
„ The stack pointer is set to reside in the M3 memory space dedicated to the boot operation.
„ The Error Detection Code (EDC) exception is enabled.
Note:
The EPIC, L1 ICache, and MMU are part of the SC3850 DSP core subsystem. See the
the MSC8156 SC3850 DSP Core Subsystem Reference Manual for configuration
details. The manual is only available with a signed non-disclosure agreement (NDA).
Contact your Freescale sales office or representative for more information.
6.1.2 Shared Configuration
The shared configuration includes the following:
„ If the I2C controller is used to load the RCW for multi-device slaves (see
Section 6.1.4, Multi Device Support for the I2C Bus, on page 6-4) the necessary number
of GPIO lines from the {GPIO[0–3], GPIO[21]} of the master device are set to output and
used to drive STOP_BS signals as follows:
— For up to 5 slaves, the lines drive the signals directly, and the number of lines equals
the number of slaves.
— For up to 15 slaves, using glue logic to drive the STOP_BS signals; the number of
required lines is equal to 1 + log 2numSlaves .
„ If RCWHR[RIO] is set or boot is over the RapidIO interface:
— LCSBA1CSR is set to 0x1FFE0000, thereby allowing the configuration register space
to be physically mapped. This allows configuration and maintenance of the registers
through regular read and write operations rather than by maintenance operations.
— The necessary bits of HSSI_CR1[0:1] are set in order to disable the tri-state on the
Serial RapidIO lanes.
— The necessary bits of P0CCSR and P1CCSR (RapidIO) are set to force 1x or 4x based
on RCWLR[S1P] and RCWLR[S2P].
„ QUICC Engine module priority is set to be 1 with emergency not masked (that is
SDMR[EB1_PR] = 01).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
6-3
Boot Program
6.1.3 Patch Mode
Patch mode is defined as follows:
„ Patch Mode is enabled when RCWHR[BP] is set. See Chapter 5, Reset for details.
„ Boot loads patch code from I2C and executes in the same manner as boot over I2C.
„ After the patch is executed, the patch code jumps to the address in the boot code defined in
address 0xC0101C14. The jump address can be changed by the patch code. By default, the
boot code continues Boot Flow from same place after returning from the patch loading.
„ Execution continues to load boot code from the boot port defined by RCWHR[BPRT]. If
boot port is I2C, the boot code generates an error and the core goes into a debug state.
6.1.4 Multi Device Support for the I2C Bus
The MSC8156 can share the I2C EEPROM device with other MSC8156 devices for loading the
reset configuration word (RCW), as well as for reading configuration during boot loading and
execution. When the bus is shared, the bus must distinguish among reset masters, reset slaves,
and EEPROM slaves:
The reset master (indicated by RCWHR[RM]) holds the STOP_BS signals of all the slaves high
and releases them one by one, thus arbitrating which slave has access to the bus at any moment.
When the master deasserts STOP_BS for a slave, the slave device attempts to access an EEPROM
at address 0x57. The actual EEPROM address is 0x50, but the master emulates the EEPROM
using address 0x57 to drive the RCW to each slave in turn.
There are a number of assumptions and limitations imposed when multiple devices share the I2C
bus:
1.
For each EEPROM in the system, there must be at least one EEPROM master. The
EEPROM master is also the reset master (RCWHR[RM])
2.
For each EEPROM, there can be 0 or more EEPROM slaves. An EEPROM slave is
defined as a device that reads is RCW from the EEPROM and uses data on the bus
during boot. The number of EEPROM slaves is stored as a single byte at address 0x8F
of the EEPROM.
3.
For each EEPROM, there can be 0 or more reset slaves. A reset slave is defined as a
device that only reads its RCW from the EEPROM but does not read data from it during
boot. The number of reset slaves is stored as a single byte at address 0x11 of the
EEPROM.
4.
Every EEPROM slave must also be a reset slave.
5.
There may be up to 15 reset slaves per EEPROM
MSC8156 Reference Manual, Rev. 2
6-4
Freescale Semiconductor
Functional Description
6.
As a consequence of the conditions listed in 1–5, the limitations on the number of slaves
is defined as 0 ≤ #EEPROM slaves ≤ #reset slaves ≤ 15
7.
The lowest numbered reset slave must be a higher numbered slave than the highest
numbered EEPROM slave (for example, if EEPROM slaves are slaves 0–4, then reset
slaves are slaves 5–12).
8.
EEPROM slaves must be numbered sequentially from 0 upward.
9.
All devices connected to the same EEPROM must have PORESET asserted
simultaneously, that is, no single device go through the PORESET sequence without the
others.
10.
For multi-device RCW only. The EEPROM master can have HRESET/SRESET asserted
without the slaves being reset as well. Each reset slave can have its HRESET/SRESET
asserted without the master being reset.
11.
For multi-device RCW and Boot using I2C. If the EEPROM master has its
HRESET/SRESET asserted, the EEPROM slaves must have their HRESET/SRESET asserted
as well. Each reset slaves can have its HRESET/SRESET asserted without the master being
reset. However, there must be external logic that performs the actions that the master
performs during its boot sequence. The logic may be implemented as periodic polling by
the master, asserting NMI to the reset master, or using an FPGA or other
implementation.
12.
If there is a shared EEPROM in use in any stage of the reset/boot flow (RCW, serial
RapidIO interface configuration, MAC address, I2C boot), all devices MUST load their
RCW from the shared EEPROM.
Note:
If the reset master (RCWHR[RM]) fails (due to a stuck I2C_SDA) to read the data at
0x11 or 0x8F of the EEPROM or fails during the sequence of driving the RCW to the
reset slaves, the core goes into a debug state and writes the appropriate error code to
the M3 memory (see Section 6.5).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
6-5
Boot Program
6.1.5 Example Configuration
Figure 6-2 describes a I2C multi device system in which MSC8156 #0 is a reset master and
MSC8156 #1 is a reset slave. The reset master uses {GPIO[0–3], GPIO[21]} to release the reset
slaves. The MSC8156 boot supports up to 15 slaves on a single EEPROM (for RCW). There are
two possibilities as to how the reset slave STOP_BS signals are handled:
„ If there are 5 slaves or less, connect each GPIO line directly to one of the slaves. The
master deasserts and asserts the lines when necessary.
„ If there are more than 5 slaves, GPIO[21] is used to latch the values of GPIO[0–3] into the
decoder glue logic (latch when high). This value indicates which of the slave STOP_BS
signals to pull low. When an all 1 values are latched, all STOP_BS signals should be
pulled high.
DSP Device 0
VDD
RCW_SRC
Reset Logic
I2C EPROM
3
I2C_SCL
A[0–2]
I2C_SDA
I2C_SCL
SRESET
HRESET
PORESET
I2C_SDA
GPIO
Decoder
STOP_BS
VDD
DSP Device 1
RCW_SRC
3
I2C_SCL
SRESET
I2C_SDA
HRESET
PORESET
VDD
STOP_BS
Figure 6-2. I2C Multi Device System
MSC8156 Reference Manual, Rev. 2
6-6
Freescale Semiconductor
Functional Description
Figure 6-3 shows the I2C initialization and multi device support.
RCWLR[MODCK]
PCMR0[INP_RNG]
need to reach
400 KHz
Write freq. division ratio
& sampling rate
No
Yes
RCWHR[RM]
1. Read slave RCW and generate STOP
2. Configure I2C controller to emulate
EEPROM with address 0x57
No
numSlaves > 5
Decoded STOP_SLV_BS == 0
Yes
Encoded STOP_SLV_BS == 0
1. Reload time out counter
2. Drive corresponding slave RCWs
3. Disable time out counter
RCWHR[BPRC] = I2C
Last Slave?
Yes
No
No
No
STOP_BS == 1
RCWHR[BPRC] = I2C
Yes
No
Yes
All STOP_BS == 1
End of flow
Figure 6-3. I2C initialization and Multi Device Support
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
6-7
Boot Program
The following stages are performed to serve as the master chip on a multi-device board.
1.
The MSC8156 reads RSR to determine if the reset is PORESET. If it is not PORESET,
this section of the boot is bypassed entirely.
2.
The MSC8156 reads RCWHR[RM] to determine if it is the master on the multi-device
board or a slave on the multi-device board.
3.
If the MSC8156 is the master on the multi-device board:
a.
I2CFDR and I2CDFSSR are programed based on the following data
— RCWLR[MODCK]
— RSR[RSTSRC]
b.
c.
d.
e.
f.
g.
4.
Note:
The frequency used for I2C_SCL is set as closely as possible to 400 kHz.
The Reset master reads the slaves RCW from their location in the I2C EEPROM (with
address 0x50) and stores them into M3.
The reset masters I2C controller is configured to work as an EEPROM (slave mode)
with address 0x57.
The reset master deassert STOP_BS for the current slave (directly or via the decoder).
The reset master:
• Drives preamble 0xAA55AA
• Drives header 0xFFFFFF
• Drives RCWLR
• Drives header 0xFFFFFF
• Drives RCWHR
for each read request of the reset slave, and then generates a STOP condition on the
bus in order to free it up because the slave I2C controller does not generate a STOP
condition.
Repeat steps a–e for all slaves.
{GPIO[0–3}, GPIO[21]} are set to 0x1F thus deasserting all the slaves STOP_BS
signals, and the master can continue performing its boot flow.
After getting its RCS, the reset slave starts to run the boot program.
If the MSC8156 is a an EEPROM slave, the boot waits until STOP_BS is to pulled
high before continuing with the boot program, thus allowing all reset slaves to read
their reset word before any device tries to access the EEPROM for boot code.
MSC8156 Reference Manual, Rev. 2
6-8
Freescale Semiconductor
Boot Modes
6.2 Boot Modes
The Boot Mode is selected by the value in the RCWHR[BPRT] field. The following sections
describe the operation of each boot mode.
6.2.1 I2C EEPROM
The MSC8156 boot expects the I2C EEPROM to be divided in to four sections:
1.
Reset words. This section starts at address 0x0000 of the EEPROM and includes the
reset words for the reset master, an indication as to the number of reset slaves and the
reset words for all the slaves.
2.
Reserved.
3.
Boot configuration. This section starts at address 0x0090 of the EEPROM and can
contain one of the following:
— MAC addresses for up to 64 devices (6 bytes per address). The boot knows to associate
each address with the appropriate device based on an offset of 6 × RCWHR[DEVID].
The expected format is consecutive 6 byte fields.
— Serial RapidIO configuration. This option allows the user to configure up to 471
registers and should be used to set the appropriate values of HSSI_CR1 and
HSSI_CR2 in the general configuration block. The expected format is address, data
pairs. The 8 bytes following the last pair should always be set to {0xFFFFFFFF,
0xFFFFFFFF}, regardless of the actual number of pairs placed in the EEPROM to
signal that no more configurations are necessary.
4.
Boot code. This section starts at address 0x0210 of the EEPROM and contains the user
code. The boot code must be of the size (n × 4) + m[bytes], where n is any integer
greater than or equal to 0 and m is either 0 or 1. If n is larger than 0, the value in the
Destination Address field must be 32-bit aligned.
Note:
Although not all sections are used by all boot options, the section addresses are fixed.
However, any section not used by a specific boot option can be used for general
purposes within the following guideline examples:
•
•
In a system with only two DSP devices that supports multi-device boot, only
addresses 0x0 to 0x19 within the reset word section must carry the appropriate
valid values, as shown in Figure 6-4. Addresses 0x20 to 0x89 are available for any
general-purpose use.
For boot scenarios without I2C support, addresses 0x90 to 0x20F are available for
any general-purpose use.
1.47 pairs along with 8 bytes end flag of {0xFFFFFFFF, 0xFFFFFFFF} is the amount that fits in the same space as 64
MAC addresses ( ( 64 ⋅ 6 ) ⁄ ( 2 ⋅ 4 ) = 47 + 1 )
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
6-9
Boot Program
•
•
For boot scenarios that do not use I2C and do not use boot patch, addresses 0x210
and above are available for general-purpose use.
Addresses 0x11 (number of reset slaves) and 0x8F (number of EEPROM slaves)
must be used for their defined function for all boot options. These addresses are
never available for general-purpose use.
Figure 6-4 shows a complete example of an EEPROM contents:
Address
0
1
2
3
4
5
6
7
Description
0x0000
1
0
1
0
1
0
1
0
Preamble
0x0001
0
1
0
1
0
1
0
1
0x0002
1
0
1
0
1
0
1
0
0x0003
1
1
1
1
1
1
1
1
0x0004
1
1
1
1
1
1
1
1
0x0005
1
1
1
1
1
1
1
1
0x0006
Reset Configuration Word Low [31–24]
0x0007
Reset Configuration Word Low [23–16]
0x0008
Reset Configuration Word Low [15–8]
0x0009
Reset Configuration Word Low [7–0]
0x000A
1
1
1
1
1
1
1
1
0x000B
1
1
1
1
1
1
1
1
0x000C
1
1
1
1
1
1
1
1
Master Reset Configuration Word
Low
Preload Command
Master Reset Configuration Word
High
Preload Command
0x000D
Reset Configuration Word High [31–24]
0x000E
Reset Configuration Word High [23–16]
0x000F
Reset Configuration Word High [15–8]
0x0010
Reset Configuration Word High [7–0]
0x0011
numResetSlaves ∈ [ 0 – 15 ]
Number of Reset Slaves
0x0012
Reset Configuration Word Low [31–24]
0x0013
Reset Configuration Word Low [23–16]
Reset Configuration Word Low
of Slave 1
0x0014
Reset Configuration Word Low [15–8]
0x0015
Reset Configuration Word Low [7–0]
0x0016
Reset Configuration Word High [31–24]
0x0017
Reset Configuration Word High [23–16]
0x0018
Reset Configuration Word High [15–8]
0x0019
Reset Configuration Word High [7–0]
Reset Configuration Word High
of Slave 1
..................
..................
0x0082
Reset Configuration Word Low [31–24]
0x0083
Reset Configuration Word Low [23–16]
0x0084
Reset Configuration Word Low [15–8]
0x0085
Reset Configuration Word Low [7–0]
Reset Configuration Word Low
of Slave 15
Figure 6-4. EEPROM Contents
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Boot Modes
Address
0
1
2
3
4
5
0x0086
Reset Configuration Word High [31–24]
0x0086
Reset Configuration Word High [23–16]
0x0088
Reset Configuration Word High [15–8]
0x0089
Reset Configuration Word High [7–0]
0x008A
..................
6
7
Description
Reset Configuration Word High
of Slave 15
Reserved
0x008B
..................
0x008C
..................
0x008D
..................
0x008E
..................
0x008F
15 ≤ numResetSlaves ≤ numEEPROMslaves ≤ 0
Number of EEPROM Slaves
0x0090
Configuration/MAC Address First
Byte
..................
0x020F
0x0210
Configuration Last Byte/ Device
0x2F Last MAC Address Byte
1
0
1
1
1
1
1
1
Block Control (Block #0)
size[0–7]
0x0211
0x0212
size[8–15]
0x0213
size[16–23]
0x0214
NBA[31–24]
0x0215
NBA[23–16]
0x0216
NBA[15–8]
0x0217
NBA[7–0]
0x0218
DA[31–24]
0x0219
DA[23–16]
0x021A
DA[15–8]
0x021B
DA[7–0]
Block Size
Next Block Address
Destination Address
Payload Data
CODE
Checksum[15–8]
Checksum and Checksum
Checksum[7–0]
Checksum[15–8]
Checksum[7–0]
1
0
1
1
1
1
1
1
Block Control (Block #1)
..................
End of EEPROM
Note:
The value shown for Block Control is an example only.
Figure 6-4. EEPROM Contents (Continued)
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6-11
Boot Program
The I2C boot loading is performed with the I2C controller. To allow for EEPROMs of up to 64
Kbytes, 19-bit addressing is used. The 7 most significant bits (msb) of the I2C slave address are
always 0b1010000. The I2C controller expects a specific memory image when trying to read data
from the EEPROM. The I2C memory image consists of the following:
1.
Block Control. A 1-byte control field that contains:
— 1 bit of CSE. A 1 indicates that the checksum is enabled.
— 1 reserved bit that should be cleared (0).
— 6 bits of CHIP_ID indicate the destination chip. 0x3F means broadcast.
2.
Block Size. These 3 bytes represent the number of bytes in the payload data field (e.g if
the payload size is 12 bytes, Block Size = {0x00, 0x00, 0x0C}).
3.
Next Block Address. The address in which the next block is located. If the next block
address equals 0x0 the bootloader assumes that the next block is sequential. If next
block address equals 0xFFFFFFFF, this block is the end block.
4.
Destination Address. The address to which the payload data should be written.
5.
Payload Data. Holds 1≤size<216 bytes (up to 64 Kbytes) of data to be written to
on-device memory according to the destination address.
6.
Checksum. A 2-byte field that holds the XOR of all previous data (Block Control and
on). The boot code XORs each received 2 bytes with the previous checksum value and
verifies the validation by comparing it to this field.
7.
Checksum. A 2-byte field that holds bitwise-not of the Checksum.
The I2C bootloader expects the 4 bytes of Checksum and Checksum regardless of the CSE value.
If the Checksum is disabled, these 4 bytes are not checked. By using Checksum and Checksum,
the boot ensures that all values of the bits are real values and that there are no stuck signals. If
both Checksum and Checksum are erroneous in a block, core 0 enters the debug state.
The I2C_SCL frequency is set as closely to 400KHz as possible, as mentioned in Section 6.1.4.
For each block, the Software I2C read access begins with the boot code driving the device select
({A0,A1,A2} = 0b000) and 2 bytes of address, followed by a RESTART condition. The I2C
slave drives its data (beginning with the Block Control byte) until the end of the block. The last
byte of each block is not acknowledged by the MSC8156. After the ninth unacknowledged bit,
the boot code generates a STOP condition. Figure 6-5 describes the Software I2C read access.
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Boot Modes
ACK
ACK
BYTE ADDR
A3 A4 A5 A6 A7 A8 A9 A10
BYTE ADDR
A11 A12 A13 A14 A15 A16 A17 A18
R/W
ACK
DEVICE SELECT
1 0 1 0 A0 A1 A2
STOP
START
START
DEVICE SELECT
A0 A1 A2
1 0 1 0 =0 =0 =0
ACK
ACK
NO ACK
ACK
DATA OUT 1
D0 D1 D2 D3 D4 D5 D6 D7
R/W
STOP
DATA OUT N
D0 D1 D2 D3 D4 D5 D6 D7
Note: A0 and D0 are the most significant bits.
Figure 6-5. I2C Read Access
6.2.2 Ethernet
„ The MSC8156 device can load files through the Ethernet port using DHCP (Dynamic
Host Configuration Protocol) and TFTP (Trivial File Transfer Protocol).Supports RGMII
@1000 Mbps and SGMII @1000 Mbps full duplex.
„ For DHCP, each client must have its own unique MAC (Media Access Control) address.
This MAC address can be based on RCWHR[DEVID] or be user-defined.
„ This DHCP implementation supports IPv4.
Booting over Ethernet is enabled on GE1 (UCC1) and GE2 (UCC3) depending on the values of the
following bit fields:
„ RCWHR[BPRT]. Determines which ports to use for boot loading.
— 0x4 = RGMII1 without I2C
— 0x5 = SGMII1 without I2C
— 0x6 = RGMII1 with I2C
— 0x7 = SGMII1 with I2C
— 0x8 = RGMII2 without I2C
— 0x9 = SGMII2 without I2C
— 0xA = RGMII2 with I2C
— 0xB = SGMII2 with I2C
„ RCWHR[GE1]. Determines whether the signals lines are TDM[2–3] or RGMII1.
„ RCWHR[GE2]. Determines whether the signal lines are TDM[0–1] or RGMII2
„ RCWLR[S1P]. Determines which SGMII signals are enabled on SerDes port 1:
— 0x5 = SGMII1 and SGMII2.
— 0x6 = SGMII1 and SGMII2
— 0x7 = SGMII1
— 0x8 = SGMII1
„ RCWLR[S2P]. Determines which SGMII signals are enabled on SerDes port 2.
— 0x5 = SGMII1 and SGMII2
— 0x6 = SGMII1 and SGMII2
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Freescale Semiconductor
6-13
Boot Program
—
—
—
—
—
—
Note:
0x7 = SGMII2
0xA = SGMII1 and SGMII2
0xB = SGMII2
0xE = SGMII1 and SGMII2
0x14 = SGMII2
0x16 = SGMII2
It is valid to program RCWLR[S1P] and RCWLR[S2P] to have SGMII1 on both ports,
SGMII2 on both ports, or to have SGMII1 and SGMII2 on both ports. An internal
multiplexer always routes only two physical connections to the QUICC Engine
controllers. If the SGMII interfaces are configured by S1P and S2P, SGMII1 (if
selected by S1P and S2P) is physically connected to SerDes Port 1 and SGMII2 (if
selected by S1P and S2P) is physically connected to SerDes Port 2
Figure 6-6 describes the Ethernet bootloader flow.
BOOT CODE
DHCP
Server
DHCP
Client
filename, next server address
TFTP
Server
TFTP
Client
TFTP Data Block
Read S-R
Code
Installation
ecord
application code
Temporary
Storage
Space
In M3
Internal
Memory
Space
Figure 6-6. Ethernet Bootloader Flow
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Boot Modes
:The Ethernet bootloader flow includes:
1.
Configuring the QUICC Engine drivers based on RCWHR[BPRT].
2.
Finding a DHCP server and receive configuration parameters (filename, server address,
and so on).
3.
Reading a block of the boot file, in S-Record format, from a TFTP server.
4.
Processing each TFTP data block and placing it in its memory destination.
5.
Sending a TFTP acknowledge to the TFTP server.
6.
Repeating steps 2–5 until the end of the data is transferred.
6.2.2.1 DHCP Client
The basic steps that occur when a DHCP client requests an IP address from a DHCP server are
shown in Figure 6-7.
DHCP Discover (broadcast)
DHCP Offer (unicast)
DHCP
CLIENT
DHCP Request (broadcast)
DHCP
SERVER
DHCP Ack (unicast)
Figure 6-7. DHCP Transactions
„ The client sends a DHCP DISCOVER broadcast message to locate a DHCP server.
„ A DHCP server offers configuration parameters (such as an IP address, a TFTP server IP
address, bootfile name...).
„ The client returns a formal request for the first offered IP address to the DHCP server in a
DHCPREQUEST broadcast message.
„ The DHCP server confirms that the IP address has been allocated to the client by returning
a DHCPACK unicast message to the client.
There are two possibilities for setting the MSC8156 MAC address during the boot:
„ User defined and read from an I2C EEPROM. See Section 6.2.1 for details.
„ Predefined default using the following fields:
— A constant of 32 bits: {0x1E, 0xF7, 0xD5, 0x00}
— 8 bits consisting of (RCWHR[DEVID]) (aligned to the right and padded with 0)
— A constant of 8 bits: {0x00}
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6-15
Boot Program
The predefined option is configured to be an individual locally administered address in
accordance with IEEE Std. 802-2001™. This MAC address scheme allows for more that 8
unique MAC addresses per device by changing the last 4 bit values, thus allowing each core to
have 2 MAC addresses for use during operational mode.
6.2.2.2 TFTP Client
This implementation supports three types of messages: TFTP REQUEST, TFTP DATA and
TFTP ACK. Figure 6-8 describes the TFTP handshake.
TFTP REQUEST
TFTP DATA
TFTP
CLIENT
TFTP ACK
TFTP
SERVER
TFTP DATA (last)
TFTP ACK
Figure 6-8. TFTP Transactions
„ The TFTP transfer is initiated by the client when it issues a TFTP REQUEST (which
contains the file name to download).
„ In response, the server provides the application with a series of TFTP DATA messages.
„ The client handshakes each data block by issuing a TFTP ACK allowing the server to
proceed with subsequent TFTP DATA messages.
„ This process repeats until all data blocks are received.
6.2.2.3 Boot File Format
The Ethernet bootloader expects an application file in the form of an S-Record file. The S-Record
file is a text representation of the binary program code. The S-Record file structure is describes in
Figure 6-9.
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Boot Modes
Start Record
Data Record 1
Data Record 2
Data Record n
End Record
Figure 6-9. S-Record File Structure
Each line of an S-Record file corresponds to any of the following: start record, data record, or end
record. Each record is terminated with a line feed.
Note:
The S-Record that is downloaded during boot over Ethernet should include no
whitespaces (including newlines).
A record has the following format:
S<type><length><address><data><checksum>
Note:
This implementation supports only record of types: S0, S3 or S7.
„ The description of fields is described in Table 6-1.
Table 6-1. S-Record description of Fields
Field
Width in
Characters
S<type>
2
The type of record (S0, S3 or S7)
<length>
2
The count of remaining character pairs in the record
<address>
4
The address at which the data field is to be loaded into memory
<data>
≤64
<checksum>
2
Description
The memory loadable data or descriptive information
The least significant byte of the ones complement of the sum of the byte values
represented by the pairs of characters making up the length, the address, and the
data fields
„ S0 Record. Starting record. The address and data fields are ignored and checksum check is
executed.
„ S3 Record. Data record. The address field is interpreted as a 4-byte address. The data field
is composed of memory loadable data.
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Boot Program
„ S7 Record. Termination record. The address fields is interpreted as the 4-byte address to
which to jump after boot. No checksum check is executed.
Shown below is a typical S-record format file:
S0030000FC
S30D00002FE731DC3180BEF09E7062
S705000000000C
The S0 record is composed as follows:
„ S0. Indicating it is a starting record.
„ 03. Hexadecimal 03 (decimal 3). Indicating that three character pairs (or ASCII bytes)
follow.
„ 0000. Information string (ignored)
„ FC. Checksum field.
The S3 record is composed as follows:
„ S3. Indicating it is a data record to be loaded at a 4-byte address.
„ 0D. Hexadecimal D (decimal 13), representing a 4 byte address, 8 bytes of binary data,
and a 1 byte checksum, follow.
„ 00002FE7. Eight character 4-byte address field.
„ 31DC3180BEF09E70. 8-character pairs representing the actual binary data.
„ 62. Checksum field.
The S7 record is composed as follows:
„ S7. Indicating it is the last record.
„ 05. Hexadecimal 05 (decimal 5). Indicating that five character pairs (4 byte address and a
1 byte checksum follow).
„ 00000000. Address field to jump to at the end of boot (is written to 0xC0101C10).
„ 0C. Checksum field.
Each S-Record line includes an address field that maps the lines data content to a memory
location in MSC8156. Core 0 moves the data to this address.
Note:
Because the MSC8156 uses 32-bit addressing, use of S3 and S7 is recommended.
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Boot Modes
6.2.3 Simple Ethernet Boot
The MSC8156 supports a simple Ethernet boot mode. This mode is selected by setting the
RCWHR[SBETH] bit during the PORESET sequence (see Section 5.3.2, Reset Configuration
Word High Register (RCWHR), on page 5-19 for details).
6.2.3.1 Simple Ethernet Boot Flow
The simple Ethernet boot mode uses the following sequence for processing:
„ The bootloader configures the QUICC Engine subsystem drivers based on the
RCWHR[BPRT].
„ There are two possibilities for setting the MAC address during the boot. See Section
6.2.2.1 for details.
„ When the Ethernet interface is configured, the bootloader sends the start handshake data
0x17171717.
„ The boot data is read a block at a time by the bootloader using a simple Ethernet frame
format:
<MAC Dest><MAC Source><Type><2 Bytes Data_Length><4 Bytes Address><Data>
„ Simple boot over Ethernet packets should have the ethertype field of the MAC header set
to 0x0004.
„ The bootloader processes each data block: <data_length><address><data> and places it in
the destination memory location.
„ The bootloader continues to process blocks until the end handshake data 0xA5A5A5A5 is
written to address 0xC0101C00.
„ All cores jump to the address written in 0xC0101C10. The value in the address should be
written during the boot loading process.
6.2.3.2 Simple Ethernet Boot Ports
Booting over Ethernet is enabled on GE1 (UCC1) and GE2 (UCC3) depending on the values of
RCWHR[BPRT], RCWHR[GE1], RCWHR[GE2], RCWLR[S1P] and RCWLR[S2P].
Note:
Use the following guidelines to configure bits to support the selected boot modes:
„ For boot over Ethernet in RGMII mode the following bits should be configured:
— RCWHR[GE1] = 1 for boot over port 1
— RCWHR[GE2] = 1 for boot over port 2
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Boot Program
6.2.3.3 Boot File Format
The Ethernet bootloader expects an application file in the format of a Simple Ethernet frame. The
Simple Ethernet frame has the following format:
<Length><Address><Data>
The description of fields is described in Table 6-2.
Table 6-2. Simple Ethernet Description of Fields
Field
Width in
Characters
<length>
2
The count of remaining character pairs in the record
<address>
4
The address at which the data field is to be loaded into memory
<data>
Description
The memory loadable data or descriptive information
Each Simple Ethernet address field maps the data content to a memory location in the DSP. Core
0 moves the data to this address. The following example shows a typical Simple-Ethernet packet
for End-of-handshake between the Ethernet master and the MSC8156 boot:
1E7FD5000000
1E7FD5100000
0004
0004
C0101C00
A5A5A5A5
The End-of-handshake packet sent by the Ethernet Master comprises the following:
„
„
„
„
„
1E7FD5000000, Destination MAC address (default MSC8156 address)
1E7FD5100000. Source MAC address.
0004. Ethernet type. The MSC8156 expects Ethernet type 0x0004.
0004. Length is 4 bytes.
C0101C00. The address at which the data field is to be loaded into memory. This is the
Handshake address for the MSC8156.
„ A5A5A5A5. Handshake data.
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Boot Modes
6.2.4 Serial RapidIO Interconnect
In this procedure a Serial RapidIO master waits for the MSC8156 boot program to finish its
default initialization and then initializes the device by typically loading code and data to the on
device memory.
6.2.4.1 Serial RapidIO Without I2C Support
The boot code configures HSSI_CR[0–1] and PxCCSR according to RCWLR[S1P] and
RCWLR[S2P] and writes 0x17171717 to address 0xC0101C00. The flow is:
1.
Disable port by writing to PxCCS register.
2.
Set x1 or x4 by writing to PxCCSR.
3.
Enable lanes by writing to the HSSI_CR1[0–1].
4.
Enable the port by writing to PxCCSR.
5.
Afterwards, it polls this address until the serial RapidIO master writes 0xA5A5A5A5 to
it, thereby indicating that it has finished its code loading.
Figure 6-10 describes the boot flow from Serial RapidIO interconnect.
boot mode select = Serial RapidIO interface
Disable tri-state on lanes
Set 0xC0101C00
to 0x17171717
read address 0xC0101C00
==0xA5A5A5A5
No
Yes
Continue Boot Flow
Figure 6-10. Serial RapidIO Interface Boot Flow
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Boot Program
6.2.4.2 Serial RapidIO Interface with I2C Support
The user can place {addr, data} pairs in the I2C EEPROM to configure various registers. The
address field should be as seen by the SC3850 DSP core. This feature is most commonly used to
configure registers in the general configuration block (see Section 6.2.1, I2C EEPROM, on page
6-9 for details). The boot supports up to 47 such pairs. The 8 bytes following the last pair should
always be set to {0xFFFFFFFF, 0xFFFFFFFF}, regardless of the actual number of pairs placed
in the I2C EEPROM.
Note:
Multiple devices connected to a shared EEPROM see the same address/data pairs.
6.2.5 SPI
The MSC8156 can boot from a Flash memory on the SPI. The boot expects a Flash memory that
latches on the rising edge of the clock and on which data is valid after the falling edge. The
chip-select should be a CS low signal. The boot code expects to see the same data format used for
the I2C EEPROM (see described in Section 6.2.1, I2C EEPROM, on page 6-9, item 4 for details
on the boot code requirements) starting at address 0 of the SPI.
A shared SPI bus is arbitrated by all the devices connected to it by polling CS. All signals should
be connected as open-drain if more than one device is connected to the SPI flash. The SPI bus
will run no faster than 400 KHz to support multiple devices connected with an open drain.
Note:
If the RCW is read from EEPROM, the device for which RCWHR[RM] equals 1
should have RCWHR[DEVID] of 0. Using this configuration setting saves on
arbitration cycles towards the SPI flash.
Note:
During boot over SPI, the pins described in Chapter 22, GPIO are used per their SPI
functionality. In addition, GPIO23 is used as a chip-select signal (CS) to control access
to the SPI Flash memory.
6.3 Jump to User Code
Before finishing its tasks the boot code preforms these actions:
„ If RCWHR[RIO] is cleared, the boot code disables host accesses by RapidIO interface to
internal memory space by putting the lanes into tri-state high impedance state.
„ Invalidate all range of ICaches and close MMU program windows.
„ Core internal registers (other than R0 and VBA) are set to 0x00000000.
„ All configurations which were done by the boot code are cleared.
— Module registers
— GPIO configurations
— Write 0x00000000 to GIER (see Chapter 8, General Configuration Registers) to clear
the register.
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System after Boot
— Disable all interrupts (NMI excluded)
— Clear all QUICC Engine registers by writing 1 to QECMDR[RST]
„ 0x900D900D is written to 0xC0101C0C in M3 indicating that the boot has finished
executing.
„ All cores jump to the address written in 0xC0101C10. The value in this address should be
written during the boot loading process.
6.4 System after Boot
„ All MATTs in the MMUs are set to their reset value values (except M_xSDBx[PBS]
which is set to 0x2).
„ L1 I-Cache is enabled, but there are no cacheable windows.
„ All NMIs will be configured as NMIs in the EPIC.
„ VBA equals 0xFEF17000. Any interrupt in the EPIC puts the core in debug.
„ EDC is enabled.
„ Core register values are not guaranteed and should be initialized before use.
6.5 Boot Errors
If the boot code fails, an indication as to the root cause is written to 0xC0101C04. The possible
reasons are listed in Table 6-3.
Table 6-3. Boot Error Codes
Error Code
Description
0x003FEFFF
Catastrophic Error. SmartDSP OS Function failed
0x003FEFFE
DHCP server time out
0x003FEFFD
Corrupted boot file. The possible causes are:
• Checksum wrong in TFTP file
• Checksum wrong in I2C file
• Unsupported S-Record type
0x003FEFFC
TFTP server time out
0x003FEFFA
TFTP server sent ERROR code (05)
0x003FEFF9
Unsupported boot port
0x003FEFF8
Reset slave does not respond
0x003FEFF5
Boot over Ethernet or RapidIO isn’t supported with current RCW configuration
0x003FEFF4
Too many I2C RCW slaves in address 0x11 of the EEPROM
0x003FEFF3
Error in protocol between I2C RCW master and slave
0x003FEFF2
Boot port trying to write to area designated for boot (0xC0101C18–0xC0107FFF)
0x003FEFF1
In patch mode, the boot port is I2C.
0x0027EFFE
Lost arbitration on I2C us.
0x0027EFFD
Time-out on I2C acknowledge (9th clock).
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Boot Program
Table 6-3. Boot Error Codes
Error Code
Description
0x0027EFFC
Stuck I2C_SDA (I2C bus).
0x00000000
Unexpected debug condition in the SC3850 Core (unexpected interrupt, EE0 asserted
and so on)
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7
Clocks
The clock circuits contains five PLLs:
„ Three PLLs driven from a single CLKIN signal generated by a crystal-based oscillator that
generate the clocks for the DSP core subsystems, the internal CLASS buses, the RapidIO
controller, the QUICC Engine subsystem, the MAPLE-B subsystem, the TDM interfaces,
internal memory, the DDR-SDRAM memory controllers, and the PCI Express interface.
„ Two PLLs that generate clocks for the SerDes interfaces in the HSSI.
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Freescale Semiconductor
7-1
Clocks
7.1 Clock Generation Components and Modes
The clock generation components and clock scheme are shown in Figure 7-1.
CLKIN
PLL0
PLL 0 clk
PLL 0 clk
PLL 1 clk
0
1
DIV
CLASS Subsystem
DSP Core Subsystem 0
DSP Core Subsystem 1
PLL 0 clk
PLL 1 clk
0
1
DIV
DSP Core Subsystem 2
DSP Core Subsystem 3
DSP Core Subsystem 4
DSP Core Subsystem 5
PLL1
PLL2
PLL 1 clk
PLL 0 clk
PLL 1 clk
0
1
DIV
PLL 0 clk
PLL 1 clk
0
1
DIV
QUICC Engine Subsystem
PLL 0 clk
PLL 2 clk
0
1
DIV
MAPLE-B Subsystem
PLL 0 clk
PLL 2 clk
0
1
DIV
DDR1 Controller
PLL 0 clk
PLL 2 clk
0
1
DIV
DDR2 Controller
HSSI Subsystem
PLL 2 clk
SerDes PLL = SerDes Clock
SerDes1_REF_CLK
SerDes1 PLL
SERDES1CLK
SerDes PLL = SerDes Clock
SerDes2_REF_CLK
SerDes2 PLL
SERDES2CLK
Note: The source for CLKOUT is selected at reset via the Reset Configuration Word (RCW). See Chapter 5, Reset for details.
Figure 7-1. MSC8156 Clock Scheme
Each PLL uses its input clock to generate a fast clock that is synchronized to the input clock. The
fast clock is distributed to each of the clock dividers to generate the clocks that are distributed to
the system blocks. The clock circuits are locked, according to the selected clock mode, when the
first stage of the system reset configuration is done (reset configuration is controlled by the
RESET block). The clock circuits are initialized after the first phase of the reset configuration,
when the low part of the reset configuration word is loaded, according to the selected clock
mode.
MSC8156 Reference Manual, Rev. 2
7-2
Freescale Semiconductor
Clock Generation Components and Modes
The MSC8156 clock modes are listed in Table 7-1.
Table 7-1. MSC8156 Clock Modes
QUICC
MAPLE-B
Engine
Subsystem
Mode
CLKIN
PLL0
PLL1
PLL2
CLASS
DSP Core
Subsystems
HSSI
0
100
900
1000
800
500
1000
333
500
1
66.67
800
0
667
400
800
267
4
100
900
1000
667
500
1000
19
100
900
1000
800
450
21
100
900
1000
667
36
100
900
1000
37
66.67
800
39
100
45
100
Notes: 1.
2.
DDR1
DDR2
450
800
800
400
400
667
667
333
450
450
667
667
1000
333
500
450
800
800
450
1000
333
450
450
667
667
800
500
1000
333
500
450
800
267
0
667
400
800
267
400
400
667
267
900
1000
667
500
1000
333
450
450
667
222
900
1000
667
450
1000
333
450
450
667
222
The color of each cell, states which PLL drives its clock domain. PLL 0 is red, PLL1 is yellow, and PLL2 is blue
with white lettering.
In clock modes 1 and 37, PLL1 is not used. In order to save power and reduce noise, this PLL should be disabled
by setting bit 7 of RCW low (for RCW details, see Chapter 5, Reset).
CLK_OUT pin can be driven from either PLL with selection determined by the value of
RCWLR[CLKO] (bits 31–30 of the low part of the reset configuration word—for details, see
Chapter 5, Reset). The possible CLK_OUT frequencies are listed in Table 7-2.
Table 7-2. MSC8156 CLK_OUT Frequencies
Mode
PLL0
PLL1
PLL2
CLK_OUT from PLL0
CLK_OUT from PLL1
CLK_OUT from PLL2
0
900
1000
800
75
100
80
1
800
0
667
66.67
6.7
66.67
4
900
1000
667
75
100
66.67
19
900
1000
800
75
100
80
21
900
1000
667
75
100
66.67
36
900
1000
800
75
100
80
37
800
0
667
66.67
6.7
66.67
39
900
1000
667
75
100
66.67
45
900
1000
667
75
100
66.67
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
7-3
Clocks
7.2
.Programming
Model
The registers covered in this section are as follows:
„ System Clock Control Register (SCCR), page 7-4.
„ Clock General Purpose Register 0 (CLK_GRP0), page 7-5.
Note:
The clock registers use a base address of: 0xFFF24000.
7.2.1 System Clock Control Register (SCCR)
SCCR
Bit
System Clock Control Register
31
30
29
28
27
26
25
24
Offset 0x000
23
22
21
20
19
18
17
16
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
CLASS CORE CORE HSSI
DIS 3-0DIS 5-4DIS DIS
Type
Reset
QEDIS MAPLE DDR1
DIS
DIS
DDR2
DIS
—
R/W
0
0
0
0
0
0
0
0
0
0
0
0
The SCCR can be used to shut down the clock for some of the clock domains. This register can
only be reset by a power-on reset. Table 7-3 defines the SCCR bit fields.
Table 7-3. SCCR Bit Descriptions
Name
Reset
Description
Settings
—
31–16
0
Reserved. Write to zero for future compatibility.
CLASSDIS
15
0
CLASS Clock Domain Disable
Used to disable the CLASS clock domain to
conserve power.
0
CLASS clock domain enabled.
1
CLASS clock domain disabled.
CORE3-0
DIS
14
0
Core 3–0 Clock Domain Disable
Used to disable the Core 3–0 clock domain to
conserve power.
0
Core 3–0 clock domain enabled.
1
Core 3–0 clock domain disabled.
CORE5-4
DIS
13
0
Core 5–4 Clock Domain Disable
Used to disable the Core 5–4 clock domain to
conserve power.
0
Core 5–4 clock domain enabled.
1
Core 5–4 clock domain disabled.
HSSIDIS
12
0
HSSI Clock Domain Disable
Used to disable the HSSI clock domain to
conserve power.
0
HSSI clock domain enabled.
1
HSSI clock domain disabled.
QEDIS
11
0
QUICC Engine Clock Domain Disable
Used to disable the QUICC Engine subsystem
clock domain to conserve power.
0
QUICC Engine clock domain enabled.
1
QUICC Engine clock domain disabled.
MAPLEDIS
10
0
MAPLE-B Clock Domain Disable
Used to disable the MAPLE-B clock domain to
conserve power.
0
MAPLE-B clock domain enabled.
1
MAPLE-B clock domain disabled.
MSC8156 Reference Manual, Rev. 2
7-4
Freescale Semiconductor
.Programming Model
Table 7-3. SCCR Bit Descriptions (Continued)
Name
Reset
DDR1DIS
9
0
DDR2DIS
8
0
—
7–0
0
Description
Settings
DDR1 Clock Domain Disable
Used to disable the DDR1 controller clock
domain to conserve power.
0
DDR1 clock domain enabled.
1
DDR1 clock domain disabled.
DDR2 Clock Domain Disable
Used to disable the DDR2 controller clock
domain to conserve power.
0
DDR2 clock domain enabled.
1
DDR2 clock domain disabled.
Reserved. Write to zero for future compatibility.
7.2.2 Clock General Purpose Register 0 (CLK_GPR0)
CLK_GPR0
Bit
31
Clock General Purpose Register 0
30
29
28
27
26
24
23
22
21
20
19
18
17
16
5
4
3
2
1
0
—
R
Determined by MODCK
Type
Reset
Bit
25
Offset 0x004
15
14
13
12
11
10
9
8
7
6
RPTE
R/W
—
Type
Reset
R
Determined by MODCK
The CLK_GPR0 is used to set the RapidIO prescale value to yield the 8 MHz clock required for
event timing. Table 7-4 defines the CLK_GPR0 bit fields.
Table 7-4. CLK_GPR0 Bit Descriptions
Name
Reset
Description
Settings
—
31–6
MODCK
value
Reserved.
RPTE
5–0
MODCK
value
RapidIO Prescaler for Timed Event Clock
100000 For MODCK 1
This value is used to scale the OCN clock (which is equal to the HSSI
and 37.
clock that is derived from the MODCK settings; see Table 7-1) to yield 101001 For MODCK 0,
an 8 MHz clock used by the RapidIO subsystem to calculate different
4, 21, 36, 39, 45
event times. The value to enter into this field is computed by the
All other values reserved.
formula: (ocn_clk_freq/8 MHz) – 1, rounded to the nearest whole value
(ocn_clk_freq = HSSI clock frequency). The default is selected by the
MODCK settings at power-up reset.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
7-5
Clocks
MSC8156 Reference Manual, Rev. 2
7-6
Freescale Semiconductor
General Configuration Registers
8
The MSC8156 device includes a general configuration block that includes fifty-six 32-bit
registers. This block provides sets of control and status registers for modules in the device that do
not include their own control and status registers.
8.1 Programming Model
The general configuration registers include the following:
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
General Control Register 1 (GCR1), see page 8-2
General Control Register 2 (GCR2), see page 8-3
General Status Register 1 (GSR1), see page 8-5
High Speed Serial Interface Status Register (HSSI_SR), see page 8-7
DDR General Configuration Register (DDR_GCR), see page 8-10
High Speed Serial Interface Control Register 1 (HSSI_CR1), see page 8-12
High Speed Serial Interface Control Register 2 (HSSI_CR2), see page 8-15
QUICC Engine Control Register (QECR), see page 8-16
GPIO Pull-Up Enable Register (GPUER), see page 8-17
GPIO Input Enable Register (GIER), see page 8-18
System Part and Revision ID Register (SPRIDR), see page 8-19
General Control Register 4 (GCR4), see page 8-20
General Control Register 5 (GCR5), see page 8-22
General Status Register 2 (GSR2), see page 8-24
Core Subsystem Slave Port Priority Control Register (TSPPCR), see page 8-26
QUICC Engine First External Request Multiplex Register (CPCE1R), see page 8-27
QUICC Engine Second External Request Multiplex Register (CPCE2R). see page 8-28
QUICC Engine Third External Request Multiplex Register (CPCE3R), see page 8-29
QUICC Engine Fourth External Request Multiplex Register (CPCE4R), see page 8-30
General Control Register 10 (GCR10), page 8-31
General Interrupt Register 1 (GIR1), see page 8-32
General Interrupt Enable Register 1 for Cores 0–5 (GIER1_[0–5]), see page 8-35
General Interrupt Register 3 (GIR3), see page 8-37
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-1
General Configuration Registers
„
„
„
„
„
„
„
„
„
„
„
Note:
General Interrupt Enable Register 3 for Cores 0–5 (GIER3_[0–5]), see page 8-39
General Interrupt Register 5 (GIR5), see page 8-40
General Interrupt Enable Register 5 for Cores 0–5 (GIER5_[0–5]), see page 8-42
General Control Register 11 (GCR11), see page 8-43
General Control Register 12 (GCR12), see page 8-44
DMA Request0 Control Register (GCR_DREQ0), see page 8-46
DMA Request1 Control Register (GCR_DREQ1), see page 8-50
DMA Done Control Register (GCR_DDONE), see page 8-54
DDR1 General Configuration Register (DDR1_GCR), see page 8-57
DDR2 General Configuration Register (DDR2_GCR), see page 8-58
Core Subsystem Slave Port General Configuration Register (CORE_SLV_GCR), see
page 8-59
The base address for the general configuration registers is: 0xFFF28000.
8.2 Detailed Register Descriptions
8.2.1
General Configuration Register 1 (GCR1)
GCR1
Bit
General Configuration Register 1
31
30
29
Type
Reset
0
R
0
0
Bit
23
22
21
28
Offset 0x00
27
26
25
24
0
0
R/W
0
0
0
20
19
18
17
16
—
—
Type
Reset
0
0
0
Bit
15
14
UART_STOP
R/W
0
0
0
13
12
11
10
0
0
1
0
3
2
1
0
0
0
—
Type
Reset
0
1
0
DDR2_PIPE_LMT
R/W
0
Bit
7
6
5
4
0
9
8
DDR1_PIPE_LMT
DDR1_PIPE_LMT
Type
Reset
0
TDM_PIPE_LMT
R/W
0
0
0
1
0
0
MSC8156 Reference Manual, Rev. 2
8-2
Freescale Semiconductor
Detailed Register Descriptions
GCR1 configures various general functions for the MSC8156 device. Table 8-1 lists the GCR1 bit
field descriptions.
Table 8-1. GCR1 Bit Descriptions
Name
Reset
Description
—
31–17
UART_STOP
16
0
Reserved. Write to 0 for future compatibility.
0
UART Stop
Stops the UART clock.
—
15
DDR2_PIPE_LMT
14–10
0
Reserved. Write to 0 for future compatibility.
10000
DDR2 Pipeline Limit
Specifies the DDR2 complex pipeline
depth.
DDR1 Pipeline Limit
Specifies the DDR1 complex pipeline
depth.
TDM Pipeline Limit
Specifies the TDM complex pipeline depth.
DDR1_PIPE_LMT
9–5
10000
TDM_PIPE_LMT
4–0
10000
8.2.2
0
1
Normal operation.
UART clock stopped.
General Configuration Register 2 (GCR2)
GCR2
Bit
Settings
General Configuration Register 2
31
30
29
28
Offset 0x04
27
26
25
24
0
—
R/W
Type
Reset
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
—
16
DMA_DBG
Type
Reset
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
Reset
0
0
Bit
7
6
—
Type
Reset
0
0
CORE5_STP_ CORE4_STP_ CORE3_STP_ CORE2_STP_ CORE1_STP_ CORE0_STP_
EN
EN
EN
EN
EN
EN
R/W
0
0
0
0
0
0
5
4
3
2
1
0
CORE5_DBG CORE4_DBG CORE3_DBG CORE2_DBG CORE1_DBG CORE0_DBG
_REQ
_REQ
_REQ
_REQ
_REQ
_REQ
R/W
0
0
0
0
0
0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-3
General Configuration Registers
GCR2 configures various general functions for the MSC8156 device. Table 8-2 lists the GCR2 bit
field descriptions.
Table 8-2. GCR2 Bit Descriptions
Name
Reset
Description
Settings
—
31–17
DMA_DBG
16
0
Reserved. Write to 0 for future compatibility.
0
No request.
DMA debug request.
—
15–14
CORE5_STP_EN
13
0
DMA Debug Mode Request
0
When set, initiates a request for the DMA
1
controller to enter Debug mode. See
Section 14.7.17, DMA Debug Event
Status Register (DMADESR), on page
14-43.
Reserved. Write to 0 for future compatibility.
0
Core 5 Stop Enable
Enables core 5 subsystem to stop.
CORE4_STP_EN
12
0
Core 4 Stop Enable
Enables core 4 subsystem to stop.
CORE3_STP_EN
11
0
Core 3 Stop Enable
Enables core 3 subsystem to stop.
CORE2_STP_EN
10
0
Core 2 Stop Enable
Enables core 2 subsystem to stop.
CORE1_STP_EN
9
0
Core 1 Stop Enable
Enables core 1subsystem to stop.
CORE0_STP_EN
8
0
Core 0 Stop Enable
Enables core 0 subsystem to stop.
0
1
0
1
0
1
0
1
0
1
0
1
Stop disabled.
Stop enabled.
Stop disabled.
Stop enabled.
Stop disabled.
Stop enabled.
Stop disabled.
Stop enabled.
Stop disabled.
Stop enabled.
Stop disabled.
Stop enabled.
—
7–6
CORE5_DBG_REQ
5
0
Reserved. Write to 0 for future compatibility.
0
Core 5 Debug Request
Asserts a debug request to core 5.
CORE4_DBG_REQ
4
0
Core 4 Debug Request
Asserts a debug request to core 4.
CORE3_DBG_REQ
3
0
Core 3 Debug Request
Asserts a debug request to core 3.
CORE2_DBG_REQ
2
0
Core 2 Debug Request
Asserts a debug request to core 2.
CORE1_DBG_REQ
1
0
Core 1 Debug Request
Asserts a debug request to core 1.
CORE0_DBG_REQ
0
0
Core 0 Debug Request
Asserts a debug request to core 0.
0
1
0
1
0
1
0
1
0
1
0
1
No debug request.
Debug request.
No debug request.
Debug request.
No debug request.
Debug request.
No debug request.
Debug request.
No debug request.
Debug request.
No debug request.
Debug request.
MSC8156 Reference Manual, Rev. 2
8-4
Freescale Semiconductor
Detailed Register Descriptions
8.2.3
General Status Register 1 (GSR1)
GSR1
Bit
General Status Register 1
31
30
29
—
Type
Reset
0
0
Bit
23
22
28
21
20
0
0
Bit
15
14
13
12
—
M3_PU_1
M3_PU_0
MAPLE_PU
0
Bit
7
6
25
24
19
18
17
16
11
10
9
8
—
R
0
0
0
0
0
0
0
5
4
3
2
1
0
CORE_DBG_ CORE_DBG_ CORE_DBG_ CORE_DBG_ CORE_DBG_ CORE_DBG_
STS5
STS4
STS3
STS2
STS1
STS0
R
0
0
0
0
0
0
—
Type
Reset
26
CORE_
CORE_
CORE_
CORE_
CORE_
CORE_
STOP_ACK5 STOP_ACK4 STOP_ACK3 STOP_ACK2 STOP_ACK1 STOP_ACK0
R
0
0
0
0
0
0
Type
Reset
0
27
CORE_
CORE_
CORE_
CORE_
CORE_
CORE_
WAIT_ACK5 WAIT_ACK4 WAIT_ACK3 WAIT_ACK2 WAIT_ACK1 WAIT_ACK0
R
0
0
0
0
0
0
—
Type
Reset
Offset 0x08
0
GSR1 reports the status various general functions for the MSC8156 device. Table 8-3 lists the
GSR1 bit field descriptions.
Table 8-3. GSR1 Bit Descriptions
Name
Reset
Description
—
31–30
CORE_WAIT_ACK5
29
0
Reserved. Write to 0 for future compatibility.
0
Core Wait Acknowledge 5
Reflects whether core 5 subsystem is in
Wait state.
Core Wait Acknowledge 4
Reflects whether core 4 subsystem is in
Wait state
Core Wait Acknowledge 3
Reflects whether core 3 subsystem is in
Wait state.
Core2 Wait Acknowledge 2
Reflects whether core 2 subsystem is in
Wait state
Core1 Wait Acknowledge 1
Reflects whether core 1 subsystem is in
Wait state.
Core Wait Acknowledge 0
Reflects whether core 0 subsystem is in
Wait state.
CORE_WAIT_ACK4
28
0
CORE_WAIT_ACK3
27
0
CORE_WAIT_ACK2
26
0
CORE_WAIT_ACK1
25
0
CORE_WAIT_ACK0
24
0
Settings
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
0
1
Core subsystem not in Wait state.
Core subsystem in Wait state.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-5
General Configuration Registers
Table 8-3. GSR1 Bit Descriptions (Continued)
Name
Reset
Description
—
23–22
CORE_STOP_ACK5
21
0
Reserved. Write to 0 for future compatibility.
0
Core Stop Acknowledge 5
Reflects whether core 5 subsystem is in
Stop state.
Core Stop Acknowledge 4
Reflects whether core 4 subsystem is in
Stop state
Core Stop Acknowledge 3
Reflects whether core 3 subsystem is in
Stop state.
Core Stop Acknowledge 2
Reflects whether core 2 subsystem is in
Stop state
Core Stop Acknowledge 1
Reflects whether core 1 subsystem is in
Stop state.
Core Stop Acknowledge 0
Reflects whether core 0 subsystem is in
Stop state.
Reserved. Write to 0 for future compatibility.
CORE_STOP_ACK4
20
0
CORE_STOP_ACK3
19
0
CORE_STOP_ACK2
18
0
CORE_STOP_ACK1
17
0
CORE_STOP_ACK0
16
0
—
15
M3_PU_1
14
0
0
M3 Power Up Second Half
Reflects the M3 512 KB power up status.
M3_PU_0
13
0
M3 Power Up First Half
Reflects the M3 512 KB power up status.
MAPLE_PU
12
0
MAPLE Power Up
Reflects the MAPLE block power status.
—
11–6
CORE_DBG_STS5
5
0
Reserved. Write to 0 for future compatibility.
0
Core Debug Status 5
Reflects the mode of core 5.
CORE_DBG_STS4
4
0
Core Debug Status 4
Reflects the mode of core 4.
CORE_DBG_STS3
3
0
Core Debug Status 3
Reflects the mode of core 3.
CORE_DBG_STS2
2
0
Core Debug Status 2
Reflects the mode of core 2.
CORE_DBG_STS1
1
0
Core Debug Status 1
Reflects the mode of core 1.
CORE_DBG_STS0
0
0
Core0 Debug Status 0
Reflects the mode of core 0.
Settings
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
Core subsystem not in Stop state.
Core subsystem in Stop state.
0
1
0
1
0
1
512 KB M3 (2nd half) powered down.
512 KB M3 (2nd half) powered up.
512 KB M3 (1st half) powered down.
512 KB M3 (1st half) powered up.
MAPLE powered down.
MAPLE powered up.
0
1
0
1
0
1
0
1
0
1
0
1
Not in Debug mode.
In Debug mode.
Not in Debug mode.
In Debug mode.
Not in Debug mode.
In Debug mode.
Not in Debug mode.
In Debug mode.
Not in Debug mode.
In Debug mode.
Not in Debug mode.
In Debug mode.
MSC8156 Reference Manual, Rev. 2
8-6
Freescale Semiconductor
Detailed Register Descriptions
8.2.4
High Speed Serial Interface Status Register (HSSI_SR)
HSSI_SR
Bit
High Speed Serial Interface Status Register
31
30
29
—
28
27
SERDES2_ PD
Offset 0x0C
26
25
24
DMA1_PD
SRIO1_PD
SERDES1_
PD
Type
Reset
R
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DMA0_PD
SRIO0_PD
PEX_PD
OCN_PD
RMU_PD
SRIO1_STOP
_ACK
SERDES1_PD
Type
Reset
0
0
0
0
R
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SRIO0_STOP
_ACK
SERDES2_
RST_DONE
—
SERDES2_ SRIO_1_ IDLE SRIO_1_OB_I
PD
DLE
Type
Reset
0
0
0
0
R
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PEX_IDLE
—
RMU_IDLE
0
0
0
SERDES1_
RST_DONE
Type
Reset
0
SERDES1_ SRIO_0_ IDLE SRIO_0_OB_I PEX_OB_
PD
DLE
IDLE
R
0
0
0
0
HSSI_SR controls part of the SerDes operation for the MSC8156 device. The register is reset on a
Hard reset. Write accesses can only be performed in Supervisor mode. Table 8-4 lists the HSSI_SR bit
field descriptions.
Table 8-4. HSSI_SR Bit Descriptions
Name
Reset
—
31–30
SERDES2_PD
29–27
0
000
DMA1_PD
26
0
SRIO1_PD
25
0
SERDES1_PD
24–22
000
Description
Settings
Reserved. Write to 0 for future compatibility.
SERDES2 Power Down Status
Indicates the power status of the SERDES2
port. Can be powered down by the Reset
Control Word or GCR control.
DMA1 Power Down Status
Indicates the power status of DMA1. Can be
powered down by the Reset Control Word or
GCR control.
Serial RapidIO Interface 1 Power Down
Status
Indicates the power status of the serial RapidIO
interface 1. Can be powered down by the Reset
Control Word or GCR control.
SERDES1 Power Down Status
Indicates the power status of the SERDES2
port. Can be powered down by the Reset
Control Word or GCR control.
000 Power up.
111 Power down.
All other values reserved.
0
1
Power up.
Power down.
0
1
Power up.
Power down.
000 Power up.
111 Power down.
All other values reserved.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-7
General Configuration Registers
Table 8-4. HSSI_SR Bit Descriptions (Continued)
Name
Reset
Description
DMA0_PD
21
0
SRIO0_PD
20
0
PEX_PD
19
0
OCN_PD
18
0
RMU_PD
17
0
SRIO1_STOP_ACK
16
0
SRIO0_STOP_ACK
15
0
—
14–12
SERDES2_RST_DONE
11
0
DMA0 Power Down Status
Indicates the power status of DMA0. Can be
powered down by the Reset Control Word or
GCR control.
Serial RapidIO Interface 0 Power Down
Status
Indicates the power status of the serial RapidIO
interface 0. Can be powered down by the Reset
Control Word or GCR control.
PCI Express Power Down Status
Indicates the power status of the PCI Express
interface. Can be powered down by the Reset
Control Word or GCR control.
OCN Fabric Power Down Status
Indicates the power status of the OCN fabric.
Can be powered down by the Reset Control
Word or GCR control.
RapidIO Messaging Unit Power Down Status
Indicates the power status of the RapidIO
Messaging Unit. Can be powered down by the
Reset Control Word or GCR control.
Serial RapidIO Interface 1 Stop Acknowledge
Status
Indicates the serial RapidIO interface 1 Stop
Acknowledge status.
Serial RapidIO Interface 0 Stop Acknowledge
Status
Indicates the serial RapidIO interface 0 Stop
Acknowledge status.
Reserved. Write to 0 for future compatibility.
SERDES2_PD
10
0
SRIO1_IDLE
9
0
SRIO1_OB_IDLE
8
0
SERDES1_RST_DONE
7
0
0
SERDES2 Reset Done
Indicates whether the SERDES2 has completed
the reset sequence.
Note: Although the reset value is 0, the bit will
change to 1 within 160 µs after reset
depending on whether the SerDes port
is used.
SERDES2 Power Down Status
Indicates the power status of the SERDES2
PHY.
SRIO1 Idle
Indicates whether the SRIO1 unit is idle, that is,
no transactions in progress.
SRIO1 Outbound Idle
Indicates whether the SRIO1 outbound activity
is idle, that is, no outbound transactions in
progress.
SERDES1 Reset Done
Indicates whether the SERDES1 has completed
the reset sequence.
Note: Although the reset value is 0, the bit will
change to 1 within 160 µs after reset
depending on whether the SerDes port
is used.
Settings
0
1
Power up.
Power down.
0
1
Power up.
Power down.
0
1
Power up.
Power down.
0
1
Power up.
Power down.
0
1
Power up.
Power down.
0
1
Not stopped.
Stop ACK issued.
0
1
Not stopped.
Stop ACK issued.
0
1
Reset not complete.
Reset complete.
0
1
Power up.
Power down (PLL is not working).
0
1
Active.
Idle.
0
1
Active.
Idle.
0
1
Reset not complete.
Reset complete.
MSC8156 Reference Manual, Rev. 2
8-8
Freescale Semiconductor
Detailed Register Descriptions
Table 8-4. HSSI_SR Bit Descriptions (Continued)
Name
Reset
Description
SERDES1_PD
6
0
SRIO0_IDLE
5
0
SRIO0_OB_IDLE
4
0
PEX_OB_IDLE
3
0
PEX_IDLE
2
0
—
1
RMU_IDLE
0
0
SERDES1 Power Down Status
Indicates the power status of the SERDES1
PHY.
SRIO0 Idle
Indicates whether the SRIO0 unit is idle, that is,
no transactions in progress.
SRIO0 Outbound Idle
Indicates whether the SRIO0 outbound activity
is idle, that is, no outbound transactions in
progress.
PCI Express Outbound Idle
Indicates whether the PCI Express outbound
activity is idle, that is, no outbound transactions
in progress.
PCI Express Idle
Indicates whether the PCI Express is idle, that
is, no transactions in progress.
Reserved. Write to 0 for future compatibility.
0
RMU Idle
Indicates whether the RMU is idle, that is, no
transactions in progress.
Settings
0
1
Power up.
Power down (PLL is not working).
0
1
Active.
Idle.
0
1
Active.
Idle.
0
1
Active.
Idle.
0
1
Active.
Idle.
0
1
Active.
Idle.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-9
General Configuration Registers
8.2.5
DDR General Control Register (DDR_GCR)
DDR_GCR
Bit
DDR General Control Register
31
30
29
28
27
Offset 0x10
26
25
24
DDR2_GCR_
VSEL
—
Type
Reset
R
0
0
0
0
1
1
0
1
Bit
23
22
21
20
19
18
17
16
—
R/W
DDR2_COP_TERMSEL_OVERRIDE_
VALUE
DDR2_COP_
DDR2_
TERMSEL_ DISABLE_BIT
OVERRIDE_ _DESKEW
EN
—
Type
Reset
0
0
0
0
R/W
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DDR1_GCR_
VSEL
—
Type
Reset
R/W
0
0
0
0
1
1
0
1
Bit
7
6
5
4
3
2
1
0
—
Type
Reset
DDR1_COP_TERMSEL_OVERRIDE_
VALUE
DDR1_COP_
DDR1_
TERMSEL_ DISABLE_BIT
OVERRIDE_ _DESKEW
EN
—
R/W
0
0
0
0
0
0
0
0
DDR_GCR controls the DDR operation the MSC8156 device. The register is reset on a Hard reset.
Write accesses can only be performed in Supervisor mode. Table 8-5 lists the DDR_GCR bit field
descriptions.
Table 8-5. DDR_GCR Bit Descriptions
Name
Reset
Description
—
31–25
DDR2_GCR_VSEL
24
0
Reserved. Write to 0 for future compatibility.
1
DDRC2 Voltage Select
Indicates the type of memory used.
—
23–22
DDR2_COP_TERMSEL_
OVERRIDE_VALUE
21–19
0
Reserved. Write to 0 for future compatibility.
0
DDRC2 Termination Select Override
Value
Sets the value for the termination select
override.
DDRC2 Termination Select Override
Enable
Disables/enables the termination select
override.
DDR2_COP_TERMSEL_
OVERRIDE_EN
18
0
Settings
0
1
DDR3.
DDR2.
0
1
Disable
Enable.
MSC8156 Reference Manual, Rev. 2
8-10
Freescale Semiconductor
Detailed Register Descriptions
Table 8-5. DDR_GCR Bit Descriptions (Continued)
Name
Reset
DDR2_DISABLE_BIT_
DESKEW
17
—
16–9
DDR1_GCR_VSEL
8
0
—
7–6
DDR1_COP_TERMSEL_
OVERRIDE_VALUE
5–3
Description
Settings
DDRC2 Disable Per-Bit Deskew
0
Disables/enables per-bit deskew calibration 1
initialization.
Reserved. Write to 0 for future compatibility.
Enable.
Disable.
1
DDRC1 Voltage Select
Indicates the type of memory used.
0
1
DDR3.
DDR2.
0
Reserved. Write to 0 for future compatibility.
0
DDRC1 Termination Select Override
Value
Sets the value for the termination select
override.
DDRC1 Termination Select Override
Enable
Disables/enables the termination select
override.
DDRC1 Disable Per-Bit Deskew
Disables/enables per-bit deskew calibration
initialization.
Reserved. Write to 0 for future compatibility.
0
1
Disable
Enable.
0
1
Enable.
Disable.
0
DDR1_COP_TERMSEL_
OVERRIDE_EN
2
0
DDR1_DISABLE_BIT_
DESKEW
1
—
0
0
0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-11
General Configuration Registers
8.2.6
High Speed Serial Interface Control Register 1 (HSSI_CR1)
HSSI_CR1
Bit
High Speed Serial Interface Control Register 1
31
30
29
SERDES2_
STOP
SERDES2_
CB_ PD
SERDES2_
ISOR_PD
Type
Reset
0
0
0
Bit
23
22
21
SRIO1_PD
—
Type
Reset
0
0
Bit
15
14
13
12
SRIO0_DOZE
—
SRIO0_PD
—
Type
Reset
0
0
0
Bit
7
6
27
SERDES2_
DOZE
R/W
0
20
26
—
25
24
SRIO1_DOZE
—
0
0
0
0
19
18
17
16
SRIO1_ECC_ SERDES1_ SERDES1_
D
CB_ PD
ISOR_PD
R/W
0
0
0
SERDES1_
DOZE
—
0
0
0
11
10
9
8
—
SERDES1_
STOP
PEX_PD
PEX_DOZE
0
0
0
0
0
5
4
3
2
1
0
OCN_PD
RMU_PD
RMU_DOZE
—
SERDES2_
CONFIG_
DISABLE
SERDES1_
CONFIG_
DISABLE
0
0
0
1
1
R/W
—
Type
Reset
28
Offset 0x14
R/W
0
0
0
HSSI_CR1 controls various functions within the SerDes block for the MSC8156 device. The
register is reset on a hard reset. Write accesses can only be performed in Supervisor mode. Table 8-6
lists the HSSI_CR1 bit field descriptions.
Table 8-6. HSSI_CR1 Bit Descriptions
Name
Reset
Description
Settings
SERDES2_STOP
31
0
SERDES2 PHY Stop
Holds the SERDES2 PHY in reset.
SERDES2_CB_PD
30
0
SERDES2_ISOR_PD
29
0
SERDES2_DOZE
28
0
—
27–26
0
SERDES2 Control Block Power Down
Shuts down SERDES2 control block ring
power.
SERDES2 Isolation Ring Power Down
0
Shuts down SERDES2 isolation ring power. 1
SERDES2 Doze
0
Used to select Doze mode, in which all
1
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
SerDes port is stopped.
Reserved. Write to 0 for future compatibility.
0
1
0
1
PHY not stopped.
PHY stopped.
Power up.
Power down.
Power up.
Power down.
Normal operation.
Doze mode.
MSC8156 Reference Manual, Rev. 2
8-12
Freescale Semiconductor
Detailed Register Descriptions
Table 8-6. HSSI_CR1 Bit Descriptions (Continued)
Name
Reset
SRIO1_DOZE
25
0
—
24
SRIO1_PD
23
0
—
22–21
SERDES1_CB_PD
20
0
SERDES1_ISOR_PD
19
0
SERDES1_DOZE
18
0
—
17–16
SRIO0_DOZE
15
0
—
14
SRIO0_PD
13
0
—
12–11
SERDES1_STOP
10
0
Description
Settings
Serial RapidIO Interface 1 Doze
0
Used to select Doze mode, in which all
1
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
Serial RapidIO interface clock is stopped.
Reserved. Write to 0 for future compatibility.
Normal operation.
Doze mode.
Serial RapidIO Interface 1 Power Down
0
Shuts down serial RapidIO interface 1
1
power.
Reserved. Write to 0 for future compatibility.
Power up.
Power down.
SERDES1 Control Block Power Down
Shuts down SERDES1 control block ring
power.
SERDES1 Isolation Ring Power Down
Shuts down SERDES1 isolation ring power.
0
1
Power up.
Power down.
0
1
0
1
Power up.
Power down.
Normal operation.
Doze mode.
Serial RapidIO Interface 0 Doze
0
Used to select Doze mode, in which all
1
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
Serial RapidIO clock is stopped.
Reserved. Write to 0 for future compatibility.
Normal operation.
Doze mode.
Serial RapidIO Interface 0 Power Down
0
Shuts down serial RapidIO interface 0
1
power.
Reserved. Write to 0 for future compatibility.
Power up.
Power down.
0
SERDES1 PHY Stop
Holds the SERDES1 PHY in reset.
PEX_PD
9
0
PCI Express Power Down
Shuts down PCI Express power.
PEX_DOZE
8
0
PCI Express Doze
Used to select Doze mode, in which all
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
PCI Express clock is stopped.
PHY not stopped.
PHY stopped.
Power up.
Power down.
Normal operation.
Doze mode.
0
0
0
0
SERDES1 Doze
Used to select Doze mode, in which all
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
SerDes port is stopped.
Reserved. Write to 0 for future compatibility.
0
1
0
1
0
1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-13
General Configuration Registers
Table 8-6. HSSI_CR1 Bit Descriptions (Continued)
Name
Reset
Description
—
7–6
OCN_PD
5
0
Reserved. Write to 0 for future compatibility.
0
OCN Power Down
Shuts down OCN fabric power.
RMU_PD
4
0
RMU Power Down
Shuts down RMU power.
RMU_DOZE
3
0
Settings
0
1
0
1
0
1
Power up.
Power down.
Power up.
Power down.
Normal operation.
Doze mode.
RMU Doze
Used to select Doze mode, in which all
register accesses are acknowledged, but
writes are not written and reads do not
contain valid data. Setting this bit prevents
lockup of the device internal bus while the
RMU is stopped.
—2
0
Reserved. Write to 0 for future compatibility.
SERDES2_CONFIG_
1
SERDES2 SRDS2CR2 Override
0 Disabled.
DISABLE
Enables/disables SERDES2 SRDS2CR2.
1 Enabled.
1
When enabled (1), overrides the values in
SRDS2CR2[X3SA/X3SB/X3SE/X3SF] and
forces them to be 1. This forces all four
SerDes lanes to be tri-stated. When
disabled (0), there is no override and the
values defined for each channel by
SRDS2CR2[X3SA/X3SB/X3SE/X3SF] are
used to determine whether the port is in a
normal operation mode or tri-stated. The
value of this bit has no effect on any other
fields in SRDS2CR2 and only overrides the
specified fields.
SERDES1_CONFIG_
1
SERDES1 SRDS1CR2 Override
0 Disabled.
DISABLE
Enables/disables SERDES1 SRDS1CR2.
1 Enabled.
0
When enabled (1), overrides the values in
SRDS1CR2[X3SA/X3SB/X3SE/X3SF] and
forces them to be 1. This forces all four
SerDes lanes to be tri-stated. When
disabled (0), there is no override and the
values defined for each channel by
SRDS1CR2[X3SA/X3SB/X3SE/X3SF] are
used to determine whether the port is in a
normal operation mode or tri-stated. The
value of this bit has no effect on any other
fields in SRDS1CR2 and only overrides the
specified fields.
Note: Doze mode is a special mode used by the MSC8156 to allow register reads/writes to continue and be acknowledged
without changing or reporting any register contents while the peripheral clocking is stopped. Processing of
reads/writes can continue after the peripheral has entered power down mode. Without Doze mode, the device could
hang up waiting for a response from the peripheral. This mode permits acknowledgement of the read or write, but
does not read or write any meaningful data.
MSC8156 Reference Manual, Rev. 2
8-14
Freescale Semiconductor
Detailed Register Descriptions
8.2.7
High Speed Serial Interface Control Register 2 (HSSI_CR2)
HSSI_CR2
Bit
High Speed Serial Interface Control Register 2
31
30
29
28
Offset 0x18
27
26
25
24
—
Type
Reset
0
0
0
0
R
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
Reset
0
0
0
0
R
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
RMU_COL_D
0
MAG2SB_
STOP
R/W
0
0
0
—
Type
Reset
R
0
0
0
0
HSSI_CR2 controls various functions within the SerDes block for the MSC8156 device. The
register is reset on a hard reset. Write accesses can only be performed in Supervisor mode. Table 8-7
lists the HSSI_CR2 bit field descriptions.
Table 8-7. HSSI_CR2 Bit Descriptions
Name
Reset
—
31–3
MAG2SB_STOP
2
0
Reserved. Write to 0 for future compatibility.
0
Not stopped.
Stopped.
—
1
RMU_COL_D
0
0
MBus to SBus Stop
0
Stops the master bus to slave bus bridge. The MBus is the internal 1
bus controlled by internal master devices. The SBus is used to
access internal registers. This bridge is the interface between the
MBus and the SBus. To prevent. lockup if a master device
read/writes a peripheral register when the clock is stopped, the
MBus completes the access, but read data is invalid and no data is
written. This bit can be used to determine if read data is valid or if
the write occurred.
Reserved. Write to 0 for future compatibility.
RapidIO Messaging Unit Collision Disable
Enables/disables the RMU collision detection.
Collision detection
enabled.
Collision detection
disabled.
0
Description
Settings
0
1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-15
General Configuration Registers
8.2.8
QUICC Engine Control Register (QECR)
QECR
Bit
QUICC Engine Control Register
31
30
29
28
Offset 0x1C
27
26
25
24
—
R
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
Reset
R
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
Type
Reset
R
0
0
0
0
ENET_SGMII ENET_SGMII
_MODE1
_MODE0
R/W
0
0
—
0
0
QECR controls various functions within the QUICC Engine module for the MSC8156 device. The
register is reset on a Hard reset. Write accesses can only be performed in Supervisor mode. Table 8-8
lists the QECR bit field descriptions.
Table 8-8. QECR Bit Descriptions
Name
Reset
Description
—
31–4
ENET_SGMII_MODE1
3
0
Reserved. Write to 0 for future compatibility.
0
Selects GMII or RGMII for Ethernet
Controller 2
Selects SGMII mode for Ethernet controller
2.
Selects GMII or RGMII for Ethernet
Controller 1
Selects SGMII mode for Ethernet controller
1.
Reserved. Write to 0 for future compatibility.
ENET_SGMII_MODE0
2
0
—
1–0
0
Settings
0
1
RGMII selected.
SGMII selected.
0
1
RGMII1 selected.
SGMII1 selected.
MSC8156 Reference Manual, Rev. 2
8-16
Freescale Semiconductor
Detailed Register Descriptions
8.2.9
GPIO Pull-Up Enable Register (GPUER)
GPUER
Bit
GPIO Pull-Up Enable Register
Offset 0x20
31
30
29
28
27
26
25
24
PUE_B31
PUE_B30
PUE_B29
PUE_B28
PUE_B27
PUE_B26
PUE_B25
PUE_B24
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
PUE_B23
PUE_B22
PUE_B21
PUE_B20
PUE_B19
PUE_B18
PUE_B17
PUE_B16
0
0
0
0
Type
Reset
Bit
R/W
R/W
0
0
0
0
15
14
13
12
11
10
9
8
PUE_B15
PUE_B14
PUE_B13
PUE_B12
PUE_B11
PUE_B10
PUE_B9
PUE_B8
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PUE_B7
PUE_B6
PUE_B5
PUE_B4
PUE_B3
PUE_B2
PUE_B1
PUE_B0
0
0
0
0
Type
Reset
R/W
R/W
0
0
0
0
GPUER enables/disables the individual GPIO pull-up resistors. The register is reset on a Hard reset.
Write accesses can only be performed in Supervisor mode. Table 8-9 lists the GPUER bit field
descriptions.
Table 8-9. GPUER Bit Descriptions
Name
Reset
PUE_B[31–0]
31–0
0
Description
Pull-Up Enable 31–0
Each bit in this field enables/disables the
GPIO pull-up resistor corresponding to the
bit index number.
Settings
0
1
Pull-up input is enabled.
Pull-up input is disabled.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-17
General Configuration Registers
8.2.10
GPIO Input Enable Register (GIER)
GIER
Bit
GPIO Input Enable Register
Offset 0x24
31
30
29
28
27
26
25
24
IE31
IE30
IE29
IE28
IE27
IE26
IE25
IE24
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
IE23
IE22
IE21
IE20
IE19
IE18
IE17
IE16
0
0
0
0
Type
Reset
Bit
R/W
R/W
0
0
0
0
15
14
13
12
11
10
9
8
IE15
IE14
IE13
IE12
IE11
IE10
IE9
IE8
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
IE7
IE6
IE5
IE4
IE3
IE2
IE1
IE0
0
0
0
0
Type
Reset
R/W
R/W
0
0
0
0
GIER enables/disables the individual GPIO signals. The register is reset on a hard reset. Write
accesses can only be performed in Supervisor mode. Table 8-10 lists the GIER bit field descriptions.
Table 8-10. GIER Bit Descriptions
Name
Reset
IE[31–0]
31–0
0
Description
Input Enable 31–0
Each bit in this field enables/disables the
individual GPIO corresponding to the bit
index number.
Settings
0
1
Input is disabled.
Input is enabled.
MSC8156 Reference Manual, Rev. 2
8-18
Freescale Semiconductor
Detailed Register Descriptions
8.2.11
System Part and Revision ID Register (SPRIDR)
SPRIDR
Bit
System Part and Revision ID Register
31
30
29
28
Offset 0x28
27
26
25
24
PARTID
R
Type
Reset
1
0
0
0
0
0
1
1
Bit
23
22
21
20
19
18
17
16
0
0
1
0
11
10
9
8
PARTID
R
Type
Reset
0
0
0
0
Bit
15
14
13
12
REVID
R
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0
0
0
0
Type
Reset
REVID
R
0
0
0
0
SPRIDR provides information about the device and revision numbers. Table 8-11 lists the
SPRIDR bit field descriptions.
Table 8-11. SPRIDR Bit Descriptions
Name
Reset
Description
PARTID
31–16
REVID
15–0
0x8302
Part Identification
Mask-programmed with a code corresponding to the device number.
Revision Identification
Mask-programmed with a code corresponding to the revision number of
the part identified by the PARTID value.
0x0000
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-19
General Configuration Registers
8.2.12
General Control Register 4 (GCR4)
GCR4
Bit
General Control Register 4
31
30
29
28
Offset 0x30
27
26
25
24
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
UCC3RCLKID
Type
Reset
0
0
0
Bit
15
14
13
UCC3TCLKID
R/W
UCC3CLKOD
0
0
12
11
0
0
0
10
9
8
UCC3TXDD
UCC3RXDD
UCC1RCLKID
Type
Reset
R/W
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
UCC1TCLKID
Type
Reset
UCC1CLKOD
UCC1RXDD
UCC1TXDD
R/W
0
0
0
0
0
0
0
0
GCR4 controls the delay lines for UCC1 and UCC3. The register is reset on a Hard reset. Write
accesses can only be performed in Supervisor mode.
The MSC8156 Data Sheet includes recommended default values for this register to use with a
standard RGMII PHY device. AN3811 Using GCR4 to Adjust Ethernet Timing in MSC8144
DSPs (available under NDA) provides guidelines for adjusting GCR4 values for specific
applications, if required. Although this application note is directed toward designs using the
MSC8144 DSP, the procedures used to adjust GCR4 apply to the MSC8156 DSP.
Table 8-8 lists the GCR4 bit field descriptions.
Table 8-12. GCR4 Bit Descriptions
Name
Reset
Description
—
31–20
UCC3RCLKID
19–18
0
Reserved. Write to 0 for future compatibility.
0
UCC3 RX Clock In Delay
Adds a delay to the specified signal.
0
UCC3 TX Clock In Delay
Adds a delay to the specified signal.
UCC3TCLKID
17–16
Settings
00
01
10
11
00
01
10
11
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
MSC8156 Reference Manual, Rev. 2
8-20
Freescale Semiconductor
Detailed Register Descriptions
Table 8-12. GCR4 Bit Descriptions (Continued)
Name
Reset
UCC3CLKOD
15–14
0
UCC3 Clock Out Delay
Adds a delay to the specified signal.
UCC3RXDD
13–12
0
UCC3 RX Data Delay
Adds a delay to the specified signal.
UCC3TXDD
11–10
0
UCC3 TX Data Delay
Adds a delay to the specified signal.
UCC1RCLKID
9–8
0
UCC1 RX Clock In Delay
Adds a delay to the specified signal.
UCC1TCLKID
7–6
0
UCC1 TX Clock In Delay
Adds a delay to the specified signal.
UCC1CLKOD
5–4
0
UCC1 Clock Out Delay
Adds a delay to the specified signal.
UCC1RXDD
3–2
0
UCC1 RX Data Delay
Adds a delay to the specified signal.
UCC1TXDD
1–0
0
UCC1 TX Data Delay
Adds a delay to the specified signal.
Note:
Description
Settings
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
No delay.
One delay unit.
Two delay units.
Three delay units.
The clock for the delay unit is the TX clock.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-21
General Configuration Registers
8.2.13
General Control Register 5 (GCR5)
GCR5
Bit
General Control Register 5
31
30
29
28
Offset 0x34
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PEX_IRQ_
OUT
OCNDMA1_
POWER
DOWN
OCNDMA1_
DOZE
OCNDMA1_
STOP
—
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
OCNDMA0_
POWER
DOWN
OCNDMA0_
DOZE
OCNDMA0_
STOP
—
0
0
0
—
Type
Reset
R/W
0
0
0
0
0
GCR5 performs various control functions. All bits are cleared on reset.
Table 8-13. GCR5 Bit Descriptions
Name
Reset
Description
Settings
—
31–13
0
Reserved. Write to zero for future compatibility.
PEX_IRQ_
OUT
12
0
PCI Express Message Signal Interrupt
0
No PCI Express message.
Triggers the PCI Express message signal interrupt.
1
PCI Express message
interrupt.
OCNDMA1_
POWER
DOWN
11
0
OCNDMA 1 Complex Power Down
0
OCNDMA1 powered up.
Makes the OCNDMA1 complex power down.
1
OCNDMA1 power down (Stop
ACK).
OCNDMA1_
DOZE
10
0
OCNDMA 1 Doze
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA1 is stopped.
0
Normal operation.
1
Doze mode.
MSC8156 Reference Manual, Rev. 2
8-22
Freescale Semiconductor
Detailed Register Descriptions
Table 8-13. GCR5 Bit Descriptions (Continued)
Name
Reset
Description
OCNDMA1_
STOP
9
0
—
8–4
0
Reserved. Write to zero for future compatibility.
OCNDMA0_
POWER
DOWN
3
0
OCNDMA0_
DOZE
2
0
OCNDMA0_
STOP
1
0
—
0
0
Settings
OCNDMA 1 Stop
0
OCNDMA1 normal operation.
Makes the OCNDMA1 enter Stop mode.
1
OCNDMA1 Stop mode.
OCNDMA 0 Complex Power Down
Drives the ips_wait signal to 0 in preparation for
power down to avoid ips transactions becoming
stuck.
0
OCNDMA0 powered up.
1
OCNDMA0 power down (Stop
ACK).
OCNDMA 0 Doze
Used to select Doze mode, in which all register
accesses are acknowledged, but writes are not
written and reads do not contain valid data. Setting
this bit prevents lockup of the device internal bus
while the OCNDMA0 is stopped.
0
Normal operation.
1
Doze mode.
OCNDMA 0 Stop
0
OCNDMA0 normal operation.
Makes the OCNDMA0 enter Stop mode.
1
OCNDMA0 Stop mode.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-23
General Configuration Registers
8.2.14
General Status Register 2 (GSR2)
GSR2
Bit
General Status Register 2
31
30
29
28
27
Offset 0x38
26
DDR2_IDLE_ DDR2_YMMC DDR1_IDLE_ DDR1_YMMC
MEM
_STOP_ACK
MEM
_STOP_ACK
Type
25
24
—
R
Reset
1
0
1
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
CORE_STOP CORE_STOP CORE_STOP CORE_STOP CORE_STOP CORE_STOP
_REQ5
_REQ4
_REQ3
_REQ2
_REQ1
_REQ0
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SCOP_IDLE
—
OCNDMA1_
IDLE
—
OCNDMA0_
IDL:E
—
1
0
1
0
—
Type
Reset
R
0
0
1
0
GSR2 reflects the status of various functions. All bits are cleared on reset.
Table 8-14. GSR2 Bit Descriptions
Name
Reset
DDR2_IDLE_
MEM
31
0
DDR2_YMMC_
STOP_ACK
30
0
DDR1_IDLE_
MEM
29
0
DDR1_YMMC_
STOP_ACK
30
0
—
27–22
0
Description
Settings
DDR2 Controller Idle
Reflects the current status of DDR Controller 2.
0
Memory controller 2 active.
1
Memory controller 2 idle.
DDR2 Controller Refresh Mode
Reflects the current status of DDR Controller 2
refresh mode.
0
Memory controller 2 not in
self-refresh mode.
1
Memory controller 2 in
self-refresh mode.
DDR1 Controller Idle
Reflects the current status of DDR Controller 1.
0
Memory controller 1 active.
1
Memory controller 1 idle.
DDR1 Controller Refresh Mode
Reflects the current status of DDR Controller 1
refresh mode.
0
Memory controller 1 not in
self-refresh mode.
1
Memory controller 1 in
self-refresh mode.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
8-24
Freescale Semiconductor
Detailed Register Descriptions
Table 8-14. GSR2 Bit Descriptions (Continued)
Name
Reset
Description
CORE_STOP_
REQ5
21
0
CORE_STOP_
REQ4
20
0
CORE_STOP_
REQ3
19
0
CORE_STOP_
REQ2
18
0
CORE_STOP_
REQ1
17
0
CORE_STOP_
REQ0
16
0
—
15–6
0
Reserved. Write to zero for future compatibility.
SCOP_IDLE
5
0
SEC Idle
Reflects the current status of the SEC block.
—
4
0
Reserved. Write to zero for future compatibility.
OCNDMA1_
IDLE
3
0
OCNDMA1 Idle
Reflects the current status of the OCNDMA1 block.
—
2
0
Reserved. Write to zero for future compatibility.
OCNDMA0_
IDLE
1
0
OCNDMA0 Idle
Reflects the current status of the OCNDMA0 block.
—
0
0
Settings
Core 5 Stop Request
Reflects whether a core stop was requested.
0
Core 5 stop not requested.
1
Core 5 stop requested.
Core 4 Stop Request
Reflects whether a core stop was requested.
0
Core 4 stop not requested.
1
Core 4 stop requested.
Core 3 Stop Request
Reflects whether a core stop was requested.
0
Core 3 stop not requested.
1
Core 3 stop requested.
Core 2 Stop Request
Reflects whether a core stop was requested.
0
Core 2 stop not requested.
1
Core 2 stop requested.
Core 1 Stop Request
Reflects whether a core stop was requested.
0
Core 1 stop not requested.
1
Core 1 stop requested.
Core 0 Stop Request
Reflects whether a core stop was requested.
0
Core 0 stop not requested.
1
Core 0 stop requested.
0
Active
1
Idle
0
Active
1
Idle
0
Active
1
Idle
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-25
General Configuration Registers
8.2.15
Core Subsystem Slave Port Priority Control Register (TSPPCR)
TSPPCR
Bit
Core Subsystem Slave Port Priority Control Register
31
30
29
28
Offset 0x3C
27
26
25
24
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Type
Reset
0
0
—
SPP_P3_MAP SPP_P2_MAP SPP_P1_MAP SPP_P0_MAP
R
R/W
0
0
1
1
0
0
TSPPCR reflects the priority assigned to the core subsystem slave ports.
Table 8-15. TSPPCR Bit Descriptions
Name
Reset
—
31–4
0x0000000
SPP_P3_MAP
3
1
SPP_P2_MAP
2
SPP_P1_MAP
1
SPP_P0_MAP
0
Description
Settings
Reserved. Write to zero for future compatibility.
Slave Port Mapping for Priority 3
0
All transactions with priority 3
are assigned priority 0.
1
All transactions with priority 3
are assigned priority 1.
0
All transactions with priority 2
are assigned priority 0.
1
All transactions with priority 2
are assigned priority 1.
0
All transactions with priority 1
are assigned priority 0.
1
All transactions with priority 1
are assigned priority 1.
0
All transactions with priority 0
are assigned priority 0.
1
All transactions with priority 0
are assigned priority 1.
Indicates the priority for the core slave port.
1
Slave Port Mapping for Priority 2
Indicates the priority for the core slave port.
0
Slave Port Mapping for Priority 1
Indicates the priority for the core slave port.
0
Slave Port Mapping Priority 0
Indicates the priority for the core slave port.
MSC8156 Reference Manual, Rev. 2
8-26
Freescale Semiconductor
Detailed Register Descriptions
8.2.16
QUICC Engine First External Request Multiplex Register (CPCE1R)
CPCE1R
Bit
QUICC Engine First External Request Multiplex Register
31
30
29
28
Offset 0x40
27
26
25
24
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Type
Reset
0
0
0
—
QE_INT1_MNG
R
R/W
0
0
0
0
0
CPE1R determines how the first QUICC Engine external request is assigned. All bits are cleared
on reset.
Table 8-16. CPE1R Bit Descriptions
Name
Reset
Description
—
31–2
0
Reserved. Write to zero for future compatibility.
QE_INT1_
MNG
1–0
0
QUICC Engine External Request 1 Multiplexing
Indicates how to process the external request.
Settings
00
01
10
11
RapidIO interrupt.
Reserved.
SEC primary interrupt.
Reserved.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-27
General Configuration Registers
8.2.17
QUICC Engine Second External Request Multiplex Register
(CPCE2R)
CPCE2R
Bit
QUICC Engine Second External Request Multiplex Register
31
30
29
28
Offset 0x44
27
26
25
24
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Type
Reset
0
0
0
—
QE_INT2_MNG
R
R/W
0
0
0
0
0
CPE2R determines how the second QUICC Engine external request is assigned. All bits are
cleared on reset.
Table 8-17. CPE2R Bit Descriptions
Name
Reset
Description
—
31–2
0
Reserved. Write to zero for future compatibility.
QE_INT2_
MNG
1–0
0
QUICC Engine External Request 2 Multiplexing
Indicates how to process the external request.
Settings
00
01
10
11
RapidIO interrupt.
Reserved.
SEC primary interrupt.
Reserved.
MSC8156 Reference Manual, Rev. 2
8-28
Freescale Semiconductor
Detailed Register Descriptions
8.2.18
QUICC Engine Third External Request Multiplex Register
(CPCE3R)
CPCE3R
Bit
QUICC Engine Third External Request Multiplex Register
31
30
29
28
Offset 0x48
27
26
25
24
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Type
Reset
0
0
0
—
QE_INT3_MNG
R
R/W
0
0
0
0
0
CPE3R determines how the third QUICC Engine external request is assigned. All bits are cleared
on reset.
Table 8-18. CPE3R Bit Descriptions
Name
Reset
Description
—
31–2
0
Reserved. Write to zero for future compatibility.
QE_INT3_
MNG
1–0
0
QUICC Engine External Request 3 Multiplexing
Indicates how to process the external request.
Settings
00
01
10
11
RapidIO interrupt.
Reserved.
SEC primary interrupt.
Reserved.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-29
General Configuration Registers
8.2.19
QUICC Engine Fourth External Request Multiplex Register
(CPCE4R)
CPCE4R
Bit
QUICC Engine Fourth External Request Multiplex Register
31
30
29
28
Offset 0x4C
27
26
25
24
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Type
Reset
0
0
0
—
QE_INT4_MNG
R
R/W
0
0
0
0
0
CPE4R determines how the fourth QUICC Engine external request is assigned. All bits are
cleared on reset.
Table 8-19. CPE4R Bit Descriptions
Name
Reset
Description
—
31–2
0
Reserved. Write to zero for future compatibility.
QE_INT4_
MNG
1–0
0
QUICC Engine External Request 4 Multiplexing
Indicates how to process the external request.
Settings
00
01
10
11
RapidIO interrupt.
Reserved.
SEC primary interrupt.
Reserved.
MSC8156 Reference Manual, Rev. 2
8-30
Freescale Semiconductor
Detailed Register Descriptions
8.2.20
General Control Register 10 (GCR10)
GCR10
Bit
General Control Register 10
31
30
29
28
Offset 0x74
27
26
25
24
—
Type
R/W
Reset
1
1
1
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
MCK1_EN_
DDR1
MCK2_EN_
DDR1
MCK1_EN_
DDR2
MCK2_EN_
DDR2
1
1
1
—
Type
R/W
Reset
1
1
1
1
1
GCR10 is used to control the DDR controller clocks.
Table 8-20. GCR10 Bit Descriptions
Name
Reset
—
31–4
0xFFFFFFF
MCK1_EN_DDR1
3
1
MCK2_EN_DDR1
2
1
MCK1_EN_DDR2
1
1
MCK2_EN_DDR2
0
1
Description
Settings
Reserved. Write to zero for future compatibility.
DDR1 MCK1 Enable
Enables/disables MCK1 for DDR1
0
Disabled.
1
Enabled
DDR1 MCK2 Enable
Enables/disables MCK2 for DDR1
0
Disabled.
1
Enabled
DDR2 MCK1 Enable
Enables/disables MCK1 for DDR2
0
Disabled.
1
Enabled
DDR2 MCK2 Enable
Enables/disables MCK2 for DDR2
0
Disabled.
1
Enabled
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-31
General Configuration Registers
8.2.21
General Interrupt Register 1 (GIR1)
GIR1
General Interrupt Register 1
Bit
Offset 0x80
31
30
29
28
27
26
25
24
SWT7
SWT6
SWT5
SWT4
SWT3
SWT2
SWT1
SWT0
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
O2M1_ERR
O2M0_ERR
—
DMA_ERR
CE_IECC
CE_DECC
—
TDM_P0ECC
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TDM3_TERR TDM3_RERR TDM2_TERR TDM2_RERR TDM1_TERR TDM1_RERR TDM0_TERR TDM0_RERR
Type
Reset
R/W
0
0
0
0
0
0
0
0
GIR1 includes the interrupt status of several events that are rare. Those bits are not sticky and
only sample the events. The GIR1 is reset by a hard reset event. All bits are cleared on reset.
Table 8-21. GIR1 Bit Descriptions
Name
Reset
SWT7
31
0
SWT6
30
0
SWT5
29
0
SWT4
28
0
SWT3
27
0
Description
Settings
Software Watchdog Timer 7
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 6
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 5
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 4
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 3
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
MSC8156 Reference Manual, Rev. 2
8-32
Freescale Semiconductor
Detailed Register Descriptions
Table 8-21. GIR1 Bit Descriptions (Continued)
Name
Reset
Description
SWT2
26
0
SWT1
25
0
SWT0
24
0
O2M1_ERR
23
0
O2M0_ERR
22
0
—
21
0
Reserved. Write to zero for future compatibility.
DMA_ERR
20
0
CE_IECC
19
0
CE_DECC
18
0
—
17
0
Reserved. Write to zero for future compatibility.
TDM_P0ECC
16
0
TDM Parity Error
Reflects the ORed status of the TDM[0–3] parity
error interrupts.
—
15–8
0
Reserved. Write to zero for future compatibility.
TDM3_TERR
7
0
TDM3 Transmit Error
Reflects the status of the TDM3 transmit error
interrupt.
Settings
Software Watchdog Timer 2
Reflects the status of the watchdog timer
interrupt.See Section 21.3, Software Watchdog
Timers, on page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 1
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
Software Watchdog Timer 0
Reflects the status of the watchdog timer interrupt.
See Section 21.3, Software Watchdog Timers, on
page 21-13.
0
Interrupt not asserted
1
Interrupt asserted
O2M 1 Error
Reflects the status of the O2M1 error interrupt.
Possible causes for an interrupt include:
• Unsupported packet type detected on the OCN
outbound interface.
• OCN end-of-packet signal is asserted before the
expected end-of-transaction.
• Data error. Data is corrupted on the O2M bridge.
0
Interrupt not asserted
1
Interrupt asserted
O2M 0 Error
Reflects the status of the O2M0 error interrupt.
Possible causes for an interrupt include:
• Unsupported packet type detected on the OCN
outbound interface.
• OCN end-of-packet signal is asserted before the
expected end-of-transaction.
• Data error. Data is corrupted on the O2M bridge.
0
Interrupt not asserted
1
Interrupt asserted
DMA Error
Reflects the status of the DMA error interrupt. See
Section 14.7.16, DMA Error Register
(DMAERR), on page 14-41.
0
Interrupt not asserted
1
Interrupt asserted
QUICC Engine IRAM Error
Reflects the status of the QUICC Engine IRAM ECC
error interrupt.
0
Interrupt not asserted
1
Interrupt asserted
QUICC Engine DRAM Error
Reflects the status of the QUICC Engine DRAM
ECC error interrupt.
0
Interrupt not asserted
1
Interrupt asserted
0
Interrupt not asserted
1
Interrupt asserted
0
Interrupt not asserted
1
Interrupt asserted
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-33
General Configuration Registers
Table 8-21. GIR1 Bit Descriptions (Continued)
Name
Reset
TDM3_RERR
6
0
TDM2_TERR
5
0
TDM2_RERR
4
0
TDM1_TERR
3
0
TDM1_RERR
2
0
TDM0_TERR
1
0
TDM0_RERR
0
0
Description
Settings
TDM3 Receive Error
Reflects the status of the TDM3 receive error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM2 Transmit Error
Reflects the status of the TDM2 transmit error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM2 Receive Error
Reflects the status of the TDM2 receive error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM1 Transmit Error
Reflects the status of the TDM1 transmit error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM1 Receive Error
Reflects the status of the TDM1 receive error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM0 Transmit Error
Reflects the status of the TDM0 transmit error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
TDM0 Receive Error
Reflects the status of the TDM0 receive error
interrupt.
0
Interrupt not asserted
1
Interrupt asserted
MSC8156 Reference Manual, Rev. 2
8-34
Freescale Semiconductor
Detailed Register Descriptions
8.2.22
General Interrupt Enable Register 1 (GIER1_x)
GIER1_0
GIER1_1
GIER1_2
GIER1_3
GIER1_4
GIER1_5
Bit
‘General Interrupt Enable Register 1 for Cores 0–5
Offset 0x84
Offset 0x88
Offset 0x8C
Offset 0x90
Offset 0x94
Offset 0x98
31
30
29
28
27
26
25
24
SWT7_EN_n
SWT6_EN_n
SWT5_EN_n
SWT4_EN_n
SWT3_EN_n
SWT2_EN_n
SWT1_EN_n
SWT0_EN_n
Type
Reset
R/W
1
1
1
1
1
1
1
1
Bit
23
22
21
20
19
18
17
16
—
TDM_P0ECC_
EN_n
O2M1_ERR_EN O2M0_ERR_EN
_n
_n
—
DMA_ERR_EN_ CE_IECC_EN_nCE_DECC_EN_
n
n
Type
Reset
0
0
0
0
R/W
Bit
15
14
13
12
0
0
0
0
11
10
9
8
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TDM3_TERR_ TDM3_RERR_ TDM2_TERR_ TDM2_RERR_ TDM1_TERR_ TDM1_RERR_ TDM0_TERR_
EN_n
EN_n
EN_n
EN_n
EN_n
EN_n
EN_n
Type
Reset
TDM0_RERr_
EN_n
R/W
0
0
0
0
0
0
0
0
GIER1_[0–5] includes interrupt enable bits of for the interrupts defined in GIR1 for cores 0–5.
The register is reset by a hard reset event. All bits are cleared by reset. Write accesses to this
register can only be performed in supervisor mode.
Table 8-22. GIER1_n Bit Descriptions
Name
Reset
Description
SWT7_EN_n
31
0
SWT 7 Interrupt Enable
SWT6_EN_n
30
0
SWT 6 Interrupt Enable
SWT5_EN_n
29
0
SWT 5 Interrupt Enable
SWT4_EN_n
28
0
SWT 4 Interrupt Enable
SWT3_EN_n
27
0
SWT 3 Interrupt Enable
SWT2_EN_n
26
0
SWT 2 Interrupt Enable
Settings
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-35
General Configuration Registers
Table 8-22. GIER1_n Bit Descriptions
Name
Reset
Description
SWT1_EN_n
25
0
SWT0_EN_n
24
0
O2M1_ERR_EN
_n
23
0
O2M0_ERR_EN
_n
22
0
—
21
0
Reserved. Write to zero for future compatibility.
DMA_ERR_EN_
n
20
0
DMA Error Interrupt Enable
CE_IECC_EN_n
19
0
CE_DECC_EN_
n
18
0
—
17
0
Reserved. Write to zero for future compatibility.
TDM_P0ECC_E
N_n
16
0
Parity Error Interrupt of TDM[0–3] Enable
—
15–8
0
Reserved. Write to zero for future compatibility.
TDM3_TER_EN
_n
7
0
TDM3 Transmit Error Interrupt Enable
TDM3_RER_EN
_n
6
0
TDM2_TER_EN
_n
5
0
TDM2_RER_EN
_n
4
0
TDM1_TER_EN
_n
3
0
TDM1_RER_EN
_n
2
0
TDM0_TER_EN
_n
1
0
TDM0_RER_EN
_n
0
0
SWT 1 Interrupt Enable
SWT 0 Interrupt Enable
O2M1 Error Interrupt Enable
O2M0 Error Interrupt Enable
Settings
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
ECC Error Interrupt of the QUICC Engine IMEM
Enable
0
Interrupt disabled
1
Interrupt enabled
ECC Error Interrupt of the QUICC Engine DRAM
Enable
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
TDM3 Receive Error Interrupt Enable
TDM2 Transmit Error Interrupt Enable
TDM2 Receive Error Interrupt Enable
TDM1 Transmit Error Interrupt Enable
TDM1 Receive Error Interrupt Enable
TDM0 Transmit Error Interrupt Enable
TDM0 Receive Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
MSC8156 Reference Manual, Rev. 2
8-36
Freescale Semiconductor
Detailed Register Descriptions
8.2.23
General Interrupt Register 3 (GIR3)
GIR3
Bit
General Interrupt Register 3
31
30
29
28
Offset 0xA4
27
26
25
24
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
DDR2_ERR
DDR1_ERR
Type
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
MAPLE_ECC_ MAPLE_ECC_ MAPLE_ECC_ MAPLE_ECC_
DRAM
IMEM
DFT
FFT
—
R/W
—
MAPLE_GEN_
ERR
—
PM
Type
Reset
R/W
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CLS0_WP
CLS0_OV
0
0
—
Type
Reset
CLS0_ERR
—
R/W
0
0
0
0
0
0
GIR3 includes interrupt status of some debug/profiling events within MSC8156. Those bits are
not sticky but only sample the events. The GIR3 register is reset by a hard reset event. All bits are
cleared on reset.
Table 8-23. GIR3 Bit Descriptions
Name
Reset
Description
Settings
—
31–23
0
Reserved. Write to zero for future compatibility.
DDR2_ERR
22
0
DDR2 Error Interrupt
Reflects the status of the interrupt. See
Section 12.6, Error Management, on page
12-35.
0
Interrupt not asserted
1
Interrupt asserted
DDR1_ERR
21
0
DDR1 Error Interrupt
Reflects the status of the interrupt. See
Section 12.6, Error Management, on page
12-35.
0
Interrupt not asserted
1
Interrupt asserted
MAPLE_ECC_DRAM
20
0
MAPLE DRAM Error Interrupt
Reflects the status of the interrupt.
0
Interrupt not asserted
1
Interrupt asserted
MAPLE_ECC_IMEM
19
0
MAPLE IMEM Error Interrupt
Reflects the status of the interrupt.
0
Interrupt not asserted
1
Interrupt asserted
MAPLE_ECC_DFT
18
0
MAPLE DFT ECC Error Interrupt
Reflects the status of the interrupt.
0
Interrupt not asserted
1
Interrupt asserted
MAPLE_ECC_FFT
17
0
MAPLE FFT0 ECC Error Interrupt
Reflects the status of the interrupt.
0
Interrupt not asserted
1
Interrupt asserted
—
16–13
0
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-37
General Configuration Registers
Table 8-23. GIR3 Bit Descriptions
Name
Reset
Description
MAPLE_GEN_ERR
12
0
—
11–9
0
Reserved. Write to zero for future compatibility.
PM
8
0
Performance Monitor Interrupt
Reflects the performance monitor interrupt
—
7–5
0
Reserved. Write to zero for future compatibility.
CLS0_ERR
4
0
CLASS0 Error Interrupt
0
Interrupt not asserted
Reflects CLASS0 Error Interrupt
1
Interrupt asserted
—
3–2
0
Reserved. Write to zero for future compatibility.
CLS0_WP
1
0
CLASS0 Watchpoint Interrupt
0
Interrupt not asserted
Reflects Class0 watchpoint interrupt
1
Interrupt asserted
CLS0_OV
0
0
CLASS0 Overrun Interrupt
0
Interrupt not asserted
Reflects CLASS0 overrun interrupt
1
Interrupt asserted
MAPLE General Error Interrupt
Reflects the status of the interrupt. This is
an aggregation of errors that can occur in
the MAPLE-B. See Section 26.3.3.2,
Interrupts.
Settings
0
Interrupt not asserted
1
Interrupt asserted
0
Interrupt not asserted
1
Interrupt asserted
MSC8156 Reference Manual, Rev. 2
8-38
Freescale Semiconductor
Detailed Register Descriptions
8.2.24
General Interrupt Enable Register 3 for Cores 0–3 (GIER3_x)
GIER3_0
GIER3_1
GIER3_2
GIER3_3
GIER3_4
GIER3_5
Bit
General Interrupt Enable Register 3 for Cores 0–3
31
30
29
28
Offset 0xA8
Offset 0xAC
Offset 0xB0
Offset 0xB4
Offset 0xB8
Offset 0xBC
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
DDR2_ERR_EN DDR1_ERR_EN MAPLE_ECC_ MAPLE_ECC_ MAPLE_ECC_ MAPLE_ECC_
_n
_n
DRAM_EN_n
IMEM_EN_n
DFT_EN_n
FFT_EN_n
Type
—
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
MAPLE_GEN_
ERR_EN_n
Type
—
PM_EN_n
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
CLS0_ERR_EN
_n
Type
Reset
—
CLS0_WP_EN_ CLS0_OV_EN_
n
n
R/W
0
0
0
0
0
0
0
0
GIER3_[0–5] include interrupt enable bits for cores 0–5 for debug/profiling events within
MSC8156. GIER3_[0–5] are reset by a hard reset event. All bits are cleared on reset. Write
accesses to this register can be performed only in supervisor mode.
Table 8-24. GIER3_[0–5] Bit Descriptions
Name
Reset
Description
Settings
—
31–23
0
Reserved. Write to zero for future compatibility.
DDR2_ERR_EN_n
22
0
DDR2 Error Interrupt Enable
0
1
Interrupt enabled
DDR1_ERR_EN_n
21
0
DDR1 Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
MAPLE_ECC_DRAM_EN_n
20
0
MAPLE DRAM Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
MAPLE_ECC_IMEM_EN_n
19
0
MAPLE IMEM Error Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
Interrupt disabled
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-39
General Configuration Registers
Table 8-24. GIER3_[0–5] Bit Descriptions
Name
Reset
MAPLE_ECC_DFT_EN_n
18
0
MAPLE_ECC_FFT_EN_n
17
0
—
13–16
0
Reserved. Write to zero for future compatibility.
MAPLE_GEN_ERR_EN_n
12
0
MAPLE General Error Interrupt Enable
—
11–9
0
Reserved. Write to zero for future compatibility.
PM_EN_n
8
0
Performance Monitor Interrupt Enable
—
7–5
0
Reserved. Write to zero for future compatibility.
CLS0_ERR_EN_n
4
0
CLASS0 Error Interrupt Enable
—
3–2
0
Reserved. Write to zero for future compatibility.
CLS0_WP_EN_n
1
0
CLASS0 Watchpoint Interrupt Enable
CLS0_OV_EN_n
0
0
8.2.25
Settings
MAPLE FFT1 ECC Error Interrupt Enable
MAPLE FFT0 ECC Error Interrupt Enable
CLASS0 Overrun Interrupt Enable
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
0
Interrupt disabled
1
Interrupt enabled
General Interrupt Register 5 (GIR5)
GIR5
Bit
Description
General Interrupt Register 5
31
30
29
28
Offset 0xEC
27
26
25
24
—
W1C
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
W1C
Type
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
W1C
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
T4_T5_AE
T2_T3_AE
T0_T1_AE
0
0
0
—
Type
Reset
W1C
0
0
0
0
0
MSC8156 Reference Manual, Rev. 2
8-40
Freescale Semiconductor
Detailed Register Descriptions
GIR5 includes interrupt status of some internal events within MSC8156. Those bits are sticky
and cleared by writing a 1 to the bit. The GIR5 register is reset by a hard reset event. All bits are
cleared on reset. Write accesses to this register can only be performed in supervisor mode.
Table 8-25. GIR5 Bit Descriptions
Name
Reset
Description
—
31–3
0
Reserved. Write to zero for future compatibility.
T4_T5_AE
2
0
Core 4 or Core 5 L2/M2 Access Error Interrupt
Reflects L2/M2 Access Error Interrupt which occurs
when the referenced core is in Stop mode. One of
the cores tried to access core subsystem 4 or core
subsystem 5 M2/L2 memory.
T2_T3_AE
1
0
T0_T1_AE
0
0
Settings
0
Interrupt not asserted
1
Interrupt asserted
Core 2 or Core3 L2/M2 Access Error Interrupt
0
Reflects L2/M2 Access Error Interrupt which occurs 1
when the referenced core is in Stop mode.One of the
cores tried to access core subsystem 2 or core
subsystem 3 M2/L2 memory.
Core 0 or Core 1 L2/M2 Access Error Interrupt
0
Reflects L2/M2 Access Error Interrupt which occurs 1
when the referenced core is in Stop mode.One of the
cores tried to access core subsystem 0 or core
subsystem 1 M2/L2 memory.
Interrupt not asserted
Interrupt asserted
Interrupt not asserted
Interrupt asserted
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-41
General Configuration Registers
8.2.26
General Interrupt Enable Register 5 (GIER5_x)
GIER5_0
GIER5_1
GIER5_2
GIER5_3
GIER5_4
GIER5_5
Bit
General Interrupt Enable Register 5 for Cores 0–5
31
30
29
28
Offset 0xF0
Offset 0xF4
Offset 0xF8
Offset 0xFC
Offset 0x100
Offset 0x104
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
T4_T5_AE_EN T2_T3_AE_EN T0_T1_AE_EN
Type
Reset
R/W
0
0
0
0
0
0
0
0
GIER5_[0–5] include interrupt enable bits for cores 0–5 for interrupts defined by GIR5.
GIER5_[0–5] are reset by a hard reset event. All bits are cleared on reset. Write accesses to this
register can be performed only in supervisor mode.
Table 8-26. GIER5_[0–5] Bit Descriptions
Name
Reset
Description
Settings
—
31–3
0
Reserved. Write to zero for future compatibility.
T4_T5_AE_EN_n
2
0
Core 4 or Core 5 L2/M2 Access Error
Interrupt Enable
Enables/disable the interrupt.
0
Interrupt disabled
1
Interrupt enabled
T2_T3_AE_EN_n
1
0
Core 2 or Core 3 L2/M2 Access Error
Interrupt Enable
Enables/disable the interrupt.
0
Interrupt disabled
1
Interrupt enabled
T0_T1_AE_EN_n
0
0
Core 0 or Core 1 L2/M2 Access Error
Interrupt Enable
Enables/disable the interrupt.
0
Interrupt disabled
1
Interrupt enabled
MSC8156 Reference Manual, Rev. 2
8-42
Freescale Semiconductor
Detailed Register Descriptions
8.2.27
General Control Register 11 (GCR11)
GCR11
Bit
General Control Register 11
31
30
29
28
27
Offset 0x110
26
25
—
24
PERIPHER_
SYS_LATE_
ARBITARTION
Type
Reset
0
0
0
0
R/W
0
0
0
0
Bit
23
22
21
20
19
18
17
16
0
0
0
10
9
8
—
R/W
Type
Reset
0
0
Bit
15
14
0
0
0
13
12
11
—
PERIPHER_ SYS_INIT2_WEIGHT
Type
Reset
0
0
0
0
R/W
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PERIPHER_ SYS_INIT1_WEIGHT
Type
Reset
PERIPHER_ SYS_INIT0_WEIGHT
R/W
0
0
0
0
0
0
0
0
GCR11 controls the initial values for weighted and late arbitration operation of the peripheral
system. All bits are cleared on reset.
Table 8-27. GCR11 Bit Descriptions
Name
Reset
Description
—
31–25
PERIPHER_
SYS_LATE_
ARBITRATION
24
—
23–12
PERIPHER_
SYS_INIT2_
WEIGHT
11–8
PERIPHER_
SYS_INIT1_
WEIGHT
7–4
PERIPHER_
SYS_INIT0_
WEIGHT
3–0
0
Reserved. Write to zero for future compatibility.
0
Late Arbitration
Enables/disables late arbitration for the peripheral
system.
0
Reserved. Write to zero for future compatibility.
0
Initial TDM Arbitration Weight
Sets the initial weight given to TDM transactions for
peripheral system arbitration.
0
Initial QUICC Engine Module Arbitration Weight
Sets the initial weight given to the QUICC Engine
module for peripheral system arbitration.
0
Initial SEC Arbitration Weight
Sets the initial weight given to the SEC for
peripheral system arbitration.
Settings
0
Do not allow late arbitration.
1
Allow late arbitration.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-43
General Configuration Registers
8.2.28
General Control Register 12 (GCR12)
GCR12
Bit
General Control Register 12
31
30
29
28
Offset 0x114
27
26
25
24
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
Reset
0
0
0
0
Bit
15
14
13
12
HSSI_SYS_
LATE_
ARBITARTION
R/W
0
0
0
0
11
10
9
8
—
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
HSSI_SYS_INIT1_WEIGHT
Type
Reset
HSSI_SYS_INIT0_WEIGHT
R/W
0
0
0
0
0
0
0
0
GCR12 controls the initial values for weighted and late arbitration operation of the HSSI CLASS.
All bits are cleared on reset.
Table 8-28. GCR12 Bit Descriptions
Name
Reset
—
31–17
HSSI_SYS_
LATE_
ARBITRATION
16
—
15–8
0
Reserved. Write to zero for future compatibility.
0
Late Arbitration
Enables/disables late arbitration for the HSSI
system.
0
Description
Settings
0
Do not allow late arbitration.
1
Allow late arbitration.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
8-44
Freescale Semiconductor
Detailed Register Descriptions
Table 8-28. GCR12 Bit Descriptions (Continued)
Name
Reset
Description
HSSI_SYS_
INIT1_
WEIGHT
7–4
0
HSSI Internal Interface 1 Arbitration Weight
Sets the initial weight given to the internal interface
1 (MBus side) of the HSSI. The interface can have a
maximum weight of 16.
HSSI_SYS_
INIT0_
WEIGHT
3–0
0
HSSI Internal Interface 0 Arbitration Weight
Sets the initial weight given to the internal interface
0 (MBus side) of the HSSI. The interface can have a
maximum weight of 16.
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Weight = 1
Weight = 2
Weight = 3
Weight = 4
Weight = 5
Weight = 6
Weight = 7
Weight = 8
Weight = 9
Weight = 10
Weight = 11
Weight = 12
Weight = 13
Weight = 14
Weight = 15
Weight = 16
Weight = 1
Weight = 2
Weight = 3
Weight = 4
Weight = 5
Weight = 6
Weight = 7
Weight = 8
Weight = 9
Weight = 10
Weight = 11
Weight = 12
Weight = 13
Weight = 14
Weight = 15
Weight = 16
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-45
General Configuration Registers
8.2.29
DMA Request0 Control Register (GCR_DREQ0)
GCR_DREQ0
Bit
DMA Request0 Control Register
31
30
29
28
27
Offset 0x120
26
25
24
DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0
_D15
_S15
_D14
_S14
_D13
_S13
_D12
_S12
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0
_D11
_S11
_D10
_S10
_D9
_S9
_D8
_S8
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0
_D7
_S7
_D6
_S6
_D5
_S5
_D4
_S4
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0 DMA_DREQ0
_D3
_S3
_D2
_S2
_D1
_S1
_D0
_S0
Type
Reset
R/W
0
0
0
0
0
0
0
0
GCR_DREQ0 associates an external peripheral DMA request 0 to the DMA Controller channel
with its destination or source. The user must clear the corresponding bits for a channel for
memory-only transactions.
Table 8-29. GCR_DREQ0 Bit Descriptions
Name
Reset
DMA_DREQ0_
D15
31
0
DMA_DREQ0_
S15
30
0
DMA_DREQ0_
D14
29
0
Description
Settings
DMA DREQ0 Destination Channel 15
Associates the DREQ with the destination for
Channel 15.
0
DREQ not associated with
Channel 15 destination.
1
DREQ associated with
Channel 15 destination.
DMA DREQ0 Source Channel 15
Associates the DREQ with the source for Channel
15.
0
DREQ not associated with
Channel 15 source.
1
DREQ associated with
Channel 15 source.
DMA DREQ0 Destination Channel 14
Associates the DREQ with the destination for
Channel 14.
0
DREQ not associated with
Channel 14 destination.
1
DREQ associated with
Channel 14 destination.
MSC8156 Reference Manual, Rev. 2
8-46
Freescale Semiconductor
Detailed Register Descriptions
Table 8-29. GCR_DREQ0 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ0_
S14
28
0
DMA_DREQ0_
D13
27
0
DMA_DREQ0_
S13
26
0
DMA_DREQ0_
D12
25
0
DMA_DREQ0_
S12
24
0
DMA_DREQ0_
D11
23
0
DMA_DREQ0_
S11
22
0
DMA_DREQ0_
D10
21
0
DMA_DREQ0_
S10
20
0
DMA_DREQ0_
D9
19
0
DMA_DREQ0_
S9
18
0
Description
Settings
DMA DREQ0 Source Channel 14
Associates the DREQ with the source for Channel
14.
0
DREQ not associated with
Channel 14 source.
1
DREQ associated with
Channel 14 source.
DMA DREQ0 Destination Channel 13
Associates the DREQ with the destination for
Channel 13.
0
DREQ not associated with
Channel 13 destination.
1
DREQ associated with
Channel 13 destination.
DMA DREQ0 Source Channel 13
Associates the DREQ with the source for Channel
13.
0
DREQ not associated with
Channel 13 source.
1
DREQ associated with
Channel 13 source.
DMA DREQ0 Destination Channel 12
Associates the DREQ with the destination for
Channel 12.
0
DREQ not associated with
Channel 12 destination.
1
DREQ associated with
Channel 12 destination.
DMA DREQ0 Source Channel 12
Associates the DREQ with the source for Channel
12.
0
DREQ not associated with
Channel 12 source.
1
DREQ associated with
Channel 12 source.
DMA DREQ0 Destination Channel 11
Associates the DREQ with the destination for
Channel 11.
0
DREQ not associated with
Channel 11 destination.
1
DREQ associated with
Channel 11 destination.
DMA DREQ0 Source Channel 11
Associates the DREQ with the source for Channel
11.
0
DREQ not associated with
Channel 11 source.
1
DREQ associated with
Channel 11 source.
DMA DREQ0 Destination Channel 10
Associates the DREQ with the destination for
Channel 10.
0
DREQ not associated with
Channel 10 destination.
1
DREQ associated with
Channel 10 destination.
DMA DREQ0 Source Channel 10
Associates the DREQ with the source for Channel
10.
0
DREQ not associated with
Channel 10 source.
1
DREQ associated with
Channel 10 source.
DMA DREQ0 Destination Channel 9
Associates the DREQ with the destination for
Channel 9.
0
DREQ not associated with
Channel 9 destination.
1
DREQ associated with
Channel 9 destination.
DMA DREQ0 Source Channel 9
Associates the DREQ with the source for Channel
9.
0
DREQ not associated with
Channel 9 source.
1
DREQ associated with
Channel 9 source.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-47
General Configuration Registers
Table 8-29. GCR_DREQ0 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ0_
D8
17
0
DMA_DREQ0_
S8
16
0
DMA_DREQ0_
D7
15
0
DMA_DREQ0_
S7
14
0
DMA_DREQ0_
D6
13
0
DMA_DREQ0_
S6
12
0
DMA_DREQ0_
D5
11
0
DMA_DREQ0_
S5
10
0
DMA_DREQ0_
D4
9
0
DMA_DREQ0_
S4
8
0
DMA_DREQ0_
D3
7
0
Description
Settings
DMA DREQ0 Destination Channel 8
Associates the DREQ with the destination for
Channel 8.
0
DREQ not associated with
Channel 8 destination.
1
DREQ associated with
Channel 8 destination.
DMA DREQ0 Source Channel 8
Associates the DREQ with the source for Channel
8.
0
DREQ not associated with
Channel 8 source.
1
DREQ associated with
Channel 8 source.
DMA DREQ0 Destination Channel 7
Associates the DREQ with the destination for
Channel 7.
0
DREQ not associated with
Channel 7 destination.
1
DREQ associated with
Channel 7 destination.
DMA DREQ0 Source Channel 7
Associates the DREQ with the source for Channel
7.
0
DREQ not associated with
Channel 7 source.
1
DREQ associated with
Channel 7 source.
DMA DREQ0 Destination Channel 6
Associates the DREQ with the destination for
Channel 6.
0
DREQ not associated with
Channel 6 destination.
1
DREQ associated with
Channel 6 destination.
DMA DREQ0 Source Channel 6
Associates the DREQ with the source for Channel
6.
0
DREQ not associated with
Channel 6 source.
1
DREQ associated with
Channel 6 source.
DMA DREQ0 Destination Channel 5
Associates the DREQ with the destination for
Channel 5.
0
DREQ not associated with
Channel 5 destination.
1
DREQ associated with
Channel 5 destination.
DMA DREQ0 Source Channel 5
Associates the DREQ with the source for Channel
5.
0
DREQ not associated with
Channel 5 source.
1
DREQ associated with
Channel 5 source.
DMA DREQ0 Destination Channel 4
Associates the DREQ with the destination for
Channel 4.
0
DREQ not associated with
Channel 4 destination.
1
DREQ associated with
Channel 4 destination.
DMA DREQ0 Source Channel 4
Associates the DREQ with the source for Channel
4.
0
DREQ not associated with
Channel 4 source.
1
DREQ associated with
Channel 4 source.
DMA DREQ0 Destination Channel 3
Associates the DREQ with the destination for
Channel 3.
0
DREQ not associated with
Channel 3 destination.
1
DREQ associated with
Channel 3 destination.
MSC8156 Reference Manual, Rev. 2
8-48
Freescale Semiconductor
Detailed Register Descriptions
Table 8-29. GCR_DREQ0 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ0_
S3
6
0
DMA_DREQ0_
D2
5
0
DMA_DREQ0_
S2
4
0
DMA_DREQ0_
D1
3
0
DMA_DREQ0_
S1
2
0
DMA_DREQ0_
D0
1
0
DMA_DREQ0_
S0
0
0
Description
Settings
DMA DREQ0 Source Channel 3
Associates the DREQ with the source for Channel
3.
0
DREQ not associated with
Channel 3 source.
1
DREQ associated with
Channel 3 source.
DMA DREQ0 Destination Channel 2
Associates the DREQ with the destination for
Channel 2.
0
DREQ not associated with
Channel 2 destination.
1
DREQ associated with
Channel 2 destination.
DMA DREQ0 Source Channel 2
Associates the DREQ with the source for Channel
2.
0
DREQ not associated with
Channel 2 source.
1
DREQ associated with
Channel 2 source.
DMA DREQ0 Destination Channel 1
Associates the DREQ with the destination for
Channel 1.
0
DREQ not associated with
Channel 1 destination.
1
DREQ associated with
Channel 1 destination.
DMA DREQ0 Source Channel 1
Associates the DREQ with the source for Channel
1.
0
DREQ not associated with
Channel 1 source.
1
DREQ associated with
Channel 1 source.
DMA DREQ0 Destination Channel 0
Associates the DREQ with the destination for
Channel 0.
0
DREQ not associated with
Channel 0 destination.
1
DREQ associated with
Channel 0 destination.
DMA DREQ0 Source Channel 0
Associates the DREQ with the source for Channel
0.
0
DREQ not associated with
Channel 0 source.
1
DREQ associated with
Channel 0 source.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-49
General Configuration Registers
8.2.30
DMA Request1 Control Register (GCR_DREQ1)
GCR_DREQ1
Bit
DMA Request1 Control Register
31
30
29
28
27
Offset 0x124
26
25
24
DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1
_D15
_S15
_D14
_S14
_D13
_S13
_D12
_S12
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1
_D11
_S11
_D10
_S10
_D9
_S9
_D8
_S8
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1
_D7
_S7
_D6
_S6
_D5
_S5
_D4
_S4
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1 DMA_DREQ1
_D3
_S3
_D2
_S2
_D1
_S1
_D0
_S0
Type
Reset
R/W
0
0
0
0
0
0
0
0
GCR_DREQ1 associates an external peripheral DMA request 1 to the DMA Controller channel
with its destination or source. The user must clear the corresponding bits for a channel for
memory-only transactions.
Table 8-30. GCR_DREQ1 Bit Descriptions
Name
Reset
DMA_DREQ1_
D15
31
0
DMA_DREQ1_
S15
30
0
DMA_DREQ1_
D14
29
0
Description
Settings
DMA DREQ1 Destination Channel 15
Associates the DREQ with the destination for
Channel 15.
0
DREQ not associated with
Channel 15 destination.
1
DREQ associated with
Channel 15 destination.
DMA DREQ1 Source Channel 15
Associates the DREQ with the source for Channel
15.
0
DREQ not associated with
Channel 15 source.
1
DREQ associated with
Channel 15 source.
DMA DREQ1 Destination Channel 14
Associates the DREQ with the destination for
Channel 14.
0
DREQ not associated with
Channel 14 destination.
1
DREQ associated with
Channel 14 destination.
MSC8156 Reference Manual, Rev. 2
8-50
Freescale Semiconductor
Detailed Register Descriptions
Table 8-30. GCR_DREQ1 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ1_
S14
28
0
DMA_DREQ1_
D13
27
0
DMA_DREQ1_
S13
26
0
DMA_DREQ1_
D12
25
0
DMA_DREQ1_
S12
24
0
DMA_DREQ1_
D11
23
0
DMA_DREQ1_
S11
22
0
DMA_DREQ1_
D10
21
0
DMA_DREQ1_
S10
20
0
DMA_DREQ1_
D9
19
0
DMA_DREQ1_
S9
18
0
Description
Settings
DMA DREQ1 Source Channel 14
Associates the DREQ with the source for Channel
14.
0
DREQ not associated with
Channel 14 source.
1
DREQ associated with
Channel 14 source.
DMA DREQ1 Destination Channel 13
Associates the DREQ with the destination for
Channel 13.
0
DREQ not associated with
Channel 13 destination.
1
DREQ associated with
Channel 13 destination.
DMA DREQ1 Source Channel 13
Associates the DREQ with the source for Channel
13.
0
DREQ not associated with
Channel 13 source.
1
DREQ associated with
Channel 13 source.
DMA DREQ1 Destination Channel 12
Associates the DREQ with the destination for
Channel 12.
0
DREQ not associated with
Channel 12 destination.
1
DREQ associated with
Channel 12 destination.
DMA DREQ1 Source Channel 12
Associates the DREQ with the source for Channel
12.
0
DREQ not associated with
Channel 12 source.
1
DREQ associated with
Channel 12 source.
DMA DREQ1 Destination Channel 11
Associates the DREQ with the destination for
Channel 11.
0
DREQ not associated with
Channel 11 destination.
1
DREQ associated with
Channel 11 destination.
DMA DREQ1 Source Channel 11
Associates the DREQ with the source for Channel
11.
0
DREQ not associated with
Channel 11 source.
1
DREQ associated with
Channel 11 source.
DMA DREQ1 Destination Channel 10
Associates the DREQ with the destination for
Channel 10.
0
DREQ not associated with
Channel 10 destination.
1
DREQ associated with
Channel 10 destination.
DMA DREQ1 Source Channel 10
Associates the DREQ with the source for Channel
10.
0
DREQ not associated with
Channel 10 source.
1
DREQ associated with
Channel 10 source.
DMA DREQ1 Destination Channel 9
Associates the DREQ with the destination for
Channel 9.
0
DREQ not associated with
Channel 9 destination.
1
DREQ associated with
Channel 9 destination.
DMA DREQ1 Source Channel 9
Associates the DREQ with the source for Channel
9.
0
DREQ not associated with
Channel 9 source.
1
DREQ associated with
Channel 9 source.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-51
General Configuration Registers
Table 8-30. GCR_DREQ1 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ1_
D8
17
0
DMA_DREQ1_
S8
16
0
DMA_DREQ1_
D7
15
0
DMA_DREQ1_
S7
14
0
DMA_DREQ1_
D6
13
0
DMA_DREQ1_
S6
12
0
DMA_DREQ1_
D5
11
0
DMA_DREQ1_
S5
10
0
DMA_DREQ1_
D4
9
0
DMA_DREQ1_
S4
8
0
DMA_DREQ1_
D3
7
0
Description
Settings
DMA DREQ1 Destination Channel 8
Associates the DREQ with the destination for
Channel 8.
0
DREQ not associated with
Channel 8 destination.
1
DREQ associated with
Channel 8 destination.
DMA DREQ1 Source Channel 8
Associates the DREQ with the source for Channel
8.
0
DREQ not associated with
Channel 8 source.
1
DREQ associated with
Channel 8 source.
DMA DREQ1 Destination Channel 7
Associates the DREQ with the destination for
Channel 7.
0
DREQ not associated with
Channel 7 destination.
1
DREQ associated with
Channel 7 destination.
DMA DREQ1 Source Channel 7
Associates the DREQ with the source for Channel
7.
0
DREQ not associated with
Channel 7 source.
1
DREQ associated with
Channel 7 source.
DMA DREQ1 Destination Channel 6
Associates the DREQ with the destination for
Channel 6.
0
DREQ not associated with
Channel 6 destination.
1
DREQ associated with
Channel 6 destination.
DMA DREQ1 Source Channel 6
Associates the DREQ with the source for Channel
6.
0
DREQ not associated with
Channel 6 source.
1
DREQ associated with
Channel 6 source.
DMA DREQ1 Destination Channel 5
Associates the DREQ with the destination for
Channel 5.
0
DREQ not associated with
Channel 5 destination.
1
DREQ associated with
Channel 5 destination.
DMA DREQ1 Source Channel 5
Associates the DREQ with the source for Channel
5.
0
DREQ not associated with
Channel 5 source.
1
DREQ associated with
Channel 5 source.
DMA DREQ1 Destination Channel 4
Associates the DREQ with the destination for
Channel 4.
0
DREQ not associated with
Channel 4 destination.
1
DREQ associated with
Channel 4 destination.
DMA DREQ1 Source Channel 4
Associates the DREQ with the source for Channel
4.
0
DREQ not associated with
Channel 4 source.
1
DREQ associated with
Channel 4 source.
DMA DREQ1 Destination Channel 3
Associates the DREQ with the destination for
Channel 3.
0
DREQ not associated with
Channel 3 destination.
1
DREQ associated with
Channel 3 destination.
MSC8156 Reference Manual, Rev. 2
8-52
Freescale Semiconductor
Detailed Register Descriptions
Table 8-30. GCR_DREQ1 Bit Descriptions (Continued)
Name
Reset
DMA_DREQ1_
S3
6
0
DMA_DREQ1_
D2
5
0
DMA_DREQ1_
S2
4
0
DMA_DREQ1_
D1
3
0
DMA_DREQ1_
S1
2
0
DMA_DREQ1_
D0
1
0
DMA_DREQ1_
S0
0
0
Description
Settings
DMA DREQ1 Source Channel 3
Associates the DREQ with the source for Channel
3.
0
DREQ not associated with
Channel 3 source.
1
DREQ associated with
Channel 3 source.
DMA DREQ1 Destination Channel 2
Associates the DREQ with the destination for
Channel 2.
0
DREQ not associated with
Channel 2 destination.
1
DREQ associated with
Channel 2 destination.
DMA DREQ1 Source Channel 2
Associates the DREQ with the source for Channel
2.
0
DREQ not associated with
Channel 2 source.
1
DREQ associated with
Channel 2 source.
DMA DREQ1 Destination Channel 1
Associates the DREQ with the destination for
Channel 1.
0
DREQ not associated with
Channel 1 destination.
1
DREQ associated with
Channel 1 destination.
DMA DREQ1 Source Channel 1
Associates the DREQ with the source for Channel
1.
0
DREQ not associated with
Channel 1 source.
1
DREQ associated with
Channel 1 source.
DMA DREQ1 Destination Channel 0
Associates the DREQ with the destination for
Channel 0.
0
DREQ not associated with
Channel 0 destination.
1
DREQ associated with
Channel 0 destination.
DMA DREQ1 Source Channel 0
Associates the DREQ with the source for Channel
0.
0
DREQ not associated with
Channel 0 source.
1
DREQ associated with
Channel 0 source.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-53
General Configuration Registers
8.2.31
DMA Done Control Register (GCR_DDONE)
GCR_DDONE
Bit
DMA Done Control Register
31
30
29
28
Offset 0x128
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
V1
DONE1_CH
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0
0
—
V0
DONE0_CH
Type
R/W
Reset
0
0
0
0
0
0
GCR_DONE controls DMA external request DONE for requestor 1 and 2.
Table 8-31. GCR_DDONE Bit Descriptions
Name
Reset
Description
—
31–14
0
Reserved. Write to zero for future compatibility.
V1
13
0
Valid DONE1
Indicates whether the value of DONE1_CH is valid.
Settings
0
DONE1_CH is not valid.
1
DONE1_CH is valid.
MSC8156 Reference Manual, Rev. 2
8-54
Freescale Semiconductor
Detailed Register Descriptions
Table 8-31. GCR_DDONE Bit Descriptions (Continued)
Name
Reset
Description
DONE1_CH
12–8
0
DMA DONE1 Channel Select
Defines the unidirectional channel that drives the
DONE1 signal. The signal is valid when
GCR_DDONE[V1] is set.
—
7–6
0
Reserved. Write to zero for future compatibility.
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Channel 0 source.
Channel 0 destination.
Channel 1 source.
Channel 1 destination.
Channel 2 source.
Channel 2 destination.
Channel 3 source.
Channel 3 destination.
Channel 4 source.
Channel 4 destination.
Channel 5 source.
Channel 5 destination.
Channel 6 source.
Channel 6 destination.
Channel 7 source.
Channel 7 destination.
Channel 8 source.
Channel 8 destination.
Channel 9 source.
Channel 9 destination.
Channel 10 source.
Channel 10 destination.
Channel 11 source.
Channel 11 destination.
Channel 12 source.
Channel 12 destination.
Channel 13 source.
Channel 13 destination.
Channel 14 source.
Channel 14 destination.
Channel 15 source.
Channel 15 destination.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-55
General Configuration Registers
Table 8-31. GCR_DDONE Bit Descriptions (Continued)
Name
Reset
Description
Settings
V0
5
0
Valid DONE0
Indicates whether the value of DONE0_CH is valid.
0
DONE0_CH is not valid.
1
DONE0_CH is valid.
DONE0_CH
4–0
0
DMA DONE0 Channel Select
Defines the unidirectional channel that drives the
DONE0 signal. The signal is valid when
GCR_DDONE[V0] is set.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Channel 0 source.
Channel 0 destination.
Channel 1 source.
Channel 1 destination.
Channel 2 source.
Channel 2 destination.
Channel 3 source.
Channel 3 destination.
Channel 4 source.
Channel 4 destination.
Channel 5 source.
Channel 5 destination.
Channel 6 source.
Channel 6 destination.
Channel 7 source.
Channel 7 destination.
Channel 8 source.
Channel 8 destination.
Channel 9 source.
Channel 9 destination.
Channel 10 source.
Channel 10 destination.
Channel 11 source.
Channel 11 destination.
Channel 12 source.
Channel 12 destination.
Channel 13 source.
Channel 13 destination.
Channel 14 source.
Channel 14 destination.
Channel 15 source.
Channel 15 destination.
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Detailed Register Descriptions
8.2.32
DDR1 General Configuration Register (DDR1_GCR)
DDR1_GCR
Bit
DDR1 General Configuration Register
31
30
29
28
Offset 0x12C
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
DDR1_STOP DDR1_DOZE DDR1_PWR_
DOWN
Type
R/W
Reset
0
0
0
0
0
0
0
0
DDR1_GCR controls part of the DDR1 operation. All bits are cleared on a hard reset event.
Table 8-32. DDR1_GCR Bit Descriptions
Name
Reset
Description
Settings
—
31–3
0
Reserved. Write to zero for future compatibility.
DDR1_STOP
2
0
DDR1 Stop
With the DDRC Stop ACK, actively stops the controller and
DDR memory clock. If the memory is not put in self-refresh
mode prior to activating Stop mode, data is lost.
0
DDR1 Stop not requested.
1
DDR1 Stop requested.
DDR1_DOZE
1
0
DDR1 Doze
Used to select Doze mode, in which all register accesses are
acknowledged, but writes are not written and reads do not
contain valid data. Setting this bit prevents lockup of the
device internal bus while the DDR controller 1 is stopped.
Note: To conserve power, when DDR1 is not used by an
application, set this bit as soon as possible after
reset. This step should be included as part of the
initialization code.
0
Normal operation.
1
Doze mode.
DDR1_
POWER_
DOWN
0
0
DDR1 Power Down
When set, powers down all DDR1 areas with gated clocks.
0
DDR1 power up.
1
DDR1 power down.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-57
General Configuration Registers
8.2.33
DDR2 General Configuration Register (DDR2_GCR)
DDR2_GCR
Bit
DDR2 General Configuration Register
31
30
29
28
Offset 0x130
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
DDR2_STOP DDR2_DOZE DDR2_PWR_
DOWN
Type
R/W
Reset
0
0
0
0
0
0
0
0
DDR2_GCR controls part of the DDR2 operation. All bits are cleared on a hard reset event.
Table 8-33. DDR2_GCR Bit Descriptions
Name
Reset
Description
Settings
—
31–3
0
Reserved. Write to zero for future compatibility.
DDR2_STOP
2
0
DDR2 Stop
With the DDRC Stop ACK, actively stops the controller and
DDR memory clock. If the memory is not put in self-refresh
mode prior to activating Stop mode, data is lost.
0
DDR2 Stop not requested.
1
DDR2 Stop requested.
DDR2_DOZE
1
0
DDR2 Doze
Used to select Doze mode, in which all register accesses are
acknowledged, but writes are not written and reads do not
contain valid data. Setting this bit prevents lockup of the
device internal bus while the DDR2 controller is stopped.
Note: To conserve power, when DDR2 is not used by an
application, set this bit as soon as possible after
reset. This step should be included as part of the
initialization code.
0
Normal operation.
1
Doze mode.
DDR2_
POWER_
DOWN
0
0
DDR2 Power Down
When set, powers down all DDR2 areas with gated clocks.
0
DDR2 power up.
1
DDR2 power down.
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
Detailed Register Descriptions
8.2.34
Core Subsystem Slave Port General Configuration Register
(CORE_SLV_GCR)
CORE_SLV_GCRCore Subsystem Slave Port General Configuration Register
Bit
31
30
29
28
Offset 0x138
27
26
25
24
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
—
Type
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
—
CORE_SLV_ CORE_SLV_ CORE_SLV_ CORE_SLV_ CORE_SLV_ CORE_SLV_
WIN_CLOSE5 WIN_CLOSE4 WIN_CLOSE3 WIN_CLOSE2 WIN_CLOSE1 WIN_CLOSE0
Type
R/W
Reset
0
0
0
0
0
0
0
0
CORE_SLV_GCR controls the status of the slave ports for the core subsystems.
Table 8-34. CORE_SLV_GCR Bit Descriptions
Name
Reset
Description
Settings
—
31–6
0
Reserved. Write to zero for future compatibility.
CORE_SLV_
WIN_CLOSE5
5
0
Peripheral Access to Core 5 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 5.
0
Enable peripheral access to
Core 5 M2/L2 memory.
1
Disable peripheral access to
Core 5 M2/L2 memory.
CORE_SLV_
WIN_CLOSE4
4
0
Peripheral Access to Core 4 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 4.
0
Enable peripheral access to
Core 4 M2/L2 memory.
1
Disable peripheral access to
Core 4 M2/L2 memory.
CORE_SLV_
WIN_CLOSE3
3
0
Peripheral Access to Core 3 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 3.
0
Enable peripheral access to
Core 3 M2/L2 memory.
1
Disable peripheral access to
Core 3 M2/L2 memory.
CORE_SLV_
WIN_CLOSE2
2
0
Peripheral Access to Core 2 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 2.
0
Enable peripheral access to
Core 2 M2/L2 memory.
1
Disable peripheral access to
Core 2 M2/L2 memory.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
8-59
General Configuration Registers
Table 8-34. CORE_SLV_GCR Bit Descriptions (Continued)
Name
Reset
Description
Settings
CORE_SLV_
WIN_CLOSE1
1
0
Peripheral Access to Core 1 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 1.
0
Enable peripheral access to
Core 15 M2/L2 memory.
1
Disable peripheral access to
Core 1 M2/L2 memory.
CORE_SLV_
WIN_CLOSE0
0
0
Peripheral Access to Core 0 L2/M2 Disable
Set the bit to 1 to disable accesses by the device
peripherals (that is, DMAC, QUICC Engine module,
and so on) to M2/L2 in core 0.
0
Enable peripheral access to
Core 0 M2/L2 memory.
1
Disable peripheral access to
Core 0 M2/L2 memory.
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9
Memory Map
This section describes the memory map of MSC8156.
The MSC8156 incorporates four address groups:
„ Shared memory (M3, DDR, QUICC Engine subsystem, and MAPLE-B) address space.
„ Shared SC3850 DSP core subsystem M2/L2 memories
„ SC3850 DSP core subsystem internal address space is accessible only by the SC3850
core. Each SC3850 core can access its own internal address space.
„ Control Configuration and Status Registers (CCSR) address space.
9.1 Shared Memory Address Space
The shared memory address space resides within addresses 0x40000000–0xFEFFFFFF. It
includes the M3 memory, two DDR memories, MAPLE-B, QUICC Engine subsystem, and the
boot ROM.
Note:
The CCSR address space is not part of the shared memory space because the SC3850
DSP core subsystem internal memory resides in the middle (the CCSR address space
starts at address 0xFFF10000).
Table 9-1. Shared Memory Address Space
Address
Purpose
Size in Bytes
0x40000000–0x5FFFFFFF
DDR1 Memory (default value)
512 M
0x60000000–0x7FFFFFFF
Reserved; used for DDR1 memory if configured for 1 GB.
512 M
0x80000000–0x9FFFFFFF
DDR2 Memory (default value)
512 M
0xA0000000–0xBFFFFFFF
Reserved; used for DDR2 memory if configured for 1 GB
512 M
0xC0000000–0xC0107FFF
M3 Memory
0xC0108000–0xFECFFFFF
Reserved
511 M – 32 K
0xFED00000–0xFEDFFFFF
MAPLE-B
1M
0xFEE00000–0xFEE3FFFF
QUICC Engine Subsystem
256 K
0xFEE40000–0xFEEFFFFF
Reserved (QUICC Engine Subsystem)
768 K
0xFEF00000–0xFEF17FFF
Boot ROM
96 K
0xFEF18000–0xFEFFFFFF
Reserved
928 K
1 M + 32 K
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-1
Memory Map
9.2 Shared SC3850 DSP Core Subsystem M2/L2 Memories
Each SC3850 core subsystem includes 512 KB of level-2 memory that can be partitioned into M2
memory and L2 cache. The minimal size of each partition is 64 KB and each core can have a
unique combination of M2 and L2 memory partitions. The partition size can be changed during
operation, but the user must make sure that all ongoing accesses are terminated before making the
change. The default partitioning out of reset defines all of the level-2 memory as shared M2
memory. The boot program configures the MMU to support that configuration and sets the
CLASS values accordingly.
When partitioned as M2 memory, the memory is available as a shared memory that can be used
as private memory by the core to which it belongs and accessed by all other system masters and
external hosts, but not by the other cores. Although the M2 memories have different physical
addresses, all cores use a virtual address of 0x0 to access its own M2 memory and uses MMU
translation to access the correct memory space.
When partitioned as L2 cache memory, the L2 cache can be accessed by the core to which it
belongs and by other masters in the system, but not by other cores. The L2 accesses are translated
through the core subsystem slave ports to the L2 cache, allowing DDR access for specific core
cache. The size in bytes shown in Table 9-2 indicates the total DDR access range.
The shared M2/L2 memory space resides within the address range 0x20000000–0x3FFFFFFF
and includes all cores.
As shown at the Table 9-2, when an initiator other than the core accesses L2 cache, its address
range is limited to 32 MB. Before hitting the cache, this address range is always mapped to the
first 32 MB of DDR0 which uses the address range 0x40000000–0x41FFFFFF. The mapping is
the same for all DSP subsystems. If L2 acts as a shared cache by the core and the additional
initiators, this feature has the following benefits:
„ In the DMA model in which the DMA controller transfers data to L2 cache and the core
can use it, the scheduling restriction between DMA job completion and core job start is
relaxed (in comparison to DMA and M2). If the core starts reading data not written by the
DMA controller, a miss is generated to the DDR and data is read directly.
„ If an initiator must read the same data from DDR several times to save DDR bandwidth,
the data resides in L2 after the first read and is than read from L2 repeatedly without
having to access the DDR memory.
„ This feature can be used in conjunction with cache partitioning in which the cache can be
used as two separate caches, one for the core and the other for another initiator.
Table 9-2. Shared M2/L2 Memories Address Space
Address
0x20000000–0x23FFFFFF
0x24000000–0x25FFFFFF
Purpose
Reserved
DDR through Core 5 L2
Size in Bytes
64 M
32 M
MSC8156 Reference Manual, Rev. 2
9-2
Freescale Semiconductor
SC3850 DSP Core Subsystem Internal Address Space
Table 9-2. Shared M2/L2 Memories Address Space (Continued)
Address
Purpose
Size in Bytes
0x26000000–0x27FFFFFF
DDR through Core 4 L2
32 M
0x28000000–0x29FFFFFF
DDR through Core 3 L2
32 M
0x2A000000–0x2BFFFFFF
DDR through Core 2 L2
32 M
0x2C000000–0x2DFFFFFF
DDR through Core 1 L2
32 M
0x2E000000–0x2FFFFFFF
DDR through Core 0 L2
32 M
0x30000000–0x3007FFFF
Core 0 M2 memory
512 K max.
0x30080000–0x30FFFFFF
Reserved
16 M – 512 K
0x31000000–0x3107FFFF
Core 1 M2 memory
512 K max.
0x31080000–0x31FFFFFF
Reserved
16 M – 512 K
0x32000000–0x3207FFFF
Core 2 M2 memory
512 K max.
0x32080000–0x32FFFFFF
Reserved
16 M – 512 K
0x33000000–0x3307FFFF
Core 3 M2 memory
512 K max.
0x33080000–0x33FFFFFF
Reserved
16 M – 512 K
0x34000000–0x3407FFFF
Core 4 M2 memory
512 K max.
0x34080000–0x34FFFFFF
Reserved
16 M – 512 K
0x35000000–0x3507FFFF
Core 5 M2 memory
512 K max.
0x35080000–0x37FFFFFF
Reserved
48 M – 512 K
Note: Each of the M2 memory areas is configurable in size in 64 KB increments starting from the lowest 64 KB address
block up to the maximum 512 KB. Any blocks not allocated as M2 memory are reserved.
9.3 SC3850 DSP Core Subsystem Internal Address Space
Each SC3850 core can access the internal address space of its DSP core subsystem. The SC3850
internal address space is located from address 0xFF000000–0xFFF0FFFF (15 MB + 64 KB).
Table 9-3 lists details for the DSP core subsystem internal address space.
Table 9-3. SC3850 DSP Core Subsystem Internal Address Space
Address
Purpose
Size (Bytes)
Remarks
0xFF000000–0xFFEFFDFF
Reserved
15 M – 512
0xFFEFFE00–0xFFEFFFFF
OCE
512
User/Supervisor
Reserved
1K
0xFFF000002–0xFFF003FF
0xFFF00400–0xFFF007FF
EPIC
1K
Supervisor
0xFFF00800–0xFFF00BFF
Data Cache registers
1K
Supervisor
0xFFF00C00–0xFFF00FFF
Instruction Cache registers
1K
Supervisor
0xFFF01000–0xFFF05FFF
Reserved
20 K
0xFFF06000–0xFFF09FFF
MMU
16 K
Supervisor
0xFFF0A000–0xFFF0A2FF
DPU
768
User/Supervisor
0xFFF0A300–0xFFF0A3FF
TIMERS
256
User/Supervisor
0xFFF0A400–0xFFF0FFFF
Reserved
23 K
Note: Access in both User and Supervisor modes is allowed only if enabled via the EMR[EMEA] bit in the core.
Note:
See the MSC8156 SC3850 DSP Subsystem Reference Manual for details.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-3
Memory Map
9.4 CCSR Address Space
The MSC8156 CCSR is mapped within a contiguous block of memory. The size of the CCSR in
MSC8156 is 956 KB. Table 9-4 details the CCSR address space.
Table 9-4. CCSR Address Space
Address
0xFFF10000–0xFFF103FF
0xFFF10400–0xFFF17FFF
0xFFF18000–0xFFF18FFF
0xFFF19000–0xFFF1BFFF
0xFFF1C000–0xFFF1FFFF
0xFFF20000–0xFFF21FFF
0xFFF22000–0xFFF23FFF
0xFFF24000–0xFFF2407F
0xFFF24080–0xFFF247FF
0xFFF24800–0xFFF248FF
0xFFF24900–0xFFF24BFF
0xFFF24C00–0xFFF24CFF
0xFFF24D00–0xFFF24FFF
0xFFF25000–0xFFF250FF
0xFFF25100–0xFFF251FF
0xFFF25200–0xFFF252FF
0xFFF25300–0xFFF253FF
0xFFF25400–0xFFF254FF
0xFFF25500–0xFFF255FF
0xFFF25600–0xFFF256FF
0xFFF25700–0xFFF257FF
0xFFF25800–0xFFF25FFF
0xFFF26000–0xFFF260FF
0xFFF26100–0xFFF261FF
0xFFF26200–0xFFF262FF
0xFFF26300–0xFFF263FF
0xFFF26400–0xFFF26BFF
0xFFF26C00–0xFFF26C3F
0xFFF26C40–0xFFF26FFF
0xFFF27000–0xFFF270FF
0xFFF27100–0xFFF271FF
0xFFF27200–0xFFF272FF
0xFFF27300–0xFFF27FFF
0xFFF28000–0xFFF281FF
0xFFF28200–0xFFF2FFFF
0xFFF30000–0xFFF33FFF
0xFFF34000–0xFFF37FFF
0xFFF38000–0xFFF3BFFF
0xFFF3C000–0xFFF3FFFF
0xFFF40000–0xFFF7FFFF
0xFFF80000–0xFFF9FFFF
0xFFFA0000–0xFFFA0FFF
0xFFFA1000–0xFFFA103F
Purpose
DMA
Reserved
CLASS Registers
Reserved
MAPLE-B Registers
DDR Controller 1
DDR Controller 2
Clock
reserved
Reset
reserved
I2C
reserved
Watch Dog Timers
reserved
Timers
Reserved
UART
Reserved
GIC Registers
Hardware Semaphores
GPIO Registers
Reserved
General Configuration Registers
Reserved
TDM0 Registers
TDM1 Registers
TDM2 Registers
TDM3 Registers
Reserved
RapidIO Registers
Reserved
OCN Crossbar Switch to MBus0
Size (Bytes)
1K
31 K
4K
12 K
16 K
8K
8K
128
2 K – 128
256
768
256
768
256
256
256
256
256
256
256
256
2K
256
256
256
256
2K
64
1K – 64
256
256
256
4 K – 768
512
16 K – 32
16 K
16 K
16 K
16 K
256 K
128 K
4K
64
MSC8156 Reference Manual, Rev. 2
9-4
Freescale Semiconductor
Initiators Views of the System Address Space
Table 9-4. CCSR Address Space (Continued)
Address
0xFFFA1040–0xFFFA107F
0xFFFA1080–0xFFFA7FFF
0xFFFA8000–0xFFFA8FFF
0xFFFA9000–0xFFFA9FFF
0xFFFAA000–0xFFFAAFFF
0xFFFAB000–0xFFFABFFF
0xFFFAC000–0xFFFAC07F
0xFFFAC080–0xFFFACFFF
0xFFFAD000–0xFFFAD07F
0xFFFAD080–0xFFFB6FFF
0xFFFB7000–0xFFFB7FFF
0xFFFB8000–0xFFFBAFFF
0xFFFBB000–0xFFFBB7FF
0xFFFBB800–0xFFFBB8FF
0xFFFBB900–0xFFFCFFFF
0xFFFD0000–0xFFFDFFFF
0xFFFDE000–0xFFFFEFFF
Purpose
OCN Crossbar Switch to MBus1
Reserved
Dedicated DMA Controller 0 Registers
DMA Controller 0 to OCN
Dedicated DMA Controller 1 Registers
DMA Controller 1 to OCN
SerDes PHY 0 Registers
Reserved
SerDes PHY 1 Registers
Reserved
PCI Express Registers
Reserved
RapidIO/PCI Express Security Bridge Registers
Performance Monitor Registers
Reserved
Security Engine Registers
Reserved
Size (Bytes)
64
28 K – 128
4K
4K
4K
4K
128
4 K – 128
128
40 K – 128
4K
12 K
2K
256
82 K – 256
64 K
128 K
9.5 Initiators Views of the System Address Space
Addressing within the system address space depends on the device addressing the system
memory space. The following sections define how the cores, system peripherals, and the Security
Engine address this space.
9.5.1 SC3850 (Data) View of the System Address Space
Table 9-5 describes the system address space as seen by each SC3850 core subsystem.
Table 9-5. SC3850 (Data) View of the System Address Space
Address
Purpose
Size (Bytes)
0x00000000–0x2FFFFFFF
Reserved
768 M
The allocation of the memory space from 0x30000000–0x3FFFFFFF is core subsystem dependent as follows:
0x30000000–0x3007FFFF
Private M2 memory (size is configurable)
512 K maximum
Core 0
0x30080000–0x3FFFFFFF
Reserved
256 M – 512 K
0x30000000–0x30FFFFFF
Reserved
16 M
Core 1
0x31000000–0x3107FFFF
Private M2 memory (size is configurable)
512 K maximum
0x31080000–0x3FFFFFFF
Reserved
240 M – 512 K
0x30000000–0x31FFFFFF
Reserved
32 M
Core 2
0x32000000–0x3207FFFF
Private M2 memory (size is configurable)
512 K maximum
0x32080000–0x3FFFFFFF
Reserved
224 M – 512 K
0x30000000–0x32FFFFFF
Reserved
48 M
Core 3
0x33000000–0x3307FFFF
Private M2 memory (size is configurable)
512 K maximum
0x33080000–0x3FFFFFFF
Reserved
208 M – 512 K
0x30000000–0x33FFFFFF
Reserved
64 M
Core 4
0x34000000–0x3407FFFF
Private M2 memory (size is configurable)
512 K maximum
0x34080000–0x3FFFFFFF
Reserved
192 M – 512 K
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-5
Memory Map
Table 9-5. SC3850 (Data) View of the System Address Space
Address
Purpose
Size (Bytes)
0x30000000–0x34FFFFFF
Reserved
80 M
0x35000000–0x3507FFFF
Private M2 memory (size is configurable)
512 K maximum
0x35080000–0x3FFFFFFF
Reserved
176 M – 512 K
Note: Each core subsystem L2 memory can be allocated in 64 KB increments starting from the lowest 64 KB address
block up to the maximum 512 KB. Any blocks not allocated as M2 memory are reserved.
0x40000000–0xFEFFFFFF
Shared Memory Address Space
3 G – 528 M
0xFF000000–0xFFF0FFFF
SC3850 DSP core subsystem Internal Address Space
15 M + 64 K
0xFFF10000–0xFFFFEFFF
CCSR Address Space
956 K
0xFFFFF000–0xFFFFFFFF
Reserved
4K
Core 5
9.5.2 Peripherals View of the System Address Space
Table 9-6 describes the system address space as seen by the MSC8156 peripherals (RapidIO and
PCI Express controllers, JTAG, QUICC Engine subsystem, TDM, DMA, and MAPLE-B–both
MBus interfaces).
Table 9-6. Peripherals View of the System Address Space
Address
Purpose
Size (Bytes)
0x00000000–0x1FFFFFFF
Reserved
512 M
0x20000000–0x3FFFFFFF
Shared L2/M2 Memory Space
512 M
0x40000000–0xFEFFFFFF
Shared Memory Address Space
0xFF000000–0xFFF0FFFF
Reserved
0xFFF10000–0xFFFFEFFF
CCSR Address Space
0xFFFFF000–0xFFFFFFFF
Reserved
3 G – 528 M
15M + 64K
956 K
4K
An external initiator (to the MSC8156 device) can generate accesses to the system address space
using the:
„ Test Access Port/JTAG with direct addressing.
„ The RapidIO subsystem/PCI Express controller using the RapidIO/PCI Express inbound
address translation.
9.6 Detailed System Memory Map
Table 9-7. Detailed System Memory Map
Address
Name/Status
0x00000000–
0x3FFFFFFF
Reserved
0x40000000–
0xFEFFFFFF
Shared memory
• 0x40000000–
0x5FFFFFFF
DDR1 memory
Acronym
MSC8156 Reference Manual, Rev. 2
9-6
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
• 0x60000000–
0x7FFFFFFF
reserved
• 0x80000000–
0x9FFFFFFF
DDR2 Memory
• 0xA0000000–
0xBFFFFFFF
reserved
• 0xC0000000–
0xC010FFFF
M3 Memory
• 0xC0108000–
0xFECFFFFF
reserved
• 0xFED00000–
0xFEDFFFFF
MAPLE-B
Acronym
− 0xFED00000–
0xFED005FF
Parameter RAM
− 0xFED00000–
0xFED00003
reserved
− 0xFED00004–
0xFED00007
MAPLE BD Rings Configuration Parameter
− 0xFED00008–
0xFED0000F
reserved
− 0xFED00010
MAPLE UCode Version Number
− 0xFED00014–
0xFED00017
reserved
− 0xFED00018
MAPLE Timer Period Parameter
− 0xFED0001C–
0xFED0007F
reserved
− 0xFED00080–
0xFED00083
MAPLE TVPE BD Ring High Priority A 0 Parameter
MTVBRHPA0P
− 0xFED00084–
0xFED00087
MAPLE TVPE BD Ring High Priority B 0 Parameter
MTVBRHPB0P
− 0xFED00088–
0xFED0008B
MAPLE TVPE BD Ring High Priority A 1 Parameter
MTVBRHPA1P
− 0xFED0008C–
0xFED0008F
MAPLE TVPE BD Ring High Priority B 1 Parameter
MTVBRHPB1P
− 0xFED00090–
0xFED00093
MAPLE TVPE BD Ring High Priority A 2 Parameter
MTVBRHPA2P
− 0xFED00094–
0xFED00097
MAPLE TVPE BD Ring High Priority B 2 Parameter
MTVBRHPB2P
− 0xFED00098–
0xFED0009B
MAPLE TVPE BD Ring High Priority A 3 Parameter
MTVBRHPA3P
− 0xFED0009C–
0xFED0009F
MAPLE TVPE BD Ring High Priority B 3 Parameter
MTVBRHPB3P
− 0xFED000A0–
0xFED000A3
MAPLE TVPE BD Ring High Priority A 4 Parameter
MTVBRHPA4P
− 0xFED000A4–
0xFED000A7
MAPLE TVPE BD Ring High Priority B 4 Parameter
MTVBRHPB4P
− 0xFED000A8–
0xFED000AB
MAPLE TVPE BD Ring High Priority A 5 Parameter
MTVBRHPA5P
MBDRCP
MUCVP
MP_TPP
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-7
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED000AC–
0xFED000AF
MAPLE TVPE BD Ring High Priority B 5 Parameter
MTVBRHPB5P
− 0xFED000B0–
0xFED000B3
MAPLE TVPE BD Ring High Priority A 6 Parameter
MTVBRHPA6P
− 0xFED000B4–
0xFED000B7
MAPLE TVPE BD Ring High Priority B 6 Parameter
MTVBRHPB6P
− 0xFED000B8–
0xFED000BB
MAPLE TVPE BD Ring High Priority A 7 Parameter
MTVBRHPA7P
− 0xFED000BC–
0xFED000BF
MAPLE TVPE BD Ring High Priority B 7 Parameter
MTVBRHPB7P
− 0xFED000C0–
0xFED000C3
MAPLE TVPE BD Ring Low Priority A 0 Parameter
MTVBRLPA0P
− 0xFED000C4–
0xFED000C7
MAPLE TVPE BD Ring Low Priority B 0 Parameter
MTVBRLPB0P
− 0xFED000C8–
0xFED000CB
MAPLE TVPE BD Ring Low Priority A 1 Parameter
MTVBRLPA1P
− 0xFED000CC–
0xFED000CF
MAPLE TVPE BD Ring Low Priority B 1 Parameter
MTVBRLPB1P
− 0xFED000D0–
0xFED000D3
MAPLE TVPE BD Ring Low Priority A 2 Parameter
MTVBRLPA2P
− 0xFED000D4–
0xFED000D7
MAPLE TVPE BD Ring Low Priority B 2 Parameter
MTVBRLPB2P
− 0xFED000D8–
0xFED000DB
MAPLE TVPE BD Ring Low Priority A 3 Parameter
MTVBRLPA3P
− 0xFED000DC–
0xFED000DF
MAPLE TVPE BD Ring Low Priority B 3 Parameter
MTVBRLPB3P
− 0xFED000E0–
0xFED000E3
MAPLE TVPE BD Ring Low Priority A 4 Parameter
MTVBRLPA4P
− 0xFED000E4–
0xFED000E7
MAPLE TVPE BD Ring Low Priority B 4 Parameter
MTVBRLPB4P
− 0xFED000E8–
0xFED000EB
MAPLE TVPE BD Ring Low Priority A 5 Parameter
MTVBRLPA5P
− 0xFED000EC–
0xFED000EF
MAPLE TVPE BD Ring Low Priority B 5 Parameter
MTVBRLPB5P
− 0xFED000F0–
0xFED000F3
MAPLE TVPE BD Ring Low Priority A 6 Parameter
MTVBRLPA6P
− 0xFED000F4–
0xFED000F7
MAPLE TVPE BD Ring Low Priority B 6 Parameter
MTVBRLPB6P
− 0xFED000F8–
0xFED000FB
MAPLE TVPE BD Ring Low Priority A 7 Parameter
MTVBRLPA7P
− 0xFED000FC–
0xFED000FF
MAPLE TVPE BD Ring Low Priority B 7 Parameter
MTVBRLPB7P
− 0xFED00100–
0xFED00103
MAPLE FFTPE BD Ring High Priority A 0 Parameter
MFFBRHPA0P
− 0xFED00104–
0xFED00107
MAPLE FFTPE BD Ring High Priority B 0 Parameter
MFFBRHPB0P
− 0xFED00108–
0xFED0010B
MAPLE FFTPE BD Ring High Priority A 1 Parameter
MFFBRHPA1P
MSC8156 Reference Manual, Rev. 2
9-8
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED0010C–
0xFED0010F
MAPLE FFTPE BD Ring High Priority B 1 Parameter
MFFBRHPB1P
− 0xFED00110–
0xFED00113
MAPLE FFTPE BD Ring High Priority A 2 Parameter
MFFBRHPA2P
− 0xFED00114–
0xFED00117
MAPLE FFTPE BD Ring High Priority B 2 Parameter
MFFBRHPB2P
− 0xFED00118–
0xFED0011B
MAPLE FFTPE BD Ring High Priority A 3 Parameter
MFFBRHPA3P
− 0xFED0011C–
0xFED0011F
MAPLE FFTPE BD Ring High Priority B 3 Parameter
MFFBRHPB3P
− 0xFED00120–
0xFED00123
MAPLE FFTPE BD Ring High Priority A 4 Parameter
MFFBRHPA4P
− 0xFED00124–
0xFED00127
MAPLE FFTPE BD Ring High Priority B 4 Parameter
MFFBRHPB4P
− 0xFED00128–
0xFED0012B
MAPLE FFTPE BD Ring High Priority A 5 Parameter
MFFBRHPA5P
− 0xFED0012C–
0xFED0012F
MAPLE FFTPE BD Ring High Priority B 5 Parameter
MFFBRHPB5P
− 0xFED00130–
0xFED00133
MAPLE FFTPE BD Ring High Priority A 6 Parameter
MFFBRHPA6P
− 0xFED00134–
0xFED00137
MAPLE FFTPE BD Ring High Priority B 6 Parameter
MFFBRHPB6P
− 0xFED00138–
0xFED0013B
MAPLE FFTPE BD Ring High Priority A 7 Parameter
MFFBRHPA7P
− 0xFED0013C–
0xFED0013F
MAPLE FFTPE BD Ring High Priority B 7 Parameter
MFFBRHPB7P
− 0xFED00140–
0xFED00143
MAPLE FFTPE BD Ring Low Priority A 0 Parameter
MFFBRLPA0P
− 0xFED00144–
0xFED00147
MAPLE FFTPE BD Ring Low Priority B 0 Parameter
MFFBRLPB0P
− 0xFED00148–
0xFED0014B
MAPLE FFTPE BD Ring Low Priority A 1 Parameter
MFFBRLPA1P
− 0xFED0014C–
0xFED0014F
MAPLE FFTPE BD Ring Low Priority B 1 Parameter
MFFBRLPB1P
− 0xFED00150–
0xFED00153
MAPLE FFTPE BD Ring Low Priority A 2 Parameter
MFFBRLPA2P
− 0xFED00154–
0xFED00157
MAPLE FFTPE BD Ring Low Priority B 2 Parameter
MFFBRLPB2P
− 0xFED00158–
0xFED0015B
MAPLE FFTPE BD Ring Low Priority A 3 Parameter
MFFBRLPA3P
− 0xFED0015C–
0xFED0015F
MAPLE FFTPE BD Ring Low Priority B 3 Parameter
MFFBRLPB3P
− 0xFED00160–
0xFED00163
MAPLE FFTPE BD Ring Low Priority A 4 Parameter
MFFBRLPA4P
− 0xFED00164–
0xFED00167
MAPLE FFTPE BD Ring Low Priority B 4 Parameter
MFFBRLPB4P
− 0xFED00168–
0xFED0016B
MAPLE FFTPE BD Ring Low Priority A 5 Parameter
MFFBRLPA5P
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-9
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED0016C–
0xFED0016F
MAPLE FFTPE BD Ring Low Priority B 5 Parameter
MFFBRLPB5P
− 0xFED00170–
0xFED00173
MAPLE FFTPE BD Ring Low Priority A 6 Parameter
MFFBRLPA6P
− 0xFED00174–
0xFED00177
MAPLE FFTPE BD Ring Low Priority B 6 Parameter
MFFBRLPB6P
− 0xFED00178–
0xFED0017B
MAPLE FFTPE BD Ring Low Priority A 7 Parameter
MFFBRLPA7P
− 0xFED0017C–
0xFED0017F
MAPLE FFTPE BD Ring Low Priority B 7 Parameter
MFFBRLPB7P
− 0xFED00180–
0xFED00183
MAPLE DFTPE BD Ring High Priority A 0 Parameter
MDFBRHPA0P
− 0xFED00184–
0xFED00187
MAPLE DFTPE BD Ring High Priority B 0 Parameter
MDFBRHPB0P
− 0xFED00188–
0xFED0018B
MAPLE DFTPE BD Ring High Priority A 1 Parameter
MDFBRHPA1P
− 0xFED0018C–
0xFED0018F
MAPLE DFTPE BD Ring High Priority B 1 Parameter
MDFBRHPB1P
− 0xFED00190–
0xFED00183
MAPLE DFTPE BD Ring High Priority A 2 Parameter
MDFBRHPA2P
− 0xFED00194–
0xFED00197
MAPLE DFTPE BD Ring High Priority B 2 Parameter
MDFBRHPB2P
− 0xFED00198–
0xFED0019B
MAPLE DFTPE BD Ring High Priority A 3 Parameter
MDFBRHPA3P
− 0xFED0019C–
0xFED0019F
MAPLE DFTPE BD Ring High Priority B 3 Parameter
MDFBRHPB3P
− 0xFED001A0–
0xFED001A3
MAPLE DFTPE BD Ring High Priority A 4 Parameter
MDFBRHPA4P
− 0xFED001A4–
0xFED001A7
MAPLE DFTPE BD Ring High Priority B 4 Parameter
MDFBRHPB4P
− 0xFED001A8–
0xFED001AB
MAPLE DFTPE BD Ring High Priority A 5 Parameter
MDFBRHPA5P
− 0xFED001AC–
0xFED001AF
MAPLE DFTPE BD Ring High Priority B 5 Parameter
MDFBRHPB5P
− 0xFED001B0–
0xFED001B3
MAPLE DFTPE BD Ring High Priority A 6 Parameter
MDFBRHPA6P
− 0xFED001B4–
0xFED001B7
MAPLE DFTPE BD Ring High Priority B 6 Parameter
MDFBRHPB6P
− 0xFED001B8–
0xFED001BB
MAPLE DFTPE BD Ring High Priority A 7 Parameter
MDFBRHPA7P
− 0xFED001BC–
0xFED001BF
MAPLE DFTPE BD Ring High Priority B 7 Parameter
MDFBRHPB7P
− 0xFED001C0–
0xFED001C3
MAPLE DFTPE BD Ring Low Priority A 0 Parameter
MDFBRLPA0P
− 0xFED001C4–
0xFED001C7
MAPLE DFTPE BD Ring Low Priority B 0 Parameter
MDFBRLPB0P
− 0xFED001C8–
0xFED001CB
MAPLE DFTPE BD Ring Low Priority A 1 Parameter
MDFBRLPA1P
MSC8156 Reference Manual, Rev. 2
9-10
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED001CC–
0xFED001CF
MAPLE DFTPE BD Ring Low Priority B 1 Parameter
MDFBRLPB1P
− 0xFED001D0–
0xFED001D3
MAPLE DFTPE BD Ring Low Priority A 2 Parameter
MDFBRLPA2P
− 0xFED001D4–
0xFED001D7
MAPLE DFTPE BD Ring Low Priority B 2 Parameter
MDFBRLPB2P
− 0xFED001D8–
0xFED001DB
MAPLE DFTPE BD Ring Low Priority A 3 Parameter
MDFBRLPA3P
− 0xFED001DC–
0xFED001DF
MAPLE DFTPE BD Ring Low Priority B 3 Parameter
MDFBRLPB3P
− 0xFED001E0–
0xFED001E3
MAPLE DFTPE BD Ring Low Priority A 4 Parameter
MDFBRLPA4P
− 0xFED001E4–
0xFED001E7
MAPLE DFTPE BD Ring Low Priority B 4 Parameter
MDFBRLPB4P
− 0xFED001E8–
0xFED001EB
MAPLE DFTPE BD Ring Low Priority A 5 Parameter
MDFBRLPA5P
− 0xFED001EC–
0xFED001EF
MAPLE DFTPE BD Ring Low Priority B 5 Parameter
MDFBRLPB5P
− 0xFED001F0–
0xFED001F3
MAPLE DFTPE BD Ring Low Priority A 6 Parameter
MDFBRLPA6P
− 0xFED001F4–
0xFED001F7
MAPLE DFTPE BD Ring Low Priority B 6 Parameter
MDFBRLPB6P
− 0xFED001F8–
0xFED001FB
MAPLE DFTPE BD Ring Low Priority A 7 Parameter
MDFBRLPA7P
− 0xFED001FC–
0xFED001FF
MAPLE DFTPE BD Ring Low Priority B 7 Parameter
MDFBRLPB7P
− 0xFED00200–
0xFED00203
MAPLE CRCPE BD Ring High Priority A 0 Parameter
MCRCBRHPA0P
− 0xFED00204–
0xFED00207
MAPLE CRCPE BD Ring High Priority B 0 Parameter
MCRCBRHPB0P
− 0xFED00208–
0xFED0020B
MAPLE CRCPE BD Ring High Priority A 1 Parameter
MCRCBRHPA1P
− 0xFED0020C–
0xFED0020F
MAPLE CRCPE BD Ring High Priority B 1 Parameter
MCRCBRHPB1P
− 0xFED00210–
0xFED00213
MAPLE CRCPE BD Ring High Priority A 2 Parameter
MCRCBRHPA2P
− 0xFED00214–
0xFED00217
MAPLE CRCPE BD Ring High Priority B 2 Parameter
MCRCBRHPB2P
− 0xFED00218–
0xFED0021B
MAPLE CRCPE BD Ring High Priority A 3 Parameter
MCRCBRHPA3P
− 0xFED0021C–
0xFED0021F
MAPLE CRCPE BD Ring High Priority B 3 Parameter
MCRCBRHPB3P
− 0xFED00220–
0xFED00223
MAPLE CRCPE BD Ring High Priority A 4 Parameter
MCRCBRHPA4P
− 0xFED00224–
0xFED00227
MAPLE CRCPE BD Ring High Priority B 4 Parameter
MCRCBRHPB4P
− 0xFED00228–
0xFED0022B
MAPLE CRCPE BD Ring High Priority A 5 Parameter
MCRCBRHPA5P
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-11
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED0022C–
0xFED0022F
MAPLE CRCPE BD Ring High Priority B 5 Parameter
MCRCBRHPB5P
− 0xFED00230–
0xFED00233
MAPLE CRCPE BD Ring High Priority A 6 Parameter
MCRCBRHPA6P
− 0xFED00234–
0xFED00237
MAPLE CRCPE BD Ring High Priority B 6 Parameter
MCRCBRHPB6P
− 0xFED00238–
0xFED0023B
MAPLE CRCPE BD Ring High Priority A 7 Parameter
MCRCBRHPA7P
− 0xFED0023C–
0xFED0023F
MAPLE CRCPE BD Ring High Priority B 7 Parameter
MCRCBRHPB7P
− 0xFED00240–
0xFED00243
MAPLE CRCPE BD Ring Low Priority A 0 Parameter
MCRCBRLPA0P
− 0xFED00244–
0xFED00247
MAPLE CRCPE BD Ring Low Priority B 0 Parameter
MCRCBRLPB0P
− 0xFED00248–
0xFED0024B
MAPLE CRCPE BD Ring Low Priority A 1 Parameter
MCRCBRLPA1P
− 0xFED0024C–
0xFED0024F
MAPLE CRCPE BD Ring Low Priority B 1 Parameter
MCRCBRLPB1P
− 0xFED00250–
0xFED00253
MAPLE CRCPE BD Ring Low Priority A 2 Parameter
MCRCBRLPA2P
− 0xFED00254–
0xFED00257
MAPLE CRCPE BD Ring Low Priority B 2 Parameter
MCRCBRLPB2P
− 0xFED00258–
0xFED0025B
MAPLE CRCPE BD Ring Low Priority A 3 Parameter
MCRCBRLPA3P
− 0xFED0025C–
0xFED0025F
MAPLE CRCPE BD Ring Low Priority B 3 Parameter
MCRCBRLPB3P
− 0xFED00260–
0xFED00263
MAPLE CRCPE BD Ring Low Priority A 4 Parameter
MCRCBRLPA4P
− 0xFED00264–
0xFED00267
MAPLE CRCPE BD Ring Low Priority B 4 Parameter
MCRCBRLPB4P
− 0xFED00268–
0xFED0026B
MAPLE CRCPE BD Ring Low Priority A 5 Parameter
MCRCBRLPA5P
− 0xFED0026C–
0xFED0026F
MAPLE CRCPE BD Ring Low Priority B 5 Parameter
MCRCBRLPB5P
− 0xFED00270–
0xFED00273
MAPLE CRCPE BD Ring Low Priority A 6 Parameter
MCRCBRLPA6P
− 0xFED00274–
0xFED00277
MAPLE CRCPE BD Ring Low Priority B 6 Parameter
MCRCBRLPB6P
− 0xFED00278–
0xFED0027B
MAPLE CRCPE BD Ring Low Priority A 7 Parameter
MCRCBRLPA7P
− 0xFED0027C–
0xFED0027F
MAPLE CRCPE BD Ring Low Priority B 7 Parameter
MCRCBRLPB7P
− 0xFED00280–
0xFED002FF
reserved
− 0xFED00300–
0xFED00303
MAPLE Turbo Stop Criteria Configuration Parameter
− 0xFED00304–
0xFED0037F
reserved
MTSCCP
MSC8156 Reference Manual, Rev. 2
9-12
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED00380–
0xFED00383
MAPLE Turbo Viterbi Puncturing Vector 0 High Configuration
Parameter
MTVPV0HCP
− 0xFED00384–
0xFED00387
MAPLE Turbo Viterbi Puncturing Vector 0 Low Configuration
Parameter
MTVPV0LCP
− 0xFED00388–
0xFED0038B
MAPLE Turbo Viterbi Puncturing Vector 1 High Configuration
Parameter
MTVPV1HCP
− 0xFED0038C–
0xFED0038F
MAPLE Turbo Viterbi Puncturing Vector 1 Low Configuration
Parameter
MTVPV1LCP
− 0xFED00390–
0xFED00393
MAPLE Turbo Viterbi Puncturing Vector 2 High Configuration
Parameter
MTVPV2HCP
− 0xFED00394–
0xFED00397
MAPLE Turbo Viterbi Puncturing Vector 2 Low Configuration
Parameter
MTVPV2LCP
− 0xFED00398–
0xFED0039B
MAPLE Turbo Viterbi Puncturing Vector 3 High Configuration
Parameter
MTVPV3HCP
− 0xFED0039C–
0xFED0039F
MAPLE Turbo Viterbi Puncturing Vector 3 Low Configuration
Parameter
MTVPV3LCP
− 0xFED003A0–
0xFED003A3
MAPLE Turbo Viterbi Puncturing Vector 4 High Configuration
Parameter
MTVPV4HCP
− 0xFED003A4–
0xFED003A7
MAPLE Turbo Viterbi Puncturing Vector 4 Low Configuration
Parameter
MTVPV4LCP
− 0xFED003A8–
0xFED003AB
MAPLE Turbo Viterbi Puncturing Vector 5 High Configuration
Parameter
MTVPV5HCP
− 0xFED003AC–
0xFED003AF
MAPLE Turbo Viterbi Puncturing Vector 5 Low Configuration
Parameter
MTVPV5LCP
− 0xFED003B0–
0xFED003B3
MAPLE Turbo Viterbi Puncturing Vector 6 High Configuration
Parameter
MTVPV6HCP
− 0xFED003B4–
0xFED003B7
MAPLE Turbo Viterbi Puncturing Vector 6 Low Configuration
Parameter
MTVPV6LCP
− 0xFED003B8–
0xFED003BB
MAPLE Turbo Viterbi Puncturing Vector 7 High Configuration
Parameter
MTVPV7HCP
− 0xFED003BC–
0xFED003BF
MAPLE Turbo Viterbi Puncturing Vector 7 Low Configuration
Parameter
MTVPV7LCP
− 0xFED003C0–
0xFED003C3
MAPLE Turbo Viterbi Puncturing Vector 8 High Configuration
Parameter
MTVPV8HCP
− 0xFED003C4–
0xFED003C7
MAPLE Turbo Viterbi Puncturing Vector 8 Low Configuration
Parameter
MTVPV8LCP
− 0xFED003C8–
0xFED003CB
MAPLE Turbo Viterbi Puncturing Vector 9 High Configuration
Parameter
MTVPV9HCP
− 0xFED003CC–
0xFED003CF
MAPLE Turbo Viterbi Puncturing Vector 9 Low Configuration
Parameter
MTVPV9LCP
− 0xFED003D0–
0xFED003D3
MAPLE Turbo Viterbi Puncturing Period Configuration 0
Parameter
MTVPPC0P
− 0xFED003D4–
0xFED003D7
MAPLE Turbo Viterbi Puncturing Period Configuration 1
Parameter
MTVPPC1P
− 0xFED003D8–
0xFED003DB
MAPLE Turbo Viterbi Puncturing Period Configuration 2
Parameter
MTVPPC2P
− 0xFED003DC–
0xFED003DF
reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-13
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED003E0–
0xFED003E3
MAPLE Turbo Viterbi Polynomial Vector Set 0 Configuration 0
Parameter
MTVPVS0C0P
− 0xFED003E4–
0xFED003E7
MAPLE Turbo Viterbi Polynomial Vector Set 0 Configuration 1
Parameter
MTVPVS0C1P
− 0xFED003E8–
0xFED003EB
MAPLE Turbo Viterbi Polynomial Vector Set 1 Configuration 0
Parameter
MTVPVS1C0P
− 0xFED003EC–
0xFED003EF
MAPLE Turbo Viterbi Polynomial Vector Set 1 Configuration 1
Parameter
MTVPVS1C1P
− 0xFED003F0–
0xFED003F3
MAPLE Turbo Viterbi Polynomial Vector Set 2 Configuration 0
Parameter
MTVPVS2C0P
− 0xFED003F4–
0xFED003F7
MAPLE Turbo Viterbi Polynomial Vector Set 2 Configuration 1
Parameter
MTVPVS2C1P
− 0xFED003F8–
0xFED0043F
reserved
− 0xFED00440–
0xFED00443
MAPLE-B Turbo Total Performance Parameter
MTTPP
− 0xFED00444–
0xFED00447
MAPLE-B Viterbi Total Performance Parameter
MVTPP
− 0xFED00448–
0xFED0044B
MAPLE-B Total BLER Parameter
MTBP
− 0xFED0044C–
0xFED0044F
MAPLE-B TVPE Turbo BDs Counter Parameter
MTBDCP
− 0xFED00450–
0xFED00453
MAPLE-B FFT Total Performance Parameter
MFTPP
− 0xFED00454–
0xFED00457
MAPLE-B FFTPE BDs Counter Parameter
MFBDCP
− 0xFED00458–
0xFED0045B
MAPLE-B DFT Total Performance Parameter
MDTPP
− 0xFED0045C–
0xFED0045F
MAPLE-B DFTPE BDs Counter Parameter
MDBDCP
− 0xFED00460–
0xFED00463
MAPLE-B Profiling Enable Parameter
MPEP
− 0xFED00464–
0xFED0047F
reserved
− 0xFED00480–
0xFED00483
Serial RapidIO Outbound RapidIO Doorbell Port0 Base Address
Parameter
SORDP0BAP
− 0xFED00484–
0xFED00487
Serial RapidIO Outbound RapidIO Doorbell Port1 Base Address
Parameter
SORDP1BAP
− 0xFED00488–
0xFED0048B
Hardware Semaphore Port0 Base Address Parameter
HSP0BAP
− 0xFED0048C–
0xFED0048F
Hardware Semaphore Port1 Base Address Parameter
HSP1BAP
− 0xFED00490–
0xFED00493
MAPLE-B Doorbell Hardware Semaphore ID Configuration
Parameter
MDHSIDCP
− 0xFED00494–
0xFED00497
MAPLE-B Doorbell General Configuration Parameter
MDGCP
− 0xFED00498–
0xFED004FF
reserved
MSC8156 Reference Manual, Rev. 2
9-14
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFED00500–
0xFED03FFF
reserved
− 0xFED04000–
0xFED06FFF
Buffer Descriptor (BD) Rings
− 0xFED07000–
0xFED1FFFF
reserved
− 0xFED20000–
0xFED3FFFF
reserved
− 0xFED40000–
0xFED5FFFF
TVPE
− 0xFED40000–
0xFED5DFFF
reserved
− 0xFED5E000
TVPE Configuration 0 Register
− 0xFED5E004
reserved
− 0xFED5E008
TVPE Symbol Identification 0 Configuration Register
Acronym
TVPEC0R
TVSI0CR
− 0xFED5E00C
TVPE Symbol Identification 1 Configuration Register
TVSI1CR
− 0xFED5E010–
0xFED5E023
TVPE Turbo Tail Symbol Identification X Configuration Register
TVTTSIxCR
− 0xFED5E024–
0xFED5E03B
reserved
− 0xFED5E03C
TVPE Aposteriori Quality Configuration Register
TVAQCR
− 0xFED5E040
Viterbi Polynomial Vector Generation 0 Configuration Register
TVVPVG0CR
− 0xFED5E044
TVPE Viterbi Polynomial Vector Generation 1 Configuration
Register
TVVPVG1CR
− 0xFED5E048–
0xFED5ECFF
reserved
− 0xFED5ED00
TVPE Decoder Status Register
− 0xFED5ED10–
0xFED5FFFF
reserved
− 0xFED60000–
0xFED7FFFF
FFTPE
− 0xFED60000–
0xFED67FFF
reserved
− 0xFED68000–
0xFED69FFF
Pre-Multiplication Memory
− 0xFED6A000–
0xFED7E13F
reserved
− 0xFED7E140–
0xFED7E148
FFTPE Data Size Registers
− 0xFED7E149–
0xFED7E237
reserved
− 0xFED7E238
FFTPE Status Register
FFTPESTR
− 0xFED7E23C
FFTPE Scaling Status Register
FFTPESCLSTR
− 0xFED7E240
FFTPE Saturation Status Register 0
FFTPESSTR0
− 0xFED7E244
FFTPE Saturation Status Register 1
FFTPESSTR1
− 0xFED7E248
FFTPE Saturation Status Register 2
FFTPESSTR2
TVPESR
FFTPEDSRx
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-15
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFED7E24C–
0xFED7FFFF
reserved
− 0xFED80000–
0xFED9FFFF
DFTPE
− 0xFED80000–
0xFED87FFF
reserved
− 0xFED88000–
0xFED89FFF
Pre-Multiplication Memory
− 0xFED8A000–
0xFED9E13F
reserved
− 0xFED9E140–
0xFED9E147
DFTPE Data Size Registers
− 0xFED9E148–
0xFED9E237
reserved
− 0xFED9E238
DFTPE Status Register
DFTPESTR
− 0xFED9E23C
DFTPE Scaling Status Register
DFTPESCLSTR
− 0xFED9E240
DFTPE Saturation Status Register 0
DFTPESSTR0
− 0xFED9E244
DFTPE Saturation Status Register 1
DFTPESSTR1
− 0xFED9E248
DFTPE Saturation Status Register 2
DFTPESSTR2
− 0xFED9E24C
DFTPE Saturation Status Register 3
DFTPESSTR3
− 0xFED9E250–
0xFED9FFFF
reserved
− 0xFEDA0000–
0xFEDFFFFF
reserved
• 0xFEE00000–
0xFEE3FFFF
DFTPEDSRx
QUICC Engine Subsystem. See QUICC Engine™ Block Reference Manual with Protocol Interworking
(QEIWRM) for register details.
− 0xFEE00000
IRAM Address Register
IADD
− 0xFEE00004
IRAM Data Register
IDATA
− 0xFEE00008–
0xFEE0007F
reserved
− 0xFEE00080
QUICC Engine Interrupt Configuration Register
CICR
− 0xFEE00084
QUICC Engine System Interrupt Vector Register
CIVEC
− 0xFEE00088
QUICC Engine Interrupt Pending Register
CRIPNR
− 0xFEE0008C
QUICC Engine System Interrupt Pending Register
CIPNR
− 0xFEE00090
QUICC Engine Interrupt Priority Register (XCC)
CIPXCC
− 0xFEE00094–
0xFEE00097
reserved
− 0xFEE00098
QUICC Engine Interrupt Priority Register (WCC)
CIPWCC
− 0xFEE0009C
QUICC Engine Interrupt Priority Register (ZCC)
CIPZCC
− 0xFEE000A0
QUICC Engine System Interrupt Mask Register
CIMR
− 0xFEE000A4
QUICC Engine RISC Interrupt Mask Register
CRIMR
− 0xFEE000A8
QUICC Engine System Interrupt Control Register
CICNR
− 0xFEE000AC–
0xFEE000AF
reserved
MSC8156 Reference Manual, Rev. 2
9-16
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFEE000B0
QUICC Engine System Interrupt Priority Register for RISC Tasks CIPRTA
A
− 0xFEE000B4–
0xFEE000BB
reserved
− 0xFEE000BC
QUICC Engine System RISC Interrupt Control Register
− 0xFEE000C0–
0xFEE000DF
reserved
CRICR
− 0xFEE000E0
QUICC Engine High System Interrupt Vector Register
− 0xFEE000E4–
0xFEE000FF
reserved
− 0xFEE00100
QUICC Engine Command Register
− 0xFEE00104–
0xFEE00107
reserved
− 0xFEE00108
QUICC Engine Command Data Register
− 0xFEE0010C–
0xFEE0011B
reserved
− 0xFEE0011C
QUICC Engine Time-Stamp Control Register
− 0xFEE00120–
0xFEE0012F
reserved
− 0xFEE00130
QUICC Engine Virtual Task Event Register
CEVTER
− 0xFEE00134
QUICC Engine Virtual Task Mask Register
CEVTMR
− 0xFEE00138
QUICC Engine RAM Control Register
CERCR
− 0xFEE0013C–
0xFEE001B7
reserved
− 0xFEE001B8
QUICC Engine Microcode Revision Number Register
− 0xFEE001BC–
0xFEE003FF
reserved
− 0xFEE00400
CMX General Clock Route Register
− 0xFEE00404–
0xFEE0040F
reserved
− 0xFEE00410
CMX Clock Route Register 1
− 0xFEE00414–
0xFEE004DF
Reserved
− 0xFEE004E0
SPI Mode Register
SPIMODE
− 0xFEE004E4
SPI Event Register
SPIE
− 0xFEE004E8
SPI Mask Register
SPIM
− 0xFEE004EC
SPI Command Register
SPCOM
− 0xFEE004F0–
0xFEE0064F
Reserved
− 0xFEE00650
Baud-Rate Generator Configuration Register 5
BRGCR5
− 0xFEE00654
Baud-Rate Generator Configuration Register 6
BRGCR6
− 0xFEE00658
Baud-Rate Generator Configuration Register 7
BRGCR7
− 0xFEE0065C
Baud-Rate Generator Configuration Register 8
BRGCR8
− 0xFEE00660–
0xFEE01FFF
reserved
CHIVEC
CECR
CECDR
CETSCR
CEURNR
CMXGCR
CMXUCR1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-17
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFEE02000
UCC 1 Mode Register
GUMR1
− 0xFEE02004
UCC 1 Protocol Specific Mode Register
UPSMR1
− 0xFEE02008
UCC 1 Transmit-on-Demand Register
UTODR1
− 0xFEE0200A–
0xFEE0200F
reserved
− 0xFEE02010
UCC 1 Event Register
UCCE1
− 0xFEE02014
UCC 1 Mask Register
UCCM1
− 0xFEE02018
UCC 1 Ethernet Transmitter Status Register
UCCS1
− 0xFEE02019–
0xFEE0201F
reserved
− 0xFEE02020
UCC 1 Receive FIFO Base
URFB1
− 0xFEE02024
UCC 1 Receive FIFO Size
URFS1
− 0xFEE02026–
0xFEE02027
reserved
− 0xFEE02028
UCC 1 Receive FIFO Emergency Threshold
URFET1
− 0xFEE0202A
UCC 1 Receive FIFO Special Emergency Threshold
URFSET1
− 0xFEE0202C
UCC 1 Transmit FIFO Base
UTFB1
− 0xFEE02030
UCC 1 Transmit FIFO Size
UTFS1
− 0xFEE02032–
0xFEE02033
reserved
− 0xFEE02034
UCC 1 Transmit FIFO Emergency Threshold
− 0xFEE02036–
0xFEE02037
reserved
− 0xFEE02038
UCC 1 Transmit FIFO Transmit Threshold
− 0xFEE0203A–
0xFEE0203B
reserved
− 0xFEE0203C
UCC 1 Transmit Polling Timer
− 0xFEE0203E–
0xFEE0203F
reserved
− 0xFEE02040
UCC 1 Retry Counter Register
− 0xFEE02044–
0xFEE0208F
reserved
− 0xFEE02090
UCC 1 General Extended Mode Register
− 0xFEE02094–
0xFEE020FF
reserved
− 0xFEE02100
Ethernet 1 MAC Configuration Register 1
UTFET1
UTFTT1
UFPT1
URTRY1
GUEMR1
E1MACCFG1
− 0xFEE02104
Ethernet 1 MAC Configuration Register 2
E1MACCFG2
− 0xFEE02108
Ethernet 1 Interframe Gap Register
E1IPGFG
− 0xFEE0210A–
0xFEE0210B
reserved
− 0xFEE0210C
Ethernet 1 Half-Duplex Register
− 0xFEE02110–
0xFEE0211F
reserved
− 0xFEE02120
Ethernet 1 MII Management Configuration Register
MIIMCFG1
− 0xFEE02124
Ethernet 1 MII Management Command Register
MIIMCOM1
HAFDUP1
MSC8156 Reference Manual, Rev. 2
9-18
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFEE02128
Ethernet 1 MII Management Address Register
MIIMADD1
− 0xFEE0212C
Ethernet 1 MII Management Control Register
MIIMCON1
− 0xFEE02130
Ethernet 1 MII Management Status Register
MIIMSTAT1
− 0xFEE02134
Ethernet 1 MII Management Indication Register
MIIMIND1
− 0xFEE0213C
Ethernet 1 Interface Status Register
IFSTAT1
− 0xFEE02140
Ethernet 1 Station Address Pt. 1 Register
E1MACSTNADDDR1
− 0xFEE02144
Ethernet 1 Station Address Pt. 2 Register
E1MACSTNADDR2
− 0xFEE02148–
0xFEE0214F
reserved
− 0xFEE02150
Ethernet 1 MAC Parameter Register
UEMPR1
− 0xFEE02154
Ethernet 1 Ten-Bit Interface Physical Address Register
UTBIPAR1
− 0xFEE02158
Ethernet 1 Statistical Control Register
UESCR1
− 0xFEE0215C–
0xFEE0217F
reserved
− 0xFEE02180
Ethernet 1 Tx 64-byte Frames
E1TX64
− 0xFEE02184
Ethernet 1 Tx 65- to 127-byte Frames
E1TX127
− 0xFEE02188
Ethernet 1 Tx 128- to 255-byte Frames
E1TX255
− 0xFEE0218C
Ethernet 1 Rx 64-byte Frames
E1RX64
− 0xFEE02190
Ethernet 1 Rx 65- to 127-byte Frames
E1RX127
− 0xFEE02194
Ethernet 1 Rx 128- to 255-byte Frames
E1RX255
− 0xFEE02198
Ethernet 1 Octet Transmitted OK
E1TXOK
− 0xFEE0219C
Ethernet 1 Tx Pause Frames
E1TXCF
− 0xFEE021A0
Ethernet 1 Multicast Frame Transmitted OK
E1TMCA
− 0xFEE021A4
Ethernet 1 Broadcast Frames Transmitted OK
E1TBCA
− 0xFEE021A8
Ethernet 1 Number of Frames Received OK
E1RXFOK
− 0xFEE021AC
Ethernet 1 Rx Octets OK
E1RBYT
− 0xFEE021B0
Ethernet 1 Rx Octets
E1RXBOK
− 0xFEE021B4
Ethernet 1 Multicast Frame Received OK
E1RMCA
− 0xFEE021B8
Ethernet 1 Broadcast Frames Received OK
E1RBCA
− 0xFEE021BC
Ethernet 1 Statistic Counters Carry Register
E1SCAR
− 0xFEE021C0
Ethernet 1 Statistic Counters Carry Mask Register
E1SCAM
− 0xFEE021C4–
0xFEE021FF
reserved
− 0xFEE02200
UCC 3 General Mode Register
GUMR3
− 0xFEE02204
UCC 3 Protocol Specific Mode Register
UPSMR3
− 0xFEE02208
UCC 3 Transmit-on-Demand Register
UTODR3
− 0xFEE0220A–
0xFEE0220F
reserved
− 0xFEE02210
UCC 3 Event Register
UCCE3
− 0xFEE02214
UCC 3 Mask Registers
UCCM3
− 0xFEE02218
UCC 3 Status Register
UCCS3
− 0xFEE02219–
0xFEE0221F
reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-19
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFEE02220
UCC 3 Receive FIFO Base
URFB3
− 0xFEE02224
UCC 3 Receive FIFO Size
URFS3
− 0xFEE02226–
0xFEE02227
reserved
− 0xFEE02228
UCC 3 Receive FIFO Emergency Threshold
URFET3
− 0xFEE0222A
UCC 3 Receive FIFO Special Emergency Threshold
URFSET3
− 0xFEE0222C
UCC 3 Transmit FIFO Base
UTFB3
− 0xFEE02230
UCC 3 Transmit FIFO Size
UTFS3
− 0xFEE02232–
0xFEE02233
reserved
− 0xFEE02234
UCC 3 Transmit FIFO Emergency Threshold
− 0xFEE02236–
0xFEE02237
reserved
− 0xFEE02238
UCC 3 Transmit FIFO Transmit Threshold
− 0xFEE0223A–
0xFEE0223B
reserved
− 0xFEE0223C
UCC 3 Transmit Polling Timer
− 0xFEE0223E–
0xFEE0223F
reserved
− 0xFEE02240
UCC 3 Retry Counter
− 0xFEE02244–
0xFEE0228F
reserved
− 0xFEE02290
UCC 3 General Extended Mode Register
− 0xFEE02294–
0xFEE022FF
reserved
− 0xFEE02300
Ethernet 2 MAC Configuration Register 1
E2MACCFG1
− 0xFEE02304
Ethernet 2 MAC Configuration Register 2
E2MACCFG2
− 0xFEE02308
Ethernet 2 Interframe Gap Register
E2IPGIFG
− 0xFEE0230A–
0xFEE0230B
reserved
− 0xFEE0230C
Ethernet 2 Half-Duplex Register
− 0xFEE02310–
0xFEE0231F
reserved
− 0xFEE02320
Ethernet 2 MII Management Configuration Register
MIIMCFG3
− 0xFEE02324
Ethernet 2 MII Management Command Register
MIIMCOM3
− 0xFEE02328
Ethernet 2 MII Management Address Register
MIIMADD3
UTFET3
UTFTT3
UFPT3
URTRY3
GUEMR3
HAFDUP3
− 0xFEE0232C
Ethernet 2 MII Management Control Register
MIIMCON3
− 0xFEE02330
Ethernet 2 MII Management Status Register
MIIMSTAT3
− 0xFEE02334
Ethernet 2 MII Management Indication Register
MIIMIND3
− 0xFEE02338–
0xFEE0233B
reserved
− 0xFEE0233C
Ethernet 2 Interface Status Register
IFSTAT3
− 0xFEE02340
Ethernet 2 Station Address Pt. 1 Register
E2MACSTNADDR1
− 0xFEE02344
Ethernet 2 Station Address Pt. 2 Register
E2MACSTNADDR2
MSC8156 Reference Manual, Rev. 2
9-20
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFEE02348–
0xFEE0234F
reserved
− 0xFEE02350
Ethernet 2 Ethernet MAC Parameter Register
UEMPR3
− 0xFEE02354
Ethernet 2 Ten-Bit Interface Physical Address Register
TBIPAR3
− 0xFEE02358
Ethernet 2 Ethernet Statistical Control Register
UESCR3
− 0xFEE0235C–
0xFEE0237F
reserved
− 0xFEE02380
Ethernet 2 Tx 64-byte Frames
− 0xFEE02384
Ethernet 2 Tx 65- to 127-byte Frames
E2TX127
− 0xFEE02388
Ethernet 2 Tx 128- to 255-byte Frames
E2TX255
− 0xFEE0238C
Ethernet 2 Rx 64-byte Frames
E2RX64
− 0xFEE02390
Ethernet 2 Rx 65- to 127-byte Frames
E2RX127
− 0xFEE02394
Ethernet 2 Rx 128- to 255-byte Frames
E2RX255
− 0xFEE02398
Ethernet 2 Octet Transmitted OK
E2TXOK
− 0xFEE0239C
Ethernet 2 Tx Pause Frames
E2TXCF
− 0xFEE023A0
Ethernet 2 Multicast Frame Transmitted OK
E2TMCA
E2TX64
− 0xFEE023A4
Ethernet 2 Broadcast Frames Transmitted OK
E2TBCA
− 0xFEE023A8
Ethernet 2 Number of Frames Received OK
E2RXFOK
− 0xFEE023AC
Ethernet 2 Rx Octets OK
E2RBYT
− 0xFEE023B0
Ethernet 2 Rx Octets
E2RXBOK
− 0xFEE023B4
Ethernet 2 Multicast Frame Received OK
E2RMCA
− 0xFEE023B8
Ethernet 2 Broadcast Frames Received OK
E2RBCA
− 0xFEE023BC
Ethernet 2 Statistic Counters Carry Register
E2SCAR
− 0xFEE023C0
Ethernet 2 Statistic Counters Carry Mask Register
E2SCAM
− 0xFEE023C4–
0xFEE021FF
reserved
− 0xFEE04000
Serial DMA Status Register
SDSR
− 0xFEE04004
Serial DMA Mode Register
SDMR
− 0xFEE04008
Serial DMA Threshold Register
SDTR
− 0xFEE0400C–
0xFEE0400F
reserved
− 0xFEE04010
Serial DMA Hysteresis Register
− 0xFEE04014–
0xFEE04017
reserved
− 0xFEE04018
Serial DMA Address Register
− 0xFEE0401C–
0xFEE0401F
reserved
− 0xFEE04020
Serial DMA MSNUM Register
− 0xFEE04024–
0xFEE04037
reserved
− 0xFEE04038
Serial DMA Address Qualify Register
SDAQR
− 0xFEE0403C
Serial DMA Address Qualify Mask Register
SDAQMR
− 0xFEE04040–
0xFEE04043
reserved
SDHY
SDTA
SDTM
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-21
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFEE04044
Serial DMA Temporary Buffer Base in Multi-User RAM Value
− 0xFEE04048–
0xFEE07FFF
reserved
− 0xFEE08000–
0xFEE0FFFF
RAM space reserved
− 0xFEE10000–
0xFEE1BFFF
Multi-User RAM
− 0xFEE1C000–
0xFEE3FFFF
reserved
Acronym
SDEBCR
• 0xFEE40000–
0xFEEFFFFF
reserved (for QUICC Engine subsystem)
• 0xFEF00000–
0xFEF17FFF
Boot ROM
• 0xFEF18000–
0xFEFFFFFF
reserved
0xFF000000–
0xFFF0FFFF
DSP core subsystem internal memory space. See the MSC8156 SC3850 DSP Core Subsystem
Reference Manual for details.
0xFFF10000–
0xFFFFEFFF
CCSR
• 0xFFF10000–
0xFFF103FF
DMA
− 0xFFF10000
DMA Buffer Descriptor Base Register 0
DMABDBR0
− 0xFFF10004
DMA Buffer Descriptor Base Register 1
DMABDBR1
− 0xFFF10008
DMA Buffer Descriptor Base Register 2
DMABDBR2
− 0xFFF1000C
DMA Buffer Descriptor Base Register 3
DMABDBR3
− 0xFFF10010
DMA Buffer Descriptor Base Register 4
DMABDBR4
− 0xFFF10014
DMA Buffer Descriptor Base Register 5
DMABDBR5
− 0xFFF10018
DMA Buffer Descriptor Base Register 6
DMABDBR6
− 0xFFF1001C
DMA Buffer Descriptor Base Register 7
DMABDBR7
− 0xFFF10020
DMA Buffer Descriptor Base Register 8
DMABDBR8
− 0xFFF10024
DMA Buffer Descriptor Base Register 9
DMABDBR9
− 0xFFF10028
DMA Buffer Descriptor Base Register 10
DMABDBR10
− 0xFFF1002C
DMA Buffer Descriptor Base Register 11
DMABDBR11
− 0xFFF10030
DMA Buffer Descriptor Base Register 12
DMABDBR12
− 0xFFF10034
DMA Buffer Descriptor Base Register 13
DMABDBR13
− 0xFFF10038
DMA Buffer Descriptor Base Register 14
DMABDBR14
− 0xFFF1003C
DMA Buffer Descriptor Base Register 15
DMABDBR15
− 0xFFF10040–
0xFFF100FF
Reserved
− 0xFFF10100
DMA Channel Configuration Register 0
DMACHCR0
− 0xFFF10104
DMA Channel Configuration Register 1
DMACHCR1
− 0xFFF10108
DMA Channel Configuration Register 2
DMACHCR2
− 0xFFF1010C
DMA Channel Configuration Register 3
DMACHCR3
− 0xFFF10110
DMA Channel Configuration Register 4
DMACHCR4
− 0xFFF10114
DMA Channel Configuration Register 5
DMACHCR5
MSC8156 Reference Manual, Rev. 2
9-22
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF10118
DMA Channel Configuration Register 6
DMACHCR6
− 0xFFF1011C
DMA Channel Configuration Register 7
DMACHCR7
− 0xFFF10120
DMA Channel Configuration Register 8
DMACHCR8
− 0xFFF10124
DMA Channel Configuration Register 9
DMACHCR9
− 0xFFF10128
DMA Channel Configuration Register 10
DMACHCR10
− 0xFFF1012C
DMA Channel Configuration Register 11
DMACHCR11
− 0xFFF10130
DMA Channel Configuration Register 12
DMACHCR12
− 0xFFF10134
DMA Channel Configuration Register 13
DMACHCR13
− 0xFFF10138
DMA Channel Configuration Register 14
DMACHCR14
− 0xFFF1013C
DMA Channel Configuration Register 15
DMACHCR15
− 0xFFF10140–
0xFFF101FF
Reserved
− 0xFFF10200
DMA Global Configuration Register
DMAGCR
− 0xFFF10204
DMA Channel Enable Register
DMACHER
− 0xFFF10208–
0xFFF1020B
Reserved
− 0xFFF1020C
DMA Channel Disable Register
− 0xFFF10210–
0xFFF10213
Reserved
− 0xFFF10214
DMA Channel Freeze Register
− 0xFFF10218–
0xFFF10223
Reserved
− 0xFFF10224
DMA Channel Defrost Register
− 0xFFF10228–
0xFFF10233
Reserved
− 0xFFF10234
DMA Time-To-Deadline Register 0
DMAEDFTDL0
− 0xFFF10238
DMA Time-To-Deadline Register 1
DMAEDFTDL1
− 0xFFF1023C
DMA Time-To-Deadline Register 2
DMAEDFTDL2
− 0xFFF10240
DMA Time-To-Deadline Register 3
DMAEDFTDL3
− 0xFFF10244
DMA Time-To-Deadline Register 4
DMAEDFTDL4
− 0xFFF10248
DMA Time-To-Deadline Register 5
DMAEDFTDL5
− 0xFFF1024C
DMA Time-To-Deadline Register 6
DMAEDFTDL6
− 0xFFF10250
DMA Time-To-Deadline Register 7
DMAEDFTDL7
− 0xFFF10254
DMA Time-To-Deadline Register 8
DMAEDFTDL8
− 0xFFF10258
DMA Time-To-Deadline Register 9
DMAEDFTDL9
− 0xFFF1025C
DMA Time-To-Deadline Register 10
DMAEDFTDL10
DMACHDR
DMACHFR
DMACHDFR
− 0xFFF10260
DMA Time-To-Deadline Register 11
DMAEDFTDL11
− 0xFFF10264
DMA Time-To-Deadline Register 12
DMAEDFTDL12
− 0xFFF10268
DMA Time-To-Deadline Register 13
DMAEDFTDL13
− 0xFFF1026C
DMA Time-To-Deadline Register 14
DMAEDFTDL14
− 0xFFF10270
DMA Time-To-Deadline Register 15
DMAEDFTDL15
− 0xFFF10274–
0xFFF10333
Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-23
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF10334
DMA EDF Control Register
DMAEDFCTRL
− 0xFFF10338
DMA EDF Mask Register
DMAEDFMR
− 0xFFF1033C–
0xFFF1033f
Reserved
− 0xFFF10340
DMA EDF Mask Update Register
DMAEDFMUR
− 0xFFF10344
DMA EDF Status Register
DMAEDFSTR
− 0xFFF10348–
0xFFF1034B
Reserved
− 0xFFF1034C
DMA Mask Register
− 0xFFF10350–
0xFFF1035B
Reserved
DMAMR
− 0xFFF1035C
DMA Mask Update Register
DMAMUR
− 0xFFF10360
DMA Status Register
DMASTR
− 0xFFF10364–
0xFFF1036F
Reserved
− 0xFFF10370
DMA Error Register
DMAERR
− 0xFFF10374
DMA Debug Event Status Register
DMADESR
− 0xFFF10378
DMA Local Profiling Configuration Register
DMALPCR
− 0xFFF1037C
DMA Round Robin Priority Group Update Register
DMARRPGUR
− 0xFFF10380
DMA Channel Active Status Register
DMACHASTR
− 0xFFF10384–
0xFFF10387
Reserved
− 0xFFF10388
DMA Channel Freeze Status Register
− 0xFFF1038C–
0xFFF103FF
reserved
• 0xFFF10400–
0xFFF17FFF
reserved
• 0xFFF18000–
0xFFF18FFF
CLASS
− 0xFFF18000–
0xFFF1801F
Reserved
− 0xFFF18020
CLASS MBus Target Configuration Register 1
− 0xFFF18024–
0xFFF1803F
Reserved
− 0xFFF18040
CLASS MBus Target Configuration Register 2
− 0xFFF18044–
0xFFF1805F
Reserved
− 0xFFF18060
CLASS MBus Target Configuration Register 3
− 0xFFF18064–
0xFFF1807F
Reserved
− 0xFFF18080
CLASS MBus Target Configuration Register 4
− 0xFFF18084–
0xFFF1808F
Reserved
− 0xFFF18090
CLASS MBus Target Configuration Register 5
DMACHFSTR
C0MTCR1
C0MTCR2
C0MTCR3
C0MTCR4
C0MTCR5
MSC8156 Reference Manual, Rev. 2
9-24
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF18094–
0xFFF1809F
Reserved
− 0xFFF180A0
CLASS MBus Target Configuration Register 6
− 0xFFF180A4–
0xFFF180AF
Reserved
− 0xFFF180B0
CLASS MBus Target Configuration Register 7
− 0xFFF180B4–
0xFFF187FF
Reserved
− 0xFFF18800
CLASS Priority Mapping Register 0
C0PMR0
− 0xFFF18804
CLASS Priority Mapping Register 1
C0PMR1
− 0xFFF18808
CLASS Priority Mapping Register 2
C0PMR2
− 0xFFF1880C
CLASS Priority Mapping Register 3
C0PMR3
− 0xFFF18810
CLASS Priority Mapping Register 4
C0PMR4
− 0xFFF18814
CLASS Priority Mapping Register 5
C0PMR5
− 0xFFF18818
CLASS Priority Mapping Register 6
C0PMR6
− 0xFFF1881C
CLASS Priority Mapping Register 7
C0PMR7
− 0xFFF18820
CLASS Priority Mapping Register 8
C0PMR8
− 0xFFF18824
CLASS Priority Mapping Register 9
C0PMR9
− 0xFFF18828
CLASS Priority Mapping Register 10
C0PMR10
− 0xFFF1882C
CLASS Priority Mapping Register 11
C0PMR11
− 0xFFF18830–
0xFFF1883F
reserved
− 0xFFF18840
CLASS Priority Auto Upgrade Value Register 0
C0PAVR0
− 0xFFF18844
CLASS Priority Auto Upgrade Value Register 1
C0PAVR1
− 0xFFF18848
CLASS Priority Auto Upgrade Value Register 2
C0PAVR2
− 0xFFF1884C
CLASS Priority Auto Upgrade Value Register 3
C0PAVR3
− 0xFFF18850
CLASS Priority Auto Upgrade Value Register 4
C0PAVR4
− 0xFFF18854
CLASS Priority Auto Upgrade Value Register 5
C0PAVR5
− 0xFFF18858
CLASS Priority Auto Upgrade Value Register 6
C0PAVR6
− 0xFFF1885C
CLASS Priority Auto Upgrade Value Register 7
C0PAVR7
− 0xFFF18860
CLASS Priority Auto Upgrade Value Register 8
C0PAVR8
− 0xFFF18864
CLASS Priority Auto Upgrade Value Register 9
C0PAVR9
− 0xFFF18868
CLASS Priority Auto Upgrade Value Register 10
C0PAVR10
− 0xFFF1886C
CLASS Priority Auto Upgrade Value Register 11
C0PAVR11
− 0xFFF18870–
0xFFF1887F
reserved
− 0xFFF18880
CLASS Priority Auto Upgrade Control Register 0
C0PACR0
− 0xFFF18884
CLASS Priority Auto Upgrade Control Register 1
C0PACR1
− 0xFFF18888
CLASS Priority Auto Upgrade Control Register 2
C0PACR2
− 0xFFF1888C
CLASS Priority Auto Upgrade Control Register 3
C0PACR3
− 0xFFF18890
CLASS Priority Auto Upgrade Control Register 4
C0PACR4
− 0xFFF18894
CLASS Priority Auto Upgrade Control Register 5
C0PACR5
− 0xFFF18898
CLASS Priority Auto Upgrade Control Register 6
C0PACR6
C0MTCR6
C0MTCR7
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-25
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF1889C
CLASS Priority Auto Upgrade Control Register 7
C0PACR7
− 0xFFF188A0
CLASS Priority Auto Upgrade Control Register 8
C0PACR8
− 0xFFF188A4
CLASS Priority Auto Upgrade Control Register 9
C0PACR9
− 0xFFF188A8
CLASS Priority Auto Upgrade Control Register 10
C0PACR10
− 0xFFF188AC
CLASS Priority Auto Upgrade Control Register 11
C0PACR11
− 0xFFF188B0–
0xFFF1897F
reserved
− 0xFFF18980
CLASS Error Address Register 0
C0EAR0
− 0xFFF18984
CLASS Error Address Register 1
C0EAR1
− 0xFFF18988
CLASS Error Address Register 2
C0EAR2
− 0xFFF1898C
CLASS Error Address Register 3
C0EAR3
− 0xFFF18990
CLASS Error Address Register 4
C0EAR4
− 0xFFF18994
CLASS Error Address Register 5
C0EAR5
− 0xFFF18998
CLASS Error Address Register 6
C0EAR6
− 0xFFF1899C
CLASS Error Address Register 7
C0EAR7
− 0xFFF189A0
CLASS Error Address Register 8
C0EAR8
− 0xFFF189A4
CLASS Error Address Register 9
C0EAR9
− 0xFFF189A8
CLASS Error Address Register 10
C0EAR10
− 0xFFF189AC
CLASS Error Address Register 11
C0EAR11
− 0xFFF189B0–
0xFFF189BF
reserved
− 0xFFF189C0
CLASS Error Extended Address Register 0
C0EEAR0
− 0xFFF189C4
CLASS Error Extended Address Register 1
C0EEAR1
− 0xFFF189C8
CLASS Error Extended Address Register 2
C0EEAR2
− 0xFFF189CC
CLASS Error Extended Address Register 3
C0EEAR3
− 0xFFF189D0
CLASS Error Extended Address Register 4
C0EEAR4
− 0xFFF189D4
CLASS Error Extended Address Register 5
C0EEAR5
− 0xFFF189D8
CLASS Error Extended Address Register 6
C0EEAR6
− 0xFFF189DC
CLASS Error Extended Address Register 7
C0EEAR7
− 0xFFF189E0
CLASS Error Extended Address Register 8
C0EEAR8
− 0xFFF189E4
CLASS Error Extended Address Register 9
C0EEAR9
− 0xFFF189E8
CLASS Error Extended Address Register 10
C0EEAR10
− 0xFFF189EC
CLASS Error Extended Address Register 11
C0EEAR11
− 0xFFF189F0–
0xFFF189FF
reserved
− 0xFFF18A00
CLASS Initiator Profiling Configuration Register 0
C0IPCR0
− 0xFFF18A04
CLASS Initiator Profiling Configuration Register 1
C0IPCR1
− 0xFFF18A08
CLASS Initiator Profiling Configuration Register 2
C0IPCR2
− 0xFFF18A0C
CLASS Initiator Profiling Configuration Register 3
C0IPCR3
− 0xFFF18A10
CLASS Initiator Profiling Configuration Register 4
C0IPCR4
− 0xFFF18A14
CLASS Initiator Profiling Configuration Register 5
C0IPCR5
− 0xFFF18A18
CLASS Initiator Profiling Configuration Register 6
C0IPCR6
MSC8156 Reference Manual, Rev. 2
9-26
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF18A1C
CLASS Initiator Profiling Configuration Register 7
C0IPCR7
− 0xFFF18A20
CLASS Initiator Profiling Configuration Register 8
C0IPCR8
− 0xFFF18A24
CLASS Initiator Profiling Configuration Register 9
C0IPCR9
− 0xFFF18A28
CLASS Initiator Profiling Configuration Register 10
C0IPCR10
− 0xFFF18A2C
CLASS Initiator Profiling Configuration Register 11
C0IPCR11
− 0xFFF18A30–
0xFFF18A3F
reserved
− 0xFFF18A40
CLASS Initiator Watch Point Control Register 0
C0IWPCR0
− 0xFFF18A44
CLASS Initiator Watch Point Control Register 1
C0IWPCR1
− 0xFFF18A48
CLASS Initiator Watch Point Control Register 2
C0IWPCR2
− 0xFFF18A4C
CLASS Initiator Watch Point Control Register 3
C0IWPCR3
− 0xFFF18A50
CLASS Initiator Watch Point Control Register 4
C0IWPCR4
− 0xFFF18A54
CLASS Initiator Watch Point Control Register 5
C0IWPCR5
− 0xFFF18A58
CLASS Initiator Watch Point Control Register 6
C0IWPCR6
− 0xFFF18A5C
CLASS Initiator Watch Point Control Register 7
C0IWPCR7
− 0xFFF18A60
CLASS Initiator Watch Point Control Register 8
C0IWPCR8
− 0xFFF18A64
CLASS Initiator Watch Point Control Register 9
C0IWPCR9
− 0xFFF18A68
CLASS Initiator Watch Point Control Register 10
C0IWPCR10
− 0xFFF18A6C
CLASS Initiator Watch Point Control Register 11
C0IWPCR11
− 0xFFF18A70–
0xFFF18A7F
reserved
− 0xFFF18A80
CLASS Arbitration Weight Register 0
C0AWR0
− 0xFFF18A84
CLASS Arbitration Weight Register 1
C0AWR1
− 0xFFF18A88
CLASS Arbitration Weight Register 2
C0AWR2
− 0xFFF18A8C
CLASS Arbitration Weight Register 3
C0AWR3
− 0xFFF18A90
CLASS Arbitration Weight Register 4
C0AWR4
− 0xFFF18A94
CLASS Arbitration Weight Register 5
C0AWR5
− 0xFFF18A98
CLASS Arbitration Weight Register 6
C0AWR6
− 0xFFF18A9C
CLASS Arbitration Weight Register 7
C0AWR7
− 0xFFF18AA0
CLASS Arbitration Weight Register 8
C0AWR8
− 0xFFF18AA4
CLASS Arbitration Weight Register 9
C0AWR9
− 0xFFF18AA8
CLASS Arbitration Weight Register 10
C0AWR10
− 0xFFF18AAC
CLASS Arbitration Weight Register 11
C0AWR11
− 0xFFF18AB0–
0xFFF18C13
reserved
− 0xFFF18C14
CLASS Start Address Decoder 5
C0SAD5
− 0xFFF18C18
CLASS Start Address Decoder 6
C0SAD6
− 0xFFF18C1C–
0xFFF18C53
reserved
− 0xFFF18C54
CLASS End Address Decoder 5
C0EAD5
− 0xFFF18C58
CLASS End Address Decoder 6
C0EAD6
− 0xFFF18C5C–
0xFFF18C93
reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-27
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF18C94
CLASS Attributes Decoder 5
C0ATD5
− 0xFFF18C98
CLASS Attributes Decoder 6
C0ATD6
− 0xFFF18C9C–
0xFFF18D7F
reserved
− 0xFFF18D80
CLASS IRQ Status Register
− 0xFFF18D84–
0xFFF18DBF
Reserved
− 0xFFF18DC0
CLASS IRQ Enable Register
− 0xFFF18DC4–
0xFFF18DFF
Reserved
− 0xFFF18E00
CLASS Target Profiling Configuration Register
− 0xFFF18E04
CLASS Profiling Control Register
C0PCR
− 0xFFF18E08
CLASS Watch Point Control Register
C0WPCR
− 0xFFF18E0C
CLASS Watch Point Access Configuration Register
C0WPACR
− 0xFFF18E10
CLASS Watch Point Extended Access Configuration Register
C0WPEACR
− 0xFFF18E14
CLASS Watch Point Address Mask Register
C0WPAMR
− 0xFFF18E18
CLASS Profiling Time-Out Register
C0PTOR
− 0xFFF18E1C
CLASS Target Watch Point Control Register
C0TWPCR
− 0xFFF18E20
CLASS Profiling IRQ Status Register
C0PISR
− 0xFFF18E24
CLASS Profiling IRQ Enable Register
C0PIER
− 0xFFF18E280xFFF18E3F
Reserved
− 0xFFF18E40
CLASS Profiling Reference Counter Register
C0PRCR
− 0xFFF18E44
CLASS Profiling General Counter Register 0
C0PGCR0
− 0xFFF18E48
CLASS Profiling General Counter Register 1
C0PGCR1
− 0xFFF18E4C
CLASS Profiling General Counter Register 2
C0PGCR2
− 0xFFF18E50
CLASS Profiling General Counter Register 3
C0PGCR3
− 0xFFF18E54–
0xFFF18FBF
Reserved
− 0xFFF18FC0
CLASS Arbitration Control Register
− 0xFFF18FC4–
0xFFF18FFF
Reserved
• 0xFFF19000–
0xFFF1BFFF
reserved
• 0xFFF1C000–
0xFFF1FFFF
MAPLE-B
C0ISR
C0IER
C0TPCR
C0ACR
− 0xFFF1C000–
0xFFF1CFFF
reserved
− 0xFFF1D000–
0xFFF1D7FF
PSIF_PIC
− 0xFFF1D600
PSIF PIC Event Register
PSPICER
− 0xFFF1D604
PSIF PIC Edge/Level Register
PSPICELR
− 0xFFF1D608
PSIF PIC Mask Register
PSPICMR
− 0xFFF1D60C
PSIF PIC Interrupt Assertion Clocks Register
PSPICIACR
MSC8156 Reference Manual, Rev. 2
9-28
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF1D610–
0xFFF1D7FF
reserved
− 0xFFF1D800–
0xFFF1FFFF
reserved
• 0xFFF20000–
0xFFF21FFF
Acronym
DDR Controller 1
− 0xFFF20000
Chip Select 0 Bounds
− 0xFFF20004–
0xFFF20007
reserved
− 0xFFF20008
Chip Select 1 Bounds
− 0xFFF2000C–
0xFFF2007F
reserved
− 0xFFF20080
Chip Select 0 Configuration
M1CS0_CONFIG
− 0xFFF20084
Chip Select 1 Configuration
M1CS1_CONFIG
− 0xFFF20088–
0xFFF200BF
reserved
− 0xFFF200C0
Chip Select 0 Configuration 2
M1CS0_CONFIG_2
− 0xFFF200C4
Chip Select 1 Configuration 2
M1CS1_CONFIG_2
− 0xFFF200C8–
0xFFF200FF
reserved
− 0xFFF20100
DDR SDRAM Timing Configuration 3
M1TIMING_CFG_3
− 0xFFF20104
DDR SDRAM Timing Configuration 0
M1TIMING_CFG_0
− 0xFFF20108
DDR SDRAM Timing Configuration 1
M1TIMING_CFG_1
− 0xFFF2010C
DDR SCRAM Timing Configuration 2
M1TIMING_CFG_2
− 0xFFF20110
DDR SDRAM Control Configuration
M1DDR_SDRAM_CFG
− 0xFFF20114
DDR SDRAM Control Configuration 2
M1DDR_SDRAM_CFG_2
− 0xFFF20118
DDR SDRAM Mode Configuration
M1DDR_SDRAM_MODE
− 0xFFF2011C
DDR SDRAM Mode Configuration 2
M1DDR_SDRAM_MODE_2
− 0xFFF20120
DDR SDRAM Mode Control
M1DDR_SCRAM_MD_CNTL
− 0xFFF20124
DDR SDRAM Interval Configuration
M1DDR_SDRAM_INTERVAL
− 0xFFF20128
DDR SDRAM Data Initialization
M1DDR_DATA_INIT
− 0xFFF2012C–
0xFFF2012F
reserved
− 0xFFF20130
DDR SDRAM Clock Control
− 0xFFF20134–
0xFFF20147
reserved
− 0xFFF20148
DDR SDRAM Initialization Address
M1DDR_INIT_ADDRESS
− 0xFFF2014C
DDR Initialization Enable Extended Address
M1DDR_INIT_ENXT_ADDR
− 0xFFF20150–
0xFFF2015F
reserved
− 0xFFF20160
DDR SDRAM Timing Configuration 4
M1TIMING_CFG_4
− 0xFFF20164
DDR SDRAM Timing Configuration 5
M1TIMING_CFG_5
− 0xFFF20168–
0xFFF2016F
reserved
− 0xFFF20170
DDR ZQ Calibration Control
M1CS0_BNDS
M1CS1_BNDS
M1DDR_SDRAM_CLK_CNT
M1DDR_ZQ_CNTL
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-29
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF20174
DDR Write Leveling Control
M1DDR_WRLVL_CNTL
− 0xFFF22178
DDR Pre-Drive Conditioning Control
M1DDR_PD_CNTL
− 0xFFF2017C
DDR Self Refresh Counter
M1DDR_SR_CNTR
− 0xFFF20180
DDR SDRAM Register Control Words 1
M1DDR_SDRAM_RCW_1
− 0xFFF20184
DDR SDRAM Register Control Words 2
M1DDR_SDRAM_RCW_2
− 0xFFF20188–
0xFFF2018F
reserved
− 0xFFF20190
DDR Write Leveling Control 2
M1DDR_WRLVL_CNTL_2
− 0xFFF20194
DDR Write Leveling Control 3
M1DDR_WRLVL_CNTL_3
− 0xFFF20198–
0xFFF20B1F
reserved
− 0xFFF20B20
DDR Debug Status Register 1
M1DDRDSR_1
− 0xFFF20B24
DDR Debug Status Register 2
M1DDRDSR_2
− 0xFFF20B28
DDR Control Driver Register 1
M1DDRCDR_1
− 0xFFF20B2C
DDR Control Driver Register 2
M1DDRCDR_2
− 0xFFF20B30–
0xFFF20BF7
reserved
− 0xFFF20BF8
DDR IP Block Revision 1
M1DDR_IP_REV1
− 0xFFF20BFC
DDR IP Block Revision 2
M1DDR_IP_REV2
− 0xFFF20C00–
0xFFF20DFF
reserved
− 0xFFF20E00
Memory Data Path Error Injection Mask High
M1DDR_ERR_INJECT_HI
− 0xFFF20E04
Memory Data Path Error Injection Mask Low
M1DDR_ERR_INJECT_LO
− 0xFFF20E08
Memory Data Path Error Injection Mask ECC
M1DDR_ERR_INJECT
− 0xFFF20E0C–
0xFFF20E1F
reserved
− 0xFFF20E20
Memory Data Path Read Capture High
M1CAPTURE_DATA_HI
− 0xFFF20E24
Memory Data Path Read Capture Low
M1CAPTURE-DATA_LO
− 0xFFF20E28
Memory Data Path Read Capture ECC
M1CAPTURE_ECC
− 0xFFF20E2C–
0xFFF20E3F
reserved
− 0xFFF20E40
Memory Error Detect
− 0xFFF20E44
Memory Error Disable
M1ERR_DISABLE
− 0xFFF20E48
Memory Error Interrupt Enable
M1ERR_INT_EN
− 0xFFF20E4C
Memory Error Attributes Capture
M1CAPTURE_ATTRIBUTES
− 0xFFF20E50
Memory Error Address Capture
M1CAPTURE_ADDRESS
− 0xFFF20E54–
0xFFF20E57
reserved
− 0xFFF20E58
Single-Bit ECC Memory Error Management
− 0xFFF20E5C–
0xFFF20F03
reserved
− 0xFFF20F04
Debug Register 2
− 0xFFF20F08–
0xFFF21FFF
reserved
M1ERR_DETECT
M1ERR_SBE
M1DEBUG_2
MSC8156 Reference Manual, Rev. 2
9-30
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
• 0xFFF22000–
0xFFF23FFF
Name/Status
Acronym
DDR Controller 2
− 0xFFF22000
Chip Select 0 Memory Bounds
− 0xFFF22004–
0xFFF22007
reserved
− 0xFFF22008
Chip Select 1 Memory Bounds
− 0xFFF2200C–
0xFFF2207F
reserved
− 0xFFF22080
Chip Select 0 Configuration
M2CS0_CONFIG
− 0xFFF22084
Chip Select 1 Configuration
M2CS1_CONFIG
− 0xFFF22088–
0xFFF220BF
reserved
− 0xFFF220C0
Chip Select 0 Configuration 2
M2CS0_CONFIG_2
− 0xFFF220C4
Chip Select 1 Configuration 2
M2CS1_CONFIG_2
− 0xFFF220C8–
0xFFF220FF
reserved
− 0xFFF22100
DDR SDRAM Timing Configuration 3
M2TIMING_CFG_3
− 0xFFF22104
DDR SDRAM Timing Configuration 0
M2TIMING_CFG_0
− 0xFFF22108
DDR SDRAM Timing Configuration 1
M2TIMING_CFG_1
− 0xFFF2210C
DDR SCRAM Timing Configuration 2
M2TIMING_CFG_2
− 0xFFF22110
DDR SDRAM Control Configuration
M2DDR_SDRAM_CFG
− 0xFFF22114
DDR SDRAM Control Configuration 2
M2DDR_SDRAM_CFG_2
− 0xFFF22118
DDR SDRAM Mode Configuration
M2DDR_SDRAM_MODE
− 0xFFF2211C
DDR SDRAM Mode Configuration 2
M2DDR_SDRAM_MODE_2
− 0xFFF22120
DDR SDRAM Mode Control
M2DDR_SCRAM_MD_CNTL
− 0xFFF22124
DDR SDRAM Interval Configuration
M2DDR_SDRAM_INTERVAL
− 0xFFF22128
DDR SDRAM Data Initialization
M2DDR_DATA_INIT
− 0xFFF2212C–
0xFFF2212F
reserved
− 0xFFF22130
DDR SDRAM Clock Control
− 0xFFF22134–
0xFFF22147
reserved
− 0xFFF22148
DDR SDRAM Initialization Address
M2DDR_INIT_ADDRESS
− 0xFFF2214C
DDR Initialization Enable Extended Address
M2DDR_INIT_ENXT_ADDR
− 0xFFF22150–
0xFFF2215F
reserved
− 0xFFF22160
DDR SDRAM Timing Configuration 4
M2TIMING_CFG_4
− 0xFFF22164
DDR SDRAM Timing Configuration 5
M2TIMING_CFG_5
− 0xFFF22168–
0xFFF2216F
reserved
− 0xFFF22170
DDR ZQ Calibration Control
M2DDR_ZQ_CNTL
− 0xFFF22174
DDR Write Leveling Control
M2DDR_WRLVL_CNTL
− 0xFFF22178
DDR Pre-Drive Conditioning Control
M2DDR_PD_CNTL
− 0xFFF2217C
DDR Self Refresh Counter
M2DDR_SR_CNTR
M2CS0_BNDS
M2CS1_BNDS
M2DDR_SDRAM_CLK_CNT
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-31
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF22180
DDR SDRAM Register Control Words 1
M2DDR_SDRAM_RCW_1
− 0xFFF22184
DDR SDRAM Register Control Words 2
M2DDR_SDRAM_RCW_2
− 0xFFF22188–
0xFFF2218F
reserved
− 0xFFF22190
DDR Write Leveling Control 2
M2DDR_WRLVL_CNTL_2
− 0xFFF22194
DDR Write Leveling Control 3
M2DDR_WRLVL_CNTL_3
− 0xFFF22198–
0xFFF22B1F
reserved
− 0xFFF22B20
DDR Debug Status Register 1
M2DDRDSR_1
− 0xFFF22B24
DDR Debug Status Register 2
M2DDRDSR_2
− 0xFFF22B28
DDR Control Driver Register 1
M2DDRCDR_1
− 0xFFF22B2C
DDR Control Driver Register 2
M2DDRCDR_2
− 0xFFF22B30–
0xFFF22BF7
reserved
− 0xFFF22BF8
DDR IP Block Revision 1
M2DDR_IP_REV1
− 0xFFF22BFC
DDR IP Block Revision 2
M2DDR_IP_REV2
− 0xFFF22C00–
0xFFF22DFF
reserved
− 0xFFF22E00
Memory Data Path Error Injection Mask High
M2DDR_ERR_INJECT_HI
− 0xFFF22E04
Memory Data Path Error Injection Mask Low
M2DDR_ERR_INJECT_LO
− 0xFFF22E08
Memory Data Path Error Injection Mask ECC
M2DDR_ERR_INJECT
− 0xFFF22E0C–
0xFFF22E1F
reserved
− 0xFFF22E20
Memory Data Path Read Capture High
M2CAPTURE_DATA_HI
− 0xFFF22E24
Memory Data Path Read Capture Low
M2CAPTURE-DATA_LO
− 0xFFF22E28
Memory Data Path Read Capture ECC
M2CAPTURE_ECC
− 0xFFF22E2C–
0xFFF22E3F
reserved
− 0xFFF22E40
Memory Error Detect
M2ERR_DETECT
− 0xFFF22E44
Memory Error Disable
M2ERR_DISABLE
− 0xFFF22E48
Memory Error Interrupt Enable
M2ERR_INT_EN
− 0xFFF22E4C
Memory Error Attributes Capture
M2CAPTURE_ATTRIBUTES
− 0xFFF22E50
Memory Error Address Capture
M2CAPTURE_ADDRESS
− 0xFFF22E54–
0xFFF22E57
reserved
− 0xFFF22E58
Single-Bit ECC Memory Error Management
− 0xFFF22E5C–
0xFFF22F03
reserved
− 0xFFF22F04
Debug Register 2
− 0xFFF22F08–
0xFFF23FFF
reserved
• 0xFFF24000–
0xFFF2407F
− 0xFFF24000
M2ERR_SBE
M2DEBUG_2
Clocks
System Clock Control Register
SCCR
MSC8156 Reference Manual, Rev. 2
9-32
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF24004
Clock General Purpose Register 0
− 0xFFF24008–
0xFFF2407F
reserved
• 0xFFF24080–
0xFFF247FF
reserved
• 0xFFF24800–
0xFFF248FF
Reset
Acronym
CLK_GPR0
− 0xFFF24800
Reset Configuration Word Low Register
RCWLR
− 0xFFF24804
Reset Configuration Word High Register
RCWHR
− 0xFFF24808–
0xFFF2480F
reserved
− 0xFFF24810
Reset Status Register
− 0xFFF24814–
0xFFF24817
reserved
− 0xFFF24818
Reset Protection Register
RPR
− 0xFFF2481C
Reset Control Register
RCR
− 0xFFF24820
Reset Control Enable Register
RCER
− 0xFFF24824–
0xFFF248FF
reserved
• 0xFFF24900–
0xFFF24BFF
reserved
• 0xFFF24C00–
0xFFF24CFF
I2 C
− 0xFFF24C00
I2C Address Register
2C
RSR
I2CADR
− 0xFFF24C04
I
− 0xFFF24C08
I2C Control Register
I2CCR
− 0xFFF24C0C
I2C Status Register
I2CSR
Frequency Divider Register
I2CFDR
I
2C
Data Register
I2CDR
− 0xFFF24C14
I
2C
Digital Filter Sampling Rate Register
I2CDFSRR
− 0xFFF24C18–
0xFFF24CFF
reserved
− 0xFFF24C10
• 0xFFF24D00–
0xFFF24FFF
reserved
• 0xFFF25000–
0xFFF250FF
Watchdog Timer 0
− 0xFFF25000–
0xFFF25003
reserved
− 0xFFF25004
System Watchdog Control Register 0
SWCRR0
− 0xFFF25008
System Watchdog Count Register 0
SWCNR0
− 0xFFF2500C–
0xFFF2500D
reserved
− 0xFFF2500E
System Watchdog Service Register 0
− 0xFFF25010–
0xFFF250FF
reserved
• 0xFFF25100–
0xFFF251FF
SWSRR0
Watchdog Timer 1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-33
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF25100–
0xFFF25103
reserved
− 0xFFF25104
System Watchdog Control Register 1
SWCRR1
− 0xFFF25108
System Watchdog Count Register 1
SWCNR1
− 0xFFF2510C–
0xFFF2510D
reserved
− 0xFFF2510E
System Watchdog Service Register 1
− 0xFFF25110–
0xFFF251FF
reserved
• 0xFFF25200–
0xFFF252FF
SWSRR1
Watchdog Timer 2
− 0xFFF25200–
0xFFF25203
reserved
− 0xFFF25204
System Watchdog Control Register 2
SWCRR2
− 0xFFF25208
System Watchdog Count Register 2
SWCNR2
− 0xFFF2520C–
0xFFF2520D
reserved
− 0xFFF2520E
System Watchdog Service Register 2
− 0xFFF25210–
0xFFF252FF
reserved
• 0xFFF25300–
0xFFF253FF
SWSRR2
Watchdog Timer 3
− 0xFFF25300–
0xFFF25303
reserved
− 0xFFF25304
System Watchdog Control Register 3
SWCRR3
− 0xFFF25308
System Watchdog Count Register 3
SWCNR3
− 0xFFF2530C–
0xFFF2530D
reserved
− 0xFFF2530E
System Watchdog Service Register 3
− 0xFFF25310–
0xFFF253FF
reserved
• 0xFFF25400–
0xFFF254FF
SWSRR3
Watchdog Timer 4
− 0xFFF25400–
0xFFF25403
reserved
− 0xFFF25404
System Watchdog Control Register 4
SWCRR4
− 0xFFF25408
System Watchdog Count Register 4
SWCNR4
− 0xFFF2540C–
0xFFF2540D
reserved
− 0xFFF2540E
System Watchdog Service Register 4
− 0xFFF25410–
0xFFF254FF
reserved
• 0xFFF25500–
0xFFF255FF
− 0xFFF25500–
0xFFF25503
SWSRR4
Watchdog Timer 5
reserved
MSC8156 Reference Manual, Rev. 2
9-34
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF25504
System Watchdog Control Register 5
SWCRR5
− 0xFFF25508
System Watchdog Count Register 5
SWCNR5
− 0xFFF2550C–
0xFFF2550D
reserved
− 0xFFF2550E
System Watchdog Service Register 5
− 0xFFF25510–
0xFFF255FF
reserved
• 0xFFF25600–
0xFFF256FF
SWSRR5
Watchdog Timer 6
− 0xFFF25600–
0xFFF25603
reserved
− 0xFFF25604
System Watchdog Control Register 6
SWCRR6
− 0xFFF25608
System Watchdog Count Register 6
SWCNR6
− 0xFFF2560C–
0xFFF2560D
reserved
− 0xFFF2560E
System Watchdog Service Register 6
− 0xFFF25610–
0xFFF256FF
reserved
• 0xFFF25700–
0xFFF257FF
SWSRR6
Watchdog Timer 7
− 0xFFF25700–
0xFFF25703
reserved
− 0xFFF25704
System Watchdog Control Register 7
SWCRR7
− 0xFFF25708
System Watchdog Count Register 7
SWCNR7
− 0xFFF2570C–
0xFFF2570D
reserved
− 0xFFF2570E
System Watchdog Service Register 7
− 0xFFF25710–
0xFFF257FF
reserved
• 0xFFF25800–
0xFFF25FFF
reserved
• 0xFFF26000–
0xFFF260FF
Timer 0
SWSRR7
− 0xFFF26000
Timer 0 Channel 0 Compare 1 Register
TMR0CMP10
− 0xFFF26004
Timer 0 Channel 0 Compare 2 Register
TMR0CMP20
− 0xFFF26008
Timer 0 Channel 0 Capture Register
TMR0CAP0
− 0xFFF2600C
Timer 0 Channel 0 Load Register
TMR0LD0
− 0xFFF26010
Timer 0 Channel 0 Hold Register
TMR0HOLD0
− 0xFFF26014
Timer 0 Channel 0 Counter Register
TMR0CNTR0
− 0xFFF26018
Timer 0 Channel 0 Control Register
TMR0CTL0
− 0xFFF2601C
Timer 0 Channel 0 Status and Control Register
TMR0SCTL0
− 0xFFF26020
Timer 0 Channel 0 Compare Load 1 Register
TMR0CMPLD10
− 0xFFF26024
Timer 0 Channel 0 Compare Load 2 Register
TMR0CMPLD20
− 0xFFF26028
Timer 0 Channel 0 Comparator Status and Control Register
TMR0COMSC0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-35
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF2602C–
0xFFF2603F
reserved
− 0xFFF26040
Timer 0 Channel 1 Compare 1 Register
TMR0CMP11
− 0xFFF26044
Timer 0 Channel 1 Compare 2 Register
TMR0CMP21
− 0xFFF26048
Timer 0 Channel 1 Capture Register
TMR0CAP1
− 0xFFF2604C
Timer 0 Channel 1 Load Register
TMR0LOAD1
− 0xFFF26050
Timer 0 Channel 1 Hold Register
TMR0HOLD1
− 0xFFF26054
Timer 0 Channel 1 Counter Register
TMR0CNTR1
− 0xFFF26058
Timer 0 Channel 1 Control Register
TMR0CTL1
− 0xFFF2605C
Timer 0 Channel 1 Status and Control Register
TMR0SCTL1
− 0xFFF26060
Timer 0 Channel 1 Compare Load 1 Register
TMR0CMPLD11
− 0xFFF26064
Timer 0 Channel 1 Compare Load 2 Register
TMR0CMPLD21
− 0xFFF26068
Timer 0 Channel 1 Comparator Status and Control Register
TMR0COMSC1
− 0xFFF2606C–
0xFFF2607F
reserved
− 0xFFF26080
Timer 0 Channel 2 Compare 1 Register
TMR0CMP12
− 0xFFF26084
Timer 0 Channel 2 Compare 2 Register
TMR0CMP22
− 0xFFF26088
Timer 0 Channel 2 Capture Register
TMR0CAP2
− 0xFFF2608C
Timer 0 Channel 2 Load Register
TMR0LOAD2
− 0xFFF26090
Timer 0 Channel 2 Hold Register
TMR0HOLD2
− 0xFFF26094
Timer 0 Channel 2 Counter Register
TMR0CNTR2
− 0xFFF26098
Timer 0 Channel 2 Control Register
TMR0CTL2
− 0xFFF2609C
Timer 0 Channel 2 Status and Control Register
TMR0SCTL2
− 0xFFF260A0
Timer 0 Channel 2 Compare Load 1 Register
TMR0CMPLD12
− 0xFFF260A4
Timer 0 Channel 2 Compare Load 2 Register
TMR0CMPLD22
− 0xFFF260A8
Timer 0 Channel 2 Comparator Status and Control Register
TMR0COMSC2
− 0xFFF260AC–
0xFFF260BF
reserved
− 0xFFF260C0
Timer 0 Channel 3 Compare 1 Register
TMR0CMP13
− 0xFFF260C4
Timer 0 Channel 3 Compare 2 Register
TMR0CMP23
− 0xFFF260C8
Timer 0 Channel 3 Capture Register
TMR0CAP3
− 0xFFF260CC
Timer 0 Channel 3 Load Register
TMR0LOAD3
− 0xFFF260D0
Timer 0 Channel 3 Hold Register
TMR0HOLD3
− 0xFFF260D4
Timer 0 Channel 3 Counter Register
TMR0CNTR3
− 0xFFF260D8
Timer 0 Channel 3 Control Register
TMR0CTL3
− 0xFFF260DC
Timer 0 Channel 3 Status and Control Register
TMR0SCTL3
− 0xFFF260E0
Timer 0 Channel 3 Compare Load 1 Register
TMR0CMPLD13
− 0xFFF260E4
Timer 0 Channel 3 Compare Load 2 Register
TMR0CMPLD23
− 0xFFF260E8
Timer 0 Channel 3 Comparator Status and Control Register
TMR0COMSC3
− 0xFFF260EC–
0xFFF260FF
reserved
• 0xFFF26100–
0xFFF261FF
Timer 1
MSC8156 Reference Manual, Rev. 2
9-36
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF26100
Timer 1 Channel 0 Compare 1 Register
TMR1CMP10
− 0xFFF26104
Timer 1 Channel 0 Compare 2 Register
TMR1CMP20
− 0xFFF26108
Timer 1 Channel 0 Capture Register
TMR1CAP0
− 0xFFF2610C
Timer 1 Channel 0 Load Register
TMR1LOAD0
− 0xFFF26110
Timer 1 Channel 0 Hold Register
TMR1HOLD0
− 0xFFF26114
Timer 1 Channel 0 Counter Register
TMR1CNTR0
− 0xFFF26118
Timer 1 Channel 0 Control Register
TMR1CTL0
− 0xFFF2611C
Timer 1 Channel 0 Status and Control Register
TMR1SCTL0
− 0xFFF26120
Timer 1 Channel 0 Compare Load 1 Register
TMR1CMPLD10
− 0xFFF26124
Timer 1 Channel 0 Compare Load 2 Register
TMR1CMPLD20
− 0xFFF26128
Timer 1 Channel 0 Comparator Status and Control Register
TMR1COMSC0
− 0xFFF2612C–
0xFFF2613F
reserved
− 0xFFF26140
Timer 1 Channel 1 Compare 1 Register
TMR1CMP11
− 0xFFF26144
Timer 1 Channel 1 Compare 2 Register
TMR1CMP21
− 0xFFF26148
Timer 1 Channel 1 Capture Register
TMR1CAP1
− 0xFFF2614C
Timer 1 Channel 1 Load Register
TMR1LOAD1
− 0xFFF26150
Timer 1 Channel 1 Hold Register
TMR1HOLD1
− 0xFFF26154
Timer 1 Channel 1 Counter Register
TMR1CNTR1
− 0xFFF26158
Timer 1 Channel 1 Control Register
TMR1CTL1
− 0xFFF2615C
Timer 1 Channel 1 Status and Control Register
TMR1SCTL1
− 0xFFF26160
Timer 1 Channel 1 Compare Load 1 Register
TMR1CMPLD11
− 0xFFF26164
Timer 1 Channel 1 Compare Load 2 Register
TMR1CMPLD21
− 0xFFF26168
Timer 1 Channel 1 Comparator Status and Control Register
TMR1COMSC1
− 0xFFF2616C–
0xFFF2617F
reserved
− 0xFFF26180
Timer 1 Channel 2 Compare 1 Register
TMR1CMP12
− 0xFFF26184
Timer 1 Channel 2 Compare 2 Register
TMR1CMP22
− 0xFFF26188
Timer 1 Channel 2 Capture Register
TMR1CAP2
− 0xFFF2618C
Timer 1 Channel 2 Load Register
TMR1LOAD2
− 0xFFF26190
Timer 1 Channel 2 Hold Register
TMR1HOLD2
− 0xFFF26194
Timer 1 Channel 2 Counter Register
TMR1CNTR2
− 0xFFF26198
Timer 1 Channel 2 Control Register
TMR1CTL2
− 0xFFF2619C
Timer 1 Channel 2 Status and Control Register
TMR1SCTL2
− 0xFFF261A0
Timer 1 Channel 2 Compare Load 1 Register
TMR1CMPLD12
− 0xFFF261A4
Timer 1 Channel 2 Compare Load 2 Register
TMR1CMPLD22
− 0xFFF261A8
Timer 1 Channel 2 Comparator Status and Control Register
TMR1COMSC2
− 0xFFF261AC–
0xFFF261BF
reserved
− 0xFFF261C0
Timer 1 Channel 3 Compare 1 Register
TMR1CMP13
− 0xFFF261C4
Timer 1 Channel 3 Compare 2 Register
TMR1CMP23
− 0xFFF261C8
Timer 1 Channel 3 Capture Register
TMR1CAP3
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-37
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF261CC
Timer 1 Channel 3 Load Register
TMR1LOAD3
− 0xFFF261D0
Timer 1 Channel 3 Hold Register
TMR1HOLD3
− 0xFFF261D4
Timer 1 Channel 3 Counter Register
TMR1CNTR3
− 0xFFF261D8
Timer 1 Channel 3 Control Register
TMR1CTL3
− 0xFFF261DC
Timer 1 Channel 3 Status and Control Register
TMR1SCTL3
− 0xFFF261E0
Timer 1 Channel 3 Compare Load 1 Register
TMR1CMPLD13
− 0xFFF261E4
Timer 1 Channel 3 Compare Load 2 Register
TMR1CMPLD23
− 0xFFF261E8
Timer 1 Channel 3 Comparator Status and Control Register
TMR1COMSC3
− 0xFFF261EC–
0xFFF261FF
reserved
• 0xFFF26200–
0xFFF262FF
Timer 2
− 0xFFF26200
Timer 2 Channel 0 Compare 1 Register
TMR2CMP10
− 0xFFF26204
Timer 2 Channel 0 Compare 2 Register
TMR2CMP20
− 0xFFF26208
Timer 2 Channel 0 Capture Register
TMR2CAP0
− 0xFFF2620C
Timer 2 Channel 0 Load Register
TMR2LOAD0
− 0xFFF26210
Timer 2 Channel 0 Hold Register
TMR2HOLD0
− 0xFFF26214
Timer 2 Channel 0 Counter Register
TMR2CNTR0
− 0xFFF26218
Timer 2 Channel 0 Control Register
TMR2CTL0
− 0xFFF2621C
Timer 2 Channel 0 Status and Control Register
TMR2SCTL0
− 0xFFF26220
Timer 2 Channel 0 Compare Load 1 Register
TMR2CMPLD10
− 0xFFF26224
Timer 2 Channel 0 Compare Load 2 Register
TMR2CMPLD20
− 0xFFF26228
Timer 2 Channel 0 Comparator Status and Control Register
TMR2COMSC0
− 0xFFF2622C–
0xFFF2623F
reserved
− 0xFFF26240
Timer 2 Channel 1 Compare 1 Register
TMR2CMP11
− 0xFFF26244
Timer 2 Channel 1 Compare 2 Register
TMR2CMP21
− 0xFFF26248
Timer 2 Channel 1 Capture Register
TMR2CAP1
− 0xFFF2624C
Timer 2 Channel 1 Load Register
TMR2LOAD1
− 0xFFF26250
Timer 2 Channel 1 Hold Register
TMR2HOLD1
− 0xFFF26254
Timer 2 Channel 1 Counter Register
TMR2CNTR1
− 0xFFF26258
Timer 2 Channel 1 Control Register
TMR2CTL1
− 0xFFF2625C
Timer 2 Channel 1 Status and Control Register
TMR2SCTL1
− 0xFFF26260
Timer 2 Channel 1 Compare Load 1 Register
TMR2CMPLD11
− 0xFFF26264
Timer 2 Channel 1 Compare Load 2 Register
TMR2CMPLD21
− 0xFFF26268
Timer 2 Channel 1 Comparator Status and Control Register
TMR2COMSC1
− 0xFFF2626C–
0xFFF2627F
reserved
− 0xFFF26280
Timer 2 Channel 2 Compare 1 Register
TMR2CMP12
− 0xFFF26284
Timer 2 Channel 2 Compare 2 Register
TMR2CMP22
− 0xFFF26288
Timer 2 Channel 2 Capture Register
TMR2CAP2
− 0xFFF2628C
Timer 2 Channel 2 Load Register
TMR2LOAD2
− 0xFFF26290
Timer 2 Channel 2 Hold Register
TMR2HOLD2
MSC8156 Reference Manual, Rev. 2
9-38
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF26294
Timer 2 Channel 2 Counter Register
TMR2CNTR2
− 0xFFF26298
Timer 2 Channel 2 Control Register
TMR2CTL2
− 0xFFF2629C
Timer 2 Channel 2 Status and Control Register
TMR2SCTL2
− 0xFFF262A0
Timer 2 Channel 2 Compare Load 1 Register
TMR2CMPLD12
− 0xFFF262A4
Timer 2 Channel 2 Compare Load 2 Register
TMR2CMPLD22
− 0xFFF262A8
Timer 2 Channel 2 Comparator Status and Control Register
TMR2COMSC2
− 0xFFF262AC–
0xFFF262BF
reserved
− 0xFFF262C0
Timer 2 Channel 3 Compare 1 Register
TMR2CMP13
− 0xFFF262C4
Timer 2 Channel 3 Compare 2 Register
TMR2CMP23
− 0xFFF262C8
Timer 2 Channel 3 Capture Register
TMR2CAP3
− 0xFFF262CC
Timer 2 Channel 3 Load Register
TMR2LOAD3
− 0xFFF262D0
Timer 2 Channel 3 Hold Register
TMR2HOLD3
− 0xFFF262D4
Timer 2 Channel 3 Counter Register
TMR2CNTR3
− 0xFFF262D8
Timer 2 Channel 3 Control Register
TMR2CTL3
− 0xFFF262DC
Timer 2 Channel 3 Status and Control Register
TMR2SCTL3
− 0xFFF262E0
Timer 2 Channel 3 Compare Load 1 Register
TMR2CMPLD13
− 0xFFF262E4
Timer 2 Channel 3 Compare Load 2 Register
TMR2CMPLD23
− 0xFFF262E8
Timer 2 Channel 3 Comparator Status and Control Register
TMR2COMSC3
− 0xFFF262EC–
0xFFF262FF
reserved
• 0xFFF26300–
0xFFF263FF
Timer 3
− 0xFFF26300
Timer 3 Channel 0 Compare 1 Register
TMR3CMP10
− 0xFFF26304
Timer 3 Channel 0 Compare 2 Register
TMR3CMP20
− 0xFFF26308
Timer 3 Channel 0 Capture Register
TMR3CAP0
− 0xFFF2630C
Timer 3 Channel 0 Load Register
TMR3LOAD0
− 0xFFF26310
Timer 3 Channel 0 Hold Register
TMR3HOLD0
− 0xFFF26314
Timer 3 Channel 0 Counter Register
TMR3CNTR0
− 0xFFF26318
Timer 3 Channel 0 Control Register
TMR3CTL0
− 0xFFF2631C
Timer 3 Channel 0 Status and Control Register
TMR3SCTL0
− 0xFFF26320
Timer 3 Channel 0 Load 1 Register
TMR3CMPLD10
− 0xFFF26324
Timer 3 Channel 0 Load 2 Register
TMR3CMPLD20
− 0xFFF26328
Timer 3 Channel 0 Comparator Status and Control Register
TMR3COMSC0
− 0xFFF2632C–
0xFFF2633F
reserved
− 0xFFF26340
Timer 3 Channel 1 Compare 1 Register
TMR3CMP11
− 0xFFF26344
Timer 3 Channel 1 Compare 2 Register
TMR3CMP21
− 0xFFF26348
Timer 3 Channel 1 Capture Register
TMR3CAP1
− 0xFFF2634C
Timer 3 Channel 1 Load Register
TMR3LOAD1
− 0xFFF26350
Timer 3 Channel 1 Hold Register
TMR3HOLD1
− 0xFFF26354
Timer 3 Channel 1 Counter Register
TMR3CNTR1
− 0xFFF26358
Timer 3 Channel 1 Control Register
TMR3CTL1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-39
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF2635C
Timer 3 Channel 1 Status and Control Register
TMR3SCTL1
− 0xFFF26360
Timer 3 Channel 1 Load 1 Register
TMR3CMPLD11
− 0xFFF26364
Timer 3 Channel 1 Load 2 Register
TMR3CMPLD21
− 0xFFF26368
Timer 3 Channel 1 Comparator Status and Control Register
TMR3COMSC1
− 0xFFF2636C–
0xFFF2637F
reserved
− 0xFFF26380
Timer 3 Channel 2 Compare 1 Register
TMR3CMP12
− 0xFFF26384
Timer 3 Channel 2 Compare 2 Register
TMR3CMP22
− 0xFFF26388
Timer 3 Channel 2 Capture Register
TMR3CAP2
− 0xFFF2638C
Timer 3 Channel 2 Load Register
TMR3LOAD2
− 0xFFF26390
Timer 3 Channel 2 Hold Register
TMR3HOLD2
− 0xFFF26394
Timer 3 Channel 2 Counter Register
TMR3CNTR2
− 0xFFF26398
Timer 3 Channel 2 Control Register
TMR3CTL2
− 0xFFF2639C
Timer 3 Channel 2 Status and Control Register
TMR3SCTL2
− 0xFFF263A0
Timer 3 Channel 2 Load 1 Register
TMR3CMPLD12
− 0xFFF263A4
Timer 3 Channel 2 Load 2 Register
TMR3CMPLD22
− 0xFFF263A8
Timer 3 Channel 2 Comparator Status and Control Register
TMR3COMSC2
− 0xFFF263AC–
0xFFF263BF
reserved
− 0xFFF263C0
Timer 3 Channel 3 Compare 1 Register
TMR3CMP13
− 0xFFF263C4
Timer 3 Channel 3 Compare 2 Register
TMR3CMP23
− 0xFFF263C8
Timer 3 Channel 3 Capture Register
TMR3CAP3
− 0xFFF263CC
Timer 3 Channel 3 Load Register
TMR3LOAD3
− 0xFFF263D0
Timer 3 Channel 3 Hold Register
TMR3HOLD3
− 0xFFF263D4
Timer 3 Channel 3 Counter Register
TMR3CNTR3
− 0xFFF263D8
Timer 3 Channel 3 Control Register
TMR3CTL3
− 0xFFF263DC
Timer 3 Channel 3 Status and Control Register
TMR3SCTL3
− 0xFFF263E0
Timer 3 Channel 3 Load 1 Register
TMR3CMPLD13
− 0xFFF263E4
Timer 3 Channel 3 Load 2 Register
TMR3CMPLD23
− 0xFFF263E8
Timer 3 Channel 3 Comparator Status and Control Register
TMR3COMSC3
− 0xFFF263EC–
0xFFF263FF
reserved
• 0xFFF26400–
0xFFF26BFF
reserved
• 0xFFF26C00–
0xFFF26C3F
UART
− 0xFFF26C00
SCI Baud-Rate Register
− 0xFFF26C04–
0xFFF26C07
reserved
− 0xFFF26C08
SCI Control Register
− 0xFFF26C0C–
0xFFF26C0F
reserved
− 0xFFF26C10
SCI Status Register
SCIBR
SCICR
SCISR
MSC8156 Reference Manual, Rev. 2
9-40
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF26C14–
0xFFF26C17
reserved
− 0xFFF26C18
SCI Data Register
− 0xFFF26C1C–
0xFFF26C27
reserved
− 0xFFF26C28
SCI Data Direction Register
− 0xFFF26C2C–
0xFFF26C3F
reserved
• 0xFFF26C40–
0xFFF26FFF
reserved
• 0xFFF27000–
0xFFF270FF
GIC
SCIDR
− 0xFFF27000
Virtual Interrupt Generation Register
− 0xFFF27004–
0xFFF27007
reserved
− 0xFFF27008
Virtual Interrupt Status Register
− 0xFFF2700C–
0xFFF270FF
reserved
• 0xFFF27100–
0xFFF271FF
SCIDDR
VIGR
VISR
Hardware Semaphores
− 0xFFF27100
Hardware Semaphore Register 0
− 0xFFF27104–
0xFFF27107
reserved
− 0xFFF27108
Hardware Semaphore Register 1
− 0xFFF2710C–
0xFFF2710F
reserved
− 0xFFF27110
Hardware Semaphore Register 2
− 0xFFF27114–
0xFFF27117
reserved
− 0xFFF27118
Hardware Semaphore Register 3
− 0xFFF2711C–
0xFFF2711F
reserved
− 0xFFF27120
Hardware Semaphore Register 4
− 0xFFF27124–
0xFFF27127
reserved
− 0xFFF27128
Hardware Semaphore Register 5
− 0xFFF2712C–
0xFFF2712F
reserved
− 0xFFF27130
Hardware Semaphore Register 6
− 0xFFF27134–
0xFFF27137
reserved
− 0xFFF27138
Hardware Semaphore Register 7
− 0xFFF2713C–
0xFFF271FF
reserved
• 0xFFF27200–
0xFFF272FF
Acronym
HSMPR0
HSMPR1
HSMPR2
HSMPR3
HSMPR4
HSMPR5
HSMPR6
HSMPR7
GPIO
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-41
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF27200
Pin Open-Drain Register
− 0xFFF27204–
0xFFF27207
reserved
− 0xFFF27208
Pin Data Register
− 0xFFF2720C–
0xFFF2720F
reserved
− 0xFFF27210
Pin Data Direction Register
− 0xFFF27214–
0xFFF27217
reserved
− 0xFFF27218
Pin Assignment Register
− 0xFFF2721C–
0xFFF2721F
reserved
− 0xFFF27220
Pin Special Options Register
− 0xFFF27224–
0xFFF272FF
reserved
PODR
PDAT
• 0xFFF27300–
0xFFF27FFF
reserved
• 0xFFF28000–
0xFFF281FF
General Configuration Registers
− 0xFFF28000
Acronym
General Configuration Register 1
PDIR
PAR
PSOR
GCR1
− 0xFFF28004
General Configuration Register 2
GCR2
− 0xFFF28008
General Status Register 1
GSR1
− 0xFFF2800C
High Speed Serial Interface Status Register
HSSI_SR
− 0xFFF28010
DDR General Configuration Register
DDR_GCR
− 0xFFF28014
High Speed Serial Interface Control Register 1
HSSI_CR1
− 0xFFF28018
High Speed Serial Interface Control Register 2
HSSI_CR2
− 0xFFF2801C
QUICC Engine Control Register
QECR
− 0xFFF28020
GPIO Pull-Up Enable Register
GPUER
− 0xFFF28024
GPIO Input Enable Register
GIER
− 0xFFF28028
System Part and Revision ID Register
SPRIDR
− 0xFFF2802C–
0xFFF2802F
reserved
− 0xFFF28030
General Control Register 4
GCR4
− 0xFFF28034
General Control Register 5
GCR5
− 0xFFF28038
General Status Register 2
GSR2
− 0xFFF2803C
Core Subsystem Slave Port Priority Control Register
TSPPCR
− 0xFFF28040
QUICC Engine First External Request Multiplex Register
CPCE1R
− 0xFFF28044
QUICC Engine Second External Request Multiplex Register
CPCE2R
− 0xFFF28048
QUICC Engine Third External Request Multiplex Register
CPCE3R
− 0xFFF2804C
QUICC Engine Fourth External Request Multiplex Register
CPCE4R
− 0xFFF28050–
0xFFF28073
reserved
− 0xFFF28074
General Control Register 10
GCR10
MSC8156 Reference Manual, Rev. 2
9-42
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF28078–
0xFFF2807F
reserved
− 0xFFF28080
General Interrupt Register 1
GIR1
− 0xFFF28084
General Interrupt Enable Register 1 for Core 0
GIER1_0
− 0xFFF28088
General Interrupt Enable Register 1 for Core 1
GIER1_1
− 0xFFF2808C
General Interrupt Enable Register 1 for Core 2
GIER1_2
− 0xFFF28090
General Interrupt Enable Register 1 for Core 3
GIER1_3
− 0xFFF28094
General Interrupt Enable Register 1 for Core 4
GIER1_4
− 0xFFF28098
General Interrupt Enable Register 1 for Core 5
GIER1_5
− 0xFFF2809C–
0xFFF280A3
reserved
− 0xFFF280A4
General Interrupt Register 3
GIR3
− 0xFFF280A8
General Interrupt Enable Register 3 for Core 0
GIER3_0
− 0xFFF280AC
General Interrupt Enable Register 3 for Core 1
GIER3_1
− 0xFFF280B0
General Interrupt Enable Register 3 for Core 2
GIER3_2
− 0xFFF280B4
General Interrupt Enable Register 3 for Core 3
GIER3_3
− 0xFFF280B8
General Interrupt Enable Register 3 for Core 4
GIER3_4
− 0xFFF280BC
General Interrupt Enable Register 3 for Core 5
GIER3_5
− 0xFFF280C0–
0xFFF280EB
reserved
− 0xFFF280EC
General Interrupt Register 5
GIR5
− 0xFFF280F0
General Interrupt Enable Register 5 for Core 0
GIER5_0
− 0xFFF280F4
General Interrupt Enable Register 5 for Core 1
GIER5_1
− 0xFFF280F8
General Interrupt Enable Register 5 for Core 2
GIER5_2
− 0xFFF280FC
General Interrupt Enable Register 5 for Core 3
GIER5_3
− 0xFFF28100
General Interrupt Enable Register 5 for Core 4
GIER5_4
− 0xFFF28104
General Interrupt Enable Register 5 for Core 5
GIER5_5
− 0xFFF28108–
0xFFF2810F
reserved
− 0xFFF28110
General Control Register 11
GCR11
− 0xFFF28114
General Control Register 12
GCR12
− 0xFFF28118–
0xFFF2811F
reserved
− 0xFFF28120
DMA Request0 Control Register
GCR_DREQ0
− 0xFFF28124
DMA Request1 Control Register
GCR_DREQ1
− 0xFFF28128
DMA Done Control Register
GCR_DDONE
− 0xFFF2812C
DDR1 General Configuration Register
DDR1_GCR
− 0xFFF28130
DDR2 General Configuration Register
DDR2_GCR
− 0xFFF28134–
0xFFF28137
reserved
− 0xFFF28138
Core Subsystem Slave Port General Configuration Register
− 0xFFF2813C–
0xFFF281FF
reserved
CORE_SLV_GCR
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-43
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
• 0xFFF28200–
0xFFF2FFFF
reserved
• 0xFFF30000–
0xFFF33FFF
TDM0
− 0xFFF30000–
0xFFF307FF
TDM0 Receive Local Memory
− 0xFFF30800–
0xFFF30FFF
reserved
− 0xFFF31000–
0xFFF313FC
TDM0 Receive Channel Parameters Register 0–255
− 0xFFF31400–
0xFFF317FF
reserved
− 0xFFF31800–
0xFFF31FFF
TDM0 Transmit Local Memory
− 0xFFF32000–
0xFFF327FF
reserved
− 0xFFF32800–
0xFFF32BFC
TDM0 Transmit Channel Parameters Register 0–255
− 0xFFF32C00–
0xFFF33EFF
reserved
− 0xFFF33F00
TDM0 Parity Control Register
− 0xFFF33F04–
0xFFF33F07
reserved
− 0xFFF33F08
TDM0 Parity Error Register
− 0xFFF33F0C–
0xFFF33F0F
reserved
− 0xFFF33F10
TDM0 Transmit Force Register
− 0xFFF33F14–
0xFFF33F17
reserved
− 0xFFF33F18
TDM0 Receive Force Register
− 0xFFF33F1C–
0xFFF33F1F
reserved
− 0xFFF33F20
TDM0 Transmit Status Register
− 0xFFF33F24–
0xFFF33F27
reserved
− 0xFFF33F28
TDM0 Receive Status Register
− 0xFFF33F2C–
0xFFF33F2F
reserved
− 0xFFF33F30
TDM0 Adaptation Status Register
− 0xFFF33F34–
0xFFF33F37
reserved
− 0xFFF33F38
TDM0 Transmit Event Register
− 0xFFF33F3C–
0xFFF33F3F
reserved
− 0xFFF33F40
TDM0 Receive Event Register
− 0xFFF33F44–
0xFFF33F47
reserved
Acronym
TDM0RCPR[0–255]
TDM0TCPR[0–255]
TDM0PCR
TDM0PER
TDM0TFR
TDM0RFR
TDM0TSR
TDM0RSR
TDM0ASR
TDM0TER
TDM0RER
MSC8156 Reference Manual, Rev. 2
9-44
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF33F48
TDM0 Transmit Number of Buffers
− 0xFFF33F4C–
0xFFF33F4F
reserved
− 0xFFF33F50
TDM0 Receive Number of Buffers
− 0xFFF33F54–
0xFFF33F57
reserved
− 0xFFF33F58
TDM0 Transmit Data Buffer Displacement Register
− 0xFFF33F5C–
0xFFF33F5F
reserved
− 0xFFF33F60
TDM0 Receive Data Buffer Displacement Register
− 0xFFF33F64–
0xFFF33F67
reserved
− 0xFFF33F68
TDM0 Adaptation Sync Distance Register
− 0xFFF33F6C–
0xFFF33F6F
reserved
− 0xFFF33F70
TDM0 Transmit Interrupt Enable Register
− 0xFFF33F74–
0xFFF33F77
reserved
− 0xFFF33F78
TDM0 Receive Interrupt Enable Register
− 0xFFF33F7C–
0xFFF33F7F
reserved
− 0xFFF33F80
TDM0 Transmit Data Buffer Second Threshold
− 0xFFF33F84–
0xFFF33F87
reserved
− 0xFFF33F88
TDM0 Receive Data Buffer Second Threshold
− 0xFFF33F8C–
0xFFF33F8F
reserved
− 0xFFF33F90
TDM0 Transmit Data Buffer First Threshold
− 0xFFF33F94–
0xFFF33F97
reserved
− 0xFFF33F98
TDM0 Receive Data Buffer First Threshold
− 0xFFF33F9C–
0xFFF33F9F
reserved
− 0xFFF33FA0
TDM0 Transmit Control Register
− 0xFFF33FA4–
0xFFF33FA7
reserved
− 0xFFF33FA8
TDM0 Receive Control Register
− 0xFFF33FAC–
0xFFF33FAF
reserved
− 0xFFF33FB0
TDM0 Adaptation Control Register
− 0xFFF33FB4–
0xFFF33FB7
reserved
− 0xFFF33FB8
TDM0 Transmit Global Base Address
− 0xFFF33FBC–
0xFFF33FBF
reserved
− 0xFFF33FC0
TDM0 Receive Global Base Address
Acronym
TDM0TNB
TDM0RNB
TDM0TDBDR
TDM0RDBDR
TDM0ASDR
TDM00TIER
TDM0RIER
TDM0TDBST
TDM0RDBST
TDM0TDBFT
TDM0RDBFT
TDM0TCR
TDM0RCR
TDM0ACR
TDM0TGBA
TDM0RGBA
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-45
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF33FC4–
0xFFF33FC7
reserved
− 0xFFF33FC8
TDM0 Transmit Data Buffer Size
− 0xFFF33FCC–
0xFFF33FCF
reserved
− 0xFFF33FD0
TDM0 Receive Data Buffer Size
− 0xFFF33FD4–
0xFFF33FD7
reserved
− 0xFFF33FD8
TDM0 Transmit Frame Parameters
− 0xFFF33FDC–
0xFFF33FDF
reserved
− 0xFFF33FE0
TDM0 Receive Frame Parameters
− 0xFFF33FE4–
0xFFF33FE7
reserved
− 0xFFF33FE8
TDM0 Transmit Interface Register
− 0xFFF33FEC–
0xFFF33FEF
reserved
− 0xFFF33FF0
TDM0 Receive Interface Register
− 0xFFF33FF4–
0xFFF33FF7
reserved
− 0xFFF33FF8
TDM0 General Interface Register
− 0xFFF33FFC–
0xFFF33FFF
reserved
• 0xFFF34000–
0xFFF37FFF
Acronym
TDM0TDBS
TDM0RDBS
TDM0TFP
TDM0RFP
TDM0TIR
TDM0RIR
TDM0GIR
TDM1
− 0xFFF34000–
0xFFF347FF
TDM1 Receive Local Memory
− 0xFFF34800–
0xFFF34FFF
reserved
− 0xFFF35000–
0xFFF353FC
TDM1 Receive Channel Parameters Register 0–255
− 0xFFF35400–
0xFFF357FF
reserved
− 0xFFF35800–
0xFFF35FFF
TDM1 Transmit Local Memory
− 0xFFF36000–
0xFFF367FF
reserved
− 0xFFF36800–
0xFFF36BFC
TDM1 Transmit Channel Parameters Register 0–255
− 0xFFF36C00–
0xFFF37EFF
reserved
− 0xFFF37F00
TDM1 Parity Control Register
− 0xFFF37F04–
0xFFF37F07
reserved
− 0xFFF37F08
TDM1 Parity Error Register
− 0xFFF37F0C–
0xFFF37F0F
reserved
TDM1RCPR[0–255]
TDM1TCPR[0–255]
TDM1PCR
TDM1PER
MSC8156 Reference Manual, Rev. 2
9-46
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF37F10
TDM1 Transmit Force Register
− 0xFFF37F14–
0xFFF37F17
reserved
− 0xFFF37F18
TDM1 Receive Force Register
− 0xFFF37F1C–
0xFFF37F1F
reserved
− 0xFFF37F20
TDM1 Transmit Status Register
− 0xFFF37F24–
0xFFF37F27
reserved
− 0xFFF37F28
TDM1 Receive Status Register
− 0xFFF37F2C–
0xFFF37F2F
reserved
− 0xFFF37F30
TDM1 Adaptation Status Register
− 0xFFF37F34–
0xFFF37F37
reserved
− 0xFFF37F38
TDM1 Transmit Event Register
− 0xFFF37F3C–
0xFFF37F3F
reserved
− 0xFFF37F40
TDM1 Receive Event Register
− 0xFFF37F44–
0xFFF37F47
reserved
− 0xFFF37F48
TDM1 Transmit Number of Buffers
− 0xFFF37F4C–
0xFFF37F4F
reserved
− 0xFFF37F50
TDM1 Receive Number of Buffers
− 0xFFF37F54–
0xFFF37F57
reserved
− 0xFFF37F58
TDM1 Transmit Data Buffer Displacement Register
− 0xFFF37F5C–
0xFFF37F5F
reserved
− 0xFFF37F60
TDM1 Receive Data Buffer Displacement Register
− 0xFFF37F64–
0xFFF37F67
reserved
− 0xFFF37F68
TDM1 Adaptation Sync Distance Register
− 0xFFF37F6C–
0xFFF37F6F
reserved
− 0xFFF37F70
TDM1 Transmit Interrupt Enable Register
− 0xFFF37F74–
0xFFF37F77
reserved
− 0xFFF37F78
TDM1 Receive Interrupt Enable Register
− 0xFFF37F7C–
0xFFF37F7F
reserved
− 0xFFF37F80
TDM1 Transmit Data Buffer Second Threshold
− 0xFFF37F84–
0xFFF37F87
reserved
− 0xFFF37F88
TDM1 Receive Data Buffer Second Threshold
Acronym
TDM1TFR
TDM1RFR
TDM1TSR
TDM1RSR
TDM1ASR
TDM1TER
TDM1RER
TDM1TNB
TDM1RNB
TDM1TDBDR
TDM1RDBDR
TDM1ASDR
TDM10TIER
TDM1RIER
TDM1TDBST
TDM1RDBST
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-47
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF37F8C–
0xFFF37F8F
reserved
− 0xFFF37F90
TDM1 Transmit Data Buffer First Threshold
− 0xFFF37F94–
0xFFF37F97
reserved
− 0xFFF37F98
TDM1 Receive Data Buffer First Threshold
− 0xFFF37F9C–
0xFFF37F9F
reserved
− 0xFFF37FA0
TDM1 Transmit Control Register
− 0xFFF37FA4–
0xFFF37FA7
reserved
− 0xFFF37FA8
TDM1 Receive Control Register
− 0xFFF37FAC–
0xFFF37FAF
reserved
− 0xFFF37FB0
TDM1 Adaptation Control Register
− 0xFFF37FB4–
0xFFF37FB7
reserved
− 0xFFF37FB8
TDM1 Transmit Global Base Address
− 0xFFF37FBC–
0xFFF37FBF
reserved
− 0xFFF37FC0
TDM1 Receive Global Base Address
− 0xFFF37FC4–
0xFFF37FC7
reserved
− 0xFFF37FC8
TDM1 Transmit Data Buffer Size
− 0xFFF37FCC–
0xFFF37FCF
reserved
− 0xFFF37FD0
TDM1 Receive Data Buffer Size
− 0xFFF37FD4–
0xFFF37FD7
reserved
− 0xFFF37FD8
TDM1 Transmit Frame Parameters
− 0xFFF37FDC–
0xFFF37FDF
reserved
− 0xFFF37FE0
TDM1 Receive Frame Parameters
− 0xFFF37FE4–
0xFFF37FE7
reserved
− 0xFFF37FE8
TDM1 Transmit Interface Register
− 0xFFF37FEC–
0xFFF37FEF
reserved
− 0xFFF37FF0
TDM1 Receive Interface Register
− 0xFFF37FF4–
0xFFF37FF7
reserved
− 0xFFF37FF8
TDM1 General Interface Register
− 0xFFF37FFC–
0xFFF37FFF
reserved
• 0xFFF38000–
0xFFF3BFFF
Acronym
TDM1TDBFT
TDM1RDBFT
TDM1TCR
TDM1RCR
TDM1ACR
TDM1TGBA
TDM1RGBA
TDM1TDBS
TDM1RDBS
TDM1TFP
TDM1RFP
TDM1TIR
TDM1RIR
TDM1GIR
TDM2
MSC8156 Reference Manual, Rev. 2
9-48
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF38000–
0xFFF387FF
TDM2 Receive Local Memory
− 0xFFF38800–
0xFFF38FFF
reserved
− 0xFFF39000–
0xFFF393FC
TDM2 Receive Channel Parameters Register 0–255
− 0xFFF39400–
0xFFF397FF
reserved
− 0xFFF39800–
0xFFF39FFF
TDM2 Transmit Local Memory
− 0xFFF3A000–
0xFFF3A7FF
reserved
− 0xFFF3A800–
0xFFF3ABFC
TDM2 Transmit Channel Parameters Register 0–255
− 0xFFF3AC00–
0xFFF3BEFF
reserved
− 0xFFF3BF00
TDM2 Parity Control Register
− 0xFFF3BF04–
0xFFF3BF07
reserved
− 0xFFF3BF08
TDM2 Parity Error Register
− 0xFFF3BF0C–
0xFFF3BF0F
reserved
− 0xFFF3BF10
TDM2 Transmit Force Register
− 0xFFF3BF14–
0xFFF3BF17
reserved
− 0xFFF3BF18
TDM2 Receive Force Register
− 0xFFF3BF1C–
0xFFF3BF1F
reserved
− 0xFFF3BF20
TDM2 Transmit Status Register
− 0xFFF3BF24–
0xFFF3BF27
reserved
− 0xFFF3BF28
TDM2 Receive Status Register
− 0xFFF3BF2C–
0xFFF3BF2F
reserved
− 0xFFF3BF30
TDM2 Adaptation Status Register
− 0xFFF3BF34–
0xFFF38F37
reserved
− 0xFFF3BF38
TDM2 Transmit Event Register
− 0xFFF3BF3C–
0xFFF3BF3F
reserved
− 0xFFF3BF40
TDM2 Receive Event Register
− 0xFFF3BF44–
0xFFF3BF47
reserved
− 0xFFF3BF48
TDM2 Transmit Number of Buffers
− 0xFFF3BF4C–
0xFFF3BF4F
reserved
Acronym
TDM2RCPR[0–255]
TDM2TCPR[0–255]
TDM2PCR
TDM2PER
TDM2TFR
TDM2RFR
TDM2TSR
TDM2RSR
TDM2ASR
TDM2TER
TDM2RER
TDM2TNB
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-49
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF3BF50
TDM2 Receive Number of Buffers
− 0xFFF3BF54–
0xFFF3BF57
reserved
− 0xFFF3BF58
TDM2 Transmit Data Buffer Displacement Register
− 0xFFF3BF5C–
0xFFF3BF5F
reserved
− 0xFFF3BF60
TDM2 Receive Data Buffer Displacement Register
− 0xFFF3BF64–
0xFFF3BF67
reserved
− 0xFFF3BF68
TDM2 Adaptation Sync Distance Register
− 0xFFF3BF6C–
0xFFF3BF6F
reserved
− 0xFFF3BF70
TDM2 Transmit Interrupt Enable Register
− 0xFFF3BF74–
0xFFF3BF77
reserved
− 0xFFF3BF78
TDM2 Receive Interrupt Enable Register
− 0xFFF3BF7C–
0xFFF3BF7F
reserved
− 0xFFF3BF80
TDM2 Transmit Data Buffer Second Threshold
− 0xFFF3BF84–
0xFFF3BF87
reserved
− 0xFFF3BF88
TDM2 Receive Data Buffer Second Threshold
− 0xFFF3BF8C–
0xFFF3BF8F
reserved
− 0xFFF3BF90–
0xFFF38F94
TDM2 Transmit Data Buffer First Threshold
TDM2TDBFT
− 0xFFF3BF98
TDM2 Receive Data Buffer First Threshold
TDM2RDBFT
− 0xFFF3BF9C–
0xFFF3BF9F
reserved
− 0xFFF3BFA0
TDM2 Transmit Control Register
− 0xFFF3BFA4–
0xFFF3BFA7
reserved
− 0xFFF3BFA8
TDM2 Receive Control Register
− 0xFFF3BFAC–
0xFFF3BFAF
reserved
− 0xFFF3BFB0
TDM2 Adaptation Control Register
− 0xFFF3BFB4–
0xFFF3BFB7
reserved
− 0xFFF3BFB8
TDM2 Transmit Global Base Address
− 0xFFF3BFBC–
0xFFF3BFBF
reserved
− 0xFFF3BFC0
TDM2 Receive Global Base Address
− 0xFFF3BFC4–
0xFFF3BFC7
reserved
− 0xFFF3BFC8
TDM2 Transmit Data Buffer Size
TDM2RNB
TDM2TDBDR
TDM2RDBDR
TDM2ASDR
TDM20TIER
TDM2RIER
TDM2TDBST
TDM2RDBST
TDM2TCR
TDM2RCR
TDM2ACR
TDM2TGBA
TDM2RGBA
TDM2TDBS
MSC8156 Reference Manual, Rev. 2
9-50
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF3BFCC–
0xFFF3BFCF
reserved
− 0xFFF3BFD0
TDM2 Receive Data Buffer Size
− 0xFFF3BFD4–
0xFFF3BFD7
reserved
− 0xFFF3BFD8
TDM2 Transmit Frame Parameters
− 0xFFF3BFDC–
0xFFF3BFDF
reserved
− 0xFFF3BFE0
TDM2 Receive Frame Parameters
− 0xFFF3BFE4–
0xFFF3BFE7
reserved
− 0xFFF3BFE8
TDM2 Transmit Interface Register
− 0xFFF3BFEC–
0xFFF3BFEF
reserved
− 0xFFF3BFF0
TDM2 Receive Interface Register
− 0xFFF3BFF4–
0xFFF3BFF7
reserved
− 0xFFF3BFF8
TDM2 General Interface Register
− 0xFFF3BFFC–
0xFFF3BFFF
reserved
• 0xFFF3C000–
0xFFF3FFFF
Acronym
TDM2RDBS
TDM2TFP
TDM2RFP
TDM2TIR
TDM2RIR
TDM2GIR
TDM3
− 0xFFF3C000–
0xFFF3C7FF
TDM3 Receive Local Memory
− 0xFFF3C800–
0xFFF3CFFF
reserved
− 0xFFF3D000–
0xFFF3D3FC
TDM3 Receive Channel Parameters Register 0–255
− 0xFFF3D400–
0xFFF3D7FF
reserved
− 0xFFF3D800–
0xFFF3DFFF
TDM3 Transmit Local Memory
− 0xFFF3E000–
0xFFF3E7FF
reserved
− 0xFFF3E800–
0xFFF3EBFC
TDM3 Transmit Channel Parameters Register 0–255
− 0xFFF3EC00–
0xFFF3FEFF
reserved
− 0xFFF3FF00
TDM3 Parity Control Register
− 0xFFF3FFF04–
0xFFF3FF07
reserved
− 0xFFF3FF08
TDM3 Parity Error Register
− 0xFFF3FF0C–
0xFFF3FF0F
reserved
− 0xFFF3FF10
TDM3 Transmit Force Register
− 0xFFF3FF14–
0xFFF3FF17
reserved
TDM3RCPR[0–255]
TDM3TCPR[0–255]
TDM3PCR
TDM3PER
TDM3TFR
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-51
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF3FF18
TDM3 Receive Force Register
− 0xFFF3FF1C–
0xFFF3FF1F
reserved
− 0xFFF3FF20
TDM3 Transmit Status Register
− 0xFFF3FF24–
0xFFF3FF27
reserved
− 0xFFF3FF28
TDM3 Receive Status Register
− 0xFFF3FF2C–
0xFFF3FF2F
reserved
− 0xFFF3FF30
TDM3 Adaptation Status Register
− 0xFFF3FF34–
0xFFF3FF37
reserved
− 0xFFF3FF38
TDM3 Transmit Event Register
− 0xFFF3FF3C–
0xFFF3FF3F
reserved
− 0xFFF3FF40
TDM3 Receive Event Register
− 0xFFF3FF44–
0xFFF3FF47
reserved
− 0xFFF3FF48
TDM3 Transmit Number of Buffers
− 0xFFF3FF4C–
0xFFF3FF4F
reserved
− 0xFFF3FF50
TDM3 Receive Number of Buffers
− 0xFFF3FF54–
0xFFF3FF57
reserved
− 0xFFF3FF58
TDM3 Transmit Data Buffer Displacement Register
− 0xFFF3FF5C–
0xFFF3FF5F
reserved
− 0xFFF3FF60
TDM3 Receive Data Buffer Displacement Register
− 0xFFF3FF64–
0xFFF3FF67
reserved
− 0xFFF3FF68
TDM3 Adaptation Sync Distance Register
− 0xFFF3FF6C–
0xFFF3FF6F
reserved
− 0xFFF3FF70
TDM3 Transmit Interrupt Enable Register
− 0xFFF3FF74–
0xFFF3FF77
reserved
− 0xFFF3FF78
TDM3 Receive Interrupt Enable Register
− 0xFFF3FF7C–
0xFFF3FF7F
reserved
− 0xFFF3FF80
TDM3 Transmit Data Buffer Second Threshold
− 0xFFF3FF84–
0xFFF3FF87
reserved
− 0xFFF3FF88
TDM3 Receive Data Buffer Second Threshold
− 0xFFF3FF8C–
0xFFF3FF8F
reserved
− 0xFFF3FF90
TDM3 Transmit Data Buffer First Threshold
Acronym
TDM3RFR
TDM3TSR
TDM3RSR
TDM3ASR
TDM3TER
TDM3RER
TDM3TNB
TDM3RNB
TDM3TDBDR
TDM3RDBDR
TDM3ASDR
TDM30TIER
TDM3RIER
TDM3TDBST
TDM3RDBST
TDM3TDBFT
MSC8156 Reference Manual, Rev. 2
9-52
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFF3FF94–
0xFFF3FF97
reserved
− 0xFFF3FF98
TDM3 Receive Data Buffer First Threshold
− 0xFFF3FF9C–
0xFFF3FF9F
reserved
− 0xFFF3FFA0
TDM3 Transmit Control Register
− 0xFFF3FFA4–
0xFFF3FFA7
reserved
− 0xFFF3FFA8
TDM3 Receive Control Register
− 0xFFF3FFAC–
0xFFF3FFAF
reserved
− 0xFFF3FFB0
TDM3 Adaptation Control Register
Acronym
TDM3RDBFT
TDM3TCR
TDM3RCR
TDM3ACR
− 0xFFF3FFB4–0xF reserved
FF3FFB7
− 0xFFF3FFB8
TDM3 Transmit Global Base Address
− 0xFFF3FFBC–
0xFFF3FFBF
reserved
− 0xFFF3FFC0
TDM3 Receive Global Base Address
− 0xFFF3FFC4–
0xFFF3FFC7
reserved
− 0xFFF3FFC8
TDM3 Transmit Data Buffer Size
− 0xFFF3FFCC–
0xFFF3FFCF
reserved
− 0xFFF3FFD0
TDM3 Receive Data Buffer Size
− 0xFFF3FFD4–
0xFFF3FFD7
reserved
− 0xFFF3FFD8
TDM3 Transmit Frame Parameters
− 0xFFF3FFDC–
0xFFF3FFDF
reserved
− 0xFFF3FFE0
TDM3 Receive Frame Parameters
− 0xFFF3FFE4–
0xFFF3FFE7
reserved
− 0xFFF3FFE8
TDM3 Transmit Interface Register
− 0xFFF3FFEC–
0xFFF3FFEF
reserved
− 0xFFF3FFF0
TDM3 Receive Interface Register
− 0xFFF3FFF4–
0xFFF3FFF7
reserved
− 0xFFF3FFF8
TDM3 General Interface Register
− 0xFFF3FFFC–
0xFFF3FFFF
reserved
• 0xFFF40000–
0xFFF7FFFF
reserved
• 0xFFF80000–
0xFFF9FFFF
RapidIO
− 0xFFF80000
Device Identity Capability Register
TDM3TGBA
TDM3RGBA
TDM3TDBS
TDM3RDBS
TDM3TFP
TDM3RFP
TDM3TIR
TDM3RIR
TDM3GIR
DIDCAR
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-53
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF80004
Device Information Capability Register
DICAR
− 0xFFF80008
Assembly Identity Capability Register
AIDCAR
− 0xFFF8000C
Assembly Information Capability Register
AICAR
− 0xFFF80010
Processing Element Features Capability Register
PEFCAR
− 0xFFF80018
Source Operations Capability Register
SOCAR
− 0xFFF8001C
Destination Operations Capability Register
DOCAR
− 0xFFF80020–
0xFFF8003F
reserved
− 0xFFF80040
Mailbox Command And Status Register
MCSR
− 0xFFF80044
Port -Write and Doorbell Command and Status Register
PWDCSR
− 0xFFF80048–
0xFFF8004B
reserved
− 0xFFF8004C
Processing Element Logical Layer Control Command and Status PELLCCSR
Register
− 0xFFF80050–
0xFFF8005B
reserved
− 0xFFF8005C
Local Configuration Space Base Address 1 Command and Status LCSBA1CSR
Register
− 0xFFF80060
Base Device ID Command and Status Register
− 0xFFF80064–
0xFFF80067
reserved
− 0xFFF80068
Host Base Device ID Lock Command and Status Register
HBDIDLCSR
− 0xFFF8006C
Component Tag Command and Status Register
CTCSR
− 0xFFF80070–
0xFFF800FF
reserved
− 0xFFF80100
Port Maintenance Block Header 0
− 0xFFF80104–
0xFFF8011F
reserved
− 0xFFF80120
Port Link Time-out Control Command and Status Register
PLTOCCSR
− 0xFFF80124
Port Response Time-out Control Command and Status Register
PRTOCCSR
− 0xFFF80128–
0xFFF8013B
reserved
− 0xFFF8013C
Port General Control Command and Status Register
− 0xFFF80140
Port 0 Link Maintenance Request Command and Status Register P0LMREQCSR
− 0xFFF80144
Port 0 Link Maintenance Response Command and Status
Register
P0LMRESPCSR
− 0xFFF80148
Port 0 Local ackID Status Command and Status Register
P0LASCSR
− 0xFFF8014C–
0xFFF80157
reserved
− 0xFFF80158
Port 0 Error and Status Command and Status Register
P0ESCSR
− 0xFFF8015C
Port 0 Control Command and Status Register
P0CCSR
− 0xFFF80160
Port 1 Link Maintenance Request Command and Status Register P1LMREQCSR
− 0xFFF80164
Port 1 Link Maintenance Response Command and Status
Register
P1LMRESPCSR
− 0xFFF80168
Port 1 Local ackID Status Command and Status Register
P1LASCSR
BDIDCSR
PMBH0
PGCCSR
MSC8156 Reference Manual, Rev. 2
9-54
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF8016C–
0xFFF80177
reserved
− 0xFFF80178
Port 1 Error and Status Command and Status Register
P1ESCSR
− 0xFFF8017C
Port 1 Control Command and Status Register
P1CCSR
− 0xFFF80180–
0xFFF805FF
reserved
− 0xFFF80600
Error Reporting Block Header
− 0xFFF80604–
0xFFF80607
reserved
− 0xFFF80608
Logical/Transport Layer Error Detect Command and Status
Register
LTLEDCSR
− 0xFFF8060C
Logical/Transport Layer Error Enable Command and Status
Register
LTLEECSR
− 0xFFF80610–
0xFFF80613
reserved
− 0xFFF80614
Logical/Transport Layer Address Capture Command and Status
Register
− 0xFFF80618
Logical/Transport Layer Device ID Capture Command and Status LTLDIDCCSR
Register
− 0xFFF8061C
Logical/Transport Layer Control Capture Command and Status
Register
− 0xFFF80620–
0xFFF8063F
reserved
− 0xFFF80640
Port 0 Error Detect Command and Status Register
P0EDCSR
− 0xFFF80644
Port 0 Error Rate Enable Command and Status Register
P0ERECSR
− 0xFFF80648
Port 0 Error Capture Attributes Command and Status Register
P0ECACSR
− 0xFFF8064C
Port 0 Packet/Control Symbol Error Capture Command and
Status Register 0
P0PCSECCSR0
ERBH
LTLACCSR
LTLCCCSR
− 0xFFF80650
Port 0 Packet Error Capture Command and Status Register 1
P0PECCSR1
− 0xFFF80654
Port 0 Packet Error Capture Command and Status Register 2
P0PECCSR2
− 0xFFF80658
Port 0 Packet Error Capture Command and Status Register 3
P0PECCSR3
− 0xFFF8065C–
0xFFF80667
reserved
− 0xFFF80668
Port 0 Error Rate Command and Status Register
P0ERCSR
− 0xFFF8066C
Port 0 Error Rate Threshold Command and Status Register
P0ERTCSR
− 0xFFF80670–
0xFFF8067F
reserved
− 0xFFF80680
Port 1 Error Detect Command and Status Register
P1EDCSR
− 0xFFF80684
Port 1 Error Rate Enable Command and Status Register
P1ERECSR
− 0xFFF80688
Port 1 Error Capture Attributes Command and Status Register
P1ECACSR
− 0xFFF8068C
Port 1 Packet/Control Symbol Error Capture Command and
Status Register 0
P1PCSECCSR0
− 0xFFF80690
Port 1 Packet Error Capture Command and Status Register 1
P1PECCSR1
− 0xFFF80694
Port 1 Packet Error Capture Command and Status Register 2
P1PECCSR2
− 0xFFF80698
Port 1 Packet Error Capture Command and Status Register 3
P1PECCSR3
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-55
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF8069C–
0xFFF806A7
reserved
− 0xFFF806A8
Port 1 Error Rate Command and Status Register
P1ERCSR
− 0xFFF806AC
Port 1 Error Rate Threshold Command and Status Register
P1ERTCSR
− 0xFFF806B0–
0xFFF90003
reserved
− 0xFFF90004
Logical Layer Configuration Register
− 0xFFF90008–
0xFFF9000F
reserved
− 0xFFF90010
Error/Port-Write Interrupt Status Register
− 0xFFF90014–
0xFFF9001F
reserved
− 0xFFF90020
Logical Retry Error Threshold Configuration Register
− 0xFFF90024–
0xFFF9007F
reserved
− 0xFFF90080
Physical Retry Error Threshold Configuration Register
− 0xFFF90084–
0xFFF900FF
reserved
− 0xFFF90100
Port 0 Alternate Device ID Command and Status Register
− 0xFFF90104–
0xFFF9011F
reserved
− 0xFFF90120
Port 0 Pass-Through Accept-All Configuration Register
P0PTAACR
− 0xFFF90124
Port 0 Logical Outbound Packet Time-to-Live Configuration
Register
P0LOPTTLCR
− 0xFFF90128–
0xFFF9012F
reserved
− 0xFFF90130
Port 0 Implementation Error Command and Status Register
− 0xFFF90134–
0xFFF9013F
reserved
− 0xFFF90140
Port 0 Physical Configuration Register
− 0xFFF90144–
0xFFF90157
reserved
− 0xFFF90158
Port 0 Serial Link Command And Status Register
− 0xFFF9015C–
0xFFF9015F
reserved
− 0xFFF90160
Port 0 Serial Link Error Injection Configuration Register
− 0xFFF90164–
0xFFF9017F
reserved
− 0xFFF90180
Port 1 Alternate Device ID Command and Status Register
− 0xFFF90184–
0xFFF9019F
reserved
− 0xFFF901A0
Port 1 Pass-Through Accept-All Configuration Register
P1PTAACR
− 0xFFF901A4
Port 1 Logical Outbound Packet Time-to-Live Configuration
Register
P1LOPTTLCR
− 0xFFF901A8–
0xFFF901AF
reserved
LLCR
EPWISR
LRETCR
PRETCR
P0ADIDCSR
P0IECSR
P0PCR
P0SLCSR
P0SLEICR
P1ADIDCSR
MSC8156 Reference Manual, Rev. 2
9-56
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF901B0
Port 1 Implementation Error Command and Status Register
− 0xFFF901B4–
0xFFF901BF
reserved
− 0xFFF901C0
Port 1 Physical Configuration Register
− 0xFFF901C4–
0xFFF901D7
reserved
− 0xFFF901D8
Port 1 Serial Link Command And Status Register
− 0xFFF901DC–
0xFFF901DF
reserved
− 0xFFF901E0
Port 1 Serial Link Error Injection Configuration Register
− 0xFFF901E4–
0xFFF90BF7
reserved
− 0xFFF90BF8
IP Block Revision Register 1
IPBRR1
− 0xFFF90BFC
IP Block Revision Register 2
IPBRR2
− 0xFFF90C00
Port 0 RapidIO Outbound Window Translation Address Register 0 P0ROWTAR0
− 0xFFF90C04
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR0
Register 0
− 0xFFF90C08–
0xFFF90C0F
reserved
− 0xFFF90C10
Port 0 RapidIO Outbound Window Attributes Register 0
− 0xFFF90C14–
0xFFF90C1F
reserved
− 0xFFF90C20
Port 0 RapidIO Outbound Window Translation Address Register 1 P0ROWTAR1
− 0xFFF90C24
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR1
Register 1
− 0xFFF90C28–
0xFFF90C2F
reserved
− 0xFFF90C30
Port 0 RapidIO Outbound Window Attributes Register 1
P0ROWAR1
− 0xFFF90C34
Port 0 RapidIO Outbound Window Segment 1 Register 1
P0ROWS1R1
− 0xFFF90C38
Port 0 RapidIO Outbound Window Segment 2 Register 1
P0ROWS2R1
− 0xFFF90C3C
Port 0 RapidIO Outbound Window Segment 3 Register 1
P0ROWS3R1
− 0xFFF90C40
Port 0 RapidIO Outbound Window Translation Address Register 2 P0ROWTAR2
− 0xFFF90C44
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR2
Register 2
− 0xFFF90C48
Port 0 RapidIO Outbound Window Base Address Register 2
− 0xFFF90C4C–
0xFFF90C4F
reserved
− 0xFFF90C50
Port 0 RapidIO Outbound Window Attributes Register 2
P0ROWAR2
− 0xFFF90C54
Port 0 RapidIO Outbound Window Segment 1 Register 2
P0ROWS1R2
− 0xFFF90C58
Port 0 RapidIO Outbound Window Segment 2 Register 2
P0ROWS2R2
− 0xFFF90C5C
Port 0 RapidIO Outbound Window Segment 3 Register 2
P0ROWS3R2
− 0xFFF90C60
Port 0 RapidIO Outbound Window Translation Address Register 3 P0ROWTAR3
− 0xFFF90C64
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR3
Register 3
− 0xFFF90C68
Port 0 RapidIO Outbound Window Base Address Register 3
P1IECSR
P1PCR
P1SLCSR
P1SLEICR
P0ROWAR0
P0ROWBAR2
P0ROWBAR3
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-57
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90C6C–
0xFFF90C6F
reserved
− 0xFFF90C70
Port 0 RapidIO Outbound Window Attributes Register 3
P0ROWAR3
− 0xFFF90C74
Port 0 RapidIO Outbound Window Segment 1 Register 3
P0ROWS1R3
− 0xFFF90C78
Port 0 RapidIO Outbound Window Segment 2 Register 3
P0ROWS2R3
− 0xFFF90C7C
Port 0 RapidIO Outbound Window Segment 3 Register 3
P0ROWS3R3
− 0xFFF90C80
Port 0 RapidIO Outbound Window Translation Address Register 4 P0ROWTAR4
− 0xFFF90C84
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR4
Register 4
− 0xFFF90C88
Port 0 RapidIO Outbound Window Base Address Register 4
− 0xFFF90C8C–
0xFFF90C8F
reserved
− 0xFFF90C90
Port 0 RapidIO Outbound Window Attributes Register 4
P0ROWAR4
− 0xFFF90C94
Port 0 RapidIO Outbound Window Segment 1 Register 4
P0ROWS1R4
− 0xFFF90C98
Port 0 RapidIO Outbound Window Segment 2 Register 4
P0ROWS2R4
− 0xFFF90C9C
Port 0 RapidIO Outbound Window Segment 3 Register 4
P0ROWS3R4
P0ROWBAR4
− 0xFFF90CA0
Port 0 RapidIO Outbound Window Translation Address Register 5 P0ROWTAR5
− 0xFFF90CA4
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR5
Register 5
− 0xFFF90CA8
Port 0 RapidIO Outbound Window Base Address Register 5
− 0xFFF90CAC–
0xFFF90CAF
reserved
− 0xFFF90CB0
Port 0 RapidIO Outbound Window Attributes Register 5
P0ROWAR5
− 0xFFF90CB4
Port 0 RapidIO Outbound Window Segment 1 Register 5
P0ROWS1R5
− 0xFFF90CB8
Port 0 RapidIO Outbound Window Segment 2 Register 5
P0ROWS2R5
− 0xFFF90CBC
Port 0 RapidIO Outbound Window Segment 3 Register 5
P0ROWS3R5
− 0xFFF90CC0
Port 0 RapidIO Outbound Window Translation Address Register 6 P0ROWTAR6
− 0xFFF90CC4
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR6
Register 6
− 0xFFF90CC8
Port 0 RapidIO Outbound Window Base Address Register 6
− 0xFFF90CCC–
0xFFF90CCF
reserved
− 0xFFF90CD0
Port 0 RapidIO Outbound Window Attributes Register 6
P0ROWAR6
− 0xFFF90CD4
Port 0 RapidIO Outbound Window Segment 1 Register 6
P0ROWS1R6
− 0xFFF90CD8
Port 0 RapidIO Outbound Window Segment 2 Register 6
P0ROWS2R6
− 0xFFF90CDC
Port 0 RapidIO Outbound Window Segment 3 Register 6
P0ROWS3R6
P0ROWBAR5
P0ROWBAR6
− 0xFFF90CE0
Port 0 RapidIO Outbound Window Translation Address Register 7 P0ROWTAR7
− 0xFFF90CE4
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR7
Register 7
− 0xFFF90CE8
Port 0 RapidIO Outbound Window Base Address Register 7
− 0xFFF90CEC–
0xFFF90CEF
reserved
− 0xFFF90CF0
Port 0 RapidIO Outbound Window Attributes Register 7
P0ROWAR7
− 0xFFF90CF4
Port 0 RapidIO Outbound Window Segment 1 Register 7
P0ROWS1R7
P0ROWBAR7
MSC8156 Reference Manual, Rev. 2
9-58
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90CF8
Port 0 RapidIO Outbound Window Segment 2 Register 7
P0ROWS2R7
− 0xFFF90CFC
Port 0 RapidIO Outbound Window Segment 3 Register 7
P0ROWS3R7
− 0xFFF90D00
Port 0 RapidIO Outbound Window Translation Address Register 8 P0ROWTAR8
− 0xFFF90D04
Port 0 RapidIO Outbound Window Translation Extended Address P0ROWTEAR8
Register 8
− 0xFFF90D08
Port 0 RapidIO Outbound Window Base Address Register 8
− 0xFFF90D0C–
0xFFF90D0F
reserved
− 0xFFF90D10
Port 0 RapidIO Outbound Window Attributes Register 8
P0ROWAR8
− 0xFFF90D14
Port 0 RapidIO Outbound Window Segment 1 Register 8
P0ROWS1R8
− 0xFFF90D18
Port 0 RapidIO Outbound Window Segment 2 Register 8
P0ROWS2R8
− 0xFFF90D1C
Port 0 RapidIO Outbound Window Segment 3 Register 8
P0ROWS3R8
− 0xFFF90D20–
0xFFF90D5F
reserved
− 0xFFF90D60
Port 0 RapidIO Inbound Window Translation Address Register 4
− 0xFFF90D64–
0xFFF90D67
reserved
− 0xFFF90D68
Port 0 RapidIO Inbound Window Base Address Register 4
− 0xFFF90D6C–
0xFFF90D6F
reserved
− 0xFFF90D70
Port 0 RapidIO Inbound Window Attributes Register 4
− 0xFFF90D74–
0xFFF90D7F
reserved
− 0xFFF90D80
Port 0 RapidIO Inbound Window Translation Address Register 3
− 0xFFF90D84–
0xFFF90D87
reserved
− 0xFFF90D88
Port 0 RapidIO Inbound Window Base Address Register 3
− 0xFFF90D8C–
0xFFF90D8F
reserved
− 0xFFF90D90
Port 0 RapidIO Inbound Window Attributes Register 3
− 0xFFF90D94–
0xFFF90D9F
reserved
− 0xFFF90DA0
Port 0 RapidIO Inbound Window Translation Address Register 2
− 0xFFF90DA4–
0xFFF90DA7
reserved
− 0xFFF90DA8
Port 0 RapidIO Inbound Window Base Address Register 2
− 0xFFF90DAC–
0xFFF90DAF
reserved
− 0xFFF90DB0
Port 0 RapidIO inbound window attributes register 2
− 0xFFF90DB4–
0xFFF90DBF
reserved
− 0xFFF90DC0
Port 0 RapidIO Inbound Window Translation Address Register 1
− 0xFFF90DC4–
0xFFF90DC7
reserved
− 0xFFF90DC8
Port 0 RapidIO Inbound Window Base Address Register 1
P0ROWBAR8
P0RIWTAR4
P0RIWBAR4
P0RIWAR4
P0RIWTAR3
P0RIWBAR3
P0RIWAR3
P0RIWTAR2
P0RIWBAR2
P0RIWAR2
P0RIWTAR1
P0RIWBAR1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-59
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90DCC–
0xFFF90DCF
reserved
− 0xFFF90DD0
Port 0 RapidIO Inbound Window Attributes Register 1
− 0xFFF90DD4–
0xFFF90DDF
reserved
− 0xFFF90DE0
Port 0 RapidIO Inbound Window Translation Address Register 0
− 0xFFF90DE4–
0xFFF90DEF
reserved
− 0xFFF90DF0
Port 0 RapidIO Inbound Window Attributes Register 0
− 0xFFF90DF4–
0xFFF92DFF
reserved
− 0xFFF90E00
Port 1 RapidIO Outbound Window Translation Address Register 0 P1ROWTAR0
− 0xFFF90E04
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR0
Register 0
− 0xFFF90E08
Port 1 RapidIO Outbound Window Base Address Register 0
− 0xFFF90E0C–
0xFFF90E0F
reserved
− 0xFFF90E10
Port 1 RapidIO Outbound Window Attributes Register 0
− 0xFFF90E14–
0xFFF90E1F
reserved
P0RIWAR1
P0RIWTAR0
P0RIWAR0
P1ROWBAR0
P1ROWAR0
− 0xFFF90E20
Port 1 RapidIO Outbound Window Translation Address Register 1 P1ROWTAR1
− 0xFFF90E24
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR1
Register 1
− 0xFFF90E28
Port 1 RapidIO Outbound Window Base Address Register 1
− 0xFFF90E2C–
0xFFF90E2F
reserved
− 0xFFF90E30
Port 1 RapidIO Outbound Window Attributes Register 1
P1ROWAR1
− 0xFFF90E34
Port 1 RapidIO Outbound Window Segment 1 Register 1
P1ROWS1R1
− 0xFFF90E38
Port 1 RapidIO Outbound Window Segment 2 Register 1
P1ROWS2R1
− 0xFFF90E3C
Port 1 RapidIO Outbound Window Segment 3 Register 1
P1ROWS3R1
− 0xFFF90E40
Port 1 RapidIO Outbound Window Translation Address Register 2 P1ROWTAR2
− 0xFFF90E44
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR2
Register 2
− 0xFFF90E48
Port 1 RapidIO Outbound Window Base Address Register 2
− 0xFFF90E4C–
0xFFF90E4F
reserved
− 0xFFF90E50
Port 1 RapidIO Outbound Window Attributes Register 2
P1ROWAR2
− 0xFFF90E54
Port 1 RapidIO Outbound Window Segment 1 Register 2
P1ROWS1R2
− 0xFFF90E58
Port 1 RapidIO Outbound Window Segment 2 Register 2
P1ROWS2R2
− 0xFFF90E5C
Port 1 RapidIO Outbound Window Segment 3 Register 2
P1ROWS3R2
P1ROWBAR1
P1ROWBAR2
− 0xFFF90E60
Port 1 RapidIO Outbound Window Translation Address Register 3 P1ROWTAR3
− 0xFFF90E64
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR3
Register 3
− 0xFFF90E68
Port 1 RapidIO Outbound Window Base Address Register 3
P1ROWBAR3
MSC8156 Reference Manual, Rev. 2
9-60
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90E6C–
0xFFF90E6F
reserved
− 0xFFF90E70
Port 1 RapidIO Outbound Window Attributes Register 3
P1ROWAR3
− 0xFFF90E74
Port 1 RapidIO Outbound Window Segment 1 Register 3
P1ROWS1R3
− 0xFFF90E78
Port 1 RapidIO Outbound Window Segment 2 Register 3
P1ROWS2R3
− 0xFFF90E7C
Port 1 RapidIO Outbound Window Segment 3 Register 3
P1ROWS3R3
− 0xFFF90E80
Port 1 RapidIO Outbound Window Translation Address Register 4 P1ROWTAR4
− 0xFFF90E84
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR4
Register 4
− 0xFFF90E88
Port 1 RapidIO Outbound Window Base Address Register 4
− 0xFFF90E8C–
0xFFF90E8F
reserved
− 0xFFF90E90
Port 1 RapidIO Outbound Window Attributes Register 4
P1ROWAR4
− 0xFFF90E94
Port 1 RapidIO Outbound Window Segment 1 Register 4
P1ROWS1R4
− 0xFFF90E98
Port 1 RapidIO Outbound Window Segment 2 Register 4
P1ROWS2R4
− 0xFFF90E9C
Port 1 RapidIO Outbound Window Segment 3 Register 4
P1ROWS3R4
P1ROWBAR4
− 0xFFF90EA0
Port 1 RapidIO Outbound Window Translation Address Register 5 P1ROWTAR5
− 0xFFF90EA4
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR5
Register 5
− 0xFFF90EA8
Port 1 RapidIO Outbound Window Base Address Register 5
− 0xFFF90EAC–
0xFFF90EAF
reserved
− 0xFFF90EB0
Port 1 RapidIO Outbound Window Attributes Register 5
P1ROWAR5
− 0xFFF90EB4
Port 1 RapidIO Outbound Window Segment 1 Register 5
P1ROWS1R5
− 0xFFF90EB8
Port 1 RapidIO Outbound Window Segment 2 Register 5
P1ROWS2R5
− 0xFFF90EBC
Port 1 RapidIO Outbound Window Segment 3 Register 5
P1ROWS3R5
− 0xFFF90EC0
Port 1 RapidIO Outbound Window Translation Address Register 6 P1ROWTAR6
− 0xFFF90EC4
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR6
Register 6
− 0xFFF90EC8
Port 1 RapidIO Outbound Window Base Address Register 6
− 0xFFF90ECC–
0xFFF90ECF
reserved
− 0xFFF90ED0
Port 1 RapidIO Outbound Window Attributes Register 6
P1ROWAR6
− 0xFFF90ED4
Port 1 RapidIO Outbound Window Segment 1 Register 6
P1ROWS1R6
− 0xFFF90ED8
Port 1 RapidIO Outbound Window Segment 2 Register 6
P1ROWS2R6
− 0xFFF90EDC
Port 1 RapidIO Outbound Window Segment 3 Register 6
P1ROWS3R6
P1ROWBAR5
P1ROWBAR6
− 0xFFF90EE0
Port 1 RapidIO Outbound Window Translation Address Register 7 P1ROWTAR7
− 0xFFF90EE4
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR7
Register 7
− 0xFFF90EE8
Port 1 RapidIO Outbound Window Base Address Register 7
− 0xFFF90EEC–
0xFFF90EEF
reserved
− 0xFFF90EF0
Port 1 RapidIO Outbound Window Attributes Register 7
P1ROWAR7
− 0xFFF90EF4
Port 1 RapidIO Outbound Window Segment 1 Register 7
P1ROWS1R7
P1ROWBAR7
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-61
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90EF8
Port 1 RapidIO Outbound Window Segment 2 Register 7
P1ROWS2R7
− 0xFFF90EFC
Port 1 RapidIO Outbound Window Segment 3 Register 7
P1ROWS3R7
− 0xFFF90F00
Port 1 RapidIO Outbound Window Translation Address Register 8 P1ROWTAR8
− 0xFFF90F04
Port 1 RapidIO Outbound Window Translation Extended Address P1ROWTEAR8
Register 8
− 0xFFF90F08
Port 1 RapidIO Outbound Window Base Address Register 8
− 0xFFF90F0C–
0xFFF90F0F
reserved
− 0xFFF90F10
Port 1 RapidIO Outbound Window Attributes Register 8
P1ROWAR8
− 0xFFF90F14
Port 1 RapidIO Outbound Window Segment 1 Register 8
P1ROWS1R8
− 0xFFF90F18
Port 1 RapidIO Outbound Window Segment 2 Register 8
P1ROWS2R8
− 0xFFF90F1C
Port 1 RapidIO Outbound Window Segment 3 Register 8
P1ROWS3R8
− 0xFFF90F20–
0xFFF90F5F
reserved
− 0xFFF90F60
Port 1 RapidIO Inbound Window Translation Address Register 4 P1RIWTAR4
− 0xFFF90F64–
0xFFF90F67
reserved
− 0xFFF90F68
Port 1 RapidIO Inbound Window Base Address Register 4
− 0xFFF90F6C–
0xFFF90F6F
reserved
− 0xFFF90F70
Port 1 RapidIO Inbound Window Attributes Register 4
− 0xFFF90F74–
0xFFF90F7F
reserved
− 0xFFF90F80
Port 1 RapidIO Inbound Window Translation Address Register 3
− 0xFFF90F84–
0xFFF90F87
reserved
− 0xFFF90F88
Port 1 RapidIO Inbound Window Base Address Register 3
− 0xFFF90F8C–
0xFFF90F8F
reserved
− 0xFFF90F90
Port 1 RapidIO Inbound Window Attributes Register 3
− 0xFFF90F94–
0xFFF90F9F
reserved
− 0xFFF90FA0
Port 1 RapidIO Inbound Window Translation Address Register 2
− 0xFFF90FA4–
0xFFF90FA7
reserved
− 0xFFF90FA8
Port 1 RapidIO Inbound Window Base Address Register 2
− 0xFFF90FAC–
0xFFF90FAF
reserved
− 0xFFF90FB0
Port 1 RapidIO inbound window attributes register 2
− 0xFFF90FB4–
0xFFF90FBF
reserved
− 0xFFF90FC0
Port 1 RapidIO Inbound Window Translation Address Register 1
− 0xFFF90FC4–
0xFFF90FC7
reserved
− 0xFFF90FC8
Port 1 RapidIO Inbound Window Base Address Register 1
P1ROWBAR8
P1RIWBAR4
P1RIWAR4
P1RIWTAR3
P1RIWBAR3
P1RIWAR3
P1RIWTAR2
P1RIWBAR2
P1RIWAR2
P1RIWTAR1
P1RIWBAR1
MSC8156 Reference Manual, Rev. 2
9-62
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF90FCC–
0xFFF90FCF
reserved
− 0xFFF90FD0
Port 1 RapidIO Inbound Window Attributes Register 1
− 0xFFF90FD4–
0xFFF90FDF
reserved
− 0xFFF90FE0
Port 1 RapidIO Inbound Window Translation Address Register 0
− 0xFFF90FE4–
0xFFF90FE7
reserved
− 0xFFF90FE8
Port 1 RapidIO Inbound Window Base Address Register 1
− 0xFFF90FEC–
0xFFF90FEF
reserved
− 0xFFF90FF0
Port 1 RapidIO Inbound Window Attributes Register 0
− 0xFFF90FF4–
0xFFF92DFF
reserved
− 0xFFF90FF4–
0xFFF92FFF
reserved
− 0xFFF93000
Outbound Message 0 Mode Register
OM0MR
− 0xFFF93004
Outbound Message 0 Status Register
OM0SR
− 0xFFF93008–
0xFFF9300B
reserved
− 0xFFF9300C
Outbound Message 0 Descriptor Queue Dequeue Pointer
Address Register
− 0xFFF93010–
0xFFF93013
reserved
− 0xFFF93014
Outbound Message 0 Source Address Register
OM0SAR
− 0xFFF93018
Outbound Message 0 Destination Port Register
OM0DPR
− 0xFFF9301C
Outbound Message 0 Destination Attributes Register
OM0DATR
− 0xFFF93020
Outbound Message 0 Double-word Count Register
OM0DCR
− 0xFFF93024–
0xFFF93027
reserved
− 0xFFF93028
Outbound Message 0 Descriptor Queue Enqueue Pointer
Address Register
OM0DQEPAR
− 0xFFF9302C
Outbound Message 0 Retry Error Threshold Configuration
Register
OM0RETCR
− 0xFFF93030
Outbound Message 0 Multicast Group Register
OM0MGR
− 0xFFF93034
Outbound Message 0 Multicast List Register
OM0MLR
− 0xFFF93038–
0xFFF9305F
reserved
− 0xFFF93060
Inbound Message 0 Mode Register
IM0MR
− 0xFFF93064
Inbound Message 0 Status Register
IM0SR
− 0xFFF93068–
0xFFF9306B
reserved
− 0xFFF9306C
Inbound Message 0 Frame Queue Dequeue Pointer Address
Register
− 0xFFF93070–
0xFFF93073
reserved
P1RIWAR1
P1RIWTAR0
P1RIWBAR1
P1RIWAR0
OM0DQDPAR
IM0FQDPAR
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-63
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF93074
Inbound Message 0 Frame Queue Enqueue Pointer Address
Register
IM0FQEPAR
− 0xFFF93078
Inbound Message 0 Maximum Interrupt Report Interval Register
IM0MIRIR
− 0xFFF9307C–
0xFFF930FF
reserved
− 0xFFF93100
Outbound Message 1 Mode Register
OM1MR
− 0xFFF93104
Outbound Message 1 Status Register
OM1SR
− 0xFFF93108–
0xFFF9310B
reserved
− 0xFFF9310C
Outbound Message 1 Descriptor Queue Dequeue Pointer
Address Register
− 0xFFF93110–
0xFFF93113
reserved
− 0xFFF93114
Outbound Message 1 Source Address Register
OM1SAR
− 0xFFF93118
Outbound Message 1 Destination Port Register
OM1DPR
− 0xFFF9311C
Outbound Message 1 Destination Attributes Register
OM1DATR
− 0xFFF93120
Outbound Message 1 Double-word Count Register
OM1DCR
− 0xFFF93124–
0xFFF93127
reserved
− 0xFFF93128
Outbound Message 1 Descriptor Queue Enqueue Pointer
Address Register
OM1DQEPAR
− 0xFFF9312C
Outbound Message 1 Retry Error Threshold Configuration
Register
OM1RETCR
− 0xFFF93130
Outbound Message 1 Multicast Group Register
OM1MGR
− 0xFFF93134
Outbound Message 1 Multicast List Register
OM1MLR
− 0xFFF93138–
0xFFF9315F
reserved
OM1DQDPAR
− 0xFFF93160
Inbound Message 1 Mode Register
IM1MR
− 0xFFF93164
Inbound Message 1 Status Register
IM1SR
− 0xFFF93168–
0xFFF9316B
reserved
− 0xFFF9316C
Inbound Message 1 Frame Queue Dequeue Pointer Address
Register
− 0xFFF93170–
0xFFF93173
reserved
− 0xFFF93174
Inbound Message 1 Frame Queue Enqueue Pointer Address
Register
IM1FQEPAR
− 0xFFF93178
Inbound Message 1 Maximum Interrupt Report Interval Register
IM1MIRIR
− 0xFFF9317C–
0xFFF933FF
reserved
IM1FQDPAR
− 0xFFF93400
Outbound Doorbell Mode Register
ODMR
− 0xFFF93404
Outbound Doorbell Status Register
ODSR
− 0xFFF93408–
0xFFF93417
reserved
− 0xFFF93418
Outbound Doorbell Destination Port Register
ODDPR
− 0xFFF9341C
Outbound Doorbell Destination Attributes Register
ODDATR
MSC8156 Reference Manual, Rev. 2
9-64
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFF93420–
0xFFF9342B
reserved
− 0xFFF9342C
Outbound Doorbell Retry Error Threshold Configuration Register ODRETCR
− 0xFFF93430–
0xFFF9345F
reserved
− 0xFFF93460
Inbound Doorbell Mode Register
IDMR
− 0xFFF93464
Inbound Doorbell Status Register
IDSR
− 0xFFF93468–
0xFFF9346B
reserved
− 0xFFF9346C
Inbound Doorbell Queue Dequeue Pointer Address Register
− 0xFFF93470–
0xFFF93473
reserved
− 0xFFF93474
Inbound Doorbell Queue Enqueue Pointer Address Register
IDQEPAR
− 0xFFF93478
Inbound Doorbell Maximum Interrupt Report Interval Register
IDMIRIR
− 0xFFF9347C–
0xFFF934DF
reserved
IDQDPAR
− 0xFFF934E0
Inbound Port-write Mode Register
IPWMR
− 0xFFF934E4
Inbound Port-write Status Register
IPWSR
− 0xFFF934EC
Inbound Port-write Queue Base Address Register
IPWQBAR
− 0xFFF934F0–
0xFFF9FFFF
reserved
• 0xFFFA0000–
0xFFFA0FFF
reserved
• 0xFFFA1000–
0xFFFA103F
HSSI OCN Crossbar Switch to MBus0
• 0xFFFA1040–
0xFFFA107F
HSSI OCN Crossbar Switch to MBus1
• 0xFFFA1080–
0xFFFA7FFF
reserved
• 0xFFFA8000–
0xFFFA8FFF
HSSI Dedicated DMA Controller 0 Registers
− 0xFFFA8000–
0xFFFA80FF
reserved
− 0xFFFA8100
DMA 0 Mode Register
D0MR0
− 0xFFFA8104
DMA 0 Status Register
D0SR0
− 0xFFFA8108
DMA 0 Current Link Descriptor Extended Address Register
D0ECLNDAR0
− 0xFFFA810C
DMA 0 Current Link Descriptor Address Register
D0CLNDAR0
− 0xFFFA8110
DMA 0 Source Attributes Register
D0SATR0
− 0xFFFA8114
DMA 0 Source Address Register
D0SAR0
− 0xFFFA8118
DMA 0 Destination Attributes Register
D0DATR0
− 0xFFFA811C
DMA 0 Destination Address Register
D0DAR0
− 0xFFFA8120
DMA 0 Byte Count Register
D0BCR0
− 0xFFFA8124–
0xFFFA8127
reserved
− 0xFFFA8128
DMA 0 Next Link Descriptor Address Register
D0NLNDAR0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-65
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFA812C–
0xFFFA8133
reserved
− 0xFFFA8134
DMA 0 Current List Descriptor Address Register
D0CLSDAR0
− 0xFFFA8138
DMA 0 Extended Next List Descriptor Address Register
D0ENLSDAR0
− 0xFFFA813C
DMA 0 Next List Descriptor Address Register
D0NLSDAR0
− 0xFFFA8140
DMA 0 Source Stride Register
D0SSR0
− 0xFFFA8144
DMA 0 Destination Stride Register
D0DSR0
− 0xFFFA8148–
0xFFFA817F
reserved
− 0xFFFA8180
DMA 1 Mode Register
D0MR1
− 0xFFFA8184
DMA 1 Status Register
D0SR1
− 0xFFFA8188
DMA 1 Current Link Descriptor Extended Address Register
D0ECLNDAR1
− 0xFFFA818C
DMA 1 Current Link Descriptor Address Register
D0CLNDAR1
− 0xFFFA8190
DMA 1 Source Attributes Register
D0SATR1
− 0xFFFA8194
DMA 1 Source Address Register
D0SAR1
− 0xFFFA8198
DMA 1 Destination Attributes Register
D0DATR1
− 0xFFFA819C
DMA 1 Destination Address Register
D0DAR1
− 0xFFFA81A0
DMA 1 Byte Count Register
D0BCR1
− 0xFFFA81A4
DMA 1 Extended Next Link Descriptor Address Register
D0ENLNDAR1
− 0xFFFA81A8
DMA 1 Next Link Descriptor Address Register
D0NLNDAR1
− 0xFFFA81AC–
0xFFFA81AF
reserved
− 0xFFFA81B0
DMA 1 Extended Current List Descriptor Address Register
D0ECLSDAR1
− 0xFFFA81B4
DMA 1 Current List Descriptor Address Register
D0CLSDAR1
− 0xFFFA81B8
DMA 1 Extended Next List Descriptor Address Register
D0ENLSDAR1
− 0xFFFA81BC
DMA 1 Next List Descriptor Address Register
D0NLSDAR1
− 0xFFFA81C0
DMA 1 Source Stride Register
D0SSR1
− 0xFFFA81C4
DMA 1 Destination Stride Register
D0DSR1
− 0xFFFA81C8–
0xFFFA81FF
reserved
− 0xFFFA8200
DMA 2 Mode Register
D0MR2
− 0xFFFA8204
DMA 2 Status Register
D0SR2
− 0xFFFA8208
DMA 2 Extended Current Link Descriptor Address Register
D0ECLNDAR2
− 0xFFFA820C
DMA 2 Current Link Descriptor Address Register
D0CLNDAR2
− 0xFFFA8210
DMA 2 Source Attributes Register
D0SATR2
− 0xFFFA8214
DMA 2 Source Address Register
D0SAR2
− 0xFFFA8218
DMA 2 Destination Attributes Register
D0DATR2
− 0xFFFA821C
DMA 2 Destination Address Register
D0DAR2
− 0xFFFA8220
DMA 2 Byte Count Register
D0BCR2
− 0xFFFA8224
DMA 2 Extended Next Link Descriptor Address Register
D0ENLNDAR2
− 0xFFFA8228
DMA 2 Next Link Descriptor Address Register
D0NLNDAR2
− 0xFFFA822C–
0xFFFA822F
reserved
MSC8156 Reference Manual, Rev. 2
9-66
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFA8230
DMA 2 Extended Current List Descriptor Address Register
D0ECLSDAR2
− 0xFFFA8234
DMA 2 Current List Descriptor Address Register
D0CLSDAR2
− 0xFFFA8238
DMA 2 Extended Next List Descriptor Address Register
D0ENLSDAR2
− 0xFFFA823C
DMA 2 Next List Descriptor Address Register
D0NLSDAR2
− 0xFFFA8240
DMA 2 Source Stride Register
D0SSR2
− 0xFFFA8244
DMA 2 Destination Stride Register
D0DSR2
− 0xFFFA8248–
0xFFFA827F
reserved
− 0xFFFA8280
DMA 3 Mode Register
D0MR3
− 0xFFFA8284
DMA 3 Status Register
D0SR3
− 0xFFFA8288
DMA 3 Extended Current Link Descriptor Address Register
D0ECLNDAR3
− 0xFFFA828C
DMA 3 Current Link Descriptor Address Register
D0CLNDAR3
− 0xFFFA8290
DMA 3 Source Attributes Register
D0SATR3
− 0xFFFA8294
DMA 3 Source Address Register
D0SAR3
− 0xFFFA8298
DMA 3 Destination Attributes Register
D0DATR3
− 0xFFFA829C
DMA 3 Destination Address Register
D0DAR3
− 0xFFFA82A0
DMA 3 Byte Count Register
D0BCR3
− 0xFFFA82A4
DMA 3 Extended Next Link Descriptor Address Register
D0ENLNDAR3
− 0xFFFA82A8
DMA 3 Next Link Descriptor Address Register
D0NLNDAR3
− 0xFFFA82AC–
0xFFFA82AF
reserved
− 0xFFFA82B0
DMA 3 Extended Current List Descriptor Address Register
D0ECLSDAR3
− 0xFFFA82B4
DMA 3 Current List Descriptor Address Register
D0CLSDAR3
− 0xFFFA82B8
DMA 3 Extended Next List Descriptor Address Register
D0ENLSDAR3
− 0xFFFA82BC
DMA 3 Next List Descriptor Address Register
D0NLSDAR3
− 0xFFFA82C0
DMA 3 Source Stride Register
D0SSR3
− 0xFFFA82C4
DMA 3 Destination Stride Register
D0DSR3
− 0xFFFA82C8–
0xFFFA82FF
reserved
− 0xFFFA8300
DMA General Status Register
− 0xFFFA8304–
0xFFFA9C07
reserved
− 0xFFFA9C08
Local Access Window Base Address Register 0
− 0xFFFA9C0C–
0xFFFA9C0F
reserved
− 0xFFFA9C10
Local Access Window Attributes Register 0
− 0xFFFA9C14–
0xFFFA9C27
reserved
− 0xFFFA9C28
Local Access Window Base Address Register 1
− 0xFFFA9C2C–
0xFFFA9C2F
reserved
− 0xFFFA9C30
Local Access Window Attributes Register 1
− 0xFFFA9C34–
0xFFFA9C47
reserved
D0DGSR
D0LAWBAR0
D0LAWAR0
D0LAWBAR1
D0LAWAR1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-67
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFFA9C48
Local Access Window Base Address Register 2
− 0xFFFA9C4C–
0xFFFA9C4F
reserved
− 0xFFFA9C50
Local Access Window Attributes Register 2
− 0xFFFA9C54–
0xFFFA9C67
reserved
− 0xFFFA9C68
Local Access Window Base Address Register 3
− 0xFFFA9C6C–
0xFFFA9C6F
reserved
− 0xFFFA9C70
Local Access Window Attributes Register 3
− 0xFFFA9C74–
0xFFFA9C87
reserved
− 0xFFFA9C88
Local Access Window Base Address Register 4
− 0xFFFA9C8C–
0xFFFA9C8F
reserved
− 0xFFFA9C90
Local Access Window Attributes Register 4
− 0xFFFA9C94–
0xFFFA9CA7
reserved
− 0xFFFA9CA8
Local Access Window Base Address Register 5
− 0xFFFA9CAC–
0xFFFA9CAF
reserved
− 0xFFFA9CB0
Local Access Window Attributes Register 5
− 0xFFFA9CB4–
0xFFFA9CC7
reserved
− 0xFFFA9CC8
Local Access Window Base Address Register 6
− 0xFFFA9CCC–
0xFFFA9CCF
reserved
− 0xFFFA9CD0
Local Access Window Attributes Register 6
− 0xFFFA9CD4–
0xFFFA9CE7
reserved
− 0xFFFA9CE8
Local Access Window Base Address Register 7
− 0xFFFA9CEC–
0xFFFA9CEF
reserved
− 0xFFFA9CF0
Local Access Window Attributes Register 7
− 0xFFFA9CF4–
0xFFFA9D07
reserved
− 0xFFFA9D08
Local Access Window Base Address Register 8
− 0xFFFA9D0C–
0xFFFA9D0F
reserved
− 0xFFFA9D10
Local Access Window Attributes Register 8
− 0xFFFA9D14–
0xFFFA9D27
reserved
− 0xFFFA9D28
Local Access Window Base Address Register 9
− 0xFFFA9D2C–
0xFFFA9D2F
reserved
− 0xFFFA9D30
Local Access Window Attributes Register 9
Acronym
D0LAWBAR2
D0LAWAR2
D0LAWBAR3
D0LAWAR3
D0LAWBAR4
D0LAWAR4
D0LAWBAR5
D0LAWAR5
D0LAWBAR6
D0LAWAR6
D0LAWBAR7
D0LAWAR7
D0LAWBAR8
D0LAWAR8
D0LAWBAR9
D0LAWAR9
MSC8156 Reference Manual, Rev. 2
9-68
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
− 0xFFFA9D34–
0xFFFA8FFF
Name/Status
reserved
• 0xFFFA9000–
0xFFFA9FFF
DMA Controller 0 to OCN
• 0xFFFAA000–
0xFFFAAFFF
Dedicated DMA Controller 1 Registers
− 0xFFFAA000–
0xFFFAA0FF
Acronym
reserved
− 0xFFFAA100
DMA 0 Mode Register
D1MR0
− 0xFFFAA104
DMA 0 Status Register
D1SR0
− 0xFFFAA108
DMA 0 Current Link Descriptor Extended Address Register
D1ECLNDAR0
− 0xFFFAA10C
DMA 0 Current Link Descriptor Address Register
D1CLNDAR0
− 0xFFFAA110
DMA 0 Source Attributes Register
D1SATR0
− 0xFFFAA114
DMA 0 Source Address Register
D1SAR0
− 0xFFFAA118
DMA 0 Destination Attributes Register
D1DATR0
− 0xFFFAA11C
DMA 0 Destination Address Register
D1DAR0
− 0xFFFAA120
DMA 0 Byte Count Register
D1BCR0
− 0xFFFAA124–
0xFFFAA127
reserved
− 0xFFFAA128
DMA 0 Next Link Descriptor Address Register
− 0xFFFAA12C–
0xFFFAA133
reserved
− 0xFFFAA134
DMA 0 Current List Descriptor Address Register
D1CLSDAR0
− 0xFFFAA138
DMA 0 Next List Descriptor Extended Address Register
D1ENLSDAR0
D1NLNDAR0
− 0xFFFAA13C
DMA 0 Next List Descriptor Address Register
D1NLSDAR0
− 0xFFFAA140
DMA 0 Source Stride Register
D1SSR0
− 0xFFFAA144
DMA 0 Destination Stride Register
D1DSR0
− 0xFFFAA148–
0xFFFAA17F
reserved
− 0xFFFAA180
DMA 1 Mode Register
D1MR1
− 0xFFFAA184
DMA 1 Status Register
D1SR1
− 0xFFFAA188
DMA 1 Current Link Descriptor Extended Address Register
D1ECLNDAR1
− 0xFFFAA18C
DMA 1 Current Link Descriptor Address Register
D1CLNDAR1
− 0xFFFAA190
DMA 1 Source Attributes Register
D1SATR1
− 0xFFFAA194
DMA 1 Source Address Register
D1SAR1
− 0xFFFAA198
DMA 1 Destination Attributes Register
D1DATR1
− 0xFFFAA19C
DMA 1 Destination Address Register
D1DAR1
− 0xFFFAA1A0
DMA 1 Byte Count Register
D1BCR1
− 0xFFFAA1A4
DMA 1 Next Link Descriptor Extended Address Register
D1ENLNDAR1
− 0xFFFAA1A8
DMA 1 Next Link Descriptor Address Register
D1NLNDAR1
− 0xFFFAA1AC–
0xFFFAA1AF
reserved
− 0xFFFAA1B0
DMA 1 Current List Descriptor Extended Address Register
D1ECLSDAR1
− 0xFFFAA1B4
DMA 1 Current List Descriptor Address Register
D1CLSDAR1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
9-69
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFAA1B8
DMA 1 Next List Descriptor Extended Address Register
D1ENLSDAR1
− 0xFFFAA1BC
DMA 1 Next List Descriptor Address Register
D1NLSDAR1
− 0xFFFAA1C0
DMA 1 Source Stride Register
D1SSR1
− 0xFFFAA1C4
DMA 1 Destination Stride Register
D1DSR1
− 0xFFFAA1C8–
0xFFFAA1FF
reserved
− 0xFFFAA200
DMA 2 Mode Register
D1MR2
− 0xFFFAA204
DMA 2 Status Register
D1SR2
− 0xFFFAA208
DMA 2 Current Link Descriptor Extended Address Register
D1ECLNDAR2
− 0xFFFAA20C
DMA 2 Current Link Descriptor Address Register
D1CLNDAR2
− 0xFFFAA210
DMA 2 Source Attributes Register
D1SATR2
− 0xFFFAA214
DMA 2 Source Address Register
D1SAR2
− 0xFFFAA218
DMA 2 Destination Attributes Register
D1DATR2
− 0xFFFAA21C
DMA 2 Destination Address Register
D1DAR2
− 0xFFFAA220
DMA 2 Byte Count Register
D1BCR2
− 0xFFFAA224
DMA 2 Next Link Descriptor Extended Address Register
D1ENLNDAR2
− 0xFFFAA228
DMA 2 Next Link Descriptor Address Register
D1NLNDAR2
− 0xFFFAA22C–
0xFFFAA22F
reserved
− 0xFFFAA230
DMA 2 Current List Descriptor Extended Address Register
D1ECLSDAR2
− 0xFFFAA234
DMA 2 Current List Descriptor Address Register
D1CLSDAR2
− 0xFFFAA238
DMA 2 Next List Descriptor Extended Address Register
D1ENLSDAR2
− 0xFFFAA23C
DMA 2 Next List Descriptor Address Register
D1NLSDAR2
− 0xFFFAA240
DMA 2 Source Stride Register
D1SSR2
− 0xFFFAA244
DMA2 Destination Stride Register
D1DSR2
− 0xFFFAA248–
0xFFFAA27F
reserved
− 0xFFFAA280
DMA 3 Mode Register
− 0xFFFAA284
DMA 3 Status Register
D1SR3
− 0xFFFAA288
DMA 3 Current Link Descriptor Extended Address Register
D1ECLNDAR3
− 0xFFFAA28C
DMA 3 Current Link Descriptor Address Register
D1CLNDAR3
− 0xFFFAA290
DMA 3 Source Attributes Register
D1SATR3
− 0xFFFAA294
DMA 3 Source Address Register
D1SAR3
− 0xFFFAA298
DMA 3 Destination Attributes Register
D1DATR3
− 0xFFFAA29C
DMA 3 Destination Address Register
D1DAR3
− 0xFFFAA2A0
DMA 3 Byte Count Register
D1BCR3
− 0xFFFAA2A4
DMA 3 Next Link Descriptor Extended Address Register
D1ENLNDAR3
− 0xFFFAA2A8
DMA 3 Next Link Descriptor Address Register
D1NLNDAR3
− 0xFFFAA2AC–
0xFFFAA2AF
reserved
D1MR3
− 0xFFFAA2B0
DMA 3 Current List Descriptor Extended Address Register
D1ECLSDAR3
− 0xFFFAA2B4
DMA 3 Current List Descriptor Address Register
D1CLSDAR3
− 0xFFFAA2B8
DMA 3 Next List Descriptor Extended Address Register
D1ENLSDAR3
MSC8156 Reference Manual, Rev. 2
9-70
Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFAA2BC
DMA 3 Next List Descriptor Address Register
D1NLSDAR3
− 0xFFFAA2C0
DMA 3 Source Stride Register
D1SSR3
− 0xFFFAA2C4
DMA 3 Destination Stride Register
D1DSR3
− 0xFFFAA2C8–
0xFFFAA2FF
reserved
− 0xFFFAA300
DMA General Status Register
− 0xFFFAA304–
0xFFFABC07
reserved
− 0xFFFABC08
Local Access Window Base Address Register 0
− 0xFFFABC0C–
0xFFFABC0F
reserved
− 0xFFFABC10
Local Access Window Attributes Register 0
− 0xFFFABC14–
0xFFFABC27
reserved
− 0xFFFABC28
Local Access Window Base Address Register 1
− 0xFFFABC2C–
0xFFFABC2F
reserved
− 0xFFFABC30
Local Access Window Attributes Register 1
− 0xFFFABC34–
0xFFFABC47
reserved
− 0xFFFABC48
Local Access Window Base Address Register 2
− 0xFFFABC4C–
0xFFFABC4F
reserved
− 0xFFFABC50
Local Access Window Attributes Register 2
− 0xFFFABC54–
0xFFFABC67
reserved
− 0xFFFABC68
Local Access Window Base Address Register 3
− 0xFFFABC6C–
0xFFFABC6F
reserved
− 0xFFFABC70
Local Access Window Attributes Register 3
− 0xFFFABC74–
0xFFFABC87
reserved
− 0xFFFABC88
Local Access Window Base Address Register 4
− 0xFFFABC8C–
0xFFFABC8F
reserved
− 0xFFFABC90
Local Access Window Attributes Register 4
− 0xFFFABC94–
0xFFFABCA7
reserved
− 0xFFFABCA8
Local Access Window Base Address Register 5
− 0xFFFABCAC–
0xFFFABCAF
reserved
− 0xFFFABCB0
Local Access Window Attributes Register 5
− 0xFFFABCB4–
0xFFFABCC7
reserved
− 0xFFFABCC8
Local Access Window Base Address Register 6
D1DGSR
D1LAWBAR0
D1LAWAR0
D1LAWBAR1
D1LAWAR1
D1LAWBAR2
D1LAWAR2
D1LAWBAR3
D1LAWAR3
D1LAWBAR4
D1LAWAR4
D1LAWBAR5
D1LAWAR5
D1LAWBAR6
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9-71
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
− 0xFFFABCCC–
0xFFFABCCF
reserved
− 0xFFFABCD0
Local Access Window Attributes Register 6
− 0xFFFABCD4–
0xFFFABCE7
reserved
− 0xFFFABCE8
Local Access Window Base Address Register 7
− 0xFFFABCEC–
0xFFFABCEF
reserved
− 0xFFFABCF0
Local Access Window Attributes Register 7
− 0xFFFABCF4–
0xFFFABD07
reserved
− 0xFFFABD08
Local Access Window Base Address Register 8
− 0xFFFABD0C–
0xFFFABD0F
reserved
− 0xFFFABD10
Local Access Window Attributes Register 8
− 0xFFFABD14–
0xFFFABD27
reserved
− 0xFFFABD28
Local Access Window Base Address Register 9
− 0xFFFABD2C–
0xFFFABD2F
reserved
− 0xFFFABD30
Local Access Window Attributes Register 9
− 0xFFFABD34–
0xFFFA8FFF
reserved
Acronym
D1LAWAR6
D1LAWBAR7
D1LAWAR7
D1LAWBAR8
D1LAWAR8
D1LAWBAR9
D1LAWAR9
• 0xFFFAB000–
0xFFFABFFF
DMA Controller 1 to OCN
• 0xFFFAC000–
0xFFFAC07F
SerDes PHY 1 Registers
• 0xFFFAC000
SRDS Control Register 0 for SerDes Port 1
SRDS1CR0
• 0xFFFAC004
SRDS Control Register 1 for SerDes Port 1
SRDS1CR1
• 0xFFFAC008
SRDS Control Register 2 for SerDes Port 1
SRDS1CR2
• 0xFFFAC00C
SRDS Control Register 3 for SerDes Port 1
SRDS1CR3
• 0xFFFAC010
SRDS Control Register 4 for SerDes Port 1
SRDS1CR4
• 0xFFFAC014
SRDS Control Register 5 for SerDes Port 1
SRDS1CR5
• 0xFFFAC018
SRDS Control Register 6 for SerDes Port 1
SRDS1CR6
• 0xFFFAC0020–
0xFFFACFFF
reserved
• 0xFFFAD000–
0xFFFAD007
SerDes PHY 2 Registers
• 0xFFFAD000
SRDS Control Register 0 for SerDes Port 2
SRDS2CR0
• 0xFFFAD004
SRDS Control Register 1 for SerDes Port 2
SRDS2CR1
• 0xFFFAD008
SRDS Control Register 2 for SerDes Port 2
SRDS2CR2
• 0xFFFAD00C
SRDS Control Register 3 for SerDes Port 2
SRDS2CR3
• 0xFFFAD010
SRDS Control Register 4 for SerDes Port 2
SRDS2CR4
• 0xFFFAD014
SRDS Control Register 5 for SerDes Port 2
SRDS2CR5
• 0xFFFAD018
SRDS Control Register 6 for SerDes Port 2
SRDS2CR6
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Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
• 0xFFFAD020–
0xFFFB6FFF
reserved
• 0xFFFB7000–
0xFFFB7FFF
PCI Express Registers
Acronym
− 0xFFFB7000
PCI Express Configuration Address Register
PEX_CONFIG_ADDR
− 0xFFFB7004
PCI Express Configuration Data Register
PEX_CONFIG_DATA
− 0xFFFB7008–
0xFFFB700B
reserved
− 0xFFFB700C
PCI Express Outbound Completion Timeout Register
PEX_OTB_CPL_TOR
− 0xFFFB7010
PCI Express Configuration Retry Timeout Register
PEX_CONF_RTY_TOR
− 0xFFFB7014
PCI Express Configuration Register
PEX_CONFIG
− 0xFFFB7018–
0xFFFB701F
reserved
− 0xFFFB7020
PCI Express PME and Message Detect Register
PEX_PME_MES_DR
− 0xFFFB7024
PCI Express PME and Message Disable Register
PEX_PME_MES_DISR
− 0xFFFB7028
PCI Express PME and Message Interrupt Enable Register
PEX_PME_MES_IER
− 0xFFFB702C
PCI Express Power Management Command Register
PEX_PMCR
− 0xFFFB7030–
0xFFFB70FF
reserved
− 0xFFFB7100
PCI Express Link Width Control Register
PEX_LWCR
− 0xFFFB7104
PCI Express Link Width Status Register
PEX_LWSR
− 0xFFFB7108
PCI Express Link Speed Control Register
PEX_LSCR
− 0xFFFB710C
PCI Express Link Speed Status Register
PEX_LSSR
− 0xFFFB7110–
0xFFFB7BF7
reserved
− 0xFFFB7BF8
IP Block Revision Register 1
PEX_IP_BLK_REV1
− 0xFFFB7BFC
IP Block Revision Register 2
PEX_IP_BLK_REV2
− 0xFFFB7C00
PCI Express Outbound Translation Address Register 0
PEXOTAR0
− 0xFFFB7C04
PCI Express Outbound Translation Extended Address Register 0 PEXOTEAR0
− 0xFFFB7C08–
0xFFFB7C0F
reserved
− 0xFFFB7C10
PCI Express Outbound Window Attributes Register 0
− 0xFFFB7C14–
0xFFFB7C1F
reserved
− 0xFFFB7C20
PCI Express Outbound Translation Address Register 1
− 0xFFFB7C24
PCI Express Outbound Translation Extended Address Register 1 PEXOTEAR1
PEXOWAR0
PEXOTAR1
− 0xFFFB7C28
PCI Express Outbound Window Base Address Register 1
− 0xFFFB7C2C–
0xFFFB7C2F
reserved
− 0xFFFB7C30
PCI Express Outbound Window Attributes Register 1
− 0xFFFB7C34–
0xFFFB7C3F
reserved
− 0xFFFB7C40
PCI Express Outbound Translation Address Register 2
− 0xFFFB7C44
PCI Express Outbound Translation Extended Address Register 2 PEXOTEAR2
PEXOWBAR1
PEXOWAR1
PEXOTAR2
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9-73
Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFB7C48
PCI Express Outbound Window Base Address Register 2
− 0xFFFB7C4C–
0xFFFB7C4F
reserved
− 0xFFFB7C50
PCI Express Outbound Window Attributes Register 2
− 0xFFFB7C54–
0xFFFB7C5F
reserved
− 0xFFFB7C60
PCI Express Outbound Translation Address Register 3
− 0xFFFB7C64
PCI Express Outbound Translation Extended Address Register 3 PEXOTEAR3
PEXOWBAR2
PEXOWAR2
PEXOTAR3
− 0xFFFB7C68
PCI Express Outbound Window Base Address Register 3
− 0xFFFB7C6C–
0xFFFB7C6F
reserved
− 0xFFFB7C70
PCI Express Outbound Window Attributes Register 3
− 0xFFFB7C74–
0xFFFB7C7F
reserved
− 0xFFFB7C80
PCI Express Outbound Translation Address Register 4
− 0xFFFB7C84
PCI Express Outbound Translation Extended Address Register 4 PEXOTEAR4
PEXOWBAR3
PEXOWAR3
PEXOTAR4
− 0xFFFB7C88
PCI Express Outbound Window Base Address Register 4
− 0xFFFB7C8C–
0xFFFB7C8F
reserved
− 0xFFFB7C90
PCI Express Outbound Window Attributes Register 4
− 0xFFFB7C94–
0xFFFB7D9F
reserved
− 0xFFFB7DA0
PCI Express Inbound Translation Address Register 3
− 0xFFFB7DA4–
0xFFFB7DA7
reserved
− 0xFFFB7DA8
PCI Express Inbound Window Base Address Register 3
− 0xFFFB7DAC
PCI Express Inbound Window Base Extended Address Register 3 PEXIWBEAR3
− 0xFFFB7DB0
PCI Express Inbound Window Attributes Register 3
− 0xFFFB7DB4–
0xFFFB7DBF
reserved
− 0xFFFB7DC0
PCI Express Inbound Translation Address Register 2
− 0xFFFB7DC4–
0xFFFB7DC7
reserved
− 0xFFFB7DC8
PCI Express Inbound Window Base Address Register 2
− 0xFFFB7DCC
PCI Express Inbound Window Base Extended Address Register 2 PEXIWBEAR2
− 0xFFFB7DD0
PCI Express Inbound Window Attributes Register 2
− 0xFFFB7DD4–
0xFFFB7DDF
reserved
− 0xFFFB7DE0
PCI Express Inbound Translation Address Register 1
− 0xFFFB7DE4–
0xFFFB7DE7
reserved
− 0xFFFB7DE8
PCI Express Inbound Window Base Address Register 1
− 0xFFFB7DEC–
0xFFFB7DEF
reserved
− 0xFFFB7DF0
PCI Express Inbound Window Attributes Register 1
PEXOWBAR4
PEXOWAR4
PEXITAR3
PEXIWBAR3
PEXIWAR3
PEXITAR2
PEXIWBAR2
PEXIWAR2
PEXITAR1
PEXIWBAR1
PEXIWAR1
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Freescale Semiconductor
Detailed System Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFB7DF4–
0xFFFB7DFF
reserved
− 0xFFFB7E00
PCI Express Error Detect Register
− 0xFFFB7E04–
0xFFFB7E07
reserved
− 0xFFFB7E08
PCI Express Error Interrupt Enable Register
− 0xFFFB7E0C–
0xFFFB7E0F
reserved
− 0xFFFB7E10
PCI Express Error Disable Register
− 0xFFFB7E14–
0xFFFB7E1F
reserved
− 0xFFFB7E20
PCI Express Error Capture Status Register
− 0xFFFB7E24–
0xFFFB7E27
reserved
− 0xFFFB7E28
PCI Express Error Capture Register 0
PEX_ERR_CAP_R0
− 0xFFFB7E2C
PCI Express Error Capture Register 1
PEX_ERR_CAP_R1
− 0xFFFB7E30
PCI Express Error Capture Register 2
PEX_ERR_CAP_R2
− 0xFFFB7E34
PCI Express Error Capture Register 3
PEX_ERR_CAP_R3
PEX_ERR_DR
PEX_ERR_EN
PEX_ERR_DISR
PEX_ERR_CAP_STAT
− 0xFFFB7E38– 0x reserved
FFFB7FFF
• 0xFFFBB000–
0xFFFBB7FF
RapidIO/PCI Express Security Bridge Registers
• 0xFFFBB800–
0xFFFBB8FF
Performance Monitor
− 0xFFFBB800
Performance Monitor Global Control Register
− 0xFFFBB804–
0xFFFBB80F
reserved
PMGCR
− 0xFFFBB810
Performance Monitor Local Control Register A0
− 0xFFFBB814
reserved
− 0xFFFBB818
Performance Monitor Counter 0
− 0xFFFBB81C–
0xFFFBB81F
reserved
− 0xFFFBB820
Performance Monitor Local Control Register A1
PMLCA1
− 0xFFFBB824
Performance Monitor Local Control Register B1
PMLCB1
− 0xFFFBB828
Performance Monitor Counter 1
PMC1
− 0xFFFBB82C–
0xFFFBB82F
reserved
− 0xFFFBB830
Performance Monitor Local Control Register A2
PMLCA2
− 0xFFFBB834
Performance Monitor Local Control Register B2
PMLCB2
− 0xFFFBB838
Performance Monitor Counter 2
PMC2
− 0xFFFBB83C–
0xFFFBB83F
reserved
− 0xFFFBB840
Performance Monitor Local Control Register A3
PMLCA3
− 0xFFFBB844
Performance Monitor Local Control Register B3
PMLCB3
− 0xFFFBB848
Performance Monitor Counter 3
PMC3
PMLCA0
PMC0
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Memory Map
Table 9-7. Detailed System Memory Map (Continued)
Address
Name/Status
Acronym
− 0xFFFBB84C–
0xFFFBB84F
reserved
− 0xFFFBB850
Performance Monitor Local Control Register A4
PMLCA4
− 0xFFFBB854
Performance Monitor Local Control Register B4
PMLCB4
− 0xFFFBB858
Performance Monitor Counter 4
PMC4
− 0xFFFBB85C–
0xFFFBB85F
reserved
− 0xFFFBB860
Performance Monitor Local Control Register A5
PMLCA5
− 0xFFFBB864
Performance Monitor Local Control Register B5
PMLCB5
− 0xFFFBB868
Performance Monitor Counter 5
PMC5
− 0xFFFBB86C–
0xFFFBB86F
reserved
− 0xFFFBB870
Performance Monitor Local Control Register A6
PMLCA6
− 0xFFFBB874
Performance Monitor Local Control Register B6
PMLCB6
− 0xFFFBB878
Performance Monitor Counter 6
PMC6
− 0xFFFBB87C–
0xFFFBB87F
reserved
− 0xFFFBB880
Performance Monitor Local Control Register A7
PMLCA7
− 0xFFFBB884
Performance Monitor Local Control Register B7
PMLCB7
− 0xFFFBB888
Performance Monitor Counter 7
PMC7
− 0xFFFBB88C–
0xFFFBB88F
reserved
− 0xFFFBB890
Performance Monitor Local Control Register A8
PMLCA8
− 0xFFFBB894
Performance Monitor Local Control Register B8
PMLCB8
− 0xFFFBB898
Performance Monitor Counter 8
PMC8
− 0xFFFBB89C–
0xFFFBB8FF
reserved
• 0xFFFBB900–
0xFFFCFFFF
reserved
• 0xFFFD0000–
0xFFFDFFFF
Reserved
• 0xFFFE0000–
0xFFFFEFFF
reserved
0xFFFFF000–
0xFFFFFFFF
reserved
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10
MSC8156 SC3850 DSP Subsystem
Each SC3850 core is embedded in an DSP subsystem that enhances the power of the SC3850
core and provides a simple interface to each SC3850 core. The DSP core subsystem includes:
„
„
„
„
„
„
„
„
„
SC3850 core.
Instruction channel with a 32-Kbyte instruction cache that supports advanced prefetching.
Data channel built around a 32-Kbyte data cache, which supports advanced prefetching.
Memory management unit (MMU) for task protection and address translation.
Unified 512-Kbyte L2 cache with partitioning support for multitasking reconfigurable in
64-Kbyte partitions as M2 memory.
Write queue that interfaces between the core and the data channel
Dual timer for internal use (such as RTOS).
Extended programmable interrupt controller (EPIC) supporting 256 interrupts.
Real-time debug support with the OCE and a debug and profiling unit (DPU).
Interrupts
Master MBus
222
128
DMA Bus
128
M2 DMA Bus (128 bits wide)
DMA Bridge
L2 Cache
EPIC
Debug Support
Timer
DPU
Instruction
Channel
MMU
Data
Channel
OCE
Write Queue
64
SC3850 Core
64
128
Xa
Xb
P
Figure 10-1. DSP Core Subsystem
MSC8156 Reference Manual, Rev. 2
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10-1
MSC8156 SC3850 DSP Subsystem
Note:
The SC3850 DSP Core Reference Manual and the MSC8156 SC3850 DSP Core
Subsystem Reference Manual have detailed information on the DSP core and core
subsystem. Both manuals are available with a signed non-disclosure agreement.
Contact your local Freescale dealer or sales representative for more information.
The remainder of this chapter describes each of these DSP core subsystem components.
10.1
SC3850 DSP Core Subsystem Features
The subsystem has the following units and distinctive features:
„ SC3850 DSP core (see Chapter 2, SC3850 Core Overview for details).
„ Instruction cache (ICache):
— 32 Kbytes
— 8 ways with 16 lines per way
— Multi-task support
— Real-time support through locking flexible boundaries
— Prefetch capability
— Software coherency support (‘Sweep’)
— PFETCH touch loading instruction support
„ Data cache (DCache):
— 32 Kbytes
— 8 ways with 16 lines per way
— Can serve two data accesses in parallel (XA, XB)
— Multi-task support
— Real-time support through locking flexible boundaries
— Software coherency support (Cache ISA or “Sweep”)
— Write-back writing policy
— Write-through writing policy
— Hardware line prefetch capability
— Cache performance ISA support (DFETCH touch loading and DMALLOC)
„ Memory management unit (MMU):
— Virtual to physical address translation
— Task protection
— Multi-tasking
— Defines the memory and access attributes of memory regions
„ Unified L2 cache:
— 512 KB
— 8 ways with 1024 indices
— 64-byte line size
— Physically addressed
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Freescale Semiconductor
SC3850 Core
„
„
„
„
10.2
— Maximum user flexibility for real-time support through address partitioning of the
cache
— Rich cache policy support
— Multi channel, two dimensional software prefetch support
— Software coherency support with seamless transition from L1 cache coherency
operation.
— External memory Interface:
— MBus unified address separate data bus, with 32-bit address and 128-bit data
— Supports asynchronous clock ratio
Debug and profiling:
— On-chip emulator (OCE) for core-related debug and profiling support
— Debug and profiling unit (DPU) for subsystem level debug and profiling support
— Debug state, single stepping and command insertion from the host debugger
— Breakpoints on PC, data address, and data bus values
— More than 40 event counting options in 6 parallel counters
— Cache debug mode enabling to observe the cache state (cache array, tags, valid and
dirty bits, and so on) and to change the contents of the data cache array.
— Real-time tracing of PC, task ID, and profiling information to the main memory
Interrupt handling:
— Extended programmable interrupt controller (EPIC) to handle 256 interrupts, including
from internal sources
— Supports 222 interrupts external to the MSC8156 SC3850 DSP subsystem,
independently configured as maskable or non-maskable
— 32 priority levels for interrupts
— Asynchronous and synchronous interrupts.
Timer. Two general-purpose 32-bit timers for RTOS support
Low-power design modes of operation:
— Wait processing state, where the clocks of the core and caches are gated but
peripherals operate.
— Stop processing state for full clock gating
SC3850 Core
The SC3850 core is an improved superset of the SC3400 architecture that is binary compatible
with the previous StarCore architectures, including the SC140/SC140e and SC3400. The SC3850
core is organized the same way as the StarCore architectures. See Chapter 2, SC3850 Core
Overview and the SC3850 DSP Core Reference Manual for details on the SC3850 core.
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10-3
MSC8156 SC3850 DSP Subsystem
10.3
Instruction Channel
The instruction channel, which comprises the instruction cache (ICache) and the instruction fetch
unit (IFU), provides the core with instructions that are stored in higher-level memory. The ICache
operates at core speed and stores recently accessed instructions. Whenever an addressed
instruction (from the cacheable memory area) is found in the array, it is immediately made
available to the core (ICache hit). When the required address is not found in the array, it is loaded
to the ICache from the external (off-subsystem) memory by the IFU (ICache miss). The IFU
operates in parallel with the core to implement a HW line prefetching algorithm that loads the
ICache with information that has a high probability of being needed soon. This action reduces the
number of cache misses. When an instruction is addressed from a non-cacheable area, the IFU
fetches it directly to the XP bus of the core without writing it to the cache.
10.3.1 Instruction Cache
The ICache has the following parameters:
„ A size of 32 Kbytes with 256 bytes per cache line (total of 128 lines in the cache) arranged
in an 8 way set-associative structure.
„ A cache line logically divided into 16 valid bit resolutions (VBRs), each 16 bytes long.
This is the resolution for hit or miss detection.
Upon a cache miss, the ICache fetches the required information. A pseudo-LRU replacement
algorithm is used to select the line to be replaced when required. The flexible ICache has a
locking mechanism that can lock some ways, thus partitioning the cache between tasks. The
programmer can flush the full contents of the ICache (meaning, invalidate all tags and VBRs) or
selectively flush its contents between programmable address boundaries.
The cache fetches a core instruction for touch loading (PFETCH) by queuing it and initiating it
when there is a free slot on the program bus. Using this touch loaded instruction can dramatically
reduce the average cache miss penalty. In addition, a programmable HW next line prefetch is
used to further reduce the miss ratio for code that is sequential in nature.
The ICache supports real-time and non-real-time debugging and profiling. In real time, it
provides information on misses and hits. In non-real-time, it supports access to all its internal
information, namely, the tag, the replacement status, and the valid arrays. The cache array itself
can be either read or written. This information is accessed through the JTAG interface in Debug
processing state.
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Data Channel
10.3.2 Instruction Fetch Unit
The IFU controls the fetching of instructions from cacheable external memory when a miss
indication is received from the ICache. It controls information updates in the ICache. The
programmer can control the IFU HW line prefetching to adjust it for better performance for an
application. For a request from a non-cacheable area, the information from the external memory
is made available directly to the core through the XP bus. To minimize the idle time of the core,
the IFU implements critical word first external access and also supports prefetch hit.
10.4
Data Channel
The data channel comprises the data cache (DCache), the data fetch unit (DFU), the data control
unit (DCU), the write-back buffer (WBB), and the write-through buffer (WTB). This two-way
channel reads and writes information from the core to/from higher-level memory (M2 or L2) and
control memory (internal blocks and external peripherals) spaces.
The DCache, which operates at core speed, keeps the recently accessed data. When addressed
data (from a cacheable memory area) is found in the array, it is immediately made available to the
core (DCache hit) in a read and updated if written to. When the required address is not found in
the array, a DCache miss occurs, and the DFU loads the data to the DCache from the external
(off-subsystem) memory and drives it to the core. The DFU operates in parallel with the core and
implements a HW line prefetch algorithm that loads the DCache with information that has a high
probability of being needed soon, thus reducing the number of data cache misses.
The channel differentiates between cacheable and non-cacheable addresses. For cacheable
addresses, it supports the write-back allocate and write-through writing policies. The selection is
made on an address segment basis, as programmed in the MMU. The data channel supports the
arrangement of data in big-endian formats. Core data types can be byte, word, long (4 bytes), or 2
long (8 bytes) wide.
10.4.1 Data Cache
The DCache has the following parameters:
„ A size of 32 Kbytes with 256 bytes per cache line (total of 128 lines in the cache) arranged
in an 8 way set-associative structure.
„ A cache line logically divided into 16 VBRs, each 16 bytes long. This is the resolution for
hit or miss detection. Big-endian byte arrangements are supported.
A data access that is identified as a hit in the DCache is served without freezing the core, with the
exception of DCache contention (dual access from two core buses to the same module). If the
requested data is not in the cache, the DFU fetches it. If the requested data belongs to a cache line
that is not in the cache, the line is allocated at the expense of another line. A pseudo-LRU
(PLRU) replacement algorithm selects the line to be replaced. If the line to be replaced contains
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10-5
MSC8156 SC3850 DSP Subsystem
valid and dirty VBRs, it must be written (thrashed) to the external memory. The DCache
implements the write-back and write-through writing policies. To speed up the freeing of the
cache line, a write is directed to the write-back buffer and later copied from there to the external
memory.
The DCache enables the system/software architect to control its operation. A locking mechanism
with global locking or partial locking helps reduce the penalty of restoring critical tasks.
A great deal of control flexibility is offered by the sweep command, by which information in the
DCache is managed according to its virtual address. The programmer defines a virtual address
range and a specific operation to be carried out on cache lines within that range. The operation
can involve line invalidation, line synchronization, or line flush. The operation can execute in
parallel with core operation. The core can be interrupted at the end of the operation. In addition to
sweep, the cache supports SC3850 coherency instructions Flush memory block (DFLUSH) that
writes back and invalidates a block of 64 bytes belonging to the specified address and
Synchronize memory block (DSYNC) that writes back a block of 64 bytes belonging to the
specified address back to memory.
The cache supports touch loading data fetch core instructions (DFETCH) by queuing them and
initiating them when there is a free slot on the data bus. Using this instruction can dramatically
reduce the average cache miss penalty.
The cache also supports the data memory allocation instruction (DMALLOC), which causes the
cache to allocate a line matching the designated address and validating a 64 byte resolution
(wrapped on 64-byte boundary) with almost zero overhead without actually fetching the data
from memory.
The DCache supports real-time and non-real-time debugging and profiling. In real time, it
provides information on misses, hits, and other cache-related events. In non-real time (debug
processing state), it enables access to all of its internal information, such as the tag, the PLRU,
the valid arrays, and the DCache array. The cache array can be written to as well. This
information is accessed through the JTAG interface in debug processing state.
10.4.2 Data Fetch Unit
The DFU controls data fetches from cacheable external memory when it receives a miss
indication from the DCache. The unit controls information updates in the DCache. The
programmer can control its HW line prefetch to adjust for better performance for an application.
For a request from a non-cacheable area, the information from the external memory is made
available directly to the core through the requesting bus, WA or WB without updating the cache.
The programmer can control the burst size, as well as turn the HW line prefetch mechanism on or
off. To minimize the time that the core stalls, the DFU implements critical word first external
access and also supports prefetch hit.
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Data Channel
10.4.3 Write-Back Buffer
The WBB expedites freeing of the DCache to enable fetching of new data with minimal core
delay. Modified data from the DCache array is transferred to the WBB, thus freeing the array for
additional data fetch from a higher-level memory. This effectively splits the thrashing process
into two separate operations. During the first operation, the data to be thrashed is stored in the
WBB until after the fetch operation completes. The second operation writes the data to be
thrashed out to the higher-level memory.
The WBB has the size of 16 VBRs arranged as 8 entries of 2 VBRs each. It operates as a FIFO
buffer. It sends data to the external memory using the QBus protocol through the DCU. It
provides the DCU with priority information, either normal or high. Normal priority is used for
standard DCache line replacement. High priority is used for the DCache flushing operation.
The WBB also snoops the external core accesses (the physical addresses that are translated from
the virtual addresses by the MMU) to detect a hazard situation in which a request is made for a
line in the WBB before it gets to the higher-level memory. When such a situation occurs, the
WBB is flushed as a high priority request for updating the higher-level memory before fetching
from the memory continues. This ensures data coherency.
10.4.4 Write-Through Buffer
The WTB provides a short route for writing data to the data QBus memory space, meaning to
external (off-subsystem) memory through the MBus and to internal subsystem registers and
external peripherals. The WTB block generates write accesses from the write queue output buses
to the devices connected to the data QBus when the application requires a non-cacheable or
write-through write access. The WTB also serves write accesses when the cache is disabled, in
debug, or missed when in lock. The WTB is arranged as six 64-bit entries. It operates as a FIFO
buffer to buffer the latency of the write accesses passing through it from the DSP core.
10.4.5 Data Control Unit
The DCU prioritizes and arbitrates between the various write transactions (from the WBB, the
WTB, and the trace writes from the TWB) and the read transactions of the DFU. The DCU
transfers the transactions to the data QBus after mastership on the bus is obtained or directly
when it accesses the internal subsystem memory-mapped registers.
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10.4.6 Write Queue
The write queue (WRQ) interfaces between the SC3850 core and the data channel. The WRQ
stores up to 14 write accesses from both the XA and the XB buses and has the following primary
functions:
„ Bridge the core pipeline gap between the address generation and the data drive.
„ Enable read accesses to bypass write accesses (unless there is a read after write hazard).
„ Store write accesses (already with data) until they have an available memory slot, thus
freeing the core to execute instructions.
„ Identify a read-after-write hazard and forward newer write data of pending accessed to
replace the older data bytes were read from memory.
„ Handles core DCache instructions like DFETCH, DSYNC, DMALLOC, and others.
„ Buffer DFETCH and write-back misses that the system currently can not handle without
stalling the core until the WRQ is full.
10.5
Memory Management Unit (MMU)
The MMU performs three main functions:
„ Memory hardware protection for instruction and data access with two privilege levels
(user and supervisor).
„ High-speed address translation from virtual to physical address to support memory
relocation.
„ Cache and bus controls for advanced memory management
Memory protection increases the reliability of the system so that errant tasks cannot ruin the
privileged state and the state of other tasks. Program and data accesses from the core can occur at
either the user or supervisor level. The MMU checks each access to determine whether it matches
the permissions defined for this task in the memory attributes and translation table (MATT). If it
does not, the access is killed and a memory exception is generated.
The MMU performs address translation on external (off-subsystem) addresses, from virtual
addresses (used by the software that runs on the core) to physical addresses (used by the system
buses). Benefits of address translation include the following:
„ Enables software to be written without consideration of the physical location of the code
in memory, thereby providing a simpler software model that enhances modularity and
reuse.
„ Allows true dynamic code relocation without performance cost or overhead.
The same virtual addresses can be reused between tasks without a need to flush the caches
between tasks because the caches store the task ID in their line tags and thus have a unique
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L2 Cache
memory image per task. Protection and address translation are applied to memory segments
defined in the MMU. A segment descriptor (SD) can set cacheable/non-cacheable, prefetch
policy, shared/non-shared, and more. The MMU controls up to 20 data and up to 12 program
segment descriptors.
The MSC8156 SC3850 DSP subsystem introduces a new programming model for more flexible
memory mapping of the SD that reduces previous constraints allowing reduction in the number of
descriptors needed and memory waste. For compatibility, the MMU also supports the old
programming model.
10.6
L2 Cache
The L2 cache processes data and program accesses to the external M3/DDR memory. Caching
the accesses requested by the L1 subsystem reduces the average penalty of accessing the high
latency M3. The L2 cache includes a slave arbitration and tag unit, cache logic and arrays, along
with a write buffer for write back and write through accesses, fetch logic to fetch data from the
off platform memory upon a miss or a non-cacheable access, and a master arbiter that arbitrates
between the different internal units.
Features of the L2 cache are as follows:
„ A size of 512 Kbytes with 64 bytes per cache line (total of 8192 lines in the cache)
arranged in an 8 way set-associative structure.
„ 64Byte valid bit resolution (VBR) and dirty bit resolution (DBR). Fetch the whole line at
once. Write back the whole line at once when a dirty line is thrashed from the cache.
„ Physically addressed
„ Dynamically configurable as a DMA accessible M2 RAM
„ Software coherency support with seamless transition from L1 cache coherency operation
„ Multichannel (4) L2 software prefetch for two-dimensional arrays
„ Cache partitioning by way
„ Write policies:
— Non-cacheable and non-cacheable on read and write (NC)
— Cacheable write-through and cacheable on read non-cacheable on write (WT). Update
the cache on hit.
— Cacheable write back; both read and write are cacheable (WB)
— Adaptive write policy (AWP). Cacheable WB on hit and NC on miss.
„ WB composed of eight 32-byte entries
„ Full ECC support
The main components of the L2 cache are as follows:
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„ L2 Qbus arbiter (L2Q) to arbitrate the input data QBus, instruction QBus, and the slave
port to one output bus (necessary because the cache serves one access per cycle).
„ Cache logic to manage the cache arrays and state machines
„ Fetch unit (L2FU) to fetch cacheable accesses from the M3/DDR memory, including L2
SW prefetching of data and instructions not yet requested by the core.
„ Write buffer (L2WB) to temporarily hold modified (dirty) cache lines thrashed by the
cache and also serve as a buffer for non-cacheable memory.
„ Arbitration unit (L2AU) to arbitrate among the different masters (access generators) of the
L2 cache (L2FU and L2WB).
„ QBus to MBus interface (Q2M) to interface the external memory IF bus asynchronously
while maintaining the pipeline.
„ Register file to hold the L2 cache status and control registers. Mapped to the internal
peripherals on bank0.
10.7
On-Chip Emulator and Debug and Profiling Unit
The on-chip emulator (OCE) and the debug and profiling unit (DPU) are hardware blocks for
debugging and profiling. The OCE performs the following tasks:
„ Communicates with the host debugger through the SoC JTAG test access port (TAP)
controller
„ Enables the SC3850 core to enter the debug processing state upon a varied set of
conditions to:
— Single step
— Execute core commands inserted from the host debugger to upload and download
memory and core registers.
„ Sets up to six address-related breakpoints on either PC or a data address
„ Sets a data breakpoint on a data value, optionally combined with a data address
„ Generates the PC tracing flow, optionally filtered to a subset of events such as only
jumps/returns from subroutine, interrupts, and so on.
The DPU has the following characteristics:
„ Enables parallel counting of subsystem events in six dedicated counters, from more than
40 events
„ Filters, processes, and adds task ID and profiling information on the OCE PC trace
information
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Extended Programmable Interrupt Controller
10.8
Extended Programmable Interrupt Controller
The internal extended programmable interrupt controller (EPIC) manages internal and external
interrupts. The EPIC handles up to 256 interrupts, 222 of which are external subsystem inputs.
The rest of the interrupts serve internal subsystem conditions. The external interrupts can be
configured as either maskable interrupts or non-maskable interrupts (NMIs). The EPIC can
handle 33 levels of interrupt priorities, of which 32 levels are maskable at the core and 1 level is
NMI.
10.9
Timer
The timer block includes two 32-bit general-purpose counters with pre-loading capability. It
counts clocks at the core frequency. It is intended mainly for operating system use.
10.10 Interfaces
The interfaces transfer data from the subsystem to the rest of the system and vice versa.
10.10.1 QBus to MBus Interface Bridge
The instruction QBus to MBus interface (IQ2MA) bridge translates the bus from the L2 Cache,
which uses the proprietary QBus protocol, to the MBus line protocol. The Q2M is placed
between two different asynchronous clock domains:
„ Internal, MSC8156 SC3850 DSP subsystem clock domain
„ External (out of subsystem) clock domain, which is slower or equal to the internal clock
domain.
10.10.2 MBus to DMA Bridge
The MBus to DMA bridge converts the signals coming from the MBus to the protocol used by
the L2 Cache slave port. The bridge is placed between two different asynchronous clock
domains:
„ Internal, MSC8156 SC3850 DSP subsystem clock domain
„ External (out of subsystem) clock domain, which is slower or equal to the internal clock
domain.
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10.11 Entering and Exiting Wait and Stop States Safely
The following subsections describe how to enter and exit from the Wait and Stop states safely.
10.11.1 Wait State
The Wait state is described in Section 2.12.4 of the MSC8156 SC3850 DSP Subsystem Reference
Manual. The subsystem enters the Wait processing state when the SC3850 core executes the wait
instruction. The subsystem exits from the Wait state when an enabled level interrupt request is
asserted or the subsystem transfers to the Debug or Reset state. During a Wait state, the
subsystem L2/M2 memory is available for access through the slave port. No further steps are
required.
10.11.2 Stop State
The Stop state is described in Section 2.12.5 of the MSC8156 SC3850 DSP Subsystem Reference
Manual.
10.11.2.1 Procedure for Entering DSP Subsystem Stop State Safely
Note:
Before entering the Stop state, terminate any L2 software prefetch activities to reduce
the time needed to enter Stop.
Use the following procedure to enter the Stop state:
1.
Stop all accesses to the M2/L2 memory in the core subsystem by peripherals and
external hosts (if applicable).
2.
Close the subsystem slave port window by writing a 1 to the relevant bit in the
CORE_SLV_GCR (see Section 8.2.34, Core Subsystem Slave Port General
Configuration Register (CORE_SLV_GCR), on page 8-59 for details).
3.
Read the CORE_SLV_GCR to make sure that the 1 is written and the bit is set.
Note:
After the slave port window is closed, all core accesses will generate an error interrupt
to the core.
4.
Send a read request from the specified core and subsystem to an adjacent core M2
according to its index, as follows: from Core0 to Core1, from Core1 to Core0, from
Core2 to Core3, or from Core3 to Core2.
5.
Step 4 generates an address error interrupt. Read GIR5 to make sure that the interrupt is
generated by the specified core (see Section 8.2.25, General Interrupt Register 5
(GIR5), on page 8-40 for details).
6.
Make sure that the appropriate Stop ACK is asserted in GSR1. If not, assert the bit. (see
Section 8.2.3, General Status Register 1 (GSR1), on page 8-5 for details).
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Entering and Exiting Wait and Stop States Safely
7.
Issue a stop command to the specified core.
10.11.2.2 Procedure for Exiting the Stop State Safely
Use the following process to exit from the Stop state:
1.
Initiate an enabled level subsystem interrupt. This causes the subsystem to exit the Stop
state.
2.
The core will open its own slave port window by deasserting the relevant bit in the
CORE_SLV_GCR (see Section 8.2.34, Core Subsystem Slave Port General
Configuration Register (CORE_SLV_GCR), on page 8-59).
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Internal Memory Subsystem
11
The internal memory system supports 4.5 MB of internal memory and includes:
„
„
„
„
„
Memory management unit (MMU) per core.
Instruction channel with 32 KB L1 ICache per core.
Data channel with 32 KB L1 DCache per core.
512 KB L2 shared unified Cache, configurable in 64 KB blocks as M2 memory, per core.
1 MB + 32 KB 128-bit wide M3 memory connected to three internal memory buses. The
1 MB block can be turned off to reduce power consumption. The M3 memory supports
semaphores and the RapidIO mail boxes.
„ 96 KB of boot ROM accessible from the cores.
Note:
The MMU, L1 ICache, L1 DCache, and L2 Cache/M2 memory are part of the
MSC8156 SC3850 DSP core subsystem. For detailed programming and functional
information, refer to the MSC8156 SC3850 DSP Core Reference Manual, available
with a signed non-disclosure agreement. Contact your local Freescale dealer or sales
representative for more information.
Note:
The default burst size for the caches and MMU is 1 VBR, but for most operations,
programming the burst size as 4 VBR provides the best performance.
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Internal Memory Subsystem
11.1
Memory Management Unit (MMU)
The MMU provides a high-speed address translation mechanism to enable memory relocation,
and checks access permissions for core instructions and data buses. It also controls hardware task
protection and provides cache and bus controls for advanced memory management. The MMU
enables better integration of system resources and defines a cleaner software model. For example,
programing protected regions, address translation regions, cacheable regions, and so on can be
combined. In addition, cache usage can be optimized based on the specific attributes controlled
by the MMU programming. For memory protection, the MMU enables the implementation of an
RTOS with MMU support, thereby protecting the operating system, task code, and data from
errant tasks. Address translation enables implementation of a software model in which the code
uses virtual addresses that are translated to physical addresses accessing memory. The MMU
provides a virtual memory software model with a hole for the OCE and internal device registers
and peripherals. The core generates virtual addresses during its operation. The virtual address
together with the task ID from the MMU become the task-extended (TE) virtual address. The
MMU translates between virtual and physical addresses during each core access, providing
control attributes for each core access per memory segment, such as burst size, prefetch enable,
write-policy, cacheability, and so forth.
The MMU has the following functions and features:
„ A memory attributes and translation table (MATT), composed of 20 data segment
descriptors and 12 program segment descriptors.
„ Each segment descriptor defines a related memory region and its cache and attributes,
protection and address translation.
„ The descriptor related memory space has a long-range variable mapping size. The size is
designated in steps as a power of 2, starting from 256 bytes. The mapping size can be
between 256 bytes to 4 GB. The base address must be aligned to a segment size.
„ The memory region dedicated cache and attributes support the following:
— Cacheable access.
— A burst size of 1, 2, or 4 for the data fetch unit (DFU) and instruction fetch unit (IFU).
— Hardware line prefetch enable.
— Hardware next line prefetch enable (instruction only)
— System/shared attributes
— Write policy for data memory
— L2 cache policy
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Instruction Channel (ICache and IFU)
„ Hardware data and program access protection is defined for each data/program memory
region for two privilege levels: user and supervisor. The MMU provides abort signals for
the Xa/Xb/P buses for errant accesses. The MMU provides memory region support, as
follows:
— For the program memory region, provides read allowed/not allowed access for both the
Supervisor and User levels
— For the data memory region, provides read/write allowed/not allowed for both the
Supervisor and User levels
„ Address translation is defined for each data/program memory region, enabling allocation
of a virtual memory region to a valid physical memory space.
„ Priority mechanism between descriptors, allowing memory regions overlapping.
„ Stores the program task ID and data task ID for multi-task mechanism. Up to 255 different
Program IDs and 255 different data IDs are available.
„ Subsystem ID register and general-purpose register among its control and status registers.
„ Access error detection including non-mapped memory access and misaligned memory
access.
„ Captures error status bits and enables a fast error diagnostic.
„ Precise interrupts allowing handling MMU MATT misses supporting a virtually paged
operating system.
„ Core branch target buffer (BTB) that enables manual and automatic BTB maintenance.
„ Subsystem error detection code (EDC) recovery scheme.
„ Enable/disable EDC exception mechanism.
„ Subsystem master and slave error handling.
„ Program and data query mechanism.
11.2
Instruction Channel (ICache and IFU)
The Instruction Channel comprises the Instruction Cache (ICache) and the Instruction Fetch Unit
(IFU). This channel provides the core with instructions that are stored in higher-level memory.
The ICache, which operates at core speed, stores recently accessed instructions. Whenever an
addressed instruction (from the cacheable memory area) is found in the array, it is immediately
made available to the core (ICache hit). When the required address is not found in the array, it is
loaded to the ICache from the external (not part of the DSP core subsystem) memory by the IFU
(ICache miss). The IFU operates in parallel to the core to implement a prefetch algorithm that
loads the ICache with information that with high probability will be needed soon. This action
reduces the number of cache misses. Whenever an instruction is addressed from a non-cacheable
area, the IFU fetches it directly to the P bus of the core without writing it to the cache.
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Internal Memory Subsystem
Instruction channel features include:
„ Aligned 128-bit XP core accesses.
„ Concurrent cacheable and non-cacheable accesses, as identified in the MMU based on the
address ranges.
„ Task-extended virtually addressed cache. The 8-bit task ID from the MMU is stored as
part of the line tag that allows a task-specific cache image that is not overridden by other
tasks that use the same virtual address. This feature can support multi-task mechanism.
This extended tag is named the ETAG.
„ Cacheable shared memory between tasks marked by the MMU according to the memory
range, and stored in the cache with TASKID 0.
„ Cache hit access without wait states (except during memory conflicts).
„ Issues 128-bit accesses to the higher level memory when a cache miss occurs.
„ Programmable to issue hardware line prefetch accesses upon cache miss that fetch data to
the end of the cache line (256 bytes).
— Hardware line prefetching is aborted in case of a new miss on a burst size boundary.
— Programmable burst size of 1, 2, or 4 VBRs.
„ A miss access identified as a prefetch by the prefetch hit stalls the core to reduce the
number of wait states relative to a simple miss.
„ Automatic hardware next line prefetch on a mis or a hit to a previously fetched line
controlled by the MMU.
„ Supports SC3850 core touch loading PFETCH command that allows the user to prepare
specific memory lines in the cache to reduce or remove the penalty for miss accesses.
„ Pseudo-LRU (PLRU) as the cache line replacement mechanism (LRM).
„ Partial lock allows locking of a subset of cache lines based on ways boundaries to reduce
the cache restoration penalty of a restored task. Instructions can be locked in the cache,
preventing the thrashing of instructions that have expected reuse. This mechanism is
useful during rapid task switching and prevents a situation in which a task thrashes
important instructions associated with other tasks.
„ Global lock allows locking of all cache lines to reduce the cache restoration penalty of a
restored task. In this case, the cache does not serve cache misses.
„ User-initiated cache sweep operations for coherency support. These operations are
performed on each line in a user-specified address range. An invalidate discards the cache
line (clears the valid bits).
„ Cache debug mode in which the cache state (ETAG values, Valid, PLRU state) can be
read and the memory array can be read or written.
„ Dedicated programmable cache control registers that control or reflect its operation.
„ EDC (error detection) support.
„ Dedicated exceptions for each of the following events:
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Data Channel and Write Queue (DCache)
— End of sweep operation. This exception indicates the completion of the sweep
operation.
— XP non-cacheable hit access. This exception indicates that an access is a hit access,
even though the MMU classifies it as a non-cacheable access. This type of situation
can occur if the memory space attributes changed in the MMU without invalidating the
appropriate cache lines Assertion of the exception is not guaranteed when the attribute
change that led to this error is not performed with SYNCIO as restricted.
— XP double match. This is an error that occurs when a task-shared access has an address
that matches a non-shared cache line.
11.3
Data Channel and Write Queue (DCache)
The data channel and write queue is a two-way channel for reading and writing information from
the core to/from higher level memory (M2 or L2) and Control Memory (internal blocks and
external peripherals) spaces. The DCache, which operates at core speed, keeps the recently
accessed data. Whenever addressed data (from a cacheable memory area) is found in the array, it
is immediately made available to the core (DCache hit) in a read, and updated if written. When
the required address is not found in the array, a DCache miss occurs, and the data is loaded to the
DCache from the external (not part of the DSP core subsystem) memory by the DFU, and driven
through the write queue to the core.
The data channel is fed by accesses from the write queue buses and not directly from the core
XA/XB data buses. Data reads are normally forwarded directly from the write queue, so there is
no delay in processing them. On the other hand, data writes can be delayed for extended periods
in the write queue. Therefore, they are bypassed by read accesses and their processing in the data
channel is completely detached from the core execution flow. The write queue performs the
necessary hazard checks and enforces the access order issued by the core.
The DFU operates in parallel with the core and implements a prefetch algorithm to load to the
DCache, information that with high probability will be needed soon, thus reducing the number of
data cache misses. The channel differentiates between cacheable and non-cacheable addresses as
defined by the MMU. For cacheable addresses, it supports the write-back allocate or
write-through accesses. Cacheable accesses activate the cache (if the cache is enabled) and
respond to the core with no wait states when a hit occurs. For a miss, the data channel issues a
fetch request to higher-level memory and typically executes hardware line prefetches limited at
most by the end of the cache line. Write-through accesses do not allocate a new line in the cache
for a write-miss access.
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Internal Memory Subsystem
Cacheable write back data writes wait in the cache until a line is flushed, either automatically as
part of the replacement policy or when initiated by the user. During flushing, the writes wait in
the write back buffer until they are written to higher-level memory. Hardware line prefetching
and write backs are issued on the QBus as compact 128-bit transactions, which helps reduce the
traffic on the DSP subsystem connection to the higher level memories. Non-cacheable accesses
are written through the data channel without changing the cache state. Cacheable write-through
accesses, however, are written to the higher level memory, and they update the cache when there
is a hit access.
The data channel has the following features:
„ Handling 2 parallel core accesses WA/WB each with a width of 1, 2, 4 or 8 bytes
„ Supports both cacheable and non-cacheable accesses concurrently, as identified in the
MMU based on their address ranges.
„ Task-extended virtually addressed cache. The 8-bit task ID from the MMU is stored as
part of the line tag, which allows a task-specific cache image that is not overridden by
other tasks that use the same virtual address. This feature can support multi-task
mechanism. This extended tag is named ETAG.
„ Supports cacheable shared memory between tasks that is marked by the MMU according
to the memory range, and is stored in the cache with task ID 0.
„ Serves a cache hit access without wait states (except memory conflicts).
„ Upon a cache miss, issues 128-bit accesses to the higher level memory
„ Upon a cache miss, could be programmed to issues prefetch accesses that will bring in
data until the end of the cache line (256 bytes).
— Hardware line prefetching is aborted when there is a new miss on a burst size
boundary.
— Programmable burst size of 1, 2, or 4 VBRs.
„ Miss access, identified as being hardware line prefetched (prefetch hit), stalls the core for
a reduced number of wait states relative to a simple miss.
„ Supports SC3850 core cache maintenance instructions that are operable for both user and
supervisor levels:
— DMALLOC. Allocate a line used later in the code and validate 4 VBRs in the line. Saves
time and bus resources need to fetch VBRs from main memory when going to
overwrite it.
— DFETCH/W. Allocate a line and fetch the relevant data (at least one memory burst) that is
used later in the code. Adding the W indicate to the L2 cache not to allocate the data
even if it is cacheable to reduce cache inclusiveness.
— DFLUSH. The DCache writes back and invalidates a cache line belonging to the
specified address of the M3 or external memory.
— DSYNC. The DCache writes back a cache line belonging to the specified address of the
M3 or external memory.
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Data Channel and Write Queue (DCache)
„ Pseudo-LRU (PLRU) as the cache Line Replacement Mechanism (LRM).
„ Partial lock allows locking of a subset of cache lines based on ways boundaries, to reduce
cache restoration penalty of a restored task. Data can be locked in the cache, thus
preventing the thrashing of data expected to be used again. This mechanism is useful when
rapid task switching is required, thereby preventing a situation in which a task thrashes
important data associated with other tasks.
„ Global lock allows locking of all cache lines to reduce cache restoration penalty of a
restored task. Miss accesses are not served by the cache in this case.
„ Supports user-initiated cache sweep operations for coherency support. These operations
are performed on each line in a user-specified address range:
— Synchronize: write back the cache line if it was modified, clearing its “dirty” bit
without affecting its validity.
— Flush: write back any cache line (and clear the “dirty” bit), and also invalidate it in the
cache (clearing the “valid” bit).
— Invalidate: discard the cache line without writing it back (clear both “dirty” and “valid”
bits).
„ Cache debug mode where the cache state (ETAG values, Valid-Dirty, PLRU state) could
be read and the memory array could be read or written.
„ Dedicated programmable cache control registers that control or reflect its operation.
„ EDC (error detection) support.
„ Provides dedicated exceptions for each of the following events:
— End of sweep operation: This exception indicates the completion of the sweep
operation.
— WA/WB non-cacheable hit access: This exception indicates that an access is a hit (or
prefetch hit) access, although it is indicated by the MMU as a non-cacheable access.
This type of situation can occur if the memory space attributes are changed in the
MMU without flushing/invalidating the appropriate cache lines Assertion of the
exception is not guaranteed if the attribute change that leads to the error was not done
with the SYNCIO command as restricted.
— WA/WB double match: This is an error that occurs when a task-shared access has an
address that matches a non-shared cache line.
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Internal Memory Subsystem
11.4
L2 Unified Cache/M2 Memory
Each core subsystem contains a memory region that can be allocated as L2 unified cache or M2
memory. Allocation of M2 memory is done in 64 KB blocks from 0 to 512 KB (the full memory
space). Whatever portion is not allocated as M2 memory is used as L2 cache. Allocation can be
done dynamically, but must be done when the L2 cache is disabled. The selection of 64 KB
blocks is done through address partitioning. After the M2 region is defined, the cache should be
flushed and after the flush is completed, the L2 cache controller is enabled and the defined M2
region becomes available for addressing with the remainder of the space available to the L2 cache
controller (L2Cache).
The L2Cache is responsible for processing data and program accesses to the M3 and external
DDR memory. By caching the accesses requested by the L1 subsystem, the average penalty of
accessing the high latency M3/DDR memory is reduced. The L2Cache includes slave arbitration
and a Tag unit, cache logic and arrays along with a write buffer for write back and write through
accesses, fetch logic that is responsible for fetching data from the M3/DDR memory on a miss or
a non-cacheable access, and a master arbiter that arbitrates between the different units.
The main L2Cache components include the following:
„ Cache logic. Responsible on managing the cache arrays and state machines.
„ Fetch Unit (L2FU). Responsible for fetching cacheable accesses from the M3/DDR
memory, including the rest of the line.
„ Write Buffer (L2WB). A buffer for temporarily holding modified (dirty) cache lines that
were thrashed by the cache and also serving as a buffer for non-cacheable memory.
„ Control Unit (L2AU). Responsible for arbitration between the different masters (access
generators) of the L2Cache (L2FU and L2WB) and interface to the asynchronous bus.
„ QBus to MBus (Q2M). Enables the interface to the external memory bus asynchronously
while maintaining the pipeline.
„ Register file. Holds the L2Cache status and control registers that are mapped to the
internal peripherals on Bank0.
The cache has the following characteristics:
„
„
„
„
„
Up to 512 KB cache memory.
8 ways
1024 cache indexes.
64-byte cache line.
64-byte Valid Bit Resolution (VBR) and Dirty Bit Resolution (DBR). Fetches the whole
line at once. Writes back the whole line at once when a dirty line is thrashed from the
cache.
„ 8192 cache lines (TAGs).
Reference Manual, Rev. 2
11-8
Freescale Semiconductor
L2 Unified Cache/M2 Memory
„ Physically addressed.
„ L2WB comprises eight 32-byte entries.
„ Slave port support.
The L2 Cache Controller is connected to the Data and Instruction QBus. The L2 Cache
Controller has a chip select input that signals the access to it. Each access is qualified by the
cache policy bits that are linked to the access address, as either a cacheable (CA) access,
non-cacheable (NC) access, cacheable write-through (WT), and Adaptive Write Policy (AWP),
that is, a CA on a read access or a hit access, and NC on a write miss. Cacheable accesses activate
the cache and, in case of a hit, answer after a minimum of five cycles. In case of a miss, the L2
Cache Controller issues fetch requests to the higher-level memory (M3/DDR), and fetches more
data than asked for by requesting the whole cache line to reduce the performance impact due to
subsequent accesses. In case the access is a WB or AWP hit, the data writes wait in the cache
until the line is flushed (automatically as part of the replacement policy or if initiated by the user).
Upon flushing, the writes wait in the Write Buffer (L2WB) until they are written to the
higher-level memory. Miss fetch and write backs are issued on the MBus as 128-bit transactions,
which help reduce the traffic on the platform connection to the higher level memories. NC
accesses, WT or AWP miss are written through the L2Cache without changing the cache state via
the L2WB. The cache does not calculate hits for NC accesses. To prevent a coherency problem,
the cache must be flushed when changing an area from CA policy to NC policy in the MMU
MATT descriptors.
The L2 Cache Controller has the following features:
„ Input ports (DQBus, IQBus, and MBus):
— Handling 2 input QBuses and 1 input MBus, arbitrating them to one internal bus with
pipeline support.
— Slave ports (Qbus and MBus) supporting partial bus width accesses of 1, 2, 4, and 8
bytes and full bus bursts of 1, 2, and 4 beats of 128-bit accesses.
— Round-Robin arbitration according to the access type signal and the origin of the
access.
— Physically addressed.
„ Output Port (MBus):
— Interface to the external memory (Master bus) with a bus working in MBus protocol
and supporting asynchronous connection.
— The maximum accumulative burst size is 64 bytes. The number of beats in the burst is
equal to the burst size divided by the bus size.The maximum accumulative burst size is
64 bytes which is made in 4 beats of 128 bits.
Reference Manual, Rev. 2
Freescale Semiconductor
11-9
Internal Memory Subsystem
„ Access handling:
— Supports the following cache policies:
• Noncacheable on read and write (NC).
• Cacheable write-through on read noncacheable on write (WT)
• Cacheable write back on both read and write are cacheable (WB)
• Adaptive write policy (AWP). Cacheable WB on read or hit and NC on write miss.
• Adaptive read cacheability according to a read-with-intent-to-write indiction.
• Policy is identified by the cache policy bits (defined by MMU programming) that
are part of the accesses attributes signals.
— Supports user-initiated D/PFL2_x commands.
— Upon a cache miss, brings the entire line using critical word first and wraps on 64-byte
boundaries.
— Identifies data that is being fetched (prefetch hit), which reduces the number of wait
states relative to a simple miss and reduces the external memory bus load.
— Detects hazards for reads that use data that was flushed (or noncacheable) and is still in
the L2WB. The access is stalled until the write is completed.
— Supports fast write and response request
— Issues a transfer acknowledge as soon as the write data is sampled. When response is
high, issues the transfer acknowledge signal when the write access is sampled at the
end target.
— Supports core atomic accesses to external memory. Atomic access to L2 cacheable
location or to L2 as M2 is not supported (will always succeed)
— Constantly memory maps the cache array to enable read and write to it for debug
purposes and also to allow use as M2 with DMA connectivity.
„ Replacement mechanism:
— Uses random cache line replacement mechanism (LRM).—Partitioning mechanism by
ways and address ranges
— Allows assignment of a subset of cache lines to an address range to reduce cache
restoration penalty of a restored task. This mechanism is useful when rapid task
switching is required, thereby preventing a situation in which a task thrashes important
data or instructions associated with other tasks.
„ ECC is able to fix 1 error in 64 bits. In addition, ECC test mode is supported. This mode
enables the user to check the ECC mechanism by initiation of error.
„ Cache programming:
— Dedicated programmable cache control registers that control or reflect its operation.
— Supports reading and writing memory mapped registers through memory mapped
bank0.
„ Supports user-initiated SW-PF (L2 software prefetch) operation. This operation enables
PF of a specific (two-dimensional) address space as programmed in the cache registers.
Reference Manual, Rev. 2
11-10
Freescale Semiconductor
L2 Unified Cache/M2 Memory
„ Supports SW cache coherency:
— SW initiated DFLUSH/DSYNC operations. These operations are performed in a line
resolution.
— SW initiated cache sweep operations for coherency support. These operations are
performed on each line in a user-specified address range:
• Synchronize: write back the cache line if it was modified, clearing its dirty bit
without affecting its validity.
• Flush: write back any dirty cache line (and clear the dirty bit), and also invalidate it
in the cache (clearing the valid bit).
• Invalidate: discard the cache line without writing it back (clear both dirty and valid
bits).
„ Cache debug mode where the cache state (tag, valid, and dirty) could be read through the
DQbus slave port.
„ Provides dedicated interrupts for each of the following events:
— Master port () error: This interrupt indicates that one of the accesses generated by the
L2 cache to the off platform memories has failed (that is, non-mapped access).
— End of sweep operation: This interrupt indicates the completion of the sweep
operation.
— End of SW-PF operation: This interrupt indicates the completion of a L2 software
prefetch operation.
— Noncacheable hit error: This interrupt indicates that an access to a noncacheable area
was found to be hit. This indicates user violation of a restriction, which obligates the
user to flush the cache before changing descriptors’ attributes.
— Non-aligned non-allocate error: This interrupt indicates that a non-aligned access from
the slave port isn’t allocated in the cache and is forwarded to the external memory
instead.
— M2 non-mapped access error: This interrupt indicates that an access intended to access
the L2 cache as M2, has exceeded the M2 boundaries indicating an issue with memory
mapping to M2 configuration.
„ Disabled on reset. Cannot be disabled after enabled.
Reference Manual, Rev. 2
Freescale Semiconductor
11-11
Internal Memory Subsystem
11.5
M3 Memory
The 1056 KB M3 memory can be used for storing critical program and data shared between the
cores and the device peripherals. The M3 memory has a 128-bit wide port and runs at 500 MHz.
The M3 memory is ECC protected for soft errors.
The M3 memory uses 64 KB compiled memory banks of SRAM. The memory is divided into
three groups, two 512 KB groups and one 32 KB group, each with its own bus controller. The
two 512 KB groups of memory are located between addresses 0xC0000000 and 0xC00FFFFF in
the MSC8156 memory map. The 32 KB group is located between addresses 0xC0100000 and
0xC0107FFF. To support decreased power consumption, power to the two 512 KB memory
groups can be disabled. All of the M3 memory supports semaphores and the RapidIO mail boxes.
When the power is removed from the two 512 KB memory groups, the remaining 32 KB group
still has power to provide minimal support for the hardware semaphores and the RapidIO mail
boxes.
11.6
Internal Boot ROM
The MSC8156 device includes 96 KB of boot ROM accessible from all of the cores. This ROM
provides the basic loading programming that allows the device to complete its initialization and
load additional configuration and booting from external sources.
Reference Manual, Rev. 2
11-12
Freescale Semiconductor
DDR SDRAM Memory Controller
12
The two fully programmable DDR SDRAM memory controllers support most available
JEDEC-standard ×8 or ×16 DDR2 and DDR3 memories. In addition, unbuffered and registered
DIMMs are supported. However, mixing different memory types or unbuffered and registered
DIMMs in the same system is not supported. Built-in error checking and correction (ECC)
ensures very low bit-error rates for reliable high-frequency operation. Dynamic power
management and auto-precharge modes simplify memory system design. A large set of special
features, including ECC error injection, support rapid system debug. Figure 12-1 shows a
high-level view of the DDR memory controller with its associated interfaces.
Request from
Initiator
Input
Staging
Queue
Address
Decode
Address from
Initiator
Physical Bank,
Logical Bank,
Row
DDR SDRAM
Memory Array
MA[15–0]
MBA[2–0]
Address
Control
DDR SDRAM
Memory Control
Row
Open
SDRAM
Control
Row Open
Table
EN
To Error
Management
Error
Signals
ECC
Delay Chain
Data from
SDRAM
Data from
Initiator
MDQS[0–8]
MPAR_IN
MPAR_OUT
FIFO
RMW
ECC
MCS[0–1]
MCAS
MRAS
MWE
MDM[0–8]
MCKE[0–1]
MODT[0–1]
MDIC[0–1]
Data Qualifiers
MDQS[0–8]
Data Signals
MDQ[0–63]
MECC[0–7]
EN
SDRAM
Control
Clocks
Clock
Control
MCK[0–2]
MCK[0–2]
Note: Register names in most of the chapter use the generic form shown in this figure. Actual names prepend M1 or M2 for the individual controllers.
Figure 12-1. DDR SDRAM Memory Controller Simplified Block Diagram
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-1
DDR SDRAM Memory Controller
12.1
Features
Each one of the dual independent DDR memory controllers includes these distinctive features:
„
„
„
„
„
„
„
„
Support for DDR2 and DDR3 SDRAM
64-/72-bit or 32-/40-bit SDRAM data bus for DDR2 and DDR3
Programmable settings for meeting all SDRAM timing parameters
The following SDRAM configurations are supported:
— Two physical banks (chip selects), each bank independently addressable
— 256-Mbit to 2-Gbit devices depending on internal device configuration with ×8/×16
data ports (no direct ×4 support)
— Unbuffered and registered DIMMs
Chip select interleaving support
Partial array self refresh support
Support for data mask signals and read-modify-write for sub-double-word writes. Note
that a read-modify-write sequence is only necessary when ECC is enabled.
Support for double-bit error detection and single-bit error correction ECC (8-bit check
word across 64-bit data)
Support for address parity for registered DIMMs
Open page management (dedicated entry for each logical bank)
Automatic DRAM initialization sequence or software-controlled initialization sequence
Automatic DRAM data initialization
„
„
„
„
„ Write leveling supported for DDR3 memories
„ Support for up to eight posted refreshes
„ Memory controller clock frequency of two times the SDRAM clock with support for sleep
power management
„ Support for error injection
The DDR memory controller supports the following modes:
„ 32-byte cache line wrap.
„ Dynamic power management mode. The DDR memory controller can reduce power
consumption by deasserting the SDRAM CKE signal when no transactions are pending to
the SDRAM.
„ Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the
memory controller to issue an auto-precharge command with every read or write
transaction. Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
MSC8156 Reference Manual, Rev. 2
12-2
Freescale Semiconductor
Functional Description
12.2
Functional Description
The DDR SDRAM controller controls processor and I/O interactions with system memory. It
supports JEDEC-compliant DDR2 and DDR3 SDRAMs. The memory system allows a wide
range of memory devices to be mapped to any arbitrary chip select, and support is provided for
registered DIMMs and unbuffered DIMMs. However, registered DIMMs cannot be mixed with
unbuffered DIMMs. In addition, DDR3 DIMM module specifications allow for vendors to use mirrored
DIMMs, where some address and bank address lines are mirrored on the DIMM. The memory controller
only supports these if the DDR_SDRAM_MD_CNTL register is used to initialize memory with
DDR_SDRAM_CFG[BI] set. However, write leveling is not supported if these DIMMs are used.
Note:
A bank is a physical bank specified by a chip select; a logical bank is one of the four or
eight sub-banks in each SDRAM chip. A sub-bank is specified by the two or three bits
on the memory bank address (MBA) pins during a memory access. Each memory
interface supports two physical banks of 64-/72-bit or 32-/40-bit wide memory.
As shown in Figure 12-1, requests are received from the internal mastering device, and the
address is decoded to generate the physical bank, logical bank, row, and column addresses. The
transaction is compared with values in the row open table to determine if the address maps to an
open page. If the transaction does not map to an open page, an active command is issued.
The memory interface supports two physical banks of 64-/72-bit wide or 32-/40bit wide memory.
Total memory size can be up to 2 Gbyte while using one or two banks (chip selects).
Programmable parameters allow for a variety of memory organizations and timings. Using
optional error checking and correcting (ECC) protection, the DDR memory controller detects and
corrects all single-bit errors within the 64-bit or 32-bit data bus, detects all double-bit errors
within the 64-bit or 32-bit data bus, and detects all errors within a nibble. The controller allows as
many as 16 pages to be opened simultaneously. The amount of time (in clock cycles) the pages
remain open is programmed via the DDR_SDRAM_INTERVAL[BSTOPRE] bit (see
Table 12-34 on page 12-74).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-3
DDR SDRAM Memory Controller
Read and write accesses to memory are burst oriented; accesses start at a selected location and
continue for a programmed number of higher locations (four or eight) in a programmed sequence.
Accesses to closed pages start with the registration of an ACTIVE command followed by a READ or
WRITE. Accessing open pages does not require an ACTIVE command. The address bits registered
with the ACTIVATE command specify the logical bank and row to be accessed. The address
coincident with the READ or WRITE command specify the logical bank and starting column for the
burst access.
The data interface is source synchronous, so the source of the data provides a clocking signal to
synchronize data reception. These bidirectional data strobes (MDQS[0–8]) are inputs to the
controller during reads and outputs during writes. The DDR SDRAM specification requires the
data strobe signals to be centered within the data tenure during writes and to be offset by the
controller to the center of the data tenure during reads. These delays are implemented by the
DDR SDRAM memory controller for both reads and writes.
When ECC is enabled, 1 clock cycle is added to the read path to check ECC and correct single-bit
errors. ECC generation does not add a cycle to the write path.
The address and command interface is also source synchronous, although 1/8 cycle adjustments
are provided for adjusting the clock alignment.
Figure 12-2 shows an example DDR SDRAM configuration with four logical banks.
Data Bus
Data-Out Registers
Data-In Registers
SDRAM
Multiplex, Mask,
Read Data Latch
ADDR
COMMAND–
MCS, MRAS, MCAS, MWE
DQM
Logical
Logical
Logical
Logical
Bank 0
Bank 1
Bank 2
Bank 3
Control
BA1,BA0
CKE, MCK, MCK
Figure 12-2. Typical Dual Data Rate SDRAM Internal Organization
MSC8156 Reference Manual, Rev. 2
12-4
Freescale Semiconductor
Functional Description
Figure 12-3 shows some typical signal connections.
64 M × 1 Byte
512 Mbit
ADDR
SUB
BANK ADDR
13
2
A[12–0]
MWE
8
Data
BA[1–0]
DQS
MRAS
MCAS
DQ[7–0]
Data
Strobe
Command
Bus
MCS
DM
Write Enable
CKE
MCK
CK
MCK
Figure 12-3. Typical DDR SDRAM Interface Signals
Figure 12-4 shows an example DDR SDRAM configuration with two physical banks, each
containing nine 32M × 8 DDR modules for a total of 512 MB of system memory. One of the nine
modules is used for the memory ECC checking function. Certain address and control lines
software may require buffering. Analysis of the AC timing specifications, desired memory
operating frequency, capacitive loads, and board routing loads can assist the system designer in
defining signal buffering requirements. The DDR memory controller drives 16 address pins, but
in this example the DDR SDRAM devices use only 13 bits.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-5
DDR SDRAM Memory Controller
MDQS[0–8]
Memory Data Bus and Strobes
MDQ[0–63]
MECC[0–7]
MA[15–0]
MBA[2–0]
MRAS
To all SDRAM
Devices in
Common
MCAS
MWE
MCKE[0:1]
MCK[0–2]
MCK[0–2]
MODT[0:1]
MCS[0–1]
MCS1
MCS0
DDR
Controller
0
1
2
3
4
5
6
7
32M × 8 SDRAM
2 Mx8 SDRAM
A[12–0]
2 Mx8 SDRAM
BA
[1–0]
A[0-11]
RAS
2 Mx8 MDQS
SDRAM
BA[0-1]
A(11-0)
CAS
RAS
2Mx8 SDRAM
BA(1-0)
A(11-0)
DQ[7–0]
WE
CAS
RAS
2Mx8
SDRAM
BA(1-0)
A[0-11]
CKE
DQ[0-7]
CAS
RAS
2Mx8
SDRAM
BA[0-1]
A[0-11]
CK
CKE
DQ(7-0)
CAS
RAS
2Mx8
SDRAM
BA[0-1]
A[0-11]
CS
CLK
CKE
DQ(7-0)
CAS
RAS
BA[0-1]
A[0-11]
DM
CS
CLK
CKE
DQ[0-7]
CAS
RAS
BA[0-1]
DM
CS
CLK
CKE
CAS
RAS DQ[0-7]
DM
CS
CLK
CKE
CAS DQ[0-7]
DM
CS
CLK
CKE
DQ[0-7]
DM
CS
CLK
CKE
DM
CS
CLK
DM
CS
DM
MDQS[0]
MDQ[0–7]
MDQ[8–15]
MDQ[16–23]
MDQ[24–31]
MDQ[32–39]
MDQ[40–47]
MDQ[48–55]
MDQ[56–63]
MDQS[7]
0
1
2
3
4
5
6
7
32M × 8 SDRAM
2Mx8 SDRAM
A[12–0]
2Mx8 SDRAM
BA[1–0]
A[0-11]
RAS
2Mx8 MDQS
SDRAM
BA[0-1]
A(11-0)
CAS
RAS
2Mx8 SDRAM
BA(1-0)
A(11-0)
DQ[7–0]
WE
CAS
RAS
2Mx8
SDRAM
BA(1-0)
A[0-11]
CKE
DQ[0-7]
CAS
RAS
2Mx8
BA[0-1]
A[0-11] SDRAM
CK
CKE
DQ(7-0)
CAS
RAS
2Mx8
SDRAM
BA[0-1]
A[0-11]
CS
CLK
CKE
DQ(7-0)
CAS
RAS
BA[0-1]
A[0-11]
DM
CS
CLK
CKE
DQ[0-7]
CAS
RAS
BA[0-1]
DM
CS
CLK
CKE
CAS
RAS DQ[0-7]
DM
CS
CLK
CKE
CAS DQ[0-7]
DM
CS
CLK
CKE
DQ[0-7]
DM
CS
CLK
CKE
DM
CS
CLK
DM
CS
DM
MDQS[0]
MDQ[0–7]
MDQ[8–15]
MDQ[16–23]
MDQ[24–31]
MDQ[32–39]
MDQ[40–47]
MDQ[48–55]
MDQ[56–63]
MDQS[7]
MDM[0–8]
32M × 8 SDRAM
32M × 8 SDRAM
A[12–0]
BA[1–0]
RAS
MDQS
CAS
DQ[7–0]
WE
CKE
CK
CS
8
DM
A[12–0]
BA[1–0]
RAS
MDQS
CAS
DQ[7–0]
WE
CKE
CK
CS
8
DM
MDQS[8]
MECC[0–7]
MDQS[8]
MECC[0–7]
Bank 0
Bank 1
8M × 72 (256 Mbytes)
8M × 72 (256 Mbytes)
1. All signals are connected in common (in parallel) except for MCS[0–1], MCK[0–2], MDM[0–8], and the data bus signals.
2. Each of the MCS[0–1] signals correspond with a separate physical bank of memory.
3. Buffering may be needed if large memory arrays are used.
4. MCK[0–2] can be apportioned among all memory devices. Complementary bus is not shown.
Figure 12-4. Example 512 MB DDR SDRAM Configuration With ECC
MSC8156 Reference Manual, Rev. 2
12-6
Freescale Semiconductor
Functional Description
12.2.1
DDR SDRAM Interface Operation
The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs
with different sizes can be used in the same system. Sixteen multiplexed address signals
MA[15–0] and three logical bank select signals MBA[2–0] support device densities from
256 Mb to 2 Gb. Two chip select signals MCS[0–1] support one double rank DIMM or up to two
single rank DIMM. The DDR SDRAM physical banks can be built from standard memory
modules or directly-attached memory devices. The data path to individual physical banks is 64 or
32 bits wide (72 or 40 bits with ECC). The DDR memory controller supports physical bank sizes
from 32 MB to 2 GB. The physical banks can be constructed using × 8 or ×16 memory devices.
Supported memory technologies include 256 Mbits, 512 Mbits, 1 Gbit and 2 Gbits. Nine data
qualifier (DQM) signals provide byte selection for memory accesses.
Note:
An 8-bit DDR SDRAM device has a DQM signal a pair of differential data strobe
signals and eight data signals (DQ[0–7]). A 16-bit DDR SDRAM device has two DQM
signals, two pairs of differential data strobe signals associated with specific halves of
the 16 data signals (DQ[0–7] and DQ[8–15]).
When ECC is enabled, all memory accesses are performed on 64-bit boundaries (that is, all DQM
signals are set simultaneously). However, when ECC is disabled, the memory system uses the
DQM signals for byte lane selection. Table 12-1 shows the relationship between data byte lane
0–7, MDM[0–7], MDQS[0–7] and MDQ[0–63] when DDR SDRAM memories are used with × 8
and × 16 devices.
Table 12-1. Byte Lane to Data Relationship
Data Byte Lane
Data Bus Mask
Data Bus Strobe
Data Bus 64-Bit Mode
0 (MSB)
1
2
3
4
5
6
7 (LSB)
8
MDM0
MDM1
MDM2
MDM3
MDM4
MDM5
MDM6
MDM7
MDM8
MDQS0
MDQS1
MDQS2
MDQS3
MDQS4
MDQS5
MDQS6
MDQS7
MDQS8
MDQ[0–7]
MDQ[8–15]
MDQ[16–23]
MDQ[24–31]
MDQ[32–39]
MDQ[40–47]
MDQ[48–55]
MDQ[56–63]
MECC[0–7]
Note:
For a 32-bit interface, only data byte lanes 0, 1, 2, 3 and 8 (ECC) are used.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-7
DDR SDRAM Memory Controller
12.2.2
DDR SDRAM Organization
Although the DDR memory controller multiplexes row and column address bits onto 16 memory
address signals MA[15:0] and 3 logical bank select signals MBA[2–0], individual physical banks
can contain memory devices with fewer than 31 address bits. Each physical bank can be
individually configured to provide from 12 to 16 row address bits plus 2 or 3 logical bank-select
bits and from 8–11 column address bits. Table 12-2 and Table 12-3 list the DDR2 and DDR3
SDRAM device configurations supported by the DDR memory controller, respectively.
Note:
DDR SDRAM is limited to 31 total address bits.
Table 12-2. Supported DDR2 Device Configurations
SDRAM Device
Device Configuration
Row × Column ×
Sub-bank Bits
64-Bit Bank Size
Two 64-bit Banks of
Memory
256 Mb
32 M × 8
13 × 10 × 2
256 MB
512 MB
256 Mb
16 M × 16
13 × 9 × 2
128 MB
256 MB
512 Mb
64 M × 8
14 × 10 × 2
512 MB
1 GB
512 Mb
32 M × 16
13 × 10 × 2
256 MB
512 MB
1 Gb
128 M × 8
14 × 10 × 3
1 GB
2 GB
1 Gb
64 M × 16
13 × 10 × 3
512 MB
1 GB
2 Gb
256 M x 8
15 x 10 x 3
2 GB
NA
2 Gb
128 M × 16
14 × 10 × 3
1 GB
2 GB
Table 12-3. Supported DDR3 SDRAM Device Configurations
SDRAM Device
Device Configuration
Row x Column x
Sub-bank Bits
64-Bit Bank Size
Two 64-bit Banks of
Memory
1 Gb
128 M × 8
14 × 10 × 3
1 GB
2 GB
1 Gb
64 M × 16
13 × 10 × 3
512 MB
1 GB
2 Gb
256 M x 8
15 x 10 x 3
2 GB
NA
2 Gb
128 M x 16
14 x 10 x 3
1 GB
2 GB
Note:
DDR SDRAM is limited to 31 total address bits.
Table 12-4. Supported DDR2 Device Configurations
SDRAM Device
Device Configuration
Row × Column ×
Sub-bank Bits
32-Bit Bank Size
Two 32-bit Banks of
Memory
256 Mb
32 M × 8
13 × 10 × 2
128 MB
256 MB
256 Mb
16 M × 16
13 × 9 × 2
64 MB
128 MB
512 Mb
64 M × 8
14 × 10 × 2
256 MB
512 MB
512 Mb
32 M × 16
13 × 10 × 2
128 MB
256 MB
1 Gb
128 M × 8
14 × 10 × 3
512 MB
1 GB
MSC8156 Reference Manual, Rev. 2
12-8
Freescale Semiconductor
Functional Description
Table 12-4. Supported DDR2 Device Configurations
SDRAM Device
Device Configuration
Row × Column ×
Sub-bank Bits
32-Bit Bank Size
Two 32-bit Banks of
Memory
1 Gb
64 M × 16
13 × 10 × 3
256 MB
512 MB
2 Gb
256 M × 8
15 × 10 × 3
1 GB
2 GB
2 Gb
128 M × 16
14 × 10 × 3
512 MB
1 GB
Table 12-5. Supported DDR3 SDRAM Device Configurations
SDRAM Device
Device Configuration
Row x Column x
Sub-bank Bits
32-Bit Bank Size
Two 32-bit Banks of
Memory
1 Gb
128 M × 8
14 × 10 × 3
512 MB
1 GB
1 Gb
64 M × 16
13 × 10 × 3
256 MB
512 MB
2 Gb
256 M × 8
15 × 10 × 3
1 GB
2 GB
2 Gb
128 M × 16
14 × 10 × 3
512 MB
1 GB
If a transaction request is issued to the DDR memory controller and the address does not lie
within any of the programmed address ranges for an enabled chip select, a memory select error is
flagged (see Section 12.6, Error Management, on page 12-35).
If the starting and ending address of a disabled bank overlaps with the address space of an
enabled bank, system memory in the overlapping address range can be corrupted. The starting
and ending addresses of unused memory banks should be mapped to unused memory space.
Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence
detect capability of memory modules, system firmware configures the memory-boundary
registers to map the size of each bank in memory. The memory controller uses its bank map to
assert the appropriate MCSx signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks do not have to be mapped to a contiguous address
space.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-9
DDR SDRAM Memory Controller
12.2.3
DDR SDRAM Address Multiplexing
Table 12-6 and Table 12-7 show the address bit encodings for each DDR SDRAM
configuration. The address at the memory controller signals MA[15–0] use MA15 as the MSB and
MA0 as the LSB. MA10 is the auto-precharge bit in DDR2/DDR3 modes for reads and writes, so
the column address can never use MA10.
Table 12-6. DDR2 Address Multiplexing for 64-bit Data Bus with Interleaving and Partial Array
Self Refresh Disabled
Row
x
Col
MSB
31
Address from Core Initiator
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
15 MRAS
x
MBA
10
x MCAS
3
14 13 12 11 10 9
14 MRAS
x
MBA
10
x MCAS
3
13 12 11 10 9
8
8
6
5 4
3 2
7
6
5 4
3 2
13 MRAS
x
MBA
10
x MCAS
3
12 11 10 9
8
7
6 5
4 3
8 7
6 5
4 3
2–0
1 0
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
7 6
5 4
3 2
1 0
1 0
2
13 12 11 10 9
13 MRAS
x
MBA
9
x MCAS
2
7
2
14 MRAS
x
MBA
10
x MCAS
2
13 MRAS
x
MBA
10
x MCAS
2
LSB
1 0
2 1 0
1 0
8
7
6
5 4
3 2
1 0
2
12 11 10 9
8
7
6 5
4 3
1 0
2 1 0
1 0
12 11 10 9
8
7 6
5 4
3 2 1
0
1
0
8
MSC8156 Reference Manual, Rev. 2
12-10
Freescale Semiconductor
Functional Description
Table 12-7. DDR2 Address Multiplexing for 32-bit Data Bus with Interleaving and Partial Array
Self Refresh Disabled
Row
x
Col
MSB
30
Address from Core Initiator
LSB
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
15 MRAS
x
MBA
10
x MCAS
3
14 13 12 11 10 9
14 MRAS
x
MBA
10
x MCAS
3
13 12 11 10 9
8
7
6
5 4
3 2
13 12 11 10 9
13 MRAS
x
MBA
10
x MCAS
3
12 11 10 9
13 MRAS
x
MBA
9
x MCAS
2
6
5 4
3 2
8
7
6 5
4 3
3 2
1–0
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
9 8
7 6
5 4
3 2
1 0
7 6
5 4
3 2
1 0
1 0
2
14 MRAS
x
MBA
10
x MCAS
2
13 MRAS
x
MBA
10
x MCAS
2
7
5 4
1 0
2
8
7 6
1 0
2 1 0
1 0
8
7
6
5 4
3 2
1 0
2
12 11 10 9
8
7
6 5
4 3
1 0
2 1 0
1 0
12 11 10 9
8
7 6
5 4
3 2 1
0
1
0
8
Chip select interleaving is supported for the memory controller, and is programmed in
DDR_SDRAM_CFG[BA_INTLV_CTL]. Interleaving is supported between chip selects 0 and 1
When interleaving is enabled, the chip selects being interleaved must use the same size of
memory. If two chip selects are interleaved, then 1 extra bit in the address decode is used for the
interleaving to determine which chip select to access.
Table 12-8 and Table 12-9 illustrate examples of address decode when interleaving between two
chip selects,
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-11
DDR SDRAM Memory Controller
Table 12-8. Example of Address Multiplexing for 64-Bit Data Bus Interleaving Between
Two Banks with Partial Array Self Refresh Disabled
Row
x
Col
MSB
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 x 10 MRAS
x3
MBA
14
13 12 11 10 9
Address from Core Initiator
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3
2–0
8 7 6 5 4 3 2 1 0
CS
SEL
MCAS
14 x 10 MRAS
x3
MBA
13 12 11 10 9
8 7 6 5 4 3 2 1 0
CS
SEL
MCAS
14 x 10 MRAS
x2
MBA
13 12 11 10 9 8 7 6 5 4 3 2 1
2
1 0
9 8 7 6 5 4 3 2 1 0
0
CS 1 0
SEL
MCAS
13 x 10 MRAS
x3
MBA
12 11 10 9
8
7
6
5
4
3
2
1
CS
SEL
MCAS
13 x 10 MRAS
x2
MBA
12 11 10 9
8
7
6
5
4
3
9 8 7 6 5 4 3 2 1 0
0
2
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
CS 1
SEL
MCAS
0
Table 12-9. Example of Address Multiplexing for 32-Bit Data Bus Interleaving Between Two Banks
with Partial Array Self Refresh Disabled
Row
x
Col
15 x 10 MRAS
x3
MBA
MSB
Address from Core Initiator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15
14 13 12 11 10 9
CS
SEL
13 12 11 10 9
8 7 6 5 4 3 2 1 0
CS
SEL
MCAS
14 x 10 MRAS
x2
MBA
13 12 11 10 9 8 7 6 5 4 3 2 1
MCAS
1 0
9 8 7 6 5 4 3 2 1 0
CS 1 0
SEL
12 11 10 9
8
7
6
5
4
3
2
1
CS
SEL
12 11 10 9
8
7
6
5
4
3
2
9 8 7 6 5 4 3 2 1 0
0
MCAS
13 x 10 MRAS
x2
MBA
2
0
MCAS
13 x 10 MRAS
x3
MBA
14 13 12 11 10 9 8 7 6 5 4 3 2 1–0
8 7 6 5 4 3 2 1 0
MCAS
14 x 10 MRAS
x3
MBA
LSB
1
2
1
0
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
CS 1
SEL
0
Partial Array Self Refresh (PASR) can be enabled for any chip select using the
CSn_CONFIG_2[PASR_CFG] fields. If PASR is enabled for a given chip select, then the
sub-bank and row decode are swapped, and the sub-bank is decoded as the most significant
portion of the DRAM address, as shown in Table 12-10.
MSC8156 Reference Manual, Rev. 2
12-12
Freescale Semiconductor
Functional Description
If chip select interleaving and PASR are enabled simultaneously for a chip select, then the
interleaved chip select bit is placed immediately at the top the left of column decode as shown in
Table 12-11.
Table 12-10. DDR2 Address Multiplexing with Partial Array Self Refresh Enabled for 32-Bit Data
Bus Without Interleaving
Row
x
Col
msb
Address from Core Initiator
lsb
31
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
1–0
15 x 10 MRAS
x3
MBA
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 1 0
MCAS
9 8 7 6 5 4 3 2 1 0
14 x 10 MRAS
x3
MBA
13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 1
0
MCAS
9 8 7 6 5 4 3 2 1 0
14 x 10 MRAS
x2
MBA
13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
0
MCAS
9 8 7 6 5 4 3 2 1 0
13 x 10 MRAS
x3
MBA
2
1
12 11 10 9
8
7
6
5
4
3
2
1
0
12 11 10 9
8
7
6
5
4
3
2
1
0
0
MCAS
13 x 10 MRAS
x2
MBA
1
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
0
MCAS
13 x 9 MRAS
x2
MBA
9
12 11 10 9
8
7
6
5
4
3
2
1
0
1 0
MCAS
Table 12-11. Example of Address Multiplexing for 64-bit Data Bus Interleaving Between
Two Banks with Partial Array Self Refresh Enabled
Row
x
Col
15 x 10 MRAS
x3
MBA
msb
Address from Core Initiator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
14 13 12 11 10 9 8 7 6 5 4 3 2
2
1
CS
SEL
1 0
13 12 11 10 9 8 7 6 5 4 3 2
1
0
CS
SEL
2 1 0
MCAS
14 x 10 MRAS
x2
MBA
MCAS
13 12 11 10 9 8 7 6 5 4 3 2
1 0
2–0
0
MCAS
14 x 10 MRAS
x3
MBA
lsb
1
9 8 7 6 5 4 3 2 1 0
0
CS
SEL
9 8 7 6 5 4 3 2 1 0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-13
DDR SDRAM Memory Controller
Table 12-11. Example of Address Multiplexing for 64-bit Data Bus Interleaving Between
Two Banks with Partial Array Self Refresh Enabled (Continued)
Row
x
Col
13 x 10 MRAS
x3
MBA
msb
Address from Core Initiator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3
12 11 10 9
2
1
8
7
6
5
4
3
2
1
CS
SEL
0
MCAS
12 11 10 9
1
0
8
7
6
5
4
3
2
1
2–0
0
MCAS
13 x 10 MRAS
x2
MBA
lsb
9
8
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
0
CS
SEL
MSC8156 Reference Manual, Rev. 2
12-14
Freescale Semiconductor
JEDEC Standard DDR SDRAM Interface Commands
12.3
JEDEC Standard DDR SDRAM Interface Commands
This section describes the commands and timings for DDR2 or DDR3 modes. The DDR memory
controller performs all read or write accesses to DDR SDRAM using JEDEC standard DDR
SDRAM interface commands. The SDRAM device samples command and address inputs on
rising edges of the memory clock; data is sampled on both the rising and falling edges of DQS.
Data read from the DDR SDRAM is also sampled on both edges of DQS.
Following are the DDR SDRAM interface commands (summarized in Table 12-12 and Table
12-14) provided by the DDR controller. All actions for these commands are described from the
perspective of the SDRAM device.
„ Row activate. Latches row address and initiates memory read of that row. Row data is
latched in SDRAM sense amplifiers and must be restored by a precharge command before
another row activate occurs.
„ Precharge. Restores data from the sense amplifiers to the appropriate row. Also initializes
the sense amplifiers in preparation for reading another row in the memory array,
(performing another activate command). Precharge must occur after read or write, if the
row address changes on the next open page mode access.
„ Read. Latches column address and transfers data from the selected sense amplifier to the
output buffer as determined by the column address. During each succeeding clock edge,
additional data is driven without additional read commands. The amount of data
transferred is determined by the burst size, which defaults to 4.
„ Write. Latches column address and transfers data from the data pins to the selected sense
amplifier as determined by the column address. During each succeeding clock edge,
additional data is transferred to the sense amplifiers from the data pins without additional
write commands. The amount of data transferred is determined by the data masks and the
burst size, which is set to four by the DDR memory controller.
„ Refresh (similar to MCAS before MRAS). Causes a row to be read in all logical banks
(JEDEC SDRAM) as determined by the refresh row address counter. This refresh row
address counter is internal to the SDRAM. After it is read, the row is automatically
rewritten in the memory array. All logical banks must be in a precharged state before a
refresh. The memory controller also supports posted refreshes in which several refreshes
execute at once, and the refresh interval can be extended.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-15
DDR SDRAM Memory Controller
„ Mode register set (for configuration). Allows DDR SDRAM options to be set. These
options are: MCAS latency, additive latency (for DDR2), write recovery (for DDR2), burst
type, and burst length. MCAS latency can be chosen as provided by the preferred SDRAM
(some SDRAMs provide MCAS latency {1,2,3}, some provide MCAS latency {1,2,3,4,5},
and so on). Burst type is always sequential. Although some SDRAMs provide burst
lengths of 4 and 8, this memory controller supports only a burst length of 4. A burst length
of 8 is supported only for DDR3 memory devices. For DDR2 in 32-bit bus mode, all
32-byte burst accesses from the platform are split into two 16-byte (that is, 4 beat)
accesses to the SDRAMs in the memory controller. The DDR memory controller executes
the mode register set command during system initialization. Parameters such as mode
register data, MCAS latency, burst length, and burst type, are set by software in
DDR_SDRAM_MODE[SDMODE] and transferred to the SDRAM array by the DDR
memory controller after DDR_SDRAM_CFG[MEMEN] is set. If
DDR_SDRAM_CFG[BI] is set to bypass the automatic initialization, software can
configure the mode registers via the DDR_SDRAM_MD_CNTL register.
„ Self refresh. For use when the device is in standby for very long periods of time.
Automatically generates internal refresh cycles to keep the data in all memory banks
refreshed. Before execution of this command, the DDR controller places all logical bank
in a precharged state.
MSC8156 Reference Manual, Rev. 2
12-16
Freescale Semiconductor
JEDEC Standard DDR SDRAM Interface Commands
Table 12-12. DDR2 Command Truth Table
CKE
Function
RAS
CAS
WE
BA0
BA1
BA2
A15–
A11
Previous
Cycle
Current
Cycle
CS
(Extended) Mode
Register Set
(MRS)
H
H
L
L
L
L
BA
Refresh (REF)
H
H
L
L
L
H
X
X
X
X
1
Self Refresh Entry
(SRE)
H
L
L
L
L
H
X
X
X
X
1, 8
Self Refresh Exit
(SRX)
L
H
X
X
X
X
1, 7, 8
Single Bank
Precharge (PRE)
H
Precharge All
Banks (PREA)
A10
A9– A0
OP Code
Notes
1, 2
H
X
X
X
L
H
H
H
H
L
L
H
L
BA
X
L
X
1, 2
H
H
L
L
H
L
X
X
H
X
1
Bank Activate
(ACT)
H
H
L
L
H
H
BA
Write (WR)
H
H
L
H
L
L
BA
Column
L
Column
1, 2, 3
Write with
auto-precharge
(WRA)
H
H
L
H
L
L
BA
Column
H
Column
1, 2, 3
Read (RD)
H
H
L
H
L
H
BA
Column
L
Column
1, 2, 3
Read with
auto-precharge
(RDA)
H
H
L
H
L
H
BA
Column
H
Column
1, 2, 3
No operation
(NOP)
H
X
L
H
H
H
X
X
X
X
1
Device Deselect
(DES)
H
X
H
X
X
X
X
X
X
X
1
Power Down Entry
(PDE)
H
L
X
X
X
X
1, 4
Power Down Exit
(PDX)
L
H
X
X
X
X
1, 4
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
Row Address
1, 2
All DDR2 SDRAM commands are defined by states of CS, RAS, WE, and CKE at the rising edge of the clock.
Bank addresses BA0, BA1, BA2 (BA) determine which bank is operated on. For (E)MRS BA selects an
(Extended) Mode Register.
Burst reads or writes at BL = 4 cannot be terminated or interrupted. See “Reads interrupted by a Read” and
“Writes interrupted by a Write” in section 2.6 of the JEDEC DDR2 SDRAM Specification (JESD79-2C).
The Power Down Mode does not perform any refresh operations. The during of Power Down is therefore limited
by the refresh requirements listed in section 2.9 of the JEDEC DDR2 SDRAM Specification (JESD79-2C)..
The state of ODT does not affect the state described in this table. The ODT function is not available during
Self-Refresh. See. section 2.4.4 of the JEDEC DDR2 SDRAM Specification (JESD79-2C).
X can be H or L, but must be a defined logic level.
Self refresh exit is asynchronous.
VREF must be maintained during Self Refresh operation.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-17
DDR SDRAM Memory Controller
Table 12-13. DDR3 Command Truth Table
CKE
A9–
A0
A11
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0
BA1
BA2
Mode Register
Set (MRS)
H
H
L
L
L
L
BA
Refresh (REF)
H
H
L
L
L
H
V
V
V
V
V
Self Refresh
Entry (SRE)
H
L
L
L
L
H
V
V
V
V
V
7, 9, 12
Self Refresh
Exit (SRC)
L
H
V
V
V
V
V
7, 8, 9,
12
Single Bank
Precharge
(PRE)
H
Precharge All
Banks (PREA)
Function
A15–
A13
A12
BC
A10
Notes
OP Code
H
V
V
V
L
H
H
H
H
L
L
H
L
BA
V
V
L
V
H
H
L
L
H
L
V
V
V
H
V
Bank Activate
(ACT)
H
H
L
L
H
H
BA
Write (Fixed
BL8 or BC4)
(WR)
H
H
L
H
L
L
BA
RFU
V
L
CA
Write (BC4, on
the Fly) (WRS4)
H
H
L
H
L
L
BA
RFU
L
L
CA
Write (BC8, on
the Fly) (WRS8)
H
H
L
H
L
L
BA
RFU
H
L
CA
Write with
auto-precharge
(Fixed BL8 or
BC4) (WRA)
H
H
L
H
L
L
BA
RFU
V
H
CA
Write with
auto-precharge
(BC4, on the
Fly) (WRAS4)
H
H
L
H
L
L
BA
RFU
L
H
CA
Write with
auto-precharge
(BL8) (WRAS8)
H
H
L
H
L
L
BA
RFU
H
H
CA
Read (Fixed
BL8 or BC4)
(RD)
H
H
L
H
L
H
BA
RFU
V
H
CA
Read (BC4, on
the Fly) (RDS4)
H
H
L
H
L
H
BA
RFU
L
H
CA
Read (BL8, on
the Fly) (RDS8)
H
H
L
H
L
H
BA
RFU
H
H
CA
Read with
auto-precharge
(Fixed BL8 or
BC4) (RDA)
H
H
L
H
L
H
BA
RFU
V
H
CA
Read with
auto-precharge
(BC4, on the
Fly) (RDAS4)
H
H
L
H
L
H
BA
RFU
L
H
CA
Row Address
1, 2
MSC8156 Reference Manual, Rev. 2
12-18
Freescale Semiconductor
JEDEC Standard DDR SDRAM Interface Commands
Table 12-13. DDR3 Command Truth Table (Continued)
CKE
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
BA0
BA1
BA2
A15–
A13
A12
BC
A10
A9–
A0
A11
Read with
auto-precharge
(BL8, on the Fly)
(RDAS8)
H
H
L
H
L
H
BA
RFU
H
H
CA
No operation
(NOP)
H
H
L
H
H
H
V
V
V
V
V
10
Device
Deselected
(DES)
H
H
H
X
X
X
X
X
X
X
X
11
Power Down
Entry (PDE)
H
L
L
H
H
H
H
V
V
V
V
V
V
V
V
6. 12
Power Down
Exit (PDX)
L
H
L
H
H
H
H
V
V
V
V
V
V
V
V
1, 4
ZQ Calibration
Long (ZQCL)
H
H
L
H
H
L
X
X
X
H
X
Function
Notes: 1.
Notes
All DDR3 SDRAM commands are defined by states of CS, RAS, CAS, WE, and CKE at the rising edge of the
clock. The MSB of BA, RA, and CA are device density and configuration dependent.
RESET is Low enable command which is only used for asynchronous reset and must be maintained HIGH
during any function.
3. Bank addresses BA0, BA1, BA2 (BA) determine which bank is operated on. For (E)MRS BA selects an
(Extended) Mode Register.
4. V means H or L, but must be a defined level. X means either defined or undefined (such as floating) logic level.
5. Burst reads or writes cannot be terminated or interrupted. Fixed/on-the-Fly BL is defined by MRS..
6. The Power Down Mode does not perform any refresh operations.
7. The state of ODT does not affect the states described in this table. The ODT function is not available during
Self-Refresh.
8. Self refresh exit is asynchronous.
9. VREF (both VrefDQ and VrefCA) must be maintained during Self-Refresh operation.
10. The No Operation command should be used in cases when th DDR3 SDRAM is in an idle or wait state. The
purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands
between operations. A NOP does not terminate a previous operation that is still executing, such as a burst read
or write cycle.
11. The Deselect command perfoms the same function as a NOP.
12. Refer to the CKE Truth Table in the JEDEC DDR3 SDRAM Specification (JESD79-3B)for details about CKE
transition.
2.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-19
DDR SDRAM Memory Controller
12.4
DDR SDRAM Clocking and Interface Timing
The DDR memory controller supports four-beat bursts to SDRAM. For single-beat reads, the
DDR memory controller performs a four-beat burst read but ignores the last three beats.
Single-beat writes are performed by masking the last three beats of the four-beat burst using the
data mask MDM[0–8]. If ECC is disabled, writes smaller than the data bus width are performed
by appropriately activating the data mask. If ECC is enabled, the controller performs a
read-modify write.
Note:
If a second read or write is pending, reads shorter than four beats are not terminated
early even if some data is irrelevant.
To accommodate available memory technologies across a wide spectrum of operating
frequencies, the DDR memory controller allows you to set the timing intervals listed in Table
12-14 with a granularity of 1, 1/2, 1/4, or 1/8 SDRAM clock cycle. The value of these parameters
(in whole clock cycles) must be set by application software at system initialization before the
DDR controller is enabled and must be kept in the DDR memory controller configuration
registers. Any update of the timing parameters should be done while the controller is disabled.
Table 12-14. DDR SDRAM Interface Timing Intervals
Timing Intervals
Definition
ACTTOACT
Activate-to-Activate Interval
The number of clock cycles from a bank-activate command to
another bank-activate command within a physical bank. This
interval is listed in the AC specifications of the SDRAM as
tRRD.
Activate-to-Precharge Interval
The number of clock cycles from an activate command until a
precharge command is allowed. This interval is listed in the
AC specifications of the SDRAM as tRAS.
Activate-to-Read/Write Interval for SDRAM
The number of clock cycles from an activate command until a
read or write command is allowed. This interval is listed in the
AC specifications of the SDRAM as tRCD.
Open Page Interval
The number of clock cycles to maintain a page open after an
access. The page open duration counter is reloaded with
BSTOPRE each time the page is accessed (including page
hits). When the counter expires, the open page is closed with
a SDRAM precharge bank command as soon as possible.
MCAS Latency from READ Command
Used in conjunction with additive latency to obtain the READ
latency. The number of clock cycles between the registration
of a READ command by the SDRAM and the availability of the
first piece of output data. If a READ command is registered at
clock edge n, and the read latency is m clocks, the data is
available nominally coincident with clock edge n + m.
Precharge-to-Activate Interval
The number of clock cycles from a precharge command until
an activate or a refresh command is allowed. This interval is
listed in the AC specifications of the SDRAM as tRP.
ACTTOPRE
ACTTORW
BSTOPRE
CASLAT
PRETOACT
Register/Page
DDR SDRAM Timing Configuration
Register 1 (TIMING_CFG_1)
page 12-55
DDR SDRAM Interval Configuration
Register (DDR_SDRAM_INTERVAL)
page 12-74
DDR SDRAM Timing Configuration
Register 1 (TIMING_CFG_1)
page 12-55
DDR SDRAM Timing Configuration
Register 1 (TIMING_CFG_1)
page 12-55
MSC8156 Reference Manual, Rev. 2
12-20
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
Table 12-14. DDR SDRAM Interface Timing Intervals (Continued)
Timing Intervals
Definition
REFINT
Refresh Interval
Represents the number of memory bus clock cycles between
refresh cycles. One row is refreshed in each SDRAM bank
during each refresh cycle. Depending on
DDR_SDRAM_CFG_2[NUM_PR], some number of rows are
refreshed in each SDRAM bank during each refresh cycle.
The value of REFINT depends on the specific SDRAMs used
and the frequency of the interface. This interval is listed in the
AC specifications of the SDRAM as tREFI.
Refresh Recovery Time
The number of clock cycles from the refresh command until an
activate command is allowed. This interval is listed in the AC
specifications of the SDRAM as tRFC.
Register/Page
DDR SDRAM Interval Configuration
Register (DDR_SDRAM_INTERVAL)
page 12-74
DDR SDRAM Timing Configuration
Register 1 (TIMING_CFG_1)
page 12-55 and DDR SDRAM Timing
Configuration Register 3
(TIMING_CFG_3)
page 12-50
WR_DATA_DELAY Write Data Delay
DDR SDRAM Timing Configuration
Provides different options for the timing between a write
Register 2 (TIMING_CFG_2)
command and the write data strobe. This allows write data to page 12-60
be sent later than the nominal time to meet the SDRAM timing
requirement between the registration of a write command and
the reception of a data strobe associated with the write
command.
The specification dictates that the data strobe may not be
received earlier than 75% of a cycle, or later
than 125% of a cycle, from the registration of a write
command. This parameter is not defined in the
SDRAM specification. It is implementation-specific,
DDR SDRAM Timing Configuration
WRREC
Write Recovery
The number of clock cycles from the last beat of a write until a Register 1 (TIMING_CFG_1)
precharge command is allowed. This interval, write recovery page 12-55
time, is listed in the AC specifications of the SDRAM as tWR.
WRTORD
Last Write Pair to Read Command.
Controls the number of clock cycles from the last write data
pair to the subsequent read command to the same bank. This
interval is listed in the AC specifications of the SDRAM as
tWTR.
CLK_ADJUST
Clock Adjust
DDR SDRAM Clock Control
Adjusts the MCK timing relative to address/command. The
Configuration Register
delay is set from the address/command start timing to the
(DDR_SDRAM_CLK_CNTL) page 12-75
MCK rising edge. The resolution is 1/8 SDRAM clock cycle.
ADD_LAT
Additive Latency
DDR SDRAM Timing Configuration
Specifies the number of clock cycles for a Posted CAS
Register 2 (TIMING_CFG_2) page 12-60
operation until the registered read/write command is issued
inside the SDRAM as defined in the JEDEC DDR2 and DDR3
standards.
CPO
CAS-to-Preamble Override
DDR SDRAM Timing Configuration
(if automatic
Specifies when the DDR controller starts waiting for the first Register 2 (TIMING_CFG_2) page 12-60
calibration is not DQS rising edge from DDR memory during the DQS
selected)
preamble for read access. The DQS rising edge should occur
within 1 clock cycle from the timing defined by this parameter.
REFREC
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-21
DDR SDRAM Memory Controller
Table 12-14. DDR SDRAM Interface Timing Intervals (Continued)
Timing Intervals
Definition
Register/Page
WR_LAT
Write Latency
Specifies the number of clock cycles between the WRITE
command and the first data write when AL = 0. When additive
latency is applied, WR_LAT specifies the number of clock
cycles between issuing the REGISTERED WRITE command
inside the SDRAM and the first data write.
Read to Precharge (tRTP)
Specifies the number of clock cycles between the READ
command and the PRECHARGE command when AL = 0. When
additive latency is applied, RD_TO_PRE specifies the
minimum tRTP timing from the REGISTERED READ command
inside the SDRAM and the PRECHARGE command.
DDR SDRAM Timing Configuration
Register 2 (TIMING_CFG_2) page 12-60
RD_TO_PRE
DDR SDRAM Timing Configuration
Register 2 (TIMING_CFG_2) page 12-60
Software should initialize the parameters in the DDR controller registers with the appropriate
values before the controller is enabled. Altering the register values while the controller is enabled
can produce unpredictable controller behavior, can cause data loss, and can lock the controller or
device. System software is responsible for optimally configuring of SDRAM timing parameters.
The programmable timing parameters apply to both read and write timing configuration. The
configuration process must be completed and the DDR SDRAM initialized before attempting any
accesses to SDRAM.
Figure 12-5 through Figure 12-7 show DDR SDRAM timing for various types of accesses,
including a single-beat read, a single-beat write, and a burst-write. Note that all control signals
transitions occur on the rising edge of the memory bus clock and that single-beat read operations
are identical to burst-reads also note that data and MDQS signal transitions occur on every edge
of the memory bus clock. Figure 12-5 through Figure 12-7 assume that
DDR_SDRAM_CLK_CNTL[CLK_ADJUST] = 0100 (set to 1/2 SDRAM cycle), the additive
latency is 0 SDRAM cycles, and the write latency is 1 SDRAM cycle.
MSC8156 Reference Manual, Rev. 2
12-22
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
ar
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Clock
MCS
ACTTORW
MRAS
MCAS
MA[15–0]
ROW
COL
COL
CASLAT
MWE
MDQ[0–31]
D0 D1 D2 D3 D0 D1 D2 D3
MDQS
Figure 12-5. DDR SDRAM Burst Read Timing: ACTTORW = 3, MCAS Latency = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Clock
MCS
ACTTORW
PRECHARGE
MRAS
MCAS
WRREC
MA[15–0]
ROW
PRETOACT
A10=0
COL
ROW
MWE
MDQ[0–31]
D0 D1 D2 D3
WL=1
MDQS
MDM[0–3]
0
F
F
F
Figure 12-6. DDR SDRAM Single-Beat (32-Bit) Write Timing: ACTTORW = 3
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-23
DDR SDRAM Memory Controller
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM clock
MCS0
MCS1
ACTTORW
MRAS
MCAS
MA[15–0]
ROW
ROW
COL
COL
COL
COL
MWE
MDQ[0–31]
D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3
WL=1
MDQS
MDM[0–3]
0
Figure 12-7. DDR SDRAM 4-Beat Burst Write Timing: ACTTORW = 4
12.4.1
Clock Distribution
„ If a system is composed of many devices, consider using zero-delay PLL clock buffers
that are compliant with the JEDEC-JESD82 standard. These buffers are designed for DDR
applications.
„ A 72-bit × 64 Mbyte DDR bank has 9-byte-wide DDR memory chips resulting in 18 DDR
chips in a two-bank system. For this case, each MCK/MCK signal pair should drive exactly
six devices, as shown in Figure 12-8.
„ PCB traces for DDR clock signals should be short, all on the same layer, and of equal
length and loading.
„ DDR SDRAM manufacturers provide details on PCB layout and termination issues.
A[15–0], BA[2–0], MRAS, MCAS, MWE, CKE
CS0
MCK0, MCK0
CS1
DDR
DQ[0–7], DQS0, DM0
MCK1, MCK1
DQ[8–15], DQS1, DM1
DQ[16–23], DQS2, DM2
DQ[24–31], DQS3, DM3
DQ[32–39], DQS4, DM4
DQ[40–47], DQS5, DM5
MCK2, MCK2
DQ[48–55], DQS6, DM6
MCK2, MCK2
DQ[56–63], DQS7, DM7
ECC[0–7], DQS8, DM8
Figure 12-8. DDR SDRAM Clock Distribution Example for x8 DDR SDRAMs
MSC8156 Reference Manual, Rev. 2
12-24
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
12.4.2
DDR SDRAM Mode-Set Command Timing
The DDR controller transfers the mode register set commands to the SDRAM array and it uses
the setting of TIMING_CFG_0[MRS_CYC] for the Mode Register Set cycle time. Figure 12-9
shows the timing of the mode-set command. The first transfer corresponds to the ESDMODE
code; the second corresponds to SDMODE of DDR_SDRAM_MODE in the case of automatic
hardware initialization. The Mode Register Set cycle time is set to 2 DRAM cycles in Figure
12-9.
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Clock
MCS
MRAS
MCAS
MAn
MBAn
Code
Code
0x4
0x0
MWE
MDQn
MDQS
Figure 12-9. DDR SDRAM Mode-Set Command Timing
12.4.3
DDR SDRAM Registered DIMM Mode
To reduce loading, registered DIMMs latch the DDR SDRAM control signals internally before
using them to access the array. Setting DDR_SDRAM_CFG[RD_EN] compensates for this delay
on the DIMM control bus by delaying the data and data mask writes (on SDRAM buses) by an
extra SDRAM clock cycle.
NOTE
Application system board must assert the reset signal on DDR memory
devices until software is able to program the DDR memory controller
configuration registers, and must deassert the reset signal on DDR memory
devices before DDR_SDRAM_CFG[MEM_EN] is set. This ensures that
the DDR memory devices are held in reset until a stable clock is provided
and, further, that a stable clock is provided before memory devices are
released from reset.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-25
DDR SDRAM Memory Controller
Figure 12-10 shows the registered DDR SDRAM DIMM single-beat write timing.
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Clock
MCS
ACTTORW
MRAS
MCAS
MAn
ROW
COL
COL
MWE
MDQn
D0 D1 D2 D3 D0 D1 D2 D3
MDQS
MDMn
00
Figure 12-10. Registered DDR SDRAM DIMM Burst Write Timing
12.4.4
DDR SDRAM Write Timing Adjustments
The DDR memory controller facilitates system design flexibility by providing a write timing
adjustment parameter, DATA DELAY, configured in TIMING_CFG_2[WR_DATA_DELAY]
for data and DQS.
The DDR SDRAM specification requires DQS be received no sooner than 75% of an SDRAM
clock period—and no later than 125% of a clock period—from the capturing clock edge of the
command/address at the SDRAM. The TIMING_CFG_2[WR_DATA_DELAY] parameter can
be used to meet this timing requirement for a variety of system configurations, ranging from a
system with one bank of SDRAM devices to a fully populated system.
TIMING_CFG_2[WR_DATA_DELAY] specifies how much to delay the launching of DQS and
data from the first clock edge occurring one SDRAM clock cycle after the command is launched.
The delay increment step sizes are in 1/4 SDRAM clock periods, starting with the default value
of 0.
MSC8156 Reference Manual, Rev. 2
12-26
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM Clock
associated clock during first write
MCS
ACTTORW
MRAS
MCAS
MAn
ROW
COL
COL
MWE
MDQn
D0 D1 D2 D3 D0 D1 D2 D3
MDQS
MDMn
MDQn
WR_DATA_DELAY = 001
1/4 Clock Delay
1/4 clock early from MCK
rising edge
00
D0 D1 D2 D3 D0 D1 D2 D3
MDQS
MDMn
WR_DATA_DELAY = 010
1/2 Clock Delay
Nominal (no adjust) Timing.
No tDQSS skew.
00
WL = 1
Figure 12-11. Write Timing Adjustments Example for Write Latency = 1 for the Case Where
DDR_SDRAM_CLK_CNTL[CLK_ADJUST] = 0100
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-27
DDR SDRAM Memory Controller
12.4.5
DDR SDRAM Refresh
The DDR memory controller supports auto refresh and self refresh. Auto refresh is used during
normal operation and is controlled by the DDR_SDRAM_INTERVAL[REFINT] value; self
refresh is used only when the DDR memory controller is set to enter a sleep power management
state. The REFINT value, which represents the number of memory bus clock cycles between
refresh cycles, must allow any outstanding transactions to complete before a refresh request is
sent to the memory after the REFINT value is reached. If a memory transaction is in progress
when the refresh interval is reached, the refresh cycle waits for the transaction to complete. In the
worst case, the refresh cycle must wait the number of bus clock cycles required by the longest
programmed access. To ensure that the latency caused by a memory transaction does not violate
the device refresh period, it is recommended that the programmed value of REFINT be less than
that required by the SDRAM. When a refresh cycle is required, the DDR memory controller does
the following:
1.
Completes all current memory requests.
2.
Closes all open pages with a PRECHARGE ALL command to each DDR SDRAM bank
with an open page (as indicated by the row open table).
3.
Issues one or more auto-refresh commands to each DDR SDRAM bank (as identified by
its chip select) to refresh one row in each logical bank of the selected physical bank.
The auto refresh commands are staggered across the possible banks to reduce instantaneous
power requirements. Three sets of auto refresh commands are issued on consecutive cycles. The
initial PRECHARGE ALL commands are also staggered in three groups. When the system enters self
refresh mode, only one refresh command is issued simultaneously to all physical banks. For the
entire refresh sequence, no cycle optimization occurs for the usual case where fewer banks are
installed. After the refresh sequence completes, any pending memory request is initiated after an
inactive period specified by TIMING_CFG_1[REFREC] and
TIMING_CFG_3[EXT_REFREC]. In addition, posted refreshes in
DDR_SDRAM_CFG_2[NUM_PR] allow the refresh interval to be set to a larger value.
Note:
12.4.5.1
The MSC8156 initiates three cycles of PRECHARGE ALL commands and three cycles of
REFRESH commands although there are only two banks (chip selects) available,
DDR SDRAM Refresh Timing
Refresh timing for the DDR SDRAM is controlled by the programmable timing parameter
TIMING_CFG_1[REFREC] and TIMING_CFG_3[EXT_REFREC], which specify the number
of memory bus clock cycles from the refresh command until a logical bank activate command is
allowed. The DDR memory controller implements bank staggering for refreshes, as shown in
Figure 12-12 (TIMING_CFG_1[REFREC] = 10 in this example). System software is
responsible for optimal configuration of TIMING_CFG_1 [REFREC] and
MSC8156 Reference Manual, Rev. 2
12-28
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
TIMING_CFG_3[EXT_REFREC] at reset. Configuration must be complete before DDR
SDRAM accesses are attempted.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SDRAM clock
CKE
0
MCS[0,1]
MCS1
MCS2
REFREC
MRAS
MCAS
MAn
ROW
Figure 12-12. DDR SDRAM Bank Staggered Auto Refresh Timing
12.4.5.2
DDR SDRAM Refresh and Power-Saving Modes
In full-on mode, the DDR memory controller supplies the normal auto refresh to SDRAM. In
sleep mode, the DDR memory controller can be configured to take advantage of self-refreshing
SDRAMs or to provide no refresh support. Self-refresh support is enabled by the
DDR_SDRAM_CFG[SREN] bit.
Note:
In absence of self-refresh support, system software must preserve the DDR’s DRAM
data (for example, by copying the memory content to a non-volatile memory, such as a
disk, Flash memory, and so on) before entering power saving mode.
The dynamic power-saving mode uses the CKE pin to power down the memory device
dynamically when there is no system memory activity. The CKE pin is deasserted when both
conditions are met
„ No memory refreshes are scheduled.
„ No memory accesses are scheduled.
The CKE pin is reasserted when a new access or refresh is scheduled or the dynamic power mode
is disabled. This mode is controlled with DDR_SDRAM_CFG[DYN_PWR].
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-29
DDR SDRAM Memory Controller
Dynamic power management mode offers tight control of the memory system power
consumption by trading power for performance through the use of CKE. Powering up the DDR
SDRAM when a new memory reference is scheduled causes an access latency penalty,
depending upon whether active or precharge power-down is used, along with the settings of
TIMING_CFG_0[ACT_PD_EXIT] and TIMING_CFG_0[PRE_PD_EXIT]. A penalty of one
cycle is shown in Figure 12-13.
Memory Bus Clock
MCKE
COMMAND
NOP
NOP
ACT
Figure 12-13. DDR SDRAM Power-Down Mode
The entry and exit timing for self-refreshing SDRAMs in Sleep mode is shown in Figure 12-14
and Figure 12-15.
0
1
2
3
4
5
6
7
8
9
10
11
12
SDRAM clock
MCKE
MCS
MRAS
MCAS
MAn
MWE
MDQn
(High Impedance)
MDQS
Figure 12-14. DDR SDRAM Self-Refresh Entry Timing
MSC8156 Reference Manual, Rev. 2
12-30
Freescale Semiconductor
DDR SDRAM Clocking and Interface Timing
0
1
2
3
4
5
6
7
202
203
204
205
206
SDRAM Clock
MCKE
MCS
MRAS
MCAS
MAn
MWE
MDQn
(High Impedance)
MDQS
200 cycles
Figure 12-15. DDR SDRAM Self-Refresh Exit Timing
12.4.6
DDR Data Beat Ordering
Transfers to and from memory are always performed in four- or eight-beat bursts (four beats = 32
bytes for a 64-bit bus). For transfer sizes other than four or eight beats, the data transfers are still
in four- or eight-beat bursts. If ECC is enabled and either the access is not 64-bit-aligned or the
size is not a multiple of 64 bits, a full read-modify-write is performed for a write to SDRAM. If
ECC is disabled or the access is 64-bit-aligned with a size that is a multiple of 64 bits, the data
masks MDM[0–8] (MDM[0–3,8] for a 32-bit bus) can be used to prevent the writing of unwanted
data to SDRAM. The DDR memory controller also uses data masks to prevent all unintended full
64-bit words from writing to SDRAM. For example, if a write transaction with a size of 8 bytes is
desired, then the second, third, and fourth beats of data are not written to SDRAM.
Table 12-15 lists the data beat sequencing to and from the DDR SDRAM and the data queues for
each of the possible transfer sizes with each of the possible starting 64-bit offsets. All underlined
64-bit offsets are valid for the transaction.
Table 12-15. Memory Controller–Data Beat Ordering for the 64-Bit Interface
Transfer Size
Starting Double-Word Offset
Double-Word Sequence to/from DRAM and Queues
8 bytes
0
1
2
3
0
1
2
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-2-3-0
2-3-0-1
16 bytes
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-31
DDR SDRAM Memory Controller
Table 12-15. Memory Controller–Data Beat Ordering for the 64-Bit Interface
Transfer Size
Starting Double-Word Offset
Double-Word Sequence to/from DRAM and Queues
24 bytes
Note:
12.4.7
0
1
32 bytes
0
1
2
3
All underlined word offsets are valid for the transaction.
0-1-2-3
1-2-3-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
Page Mode and Logical Bank Retention
The DDR memory controller supports an open/closed page mode that allows an open page for
each logical bank of DRAM. In closed page mode for DDR SDRAMs, the DDR memory
controller uses the auto-precharge feature, which allows the controller to indicate the DDR
SDRAM that it must automatically close the page after the read or write access. This is
performed by using MA10 of the address during the COMMAND phase of the access to enable
auto-precharge. Auto-precharge is non-persistent in that it is either enabled or disabled for each
individual READ or WRITE command. However, it can be separately enabled or disabled for each
chip select. In open page mode, the DDR memory controller retains the currently active SDRAM
page by not issuing a precharge command. The page remains opens until one of the following
conditions occurs:
„ Refresh interval is met.
„ The user-programmable DDR_SDRAM_INTERVAL[BSTOPRE] value is exceeded.
„ There is a logical bank row collision with another transaction that must be issued.
Page mode can dramatically reduce access latencies for page hits. Depending on the memory
system design and timing parameters, using page mode can save two to three clock cycles for
subsequent burst accesses that hit in an active page. Also, better performance can be obtained by
using more banks, especially in systems which use many different channels. Page mode is
disabled by clearing DDR_SDRAM_INTERVAL[BSTOPRE] or setting
CSx_CONFIG[AP_x_EN].
12.5
Error Checking and Correction
The DDR memory controller supports error checking and correcting (ECC) for the data path
between the core Initiator and system memory. The DDR memory controller detects all
double-bit errors, detects all multi-bit errors within a nibble, and it corrects all single-bit errors.
Other errors may be detected, but are not guaranteed to be corrected or detected. Multiple-bit
errors are always reported when error reporting is enabled. When a single-bit error occurs, the
single-bit error counter register is incremented, its value compared to the single-bit error
threshold register. An error is reported when the counter value is equal to the threshold register
MSC8156 Reference Manual, Rev. 2
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Freescale Semiconductor
Error Checking and Correction
value. The single-bit error registers can be programmed so that minor memory faults are
corrected and ignored, but a catastrophic memory failure generates an interrupt.
For writes smaller than 64 bits, the DDR memory controller performs a 64-bit read from system
memory of the address for the write (checking for errors), and merges the write data with the data
read from memory. Then, a new ECC code is generated for the 64-bit of merged data. The data
and ECC code is then written to memory. If a multi-bit error is detected on the read, the
transaction completes the read-modify-write to keep the DDR memory controller from hanging.
However, the corrupt data is masked on the write, so the original contents in SDRAM remain
unchanged.
The syndrome encoding for the ECC code is shown in Table 12-16 and Table 12-17. In 32-bit
mode, Table 12-16 is split into 2 halves. The first half, consisting of rows 0–31, is used to
calculate the ECC bits for the first 32 data bits of any 64-bit granule of data. This always applies
to the odd data beats on the DDR data bus. The second half of the table, consisting of rows
32–63, is used to calculate the ECC bits for the second 32 bits of any 64-bit granule of data. This
always applies to the even data beats on the DDR data bus.
Table 12-16. DDR SDRAM ECC Syndrome Encoding
Syndrome Bit
Data
Bit
0
1
0
•
•
1
•
2
•
3
•
4
•
5
•
6
•
7
•
8
•
9
•
10
•
11
•
12
•
13
•
14
•
15
•
2
3
4
•
•
•
•
•
•
•
•
17
•
18
•
•
•
•
•
2
3
32
•
•
•
33
•
•
•
34
•
•
•
35
•
•
•
•
4
5
6
7
•
37
•
•
•
•
38
•
•
•
•
•
39
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
0
36
•
•
7
Syndrome Bit
•
•
•
•
6
•
16
19
5
Data
Bit
•
•
40
•
•
41
•
•
•
•
42
•
•
•
•
•
43
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
44
•
•
•
•
45
•
•
•
•
•
•
•
46
•
•
•
•
•
•
•
47
•
•
•
•
•
•
48
•
•
•
•
49
•
•
•
50
•
•
•
•
51
•
•
•
•
•
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-33
DDR SDRAM Memory Controller
Table 12-16. DDR SDRAM ECC Syndrome Encoding (Continued)
Data
Bit
Syndrome Bit
1
2
20
•
•
21
•
22
•
•
23
0
•
24
•
25
•
26
•
•
27
•
3
4
5
6
52
•
53
•
•
54
•
•
•
•
56
•
57
•
•
58
•
•
•
59
•
•
•
60
•
•
•
61
•
62
•
•
29
•
30
•
•
•
•
•
•
•
•
•
•
•
0
1
2
3
4
•
•
•
•
55
•
28
31
7
•
•
Syndrome Bit
Data
Bit
•
•
•
•
•
•
•
63
5
6
7
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Table 12-17. DDR SDRAM ECC Syndrome Encoding (Check Bits)
Check
Bit
0
1
2
3
4
5
6
Syndrome Bit
0
1
2
3
4
5
6
7
•
•
•
•
•
•
•
7
•
MSC8156 Reference Manual, Rev. 2
12-34
Freescale Semiconductor
Error Management
12.6
Error Management
The DDR memory controller detects single-bit, multi-bit, memory select, training errors and
address/command parity errors. The following discussion assumes all the relevant error
detection, correction, and reporting functions are enabled as described in 12.8.40, DDR SDRAM
Memory Error Detect Register (MnERR_DETECT) and 12.8.41, DDR SDRAM Memory Error
Disable Register (MnERR_DISABLE).
Single-bit errors are counted and reported based on the ERR_SBE register value (see
Table 12-66 on page 12-115). When a single-bit error is detected, the DDR memory controller
does the following:
1.
Corrects the data.
2.
Increments the single-bit error counter ERR_SBE[SBEC].
3.
Generates a critical interrupt if the counter value ERR_SBE[SBEC] equals the
programmable threshold ERR_SBE[SBET].
4.
Completes the transaction normally.
If a multi-bit error is detected for a read, the DDR memory controller logs the error and generates
the critical interrupt (if enabled, as described in Table 12-62 on page 12-111).
The DDR memory controller also detects a memory select error, which causes the DDR memory
controller to log the error and generate a critical interrupt (if enabled, as described in Table 12-61
on page 12-110). This error is detected if the address from the memory request does not fall into
any of the enabled, programmed chip-select address ranges. For all memory select errors, the
DDR memory controller does not issue any transactions onto the pins after the first read has
returned data strobes. If the DDR memory controller is not using sample points, then a dummy
transaction is issued to DDR SDRAM with the first enabled chip select. Table 12-18 describes
the errors.
The final error the memory controller detects is the automatic calibration error. This error is set if
the memory controller detects an error during its training sequence.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-35
DDR SDRAM Memory Controller
The training error the memory controller detects is the automatic calibration error. This error is
set if the memory controller detects an error during its training sequence.
Table 12-18. Memory Controller Errors
Category
Error
Notification
Single-bit ECC
threshold
The number of ECC errors has reached the
threshold specified in the ERR_SBE.
Access
Error
Multi-bit ECC
error
A multi-bit ECC error is detected during a read,
or read-modify-write memory operation.
Memory select
error
Read, or write, address does not fall within the
address range of any of the memory banks.
Training
Calibration
error
One of the calibration processes executed
during the initialization failed
Parity
Address and
Command
error
The memory device detects that the parity bit
calculated by the controller doesn’t correspond
to the parity calculated by the memory device.
12.7
Descriptions
Action
Detect Register
The error is reported
via critical interrupt if
enabled.
The error control
register logs only
read versus
write, not full
type
Set-Up and Initialization
System software must configure the DDR memory controller, using a memory polling algorithm
at system start-up, to correctly map the size of each bank in memory. The DDR memory
controller uses this bank map to assert the appropriate MCSx signal for memory accesses
according to the provided bank depths. System software also configures the DDR memory
controller at system start-up to multiplex the row and column address bits for each bank (see
Table 12-22 on page 12-47). Address multiplexing occurs according to these configuration bits.
At system power-up, initialization software (boot code, for example) must set up the
programmable parameters in the memory interface configuration registers listed in Table 12-19.
Table 12-19. Memory Interface Configuration Register Initialization Parameters
Register
Parameter Bits
Page
Chip-Select Memory Bounds
Register (MCSx_BNDS)
Starting Address for Chip Select x (SAx)
Ending Address for Chip Select x (EAx)
Table 12-21 on
page 12-46
Chip-Select Configuration
Register (MCSx_CONFIG)
Chip Select x Enable (CS_x_EN)
Chip Select x Auto-Precharge Enable (AP_x_EN)
ODT for Reads (ODT_RD_CFG)
ODT for Writes (ODT_WR_CFG)
Number of Bank Bits (BA_BITS_CS_x)
Number of Row Bits (ROW_BITS_CS_x)
Number of Column Bits (COL_BITS_CS_x)
(INTLV_EN_CTL)
Table 12-22 on
page 12-47
PASR_CFG
Table 12-23 on
page 12-49
EXT_REFREC
EXT_ACTTOPRE
EXT_CASLAT
CNTL_ADJ
Table 12-23 on
page 12-49
Table 12-24 on
page 12-50
Chip Select Configuration
2(MCSx_CONFIG_2)
Extended Timing Parameters
for Fields in TIMING_CFG_3
(TIMING_CFG_3)
MSC8156 Reference Manual, Rev. 2
12-36
Freescale Semiconductor
Set-Up and Initialization
Table 12-19. Memory Interface Configuration Register Initialization Parameters (Continued)
Register
Parameter Bits
Page
Timing Configuration 0
Register (TIMING_CFG_0)
Read-to-Write Turn-Around (RWT)
Write-to-Read Turn-Around (WRT)
Read-to-Read Turn-Around (RRT)
Write-to-Write Turn-Around (WWT)
Active Power-Down Exit Timing (ACT_PD_EXIT)
Precharge Power-Down Exit Timing (PRE_PD_EXIT)
ODT Power-Down Exit Timing (ODT_PD_EXIT)
Mode Register Set Cycle Time (MRS_CYC)
Table 12-25 on
page 12-52
Timing Configuration 1
Register (TIMING_CFG_1)
Precharge-to-Activate Interval (PRETOACT)
Activate-to-Precharge Interval (ACTTOPRE)
Activate to Read/Write Interval for SDRAM (ACTTORW)
MCAS Latency from Read Command (CASLAT)
Refresh Recovery Time (REFREC)
Last Data to Precharge Minimum Interval (WRREC)
Activate-to-Activate Interval (ACTTOACT)
Last Write Data Pair to Read Interval (WR_TO_RD)
Table 12-26 on
page 12-56
Additive Latency (ADD_LAT)
Table 12-27 on
page 12-60
Timing Configuration 2
Register (TIMING_CFG_2)
MCAS-to-Preamble Override (CPO)
Write Latency (WR_LAT)
Read-to-Precharge (RD_TO_PRE)
Write Data Delay (WR_DATA_DELAY)
Minimum CKE Pulse Width (CKE_PLS)
Window for Four Activates (FOUR_ACT)
DDR SDRAM Control
Configuration Register
(DDR_SDRAM_CFG)
Self Refresh Enable (SREN)
ECC Enable (ECC_EN)
Registereed DIMM Enable (RD_EN)
SDRAM Type (SDRAM_Type)
Dynamic Power Management Mode (DYN_PWR)
32-Bit Bus Enable (32_BE)
8-Beat Burst Enable (8_BE)
Non-Current Auto Precharge (NCAP)
3T Timing Enable (3T_EN)
2T Timing Enable (2T_EN)
Half-Strength Drive Enable (HSE)
Bypass Initialization (BI)
Table 12-28 on
page 12-65
DDR SDRAM Control
Configuration Register 2
(DDR_SDRAM_CFG_2)
Force Self Refresh (FRC_SR)
DLL Reset Disable (DLL_RST_DIS)
DQS Configuration (DQS_CFG)
ODT Configuration (ODT_CFG)
Number of Posted Refreshes (NUM_PR)
DRAM Data Initialization (D_INIT)
Table 12-29 on
page 12-68
DDR SDRAM Mode
Configuration Register
(DDR_SDRAM_MODE)
Extended SDRAM Mode (ESDMODE)
SDRAM Mode (SDMODE)
Table 12-30 on
page 12-70
DDR SDRAM Mode
Configuration 2 Register
(DDR_SDRAM_MODE_2)
Extended SDRAM Mode 2 (ESDMODE2)
Extended SDRAM Mode 3 (ESDMODE3)
Table 12-31 on
page 12-71
DDR SDRAM Interval
Configuration Register
(DDR_SDRAM_INTERVAL)
Refresh Interval (REFINT)
Precharge Interval (BSTOPRE)
Table 12-34 on
page 12-74
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-37
DDR SDRAM Memory Controller
Table 12-19. Memory Interface Configuration Register Initialization Parameters (Continued)
Register
Parameter Bits
Page
DDR SDRAM Data
Initialization Register
(DDR_DATA_INIT)
Initialization Value (INIT_VALUE)
Table 12-35 on
page 12-75
DDR SDRAM Clock Control
Configuration Register
(DDR_SDRAM_CLK_CNTL)
Clock Adjust (CLK_ADJUST)
Table 12-36 on
page 12-76
DDR SDRAM Initialization
Address Register
(DDR_INIT_ADDRESS)
Initialization Address (INIT_ADDR)
Table 12-37 on
page 12-77
DDR Initialization Enable
(MDDR_INIT_EN)
Use Initialization Address (UIA)
Table 12-38 on
page 12-77
DDR SDRAM Timing
Configuration 4 Register
(TIMING_CFG_4)
Read-to-Write Turnaround for Same Chip Select (RWT)
Write-to-Read Turnaround for Same Chip Select (WRT)
Read-to-Read Turnaround for Same Chip Select (RRT)
Write-to-Write Turnaround for Same Chip Select (WWT)
DDR SDRAM DLL Lock Time (DLL_LOCK)
Table 12-39 on
page 12-78
DDR SDRAM Timing
Configuration 5 Register
(TIMING_CFG_5)
Read-to-ODT On (RODT_ON)
Read-to-ODT Off (RODT_OFF)
Write-to-ODT On (WODT_ON)
Write-to-ODT Off (WODT_OFF)
Table 12-40 on
page 12-80
DDR ZQ Calibration Control
(MDDR_ZQ_CNTL
ZQ Calibration Enable (ZQ_EN)
Power-on Reset ZQ Calibration Time (ZQINIT)
Normal Operation Full Calibration Time (ZQOPER)
Normal Operation Short Calibration Time (ZQCS)
Table 12-41 on
page 12-83
DDR Write Leveling Control
(MDDR_WRLVL_CNTL)
Write Leveling Enable (WRLVL_EN)
First DQS Pulse Rising Edge after Margining Mode Is Programmed
(WRLVL_MRD)
ODT Delay after Margining Mode Is Programmed
(WRLVL_ODTEN)
DQS/DQS Delay after Margining Mode Is Programmed
(WRLVL_DQSEN)
Write Leveling Sample Time (WRLVL_SMPL)
Write Leveling Repetition Time (WRLVL_WLR)
Write Leveling Start Time (WRLVL_START)
Table 12-42 on
page 12-84
DDR Write Leveling Control 2
(MDDR_WRLVL_CNTL_2)
Write Leveling Start Time for DQS1 (WRLVL_START_1)
Write Leveling Start Time for DQS2 (WRLVL_START_2)
Write Leveling Start Time for DQS3 (WRLVL_START_3)
Write Leveling Start Time for DQS4 (WRLVL_START_4)
Table 12-43 on
page 12-87
DDR Write Leveling Control 3
(MDDR_WRLVL_CNTL_3)
Write Leveling Start Time for DQS5 (WRLVL_START_5)
Write Leveling Start Time for DQS6 (WRLVL_START_6)
Write Leveling Start Time for DQS7 (WRLVL_START_7)
Write Leveling Start Time for DQS8 (WRLVL_START_8)
Table 12-44 on
page 12-90
DDR Self Refresh Counter
(MDDR_SR_CNTR)
Self Refresh Idle Threshold (SR_IT)
Table 12-46 on
page 12-96
MSC8156 Reference Manual, Rev. 2
12-38
Freescale Semiconductor
Set-Up and Initialization
Table 12-19. Memory Interface Configuration Register Initialization Parameters (Continued)
Register
Parameter Bits
Page
DDR SDRAM Register
Control Words 1
(MDDR_SDRAM_RCW_1)
Register Control Word 0 (RCW0)
Register Control Word 1 (RCW1)
Register Control Word 2 (RCW2)
Register Control Word 3 (RCW3)
Register Control Word 4 (RCW4)
Register Control Word 5 (RCW5)
Register Control Word 6 (RCW6)
Register Control Word 7 (RCW7)
Table 12-47 on
page 12-97
DDR SDRAM Register
Control Words 2
(MDDR_SDRAM_RCW_2)
Register Control Word 8 (RCW8)
Register Control Word 9 (RCW9)
Register Control Word 10 (RCW10)
Register Control Word 11 (RCW11)
Register Control Word 12 (RCW12)
Register Control Word 13 (RCW13)
Register Control Word 14 (RCW14)
Register Control Word 15 (RCW15)
Table 12-48 on
page 12-98
DDR Control Driver Register 1
(MDDRCDR_1)
DDR Driver Hardware Compensation Enable (DHC_EN)
Driver Software Override Enable for MDIC (DSO_MDIC_EN)
Driver Software Override valeu for MDIC P-Impedance
(DSO_MDICPZ)
Driver Software Override valeu for MDIC N-Impedance
(DSO_MDIC_NZ)
Driver Software Override Output Enable for P-Impedance
(DSO_MDIC_PZ_OE)
Driver Software Override Output Enable for N-Impedance
(DSO_MDIC_NZ_OE)
ODT Termination Value for I/O (ODT)
Driver Software Override Enable for Address/Command
(DSO_C_EN)
Driver Software Override Enable for Data (DSO_D_EN)
DDR Driver Software override value for Command P-Impedance
override (DSO_CPZ)
DDR Driver Software override value for Command N-Impedance
override (DSO_CNZ)
DDR Driver Software override value for Data P-Impedance
override (DSO_DPZ)
DDR Driver Software override value for Data N-Impedance
override (DSO_DNZ)
Table 12-51 on
page 12-101
DDR Control Driver Register 2
(MDDRCDR_2)
Driver Software Override Enable for Clocks (DSO_CLK_EN)
DDR Driver Software override value for Clocks P-Impedance
override (DSO_CLKPZ)
DDR Driver Software override value for Clocks N-Impedance
override (DSO_CLKNZ)
ODT Termination Value for I/O (ODT)
Table 12-52 on
page 12-104
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-39
DDR SDRAM Memory Controller
12.7.1
Programming Differences Between Memory Types
Several fields in the configuration registers must be programmed to reflect the characteristics of
the DDR memory used in the application. Table 12-20 lists several of the characteristics. Refer
to the DDR memory specifications to determine the required settings. Table 12-20 does not list
all fields that must be programmed.
Table 12-20. Programming Differences Between Memory Types
Parameter
APn_EN
ODT_RD_CFG
ODT_WR_CFG
ODT_PD_EXIT
PRETOACT
ACTTOPRE
ACTTORW
Description
Differences
Chip Select n Auto Precharge DDR2
Enable
DDR3
Can be used to place chip select n in auto precharge mode
Chip Select ODT Read
Configuration
DDR2
Can be enabled to assert ODT if desired. This could be set
differently depending on system topology. However, systems
with only 1 chip select typically does not use ODT when
issuing reads to the memory.
DDR3
Can be enabled to assert ODT if desired. This could be set
differently depending on system topology. However, systems
with only 1 chip select typically does not use ODT when
issuing reads to the memory.
DDR2
Can be enabled to assert ODT if desired. This could be set
differently depending on system topology. However, ODT is
typically set to assert for the chip select that is getting written
to (value would be set to 001).
DDR3
Can be enabled to assert ODT if desired. This could be set
differently depending on system topology. However, ODT
typically is set to assert for the chip select that is getting
written to (value would be set to 001).
DDR2
Should be set according to the DDR2 specifications for the
memory used. The JEDEC parameter this applies to is tAXPD.
DDR3
Should be set to 0001 for DDR3. The powerdown times (tXP
and tXPDLL) required for DDR3 are controlled via
TIMING_CFG_0[ACT_PD_EXIT] and
TIMING_CFG_0[PRE_PD_EXIT].
DDR2
Should be set according to the specifications for the memory
used (tRP)
DDR3
Should be set according to the specifications for the memory
used (tRP)
DDR2
Should be set, along with the Extended Activate to Precharge
Timing, according to the specifications for the memory used
(tRAS)
DDR3
Should be set, along with the Extended Activate to Precharge
Timing, according to the specifications for the memory used
(tRAS)
Activate to Read/Write Timing DDR2
Should be set according to the specifications for the memory
used (tRCD)
DDR3
Should be set according to the specifications for the memory
used (tRCD)
Chip Select ODT Write
Configuration
ODT Powerdown Exit
Precharge to Activate Timing
Activate to Precharge Timing
Can be used to place chip select n in auto precharge mode
MSC8156 Reference Manual, Rev. 2
12-40
Freescale Semiconductor
Set-Up and Initialization
Table 12-20. Programming Differences Between Memory Types (Continued)
Parameter
CASLAT
REFREC
WRREC
ACTTOACT
WRTORD
ADD_LAT
WR_LAT
RD_TO_PRE
CKE_PLS
Description
CAS Latency
Refresh Recovery
Write Recovery
Activate A to Activate B
Write to Read Timing
Additive Latency
Write Latency
Read to Precharge Timing
Minimum CKE Pulse Width
Differences
DDR2
Should be set, along with the Extended CAS Latency, to the
desired CAS latency
DDR3
Should be set, along with the Extended CAS Latency, to the
desired CAS latency
DDR2
Should be set, along with the Extended Refresh Recovery, to
the specifications for the memory used (TRFC)
DDR3
Should be set, along with the Extended Refresh Recovery, to
the specifications for the memory used (TRFC)
DDR2
Should be set according to the specifications for the memory
used (tWR)
DDR3
Should be set according to the specifications for the memory
used (tWR). If DDR_SDRAM_CFG_2[OBC_CFG] is set, then
this should be programmed to tWR + 2 DRAM cycles.
DDR2
Should be set according to the specifications for the memory
used (tRRD)
DDR3
Should be set according to the specifications for the memory
used (tRRD)
DDR2
Should be set according to the specifications for the memory
used (tWTR)
DDR3
Should be set according to the specifications for the memory
used (tWTR)
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this should
be programmed to tWTR + 2 DRAM cycles.
DDR2
Should be set to the desired additive latency. This must be set
to a value less than TIMING_CFG_1[ACTTORW]
DDR3
Should be set to the desired additive latency. This must be set
to a value less than TIMING_CFG_1[ACTTORW]
DDR2
Should be set to CAS latency – 1 cycle. For example, if the
CAS latency if 5 cycles, then this field should be set to 100 (4
cycles).
DDR3
Should be set to the desired write latency. Note that DDR3
SDRAMs do not necessarily require the write latency to equal
the CAS latency minus 1 cycle.
DDR2
Should be set according to the specifications for the memory
used (tRTP). Time between read and precharge for non-zero
value of additive latency (AL) is a minimum of AL + tRTP
cycles.
DDR3
Should be set according to the specifications for the memory
used (tRTP). Time between read and precharge for non-zero
value of additive latency (AL) is a minimum of AL + tRTP
cycles. If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this
should be programmed to tRTP + 2 DRAM cycles.
DDR2
Should be set according to the specifications for the memory
used (tCKE)
DDR3
Should be set according to the specifications for the memory
used (tCKE)
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-41
DDR SDRAM Memory Controller
Table 12-20. Programming Differences Between Memory Types (Continued)
Parameter
FOUR_ACT
RD_EN
8_BE
2T_EN
DLL_RST_DIS
DQS_CFG
ODT_CF
OBC_CFG
RWT
WRT
RRT
Description
Four Activate Window
Differences
DDR2
Should be set according to the specifications for the memory
used (tFAW). Only applies to eight logical banks.
DDR3
Should be set according to the specifications for the memory
used (tFAW).
DDR2
If registered are used, then this field should be set to 1
DDR3
If registered are used, then this field should be set to 1
DDR2
Should be set to 0
DDR3
If a 64-bit bus is used, this should be set to 0. Otherwise, this
should be set to 1. If this is set to 0, then other requirements
in TIMING_CFG_4 is needed to ensure tCCD is met.
DDR2
In heavily loaded systems, this can be set to 1 to gain extra
timing margin on the interface at the cost of
address/command bandwidth.
DDR3
In heavily loaded systems, this can be set to 1 to gain extra
timing margin on the interface at the cost of
address/command bandwidth.
DDR2
Should typically be set to 0, unless it is desired to bypass the
DLL reset when exiting self refresh.
DDR3
Should be set to 1
DDR2
Should be set to 01
DDR3
Should be set to 01
DDR2
Can be set for termination at the IOs according to system
topology. Typically, if ODT is enabled, then the internal IOs
should be set up for termination only during reads to DRAM.
DDR3
Can be set for termination at the IOs according to system
topology. Typically, if ODT is enabled, then the internal IOs
should be set up for termination only during reads to DRAM.
On-The-Fly Burst Chop
Configuration
DDR2
Should be set to 0
DDR3
Can be set to 1 if on-the-fly burst chop is used. This is
expected to give the best performance in DDR3 mode. This
feature can only be used if a 64-bit data bus is used.
Read-to-write turnaround for
same chip select (in
TIMING_CFG_4)
DDR2
Should typically be set to 0000
DDR3
This can be used to force a longer read-to-write turnaround
time when accessing the same chip select. This is useful for
burst chop mode, as there are some timing requirements to
the same chip select that still must be met.
Write-to-read turnaround for
same chip select (in
TIMING_CFG_4)
DDR2
Should typically be set to 0000
DDR3
This could be used to force a certain turnaround time
between a write and read to the same chip select. This is
useful for burst chop mode. However, it is expected that
TIMING_CFG_1[WRTORD] is programmed appropriately
such that TIMING_CFG_4[WRT] can be set to 0000.
Read-to-read turnaround for
same chip select (in
TIMING_CFG_4)
DDR2
Should typically be set to 0000
DDR3
Should typically be set to 0100 in burst chop mode (on-the-fly
or fixed).
Registered DIMM Enable
8-beat burst enable
2T Timing Enable
DLL Reset Disable
DQS Configuration
ODT Configuration
MSC8156 Reference Manual, Rev. 2
12-42
Freescale Semiconductor
Set-Up and Initialization
Table 12-20. Programming Differences Between Memory Types (Continued)
Parameter
WWT
ZQ_EN
WRLVL_EN
BSTOPRE
Description
Differences
Write-to-write turnaround for
same chip select (in
TIMING_CFG_4)
DDR2
Should typically be set to 0000
DDR3
Should typically be set to 0100 in burst chop mode (on-the-fly
or fixed).
ZQ Calibration Enable
DDR2
Should be set to 0
DDR3
Should be set to 1. The other fields in DDR_ZQ_CNTL should
also be programmed appropriately based on the DRAM
specifications.
DDR2
Should be set to 0
DDR3
Can be set to 1 if write leveling is desired. Otherwise the value
used in TIMING_CFG_2[WR_DATA_DELAY] is used to shift
all bytes during writes to DRAM. If write leveling is used, all
other fields in DDR_WRLVL_CNTL should be programmed
appropriately based on the DRAM specifications.
DDR2
Can be set to any value, depending on the application. Auto
precharge can be enabled by setting this field to all 0s.
DDR3
Can be set to any value, depending on the application. Auto
precharge can be enabled by setting this field to all 0s.
Write Leveling Enable
Burst To Precharge Interval
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-43
DDR SDRAM Memory Controller
12.7.2
DDR SDRAM Initialization Sequence
After all parameters are configured, system software must set DDR_SDRAM_CFG[MEM_EN] to
enable the memory interface. You must allow 200 μs (500 μs for DDR3) to elapse after DRAM
clocks are stable (DDR_SDRAM_CLK_CNTL[CLK_ADJUST] is set and any chip select is
enabled) before setting MEMEN. Therefore, a delay loop in the initialization code may be
necessary if software is enabling the memory controller. If DDR_SDRAM_CFG[BI] bit is not set
to bypass initialization, the DDR memory controller conducts an automatic initialization
sequence to the memory, which follows the memory specifications. If the bypass initialization
mode is used, software can initialize the memory through the DDR_SDRAM_MD_CNTL
register.
12.8
Memory Controller Programming Model
In the register figures and field descriptions, the following access definitions apply:
„ Reserved fields are always ignored for the purposes of determining access type.
„ Read/write, read only, and write only (R/W, R, and W, respectively) indicate that all the
non-reserved fields in a register have the same access type.
„ Non-reserved fields that are cleared by writing 1s to them are indicated by w1c.
„ Mixed indicates a combination of access types.
„ Special is used when no other category applies. For special access registers, read the figure
and field descriptions very carefully.
The DDR memory controller registers are as follows:
„
„
„
„
„
„
„
„
„
Chip-Select Memory Bounds Register (MnCSx_BNDS), page 12-46.
Chip-Select Configuration Register (MnCSx_CONFIG), page 12-47.
Chip-Select Configuration Register 2 (MnCSx_CONFIG_2), page 12-49
DDR SDRAM Timing Configuration 3 (MnTIMING_CFG_3), page 12-50.
DDR SDRAM Timing Configuration 0 Register (MnTIMING_CFG_0), page 12-52.
DDR SDRAM Timing Configuration 1 Register (MnTIMING_CFG_1), page 12-55.
DDR SDRAM Timing Configuration 2 Register (MnTIMING_CFG_2), page 12-60.
DDR SDRAM Control Configuration Register (MnDDR_SDRAM_CFG), page 12-65.
DDR SDRAM Control Configuration 2 Register (MnDDR_SDRAM_CFG_2),
page 12-67.
„ DDR SDRAM Mode Configuration Register (MnDDR_SDRAM_MODE), page 12-70.
„ DDR SDRAM Mode Configuration 2 Register (MnDDR_SDRAM_MODE_2),
page 12-71.
„ DDR SDRAM Mode Control Register (MnDDR_SDRAM_MD_CNTL), page 12-71.
MSC8156 Reference Manual, Rev. 2
12-44
Freescale Semiconductor
Memory Controller Programming Model
„ DDR SDRAM Interval Configuration Register (MnDDR_SDRAM_INTERVAL),
page 12-74.
„ DDR SDRAM Data Initialization Register (MnDDR_DATA_INIT), page 12-75.
„ DDR SDRAM Clock Control Configuration Register (MnDDR_SDRAM_CLK_CNTL),
page 12-75.
„ DDR Initialization Address Register (MnDDR_INIT_ADDRESS), page 12-76.
„ DDR Initialization Enable Extended Address (MnDDR_INIT_ENXT_ADDR),
page 12-77
„ DDR SDRAM Timing Configuration 4 (MnTIMING_CFG_4), page 12-78
„ DDR SDRAM Timing Configuration 5 (MnTIMING_CFG_5), page 12-80
„ DDR ZQ Calibration Control (MnDDR_ZQ_CNTL), page 12-82
„ DDR Write Leveling Control (MnDDR_WRLVL_CNTL), page 12-84
„ DDR Write Leveling Control 2 (MnDDR_WRLVL_CNTL_2), page 12-87
„ DDR Write Leveling Control 3 (MnDDR_WRLVL_CNTL_3), page 12-90
„ DDR Pre-Drive Conditioning Control (MnDDR_PD_CNTL), page 12-93
„ DDR SDRAM Self Refresh Counter (MnDDR_SR_CNTR), page 12-96
„ DDR SDRAM Register Control Words 1 (MnDDR_SDRAM_RCW_1), page 12-97
„ DDR SDRAM Register Control Words 2 (MnDDR_SDRAM_RCW_2), page 12-98
„ DDR Debug Status Register 1 (MnDDRDSR_1), page 12-99
„ DDR Debug Status Register 2 (MnDDRDSR_2), page 12-100
„ DDR Control Driver Register 1 (MnDDRCDR_1), page 12-100
„ DDR Control Driver Register 2 (MnDDRCDR_2), page 12-104
„ DDR IP Block Revision 1 Register (MnDDR_IP_REV1), page 12-105.
„ DDR IP Block Revision 2 Register (MnDDR_IP_REV2), page 12-105.
„ Memory Data Path Error Injection Mask High Register (MnDDR_ERR_INJECT_HI),
page 12-106.
„ Memory Data Path Error Injection Mask Low Register (MnDDR_ERR_INJECT_LO),
page 12-106.
„ Memory Data Path Error Injection Mask ECC Register (MnDDR_ERR_INJECT),
page 12-107
„ Memory Data Path Read Capture High Register (MnCAPTURE_DATA_HI),
page 12-108.
„ Memory Data Path Read Capture Low Register (MnCAPTURE_DATA_LO),
page 12-108.
„ Memory Data Path Read Capture ECC Register (MnCAPTURE_ECC), page 12-109.
„ Memory Error Detect Register (MnERR_DETECT), page 12-109.
„ Memory Error Disable Register (MnERR_DISABLE), page 12-110.
„ Memory Error Interrupt Enable Register (MnERR_INT_EN), page 12-112.
„ Memory Error Attributes Capture Register (MnCAPTURE_ATTRIBUTES),
page 12-113.
„ Memory Error Address Capture Register (MnCAPTURE_ADDRESS), page 12-114.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-45
DDR SDRAM Memory Controller
„ Single-Bit ECC Memory Error Management Register (MnERR_SBE), page 12-114.
„ Debug Register 2 (MnDEBUG_2), page 12-115
Note:
DDR1 controller uses base address: 0xFFF20000. DDR2 controller uses base address:
0xFFF22000.
12.8.1
Chip-Select Bounds (MnCSx_BNDS)
CS0_BNDS
CS1_BNDS
Bit
31
Chip-Select Bounds Register
30
29
28
27
26
25
24
23
22
Offset 0x0000
0x0008
21
20
—
R
19
18
17
16
SAx
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
Type
Reset
—
R
0
0
0
0
EAx
R/W
0
0
0
0
0
0
0
0
CSx_BNDS defines the starting and ending address of the memory space that corresponds to the
individual chip selects.
Note:
The size specified in CSx_BNDS should equal the size of physical DRAM. Also, note
that EAx must be greater than or equal to SAx. The 8 msb of the address is used to
define the SAx and EAx.
If chip select interleaving is enabled, all fields in the lower interleaved chip select are used, and
the other chip selects bounds registers are not used. For example, if chip selects 0 and 1 are
interleaved, all fields in CS0_BNDS are used, and all fields in CS1_BNDS are not used.
Table 12-21. CSx_BNDS Field Descriptions
Bit
Reset
—
31–24
SAx
23–16
0
Reserved. Cleared to zero for future compatibility.
0
—
15–8
EAx
7–0
0
Starting Address
Specifies the starting address for chip-select (bank) x. This value is compared against the 8 MSBs of
the 32-bit address. See the previous note.
Reserved. Cleared to zero for future compatibility.
0
Description
Ending Address
Specifies the ending address for chip select (bank) x. This value is compared against the 8 MSBs of
the 32-bit address. See the previous note.
MSC8156 Reference Manual, Rev. 2
12-46
Freescale Semiconductor
Memory Controller Programming Model
12.8.2
Chip-Select x Configuration Register (MnCSx_CONFIG)
CS0_CONFIG
CS1_CONFIG
Bit
31
CS_x_
EN
Type R/W
Reset
0
Bit
15
Chip-Select 0 Configuration Register
Chip-Select 1 Configuration Register
30
29
28
27
26
23
25
24
ODT_RD_CFG
—
ODT_WR_CFG
0
0
0
R
0
0
R/W
0
0
6
5
4
3
2
1
0
0
0
R
0
0
0
0
AP_x_
EN
R/W
0
0
14
13
12
11
10
9
8
—
R/W
BA_BITS_CS
_x
Type
R/W
Reset
0
0
—
0
R
0
7
22
21
ROW_BITS_CS_x
0
0
Offset 0x0080
Offset 0x0084
R/W
0
0
20
19
—
0
R
0
0
18
17
16
COL_BITS_CS_x
0
0
0
R/W
0
0
The CSx_CONFIG register enables the DDR chip select x and sets the number of row and
column bits used for the chip select. The register should be loaded with the correct number of row
and column bits for each SDRAM. Because the ROW_BITS_CS_x and COL_BITS_CS_x fields
establish address multiplexing, it is essential to set these values correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used,
and the other registers’ fields are unused, with the exception of the ODT_RD_CFG and
ODT_WR_CFG fields. For example, if chip selects 0 and 1 are interleaved, all fields in
CS0_CONFIG are used, but only the ODT_RD_CFG and ODT_WR_CFG fields in
CS1_CONFIG are used.
Table 12-22. CSx_CONFIG Field Descriptions
Bit
Reset
Description
CS_x_EN
31
0
—
30-24
AP_x_EN
23
0
Reserved. Write to zero for future compatibility.
0
Chip Select x Auto-Precharge Enable
Specifies when auto-precharged is enabled for chip
select x.
ODT_RD_
CFG
22–20
0
On-Die Termination (ODT) for Reads
Specifies when ODT is to be asserted for read
accesses. Note that CAS latency plus additive
latency must be at least 3 cycles for ODT_RD_CFG
to be enabled.
Chip Select x Enable
Enables/disables chip select.
Settings
0
Chip select x is not active.
1
Chip select x is active and assumes the
state set in CSx_BNDS.
0 Chip select x is auto-precharged only if
global auto-precharge mode is enabled
(DDR_SDRAM_INTERVAL[BSTOPRE] =
0).
1 Chip select x always issues an
auto-precharge for read and write
transactions.
000
Never assert ODT for reads.
001
Assert ODT only during reads to
CSx.
010
Assert ODT only during reads to
other chip selects.
011
Reserved.
100
Assert ODT for all reads.
101–111Reserved.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-47
DDR SDRAM Memory Controller
Table 12-22. CSx_CONFIG Field Descriptions (Continued)
Bit
Reset
—
19
ODT_WR_
CFG
18–16
0
Reserved. Write to zero for future compatibility.
0
ODT for Writes
000
Specifies when ODT is to be asserted for write
001
accesses. Note that write latency plus additive
latency must be at least 3 cycles for ODT_WR_CFG
010
to be enabled.
BA_BITS_
CS_x
15–14
0
—
13–11
ROW_
BITS_CS_x
10–8
0
0
Description
Number of Bank Bits
Specifies the number of logical bank bits MBA[2–0]
for SDRAM on chip select x. See Table 12-6 and
Table 12-7 for details
Reserved. Write to zero for future compatibility.
Number of Row Bits
Specifies the number of row bits for SDRAM on chip
select x. See Table 12-6 and Table 12-7 for details
Settings
Never assert ODT for writes.
Assert ODT only during writes to
CSx.
Assert ODT only during writes to
other chip selects.
011
Reserved.
100
Assert ODT for all writes.
101–111Reserved.
00
2 logical bank bits.
01
3 logical bank bits.
10–11 Reserved
000
12 row bits
001
13 row bits
010
14 row bits
011
15 row bits
100
16 row bits
101–111Reserved
—
7–3
COL_
BITS_CS_x
2–0
0
Reserved. Write to zero for future compatibility.
0
Number of Column Bits
Specifies the number of column bits for SDRAM on
chip select x. See Table 12-6 and Table 12-7 for
details.
000
8 column bits.
001
9 column bits.
010
10 column bits.
011
11 column bits.
100–111Reserved.
MSC8156 Reference Manual, Rev. 2
12-48
Freescale Semiconductor
Memory Controller Programming Model
12.8.3
Chip-Select x Configuration Register 2 (MnCSx_CONFIG_2)
CS0_CONFIG_2
CS1_CONFIG_2
Bit
31
30
Chip-Select x Configuration Register 2
29
28
27
26
0
Bit
15
Type
Reset
24
0
0
0
7
6
5
0
0
0
0
0
R
0
0
0
PASR_CFG
R/W
0
0
0
14
13
12
11
10
—
Type
Reset
25
9
23
22
21
Offset 0x00C0
0x00C4
20
19
18
17
16
0
0
0
0
0
4
3
2
1
0
0
0
0
0
—
R
8
—
R
0
0
0
0
0
0
0
0
CSx_CONFIG_2 registers enable the partial array self refresh address decode in each chip select
If chip select interleaving is enabled, then all fields in the lower interleaved chip select are used,
and the other register fields are unused..
Table 12-23. CSx_CONFIG Field Descriptions
Bit
Reset
Description
—
31–27
PASR_
CFG
26–24
0
Reserved. Write to zero for future compatibility.
0
—
23–0
0
Partial Array Self Refresh Configuration
000
Controls the bits that is placed on MA[2:0] during the 001–
write to the EMRS(2) register DDR2/DDR3 when the
111
automatic hardware DRAM initialization is used
(DDR_SDRAM_CFG[BI] is cleared when
DDR_SDRAM_CFG[MEM_EN] is set). If this field is
a non-zero value, then it overrides the least
significant 3 bits in
DDR_SDRAM_MODE_2[ESDMODE2] for
DDR2/DDR3 during the automatic initialization for
chip select x. In addition, if a non-zero value is
programmed in this field, then the address decode
for chip select x is optimized for partial array self
refresh (see Section 12.2.3),
Reserved. Write to zero for future compatibility.
Settings
Partial array self refresh is disabled
Partial array self refresh is enabled
per JEDEC specifications. Overriding
the least significant 3 bits of EMRS or
EMRS2 is only supported for DDR2
and DDR3 memory types.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-49
DDR SDRAM Memory Controller
12.8.4
DDR SDRAM Timing Configuration 3 (MnTIMING_CFG_3)
TIMING_CFG_3
Bit
31
30
DDR SDRAM Timing Configuration 3 Register
29
28
27
26
25
—
24
23
22
21
Offset 0x0100
20
19
—
EXT_
ACTTO
PRE
18
17
16
EXT_REFREC
Type
Reset
0
0
0
R
0
0
0
0
R/W
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
EXT_
CAS
LAT
R/W
0
—
Type
Reset
0
R
0
R
R/W
—
0
0
0
0
R
0
CNTL_ADJ
0
0
0
0
0
R/W
0
0
TIMING_CFG_3 sets the extended refresh recovery time, which is combined with
TIMING_CFG_1[REFREC] to determine the full refresh recovery time.
Table 12-24. TIMING_CFG_3 Bit Descriptions
Bits
Reset
Description
—
31–25
0
Reserved. Write to zero for future compatibility.
EXT_ACTTOPRE
24
0
Extended Activate to precharge interval (tRAS ). Determines
the number of clock cycles from an activate command until a
precharge command is allowed. This field is concatenated
with TIMING_CFG_1[ACTTOPRE] to obtain a 5-bit value for
the total activate to precharge. Note that a 5-bit value of
0_0000 is the same as a 5-bit value of 1_0000. Both values
represent 16 cycles.
—
23–20
0
Reserved. Write to zero for future compatibility.
EXT_ REFREC
19–16
0
Extended Refresh Recovery Time (tRFC)
Controls the number of clock cycles from a refresh command
until an activate command is allowed. This field is combined
with TIMING_CFG_1[REFREC] to obtain the total refresh
recovery time.
Note that the minimum value for REFREC is 8 clock cycles.
tRFC = {REFREC | + | EXT_REFREC}
min. value = 8 clocks (REFREC = 0x0) + EXT_REFREC =
0x0
max. value = 240+ 23 = 263
Setting
0
1
0 clocks
16 clocks
0000
0 clock cycles.
0001
16 clock cycles.
0010
32 clock cycles.
0011
48 clock cycles.
0100
64 clock cycles.
0101
80 clock cycles.
0110
96 clock cycles.
0111
112 clock cycles
1000
128 clock cycles
1001
144 clock cycles
1010
160 clock cycles
1011
176 clock cycles
1100
192 clock cycles
1101
208 clock cycles
1110
224 clock cycles
1111
240 clock cycles
MSC8156 Reference Manual, Rev. 2
12-50
Freescale Semiconductor
Memory Controller Programming Model
Table 12-24. TIMING_CFG_3 Bit Descriptions (Continued)
Bits
Reset
Description
—
15–13
0
Reserved. Write to zero for future compatibility.
EXT_CASLAT
12
0
Extended MCAS latency from READ command. Number of
clock cycles between registration of a READ command by the
SDRAM and the availability of the first output data. If a READ
command is registered at clock edge n and the latency is m
clocks, data is available nominally coincident with clock edge
n + m. This field is concatenated with
TIMING_CFG_1[CASLAT] to obtain a 5-bit value for the total
CAS latency. Note that if this bit is set, then 8 clocks are added
to the programmed value in TIMING_CFG_1[CASLAT].
—
11–3
0
Reserved. Write to zero for future compatibility.
CNTL_ADJ
2-0
0
Control Adjust. Controls the amount of delay to add to the
lightly loaded control signals w/ respect to all other DRAM
address and command signals. The signals affected by this
field are MODT[0:1], MCS[0:1], and MCKE[0:1]
Setting
0 0 clocks
1 8 clocks
000 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched aligned with
the other DRAM
address and control
signals.
001 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched 1/4 platform
cycle later than the
other DRAM address
and control signals.
010 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched 1/2 platform
cycle later than the
other DRAM address
and control signals.
011 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched 3/4 platform
cycles later than the
other DRAM address
and control signals.
100 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched 1platform
cycles later than the
other DRAM address
and control signals.
101 MODT[0:1], MCS[0:1],
and MCKE[0:1] is
launched 5/4 platform
cycles later than the
other DRAM address
and control signals.
110-111Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-51
DDR SDRAM Memory Controller
12.8.5
DDR SDRAM Timing Configuration Register 0 (MnTIMING_CFG_0)
TIMING_CFG_0
Bit
31
DDR SDRAM Timing Configuration Register 0
30
29
RWT
28
27
0
0
Bit
15
14
25
RRT
WRT
Type
Reset
26
24
23
22
ACT_PD_EXIT
R/W
0
0
1
0
6
3
WWT
0
0
0
—
R
0
10
9
8
7
R/W
0
0
0
13
12
11
—
R
Type
Reset
0
0
0
0
0
ODT_PD_EXIT
R/W
0
0
21
5
20
Offset 0x0104
4
19
18
PRE_PD_EXIT
R/W
0
0
—
R
1
0
0
0
0
17
0
2
1
MRS_CYC
R/W
1
0
16
1
0
1
TIMING_CFG_0 sets the number of clock cycles between various SDRAM control commands.
Table 12-25. TIMING_CFG_0 Field Descriptions
Bit
Reset
Description
RWT
31–30
0
Read-to-Write Turn-Around (tRTW)
Specifies how many extra cycles to add between a read-to-write
turnaround. If 0 clock cycles is chosen, then the DDR controller
uses a fixed number based on the CAS latency and write
latency. A value other than 0 adds extra cycles to this default
calculation. By default, the DDR controller determines the
read-to-write turn-around as CL – WL + BL/2 + 2. CL is the CAS
latency rounded up to the next integer, WL is the programmed
write latency, and BL is the burst length.
Write-to-Read Turn-Around
Specifies how many extra cycles to add between a write-to-read
turn-around. If 0 clock cycles is chosen, then the DDR controller
uses a fixed number based on the read latency and write
latency. A value other than 0 adds extra cycles to this default
calculation. By default, the DDR controller determines the
write-to-read turn-around as WL – CL + BL/2 + 1. CL is the CAS
latency rounded down to the next integer, WL is the
programmed write latency, and BL is the burst length.
Read-to-Read Turn-Around
Specifies how many extra cycles to add between reads to
different chip selects. By default, 3 cycles are required between
read commands to different chip selects.
If 00 is selected the DDR Controller uses a predefined value - 3
clocks for the turnaround, selecting a value other than 00 adds
extra cycles to this predefined value according to the selection
When DDR works in 8 beat burst the default is 5 clock cycles.
Note: DDR2 does not support 8-beat bursts.
Write-to-Write Turn-Around
Specifies how many extra cycles to add between writes to
different chip selects. By default, 2 cycles are required between
write commands to different chip selects.
If 00 is selected the DDR Controller uses a predefined value - 2
clocks for the turnaround, selecting a value other than 00 adds
extra cycles to this predefined value according to the selection
When DDR works in 8 beat burst the default is 4 clock cycles.
Note: DDR2 does not support 8-beat bursts.
Reserved. Write to zero for future compatibility.
WRT
29–28
RRT
27–26
WWT
25–24
—
23
0
0
0
0
Settings
00 0 clock cycles.
01 1 clock cycle.
10 2 clock cycles.
11 3 clock cycles.
00
0 clock cycles.
01
1 clock cycle.
10
2 clock cycles.
11
3 clock cycles.
DDR2:
00
3 clock cycles.
01
4 clock cycle.
10
5 clock cycles.
11
6 clock cycles.
DDR2:
00
2 clock cycles.
01
3 clock cycle.
10
4 clock cycles.
11
5 clock cycles.
MSC8156 Reference Manual, Rev. 2
12-52
Freescale Semiconductor
Memory Controller Programming Model
Table 12-25. TIMING_CFG_0 Field Descriptions (Continued)
Bit
Reset
ACT_PD_
EXIT
22–20
0b001
PRE_PD_
EXIT
19–16
—
15–12
ODT_PD_
EXIT
11–8
—
7–4
0b0001
0
0b0001
0
Description
Active Power-Down Exit Timing (tXARD and tXARDS)
Specifies how many clock cycles to wait between exit from
active power-down and issuing a command. The default is one
clock cycle.
Precharge Power-Down Exit Timing (txp)
Specifies how many clock cycles to wait after exiting precharge
power-down before issuing any command.
The default is one clock cycle.
Settings
000
Reserved
001
1 clock cycles.
010
2 clock cycles.
011
3 clock cycles.
100
4 clock cycles.
101
5 clock cycles.
110
6 clock cycles.
111
0000
7 clock cycles
Reserved.
0001
1 clocks.
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles
1000
8 clock cycles
1001
9 clock cycle.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
0000
0 clock
0001
1 clock
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles.
1000
8 clock cycles.
Reserved. Write to zero for future compatibility.
ODT Power-Down Exit Timing (tAXPD)
Specifies how many clock cycles must pass after exit from
power-down before ODT can be asserted. The default is 1 clock
cycle.
Note: For DDR3, ODT_PD_EXIT must be greater than
TIMING_CFG_5[RODT_ON] when using RODT_ON
overrides and must be grater than
TIMING_CFG_5[WODT_ON] when using WODT_ON
overrides.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-53
DDR SDRAM Memory Controller
Table 12-25. TIMING_CFG_0 Field Descriptions (Continued)
Bit
Reset
Description
MRS_CYC
3–0
0b0101
Mode Register Set Cycle Time (tMRD)
Specifies the number of clock cycles that must pass between a
Mode Register Set command and another command. The
default is 5 clock cycles.
Settings
0000
Reserved
0001
1 clock
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles.
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
MSC8156 Reference Manual, Rev. 2
12-54
Freescale Semiconductor
Memory Controller Programming Model
12.8.6
DDR SDRAM Timing Configuration Register 1 (MnTIMING_CFG_1)
TIMING_CFG_1
Bit
31
30
DDR SDRAM Timing Configuration Register 1
29
PRETOACT
R/W
0
0
Type
Reset
0
Bit
15
14
0
REFREC
R/W
0
0
Type
Reset
13
28
27
26
25
ACTTOPRE
R/W
0
0
0
0
12
11
10
0
WRREC
R/W
0
0
0
9
24
23
22
21
ACTTORW
R/W
0
0
20
Offset 0x0108
19
18
17
16
0
0
CASLAT
R/W
0
0
0
0
0
0
8
7
6
4
3
2
0
—
R
0
ACTTOACT
R/W
0
0
0
—
R
0
WRTORD
R/W
0
0
0
5
1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-55
DDR SDRAM Memory Controller
TIMING_CFG_1 sets the number of clock cycles between various SDRAM control commands.
Table 12-26. TIMING_CFG_1 Field Descriptions
Bits
Reset
Description
PRETOACT
31–28
0
Precharge-to-Activate Interval (tRP)
Specifies the minimum number of clock cycles between a
precharge command and an activate or refresh command. This
number is calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
ACTTOPRE
27–24
0
Activate to Precharge Interval (tRAS)
Specifies the minimum number of clock cycles between an
activate command and a precharge command. This number is
calculated from the AC specifications of the SDRAM.
This field is concatenated with
TIMING_CFG_3[EXT_ACTTOPRE] to obtain a 5-bit value for the
total activate to precharge time. Note that the decode of
0000–0011 is equal to 16-19 clocks when
TIMING_CFG_3[EXT_ACTTOPRE] = 0, but it is equal to 0-3
clocks when TIMING_CFG_3[EXT_ACTTOPRE] = 1.
This field must be programmed for proper operation of the DDR
Controller.
Settings
0000
Reserved.
0001
1 clock
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
0000
16 clock cycles.
0001
17 clock cycles.
0010
18 clock cycles.
0011
19 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles.
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
MSC8156 Reference Manual, Rev. 2
12-56
Freescale Semiconductor
Memory Controller Programming Model
Table 12-26. TIMING_CFG_1 Field Descriptions (Continued)
Bits
Reset
Description
ACTTORW
23–20
0
Activate to Read/Write Interval for SDRAM (tRCD)
Specifies the minimum number of clock cycles between an
activate command and a read or write command. This interval is
calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
CASLAT
19–16
0
Settings
0000
Reserved.
0001
1 clock cycle.
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
MCAS Latency from READ Command
0000
Reserved.
Specifies the number of clock cycles between the time the
SDRAM registers a READ command and the availability of the
first output data. If a READ command is registered at clock edge
n and the latency is m clock cycles., data is available nominally
coincident with clock edge n + m. This field is concatenated
with TIMING_CFG_3[EXT_CASLAT] to obtain a 5-bit value for
the total CAS latency. This value must be programmed at
initialization as described in Section 12.8.9, DDR SDRAM
Control Configuration Register 2 (MnDDR_SDRAM_CFG_2) on
page 12-70.
This field must be programmed for proper operation of the DDR
Controller.
0001
1 clock cycle.
0010
Reserved.
0011
2 clock cycles.
0100
Reserved.
0101
3 clock cycles.
0110
Reserved.
0111
4 clock cycles.
1000
Reserved.
1001
5 clock cycles.
1010
Reserved.
1011
6 clock cycles.
1100
Reserved.
1101
7 clock cycles.
1110
Reserved.
1111
8 clock cycles.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-57
DDR SDRAM Memory Controller
Table 12-26. TIMING_CFG_1 Field Descriptions (Continued)
Bits
Reset
Description
REFREC
15–12
0
Refresh Recovery Time (t RFC )
Controls the number of clock cycles from a refresh command
until an activate command is allowed. This field is combined with
TIMING_CFG_3[EXT_REFREC] to obtain the total refresh
recovery time.
Note that the minimum value for REFREC is 8 clock cycles.
tRFC = {REFREC || EXT_REFREC} + 8
min. value = 8 clocks (REFREC = 0x0) + EXT_REFREC = 0x0
max. value = 240 + 15 + 8 = 263
This required value can be calculated by referring to the AC
specification of the SDRAM device. The AC specification
indicates a minimum refresh to activate interval in nanoseconds.
WRREC
11–8
0
Write Recovery (t WR)
Specifies the minimum number of clock cycles between the last
data associated with a write command and a precharge
command. This interval, write recovery time, is calculated from
the AC specifications of the SDRAM.
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs
to be programmed to (tWR + 2 cycles).
This field must be programmed for proper operation of the DDR
Controller.
Note:
DDR_SDRAM_CFG_2[OBC_CFG] = 1 is the
recommended mode.
—
7
0
Reserved. Write to zero for future compatibility.
ACTTOACT
6–4
0
Activate-to-Activate Interval (t RRD )
Specifies the minimum number of clock cycles between an
activate command and another activate command for a different
logical bank in the same physical bank (chip select). This
interval is calculated from the AC specifications of the SDRAM.
This field must be programmed for proper operation of the DDR
Controller.
Settings
0000
8 clock cycles.
0001
9 clock cycles.
0010
10 clock cycles.
0011
11 clock cycles.
0100
12 clock cycles.
0101
13 clock cycles.
0110
14 clock cycles.
0111
15 clock cycles.
0000
16 clock cycles.
0001
17 clock cycles.
0010
18 clock cycles.
0011
19 clock cycles.
0100
20 clock cycles.
0101
21 clock cycles.
0110
22 clock cycles.
1111
23 clock cycles.
0000
0 clock cycle.
0001
1 clock cycle.
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles.
0110
6 clock cycles.
0111
7 clock cycles
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
000
Reserved.
001
1 clock cycle.
010
2 clock cycles.
011
3 clock cycles.
100
4 clock cycles.
101
5 clock cycles.
110
6 clock cycles.
111
7 clock cycles.
MSC8156 Reference Manual, Rev. 2
12-58
Freescale Semiconductor
Memory Controller Programming Model
Table 12-26. TIMING_CFG_1 Field Descriptions (Continued)
Bits
Reset
Description
—
3
0
Reserved. Write to zero for future compatibility.
WRTORD
2–0
0
Last Write Data Pair to Read Command Interval (tWTR)
Specifies the minimum number of clock cycles between the last
write data pair and the subsequent read command to the same
physical bank.
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field needs
to be programmed to (tWTR + 2 cycles)
This field must be programmed for proper operation of the DDR
Controller.
000
Reserved.
001
1 clock cycle.
010
2 clock cycles.
011
3 clock cycles.
100
4 clock cycles.
101
5 clock cycles.
110
6 clock cycles.
Note:
111
7 clock cycles.
DDR_SDRAM_CFG_2[OBC_CFG] = 1 is the
recommended mode.
Settings
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-59
DDR SDRAM Memory Controller
12.8.7
DDR SDRAM Timing Configuration Register 2 (MnTIMING_CFG_2)
TIMING_CFG_2
Bit
31
DDR SDRAM Timing Configuration Register 2
30
29
28
27
26
25
0
0
0
0
0
8
7
6
5
4
0
R/W
0
ADD_LAT
Type
Reset
0
0
0
0
0
0
CPO
R/W
0
Bit
15
14
13
12
11
10
9
RD_TO_PRE
Type
Reset
0
0
WR_DATA_ DELAY
R/W
0
0
0
0
—
R
0
24
23
22
21
20
Offset 0x010C
19
18
17
16
0
0
—
R
0
0
3
2
1
0
0
0
WR_LAT
CKE_PLS
0
0
FOUR_ACT
0
0
0
TIMING_CFG_2 sets the clock delay to data for writes and should be defined according to the
system timing. Table 12-28 describes the TIMING_CFG_2 fields.
Table 12-27. TIMING_CFG_2 Field Descriptions
Bit
Reset
Description
ADD_LAT
31–28
0
Additive Latency
Specifies the number of clock cycles from the Posted CAS
operation until the registered read/write command is issued
inside the SDRAM as defined in the JEDEC DDR2 and DDR3
standards. The additive latency must be set to a value less than
TIMING_CFG_1[ACTTORW].
Note:
For DDR2 ADD_LAT can be 0–4.
For DDR3 ADD_LAT can be 0–2.
Settings
0000
0 clock cycles.
0001
1 clock cycle.
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles.
0101
5 clock cycles
0110
6 clock cycles
0111
7 clock cycles
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
MSC8156 Reference Manual, Rev. 2
12-60
Freescale Semiconductor
Memory Controller Programming Model
Table 12-27. TIMING_CFG_2 Field Descriptions (Continued)
Bit
Reset
Description
CPO
27–23
0
MCAS-to-Preamble Override
Defines the number of DRAM cycles between a read command
and the time the corresponding DQS preamble is valid for the
memory controller. For these decodings, read latency (RL) is
equal to the CAS latency plus the additive latency. For CPO
decodings other than 00000 and 11111, read latency is rounded
up to the next integer value. In other words, CPO timing decides
when the DDR controller starts to wait for the first DQS rising
edge from DDR memory during the DQS preamble for read
access. The DQS rising edge should occur within 1 clock cycle
from the timing defined by this parameter.
Settings
00000 RL + 1
00001 Reserved
00010 RL
00011 RL + 1/4
00100 RL + 1/2
00101 RL + 3/4
00110 RL + 1
00111 RL + 5/4
01000 RL + 3/2
01001 RL + 7/4
01010 RL + 2
01011 RL + 9/4
01100 RL + 5/2
01101 RL + 11/4
01110 RL + 3
01111 RL + 13/4
10000 RL + 7/2
10001 RL + 15/4
10010 RL + 4
10011 RL + 17/4
10100 RL + 9/2
10101 RL + 19/4
10110 RL + 5
10111 RL + 21/4
11000 RL + 11/2
11001 RL + 23/4
11010 RL + 6
11011 RL + 25/4
11100 RL + 13/2
11101 RL + 27/4
11110 RL + 7
11111 Automatic
Calibration
(recommended)
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-61
DDR SDRAM Memory Controller
Table 12-27. TIMING_CFG_2 Field Descriptions (Continued)
Bit
Reset
WR_LAT
22–19
0
Description
Write Latency
Specifies the number of clock cycles between the write
command and the first data write when AL = 0. When additive
latency is applied, WR_LAT specifies the number of clock
cycles from when the SDRAM issues the registered write
command to the first data write.
This field must be programmed for proper operation of the DDR
Controller.
—
18–16
0
Reserved. Write to zero for future compatibility.
RD_TO_PRE
15–13
0
Read to Precharge (t RTP)
When AL = 0 then RD_TO_PRE specifies the number of clock
cycles between the read command and the precharge
command. When additive latency is applied, RD_TO_PRE
specifies minimum tRTP timing from the registered read
command issued internally by the SDRAM to the precharge
command. The interval between the posted read command and
the precharge command is ADD_LAT + RD_TO_PRE cycles.
If DDR_SDRAM_CFG_2[OBC_CFG] is set, then this field
needs to be programmed to (tRTP + 2 cycles)
This field must be programmed for proper operation of the DDR
Controller.
Note:
Settings
0000
Reserved.
0001
1 clock cycle.
0010
2 clock cycles.
0011
3 clock cycles.
0100
4 clock cycles
0101
5 clock cycles
0110
6 clock cycles
0111
7 clock cycles
1000
8 clock cycles.
1001
9 clock cycles.
1010
10 clock cycles.
1011
11 clock cycles.
1100
12 clock cycles.
1101
13 clock cycles.
1110
14 clock cycles.
1111
15 clock cycles.
000
Reserved.
001
1 clock cycle.
010
2 clock cycles.
011
3 clock cycles.
100
4 clock cycles.
101
5 clock cycle.
110
6 clock cycles.
111
7 clock cycles.
DDR_SDRAM_CFG_2[OBC_CFG] = 1 is the
recommended mode.
MSC8156 Reference Manual, Rev. 2
12-62
Freescale Semiconductor
Memory Controller Programming Model
Table 12-27. TIMING_CFG_2 Field Descriptions (Continued)
Bit
Reset
Description
WR_ DATA_
DELAY
12–10
0
Write Data Delay
Specifies the adjust timing of DQS and data from its associated
clock edge during write cycles. The adjust timing range step
sizes are in 1/4 SDRAM clock periods. The tDQSS specification
must be within ±25% of the SDRAM clock in the case of
DDR2.This parameter is used to meet the tDQSS timing
requirement. Using the same clock delay setting for
TIMING_CFG_2[WR_DATA_DELAY] and
DDR_SDRAM_CLK_CNTL[CLK_ADJUST] ideally results in no
tDQSS skew.
The write preamble is typically driven high for 1/2 DRAM cycle,
and then it is driven low for 1/2 DRAM cycle. However, for
WR_DATA_DELAY settings of 0 clocks and 1/4 clocks, the write
preamble is driven low for the entire DRAM cycle. If the
preamble needs to switch high first (to meet DDR3
specifications), then these values should not be used.
Figure 12-11 is an example of the timing definition of
WR_DATA_DELAY when using CLK_ADJUST with a 1/2 clock
delay.
Note: The recommended value for this field is 0b010.
—
9
0
Reserved. Write to zero for future compatibility.
CKE_PLS
8–6
0
Minimum CKE Pulse Width (tCKE)
Specifies the minimum clock cycles tCKE that SDRAM must
remain in Self-Refresh mode.
This field must be programmed for proper operation of the DDR
Controller.
Settings
000
0 clock delay
001
1/4 clock delay
010
1/2 clock delay
011
3/4 clock delay
100
1 clock delay
101
5/4 clock delay
110
3/2 clock delay
111
Reserved
000
Reserved.
001
1 clock cycle.
010
2 clock cycles.
011
3 clock cycles.
100
4 clock cycles.
101
5 clock cycle.
110
6 clock cycles.
111
7 clock cycles.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-63
DDR SDRAM Memory Controller
Table 12-27. TIMING_CFG_2 Field Descriptions (Continued)
Bit
Reset
FOUR_ACT
5–0
0
Description
Window for Four Activates (tFAW).
Specifies the tFAW timing.
This is applied to DDR2/DDR3 with eight logical banks only.
See Section 2.5 Bank Active Command in JESD79-2C, p. 28.
Settings
000000 Reserved.
000001 1 clock cycle.
000010 2 clock cycles.
000011 3 clock cycles.
000100 4 clock cycles.
000101 5 clock cycle.
000110 6 clock cycles.
000111 7clock cycles.
001000 8clock cycles.
001001 9 clock cycle.
001010 10 clock cycles.
001011 11 clock cycles.
001100 12 clock cycles.
001101 13 clock cycle.
001110 14 clock cycles.
001111 15 clock cycles.
010000 16 clock cycles.
010001 17 clock cycle.
010010 18 clock cycles.
010011 19clock cycles.
010100 20clock cycles.
010101 21 clock cycle.
010110 22 clock cycles.
010111 23 clock cycles.
011000 24 clock cycles.
011001 25 clock cycle.
011010 26 clock cycles.
011011 27clock cycles.
011100 28clock cycles.
011101 29 clock cycle.
011110 30 clock cycles.
011111 31 clock cycles.
100000 32 clock cycles.
100001–111111 Reserved.
MSC8156 Reference Manual, Rev. 2
12-64
Freescale Semiconductor
Memory Controller Programming Model
12.8.8
DDR SDRAM Control Configuration Register
(MnDDR_SDRAM_CFG)
DDR_SDRAM_CFG
Bit
31
30
DDR SDRAM Control Configuration Register
29
28
27
26
—
SDRAM_TYPE
0
R
0
0
R/W
1
1
12
11
10
9
8
MEM_ SREN ECC_ RD_
EN
EN
EN
Type
Reset
Bit
0
R/W
0
0
15
14
13
2T_EN
Type
Reset
0
25
24
23
22
21
20
—
0
0
DYN_
PWR_
MGMT
R/W
0
7
6
5
4
—
R
BA_INTLV_CTL
0
0
R/W
0
0
—
0
0
0
0
0
19
0
18
17
16
32_BE 8_BE NCAP 3T_EN
R
0
R
0
Offset 0x0110
R/W
0
0
3
2
HSE
—
R/W
0
R
0
0
0
1
0
MEM_
BI
HALT
R/W
0
0
DDR_SDRAM_CFG enables the interface logic and specifies certain operating features such as
self refreshing, error checking and correcting and dynamic power management.
Table 12-28. DDR_SDRAM_CFG Field Descriptions
Bits
Reset
Description
MEM_EN
31
0
DDR SDRAM Interface Logic Enable
Enables/disables SDRAM interface logic. This bit
must not be set until the initialization code has
appropriately configured all other memory
configuration parameters.
Self Refresh Enable (during sleep)
Enables/disables self refresh during sleep. When self
refresh is disabled, the system is responsible for
preserving the integrity of SDRAM during sleep.
0
SDRAM interface logic is
disabled.
1
SDRAM interface logic is
enabled.
0
SDRAM self refresh is disabled
during sleep.
1
0
SDRAM self refresh is enabled
during sleep
No ECC errors are reported. No
ECC interrupts are generated.
SREN
30
0
ECC_EN
29
0
ECC Enable
Enables/disables ECC protection mechanism
including error reporting and interrupts.
RD_EN
28
0
Registered DIMM Enable
Specifies the type of DIMM used in the system.
Note: RD_EN and 2T_EN must not be both set at
the same time.
Reserved. Write to zero for future compatibility.
—
27
SDRAM_ TYPE
26–24
—
23–22
DYN_PWR
21
0
011
Type of SDRAM Device
Specifies the type of device. The default value is
0b011 to designate DDR2 SDRAM.
0
Reserved. Write to zero for future compatibility.
0
Dynamic Power Management Mode
Enabled/disables dynamic power management
mode. When this bit is set and there is no on-going
memory activity, the SDRAM CKE signal is
deasserted.
Settings
1
0
ECC is enabled.
Unbuffered DIMM.or discrete
memory devices.
1
Registered DIMM.
011
DDR2 SDRAM.
111
DDR3 SDRAM.
All other values reserved.
0
Dynamic power management
mode is disabled.
1
Dynamic power management
mode is enabled.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-65
DDR SDRAM Memory Controller
Table 12-28. DDR_SDRAM_CFG Field Descriptions (Continued)
Bits
Reset
—
20
32_BE
19
0
Reserved. Write to zero for future compatibility.
0
32-Bit Bus Enable
Selects bus size.
8_BE
18
0
NCAP
17
0
3T_EN
16
2T_EN
15
BA_INTLV_CTL
14–8
0
0
0
Description
8-Beat Burst Enable
Note: DDR2 (SDRAM_TYPE = 011) must use
4-beat bursts, even when using 32-bit bus
mode; DDR3 (SDRAM_TYPE = 111) must
use 8-beat bursts when using 32-bit bus
mode. DDR3 must use 4 beat burst when
using 64-bit bus mode.
Non-Concurrent Auto-Precharge
Some older DDR DRAMs do not support concurrent
auto precharge. If one of these devices is used, this
bit must be set if auto precharge is used.
3T Timing Enable
Enables/disabled 3T timing. This field cannot be set if
DDR_SDRAM_CFG[2T_EN] is also set.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for three full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the third
cycle.
2T Timing Enable
Enables/disabled 2T timing.
This field cannot be used with a 32-bit bus if 4-beat
bursts are used.
When this bit is cleared, the DRAM
command/address are held for only one cycle on the
DRAM bus. When this bit is set, the DRAM
command/address are held for two full clock cycles.
on the DRAM bus for every DRAM transaction.
However, the chip select is held only for the second
cycle.
Bank (chip select) interleaving control.
Set this field only if you wish to use bank interleaving.
Settings
0
64-bit bus is used.
1
0
32-bit bus is used.
4-beat burst.
1
8-beat burst.
0
DRAMs in system support
concurrent auto-precharge.
1
0
DRAMs in system do not support
concurrent auto-precharge.
1T timing is enabled if 2T_EN is
also cleared. The DRAM
command/address are held for
only 1 cycle on the DRAM bus.
1
3T timing is enabled.
0
1T timing is used if 3T_EN is also
cleared.
1
2T timing is enabled.
0000000 No external memory banks are
interleaved
1000000 External memory banks 0 and
1 are interleaved
—
7–4
HSE
3
—
2
0
Reserved. Write to zero for future compatibility.
0
Half-Strength Drive Enable
Specifies whether the I/O drivers are configured to full
strength or half strength. This bit applies only when
automatic driver compensation is disabled and the
software override for the driver strength is not used in
DDRCDR1 and 2.
Reserved. Write to zero for future compatibility.
0
0
I/O drivers are configured to
full-strength.
1
IO drivers are configured to
half-strength.
MSC8156 Reference Manual, Rev. 2
12-66
Freescale Semiconductor
Memory Controller Programming Model
Table 12-28. DDR_SDRAM_CFG Field Descriptions (Continued)
Bits
Reset
Description
MEM_HALT
1
0
DDR Memory Controller Halt
When this bit is set, the memory controller does not
accept any new transactions until the bit is cleared.
This bit can be used when initialization is bypassed
and the MODE REGISTER SET, EXTENDED MODE
REGISTER SET, EXTENDED MODE REGISTER2
SET and EXTENDED MODE REGISTER3 SET
commands are forced through software. This bit
should be used carefully.
Using this MHALT option can create congestion on
the system interconnection and can cause hangs of
the cores and other initiator.
Bypass Initialization
Specifies the conditions for initialization. When this bit
is set, software is responsible for initializing memory
through the DDR_SDRAM_MD_CNTL register. If
software is initializing memory, the MEM_HALT bit
can be set to prevent the DDR controller from issuing
transactions during the initialization sequence.
Note: Note that the DDR controller does not issue
a DLL reset to the DRAMs when bypassing
the initialization routine, regardless of the
value of
DDR_SDRAM_CFG[DLL_RST_DIS]. If a
DLL reset is required, then the controller
should be forced to enter and exit self
refresh after the controller is enabled.
For details on avoiding ECC errors in this mode, see
the discussion of the DDR SDRAM Initialization
Address Register on page 12-76.
BI
0
0
12.8.9
Settings
0
DDR controller accepts new
transactions.
1
DDR controller finishes any
remaining transactions and then
halts until software clears this bit.
0
DDR controller cycles through
the initialization routine based on
the value of SDRAM_Type.
1
Initialization routine is bypassed.
DDR SDRAM Control Configuration Register 2
(MnDDR_SDRAM_CFG_2)
DDR_SDRAM_CFG_2 DDR SDRAM Control Configuration Register 2
Bit
26
31
30
29
28
27
FRC_
SR
—
—
DQS_CFG
—
ODT_CFG
—
Type
Reset
R/W
0
R
0
DLL_
RST_
DIS
R/W
0
R
0
R/W
R/W
0
0
0
R
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
NUM_PR
Type
Reset
0
0
24
23
—
R/W
0
25
0
0
0
R
0
0
0
22
21
20
Offset 0x0114
OBC_ AP_ D_INIT
CFG
EN
R/W
0
0
0
19
17
16
0
R
0
0
0
3
2
1
0
—
RCW_
EN
R/W
0
—
MD_
EB
R/W
0
R
0
18
R
0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-67
DDR SDRAM Memory Controller
DDR_SDRAM_CFG_2 provides control configuration for the DDR controller in addition to that
provided by DDR_SDRAM_CFG.
Table 12-29. DDR_SDRAM_CFG_2 Field Descriptions
Bit
Reset
FRC_SR
31
0
—
30
DLL_RST_
DIS
29
0
Reserved. Write to zero for future compatibility.
0
DLL Reset Disable
The DDR controller typically issues a DLL reset to the
DRAMs when it exists self refresh. However, you can
disable this function by setting this bit during
initialization.
—
28
DQS_CFG
27–26
—
25–23
ODT_CFG
22–21
—
20–16
NUM_PR
15–12
—
11–7
Description
Force Self Refresh
0
Reserved. Write to zero for future compatibility.
0
DQS Configuration
This bit must be programmed for proper operation.
0
Reserved. Write to zero for future compatibility.
0
ODT Configuration
Defines how ODT is driven to the on-chip I/O.
See Table 12-51 and Table 12-52 for the definition of
the impedance value that is used.
0
Reserved. Write to zero for future compatibility.
0
Number of Posted Refreshes
Determines how many posted refreshes, if any, can be
issued at one time. If posted refreshes are used, this
field, along with DDR_SDRAM_INTERVAL[REFINT],
must be programmed so that the maximum tras
specification cannot be violated. For example, some
DDR SDRAMs cannot use more than three posted
refreshes because the required refresh interval can
exceed the maximum constraint for tras.
Note: {TIMING_CFG_1[PRETOACT] +
[DDR_SDRAM_CFG_2[NUM_PR] *
({EXT_REFREC || REFREC} + 8 + 2)]} <<
DDR_SDRAM_INTERVAL[REFINT
Reserved. Write to zero for future compatibility.
0
0
Normal operating mode.
1
Enter ‘Self Refresh mode.
0
DDR controller issues a DLL
reset when exiting self refresh.
1
DDR controller does not issue a
DLL reset when exiting self
refresh.
00
Reserved
01
Differential DQS signals are
used for DDR2 support.
10
Reserved.
11
Reserved.
00
Never assert ODT to internal
I/O.
01
Assert ODT to internal I/O
only during writes to DRAM.
10
Assert ODT to internal I/O
only during reads to DRAM.
11
Always keep ODT asserted to
internal I/O.
0000
Reserved.
0001
1 refresh at a time.
0010
2 refreshes at a time.
0011
3 refreshes at a time.
0100
4 refreshes at a time.
0101
5 refresh at a time.
0110
6 refreshes at a time.
0111
7 refreshes at a time.
1000
8 refreshes at a time.
1001–1111Reserved.
MSC8156 Reference Manual, Rev. 2
12-68
Freescale Semiconductor
Memory Controller Programming Model
Table 12-29. DDR_SDRAM_CFG_2 Field Descriptions (Continued)
Bit
Reset
Description
OBC_CFG
6
0
On-The-Fly Burst Chop Configuration
Determines if on-the-fly Burst Chop is used. This bit
should only be set if DDR3 memories are used. If
on-the-fly Burst Chop mode is not used with DDR3
memories, then fixed Burst Chop mode may be used if
the proper turnaround times are programmed into
TIMING_CFG_0 and TIMING_CFG_4.
DDR_SDRAM_CFG[8_BE] should be cleared for both
on-the-fly Burst Chop mode or fixed Burst Chop mode
when using a 64-bit data bus with DDR3 memories.
AP_EN
5
0
D_INIT
4
0
Address Parity Enable
Determines whether to generate and check address
parity for the address and control signals when using
registered DIMMs. If address parity is used, the
MAPAR_OUT and MAPAR_IN pins are used to drive
the parity bit and to receive errors from the open-drain
parity error signal. Even parity are used, and parity is
generated for the MA[15–0], MBA[2–0], MRAS,
MCAS, MWE signals. Parity is not generated for the
MCKE[0–1], MODT[0–1], or MCS[0–1] signals.
Note: Address parity should not be used for
non-zero values of
TIMING_CFG_3[CNTL_ADJ].
DRAM Data Initialization
This bit is set by software, and it is cleared by
hardware. If software sets this bit before the memory
controller is enabled, the controller automatically
initializes DRAM after it is enabled. This bit is
automatically cleared by hardware once the
initialization is completed. This data initialization bit
should only be set when the controller is idle..
Reserved. Write to zero for future compatibility.
—
3
RCW_EN
2
—
1
0
0
0
Register Control Word Enable
If DDR3 registered DIMMs are used, it may be
necessary to write the register control words before
issuing commands to DRAM. If this bit is set, the
controller writes the register control words after
DDR_SDRAM_CFG[MEM_EN] is set, unless
DDR_SDRAM_CFG[BI] is set. The register control
words are written with the values in
DDR_SDRAM_RCW_1 and DDR_SDRAM_RCW_2.
0
On-the-fly Burst Chop mode is
disabled. Fixed burst lengths
defined in
DDR_SDRAM_CFG[8_BE] are
used. If fixed Burst Chop is used
(with DDR3 memories), then
DDR_SDRAM_CFG[8_BE]
should be cleared.
1 On-the-fly Burst Chop mode is
used. DDR_SDRAM_CFG[8_BE]
should be cleared for on-the-fly
Burst Chop mode.
DDR_SDRAM_CFG[32-BE]
should also be cleared for
on-the-fly Burst Chop mode
0 Address parity not used
1
Address parity used
0
No data initialization, and no data
initialization is scheduled.
1
The memory controller initializes
memory when it is enabled.
0
Register control words are not
automatically written during
DRAM initialization.
1
Register control words are
automatically written during
DRAM initialization. This bit
should only be set if DDR3
registered DIMMs are used, and
the default settings need to be
modified.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-69
DDR SDRAM Memory Controller
Table 12-29. DDR_SDRAM_CFG_2 Field Descriptions (Continued)
Bit
Reset
Description
MD_EN
0
0
Mirrored DIMM Enable
Some DDR3 DIMMs are mirrored, where certain MA
and MBA pins are mirrored on one side of the DIMM.
When this bit is set, the controller knows to swap these
signals before transmitting to the DRAM. The
controller assumes that CS1 and CS3 are the
‘mirrored’ ranks of memory. The following signals are
mirrored (MnBA0 versus MBA1; MA3 versus MA4;
MA5 versus MA6; MA7 versus MA8).
12.8.10
Mirrored DIMMs are not used.
1
Mirrored DIMMs are used.
DDR SDRAM Mode Configuration Register
(MnDDR_SDRAM_MODE)
DDR_SDRAM_MODE
Bit
0
31
30
29
DDR SDRAM Mode Configuration Register
28
27
26
25
24
23
ESDMODE
R/W
0
0
Offset 0x0118
22
21
20
19
18
17
16
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
SDMODE
R/W
0
0
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
DDR_SDRAM_MODE sets the values loaded into the DDR mode registers.
Table 12-30. DDR_SDRAM_MODE Bit Descriptions
Bit
Refresh
Description
ESDMODE
31–16
0
SDMODE
15–0
0
Extended SDRAM Mode
Specifies the initial value loaded into the DDR SDRAM extended mode register. The range
of legal values is specified by the DDR SDRAM manufacturer. When this value is driven
onto the address bus during DDR SDRAM initialization, MA0 presents the LSB of
ESDMODE, which corresponds to DDR_SDRAM_MODE bit 16. The MSB of the SDRAM
extended mode register value must be stored at DDR_SDRAM_MODE bit 31
The value programmed into this field is also used for writing MR1 during write leveling for
DDR3, although the bits specifically related to the write leveling scheme are handled
automatically by the DDR controller. Even if DDR_SDRAM_CFG[BI] is set, this field is still
used during write leveling.
SDRAM Mode
Specifies the initial value loaded into the DDR SDRAM mode register. The range of legal
values is specified by the DDR SDRAM manufacturer. When this value is driven onto the
address bus during DDR SDRAM initialization, MA0 presents the LSB of SDMODE, which,
corresponds to DDR_SDRAM_MODE bit 0. The MSB of the SDRAM mode register value
must be stored at DDR_SDRAM_MODE bit 15. Because the memory controller forces
SDMODE[8] to certain values depending upon the state of the initialization sequence (for
resetting the SDRAM DLL) which is mapped to MA8; the memory controller ignores the
corresponding bits of this field.
MSC8156 Reference Manual, Rev. 2
12-70
Freescale Semiconductor
Memory Controller Programming Model
12.8.11
DDR SDRAM Mode Configuration 2 Register
(MnDDR_SDRAM_MODE_2)
DDR_SDRAM_MODE_2
Bit
31
30
29
DDR SDRAM Mode Configuration 2
Register
28
27
26
25
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
Type
Reset
0
0
0
0
0
0
0
24
23
22
ESDMODE2
R/W
0
0
8
7
ESDMODE3
R/W
0
0
21
Offset 0x011C
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DDR_SDRAM_MODE_2 sets the values loaded into the DDR extended mode 2 and 3 registers.
Table 12-31. DDR_SDRAM_MODE_2 Bit Descriptions
Bit
Reset
Description
ESDMODE2
31–16
0
ESDMODE3
15–0
0
Extended SDRAM Mode 2
Specifies the initial value loaded into the DDR SDRAM Extended 2 Mode Register. The range
and meaning of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus during the DDR SDRAM initialization sequence,
MA0 presents the LSB bit of ESDMODE2, which corresponds to DDR_SDRAM_MODE_2 bit
16. The MSB of the SDRAM extended mode 2 register value must be stored at
DDR_SDRAM_MODE_2 bit 31.
Extended SDRAM Mode 3
Specifies the initial value loaded into the DDR SDRAM Extended 3 Mode Register. The range
of legal values is specified by the DDR SDRAM manufacturer.
When this value is driven onto the address bus during DDR SDRAM initialization, MA0 presents
the LSB of ESDMODE3, which corresponds to DDR_SDRAM_MODE_2 bit 0. The MSB of the
SDRAM extended mode 3 register value must be stored at DDR_SDRAM_MODE_2 bit 15.
12.8.12
DDR SDRAM Mode Control Register (MnDDR_SDRAM_MD_CNTL)
DDR_SDRAM_MD_CNTL
DDR SDRAM Mode Control Register
Bit
31
30
29
28
27
—
CS_ SEL
—
Type
Reset
MD_
EN
R/W
0
R
0
R/W
0
0
R
0
0
Bit
15
14
13
12
11
10
Type
Reset
0
0
0
0
0
26
25
24
23
22
SET_
PRE
0
0
SET_
REF
R/W
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
MD_VALUE
R/W
0
0
0
0
0
0
0
0
0
MD_SEL
0
Offset 0x0120
0
21
20
19
18
17
CKE_CNTL WRC
W
16
—
R
DDR_SDRAM_MD_CNTL allows software to force mode/extended mode register set
commands to DRAM, including the following:
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-71
DDR SDRAM Memory Controller
„
„
„
„
Issue a MODE REGISTER SET command to a particular chip select
Issue an immediate REFRESH to a particular chip select
Issue an immediate PRECHARGE or PRECHARGE ALL command to a particular chip select
Force the CKE signals to a specific value
Note:
Each command initiated through the DDR_SDRAM_MD_CNTL register should be
initiated separately in the order required by the DDR SDRAM. If multiple commands
are initiated simultaneously, the execution order is not guarantied and can cause
malfunction of the DDR SDRAM.
Table 12-32. DDR_SDRAM_MD_CNTL Bit Descriptions
Bit
Reset
Description
MD_EN
31
0
Mode Enable
Setting this bit specifies that valid data in MD_VALUE is
ready to be written to DRAM as one of the following
commands:
• MODE REGISTER SET
• EXTENDED MODE REGISTER SET
• EXTENDED MODE REGISTER SET 2
• EXTENDED MODE REGISTER SET 3
The specific command to be executed is selected by setting
MD_SEL. In addition, the chip select must be chosen by
setting CS_SEL. MD_EN is set by software and cleared by
hardware once the command has been issued.
Reserved. Write to zero for future compatibility.
—
30
CS_SEL
29–28
—
27
MD_SEL
26–24
SET_REF
23
0
0
0
000
0
Select Chip Select
Specifies the chip select to drive active due to any
command forced by software in
DDR_SDRAM_MD_CNTL.
Settings
0
Indicates that no MODE REGISTER
SET command needs to be
issued.
1
Indicates that valid data
contained in the register is ready
to be issued as a MODE REGISTER
SET command.
00
Chip select 0 is active.
01
Chip select 1 is active.
10
Reserved.
11
Reserved.
Reserved. Write to zero for future compatibility.
Mode Register Select
MD_SEL specifies one of the following:
• During a mode select command, selects the SDRAM
mode register to be changed
• During a precharge command, selects the SDRAM
logical bank to be precharged. A precharge all command
ignores this field.
• During a refresh command, this field is ignored.
Note that MD_SEL contains the value that is presented
onto the memory bank address pins (MBAn) of the DDR
controller.
000 MR
001 EMR
010 EMR2
011 EMR3
Set Refresh
Forces an immediate refresh to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. Software sets this bit
and hardware clears it when the command is issued.
Note: SET_REF, and SET_PRE are mutually exclusive;
they cannot be set at the same time
000
MR Mode register
001
EMR Extended Mode
Register
010
EMR2 Extended Mode
Register 2
011
EMR3 Extended Mode
Register 3
0 No REFRESH command to issue.
1 A REFRESH command is ready to
issue.
MSC8156 Reference Manual, Rev. 2
12-72
Freescale Semiconductor
Memory Controller Programming Model
Table 12-32. DDR_SDRAM_MD_CNTL Bit Descriptions (Continued)
Bit
Reset
Description
Settings
SET_PRE
22
0
0 No PRECHARGE ALL command to
issue.
1 Issue a PRECHARGE or PRECHARGE
ALL command.
CKE_CNTL
21–20
0
Set Precharge
Forces a precharge command or precharge all command
to be issued to the chip select specified by
DDR_SDRAM_MD_CNTL[CS_SEL]. Software sets this
bit, and hardware clears it when the command is issued.
Note: SET_REF, and SET_PRE are mutually exclusive;
they cannot be set at the same time
Clock Enable Control
Software uses tthese bits to set or clear all CKE signals
issued to DRAM. When software forces the value driven
on CKE, that value continues to be forced until software
clears the CKE_CNTL bits. The DDR controller continues
to drive the CKE signals to the value forced by software
until another event causes the CKE signals to change (that
is, self refresh entry/exit, power down entry/exit).
Write Register Control Word
If software sets this bit, then a register control word is
written by asserting the selected chip selects while
providing the programmed data on the MA and MBA
signals. RAS, CAS, and WE remain deasserted during this
write The MD_EN field should also be set to force a
register control word write. This should only be set if DDR3
registered DIMMs are used and the register needs to be
configured. If DDR_SDRAM_MD_CNTL is used to write
RCW2 specifically, then software must guarantee that the
timing parameter, t-STAB, is met before future accesses to
the controller are allowed. In addition,
DDR_SDRAM_MD_CNTL register cannot be used to write
the RCWs if write leveling is used, since write leveling is
run automatically before DDR_SDRAM_MD_CNTL can be
used to force RCW writes.
Reserved. Write to zero for future compatibility.
Mode Register Value
This field specifies the value that is presented on the
memory address pins of the DDR controller during a MODE
REGISTER SET command. This field is significant only when
this register is used to issue a MODE REGISTER SET
command or a PRECHARGE or PRECHARGE ALL command.
For a MODE REGISTER SET command, this field contains the
data to be written to the selected mode register.
For a PRECHARGE command, MD_VALUE10 is mapped to
MA10 to distinguish between a PRECHARGE command and
a PRECHARGE ALL command, as follows:
0
Issue a PRECHARGE command;
MD_SEL selects the logical bank
to be precharged
1
Issue a PRECHARGE ALL
command; all logical banks are
precharged
WRCW
19
0
—
18–16
MD_
VALUE
15–0
0
0
00 Software does not force the CKE
signals.
01 Software forces the CKE signals
to a low value.
10 Software forces the CKE signals
to a high value.
11 Reserved.
0 Indicates that a register control
word write is not issued if MD_EN
is set.
1 Indicates that a register control
word write is issued if MD_EN is
set.
All other values are not valid.
Table 12-33 shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks
described above.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-73
DDR SDRAM Memory Controller
Table 12-33. Settings of DDR_SDRAM_MD_CNTL Fields
Field
Mode Register Set
Refresh
Precharge
Clock Enable Signals
Control
MD_EN
1
0
0
—
SET_REF
0
1
0
—
SET_PRE
0
0
1
—
CS_SEL
Chooses chip select (CS)
MD_SEL
Select mode register.
See Table 12-32.
—
MD_VALUE
Value written to mode
register
—
CKE_CNTL
12.8.13
0
0
Bit
15
0
—
Only MD_VALUE10 is
significant. See Table
12-32.
See Table 12-32.
0
30
29
28
DDR SDRAM Interval Configuration
Register
27
26
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
REFINT
R/W
0
0
14
13
12
11
10
9
8
0
0
0
0
0
Offset 0x0124
25
—
Type
Reset
—
DDR SDRAM Interval Configuration Register
(MnDDR_SDRAM_INTERVAL)
31
Type
Reset
Selects logical bank
0
DDR_SDRAM_INTERVAL
Bit
—
0
0
7
BSTOPRE
R/W
0
0
DDR_SDRAM_INTERVAL sets the number of DRAM clock cycles between bank refreshes
issued to the DDR SDRAMs. In addition, it specifies the number of DRAM cycles that a page is
maintained after it is accessed.
Table 12-34. DDR_SDRAM_INTERVAL Bit Descriptions
Bit
Refresh
REFINT
31–16
0
Description
Refresh Interval
Represents the number of memory bus clock cycles between refresh cycles. Depending on
DDR_SDRAM_CFG_2 [NUM_PR], some number of rows are refreshed in each DDR SDRAM
physical bank during each refresh cycle. The value for REFINT depends on the specific
SDRAMs used and the interface clock frequency. Refreshes are not issued when REFINT is
cleared to all 0s.
MSC8156 Reference Manual, Rev. 2
12-74
Freescale Semiconductor
Memory Controller Programming Model
Table 12-34. DDR_SDRAM_INTERVAL Bit Descriptions (Continued)
Bit
Refresh
—
15–14
BSTOPRE
13–0
0
Reserved. Write to zero for future compatibility.
0
Precharge Interval
Specifies the duration (in memory bus clock cycles) that a page is retained after a DDR SDRAM
access. The page open counter is loaded with BSTOPRE each time the page is accessed
(including page hits). When the counter expires, the open page is closed with an SDRAM
precharge bank command as soon as possible. If BSTOPRE has a value of zero, the DDR
memory controller uses auto-precharge read and write commands rather than operating in page
mode. This is called global auto-precharge mode.
12.8.14
Description
DDR SDRAM Data Initialization Register (MnDDR_DATA_INIT)
DDR_DATA_INIT
Bit
31
30
DDR SDRAM Data Initialization Register
29
28
27
26
25
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
Type
Reset
0
0
0
0
0
0
0
24
23
22
INIT_VALUE
R/W
0
0
8
7
INIT_VALUE
R/W
0
0
21
Offset 0x0128
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DDR_DATA_INIT provides the value to initialize memory if DDR_SDRAM_CFG_2[D_INIT]
is set. When ECC is enabled, initializing all the available memory space can ensure that reads
from unwritten addresses does not return ECC errors and interrupts.
Table 12-35. DDR_DATA_INIT Bit Descriptions
Bits
Reset
INIT_VALUE
31–0
0
12.8.15
Description
Initialization Value
Specifies the initialization value for the DRAM if DDR_SDRAM_CFG_2[D_INIT] is set.
DDR SDRAM Clock Control Configuration Register
(MnDDR_SDRAM_CLK_CNTL)
DDR_SDRAM_CLK_CNTL
Bit
31
30
29
0
0
0
12
11
10
Type
Reset
0
0
—
R
0
Bit
15
14
13
Type
Reset
28
DDR SDRAM Clock
Control Configuration Register
27
26
25
24
23
CLK_ADJUST
R/W
1
0
9
8
22
Offset 0x0130
21
20
19
18
17
16
0
0
0
0
0
0
0
—
R
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
R
0
0
0
0
0
0
0
0
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-75
DDR SDRAM Memory Controller
DDR_SDRAM_CLK_CNTL provides a source synchronous option, along with a 1/8 cycle clock
adjustment.
Table 12-36. DDR_SDRAM_CLK_CNTL Bit Descriptions
Bit
Reset
Description
Settings
—
31–27
CLK_ADJUST
26–23
0
Reserved. Write to zero for future compatibility.
4’b0100
Clock Adjust
Specifies when the clock is launched in
relationship to the address/command. Set delay
from address/command start timing to MCK
rising edge.
0000 Clock launched and aligned with
address/command.
0001 Clock launched 1/8 applied
cycle after address/command.
0010 Clock launched 1/4 applied
cycle after address/command.
0011 Clock launched 3/8 applied
cycle after address/command.
0100 Clock launched 1/2 applied
cycle after address/command.
0101 Clock launched 5/8 applied
cycle after address/command.
0110 Clock launched 3/4 applied
cycle after address/command.
0111 Clock launched 7/8 applied
cycle after address/command.
1000 Clock launched 1 applied cycle
after address/command.
1001–1111Reserved.
Figure 12-5, Figure 12-6, and Figure 12-7 in
Section 12.4 show the timing relationships
between clock and command for the case of
CLK_ADJUST 0100 1/2 clock delay, which
means nominal timing. The MCK rising edge is in
the center of the address/command period in
general.
—
22–0
12.8.16
0
DDR SDRAM Initialization Address Register (MnDDR_INIT_ADDR)
DDR_INIT_ADDR
Bit
31
Reserved. Write to zero for future compatibility.
30
DDR SDRAM Initialization Address Register
29
28
27
26
25
Type
Reset
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
Type
Reset
0
0
0
0
0
0
0
24
23
INIT_ADDR
R/W
0
0
8
7
INIT_ADDR
R/W
0
0
22
21
Offset 0x0148
20
19
18
17
16
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
0
0
0
0
0
0
DDR_INIT_ADDR provides the address for the data strobe to data skew adjustment and
automatic CAS to preamble calibration after setting DDR_SDRAM_CFG[MEM_EN].
Note:
After the skew adjustment, this address contains bad ECC data, which is not important
at power-on reset because all memory should subsequently be initialized if ECC is
enabled either through software or through the use of the
DDR_SDRAM_CFG_2[D_INIT] bit. However, if the DSP is reset after the DRAM
enters Self-Refresh mode, memory is not initialized. Therefore this address should be
written to avoid possible ECC errors when this address is accessed later.
MSC8156 Reference Manual, Rev. 2
12-76
Freescale Semiconductor
Memory Controller Programming Model
Table 12-37. DDR_INIT_ADDR Bit Descriptions
Bit
Reset
INIT_ADDR
31–0
0
12.8.17
Description
Initialization Address
Provides the address used for the data to data strobes skew adjustment and automatic
CAS to preamble calibration after setting DDR_SDRAM_CFG[MEM_EN].
This address is written during the initialization sequence.
DDR Initialization Enable (MnDDR_INIT_EN)
DDR_INIT_EN
30
DDR SDRAM Initialization
Enable
Bit
31
Type
Reset
UIA
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Type
Reset
Settings
29
28
27
26
25
24
23
Offset 0x014C
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
—
R
0
0
0
0
0
0
0
0
The DDR SDRAM initialization enable register provides the enable bit to use the address given
by DDR_INIT_ADDR[INIT_ADDR] for the data to data strobes deskew calibration and for
automatic CAS to preamble calibration during the DDR SDRAM initialization. Table 12-38
describes the DDR_INIT_EN fields.
Table 12-38. DDR_INIT_EN Field Descriptions
Bit
Reset
UIA
31
0
—
30–0
0
Description
Use Initialization Address
Indicates whether to use the initialization address.
Settings
0
Use the default address for training
sequence as calculated by the
controller. This is the first valid
address in the first enabled chip
select.
1
Use the initialization address
programmed in DDR_INIT_ADDR.
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-77
DDR SDRAM Memory Controller
12.8.18
DDR SDRAM Timing Configuration 4 (MnTIMING_CFG_4)
TIMING_CFG_4
Bit
31
30
DDR SDRAM Timing Con figuration 4
29
28
27
26
RWT
25
24
23
22
WRT
21
Offset 0x0160
20
19
18
RRT
17
16
WWT
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
Type
Reset
DLL_LOCK
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DDR SDRAM timing configuration 4 register provides additional timing fields required to
support DDR3 memories. Table 12-39 describes the TIMING_CFG_4 fields.
Table 12-39. TIMING_CFG_4 Field Descriptions
Bits
Reset
Description
Settings
RWT
31–28
0
Read-to-Write Turnaround for Same Chip Select
Specifies how many cycles are added between a read to write
turnaround for transactions to the same chip select. If a value of 0000
is chosen, then the DDR controller uses the value used for
transactions to different chip selects, as defined in
TIMING_CFG_0[RWT]. This field can be used to improve performance
when operating in burst-chop mode by forcing transactions to the
same chip select to use extra cycles, while transaction to different chip
selects can utilize the tri-state time on the DRAM interface. Regardless
of the value that is set in this field, the value defined by
TIMING_CFG_0[RWT] is also met before issuing a write command.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Default
1 clock
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
9 clocks
10 clocks
11 clocks
12 clocks
13 clocks
14 clocks
15 clocks
WRT
27–24
0
Write-to-Read Turnaround for Same Chip Select
Specifies how many cycles are added between a write to read
turnaround for transactions to the same chip select. If a value of 0000
is chosen, then the DDR controller uses the value used for
transactions to different chip selects, as defined in
TIMING_CFG_0[WRT]. This field can be used to improve performance
when operating in burst-chop mode by forcing transactions to the
same chip select to use extra cycles, while transaction to different chip
selects can utilize the tri-state time on the DRAM interface. Regardless
of the value that is set in this field, the value defined by
TIMING_CFG_0[WRT] is also met before issuing a read command.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Default
1 clock
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
9 clocks
10 clocks
11 clocks
12 clocks
13 clocks
14 clocks
15 clocks
MSC8156 Reference Manual, Rev. 2
12-78
Freescale Semiconductor
Memory Controller Programming Model
Table 12-39. TIMING_CFG_4 Field Descriptions (Continued)
Bits
Reset
Description
Settings
RRT
23–20
0
Read-to-Read Turnaround for Same Chip Select
Specifies how many cycles are added between reads to the same
chip select. If a value of 0000 is chosen, then 2 cycles is required
between read commands to the same chip select if 4-beat bursts are
used (4 cycles are required if 8-beat bursts are used). Note that DDR3
does not support 4-beat bursts. However, this field may be used to
add extra cycles when burst-chop mode is used, and the DDR
controller must wait 4 cycles for read-to-read transactions to the same
chip select.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BL/2 clocks
BL/2 + 1 clock
BL/2 + 2 clocks
BL/2 + 3 clocks
BL/2 + 4 clocks
BL/2 + 5 clocks
BL/2 + 6 clocks
BL/2 + 7 clocks
BL/2 + 8 clocks
BL/2 + 9 clocks
BL/2 + 10 clocks
BL/2 + 11 clocks
BL/2 + 12 clocks
BL/2 + 13 clocks
BL/2 + 14 clocks
BL/2 + 15 clocks
WWT
19–16
0
Write-to-Write Turnaround for Same Chip Select
Specifies how many cycles are added between writes to the same chip
select. If a value of 0000 is chosen, then 2 cycles is required between
write commands to the same chip select if 4-beat bursts are used (4
cycles are required if 8-beat bursts are used). Note that DDR3 does not
support 4-beat bursts. However, this field may be used to add extra
cycles when burst-chop mode is used, and the DDR controller must
wait 4 cycles for write-to-write transactions to the same chip select.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
BL/2 clocks
BL/2 + 1 clock
BL/2 + 2 clocks
BL/2 + 3 clocks
BL/2 + 4 clocks
BL/2 + 5 clocks
BL/2 + 6 clocks
BL/2 + 7 clocks
BL/2 + 8 clocks
BL/2 + 9 clocks
BL/2 + 10 clocks
BL/2 + 11 clocks
BL/2 + 12 clocks
BL/2 + 13 clocks
BL/2 + 14 clocks
BL/2 + 15 clocks
—
15–2
0
Reserved. Write to zero for future compatibility.
DLL_LOCK
1–0
0
DDR SDRAM DLL Lock Time
This provides the number of cycles that it takes for the DRAMs DLL to
lock at power-on reset and after exiting self refresh. The controller
waits the specified number of cycles before issuing any commands
after exiting POR or self refresh.
00
01
10
11
200 clocks
512 clocks
Reserved
Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-79
DDR SDRAM Memory Controller
12.8.19
DDR SDRAM Timing Configuration 5 (MnTIMING_CFG_5)
TIMING_CFG_5
Bit
31
30
DDR SDRAM Timing Con figuration 5
29
28
27
—
Type
Reset
0
Bit
15
25
24
23
22
—
21
20
19
RODT_OFF
18
17
16
WODT
_ON
—
R/W
0
0
0
0
0
14
13
12
11
10
WODT_ON
Type
Reset
26
RODT_ON
Offset 0x0164
—
0
0
0
0
0
0
9
8
7
6
5
4
WODT_OFF
0
0
0
0
3
2
1
0
0
0
0
0
—
R/W
0
0
0
0
0
0
0
0
0
0
0
0
The DDR SDRAM timing configuration 5 register provides additional timing fields required to
support DDR3 memories. Table 12-40 describes the TIMING_CFG_5 fields.
Table 12-40. TIMING_CFG_5 Field Descriptions
Bits
Reset
Description
—
31–29
0
Reserved. Write to zero for future compatibility.
RODT_ON
28–24
0
Read-to-ODT On
Specifies the number of cycles that passes from when a read command is
placed on the DRAM bus until the assertion of the relevant ODT signal(s).
The default case (00000) provides a decode of RL - 3 cycles to support
legacy of past products. RL is the read latency, derived from CAS latency
+ additive latency. If 2T/3T timing is used, one/two extra cycles are
automatically added to the value selected in this field.
Settings
00000 RL - 3 clocks
00001 0 clocks
00010 1 clocks
00011 2 clocks
00100 3 clocks
00101 4 clocks
00110 5 clocks
00111 6 clocks
01000 7 clocks
01001 8 clocks
01010 9 clocks
01011 10 clocks
01100 11 clocks
01101 12 clocks
01110 13 clocks.
011111 14 clocks
10000 15 clocks
10001 16 clocks
10010 17 clocks
10011 18 clocks
10100 19 clocks
10101 20 clocks
10110 21 clocks
10111 22 clocks
11000 23 clocks
11001 24 clocks
11010 25 clocks
11011 26 clocks
11100 27 clocks
11101 28 clocks
11110 29 clocks.
11111 30 clocks
MSC8156 Reference Manual, Rev. 2
12-80
Freescale Semiconductor
Memory Controller Programming Model
Table 12-40. TIMING_CFG_5 Field Descriptions (Continued)
Bits
Reset
Description
—
23
0
Reserved. Write to zero for future compatibility.
RODT_OFF
22–20
0
Read to ODT Off
Specifies the number of cycles that the relevant ODT signal(s) remains
asserted for each read transaction. The default case (000) leaves the ODT
signal(s) asserted for 3 DRAM cycles.
—
19–17
0
Reserved. Write to zero for future compatibility.
WODT_ON
16–12
0
Write-to-ODT On
Specifies the number of cycles that passes from when a write command is
placed on the DRAM bus until the assertion of the relevant ODT signal(s).
The default case (00000) provides a decode of WL - 3 cycles to support
legacy of past products. WL is the write latency, derived from Write Latency
+ Additive Latency. If 2T/3T timing is used, one/two extra cycles are
automatically added to the value selected in this field.
—
11
0
Reserved. Write to zero for future compatibility.
Settings
000
001
010
010
100
101
110
111
3 clocks
1 clock
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
00000 WL - 3 clocks
00001 0 clocks
00010 1 clocks
00011 2 clocks
00100 3 clocks
00101 4 clocks
00110 5 clocks
00111 6 clocks
01000 7 clocks
01001 8 clocks
01010 9 clocks
01011 10 clocks
01100 11 clocks
01101 12 clocks
01110 13 clocks.
011111 14 clocks
10000 15 clocks
10001 16 clocks
10010 17 clocks
10011 18 clocks
10100 19 clocks
10101 20 clocks
10110 21 clocks
10111 22 clocks
11000 23 clocks
11001 24 clocks
11010 25 clocks
11011 26 clocks
11100 27 clocks
11101 28 clocks
11110 29 clocks.
11111 30 clocks
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-81
DDR SDRAM Memory Controller
Table 12-40. TIMING_CFG_5 Field Descriptions (Continued)
Bits
Reset
Description
WODT_
OFF
10–8
0
Write to ODT Off
Specifies the number of cycles that the relevant ODT signal(s) remains
asserted for each write transaction. The default case (000) leaves the ODT
signal(s) asserted for 3 DRAM cycles.
—
7–0
0
Reserved. Write to zero for future compatibility.
12.8.20
31
000
001
010
010
100
101
110
111
3 clocks
1 clock
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
DDR ZQ Calibration Control (MnDDR_ZQ_CNTL)
DDR_ZQ_ CNTL
Bit
Settings
30
DDR ZQ Calibration Control
29
ZQ_
EN
28
27
26
25
24
23
22
ZQINIT
—
Offset 0x0170
21
20
19
—
18
17
16
ZQOPER
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
—
Type
Reset
ZQCS
—
R/W
0
0
0
0
0
0
0
0
0
0
0
0
The DDR ZQ Calibration Control register provides the enable and controls required for ZQ
calibration when using DDR3 SDRAM devices. There is a limitation for various DRAM timing
parameters when ZQ calibration is used. The factors involved in this limitation are
DDR_ZQ_CNTL[ZQOPER], DDR_ZQ_CNTL[ZQCS], TIMING_CFG_1[PRETOACT],
TIMING_CFG_1[REFREC], DDR_SDRAM_INTERVAL[REFINT], and the number of chip
selects enabled. If the following condition is true:
[((DDR_ZQ_CNTL[ZQOPER] + DDR_ZQ_CNTL[ZQCS])* (# enabled chip selects)) +
TIMING_CFG_1[PRETOACT] + TIMING_CFG_1[REFREC] + 2tCK] > (DDR_SDRAM_INTERVAL[REFINT])
it is possible that one refresh is skipped when the controller exits self refresh. If this is an issue,
then posted refreshes can be used to extend the refresh interval. Another alternative is to use the
DDR_SDRAM_MD_CNTL register to force an extra refresh to each chip select after exiting self
refresh mode. However, DDR3 timing parameters for most devices/frequencies do not allow
missed refresh cycles. Table 12-41 describes the DDR_ZQ_CNTL fields.
MSC8156 Reference Manual, Rev. 2
12-82
Freescale Semiconductor
Memory Controller Programming Model
Table 12-41. DDR_ZQ_CNTL Field Descriptions
Bit
Reset
Description
ZQ_EN
31
0
ZQ Calibration Enable
This bit determines whether ZQ calibration is used.
This bit should be set only if DDR3 memory is used
(DDR_SDRAM_CFG[SDRAM_TYPE] = 0b111).
—
30–28
ZQ_INIT
27–24
0
Reserved. Write to zero for future compatibility.
0
Power-on Reset ZQ Calibration Time (tZQinit)
Determines the number of cycles that must be
allowed for DRAM ZQ calibration at power-on reset.
Each chip select is calibrated separately, and this
time must elapse after the ZQCL command is
issued for each chip select before a separate
command can be issued.
Reserved. Write to zero for future compatibility.
0111
128 clocks
1000
256 clocks
1001
512 clocks
1010
1024 clocks
Normal Operation Full Calibration Time (tZQoper)
Determines the number of cycles that must be
allowed for DRAM ZQ calibration when exiting self
refresh. Each chip select is calibrated separately,
and this time must elapse after the ZQCL command
is issued for each chip select before a separate
command may be issued.
Reserved. Write to zero for future compatibility.
0111
128 clocks
1000
256 clocks
1001
512 clocks
1010
1024 clocks
Normal Operation Short Calibration Time (tZQCS)
Determines the number of cycles that must be
allowed for DRAM ZQ calibration during dynamic
calibration which is issued every 32 refresh cycles.
Each chip select is calibrated separately, and this
time must elapse after the ZQCS command is
issued for each chip select before a separate
command may be issued.
0000
1 clocks
0001
2 clocks
0010
4 clocks
0011
8 clocks
0100
16 clocks
0101
32 clocks
—
23–20
ZQOPER
19–16
—
15–12
ZQCS
11–8
0
0
0
0
Settings
0
ZQ Calibration is not used.
1
ZQ Calibration is used. A ZQCL
command is issued by the DDR
controller after power-on reset and
anytime the DDR controller exits
self refresh. A ZQCS command is
issued every 32 refresh
sequences to account for VT
variations.
All other values reserved.
All other values reserved.
0110
64 clocks
0111
128 clocks
1000
256 clocks
1001
512 clocks
All other values reserved.
—
7–0
0
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-83
DDR SDRAM Memory Controller
12.8.21
DDR Write Leveling Control (MnDDR_WRLVL_CNTL)
DDR_WRLVL_CNTL
Bit
31
30
DDR Write Leveling Control
29
28
27
26
25
24
23
WRLVL_MRD
—
WRLVL
_EN
22
Offset 0x0174
19
18
—
WRLVL_ODTEN
21
20
—
WRLVL_DQSEN
17
16
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRLVL_SMPL
Type
Reset
—
WRLVL_WLR
—
WRLVL_START
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DDR Write Leveling Control register provides controls for write leveling, as it is supported
for DDR3 memory devices. Table 12-42 describes the DDR_WRLVL_CNTL fields.
Table 12-42. DDR_WRLVL_CNTL Field Descriptions
Bits
Reset
WRLVL_EN
31
0
Description
Write Leveling Enable
This bit determines if write leveling is used. If this bit is set, then the
DDR controller performs write leveling immediately after initializing
the DRAM. This bit should only be set if DDR3 memory is used
(DDR_SDRAM_CFG[SDRAM_TYPE] = 3’b111). In addition, write
leveling is not supported for DDR3 mirrored DIMMs.
—
30–27
0
Reserved. Write to zero for future compatibility.
WRLVL_
MRD
26–24
0
First DQS Pulse Rising Edge after Margining Mode Is
Programmed (tWL_MRD)
Determines how many cycles to wait after margining mode has been
programmed before the first DQS pulse may be issued. This field is
only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
—
23
0
Reserved. Write to zero for future compatibility.
WRLVL_
ODTEN
22–20
0
ODT Delay after Margining Mode Is Programmed (tWL_ODTEN)
Determines how many cycles to wait after margining mode is
programmed.until ODT is asserted.This field is only relevant when
DDR_WRLVL_CNTL[WRLVL_EN] is set.
—
19
0
Reserved. Write to zero for future compatibility.
Settings
0
Write leveling is not
used
1
Write leveling is used
000
001
010
011
100
101
110
111
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
000
001
010
011
100
101
110
111
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
MSC8156 Reference Manual, Rev. 2
12-84
Freescale Semiconductor
Memory Controller Programming Model
Table 12-42. DDR_WRLVL_CNTL Field Descriptions (Continued)
Bits
Reset
Description
WRLVL_
DQSEN
18–16
0
DQS/DQS Delay after Margining Mode Is Programmed
(tWL_DQSEN)
Determines how many cycles to wait after margining mode has been
programmed until DQS may be actively driven. This field is only
relevant when DDR_WRLVL_CNTL[WRLVL_EN] is set.
000
001
010
011
100
101
110
111
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
WRLVL_
SMPL
15–12
0
Write Leveling Sample Time
Determines the number of cycles that must pass before the data
signals are sampled after a DQS pulse during margining mode. This
field should be programmed at least 6 cycles higher than tWLO to allow
enough time for propagation delay and sampling of the prime data bits.
This field is only relevant when DDR_WRLVL_CNTL[WRLVL_EN] is
set.
0000
0001
0010
0011
0100
0101
1010
0111
1000
1001
1010
1011
1100
1101
1010
1111
Reserved
(if DDR_
WRLVL_CNTL[WRL
VL_EN] is set)
1 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
9 clocks
10 clocks
11 clocks
12 clocks
13 clocks
14 clocks
15 clocks
000
001
010
011
100
101
110
111
1 clocks
2 clocks
4 clocks
8 clocks
16 clocks
32 clocks
64 clocks
128 clocks
—
11
0
Reserved. Write to zero for future compatibility.
WRLVL_
WLR
10–8
0
Write Leveling Repetition Time
Determines the number of cycles that must pass between DQS pulses
during write leveling. This field is only relevant when
DDR_WRLVL_CNTL[WRLVL_EN] is set.
Settings
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-85
DDR SDRAM Memory Controller
Table 12-42. DDR_WRLVL_CNTL Field Descriptions (Continued)
Bits
Reset
Description
—
7–5
0
Reserved. Write to zero for future compatibility.
WRLVL_
START
4–0
0
Write Leveling Start Time
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 0 clock delay
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
12-86
Freescale Semiconductor
Memory Controller Programming Model
12.8.22
DDR Write Leveling Control 2 (MnDDR_WRLVL_CNTL_2)
DDR_WRLVL_CNTL_2
Bit
31
30
29
DDR Write Leveling Control 2
28
27
26
25
24
23
WRLVL_START_1
—
22
Offset 0x0190
21
20
—
19
18
17
16
WRLVL_START_2
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRLVL_START_3
—
Type
Reset
—
WRLVL_START_4
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DDR Write Leveling Control 2 register provides controls for write leveling, as it is supported
for DDR3 memory devices. This register specifically defines the starting points for the individual
data strobes. Table 12-43 describes the DDR_WRLVL_CNTL_2 fields.
Table 12-43. DDR_WRLVL_CNTL_2 Field Descriptions
Bits
Reset
Description
—
31–29
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_1
28–24
0
Write Leveling Start Time for DQS1
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-87
DDR SDRAM Memory Controller
Table 12-43. DDR_WRLVL_CNTL_2 Field Descriptions (Continued)
Bits
Reset
Description
—
23–21
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_2
20–16
0
Write Leveling Start Time for DQS2
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
—
15–13
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_3
12–8
0
Write Leveling Start Time for DQS3
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
12-88
Freescale Semiconductor
Memory Controller Programming Model
Table 12-43. DDR_WRLVL_CNTL_2 Field Descriptions (Continued)
Bits
Reset
Description
—
7–5
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_4
4–0
0
Write Leveling Start Time for DQS4
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-89
DDR SDRAM Memory Controller
12.8.23
DDR Write Leveling Control 3 (MnDDR_WRLVL_CNTL_3)
DDR_WRLVL_CNTL_3
Bit
31
30
29
DDR Write Leveling Control 3
28
27
26
25
24
23
WRLVL_START_5
—
22
Offset 0x0194
21
20
—
19
18
17
16
WRLVL_START_6
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WRLVL_START_7
—
Type
Reset
—
WRLVL_START_8
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The DDR Write Leveling Control 3 register provides controls for write leveling, as it is supported
for DDR3 memory devices. This register specifically defines the starting points for the individual
data strobes. Table 12-43 describes the DDR_WRLVL_CNTL_3 fields.
Table 12-44. DDR_WRLVL_CNTL_3 Field Descriptions
Bits
Reset
Description
—
31–29
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_5
28–24
0
Write Leveling Start Time for DQS5
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
—
23–21
0
Reserved. Write to zero for future compatibility.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
12-90
Freescale Semiconductor
Memory Controller Programming Model
Table 12-44. DDR_WRLVL_CNTL_3 Field Descriptions (Continued)
Bits
Reset
Description
WRLVL_
START_6
20–16
0
Write Leveling Start Time for DQS6
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
—
15–13
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_7
12–8
0
Write Leveling Start Time for DQS7
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-91
DDR SDRAM Memory Controller
Table 12-44. DDR_WRLVL_CNTL_3 Field Descriptions (Continued)
Bits
Reset
Description
—
7–5
0
Reserved. Write to zero for future compatibility.
WRLVL_
START_8
4–0
0
Write Leveling Start Time for DQS8
Determines the value to use for the DQS_ADJUST for the first
sample when write leveling is enabled.
Settings
00000 Use value from
DDR_WRLVL_CNTL
[WRLVL_START]
00001 1/8 clock delay
00010 1/4 clock delay
00011 3/8 clock delay
00100 1/2 clock delay
00101 5/8 clock delay
00110 3/4 clock delay
00111 7/8 clock delay
01000 1 clock delay
01001 9/8 clock delay
01010 5/4 clock delay
01011 11/8 clock delay
01100 3/2 clock delay
01101 13/8 clock delay
01110 7/4 clock delay
01111 15/8 clock delay
10000 2 clock delay
10001 17/8 clock delay
10010 9/4 clock delay
10011 19/8 clock delay
10100 5/2 clock delay
10101–
11111 Reserved
MSC8156 Reference Manual, Rev. 2
12-92
Freescale Semiconductor
Memory Controller Programming Model
12.8.24
DDR Pre-Drive Conditioning Control (MnDDR_PD_CNTL)
DDR_PD_CNTL
Bit
31
30
DDR Pre_Drive Conditioning Control
29
28
27
26
25
24
0
6
—
23
Type
Reset
0
0
0
0
0
0
0
PDAR
R/W
0
0
Bit
15
14
13
12
11
10
9
8
TVPD
PD_EN
PDAW
Type
Reset
0
0
0
—
0
0
0
0
7
PD_ON
R/W
0
0
22
Offset 0x0178
21
20
19
18
16
0
0
0
0
0
0
5
4
3
2
1
0
0
0
PD_OFF
—
0
17
PDAW
—
0
0
0
0
The DDR Pre-Drive Conditioning Control register provides controls for asserting termination at
the on-chip I/Os prior to driving DQS/DQ for write commands. Table 12-45 describes the
DDR_PD_CNTL fields.
Table 12-45. DDR_PD_CNTL Field Descriptions
Bits
Reset
PD_EN
31
0
Description
0
Pre-Drive Conditioning Enable
This bit determines whether termination is asserted to the
on-chip I/Os prior to write commands. This helps bring DRAM/IO 1
terminated signals near VREF before driving an active preamble.
The result is a more symmetrical eye with less overshoot on the
first rising edge of these signals.
TVPD
30–28
0
Termination Value During Pre-drive Conditioning
This represents the value of the termination that is used during
pre-drive conditioning.
—
27
0
Reserved. Write to zero for future compatibility.
PDAR
26–20
0
Pre-Drive After Read
If pre-drive conditioning is enabled, it may not be desirable to
assert termination to the on-chip IOs immediately after a prior
read. This field represents the number of cycles that must pass
after a previous read is issue before pre-drive conditioning is
available for a future write. Note that the decision to use pre-drive
conditioning is made at the time the write command is issued.
—
19
0
Settings
000
001
010
011
100
101
110
111
Pre-drive conditioning is not
used
Pre-drive conditioning is used
75 ohms
60 ohms
150 ohms
120 ohms
46 ohms
43 ohms
33 ohms
Reserved
0000000
0000001
0000010
...
1111111
0 clocks
1 clocks
2 clocks
127 clocks
Note: The value represents the
actual number of clocks to use
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-93
DDR SDRAM Memory Controller
Table 12-45. DDR_PD_CNTL Field Descriptions (Continued)
Bits
Reset
Description
PDAW
18–12
0
Pre-Drive After Write
If pre-drive conditioning is enabled, it may not be desirable to
assert termination to the on-chip IOs immediately after a prior
write. This field represents the number of cycles that must pass
after a previous write is issue before pre-drive conditioning is
available for a future write. Note that the decision to use pre-drive
conditioning is made at the time the write command is issued.
—
11
0
Reserved. Write to zero for future compatibility.
PD_ON
10–6
0
Pre-Drive Conditioning On
Specifies the number of cycles that passes from when a write
command is placed on the DRAM bus until the assertion of
termination at the on-chip IOs. Note that
DDR_PD_CNTL[PD_ON] + DDR_PD_CNTL[PD_OFF} should
not be greater than 31.
Settings
0000000
0000001
0000010
...
1111111
0 clocks
1 clocks
2 clocks
127 clocks
Note: The value represents the
actual number of clocks to use
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Reserved
1 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
9 clocks
10 clocks
11 clocks
12 clocks
13 clocks
14 clocks
15 clocks
16 clocks
17 clocks
18 clocks
19 clocks
20 clocks
21 clocks
22 clocks
23 clocks
24 clocks
25 clocks
26 clocks
27 clocks
28 clocks
29 clocks
30 clocks
31 clocks
MSC8156 Reference Manual, Rev. 2
12-94
Freescale Semiconductor
Memory Controller Programming Model
Table 12-45. DDR_PD_CNTL Field Descriptions (Continued)
Bits
Reset
Description
—
5
0
Reserved. Write to zero for future compatibility.
PD_OFF
4–0
0
Pre-Drive Conditioning Off
Specifies the number of cycles that the termination at the on-chip
IOs remains asserted prior to a write transaction. Note that
DDR_PD_CNTL[PD_ON] + DDR_PD_CNTL[PD_OFF} should
note be greater than 31.
Settings
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Reserved
1 clocks
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks
8 clocks
9 clocks
10 clocks
11 clocks
12 clocks
13 clocks
14 clocks
15 clocks
16 clocks
17 clocks
18 clocks
19 clocks
20 clocks
21 clocks
22 clocks
23 clocks
24 clocks
25 clocks
26 clocks
27 clocks
28 clocks
29 clocks
30 clocks
31 clocks
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-95
DDR SDRAM Memory Controller
12.8.25
DDR Self Refresh Counter (MnDDR_SR_CNTR)
DDR_SR_CNTR
Bit
31
30
DDR Self Refresh Counter
29
28
27
26
25
24
23
22
Offset 0x017C
21
20
19
18
—
17
16
SR_IT
Type
Reset
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
R/W
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
R
Type
Reset
0
0
0
0
0
0
0
0
DDR_SR_CNTR can be programmed to force the DDR controller to enter self refresh after a
predefined period of idle time.
Table 12-46. DDR_SR_CNTR Bit Descriptions
Bit
Reset
Description
—
31–20
SR_IT
19–16
0
Reserved. Write to zero for future compatibility.
0
Self Refresh Idle Threshold
Defines the number of DRAM cycles that must pass
while the DDR controller is idle before it enters self
refresh. Anytime a transaction is issued to the DDR
controller, it resets its internal counter. When a new
transaction is received by the DDR controller, it exits
self refresh and reset its internal counter. If this field
is zero, then the described power savings feature is
disabled. In addition, if a non-zero value is
programmed into this field, then the DDR controller
exits self refresh anytime a transaction is issued to
the DDR controller, regardless of the reason self
refresh was initially entered.
—
15–0
0
Reserved. Write to zero for future compatibility.
Settings
0000
Automatic self refresh
entry disabled
0001
210 DRAM clocks
0010
212 DRAM clocks
0011
214 DRAM clocks
0100
216 DRAM clocks
0101
218 DRAM clocks
0110
220 DRAM clocks
0111
222 DRAM clocks
1000
224 DRAM clocks
1001
226 DRAM clocks
1010
228 DRAM clocks
1011
230 DRAM clocks
1100-1111 Reserved
MSC8156 Reference Manual, Rev. 2
12-96
Freescale Semiconductor
Memory Controller Programming Model
12.8.26
DDR SDRAM Register Control Words 1 (MnDDR_SDRAM_RCW_1)
DDR_SDRAM_RCW_1
Bit
31
30
29
DDR SDRAM Register Control Word 1
28
27
RCW0
26
25
24
23
RCW1
22
21
Offset 0x0180
20
19
RCW2
18
17
16
RCW3
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCW4
Type
Reset
RCW5
RCW6
RCW7
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDR_SDRAM_RCW_1 should be programmed with the intended values of the register control
words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is
placed on MA3, MA4, MBA0, and MBA1 during register control word writes.
Table 12-47. DDR_SDRAM_RCW_1 Bit Descriptions
Bit
Reset
Description
RCW0
31–28
0
RCW1
27–24
0
RCW2
23–20
0
RCW3
19–16
0
RCW4
15–12
0
RCW5
11–8
0
RCW6
7–4
0
RCW7
3–0
0
Register Control Word 0
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 0.
Register Control Word 1
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 1.
Register Control Word 2
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 2.
Register Control Word 3
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 3.
Register Control Word 4
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 4.
Register Control Word 5
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 5.
Register Control Word 6
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 6.
Register Control Word 7
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 7.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-97
DDR SDRAM Memory Controller
12.8.27
DDR SDRAM Register Control Words 2 (MnDDR_SDRAM_RCW_2)
DDR_SDRAM_RCW_2
Bit
31
30
29
DDR SDRAM Register Control Word 2
28
27
RCW8
26
25
24
23
RCW9
22
21
Offset 0x0184
20
19
RCW10
18
17
16
RCW11
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RCW12
Type
Reset
RCW13
RCW14
RCW15
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDR_SDRAM_RCW_2 should be programmed with the intended values of the register control
words if DDR_SDRAM_CFG[RCW_EN] is set. Each 4-bit field represents the value that is
placed on MA3, MA4, MBA0, and MBA1 during register control word writes.
Table 12-48. DDR_SDRAM_RCW_2 Bit Descriptions
Bit
Reset
Description
RCW8
31–28
0
RCW9
27–24
0
RCW10
23–20
0
RCW11
19–16
0
RCW12
15–12
0
RCW13
11–8
0
RCW14
7–4
0
RCW15
3–0
0
Register Control Word 8
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 8.
Register Control Word 9
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 9.
Register Control Word 10
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 10.
Register Control Word 11
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 11.
Register Control Word 12
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 12.
Register Control Word 13
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 13.
Register Control Word 14
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 14.
Register Control Word 15
Represents the value that is placed on MBA[1], MBA[0], MA[4], and MA[3] during writes
to register control word 15.
MSC8156 Reference Manual, Rev. 2
12-98
Freescale Semiconductor
Memory Controller Programming Model
12.8.28
DDR Debug Status Register 1 (MnDDRDSR_1)
DDRDSR_1
Bit
31
DDR Debug Status Register 1
30
29
DDRDC
28
27
26
23
25
24
0
0
0
6
5
4
Type
Reset
0
0
0
0
0
0
0
MDICNZ
R
0
0
Bit
15
14
13
12
11
10
9
8
MDICPZ
CPZ
Type
Reset
22
Offset 0x0B20
21
20
19
18
17
16
0
0
0
0
3
2
1
0
0
0
—
7
CNZ
DPZ
DNZ
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRDSR_1 contains the DDR driver compensation input value and the current settings of the P
and N FET impedance for MDICn, command/control, and data. Note: This register is read only
Table 12-49. DDRDSR_1 Bit Descriptions
Bit
Reset
Description
DDRDC
31–30
MDICPZ
29–26
MDICNZ
25–22
—
21–16
CPZ
15–12
CNZ
11–8
DPZ
7–4
DNZ
3–0
0
DDR Driver Compensation Input Value
0
Current Setting of PFET Driver MDIC Impedance
0
Current Setting of NFET Driver MDIC Impedance
0
Reserved. Always read as zero
0
Current Setting of PFET Driver Command Impedance
0
Current Setting of NFET Driver Command Impedance
0
Current Setting of PFET Driver Data Impedance
0
Current Setting of NFET Driver Data Impedance
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-99
DDR SDRAM Memory Controller
12.8.29
DDR Debug Status Register 2 (MnDDRDSR_2)
DDRDSR_2
Bit
31
DDR Debug Status Register 2
30
29
28
27
26
CLKPZ
25
24
23
22
Offset 0x0B24
21
20
CLKNZ
19
18
17
16
—
Type
Reset
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
—
R
Type
Reset
0
0
0
0
0
0
0
0
DDRDSR_2 contains the current settings of the P and N FET impedance for the DDR drivers for
clocks. Note: This register is read only
Table 12-50. DDRDSR_2 Bit Descriptions
Bit
Reset
CLKPZ
31–28
CLKNZ
27–24
—
23–0
0
Current Setting of PFET Driver Clock Impedance
0
Current Setting of NFET Driver Clock Impedance
0
Reserved. Always read as zero
12.8.30
Description
DDR Control Driver Register 1 (MnDDRCDR_1)
DDRCDR_1
Bit
31
DDR Control Driver Register 1
30
29
DHC_ DSO_
EN MDIC_
EN
28
27
26
25
DSO_MDICPZ
24
23
22
DSO_MDICNZ
Offset 0x0B28
21
20
19
DSO_ DSO_
MDIC_ MDIC_
PZ_OE NZ_OE
18
17
16
DSO_ DSO_
C_EN D_EN
ODT
Type
Reset
0
0
0
0
0
0
0
0
R/W
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DSO_CPZ
Type
Reset
DSO_CNZ
DSO_DPZ
DSO_DNZ
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DDRCDR_1 sets the driver hardware compensation enable, the DDR MDIC driver P/N
impedance, ODT termination value for IOs, driver software override enable for MDIC, driver
software override enable for address/command, driver software override enable for data, the
DDR address/command driver P/N impedance, and the DDR data driver P/N impedance.
MSC8156 Reference Manual, Rev. 2
12-100
Freescale Semiconductor
Memory Controller Programming Model
Table 12-51. DDRCDR_1 Bit Descriptions
Bit
Reset
DHC_EN
31
DSO_MDIC_
EN
30
0
DDR Driver Hardware Compensation Enable
0
Driver Software Override Enable for MDIC
DSO_MDICPZ
29–26
DSO_
MDICNZ
25–22
DSO_MDIC_
PZ_OE
21
DSO_MDIC_
NZ_OE
20
ODT
19–18
0
Driver Software Override Value for MDIC
P-Impedance
Driver Software Override Value for MDIC
N-Impedance
DSO_C_EN
17
DSO_D_EN
16
DSO_CPZ
15–12
DSO_CNZ
11–8
DSO_DPZ
7–4
DSO_DNZ
3–0
0
0
0
0
0
0
0
0
0
0
Description
Driver Software Override Output Enable for
P-Impedance This field is effective only if DSO_MDIC_EN is set
Driver Software Override Output Enable for
N-Impedance This field is effective only if DSO_MDIC_EN is set
ODT Termination Value for I/Os
This is combined with DDRCDR_2[ODT] to
determine the termination value.
The termination value is based on concatenating
these 2 fields (DDRCDR_1[ODT]|DDRCDR_2[ODT])
Driver Software Override Enable for
Address/Command
Driver Software Override Enable for Data
Settings
0 Hardware compensation disabled.
1 Hardware compensation enabled.
0 Software override for MDIC
disabled.
1 Software override for MDIC
enabled.
0 Output disabled.
1 Output enabled.
0 Output disabled.
1 Output enabled.
000
75 ohm (JEDEC DDR2)
001
55 ohm
010
60 ohm (JEDEC DDR3)
011
50 ohm (JEDEC DDR2)
100
150 ohm (JEDEC DDR2)
101
43 ohm
110
120 ohm (JEDEC DDR3)
111 Reserved
0 Override disabled.
1 Override enabled.
0 Override disabled.
1 Override enabled.
DDR Driver Software Override Value for
Command P-Impedance Override.
DDR Driver Software Override Value for
Command N-Impedance Override.
DDR Driver Software Override Value for Data
P-Impedance Override.
DDR Driver Software Override Value for Data
N-Impedance Override.
The fields in DDRCDR_1, other than DDRCDR_1[ODT], are used to enable driver calibration
with the MDIC[0–1] pins. This can be used to calibrate the DDR drivers to 18 ohms. However,
this should only be used for full-strength driver applications. If half strength is desired, then this
calibration should remain disabled. The hardware DDR driver calibration is enabled via
DDRCDR_1[DHC_EN].
Note:
All Driver Calibration setting, either software or hardware, should be set before
DDR_SDRAM_CFG[MEM_EN] is set.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-101
DDR SDRAM Memory Controller
Software can be used to calibrate the drivers instead of the automatic hardware calibration. If
software calibration is used, the following steps should be taken:
1.
Set DDRCDR_1[DSO_MDIC_EN] and ensure that DDRCDR_1[DHC_EN] is cleared
2.
Set the highest impedance (value 0000) for DDRCDR_1[DSO_MDICPZ]
3.
Set DDRCDR_1[DSO_MDIC_PZ_OE] to enable the output enable for MDIC[0]
4.
After at least 4 cycles, read DDRDSR_1[0]. If the value is 0, then use the next lowest
impedance, and read DDRDSR_1[0] again. Once a value of 1 is detected, then leave
DDRCDR_1[DSO_MDICPZ] at the calibrated value
5.
Clear DDRCDR_1[DSO_MDIC_PZ_OE]
6.
After DDRCDR_1[DSO_MDICPZ} is calibrated, set a value of 0000 for
DDRCDR_1[DSO_MDICNZ]
7.
Set DDRCDR_1[DSO_MDIC_NZ_OE] to enable the output enable for MDIC[1]
8.
After at least 4 cycles, read DDRDSR_1[1]. If the value is 1, then use the next lowest
impedance, and read DDRDSR_1[1] again. Once a value of 0 is detected, then leave
DDRCDR_1[DSO_MDICNZ] at the calibrated value
9.
Clear DDRCDR_1[DSO_MDIC_NZ_OE]
The legal impedance values (from highest impedance to lowest impedance) for DDR2 (1.8 V)
are:
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
0000 lowest strength/highest impedance
0001
0011
0010
0110
0111 half strength - used when driver calibration is not used by setting
DDR_SDRAM_CFG[HSE]
0101
0100
1100
1101
1111
1110
1010
1011 full strength (default)
1001
1000 highest strength/lowest impedance
MSC8156 Reference Manual, Rev. 2
12-102
Freescale Semiconductor
Memory Controller Programming Model
The legal impedance values (from highest impedance to lowest impedance) for DDR3 (1.5 V)
are:
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
„
Note:
0000 lowest strength/highest impedance
0001
0011
0010
0110
0111 half strength - used when driver calibration is not used by setting
DDR_SDRAM_CFG[HSE]
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000 highest strength/lowest impedance (default)
Drivers may either be calibrated to full-strength or half-strength
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-103
DDR SDRAM Memory Controller
12.8.31
DDR Control Driver Register 2 (MnDDRCDR_2)
DDRCDR_2
Bit
31
DSO_
CLK_
EN
Type R/W
Reset
0
Bit
15
Type
Reset
0
DDR Control Driver Register 2
30
29
28
27
26
25
24
23
DSO_CLKPZ
—
22
Offset 0x0B2C
21
20
19
18
DSO_CLKNZ
17
16
—
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
—
R
0
0
ODT
R/W
0
0
0
R/W
0
0
0
R
0
0
0
0
0
0
DDRCDR_2 sets the driver software override enable for clocks, and the DDR clocks driver P/N
impedance.
Table 12-52. DDRCDR_2 Bit Descriptions
Bit
Reset
DSO_CLK_
EN
31
—
30–28
DSO_CLKPZ
27–24
DSO_CLKNZ
23–20
—
19–1
ODT
0
0
Driver Software Override Enable for Clocks
0
Reserved. Write to zero for future compatibility.
0
DDR Driver Software Override Value for Clocks
P-Impedance Override
DDR Driver Software Override Value for Clocks
N-Impedance Override
Reserved. Write to zero for future compatibility.
0
0
0
Description
ODT Termination Value for I/Os
This is combined with DDRCDR_1[ODT] to
determine the termination value. The termination
value is based on concatenating these 2 fields
(DDRCDR_1[ODT]|DDRCDR_2[ODT]).
Settings
0 Software override disabled.
1 Software override enabled.
000
75 ohm (JEDEC DDR2)
001
55 ohm
010
60 ohm (JEDEC DDR3)
011
50 ohm (JEDEC DDR2)
100
150 ohm (JEDEC DDR2)
101
43 ohm
110
120 ohm (JEDEC DDR3)
111
Reserved
MSC8156 Reference Manual, Rev. 2
12-104
Freescale Semiconductor
Memory Controller Programming Model
12.8.32
DDR SDRAM IP Block Revision 1 Register (MnDDR_IP_REV1)
DDR_IP_REV1
Bit
31
DDR SDRAM IP Block Revision 1 Register
30
29
28
27
26
25
24
23
Offset 0x0BF8
22
21
20
19
18
17
16
IP_ID
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
IP_MJ
Type
Reset
IP_MN
R
0
0
0
0
0
1
0
0
0
0
0
0
0
DDR_IP_REV1 provides read-only fields with the IP block ID, along with major and minor
revision information.
Table 12-53. DDR_IP_REV1 Bit Descriptions
Bit
Reset
IP_ID
31–16
IP_MJ
15–8
IP_MN
7–0
0x0002
12.8.33
Description
0x04
IP Block ID
For the DDR controller.
Major Revision
0x00
Minor Revision
DDR SDRAM IP Block Revision 2 Register (MnDDR_IP_REV2)
DDR_IP_REV2
Bit
31
DDR SDRAM IP Block Revision 2 Register
30
29
28
27
26
25
24
23
22
21
—
Offset 0x0BFC
20
19
18
17
16
IP_INIT
Type
Reset
0
0
0
0
0
0
0
0
R
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
—
Type
Reset
IP_CFG
R
0
0
0
0
0
0
0
0
0
0
0
0
0
DDR_IP_REV2 provides read-only fields with the IP block integration and configuration
options.
Table 12-54. DDR_IP_REV2 Bit Descriptions
Bit
Reset
—
31–24
IP_INT
23–16
0
Reserved. Always read as zero
Description
0
IP Block Integration Options
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-105
DDR SDRAM Memory Controller
Table 12-54. DDR_IP_REV2 Bit Descriptions (Continued)
Bit
Reset
—
15–8
IP_CFG
7–0
0
Reserved. Always read as zero
0
IP Block Configuration Options
12.8.34
Description
DDR SDRAM Memory Data Path Error Injection Mask High Register
(MnDATA_ERR_INJECT_HI)
DATA_ERR_INJECT_HI
Bit
31
30
29
28
DDR SDRAM Memory Data Path
Error Injection Mask High Register
27
26
25
24
23
22
21
Offset 0x0E00
20
19
18
17
16
EIMH
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
EIMH
R/W
Type
Reset
0
0
0
0
0
0
0
0
DATA_ERR_INJECT_HI register is used to inject ECC errors for the 32-msb of a 64-bit
SDRAM data bus interfaces.
Table 12-55. DATA_ERR_INJECT_HI Bit Descriptions
Bit
Reset
Description
EIMH
31–0
0
Error Injection Mask High Data Path
Tests ECC by forcing errors on the highest 32 bits of the data path. When error injection is
enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus
writes.
12.8.35
DDR SDRAM Memory Data Path Error Injection Mask Low Register
(MnDATA_ERR_INJECT_LO)
DATA_ERR_INJECT_LO
Bit
31
30
29
28
DDR SDRAM Memory Data Path
Error Injection Mask Low Register
27
26
25
24
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
EIML
R/W
Type
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Type
Reset
23
Offset 0x0E04
EIML
R/W
0
0
0
0
0
0
0
0
MSC8156 Reference Manual, Rev. 2
12-106
Freescale Semiconductor
Memory Controller Programming Model
DATA_ERR_INJECT_LO register is used to inject ECC errors for the 32-lsb of a 64-bit
SDRAM data bus interfaces.
Table 12-56. DATA_ERR_INJECT_LO Bit Descriptions
Bit
Reset
Description
EIML
31–0
0
Error Injection Mask Low Data Path
Tests ECC by forcing errors on the lowest 32 bits of the data path. When the Error Injection is
enabled, setting a bit causes the corresponding data path bit to be inverted during memory bus
writes.
12.8.36
DDR SDRAM Memory Data Path Error Injection Mask ECC Register
(MnERR_INJECT)
ERR_INJECT
Bit
31
DDR SDRAM Memory Data Path
Error Injection Mask ECC Register
30
29
28
27
26
25
24
0
0
0
0
0
7
6
5
4
Type
Reset
0
0
0
0
0
0
0
—
R
0
Bit
15
14
13
12
11
10
9
8
0
—
R
0
Type
Reset
0
0
23
22
Offset 0x0E08
21
20
EIEN
0
0
0
0
0
0
0
19
18
17
16
0
0
APIEN
R/W
0
3
2
1
0
EEIM
R/W
0
0
0
0
0
ERR_INJECT register sets the ECC mask, enables errors to be written to ECC memory. In
addition, a single address parity error can be injected through this register.
Table 12-57. ERR_INJECT Bit Descriptions
Bit
Reset
Description
—
31–17
APIEN
15
0
Reserved. Write to zero for future compatibility.
0
Address Parity Error Injection Enable.
This bit is cleared by hardware after a single address parity
error has been injected.
—
15–9
EIEN
8
0
Reserved. Write to zero for future compatibility.
0
EEIM
7–0
0
Error Injection Enable
Enables/disables injection of errors.
This applies to the data mask bits and to the ECC mask
bits.
Note: Error injection should not be enabled until the
memory controller has been enabled through
DDR_SDRAM_CFG[MEM_EN].
ECC Error Injection Mask (0–7)
Setting a mask bit causes the corresponding ECC bit to
be inverted during memory bus writes.
Settings
0 Address parity error injection
disabled.
1 Address parity error injection
enabled.
0
Error injection disabled.
1
Error injection enabled.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-107
DDR SDRAM Memory Controller
12.8.37
DDR SDRAM Memory Data Path Read Capture Data High Register
(MnCAPTURE_DATA_HI)
CAPTURE_DATA_HI
Bit
31
30
29
DDR SDRAM Memory Data Path
Read Capture Data High Register
28
27
26
25
24
23
22
Offset 0x0E20
21
20
19
18
17
16
Type
Reset
0
0
0
0
0
0
0
ECHD
R/W
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ECHD
R/W
0
0
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
CAPTURE_DATA_HI stores the high 32 bits of the read data path during error capture.
Table 12-58. CAPTURE_DATA_HI Bit Descriptions
Bit
Reset
ECHD
31–0
0
12.8.38
Description
Error Capture High Data Path
Captures the high 32 bits of the data path when errors are detected.
DDR SDRAM Memory Data Path Read Capture Data Low Register
(MnCAPTURE_DATA_LO)
CAPTURE_DATA_LO
Bit
31
30
29
DDR SDRAM Memory Data Path
Read Capture Data Low Register
28
27
26
25
24
23
22
Offset 0x0E24
21
20
19
18
17
16
ECLD
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
ECLD
R/W
Type
Reset
0
0
0
0
0
0
0
0
CAPTURE_DATA_LO stores the low 32 bits of the read data path during error capture.
Table 12-59. CAPTURE_DATA_LO Bit Descriptions
Bit
Reset
ECLD
31–0
0
Description
Error Capture Low Data Path
Captures the low 32 bits of the data path when errors are detected.
MSC8156 Reference Manual, Rev. 2
12-108
Freescale Semiconductor
Memory Controller Programming Model
12.8.39
DDR SDRAM Memory Data Path Read Capture ECC Register
(MnCAPTURE_ECC)
CAPTURE_ECC
Bit
31
30
DDR SDRAM Memory Data Path Read
Capture ECC Register
29
28
27
26
25
24
23
22
Offset 0x0E28
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
ECE-32
R/W
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
ECE-64
R/W
0
0
0
0
0
—
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
CAPTURE_ECC stores the ECC syndrome bits on the data bus when an error is detected.
Table 12-60. CAPTURE_ECC Bit Descriptions
Bit
Reset
—
31–24
ECE-64
23–16
—
15–8
ECE-64
7–0
0
Reserved. Write to zero for future compatibility.
0
Error Capture ECC
In 32-bit bus mode, captures the ECC bits of the 1st 32-bits when errors are detected
Reserved. Write to zero for future compatibility.
0
0
12.8.40
Description
Error Capture ECC
In 64-bit bus mode, captures the ECC bits of entire bus when errors are detected. (0–7)
In 32-bit bus mode. captures the ECC bits of the 2nd 32-bits when errors are detected
DDR SDRAM Memory Error Detect Register (MnERR_DETECT)
ERR_DETECT
Bit
31
Type
Reset
MME
W1C
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
0
—
R
0
0
Type
Reset
Note:
0
30
DDR SDRAM Memory Error Detect Register
29
28
27
26
25
24
23
22
21
Offset 0x0E40
20
19
18
17
16
—
0
0
0
0
R
0
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
APE
W1C
0
ACE
W1C
0
0
—
R
0
—
R
0
MSE
W1C
0
0
MBE SBE
W1C
0
0
W1C - Write 0b1 to clear the bit, writing 0b0 as no effect.
ERR_DETECT stores the detection bits for multiple memory errors, single- and multiple-bit
ECC errors, calibration error, and memory select errors. Each bit is cleared when software writes
a value of 1 to it. System software can determine the type of memory error by examining the
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-109
DDR SDRAM Memory Controller
contents of this register. If an error is disabled with ERR_DISABLE, the corresponding error is
never detected or captured in ERR_DETECT.
Table 12-61. ERR_DETECT Bit Descriptions
Bit
Reset
MME
31
0
Description
Settings
Multiple Memory Errors
Indicates whether multiple memory errors of the
same type were detected. This bit is cleared by
software writing a 1 to it.
—
30–9
APE
8
0
Reserved. Write to zero for future compatibility.
0
ACE
7
0
Address parity error.
Indicates whether an address parity error was
detected. This bit is cleared by software writing a 1
to it.
Automatic Calibration Error
Indicates whether an automatic calibration error
was detected. This bit is cleared by software
writing a 1 to it.
—
6–4
MBE
3
0
Reserved. Write to zero for future compatibility.
0
Multiple-Bit Error
Indicates whether a multiple-bit error was
detected. This bit is cleared by software writing a 1
to it.
Single-Bit ECC Error
Indicates whether the number of single-bit ECC
errors detected is equal to the threshold set in
ERR_SBE[SBET]. This bit is cleared by software
writing a 1 to it.
Reserved. Write to zero for future compatibility.
SBE
2
—
1
MSE
0
0
0
12.8.41
Memory Select Error
Indicates whether a memory select error has been
detected. This bit is cleared by software writing a 1
to it.
31
Multiple memory errors were not
detected.
1
Multiple memory errors of the same
type were detected.
0 An address parity error has not been
detected.
1 An address parity error has been
detected
0 Automatic calibration Error has not
been detected.
1
Automatic calibration Error has been
detected..
0
Multiple-bit error not detected.
1
Multiple-bit error detected.
0
The number of errors is less than the
threshold.
1
The number of errors is equal or
greater than the threshold.
0
Memory select error not detected.
1
Memory select error detected.
DDR SDRAM Memory Error Disable Register (MnERR_DISABLE)
ERR_DISABLE
Bit
0
30
DDR SDRAM Memory Error Disable Register
29
28
27
26
25
24
Offset 0x0E44
23
22
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
—
R
0
0
—
R
0
—
R
0
MSED
R/W
0
Type
Reset
0
0
0
0
0
APED ACED
R/W R/W
0
0
0
MBED SBED
R/W
0
0
ERR_DISABLE selectively disables the DDR controller error detection circuitry. Disabled errors
are not detected or reported.
MSC8156 Reference Manual, Rev. 2
12-110
Freescale Semiconductor
Memory Controller Programming Model
Table 12-62. ERR_DISABLE Bit Descriptions
Bit
Reset
Description
—
31–9
APED
8
0
Reserved. Write to zero for future compatibility.
0
ACED
7
0
Address parity error disable
Address parity errors are detected if
DDR_SDRAM_CFG_2[AP_EN] is set. They are
reported if ERR_INT_EN[APEE] is set.
Automatic Calibration Error Disable
Enables/disables automatic calibration errors
detection
—
6–4
MBED
3
0
Reserved. Write to zero for future compatibility.
0
SBED
2
0
Multiple-Bit ECC Error Disable
Enables/disables multiple-bit ECC errors detection.
When this bit is cleared, multiple-bit errors are
detected if DDR_SDRAM_CFG[ECC_EN] is set.
They are reported if ERR_INT_EN[MBEE] is set.
Single-Bit ECC Error Disable
Enables/disables single-bit ECC errors detection.
1
MSED
0
0
0
Reserved. Write to zero for future compatibility.
Memory Select Error Disable
Enables/disables memory select errors detection.
Settings
0 Address parity errors are detected.
1 Address parity errors are not
detected or reported.
0
Automatic Calibration errors
enabled.
1
Automatic Calibration errors
disabled.
0
Multiple-bit ECC errors detected
1
Multiple-bit ECC errors not detected
or reported.
0
Single-bit ECC errors detection is
enabled.
1
Single-bit ECC errors detection is
disabled.
0
Memory select errors detection is
enabled.
1
Memory select errors detection is
disabled.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-111
DDR SDRAM Memory Controller
12.8.42
DDR SDRAM Memory Error Interrupt Enable Register
(MnERR_INT_EN)
ERR_INT_EN
Bit
31
DDR SDRAM Memory Error Interrupt Enable Register
30
29
28
27
26
25
24
Offset 0x0E48
23
22
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
—
R
0
0
—
R
0
—
R
0
MSEE
R/W
0
Type
Reset
0
0
0
0
0
APEE ACEE
R/W R/W
0
0
0
MBEE SBEE
R/W
0
0
ERR_INT_EN enables ECC interrupts, calibration error, address/command parity error or
memory select error interrupts. When an enabled interrupt condition occurs, the DDR Controller
interrupt request signal is asserted to the embedded programmable interrupt controller (EPIC)
Table 12-63. ERR_INT_EN Bit Descriptions
Bit
Reset
—
31–9
APEE
8
0
Reserved. Write to zero for future compatibility.
0
Address parity error interrupt enable
ACEE
7
0
Automatic Calibration Error Interrupt Enable
Specifies whether automatic calibration errors
generate interrupts.
—
6–4
MBEE
3
Description
Settings
0 Address parity errors cannot generate
interrupts.
1 Address parity errors generate interrupts.
0 Calibration errors cannot generate
interrupts.
1
Calibration errors generate interrupts.
0
Reserved. Write to zero for future compatibility.
0
Multiple-Bit ECC Error Interrupt Enable
Specifies whether multiple-bit ECC errors
generate interrupts.
0
Multiple-bit ECC errors cannot generate
interrupts.
1
0
Multiple-bit ECC errors generate
interrupts.
Single-bit ECC errors cannot generate
interrupts.
SBEE
2
0
Single-Bit ECC Error Interrupt Enable
Specifies whether single-bit ECC errors generate
interrupts.
—
1
MSEE
0
0
Reserved. Write to zero for future compatibility.
Memory Select Error Interrupt Enable
Specifies whether memory select errors generate
interrupts.
1
Single-bit ECC errors generate interrupts.
0
Memory select errors do not generate
interrupts.
1
Memory select errors generate interrupts.
MSC8156 Reference Manual, Rev. 2
12-112
Freescale Semiconductor
Memory Controller Programming Model
12.8.43
DDR SDRAM Memory Error Attributes Capture Register
(MnCAPTURE_ATTRIBUTES)
CAPTURE_ATTRIBUTES
DDR SDRAM Memory Error
Attributes Capture Register
Bit
31
30
29
28
27
26
25
Type
Reset
—
R
0
0
BNUM
R/W
0
0
—
R
0
0
TSIZ
R/W
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
0
—
R
0
Type
Reset
—
R
0
24
23
0
0
0
0
0
21
20
19
18
17
16
0
0
0
0
0
4
3
2
1
0
0
VLD
R/W
0
—
R
TTYP
R/W
0
22
Offset 0x0E4C
0
0
0
0
0
CAPTURE_ATTRIBUTES sets attributes for errors including type, size, source, and so on.
Table 12-64. CAPTURE_ATTRIBUTES Bit Descriptions
Bit
Reset
—
31
BNUM
30–28
0
Reserved. Write to zero for future compatibility.
0
—
27
TSIZ
26–24
0
Data Beat Number
Captures the data beat number for the detected error. This
bit is relevant only for ECC errors.
Reserved. Write to zero for future compatibility.
0
Description
Transaction Size for Error
Captures the transaction size in 64-bit increments.
Settings
000
4 × 64 bits.
001
1 × 64 bits.
010
2 × 64 bits.
011
3 × 64 bits.
All other values are reserved
—
23–14
TTYP
13–12
0
Reserved. Write to zero for future compatibility.
0
Transaction Type for Error
Specifies the access type that generates the error.
00 Reserved.
01 Write.
10 Read.
11 Read-modify-write.
—
11–1
VLD
0
0
Reserved. Write to zero for future compatibility.
0
Valid
Set as soon as valid information is captured in the error
capture registers.
0
No valid information captured
1
Valid information captured
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-113
DDR SDRAM Memory Controller
12.8.44
DDR SDRAM Memory Error Address Capture Register
(MnCAPTURE_ADDRESS)
CAPTURE_ADDRESS
Bit
31
30
29
DDR SDRAM Memory Error Address
Capture Register
28
27
26
25
24
23
22
21
Offset 0x0E50
20
19
18
17
16
Type
Reset
0
0
0
0
0
0
0
CADDR
R/W
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
CADDR
R/W
0
0
0
0
0
0
0
0
0
Type
Reset
0
0
0
0
0
0
CAPTURE_ADDRESS holds the 32-bit of the transaction address when a DDR ECC error is
detected.
Table 12-65. CAPTURE_ADDRESS Bit Descriptions
Bit
Reset
CADDR
31–0
0
12.8.45
31
Settings
Captured Address
Captures the 32 bits of the transaction address when an error is detected.
DDR SDRAM Single-Bit ECC Memory Error Management Register
(MnERR_SBE)
ERR_SBE
Bit
Description
DDR SDRAM Single-Bit ECC Memory Error
Management Register
30
29
28
27
26
25
24
23
22
21
Offset 0x0E58
20
—
R
19
18
17
16
SBET
R/W
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
SBEC
R/W
0
0
0
0
0
Type
Reset
—
R
0
0
0
0
0
0
0
0
0
0
ERR_SBE stores the threshold value for reporting single-bit errors and the number of single-bit
errors counted since the last error report. When the counter field reaches the threshold, it wraps
back to the reset value (0). If necessary, software must clear the counter after it has managed the
error.
MSC8156 Reference Manual, Rev. 2
12-114
Freescale Semiconductor
Memory Controller Programming Model
Table 12-66. ERR_SBE Bit Descriptions
Bit
Reset
—
31–24
SBET
23–16
0
Reserved. Write to zero for future compatibility.
0
—
15–8
SBEC
7–0
0
Single-Bit Error Threshold
Establishes the number of single-bit errors that must be detected before an error condition is
reported.
Reserved. Write to zero for future compatibility.
12.8.46
Description
0
Single-Bit Error Counter
Indicates the number of single-bit errors detected and corrected since the last error report. If
single-bit error reporting is enabled, an error is reported when this value equals the SBET value.
SBEC is automatically cleared when the threshold value is reached.
Debug Register 2 (MnDEBUG_2)
DEBUG_2
Bit
31
Debug Register 2
30
29
28
27
26
25
24
Offset 0x0F04
23
22
21
20
19
18
17
16
—
R
Type
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
IDLE
—
1
0
—
Type
Reset
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEBUG_2 is used to indicate whether the controller is active.
Table 12-67. ERR_SBE Bit Descriptions
Bit
Reset
Description
—
31–2
IDLE
1
0
Reserved. Write to zero for future compatibility.
1
Idle
The DDR controller is in idle state.
—
0
0
Settings
0
Active
1
Idle
Reserved. Write to zero for future compatibility.
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
12-115
DDR SDRAM Memory Controller
MSC8156 Reference Manual, Rev. 2
12-116
Freescale Semiconductor
Interrupt Handling
13
The MSC8156 interrupt system is optimized for a multi-processing environment and performs
the following functions:
„ Routes each of the interrupt sources to each of the extended SC3850 cores thus allowing:
— Flexible resource allocations as well as for a symmetrical or a non-symmetrical
application architecture.
— Provides a core-to-core full interrupt mesh.
— Provides external host-to-core signaling mechanism by virtual interrupt generation.
„ Allows for the enabling/disabling of each interrupt source per core.
The MSC8156 supports both internal and external interrupt sources as well as allowing for the
generation of an interrupt to external devices.
There are three device level interrupt handlers in the MSC8156:
1.
Global interrupt controller. Allows for the generation of virtual interrupt requests
(VIRQ) as well as virtual non-maskable interrupts (VNMI) towards the cores as well as
generates interrupts to external devices.
2.
General configuration block. Concentrates and routes rare and debug interrupts to the
SC3400 cores.
3.
Embedded programmable interrupt controller (EPIC). Concentrates all the interrupt
directed at the associated core and dispatches the highest priority interrupt to the
SC3400 core. Although there are various interrupts in the system designated as
non-maskable interrupts (NMIs), you must program them to be non-maskable in the
EPIC. This is typically done by the boot program.
Note:
See the SC3850 DSP Core Subsystem Reference Manual for details about the EPIC.
The manual is available with a signed non-disclosure agreement. Contact your local
Freescale dealer or sales representative for more information.
Note:
The QUICC Engine module also includes an interrupt controller that handles interrupts
within the module for the dual-RISC processor system. For details about that interrupt
controller and how to program it, refer to Chapter 18, QUICC Engine Subsystem and
the QUICC Engine™ Block Reference Manual with Protocol Interworking
(QEIWRM).
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-1
Interrupt Handling
13.1
Global Interrupt Controller (GIC)
The GIC generates 16 VIRQs and 8 VNMIs to the DSP cores by writing to registers in the GIC
memory map. The GIC also uses two additional VIRQ slots to generate a non-maskable interrupt
NMI_OUT and a maskable interrupt INT_OUT to external devices. A virtual interrupt/VNMI is
generated via a write access to the Virtual Interrupt Generation Register (VIGR) by one of the
SC3400 cores or an external host CPU. Table 13-1 describes the destination of the supported
VIRQs.
Table 13-1. VIRQ Description
VIRQ Num
Destination
VIRQ_0
Connected to Virtual Interrupt 0 at SC3400
VIRQ_1
Connected to Virtual Interrupt 1 at SC3400
VIRQ_2
Connected to Virtual Interrupt 2 at SC3400
VIRQ_3
Connected to Virtual Interrupt 3 at SC3400
VIRQ_4
Connected to Virtual Interrupt 4 at SC3400
VIRQ_5
Connected to Virtual Interrupt 5 at SC3400
VIRQ_6
Connected to Virtual Interrupt 6 at SC3400
VIRQ_7
Connected to Virtual Interrupt 7 at SC3400
VIRQ_8
Connected to Virtual Interrupt 8 at SC3400
VIRQ_9
Connected to Virtual Interrupt 9 at SC3400
VIRQ_10
Connected to Virtual Interrupt 10 at SC3400
VIRQ_11
Connected to Virtual Interrupt 11 at SC3400
VIRQ_12
Connected to Virtual Interrupt 12 at SC3400
VIRQ_13
Connected to Virtual Interrupt 13 at SC3400
VIRQ_14
Connected to Virtual Interrupt 14 at SC3400
VIRQ_15
Connected to Virtual Interrupt 15 at SC3400
VIRQ_16
Connected to VNMI_0
VIRQ_17
Connected to VNMI_1
VIRQ_18
Connected to VNMI_2
VIRQ_19
Connected to VNMI_3
VIRQ_20
Connected to VNMI_4
VIRQ_21
Connected to VNMI_5
VIRQ_22
Connected to VNMI_6
VIRQ_23
Connected to VNMI_7
VIRQ_24
Use to generate INT_OUT (see 13.2.2, External Interrupts)
VIRQ_25
Use to generate NMI_OUT (see 13.2.2, External Interrupts)
The GIC has a status register to indicate whether a virtual interrupt was generated at least once,
while not preventing the generation of another interrupt. The core that services the interrupt may
clear this status bit by writing a value of one to it, or it may ignore this bit and work locally.
MSC8156 Reference Manual, Rev. 2
13-2
Freescale Semiconductor
General Configuration Block
13.2
General Configuration Block
The general configuration block performs services for rare and debug interrupts generated
throughout the MSC8156 before they reach the SC3850 EPICs. These services include:
„ Generating ORed interrupt signals towards the SC3400 cores (see Section 13.2.1).
„ Providing an interrupt enable bit for each interrupt source for each SC3400 core (see
Section 13.5.2, General Interrupt Configuration, on page 13-26).
„ Providing a status bit for each interrupt source. These bits are shared for all the SC3400
cores (see Section 13.5.2, General Interrupt Configuration, on page 13-26).
13.2.1 Interrupt Groups
The general configuration block generates 5 interrupts based on the groups of ORed interrupts
described in Table 13-2.
Table 13-2. General Configuration Block Interrupt Sources
TDM
TDM 0 Rx error
TDM 0 Tx error
TDM 1 Rx error
TDM 1 Tx error
TDM 2 Rx error
TDM 2 Tx error
TDM 3 Rx error
TDM 3 Tx error
Debug
CLASS 0 overrun
General
Parity error from TDM[0–3]
Watch Dog Timer
MAPLE-B
MAPLE general
Watch Dog Timer 0
error
QUICC Engine module
Watch Dog Timer 1
DRAM double soft error
QUICC Engine module IMEM
Watch Dog Timer 2
CLASS 0 error
double soft error
Performance Monitor all DMA error
Watch Dog Timer 3
Core subsystems 0 and
DDR1 interrupt
Watch Dog Timer 4
1 MEX address error.
Core subsystems 2 and
DDR2 interrupt
Watch Dog Timer 5
3 MEX address error.
Core subsystems 4 and
OCN0 to MBus
Watch Dog Timer 6
5 MEX address error.
OCN1 to MBus
Watch Dog Timer 7
MAPLE FFT double soft error
MAPLE DFT double soft error
MAPLE IMEM double soft
error
MAPLE DRAM double soft
error
CLASS 0 watchpoint
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-3
Interrupt Handling
13.2.2 External Interrupts
The MSC8156 allows a number of external interrupt inputs to be multiplexed with the GPIO
signals to enable external devices to interrupt the cores (see Chapter 22, GPIO). There are also
dedicated external interrupt pins.
Note:
All external IRQ signals are multiplexed options of the associated GPIO ports.
Table 13-3 summarizes all the external interrupt inputs in the MSC8156.
Table 13-3. MSC8156 External Interrupt Pins
Name
GPIO
Direction
NMI
N/A
In
NMI_OUT
N/A
Out
INT_OUT
N/A
Out
IRQ0
GPIO0
In
IRQ1
GPIO1
In
IRQ2
GPIO2
In
IRQ3
GPIO3
In
IRQ4
GPIO4
In
IRQ5
GPIO5
In
IRQ6
GPIO6
In
IRQ7
GPIO7
In
IRQ8
GPIO8
In
IRQ9
GPIO9
In
IRQ10
GPIO10
In
IRQ11
GPIO11
In
IRQ12
GPIO12
In
IRQ13
GPIO13
In
IRQ14
GPIO14
In
IRQ15
GPIO15
In
INT_OUT is asserted when VIRQ_24 is asserted. NMI_OUT is asserted when VIRQ_25 is
asserted.
MSC8156 Reference Manual, Rev. 2
13-4
Freescale Semiconductor
General Configuration Block
13.2.3 Interrupt Handling
The MSC8156 interrupts sources can be grouped in to four basic types:
1.
Interrupts that represent a single interrupt source and are routed directly to the cores (for
example, the TDM0 Rx first threshold interrupt).
2.
Interrupts that represent multiple interrupt sources and are routed directly to the cores
(for example, all I2C interrupts).
3.
Interrupts that represent a single interrupt source and are routed to the cores via the
general configuration block (for example, MAPLE general error interrupt).
4.
Interrupts that represent multiple interrupt sources and are routed to the cores via the
General Configuration Block (for example, parity error from TDM[0–3] interrupt).
Figure 13-1 outlines the flow for handling the various types of interrupts.
Core Interrupted
Interrupt
source
type
type 4
Read General Configuration Block
Status Register(s) to decide
which interrupt source to go to
type 1
type 3
Handle General Configuration Block
Status Register
type 2
Read Status Register at
source and decide which
interrupt to handle
Handle Status Register at
interrupt source
Handle Interrupt
Figure 13-1. Interrupt Handling Flow
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-5
Interrupt Handling
As an example of handling a type 4 interrupt, processing of a QUICC Engine interrupt is
provided. In Table 13-2, there are two types of QUICC Engine interrupts that are routed through
the GCRs:
„ DRAM double soft error
„ IMEM double soft error
When enabled and unmasked, both interrupts are concentrated to the GCR general interrupt
which is routed to all cores. The GIER1_[0–5] registers allow the user to mask/unmask the
interrupts for any or all of the cores.
If the general interrupt from the GCR is received by a core (index 245), the ISR should read GIR1
(GCR offset 0x80) to identify the origin of the general interrupt. Bits 18 and 19 in the register
represent DRAM double soft error and IMEM double soft error, respectively. After identifying
that the interrupt is coming from the QUICC Engine subsystem, the cores can handle the interrupt
in the same way as other QUICC Engine interrupts that are directed to the DSP core subsystems.
There are nine other QUICC Engine interrupts that use indexes 132–141 as indicated in Table
13-4. Details about the QUICC Engine interrupt controller and how to use this interrupts is
provided in Chapter 18, QUICC Engine Subsystem and the QUICC Engine™ Block Reference
Manual with Interworking (QEIWRM).
13.3
Interrupt Mapping
The EPIC can support up to 256 interrupt sources that can be level-, edge-, or double-edge
triggered. The interrupts can have an assigned priority from 1(lowest) to 31 (highest) as well as
non-maskable (priority 32). The first 34 interrupt sources are used internally by the SC3850 DSP
cores. The core-to-core interrupt mesh uses another 12 interrupts for core-to-core
communication. All other interrupts are used by the MSC8156 device. The MSC8156 does not
implement all of these possible sources.
Table 13-4 describes the interrupt capabilities (level/edge) and index for each interrupt source.
The interrupt default priority at wake up is 0 (all interrupts are ignored). Interrupt sources routed
via the general configuration block do not appear in the table because their function is set by the
GCR.
Table 13-4. MSC8156 Interrupt Table
IRQ
index
Level
Edge
From Core Subsystem 0
34
+
+
From Core Subsystem 0
35
+
+
From Core Subsystem 1
36
+
+
From Core Subsystem 1
37
+
+
Interrupt Description
Core Subsystem Interrupt Mesh
MSC8156 Reference Manual, Rev. 2
13-6
Freescale Semiconductor
Interrupt Mapping
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
From Core Subsystem 2
38
+
+
From Core Subsystem 2
39
+
+
From Core Subsystem 3
40
+
+
From Core Subsystem 3
41
+
+
From Core Subsystem 4
42
+
+
From Core Subsystem 4
43
+
+
From Core Subsystem 5
44
+
+
From Core Subsystem 5
45
+
+
TDM 0 Rx first threshold
50
+
+
TDM 0 Rx second threshold
51
+
+
TDM 0 Tx first threshold
52
+
+
TDM 0 Tx second threshold
53
+
+
TDM 1 Rx first threshold
54
+
+
TDM 1 Rx second threshold
55
+
+
TDM 1 Tx first threshold
56
+
+
TDM 1 Tx second threshold
57
+
+
TDM 2 Rx first threshold
58
+
+
TDM 2 Rx second threshold
59
+
+
TDM 2 Tx first threshold
60
+
+
TDM 2 Tx second threshold
61
+
+
TDM 3 Rx first threshold
62
+
+
TDM 3 Rx second threshold
63
+
+
TDM 3 Tx first threshold
64
+
+
TDM 3 Tx second threshold
65
+
+
Serial RapidIO message in 0
82
+
—
Serial RapidIO message in 1
83
+
—
Serial RapidIO message out 0
84
+
—
Serial RapidIO message out 1
85
+
—
Serial RapidIO doorbell inbound
86
+
—
Serial RapidIO doorbell outbound
87
+
—
Serial RapidIO general error
88
+
—
Ethernet 1 all
91
+
—
Ethernet 1 Rx 0
92
+
—
Ethernet 1 Rx 1
93
+
—
Ethernet 1 Rx 2
94
+
—
Ethernet 1 Rx 3
95
+
—
Interrupt Description
TDM
Serial RapidIO
Ethernet 1
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-7
Interrupt Handling
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
Ethernet 1 Rx 4
96
+
—
Ethernet 1 Rx 5
97
+
—
Ethernet 1 Rx 6
98
+
—
Ethernet 1 Rx 7
99
+
—
Ethernet 1 Tx 0
100
+
—
Ethernet 1 Tx 1
101
+
—
Ethernet 1 Tx 2
102
+
—
Ethernet 1 Tx 3
103
+
—
Ethernet 1 Tx 4
104
+
—
Ethernet 1 Tx 5
105
+
—
Ethernet 1 Tx 6
106
+
—
Ethernet 1 Tx 7
107
+
—
Ethernet 2 all
109
+
—
Ethernet 2 Rx 0
110
+
—
Ethernet 2 Rx 1
111
+
—
Ethernet 2 Rx 2
112
+
—
Ethernet 2 Rx 3
113
+
—
Ethernet 2 Rx 4
114
+
—
Ethernet 2 Rx 5
115
+
—
Ethernet 2 Rx 6
116
+
—
Ethernet 2 Rx 7
117
+
—
Ethernet 2 Tx 0
118
+
—
Ethernet 2 Tx 1
119
+
—
Ethernet 2 Tx 2
120
+
—
Ethernet 2 Tx 3
121
+
—
Ethernet 2 Tx 4
122
+
—
Ethernet 2 Tx 5
123
+
—
Ethernet 2 Tx 6
124
+
—
Ethernet 2 Tx 7
125
+
—
PCI Express INTA
127
+
—
PCI Express INTB
128
+
—
PCI Express INTC
129
+
—
PCI Express INTD
130
+
—
PCI Express general interrupt
131
+
—
QUICC Engine interrupt output 0
132
+
—
QUICC Engine interrupt output 1
133
+
—
Interrupt Description
Ethernet 2
PCI Express
QUICC Engine Subsystem
MSC8156 Reference Manual, Rev. 2
13-8
Freescale Semiconductor
Interrupt Mapping
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
QUICC Engine interrupt output 2
134
+
—
QUICC Engine interrupt output 3
135
+
—
QUICC Engine interrupt output 4
136
+
—
QUICC Engine interrupt output 5
137
+
—
QUICC Engine interrupt output 6
138
+
—
QUICC Engine interrupt output 7
139
+
—
QUICC Engine module critical
140
+
—
QUICC Engine module regular
141
+
—
DMA channel 0 EOB
144
+
—
DMA channel 1 EOB
145
+
—
DMA channel 2 EOB
146
+
—
DMA channel 3 EOB
147
+
—
DMA channel 4 EOB
148
+
—
DMA channel 5 EOB
149
+
—
DMA channel 6 EOB
150
+
—
DMA channel 7 EOB
151
+
—
DMA channel 8 EOB
152
+
—
DMA channel 9 EOB
153
+
—
DMA channel 10 EOB
154
+
—
DMA channel 11 EOB
155
+
—
DMA channel 12 EOB
156
+
—
DMA channel 13 EOB
157
+
—
DMA channel 14 EOB
158
+
—
DMA channel 15 EOB
159
+
—
Timer 0 Channel 0
160
+
—
Timer 0 Channel 1
161
+
—
Timer 0 Channel 2
162
+
—
Timer 0 Channel 3
163
+
—
Timer 1 Channel 0
164
+
—
Timer 1 Channel 1
165
+
—
Timer 1 Channel 2
166
+
—
Timer 1 Channel 3
167
+
—
Timer 2 Channel 0
168
+
—
Timer 2 Channel 1
169
+
—
Timer 2 Channel 2
170
+
—
Interrupt Description
DMA
Timer 0
Timer 1
Timer 2
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-9
Interrupt Handling
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
171
+
—
Timer 3 Channel 0
172
+
—
Timer 3 Channel 1
173
+
—
Timer 3 Channel 2
174
+
—
Timer 3 Channel 3
175
+
—
176
+
—
Virtual Interrupt 0
177
—
+
Virtual Interrupt 1
178
—
+
Virtual Interrupt 2
179
—
+
Virtual Interrupt 3
180
—
+
Virtual Interrupt 4
181
—
+
Virtual Interrupt 5
182
—
+
Virtual Interrupt 6
183
—
+
Virtual Interrupt 7
184
—
+
Virtual Interrupt 8
185
—
+
Virtual Interrupt 9
186
—
+
Virtual Interrupt 10
187
—
+
Virtual Interrupt 11
188
—
+
Virtual Interrupt 12
189
—
+
Virtual Interrupt 13
190
—
+
Virtual Interrupt 14
191
—
+
Virtual Interrupt 15
192
—
+
Virtual Non Maskable Interrupt 0
193
—
+
Virtual Non Maskable Interrupt 1
194
—
+
Virtual Non Maskable Interrupt 2
195
—
+
Virtual Non Maskable Interrupt 3
196
—
+
Virtual Non Maskable Interrupt 4
197
—
+
Virtual Non Maskable Interrupt 5
198
—
+
Virtual Non Maskable Interrupt 6
199
—
+
Virtual Non Maskable Interrupt 7
200
—
+
Channel 0 Interrupt
203
+
—
Channel 1 Interrupt
204
+
—
Channel 2 Interrupt
205
+
—
Channel 3 Interrupt
206
+
—
Interrupt Description
Timer 2 Channel 3
Timer 3
UART
UART all
Global Interrupt Controller
OCNDMA0
MSC8156 Reference Manual, Rev. 2
13-10
Freescale Semiconductor
Interrupt Mapping
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
208
+
—
MAPLE BD 0
209
+
+
MAPLE BD 1
210
+
+
MAPLE BD 2
211
+
+
MAPLE BD 3
212
+
+
MAPLE BD 4
213
+
+
MAPLE BD 5
214
+
+
MAPLE BD 6
215
+
+
MAPLE BD 7
216
+
+
MAPLE BD 8
217
+
+
MAPLE BD 9
218
+
+
MAPLE BD 10
219
+
+
MAPLE BD 11
220
+
+
MAPLE BD 12
221
+
+
MAPLE BD 13
222
+
+
MAPLE BD 14
223
+
+
MAPLE BD 15
224
+
+
IRQ0 (see note)
226
+
+
IRQ1 (see note)
227
+
+
IRQ2 (see note)
228
+
+
IRQ3 (see note)
229
+
+
IRQ4 (see note)
230
+
+
IRQ5 (see note)
231
+
+
IRQ6 (see note)
232
+
+
IRQ7 (see note)
233
+
+
IRQ8 (see note)
234
+
+
IRQ9 (see note)
235
+
+
IRQ10 (see note)
236
+
+
IRQ11 (see note)
237
+
+
IRQ12 (see note)
238
+
+
IRQ13 (see note)
239
+
+
IRQ14 (see note)
240
+
+
IRQ15 (see note)
241
+
+
NMI (see note)
242
+
+
Interrupt Description
I2C
I2C all
MAPLE-B
External IRQs
General Configuration Block
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-11
Interrupt Handling
Table 13-4. MSC8156 Interrupt Table (Continued)
IRQ
index
Level
Edge
ORed TDM interrupts
243
+
—
ORed Debug Interrupts
244
+
—
ORed General Interrupts
245
+
—
ORed Watch Dog Timer Interrupts
246
+
—
ORed MAPLE Interrupts
247
+
—
Channel 0 Interrupt
248
+
—
Channel 1 Interrupt
249
+
—
Channel 2 Interrupt
250
+
—
Channel 3 Interrupt
251
+
—
Interrupt Description
OCNDMA1
Note:
For NMIs and IRQs, when configured as edge-triggered interrupts, assertion of the interrupt is sensed by the cores
when the signals are changing state from 1 to 0.
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
0
0x0
—
—
0
0x0
1
16 B
Trap0
Internal exception
(generated by a TRAP0
instruction)
Trap1
Internal exception
(generated by a TRAP1
instruction)
—
—
16
0x10
1
16 B
Trap2
Internal exception
(generated by a TRAP2
instruction)
—
—
32
0x20
1
16 B
Trap3
Internal exception
(generated by a TRAP3
instruction)
—
—
48
0x30
1
16 B
Reserved
—
1
0x1
—
—
64
0x40
4
64 B
ILLEGAL
Illegal instruction or set.
2
0x2
—
—
128
0x80
4
64 B
DEBUG
• Debug exception
(OCE)
• DEBUG/EV
instruction and EDCA
are Precise
3
0x3
—
—
192
0xC0
4
64 B
After
• EDCD is Precise
After (+2 read, +5
write)
OVERFLOW
Overflow exception
(DALU).
4
0x4
—
—
256
0x100
4
64 B
Reserved
—
5
0x5
—
—
320
0x140
1
16 B
MSC8156 Reference Manual, Rev. 2
13-12
Freescale Semiconductor
Interrupt Mapping
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
Dec
Hex
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
No.
Size
OCE
OCE exception.
—
—
328
0x148
1
16 B
IMMUAE
Instruction MMU address
error.
—
—
336
0x150
1
16 B
DMMUAE
Data MMU address error.
—
—
344
0x158
1
16 B
Reserved
—
—
—
352
0x160
1
16 B
IEDC
Instruction EDC error.
—
—
360
0x168
1
16 B
DEDC
Data EDC error.
—
—
368
0x170
1
16 B
Reserved
—
—
—
376
0x178
1
16 B
Reserved
—
6
0x6
—
—
384
0x180
4
64 B
Reserved
—
7
0x7
—
—
448
0x1C0
4
64 B
I_MIFER
Master interface errors
from the MMU (NMI)
8
0x8
0
0x0
512
0x200
1
16 B
I_SIFER
Slave interface errors
from the MMU (NMI)
9
0x9
1
0x1
528
0x210
1
16 B
I_WBBEDC
WBB soft data error
(NMI)
10
0xA
2
0x2
544
0x220
1
16 B
Reserved
Reserved
11
0xB
3
0x3
560
0x230
1
16 B
I_ICDME
ICache double match
error (NMI)
12
0xC
4
0x4
576
0x240
1
16 B
I_DCDME
DCache double match
error (NMI)
13
0xD
5
0x5
592
0x250
1
16 B
I_L2NM2
L2 non-mapped M2
access (NMI)
14
0xE
6
0x6
608
0x260
1
16 B
I_L2NAE
L2 non-aligned
non-allocated access
(NMI)
15
0xF
7
0x7
624
0x270
1
16 B
Reserved
Reserved for internal
DSP subsystem use
16
0x10
8
0x8
640
0x280
1
16 B
I_ICAES
ICache end-of-sweep
operation exception
17
0x11
9
0x9
656
0x290
1
16 B
I_DCAES
DCache end-of-sweep
operation exception
18
0x12
10
0xA
672
0x2A0
1
16 B
I_L2AES
L2 Cache end-of-sweep
operation exception
operational in a DSP
subsystem with L2 cache
19
0x13
11
0xB
688
0x2B0
1
16 B
I_TM0
Timer 0 interrupt
20
0x14
12
0xC
704
0x2C0
1
16 B
I_TM1
Timer 1 interrupt
21
0x15
13
0xD
720
0x2D0
1
16 B
I_DPUA
DPU interrupt A
22
0x16
14
0xE
736
0x2E0
1
16 B
i_DPUB
DPU interrupt B
23
0x17
15
0xF
752
0x2F0
1
16 B
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-13
Interrupt Handling
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
I_ICNCH
ICache noncacheable hit
exception
24
0x18
16
0x10
768
0x300
1
16 B
I_DCNCH
DCache noncacheable
hit exception
25
0x19
17
0x11
784
0x310
1
16 B
I_L2NCH
L2 cache noncacheable
hit exception
26
0x1A
18
0x12
800
0x320
1
16 B
I_L2ESP
L2 cache end-of-software
prefetch
27
0x1B
19
0x13
816
0x330
1
16 B
Reserved
—
28
0x1C
20
0x14
832
0x340
1
16 B
Reserved
—
29
0x1D
21
0x15
848
0x350
1
16 B
Reserved
—
30
0x1E
22
0x16
864
0x360
1
16 B
Reserved
—
31
0x1F
23
0x17
880
0x370
1
16 B
Reserved
—
32
0x20
24
0x18
896
0x380
1
16 B
Reserved
—
33
0x21
25
0x19
912
0x390
1
16 B
Reserved
—
34
0x22
26
0x1A
928
0x3A0
1
16 B
Reserved
—
35
0x23
27
0x1B
944
0x3B0
1
16 B
Reserved
—
36
0x24
28
0x1C
960
0x3C0
1
16 B
Reserved
—
37
0x25
29
0x1D
976
0x3D0
1
16 B
Reserved
—
38
0x26
30
0x1E
992
0x3E0
1
16 B
Reserved
—
39
0x27
31
0x1F
1008
0x3F0
1
16 B
Reserved
—
40
0x28
32
0x20
1024
0x400
1
16 B
Reserved
—
41
0x29
33
0x21
1040
0x410
1
16 B
IRQ34
From Core Subsystem 0
42
0x2A
34
0x22
1056
0x420
1
16 B
IRQ35
From Core Subsystem 0
43
0x2B
35
0x23
1072
0x430
1
16 B
IRQ36
From Core Subsystem 1
44
0x2C
36
0x24
1088
0x440
1
16 B
IRQ37
From Core Subsystem 1
45
0x2D
37
0x25
1104
0x450
1
16 B
IRQ38
From Core Subsystem 2
46
0x2E
38
0x26
1120
0x460
1
16 B
IRQ39
From Core Subsystem 2
47
0x2F
39
0x27
1136
0x470
1
16 B
IRQ40
From Core Subsystem 3
48
0x30
40
0x28
1152
0x480
1
16 B
IRQ41
From Core Subsystem 3
49
0x31
41
0x29
1168
0x490
1
16 B
IRQ42
—
50
0x32
42
0x2A
1184
0x4A0
1
16 B
IRQ43
—
51
0x33
43
0x2B
1200
0x4B0
1
16 B
IRQ44
—
52
0x34
44
0x2C
1216
0x4C0
1
16 B
IRQ45
—
53
0x35
45
0x2D
1232
0x4D0
1
16 B
IRQ46
—
54
0x36
46
0x2E
1248
0x4E0
1
16 B
IRQ47
—
55
0x37
47
0x2F
1264
0x4F0
1
16 B
MSC8156 Reference Manual, Rev. 2
13-14
Freescale Semiconductor
Interrupt Mapping
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
IRQ48
—
56
0x38
48
0x30
1280
0x500
1
16 B
IRQ49
—
57
0x39
49
0x31
1296
0x510
1
16 B
IRQ50
TDM 0 Rx first threshold
58
0x3A
50
0x32
1312
0x520
1
16 B
IRQ51
TDM 0 Rx second
threshold
59
0x3B
51
0x33
1328
0x530
1
16 B
IRQ52
TDM 0 Tx first threshold
60
0x3C
52
0x34
1344
0x540
1
16 B
IRQ53
TDM 0 Tx second
threshold
61
0x3D
53
0x35
1360
0x550
1
16 B
IRQ54
TDM 1 Rx first threshold
62
0x3E
54
0x36
1376
0x560
1
16 B
IRQ55
TDM 1 Rx second
threshold
63
0x3F
55
0x37
1392
0x570
1
16 B
IRQ56
TDM 1 Tx first threshold
64
0x40
56
0x38
1408
0x580
1
16 B
IRQ57
TDM 1 Tx second
threshold
65
0x41
57
0x39
1424
0x590
1
16 B
IRQ58
TDM 2 Rx first threshold
66
0x42
58
0x3A
1440
0x5A0
1
16 B
IRQ59
TDM 2 Rx second
threshold
67
0x43
59
0x3B
1456
0x5B0
1
16 B
IRQ60
TDM 2 Tx first threshold
68
0x44
60
0x3C
1472
0x5C0
1
16 B
IRQ61
TDM 2 Tx second
threshold
69
0x45
61
0x3D
1488
0x5D0
1
16 B
IRQ62
TDM 3 Rx first threshold
70
0x46
62
0x3E
1504
0x5E0
1
16 B
IRQ63
TDM 3 Rx second
threshold
71
0x47
63
0x3F
1520
0x5F0
1
16 B
IRQ64
TDM 3 Tx first threshold
72
0x48
64
0x40
1536
0x600
1
16 B
IRQ65
TDM 3 Tx second
threshold
73
0x49
65
0x41
1552
0x610
1
16 B
IRQ66
—
74
0x4A
66
0x42
1568
0x620
1
16 B
IRQ67
—
75
0x4B
67
0x43
1584
0x630
1
16 B
IRQ68
—
76
0x4C
68
0x44
1600
0x640
1
16 B
IRQ69
—
77
0x4D
69
0x45
1616
0x650
1
16 B
IRQ70
—
78
0x4E
70
0x46
1632
0x660
1
16 B
IRQ71
—
79
0x4F
71
0x47
1648
0x670
1
16 B
IRQ72
—
80
0x50
72
0x48
1664
0x680
1
16 B
IRQ73
—
81
0x51
73
0x49
1680
0x690
1
16 B
IRQ74
—
82
0x52
74
0x4A
1696
0x6A0
1
16 B
IRQ75
—
83
0x53
75
0x4B
1712
0x6B0
1
16 B
IRQ76
—
84
0x54
76
0x4C
1728
0x6C0
1
16 B
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-15
Interrupt Handling
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
IRQ77
—
85
0x55
77
0x4D
1744
0x6D0
1
16 B
IRQ78
—
86
0x56
78
0x4E
1760
0x6E0
1
16 B
IRQ79
—
87
0x57
79
0x4F
1776
0x6F0
1
16 B
IRQ80
—
88
0x58
80
0x50
1792
0x700
1
16 B
IRQ81
—
89
0x59
81
0x51
1808
0x710
1
16 B
IRQ82
Serial RapidIO message
in 0
90
0x5A
82
0x52
1824
0x720
1
16 B
IRQ83
Serial RapidIO message
in 1
91
0x5B
83
0x53
1840
0x730
1
16 B
IRQ84
Serial RapidIO message
out 0
92
0x5C
84
0x54
1856
0x740
1
16 B
IRQ85
Serial RapidIO message
out 1
93
0x5D
85
0x55
1872
0x750
1
16 B
IRQ86
Serial RapidIO doorbell
inbound
94
0x5E
86
0x56
1888
0x760
1
16 B
IRQ87
Serial RapidIO doorbell
outbound
95
0x5F
87
0x57
1904
0x770
1
16 B
IRQ88
Serial RapidIO general
error
96
0x60
88
0x58
1920
0x780
1
16 B
IRQ89
—
97
0x61
89
0x59
1936
0x790
1
16 B
IRQ90
—
98
0x62
90
0x5A
1952
0x7A0
1
16 B
IRQ91
Ethernet 1 all
99
0x63
91
0x5B
1968
0x7B0
1
16 B
IRQ92
Ethernet 1 Rx 0
100
0x64
92
0x5C
1984
0x7C0
1
16 B
IRQ93
Ethernet 1 Rx 1
101
0x65
93
0x5D
2000
0x7D0
1
16 B
IRQ94
Ethernet 1 Rx 2
102
0x66
94
0x5E
2016
0x7E0
1
16 B
IRQ95
Ethernet 1 Rx 3
103
0x67
95
0x5F
2032
0x7F0
1
16 B
IRQ96
Ethernet 1 Rx 4
104
0x68
96
0x60
2048
0x800
1
16 B
IRQ97
Ethernet 1 Rx 5
105
0x69
97
0x61
2064
0x810
1
16 B
IRQ98
Ethernet 1 Rx 6
106
0x6A
98
0x62
2080
0x820
1
16 B
IRQ99
Ethernet 1 Rx 7
107
0x6B
99
0x63
2096
0x830
1
16 B
IRQ100
Ethernet 1 Tx 0
108
0x6C
100
0x64
2112
0x840
1
16 B
IRQ101
Ethernet 1 Tx 1
109
0x6D
101
0x65
2128
0x850
1
16 B
IRQ102
Ethernet 1 Tx 2
110
0x6E
102
0x66
2144
0x860
1
16 B
IRQ103
Ethernet 1 Tx 3
111
0x6F
103
0x67
2160
0x870
1
16 B
IRQ104
Ethernet 1 Tx 4
112
0x70
104
0x68
2176
0x880
1
16 B
IRQ105
Ethernet 1 Tx 5
113
0x71
105
0x69
2192
0x890
1
16 B
IRQ106
Ethernet 1 Tx 6
114
0x72
106
0x6A
2208
0x8A0
1
16 B
MSC8156 Reference Manual, Rev. 2
13-16
Freescale Semiconductor
Interrupt Mapping
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
IRQ107
Ethernet 1 Tx 7
115
0x73
107
0x6B
2224
0x8B0
1
16 B
IRQ108
—
116
0x74
108
0x6C
2240
0x8C0
1
16 B
IRQ109
Ethernet 2 all
117
0x75
109
0x6D
2256
0x8D0
1
16 B
IRQ110
Ethernet 2 Rx 0
118
0x76
110
0x6E
2272
0x8E0
1
16 B
IRQ111
Ethernet 2 Rx 1
119
0x77
111
0x6F
2288
0x8F0
1
16 B
IRQ112
Ethernet 2 Rx 2
120
0x78
112
0x70
2304
0x900
1
16 B
IRQ113
Ethernet 2 Rx 3
121
0x79
113
0x71
2320
0x910
1
16 B
IRQ114
Ethernet 2 Rx 4
122
0x7A
114
0x72
2336
0x920
1
16 B
IRQ115
Ethernet 2 Rx 5
123
0x7B
115
0x73
2352
0x930
1
16 B
IRQ116
Ethernet 2 Rx 6
124
0x7C
116
0x74
2368
0x940
1
16 B
IRQ117
Ethernet 2 Rx 7
125
0x7D
117
0x75
2384
0x950
1
16 B
IRQ118
Ethernet 2 Tx 0
126
0x7E
118
0x76
2400
0x960
1
16 B
IRQ119
Ethernet 2 Tx 1
127
0x7F
119
0x77
2416
0x970
1
16 B
IRQ120
Ethernet 2 Tx 2
128
0x80
120
0x78
2432
0x980
1
16 B
IRQ121
Ethernet 2 Tx 3
129
0x81
121
0x79
2448
0x990
1
16 B
IRQ122
Ethernet 2 Tx 4
130
0x82
122
0x7A
2464
0x9A0
1
16 B
IRQ123
Ethernet 2 Tx 5
131
0x83
123
0x7B
2480
0x9B0
1
16 B
IRQ124
Ethernet 2 Tx 6
132
0x84
124
0x7C
2496
0x9C0
1
16 B
IRQ125
Ethernet 2 Tx 7
133
0x85
125
0x7D
2512
0x9D0
1
16 B
IRQ126
—
134
0x86
126
0x7E
2528
0x9E0
1
16 B
IRQ127
PCI Express INTA
135
0x87
127
0x7F
2544
0x9F0
1
16 B
IRQ128
PCI Express INTB
136
0x88
128
0x80
2560
0xA00
1
16 B
IRQ129
PCI Express INTC
137
0x89
129
0x81
2576
0xA10
1
16 B
IRQ130
PCI Express INTD
138
0x8A
130
0x82
2592
0xA20
1
16 B
IRQ131
PCI Express general
interrupt
139
0x8B
131
0x83
2608
0xA30
1
16 B
IRQ132
QUICC Engine interrupt
output 0
140
0x8C
132
0x84
2624
0xA40
1
16 B
IRQ133
QUICC Engine interrupt
output 1
141
0x8D
133
0x85
2640
0xA50
1
16 B
IRQ134
QUICC Engine interrupt
output 2
142
0x8E
134
0x86
2656
0xA60
1
16 B
IRQ135
QUICC Engine interrupt
output 3
143
0x8F
135
0x87
2672
0xA70
1
16 B
IRQ136
QUICC Engine interrupt
output 4
144
0x90
136
0x88
2688
0xA80
1
16 B
MSC8156 Reference Manual, Rev. 2
Freescale Semiconductor
13-17
Interrupt Handling
Table 13-5. Interrupt Summary Reference by Interrupt Indexes and VBA Offset (Continued)
Interrupt Index
Name
Description
EPIC Interrupt
Index
Offset from
VBA
Fetch Set
Dec
Hex
Dec
Hex
Dec
Hex
No.
Size
IRQ137
QUICC Engine interrupt
output 5
145
0x91
137
0x89
2704
0xA90
1
16 B
IRQ138
QUICC Engine interrupt
output 6
146
0x92
138
0x8A
2720
0xAA0
1
16 B
IRQ139
QUICC Engine interrupt
output 7
147
0x93
139
0x8B
2736
0xAB0
1
16 B
IRQ140
QUICC Engine module
critical
148
0x94
140
0x8C
2752
0xAC0
1
16 B
IRQ141
QUICC Engine module
regular
149
0x95
141
0x8D
2768
0xAD0
1
16 B
IRQ142
—
150
0x96
142
0x8E
2784
0xAE0
1
16 B
IRQ143
—
151
0x97
143
0x8F
2800
0xAF0
1
16 B
IRQ144
DMA channel 0 EOB
152
0x98
144
0x90
2816
0xB00
1
16 B
IRQ145
DMA channel 1 EOB
153
0x99
145
0x91
2832
0xB10
1
16 B
IRQ146
DMA channel 2 EOB
154
0x9A
146
0x92
2848
0xB20
1
16 B
IRQ147
DMA channel 3 EOB
155
0x9B
147
0x93
2864
0xB30
1
16 B
IRQ148
DMA channel 4 EOB
156
0x9C
148
0x94
2880
0xB40
1
16 B
IRQ149
DMA channel 5 EOB
157
0x9D
149
0x95
2896
0xB50
1
16 B
IRQ150
DMA channel 6 EOB
158
0x9E
150
0x96
2912
0xB60
1
16 B
IRQ151
DMA channel 7 EOB
159
0x9F
151
0x97
2928
0xB70
1
16 B
IRQ152
DMA channel 8 EOB
160
0xA0
152
0x98
2944
0xB80
1
16 B
IRQ153
DMA channel 9 EOB
161
0xA1
153
0x99
2960
0xB90
1
16 B
IRQ154
DMA channel 10 EOB
162
0x