NXP PCA9570 Remote 4-bit general purpose outputs Data Sheet

PCA9570

Remote 4-bit general purpose outputs for 1 MHz I

2

C-bus Rev. 5 — 16 November 2017 Product data sheet

The PCA9570 is a CMOS device that provides 4 bits of General Purpose parallel Output (GPO) expansion in low voltage processor and handheld battery powered mobile applications. It operates at 1 MHz I 2 C-bus speeds while maintaining backward compatibility to Fast-mode (400 kHz) and Standard-mode (100 kHz).

The PCA9570 is a streamlined GPO that consists of 4-bit push-pull outputs that offer low current consumption, small packaging options and a low operating voltage range of 1.1 V to 3.6 V. The latched outputs are symmetrical 4 mA current drive capability at 3.3 V to drive various control logic. The PCA9570 output expander provides a simple solution when additional outputs are needed while keeping interconnections and floor space to a minimum, for example, in battery powered mobile applications where PCBs are crowded for interfacing to sensors, push buttons, etc.

The PCA9570 contains an internal Power-On Reset (POR) and a Software Reset feature that initializes the device to its default state.

2. Features and benefits

            1 MHz I 2 C-bus interface with 6 mA SDA sink capability for lightly loaded buses (<100 pF) and improved power consumption Compliant with the I 2 C-bus Fast and Standard modes 1.1 V to 3.6 V operation Latched outputs with a sink/source capability of 4 mA at 3.3 V Readable device ID (manufacturer, device type, and revision) Software Reset Power-On Reset Low standby current  40  C to +85  C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA Packages offered: XQFN8 (0.5 mm lead pitch)

3. Applications

   Smart phones and tablets Portable medical equipment Portable instrumentation and test measurement

NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus Table 1.

Ordering information Type number Topside marking Package

PCA9570GM P7X

[1]

Name

XQFN8 [1] ‘X’ changes based on date code.

4.1 Ordering options Table 2.

Ordering options Type number Orderable part number Package

PCA9570GM PCA9570GMH XQFN8

Description

plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6

 1.6

 0.5 mm

Packing method

Reel 7” Q3/T4 *Standard mark

Version

SOT902-2

Minimum order quantity

4000

Temperature

T amb =  40  C to +85  C PCA9570

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 16 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus

SCL SDA

PCA9570

INPUT FILTER I 2 C-BUS CONTROL SHIFT REGISTER 4 bits OUTPUT PORT P0 to P3 V DD V SS POWER-ON RESET

Fig 1.

Block diagram of PCA9570

write pulse read pulse write pulse data from Shift Register D FF CI S Q power-on reset read pulse D FF CI S Q data to Shift Register

Fig 2.

Simplified schematic of the I/Os (P0 to P3)

I OH I OL

002aah230

V DD P0 to P3 V SS

002aah231

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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus 6.1 Pinning

terminal 1 index area

PCA9570GM

P0 1 7 SDA 6 SCL P1 2 P2 3

Fig 3.

Pin configuration for XQFN8

Transparent top view 5 P3

002aag941

6.2 Pin description Table 3.

Symbol

V DD P0 P1 P2 V SS P3 SCL SDA

Pin description Pin

8 1 2 3 4 5 6 7

Description

supply voltage input/output 0 input/output 1 input/output 2 supply ground input/output 3 serial clock line serial data line

Refer to Figure 1 “Block diagram of PCA9570”

.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is accessing and the operation it wants to perform (read or write). The address of the PCA9570 is 48h as shown in

Figure 4 .

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slave address 0 1 0 0 1 fixed 0 0 R/W

002aag831

Fig 4.

PCA9570 device address 7.2 Software Reset Call, and device ID addresses

Two other different addresses can be sent to the device.

• •

General Call address: allows resetting the device through the I 2 C-bus upon reception of the right I 2 C-bus sequence. See

Section 7.2.1 “Software Reset”

for more information.

Device ID address: allows reading ID information from the device (manufacturer, part

identification, revision). See Section 7.2.2 “Device ID (PCA9570 ID field)” for more

information.

R/W 0 0 0 0 0 0 0 0

002aac115

Fig 5.

General Call address

1 1 1 1 1 0 0 R/W

002aac116

Fig 6.

Device ID address

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7.2.1 Software Reset

The Software Reset Call allows all the devices in the I 2 C-bus to be reset to the power-up state value through a specific formatted I 2 C-bus command. To be performed correctly, it implies that the I 2 C-bus is functional and that there is no device hanging the bus.

The Software Reset sequence is defined as following: 1. A START command is sent by the I 2 C-bus master.

2. The reserved General Call I 2 C-bus address ‘0000 000’ with the R/W bit set to 0 (write) is sent by the I 2 C-bus master. 3. The device acknowledges after seeing the General Call address ‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I 2 C-bus master.

4. Once the General Call address has been sent and acknowledged, the master sends 1 byte. The value of the byte must be equal to 06h.

a. The device acknowledges this value only. If the byte is not equal to 06h, the device does not acknowledge it.

If more than 1 byte of data is sent, the device does not acknowledge any more.

5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the device then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed.

The I 2 C-bus master must interpret a non-acknowledge from the device (at any time) as a ‘Software Reset Abort’. The device does not initiate a reset of its registers.

The unique sequence that initiates a Software Reset is described in Figure 7

.

SWRST Call I 2 C-bus address SWRST data = 06h S 0 0 0 0 0 0 0 0 A 0 0 0 0 0 1 1 0 A P START condition

Fig 7.

Software Reset sequence

R/W acknowledge from slave(s) acknowledge from slave(s) PCA9570/PCA9571 is(are) reset.

Registers are set to default power-up values.

002aag882

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7.2.2 Device ID (PCA9570 ID field)

The Device ID field is a 3 byte read-only (24 bits) word giving the following information:

• • •

12 bits with the manufacturer name, unique per manufacturer (for example, NXP).

9 bits with the part identification, assigned by manufacturer, the 7 MSBs with the category ID and the 6 LSBs with the feature ID (for example PCA9570 4-bit I/O expander).

3 bits with the die revision, assigned by manufacturer (for example, Rev X).

The Device ID is read-only, hardwired in the device and can be accessed as follows: 1. START command 2. The master sends the Reserved Device ID I 2 C-bus address followed by the R/W bit set to 0 (write): ‘1111 1000’.

3. The master sends the I 2 C-bus slave address of the slave device it needs to identify. The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one that has the I 2 C-bus slave address).

4. The master sends a Re-START command.

Remark:

A STOP command followed by a START command resets the slave state machine and the Device ID read cannot be performed. Also, a STOP command or a Re-START command followed by an access to another slave device resets the slave state machine and the Device ID Read cannot be performed.

5. The master sends the Reserved Device ID I 2 C-bus address followed by the R/W bit set to 1 (read): ‘1111 1001’.

6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte + 4 MSB of the second byte), followed by the 9 part identification bits (4 LSBs of the second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of the third byte).

7. The master ends the reading sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command.

Remark:

The reading of the Device ID can be stopped anytime by sending a NACK command. If the master continues to ACK the bytes after the third byte, the slave rolls back to the first byte and keeps sending the Device ID sequence until a NACK has been detected.

For the PCA9570, the Device ID is as shown in Figure 8

.

manufacturer 0 0 0 0 0 0 0 0 0 0 0 0 part identification revision 1 0 0 0 0 0 0 0 0 0 0 0

002aag791

Fig 8.

PCA9570 Device ID field

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acknowledge from one or several slaves Device ID address I 2 C-bus slave address of the device to be identified acknowledge from slave to be identified Device ID address acknowledge from slave to be identified S 1 1 1 1 1 0 0 0 A A6 A5 A4 A3 A2 A1 A0 x A Sr 1 1 1 1 1 0 0 1 A START condition R/W acknowledge from master don’t care repeated START condition acknowledge from master R/W no acknowledge from master M 11 M 10 M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P manufacturer name = 000000000000 part identification = 100000000 revision = 000 STOP condition

002aah310

Fig 9.

If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the master generates a ‘no acknowledge’.

Device ID field reading 8.1 I/O architecture

The device ports (see

Figure 2 ) are entirely independent and are output ports. The state

of the ports at the pin is transferred from the ports to the microcontroller in the Read mode

(see Figure 11

). Output data is transmitted to the ports in the Write mode (see

Figure 10

).

At power-on all ports are HIGH. The state of the Output Port register determines if either Q1 or Q2 is on, driving the line either HIGH or LOW. A bit set to 1 in the data byte drives the line HIGH at the corresponding port. A bit set to 0 in the data byte drives the line LOW at the corresponding port.

If an external voltage is applied to an output, care should be exercised because of the low-impedance path that exists between the pin and either V DD or V SS .

8.2 Writing to the port (Output mode)

To write, the master (microcontroller) first addresses the slave device. By setting the last bit of the byte containing the slave address to logic 0, the Write mode is entered. The device acknowledges and the master sends the data byte for P7 to P0 and is acknowledged by the device. Writes to P7 to P4 are ignored in the PCA9570 as only P3 through P0 are available. The 4-bit data is presented on the port lines after it has been acknowledged by the device. The number of data bytes that can be sent successively is not limited. The previous data is overwritten every time a data byte has been sent.

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START condition write to port SCL 1 2 3 4 5 6 7 8 9 slave address data 1 data 2 SDA S A6 A5 A4 A3 A2 A1 A0 0 A P7 P6 P5 P4 P3 1 P1 P0 A P7 P6 P5 P4 P3 0 P1 P0 A data output from port R/W acknowledge from slave P2 acknowledge from slave t v(Q) P2 DATA 1 VALID acknowledge from slave t v(Q) DATA 2 VALID P2 output voltage

002aag833

Fig 10. Write mode (output) 8.3 Reading from a port (Input mode)

All ports are outputs and cannot be used as inputs. When reading the device, the data returned is the port state at the pin. To read, the master (microcontroller) first addresses the slave device by setting the last bit of the byte containing the slave address to logic 1. The data byte that follows on the SDA is the value of the ports pins. There is no limit to the number of bytes read, and the state of the output port pins is updated at each acknowledge cycle. Logic 1 means that the port is HIGH. Logic 0 means that the port is LOW. When the PCA9570 is read, P7 through P4 return logic ‘1’.

no acknowledge from master slave address data from port data from port SDA S A6 A5 A4 A3 A2 A1 A0 1 A DATA 1 A DATA 4 1 P START condition R/W acknowledge from slave acknowledge from master STOP condition read from port

002aag846

Fig 11. Read input port register 8.4 Power-on reset

When power is applied to V DD , an internal Power-On Reset (POR) holds the device in a reset condition until V DD has reached V POR . At that point, the reset condition is released and the device registers and I 2 C-bus/SMBus state machine initialize to their default states. See

Section 14

for DC and AC characteristics of the POR function.

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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus 9.1 I/O expander applications

Figure 12

shows a 4-bit output expander application. The desired HIGH or LOW logic levels are controlled by the master with speeds of up to 1 MHz on a lightly loaded bus (<100 pF). This allows the host processor to control various functions quickly and with very low overhead. The port read function of the device enables the host processor to poll the status of the output port pins. This is useful for system recovery operations or debugging.

1.8 V 1.8 V CORE PROCESSOR SDA SCL P0 P1 P2 P3 GPS enable vibrator control latch control switch control

002aah232

Fig 12. I/O expander application

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10. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

I I I

Symbol

V DD V I I IK I OK O OL DD T stg T j

Parameter

supply voltage input voltage input clamping current output clamping current output current LOW-level output current supply current storage temperature junction temperature

Conditions

SCL; SDA SCL; V I < 0 V P port; V O < 0 V or V O > V DD SDA; V O < 0 V or V O > V DD continuous; P port continuous; SDA; V O = 0 V to V DD continuous through V SS

[1]

-

Min

 0.5

 0.5

 65

Max

+4 +4  18  18  18  25 25 100 +150 125 [1] If the input and output current ratings are observed, the input negative-voltage and output voltage ratings may be exceeded

Unit

V V mA mA mA mA mA mA  C  C

11. Thermal characteristics

Table 5.

Symbol

Z th(j-a)

Thermal characteristics Parameter

transient thermal impedance from junction to ambient

Conditions

XQFN8 (SOT902-2) [1] The package thermal impedance is calculated in accordance with JESD 51-7.

[1]

Max

62

Unit

K/W PCA9570



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12. Static characteristics

Table 6.

T amb =



40

Static characteristics



C to +85



C; V DD = 1.1 V to 3.6 V; unless otherwise specified.

Symbol Parameter

input clamping voltage

Conditions

I I =  18 mA V IK V DD V POR V OL V OH I OL V IH V IL I I I DD C i C o T amb supply voltage power-on reset voltage LOW-level output voltage HIGH-level output voltage LOW-level output current HIGH-level input voltage LOW-level input voltage input current supply current input capacitance output capacitance ambient temperature V I = V DD or V SS ; I O = 0 mA P port; I OL = 2 mA; V DD = 1.65 V P port; I OL = 3 mA; V DD = 2.3 V P port; I OL = 4 mA; V DD = 3 V P port; I OH = 2 mA; V DD = 1.65 V P port; I OH = 3 mA; V DD = 2.3 V P port; I OH = 4 mA; V DD = 3 V SDA; V OL = 0.4 V; V DD = 2.1 V to 3.6 V SDA; V OL = 0.2

 V DD ; V DD = 1.1 V to 2.0 V SCL, SDA; V DD = 1.1 V to 1.2 V SCL, SDA; V DD = 1.2 V to 3.6 V SCL, SDA; V DD = 1.1 V to 1.2 V SCL, SDA; V DD = 1.2 V to 3.6 V SCL, SDA; V DD V I = V DD or V SS = 1.1 V to 3.6 V; SDA, P port; V I I O = 0 mA; f SCL on SDA = V DD or V SS ; = 400 kHz V DD = 2.3 V to 3.6 V V DD = 1.1 V to 2.3 V SCL, SDA, P port; V I I O on SCL, SDA = V = 0 mA; f SCL DD or V = 0 kHz SS ; V DD = 2.3 V to 3.6 V V DD = 1.1 V to 2.3 V Active mode: SCL, SDA, P port; I O f SCL = 0 mA; = 400 kHz; continuous register read V DD = 1.1 V to 2.3 V V I = V DD or V SS V O = V DD or V SS operating in free air [1] The typical values are at V DD = 2.2 V and T amb = 25  C.

-

Min

 1.2

1.1

1.35

2.0

2.7

3 1 0.8

 V DD 0.7

 V DD  0.5

 0.5

-

Typ [1]

0.7

-

Max

3.6

1.0

0.25

0.25

0.25

V V mA mA 1.2

3.6

0.2

 V DD 0.3

 V DD  1 V V V V  A V V V V

Unit

V V V  40 6.5

4 1 0.6

50 6 3 15 9 3.2

1.7

75 7 5 +85  A  A  A  A  A pF pF  C PCA9570



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NXP Semiconductors 12.1 Typical characteristics

aaa-011393

I DD (μA) 12 8 V DD = 3.6 V 3.3 V 2.5 V 1.8 V 1.1 V 4

PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus

120 I DD(stb) (nA) 80 40 V DD = 3.6 V 3.3 V 2.5 V 1.8 V 1.1 V

aaa-011394

0 −40 −15 10 35 60 85 T amb (°C)

Fig 13. Supply current versus ambient temperature

0 −40 −15 10 35 60 85 T amb (°C)

Fig 14. Standby supply current versus ambient temperature

aaa-011395

10 I DD (μA) 8 6 4 2 1 1.1

T amb = 25  C

Fig 15. Supply current versus supply voltage

1.8

2.5

3.3

V DD (V) 3.6

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I sink (mA) 8 6 4 2 T amb = −40 °C 25 °C 85 °C 0 0 0.2

a. V DD = 1.2 V 30 I sink (mA) 20 T amb = −40 °C 25 °C 85 °C

aaa-011487

0.4

V OL (V) 0.6

aaa-011489

I sink (mA) 18 12 T amb = −40 °C 25 °C 85 °C 6 0 0 0.2

b. V DD = 1.8 V I sink (mA) 36 24 T amb = -40 °C 25 °C 85 °C 12 10 0 0 0.2

0.4

V OL (V) 0.6

c. V DD = 2.5 V

Fig 16. I/O sink current versus LOW-level output voltage

0 0 d. V DD = 3.3 V 0.2

aaa-011488

0.4

V OL (V) 0.6

aaa-011490

0.4

V OL (V) 0.6

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I source (mA) 6 4 T amb = −40 °C 25 °C 85 °C 2

aaa-011563

I source (mA) 14 12 10 8 6 4 2 0 0 T amb = −40 °C 25 °C 85 °C 0.2

0 0 0.2

0.4

V DD − V OH (V) 0.6

a. V DD = 1.2 V b. V DD = 1.8 V I source (mA) 25 20 15 T amb = −40 °C 25 °C 85 °C 10 5

aaa-011565

36 I source (mA) 24 12 T amb = −40 °C 25 °C 85 °C 0 0 0.2

0.4

V DD − V OH (V) 0.6

0 0 c. V DD = 2.5 V

Fig 17. I/O source current versus HIGH-level output voltage

d. V DD = 3.3 V 0.2

aaa-011567

V OL (mV) 60 40 (1)

aaa-011564

0.4

V DD − V OH (V) 0.6

aaa-011566

0.4

V DD − V OH (V) 0.6

20 0 −40 (2) −15 10 (1) V DD = 1.8 V; I sink = 2 mA (2) V DD = 1.8 V; I sink = 100  A

Fig 18. LOW-level output voltage versus temperature

35 60 85 T amb (°C) PCA9570



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13. Dynamic characteristics

Table 7.

Dynamic characteristics

V DD = 1.1 V to 3.6 V; V SS = 0 V; T amb =



40



C to +85



C; unless otherwise specified.

Symbol Parameter Conditions Standard mode I 2 C-bus Fast mode I 2 C-bus

f t t t t t t SCL BUF HD;STA SU;STA SU;STO HD;DAT VD;ACK SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time t t t t t VD;DAT t SU;DAT r f LOW HIGH LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals t SP pulse width of spikes that must be suppressed by the input filter

Port timing

t v(Q) data output valid time

[2] [3] [4]

Min

0 4.7

4.0

4.7

4.0

0 250 4.7

4.0

-

Max

100 3.45

3.45

300 1000 50 200

Min

0 1.3

0.6

0.6

0.6

0 100 1.3

0.6

20  (V DD / 5.5 V) 20 -

Max

400 0.9

0.9

300 300 50 200

1 MHz I 2 C-bus

[1]

Min

0 0.5

Unit Max

1000 kHz  s 0.26

0.26

0.26

0 50 0.5

0.26

20  (V DD / 5.5 V) 50  s  s  s 0.45

ns  s 0.45

 s ns  s  s 120 ns 120 ns ns 200 ns [1] [2] [3] [4] Fm+ mode on a non-standard, lightly loaded bus (<100 pF).

t VD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. t VD;DAT = minimum time for SDA data out to be valid following SCL LOW.

Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

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14. Power-on reset requirements

In the event of a glitch or data corruption, the device can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

V DD ramp-up ramp-down re-ramp-up t d(rst) time (dV/dt) r (dV/dt) f time to re-ramp when V DD drops to V SS (dV/dt) r

002aah307

Fig 19. V DD is lowered below 0.6 V and then ramped up to V DD Table 8.

T amb = 25

Recommended supply sequencing and ramp rates



C (unless otherwise noted). Not tested; specified by design.

Symbol Parameter Condition

(dV/dt) f (dV/dt) r t d(rst)  V DD(gl) t w(gl)VDD V POR(trip) fall rate of change of voltage rise rate of change of voltage reset delay time glitch supply voltage difference supply voltage glitch pulse width power-on reset trip voltage

Figure 19 Figure 19 Figure 19

; when V DD drops to V SS

Figure 20

V DD = 2.1 V to 3.6 V V DD = 1.1 V to 2.1 V

Figure 20

rising V DD

[1] [2]

-

Min

0.1

0.1

1 -

Typ

0.7

Max

2000 2000 1.2

V DD  0.9

10 1.0

[1] [2] Level that V DD can glitch down to with a ramp rate of 0.4

 s/V, but not cause a functional disruption when t gw(VDD) = 1  s.

Glitch width that does not cause a functional disruption when V DD = 1.8 V to 3.6 V,  V DD(gl) V DD = 1.1 V to 1.8 V,  V DD(gl) = V DD  0.9 V.

= 0.5

 V DD ; V V  s V

Unit

ms ms  s Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (t w(gl)VDD ) and glitch height (  V DD(gl) ) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance.

Figure 20

and

Table 8 provide more information on

how to measure these specifications.

V DD ∆V DD(gl) t w(gl)VDD

Fig 20. Glitch width and glitch height

time

002aah309

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V POR is critical to the power-on reset. V POR is the voltage level at which the reset condition is released and all the registers and the I 2 C-bus/SMBus state machine are initialized to

their default states. Figure 21 and

Table 8

provide more details on this specification.

V DD V POR (rising V DD ) time POR time

002aah096

Fig 21. Power-on reset voltage (V POR )

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15. Parameter measurement information

DUT SDA V DD RL = 1 kΩ CL = 50 pF

002aag803

a. SDA load configuration STOP condition (P) START condition (S) Address Bit 7 (MSB) two bytes for read Input port register (1) Address Bit 1 R/W Bit 0 (LSB) ACK (A) Data Bit 7 (MSB) Data Bit 0 (LSB) STOP condition (P)

002aag952

b. Transaction format t LOW t HIGH t SP SCL SDA t BUF t r t f t VD;DAT t f(o) t VD;ACK t SU;STA 0.7 × V DD 0.3 × V DD t SU;STO 0.7 × V DD 0.3 × V DD t f t HD;STA t r t SU;DAT t HD;DAT t VD;ACK repeat START condition STOP condition

002aag804

c. Voltage waveforms C L includes probe and jig capacitance.

All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z o = 50  ; t r /t f  30 ns.

All parameters and waveforms are not applicable to all devices.

Byte 1 = I 2 C-bus address; Byte 2, byte 3 = P port data.

(1) See Figure 11

.

Fig 22. I 2 C-bus interface load circuit and voltage waveforms

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DUT Pn 500 Ω CL = 50 pF 500 Ω 2 × V DD

002aag805

a. P port load configuration SCL P0 A P7 0.7 × V DD 0.3 × V DD SDA t v(Q) Pn unstable data last stable bit

002aag806

b. Write mode (R/W = 0) SCL P0 t su(D) A t h(D) P7 0.7 × V DD 0.3 × V DD Pn

002aag807

c. Read mode (R/W = 1) C L includes probe and jig capacitance.

t v(Q) is measured from 0.7

 V DD on SCL to 50 % I/O (Pn) output.

All inputs are supplied by generators having the following characteristics: PRR  10 MHz; Z o = 50  ; t r /t f  30 ns.

The outputs are measured one at a time, with one transition per measurement.

All parameters and waveforms are not applicable to all devices.

Fig 23. P port load circuit and voltage waveforms

PCA9570



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NXP Semiconductors

16. Package outline

;4)1SODVWLFH[WUHPHO\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus 627

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Fig 24. Package outline SOT902-2 (XQFN8)

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17. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in

JESD625-A

or equivalent standards.

18. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note

AN10365 “Surface mount reflow soldering description”

.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

18.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

• •

Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• • • • • •

Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering

18.3 Wave soldering

Key characteristics in wave soldering are: PCA9570



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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus • •

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave Solder bath specifications, including temperature and impurities

18.4 Reflow soldering

Key characteristics in reflow soldering are:

• • •

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to

higher minimum peak temperatures (see Figure 25

) than a SnPb process, thus reducing the process window Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with

Table 9

and

10

Table 9.

SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (



C) Volume (mm 3 ) < 350



350

< 2.5

 2.5

235 220 220 220

Table 10.

Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (



C) Volume (mm 3 ) < 350 350 to 2000

< 1.6

1.6 to 2.5

> 2.5

260 260 250 260 250 245

> 2000

260 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times.

Studies have shown that small packages reach higher temperatures during reflow

soldering, see Figure 25 .

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temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note

AN10365 “Surface mount reflow soldering description”

.

19. Soldering: PCB footprints

VROGHUODQGV RFFXSLHGDUHD

Fig 26. PCB footprint for SOT505-1 (TSSOP8); reflow soldering

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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI627SDFNDJH 627

RFFXSLHGDUHD VROGHUODQGV 'LPHQVLRQVLQPP ,VVXHGDWH VROGHUUHVLVW VROGHUSDVWH

Fig 27. PCB footprint for SOT1309-1 (XQFN8); reflow soldering

PCA9570



Rev. 5 — 16 November 2017

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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI;4)1SDFNDJH 627

' î +[ &î +\ $\ 6/\ 6/[ VROGHUODQG VROGHUSDVWHGHSRVLW VROGHUODQGSOXVVROGHUSDVWH RFFXSLHGDUHD ',0(16,216LQPP $\ & ' 6/[ 6/\ +[ +\ ,VVXHGDWH

Fig 28. PCB footprint for SOT902-2 (XQFN8); reflow soldering

PCA9570



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20. Abbreviations

Table 11.

Acronym Abbreviations Description

CDM ESD FM GPIO GPS HBM I 2 C-bus I/O Charged-Device Model ElectroStatic Discharge Frequency Modulation General Purpose Input/Output Global Positioning Satellite Human Body Model Inter-Integrated Circuit bus Input/Output IC ID LED LSB MP3 MSB SMBus Integrated Circuit Identification Light Emitting Diode Least Significant Bit MPEG audio layer 3 Most Significant Bit System Management Bus

21. Revision history

Table 12.

Revision history Document ID Release date

PCA9570 v.5

Modifications: PCA9570 v.4

Modifications: PCA9570 v.3

PCA9570 v.2

20171116

•

20140515 20140204

Data sheet status

Product data sheet Removed PCA9570DP and PCA9570GM4 -

Change notice Supersedes

PCA9570 v.4

20140917

• • • • •

Product data sheet -

Table 1 “Ordering information”

: Added table note [1] .

Table 2 “Ordering options”

: Added table note [1] .

Table 8 “Recommended supply sequencing and ramp rates” :

PCA9570 v.3

Table 4 “Limiting values” , I

DD ; changed max from “200” to “100”.

Section 14 “Power-on reset requirements”

: Deleted paragraphs 2 and 3; deleted Fig 22.

– –

t d(rst) : Deleted 2nd row  V DD(gl) : Changed V DD condition from “1.8 V” to “2.1 V” Product data sheet Product data sheet PCA9570 v.2

PCA9570 v.1

PCA9570 v.1

20130910 Product data sheet PCA9570



Rev. 5 — 16 November 2017


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22. Legal information

Document status

[1][2]

Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet

Product status

Development Qualification Production

[3]

Definition

This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

22.2 Definitions Draft —

The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet —

A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification —

The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

22.3 Disclaimers Limited warranty and liability —

Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the

Terms and conditions of commercial sale

of NXP Semiconductors.

Right to make changes —

NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

PCA9570

Product data sheet Suitability for use —

NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications —

Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values —

Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale —

NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license —

Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.


Rev. 5 — 16 November 2017


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NXP Semiconductors PCA9570 Remote 4-bit general purpose outputs for 1 MHz I 2 C-bus Export control —

This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products —

Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s

23. Contact information

own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations —

A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

I 2 C-bus —

logo is a trademark of NXP Semiconductors N.V.

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

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24. Contents

1 2 3

4

4.1

5

6

6.1 6.2

7

7.1

7.2

7.2.1

7.2.2

8

8.1 8.2

8.3 8.4

9

9.1

10 11

12

12.1

13

14

15

16

17 18

18.1 18.2 18.3

18.4

19

20 21

22

22.1 22.2 22.3

22.4

General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information . . . . . . . . . . . . . . . . . . . . . 2

Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

Functional description . . . . . . . . . . . . . . . . . . . 4

Device address . . . . . . . . . . . . . . . . . . . . . . . . . 4

Software Reset Call, and device ID addresses 5

Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . 6

Device ID (PCA9570 ID field) . . . . . . . . . . . . . . 7

I/O programming . . . . . . . . . . . . . . . . . . . . . . . . 8

I/O architecture . . . . . . . . . . . . . . . . . . . . . . . . . 8 Writing to the port (Output mode) . . . . . . . . . . . 8

Reading from a port (Input mode) . . . . . . . . . . 9 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9

Application design-in information . . . . . . . . . 10

I/O expander applications . . . . . . . . . . . . . . . . 10

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal characteristics . . . . . . . . . . . . . . . . . 11

Static characteristics . . . . . . . . . . . . . . . . . . . . 12

Typical characteristics . . . . . . . . . . . . . . . . . . 13

Dynamic characteristics . . . . . . . . . . . . . . . . . 16

Power-on reset requirements . . . . . . . . . . . . . 17

Parameter measurement information . . . . . . 19

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21

Handling information. . . . . . . . . . . . . . . . . . . . 22 Soldering of SMD packages . . . . . . . . . . . . . . 22

Introduction to soldering . . . . . . . . . . . . . . . . . 22 Wave and reflow soldering . . . . . . . . . . . . . . . 22 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 22

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 23

Soldering: PCB footprints. . . . . . . . . . . . . . . . 24

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27

Legal information. . . . . . . . . . . . . . . . . . . . . . . 28

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29

23

24

Contact information . . . . . . . . . . . . . . . . . . . . 29

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2017.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 16 November 2017 Document identifier: PCA9570

NXP PCA9570 Remote 4-bit general purpose outputs Data Sheet

Remote 4-bit general purpose outputs for 1 MHz I

C-bus Rev. 5 — 16 November 2017 Product data sheet

2. Features and benefits

3. Applications

7.2.1 Software Reset

7.2.2 Device ID (PCA9570 ID field)

10. Limiting values

11. Thermal characteristics

12. Static characteristics

13. Dynamic characteristics

14. Power-on reset requirements

15. Parameter measurement information

16. Package outline

17. Handling information

18. Soldering of SMD packages

19. Soldering: PCB footprints

20. Abbreviations

21. Revision history

22. Legal information

23. Contact information

24. Contents

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