NXP MPC574xB-C-G Ultra-Reliable MCUs Reference Manual

MPC5746C Reference Manual
Supports MPC5744B, MPC5745B, MPC5746B, MPC5744C,
MPC5745C and MPC5746C
Document Number: MPC5746CRM
Rev. 6.1, 01/2019
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Contents
Section number
Title
Page
Chapter 1
About This Manual
1.1
Audience....................................................................................................................................................................... 95
1.2
Organization..................................................................................................................................................................95
1.2.1
1.3
Attachments................................................................................................................................................. 95
Module descriptions......................................................................................................................................................95
1.3.1
Example: chip-specific information that clarifies content in the same chapter........................................... 96
1.3.2
Example: chip-specific information that refers to a different chapter......................................................... 97
1.4
Register descriptions.....................................................................................................................................................98
1.5
Conventions.................................................................................................................................................................. 99
1.5.1
Notes, Cautions, and Warnings....................................................................................................................99
1.5.2
Numbering systems......................................................................................................................................99
1.5.3
Typographic notation................................................................................................................................... 100
1.5.4
Special terms................................................................................................................................................ 100
Chapter 2
Introduction
2.1
Introduction...................................................................................................................................................................103
2.1.1
Target Applications......................................................................................................................................103
2.2
Block diagram...............................................................................................................................................................103
2.3
Family comparison........................................................................................................................................................104
2.4
Feature list.....................................................................................................................................................................108
2.5
Package Options............................................................................................................................................................110
2.6
Modes of Operation...................................................................................................................................................... 111
Chapter 3
Memory Map
3.1
Introduction...................................................................................................................................................................117
3.2
System memory map.....................................................................................................................................................117
3.3
NVM memory map....................................................................................................................................................... 118
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3.4
UTEST Memory Map................................................................................................................................................... 120
3.5
RAM memory map....................................................................................................................................................... 121
3.6
Peripheral Bridges A and B memory maps...................................................................................................................122
3.6.1
Peripheral Bridge A memory map............................................................................................................... 122
3.6.2
Peripheral Bridge B memory map............................................................................................................... 126
3.7
MC_CGM mapped peripherals memory map...............................................................................................................127
3.8
PCU mapped peripherals memory map........................................................................................................................ 128
3.9
DMAMUX mapped peripherals memory map............................................................................................................. 128
Chapter 4
Signal Description
4.1
Generic pins/balls..........................................................................................................................................................129
4.1.1
4.2
MSCR assignments...................................................................................................................................... 129
PAD keeping feature in LPU/STANDBY mode.......................................................................................................... 130
Chapter 5
Security Overview
5.1
Introduction...................................................................................................................................................................135
5.2
Basic security................................................................................................................................................................ 135
5.3
Advanced security.........................................................................................................................................................135
5.4
Detailed security information....................................................................................................................................... 136
Chapter 6
Platform Overview
6.1
Introduction...................................................................................................................................................................137
6.2
Performance Enhancement........................................................................................................................................... 138
6.3
User/Privilege Access................................................................................................................................................... 139
Chapter 7
Power Management Overview
7.1
Introduction...................................................................................................................................................................141
7.1.1
7.2
Features........................................................................................................................................................ 142
Power domains..............................................................................................................................................................143
7.2.1
Power Domain0 (PD0).................................................................................................................................144
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7.2.2
Power Domain1 (PD1).................................................................................................................................144
7.2.3
Power Domain2 (PD2).................................................................................................................................144
7.2.4
Flash HV power domain.............................................................................................................................. 145
7.2.5
SRAM domains............................................................................................................................................145
7.2.6
SRAM Configuration................................................................................................................................... 145
7.3
User operating modes, power domains, and clock gating............................................................................................ 146
7.4
Voltage regulators.........................................................................................................................................................148
7.5
7.6
7.4.1
FPREG voltage regulator............................................................................................................................. 148
7.4.2
Internal regulation (Internal ballast)............................................................................................................ 150
7.4.3
LPREG voltage regulator.............................................................................................................................150
7.4.4
ULPREG voltage regulator.......................................................................................................................... 150
7.4.5
Flash voltage regulator.................................................................................................................................151
7.4.6
Regulation mode decoding scheme .............................................................................................................151
7.4.7
Voltage monitoring...................................................................................................................................... 152
7.4.8
Applications and Low Power Modes........................................................................................................... 154
External Regulation...................................................................................................................................................... 154
7.5.1
PORST in EXTERNAL REGULATION.................................................................................................... 154
7.5.2
External regulator contol..............................................................................................................................155
Accelerated Low Power Exit........................................................................................................................................ 156
Chapter 8
Low Power Subsystem (LPU)
8.1
Introduction...................................................................................................................................................................159
8.2
Block diagram...............................................................................................................................................................159
8.3
Features......................................................................................................................................................................... 160
8.4
Modes of operation....................................................................................................................................................... 162
8.5
Transition to LPU mode................................................................................................................................................163
8.6
Exit from LPU Modes...................................................................................................................................................167
8.7
Clocking........................................................................................................................................................................168
8.7.1
LPU System Clock Generation.................................................................................................................... 168
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8.7.2
FlexCAN0 Clocking.................................................................................................................................... 170
8.7.3
LinFlexD Clocking...................................................................................................................................... 170
8.7.4
SPI_0 Clocking............................................................................................................................................ 170
8.7.5
LPU clock source control.............................................................................................................................171
8.8
Reset..............................................................................................................................................................................171
8.9
Interrupts....................................................................................................................................................................... 172
8.10
Boot...............................................................................................................................................................................173
8.11
LPU Controller (LPU_CTL).........................................................................................................................................173
8.11.1
Memory map and register definition............................................................................................................173
8.11.2
LPU Mode Control Register (LPU_MCTL)................................................................................................ 174
8.11.3
LPU Run Configuration Register (LPU_RUN_CF).................................................................................... 176
8.11.4
LPU Stop Configuration Register (LPU_STOP_CF).................................................................................. 178
8.11.5
LPU Standby Configuration Register (LPU_STANDBY_CF)................................................................... 179
8.11.6
LPU Status Register (LPU_SR)................................................................................................................... 180
8.11.7
LPU Interrupt control register (LPU_ICR).................................................................................................. 183
8.11.8
Module Disable (LPU_MDIS).....................................................................................................................185
Chapter 9
Clocking Overview
9.1
Introduction...................................................................................................................................................................187
9.2
System clock generation............................................................................................................................................... 188
9.3
Dynamic Frequency Scaling......................................................................................................................................... 189
9.4
9.3.1
Overview ..................................................................................................................................................... 189
9.3.2
Linear DFS Configuration........................................................................................................................... 191
9.3.3
Non-Linear DFS Configuration................................................................................................................... 192
9.3.4
DFS Limitations........................................................................................................................................... 193
9.3.5
NLDFS Abort on Interrupt...........................................................................................................................193
Peripheral clock generation...........................................................................................................................................193
9.4.1
Overview ..................................................................................................................................................... 193
9.4.2
Enabling/Disabling of peripherals and clock sources.................................................................................. 194
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9.4.3
Communication interfaces .......................................................................................................................... 194
9.4.4
Timers Clock ...............................................................................................................................................201
9.4.5
ADC/BCTU/eMIOS clocking......................................................................................................................204
9.4.6
CLKOUT clocking ......................................................................................................................................204
9.4.7
HSM clocking ............................................................................................................................................. 206
9.4.8
LPU clocking............................................................................................................................................... 206
9.5
MC_CGM registers.......................................................................................................................................................206
9.6
Built-In Self-Test clocking........................................................................................................................................... 207
9.7
System Clock Distribution............................................................................................................................................207
9.7.1
JTAG Frequencies........................................................................................................................................209
9.7.2
Peripheral Clock Restrictions.......................................................................................................................210
9.8
Default clock configuration.......................................................................................................................................... 210
9.9
Clock sources................................................................................................................................................................ 211
9.10
9.9.1
PLL...............................................................................................................................................................211
9.9.2
Fast External Oscillator (FXOSC)............................................................................................................... 213
9.9.3
Slow external oscillator (SXOSC)............................................................................................................... 214
9.9.4
16 MHz internal RC oscillator (FIRC)........................................................................................................ 215
9.9.5
128 kHz internal RC (SIRC)........................................................................................................................ 216
Clock monitoring.......................................................................................................................................................... 217
9.10.1
9.11
CMU configuration...................................................................................................................................... 217
Loss of system clock behavior......................................................................................................................................220
9.11.1
Loss of PLL lock/FXOSC clock.................................................................................................................. 220
9.11.2
Loss of FIRC clock...................................................................................................................................... 220
Chapter 10
Embedded Memories
10.1
Overview.......................................................................................................................................................................223
10.2
System SRAM.............................................................................................................................................................. 223
10.2.1
SRAM Controller (PRAMC)....................................................................................................................... 224
10.2.2
Overlay SRAM............................................................................................................................................ 225
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10.3
Title
Page
Flash memory............................................................................................................................................................... 226
10.3.1
Flash memory controller.............................................................................................................................. 227
10.3.2
Flash memory array..................................................................................................................................... 228
10.3.3
Flash organization........................................................................................................................................ 229
10.3.4
UTest NVM memory space......................................................................................................................... 230
10.3.5
Overlay flash memory..................................................................................................................................231
10.4
End-to-end Error Correction Code (e2eECC)...............................................................................................................231
10.5
Security features............................................................................................................................................................234
Chapter 11
Device Configuration Format (DCF) records
11.1
Introduction...................................................................................................................................................................235
11.2
DCF clients................................................................................................................................................................... 236
11.2.1
Safety features of DCF clients..................................................................................................................... 236
11.2.2
DCF client modification rules......................................................................................................................237
11.3
DCF record structure.....................................................................................................................................................238
11.4
DCF records sequence.................................................................................................................................................. 239
11.5
Chip configuration records........................................................................................................................................... 241
11.5.1
External Regulation Exit Trim Wait (PMCDIG_ERETW)......................................................................... 241
11.5.2
Security and serial boot mode records......................................................................................................... 242
11.5.3
STCU configuration records........................................................................................................................ 242
Chapter 12
Debug Overview
12.1
Introduction ..................................................................................................................................................................243
12.2
Features......................................................................................................................................................................... 245
12.3
Debug scheme...............................................................................................................................................................246
12.4
Modes of operation....................................................................................................................................................... 247
12.4.1
Nexus Reset Mode....................................................................................................................................... 247
12.4.2
Full-port Mode............................................................................................................................................. 248
12.4.3
Reduced-port Mode......................................................................................................................................248
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12.4.4
Disabled-Port Mode..................................................................................................................................... 248
12.4.5
Multi mode nexus TAP................................................................................................................................ 248
12.5
External signal description............................................................................................................................................249
12.6
Memory Map and Registers..........................................................................................................................................250
12.7
Functional Description..................................................................................................................................................250
12.8
12.7.1
Enabling Nexus Clients for TAP Access..................................................................................................... 250
12.7.2
TAP Sharing.................................................................................................................................................250
12.7.3
Configuring the NDI for Nexus Messaging................................................................................................. 251
12.7.4
TCK clock relation with NPC clock............................................................................................................ 251
12.7.5
Programmable MCKO frequency................................................................................................................ 251
12.7.6
Cross Triggering Control............................................................................................................................. 253
12.7.7
Time Stamping............................................................................................................................................. 254
Nexus Port Controller (NPC)........................................................................................................................................255
12.8.1
12.9
NPC Handshake module.............................................................................................................................. 255
e200z4 core and e200z2 core debug support................................................................................................................ 260
12.10 JTAG Controller (JTAGC)........................................................................................................................................... 260
12.11 JTAG ID........................................................................................................................................................................260
12.12 CJTAGC....................................................................................................................................................................... 261
12.13 JDC............................................................................................................................................................................... 261
12.14 Debug implementation..................................................................................................................................................261
12.14.1
Debug Capabilities....................................................................................................................................... 261
12.14.2
Debug port....................................................................................................................................................262
12.15 Nexus Class 3+ Auxiliary Port..................................................................................................................................... 262
12.16 e200z2 Nexus 3.............................................................................................................................................................263
12.17 e200z4 Nexus 3.............................................................................................................................................................264
12.18 Nexus Crossbar Multi-master Client (NXMC).............................................................................................................264
Chapter 13
Reset and Boot Overview
13.1
Introduction...................................................................................................................................................................267
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13.2
13.3
Title
Page
13.1.1
Global Reset................................................................................................................................................. 267
13.1.2
Local Reset...................................................................................................................................................267
13.1.3
Reset sources................................................................................................................................................267
Global Reset Process.....................................................................................................................................................270
13.2.1
Overview...................................................................................................................................................... 270
13.2.2
Reset Process Modules.................................................................................................................................271
13.2.3
Reset Process Sequences..............................................................................................................................273
13.2.4
Reset Process State Transitions....................................................................................................................274
13.2.5
Module Status During Reset Process........................................................................................................... 284
Boot...............................................................................................................................................................................285
13.3.1
Power Up......................................................................................................................................................285
13.3.2
Exit from STANDBY/LPU_STANDBY to DRUN.................................................................................... 285
13.3.3
Exit from LPU STANDBY to LPU_RUN...................................................................................................286
13.3.4
Entry from RUNx/DRUN to LPU_RUN..................................................................................................... 286
13.3.5
Interrupt Vector Prefix retention during STANDBY.................................................................................. 286
Chapter 14
Functional Safety
14.1
Introduction...................................................................................................................................................................287
Chapter 15
System Integration Unit Lite2 (SIUL2)
15.1
15.2
Introduction...................................................................................................................................................................289
15.1.1
Overview...................................................................................................................................................... 289
15.1.2
Features........................................................................................................................................................ 291
15.1.3
Register protection....................................................................................................................................... 292
Memory map and register description.......................................................................................................................... 293
15.2.1
SIUL2 MCU ID Register #1 (SIUL2_MIDR1)........................................................................................... 340
15.2.2
SIUL2 MCU ID Register #2 (SIUL2_MIDR2)........................................................................................... 341
15.2.3
SIUL2 Interrupt Status Flag Register0 (SIUL2_ISR0)................................................................................342
15.2.4
SIUL2 Interrupt Request Enable Register0 (SIUL2_IRER0)......................................................................346
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15.3
Title
Page
15.2.5
SIUL2 Interrupt Request Select Register0 (SIUL2_IRSR0)....................................................................... 349
15.2.6
SIUL2 Interrupt Rising-Edge Event Enable Register 0 (SIUL2_IREER0)................................................. 352
15.2.7
SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0)................................................ 355
15.2.8
SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)......................................................................... 358
15.2.9
SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCRn)..................................................... 360
15.2.10
SIUL2 Interrupt Filter Clock Prescaler Register (SIUL2_IFCPR).............................................................. 361
15.2.11
SIUL2 Multiplexed Signal Configuration Register (SIUL2_MSCRn)........................................................362
15.2.12
SIUL2 Input Multiplexed Signal Configuration Register (SIUL2_IMCRn)............................................... 364
15.2.13
SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)......................................................................... 367
15.2.14
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDIn)............................................................................. 368
15.2.15
SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDOn)...............................................................370
15.2.16
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDIn)................................................................... 371
15.2.17
SIUL2 Masked Parallel GPIO Pad Data Out Register (SIUL2_MPGPDOn)............................................. 371
Functional description...................................................................................................................................................372
15.3.1
General......................................................................................................................................................... 372
15.3.2
Pad Control.................................................................................................................................................. 372
15.3.3
General Purpose Input and Output Pads (GPIO)......................................................................................... 373
15.3.4
External Interrupts Requests (REQ Pins).....................................................................................................374
Chapter 16
Crossbar Switch (AXBS)
16.1
16.2
Chip-specific AXBS information................................................................................................................................. 379
16.1.1
Crossbar Switch configuration.....................................................................................................................379
16.1.2
AXBS 0 Master and Slave assignments.......................................................................................................380
16.1.3
PRS register reset values..............................................................................................................................381
16.1.4
CRS register reset values............................................................................................................................. 381
Introduction...................................................................................................................................................................382
16.2.1
16.3
Features........................................................................................................................................................ 382
Memory Map / Register Definition...............................................................................................................................382
16.3.1
Priority Registers Slave (AXBS_PRSn)...................................................................................................... 384
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16.4
16.5
Title
Page
16.3.2
Control Register (AXBS_CRSn)................................................................................................................. 387
16.3.3
Master General Purpose Control Register (AXBS_MGPCRn)................................................................... 389
Functional Description..................................................................................................................................................390
16.4.1
General operation......................................................................................................................................... 390
16.4.2
Register coherency....................................................................................................................................... 391
16.4.3
Arbitration.................................................................................................................................................... 391
Initialization/application information........................................................................................................................... 394
Chapter 17
Peripheral Bridge
17.1
17.2
17.3
17.4
Chip-specific PBridge information............................................................................................................................... 397
17.1.1
PBRIDGE Configuration............................................................................................................................. 397
17.1.2
Register reset values.....................................................................................................................................397
Introduction...................................................................................................................................................................401
17.2.1
Features........................................................................................................................................................ 401
17.2.2
General operation......................................................................................................................................... 401
Memory map/register definition................................................................................................................................... 402
17.3.1
Master Privilege Register A (AIPS_MPRA)............................................................................................... 404
17.3.2
Master Privilege Register B (AIPS_MPRB)................................................................................................407
17.3.3
Peripheral Access Control Register (AIPS_PACRn)...................................................................................409
17.3.4
Off-Platform Peripheral Access Control Register (AIPS_OPACRn)..........................................................414
Functional description...................................................................................................................................................420
17.4.1
Access support............................................................................................................................................. 420
Chapter 18
Decorated Storage Memory Controller (DSMC)
18.1
Introduction...................................................................................................................................................................421
18.2
Decorated stores: st[b,h,w]d{cb}x rS,rA,rB................................................................................................................. 423
18.2.1
18.3
Bit Field Insert (BFINS) into an 8, 16 or 32-bit memory container............................................................ 424
DSMC instantiations.....................................................................................................................................................428
Chapter 19
Intelligent AHB Gasket (IAHBG)
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19.1
Title
Page
Chip-specific IAHBG information............................................................................................................................... 431
19.1.1
IAHBG configuration.................................................................................................................................. 431
19.1.2
IAHBG clock selection ratios...................................................................................................................... 431
19.1.3
IAHBG features enabled by Platform Configuration Module (PCM)......................................................... 432
19.2
Introduction...................................................................................................................................................................432
19.3
Timing modes............................................................................................................................................................... 432
19.3.1
1:1.................................................................................................................................................................433
19.3.2
2:1.................................................................................................................................................................433
19.3.3
1:2.................................................................................................................................................................433
Chapter 20
System Memory Protection Unit (SMPU)
20.1
20.2
20.3
Chip-specific SMPU information................................................................................................................................. 435
20.1.1
System Memory Protection Unit (SMPU) configuration............................................................................ 435
20.1.2
Default guarded region of cores...................................................................................................................437
Overview.......................................................................................................................................................................437
20.2.1
Block diagram.............................................................................................................................................. 437
20.2.2
Features........................................................................................................................................................ 438
Memory map/register definition................................................................................................................................... 439
20.3.1
Control/Error Status Register 0 (SMPU_CES0).......................................................................................... 445
20.3.2
Control/Error Status Register 1 (SMPU_CES1).......................................................................................... 446
20.3.3
Error Address Register, Bus Master (SMPU_ERR_ADRn)........................................................................447
20.3.4
Error Attribute Detail Register, Bus Master (SMPU_ERR_ADTLn)......................................................... 448
20.3.5
Error Attribute Control Detail Register, Bus Master (SMPU_ERR_ACDLn)............................................ 449
20.3.6
Region Descriptor n, Word 0 (SMPU_RGDn_WRD0)...............................................................................450
20.3.7
Region Descriptor n, Word 1 (SMPU_RGDn_WRD1)...............................................................................450
20.3.8
Region Descriptor n, Word 2 Format 0 (SMPU_RD_nW2_F0)................................................................. 451
20.3.9
Region Descriptor n, Word 2 Format 1 (SMPU_RD_nW2_F1)................................................................. 452
20.3.10
Region Descriptor n, Word 3 (SMPU_RGDn_WRD3)...............................................................................454
20.3.11
Region Descriptor n, Word 4 (SMPU_RGDn_WRD4)...............................................................................456
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20.3.12
20.4
Title
Page
Region Descriptor n, Word 5 (SMPU_RGDn_WRD5)...............................................................................457
Functional description...................................................................................................................................................458
20.4.1
Access evaluation macro..............................................................................................................................458
20.4.2
Putting it all together and error terminations............................................................................................... 460
20.5
Initialization information.............................................................................................................................................. 461
20.6
Application information................................................................................................................................................461
Chapter 21
Semaphores2 (SEMA42)
21.1
Introduction...................................................................................................................................................................465
21.1.1
21.2
21.3
Features........................................................................................................................................................ 465
Memory map/register definition................................................................................................................................... 467
21.2.1
Gate Register (SEMA42_GATEn).............................................................................................................. 467
21.2.2
Reset Gate Write (SEMA42_RSTGT_W)................................................................................................... 468
21.2.3
Reset Gate Read (SEMA42_RSTGT_R)..................................................................................................... 470
Functional description...................................................................................................................................................471
Chapter 22
Platform Configuration Module (PCM)
22.1
Memory map and register definition.............................................................................................................................473
22.1.1
Bus Bridge Configuration Register 0 (PCM_IAHB_BE0)..........................................................................474
22.1.2
Bus Bridge Configuration Register 1 (PCM_IAHB_BE1)..........................................................................476
22.1.3
IPS Clock Gating Module Enable 0 Register (PCM_IPS_CGM_EN0)...................................................... 478
Chapter 23
Interrupt Controller (INTC)
23.1
Chip-specific INTC information...................................................................................................................................481
23.1.1
INTC configuration......................................................................................................................................481
23.1.2
INTC interrupt sources.................................................................................................................................481
23.1.3
INTC implemented registers........................................................................................................................ 493
23.1.4
Interrupts handling during mode transitions................................................................................................ 494
23.2
Introduction...................................................................................................................................................................494
23.3
Block diagram...............................................................................................................................................................495
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23.4
Features......................................................................................................................................................................... 496
23.5
Modes of operation....................................................................................................................................................... 497
23.6
23.7
23.8
23.5.1
Software vector mode.................................................................................................................................. 497
23.5.2
Hardware vector mode................................................................................................................................. 498
Memory map and register definition.............................................................................................................................498
23.6.1
INTC Block Configuration Register (INTC_BCR)..................................................................................... 547
23.6.2
INTC Master Protection Register (INTC_MPROT)....................................................................................549
23.6.3
INTC Current Priority Register for Processor 0 (INTC_CPR0)..................................................................550
23.6.4
INTC Current Priority Register for Processor 1 (INTC_CPR1)..................................................................551
23.6.5
INTC Interrupt Acknowledge Register for Processor 0 (INTC_IACKR0)................................................. 552
23.6.6
INTC Interrupt Acknowledge Register for Processor 1 (INTC_IACKR1)................................................. 553
23.6.7
INTC End Of Interrupt Register for Processor 0 (INTC_EOIR0)...............................................................554
23.6.8
INTC End Of Interrupt Register for Processor 1 (INTC_EOIR1)...............................................................554
23.6.9
INTC Software Set/Clear Interrupt Register (INTC_SSCIRn)....................................................................555
23.6.10
INTC Priority Select Register (INTC_PSRn).............................................................................................. 556
Functional description...................................................................................................................................................558
23.7.1
Interrupt request sources.............................................................................................................................. 558
23.7.2
Priority management.................................................................................................................................... 560
23.7.3
Handshaking with processor........................................................................................................................ 562
Initialization/application information........................................................................................................................... 564
23.8.1
Initialization flow......................................................................................................................................... 565
23.8.2
Interrupt exception handler.......................................................................................................................... 565
23.8.3
ISR, RTOS, and task hierarchy.................................................................................................................... 567
23.8.4
Order of execution....................................................................................................................................... 567
23.8.5
Priority ceiling protocol............................................................................................................................... 568
23.8.6
Selecting priorities according to request rates and deadlines...................................................................... 571
23.8.7
Software-settable interrupt requests.............................................................................................................572
23.8.8
Lowering priority within an ISR.................................................................................................................. 573
23.8.9
Negating an interrupt request outside of its ISR.......................................................................................... 574
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Section number
23.8.10
23.9
Title
Page
Examining LIFO contents............................................................................................................................ 574
Interrupt sources............................................................................................................................................................575
Chapter 24
Wakeup Unit (WKPU)
24.1
Chip-specific WKPU information................................................................................................................................ 577
24.1.1
Wakeup configuration..................................................................................................................................577
24.1.2
NMI configuration....................................................................................................................................... 577
24.1.3
Interrupts...................................................................................................................................................... 578
24.1.4
Wakeup Sources for various modes ............................................................................................................580
24.1.5
NMI on standby exit.................................................................................................................................... 580
24.1.6
Register reset values.....................................................................................................................................581
24.1.7
Pull control of wakeup pads ........................................................................................................................581
24.2
Introduction...................................................................................................................................................................582
24.3
Features......................................................................................................................................................................... 583
24.4
External signal description............................................................................................................................................584
24.5
WKPU memory map and register definition................................................................................................................ 584
24.6
24.5.1
NMI Status Flag Register (WKPU_NSR)................................................................................................... 584
24.5.2
NMI Configuration Register (WKPU_NCR).............................................................................................. 586
24.5.3
Wakeup/Interrupt Status Flag Register (WKPU_WISR).............................................................................589
24.5.4
Interrupt Request Enable Register (WKPU_IRER).....................................................................................590
24.5.5
Wakeup Request Enable Register (WKPU_WRER)................................................................................... 591
24.5.6
Wakeup/Interrupt Rising-Edge Event Enable Register (WKPU_WIREER)...............................................591
24.5.7
Wakeup/Interrupt Falling-Edge Event Enable Register (WKPU_WIFEER).............................................. 592
24.5.8
Wakeup/Interrupt Filter Enable Register (WKPU_WIFER)....................................................................... 592
24.5.9
Wakeup/Interrupt Pull Enable Register (WKPU_WIPER)......................................................................... 593
Functional description...................................................................................................................................................593
24.6.1
24.7
Non-maskable interrupts.............................................................................................................................. 593
Initialization Information.............................................................................................................................................. 595
24.7.1
Glitch Filter and Pad Configuration.............................................................................................................595
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24.7.2
Non-Maskable Interrupts............................................................................................................................. 595
24.7.3
Reset Request............................................................................................................................................... 596
Chapter 25
PLL Digital Interface (PLLDIG)
25.1
Introduction...................................................................................................................................................................597
25.2
Block Diagram.............................................................................................................................................................. 597
25.3
Features......................................................................................................................................................................... 597
25.4
Modes of operation....................................................................................................................................................... 598
25.4.1
25.5
25.6
25.7
Normal mode with reference, PLL enabled................................................................................................. 598
Memory map and register definition.............................................................................................................................598
25.5.1
PLL Calibration Register 3 (PLLDIG_PLLCAL3)..................................................................................... 599
25.5.2
PLLDIG PLL Control Register (PLLDIG_PLLCR)................................................................................... 600
25.5.3
PLLDIG PLL Status Register (PLLDIG_PLLSR)...................................................................................... 602
25.5.4
PLLDIG PLL Divider Register (PLLDIG_PLLDV)................................................................................... 604
25.5.5
PLLDIG PLL Frequency Modulation Register (PLLDIG_PLLFM)...........................................................606
25.5.6
PLLDIG PLL Fractional Divide Register (PLLDIG_PLLFD)....................................................................608
25.5.7
PLL Calibration Register 1 (PLLDIG_PLLCAL1)..................................................................................... 610
Functional description...................................................................................................................................................610
25.6.1
Input clock frequency...................................................................................................................................610
25.6.2
Clock configuration......................................................................................................................................611
25.6.3
Fault Collection and Control Unit (FCCU)..................................................................................................612
25.6.4
Frequency modulation..................................................................................................................................612
25.6.5
PLL Wakeup from low power mode ...........................................................................................................613
25.6.6
Calibration feature........................................................................................................................................613
Initialization information.............................................................................................................................................. 614
Chapter 26
Slow Internal 128 kHz Oscillator (SIRC)
26.1
Introduction...................................................................................................................................................................615
26.2
Features ........................................................................................................................................................................ 615
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Section number
26.3
Page
Memory map and register definition.............................................................................................................................615
26.3.1
26.4
Title
Control register (SIRC_CTL)...................................................................................................................... 615
Functional description ..................................................................................................................................................617
Chapter 27
Fast Internal 16 MHz RC Oscillator (FIRC)
27.1
Introduction...................................................................................................................................................................619
27.2
Features ........................................................................................................................................................................ 619
27.3
Memory map and register definition.............................................................................................................................619
27.3.1
27.4
Control register (FIRC_CTL)...................................................................................................................... 620
Functional description ..................................................................................................................................................621
Chapter 28
Slow External 32 KHz Oscillator (SXOSC)
28.1
Introduction...................................................................................................................................................................623
28.2
Features ........................................................................................................................................................................ 623
28.3
Memory map and register definition ............................................................................................................................623
28.3.1
28.4
SXOSC_CTL............................................................................................................................................... 624
Functional description...................................................................................................................................................625
Chapter 29
Fast OSC Digital Interface (FXOSC)
29.1
Introduction...................................................................................................................................................................627
29.2
Functional description...................................................................................................................................................627
29.3
29.2.1
Oscillator power-down control and status................................................................................................... 628
29.2.2
Oscillator startup delay................................................................................................................................ 628
29.2.3
Oscillator clock available interrupt.............................................................................................................. 628
29.2.4
Oscillator bypass mode................................................................................................................................ 629
29.2.5
Crystal oscillator mode selection................................................................................................................. 629
29.2.6
Oscillator divider..........................................................................................................................................630
Memory map and register definition.............................................................................................................................631
29.3.1
FXOSC Control Register (FXOSC_CTL)................................................................................................... 631
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Title
Page
Chapter 30
Clock Monitor Unit (CMU)
30.1
Introduction...................................................................................................................................................................635
30.1.1
Main features................................................................................................................................................636
30.2
Block diagram...............................................................................................................................................................636
30.3
Signals...........................................................................................................................................................................636
30.4
Register description and memory map......................................................................................................................... 637
30.5
30.4.1
CMU Control Status Register (CMU_CSR)................................................................................................ 638
30.4.2
CMU Frequency Display Register (CMU_FDR)........................................................................................ 639
30.4.3
CMU High Frequency Reference Register CLKMN1 (CMU_HFREFR)...................................................640
30.4.4
CMU Low Frequency Reference Register CLKMN1 (CMU_LFREFR).................................................... 640
30.4.5
CMU Interrupt Status Register (CMU_ISR)............................................................................................... 641
30.4.6
CMU Measurement Duration Register (CMU_MDR)................................................................................ 643
Functional description...................................................................................................................................................643
30.5.1
Frequency meter...........................................................................................................................................643
30.5.2
CLKMN0_RMT supervisor......................................................................................................................... 644
30.5.3
CLKMN1 supervisor....................................................................................................................................644
Chapter 31
Clock Generation Module (MC_CGM)
31.1
Introduction...................................................................................................................................................................647
31.1.1
Overview...................................................................................................................................................... 647
31.1.2
Features........................................................................................................................................................ 648
31.2
External Signal Description.......................................................................................................................................... 649
31.3
Memory Map and Register Definition..........................................................................................................................649
31.3.1
Clockout 1 Select Register (MC_CGM_CLKOUT1_SC)...........................................................................651
31.3.2
CLKOUT1_DC Configuration Register (MC_CGM_CLKOUT1_DC)..................................................... 652
31.3.3
Auxiliary Clock 5 Select Control Register (MC_CGM_AC5_SC)............................................................. 653
31.3.4
Auxiliary Clock 5 Select Status Register (MC_CGM_AC5_SS)................................................................ 654
31.3.5
System Clock Divider 6 Configuration Register (MC_CGM_SC_DC6).................................................... 655
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31.3.6
Auxiliary Clock 8 Select Control Register (MC_CGM_AC8_SC)............................................................. 655
31.3.7
Auxiliary Clock 8 Select Status Register (MC_CGM_AC8_SS)................................................................ 656
31.3.8
Auxiliary Clock 9 Select Control Register (MC_CGM_AC9_SC)............................................................. 657
31.3.9
Auxiliary Clock 9 Select Status Register (MC_CGM_AC9_SS)................................................................ 658
31.3.10
PCS Switch Duration Register (MC_CGM_PCS_SDUR).......................................................................... 659
31.3.11
PCS Divider Change Register 1 (MC_CGM_PCS_DIVC1)....................................................................... 660
31.3.12
PCS Divider End Register 1 (MC_CGM_PCS_DIVE1)............................................................................. 660
31.3.13
PCS Divider Start Register 1 (MC_CGM_PCS_DIVS1)............................................................................ 661
31.3.14
PCS Divider Change Register 2 (MC_CGM_PCS_DIVC2)....................................................................... 662
31.3.15
PCS Divider End Register 2 (MC_CGM_PCS_DIVE2)............................................................................. 662
31.3.16
PCS Divider Start Register 2 (MC_CGM_PCS_DIVS2)............................................................................ 663
31.3.17
Divider Update Abort Register (MC_CGM_DIV_UPD_ABRTD).............................................................664
31.3.18
System Clock Divider Ratio Change Register (MC_CGM_SC_DIV_RC).................................................665
31.3.19
Divider Update Type Register (MC_CGM_DIV_UPD_TYPE)................................................................. 667
31.3.20
Divider Update Trigger Register (MC_CGM_DIV_UPD_TRIG).............................................................. 668
31.3.21
Divider Update Status Register (MC_CGM_DIV_UPD_STAT)................................................................669
31.3.22
System Clock Select Status Register (MC_CGM_SC_SS)......................................................................... 670
31.3.23
System Clock Divider 0 Configuration Register (MC_CGM_SC_DC0).................................................... 671
31.3.24
System Clock Divider 1 Configuration Register (MC_CGM_SC_DC1).................................................... 672
31.3.25
System Clock Divider 2 Configuration Register (MC_CGM_SC_DC2).................................................... 673
31.3.26
System Clock Divider 3 Configuration Register (MC_CGM_SC_DC3).................................................... 674
31.3.27
System Clock Divider 4 Configuration Register (MC_CGM_SC_DC4).................................................... 675
31.3.28
System Clock Divider 5 Configuration Register (MC_CGM_SC_DC5).................................................... 676
31.3.29
Auxiliary Clock 2 Select Control Register (MC_CGM_AC2_SC)............................................................. 677
31.3.30
Auxiliary Clock 2 Select Status Register (MC_CGM_AC2_SS)................................................................ 678
31.3.31
Auxiliary Clock 3 Select Status Register (MC_CGM_AC3_SS)................................................................ 679
31.3.32
Auxiliary Clock 6 Select Control Register (MC_CGM_AC6_SC)............................................................. 679
31.3.33
Auxiliary Clock 6 Select Status Register (MC_CGM_AC6_SS)................................................................ 680
31.3.34
Aux Clock 6 Divider Configuration 0 for CLKOUT_0 (MC_CGM_AC6_DC0).......................................681
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31.4
Title
Page
Functional Description..................................................................................................................................................682
31.4.1
System Clock Generation.............................................................................................................................682
31.4.2
Auxiliary Clock Generation......................................................................................................................... 688
31.4.3
Dividers Functional Description.................................................................................................................. 690
31.4.4
Halt Abort.................................................................................................................................................... 690
Chapter 32
Input Glitch Filter
32.1
Introduction...................................................................................................................................................................693
32.2
Block Diagram.............................................................................................................................................................. 693
32.3
Input Glitch Filter overview..........................................................................................................................................694
32.4
32.5
32.6
32.3.1
Interaction with other peripherals................................................................................................................ 694
32.3.2
Mode of operation........................................................................................................................................ 694
Memory map.................................................................................................................................................................697
32.4.1
Module Configuration Register (IGF_MCRn)............................................................................................ 698
32.4.2
Module Status Register (IGF_MSRn)..........................................................................................................701
32.4.3
Prescaler Register (IGF_PRESRn).............................................................................................................. 702
32.4.4
Rising edge Threshold Register (IGF_RTHRn).......................................................................................... 703
32.4.5
Falling edge Threshold Register (IGF_FTHR)............................................................................................ 703
Functional description...................................................................................................................................................703
32.5.1
Input double sampling..................................................................................................................................704
32.5.2
Filter types....................................................................................................................................................704
32.5.3
Application...................................................................................................................................................708
32.5.4
Programming guidelines.............................................................................................................................. 711
32.5.5
On-the-fly filter reconfiguration.................................................................................................................. 711
Power saving mode....................................................................................................................................................... 712
32.6.1
STOP mode.................................................................................................................................................. 712
Chapter 33
HF - Interface
33.1
Chip specific HFIF information....................................................................................................................................715
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Section number
33.1.1
Title
Page
Module Interconnect.................................................................................................................................... 715
33.2
Introduction...................................................................................................................................................................717
33.3
Block Diagram.............................................................................................................................................................. 717
33.4
Overview.......................................................................................................................................................................719
33.5
33.6
33.4.1
Receiving Data............................................................................................................................................. 719
33.4.2
Transmitting Data........................................................................................................................................ 721
Functional Description..................................................................................................................................................722
33.5.1
Clock Generation......................................................................................................................................... 722
33.5.2
Signal Level Timeout Detection.................................................................................................................. 723
33.5.3
Pulse Detection............................................................................................................................................ 723
33.5.4
Interrupts...................................................................................................................................................... 724
Memory Map and Registers..........................................................................................................................................724
33.6.1
Clock Configuration Register (HFInterface_CCR)..................................................................................... 725
33.6.2
Short Pulse Detector Configuration Register (HFInterface_SPDCR)......................................................... 726
33.6.3
Long Pulse Detector Configuration Register (HFInterface_LPDCR)......................................................... 727
33.6.4
Low-level Timeout Detector Configuration Register (HFInterface_LTDCR)............................................ 728
33.6.5
High-level Timeout Detector Configuration Register (HFInterface_HTDCR)........................................... 729
33.6.6
Interrupt Enable Register (HFInterface_IER)..............................................................................................730
33.6.7
Interrupt Status Register (HFInterface_ISR)............................................................................................... 731
Chapter 34
Analog-to-Digital Converter (ADC)
34.1
Chip-specific ADC information....................................................................................................................................733
34.1.1
ADC configuration.......................................................................................................................................733
34.1.2
Feature comparison...................................................................................................................................... 733
34.1.3
ADC register reset values............................................................................................................................ 734
34.1.4
SARADC control registers...........................................................................................................................735
34.1.5
ADC channel mapping.................................................................................................................................739
34.1.6
ADC_0 valid control register bits................................................................................................................ 742
34.1.7
ADC_1 valid control register bits................................................................................................................ 752
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34.1.8
BCTU Interface............................................................................................................................................760
34.1.9
DMA interface............................................................................................................................................. 760
34.1.10
ADC's stop-stop ack protocol...................................................................................................................... 761
34.2
Introduction...................................................................................................................................................................761
34.3
Overview.......................................................................................................................................................................761
34.3.1
Parts of the ADC.......................................................................................................................................... 761
34.3.2
ADC clock signals....................................................................................................................................... 762
34.3.3
About ADC channels................................................................................................................................... 762
34.4
Features......................................................................................................................................................................... 764
34.5
Memory Map/Register Definition.................................................................................................................................765
34.5.1
Main Configuration Register (ADC_MCR)................................................................................................ 774
34.5.2
Main Status register (ADC_MSR)............................................................................................................... 777
34.5.3
Interrupt Status Register (ADC_ISR).......................................................................................................... 779
34.5.4
Channel Pending register 0 (ADC_CEOCFR0)...........................................................................................780
34.5.5
Channel Pending register 1 (ADC_CEOCFR1)...........................................................................................783
34.5.6
Channel Pending register 2 (ADC_CEOCFR2)...........................................................................................786
34.5.7
Interrupt Mask Register (ADC_IMR)..........................................................................................................789
34.5.8
Channel Interrupt Mask Register 0 (ADC_CIMR0)....................................................................................789
34.5.9
Channel Interrupt Mask Register 1 (ADC_CIMR1)....................................................................................792
34.5.10
Channel Interrupt Mask Register 2 (ADC_CIMR2)....................................................................................794
34.5.11
Watchdog Threshold Interrupt Status Register (ADC_WTISR)................................................................. 797
34.5.12
Watchdog Threshold Interrupt Mask Register (ADC_WTIMR)................................................................. 799
34.5.13
DMA Enable register (ADC_DMAE)......................................................................................................... 800
34.5.14
DMA Channel Select Register 0 (ADC_DMAR0)......................................................................................801
34.5.15
DMA Channel Select Register 1 (ADC_DMAR1)......................................................................................803
34.5.16
DMA Channel Select Register 2 (ADC_DMAR2)......................................................................................806
34.5.17
Threshold Register (ADC_THRHLRn)....................................................................................................... 808
34.5.18
Presampling Control Register (ADC_PSCR).............................................................................................. 809
34.5.19
Presampling register 0 (ADC_PSR0).......................................................................................................... 810
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34.5.20
Presampling register 1 (ADC_PSR1).......................................................................................................... 812
34.5.21
Presampling register 2 (ADC_PSR2).......................................................................................................... 815
34.5.22
Conversion Timing Register 0 (ADC_CTR0)............................................................................................. 817
34.5.23
Conversion Timing Register 1 (ADC_CTR1)............................................................................................. 818
34.5.24
Conversion Timing Register 2 (ADC_CTR2)............................................................................................. 818
34.5.25
Normal Conversion Mask Register 0 (ADC_NCMR0)............................................................................... 819
34.5.26
Normal Conversion Mask Register 1 (ADC_NCMR1)............................................................................... 821
34.5.27
Normal Conversion Mask Register 2 (ADC_NCMR2)............................................................................... 824
34.5.28
Injected Conversion Mask Register 0 (ADC_JCMR0)................................................................................826
34.5.29
Injected Conversion Mask Register 1 (ADC_JCMR1)................................................................................828
34.5.30
Injected Conversion Mask Register 2 (ADC_JCMR2)................................................................................831
34.5.31
Decode Signals Delay Register (ADC_DSDR)........................................................................................... 834
34.5.32
Power Down Exit Delay Register (ADC_PDEDR)..................................................................................... 834
34.5.33
Channel Data Register n (Precision Channels) (ADC_CDRn)....................................................................835
34.5.34
Channel Data Register n (Internal Channels) (ADC_CDRn)...................................................................... 837
34.5.35
Channel Data Register n (External Channels) (ADC_CDRn)..................................................................... 839
34.5.36
Threshold Register (ADC_THRHLRn)....................................................................................................... 840
34.5.37
Channel Watchdog Select Register 0 (ADC_CWSELR0).......................................................................... 840
34.5.38
Channel Watchdog Select Register 1 (ADC_CWSELR1).......................................................................... 841
34.5.39
Channel Watchdog Select Register 2 (ADC_CWSELR2).......................................................................... 842
34.5.40
Channel Watchdog Select Register 4 (ADC_CWSELR4).......................................................................... 843
34.5.41
Channel Watchdog Select Register 5 (ADC_CWSELR5).......................................................................... 844
34.5.42
Channel Watchdog Select Register 6 (ADC_CWSELR6).......................................................................... 845
34.5.43
Channel Watchdog Select Register 7 (ADC_CWSELR7).......................................................................... 846
34.5.44
Channel Watchdog Select Register 8 (ADC_CWSELR8).......................................................................... 847
34.5.45
Channel Watchdog Select Register 9 (ADC_CWSELR9).......................................................................... 848
34.5.46
Channel Watchdog Select Register 10 (ADC_CWSELR10)...................................................................... 849
34.5.47
Channel Watchdog Select Register 11 (ADC_CWSELR11)...................................................................... 850
34.5.48
Channel Watchdog Enable Register 0 (ADC_CWENR0)........................................................................... 851
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Section number
34.6
34.7
Title
Page
34.5.49
Channel Watchdog Enable Register 1 (ADC_CWENR1)........................................................................... 854
34.5.50
Channel Watchdog Enable Register 2 (ADC_CWENR2)........................................................................... 856
34.5.51
Analog Watchdog Out of Range Register 0 (ADC_AWORR0)..................................................................859
34.5.52
Analog Watchdog Out of Range Register 1 (ADC_AWORR1)..................................................................862
34.5.53
Analog Watchdog Out of Range Register 2 (ADC_AWORR2)..................................................................864
34.5.54
Calibration, BIST Control and status Register (ADC_CALBISTREG)......................................................867
34.5.55
Offset and Gain User Register (ADC_OFSGNUSR).................................................................................. 869
Functional description...................................................................................................................................................870
34.6.1
Conversion................................................................................................................................................... 870
34.6.2
Crosstriggering Unit interface......................................................................................................................877
34.6.3
ADC clock prescaler and sample time settings............................................................................................878
34.6.4
Presampling..................................................................................................................................................879
34.6.5
Programmable analog watchdog.................................................................................................................. 881
34.6.6
DMA functionality....................................................................................................................................... 883
34.6.7
Interrupts...................................................................................................................................................... 884
34.6.8
External Decode signals Delay.................................................................................................................... 885
34.6.9
Power-Down mode...................................................................................................................................... 885
34.6.10
Auto-Clock-Off mode.................................................................................................................................. 886
34.6.11
Calibration....................................................................................................................................................886
34.6.12
Conversion time........................................................................................................................................... 888
34.6.13
Conversion data processing......................................................................................................................... 891
Clock frequency............................................................................................................................................................ 891
Chapter 35
Analog Comparator (CMP)
35.1
Chip-specific CMP information....................................................................................................................................893
35.1.1
CMP configuration.......................................................................................................................................893
35.1.2
CMP input output connections.....................................................................................................................894
35.1.3
CMP "VIN1" and "VIN2" references.......................................................................................................... 895
35.1.4
Interaction with RTC API to cause wakeup.................................................................................................896
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Section number
35.1.5
Title
Page
CMP Window control ................................................................................................................................. 897
35.2
Introduction...................................................................................................................................................................897
35.3
Features......................................................................................................................................................................... 898
35.3.1
CMP features................................................................................................................................................898
35.3.2
6-bit DAC key features................................................................................................................................ 899
35.3.3
ANMUX key features.................................................................................................................................. 899
35.4
CMP, DAC, and ANMUX diagram..............................................................................................................................899
35.5
CMP block diagram...................................................................................................................................................... 900
35.6
CMP pin descriptions....................................................................................................................................................902
35.6.1
35.7
35.8
35.9
External pins................................................................................................................................................ 902
CMP functional modes................................................................................................................................................. 903
35.7.1
Disabled mode (# 1)..................................................................................................................................... 904
35.7.2
Continuous mode (#s 2A & 2B).................................................................................................................. 904
35.7.3
Sampled, Non-Filtered mode (#s 3A & 3B)................................................................................................ 905
35.7.4
Sampled, Filtered mode (#s 4A & 4B)........................................................................................................ 907
35.7.5
Windowed mode (#s 5A & 5B)................................................................................................................... 909
35.7.6
Windowed/Resampled mode (# 6)...............................................................................................................911
35.7.7
Windowed/Filtered mode (#7)..................................................................................................................... 911
Memory map/register definitions..................................................................................................................................912
35.8.1
CMP Control Register 0 (CMP_C0)............................................................................................................ 913
35.8.2
CMP Control Register 1 (CMP_C1)............................................................................................................ 916
35.8.3
CMP Control Register 2 (CMP_C2)............................................................................................................ 918
CMP functional description.......................................................................................................................................... 921
35.9.1
Initialization................................................................................................................................................. 921
35.9.2
Low-pass filter............................................................................................................................................. 921
35.10 Interrupts....................................................................................................................................................................... 924
35.11 DMA support................................................................................................................................................................ 924
35.12 DAC functional description.......................................................................................................................................... 924
35.12.1
Digital-to-analog converter block diagram.................................................................................................. 924
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35.12.2
Title
Page
Voltage reference source select....................................................................................................................925
35.13 DAC resets.................................................................................................................................................................... 925
35.14 DAC clocks...................................................................................................................................................................925
35.15 DAC interrupts..............................................................................................................................................................926
35.16 Trigger mode.................................................................................................................................................................926
Chapter 36
Body Cross triggering unit (BCTU)
36.1
Chip-specific BCTU information................................................................................................................................. 929
36.1.1
BCTU configuration.................................................................................................................................... 929
36.1.2
Trigger sources.............................................................................................................................................929
36.1.3
BCTU's stop-stop ack protocol.................................................................................................................... 931
36.2
Introduction...................................................................................................................................................................931
36.3
BCTU overview............................................................................................................................................................ 932
36.4
BCTU Interacting with other peripherals..................................................................................................................... 933
36.5
BCTU Modes of operation............................................................................................................................................934
36.6
36.5.1
Configuration Mode..................................................................................................................................... 935
36.5.2
Normal Mode............................................................................................................................................... 935
36.5.3
Low Power Mode.........................................................................................................................................935
Memory Map................................................................................................................................................................ 936
36.6.1
Module Configuration Register (BCTU_MCR).......................................................................................... 939
36.6.2
Module Status register (BCTU_MSR).........................................................................................................941
36.6.3
Trigger Configuration Register (BCTU_TRGCFG_n)................................................................................945
36.6.4
Write Protection register (BCTU_WRPROT)............................................................................................. 947
36.6.5
Software Trigger register 1 (BCTU_SFTRGR1).........................................................................................948
36.6.6
Software Trigger register 2 (BCTU_SFTRGR2).........................................................................................951
36.6.7
ADC0 Result Data register (BCTU_ADC0DR).......................................................................................... 954
36.6.8
ADC1 result data register (BCTU_ADC1DR)............................................................................................ 955
36.6.9
LIST Size Status register (BCTU_LISTSTAR)...........................................................................................956
36.6.10
LIST Channel Address Register (BCTU_LISTCHR_n)............................................................................. 957
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36.7
36.8
Title
Page
Functional description ..................................................................................................................................................958
36.7.1
Trigger Configuration ................................................................................................................................. 958
36.7.2
Trigger priority and multiplexing ............................................................................................................... 959
36.7.3
Conversion LIST .........................................................................................................................................961
36.7.4
ADC conversion results access ................................................................................................................... 963
36.7.5
Trigger clearing mechanism.........................................................................................................................964
36.7.6
On-the-fly reconfiguration of BCTU registers ............................................................................................965
36.7.7
Multiple Parallel Conversions .....................................................................................................................966
Interrupts and DMA requests .......................................................................................................................................967
Chapter 37
Configurable Enhanced Modular IO Subsystem (eMIOS)
37.1
37.2
37.3
Chip-specific eMIOS information................................................................................................................................ 969
37.1.1
eMIOS configuration .................................................................................................................................. 969
37.1.2
Channel types............................................................................................................................................... 969
37.1.3
DMA channel configuration........................................................................................................................ 971
37.1.4
Channel configuration..................................................................................................................................972
37.1.5
eMIOS disabling.......................................................................................................................................... 972
37.1.6
Serialization................................................................................................................................................. 973
37.1.7
BCTU Interface............................................................................................................................................978
37.1.8
EMIOS register reset value.......................................................................................................................... 978
Introduction...................................................................................................................................................................978
37.2.1
Overview...................................................................................................................................................... 978
37.2.2
Features........................................................................................................................................................ 979
37.2.3
Modes of operation...................................................................................................................................... 980
Memory map / register definition................................................................................................................................. 981
37.3.1
37.4
Memory map................................................................................................................................................ 981
Control Memory Map and Registers.............................................................................................................................982
37.4.1
eMIOS Module Configuration Register (eMIOS_MCR)............................................................................ 983
37.4.2
eMIOS Global FLAG Register (eMIOS_GFLAG)..................................................................................... 985
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37.5
37.6
37.7
Title
Page
37.4.3
eMIOS Output Update Disable register (eMIOS_OUDIS)......................................................................... 985
37.4.4
eMIOS Disable Channel register (eMIOS_UCDIS).................................................................................... 986
Unified Channels Memory Map and Registers.............................................................................................................986
37.5.1
eMIOS UC A register n (eMIOS_An)......................................................................................................... 992
37.5.2
eMIOS UC B register n (eMIOS_Bn)..........................................................................................................993
37.5.3
eMIOS CNT register n (eMIOS_CNTn)..................................................................................................... 994
37.5.4
eMIOS UC Control register n (eMIOS_Cn)................................................................................................ 995
37.5.5
eMIOS UC Status register n (eMIOS_Sn)................................................................................................... 1001
37.5.6
eMIOS Alternate Address register n (eMIOS_ALTAn)..............................................................................1002
37.5.7
eMIOS UC Control 2 register n (eMIOS_C2_n)......................................................................................... 1003
Functional Description..................................................................................................................................................1004
37.6.1
Unified Channel (UC).................................................................................................................................. 1006
37.6.2
IP Bus Interface Unit (BIU)......................................................................................................................... 1045
37.6.3
Global Clock Prescaler Submodule (GCP).................................................................................................. 1046
Initialization/Application Information.......................................................................................................................... 1046
37.7.1
Considerations..............................................................................................................................................1046
37.7.2
Application Information...............................................................................................................................1047
Chapter 38
Power Control Unit (MC_PCU)
38.1
Introduction...................................................................................................................................................................1051
38.1.1
Overview...................................................................................................................................................... 1051
38.1.2
Features........................................................................................................................................................ 1052
Chapter 39
Power Management Controller digital interface (PMCDIG)
39.1
Overview.......................................................................................................................................................................1053
39.2
Features......................................................................................................................................................................... 1053
39.3
Memory Map and Registers..........................................................................................................................................1054
39.3.1
RAM Domain Configuration Register (PMCDIG_RDCR).........................................................................1054
39.3.2
Supply Gauge Status Register (PMCDIG_SGSR).......................................................................................1055
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Section number
39.3.3
39.4
Title
Page
MISC Control Register (PMCDIG_MCR).................................................................................................. 1059
Functional description...................................................................................................................................................1060
39.4.1
Analog PMC interface................................................................................................................................. 1061
39.4.2
Power-up Sequence......................................................................................................................................1061
Chapter 40
Mode Entry Module (MC_ME)
40.1
Introduction...................................................................................................................................................................1063
40.1.1
Overview...................................................................................................................................................... 1063
40.1.2
Features........................................................................................................................................................ 1065
40.1.3
Use Cases..................................................................................................................................................... 1065
40.1.4
Modes of Operation..................................................................................................................................... 1072
40.2
External Signal Description.......................................................................................................................................... 1074
40.3
Memory Map and Register Definition..........................................................................................................................1074
40.3.1
Global Status Register (MC_ME_GS).........................................................................................................1079
40.3.2
Mode Control Register (MC_ME_MCTL)..................................................................................................1082
40.3.3
Mode Enable Register (MC_ME_ME)........................................................................................................ 1084
40.3.4
Interrupt Status Register (MC_ME_IS)....................................................................................................... 1086
40.3.5
Interrupt Mask Register (MC_ME_IM).......................................................................................................1087
40.3.6
Invalid Mode Transition Status Register (MC_ME_IMTS)........................................................................ 1089
40.3.7
Debug Mode Transition Status Register (MC_ME_DMTS)....................................................................... 1091
40.3.8
RESET Mode Configuration Register (MC_ME_RESET_MC)................................................................. 1096
40.3.9
SAFE Mode Configuration Register (MC_ME_SAFE_MC)...................................................................... 1098
40.3.10
DRUN Mode Configuration Register (MC_ME_DRUN_MC)...................................................................1100
40.3.11
RUN0 Mode Configuration Register (MC_ME_RUN0_MC).....................................................................1103
40.3.12
RUN1 Mode Configuration Register (MC_ME_RUN1_MC).....................................................................1105
40.3.13
RUN2 Mode Configuration Register (MC_ME_RUN2_MC).....................................................................1108
40.3.14
RUN3 Mode Configuration Register (MC_ME_RUN3_MC).....................................................................1110
40.3.15
STOP0 Mode Configuration Register (MC_ME_STOP_MC).................................................................... 1112
40.3.16
STANDBY0 Mode Configuration Register (MC_ME_STANDBY_MC)..................................................1115
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40.3.17
Peripheral Status Register 0 (MC_ME_PS0)...............................................................................................1117
40.3.18
Peripheral Status Register 1 (MC_ME_PS1)...............................................................................................1120
40.3.19
Peripheral Status Register 2 (MC_ME_PS2)...............................................................................................1122
40.3.20
Peripheral Status Register 3 (MC_ME_PS3)...............................................................................................1124
40.3.21
Run Peripheral Configuration Register (MC_ME_RUN_PCn)...................................................................1126
40.3.22
Low-Power Peripheral Configuration Register (MC_ME_LP_PCn).......................................................... 1127
40.3.23
BCTU Peripheral Control Register (MC_ME_PCTL0).............................................................................. 1128
40.3.24
eMIOS_0 Peripheral Control Register (MC_ME_PCTL1)......................................................................... 1129
40.3.25
eMIOS_1 Peripheral Control Register (MC_ME_PCTL2)......................................................................... 1130
40.3.26
SAI0 Peripheral Control Register (MC_ME_PCTL10)...............................................................................1131
40.3.27
SAI1 Peripheral Control Register (MC_ME_PCTL11)...............................................................................1132
40.3.28
SAI2 Peripheral Control Register (MC_ME_PCTL12)...............................................................................1133
40.3.29
ENET Peripheral Control Register (MC_ME_PCTL15).............................................................................1134
40.3.30
CMP_0 Peripheral Control Register (MC_ME_PCTL20)...........................................................................1135
40.3.31
CMP_1 Peripheral Control Register (MC_ME_PCTL21)...........................................................................1136
40.3.32
CMP_2 Peripheral Control Register (MC_ME_PCTL22)...........................................................................1137
40.3.33
ADC_0 Peripheral Control Register (MC_ME_PCTL24)...........................................................................1138
40.3.34
ADC_1 Peripheral Control Register (MC_ME_PCTL25)...........................................................................1139
40.3.35
FlexRay Peripheral Control Register (MC_ME_PCTL28)......................................................................... 1140
40.3.36
IIC_0 Peripheral Control Register (MC_ME_PCTL30)..............................................................................1141
40.3.37
IIC_1 Peripheral Control Register (MC_ME_PCTL31)..............................................................................1142
40.3.38
IIC_2 Peripheral Control Register (MC_ME_PCTL32)..............................................................................1143
40.3.39
IIC_3 Peripheral Control Register (MC_ME_PCTL33)..............................................................................1144
40.3.40
DSPI_0 Peripheral Control Register (MC_ME_PCTL40).......................................................................... 1145
40.3.41
DSPI_1 Peripheral Control Register (MC_ME_PCTL41).......................................................................... 1146
40.3.42
DSPI_2 Peripheral Control Register (MC_ME_PCTL42).......................................................................... 1147
40.3.43
DSPI_3 Peripheral Control Register (MC_ME_PCTL43).......................................................................... 1148
40.3.44
LIN_0 Peripheral Control Register (MC_ME_PCTL50)............................................................................ 1149
40.3.45
LIN_1 Peripheral Control Register (MC_ME_PCTL51)............................................................................ 1150
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40.3.46
LIN_2 Peripheral Control Register (MC_ME_PCTL52)............................................................................ 1151
40.3.47
LIN_3 Peripheral Control Register (MC_ME_PCTL53)............................................................................ 1152
40.3.48
LIN_4 Peripheral Control Register (MC_ME_PCTL54)............................................................................ 1153
40.3.49
LIN_5 Peripheral Control Register (MC_ME_PCTL55)............................................................................ 1154
40.3.50
LIN_6 Peripheral Control Register (MC_ME_PCTL56)............................................................................ 1155
40.3.51
LIN_7 Peripheral Control Register (MC_ME_PCTL57)............................................................................ 1156
40.3.52
LIN 8 Peripheral Control Register (MC_ME_PCTL58)............................................................................. 1157
40.3.53
LIN_9 Peripheral Control Register (MC_ME_PCTL59)............................................................................ 1158
40.3.54
LIN_10 Peripheral Control Register (MC_ME_PCTL60).......................................................................... 1159
40.3.55
LIN_11 Peripheral Control Register (MC_ME_PCTL61).......................................................................... 1160
40.3.56
LIN 12 Peripheral Control Register (MC_ME_PCTL62)........................................................................... 1161
40.3.57
LIN_13 Peripheral Control Register (MC_ME_PCTL63).......................................................................... 1162
40.3.58
LIN 14 Peripheral Control Register (MC_ME_PCTL64)........................................................................... 1163
40.3.59
LIN_15 Peripheral Control Register (MC_ME_PCTL65).......................................................................... 1164
40.3.60
FLEXCAN_0 Peripheral Control Register (MC_ME_PCTL70).................................................................1165
40.3.61
FLEXCAN_1 Peripheral Control Register (MC_ME_PCTL71).................................................................1166
40.3.62
FLEXCAN_2 Peripheral Control Register (MC_ME_PCTL72).................................................................1167
40.3.63
FLEXCAN_3 Peripheral Control Register (MC_ME_PCTL73).................................................................1168
40.3.64
FLEXCAN_4 Peripheral Control Register (MC_ME_PCTL74).................................................................1169
40.3.65
FLEXCAN_5 Peripheral Control Register (MC_ME_PCTL75).................................................................1170
40.3.66
FLEXCAN_6 Peripheral Control Register (MC_ME_PCTL76).................................................................1171
40.3.67
FLEXCAN_7 Peripheral Control Register (MC_ME_PCTL77).................................................................1172
40.3.68
JDC Control Register (MC_ME_PCTL82)................................................................................................. 1173
40.3.69
MEMU_0 Control Register (MC_ME_PCTL83)........................................................................................ 1174
40.3.70
CRC Control Register (MC_ME_PCTL84)................................................................................................ 1175
40.3.71
DMAMUX Control Register (MC_ME_PCTL90)......................................................................................1176
40.3.72
PIT_RTI_0 Control Register (MC_ME_PCTL91)...................................................................................... 1177
40.3.73
WKPU Control Register (MC_ME_PCTL93).............................................................................................1178
40.3.74
SPI0 Control Register (MC_ME_PCTL96).................................................................................................1179
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40.4
Title
Page
40.3.75
SPI1 Control Register (MC_ME_PCTL97).................................................................................................1180
40.3.76
SPI2 Control Register (MC_ME_PCTL98).................................................................................................1181
40.3.77
SPI3 Control Register (MC_ME_PCTL99).................................................................................................1182
40.3.78
RTC-API Control Register (MC_ME_PCTL102)....................................................................................... 1183
40.3.79
MEMU_1 Control Register (MC_ME_PCTL105)...................................................................................... 1184
40.3.80
Core Status Register (MC_ME_CS)............................................................................................................ 1186
40.3.81
Core1 Control Register (MC_ME_CCTL1)................................................................................................ 1187
40.3.82
Core3 Control Register (MC_ME_CCTL3)................................................................................................ 1188
40.3.83
CORE1 Address Register (MC_ME_CADDR1).........................................................................................1190
40.3.84
CORE3 Address Register (MC_ME_CADDR3).........................................................................................1191
Functional Description..................................................................................................................................................1192
40.4.1
Mode Transition Request............................................................................................................................. 1192
40.4.2
Modes Details.............................................................................................................................................. 1193
40.4.3
Mode Transition Process..............................................................................................................................1199
40.4.4
Software Considerations for Preventing the Blocking of Mode Transitions............................................... 1212
40.4.5
Protection of Mode Configuration Registers............................................................................................... 1214
40.4.6
Mode Transition Interrupts.......................................................................................................................... 1215
40.4.7
Peripheral Clock Gating...............................................................................................................................1218
40.4.8
Initialization/Application Example.............................................................................................................. 1219
Chapter 41
General Programmable Registers (GPR)
41.1
Overview.......................................................................................................................................................................1223
41.2
Memory map and register definition.............................................................................................................................1223
41.2.1
GPR Control Register (GPR_CTL)............................................................................................................. 1224
41.2.2
GPR Status Register (GPR_STAT)............................................................................................................. 1227
41.2.3
GPR Control Register1 (GPR_CTL1)......................................................................................................... 1228
41.2.4
GPR SLEEP Register (GPR_SLEEP)..........................................................................................................1228
Chapter 42
Deserial Serial Peripheral Interface (DSPI)
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Section number
42.1
42.2
42.3
42.4
Title
Page
Chip-specific DSPI information................................................................................................................................... 1231
42.1.1
DSPI and SPI configuration......................................................................................................................... 1231
42.1.2
DSPI configuration...................................................................................................................................... 1231
42.1.3
SPI configuration......................................................................................................................................... 1232
42.1.4
DSPI and SPI registers................................................................................................................................. 1232
42.1.5
DSPI's stop-stop ack protocol...................................................................................................................... 1234
Introduction...................................................................................................................................................................1234
42.2.1
Block Diagram............................................................................................................................................. 1234
42.2.2
Features........................................................................................................................................................ 1235
42.2.3
Interface configurations............................................................................................................................... 1238
42.2.4
Modes of Operation..................................................................................................................................... 1239
Module signal descriptions........................................................................................................................................... 1241
42.3.1
HT—Hardware Trigger................................................................................................................................1242
42.3.2
PCS0/SS—Peripheral Chip Select/Slave Select.......................................................................................... 1242
42.3.3
PCS1–PCS3—Peripheral Chip Selects 1–3................................................................................................. 1242
42.3.4
PCS4/MTRIG—Peripheral Chip Select 4/Master Trigger.......................................................................... 1243
42.3.5
PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe.......................................................1243
42.3.6
SCK—Serial Clock...................................................................................................................................... 1243
42.3.7
SIN—Serial Input........................................................................................................................................ 1243
42.3.8
SOUT—Serial Output..................................................................................................................................1243
Memory Map/Register Definition.................................................................................................................................1244
42.4.1
Module Configuration Register (DSPI_MCR)............................................................................................ 1247
42.4.2
Transfer Count Register (DSPI_TCR)......................................................................................................... 1250
42.4.3
Clock and Transfer Attributes Register (In Master Mode) (DSPI_CTARn)............................................... 1251
42.4.4
Clock and Transfer Attributes Register (In Slave Mode) (DSPI_CTARn_SLAVE).................................. 1256
42.4.5
Status Register (DSPI_SR).......................................................................................................................... 1258
42.4.6
DMA/Interrupt Request Select and Enable Register (DSPI_RSER)........................................................... 1262
42.4.7
PUSH TX FIFO Register In Master Mode (DSPI_PUSHR)....................................................................... 1265
42.4.8
PUSH TX FIFO Register In Slave Mode (DSPI_PUSHR_SLAVE).......................................................... 1267
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Title
Page
42.4.9
POP RX FIFO Register (DSPI_POPR)....................................................................................................... 1268
42.4.10
Transmit FIFO Registers (DSPI_TXFRn)................................................................................................... 1268
42.4.11
Receive FIFO Registers (DSPI_RXFRn).................................................................................................... 1269
42.4.12
DSI Configuration Register 0 (DSPI_DSICR0).......................................................................................... 1270
42.4.13
DSI Serialization Data Register 0 (DSPI_SDR0)........................................................................................ 1273
42.4.14
DSI Alternate Serialization Data Register 0 (DSPI_ASDR0)..................................................................... 1273
42.4.15
DSI Transmit Comparison Register 0 (DSPI_COMPR0)............................................................................1274
42.4.16
DSI Deserialization Data Register 0 (DSPI_DDR0)................................................................................... 1274
42.4.17
DSI Configuration Register 1 (DSPI_DSICR1).......................................................................................... 1275
42.4.18
DSI Serialization Source Select Register 0 (DSPI_SSR0).......................................................................... 1277
42.4.19
DSI Parallel Input Select Register 0 (DSPI_PISR0)....................................................................................1277
42.4.20
DSI Parallel Input Select Register 1 (DSPI_PISR1)....................................................................................1278
42.4.21
DSI Parallel Input Select Register 2 (DSPI_PISR2)....................................................................................1279
42.4.22
DSI Parallel Input Select Register 3 (DSPI_PISR3)....................................................................................1280
42.4.23
DSI Deserialized Data Interrupt Mask Register 0 (DSPI_DIMR0).............................................................1281
42.4.24
DSI Deserialized Data Polarity Interrupt Register 0 (DSPI_DPIR0).......................................................... 1281
42.4.25
DSI Serialization Data Register 1 (DSPI_SDR1)........................................................................................ 1282
42.4.26
DSI Alternate Serialization Data Register 1 (DSPI_ASDR1)..................................................................... 1283
42.4.27
DSI Transmit Comparison Register 1 (DSPI_COMPR1)............................................................................1283
42.4.28
DSI Deserialization Data Register 1 (DSPI_DDR1)................................................................................... 1284
42.4.29
DSI Serialization Source Select Register 1 (DSPI_SSR1).......................................................................... 1285
42.4.30
DSI Parallel Input Select Register 4 (DSPI_PISR4)....................................................................................1285
42.4.31
DSI Parallel Input Select Register 5 (DSPI_PISR5)....................................................................................1286
42.4.32
DSI Parallel Input Select Register 6 (DSPI_PISR6)....................................................................................1287
42.4.33
DSI Parallel Input Select Register 7 (DSPI_PISR7)....................................................................................1288
42.4.34
DSI Deserialized Data Interrupt Mask Register 1 (DSPI_DIMR1).............................................................1289
42.4.35
DSI Deserialized Data Polarity Interrupt Register 1 (DSPI_DPIR1).......................................................... 1290
42.4.36
Clock and Transfer Attributes Register Extended (DSPI_CTAREn).......................................................... 1290
42.4.37
Status Register Extended (DSPI_SREX)..................................................................................................... 1292
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Section number
42.5
42.6
Title
Page
42.4.38
Trigger Register (DSPI_TRIG)....................................................................................................................1293
42.4.39
Time Slot Length Register (DSPI_TSL)......................................................................................................1294
42.4.40
Time Slot Configuration Register (DSPI_TS_CONF)................................................................................ 1295
Functional description...................................................................................................................................................1297
42.5.1
Start and Stop of module transfers............................................................................................................... 1298
42.5.2
Serial Peripheral Interface (SPI) configuration............................................................................................1299
42.5.3
Deserial Serial Interface (DSI) Configuration............................................................................................. 1304
42.5.4
Combined Serial Interface (CSI) Configuration.......................................................................................... 1314
42.5.5
Module baud rate and clock delay generation............................................................................................. 1316
42.5.6
Transfer formats........................................................................................................................................... 1319
42.5.7
Continuous Serial Communications Clock.................................................................................................. 1331
42.5.8
Slave Mode Operation Constraints.............................................................................................................. 1333
42.5.9
Timed Serial Bus (TSB)...............................................................................................................................1333
42.5.10
Interleaved TSB (ITSB) Mode.....................................................................................................................1336
42.5.11
Parity Generation and Check....................................................................................................................... 1345
42.5.12
Interrupts/DMA requests..............................................................................................................................1346
42.5.13
Power saving features.................................................................................................................................. 1351
Initialization/application information........................................................................................................................... 1352
42.6.1
How to manage queues................................................................................................................................ 1352
42.6.2
Switching Master and Slave mode...............................................................................................................1353
42.6.3
Initializing Module in Master/Slave Modes.................................................................................................1353
42.6.4
Baud rate settings......................................................................................................................................... 1353
42.6.5
Delay settings............................................................................................................................................... 1354
42.6.6
Calculation of FIFO pointer addresses.........................................................................................................1355
Chapter 43
Ethernet MAC (ENET)
43.1
Chip-specific ENET information..................................................................................................................................1359
43.1.1
ENET Configuration.................................................................................................................................... 1359
43.1.2
ENET Interrupt mapping............................................................................................................................. 1359
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Title
Page
43.1.3
ENET's stop-stop ack protocol.....................................................................................................................1360
43.1.4
Recieve Parser Match Array Table Depth................................................................................................... 1360
43.2
Introduction...................................................................................................................................................................1361
43.3
Overview.......................................................................................................................................................................1361
43.3.1
Features........................................................................................................................................................ 1361
43.3.2
Block diagram.............................................................................................................................................. 1364
43.4
External signal description............................................................................................................................................1365
43.5
Memory map/register definition................................................................................................................................... 1367
43.5.1
Interrupt Event Register (ENET_EIR).........................................................................................................1374
43.5.2
Interrupt Mask Register (ENET_EIMR)......................................................................................................1377
43.5.3
Receive Descriptor Active Register - Ring 0 (ENET_RDAR)....................................................................1381
43.5.4
Transmit Descriptor Active Register - Ring 0 (ENET_TDAR).................................................................. 1382
43.5.5
Ethernet Control Register (ENET_ECR)..................................................................................................... 1383
43.5.6
MII Management Frame Register (ENET_MMFR).................................................................................... 1385
43.5.7
MII Speed Control Register (ENET_MSCR).............................................................................................. 1386
43.5.8
MIB Control Register (ENET_MIBC)........................................................................................................ 1388
43.5.9
Receive Control Register (ENET_RCR)..................................................................................................... 1389
43.5.10
Transmit Control Register (ENET_TCR).................................................................................................... 1392
43.5.11
Physical Address Lower Register (ENET_PALR)...................................................................................... 1394
43.5.12
Physical Address Upper Register (ENET_PAUR)...................................................................................... 1394
43.5.13
Opcode/Pause Duration Register (ENET_OPD)......................................................................................... 1395
43.5.14
Transmit Interrupt Coalescing Register (ENET_TXICn)............................................................................ 1395
43.5.15
Receive Interrupt Coalescing Register (ENET_RXICn)............................................................................. 1396
43.5.16
Descriptor Individual Upper Address Register (ENET_IAUR).................................................................. 1397
43.5.17
Descriptor Individual Lower Address Register (ENET_IALR).................................................................. 1398
43.5.18
Descriptor Group Upper Address Register (ENET_GAUR)....................................................................... 1398
43.5.19
Descriptor Group Lower Address Register (ENET_GALR)....................................................................... 1399
43.5.20
Transmit FIFO Watermark Register (ENET_TFWR)................................................................................. 1399
43.5.21
Receive Descriptor Ring 1 Start Register (ENET_RDSR1)........................................................................ 1400
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Title
Page
43.5.22
Transmit Buffer Descriptor Ring 1 Start Register (ENET_TDSR1)........................................................... 1401
43.5.23
Maximum Receive Buffer Size Register - Ring 1 (ENET_MRBR1).......................................................... 1402
43.5.24
Receive Descriptor Ring 2 Start Register (ENET_RDSR2)........................................................................ 1403
43.5.25
Transmit Buffer Descriptor Ring 2 Start Register (ENET_TDSR2)........................................................... 1403
43.5.26
Maximum Receive Buffer Size Register - Ring 2 (ENET_MRBR2).......................................................... 1404
43.5.27
Receive Descriptor Ring 0 Start Register (ENET_RDSR).......................................................................... 1405
43.5.28
Transmit Buffer Descriptor Ring 0 Start Register (ENET_TDSR)............................................................. 1406
43.5.29
Maximum Receive Buffer Size Register - Ring 0 (ENET_MRBR)............................................................ 1406
43.5.30
Receive FIFO Section Full Threshold (ENET_RSFL)................................................................................ 1407
43.5.31
Receive FIFO Section Empty Threshold (ENET_RSEM).......................................................................... 1408
43.5.32
Receive FIFO Almost Empty Threshold (ENET_RAEM).......................................................................... 1408
43.5.33
Receive FIFO Almost Full Threshold (ENET_RAFL)................................................................................1409
43.5.34
Transmit FIFO Section Empty Threshold (ENET_TSEM)......................................................................... 1409
43.5.35
Transmit FIFO Almost Empty Threshold (ENET_TAEM).........................................................................1410
43.5.36
Transmit FIFO Almost Full Threshold (ENET_TAFL).............................................................................. 1410
43.5.37
Transmit Inter-Packet Gap (ENET_TIPG).................................................................................................. 1411
43.5.38
Frame Truncation Length (ENET_FTRL)................................................................................................... 1411
43.5.39
Transmit Accelerator Function Configuration (ENET_TACC).................................................................. 1412
43.5.40
Receive Accelerator Function Configuration (ENET_RACC)....................................................................1413
43.5.41
Receive Classification Match Register for Class n (ENET_RCMRn)........................................................ 1415
43.5.42
DMA Class Based Configuration (ENET_DMAnCFG)............................................................................. 1416
43.5.43
Receive Descriptor Active Register - Ring 1 (ENET_RDAR1)..................................................................1418
43.5.44
Transmit Descriptor Active Register - Ring 1 (ENET_TDAR1)................................................................ 1418
43.5.45
Receive Descriptor Active Register - Ring 2 (ENET_RDAR2)..................................................................1420
43.5.46
Transmit Descriptor Active Register - Ring 2 (ENET_TDAR2)................................................................ 1421
43.5.47
QOS Scheme (ENET_QOS)........................................................................................................................ 1421
43.5.48
Reserved Statistic Register (ENET_RMON_T_DROP)..............................................................................1423
43.5.49
Tx Packet Count Statistic Register (ENET_RMON_T_PACKETS).......................................................... 1423
43.5.50
Tx Broadcast Packets Statistic Register (ENET_RMON_T_BC_PKT)......................................................1424
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43.5.51
Tx Multicast Packets Statistic Register (ENET_RMON_T_MC_PKT)......................................................1424
43.5.52
Tx Packets with CRC/Align Error Statistic Register (ENET_RMON_T_CRC_ALIGN).......................... 1425
43.5.53
Tx Packets Less Than Bytes and Good CRC Statistic Register (ENET_RMON_T_UNDERSIZE).......... 1425
43.5.54
Tx Packets GT MAX_FL bytes and Good CRC Statistic Register (ENET_RMON_T_OVERSIZE)........1426
43.5.55
Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_T_FRAG)................... 1426
43.5.56
Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register (ENET_RMON_T_JAB)...... 1427
43.5.57
Tx Collision Count Statistic Register (ENET_RMON_T_COL)................................................................ 1427
43.5.58
Tx 64-Byte Packets Statistic Register (ENET_RMON_T_P64)................................................................. 1428
43.5.59
Tx 65- to 127-byte Packets Statistic Register (ENET_RMON_T_P65TO127).......................................... 1428
43.5.60
Tx 128- to 255-byte Packets Statistic Register (ENET_RMON_T_P128TO255)...................................... 1429
43.5.61
Tx 256- to 511-byte Packets Statistic Register (ENET_RMON_T_P256TO511)...................................... 1429
43.5.62
Tx 512- to 1023-byte Packets Statistic Register (ENET_RMON_T_P512TO1023).................................. 1430
43.5.63
Tx 1024- to 2047-byte Packets Statistic Register (ENET_RMON_T_P1024TO2047).............................. 1430
43.5.64
Tx Packets Greater Than 2048 Bytes Statistic Register (ENET_RMON_T_P_GTE2048)........................ 1431
43.5.65
Tx Octets Statistic Register (ENET_RMON_T_OCTETS)........................................................................ 1431
43.5.66
Reserved Statistic Register (ENET_IEEE_T_DROP)................................................................................. 1431
43.5.67
Frames Transmitted OK Statistic Register (ENET_IEEE_T_FRAME_OK).............................................. 1432
43.5.68
Frames Transmitted with Single Collision Statistic Register (ENET_IEEE_T_1COL)............................. 1432
43.5.69
Frames Transmitted with Multiple Collisions Statistic Register (ENET_IEEE_T_MCOL).......................1433
43.5.70
Frames Transmitted after Deferral Delay Statistic Register (ENET_IEEE_T_DEF)..................................1433
43.5.71
Frames Transmitted with Late Collision Statistic Register (ENET_IEEE_T_LCOL)................................ 1434
43.5.72
Frames Transmitted with Excessive Collisions Statistic Register (ENET_IEEE_T_EXCOL)...................1434
43.5.73
Frames Transmitted with Tx FIFO Underrun Statistic Register (ENET_IEEE_T_MACERR).................. 1435
43.5.74
Frames Transmitted with Carrier Sense Error Statistic Register (ENET_IEEE_T_CSERR)..................... 1435
43.5.75
Reserved Statistic Register (ENET_IEEE_T_SQE).................................................................................... 1436
43.5.76
Flow Control Pause Frames Transmitted Statistic Register (ENET_IEEE_T_FDXFC).............................1436
43.5.77
Octet Count for Frames Transmitted w/o Error Statistic Register (ENET_IEEE_T_OCTETS_OK)......... 1437
43.5.78
Rx Packet Count Statistic Register (ENET_RMON_R_PACKETS).......................................................... 1437
43.5.79
Rx Broadcast Packets Statistic Register (ENET_RMON_R_BC_PKT)..................................................... 1438
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43.5.80
Rx Multicast Packets Statistic Register (ENET_RMON_R_MC_PKT)..................................................... 1438
43.5.81
Rx Packets with CRC/Align Error Statistic Register (ENET_RMON_R_CRC_ALIGN)..........................1439
43.5.82
Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register
(ENET_RMON_R_UNDERSIZE).............................................................................................................. 1439
43.5.83
Rx Packets Greater Than MAX_FL and Good CRC Statistic Register (ENET_RMON_R_OVERSIZE).1440
43.5.84
Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register (ENET_RMON_R_FRAG).................. 1440
43.5.85
Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register (ENET_RMON_R_JAB)..... 1441
43.5.86
Reserved Statistic Register (ENET_RMON_R_RESVD_0)....................................................................... 1441
43.5.87
Rx 64-Byte Packets Statistic Register (ENET_RMON_R_P64)................................................................. 1441
43.5.88
Rx 65- to 127-Byte Packets Statistic Register (ENET_RMON_R_P65TO127)......................................... 1442
43.5.89
Rx 128- to 255-Byte Packets Statistic Register (ENET_RMON_R_P128TO255)..................................... 1442
43.5.90
Rx 256- to 511-Byte Packets Statistic Register (ENET_RMON_R_P256TO511)..................................... 1443
43.5.91
Rx 512- to 1023-Byte Packets Statistic Register (ENET_RMON_R_P512TO1023)................................. 1443
43.5.92
Rx 1024- to 2047-Byte Packets Statistic Register (ENET_RMON_R_P1024TO2047)............................. 1444
43.5.93
Rx Packets Greater than 2048 Bytes Statistic Register (ENET_RMON_R_P_GTE2048)......................... 1444
43.5.94
Rx Octets Statistic Register (ENET_RMON_R_OCTETS)........................................................................ 1445
43.5.95
Frames not Counted Correctly Statistic Register (ENET_IEEE_R_DROP)............................................... 1445
43.5.96
Frames Received OK Statistic Register (ENET_IEEE_R_FRAME_OK).................................................. 1446
43.5.97
Frames Received with CRC Error Statistic Register (ENET_IEEE_R_CRC)............................................ 1446
43.5.98
Frames Received with Alignment Error Statistic Register (ENET_IEEE_R_ALIGN).............................. 1447
43.5.99
Receive FIFO Overflow Count Statistic Register (ENET_IEEE_R_MACERR)........................................1447
43.5.100 Flow Control Pause Frames Received Statistic Register (ENET_IEEE_R_FDXFC)................................. 1448
43.5.101 Octet Count for Frames Received without Error Statistic Register (ENET_IEEE_R_OCTETS_OK)....... 1448
43.5.102 Adjustable Timer Control Register (ENET_ATCR)................................................................................... 1448
43.5.103 Timer Value Register (ENET_ATVR)........................................................................................................ 1450
43.5.104 Timer Offset Register (ENET_ATOFF)...................................................................................................... 1451
43.5.105 Timer Period Register (ENET_ATPER)......................................................................................................1451
43.5.106 Timer Correction Register (ENET_ATCOR).............................................................................................. 1452
43.5.107 Time-Stamping Clock Period Register (ENET_ATINC)............................................................................ 1452
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43.5.108 Timestamp of Last Transmitted Frame (ENET_ATSTMP)........................................................................ 1453
43.5.109 Pattern Match Data Register (ENET_MDATA)..........................................................................................1453
43.5.110 Match Entry Mask Register (ENET_MMASK).......................................................................................... 1454
43.5.111 Match Entry Rules Configuration Register (ENET_MCONFIG)............................................................... 1454
43.5.112 Match Entry Read/Write Command Register (ENET_MENTRYRW)....................................................... 1455
43.5.113 Receive Parser Control Register (ENET_RXPCTL)................................................................................... 1456
43.5.114 Maximum Frame Offset (ENET_MAXFRMOFF)......................................................................................1458
43.5.115 Receive Parser Status (ENET_RXPARST)................................................................................................. 1459
43.5.116 Parser Discard Count (ENET_PARSDSCD)............................................................................................... 1460
43.5.117 Parser Accept Count 0 (ENET_PRSACPT0).............................................................................................. 1461
43.5.118 Parser Reject Count 0 (ENET_PRSRJCT0)................................................................................................ 1461
43.5.119 Parser Accept Count 1 (ENET_PRSACPT1).............................................................................................. 1462
43.5.120 Parser Reject Count 1 (ENET_PRSRJCT1)................................................................................................ 1462
43.5.121 Parser Accept Count 2 (ENET_PRSACPT2).............................................................................................. 1463
43.5.122 Parser Reject Count 2 (ENET_PRSRJCT2)................................................................................................ 1463
43.5.123 Timer Global Status Register (ENET_TGSR).............................................................................................1464
43.5.124 Timer Control Status Register (ENET_TCSRn)..........................................................................................1465
43.5.125 Timer Compare Capture Register (ENET_TCCRn).................................................................................... 1466
43.6
Functional description...................................................................................................................................................1467
43.6.1
Ethernet MAC frame formats...................................................................................................................... 1467
43.6.2
IP and higher layers frame format................................................................................................................1470
43.6.3
IEEE 1588 message formats........................................................................................................................ 1474
43.6.4
MAC receive................................................................................................................................................ 1478
43.6.5
MAC transmit.............................................................................................................................................. 1487
43.6.6
Full-duplex flow control operation.............................................................................................................. 1493
43.6.7
Magic packet detection................................................................................................................................ 1495
43.6.8
IP accelerator functions................................................................................................................................1496
43.6.9
Resets and stop controls............................................................................................................................... 1500
43.6.10
IEEE 1588 functions.................................................................................................................................... 1503
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43.6.11
FIFO thresholds............................................................................................................................................1507
43.6.12
Loopback options......................................................................................................................................... 1510
43.6.13
Legacy buffer descriptors.............................................................................................................................1511
43.6.14
Enhanced buffer descriptors.........................................................................................................................1512
43.6.15
Client FIFO application interface................................................................................................................ 1519
43.6.16
FIFO protection............................................................................................................................................1522
43.6.17
Reference clock............................................................................................................................................1524
43.6.18
PHY management interface......................................................................................................................... 1524
43.6.19
Ethernet interfaces........................................................................................................................................1527
43.6.20
AVB configuration.......................................................................................................................................1531
43.6.21
Interrupt coalescence....................................................................................................................................1532
Chapter 44
FlexCAN
44.1
44.2
44.3
44.4
Chip-specific FlexCAN information.............................................................................................................................1535
44.1.1
FlexCAN configuration................................................................................................................................1535
44.1.2
Requirements for entering FlexCAN modes: Freeze, Module Disable, Stop.............................................. 1536
44.1.3
External time tick......................................................................................................................................... 1538
44.1.4
FlexCAN's stop-stop ack protocol............................................................................................................... 1539
Introduction...................................................................................................................................................................1539
44.2.1
Overview...................................................................................................................................................... 1540
44.2.2
FlexCAN module features........................................................................................................................... 1541
44.2.3
Modes of operation...................................................................................................................................... 1543
FlexCAN signal descriptions........................................................................................................................................ 1545
44.3.1
CAN Rx .......................................................................................................................................................1545
44.3.2
CAN Tx .......................................................................................................................................................1545
Memory map/register definition................................................................................................................................... 1545
44.4.1
FlexCAN memory mapping.........................................................................................................................1545
44.4.2
Module Configuration Register (CAN_MCR)............................................................................................ 1554
44.4.3
Control 1 register (CAN_CTRL1)............................................................................................................... 1559
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44.4.4
Free Running Timer (CAN_TIMER).......................................................................................................... 1563
44.4.5
Rx Mailboxes Global Mask Register (CAN_RXMGMASK)..................................................................... 1564
44.4.6
Rx 14 Mask register (CAN_RX14MASK).................................................................................................. 1565
44.4.7
Rx 15 Mask register (CAN_RX15MASK).................................................................................................. 1566
44.4.8
Error Counter (CAN_ECR)......................................................................................................................... 1566
44.4.9
Error and Status 1 register (CAN_ESR1).................................................................................................... 1569
44.4.10
Interrupt Masks 2 register (CAN_IMASK2)............................................................................................... 1575
44.4.11
Interrupt Masks 1 register (CAN_IMASK1)............................................................................................... 1575
44.4.12
Interrupt Flags 2 register (CAN_IFLAG2).................................................................................................. 1576
44.4.13
Interrupt Flags 1 register (CAN_IFLAG1).................................................................................................. 1577
44.4.14
Control 2 register (CAN_CTRL2)............................................................................................................... 1580
44.4.15
Error and Status 2 register (CAN_ESR2).................................................................................................... 1583
44.4.16
CRC Register (CAN_CRCR).......................................................................................................................1585
44.4.17
Rx FIFO Global Mask register (CAN_RXFGMASK)................................................................................ 1585
44.4.18
Rx FIFO Information Register (CAN_RXFIR)........................................................................................... 1586
44.4.19
CAN Bit Timing Register (CAN_CBT)...................................................................................................... 1587
44.4.20
Interrupt Masks 3 Register (CAN_IMASK3).............................................................................................. 1589
44.4.21
Interrupt Flags 3 Register (CAN_IFLAG3).................................................................................................1590
44.4.22
Rx Individual Mask Registers (CAN_RXIMRn).........................................................................................1590
44.4.23
Pretended Networking Control 1 Register (CAN_CTRL1_PN)..................................................................1592
44.4.24
Pretended Networking Control 2 Register (CAN_CTRL2_PN)..................................................................1593
44.4.25
Pretended Networking Wake Up Match Register (CAN_WU_MTC)........................................................ 1594
44.4.26
Pretended Networking ID Filter 1 Register (CAN_FLT_ID1).................................................................... 1596
44.4.27
Pretended Networking DLC Filter Register (CAN_FLT_DLC)................................................................. 1597
44.4.28
Pretended Networking Payload Low Filter 1 Register (CAN_PL1_LO).................................................... 1598
44.4.29
Pretended Networking Payload High Filter 1 Register (CAN_PL1_HI).....................................................1598
44.4.30
Pretended Networking ID Filter 2 Register / ID Mask Register (CAN_FLT_ID2_IDMASK)...................1599
44.4.31
Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register
(CAN_PL2_PLMASK_LO)........................................................................................................................ 1600
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44.4.32
Title
Page
Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register
(CAN_PL2_PLMASK_HI)......................................................................................................................... 1601
44.5
44.6
44.4.33
Wake Up Message Buffer Register for C/S (CAN_WMBn_CS)................................................................ 1601
44.4.34
Wake Up Message Buffer Register for ID (CAN_WMBn_ID)...................................................................1602
44.4.35
Wake Up Message Buffer Register for Data 0-3 (CAN_WMBn_D03)...................................................... 1603
44.4.36
Wake Up Message Buffer Register Data 4-7 (CAN_WMBn_D47)............................................................1604
44.4.37
CAN FD Control Register (CAN_FDCTRL).............................................................................................. 1604
44.4.38
CAN FD Bit Timing Register (CAN_FDCBT)........................................................................................... 1608
44.4.39
CAN FD CRC Register (CAN_FDCRC).....................................................................................................1610
44.4.40
Message buffer structure.............................................................................................................................. 1612
44.4.41
FlexCAN Memory Partition for CAN FD................................................................................................... 1618
44.4.42
FlexCAN message buffer memory map.......................................................................................................1620
44.4.43
Rx FIFO structure........................................................................................................................................ 1626
Functional description...................................................................................................................................................1628
44.5.1
Transmit process.......................................................................................................................................... 1629
44.5.2
Arbitration process....................................................................................................................................... 1630
44.5.3
Receive process............................................................................................................................................1634
44.5.4
Matching process......................................................................................................................................... 1636
44.5.5
Receive Process under Pretended Networking Mode.................................................................................. 1641
44.5.6
Move process............................................................................................................................................... 1646
44.5.7
Data coherence............................................................................................................................................. 1647
44.5.8
Rx FIFO....................................................................................................................................................... 1651
44.5.9
CAN protocol related features..................................................................................................................... 1654
44.5.10
Clock domains and restrictions.................................................................................................................... 1675
44.5.11
Modes of operation details........................................................................................................................... 1680
44.5.12
Interrupts...................................................................................................................................................... 1684
44.5.13
Bus interface................................................................................................................................................ 1685
Initialization/application information........................................................................................................................... 1686
44.6.1
FlexCAN initialization sequence................................................................................................................. 1686
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Page
Chapter 45
Inter-Integrated Circuit (I2C)
45.1
Chip-specific I2C information...................................................................................................................................... 1689
45.1.1
I2C configurations........................................................................................................................................1689
45.2
Overview.......................................................................................................................................................................1689
45.3
Introduction to I2C........................................................................................................................................................1689
45.4
45.5
45.6
45.3.1
Definition: I2C module................................................................................................................................ 1690
45.3.2
Advantages of the I2C bus........................................................................................................................... 1690
45.3.3
Module block diagram................................................................................................................................. 1690
45.3.4
Features........................................................................................................................................................ 1691
45.3.5
Modes of operation...................................................................................................................................... 1692
45.3.6
Definition: I2C conditions........................................................................................................................... 1693
External signal descriptions.......................................................................................................................................... 1694
45.4.1
Signal overview............................................................................................................................................1694
45.4.2
Detailed external signal descriptions........................................................................................................... 1694
Memory map and register definition.............................................................................................................................1694
45.5.1
Register accessibility....................................................................................................................................1695
45.5.2
Register figure conventions......................................................................................................................... 1695
45.5.3
I2C Bus Address Register (I2C_IBAD).......................................................................................................1696
45.5.4
I2C Bus Frequency Divider Register (I2C_IBFD)...................................................................................... 1697
45.5.5
I2C Bus Control Register (I2C_IBCR)........................................................................................................ 1697
45.5.6
I2C Bus Status Register (I2C_IBSR)...........................................................................................................1699
45.5.7
I2C Bus Data I/O Register (I2C_IBDR)...................................................................................................... 1700
45.5.8
I2C Bus Interrupt Config Register (I2C_IBIC)........................................................................................... 1701
45.5.9
I2C Bus Debug Register (I2C_IBDBG)...................................................................................................... 1702
Functional description...................................................................................................................................................1703
45.6.1
Notes about module operation..................................................................................................................... 1703
45.6.2
Transactions................................................................................................................................................. 1703
45.6.3
Arbitration procedure................................................................................................................................... 1707
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45.7
Title
Page
45.6.4
Clock behavior............................................................................................................................................. 1708
45.6.5
Interrupts...................................................................................................................................................... 1715
45.6.6
STOP mode.................................................................................................................................................. 1716
45.6.7
DEBUG mode.............................................................................................................................................. 1717
45.6.8
DMA interface............................................................................................................................................. 1719
Initialization/application information........................................................................................................................... 1720
45.7.1
Recommended interrupt service flow.......................................................................................................... 1720
45.7.2
General programming guidelines (for both master and slave mode)...........................................................1721
45.7.3
Programming guidelines specific to master mode....................................................................................... 1723
45.7.4
Programming guidelines specific to slave mode..........................................................................................1727
45.7.5
DMA application information......................................................................................................................1727
Chapter 46
LINFlexD
46.1
46.2
46.3
46.4
46.5
Chip-specific LINFlexD information........................................................................................................................... 1735
46.1.1
LINFlexD configurations............................................................................................................................. 1735
46.1.2
LinflexD's stop-stop ack protocol................................................................................................................ 1736
Introduction...................................................................................................................................................................1736
46.2.1
Glossary and acronyms................................................................................................................................ 1736
46.2.2
References.................................................................................................................................................... 1737
Main features................................................................................................................................................................ 1739
46.3.1
LIN mode features....................................................................................................................................... 1739
46.3.2
UART mode features................................................................................................................................... 1740
Functional description...................................................................................................................................................1741
46.4.1
LIN protocol.................................................................................................................................................1741
46.4.2
LINFlexD features....................................................................................................................................... 1743
46.4.3
Timer............................................................................................................................................................ 1763
46.4.4
UART mode................................................................................................................................................. 1763
46.4.5
DMA interface............................................................................................................................................. 1769
Memory map and register description.......................................................................................................................... 1787
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46.6
Title
Page
46.5.1
LIN Control Register 1 (LINFlexD_LINCR1)............................................................................................ 1789
46.5.2
LIN Interrupt enable register (LINFlexD_LINIER).................................................................................... 1792
46.5.3
LIN Status Register (LINFlexD_LINSR).................................................................................................... 1794
46.5.4
LIN Error Status Register (LINFlexD_LINESR)........................................................................................ 1798
46.5.5
UART Mode Control Register (LINFlexD_UARTCR).............................................................................. 1800
46.5.6
UART Mode Status Register (LINFlexD_UARTSR)................................................................................. 1806
46.5.7
LIN Time-Out Control Status Register (LINFlexD_LINTCSR)................................................................. 1808
46.5.8
LIN Output Compare Register (LINFlexD_LINOCR)................................................................................1810
46.5.9
LIN Time-Out Control Register (LINFlexD_LINTOCR)........................................................................... 1811
46.5.10
LIN Fractional Baud Rate Register (LINFlexD_LINFBRR)...................................................................... 1811
46.5.11
LIN Integer Baud Rate Register (LINFlexD_LINIBRR)............................................................................ 1812
46.5.12
LIN Checksum Field Register (LINFlexD_LINCFR)................................................................................. 1813
46.5.13
LIN Control Register 2 (LINFlexD_LINCR2)............................................................................................ 1814
46.5.14
Buffer Identifier Register (LINFlexD_BIDR)............................................................................................. 1816
46.5.15
Buffer Data Register Least Significant (LINFlexD_BDRL)....................................................................... 1817
46.5.16
Buffer Data Register Most Significant (LINFlexD_BDRM)...................................................................... 1818
46.5.17
Identifier Filter Enable Register (LINFlexD_IFER)....................................................................................1818
46.5.18
Identifier Filter Match Index (LINFlexD_IFMI)......................................................................................... 1819
46.5.19
Identifier Filter Mode Register (LINFlexD_IFMR).................................................................................... 1819
46.5.20
Identifier Filter Control Register (LINFlexD_IFCRn)................................................................................ 1820
46.5.21
Global Control Register (LINFlexD_GCR).................................................................................................1821
46.5.22
UART Preset Timeout Register (LINFlexD_UARTPTO).......................................................................... 1823
46.5.23
UART Current Timeout Register (LINFlexD_UARTCTO)....................................................................... 1824
46.5.24
DMA Tx Enable Register (LINFlexD_DMATXE)..................................................................................... 1825
46.5.25
DMA Rx Enable Register (LINFlexD_DMARXE).....................................................................................1825
Programming considerations........................................................................................................................................ 1826
46.6.1
Master node..................................................................................................................................................1826
46.6.2
Slave node.................................................................................................................................................... 1828
46.6.3
Timeout........................................................................................................................................................ 1833
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46.6.4
UART mode................................................................................................................................................. 1834
46.6.5
Interrupts...................................................................................................................................................... 1835
46.6.6
LINFlexD Clock Tolerance......................................................................................................................... 1836
Chapter 47
FlexRay
47.1
47.2
47.3
Chip-specific FlexRay information...............................................................................................................................1839
47.1.1
FlexRay configuration..................................................................................................................................1839
47.1.2
Stop Watch interface.................................................................................................................................... 1839
Introduction...................................................................................................................................................................1839
47.2.1
Reference..................................................................................................................................................... 1839
47.2.2
Glossary....................................................................................................................................................... 1840
47.2.3
Overview...................................................................................................................................................... 1841
47.2.4
Features........................................................................................................................................................ 1843
47.2.5
Modes of Operation..................................................................................................................................... 1845
External Signal Description.......................................................................................................................................... 1847
47.3.1
Detailed Signal Descriptions........................................................................................................................1847
47.4
Controller Host Interface Clocking...............................................................................................................................1849
47.5
Protocol Engine Clocking............................................................................................................................................. 1849
47.6
47.7
47.5.1
Oscillator Clocking...................................................................................................................................... 1849
47.5.2
PLL Clocking............................................................................................................................................... 1849
Register Descriptions.................................................................................................................................................... 1850
47.6.1
Register Reset.............................................................................................................................................. 1850
47.6.2
Register Write Access.................................................................................................................................. 1851
Memory map and register definition.............................................................................................................................1852
47.7.1
Module Version Register (FR_MVR)..........................................................................................................1889
47.7.2
Module Configuration Register (FR_MCR)................................................................................................ 1889
47.7.3
System Memory Base Address High Register (FR_SYMBADHR)............................................................1892
47.7.4
System Memory Base Address Low Register (FR_SYMBADLR).............................................................1892
47.7.5
Strobe Signal Control Register (FR_STBSCR)........................................................................................... 1893
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47.7.6
Message Buffer Data Size Register (FR_MBDSR)..................................................................................... 1895
47.7.7
Message Buffer Segment Size and Utilization Register (FR_MBSSUTR)................................................. 1895
47.7.8
PE DRAM Access Register (FR_PEDRAR)............................................................................................... 1896
47.7.9
PE DRAM Data Register (FR_PEDRDR)...................................................................................................1897
47.7.10
Protocol Operation Control Register (FR_POCR).......................................................................................1898
47.7.11
Global Interrupt Flag and Enable Register (FR_GIFER)............................................................................ 1899
47.7.12
Protocol Interrupt Flag Register 0 (FR_PIFR0)...........................................................................................1902
47.7.13
Protocol Interrupt Flag Register 1 (FR_PIFR1)...........................................................................................1904
47.7.14
Protocol Interrupt Enable Register 0 (FR_PIER0)...................................................................................... 1906
47.7.15
Protocol Interrupt Enable Register 1 (FR_PIER1)...................................................................................... 1908
47.7.16
CHI Error Flag Register (FR_CHIERFR)................................................................................................... 1909
47.7.17
Message Buffer Interrupt Vector Register (FR_MBIVEC)......................................................................... 1912
47.7.18
Channel A Status Error Counter Register (FR_CASERCR)....................................................................... 1913
47.7.19
Channel B Status Error Counter Register (FR_CBSERCR)........................................................................1913
47.7.20
Protocol Status Register 0 (FR_PSR0)........................................................................................................ 1914
47.7.21
Protocol Status Register 1 (FR_PSR1)........................................................................................................ 1916
47.7.22
Protocol Status Register 2 (FR_PSR2)........................................................................................................ 1917
47.7.23
Protocol Status Register 3 (FR_PSR3)........................................................................................................ 1919
47.7.24
Macrotick Counter Register (FR_MTCTR).................................................................................................1921
47.7.25
Cycle Counter Register (FR_CYCTR)........................................................................................................ 1922
47.7.26
Slot Counter Channel A Register (FR_SLTCTAR).................................................................................... 1922
47.7.27
Slot Counter Channel B Register (FR_SLTCTBR)..................................................................................... 1923
47.7.28
Rate Correction Value Register (FR_RTCORVR)...................................................................................... 1923
47.7.29
Offset Correction Value Register (FR_OFCORVR)................................................................................... 1924
47.7.30
Combined Interrupt Flag Register (FR_CIFR)............................................................................................ 1925
47.7.31
System Memory Access Time-Out Register (FR_SYMATOR)..................................................................1926
47.7.32
Sync Frame Counter Register (FR_SFCNTR).............................................................................................1927
47.7.33
Sync Frame Table Offset Register (FR_SFTOR)........................................................................................ 1927
47.7.34
Sync Frame Table Configuration, Control, Status Register (FR_SFTCCSR)............................................. 1928
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47.7.35
Sync Frame ID Rejection Filter Register (FR_SFIDRFR).......................................................................... 1930
47.7.36
Sync Frame ID Acceptance Filter Value Register (FR_SFIDAFVR)......................................................... 1930
47.7.37
Sync Frame ID Acceptance Filter Mask Register (FR_SFIDAFMR)......................................................... 1931
47.7.38
Network Management Vector Register (FR_NMVRn)............................................................................... 1931
47.7.39
Network Management Vector Length Register (FR_NMVLR).................................................................. 1932
47.7.40
Timer Configuration and Control Register (FR_TICCR)............................................................................1932
47.7.41
Timer 1 Cycle Set Register (FR_TI1CYSR)............................................................................................... 1934
47.7.42
Timer 1 Macrotick Offset Register (FR_TI1MTOR).................................................................................. 1935
47.7.43
Timer 2 Configuration Register 0 (Absolute Timer Configuration) (FR_TI2CR0_ABS).......................... 1935
47.7.44
Timer 2 Configuration Register 0 (Relative Timer Configuration) (FR_TI2CR0_REL)............................1936
47.7.45
Timer 2 Configuration Register 1 (Absolute Timer Configuration) (FR_TI2CR1_ABS).......................... 1936
47.7.46
Timer 2 Configuration Register 1 (Relative Timer Configuration) (FR_TI2CR1_REL)............................1937
47.7.47
Slot Status Selection Register (FR_SSSR).................................................................................................. 1938
47.7.48
Slot Status Counter Condition Register (FR_SSCCR)................................................................................ 1939
47.7.49
Slot Status Register (FR_SSRn).................................................................................................................. 1941
47.7.50
Slot Status Counter Register (FR_SSCRn).................................................................................................. 1943
47.7.51
MTS A Configuration Register (FR_MTSACFR).......................................................................................1943
47.7.52
MTS B Configuration Register (FR_MTSBCFR)....................................................................................... 1944
47.7.53
Receive Shadow Buffer Index Register (FR_RSBIR)................................................................................. 1945
47.7.54
Receive FIFO Watermark and Selection Register (FR_RFWMSR)........................................................... 1946
47.7.55
Receive FIFO Start Index Register (FR_RFSIR)........................................................................................ 1947
47.7.56
Receive FIFO Depth and Size Register (FR_RFDSR)................................................................................ 1947
47.7.57
Receive FIFO A Read Index Register (FR_RFARIR).................................................................................1948
47.7.58
Receive FIFO B Read Index Register (FR_RFBRIR)................................................................................. 1948
47.7.59
Receive FIFO Message ID Acceptance Filter Value Register (FR_RFMIDAFVR)...................................1949
47.7.60
Receive FIFO Message ID Acceptance Filter Mask Register (FR_RFMIDAFMR)...................................1949
47.7.61
Receive FIFO Frame ID Rejection Filter Value Register (FR_RFFIDRFVR)........................................... 1950
47.7.62
Receive FIFO Frame ID Rejection Filter Mask Register (FR_RFFIDRFMR)........................................... 1950
47.7.63
Receive FIFO Range Filter Configuration Register (FR_RFRFCFR).........................................................1951
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47.7.64
Receive FIFO Range Filter Control Register (FR_RFRFCTR)...................................................................1952
47.7.65
Last Dynamic Transmit Slot Channel A Register (FR_LDTXSLAR)........................................................ 1953
47.7.66
Last Dynamic Transmit Slot Channel B Register (FR_LDTXSLBR).........................................................1954
47.7.67
Protocol Configuration Register 0 (FR_PCR0)........................................................................................... 1954
47.7.68
Protocol Configuration Register 1 (FR_PCR1)........................................................................................... 1957
47.7.69
Protocol Configuration Register 2 (FR_PCR2)........................................................................................... 1957
47.7.70
Protocol Configuration Register 3 (FR_PCR3)........................................................................................... 1958
47.7.71
Protocol Configuration Register 4 (FR_PCR4)........................................................................................... 1958
47.7.72
Protocol Configuration Register 5 (FR_PCR5)........................................................................................... 1959
47.7.73
Protocol Configuration Register 6 (FR_PCR6)........................................................................................... 1959
47.7.74
Protocol Configuration Register 7 (FR_PCR7)........................................................................................... 1960
47.7.75
Protocol Configuration Register 8 (FR_PCR8)........................................................................................... 1960
47.7.76
Protocol Configuration Register 9 (FR_PCR9)........................................................................................... 1961
47.7.77
Protocol Configuration Register 10 (FR_PCR10)....................................................................................... 1962
47.7.78
Protocol Configuration Register 11 (FR_PCR11)....................................................................................... 1962
47.7.79
Protocol Configuration Register 12 (FR_PCR12)....................................................................................... 1963
47.7.80
Protocol Configuration Register 13 (FR_PCR13)....................................................................................... 1964
47.7.81
Protocol Configuration Register 14 (FR_PCR14)....................................................................................... 1964
47.7.82
Protocol Configuration Register 15 (FR_PCR15)....................................................................................... 1965
47.7.83
Protocol Configuration Register 16 (FR_PCR16)....................................................................................... 1965
47.7.84
Protocol Configuration Register 17 (FR_PCR17)....................................................................................... 1966
47.7.85
Protocol Configuration Register 18 (FR_PCR18)....................................................................................... 1966
47.7.86
Protocol Configuration Register 19 (FR_PCR19)....................................................................................... 1967
47.7.87
Protocol Configuration Register 20 (FR_PCR20)....................................................................................... 1967
47.7.88
Protocol Configuration Register 21 (FR_PCR21)....................................................................................... 1968
47.7.89
Protocol Configuration Register 22 (FR_PCR22)....................................................................................... 1968
47.7.90
Protocol Configuration Register 23 (FR_PCR23)....................................................................................... 1969
47.7.91
Protocol Configuration Register 24 (FR_PCR24)....................................................................................... 1969
47.7.92
Protocol Configuration Register 25 (FR_PCR25)....................................................................................... 1970
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47.7.93
Protocol Configuration Register 26 (FR_PCR26)....................................................................................... 1970
47.7.94
Protocol Configuration Register 27 (FR_PCR27)....................................................................................... 1971
47.7.95
Protocol Configuration Register 28 (FR_PCR28)....................................................................................... 1972
47.7.96
Protocol Configuration Register 29 (FR_PCR29)....................................................................................... 1972
47.7.97
Protocol Configuration Register 30 (FR_PCR30)....................................................................................... 1973
47.7.98
StopWatch Count High Register (FR_STPWHR)....................................................................................... 1973
47.7.99
Stop Watch Count Low Register (FR_STPWLR)....................................................................................... 1974
47.7.100 Protocol Event Output Enable and StopWatch Control Register (FR_PEOER)......................................... 1974
47.7.101 Receive FIFO Start Data Offset Register (FR_RFSDOR)...........................................................................1975
47.7.102 Receive FIFO System Memory Base Address High Register (FR_RFSYMBADHR)............................... 1976
47.7.103 Receive FIFO System Memory Base Address Low Register (FR_RFSYMBADLR)................................ 1976
47.7.104 Receive FIFO Periodic Timer Register (FR_RFPTR)................................................................................. 1977
47.7.105 Receive FIFO Fill Level and POP Count Register (FR_RFFLPCR)...........................................................1977
47.7.106 ECC Error Interrupt Flag and Enable Register (FR_EEIFER).................................................................... 1979
47.7.107 ECC Error Report and Injection Control Register (FR_EERICR).............................................................. 1981
47.7.108 ECC Error Report Address Register (FR_EERAR).................................................................................... 1982
47.7.109 ECC Error Report Data Register (FR_EERDR).......................................................................................... 1983
47.7.110 ECC Error Report Code Register (FR_EERCR)......................................................................................... 1984
47.7.111 ECC Error Injection Address Register (FR_EEIAR).................................................................................. 1985
47.7.112 ECC Error Injection Data Register (FR_EEIDR)........................................................................................ 1985
47.7.113 ECC Error Injection Code Register (FR_EEICR)....................................................................................... 1986
47.7.114 Message Buffer Configuration, Control, Status Register (FR_MBCCSRn)............................................... 1986
47.7.115 Message Buffer Cycle Counter Filter Register (FR_MBCCFRn)............................................................... 1988
47.7.116 Message Buffer Frame ID Register (FR_MBFIDRn)..................................................................................1990
47.7.117 Message Buffer Index Register (FR_MBIDXRn)....................................................................................... 1990
47.7.118 Message Buffer Data Field Offset Register (FR_MBDORn)...................................................................... 1991
47.7.119 LRAM ECC Error Test Register (FR_LEETRn).........................................................................................1992
47.8
Functional Description..................................................................................................................................................1992
47.8.1
Message Buffer Concept.............................................................................................................................. 1992
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47.9
Title
Page
47.8.2
Physical Message Buffer..............................................................................................................................1992
47.8.3
Message Buffer Types................................................................................................................................. 1994
47.8.4
FlexRay Memory Area Layout.................................................................................................................... 2003
47.8.5
Physical Message Buffer Description.......................................................................................................... 2007
47.8.6
Individual Message Buffer Functional Description..................................................................................... 2017
47.8.7
Individual Message Buffer Search............................................................................................................... 2037
47.8.8
Individual Message Buffer Reconfiguration................................................................................................2040
47.8.9
Receive FIFOs..............................................................................................................................................2041
47.8.10
Channel Device Modes................................................................................................................................ 2050
47.8.11
External Clock Synchronization.................................................................................................................. 2052
47.8.12
Sync Frame ID and Sync Frame Deviation Tables......................................................................................2053
47.8.13
MTS Generation...........................................................................................................................................2057
47.8.14
Key Slot Transmission................................................................................................................................. 2057
47.8.15
Sync Frame Filtering....................................................................................................................................2058
47.8.16
Strobe Signal Support.................................................................................................................................. 2060
47.8.17
Timer Support.............................................................................................................................................. 2061
47.8.18
Slot Status Monitoring................................................................................................................................. 2063
47.8.19
System Bus Access...................................................................................................................................... 2067
47.8.20
Interrupt Support.......................................................................................................................................... 2069
47.8.21
Lower Bit Rate Support............................................................................................................................... 2074
47.8.22
PE Data Memory (PE DRAM).................................................................................................................... 2075
47.8.23
CHI Lookup-Table Memory (CHI LRAM)................................................................................................. 2077
47.8.24
Memory Content Fault Detection................................................................................................................ 2078
47.8.25
Memory Fault Injection............................................................................................................................... 2083
47.8.26
StopWatch function......................................................................................................................................2086
Application Information................................................................................................................................................2088
47.9.1
Module Configuration..................................................................................................................................2088
47.9.2
Initialization Sequence................................................................................................................................. 2089
47.9.3
Memory Fault Injection out of POC:default config.....................................................................................2091
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47.9.4
Shut Down Sequence................................................................................................................................... 2092
47.9.5
Number of Usable Message Buffers............................................................................................................ 2092
47.9.6
Protocol Control Command Execution........................................................................................................ 2093
47.9.7
Message Buffer Search On Simple Message Buffer Configuration............................................................ 2094
Chapter 48
Synchronous Audio Interface (SAI)
48.1
48.2
Chip-specific SAI information......................................................................................................................................2099
48.1.1
SAI configuration.........................................................................................................................................2099
48.1.2
SAI's stop-stop ack protocol........................................................................................................................ 2100
Introduction...................................................................................................................................................................2100
48.2.1
Features........................................................................................................................................................ 2100
48.2.2
Block diagram.............................................................................................................................................. 2101
48.2.3
Modes of operation...................................................................................................................................... 2101
48.3
External signals.............................................................................................................................................................2102
48.4
Memory map and register definition.............................................................................................................................2103
48.4.1
SAI Transmit Control Register (I2S_TCSR)............................................................................................... 2105
48.4.2
SAI Transmit Configuration 1 Register (I2S_TCR1).................................................................................. 2108
48.4.3
SAI Transmit Configuration 2 Register (I2S_TCR2).................................................................................. 2108
48.4.4
SAI Transmit Configuration 3 Register (I2S_TCR3).................................................................................. 2110
48.4.5
SAI Transmit Configuration 4 Register (I2S_TCR4).................................................................................. 2111
48.4.6
SAI Transmit Configuration 5 Register (I2S_TCR5).................................................................................. 2113
48.4.7
SAI Transmit Data Register (I2S_TDRn)....................................................................................................2114
48.4.8
SAI Transmit FIFO Register (I2S_TFRn)................................................................................................... 2115
48.4.9
SAI Transmit Mask Register (I2S_TMR)....................................................................................................2115
48.4.10
SAI Receive Control Register (I2S_RCSR)................................................................................................ 2116
48.4.11
SAI Receive Configuration 1 Register (I2S_RCR1)................................................................................... 2119
48.4.12
SAI Receive Configuration 2 Register (I2S_RCR2)................................................................................... 2120
48.4.13
SAI Receive Configuration 3 Register (I2S_RCR3)................................................................................... 2121
48.4.14
SAI Receive Configuration 4 Register (I2S_RCR4)................................................................................... 2123
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Title
Page
48.4.15
SAI Receive Configuration 5 Register (I2S_RCR5)................................................................................... 2125
48.4.16
SAI Receive Data Register (I2S_RDRn)..................................................................................................... 2126
48.4.17
SAI Receive FIFO Register (I2S_RFRn).....................................................................................................2126
48.4.18
SAI Receive Mask Register (I2S_RMR)..................................................................................................... 2127
48.4.19
SAI MCLK Control Register (I2S_MCR)................................................................................................... 2128
48.4.20
SAI MCLK Divide Register (I2S_MDR).................................................................................................... 2129
Functional description...................................................................................................................................................2129
48.5.1
SAI clocking................................................................................................................................................ 2129
48.5.2
SAI resets..................................................................................................................................................... 2132
48.5.3
Synchronous modes..................................................................................................................................... 2132
48.5.4
Frame sync configuration.............................................................................................................................2134
48.5.5
Data FIFO.................................................................................................................................................... 2134
48.5.6
Word mask register...................................................................................................................................... 2138
48.5.7
Interrupts and DMA requests....................................................................................................................... 2138
Chapter 49
Periodic Interrupt Timer (PIT-RTI)
49.1
49.2
Chip-specific PIT-RTI information.............................................................................................................................. 2141
49.1.1
PIT configuration......................................................................................................................................... 2141
49.1.2
Input Output................................................................................................................................................. 2141
49.1.3
PIT-RTI's stop-stop ack protocol................................................................................................................. 2142
Introduction...................................................................................................................................................................2142
49.2.1
Block diagram.............................................................................................................................................. 2142
49.2.2
Features........................................................................................................................................................ 2143
49.3
Signal description..........................................................................................................................................................2144
49.4
Memory map/register description................................................................................................................................. 2144
49.4.1
PIT Module Control Register (PIT_MCR).................................................................................................. 2147
49.4.2
PIT Upper Lifetime Timer Register (PIT_LTMR64H)............................................................................... 2148
49.4.3
PIT Lower Lifetime Timer Register (PIT_LTMR64L)............................................................................... 2148
49.4.4
Timer Load Value Register (PIT_RTI_LDVAL)........................................................................................ 2149
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Page
49.4.5
Current Timer Value Register (PIT_RTI_CVAL).......................................................................................2149
49.4.6
Timer Control Register (PIT_RTI_TCTRL)................................................................................................2150
49.4.7
Timer Flag Register (PIT_RTI_TFLG)....................................................................................................... 2151
49.4.8
Timer Load Value Register (PIT_LDVALn)...............................................................................................2151
49.4.9
Current Timer Value Register (PIT_CVALn)............................................................................................. 2152
49.4.10
Timer Control Register (PIT_TCTRLn)...................................................................................................... 2152
49.4.11
Timer Flag Register (PIT_TFLGn)..............................................................................................................2153
Functional description...................................................................................................................................................2154
49.5.1
General operation......................................................................................................................................... 2154
49.5.2
Interrupts...................................................................................................................................................... 2156
49.5.3
Chained timers............................................................................................................................................. 2156
49.6
Initialization and application information.....................................................................................................................2156
49.7
Example configuration for chained timers....................................................................................................................2158
49.8
Example configuration for the lifetime timer............................................................................................................... 2158
Chapter 50
Software Watchdog Timer (SWT)
50.1
50.2
Chip-specific SWT information....................................................................................................................................2161
50.1.1
SWT configuration.......................................................................................................................................2161
50.1.2
SWT register reset value.............................................................................................................................. 2162
50.1.3
Service mode watchpoint input....................................................................................................................2162
Introduction...................................................................................................................................................................2162
50.2.1
Overview...................................................................................................................................................... 2163
50.2.2
Features........................................................................................................................................................ 2163
50.2.3
Modes of operation...................................................................................................................................... 2163
50.3
External signal description............................................................................................................................................2164
50.4
Memory Map and Registers..........................................................................................................................................2164
50.4.1
SWT Control Register (SWT_CR).............................................................................................................. 2165
50.4.2
SWT Interrupt Register (SWT_IR)..............................................................................................................2168
50.4.3
SWT Time-out Register (SWT_TO)............................................................................................................2169
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Title
Page
50.4.4
SWT Window Register (SWT_WN)........................................................................................................... 2169
50.4.5
SWT Service Register (SWT_SR)............................................................................................................... 2170
50.4.6
SWT Counter Output Register (SWT_CO)................................................................................................. 2170
50.4.7
SWT Service Key Register (SWT_SK)....................................................................................................... 2171
Functional description...................................................................................................................................................2171
50.5.1
Introduction.................................................................................................................................................. 2171
50.5.2
Configuration locking.................................................................................................................................. 2172
50.5.3
Unlock sequence.......................................................................................................................................... 2173
50.5.4
Servicing operations.....................................................................................................................................2173
50.5.5
Time-out.......................................................................................................................................................2175
50.5.6
Initialization................................................................................................................................................. 2175
Chapter 51
Real Time Clock (RTC-API)
51.1
51.2
51.3
Chip-specific RTC-API information.............................................................................................................................2177
51.1.1
RTC Configuration...................................................................................................................................... 2177
51.1.2
RTC register reset value...............................................................................................................................2177
51.1.3
Seamless RTC operation across functional and destructive resets.............................................................. 2177
51.1.4
RTC-API's stop-stop ack protocol............................................................................................................... 2178
Introduction...................................................................................................................................................................2178
51.2.1
Overview...................................................................................................................................................... 2178
51.2.2
Features........................................................................................................................................................ 2178
51.2.3
Block Diagram............................................................................................................................................. 2179
51.2.4
Modes of Operation..................................................................................................................................... 2180
Memory Map and Registers..........................................................................................................................................2181
51.3.1
RTC Supervisor Control register (RTC_RTCSUPV).................................................................................. 2181
51.3.2
RTC Control register (RTC_RTCC)............................................................................................................2182
51.3.3
RTC Status register (RTC_RTCS)...............................................................................................................2184
51.3.4
RTC Counter register (RTC_RTCCNT)......................................................................................................2186
51.3.5
API Compare Value register (RTC_APIVAL)............................................................................................ 2186
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Title
Page
51.3.6
RTC Compare Value register (RTC_RTCVAL)......................................................................................... 2187
51.3.7
RTC Analogue comparator count register (RTC_ANLCMP_CNT)........................................................... 2187
Functional Description..................................................................................................................................................2187
51.4.1
RTC.............................................................................................................................................................. 2187
51.4.2
API functional description........................................................................................................................... 2189
Chapter 52
System Timer Module (STM)
52.1
52.2
Chip-specific STM information....................................................................................................................................2191
52.1.1
STM configuration....................................................................................................................................... 2191
52.1.2
STM register reset value.............................................................................................................................. 2192
Introduction...................................................................................................................................................................2192
52.2.1
Overview...................................................................................................................................................... 2192
52.2.2
Features........................................................................................................................................................ 2192
52.2.3
Modes of operation...................................................................................................................................... 2192
52.3
External signal description............................................................................................................................................2193
52.4
Memory map and registers............................................................................................................................................2193
52.5
52.4.1
STM Control Register (STM_CR)...............................................................................................................2194
52.4.2
STM Count Register (STM_CNT).............................................................................................................. 2195
52.4.3
STM Channel Control Register (STM_CCRn)............................................................................................2196
52.4.4
STM Channel Interrupt Register (STM_CIRn)........................................................................................... 2196
52.4.5
STM Channel Compare Register (STM_CMPn).........................................................................................2197
Functional description...................................................................................................................................................2197
Chapter 53
Reset Generation Module (MC_RGM)
53.1
53.2
Introduction...................................................................................................................................................................2199
53.1.1
Overview...................................................................................................................................................... 2199
53.1.2
Features........................................................................................................................................................ 2200
53.1.3
Reset Sources............................................................................................................................................... 2201
External Signal Description.......................................................................................................................................... 2202
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53.3
53.4
Title
Page
Memory Map and Register Definition..........................................................................................................................2203
53.3.1
'Destructive' Event Status Register (MC_RGM_DES)................................................................................2204
53.3.2
'Destructive' Bidirectional Reset Enable Register (MC_RGM_DBRE)...................................................... 2206
53.3.3
'Functional' Event Status Register (MC_RGM_FES)..................................................................................2208
53.3.4
'Functional' Event Reset Disable Register (MC_RGM_FERD).................................................................. 2211
53.3.5
'Functional' Event Reset DisableAlternate Request Status Register (MC_RGM_FEAR)...........................2214
53.3.6
'Functional' Bidirectional Reset Enable Register (MC_RGM_FBRE)........................................................ 2216
53.3.7
'Functional' Event Short Sequence Register (MC_RGM_FESS)................................................................ 2219
53.3.8
'Functional' Reset Escalation Threshold Register (MC_RGM_FRET)....................................................... 2222
53.3.9
'Destructive' Reset Escalation Threshold Register (MC_RGM_DRET)..................................................... 2222
Functional Description..................................................................................................................................................2223
53.4.1
Reset State Machine.....................................................................................................................................2223
53.4.2
'Destructive' Resets...................................................................................................................................... 2227
53.4.3
External Reset.............................................................................................................................................. 2227
53.4.4
'Functional' Resets........................................................................................................................................2228
53.4.5
Alternate Event Generation..........................................................................................................................2229
53.4.6
'Functional' Reset Escalation........................................................................................................................2230
53.4.7
‘Destructive’ Reset Escalation..................................................................................................................... 2231
Chapter 54
System Status and Configuration Module (SSCM)
54.1
Chip-specific SSCM information................................................................................................................................. 2233
54.1.1
54.2
System Status and Configuration Module (SSCM) configuration...............................................................2233
Introduction...................................................................................................................................................................2234
54.2.1
Overview...................................................................................................................................................... 2234
54.2.2
Glossary....................................................................................................................................................... 2234
54.2.3
Features........................................................................................................................................................ 2235
54.2.4
Modes of operation...................................................................................................................................... 2235
54.3
External signal description............................................................................................................................................2235
54.4
Memory map and register definition.............................................................................................................................2236
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54.5
54.6
Page
54.4.1
SSCM System Status (SSCM_STATUS).................................................................................................... 2237
54.4.2
SSCM System Memory and ID Register (SSCM_MEMCONFIG)............................................................ 2238
54.4.3
SSCM Debug Status Port Register (SSCM_DEBUGPORT)...................................................................... 2239
54.4.4
SSCM HSM and User Option Status Register (SSCM_UOPS).................................................................. 2240
54.4.5
Processor Start Address Register (SSCM_PSA)......................................................................................... 2241
54.4.6
SSCM HSM Start Address Register (SSCM_HSA).................................................................................... 2241
54.4.7
Life Cycle Status Register (SSCM_LCSTAT)............................................................................................ 2242
Functional description...................................................................................................................................................2242
54.5.1
DCF mechanism...........................................................................................................................................2243
54.5.2
Boot mode functionality...............................................................................................................................2245
54.5.3
BAF configuration....................................................................................................................................... 2245
54.5.4
HSM boot header search.............................................................................................................................. 2245
54.5.5
Life Cycle.....................................................................................................................................................2246
Initialization and application information.....................................................................................................................2248
54.6.1
54.7
Title
Reset.............................................................................................................................................................2248
Additional safety measures........................................................................................................................................... 2248
54.7.1
Spurious reset protection..............................................................................................................................2248
Chapter 55
Boot Assist Flash (BAF)
55.1
Chip-specific BAF information.................................................................................................................................... 2249
55.1.1
BAF configuration....................................................................................................................................... 2249
55.1.2
BAF memory map........................................................................................................................................2249
55.1.3
LinFLEXD_0 pin configuration...................................................................................................................2249
55.1.4
Search boot header and boot options........................................................................................................... 2250
55.1.5
MPC5746C cores/BAF CPUn..................................................................................................................... 2251
55.1.6
BAF NMI event handling............................................................................................................................ 2252
55.1.7
BAF version................................................................................................................................................. 2253
55.2
Introduction...................................................................................................................................................................2253
55.3
BAF image header........................................................................................................................................................ 2254
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55.3.1
55.4
55.5
Title
Page
BAF image version...................................................................................................................................... 2254
Functional description...................................................................................................................................................2254
55.4.1
Boot modes.................................................................................................................................................. 2254
55.4.2
Device initialization..................................................................................................................................... 2255
55.4.3
Flow of control.............................................................................................................................................2256
55.4.4
Optionally remap calibration RAM............................................................................................................. 2257
55.4.5
Optionally wait for HSM............................................................................................................................. 2257
55.4.6
BAF SAFE mode event handling.................................................................................................................2258
55.4.7
Initialization of BAF DCF clients................................................................................................................ 2259
55.4.8
Optionally perform serial boot..................................................................................................................... 2268
55.4.9
Serial boot configuration..............................................................................................................................2272
Resources...................................................................................................................................................................... 2274
Chapter 56
Nexus Crossbar Multi-Master Client (NXMC)
56.1
56.2
Chip-specific NXMC information................................................................................................................................ 2277
56.1.1
NXMC block connections............................................................................................................................2277
56.1.2
NXMC source and master client IDs........................................................................................................... 2277
Introduction...................................................................................................................................................................2278
56.2.1
Features........................................................................................................................................................ 2278
56.3
External signal description............................................................................................................................................2279
56.4
Supported messages and TCODEs............................................................................................................................... 2280
56.5
Register description...................................................................................................................................................... 2283
56.5.1
Development control register 1 (DC1).........................................................................................................2283
56.5.2
Development control register 2 (DC2).........................................................................................................2284
56.5.3
Watchpoint trigger register (WT)................................................................................................................ 2285
56.5.4
Data trace control register (DTC)................................................................................................................ 2286
56.5.5
Data trace start address registers 1 and 2 (DTSA1 and DTSA2).................................................................2287
56.5.6
Data trace end address registers 1 and 2 (DTEA1 and DTEA2)..................................................................2287
56.5.7
Breakpoint/watchpoint control register 1 (BWC1)...................................................................................... 2288
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56.6
56.7
Title
Page
56.5.8
Breakpoint/watchpoint control register 2 (BWC2)...................................................................................... 2289
56.5.9
Breakpoint/watchpoint address registers 1 and 2 (BWA1 and BWA2).......................................................2290
56.5.10
Unimplemented registers............................................................................................................................. 2290
Programming considerations (RESET).........................................................................................................................2291
56.6.1
IEEE 1149.1 (JTAG) Test Access Port........................................................................................................2291
56.6.2
Enabling NXMC operation.......................................................................................................................... 2291
56.6.3
Enabling NXMC TAP controller................................................................................................................. 2291
56.6.4
NXMC register access via JTAG.................................................................................................................2292
Functional description...................................................................................................................................................2293
56.7.1
Data trace..................................................................................................................................................... 2293
56.7.2
Watchpoint support...................................................................................................................................... 2299
56.7.3
Timestamping feature.................................................................................................................................. 2301
Chapter 57
JTAG Controller (JTAGC)
57.1
57.2
57.3
57.4
Chip-specific JTAG information.................................................................................................................................. 2303
57.1.1
JTAG Controller (JTAGC) configuration....................................................................................................2303
57.1.2
JTAGC Control 1 register............................................................................................................................ 2303
Introduction...................................................................................................................................................................2304
57.2.1
Block diagram.............................................................................................................................................. 2305
57.2.2
Features........................................................................................................................................................ 2305
57.2.3
Modes of operation...................................................................................................................................... 2306
External signal description............................................................................................................................................2307
57.3.1
TCK—Test clock input................................................................................................................................ 2307
57.3.2
TDI—Test data input................................................................................................................................... 2307
57.3.3
TDO—Test data output................................................................................................................................2308
57.3.4
TMS—Test mode select...............................................................................................................................2308
Register description...................................................................................................................................................... 2308
57.4.1
Instruction register....................................................................................................................................... 2308
57.4.2
Bypass register............................................................................................................................................. 2309
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57.5
57.6
Title
Page
57.4.3
Device identification register....................................................................................................................... 2309
57.4.4
JTAG_PASSWORD register....................................................................................................................... 2310
57.4.5
Boundary scan register.................................................................................................................................2310
Functional description...................................................................................................................................................2310
57.5.1
JTAGC reset configuration.......................................................................................................................... 2311
57.5.2
IEEE 1149.1-2001 (JTAG) Test Access Port.............................................................................................. 2311
57.5.3
TAP controller state machine.......................................................................................................................2311
57.5.4
JTAGC block instructions............................................................................................................................2313
57.5.5
Boundary scan..............................................................................................................................................2316
Initialization/Application information.......................................................................................................................... 2317
Chapter 58
JTAG Data Communication (JDC)
58.1
Introduction...................................................................................................................................................................2319
58.2
Overview.......................................................................................................................................................................2319
58.3
Memory mapped registers.............................................................................................................................................2320
58.4
58.5
58.3.1
Module Configuration Register (JDC_MCR)..............................................................................................2321
58.3.2
Module Status Register (JDC_MSR)........................................................................................................... 2322
58.3.3
JTAG Output Data Register (JDC_JOUT_IPS)...........................................................................................2323
58.3.4
JTAG Input Data Register (JDC_JIN_IPS)................................................................................................. 2324
Non-Memory mapped register definition..................................................................................................................... 2324
58.4.1
JTAG output data register (JOUT)...............................................................................................................2324
58.4.2
JTAG input data register (JIN).....................................................................................................................2325
Functional description...................................................................................................................................................2325
58.5.1
58.6
JTAG register access....................................................................................................................................2326
Use case example..........................................................................................................................................................2326
Chapter 59
IEEE 1149.7 Compact JTAG Test Access Port Controller (CJTAG)
59.1
References.....................................................................................................................................................................2329
59.2
Abbreviations................................................................................................................................................................2329
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59.3
Title
Page
Introduction...................................................................................................................................................................2330
59.3.1
Types of operation....................................................................................................................................... 2331
59.3.2
Deployment by class.................................................................................................................................... 2331
59.3.3
1149.7 TAP signals...................................................................................................................................... 2332
59.3.4
TAP.7 architecture....................................................................................................................................... 2333
59.3.5
Protocols.......................................................................................................................................................2334
59.4
Operating models.......................................................................................................................................................... 2336
59.5
CJTAG implementation summary................................................................................................................................ 2336
59.6
59.7
59.8
59.5.1
T0 functions................................................................................................................................................. 2336
59.5.2
T1 functions................................................................................................................................................. 2337
59.5.3
T2 functions................................................................................................................................................. 2337
59.5.4
T3 functions................................................................................................................................................. 2337
59.5.5
T4 functions................................................................................................................................................. 2337
Ancillary services..........................................................................................................................................................2337
59.6.1
Overview...................................................................................................................................................... 2337
59.6.2
Resets........................................................................................................................................................... 2338
59.6.3
Start-up Options........................................................................................................................................... 2341
59.6.4
RSU operation..............................................................................................................................................2342
59.6.5
TAPC State Machine................................................................................................................................... 2344
EPU (Extended Protocol Unit) Operation.....................................................................................................................2345
59.7.1
EPU Operation............................................................................................................................................. 2345
59.7.2
EPU Registers.............................................................................................................................................. 2348
59.7.3
EPU Commands........................................................................................................................................... 2359
59.7.4
EPU operating states.................................................................................................................................... 2367
59.7.5
System and EPU Paths................................................................................................................................. 2368
APU (Advanced Protocol Unit) Operation................................................................................................................... 2368
59.8.1
Overview...................................................................................................................................................... 2368
59.8.2
Operation......................................................................................................................................................2371
59.8.3
Escape sequences......................................................................................................................................... 2373
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59.9
Title
Page
59.8.4
Signal behaviors........................................................................................................................................... 2373
59.8.5
APU Functions............................................................................................................................................. 2374
59.8.6
Configuration Change Packets (CP)............................................................................................................ 2380
59.8.7
Scan Packet.................................................................................................................................................. 2381
59.8.8
SP Format.....................................................................................................................................................2381
Functional Description..................................................................................................................................................2388
59.9.1
Switching from Standard Protocol to Advanced Protocol........................................................................... 2388
Chapter 60
Nexus Port Controller (NPC)
60.1
60.2
60.3
60.4
Chip-specific NPC information.................................................................................................................................... 2389
60.1.1
NPC configuration....................................................................................................................................... 2389
60.1.2
EVTO sharing - Pulse time.......................................................................................................................... 2390
60.1.3
Trace messages for transactions with error responses................................................................................. 2390
60.1.4
Trace loss during resets................................................................................................................................2390
60.1.5
EVTI_IN pin................................................................................................................................................ 2391
Introduction...................................................................................................................................................................2391
60.2.1
Overview...................................................................................................................................................... 2391
60.2.2
Features........................................................................................................................................................ 2392
60.2.3
Modes of operation...................................................................................................................................... 2392
External signal description............................................................................................................................................2394
60.3.1
Overview...................................................................................................................................................... 2394
60.3.2
Detailed signal descriptions......................................................................................................................... 2394
Register definition.........................................................................................................................................................2396
60.4.1
60.5
Register descriptions.................................................................................................................................... 2396
Functional Description..................................................................................................................................................2400
60.5.1
NPC reset configuration...............................................................................................................................2400
60.5.2
Auxiliary Output Port...................................................................................................................................2400
60.5.3
IEEE 1149.1-2001 (JTAG) TAP..................................................................................................................2403
60.5.4
Nexus JTAG Port Sharing............................................................................................................................2407
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60.6
Title
Page
60.5.5
MCKO Control ........................................................................................................................................... 2407
60.5.6
EVTO Sharing..............................................................................................................................................2408
60.5.7
System Clock Locked Indication................................................................................................................. 2408
Initialization/Application Information.......................................................................................................................... 2408
60.6.1
Accessing NPC tool-mapped registers.........................................................................................................2408
Chapter 61
Core Complex Overview
61.1
Overview of the e200z210n3 and e200z4204n3 cores................................................................................................. 2411
61.2
z210n3 microarchitecture summary..............................................................................................................................2411
61.3
61.2.1
Overview of the e200z210n3 core............................................................................................................... 2412
61.2.2
z210n3 instruction unit features................................................................................................................... 2414
61.2.3
z210n3 integer unit features......................................................................................................................... 2414
61.2.4
z210n3 load/store unit features.................................................................................................................... 2414
61.2.5
z210n3 performance monitor features......................................................................................................... 2415
61.2.6
z210n3 system bus features .........................................................................................................................2415
z4204n3 microarchitecture summary............................................................................................................................2415
61.3.1
Overview of the e200z4204n3..................................................................................................................... 2417
61.3.2
z4204n3 instruction unit features................................................................................................................. 2417
61.3.3
z4204n3 integer unit features....................................................................................................................... 2418
61.3.4
z210n3 load/store unit features.................................................................................................................... 2418
61.3.5
z4204n3 EFPU2 floating-point unit features............................................................................................... 2418
61.3.6
z4204n3 cache features ............................................................................................................................... 2419
61.3.7
z4204n3 performance monitor features ...................................................................................................... 2420
61.3.8
z4204n3 system bus features .......................................................................................................................2421
Chapter 62
Z2 Core description
62.1
Overview of the e200z210n3 core................................................................................................................................ 2423
62.2
Register model.............................................................................................................................................................. 2423
62.2.1
Branch Unit Control and Status Register (BUCSR).................................................................................... 2426
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Title
Page
62.2.2
Hardware Implementation Dependent Register 0 (HID0)........................................................................... 2428
62.2.3
Hardware Implementation Dependent Register 1 (HID1)........................................................................... 2429
62.3
Single-issue operation...................................................................................................................................................2431
62.4
Instruction timing..........................................................................................................................................................2431
62.5
Exceptions.....................................................................................................................................................................2438
62.6
62.5.1
Exception Syndrome Register (ESR)...........................................................................................................2439
62.5.2
Machine State Register (MSR).................................................................................................................... 2440
62.5.3
Machine Check Syndrome Register (MCSR).............................................................................................. 2442
62.5.4
Interrupt Vector Prefix Registers (IVPR).................................................................................................... 2445
62.5.5
Interrupt Definitions.....................................................................................................................................2446
End-to-End ECC Support............................................................................................................................................. 2457
62.6.1
End-to-End ECC control and configuration.................................................................................................2457
Chapter 63
Z4 Core description
63.1
Overview of the e200z4204n3 core.............................................................................................................................. 2461
63.2
Register model.............................................................................................................................................................. 2461
63.2.1
Hardware Implementation Dependent Register 0 (HID0)........................................................................... 2465
63.2.2
Hardware Implementation Dependent Register 1 (HID1)........................................................................... 2467
63.3
Instruction timing..........................................................................................................................................................2468
63.4
Dual-issue operation..................................................................................................................................................... 2475
63.5
Reservation instructions and cache interactions........................................................................................................... 2476
63.6
Signal Processing Extension/Embedded Floating-point Status and Control Register (SPEFSCR) ............................ 2476
63.7
Cache.............................................................................................................................................................................2479
63.7.1
Cache overview............................................................................................................................................2479
63.7.2
L1 Cache Control and Status Register 0 (L1CSR0) ................................................................................... 2479
63.7.3
L1 Cache Control and Status Register 1 (L1CSR1).................................................................................... 2482
63.7.4
L1 Cache Configuration Register 0 (L1CFG0) ...........................................................................................2485
63.7.5
L1 Cache Configuration Register 1 (L1CFG1)............................................................................................2486
63.7.6
Data cache software coherency....................................................................................................................2486
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Section number
63.8
63.9
Title
Page
63.7.7
Data cache hardware coherency...................................................................................................................2487
63.7.8
Cache invalidate by set and way.................................................................................................................. 2487
63.7.9
Cache EDC/ECC parity protection.............................................................................................................. 2489
63.7.10
Cache error injection.................................................................................................................................... 2491
Exceptions.....................................................................................................................................................................2492
63.8.1
Exception Syndrome Register (ESR)...........................................................................................................2492
63.8.2
Machine State Register (MSR).................................................................................................................... 2494
63.8.3
Machine Check Syndrome Register (MCSR).............................................................................................. 2496
63.8.4
Interrupt Vector Prefix Registers (IVPR).................................................................................................... 2499
63.8.5
Interrupt definitions......................................................................................................................................2499
End-to-End ECC support.............................................................................................................................................. 2510
63.9.1
End-to-End ECC control and configuration.................................................................................................2510
Chapter 64
Z2 Core Debug Support
64.1
64.2
Overview.......................................................................................................................................................................2515
64.1.1
Software Debug Facilities............................................................................................................................ 2515
64.1.2
Additional Debug Facilities......................................................................................................................... 2516
64.1.3
Hardware Debug Facilities...........................................................................................................................2517
64.1.4
Sharing Debug Resources by Software/Hardware.......................................................................................2517
Software Debug Events and Exceptions....................................................................................................................... 2519
64.2.1
Instruction Address Compare Event............................................................................................................ 2521
64.2.2
Data Address Compare Event...................................................................................................................... 2521
64.2.3
Linked Instruction Address Compare and Data Address Compare Events................................................. 2525
64.2.4
Trap Debug Event........................................................................................................................................ 2526
64.2.5
Branch Taken Debug Event......................................................................................................................... 2526
64.2.6
Instruction Complete Debug Event..............................................................................................................2526
64.2.7
Interrupt Taken Debug Event.......................................................................................................................2527
64.2.8
Critical Interrupt Taken Debug Event..........................................................................................................2527
64.2.9
Return Debug Event.....................................................................................................................................2527
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64.3
Title
Page
64.2.10
Critical Return Debug Event........................................................................................................................2528
64.2.11
External debug event....................................................................................................................................2528
64.2.12
Unconditional debug event.......................................................................................................................... 2528
64.2.13
Performance Monitor Interrupt debug event................................................................................................2529
Debug registers............................................................................................................................................................. 2529
64.3.1
Debug Address and Value Registers............................................................................................................2530
64.3.2
Debug Control and Status registers..............................................................................................................2531
64.3.3
External Debug Resource Allocation Control Register (EDBRAC0)......................................................... 2554
64.3.4
Debug Event Select Register (DEVENT).................................................................................................... 2561
64.3.5
Debug Data Acquisition Message Register (DDAM)..................................................................................2562
64.4
Using Debug Resources for Stack Limit Checking...................................................................................................... 2563
64.5
External Debug Support................................................................................................................................................2565
64.5.1
External Debug Registers.............................................................................................................................2567
64.5.2
OnCE Introduction....................................................................................................................................... 2573
64.5.3
JTAG/OnCE Pins......................................................................................................................................... 2575
64.5.4
OnCE Internal Interface Signals.................................................................................................................. 2576
64.5.5
OnCE Interface Signals................................................................................................................................2576
64.5.6
OnCE Controller and serial interface...........................................................................................................2579
64.5.7
Access to Debug Resources......................................................................................................................... 2586
64.5.8
Methods of Entering Debug Mode...............................................................................................................2588
64.5.9
CPU Status and Control Scan Chain Register (CPUSCR).......................................................................... 2590
64.5.10
Reserved Registers (Reserved).................................................................................................................... 2597
64.6
Watchpoint Support...................................................................................................................................................... 2597
64.7
Basic Steps for Enabling, Using, and Exiting External Debug Mode.......................................................................... 2600
Chapter 65
Z4 Core Debug Support
65.1
Overview.......................................................................................................................................................................2603
65.1.1
Software Debug Facilities............................................................................................................................ 2603
65.1.2
Additional Debug Facilities......................................................................................................................... 2604
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65.2
65.3
Title
Page
65.1.3
Hardware Debug Facilities...........................................................................................................................2605
65.1.4
Sharing Debug Resources by Software/Hardware.......................................................................................2605
Software Debug Events and Exceptions....................................................................................................................... 2607
65.2.1
Instruction Address Compare Event............................................................................................................ 2609
65.2.2
Data Address Compare Event...................................................................................................................... 2609
65.2.3
Linked Instruction Address Compare and Data Address Compare Events................................................. 2618
65.2.4
Trap Debug Event........................................................................................................................................ 2619
65.2.5
Branch Taken Debug Event......................................................................................................................... 2619
65.2.6
Instruction Complete Debug Event..............................................................................................................2620
65.2.7
Interrupt Taken Debug Event.......................................................................................................................2620
65.2.8
Critical Interrupt Taken Debug Event..........................................................................................................2621
65.2.9
Return Debug Event.....................................................................................................................................2621
65.2.10
Critical Return Debug Event........................................................................................................................2621
65.2.11
External debug event....................................................................................................................................2622
65.2.12
Unconditional debug event.......................................................................................................................... 2622
65.2.13
Performance Monitor Interrupt debug event................................................................................................2622
Debug registers............................................................................................................................................................. 2623
65.3.1
Debug Address and Value Registers............................................................................................................2623
65.3.2
Debug Control and Status registers..............................................................................................................2624
65.3.3
External Debug Resource Allocation Control Register (EDBRAC0)......................................................... 2647
65.3.4
Debug Event Select Register (DEVENT).................................................................................................... 2654
65.3.5
Debug Data Acquisition Message Register (DDAM)..................................................................................2655
65.4
Using Debug Resources for Stack Limit Checking...................................................................................................... 2656
65.5
External Debug Support................................................................................................................................................2659
65.5.1
External Debug Registers.............................................................................................................................2660
65.5.2
OnCE Introduction....................................................................................................................................... 2666
65.5.3
JTAG/OnCE Pins......................................................................................................................................... 2669
65.5.4
OnCE Internal Interface Signals.................................................................................................................. 2669
65.5.5
OnCE Interface Signals................................................................................................................................2670
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Title
Page
65.5.6
OnCE Controller and serial interface...........................................................................................................2673
65.5.7
Access to Debug Resources......................................................................................................................... 2680
65.5.8
Methods of Entering Debug Mode...............................................................................................................2682
65.5.9
CPU Status and Control Scan Chain Register (CPUSCR).......................................................................... 2684
65.5.10
Reserved Registers (Reserved).................................................................................................................... 2691
65.6
Watchpoint Support...................................................................................................................................................... 2691
65.7
Cache Array Access During Debug..............................................................................................................................2694
65.8
Basic Steps for Enabling, Using, and Exiting External Debug Mode.......................................................................... 2694
Chapter 66
Z2 Nexus 3 Module
66.1
66.2
Introduction...................................................................................................................................................................2697
66.1.1
General description...................................................................................................................................... 2697
66.1.2
Terms and definitions...................................................................................................................................2697
66.1.3
Feature list....................................................................................................................................................2698
66.1.4
Functional block diagram.............................................................................................................................2700
Enabling Nexus 3 operation..........................................................................................................................................2701
66.2.1
Interaction with Low Power Modes.............................................................................................................2702
66.3
TCODEs supported.......................................................................................................................................................2703
66.4
Nexus 3 Programmer's model....................................................................................................................................... 2708
66.4.1
Client Select Control (CSC) register............................................................................................................2710
66.4.2
Port Configuration Register (PCR) - reference only....................................................................................2710
66.4.3
Nexus Development Control Register 1 (DC1)........................................................................................... 2711
66.4.4
Nexus Development Control Registers 2 & 3 (DC2, DC3)......................................................................... 2713
66.4.5
Nexus Development Control Register 4 (DC4)........................................................................................... 2715
66.4.6
Development Status Register (DS).............................................................................................................. 2716
66.4.7
Watchpoint Trigger (WT, PTSTC, PTETC, DTSTC, DTETC) registers....................................................2717
66.4.8
Nexus Watchpoint Mask (WMSK) register.................................................................................................2724
66.4.9
Nexus Overrun Control Register (OVCR)...................................................................................................2725
66.4.10
Data Trace Control Register (DTC) register................................................................................................2726
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66.4.11
Data Trace Start Address Registers (DTSA1-4).......................................................................................... 2728
66.4.12
Data Trace End Address (DTEA1-4) registers............................................................................................ 2729
66.4.13
Read/Write Access Control/Status (RWCS) register...................................................................................2730
66.4.14
Read/Write Access Data (RWD) register.................................................................................................... 2732
66.4.15
Read/Write Access Address (RWA)............................................................................................................2733
66.5
Nexus 3 Register Access via JTAG/OnCE...................................................................................................................2734
66.6
Nexus 3 Register Access via Software......................................................................................................................... 2734
66.7
Nexus message fields....................................................................................................................................................2735
66.8
66.9
66.7.1
TCODE Field............................................................................................................................................... 2735
66.7.2
Source ID Field (SRC)................................................................................................................................. 2735
66.7.3
Relative Address Field (U-ADDR)..............................................................................................................2735
66.7.4
Full Address Field (F-ADDR)..................................................................................................................... 2736
66.7.5
Timestamp field (TSTAMP)........................................................................................................................ 2737
Nexus Message Queues................................................................................................................................................ 2737
66.8.1
Message Queue Overrun.............................................................................................................................. 2738
66.8.2
CPU Stall......................................................................................................................................................2738
66.8.3
Message Suppression................................................................................................................................... 2738
66.8.4
Nexus Message Priority............................................................................................................................... 2739
66.8.5
Data Acquisition Message Priority Loss Response..................................................................................... 2740
66.8.6
Ownership Trace Message Priority Loss Response..................................................................................... 2740
66.8.7
Program Trace Message Priority Loss Response.........................................................................................2741
66.8.8
Program Trace Sync Message Priority Loss Response................................................................................2741
66.8.9
Data Trace Message Priority Loss Response............................................................................................... 2741
Debug Status messages................................................................................................................................................. 2741
66.10 Error messages.............................................................................................................................................................. 2742
66.11 Ownership trace............................................................................................................................................................ 2742
66.11.1
Overview...................................................................................................................................................... 2742
66.11.2
Ownership Trace Messaging (OTM)........................................................................................................... 2742
66.12 Program trace................................................................................................................................................................ 2744
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66.12.1
Branch Trace Messaging types.................................................................................................................... 2744
66.12.2
BTM Message For mats............................................................................................................................... 2747
66.12.3
Program Trace Message Fields.................................................................................................................... 2748
66.12.4
Resource Full Messages...............................................................................................................................2749
66.12.5
Program Correlation Messages.................................................................................................................... 2750
66.12.6
Program Trace Overflow Error messages.................................................................................................... 2752
66.12.7
Program Trace Synchronization messages.................................................................................................. 2752
66.12.8
Program Trace Direct/Indirect Branch with Sync messages........................................................................2754
66.12.9
Enabling Program Trace.............................................................................................................................. 2755
66.12.10 Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration).........................................................2755
66.13 Data Trace.....................................................................................................................................................................2757
66.13.1
Data Trace Messaging (DTM)..................................................................................................................... 2757
66.13.2
DTM Message formats.................................................................................................................................2757
66.13.3
DTM Operation............................................................................................................................................2761
66.13.4
Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)............................................................... 2762
66.14 Data Acquisition messaging......................................................................................................................................... 2763
66.14.1
Data Acquisition ID Tag field......................................................................................................................2763
66.14.2
Data Acquisition Data field..........................................................................................................................2764
66.14.3
Data Acquisition Trace event.......................................................................................................................2764
66.15 Watchpoint Trace messaging........................................................................................................................................2764
66.15.1
Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration)............................................................... 2766
66.16 Nexus 3 Read/Write access to memory-mapped resources.......................................................................................... 2767
66.16.1
Single write access....................................................................................................................................... 2767
66.16.2
Block write access........................................................................................................................................2768
66.16.3
Single read access........................................................................................................................................ 2769
66.16.4
Block read access......................................................................................................................................... 2770
66.16.5
Error handling.............................................................................................................................................. 2771
66.16.6
Read/Write access error message.................................................................................................................2772
66.17 Nexus 3 pin interface.................................................................................................................................................... 2773
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66.17.1
Pins implemented......................................................................................................................................... 2773
66.17.2
Pin protocol.................................................................................................................................................. 2775
66.18 Rules for output messages............................................................................................................................................ 2777
66.19 Auxiliary port arbitration.............................................................................................................................................. 2778
66.20 Examples.......................................................................................................................................................................2778
66.21 Electrical characteristics............................................................................................................................................... 2781
66.22 IEEE 1149.1 (JTAG) RD/WR sequences..................................................................................................................... 2781
66.22.1
JTAG sequence for accessing internal Nexus registers............................................................................... 2782
66.22.2
JTAG sequence for read access of memory-mapped resources...................................................................2782
66.22.3
JTAG sequence for write access of memory-mapped resources................................................................. 2782
Chapter 67
Z4 Nexus 3 Module
67.1
67.2
Introduction...................................................................................................................................................................2785
67.1.1
General Description..................................................................................................................................... 2785
67.1.2
Terms and Definitions..................................................................................................................................2785
67.1.3
Feature List.................................................................................................................................................. 2786
67.1.4
Functional Block Diagram........................................................................................................................... 2788
Enabling Nexus 3 Operation.........................................................................................................................................2789
67.2.1
Interaction with Low Power Modes.............................................................................................................2790
67.3
TCODEs supported.......................................................................................................................................................2791
67.4
Nexus 3 Programmer's Model.......................................................................................................................................2796
67.4.1
Client Select Control (CSC) register............................................................................................................2797
67.4.2
Port Configuration Register (PCR) - reference only....................................................................................2798
67.4.3
Nexus Development Control Register 1 (DC1)........................................................................................... 2799
67.4.4
Nexus Development Control Registers 2 and 3 (DC2, DC3)...................................................................... 2800
67.4.5
Nexus Development Control Register 4 (DC4)........................................................................................... 2802
67.4.6
Development Status Register (DS).............................................................................................................. 2803
67.4.7
Watchpoint Trigger (WT, PTSTC, PTETC, DTSTC, DTETC) registers....................................................2804
67.4.8
Nexus Watchpoint Mask (WMSK) register.................................................................................................2811
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67.4.9
Nexus Overrun Control Register (OVCR)...................................................................................................2812
67.4.10
Data Trace Control Register (DTC) register................................................................................................2813
67.4.11
Data Trace Start Address Registers (DTSA1-4).......................................................................................... 2816
67.4.12
Data Trace End Address (DTEA1-4) registers............................................................................................ 2816
67.4.13
Read/Write Access Control/Status (RWCS) register...................................................................................2817
67.4.14
Read/Write Access Data (RWD) register.................................................................................................... 2819
67.4.15
Read/Write Access Address (RWA)............................................................................................................2821
67.5
Nexus 3 Register Access via JTAG/OnCE...................................................................................................................2821
67.6
Nexus 3 Register Access via Software......................................................................................................................... 2822
67.7
Nexus Message Fields...................................................................................................................................................2822
67.8
67.9
67.7.1
TCODE Field............................................................................................................................................... 2822
67.7.2
Source ID Field (SRC)................................................................................................................................. 2822
67.7.3
Relative Address Field (U-ADDR)..............................................................................................................2823
67.7.4
Full Address Field (F-ADDR)..................................................................................................................... 2824
Nexus Message Queues................................................................................................................................................ 2824
67.8.1
Message Queue Overrun.............................................................................................................................. 2825
67.8.2
CPU Stall......................................................................................................................................................2825
67.8.3
Message Suppression................................................................................................................................... 2825
67.8.4
Nexus Message Priority............................................................................................................................... 2826
67.8.5
Data Acquisition Message Priority Loss Response..................................................................................... 2827
67.8.6
Ownership Trace Message Priority Loss Response..................................................................................... 2827
67.8.7
Program Trace Message Priority Loss Response.........................................................................................2828
67.8.8
Program Trace Sync Message Priority Loss Response................................................................................2828
67.8.9
Data Trace Message Priority Loss Response............................................................................................... 2828
Debug Status messages................................................................................................................................................. 2828
67.10 Error messages.............................................................................................................................................................. 2829
67.11 Ownership trace............................................................................................................................................................ 2829
67.11.1
Overview...................................................................................................................................................... 2829
67.11.2
Ownership Trace Messaging (OTM)........................................................................................................... 2829
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67.12 Program trace................................................................................................................................................................ 2831
67.12.1
Branch Trace Messaging types.................................................................................................................... 2831
67.12.2
BTM Message For mats............................................................................................................................... 2834
67.12.3
Program Trace Message Fields.................................................................................................................... 2835
67.12.4
Resource Full Messages...............................................................................................................................2836
67.12.5
Program Correlation Messages.................................................................................................................... 2837
67.12.6
Program Trace Overflow Error messages.................................................................................................... 2839
67.12.7
Program Trace Synchronization messages.................................................................................................. 2839
67.12.8
Program Trace Direct/Indirect Branch with Sync messages........................................................................2841
67.12.9
Enabling Program Trace.............................................................................................................................. 2842
67.12.10 Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration).........................................................2842
67.13 Data Trace.....................................................................................................................................................................2844
67.13.1
Data Trace Messaging (DTM)..................................................................................................................... 2844
67.13.2
DTM Message formats.................................................................................................................................2844
67.13.3
DTM Operation............................................................................................................................................2848
67.13.4
Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)............................................................... 2849
67.14 Data Acquisition messaging......................................................................................................................................... 2850
67.14.1
Data Acquisition ID Tag field......................................................................................................................2850
67.14.2
Data Acquisition Data field..........................................................................................................................2850
67.14.3
Data Acquisition Trace event.......................................................................................................................2850
67.15 Watchpoint Trace messaging........................................................................................................................................2851
67.15.1
Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration)............................................................... 2853
67.16 Nexus 3 Read/Write access to memory-mapped resources.......................................................................................... 2853
67.16.1
Single write access....................................................................................................................................... 2854
67.16.2
Block write access........................................................................................................................................2855
67.16.3
Single read access........................................................................................................................................ 2856
67.16.4
Block read access......................................................................................................................................... 2857
67.16.5
Error handling.............................................................................................................................................. 2858
67.16.6
Read/Write access error message.................................................................................................................2859
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67.17 Nexus 3 pin interface.................................................................................................................................................... 2859
67.17.1
Pins implemented......................................................................................................................................... 2860
67.17.2
Pin protocol.................................................................................................................................................. 2862
67.18 Rules for output messages............................................................................................................................................ 2864
67.19 Auxiliary port arbitration.............................................................................................................................................. 2865
67.20 Examples.......................................................................................................................................................................2865
67.21 Electrical characteristics............................................................................................................................................... 2868
67.22 IEEE 1149.1 (JTAG) RD/WR sequences..................................................................................................................... 2868
67.22.1
JTAG sequence for accessing internal Nexus registers............................................................................... 2869
67.22.2
JTAG sequence for read access of memory-mapped resources...................................................................2869
67.22.3
JTAG sequence for write access of memory-mapped resources................................................................. 2869
Chapter 68
Enhanced Direct Memory Access (eDMA)
68.1
Introduction...................................................................................................................................................................2871
68.1.1
eDMA system block diagram...................................................................................................................... 2871
68.1.2
Block parts................................................................................................................................................... 2872
68.1.3
Features........................................................................................................................................................ 2873
68.2
Modes of operation....................................................................................................................................................... 2874
68.3
Memory map/register definition................................................................................................................................... 2875
68.3.1
TCD memory............................................................................................................................................... 2875
68.3.2
TCD initialization........................................................................................................................................ 2875
68.3.3
TCD structure...............................................................................................................................................2875
68.3.4
Reserved memory and bit fields...................................................................................................................2876
68.3.5
Control Register (DMA_CR).......................................................................................................................2903
68.3.6
Error Status Register (DMA_ES)................................................................................................................ 2906
68.3.7
Enable Request Register (DMA_ERQ)....................................................................................................... 2909
68.3.8
Enable Error Interrupt Register (DMA_EEI)...............................................................................................2912
68.3.9
Set Enable Request Register (DMA_SERQ)............................................................................................... 2916
68.3.10
Clear Enable Request Register (DMA_CERQ)........................................................................................... 2916
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68.3.11
Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 2917
68.3.12
Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 2918
68.3.13
Clear Interrupt Request Register (DMA_CINT)......................................................................................... 2919
68.3.14
Clear Error Register (DMA_CERR)............................................................................................................2920
68.3.15
Set START Bit Register (DMA_SSRT)...................................................................................................... 2921
68.3.16
Clear DONE Status Bit Register (DMA_CDNE)........................................................................................ 2922
68.3.17
Interrupt Request Register (DMA_INT)......................................................................................................2923
68.3.18
Error Register (DMA_ERR)........................................................................................................................ 2926
68.3.19
Hardware Request Status Register (DMA_HRS)........................................................................................ 2930
68.3.20
Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 2936
68.3.21
Channel n Master ID Register (DMA_DCHMIDn).................................................................................... 2937
68.3.22
TCD Source Address (DMA_TCDn_SADDR)........................................................................................... 2938
68.3.23
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................2938
68.3.24
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................2939
68.3.25
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 2940
68.3.26
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO)....................................................................................................... 2940
68.3.27
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 2942
68.3.28
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................2943
68.3.29
TCD Destination Address (DMA_TCDn_DADDR)................................................................................... 2943
68.3.30
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................2944
68.3.31
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 2945
68.3.32
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................2946
68.3.33
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 2946
68.3.34
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................2947
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Title
Page
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 2948
68.3.36
68.4
68.5
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 2949
Functional description...................................................................................................................................................2951
68.4.1
eDMA basic data flow................................................................................................................................. 2951
68.4.2
Fault reporting and handling........................................................................................................................ 2954
68.4.3
Channel preemption..................................................................................................................................... 2957
Initialization/application information........................................................................................................................... 2957
68.5.1
eDMA initialization..................................................................................................................................... 2957
68.5.2
Programming errors..................................................................................................................................... 2959
68.5.3
Arbitration mode considerations.................................................................................................................. 2960
68.5.4
Performing DMA transfers.......................................................................................................................... 2961
68.5.5
Monitoring transfer descriptor status........................................................................................................... 2965
68.5.6
Channel Linking...........................................................................................................................................2967
68.5.7
Dynamic programming................................................................................................................................ 2968
68.5.8
Suspend/resume a DMA channel with active hardware service requests.................................................... 2972
Chapter 69
Direct Memory Access Multiplexer
69.1
Chip-specific DMA MUX information........................................................................................................................ 2975
69.1.1
69.2
DMA MUX configuration........................................................................................................................... 2975
Introduction...................................................................................................................................................................2977
69.2.1
Overview...................................................................................................................................................... 2977
69.2.2
Features........................................................................................................................................................ 2978
69.2.3
Modes of operation...................................................................................................................................... 2978
69.3
External signal description............................................................................................................................................2979
69.4
Memory map/register definition................................................................................................................................... 2979
69.4.1
69.5
Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 2980
Functional description...................................................................................................................................................2981
69.5.1
DMA channels with periodic triggering capability......................................................................................2981
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69.5.2
DMA channels with no triggering capability...............................................................................................2983
69.5.3
Always-enabled DMA sources.................................................................................................................... 2984
Initialization/application information........................................................................................................................... 2985
69.6.1
Reset.............................................................................................................................................................2985
69.6.2
Enabling and configuring sources................................................................................................................2985
Chapter 70
PRAMC
70.1
Chip-specific PRAMC information.............................................................................................................................. 2989
70.1.1
Register reset value...................................................................................................................................... 2989
70.2
Introduction...................................................................................................................................................................2989
70.3
SRAM controller memory map and register definition................................................................................................ 2991
70.3.1
70.4
Platform RAM Configuration Register 1 (PRAMC_PRCR1)..................................................................... 2991
Functional description...................................................................................................................................................2993
70.4.1
Read and Write operations........................................................................................................................... 2993
70.4.2
Writes........................................................................................................................................................... 2994
70.5
Initialization/application information........................................................................................................................... 2996
70.6
Reliability considerations............................................................................................................................................. 2996
70.6.1
Hsiao ECC algorithm................................................................................................................................... 2996
70.6.2
Transaction monitor..................................................................................................................................... 2999
Chapter 71
Flash memory controller
71.1
Chip-specific Flash memory controller information.....................................................................................................3001
71.1.1
Master IDs....................................................................................................................................................3001
71.2
Introduction...................................................................................................................................................................3001
71.3
Features......................................................................................................................................................................... 3002
71.4
Block diagrams............................................................................................................................................................. 3002
71.5
Flash memory controller memory map.........................................................................................................................3003
71.5.1
Platform Flash Configuration Register 1 (PFLASH_PFCR1)..................................................................... 3007
71.5.2
Platform Flash Configuration Register 2 (PFLASH_PFCR2)..................................................................... 3010
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Title
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71.5.3
Platform Flash Configuration Register 3 (PFLASH_PFCR3)..................................................................... 3013
71.5.4
Platform Flash Access Protection Register (PFLASH_PFAPR)................................................................. 3015
71.5.5
Platform Flash Remap Control Register (PFLASH_PFCRCR).................................................................. 3018
71.5.6
Platform Flash Remap Descriptor Enable Register (PFLASH_PFCRDE)..................................................3020
71.5.7
Platform Flash Configuration Register 4 (PFLASH_PFCR4)..................................................................... 3023
71.5.8
Platform Flash Calibration Region Descriptor n Word0 (PFLASH_PFCRDn_Word0)............................. 3026
71.5.9
Platform Flash Calibration Region Descriptor n Word1 (PFLASH_PFCRDn_Word1)............................. 3026
71.5.10
Platform Flash Calibration Region Descriptor n Word2 (PFLASH_PFCRDn_Word2)............................. 3027
Functional description...................................................................................................................................................3032
71.6.1
Basic interface protocol............................................................................................................................... 3033
71.6.2
Access protections........................................................................................................................................3033
71.6.3
Security module exclusive control............................................................................................................... 3035
71.6.4
Security Module Alternate Programming Interface.....................................................................................3035
71.6.5
Access pipelining......................................................................................................................................... 3036
71.6.6
Line read buffers and prefetch operation..................................................................................................... 3037
71.6.7
Instruction/Data prefetch triggering.............................................................................................................3038
71.6.8
Per-Master prefetch triggering..................................................................................................................... 3039
71.6.9
Buffer allocation.......................................................................................................................................... 3039
71.6.10
PFlash calibration remap support.................................................................................................................3039
71.6.11
Reliability considerations.............................................................................................................................3042
71.6.12
ECC on data flash accesses.......................................................................................................................... 3046
71.6.13
Array integrity considerations......................................................................................................................3047
Chapter 72
Embedded Flash Memory
72.1
Chip-specific Embedded Flash memory information................................................................................................... 3049
72.1.1
Embedded Flash Memory configuration......................................................................................................3049
72.1.2
Register bit mapping.................................................................................................................................... 3049
72.1.3
C55FMC_LOCK0 and C55FMC_SEL0 register bit mapping.................................................................... 3049
72.1.4
C55FMC_LOCK1 and C55FMC_SEL1 register bit mapping.................................................................... 3050
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Title
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72.1.5
C55FMC_LOCK2 and C55FMC_SEL2 register bit mapping.................................................................... 3051
72.1.6
C55FMC_LOCK3 and C55FMC_SEL3 register bit mapping.................................................................... 3052
72.1.7
Embedded Flash Memory register reset value............................................................................................. 3053
72.1.8
System Address to Flash Address Mapping................................................................................................ 3053
Introduction...................................................................................................................................................................3055
72.2.1
Overview...................................................................................................................................................... 3056
72.2.2
Features........................................................................................................................................................ 3057
72.2.3
Modes of operation...................................................................................................................................... 3057
72.3
UTest NVM block.........................................................................................................................................................3058
72.4
Test mode disable seal.................................................................................................................................................. 3058
72.5
Memory map and register definition.............................................................................................................................3059
72.5.1
Module Configuration Register (C55FMC_MCR)......................................................................................3061
72.5.2
Extended Module Configuration Register (C55FMC_MCRE)................................................................... 3066
72.5.3
Lock 0 register (C55FMC_LOCK0)............................................................................................................3069
72.5.4
Lock 1 register (C55FMC_LOCK1)............................................................................................................3071
72.5.5
Lock 2 register (C55FMC_LOCK2)............................................................................................................3071
72.5.6
Lock 3 register (C55FMC_LOCK3)............................................................................................................3072
72.5.7
Select 0 register (C55FMC_SEL0).............................................................................................................. 3073
72.5.8
Select 1 register (C55FMC_SEL1).............................................................................................................. 3074
72.5.9
Select 2 register (C55FMC_SEL2).............................................................................................................. 3075
72.5.10
Select 3 register (C55FMC_SEL3).............................................................................................................. 3076
72.5.11
Address register (C55FMC_ADR).............................................................................................................. 3077
72.5.12
UTest 0 register (C55FMC_UT0)................................................................................................................3079
72.5.13
UMISR register (C55FMC_UMn)...............................................................................................................3082
72.5.14
UMISR register (C55FMC_UM9)...............................................................................................................3083
72.5.15
Over-Program Protection 0 register (C55FMC_OPP0)............................................................................... 3084
72.5.16
Over-Program Protection 1 register (C55FMC_OPP1)............................................................................... 3085
72.5.17
Over-Program Protection 2 register (C55FMC_OPP2)............................................................................... 3086
72.5.18
Over-Program Protection 3 register (C55FMC_OPP3)............................................................................... 3086
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72.5.19
72.6
72.7
Title
Page
Test Mode Disable Password Check register (C55FMC_TMD)................................................................. 3087
Functional Description..................................................................................................................................................3088
72.6.1
User Mode....................................................................................................................................................3089
72.6.2
Low Power mode......................................................................................................................................... 3097
72.6.3
UTest mode.................................................................................................................................................. 3097
Initialization information.............................................................................................................................................. 3102
Chapter 73
Memory Error Management Unit (MEMU)
73.1
Chip-specific MEMU information................................................................................................................................3103
73.1.1
MEMU configuration...................................................................................................................................3103
73.1.2
MEMU system connections......................................................................................................................... 3103
73.1.3
MEMU error sources................................................................................................................................... 3104
73.1.4
Reporting table implementation...................................................................................................................3104
73.1.5
Concurrent overflow register (OFLW) implementation for MEMU_0....................................................... 3105
73.1.6
Concurrent overflow register (OFLW) implementation for MEMU_1....................................................... 3107
73.1.7
MEMU_0 registers.......................................................................................................................................3108
73.1.8
MEMU_1 registers.......................................................................................................................................3110
73.2
Introduction...................................................................................................................................................................3111
73.3
Features......................................................................................................................................................................... 3112
73.4
Block diagram...............................................................................................................................................................3113
73.5
Design overview........................................................................................................................................................... 3113
73.6
External signal description............................................................................................................................................3117
73.7
Memory map and register definition.............................................................................................................................3118
73.7.1
Overview...................................................................................................................................................... 3118
73.7.2
Control register (MEMU_CTRL)................................................................................................................ 3122
73.7.3
Error flag register (MEMU_ERR_FLAG)...................................................................................................3122
73.7.4
Debug register (MEMU_DEBUG).............................................................................................................. 3126
73.7.5
System RAM correctable error reporting table status register (MEMU_SYS_RAM_CERR_STSn).........3128
73.7.6
System RAM correctable error reporting table address register (MEMU_SYS_RAM_CERR_ADDRn)..3129
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73.7.7
System RAM uncorrectable error reporting table status register (MEMU_SYS_RAM_UNCERR_STS). 3129
73.7.8
System RAM uncorrectable error reporting table address register
(MEMU_SYS_RAM_UNCERR_ADDR)...................................................................................................3130
73.7.9
System RAM concurrent overflow register (MEMU_SYS_RAM_OFLWn)............................................. 3130
73.7.10
Peripheral RAM correctable error reporting table status register
(MEMU_PERIPH_RAM_CERR_STSn).................................................................................................... 3131
73.7.11
Peripheral RAM correctable error reporting table address register
(MEMU_PERIPH_RAM_CERR_ADDRn)................................................................................................ 3132
73.7.12
Peripheral RAM uncorrectable error reporting table status register
(MEMU_PERIPH_RAM_UNCERR_STS).................................................................................................3132
73.7.13
Peripheral RAM uncorrectable error reporting table address register
(MEMU_PERIPH_RAM_UNCERR_ADDR)............................................................................................ 3133
73.7.14
Peripheral RAM concurrent overflow register (MEMU_PERIPH_RAM_OFLWn).................................. 3133
73.7.15
Flash memory correctable error reporting table status register (MEMU_FLASH_CERR_STSn)............. 3134
73.7.16
Flash memory correctable error reporting table address register (MEMU_FLASH_CERR_ADDRn)...... 3135
73.7.17
Flash memory uncorrectable error reporting table status register (MEMU_FLASH_UNCERR_STS)......3135
73.7.18
Flash memory uncorrectable error reporting table address register
(MEMU_FLASH_UNCERR_ADDR)........................................................................................................ 3136
73.7.19
73.8
Flash memory concurrent overflow register (MEMU_FLASH_OFLWn).................................................. 3136
Functional description...................................................................................................................................................3137
73.8.1
Initializing MEMU.......................................................................................................................................3137
73.8.2
Reading the reporting table.......................................................................................................................... 3138
73.8.3
Handling overflows (Multiple error reporting)............................................................................................ 3138
Chapter 74
Fault Collection and Control Unit (FCCU)
74.1
Chip-specific FCCU information..................................................................................................................................3141
74.1.1
FCCU configuration.....................................................................................................................................3141
74.1.2
FCCU register reset values ......................................................................................................................... 3141
74.1.3
FCCU_CFG register event bit values by source (N and C)......................................................................... 3142
74.1.4
Fault inputs...................................................................................................................................................3144
74.1.5
Error signal flow diagram............................................................................................................................ 3149
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Section number
74.2
Title
Page
Introduction...................................................................................................................................................................3150
74.2.1
Acronyms and abbreviations........................................................................................................................3151
74.3
Main features................................................................................................................................................................ 3151
74.4
Block diagram...............................................................................................................................................................3152
74.5
Signal description..........................................................................................................................................................3153
74.5.1
74.6
74.7
74.8
74.9
Signals.......................................................................................................................................................... 3153
Put FCCU in Configuration or Normal state................................................................................................................ 3154
74.6.1
Introduction.................................................................................................................................................. 3154
74.6.2
About changing states.................................................................................................................................. 3155
74.6.3
About locking the configuration.................................................................................................................. 3155
74.6.4
Put FCCU in Configuration state................................................................................................................. 3155
74.6.5
Put FCCU in Normal state........................................................................................................................... 3156
Run operations.............................................................................................................................................................. 3156
74.7.1
Introduction.................................................................................................................................................. 3156
74.7.2
About running operations.............................................................................................................................3157
74.7.3
Run an operation.......................................................................................................................................... 3157
Functional description...................................................................................................................................................3157
74.8.1
Definitions....................................................................................................................................................3157
74.8.2
FSM description........................................................................................................................................... 3158
74.8.3
Fault priority scheme and nesting................................................................................................................ 3161
74.8.4
Fault recovery.............................................................................................................................................. 3162
74.8.5
NMI/WKPU interface.................................................................................................................................. 3164
74.8.6
STCU interface............................................................................................................................................ 3165
74.8.7
Nonvolatile memory interface..................................................................................................................... 3166
74.8.8
EOUT interface............................................................................................................................................ 3167
74.8.9
Error signal flow.......................................................................................................................................... 3176
Register descriptions.....................................................................................................................................................3176
74.9.1
Control (FCCU_CTRL)............................................................................................................................... 3179
74.9.2
Control Key (FCCU_CTRLK).....................................................................................................................3181
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Section number
Title
Page
74.9.3
Configuration (FCCU_CFG)....................................................................................................................... 3182
74.9.4
Noncritical Fault Configuration (FCCU_NCF_CFGn)............................................................................... 3186
74.9.5
Noncritical Fault State Configuration (FCCU_NCFS_CFGn).................................................................... 3187
74.9.6
Noncritical Fault Status (FCCU_NCF_Sn)..................................................................................................3188
74.9.7
Noncritical Fault Key (FCCU_NCFK)........................................................................................................ 3190
74.9.8
Noncritical Fault Enable (FCCU_NCF_En)................................................................................................ 3190
74.9.9
Noncritical Fault Timeout Enable (FCCU_NCF_TOEn)............................................................................ 3191
74.9.10
Noncritical Fault Timeout (FCCU_NCF_TO).............................................................................................3192
74.9.11
Configuration-State Timer Interval (FCCU_CFG_TO).............................................................................. 3193
74.9.12
IO Control (FCCU_EINOUT)..................................................................................................................... 3194
74.9.13
Status (FCCU_STAT)..................................................................................................................................3195
74.9.14
NA Freeze Status (FCCU_N2AF_STATUS).............................................................................................. 3197
74.9.15
AF Freeze Status (FCCU_A2FF_STATUS)................................................................................................3198
74.9.16
NF Freeze Status (FCCU_N2FF_STATUS)................................................................................................3199
74.9.17
FA Freeze Status (FCCU_F2A_STATUS)..................................................................................................3200
74.9.18
Noncritical Fault Fake (FCCU_NCFF)........................................................................................................3201
74.9.19
IRQ Status (FCCU_IRQ_STAT)................................................................................................................. 3202
74.9.20
IRQ Enable (FCCU_IRQ_EN).................................................................................................................... 3204
74.9.21
X Timer (FCCU_XTMR)............................................................................................................................ 3205
74.9.22
Mode Controller Status (FCCU_MCS)........................................................................................................3206
74.9.23
Transient Configuration Lock (FCCU_TRANS_LOCK)............................................................................3208
74.9.24
Permanent Configuration Lock (FCCU_PERMNT_LOCK).......................................................................3209
74.9.25
Delta T (FCCU_DELTA_T)........................................................................................................................ 3209
74.9.26
IRQ Alarm Enable (FCCU_IRQ_ALARM_ENn).......................................................................................3210
74.9.27
NMI Enable (FCCU_NMI_ENn).................................................................................................................3211
74.9.28
Noncritical Fault-State EOUT Signaling Enable (FCCU_EOUT_SIG_ENn)............................................ 3212
74.9.29
Configuration registers.................................................................................................................................3213
74.9.30
FCCU_CFG register bit value sources (N and C) by event......................................................................... 3214
74.10 Use cases and limitations.............................................................................................................................................. 3215
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Section number
Title
Page
74.10.1
Configuration guidelines..............................................................................................................................3215
74.10.2
Recommendations to configure FCCU........................................................................................................ 3216
Chapter 75
Self-Test Control Unit (STCU2)
75.1
Chip-specific STCU2 information................................................................................................................................3217
75.1.1
STCU configuration..................................................................................................................................... 3217
75.1.2
Supported BIST sequence............................................................................................................................ 3218
75.1.3
Device specific STCU Registers .................................................................................................................3218
75.1.4
STCU register reset values ..........................................................................................................................3218
75.1.5
Partition overview........................................................................................................................................ 3219
75.1.6
AUTOLOCK_VALUE for register write access and DCF_COMPLETION value for DCF write
completion....................................................................................................................................................3221
75.1.7
Wait time for writing to the online registers................................................................................................ 3221
75.2
Introduction...................................................................................................................................................................3221
75.3
Main features................................................................................................................................................................ 3221
75.4
Block diagram...............................................................................................................................................................3222
75.5
IPS bus interface........................................................................................................................................................... 3224
75.6
BISTs and BIST partitions............................................................................................................................................3225
75.7
75.6.1
Definition: BIST.......................................................................................................................................... 3225
75.6.2
Definition: BIST partition............................................................................................................................ 3225
75.6.3
Example: BIST partitions on a chip............................................................................................................. 3225
75.6.4
Types of BIST partitions..............................................................................................................................3226
BIST sequences.............................................................................................................................................................3226
75.7.1
Definition: BIST sequence...........................................................................................................................3226
75.7.2
Example: Single-phase BIST sequence....................................................................................................... 3226
75.7.3
Example: Multiphase BIST sequence.......................................................................................................... 3226
75.7.4
Types of BIST sequences.............................................................................................................................3227
75.7.5
Supported BIST sequences.......................................................................................................................... 3227
75.7.6
Definition: Default offline BIST sequence.................................................................................................. 3227
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Section number
75.8
75.9
Title
Page
Functional description...................................................................................................................................................3228
75.8.1
FSM description........................................................................................................................................... 3228
75.8.2
Reset management....................................................................................................................................... 3228
75.8.3
Built-in self-test scheduling......................................................................................................................... 3228
75.8.4
PLL interface................................................................................................................................................3229
75.8.5
FCCU interface............................................................................................................................................ 3229
75.8.6
Watchdogs....................................................................................................................................................3229
75.8.7
SSCM interface............................................................................................................................................ 3231
Register description...................................................................................................................................................... 3231
75.9.1
STCU2 Run Register (STCU2_RUN)......................................................................................................... 3234
75.9.2
STCU2 SK Code Register (STCU2_SKC).................................................................................................. 3235
75.9.3
STCU2 Configuration Register (STCU2_CFG).......................................................................................... 3236
75.9.4
STCU2 Watchdog Granularity (STCU2_WDG)......................................................................................... 3238
75.9.5
STCU2 Error Register (STCU2_ERR_STAT)............................................................................................ 3239
75.9.6
STCU2 Error FM Register (STCU2_ERR_FM)......................................................................................... 3241
75.9.7
STCU2 Off-Line MBIST Status Low Register (STCU2_MBSL)...............................................................3243
75.9.8
STCU2 Off-Line MBIST Status Medium Register (STCU2_MBSM)....................................................... 3248
75.9.9
STCU2 Off-Line MBIST End Flag Low Register (STCU2_MBEL)..........................................................3250
75.9.10
STCU2 Off-Line MBIST End Flag Medium Register (STCU2_MBEM).................................................. 3254
75.9.11
STCU2 MBIST Unrecoverable FM Low Register (STCU2_MBUFML)................................................... 3256
75.9.12
STCU2 MBIST Unrecoverable FM Medium Register (STCU2_MBUFMM)............................................3259
75.9.13
STCU2 MBIST Control Register (STCU2_MB_CTRLn).......................................................................... 3261
75.10 Use cases and limitations.............................................................................................................................................. 3262
75.10.1
Offline self-test sequence.............................................................................................................................3262
75.10.2
Bypass USER Mode.....................................................................................................................................3263
75.10.3
Design implementation information............................................................................................................ 3264
Chapter 76
Cyclic Redundancy Check (CRC) Unit
76.1
Introduction...................................................................................................................................................................3265
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Section number
76.2
Title
Page
Main features................................................................................................................................................................ 3265
76.2.1
Standard features..........................................................................................................................................3265
76.3
Block diagram...............................................................................................................................................................3266
76.4
External signal description............................................................................................................................................3266
76.4.1
76.5
Peripheral bus interface................................................................................................................................3266
CRC memory map and registers................................................................................................................................... 3267
76.5.1
Configuration Register (CRC_CFG)........................................................................................................... 3268
76.5.2
Input Register (CRC_INP)...........................................................................................................................3269
76.5.3
Current Status Register (CRC_CSTAT)...................................................................................................... 3270
76.5.4
Output Register (CRC_OUTP).................................................................................................................... 3270
76.6
Functional description...................................................................................................................................................3271
76.7
Use cases.......................................................................................................................................................................3273
76.7.1
Programming example................................................................................................................................. 3273
76.7.2
Register programming..................................................................................................................................3274
Chapter 77
Register Protection
77.1
Chip-specific Register Protection information............................................................................................................. 3277
77.1.1
Register protection configuration.................................................................................................................3277
77.1.2
Clock Monitor Unit (CMU) protected registers...........................................................................................3278
77.1.3
Fast Oscillator Digital Interface (FXOSC) protected registers.................................................................... 3278
77.1.4
Clock Generation Module (MC_CGM) protected registers........................................................................ 3279
77.1.5
Mode Entry (MC_ME) protected registers.................................................................................................. 3279
77.1.6
Reset Generation Module (MC_RGM) protected registers......................................................................... 3280
77.1.7
Memory Error Management Unit (MEMU) protected registers.................................................................. 3281
77.1.8
PLL Digital Interface (PLL_DIG) protected registers................................................................................. 3281
77.1.9
Power Management Controller digital interface (PMCDIG) protected registers........................................ 3281
77.1.10
SIUL2 protected registers............................................................................................................................ 3282
77.1.11
Slow Oscillator Digital Interface (SXOSC) protected registers.................................................................. 3282
77.1.12
LPU Controller (LPU_CTL) protected registers......................................................................................... 3283
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Section number
Title
Page
77.2
Overview.......................................................................................................................................................................3283
77.3
Features......................................................................................................................................................................... 3284
77.4
Modes of operation....................................................................................................................................................... 3284
77.5
External signal description............................................................................................................................................3285
77.6
Memory map and register definition.............................................................................................................................3285
77.7
77.8
77.6.1
Memory map................................................................................................................................................ 3286
77.6.2
Register descriptions.................................................................................................................................... 3287
Memory map and registers............................................................................................................................................3287
77.7.1
Soft Lock Bit Register n (REG_PROT_SLBRn).........................................................................................3288
77.7.2
Global Configuration Register (REG_PROT_GCR)................................................................................... 3290
Functional description...................................................................................................................................................3290
77.8.1
General......................................................................................................................................................... 3291
77.8.2
Change lock settings.................................................................................................................................... 3291
77.8.3
Access errors................................................................................................................................................ 3294
Chapter 78
Password and Device Security Module (PASS)
78.1
Chip-specific PASS information...................................................................................................................................3297
78.1.1
78.2
78.3
Password and Device Security Module (PASS) configuration....................................................................3297
Introduction...................................................................................................................................................................3303
78.2.1
Overview...................................................................................................................................................... 3303
78.2.2
Features........................................................................................................................................................ 3303
78.2.3
Modes of operation...................................................................................................................................... 3304
Memory map and register definition.............................................................................................................................3304
78.3.1
Life Cycle Status Register (PASS_LCSTAT)............................................................................................. 3306
78.3.2
Challenge Selector Register (PASS_CHSEL)............................................................................................. 3307
78.3.3
Challenge Status Register (PASS_CSTAT)................................................................................................ 3308
78.3.4
Challenge Input Register (PASS_CINn)......................................................................................................3308
78.3.5
Password Group n - Lock 0 Status Register (PASS_LOCK0_PGn)........................................................... 3309
78.3.6
Password Group n - Lock 1 Status Register (PASS_LOCK1_PGn)........................................................... 3311
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Section number
78.4
78.5
78.6
Title
Page
78.3.7
Password Group n - Lock 2 Status Register (PASS_LOCK2_PGn)........................................................... 3312
78.3.8
Password Group n - Lock 3 Status Register (PASS_LOCK3_PGn)........................................................... 3313
DCF clients................................................................................................................................................................... 3316
78.4.1
Censorship....................................................................................................................................................3317
78.4.2
Test mode enable DCF Client...................................................................................................................... 3317
Functional description...................................................................................................................................................3318
78.5.1
Censorship....................................................................................................................................................3318
78.5.2
Debug Interface Access............................................................................................................................... 3319
78.5.3
Flash Memory Read Protection....................................................................................................................3319
78.5.4
Flash Memory Write and Erase Protection.................................................................................................. 3320
78.5.5
Test mode enable......................................................................................................................................... 3321
78.5.6
Test mode enable password......................................................................................................................... 3321
Initialization/application information........................................................................................................................... 3323
78.6.1
Reset.............................................................................................................................................................3323
78.6.2
Setting lock bits in a password group.......................................................................................................... 3323
Chapter 79
Tamper Detect Module (TDM)
79.1
Chip-specific TDM information................................................................................................................................... 3325
79.1.1
Tamper Detection Module (TDM) configuration........................................................................................ 3325
79.1.2
Diary Base Address (DBA) DCF client....................................................................................................... 3325
79.1.3
Tamper Region Override (TO) DCF client..................................................................................................3326
79.1.4
OTPENn DCF clients...................................................................................................................................3326
79.1.5
TDRx_LOCKn DCF clients.........................................................................................................................3329
79.1.6
TDM register reset value..............................................................................................................................3329
79.2
Overview.......................................................................................................................................................................3329
79.3
Features......................................................................................................................................................................... 3331
79.4
External signal description............................................................................................................................................3331
79.5
DCF clients................................................................................................................................................................... 3331
79.5.1
Diary Base Address (DBA) DCF client....................................................................................................... 3332
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Section number
79.6
79.7
Title
Page
79.5.2
Tamper Region Override (TO) DCF client..................................................................................................3333
79.5.3
Software Tamper Region Override Disable (STO_DIS) DCF client.......................................................... 3333
79.5.4
One Time Programmable Enable (OTPEN0) DCF client............................................................................3334
79.5.5
One Time Programmable Enable (OTPEN1) DCF client............................................................................3335
79.5.6
One Time Programmable Enable (OTPEN2) DCF client............................................................................3336
79.5.7
One Time Programmable Enable (OTPEN3) DCF client............................................................................3337
79.5.8
Tamper Region Assignment DCF client (TDRn_LOCK0)......................................................................... 3337
79.5.9
Tamper Region Assignment DCF client (TDRn_LOCK1)......................................................................... 3338
79.5.10
Tamper Region Assignment DCF client (TDRn_LOCK2)......................................................................... 3339
79.5.11
Tamper Region Assignment DCF client (TDRn_LOCK3)......................................................................... 3340
Memory Map/Register Definition.................................................................................................................................3341
79.6.1
TDR Status Register (TDM_TDRSR)......................................................................................................... 3341
79.6.2
Last Flash Programmed Address Register (TDM_LFPAR)........................................................................ 3344
79.6.3
Diary Base Address (TDM_DBA)...............................................................................................................3344
79.6.4
Software Tamper Override Key Region (TDM_STO_KEYn).................................................................... 3345
Functional description...................................................................................................................................................3345
79.7.1
Flash erase counter and tamper detection.................................................................................................... 3345
79.7.2
Assigning blocks to Tamper Detect Regions (TDR)................................................................................... 3347
79.7.3
Diary.............................................................................................................................................................3348
79.7.4
Specifying the diary base address................................................................................................................ 3348
79.7.5
TDR lock status............................................................................................................................................3349
79.7.6
TDR override............................................................................................................................................... 3350
79.7.7
One time programmable (OTP)................................................................................................................... 3350
Chapter 80
Flash Memory Programming and Configuration
80.1
Introduction...................................................................................................................................................................3353
80.2
Selection of flash memory blocks for erase..................................................................................................................3355
80.3
Non-secure write protection..........................................................................................................................................3358
80.4
Secure write protection................................................................................................................................................. 3360
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Section number
80.5
Title
Page
80.4.1
Implementing secure write protection..........................................................................................................3361
80.4.2
Overriding secure write protection.............................................................................................................. 3365
Secure read protection...................................................................................................................................................3367
80.5.1
Implementing secure read protection........................................................................................................... 3369
80.5.2
Overriding secure read protection................................................................................................................3373
80.6
Debug port enable/disable.............................................................................................................................................3374
80.7
Tamper detection.......................................................................................................................................................... 3374
80.7.1
Implementing tamper detection................................................................................................................... 3374
80.7.2
Creating the tamper detect diary.................................................................................................................. 3375
80.7.3
Assigning blocks to Tamper Detection Regions (TDRs).............................................................................3377
80.7.4
Overriding tamper detection........................................................................................................................ 3378
80.8
Implementing OTP........................................................................................................................................................3379
80.9
Implementing test mode disable................................................................................................................................... 3379
80.9.1
Unconditional test mode disable seal...........................................................................................................3380
80.9.2
Passcode-protected test mode disable seal...................................................................................................3381
80.9.3
Selecting flash memory blocks for test mode disable seal...........................................................................3381
80.10 Security configuration planning....................................................................................................................................3385
80.10.1
Hardware Security Module (HSM)..............................................................................................................3385
80.10.2
Creating password groups............................................................................................................................ 3386
80.10.3
Planning secure write protection..................................................................................................................3386
80.10.4
Planning secure read protection................................................................................................................... 3387
80.10.5
Planning debug port enable/disable............................................................................................................. 3387
80.10.6
Planning OTP flash memory block assignment........................................................................................... 3387
80.10.7
Planning factory test mode disable.............................................................................................................. 3387
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Chapter 1
About This Manual
1.1 Audience
This reference manual is intended for system software and hardware developers and
applications programmers who want to develop products with this device. It assumes that
the reader understands operating systems, microprocessor system design, and basic
principles of software and hardware.
1.2 Organization
This manual has two main sets of chapters.
1. Chapters in the first set contain information that applies to all components on the
chip.
2. Chapters in the second set are organized into functional groupings that detail
particular areas of functionality.
• Examples of these groupings are clocking, timers, and communication interfaces.
• Each grouping includes chapters that provide a technical description of
individual modules.
1.2.1 Attachments
This document includes key information in attachments. Examples include a memory
map and I/O details. Open these attachments and use their content in conjunction with the
document’s content.
1.3 Module descriptions
Each module chapter has two main parts:
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Module descriptions
• The first section, Chip-specific [module name] information, provides details such as
the number of module instances on the chip and connections between the module and
other modules. Read this section first because its content is crucial to understanding
the information in other sections of the chapter.
• The subsequent sections provide general information about the module, including its
signals, registers, and functional description.
E
L
Chapter 49
Enhanced Serial Communication Interface (eSCI)
P
M
49.1 Chip-specific eSCI information
This chip has six instances of the eSCI module. Some feature details vary between the
instances.
The following table summarizes the feature differences. The table does not list feature
details that the instances share.
Table 49-1. eSCI instance feature differences
Instance
DMA support
A
X
E
eSCI_A and eSCI_B
Yes
eSCI_C, eSCI_D, eSCI_E, and eSCI_F
No: descriptions of eSCI DMA functionality do not apply to
these instances
Chip-specific information
that should be read first
NOTE
For eSCI_D, the single wire feature does not apply for TX/RX
via PCSA3 because this pad works only as an output.
49.2 Introduction
The eSCI block is an enhanced SCI block with a LIN master interface layer and DMA
support. The LIN master layer complies with the specifications LIN 1.3, LIN 2.0, LIN
2.1, and SAE J2602/1.
49.2.1 Bibliography
Beginning of general
module information
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003
Sample Reference Manual
Figure 1-1. Example: chapter chip-specific information and general module information
1.3.1 Example: chip-specific information that clarifies content in
the same chapter
The example below shows chip-specific information that clarifies general module
information presented later in the chapter. In this case, the chip-specific register reset
values supercede the reset values that appear in the register diagram.
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Chapter 1 About This Manual
Chapter 34 Software Watchdog Timer (SWT)
accesses by masters without permission. If the RIA bit in the SWT_CR is set then the
SWT generates a system reset on an invalid access otherwise a bus error is generated. If
either the HLK or SLK bits in the SWT_CR are set, then the SWT_CR, SWT_TO,
SWT_WN, and SWT_SK registers are read-only.
E
L
The SWT memory map is shown in the following table.
SWT memory map
Chapter 34
Software Watchdog Timer (SWT)
Address
offset (hex)
A
X
34.2 Introduction
0005_FCD0h
This section provides an overview, list of features, and modes of operation for the SWT.
34.2.1 Overview
E
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system
lockup in situations such as software getting trapped in a loop or if a bus transaction fails
to terminate. When enabled, the SWT requires periodic execution of a watchdog
servicing operation. The servicing operation resets the timer to a specified time-out
period. If this servicing action does not occur before the timer expires the SWT generates
an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt
on an initial time-out. A reset is always generated on a second consecutive time-out.
32
R/W
SWT Time-out Register (SWT_TO)
32
R/W
See section
SWT Window Register (SWT_WN)
32
R/W
0000_0000h 34.4.4/1335
10
SWT Service Register (SWT_SR)
32
W
0000_0000h 34.4.5/1335
14
SWT Counter Output Register (SWT_CO)
32
R
0000_0000h 34.4.6/1336
18
SWT Service Key Register (SWT_SK)
32
R/W
0000_0000h 34.4.7/1336
34.4.3/1334
34.4.1 SWT Control Register (SWT_CR)
NOTE
The reset value for the SWT_CR is implementation specific.
See the configuration information.
The SWT_CR contains fields for configuring and controlling the SWT.
This register is read-only if either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
Address: 0h base + 0h offset = 0h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0*
0
R
MAP7
0005_FCD0h
0000_0000h 34.4.2/1334
SWT Interrupt Register (SWT_IR)
8
MAP6
TO
FF00_010Ah
4
C
MAP5
FF00_010Bh
34.4.1/1331
MAP4
CR
See section
MAP3
Table 34-1. Chip-specific SWT register reset values
SWT_B
R/W
MAP2
The following table identifies chip-specific reset values of SWT registers.
SWT_A
32
MAP1
34.1.1 SWT register reset values
Register
SWT Control Register (SWT_CR)
MAP0
This chip has two instances of the SWT module: SWT_A and SWT_B.
Section/
page
0
P
M
34.1 Chip-specific SWT information
Width
Access Reset value
(in bits)
Register name
Reset
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RIA
WND
ITR
HLK
SLK
CSL
STP
FRZ
WEN
0*
0*
0*
0*
0*
0*
0*
0*
0*
W
0
R
SMD
W
Reset
0*
0*
0*
0*
0*
0*
0*
* Notes:
• The reset value for the SWT_CR is implementation specific. See the configuration information.
Sample Reference Manual
Sample Reference Manual
Figure 1-2. Example: chip-specific information that clarifies content in the same chapter
1.3.2 Example: chip-specific information that refers to a different
chapter
The chip-specific information below refers to another chapter's chip-specific information.
In this case, read both sets of chip-specific information before reading further in the
chapter.
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Register descriptions
E
L
P
M
A
Chapter 10
Crossbar Integrity Checker (XBIC)
Chapter 9
Crossbar Switch (XBAR)
10.1 Chip-specific XBIC information
9.1 Chip-specific XBAR information
This chip has one instance of the XBIC module.
This chip has one instance of the XBAR module.
10.1.1 XBIC master and slave assignments
The XBIC identifies each XBAR master and slave in terms of the master or slave's
physical port number. See the "Physical master port" assignments in Table 9-1 and the
"Slave port" assignments in Table 9-2.
10.1.2 Unimplemented MCR and ESR fields
X
E
On this chip, the MCR[SE5] and ESR[DPSE5] fields are not implemented. In XBIC
Module Control Register (XBIC_MCR) and XBIC Error Status Register (XBIC_ESR),
these fields are reserved.
10.2 Overview
The Crossbar Integrity Checker (XBIC) verifies the integrity of the crossbar transfers.
For forward signals (master to slave), it is done by verifying the integrity of the attribute
information using an 8-bit Error Detection Code (EDC). The EDC detects any single- or
double-bit errors in the attribute information and signals the Fault Collection and Control
Unit (FCCU) when an error is detected. For feedback signals (slave to master), it is done
by comparing the consistency of the signals during the AHB dataphase.There are three
signals from slave to master, hready, hresp0, and hresp2. If any of the master signals is
different from the slave signals during dataphase, the error will be reported in the Error
Status Register.
9.1.1 XBAR master and slave assignments
The following table lists the XBAR physical port numbers and logical IDs for all master
ports on this SoC.
• Each port number matches the default priority assigned to the corresponding physical
master port. This default priority equals the reset value of the priority field for each
master port in the PRSn registers.
• A priority value of 0 is the highest priority. There is no "disabled" value for the
priority.
• A Nexus_3 module and core data bus share the same physical master port for each
core.
The logical master ID corresponds to the logical address provided by the master module
and is unique for each module. The logical master IDs are used by the bus masters
connected to the XBAR. The Nexus master is identified by setting the MSB in the 4-bit
field that supplies the master ID number.
Table 9-1. XBAR master ports and logical master IDs
Physical master port
Logical master ID
Core0 instruction
Module
0
0
Core0 data
1
0
Nexus_3_0
8
Core1 instruction
2
1
Core1 data
3
1
Nexus_3_1
Sample Reference Manual
9
Comment
Nexus_3_0 arbitrates with Core0 data for XBAR port 1
Nexus_3_1 arbitrates with Core1 data for XBAR port 3
Table continues on the next page...
Sample Reference Manual
Figure 1-3. Example: chip-specific information that refers to a different chapter
1.4 Register descriptions
Module chapters present register information in:
• Memory maps containing:
• An offset from the module's base address
• The name and acronym/abbreviation of each register
• The width of each register (in bits)
• Each register's reset value
• The page number on which each register is described
• Register figures
• Field-description tables
• Associated text
The register figures show the field structure using the conventions in the following figure.
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Chapter 1 About This Manual
R
W
Mnemonic
R Mnemonic
R
W
W Mnemonic
W Mnemonic
W Mnemonic
W Mnemonic
Write-only
Write-only
reads zero
Write-only
reads one
R Mnemonic
R Mnemonic
R Mnemonic
R Mnemonic
W
W
Read-only
writes undefined
Write one to clear
W
0
W
Write-only
reads undefined
R
1
R
Read-only
Read/write
R
0
R
Read-only
writes zero
R
Reserved
W
Reserved,
unimplemented
1
W
Read-only
writes one
R
R
1
Write-only one
W
0
Write-only zero
1
W
Read-only one
w1c
R
0
W
Read-only zero
Figure 1-4. Register figure conventions
1.5 Conventions
1.5.1 Notes, Cautions, and Warnings
Note, Caution, and Warning notices appear throughout this manual. Each notice type
alerts readers to a specific kind of information.
NOTE
Notes convey information that may be tangential to a topic or
that may not apply to all readers.
CAUTION
Caution notices call out information that readers should know
before taking further action. Cautions frequently point to
trouble spots that may damage the chip or board.
WARNING
Warning notices inform readers about actions that could result
in unwanted consequences, especially those that may cause
bodily injury.
1.5.2 Numbering systems
The following suffixes identify different numbering systems:
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Conventions
This suffix
Identifies a
b
Binary number. For example, the binary equivalent of the number 5 is written 101b. In some cases,
binary numbers are shown with the prefix 0b.
d
Decimal number. Decimal numbers are followed by this suffix only when the possibility of confusion
exists. In general, decimal numbers are shown without a suffix.
h
Hexadecimal number. For example, the hexadecimal equivalent of the number 60 is written 3Ch. In
some cases, hexadecimal numbers are shown with the prefix 0x.
1.5.3 Typographic notation
The following typographic notation is used throughout this document:
Example
Description
placeholder, x
Items in italics are placeholders for information that you provide. Italicized text is also used for
the titles of publications and for emphasis. Plain lowercase letters are also used as
placeholders for single letters and numbers.
code
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction
mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type
is also used for example code. Instruction mnemonics and directives in text and tables are
shown in all caps; for example, BSR.
SR[SCM]
A mnemonic in brackets represents a named field in a register. This example refers to the
Scaling Mode (SCM) field in the Status Register (SR).
REVNO[6:4], XAD[7:0]
Numbers in brackets and separated by a colon represent either:
• A subset of a register's named field
For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that
occupies bits 6–0 of the REVNO register.
• A continuous range of individual signals of a bus
For example, XAD[7:0] refers to signals 7–0 of the XAD bus.
1.5.4 Special terms
The following terms have special meanings:
Term
Meaning
asserted
Refers to the state of a signal as follows:
• An active-high signal is asserted when high (1).
• An active-low signal is asserted when low (0).
deasserted
Refers to the state of a signal as follows:
• An active-high signal is deasserted when low (0).
• An active-low signal is deasserted when high (1).
In some cases, deasserted signals are described as negated.
Table continues on the next page...
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Chapter 1 About This Manual
Term
Meaning
reserved
Refers to a memory space, register, field, or programming setting. Writes to a reserved location can
result in unpredictable functionality or behavior.
• Do not modify the default value of a reserved programming setting, such as the reset value of
a reserved register field.
• Consider undefined locations in memory to be reserved.
w1c
Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared."
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Chapter 2
Introduction
2.1 Introduction
The MPC5746C is a 32-bit Power Architecture based microcontroller unit (MCU) for
automotive applications and builds on the successful legacy of the MPC56xx family of
microcontrollers.
There are two application processor cores on this device.
Table 2-1. Processor cores
Computational Shell
Core0
Main Core 0
e200z420n3
Core1
Peripheral Core
e200z210n3
2.1.1 Target Applications
The family of devices are designed to address a wide variety of automotive applications
including but not limited to the door modules, seat modules, central body, vehicle body
controllers, smart junction box, front module applications, high end gateway or combined
body controller and gateway applications.
2.2 Block diagram
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Family comparison
80 MHz e200z2
160 MHz e200z4
System bus masters
64-bit AHB
8 KB i-cache 4 KB d-cache
E2 E-ECC
SPFP-APU
Nexus 3+
Nexus 3+
E2 E-ECC
64-bit AHB
64-bit data
E2 E-ECC
Flash Memory
2xRAM
E2 E-ECC
E2 E-ECC
3 x SA-PF buffers
64-bit wide RAM
Triple ported
256 KB array
3 MB array (inc EEE)
256 KB array
System
Ethernet
(ENET)
HSMv2
eDMA
Flexray
SMPU
Peripheral
bridge
E2 E-ECC
Low power
unit interface
(LPU)
Peripheral clusters
68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)*
(mix int and ext)
7 x FlexCAN*
16 x LINFlexD
4 x I2C
3 x analog
comparator (CMP)
4 x DSPI
4 x SPI
3 x SAI
3 x FCD
2 x eMIOS + BCTU
2-core INTC
DMA and
2 x channel mux
1 x CRC
WKPU
2 x STM
BAF
PMC
FMPLL
16 MHz FIRC
RTC/API
DEBUG/
JTAG
2 x SWTs
FCCU
16 x SEMA42
PASS
16 x PIT-RTI
SSCM
32 KHz
SXOSC
MC_CGM,
MC_PCU,
MC_ME,
MC_RGM
128 KHz
SIRC
SIUL
8–40 MHz
FXOSC
STCU
(MBIST)
MEMU
CMU
Padkeeper
support
TDM
Register
protection
* All FlexCANs optionally support
CAN FD
Figure 2-1. MPC5746C block diagram
2.3 Family comparison
The following table provides a summary of the different members of the MPC5746C
family and their proposed features. This information is intended to provide an
understanding of the range of functionality offered by this family. For full details of all of
the family derivatives please contact your marketing representative.
NOTE
All optional features (Flash memory, RAM, Peripherals) start
with lowest number or address (e.g., FlexCAN0) and end at
highest available number or address (e.g., MPC574xB/C have 6
CAN, ending with FlexCAN5).
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Chapter 2 Introduction
Table 2-2. MPC5746C Family Comparison1
Feature
MPC5745B
MPC5744B
MPC5746B
MPC5744C
MPC5745C
MPC5746C
CPUs
e200z4
e200z4
e200z4
e200z4
e200z4
e200z4
e200z2
e200z2
e200z2
FPU
e200z4
e200z4
e200z4
e200z4
e200z4
e200z4
Maximum
Operating
Frequency2
160MHz (Z4)
160MHz (Z4)
160MHz (Z4)
160MHz (Z4)
160MHz (Z4)
160MHz (Z4)
80MHz (Z2)
80MHz (Z2)
80MHz (Z2)
Flash memory
2 MB
2 MB
3 MB
EEPROM
support
RAM
1.5 MB
3 MB
1.5 MB
Emulated up to 64K
256 KB
192 KB
Emulated up to 128K
384 KB
(Optional
512KB)3
192 KB
ECC
End to End
SMPU
16 entry
DMA
32 channels
10-bit ADC
36 Standard channels
256 KB
384 KB
(Optional
512KB)3
32 External channels
12-bit ADC
15 Precision channels
16 Standard channels
Analog
Comparator
3
BCTU
1
SWT
1, SWT[0]
24
STM
1, STM[0]
2
PIT-RTI
16 channels PIT
1 channels RTI
RTC/API
1
Total Timer I/O5
64 channels
16-bits
LINFlexD
FlexCAN
1
1
Master and Slave (LINFlexD[0], 11 Master
(LINFlexD[1:11])
Master and Slave (LINFlexD[0], 15 Master
(LINFlexD[1:15])
6 with optional CAN FD support (FlexCAN[0:5])
8 with optional CAN FD support (FlexCAN[0:7])
DSPI/SPI
4 x DSPI
4 x SPI
I2C
4
4
4
SAI/I2S
3
3
3
4
3
FXOSC
8 - 40 MHz
SXOSC
32 KHz
FIRC
16 MHz
SIRC
128 KHz
Table continues on the next page...
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Family comparison
Table 2-2. MPC5746C Family Comparison1 (continued)
Feature
MPC5745B
MPC5744B
MPC5746B
MPC5744C
FMPLL
1
Low Power Unit
(LPU)
Yes
MPC5745C
FlexRay 2.1
(dual channel)
Yes, 128 MB
Yes, 128 MB
Yes, 128 MB
Yes, 128 MB
Ethernet (RMII,
MII + 1588, Muti
queue AVB
support)
1
1
1
1
CRC
1
MEMU
2
STCU2
1
HSM-v2
(security)
Optional
Censorship
Yes
FCCU
1
Safety level
Specific functions ASIL-B certifiable
User MBIST
Yes
I/O Retention in
Standby
Yes
GPI
1 (100 BGA), 17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA)
GPIO
65 (100 BGA), 129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA)
Debug
JTAGC,
MPC5746C
cJTAG
Nexus
Z4 N3+ (Only available on 324BGA (development only) )
Z2 N3+ (Only available on 324BGA (development only) )
Packages
176 LQFP-EP
176 LQFP-EP
176 LQFP-EP
176 LQFP-EP
176 LQFP-EP
176 LQFP-EP
256 BGA
256 BGA
256 BGA
256 BGA
256 BGA
256 BGA,
100 BGA
100 BGA
100 BGA
100 BGA
100 BGA
324 BGA
(development
only)
100 BGA
1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package
dependent.
2. Based on 125°C ambient operating temperature and subject to full device characterization.
3. Contact NXP representative for part number
4. Additional SWT included when HSM option selected
5. See device datasheet and reference manual for information on to timer channel configuration and functions.
Table 2-3. MPC5746C Family Comparison - NVM Memory Map 1
Start Address
End Address
Flash block
RWW partition
MPC5744
MPC5745
MPC5746
0x01000000
0x0103FFFF
256 KB code
Flash block 0
6
available
available
available
Table continues on the next page...
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Chapter 2 Introduction
Table 2-3. MPC5746C Family Comparison - NVM Memory Map 1 (continued)
Start Address
End Address
Flash block
RWW partition
MPC5744
MPC5745
MPC5746
0x01040000
0x0107FFFF
256 KB code
Flash block 1
6
available
available
available
0x01080000
0x010BFFFF
256 KB code
Flash block 2
6
available
available
available
0x010C0000
0x010FFFFF
256 KB code
Flash block3
6
available
available
available
0x01100000
0x0113FFFF
256 KB code
Flash block 4
6
not available
available
available
0x01140000
0x0117FFFF
256 KB code
Flash block 5
7
not available
available
available
0x01180000
0x011BFFFF
256 KB code
Flash block 6
7
not available
not available
available
0x011C0000
0x011FFFFF
256 KB code
Flash block 7
7
not available
not available
available
0x01200000
0x0123FFFF
256 KB code
Flash block 8
7
not available
not available
available
0x01240000
0x0127FFFF
256 KB code
Flash block 9
7
not available
not available
available
Table 2-4. MPC5746C Family Comparison - NVM Memory Map 2
Start Address
End Address
Flash block
RWW partition
MPC5744B
MPC5745B
MPC5746B
MPC5744C
MPC5745C
MPC5746C
0x00F900001
0x00F93FFF
16 KB data Flash
2
available
available1
0x00F94000
0x00F97FFF
16 KB data Flash
2
available
available1
0x00F98000
0x00F9BFFF
16 KB data Flash
2
available
available1
0x00F9C000
0x00F9FFFF
16 KB data Flash
2
available
available1
0x00FA0000
0x00FA3FFF
16 KB data Flash
3
not available
available1
0x00FA4000
0x00FA7FFF
16 KB data Flash
3
not available
available1
0x00FA8000
0x00FABFFF
16 KB data Flash
3
not available
available1
0x00FAC000
0x00FAFFFF
16 KB data Flash
3
not available
available1
0x00FB0000
0x00FB7FFF
32 KB data Flash
Reserved
0x00FB8000
0x00FBFFFF
32 KB data Flash
Reserved
0x00FC0000
0x00FC7FFF
32 KB data Flash
0
available
available
0x00FC8000
0x00FCFFFF
32 KB data Flash
1
available
available
0x00FD0000
0x00FD7FFF
32 KB data Flash
1
available
available
0x00FD8000
0x00FDFFFF
32 KB data Flash
1
available
available
0x00FE0000
0x00FEFFFF
64 KB data Flash
0
available
available
0x00FF0000
0x00FFFFFF
64 KB data Flash
1
available
available
1. Flexible patitions for boot and EEPROM
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Feature list
Table 2-5. MPC5748G Family Comparison - NVM Memory Map 3
Start Address
End Address
Flash block
RWW
MPC5744B
MPC5745B
MPC5746B
MPC5744C
MPC5745C
MPC5746C
0x00610000
0x0061FFFF
64 KB HSM Code
block 2
0
available
available
0x00620000
0x0062FFFF
64 KB HSM Code
block 3
1
available
available
HSM Data
0x00630000
0x00F7FFFF
9536 KB
Reserved
HSM Data
0x00F80000
0x00F83FFF
16 KB HSM data
block 0
4
available
available
0x00F84000
0x00F87FFF
16 KB HSM data
block 1
5
available
available
0x00F88000
0x00F8BFFF
16 KB
Reserved
Small HSM Code Block
0x00F8C000
0x00F8FFFF
16 KB Code Flash
block
0
available
available
Table 2-6. MPC5746C Family Comparison - RAM Memory Map
Start Address
End Address
Allocated size
Description
MPC5744
MPC5745
MPC5746
0x40000000
0x40001FFF
8 KB
SRAM0
available
available
available
0x40002000
0x4000FFFF
56 KB
SRAM1
available
available
available
0x40010000
0x4001FFFF
64 KB
SRAM2
available
available
available
0x40020000
0x4002FFFF
64 KB
SRAM3
available
available
available
0x40030000
0x4003FFFF
64 KB
SRAM4
not available
available
available
0x40040000
0x4004FFFF
64 KB
SRAM5
not available
not available
available
0x40050000
0x4005FFFF
64 KB
SRAM6
not available
not available
available
0x40060000
0x4006FFFF
64 KB
SRAM7
not available
not available
optional
0x40070000
0x4007FFFF
64 KB
SRAM8
not available
not available
optional
2.4 Feature list
On-chip modules available within the device include the following features:
Table 2-7. Feature List
Cores
• 1 x 160 MHz Power Architecture® e200Z4 Dual issue, 32-bit CPU
• Single precision floating point operations
• 8 KB instruction cache and 4 KB data cache
• Only variable length encoding (VLE) for significant code density improvements
• 1 x 80 MHz Power Architecture® e200Z2 Single issue, 32-bit CPU
Table continues on the next page...
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Chapter 2 Introduction
Table 2-7. Feature List (continued)
• Using variable length encoding (VLE) for significant code size footprint reduction
• End-to-End ECC ensuring full protection of all data accesses throughout the system,
from each of the core through the crossbar and into the memories and peripheral bridge
Supported memories
• 3 MB on-chip flash supported with the flash controller
• 3 x flash page buffers (3 port flash controller) to improve access time to code and
data held in flash
• 512 KB on-chip SRAM across two RAM ports
Clocks
• 8-40 MHz Fast External Crystal Oscillator (FXOSC)
• 16 MHz Fast Internal RC Oscillator (FIRC)
• 128 KHz Slow Internal RC Oscillator(SIRC)
• 32 KHz Slow External Crystal Oscillator (SXOSC)
• Clock Monitor Unit (CMU) to support monitoring of critical clocks
• Frequency modulated phase-locked loop (FMPLL)
• Sophisticated clocking architecture allowing core and peripheral clocks to be scaled
independently of the peripheral operation (some restrictions may apply)
System
• Two System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16byte region granularity
• 16 Semaphores to manage access to shared resource
• Interrupt controller (INTC) capable of routing interrupts to any CPU
• Single crossbar switch architecture for concurrent access to peripherals, flash, and
RAM from multiple bus masters
• 32-channels eDMA controller with multiple transfer request sources using DMAMUX
• Body Cross Trigger Unit (BCTU) to enable synchronization of ADC conversions with a
timer event from the eMIOS or from the PIT
• Capable of triggering groups of channels
• Supports wake-up from low power modes via the wakeup unit (WKPU)
Communications
• Four Deserial Peripheral Interface (DSPI)
• Four Serial Peripheral interface (SPI)
• 16 serial communication interface (LIN)
• Eight enhanced FlexCAN modules with configurable buffers
• Each instance supports DMA on RxFIFO
• Low power mode with Pretended Networking support on a single FlexCAN
(FlexCAN0)
• CAN FD support
• Four inter-IC communication interface (I2C)
• One dual-channel FlexRay Controller with 128 Message buffers and stopwatch function
for synchronisation to OS
• One ENET complex (10/100 Ethernet) that supports 1588 and MII/RMII
• Enhanced ENET complex supporting multiple queues
• Mutiple queue AVB support
• Three Synchronous Audio Interface (SAI) capable of supporting six stereo audio
channels
• Three Fractional clock dividers (FCD) operating in conjunction with the SAIs
Analog
• Two analog-to-digital converters (ADC), one 10-bit and one 12-bit
• 12-bit ADC has independent reference on larger packages
• Each ADC can be independently 3.3 V or 5 V
• Three analogue comparators (CMP) providing up to 24 compare inputs
• Supports analog input comparison without any software supervision during
STANDBY mode
• Supports four instances of IGF, one for each HF interface
Timers
• Real Time Counter (RTC) with clock source from internal 128 KHz SIRC, 32 KHz
SXOSC, 16 MHz FIRC or the 8-40 MHz FXOSC
• Two System Timer Module (STM), each with 4 compare registers.
Table continues on the next page...
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Package Options
Table 2-7. Feature List (continued)
• Two Software WatchDog Timers (SWT) clocked by the SIRC, one additional in HSM
• 16 Periodic Interrupt Timers (PIT) channels with 32-bit counter resolution
• Channels can be concatenated together to produce a 64-bit resolution
• RTI also supported and clocked by FXOSC
• 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels
• Provides a range of 16-bit input capture, output compare, and pulse width
modulation functions
• Improved flexibility by addition of second global counter bus and second global
pre-scaler
Boot support
• Boot Assist Flash (BAF) supports internal flash programming via a serial link (LIN/SCI
and FlexCAN)
• BAF runs initialization routines at the device boot
• Device always boot on e200Z4
• Device can boot from any core on exit from STANDBY or LPU_RUN
Input output pin configuration
• Maximum amount of general purpose pins supporting input and output operations
(Number supported is package dependent)
• General purpose I/O support state retention in all low power modes. State retention
controlled by pad keeper logic. Limted I/O supports state retention in Power Domain 0
(PD0) and Power Domain 1 (PD1)
• Configurable I/O domains supporting Ethernet and general I/O (package dependent)
Power management
• On-chip power management controller (PMC-Dig)
• External regulation mode where low voltage input supply of ~1.25 V (+/- 4 %) is
regulated and supplied through on board power supply
• Internal regulation mode where low voltage input supply of ~1.25 V (+/- 4 %) is
regulated by on-chip PMC and supplied via external ballast transistor
• Internal regulation mode where low voltage input supply of ~1.25 V (+/- 4 %) is
regulated by on-chip PMC and supplied via internal ballast transistor
Debug
• e200Z2 core: Nexus development interface (NDI) per IEEE-ISTO 5001-2012 Class 3+
• Only class 1 debug interface supported during LPU mode
• e200Z4 core: Nexus development interface (NDI) per IEEE-ISTO 5001-2012 Class 3+
• Device/board boundary Scan testing supported with per JTAG (IEEE 1149.1) and
cJTAG (1149.7)
• Possible to trace SRAM accesses via nexus auxiliary interface
Safety
• One hardware Cyclic Redundancy Check (CRC) module
• Two Memory Error Management Unit (MEMU)
• One Fault Collection and Control Unit (FCCU)
• One Self-Test Control Unit (STCU)
• Targeted for specific device functions being ASIL-B certifiable
Security
• One Password and Device Security Module (PASS) implementing password-based
read and write protection for flash blocks
• Tamper Detection Module (TDM) provides flash memory write protection mechanism
• Register protection supported on key registers
• Hardware Security Module (HSM) enabling advanced security management
2.5 Package Options
The following package options are available in the device:
• 100-pin BGA, 1mm ball pitch, 11mm x 11mm outline
• 176-pin LQFP, 0.5mm pitch, 24mm x 24mm outline
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Chapter 2 Introduction
• 256-pin BGA, 1mm ball pitch, 17mm x 17mm outline
• 324-pin BGA, 1mm ball pitch, 19mm x 19mm outline (development only)
2.6 Modes of Operation
This family of devices will have two types of modes, SYSTEM modes and USER modes.
SYSTEM Modes
SYSTEM modes are entered automatically on system events or on application request.
There are three SYSTEM modes: RESET, SAFE, and DRUN as described in the table
below.
Table 2-8. System Modes
Mode
Description
Entry
RESET
System remains in this mode
until all resources are
available for S/W to take
device control. This mode
manages hardware
initialization of flash and
various chip configuration
registers
System reset assertion from
RGM
SAFE
May be entered on detection Hardware fail, Software
of an error, reaction of which request from DRUN, RUNx
has been pre-configured via
MC_RGM and FCCU. Forces
system into pre-defined safe
configuration such as the
system clock source switches
to internal fast RC oscillator
and output pins are forced
into high impedance (Hi-z)
from which the system may
try to recover.
System reset assertion,
DRUN via Software
DRUN
Default entry mode for the
embedded software. Provides
full system accessibility &
enables system configuration.
BAF is executed in DRUN
mode if exiting from RESET
mode or STANDBY mode
provided its is configured to
execute BAF on standby exit
It is possible to transition to all
the modes from DRUN
Reset removed, from any of
the mode SAFE and RUNx
via software configuration,
from LPU_RUN via software
configuration, STANDBY/
LPU_STANDBY on wakeup
Exit
System reset deassertion
from RGM
USER Modes
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Modes of Operation
USER modes are used to control the device performance and consumption during normal
application operation. The modes are organized according to the performance provided
by the device in each mode. There are various USER modes as described in the table
below, depending on the specific device: RUNx, STOP, STANDBY, LPU_RUN,
LPU_STOP and LPU_STANDBY.
Table 2-9. User Modes
Mode
RUN0,
Description
Entry
Exit
These are software running
software request from DRUN, Device can enter in all modes
modes where most
interrupt event from wakeup
SAFE, RUNx, STOP, RESET,
processing activity is done.
request from STOP
LPU_RUN via software
These various run modes
allow to enable different clock
& power configurations of the
system with respect to each
other
RUN1,
RUN2,
RUN3
STOP0
Advanced low-power modes Software request from RUNx
during which the clock to the
core is disabled. STOP0 may
be configured to switch off
most of the peripherals
including oscillator for efficient
power management at the
cost of higher wakeup latency
STANDBY/LPU_STANDBY
Reduced-leakage low-power
mode during which power is
cut off from most of device
and content is lost and must
be restored from backup
Reset asserted, SAFE on
hardware failure, RUNx on
wakeup event
Software request from RUNx, Device will enter in DRUN
DRUN, LPU_RUN modes
mode on STANDBY exit and
LPU_RUN on
LPU_STANDBY exit. It is
possible to exit from
LPU_STANDBY to DRUN if
LPU_MCR[DIRECT_DRUN] is
configured.
Advanced Low Power USER modes: Advanced Low Power USER modes are used to
control the device performance and consumption during advanced low power operation.
The modes are organized according to the performance provided by the device in each
mode.
There are three modes on this device: LPU_RUN, LPU_STOP, and LPU_SLEEP.
Table 2-10. Advanced Low Power USER modes
Mode
LPU_RUN
Description
Entry
Exit
In LPU_RUN mode only small Software request from RUNx, Device will enter into DRUN
subsystem with Z2 core and
DRUN, from LPU_STANDBY mode on LPU_RUN exit
some communication
and LPU_STOP on wakeup
peripheral is powered. Other
cores and majority of modules
are power gated. Only FIRC
and FXOSC can be source of
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Chapter 2 Introduction
Table 2-10. Advanced Low Power USER modes (continued)
Mode
Description
Entry
Exit
system clock as PLL is power
gated.
LPU_STOP
In LPU_STOP mode, Z2 core On software request from
enters the low-power state
LPU_RUN
and its clock is gated.
FlexCAN pretended network
feature is available but all
peripherals are stopped,
clocks are gated to all
modules in LPU domain.
LPU_STOP may be
configured to switch off
oscillators for efficient power
management at the cost of
higher wakeup latency
Device will enter into
LPU_RUN mode on interrupt
from FlexCAN, WKPU or
SWT timeout
LPU_SLEEP
Z2 core is stopped and clock
gated by hardware.
LPU_SLEEP may be
configured to clock gated
module clocks by configuring
LPU_MDIS
The device can exit to
LPU_RUN mode on any
peripheral interrupt, external
interrupt or WKPU source.
On software request from
LPU_RUN
Recoverable
fault
Software
request
SAFE
RUN0
RESET
DRUN
RUN1
RUN2
POWERUP/
Non recoverable
fault
STOP0
LPU_SLEEP
LPU_RUN
LPU_STOP
STANDBY or LPU_STANDBY
Figure 2-2. Mode relationship
NOTE
If we are entering into complete power gated mode via
LPU_RUN mode, it is called LPU_STANDBY else it is
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Modes of Operation
referred as STANDBY. Only difference in two modes is that
user can select clock sources to be ON/OFF by configuring
ME_STANDBY0_MC for STANDBY mode and
LPU_STANDBY_CF for LPU_STANDBY mode
When exiting STANDBY or LPU_RUN, the user will determine which core(s) are active.
This will be optionally the Z2 or Z4.
Brief Description of Power Domains
The Power Control Unit (MC_PCU) and Low Power Subsystem LPU are used to manage
all mode transition. Power can be saved by gating the power supply via a power
switching device. The device is grouped into 3 parts which are called “power domains”.
When a power domain is disconnected from the supply, the power consumption is
reduced to zero in that domain. Any status information of such a power domain is lost.
Power Domain0 (PD0): It is an always alive domain, which consists of modules required
for mode transitions and some timers.
Power Domain1 (PD1): It consists of modules required to be operational in LPU modes.
z2 core is present in PD1. This domain is power gated off in STANDBY/
LPU_STANDBY mode.
Power Domain2 (PD2): It is the biggest domain with most of the modules, many XBAR
masters. z4 core is present in PD2. This domain is power gated off in any of the LPU
modes as well as STANDBY mode.
Powered with External Regulator
If the application is using an external 1.25 V supply, then that 1.25 V supply will
continue to be connected to the PD2 domain unless the customer application takes steps
to remove it. Hence depending on the application configuration there may be leakage
from the PD2 area in STANDBY or LPU modes. This can be avoided by disconnecting
the external supply when the device has entered the low power states, although it must be
re-applied to enable exit from the low power states. For details, see Applications and Low
Power Modes.
Maximum power saving is reached by entering the STANDBY modes. On each mode
change request, the power and mode controllers in the chip i.e. MC_ME, MC_PCU,
LPU_CTL and PMC evaluates the power domain settings in the power domain
configuration registers and initiates a power-down or a power-up sequence for each
individual power domain. The power-up/down sequences are handled by finite state
machines to ensure a smooth and safe transition from one power state to the other.
Low Power Mode Exit
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Chapter 2 Introduction
Exiting STANDBY modes can only be done via a system wakeup event or reset as all
power domains other than PD0 are in the power-down state. Refer the wakeup sources
for the wakeup event triggers details. See the device I/O Signal Description and Input
Multiplexing tables attached to this document as an Excel file. Locate the paperclip
symbol on the left side of the PDF window, and click it. Double-click the Excel file to
open it and select the I/O Signal Description table tab.
NOTE
For interrupt handling during mode transitions, refer to section:
Interrupts handling during mode transitions.
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Modes of Operation
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Chapter 3
Memory Map
3.1 Introduction
This chapter describes the memory and peripheral locations within the specified memory
space. The addresses represent the physical addresses assigned to each region or module.
An access to the reserved locations may produce undesirable results.
3.2 System memory map
The following table shows the system memory map.
Table 3-1. System memory map
Start Address
End Address
Size
Description
0x00000000
0x003FFFFF
4096 KB
Reserved
0x00400000
0x00403FFF
16 KB
UTEST
0x00404000
0x00407FFF
16 KB
BAF
0x00408000
0x0060FFFF
2080 KB
Reserved
0x00610000
0x0062FFFF
128 KB
HSM code
0x00630000
0x00F7FFFF
9536 KB
Reserved
0x00F80000
0x00F87FFF
32 KB
HSM data
0x00F88000
0x00F8BFFF
16 KB
Reserved
0x00F8C000
0x00F8FFFF
16 KB
Small HSM Code Block
0x00F90000
0x00FAFFFF
128 KB
Small and Medium NVM
Blocks
0x00FB0000
0x00FBFFFF
64 KB
Reserved
0x00FC0000
0x00FFFFFF
256 KB
Small & Medium NVM Blocks
0x01000000
0x0127FFFF
2560 KB
Large Flash NVM
0x01280000
0x0157FFFF
3072 KB
Reserved
0x01580000
0x0177FFFF
2048 KB
Reserved
0x01780000
0x3FFFFFFF
1000 MB
Reserved
Table continues on the next page...
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NVM memory map
Table 3-1. System memory map (continued)
Start Address
End Address
Size
Description
0x40000000
0x4007FFFF
512 KB
System RAM
0x40080000
0x400BFFFF
256 KB
Reserved
0x400C0000
0xEFFFFFFF
2815 MB
Reserved
0xF0000000
0xFFFFFFFF
256 MB
Peripheral Address Space
3.3 NVM memory map
Table 3-2. NVM memory map
Start Address
End Address
Allocated Size
(KB/MB)
0x00000000
0x003FFFFF
4096 KB
Complete Flash
Block Structure
RWW Partition
Block Size (KB)
Reserved
UTEST NVM Block
0x00400000
0x00403FFF
16 KB
UTEST
0
16
BAF
1
16
BAF Block
0x00404000
0x00407FFF
16 KB
0x00408000
0x0060FFFF
2080 KB
Reserved
HSM Code
0x00610000
0x0061FFFF
64 KB
HSM code block 2
0
64
0x00620000
0x0062FFFF
64 KB
HSM code block 3
1
64
0x00630000
0x00F7FFFF
9536 KB
Reserved
HSM Data
0x00F80000
0x00F83FFF
16 KB
HSM data block0
4
16
0x00F84000
0x00F87FFF
16 KB
HSM data block1
5
16
0x00F88000
0x00F8BFFF
16 KB
Reserved
Small HSM Code Block
0x00F8C000
0x00F8FFFF
16 KB
16KB Code Flash
block
0
16
Small and Medium Flash Blocks
0x00F90000
0x00F93FFF
16 KB
16KB Code Flash
block
2
16
0x00F94000
0x00F97FFF
16 KB
16KB Code Flash
block
2
16
0x00F98000
0x00F9BFFF
16 KB
16KB Code Flash
block
2
16
0x00F9C000
0x00F9FFFF
16 KB
16KB Code Flash
block
2
16
0x00FA0000
0x00FA3FFF
16KB
16KB Code Flash
block
3
16
Table continues on the next page...
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Chapter 3 Memory Map
Table 3-2. NVM memory map (continued)
Start Address
End Address
Allocated Size
(KB/MB)
Complete Flash
Block Structure
RWW Partition
Block Size (KB)
0x00FA4000
0x00FA7FFF
16 KB
16KB Code Flash
block
3
16
0x00FA8000
0x00FABFFF
16 KB
16KB Code Flash
block
3
16
0x00FAC000
0x00FAFFFF
16 KB
16KB Code Flash
block
3
16
0x00FB0000
0x00FB7FFF
32 KB
Reserved
0x00FB8000
0x00FBFFFF
32 KB
Reserved
0x00FC0000
0x00FC7FFF
32 KB
32KB Code Flash
block
0
32
0x00FC8000
0x00FCFFFF
32 KB
32KB Code Flash
block
0
32
0x00FD0000
0x00FD7FFF
32 KB
32KB Code Flash
block
1
32
0x00FD8000
0x00FDFFFF
32 KB
32KB Code Flash
block
1
32
0x00FE0000
0x00FEFFFF
64 KB
64KB Code Flash
block
0
64
0x00FF0000
0x00FFFFFF
64 KB
64KB Code Flash
block
1
64
0x01000000
0x0103FFFF
256 KB
256KB Code Flash
block0
6
256
0x01040000
0x0107FFFF
256 KB
256KB Code Flash
block1
6
256
0x01080000
0x010BFFFF
256 KB
256KB Code Flash
block2
6
256
0x010C0000
0x010FFFFF
256 KB
256KB Code Flash
block3
6
256
0x01100000
0x0113FFFF
256 KB
256KB Code Flash
block4
6
256
0x01140000
0x0117FFFF
256 KB
256KB Code Flash
block5
7
256
0x01180000
0x011BFFFF
256 KB
256KB Code Flash
block6
7
256
0x011C0000
0x011FFFFF
256 KB
256KB Code Flash
block7
7
256
0x01200000
0x0123FFFF
256 KB
256KB Code Flash
block8
7
256
0x01240000
0x0127FFFF
256 KB
256KB Code Flash
block9
7
256
0x01280000
0x012BFFFF
256 KB
Reserved
0x012C0000
0x012FFFFF
256 KB
Reserved
0x01300000
0x0133FFFF
256 KB
Reserved
Large Flash Blocks
Table continues on the next page...
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UTEST Memory Map
Table 3-2. NVM memory map (continued)
Start Address
End Address
Allocated Size
(KB/MB)
Complete Flash
Block Structure
RWW Partition
0x01340000
0x0137FFFF
256 KB
Reserved
0x01380000
0x013BFFFF
256 KB
Reserved
0x013C0000
0x013FFFFF
256 KB
Reserved
0x01400000
0x0143FFFF
256 KB
Reserved
0x01440000
0x0147FFFF
256 KB
Reserved
0x01480000
0x014BFFFF
256 KB
Reserved
0x014C0000
0x014FFFFF
256 KB
Reserved
0x01500000
0x0153FFFF
256 KB
Reserved
0x01540000
0x0157FFFF
256 KB
Reserved
0x01580000
0x0179FFFF
2176 KB
Reserved
Block Size (KB)
3.4 UTEST Memory Map
Table 3-3. UTEST Memory Map
Start Address
End Address
Allocated Size [bytes]
Decription
UTEST Flash
0x00400000
0x00400001
2
Reserved
0x00400002
0x00400003
2
Reserved
0x00400004
0x00400005
2
Reserved
0x00400006
0x00400007
2
Reserved
0x00400008
0x0040000B
4
Reserved
0x0040000C
0x0040000F
4
Test Mode Disable Seal
0x00400010
0x0040001F
16
Test Mode Disable Block
Select Group A
0x00400020
0x0040002F
16
Factory Erase diary Location
0x00400030
0x0040003F
16
Test Mode Disable Block
Select Group B
0x00400040
0x0040005F
32
Customer Single Bit
Correction Area
0x00400060
0x0040007F
32
Customer Double Bit
Detection Area
0x00400080
0x0040009F
32
Customer EDC after ECC
Area
0x004000A0
0x004000BF
32
UID
0x004000C0
0x004000C3
4
Soft DCF Record Start
Address
0x004000C4
0x004000C7
4
Reserved
0x004000C8
0x004000FF
56
Reserved
Table continues on the next page...
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Chapter 3 Memory Map
Table 3-3. UTEST Memory Map (continued)
Start Address
End Address
Allocated Size [bytes]
Decription
0x00400100
0x00400103
4
Test Mode Overide Passcode
0x00400104
0x0040011F
28
Test mode enable password
0x00400120
0x0040013F
32
JTAG Password
0x00400140
0x0040015F
32
PASS Password Group 0
0x00400160
0x0040017F
32
PASS Password Group 1
0x00400180
0x0040019F
32
PASS Password Group 2
0x004001A0
0x004001BF
32
PASS Password Group 3
0x004001C0
0x004001DF
32
Reserved
0x004001E0
0x004001FF
32
Reserved
0x00400200
0x0040020F
16
Lifecycle Slot 0 - MCU_PROD
0x00400210
0x0040021F
16
Lifecycle Slot 1 - CUST_DEL
0x00400220
0x0040022F
16
Lifecycle Slot 2 - OEM_PROD
0x00400230
0x0040023F
16
Lifecycle Slot 3 - IN_FIELD
0x00400240
0x0040024F
16
Lifecycle Slot 4 - FA
0x00400250
0x004002FF
176
Reserved
0x00400300
0x00400307
8
DCF Start Record
0x00400308 1, 2
0x00400347
64
Reserved
0x00400348
0x00400FFF
3256
DCF Records
0x00401000
0x00403FFF
12288
Reserved for customer OTP
data
1. When device is in CUST_DEL (or later) life cycle and prefetching is enabled in the platform flash controller
(PFLASH_C55FM), it reads of the HSM 'ROM' key locations (0x0400308 - 0x0400347) and return dummy DCF records.
However, accesses to these locations may cause result in anomalous operation. Reading the HSM 'ROM' key locations
can result in a false ECC event, specifically either a false single-bit correction or a false multi-bit error detection. Reading
the HSM 'ROM' key locations can also interfere with an unrelated, but coincident, loading of the PFLASH_C55FM prefetch
buffers. As a result a subsequent request to flash, may result in a false ECC event, specifically either a false single-bit
correction or a false multi-bit error detection.
2. Program MPU to prevent accesses to 0x0400308 - 0x0400347. Avoid accessing the HSM ROM key locations in the flash
UTEST region (0x0400308 - 0x0400347). Prior to accessing this region; disable flash buffer prefetches.
3.5 RAM memory map
Table 3-4. RAM memory map
Start Address
End Address
Allocated Size [KB]
Description
0x40000000
0x40001FFF
8 (STANDBY)
SRAM 0
0x40002000
0x4000FFFF
56
SRAM 1
0x40010000
0x4001FFFF
64
SRAM 2
0x40020000
0x4002FFFF
64
SRAM 3
0x40030000
0x4003FFFF
64
SRAM 4
0x40040000
0x4004FFFF
64
SRAM 5
Table continues on the next page...
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Peripheral Bridges A and B memory maps
Table 3-4. RAM memory map (continued)
Start Address
End Address
Allocated Size [KB]
Description
0x40050000
0x4005FFFF
64
SRAM 6
0x40060000
0x4006FFFF
64
SRAM 7
0x40070000
0x4007FFFF
64
SRAM 8
0x40080000
0x400BFFFF
Reserved
-
3.6 Peripheral Bridges A and B memory maps
3.6.1 Peripheral Bridge A memory map
Table 3-5. Peripheral Bridge A memory map
Start Address
End Address
Size [KB]
ME_ PCTL
Region
Peripheral Bridge
slot number
On Platform Bridge A
0xFC000000
0xFC003FFF
16 KB
PBRIDGE_A
PACR0
0xFC004000
0xFC007FFF
16 KB
XBAR_0
PACR1
0xFC008000
0xFC00BFFF
16 KB
Reserved
0xFC00C000
0xFC00FFFF
16 KB
Reserved
0xFC010000
0xFC013FFF
16 KB
SMPU_0
0xFC014000
0xFC017FFF
16 KB
Reserved
PACR4
0xFC018000
0xFC01FFFF
16 KB
Reserved
0xFC01C000
0xFC01FFFF
16 KB
Reserved
0xFC020000
0xFC023FFF
16 KB
PRAM_0
PACR8
0xFC024000
0xFC027FFF
16 KB
PRAM_1
PACR9
0xFC028000
0xFC02BFFF
16 KB
PCM
PACR10
0xFC02C000
0xFC02FFFF
16 KB
Reserved
0xFC030000
0xFC033FFF
16 KB
PFLASH
0xFC034000
0xFC037FFF
16 KB
Reserved
PACR12
0xFC038000
0xFC03BFFF
16 KB
0xFC03C000
0xFC03FFFF
16 KB
SEMA4
PACR15
0xFC040000
0xFC043FFF
16 KB
INTC
PACR16
0xFC044000
0xFC047FFF
16 KB
Reserved
0xFC048000
0xFC04BFFF
16 KB
Reserved
0xFC04C000
0xFC04FFFF
16 KB
Reserved
0xFC050000
0xFC053FFF
16 KB
SWT_0
PACR20
0xFC054000
0xFC057FFF
16 KB
SWT_1
PACR21
0xFC058000
0xFC05BFFF
16 KB
Reserved
Table continues on the next page...
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Chapter 3 Memory Map
Table 3-5. Peripheral Bridge A memory map (continued)
Start Address
End Address
Size [KB]
ME_ PCTL
Region
0xFC05C000
0xFC05CFFFF
16 KB
Reserved
0xFC060000
0xFC063FFF
16 KB
Reserved
0xFC064000
0xFC067FFF
16 KB
Reserved
0xFC068000
0xFC06BFFF
16 KB
STM_0
PACR26
0xFC06C000
0xFC06FFFF
16 KB
STM_1
PACR27
0xFC070000
0xFC09BFFF
176 KB
Reserved
0xFC0A0000
0xFC0A3FFF
16 KB
eDMA
0xFC0A4000
0xFCFFFFFF
15 MB
Reserved
Peripheral Bridge
slot number
PACR40
Off Platform Bridge A
0xFD000000
0xFFC0FFFF
Reserved
0xFFC10000
0xFFC13FFF
16 KB
0xFFC14000
0xFFC17FFF
16 KB
Reserved
0xFFC18000
0xFFC1BFFF
16 KB
Reserved
0xFFC1C000
0xFFC1FFFF
16 KB
Reserved
0xFFC20000
0xFFC23FFF
16 KB
GLITCH_FILTER_1
OPACR247
0xFFC24000
0xFFC27FFF
16 KB
GLITCH_FILTER_0
OPACR246
0xFFC28000
0xFFC2BFFF
16 KB
Reserved
0xFFC2C000
0xFFC2FFFF
16 KB
Reserved
0xFFC30000
0xFFC33FFF
16 KB
HFIF_1
OPACR243
0xFFC34000
0xFFC37FFF
16 KB
HFIF_0
OPACR242
0xFFC38000
0xFFC3BFFF
16 KB
eMIOS_0
OPACR241
0xFFC3C000
0xFFC3FFFF
16 KB
Reserved
0xFFC40000
0xFFC8FFFF
320 KB
Reserved
0xFFC90000
0xFFC93FFF
16 KB
Reserved
0xFFC94000
0xFFC97FFF
16 KB
Reserved
0xFFC98000
0xFFC9BFFF
16 KB
Reserved
0xFFC9C000
0xFFC9FFFF
16 KB
Reserved
0xFFCA0000
0xFFCA3FFF
16 KB
Reserved
0xFFCA4000
0xFFCA7FFF
16 KB
Reserved
0xFFCA8000
0xFFCB3FFF
48 KB
0xFFCB4000
0xFFCB7FFF
16 KB
10
SAI_0
OPACR210
0xFFCB8000
0xFFCBBFFF
16 KB
12
SAI_2
OPACR209
0xFFCBC000
0xFFCC3FFF
32 KB
0xFFCC4000
0xFFCC7FFF
16 KB
0xFFCC8000
0xFFCCBFFF
16 KB
Reserved
0xFFCCC000
0xFFCCFFFF
16 KB
Reserved
0xFFCD0000
0xFFCD3FFF
16 KB
Reserved
0xFFCD4000
0xFFCDBFFF
32 KB
0xFFCDC000
0xFFCDFFFF
16 KB
0
1
BCTU
OPACR251
Reserved
Reserved
15
ENET 0
OPACR206
Reserved
20
ACMP_0
OPACR200
Table continues on the next page...
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Peripheral Bridges A and B memory maps
Table 3-5. Peripheral Bridge A memory map (continued)
Start Address
End Address
Size [KB]
ME_ PCTL
Region
Peripheral Bridge
slot number
0xFFCE0000
0xFFCE3FFF
16 KB
21
ACMP_1
OPACR199
0xFFCE4000
0xFFCE7FFF
16 KB
22
ACMP_2
OPACR198
0xFFCE8000
0xFFDFFFFF
1 MB
0xFFE00000
0xFFE03FFF
16 KB
0xFFE04000
0xFFE4FFFF
304 KB
0xFFE50000
0xFFE53FFF
16 KB
0xFFE54000
0xFFE67FFF
80 KB
0xFFE68000
0xFFE6BFFF
16 KB
Reserved
24
ADC_0
OPACR127
Reserved
28
FlexRay
OPACR107
Reserved
30
I2C_0
OPACR101
OPACR100
0xFFE6C000
0xFFE6FFFF
16 KB
32
I2C_2
0xFFE70000
0xFFE73FFF
16 KB
40
DSPI_0
OPACR99
0xFFE74000
0xFFE77FFF
16 KB
42
DSPI_2
OPACR98
0xFFE78000
0xFFE8BFFF
80 KB
0xFFE8C000
0xFFE8FFFF
16 KB
50
LIN_0
OPACR92
0xFFE90000
0xFFE93FFF
16 KB
52
LIN_2
OPACR91
0xFFE94000
0xFFE97FFF
16 KB
54
LIN_4
OPACR90
0xFFE98000
0xFFE9BFFF
16 KB
56
LIN_6
OPACR89
0xFFE9C000
0xFFE9FFFF
16 KB
58
LIN_8
OPACR88
0xFFEA0000
0xFFEA3FFF
16 KB
60
LIN_10
OPACR87
0xFFEA4000
0xFFEA7FFF
16 KB
62
LIN_12
OPACR86
0xFFEA8000
0xFFEABFFF
16 KB
64
LIN_14
OPACR85
0xFFEAC000
0xFFEBFFFF
80 KB
0xFFEC0000
0xFFEC3FFF
16 KB
70
FLEXCAN_0
OPACR79
0xFFEC4000
0xFFEC7FFF
16 KB
72
FLEXCAN_2
OPACR78
0xFFEC8000
0xFFECBFFF
16 KB
74
FLEXCAN_4
OPACR77
0xFFECC000
0xFFECFFFF
16 KB
76
FLEXCAN_6
OPACR76
0xFFED0000
0xFFF2BFFF
368 KB
Reserved
0xFFF2C000
0xFFF2FFFF
16 KB
HSM_SWT
OPACR52
0xFFF30000
0xFFF33FFF
16 KB
HSM
OPACR51
0xFFF34000
0xFFF37FFF
16 KB
TDM
OPACR50
0xFFF38000
0xFFF3BFFF
16 KB
Reserved
0xFFF3C000
0xFFF3FFFF
16 KB
0xFFF40000
0xFFF43FFF
16 KB
Reserved
0xFFF44000
0xFFF47FFF
16 KB
STCU
0xFFF48000
0xFFF4BFFF
16 KB
Reserved
0xFFF4C000
0xFFF4FFFF
16 KB
0xFFF50000
0xFFF53FFF
16 KB
0xFFF54000
0xFFF57FFF
16 KB
Reserved
0xFFF58000
0xFFF5BFFF
16 KB
Reserved
Reserved
Reserved
82
JDC (JTAG Data
Communication)
OPACR48
OPACR46
Reserved
83
MEMU_0
OPACR43
Table continues on the next page...
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Chapter 3 Memory Map
Table 3-5. Peripheral Bridge A memory map (continued)
Start Address
End Address
Size [KB]
ME_ PCTL
Region
0xFFF5C000
0xFFF5FFFF
16 KB
Reserved
0xFFF60000
0xFFF63FFF
16 KB
Reserved
0xFFF64000
0xFFF67FFF
16 KB
0xFFF68000
0xFFF6BFFF
16 KB
0xFFF6C000
0xFFF6FFFF
16 KB
0xFFF70000
0xFFF73FFF
16 KB
Reserved
0xFFF74000
0xFFF77FFF
16 KB
Reserved
0xFFF78000
0xFFF7BFFF
16 KB
Reserved
0xFFF7C000
0xFFF7FFFF
16 KB
Reserved
0xFFF80000
0xFFF83FFF
16 KB
Reserved
0xFFF84000
0xFFF87FFF
16 KB
0xFFF88000
0xFFF8BFFF
16 KB
Reserved
0xFFF8C000
0xFFF8FFFF
16 KB
Reserved
0xFFF90000
0xFFF93FFF
16 KB
Reserved
0xFFF94000
0xFFF97FFF
16 KB
GPR (General
purpose registers)
OPACR26
0xFFF98000
0xFFF9BFFF
16 KB
WKPU
OPACR25
0xFFF9C000
0xFFF9FFFF
16 KB
LPU_CTL
OPACR24
0xFFFA0000
0xFFFA3FFF
16 KB
MC_PCU
OPACR23
0xFFFA4000
0xFFFA7FFF
16 KB
Reserved
84
CRC
Peripheral Bridge
slot number
OPACR38
Reserved
90
91
93
DMAMUX
PIT_RTI
0xFFFA8000
0xFFFABFFF
16 KB
MC_RGM
0xFFFAC000
0xFFFAFFFF
16 KB
Reserved
0xFFFB0000
0xFFFB3FFF
16 KB
MC_CGM
0xFFFB4000
0xFFFB7FFF
16 KB
Reserved
0xFFFB8000
0xFFFBBFFF
16 KB
MC_ME
0xFFFBC000
0xFFFBFFFF
16 KB
Reserved
0xFFFC0000
0xFFFC3FFF
16 KB
SIUL
0xFFFC4000
0xFFFC7FFF
16 KB
Reserved
OPACR36
OPACR30
OPACR21
OPACR19
OPACR17
OPACR15
0xFFFC8000
0xFFFCBFFF
16 KB
0xFFFCC000
0xFFFCFFFF
16 KB
96
Reserved
SPI_0
OPACR12
0xFFFD0000
0xFFFD3FFF
16 KB
98
SPI_2
OPACR11
0xFFFD4000
0xFFFD7FFF
16 KB
Reserved
0xFFFD8000
0xFFFDBFFF
16 KB
Reserved
0xFFFDC000
0xFFFDFFFF
16 KB
Reserved
0xFFFE0000
0xFFFE3FFF
16 KB
C55FMC (Flash
main control)
OPACR7
0xFFFE4000
0xFFFE7FFF
16 KB
ALT_C55FMC1
(Flash alternate
control)
OPACR6
0xFFFE8000
0xFFFEBFFF
16 KB
Reserved
Table continues on the next page...
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Peripheral Bridges A and B memory maps
Table 3-5. Peripheral Bridge A memory map (continued)
Start Address
End Address
Size [KB]
ME_ PCTL
Region
Peripheral Bridge
slot number
0xFFFEC000
0xFFFEFFFF
16 KB
105
MEMU_1
OPACR4
0xFFFF0000
0xFFFF3FFF
16 KB
102
RTC-API
OPACR3
0xFFFF4000
0xFFFF7FFF
16 KB
PASS
OPACR2
0xFFFF8000
0xFFFFBFFF
16 KB
SSCM
OPACR1
0xFFFFC000
0xFFFFFFFF
16 KB
Reserved
1. For ALT_C55FMC please refer the "MPC5746C Microcontroller Security Reference Manual"
3.6.2 Peripheral Bridge B memory map
Table 3-6. Peripheral Bridge B memory map
Start Address
End Address
Size [KB]
ME_ PCTL
Region
Peripheral Bridge
slot number
.
PBRIDGE_B
PACR0
On Platform Bridge B
0xF8000000
0xF8003FFF
16
0xF8004000
0xF8FFFFFF
16 MB
0xF9000000
0xFBC17FFF
44 MB
Reserved
0xFBC18000
0xFBC1BFFF
16 KB
Glitch_Filter_3
OPACR249
0xFBC1C000
0xFBC1FFFF
16 KB
Glitch_Filter_2
OPACR248
0xFBC20000
0xFBC23FFF
16 KB
Reserved
0xFBC24000
0xFBC27FFF
16 KB
Reserved
0xFBC28000
0xFBC2BFFF
16 KB
HFIF_3
OPACR245
0xFBC2C000
0xFBC2FFFF
16 KB
HFIF_2
OPACR244
0xFBC30000
0xFBC33FFF
16 KB
Reserved
0xFBC34000
0xFBC37FFF
16 KB
Reserved
0xFBC38000
0xFBCB3FFF
16 KB
0xFBC3C000
0xFBCB3FFF
16 KB
0xFBCB4000
0xFBCB7FFF
16 KB
0xFBCB8000
0xFBDFFFFF
1312 KB
0xFBE00000
0xFBE03FFF
16 KB
0xFBE04000
0xFBE67FFF
400 KB
0xFBE68000
0xFBE6BFFF
16 KB
31
I2C_1
OPACR101
0xFBE6C000
0xFBE6FFFF
16 KB
33
I2C_3
OPACR100
0xFBE70000
0xFBE73FFF
16 KB
41
DSPI_1
OPACR99
0xFBE74000
0xFBE77FFF
16 KB
43
DSPI_3
OPACR98
0xFBE78000
0xFBE8BFFF
80 KB
0xFBE8C000
0xFBE8FFFF
16 KB
Reserved
Off Platform Bridge B
2
eMIOS_1
OPACR241
Reserved
11
SAI_1
OPACR210
Reserved
25
ADC_1
OPACR127
Reserved
Reserved
51
LIN_1
OPACR92
Table continues on the next page...
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Chapter 3 Memory Map
Table 3-6. Peripheral Bridge B memory map (continued)
Start Address
End Address
Size [KB]
ME_ PCTL
Region
Peripheral Bridge
slot number
0xFBE90000
0xFBE93FFF
16 KB
53
LIN_3
OPACR91
0xFBE94000
0xFBE97FFF
16 KB
55
LIN_5
OPACR90
0xFBE98000
0xFBE9BFFF
16 KB
57
LIN_7
OPACR89
0xFBE9C000
0xFBE9FFFF
16 KB
59
LIN_9
OPACR88
0xFBEA0000
0xFBEA3FFF
16 KB
61
LIN_11
OPACR87
0xFBEA4000
0xFBEA7FFF
16 KB
63
LIN_13
OPACR86
65
LIN_15
OPACR85
0xFBEA8000
0xFBEABFFF
16 KB
0xFBEAC000
0xFBEAFFFF
16 KB
Reserved
0xFBEB0000
0xFBEBFFFF
64 KB
Reserved
0xFBEC0000
0xFBEC3FFF
16 KB
71
FLEXCAN_1
OPACR79
0xFBEC4000
0xFBEC7FFF
16 KB
73
FLEXCAN_3
OPACR78
0xFBEC8000
0xFBECBFFF
16 KB
75
FLEXCAN_5
OPACR77
0xFBECC000
0xFBECFFFF
16 KB
77
FLEXCAN_7
OPACR76
0xFBED0000
0xFBF57FFF
544 KB
Reserved
0xFBF58000
0xFBF5BFFF
16 KB
FCCU
0xFBF5C000
0xFBF9BFFF
256 KB
Reserved
OPACR41
0xFBF9C000
0xFBF9FFFF
16 KB
97
SPI_1
OPACR24
0xFBFA0000
0xFBFA3FFF
16 KB
99
SPI_3
OPACR23
0xFBFA4000
0xFBFA7FFF
16 KB
Reserved
0xFBFA8000
0xFBFAFFFF
32 KB
Reserved
0xFBFB0000
0xFBFB3FFF
16 KB
Reserved
0xFBFB4000
0xFBFFFFFF
304 KB
Reserved
3.7 MC_CGM mapped peripherals memory map
Table 3-7. MC_CGM mapped peripherals memory map
Start Address
End Address
Size [Bytes]
Mapped Peripheral
0xFFFB_0000
0xFFFB_003F
64
FIRC
0xFFFB_0040
0xFFFB_007F
64
FXOSC
0xFFFB_0080
0xFFFB_00BF
64
PLLDIG
0xFFFB_00C0
0xFFFB_00FF
64
SIRC
0xFFFB_0100
0xFFFB_013F
64
SXOSC
0xFFFB_0140
0xFFFB_017F
64
CMU
0xFFFB_0180
0xFFFB_6BC0
1084
CGM
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PCU mapped peripherals memory map
3.8 PCU mapped peripherals memory map
Table 3-8. PCU mapped peripherals memory map
Start Address
End Address
Size [Bytes]
Mapped Peripheral
0xFFFA_0400
0xFFFA_07FF
1024
PMCDIG
3.9 DMAMUX mapped peripherals memory map
Table 3-9. DMAMUX mapped peripherals memory map
Start Address
End Address
Size [Bytes]
Mapped Peripheral
0xFFF6_C000
0xFFF6_C1FF
512
DMAMUX_0
0xFFF6_C200
0xFFF6_C3FF
512
DMAMUX_1
0xFFF6_C400
0xFFF6_FFF
15 KB
Reserved
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Chapter 4
Signal Description
4.1 Generic pins/balls
The I/O Signal Description Table contains information on generic pins/balls. See the
device I/O Signal Description and Input Multiplexing tables attached to this document as
an Excel file. Locate the paperclip symbol on the left side of the PDF window, and click
it. Double-click the Excel file to open it and select the I/O Signal Description table tab.
NOTE
On 176LQFP-EP package, expose pad must be connected to
VSS_LV on board.
4.1.1 MSCR assignments
The I/O Signal Description table provides the port pin, SIUL Multiplexed Signal
Configuration Register (MSCR) number, MSCR Source Signal Select (SSS) function,
module, signal description, direction, pad type, and package pin/ball numbers for each
I/O pin on the device.
The Implemented SIUL2 Multiplexed Single Configuration Register details is provided
in the I/O Signal Description Table attached as excel.
NOTE
Implemented SIUL2 Multiplexed Single Configuration Register
are from SIUL2_MSCR0 to SIUL2_MSCR263 and
SIUL2_IMCR0 to SIUL2_IMCR511. Please note that MSCR
513 in this column corresponds to IMCR 0 and so on.
NOTE
For the Precision channel Analog inputs, SIUL2_MSCRn[PUS]
must be configured to 0 before entering STANDBY.
Example:
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PAD keeping feature in LPU/STANDBY mode
If user wants to configure CAN0RX and CAN0TX, then the following configuration can
be used in SIUL2 registers:
SIUL2.MSCR[16].R = 0x03000001; /* PB[0] -&gt OBE = 1, ODE = 1 and MSCR16_SSS = 1 */
SIUL2.MSCR[17].R = 0x00080000; /* PB[1] -&gt IBE = 1 */
SIUL2.IMCR[188].R = 0x00080002; /* PB[1] -&gt MSCR17_SSS = 2, notice that
“IO_Signal_Description_and_Input_multiplexing_tables.xls” shows 700 for the MSCR/IMCR see
note above, thus 188 must be used to properly configure the pin signal connected to it */
MSCR bit fields corresponds to pin/pad basis, these are independent of muxing
implemented on that specific pin/pad. As an example, PAD18/PB[2] has SRE, ODE,
SMC, IBE, HYS, PUS, PUE, SSS and OBE are implemented with the reset value
0000_0000.
In the “IO_Signal_Description_and_Input_multiplexing_tables.xls" spreadsheet, in "IO
Signal Table" worksheet, the MSCR register bits shows ‘0’, ‘1’, and ‘-’ for state of all
bits associated with different ports. ‘0’ or ’1’ represents the reset state and ‘-’ represents
the bit is not supported on the respective port.
NOTE
IF HSM DO functionality is used on GPIO[28], GPIO[60] pads
or GPIO[134], GPIO[135] pads using HSM_IO configurations
for security, then all four GPIOs would get dedicated to HSM.
4.2 PAD keeping feature in LPU/STANDBY mode
The device is capable to retain the output value of some selected pads when device is
power gated i.e. in LPU or STANDBY mode. These pads reside in always alive power
domain(PD0).
To enable this feature, set PMCDIG_RDCR[PAD_KEEP_EN] to '1'. The PAD's output
values are retained until software writes a '0' to this bit on exit from LPU or STANDBY
mode . If the bit is not set, latched PAD values are automatically cleared on LPU or
STANDBY exit and the PADS go to Hi-z
1. PAD STATE when Pad Keeping is enabled:
Magic_carpet mode
pad state
Standby
RUN
DRUN
- as per application -
t
2. PAD STATE when Pad Keeping is disabled:
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Chapter 4 Signal Description
Magic_carpet mode
RUN
Standby
DRUN
High Z
- as per application -
pad state
t
To further reduce power in LPU or standby mode and achieve following:
Magic_carpet mode
pad state
RUN
Standby
DRUN
High Z
- as per application -
t
SIUL config
Please use following configuration:
1. configure PADS to GPIO if they are not already GPIO
2. configure IBE, OBE and PUE of PADS to ‘0’
3. enter desired low power mode
Table 4-1 lists the pads which support PAD Keeping feature. However, the pads in the
following two tables combine to form the full list of pads available in LPU and
STANDBY modes.
Table 4-1. PADS alive in LPU mode with pad keeping feature
Function
I/O Power Segment
GPIO[12]
STBY_LPU
GPIO[13]
STBY_LPU
GPIO[14]
STBY_LPU
GPIO[16]
STBY_LPU
GPIO[27]
STBY_LPU
GPIO[28]
STBY_LPU
GPIO[32]
STBY_LPU
GPIO[33]
STBY_LPU
GPIO[38]
STBY_LPU
GPIO[42]
STBY_LPU
GPIO[60]
STBY_LPU
GPIO[61]
STBY_LPU
GPIO[80]
STBY_LPU
GPIO[81]
STBY_LPU
GPIO[82]
STBY_LPU
GPIO[83]
STBY_LPU
Table continues on the next page...
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PAD keeping feature in LPU/STANDBY mode
Table 4-1. PADS alive in LPU mode with pad keeping feature (continued)
Function
I/O Power Segment
GPIO[84]
STBY_LPU
GPIO[85]
STBY_LPU
GPIO[86]
STBY_LPU
GPIO[87]
STBY_LPU
GPIO[88]
STBY_LPU
GPIO[90]
STBY_LPU
GPIO[92]
STBY_LPU
GPIO[102]
STBY_LPU
GPIO[104]
STBY_LPU
GPIO[121]
STBY_LPU
GPIO[122]
STBY_LPU
GPIO[137]
STBY_LPU
GPIO[138]
STBY_LPU
GPIO[142]
STBY_LPU
GPIO[143]
STBY_LPU
GPIO[144]
STBY_LPU
GPIO[145]
STBY_LPU
GPIO[146]
STBY_LPU
GPIO[147]
STBY_LPU
GPIO[149]
STBY_LPU
GPIO[150]
STBY_LPU
GPIO[151]
STBY_LPU
GPIO[152]
STBY_LPU
GPIO[153]
STBY_LPU
GPIO[154]
STBY_LPU
GPIO[155]
STBY_LPU
GPIO[156]
STBY_LPU
GPIO[158]
STBY_LPU
GPIO[159]
STBY_LPU
GPIO[160]
STBY_LPU
GPIO[161]
STBY_LPU
GPIO[162]
STBY_LPU
GPIO[163]
STBY_LPU
GPIO[164]
STBY_LPU
GPIO[165]
STBY_LPU
GPIO[166]
STBY_LPU
GPIO[167]
STBY_LPU
GPIO[168]
STBY_LPU
GPIO[197]
STBY_LPU
Table continues on the next page...
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Chapter 4 Signal Description
Table 4-1. PADS alive in LPU mode with pad keeping feature (continued)
Function
I/O Power Segment
GPIO[198]
STBY_LPU
GPIO[205]
STBY_LPU
GPIO[206]
STBY_LPU
NOTE
For pads 42 and 102, only if source signal select is configured
for CMP0_O and CLKOUT1 respectively via SIUL2_MSCR
registers, the analog comparator 0 CMP0_O and CLKOUT1
clock would be exposed during standby. If expose during
standby is enabled for CMP0_O or CLKOUT1 on pad 42 and
102 respectively, then padkeeping on these pads would be
disabled.
Table 4-2. PADS used for WKPU
Function
I/O power segment
GPIO[0]
LPU_WK
GPIO[1]
LPU_WK
GPIO[2]
LPU_WK
GPIO[4]
LPU_WK
GPIO[15]
LPU_WK
GPIO[17]
LPU_WK
GPIO[19]
LPU_WK
GPI[24]
LPU_WK
GPI[25]
LPU_WK
GPIO[26]
LPU_WK
GPIO[39]
LPU_WK
GPIO[41]
LPU_WK
GPIO[43]
LPU_WK
GPI[48]
LPU_WK
GPI[49]
LPU_WK
GPIO[64]
LPU_WK
GPIO[67]
LPU_WK
GPIO[69]
LPU_WK
GPIO[73]
LPU_WK
GPIO[75]
LPU_WK
GPIO[89]
LPU_WK
GPIO[91]
LPU_WK
GPIO[93]
LPU_WK
Table continues on the next page...
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PAD keeping feature in LPU/STANDBY mode
Table 4-2. PADS used for WKPU (continued)
Function
I/O power segment
GPIO[99]
LPU_WK
GPIO[101]
LPU_WK
GPIO[103]
LPU_WK
GPIO[105]
LPU_WK
GPIO[129]
LPU_WK
GPIO[131]
LPU_WK
GPIO[157]
LPU_WK
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Chapter 5
Security Overview
5.1 Introduction
All MPC574xx family devices have a comprehensive set of customer-configurable
security features designed to protect code and data from unauthorized access. Some
security features are available in all device configurations. Other, more advanced security
features are not available in all device configurations. These more advanced features
require more than simply being turned on or off. They require significant involvement for
implementation; consequently, they provide an important opportunity to define the
security level of the device.
5.2 Basic security
All MPC574xx devices have the following basic set of security features.
• Device censorship based on life cycle model. Access to device code and data
becomes progressively more restricted as the device matures through a defined set of
life cycle steps.
• Memory security features
• NVM censorship support, password protection, and one-time-programmable
(OTP) flash memory areas, Flash erase counter and tamper detection.
• Unique ID for each device. Each MPC574xx device has a unique identification
number stored in an OTP flash memory area. This unique ID can be read by any of
the cores on the device.
• Basic debugger restrictions (on/off via censorship mode)
5.3 Advanced security
Depending on the device configuration, the following features are available:.
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Detailed security information
• Customer programmable Hardware Security Module (HSM). The HSM is a
dedicated security subsystem that includes a processor core, dedicated SRAM, an
encryption module, and exclusive access to secure areas of device flash memory. The
HSM runs code independently from the main device processor cores and can be used
to implement advanced security and monitoring functions.
• Secure debugger interface
• Boot modes
• Trusted/secure boot support.
• Handshake with Boot Assist Flash (BAF) supported.
• Monitoring of operating conditions
• Basic debugger restrictions (on/off via censorship mode)
5.4 Detailed security information
Details of most of the device security features will be published in a separate document,
the MPC574xx Microcontroller Security Reference Manual. Please contact your NXP
sales representative for details.
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Chapter 6
Platform Overview
6.1 Introduction
All MPC574xx family devices supports multiple cores with Power PC Architecture. The
MPC5746C Platform overview top level block diagram is shown below.
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Performance Enhancement
ENET0
RX
Z4
Z2
DMA
HSM
ENET0
TX
Mini Crossbar
FLEXRAY
PRAM0
PRAM1
AXBS
iAHB GASKET + E2E ECC
PFLASH CTRL
DMC
SLAVES
PBRIDGE A
PBRIDGE B
MASTERS
Figure 6-1. Platform Overview
6.2 Performance Enhancement
NOTE
If the system frequency is greater than 80 MHz, then the
PRAMCx_PRCR1[FT_DIS] field should be set to 1"
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Chapter 6 Platform Overview
6.3 User/Privilege Access
The non-core masters like ENET, Flexray etc can access the System RAM in either user
or privileged mode. The kind of access per master is summarized in the below table.
Table 6-1. User/Privilege Access
Masters
Access
DMA
Master Configurable
HSM
Master Configurable
ENET 0
Master Configurable
FlexRay
User mode only
NOTE
Bus error response will be generated when read or write access
violation occurs for these Masters.
NOTE
Burst accesses via HSM IAHB gasket are not allowed.
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User/Privilege Access
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Chapter 7
Power Management Overview
7.1 Introduction
The MPC5746C microcontroller's PMC generates, monitors and controls the power
supply and related resets in the device. This chapter describes the analog PMC and its
integration within the device, specifically detailing how the power supply to various
modules is generated. It also explains different supply configurations for the MPC5746C.
The power management infrastructure comprises the following modules:
• Mode Entry Unit (MC_ME)
• LPU Control Unit (LPU_CTL)
• Power Control Unit (MC_PCU)
• Power Management Controller (PMC)
FLASH
Controller
MC_PCU
PM C-digital
PM C-analog
M C_RGM
Analog
Peripherals,
including I/Os
LPU_CTL
Figure 7-1. Power Management Overview
Finally, the chapter gives a brief introduction about power mode transitions, in
conjunction with other sections of this reference manual.
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Introduction
NOTE
The PMC control registers are in the PMC Digital Interface
(PMC-Dig) module. See that chapter for details on configuring
the PMC.
Table 7-1 defines the abbreviations used throughout this chapter.
Table 7-1. Abbreviations used in this chapter
Abbreviation
Description
Voltage Supplies
VDD_LV
Core logic low voltage supply
VSS_LV
Core logic ground supply
VDD_HV_A
Main I/O voltage supply
VDD_HV_B
Ethernet voltage supply
VDD_LP_DEC
Low power decoupling capacitor
VDD_HV_FLA
Flash memory high voltage supply
VRC_CTRL
PMC Voltage Regulator Control Output
Internal Regulators
FLASHREG
Flash regulator. Regulates flash high voltage
FPREG
Full power regulator. Regulates core logic supply during full power operation
FPREG_init
Full power regulator with internal ballast.Regulates core logic supply during
full power operation
LPREG
Low power regulator. Active in low power modes
ULPREG
Ultra-low power regulator. Active in STANDBY modes
Other
LPU
Low Power Unit. An operational mode in which the main processor core and
some associated peripherals and logic remain powered while the entire rest
of the device is completely power gated off.
See Table 7-2 for links to related information.
Table 7-2. Related information
Link
Description
PMC Digital Interface (PMCDIG) chapter
PMC digital interface module chapter. Contains details on registers used to
configure and control the PMC.
UTEST miscellaneous register [UTEST_MISC] DCF UTEST miscellaneous register. The REG_TYPE bit referenced later in
(See the attached DCF client xls sheet)
this chapter is used when bypassing the internal core logic power regulator
and supplying the core logic voltage from an externally-regulated source.
Modes of Operation
Overview of device operational modes
Mode Entry (MC_ME) Module chapter
Mode Entry module chapter
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Chapter 7 Power Management Overview
7.1.1 Features
Features include:
• A linear regulator with an external NPN ballast to generate a regulated
1.25V(nominal) supply (VDD_LV) for the core logic, using external 5V/3.3V
supply(VDD_HV_A), with an option to bypass the regulator and provide the core
supply externally.
• A linear regulator with an internal ballast(PMOS FET) to generate a regulated
1.25V(nominal) supply (VDD12) for the core logic, using external 5V/3.3V
supply(VDDE_A), with an option to bypass the regulator and provide the core
supply externally.
• Two low power linear regulators (with internal ballasts) to power the core logic
during low power modes (supply VDD_LP_DEC and an internal supply powering
the IOP domain).
• Power switches to isolate voltage islands and configure the device in low power
modes.
• A linear regulator to generate a regulated 3.3V supply for flash memory
(VDD_HV_FLA) when the chip is configured in 5V mode.
• Voltage monitors to ensure the device transitions to a safe state (Power on RESET)
when a supply is out of valid range.
• Controls power mode transitions through the interaction with digital interface.
7.2 Power domains
The MPC5746C microcontroller features multiple power domains to provide
performance configurations with varying power consumption. The power domains are
illustrated in Figure 7-2.
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Power domains
VDD_LV
VRC_CTL
VDD_HV_A
Flash HV
domain
High Power Domain
PD2 domain
FPREG
SW21
PD1 domain
LPREG
FLASHREG
VDD_HV_FLA
ULPREG
SW10
Low Power Domain
VDD_LP_DEC
PD0 domain
RD1
8 KB SRAM
56 KB SRAM
RD2
64 KB SRAM
RD3
128 KB SRAM
Notes:
1. Yellow objects are always powered
2. FPREG - Full Power Regulator
3. LPREG - Low Power Regulator
4. FLASHREG - Flash Regulator
5. ULPREG - Ultra Low Power Regulator
6. PDx - Power Domain x
Figure 7-2. Power block diagram
The following sections describe the power domains in detail.
7.2.1 Power Domain0 (PD0)
PD0 is the ‘always ON’ power domain on the device. This domain plays an important
role in maintaining device configuration as well as providing basic autonomous
functionality with very low power.
7.2.2 Power Domain1 (PD1)
PD1 contains the computational blocks that comprise the LPU domain. This domain is
power gated OFF in STANDBY and LPU_STANDBY modes.
7.2.3 Power Domain2 (PD2)
PD2 consists of various high performance blocks. This domain is power gated off in
STANDBY mode and all LPU modes.
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Chapter 7 Power Management Overview
7.2.4 Flash HV power domain
The Flash HV power domain consists of high voltage devices inside the flash memory
module. This domain must be kept powered at all times while the chip is out of ‘power on
reset’. The domain is supplied by Flash Regulator, as described later in this chapter.
7.2.5 SRAM domains
The MPC5746C microcontroller has a total of 512 KB SRAM, which is divided among
the SRAM domains (known as RDx, where x is from 0 to 3) as follows:
• The RD0 domain contains 8KB SRAM that is always available, and resides in the
PD0 power domain.
• The RD1, RD2, and RD3 SRAM domains, can be configured to be available during
STANDBY.
• The remaining 256 KB SRAM resides in the PD2 power domain. This SRAM is
completely powered off in STANDBY and LPU modes, but is always powered on
(available) in other modes.
NOTE
All SRAM is available in RUN modes.
7.2.6 SRAM Configuration
256K RAM is available in LPU modes for code execution or data storage. Following
guidelines should be considered.
1. RAM Domain Configuration Register (PMCDIG_ RDCR) must be configured to
256K retention mode before enabling LPU subsystem.
2. There is no option to power gate RAM domains in LPU_STOP.
3. RAM Domain Configuration Register (PMCDIG_ RDCR) can be configured to
enable desired retention for enhanced power saving in LPU_STANDBY mode.
Table 7-3. RAM retention
RET_RD256
RET_RD128
RET_RD64
Comments
0
0
0
8K RAM retained
0
0
1
64K RAM retained
0
1
x
128K RAM retained
1
x
x
256K RAM retained
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User operating modes, power domains, and clock gating
7.3 User operating modes, power domains, and clock gating
User operating modes, power domains, and clock gating in the MPC5746C
microcontroller are as follows:
• Power domains are logical divisions within the microcontroller that can be powergated to put the microcontroller in a reduced-power configuration. In other words, a
power domain is a group of modules that can all be shutdown by gating the power to
that domain.
• A user operating mode is a pre-defined group of power- and/or clock settings that can
be applied to the microcontroller while in its normal operational state (DRUN). The
settings control power consumption by controlling the availability of device
functions.
• Within a given user operating mode, clocks can be configured or gated to achieve
desired power targets.
NOTE
• For a full list of the operational modes, see Modes of
Operation.
The table below shows the general settings and options available for user operating
modes.
Table 7-4. User Operating mode settings and options
Powered SRAM Domains 6,,
Flash (PD2)
LPU Peripherals (PD1)
Main Peripherals (PD2)
16 MHz FIRC
8MHz-40MHz FXOSC
Phase Locked Loop (PLL)
128 kHz SIRC
32 kHz SXOSC
OPT
OPT
All
OPT
OPT
OPT
Alway
s ON
OPT
OPT
OPT
OPT
7,, 8
Z4 cores (PD2)
RUN
STOP
PD0
PD1
PD2
PD0
PD1
PD2
Clock Sources
Z2 core (PD1)
2
Operating
Mode
Powered Domains1,,
Chip Features 3,, 4,, 5
CG
CG
All
CG
OPT
OPT
OPT
OPT
CG
OPT
Wake up
Options
N/A
OPT
All
peripheral
interrupts,
refer
Wakeup
Sources for
various
modes
Table continues on the next page...
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Table 7-4. User Operating mode settings and options (continued)
LPU_RUN
PD0
PD1
LPU_STOP PD0
PD1
STANDBY/
LPU_STAN
DBY
PD0
OPT
CG
Off
Off
Off
Off
RD0
RD1
RD2
RD3
RD0
RD1
RD2
RD3
RD0
RD19
RD2
RD3
Off
Off
Off
OPT
CG
Off
Off
Off
Off
Alway
s ON
OPT
OPT
OPT
OPT
OPT
Off
Off
Off
OPT
OPT
OPT
32 kHz SXOSC
128 kHz SIRC
Phase Locked Loop (PLL)
8MHz-40MHz FXOSC
16 MHz FIRC
Clock Sources
Main Peripherals (PD2)
LPU Peripherals (PD1)
7,, 8
Flash (PD2)
Powered SRAM Domains 6,,
Z4 cores (PD2)
Z2 core (PD1)
2
Operating
Mode
Powered Domains1,,
Chip Features 3,, 4,, 5
Wake up
Options
OPT
All
peripheral
interrupts,
refer
Wakeup
Sources for
various
modes
OPT
FLexCAN_0
(PN), no
other
peripheral
interrupts,
refer
Wakeup
Sources for
various
modes
OPT
WKPU
RTC/API
Anal Comp,
refer
Wakeup
Sources for
various
modes
1.
2.
3.
4.
5.
6.
All means all power domains, i.e., PD0, PD1, and PD2
PD0 is always powered during normal device operation
OPT means optionally configurable to be enabled or disabled
CG means clock gated, powered but clock stopped
Off means powered off and clock gated off
Depending on the specific device within the microcontroller famly, there are from 1 to 3 on-chip RAM arrays. RAM array 0
contains multiple blocks of RAM of varying sizes and each is defined by an "SRAM domain", RD0-RD3. See SRAM
domains for details.
7. On-chip RAM not assigned to an SRAM domain is part of the PD2 power domain and is available only when PD2 is
powered.
8. All means all RAM including all SRAM domains plus all additional on-chip RAM.
9. RD1, RD2, and RD3 can be independently configured to be available or not during STANDBY/LPU_STANDBY
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Voltage regulators
7.4 Voltage regulators
The MPC5746C microcontroller has a sophisticated Power Management Unit (PMU)
comprised of four separate voltage regulators.1
7.4.1 FPREG voltage regulator
The FPREG (Full Power Regulator) is a linear regulator that uses an off-chip NPN
transistor as a pass device. This regulator is used during internal regulation mode of the
microcontroller to generate a regulated 1.25V supply (VDD_LV). The VRC_CTRL pin
controls the base of the pass device, while the VDD_LV pins of the device connect to the
emitter of the pass device, as shown in diagram below. Note that VDD_HV_BALLAST
is just for representation – it can be shorted to the source of VDD_HV_A supply on the
application hardware.
Figure 7-3. FPREG voltage regulator
NOTE
VDD_HV_BALLAST can be an independent supply from
VDD_HV_A. Alternatively, these two can be shorted. The
minimum voltage for VDD_HV_BALLAST must be 2.5V-10%
(2.25V) in order to avoid NPN transistor saturation issues.
1.
Refer to datasheet for electrical specifications of these voltage regulators.
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Resistor should not be placed at the collector of NPN. Refer
Table, Voltage regulator electrical specifications, from DS for
related specifications.
If the core logic voltage (VDD_LV) needs to be supplied using an external on board
regulator, the FPREG regulator is bypassed by not connecting the NPN pass device
(leave the VRC_CTRL pin unconnected).
NOTE
Since the default configuration at boot-up is internal regulation
mode, a user option bit UTEST_MISC[REG_TYPE] must be
programmed to disable the FPREG regulator when it is not
needed.
Disabling of the FPREG regulator is applied during RGM phase 3 when SSCM reads
device configuration. Additionally, when using an external VDD_LV supply, the PORST
pin must be driven until the supplies are stable. This can be accomplished by driving
PORST pin such that when external VDD_LV is not stable, PORST is driven LOW
externally, and once VDD_LV is stable, PORST is driven HIGH. Alternatively, another
equally robust solution is to connect PORST pin to VDD_HV_A supply. In this latter
case, multiple voltage monitor resets may be seen during power-up / power-down in
presence of a non-monotonic VDD_LV supply.
Figure 7-4. Using an externally supplied core logic power supply
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Voltage regulators
NOTE
VRC_CTRL pin must be left unconnected on the application
board unless external ballast based internal regulation mode is
used.
7.4.2 Internal regulation (Internal ballast)
The FPREG has it’s ballast sitting on chip. This regulation mode is applicable to only
those use cases where the RunIDD numbers are below 160mA, due to thermal limitation
of the package.
7.4.3 LPREG voltage regulator
The LPREG (Low Power Regulator) is a linear regulator with an on-chip PMOS pass
device. This regulator is active during LPU modes. It powers both PD1 and PD0 domains
(and SW10 is closed). During these modes, power domain PD2 is powered off since
SW21 is open.
NOTE
• LPREG regulator require an off-chip decoupling capacitor,
which must be connected to the VDD_LP_DEC pin. Refer
to the data sheet for the electrical specifications of this
decoupling capacitor.
• The VDD_LP_DEC supply ramps up sometime after the
VDD_LV supply has powered, regardless of whether the
FPREG regulator is used.
7.4.4 ULPREG voltage regulator
The ULPREG (Ultra Low Power Regulator) is a very low power linear regulator with an
on-chip NMOS pass device. This regulator is active during STANDBY modes and
powers the PD0 domain. During this mode, power domains PD2 and PD1 are power
gated OFF since SW21 and SW10 are both open.
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NOTE
• ULPREG regulator require an off-chip decoupling
capacitor, which must be connected to the VDD_LP_DEC
pin. Refer to the data sheet for the electrical specifications
of this decoupling capacitor.
• The VDD_LP_DEC supply ramps up sometime after the
VDD_LV supply has powered, regardless of whether the
FPREG regulator is used.
7.4.5 Flash voltage regulator
The Flash regulator is an on-chip linear regulator that generates 3.3 V supply for Flash
memory, when the device is configured in 5 V mode (UTEST_MISC[5V_3p3V] in
default state). This regulator is bypassed when device is configured in 3.3 V mode, in
which VDD_HV_FLA is connected to VDD_HV_A and both are supplied by the same
external 3.3V source.
NOTE
The Flash regulator always require an off-chip decoupling
capacitor, which must be connected to VDD_HV_FLA pin.
Refer to data sheet for electrical specification of this capacitor.
7.4.6 Regulation mode decoding scheme
Internal regulation (internal ballast) Vs internal regulation (external ballast)
INT_BAL_SELECT pin is a dedicated pin , which is used to select regulation mode
between internal ballast mode Vs external ballast mode.
INT_BAL_SELECT pin tied to VDD_HV_A on board - Internal regulation (internal
ballast).
INT_BAL_SELECT pin tied to ground on board - Internal regulation (external ballast).
Internal regulation Vs external regulation
The ballast is disconnected (un-mounted on board). The customer can apply the core
supply externally. Selection of regulation modes between internal and external regulation
mode is done by reading a bit in DCF record. In external regulation mode as soon as the
DCF is read the internal regulators would be switched OFF.
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Voltage regulators
Table 7-5. Configuration for regulation mode selection
INT_BAL_SELECT
(PIN)
REG_TYPE (DCF bit)
FPREG (external
ballast regulator)
FPREG_int (internal
ballast regulator)
External regulation
mode
1
x
No
Yes
No
0
0
No
No
Yes
0
1
Yes
No
No
NOTE
Last row of the table is the default configuration of the device,
in which the device works in internal regulation mode with
external ballast.
7.4.7 Voltage monitoring
The microcontroller features internal voltage monitoring to ensure supplies are within
their correct operating ranges. If any ‘essential’ supply falls outside of its correct
operating range, the voltage monitors take the device into a ‘safe, power on reset’ state.
The following diagram describes the various voltage monitors and what supplies (and
what point on supply) they monitor. Refer to the data sheet for details on electrical
specifications for these voltage monitors.
NOTE
• The non essential supplies that are NOT shown in the
diagram (VDD_HV_IO_B, VDD_HV_IO_C,
VDD_HV_ADC0, VDD_HV_ADC1 and reference
voltages VDD_HV_ADC1_REF and VIN1_CMP_REF)
below are NOT monitored internally; it is recommended to
implement external voltage monitoring on these supplies, if
required.
• As shown in the followng figure, hot sense point refers to
the point of maximum internal voltage drop due to routing
grid. Hot point has the lowest voltage on that supply
domain. Conversely, cold sense point refers to the source
point for supply, which is the device supply pins.
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Figure 7-5. Voltage monitoring
The below table provides the complete list of voltage detect signals and their
configuration in various modes. For checking there status, refer Supply Gauge Status
Register (PMCDIG_SGSR)
Table 7-6. Voltage detect signals
Voltage detect signals
ULP
LP
RUN
POR_LV
ON
ON
ON
POR_HV
ON
ON
ON
LVD_LV_PD0_hot
ON
ON
ON
LVD_LV_PD1_hot
OFF
ON
ON
LVD_LV_PD2_hot
OFF
OFF
ON
LVD_LV_PD2_cold
OFF
OFF
ON
LVD_IO_A_LO
ON
ON
ON
LVD_IO_A_HI
ON
ON
ON
LVD_FLASH
ON
ON
ON
HVD_LV_cold
OFF
OFF
ON
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External Regulation
NOTE
When the device is configured in 5V mode, the user must
configure LVD_IO_A_HI as a source of functional reset before
transitioning to any of the power gated low power modes
(STANDBY, LPU etc.). If this configuration is not done, the
device may encounter a destructive reset if VDD_HV_IO_A
supply drops below 4.5V.
7.4.8 Applications and Low Power Modes
Depending on application profile, a combination of one or more power modes will be
useful to optimize power dissipation and overall execution speed. For example, powering
off the PD1 and PD2 power domains helps reduce power, particularly at higher
temperatures.
NOTE
• When determining the optimum trade-off between fully
powered and partially powered modes, consideration
should be given to the energy required to recharge the
system capacitances (VDD_LV pin decoupling
capacitance, see the datasheet for specification).
• It is essential to perform power budgeting calculations to
determine which low power mode would be more efficient.
In general, the longer the time spent in a low power mode,
the more efficient it is to use the advanced power gating
features.
7.5 External Regulation
7.5.1 PORST in EXTERNAL REGULATION
It is recommended to drive PORST pin when using external regulation mode, such that
when external VDD_LV is not stable, PORST is driven LOW externally, and once
VDD_LV is stable, PORST is driven HIGH. Alternatively, another equally robust
solution is to connect PORST pin to VDD_HV_A supply. In this latter case, multiple
voltage monitor resets may be seen during power-up/power-down in presence of a nonmonotonic VDD_LV supply.
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During Low Power Modes i.e. all LPU Modes and STANDBY mode, if
UTEST_MISC[PORST_MASK] is set to 0 then PORST must be kept high even if
VDD_LV is supplied externally or not. Pulling PORST pin low in low power modes will
result in chip getting into RESET.
In case UTEST_MISC[PORST_MASK] is set to 1 then PORST pin can be pulled low in
low power modes to indicate externally supplied VDD_LV is not present. Also PORST
pin can be pulled high if externally supplied VDD_LV is within operating range on low
power mode exit.
The device will not exit a low power mode as long as the PORST pin is kept low.
7.5.2 External regulator contol
External regulator control functionality is provided on Pin PG[6]. It indicates if external
regulator can be disabled or VDD_LV can be isolated if device is in one of the power
gated mode i.e. STANDBY or LPU modes.
• External regulator control functionality on Pin PG[6] can be enabled by configuring
UTEST_MISC[EXT_REG_CTRL].
• Polarity of PG[6] can be further controlled by appropriately configuring
UTEST_MISC[EXT_REG_POL].
• This indication can be used to control external circuitry and either disable external
regulator, or isolate VDD_LV pins from the external regulator as shown in Figure
7-6.
The circuit should be designed in such a way that electrical specs stated in the device
datasheet are respected.
VDD_LV
CHIP_MODE
UTEST_MISC
Supplied from External Regulator
RESET
FULL POWER MODE
Supplied from Internal Regulator
Supplied from External Regulator
LOW POWER MODE
FULL POWER MODE
Default Value
Programmed Value
Internal Regulation (Default)
External Regulation (Programmed)
High Polarity (Default)
High Polarity (Programmed)
RESET
PG[6]
UTEST_MISC[REG_TYPE]
UTEST_MISC[EXT_REG_POL]
UTEST_MISC[EXT_REG_CTRL] DCF Control not selected (Default)
DCF Control selected (Programmed)
Figure 7-6. External regulator control handshake protocol
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Accelerated Low Power Exit
NOTE
The circuit is based upon default high polarity of
EXT_REG_CTRL control signal. The pass device needs to
change (NMOS to PMOS) or an inverter needs to be
implemented to modify the required polarity. Refer to
UTEST_MISC register for polarity details.
Figure 7-7. External regulator control
Alternatively, if the user is switching off the external regulator in low power mode, it is
recommended to pull down the VDD_LV to at least 1.08 V.
In this case, user can program EXT_REG_EXIT_TRIM_WAIT DCF counter to indicate
the external regulator stabilization time needed on low power mode exit. See External
Regulation Exit Trim Wait (PMCDIG_ERETW) for details.
7.6 Accelerated Low Power Exit
Device supports reduced wakeup time on low power exit LPU or STANDBY, if
executing from FLASH. The device can automatically select PLL as system clock source
if MC_ME is configured prior to low power mode. This feature allows considerable
improvement in low power exit time where HSM is enabled and requires RAM
initialization as configured through HSM DCF options.
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NOTE
If booting core is z4 and executing from SRAM, this feature
cannot be used as Read Wait State needs to be configured to 1
before making read access to SRAM at PLL frequency.
PLL reference clock source is selected by MC_CGM_AC6_SC before low power mode
is selected. In case FXOSC is turned off in low power mode then wakeup time will
include the stabilization time of FXOSC as configured in FXOSC_CTL[EOCV].
Wakeup time is reduced because of the following enhancements:
• PLL fast lock mechanism is achieved by automatically restoring all the previous
programmed PLL Configurations on low power mode exit thus saving calibration
time and achieving lock faster.
NOTE
Only Last Programmed PLL configuration gets restored
which was used to attain PLL Lock
.
• Automatic selection of PLL as System clock source on low power exits, thus flash
and core initialization and mode transition to desired RUN can happen at faster clock
frequency than FIRC.
Required Software Configurations
• ME_DRUN_MC[SYSCLK] = 0x0002 and ME_DRUN_MC[PLLON] is SET.
• ME_DRUN_MC[FXOSCON] should also be set before entering low power mode,if
FXOSC is selected as the reference clock or FXOSC is available while exiting low
power mode. See DRUN Mode. GPR_CTL[0] should be programmed to 1 before
entering low power mode, if HSM is enabled.
• ME_DRUN_MC[SIRCON] is recommended to be set before entering low power
mode,if SIRC is available while exiting low power mode.
• ME_DRUN_MC[SXOSCON] is recommended to be set before entering low power
mode,if SXOSC is available while exiting low power mode. See DRUN Mode.
• PLL_DIG configured for bypass of calibration to achieve fast PLL lock. Refer PLL
Wakeup from low power mode for further details.
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Accelerated Low Power Exit
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Chapter 8
Low Power Subsystem (LPU)
8.1 Introduction
The low-power unit (LPU) is a subsystem that enables the chip to perform simple tasks
with minimal power consumption. When LPU subsystem is active majority of the chip
can remain power gated, thus achieving the minimal power consumption. Power Domain
1 (PD1) and Power Domain 0 (PD0) are together referred to as the LPU domain. Power
Domain2 is power gated when the LPU subsystem is active. Refer to Modes of Operation
for more information.
Operating modes in LPU subsystem are referred to as LPU modes. Z2 core executes from
the 256 KB system RAM in LPU RUN modes. Maximum operating frequency in LPU
modes is 40 MHz. Tasks performed in LPU modes can include:
• Reacting to incoming messages on the FlexCAN or LINFlexD buses.
• Performing ADC conversions and processing the results.
The chip can enter into LPU mode from any of the RUN modes by configuring the
MC_ME register definition and the LPU Controller (LPU_CTL). Refer to Transition to
LPU mode. LPU_CTL controls all the mode transitions and clock source configurations
in the LPU subsystem independent of the mode entry module.
8.2 Block diagram
The e200z2 core has access to all the peripherals in the LPU subsystem and executes
from the 256 KB RAM.
Modules in power domain 0 (PD0) are always powered. Modules in power domain1
(PD1) will be power gated in LPU_STANDBY mode. Refer to Modes of Operation for
more details.
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Features
e200z2 core
XBAR_LPU
PRAM0
RAM 256K
PBRIDGE_A
Debug
CJTAG
INTC
EMIOS0
SPI0
LINFlexD_0
JTAGC
BCTU
NPC
SIUL
CMU
ACMP2
LPU_CTL
SSCM
MEMU_1
FlexCAN0
ACMP1
WKPU
ACMP0
PMC
MC_
PCU
FXOSC
MC_
RGM
RTC
SXOSC
SIRC
ADC0
SWT0
STM0
FIRC
PD0 modules
PD1 modules
DMC
iAHB GASKET + E2E ECC
Figure 8-1. LPU subsystem diagram
8.3 Features
• The LPU subsystem can enter into three low-power modes:
• LPU_SLEEP
• LPU_STOP
• LPU_STANDBY
• Nexus class one seamlessly through RUN and LPU mode
• Debug through LPU_STOP and LPU_STANDBY is supported
• Full interrupt support from LPU domain peripherals
• Clock sources available:
• FIRC
• FXOSC
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• SIRC
• SXOSC
• A divided FIRC or FXOSC are available as a system clock source.
• Clock monitoring unit available for measurement of frequency for all clock sources
and frequency range check for FXOSC.
• The MEMU module captures faults from the following four sources and raises an
interrupt or NMI to the z2 core:
• AHB_E2E_ECC error from PBRIDGE A
• z2 intstruction bus error
• z2 data bus error
• PRAM_E2E_ECC error from PRAM_CTL0
• Pretended Networking supported on FlexCAN0. It is also possible to wake up from
LPU_STOP to LPU_RUN with only the protocol engine clock of FlexCAN0
working when a valid match is found on received message buffer. For details, refer
FlexCAN configuration.
• Configurable FlexCAN0 wakeup events:
• Wakeup on “bus off”
• Matching message: Receives a pre-configured message
• Matching message and data: Pre-configured message and RX data matches value
• Matching range of messages: RX a range of pre-configured messages
• Matching message range and data
• Matching data received n times
• Pre-configured data missing over specific time
• Pre-configured network management message missing over a specific time
• Payload length error if a pre-configured message
• Configurable FlexCAN0 Transmit Messages
• Transmit network management message
• Transmit pre-configured static message
NOTE
LPU_STANDBY mode is the mode when power domain 1 is
power-gated. This mode is entered from LPU_RUN mode. If
the chip enters power-gated mode from normal RUN mode, it is
referred as STANDBY mode. The only difference between the
two modes is how the clock sources are configured. Select the
clock sources to be on or off by configuring:
• ME_STANDBY0_MC for STANDBY mode
• LPU_STANDBY_CF for LPU_STANDBY mode
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Modes of operation
8.4 Modes of operation
RUNn
LPU_STOP
LPU_RUN
LPU_SLEEP
DRUN
LPU_STANDBY
Figure 8-2. LPU modes
• LPU_RUN
• All modules in the LPU domain have their clocks enabled.
• The chip can enter into LPU_RUN mode under the following conditions:
• From any of the RUN modes by configuring the ME_MCTL and
LPU_MCTL registers.
• On exit from LPU_STOP,LPU_SLEEP
• On exit from LPU_STANDBY, if LPU_MCTL[DIRECT_DRUN] is not set.
• The chip can exit to DRUN, LPU_STOP, or LPU_STANDBY only via
configuring the LPU_MCTL register.
• FIRC is always ON during either LPU_RUN or LPU_SLEEP mode. All other
clock sources can be disabled. LPU domain modules can be configured via
LPU_MDIS to be clock gated. To change clock source configuration or clock
gate modules, an LPU_RUN-to-LPU_RUN mode transition is required.
• LPU_SLEEP
• In this mode, the z2 core enters low-power state and its clock is gated. All other
modules in the LPU domain have their clocks enabled by default and can be
disabled by configuring LPU_MDIS.
• The device can enter into LPU_SLEEP mode from LPU_RUN mode.
• The device can exit to LPU_RUN mode on any peripheral interrupt or external
interrupt, or WKPU source.
• All the LPU peripheral interrupts can cause exit from LPU SLEEP.
• LPU_STOP
• In this mode, the z2 core enters the low-power state and its clock is gated.
FLexCAN pretended network feature is available but all peripherals are stopped,
clocks are gated to all modules in LPU domain. Clock sources are enabled or
disabled by configuring the LPU_STOP_CF register.
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• The chip can enter LPU_STOP mode from LPU_RUN mode.
• The chip can exit to LPU_RUN mode when a wakeup event comes from WKPU,
SWT timeout, RTC/API, or FlexCAN pretended network interrupt.
NOTE
There should be no pending interrupts or outstanding
transactions as it may not allow entry in LPU_STOP. To
centrally ensure this, all modules can be disabled by
configuring LPU_MDIS in LPU_RUN to LPU_RUN mode
transition followed by LPU_STOP mode entry. To bypass
STOP acknowledge handshake with LPU domain modules,
refer GPR_CTL[LPU_STOP_ACK_BYPASS].
• LPU_STANDBY
• This mode is entered when the chip enters STANDBY mode from LPU_RUN
mode.
• All modules in the PD1 domain are power gated.
• Device can exit to LPU_RUN mode or DRUN mode when a wakeup event
comes from the WKPU, SWT timeout interrupt, or RTC/API timeout interrupt.
An Analog comparator can also provide wakeup functionally, if enabled.To exit
to DRUN mode, LPU_RUN_CF[DIRECT_DRUN] should be set to 1 before
requesting for LPU_STANDBY mode transition.
The following guidelines should be observed when preparing to enter an LPU
mode before initiating further low power mode request in LPU:
• LPU_SR[PD2_PWR_STAT] should be polled to be 0 to ensure PD2 is power
gated.
• FIRC_CTL[FIRCDIV] should be configured to 0x0 before initiating
LPU_STANDBY mode request. It should be reconfigured appropriately on exit
to LPU_RUN or DRUN from LPU_STANDBY exit
• PMC_RDCR[PAD_KEEP_EN] should be configured appropriately.
• PMC_RDCR[RD*_RETN] should be configured appropriately
8.5 Transition to LPU mode
The following flowchart shows the hardware state transition from user RUNx/DRUN
mode to LPU subsystem RUN mode, that is, LPU_RUN.
Care should be taken that there are no active ongoing transactions on power domain 2
peripherals. Clocks to the processor are gated after the acknowledgement of the lowpower stop request from the MC_ME.
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Transition to LPU mode
The LPU subsystem is enabled after gating the main XBAR clock, while the power
gating mechanism is ongoing. Enabling the LPU subsystem before power gating PD2
will allow the z2 core to be available as early as possible to service power domain 1
peripherals, if required.
Clock source enabling and disabling is controlled by the LPU_RUN_CF register as soon
as TARGET LPU_RUN mode is requested.
NOTE
The device can enter LPU_STOP or LPU_STANDBY mode
from LPU_RUN mode only. The following mode transitions
are illegal and if attempted will result the chip to go into
STANDBY mode:
• Any RUN/DRUN to LPU_STOP
• Any RUN/DRUN to LPU_STANDBY
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Chapter 8 Low Power Subsystem (LPU)
Start
TARGET LPU
mode request
Clock source ON/OFF
based on LPU_RUN_CF
Write LPU_MCTL[TARGET_MODE] = 1011
Write ME_MCTL[TARGET_MODE] = 1101
Write key and inverted key to ME_MCTL
Write key and inverted key to LPU_MCTL
PD2 peripherals
STOPPED and
CLKS disabled
Chip low power
entry and CLKS disabled
Main XBAR CLK disabled
XBAR_LPU CLK enabled
Internal housekeeping by
MC_CGM/MC_ME
LPU modules clocks
switched to LPU
system clock
Power gating of PD2 by PCU
z2 reset vector applied.
z2 CLK enabled
LPU_SR[CURRENT_M
ODE] = LPU_RUN
End
Figure 8-3. Mode transition to LPU mode
NOTE
The transition to LPU mode will not complete if any of the
cores are in debug mode.
The following basic code snippet demonstrates how the registers and bit fields are
programmed to transition from DRUN to LPU_RUN mode. LPU entry can be carried out
on any of the cores: z4 or z2.
void LPU_RUN_init ()
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Transition to LPU mode
{
LPU.LPU_RUN_CF.B.CRSxON = 1;
/* LPU_RUN init */
LPU.LPU_MCTL.B.TARGET_MODE = 0b1011;
LPU.LPU_MCTL.B.KEY = 0x5AF0;
LPU.LPU_MCTL.B.KEY = 0xA50F;
/* Enabled clock sources for LPU_RUN mode. */
/* Request for LPU_RUN mode */
/* Write the key to initiate mode change. */
/* Write the inverted key to finalise the */
/* mode change. */
/* Mode Entry - Standby0 mode init */
/* In order to enter into LPU_RUN mode, Standby0 must be */
/* initialized to disable non-required functionality. */
MC_ME.MC_ME_MCTL.B.TARGET_MODE = 0b1101;
/* Configure ME for standby0 entry. */
MC_ME.MC_ME_MCTL.B.KEY = 0x5AF0;
/* Write the key to initiate mode change. */
MC_ME.MC_ME_MCTL.B.KEY = 0xA50F;
/* Write the inverted key to finalise the mode
change. */
/* Loop here until the
Standby0 mode */
/* transition has
occurred by reading */
/* back the current
operating mode. */
/* Loop here until the LPU mode transition has occurred */
/* and also read back the current operating mode. */
while((LPU.LPU_SR.B.MTRANS != 1) && (LPU.LPU_SR.B.CURRENT_MODE = 0b1011));
}
The following guidelines should be observed when preparing to enter an LPU mode:
• Ensure steps have been taken to initialize the appropriate core via the Mode Entry
registers MC_ME_CADRRn and MC_ME_CCTLn.
• LPU clock source configuration must be done prior to an LPU mode transition
request because the new configuration is selected only after a valid mode transition.
• Prepare to enter LPU modes by writing appropriate LPU target mode and keys to the
LPU Mode Control Register, LPU_MCTL.
• To complete the transition, enable STANDBY mode via the Mode Entry registers,
which provides the necessary preparation of disabling functionality not required
within the LPU modes.Please ensure all software guidelines mentioned for
STANDBY mode in MC_ME chapter are followed here.
• LPU mode transition status, LPU_SR[MTRANS], is asserted only after the mode
entry target mode is configured to be Standby0.
• Complete the transition by reading the LPU status register, LPU_SR, for transition
complete and current mode as expected.
• Register protection configuration should follow the guideline mentioned in section:
Register protection configuration
NOTE
SWT_0 enabling or disabling is prohibited in LPU modes. It
should be configured prior to entry in LPU.
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NOTE
After initiating any mode transition, the software should poll
for LPU_SR[MTRANS] before initiating any other mode
transition.
For the DRUN -> (LPU modes) -> DRUN transition, any one of the following two
conditions should be satisfied by the software:
• If FXOSC is to be used in LPU modes as LPU_SYS_CLK, then FXOSC should be
kept ON in DRUN before/after LPU mode is entered/exit.
• If LPU RUN is entered with FXOSC off in DRUN mode, then LPU_SYS_CLK
should be made as IRC before entering into LPU STANDBY.
8.6 Exit from LPU Modes
The following flowchart shows the hardware state transition from user LPU_RUN to
DRUN mode.
Exit from LPU_RUN to DRUN
This can be initiated by software by configuring LPU_MCTL. LPU_CTL requests
PMCDIG to initiate power up of Power Domain 2. Glitch free clock switching occurs
from LPU_SYS_CLK to CGM_CLK on LPU mode exit. LPU peripherals will be clock
gated. Care should be taken that there are no active ongoing transactions on LPU
peripherals before requesting exit to DRUN mode. Clocks to the processor are gated after
the acknowledgement that Power Domain 2 is powered. Power Domain 2 goes through
reset sequence and z2 core is enabled if it was configured via ME_CADDR and
ME_CCTL prior to entry in LPU modes.
Clock source enabling and disabling and mode transition controls are now transferred
back to ME from LPU_CTL.
Exit from LPU_STANDBY to DRUN
Any wakeup source can take the chip back to DRUN mode, if
LPU_RUN_CF[DIRECT_DRUN] was configured to 1 before LPU_STANDBY mode
transition request was initiated. Exit sequence is identical to exit from DRUN except that
LPU peripherals and processors were already power gated in LPU_STANDBY, so no
housekeeping is required by software
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Clocking
Start
End
Figure 8-4. Exit from LPU_RUN to DRUN
8.7 Clocking
8.7.1 LPU System Clock Generation
The two primary clock sources, FIRC and FXOSC, are the source of the system clock
network in the LPU domain (see Clocking chapter for details). The 16 MHz FIRC clock
is the default clock source in LPU_RUN mode. The frequency of the LPU system clock
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can be scaled down by configuring the FIRC and FXOSC dividers via the FIRC_CTL
and FXOSC_CTL registers, respectively. SIRC and SXOSC are also available for timers,
for example, SWT and RTC (see SWT and RTC).
In LPU modes, the LPU system clock is the multiplexed output of either the FIRC divider
or the FXOSC divider as shown below. The maximum operating frequency is 40 MHz.
All the module clocks switch from MC_CGM (CGM_CLK) to LPU_SYS_CLK. For
example, the z2 clock is sourced from the S80 group, but in LPU mode it will be sourced
from the LPU_SYS_CLK. There is a multiplexer between CGM_CLK and
LPU_SYS_CLK for each clock frequency node in frequency groups, that is, F160, S160,
S80, F80, F40, S40, FS80, and F20. Refer to Clock Generation Module (MC_CGM) for
clocking details.
All the module clocks will be gated for period less than or equal to 2 clock cycle of
current clock plus 2 clock cycle of next clock period to allow glitch free switching of
clocks to LPU_SYS_CLK.
LPU_MODE (See note)
LPU_RUN_CF
[SYS_CLK_SEL]
CGM_CLK
FIRCDIV
0
Module
0
LPU_SYS_CLK
1
FXOSCDIV
1
Note: LPU_MODE implies any of the three LPU modes - LPU_RUN, LPU_STOP, LPU_SLEEP, and LPU_STANDBY.
There is no software control for this mux. Switching is handled during RUN to LPU_RUN transition protocol.
Figure 8-5. LPU clocking
NOTE
If the CGM mapped peripherals registers of module FIRC,
FXOSC, SIRC, SXOSC, CMU are protected under Register
protection scheme before transitioning to LPU mode then the
protected registers will not be accessible during LPU mode for
further write operation. Protected register would be available
for read operation. Hence if any register is required to be
modified during LPU mode then software should ensure that
these registers should remain unlocked under register protection
scheme.
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Clocking
NOTE
FIRC, FXOSC, SIRC, SXOSC, CMU registers cannot be
locked under register protection scheme during LPU mode.
8.7.2 FlexCAN0 Clocking
CAN0 Clocking
During an LPU mode, working clock of all modules except CAN0 will be the same as the
LPU system clock.
Device can be configured to support seamless operation of CAN0 during LPU_RUN
mode entry and exit. This can be ensured by providing continuously running clock
through an independent mux. This configuration should be done before CAN0 is enabled
in device DRUN/RUNx modes. CAN0 CHI and PE interfaces would be synchronously
operating with frequency ratio 1:1 and corresponding CAN network configurations
should be done based on max CHI frequency equal to FXOSC frequency.
• MC_CGM_AC9_SC should be configured to select FXOSC. Refer FlexCAN
clocking
• LPU_RUN_CF[CAN0_CONT] should be SET to ensure seamless operation on
LPU_RUN to DRUN. Refer LPU Memory map and register definition
8.7.3 LinFlexD Clocking
LINFlexD[0] requires 2 clocks for operation : BUS_CLK and BAUD_CLK. Frequency
of these clocks should satisfy the equation freq(BAUD_CLK)/3 is less than
freq(BUS_CLK) and freq(BUS_CLK) is less than BAUD_CLK.
• BAUD CLK: Baud clock is generated from F40 node It is recommended to select
FXOSC as source of baud clock. The baud clock may disappear for few cycles while
switching from CGM_CLK to LPU_SYS_CLK.
• BUS CLK: While entering LPU modes, F20 node which is the BUS_CLK of
LINFlexD[0] is same as LPU_SYS_CLK. A divider is automatically enabled to scale
F20 node by 2 in LPU modes. Refer LINFlexD clocking
8.7.4 SPI_0 Clocking
SPI requires 2 clocks for operation : BUS_CLK and BAUD_CLK. BAUD_CLK is
absolutely asynchronous to BUS_CLK. Baud clock is generated from a mux which is
controlled by MC_CGM_AC8_SC. It is recommended to select FXOSC as source of
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baud clock. If F40 is selected as source of baud clock than this clock may disappear for
few cycles while switching from CGM_CLK to LPU_SYS_CLK. Refer DSPI/SPI
clocking
8.7.5 LPU clock source control
For all LPU modes, clock source enabling and disabling is controlled by the LPU mode
configuration registers.
FIRC cannot be disabled in LPU_RUN mode or LPU_SLEEP mode. All the module
clocks, that is, clocks that are operating from the LPU system clock, will be gated in the
LPU_STOP mode and the LPU_STANDBY mode. For more information, see the Table
7-4.
All clock sources can be disabled in any of the low-power modes, that is, LPU_STOP
and LPU_STANDBY.
8.8 Reset
Reset generation and control is supported through the MC_RGM module. Both
destructive and functional resets are supported.
The only reactions possible via functional reset sources is Long Reset or Short Reset. It is
not possible to generate a SAFE mode request or interrupt via the MC_RGM while in
LPU mode.
On reset, the chip will exit to DRUN mode from any of the LPU modes.
NOTE
During Low Power Modes i.e. all LPU Modes and STANDBY
in external regulation mode PORST must be kept high even if
VDD_LV is supplied externally or not. Pulling PORST pin low
in case VDD_LV is not driven externally in low power modes
will result in chip getting into RESET.
Following are the active reset sources in the LPU mode.
Table 8-1. Destructive reset sources
Reset Source Mapping
Destructive Reset Source
Reactions Possible
Bidirectional External reset
generation/Software
control
7
SWT0 (flash initialization
error)
Destructive
Yes/Read_only
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Interrupts
Table 8-2. Functional reset sources
Reset Source Mapping
Functional Reset Source
Reactions Possible
Bidirectional External reset
generation/Software
control
4
NMI from wakeup unit
Long/Short
No/Read_Write
5
JTAG Reset
Long/Short
No/Read_Write
7
FXOSC frequency out of
range from CMU
Long/Short
No/Read_Write
12
z2 Debug Reset
Long/Short
No/Read_Write
13
LVD_IO_A_HI Reset
Long/Short
No/Read_Write
NOTE
If the application software is required to trigger a software reset
in LPU_RUN this can be achieved via z2 core register
DBCR0[RST]. This reset will be flagged at
RGM_FES[F_Z2_DBG].
The LPU_CTL can enter, gate, or control the reset process as listed in the following table
together with their type of contribution.
Table 8-3. Reset Process Modules
Module
Contribution Type
LPU_CTL
event
gating
control
Yes
Yes
Yes
The types of contribution are described in the following table.
Table 8-4. Module contribution type
Contribution Type
Description
event
The module may generate events which may trigger the entry
into a reset state, if the event configuration in the MC_RGM
allows this.
gating
The module can prevent the exit of a reset state if it has not
reached a certain internal state.
control
The module controls the sequence of the reset process.
8.9 Interrupts
Interrupts from modules in the LPU domain are supported. Interrupt mapping is
consistent across full modes to LPU modes. Refer to INTC interrupt sources for details.
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NOTE
If any interrupt is pending before requesting mode transition to
LPU_STOP and LPU_STANDBY, the mode transition request
would be ignored.
8.10 Boot
On entry into LPU_RUN mode, the z2 is reset and starts executing from SRAM0 at
0x4000_0000 on reset de-assertion. On LPU_STANDBY exit to LPU_RUN mode, the z2
starts executing from SRAM0 at 0x4000_0000. The device can boot from any core on
exit from LPU_RUN/LPU_STANDBY mode.
Upon LPU_STANDBY exit to DRUN mode, which can happen if the exit occurs due to a
reset event or LPU_RUN_CF[DIRECT_DRUN] bit is set before entering in
LPU_STANDBY, the z2 will start executing from the address configured in
MC_ME[CADDR3] if it is enabled in MC_ME[CCTL3]. For more information see,
Table 13-18.
NOTE
Configure MC_ME[CADDRn] and MC_ME[CCTLn] prior to
entering LPU_RUN mode.
8.11 LPU Controller (LPU_CTL)
The LPU controller module controls the mode transition sequences for LPU modes. It
also contains configuration, control, and status registers accessible to the application. The
LPU controller takes ownership to control the mode from the MC_ME module whenever
the chip enters LPU_RUN mode. The LPU controller generates the necessary control
signals during various LPU modes for the following:
• clock gating and clock source control
• reset control
• debug handshake across RUN to LPU_RUN and within LPU_MODES
8.11.1 Memory map and register definition
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LPU Controller (LPU_CTL)
LPU memory map
Address
offset (hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
0
LPU Mode Control Register (LPU_MCTL)
32
R/W
3000_A50Fh
8.11.2/174
4
LPU Run Configuration Register (LPU_RUN_CF)
32
R/W
0000_0001h
8.11.3/176
8
LPU Stop Configuration Register (LPU_STOP_CF)
32
R/W
0000_0001h
8.11.4/178
C
LPU Standby Configuration Register (LPU_STANDBY_CF)
32
R/W
0000_0001h
8.11.5/179
10
LPU Status Register (LPU_SR)
32
R
0001_8003h
8.11.6/180
14
LPU Interrupt control register (LPU_ICR)
32
w1c
0000_0000h
8.11.7/183
18
Module Disable (LPU_MDIS)
32
R/W
0000_0000h
8.11.8/185
8.11.2 LPU Mode Control Register (LPU_MCTL)
This register is used to trigger software-controlled LPU mode changes. Software can
configure LPU_MCTL[TARGET_MODE] to DRUN, LPU_STOP, or LPU_STANDBY
only when the current mode is LPU_RUN.
Byte and half-word write accesses are not allowed to this register because a predefined
key is required to change its value.
NOTE
Further low power mode transitions i.e. LPU_STANDBY and
LPU_STOP should not be requested if
LPU_SR[PD2_PWR_STAT] is 1. Software should wait for
PD2 to be power gated before requesting further low power
modes.
NOTE
Software should always check
PMCDIG_MCR[LP_ST_CHG_IN_PRGRS] is 0 before a new
mode transition request is initiated.
Address: 0h base + 0h offset = 0h
Bit
R
W
Reset
0
1
2
3
4
5
6
7
8
9
TARGET_
MODE
0
0
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
0
0
0
1
1
1
1
KEY
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
LPU_MCTL field descriptions
Field
Description
0–3
Target Chip Mode
TARGET_MODE
This field provides the target mode to be entered by software. The mechanism to enter into any mode by
software requires two write operations:
Table continues on the next page...
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Chapter 8 Low Power Subsystem (LPU)
LPU_MCTL field descriptions (continued)
Field
Description
1. Write key.
2. Write inverted key.
NOTE: LPU_SLEEP is entered by configuration of LPU_RUN_CF[LPU_SLEEP].
0011
1011
1100
1110
4–15
Reserved
16–31
KEY
DRUN
LPU_RUN
LPU_STOP
LPU_STANDBY
This field is reserved.
This read-only field is reserved and always has the value 0.
This field provides the key to change the target mode. Any write access to the register with a value
different from the keys is always ignored. Read access will always return the inverted key
KEY: 0101_1010_1111_0000 (0x5AF0)
INVERTED KEY: 1010_0101_0000_1111 (0xA50F)
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LPU Controller (LPU_CTL)
8.11.3 LPU Run Configuration Register (LPU_RUN_CF)
This register configures system behavior during LPU_RUN.
NOTE
LPU_RUN_CF[SYS_CLK_SEL] should never be changed
from 1 to 0 in DRUN/RUNx modes. Also, if
LPU_RUN_CF[SYS_CLK_SEL] is selecting FXOSC then
LPU_RUN_CF[FXOSC_ON] should also be SET.
Address: 0h base + 4h offset = 4h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
CAN0_CONT
R
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
FXOSC_ON
0
SIRC_ON
LPU_SLEEP
0
0
SXOSC_ON
SYS_CLK_SEL
0
DIRECT_DRUN
0
R
FIRC_ON
Reset
W
Reset
0
0
0
0
0
0
0
0
0
0
1
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Chapter 8 Low Power Subsystem (LPU)
LPU_RUN_CF field descriptions
Field
0–14
Reserved
15
CAN0_CONT
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
CAN0 continuous operation across LPU modes. CAN CHI frequency will switch from FS80 to
LPU_SYS_CLK which will require reconfiguration thus inhibiting continuous operation across LPU modes.
0
1
16–22
Reserved
Continuous CAN0 operation is not supported
Continuous CAN0 operation is supported. CAN0 needs to be operated by selected FXOSC as the
source of its CHI clock by configuring MC_CGM_ACx
This field is reserved.
This read-only field is reserved and always has the value 0.
23
Transition to DRUN on LPU_STANDBY exit
DIRECT_DRUN
0 Switch to LPU_RUN on exit from LPU_STANDBY
1 Switch to DRUN on exit from LPU_STANDBY
24
System clock selection in LPU RUN mode
SYS_CLK_SEL
0 Select FIRC clock source
1 Select FXOSC clock source
25
LPU_SLEEP
Core sleep request during LPU RUN
0
1
No core sleep request
Core sleep request
26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
SXOSC_ON
SXOSC control during LPU_RUN
28
SIRC_ON
SIRC control during LPU_RUN
29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
FXOSC_ON
FXOSC control during LPU_RUN
31
FIRC_ON
FIRC oscillator control during LPU_RUN
0
1
0
1
0
1
1
0
SXOSC clock source off
SXOSC clock source on
SIRC clock source off
SIRC clock source on
FXOSC clock source off
FXOSC clock source on
FIRC clock source on
Reserved
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LPU Controller (LPU_CTL)
8.11.4 LPU Stop Configuration Register (LPU_STOP_CF)
This register configures system behavior during LPU_STOP.
Address: 0h base + 8h offset = 8h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRC_ON
0
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
SIRC_ON
0
SXOSC_ON
Reset
FXOSC_ON
W
0
0
0
0
LPU_STOP_CF field descriptions
Field
Description
0–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
SXOSC_ON
SXOSC control during LPU_STOP
28
SIRC_ON
SIRC control during LPU_STOP
29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
FXOSC_ON
FXOSC control during LPU_STOP
31
FIRC_ON
FIRC oscillator control during LPU_STOP
0
1
0
1
0
1
0
1
SXOSC clock source off
SXOSC clock source on
SIRC clock source off
SIRC clock source on
FXOSC clock source off
FXOSC clock source on
FIRC clock source off
FIRC clock source on
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Chapter 8 Low Power Subsystem (LPU)
8.11.5 LPU Standby Configuration Register (LPU_STANDBY_CF)
This register configures system behavior during LPU_STANDBY.
Address: 0h base + Ch offset = Ch
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIRC_ON
0
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
SIRC_ON
0
SXOSC_ON
Reset
FXOSC_ON
W
0
0
0
0
LPU_STANDBY_CF field descriptions
Field
Description
0–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
SXOSC_ON
SXOSC control during LPU_STANDBY
28
SIRC_ON
SIRC control during LPU_STANDBY
29
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
FXOSC_ON
FXOSC clock source control during LPU_STANDBY
31
FIRC_ON
FIRC oscillator control during LPU_STANDBY
0
1
0
1
0
1
0
1
SXOSC clock source off
SXOSC clock source on
SIRC clock source off
SIRC clock source on
FXOSC clock source off
FXOSC clock source on
FIRC clock source off
FIRC clock source on
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LPU Controller (LPU_CTL)
8.11.6 LPU Status Register (LPU_SR)
This register provides the system status during LPU mode.
NOTE
The current mode would be updated as the target mode during
the mode transition is ongoing i.e.,
LPU_SR[CURRENT_MODE] would be updated during
LPU_SR[MTRANS] = 1.
3
4
5
6
7
8
9
0
R
10
11
12
13
14
15
0
FIRC_STAT
2
FXOSC_STAT
1
SIRC_STAT
0
SXOSC_STAT
Bit
PD2_PWR_STAT
Address: 0h base + 10h offset = 10h
0
0
0
0
0
1
W
Reset
0
0
0
0
0
0
0
0
0
0
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16
17
R
CLK0_STOP
1
0
18
19
20
21
22
23
24
25
0
26
27
MTRANS
Bit
CLK1_STOP
Chapter 8 Low Power Subsystem (LPU)
0
0
0
28
29
30
31
CURRENT_MODE
W
Reset
0
0
0
0
0
0
0
0
0
0
1
1
LPU_SR field descriptions
Field
Description
0–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10
PD2_PWR_
STAT
Ensures the main domain (power domain 2) is power gated completely.
11
SXOSC_STAT
SXOSC clock source status
12
SIRC_STAT
SIRC clock status
13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
0
1
0
1
Main domain is power gated.
Main domain is powered
SXOSC clock source off
SXOSC clock source on
SIRC clock source off
SIRC clock source on
14
FXOSC_STAT
FXOSC clock source status
15
FIRC_STAT
FIRC clock status
0
1
0
1
FXOSC clock source off
FXOSC clock source on
RC Oscillator off
RC Oscillator on
Table continues on the next page...
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LPU Controller (LPU_CTL)
LPU_SR field descriptions (continued)
Field
Description
16
CLK1_STOP
FXOSC clock status during LPU mode
17
CLK0_STOP
FIRC status during LPU mode
0
1
0
1
FXOSC clock selected as system clock
FXOSC clock not selected as system clock
FIRC clock selected as system clock
FIRC clock not selected as system clock
18–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
26
MTRANS
LPU mode transition
27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–31
CURRENT_
MODE
Current mode of the chip
0
1
No LPU mode transition
LPU mode transition is in progress
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
RESET
Reserved
SAFE
DRUN
RUN0
RUN1
RUN2
RUN3
Reserved
Reserved
STOP0
LPU_RUN
LPU_STOP
STANDBY0
LPU_STANDBY
Reserved
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Chapter 8 Low Power Subsystem (LPU)
8.11.7 LPU Interrupt control register (LPU_ICR)
This register controls whether an event generates an interrupt. It also provides the
interrupt status.
Address: 0h base + 14h offset = 14h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
Reserved
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
Reserved
0
Reserved
LPU_NEM_E
0
LPU_NEM
Reset
W
LPU_MRIG
LPU_MRIG_E
R
w1c
w1c
w1c
w1c
0
0
0
0
LPU_ICR field descriptions
Field
0–11
Reserved
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
12
LPU_MRIG_E
LPU mode request ignored interrupt enable
13
LPU_NEM_E
LPU non-exist mode interrupt enable
0
1
0
1
Disable interrupt
Enable interrupt
Disable interrupt
Enable interrupt
Table continues on the next page...
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LPU Controller (LPU_CTL)
LPU_ICR field descriptions (continued)
Field
Description
14
Reserved
This field is reserved.
15
Reserved
This field is reserved.
16–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28
LPU_MRIG
LPU mode request ignored
This field is set if during LPU_RUN the core tries to enter a low-power mode, that is, LPU_STOP or
LPU_STANDBY, while the interrupt is pending. The core is still able to go to DRUN mode, however.
0
1
29
LPU_NEM
Mode request ignored interrupt is not pending
Mode request ignored interrupt is pending
LPU non-exist mode interrupt
This field is set if the mode transition request through the LPU_MCTL register is to a nonexistent mode,
that is, not one of the four valid modes: DRUN, LPU_RUN, LPU_STOP, or LPU_STANDBY. The field is
cleared by writing 1 to it.
0
1
Non-exist mode interrupt is not pending
Non-exist mode interrupt is pending
30
Reserved
This field is reserved.
31
Reserved
This field is reserved.
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Chapter 8 Low Power Subsystem (LPU)
8.11.8 Module Disable (LPU_MDIS)
If a module is disabled in RUN mode using ME_PCTL, it is suggested to configure
MDIS to 1 in LPU modes as by default the clock to that module will be enabled while
transitioning to LPU mode.
NOTE
Module system bus clocks are gated in LPU_STOP mode
without any option of keeping them ON.
NOTE
During transition from RUNx mode to LPU_RUN mode,
peripherals clock gated with LPU_MDIS will observe few
clock cycles. Hence it is recommended to check and clear any
pending interrupts in LPU_RUN mode. For example, it is
possible to have a MEMU interrupt flag set due to some free
running clock cycles during RUNx to LPU transition.
Address: 0h base + 18h offset = 18h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
R
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
eMIOS_0
CMP_2
CMP_1
CMP_0
MEMU_1
BCTU
CAN0
LIN_0
SPI_0
ADC_0
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
0
0
0
LPU_MDIS field descriptions
Field
Description
0–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
22
eMIOS_0
eMIOS_0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that eMIOS_0 will be enabled while transitioning to LPU mode.
0
1
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
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LPU Controller (LPU_CTL)
LPU_MDIS field descriptions (continued)
Field
23
CMP_2
Description
CMP_2 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that CMP_2 will be enabled while transitioning to LPU mode.
0
1
24
CMP_1
CMP_1 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that CMP_1 will be enabled while transitioning to LPU mode.
0
1
25
CMP_0
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
SPI_0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes as
by default the clock to that SPI_0 will be enabled while transitioning to LPU mode.
0
1
31
ADC_0
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
LIN_0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes as
by default the clock to that LIN_0 will be enabled while transitioning to LPU mode.
0
1
30
SPI_0
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
CAN0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes as
by default the clock to that CAN0 will be enabled while transitioning to LPU mode.
0
1
29
LIN_0
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
BCTU is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes as
by default the clock to that BCTU will be enabled while transitioning to LPU mode.
0
1
28
CAN0
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
MEMU_1 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that MEMU_1 will be enabled while transitioning to LPU mode.
0
1
27
BCTU
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
CMP_0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that CMP_0 will be enabled while transitioning to LPU mode.
0
1
26
MEMU_1
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
ADC_0 is disabled in RUN mode using ME_PCTL, it is suggested to configure MDIS to 1 in LPU modes
as by default the clock to that ADC_0 will be enabled while transitioning to LPU mode.
0
1
Module clock is enabled in LPU_RUN or LPU_SLEEP mode.
Module clock is disabled in LPU_RUN or LPU_SLEEP mode.
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Chapter 9
Clocking Overview
9.1 Introduction
This chapter describes the architecture for the system level clocks and includes the
following information:
• Dynamic frequency scaling
• System clock specifics
• Clock architecture
• Clock sources
• Clock monitoring
• Programmable clock dividers
• Clock control registers
• Progressive clock switching
NOTE
This chapter covers only clocks that are generated on the
device. Protocol clocks that are provided by external devices
are covered in the respective chapters where they are used.
The system clock can be configured as frequency modulated clock to reduce
electromagnetic emissions, while having a precise clock for timers and communication
functions1. There is also the ability of the chip to enter a low power mode and utilize the
low power clocks.
The device boots from the internal 16 MHz RC oscillator (FIRC), and uses this as a
backup clock in the event of a PLL or oscillator failure. The backup clock is enabled in
the Mode Entry Module (MC_ME) (see the "Mode Entry Module (MC_ME) Overview
chapter for details).
System clocks can be generated from the three sources:
1.
Using the frequency modulated clock is not recommended for LINFlexD.
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System clock generation
• Fast external crystal oscillator 8 – 40 MHz (FXOSC)
• Fast internal RC oscillator 16 MHz (FIRC)
• Frequency-modulated phase-locked loop (FMPLL)
Additionally, there are two low power oscillators:
• Slow internal RC oscillator 128 KHz (SIRC)
• Slow external crystal oscillator 32 KHz (SXOSC)
Internal system clocks are generated from either PLL_PHI_0, FIRC, or FXOSC. There is
one clock selector which is used exclusively for system clock source selection. The
system clocks along with PLL_PHI_0, FIRC, FXOSC, SIRC, SXOSC, can be selected to
drive system peripherals depending on the configuration of the Auxillary Clock Selectors
in the Clock Generation Module (MC_CGM), and selectors based locally in the modules.
There are six Auxillary Clock Selectors which allow developers to drive peripherals with
a specific clock source (see Figure 9-1).
The MPC5746C has a Clock Monitor Unit (CMU) that is used to check the integrity of
the clocks making sure that their frequencies stay within necessary operating limits. If the
CMU detects an issue with the monitored clocks, an interrupt or system reset could be
generated (depending on FCCU configuration).
NOTE
The auxilary clock multiplexers (for example,
MC_CGM_ACn_SC[SELCTL]) should be programmed to
select the clock source before the corresponding module is
enabled.
9.2 System clock generation
The MPC5746C supports seven synchronous clock nodes to support Dynamic Frequency
Scaling (DFS). These groups can be classified into 3 categories:
• Fixed Frequency Group (F160, F80, F40, F20): This group will not scale down
during DFS operation. It implies all the modules will continue receiving the same
frequency (for example, PIT timers are operating at F40MHz and would not scale
down).
• Scalable Frequency Group (S160, S80, S40): This group will scale down during DFS
operation (for example, Z4 core is operating at S160 and would scale down as per
configuration in MC_CGM_SC_DCn registers.
• Flexible Group (FS80): This group should be configured to scale down along with
the Scalable group during Linear DFS and should be kept at a fixed frequency during
Non-Linear DFS.
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Chapter 9 Clocking Overview
Each module can have clocks coming from different groups. See Table 9-6 for peripheral
clocking.
160MHz(max)
MC_ME_<mode>_MC[SYSCLK]
(default = 0)
8-40 MHz
(FXOSC)
1
0
CLKIN
1
FMPLL
MC_CGM_AC5_SC[SELCTL]
(default = 0)
PHI0 (160MHz) 2
PHI1 (80MHz)
PCFS
(MC_CGM)
0
System Clock
Selector (MC_CGM)
16 MHz
(FIRC)
NOTE: PHI_1 is not used for system
clock generation.
F160
MC_CGM_SC_DC0[DIV]
(÷ 1...8)
Default = ÷1 = 000b
160MHz(max)
MC_CGM_SC_DC1[DIV]
(÷ 1...8)
Default = ÷2 = 001b
80MHz(max)
MC_CGM_SC_DC5[DIV]
(÷ 1...8)
Default = ÷2 = 001b
80MHz(max)
MC_CGM_SC_DC2[DIV]
(÷ 1...16)
Default = ÷4 = 0011b
40MHz(max)
MC_CGM_SC_DC3[DIV]
(÷ 4)
Default = ÷4 = 11b
40MHz(max)
MC_CGM_SC_DC4[DIV]
(÷ 2)
Default = ÷2 = 01b
80MHz(max)
MC_CGM_SC_DC6[DIV]
(÷ 8)
Default = ÷8 = 111b
20MHz(max)
S160
S80
FS80
S40
F40
F80
F20
Figure 9-1. System clock generation
NOTE
If System clock source is FIRC/FXOSC then only default
system clock divider configuration is supported.
9.3 Dynamic Frequency Scaling
9.3.1 Overview
Dynamic Frequency Scaling (DFS) enables the core and system frequency to be reduced
during RUN mode, while keeping frequency of key peripherals constant. This enables the
power consumption of the device to be temporarily reduced when processing needs are
low.
There is a considerable amount of power savings as frequency is reduced for all three
cores, AXBS, flash memory, SRAM, PBRIDGE and bus interface unit of modules.
During this mode, the frequency for timers like PIT, SWT, eMIOS, and baud rates for
modules like LIN, DSPI, are kept constant.
The clocks scaled during DFS are the following:
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Dynamic Frequency Scaling
• S40
• S80
• S160
• FS80
NOTE
All frequencies in this chapter are based on assumption that
PLL PHI0 is 160Mhz. If PLL PHI0 is at a different clock
frequency the system clock nodes will vary based on divider
configurations in MC_CGM_SC_DCn but divider ratio
restrictions defined in Table 9-1 will still remain intact.
There are two DFS modes supported:
• Linear DFS (LDFS)
• This mode is entered by writing MC
_CGM_SC_DIV_RC[SYS_DIV_RATIO_CHNG] = 0. In LDFS, the system
clock divider ratios will not change when the next system clock divider
configuration is updated.
• Non_Linear DFS (NLDFS)
• This mode is entered by writing MC
_CGM_SC_DIV_RC[SYS_DIV_RATIO_CHNG] = 1. In NLDFS, the system
clock divider ratios will change when the next system clock divider
configuration is updated.
The below table gives frequency scaling during all DFS modes.
NOTE
FS80 must not be configured to any frequency less than that of
F40 group.
Table 9-1. Dynamic Frequency scaling
Clock nodes
RUN - Full Power
Linear DFS
NLDFS80
NLDFS40
NLDFS20
F160
160
160
160
160
160
S160
160
80
80
40
20
S80
80
40
80
40
20
S40
40
20
20
20
10
F40
40
40
40
40
40
F80
80
80
80
80
80
FS80
80
40
80
80
80
F20
20
20
20
20
20
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All the modules which are clocked from a scalable frequency group will scale down in
both the modes (see System clock generation).
9.3.2 Linear DFS Configuration
In this mode, frequency is scaled down while keeping the ratio between master (for
example, FlexRay, DMA) and AXBS as same. For example, in full run mode Z2 is at
80 MHz and AXBS is at 160 MHz, thus ratio is 1:2. In Linear DFS mode Z2 can be
scaled down to 40 MHz and AXBS to 80 MHz, thus maintaining a 1:2 ratio.
Transitioning between frequencies occurs seamlessly, such that transactions can continue
without halting AXBS.
Following is the frequency configurations supported in Linear DFS (all frequencies are in
MHz).
Table 9-2. Linear DFS supported frequencies
System (Z4 core,
AXBS, SRAM, flash
memory)
Z2
eDMA
HSM
ENET
FlexRay
PBRIDGE
Case 1: Full RUN
160
80
80
80
80
80
80
Case 2: Linear DFS
80
40
40
40
—1
—2
40
1. Linear DFS feature not supported.
2. The Flexray can be used in the Linear DFS mode only when the FXOSC is selected as the Flexray PE clock source.
Suggested configuration sequence for Linear DFS
1. Configure MC_CGM_SC_DC0[DIV] = 01b, to scale down S160 group to generate
80 MHz
2. Configure MC_CGM_SC_DC1[DIV] = 0011b, to scale down S80 group to generate
40 MHz
3. Configure MC_CGM_SC_DC2[DIV] = 0111b, to scale down S40 group to generate
20 MHz
4. Configure MC_CGM_SC_DC5[DIV] = 011b, to scale down FS80 group to generate
40 MHz
5. Configure MC_CGM_SC_DIV_RC[SYS_DIV_RATIO_CHNG] = 0 to disable
HALT/ACK handshake with AXBS.
6. Configure MC_ME_PCTLn to disable ENET (MC_ME_PCTL15) to save dynamic
power.
7. Configure MC_CGM_DIV_UPD_TRIG any non-zero value.
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Dynamic Frequency Scaling
9.3.3 Non-Linear DFS Configuration
In this mode frequency is scaled down and also the ratio between master and AXBS can
be varied. For example, in full run mode ENET is at 80 MHz and AXBS is at 160 MHz,
thus ratio is 1:2. In Non-Linear DFS mode ENET can be maintained at 80 MHz and
AXBS scaled to 80 MHz, thus changing ratio to 1:1. It is required to put the AXBS into a
quiescent state such that on a DFS request all ongoing transactions at the AXBS slave are
completed and an acknowledgement is issued to the MC_CGM to change frequencies.
Following is the frequency configurations supported in Non-Linear DFS.
Table 9-3. Non-Linear DFS supported frequencies
System (Z4 core,
AXBS, SRAM,
flash memory)
Z2
eDMA
HSM
ENET
FlexRay
PBRIDGE
Case 1:Full RUN
160
80
80
80
80
80
80
Case 3: NLDFS80
80
80
80
40
80
80
80
Case 4: NLDFS40
40
40
80
20
80
80
80
Case 5: NLDFS20
20
20
80
10
80
80
80
Suggested configuration sequence for Non-Linear DFS
• Configure MC_CGM_SC_DC0[DIV] = 01b, to scale down S160 group to generate
80 MHz
• Configure MC_CGM_SC_DC2[DIV] = 0111b, to scale down S40 group to generate
20 MHz
• Configure AXBSx_PRSn to set the priorities as per application requirement. It is
suggested to provide highest priority for FlexRay.
• Configure MC_CGM_SC_DIV_RC[SYS_DIV_RATIO_CHNG] = 1 to enable
HALT/ACK handshake with AXBS. Configure MC_CGM_DIV_UPD_TRIG any
non-zero value.
If lowest frequency Non-Linear DFS is chosen, the restrictions are same as that of lowest
frequency DFS case.
NOTE
The modules working on FS80 group will not be scaled down
in all NLDFS modes.
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9.3.4 DFS Limitations
There are some frequency requirements mandated by the protocol which should be
considered while selecting DFS mode for an application.
Refer Peripheral Clock Restrictions for more details
Table 9-4. DFS Limitations
Mode
Limitation
NLDFS80
No restriction. All modules can operate well.
LDFS
Refer Peripheral Clock Restrictions
9.3.5 NLDFS Abort on Interrupt
When the software initiates NLDFS, the crossbar including the masters are halted before
the system frequency is dynamically switched. It may take a while for all masters to halt
together. However, the NLDFS can be aborted in between using following critical
interrupts.
• NMI to Z4 and Z2
• Critical interrupts to Z4 and Z2
• Machine check request to Z4 and Z2
• SWT0 Interrupt
• SWT1 Interrupt
• HSM_SWT interrupt
• Flexray FIFO interrupts such as, FR_GIFER[FAFAIF] or FR_GIFER[FAFBIF]
• MAC0 underrun interrupt, MAC 0 Transmit FIFO Underrun
The enabling and disabling of HALT abort feature can be controlled by
MC_CGM_SC_DIV_RC[HALT_ABORT_DIS], System Clock Divider Ratio Change
Register (MC_CGM_SC_DIV_RC)
9.4 Peripheral clock generation
9.4.1 Overview
Each module requires the following clocks to operate (see Figure 9-2):
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Peripheral clock generation
• HCLK – This is the AHB interface clock of modules which are master or slaves on
AXBS. This clock is gated in low power modes, or if the module is disabled and is
supported by MC_ME_PCTL configuration.
• Peripheral CLK – This clock is required by modules for internal state machines and
processing of data.
• BIU CLK – Bus interface unit clock. This clock is required for register read write
configurations. It is available only when a module is accessed for configurations and
else it is disabled. Some modules operate its bus interface unit on peripheral clock
and corresponding column is marked as '—' for these modules (see System Clock
Distribution for details).
• Memory CLK - Memory of the modules operate on this clock.
• Baud_CLK/Auxiliary CLK - This clock is provided to generate external interface
clock or if there is any special clock requirement
Memory clock
BIU clock
Peripheral clock
Module
HCLK
Baud clock/Auxiliary clock
Figure 9-2. General module clocking
9.4.2 Enabling/Disabling of peripherals and clock sources
Disabling of peripherals and clock sources: Software should take care that secondary
(auxiliary) clock sources selected for a peripheral are not disabled during any mode
transition preceding a mode transition to disable the peripheral. For Example: In
FlexCAN when FXOSC is selected for the CAN Engine Clock Source
(CAN_CTRL1[CLKSRC]), before disabling FlexCAN Peripheral Clock the user must
ensure FXOSC is enabled in the current mode prior to the target mode transition that will
disable the FlexCAN.
Enabling of peripherals and clock sources: Software should take care that secondary
(auxiliary) clock sources are enabled for the target mode before initiating the target mode
transition to enable the peripheral.
9.4.3 Communication interfaces
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9.4.3.1 FlexCAN clocking
The FlexCAN Protocol Engine clock (PE clock) has an option to be sourced from either
the F40 or the external oscillator (FXOSC). Clock selection is controlled by
CANx_CTRL1[CLKSRC]. Control host interface(CHI) clock of CAN1 to CAN7 is
sourced from FS80 group whereas, CAN0 has an option to be sourced from either
FXOSC or FS80 group.
NOTE
FlexCAN_1-7 CHI clock frequency should not be lower than
the PE clock when the system clock is dynamically updated.
FlexCAN0 CHI clock and PE clock can operate in 1:1
frequency ratio. There is an auxiliary mux selector added to
ensure seamless operation while entry-exit from LPU
subsystem. ReferFlexCAN0 Clocking
Software Guideline: If FXOSC is selected as the FlexCAN_n clock source,
MC_ME_PCTL[70:77] (corresponding to FlexCAN_0 through FlexCAN_7,
respectively) should be configured after MC_ME_GS[S_FXOSC] = 1. For example, if
FXOSC is the source for FlexCAN_0, then MC_ME_PCTL70 should be configured after
MC_ME_GS[S_FXOSC] = 1. This is required to ensure clock source is available before
module is enabled.
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Peripheral clock generation
FlexCAN[0]
FXOSC
CHI_CLK / BIU CLK
MC_CGM_AC9_SC
FS80
CAN0_CLK_PE
CAN0_CTRL1[CLKSRC]
FXOSC
F40
FlexCAN[1:7]
CHI_CLK / BIU CLK
FS80
CANx_CLK_PE
CANx_CTRL1[CLKSRC]
(x = 1 to 7)
FXOSC
F40
NOTE: The multiplexers for all FlexCAN modules are located outside of the module,
but are controlled by registers inside the FlexCAN modules.
Figure 9-3. FlexCAN Clock generation
9.4.3.2 FlexRay clocking
The FlexRay protocol clock can be sourced from either FS80 (non-FM PLL) or the
external oscillator (FXOSC). Clock selection is controlled by configuring the FlexRay
Module Configuration register FR_MCR[CLKSEL] field. Control host interface (CHI)
clock of FlexRay is sourced from FS80 group.
• When using the external oscillator clock, a 40 MHz crystal is required for proper
operation.
• When using FS80, the MC_CGM_SC_DC5 register must be configured to provide
80 MHz on FS80 for proper operation.
• The frequency of the FS80 source must be double the frequency of the XOSC source
(40 MHz) because the PLL has a less stable duty cycle.
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• The FlexRay module itself divides the FS80 frequency to provide a steady, 50% duty
cycle, 40 MHz clock internally.
• This internal FlexRay divider is driven automatically when FR_MCR[CLKSEL] is 1.
The user cannot change this internal divider or select it for the XOSC source.
NOTE
The FlexRay module used in the device has the StopWatch
functionality. The OS_tick is the input into the FlexRay module
and the source is from the STM and PIT channels.
FlexRay Module
FR_MCR[CLKSEL]
(default = 0)
FXOSC
FS80
0
FlexRay PE clock
1
FlexRay CHI clock
Figure 9-4. FlexRay clock generation
9.4.3.2.1
FlexRay OS tick selection
The following figure shows the OS tick selection configuration which is implemented at
the device level outside the FlexRay StopWatch interface (see the StopWatch function
section in the "FlexRay" chapter for details).
FR Start cycle
Start
32 bit counter
STM1_CMP0
sys_clk
Stop
STM2_CMP0
PIT_CH13
SIUL2_IMCR510[SSS]
For detailed description, see I/O Signal Description and Input Multiplexing Tables (excel
file) attached to this document.
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Peripheral clock generation
NOTE
Software Guideline: If FXOSC is selected as the FlexRay
clock source, MC_ME_PCTL28 needs to be configured after
MC_ME_GS[S_FXOSC] = 1.
9.4.3.3 LINFlexD clocking
LINFlexD requires bus interface unit clock for configurations and a baud clock.
LINFlexD belongs to fixed frequency group such that its baud rate remains constant
during DFS.
LINFlexD[0] BIU clock is from F20 group. It cannot belong to F80 group as maximum
frequency supported in LPU subsytem is 40 MHz. Refer LinFlexD Clocking
LINFlexD[0]
F20
BIU
LIN_CLK
F40
LINFlexD[1:17]
F40
BIU
F80
LIN_CLK
Figure 9-5. LINFLexD Clock generation
9.4.3.4 ENET clocking
ENET HCLK cannot be below 50 MHz to support MII and RMII modes. Either F40 or
the Ext_CLK clocks can be selected as the timer clock. The period of this clock should be
an integer value (for example, 25 ns if 40 MHz clock frequency is used).
NOTE
Ext_CLK is sourced from the TXD_CLK/RMII_CLK external
pad which is TXD_CLK in MII mode.
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ENET Module
ENET RMII/MII
TXD_CLK/RMII_CLK
F40
0
Ext_CLK
1
ENET0_TIMER
50 MHz (max)
MC_CGM_AC2_SC[SELCTL]
ENET1_TIMER
MAC0/1 and Switch Reg access CLK
F40
BIU
F80
Switch MAC0/1_SYS_CLK
GLOBAL CLK
TX_CLK_MAC0
RXD_CLK
F160
RX_CLK_MAC0
Switch_2*CLK
TX_CLK_1
TX_CLK_MAC1
RX_CLK_1
RX_CLK_MAC1
Figure 9-6. ENET Clock generation
9.4.3.5 SAI clocking
Figure 9-7 shows how the SAI master clock (MCLK) is generated via fractional clock
divider (FCD) . The input clock to the FCD is limited to 160 MHz. MCLK[2:0] can also
come as an input via external pins. Bit clock (BCLK) is half of MCLK and can be
generated internally by dividing MCLK or they can be input via external pin. BIU
operates at S40.
NOTE
BCLK should never be greater than BIU clock which is S40 as
it will lead to underrun or overflow of FIFO inside SAI.
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Peripheral clock generation
BIU_CLK0
00
FCLK_MCLK0 01
MCLK[1] 10
MCLK[2]
11
I2S0_MCR[MICS]
FMPLL _PHI_0
GND
FXOSC
MCLK[0]1
00
I2S0_RCR2[MSEL]]
I2S0_MDR[FRACT,DIVIDE]
BIU_CLK0
01
FCD
10
1
0
11
MCLK[1]1
1
11
0
MCLK_TX_SAI0
11
I2S0_TCR2[MSEL]]
BIU_CLK1
FCD
10
00
FCLK_MCLK0 01
MCLK[1] 10
MCLK[2]
I2S1_MCR[MICS]
I2S0_MCR[MOE]
I2S1_MDR[FRACT,DIVIDE]
00
01
MCLK_RX_SAI0
00
FCLK_MCLK1 01
MCLK[0] 10
MCLK[2]
MCLK_RX_SAI1
11
I2S1_MCR[MOE]
I2S1_RCR2[MSEL]]
BIU_CLK1
00
FCLK_MCLK1 01
MCLK[0] 10
MCLK[2]
MCLK_TX_SAI1
11
I2S2_MCR[MICS]
I2S2_MDR[FRACT,DIVIDE]
I2S1_TCR2[MSEL]]
00
01
MCLK[2]1
FCD
10
1
0
11
BIU_CLK2
00
FCLK_MCLK2
01
MCLK[0] 10
MCLK[1]
MCLK_RX_SAI2
11
I2S2_MCR[MOE]
I2S2_RCR2[MSEL]]
BIU_CLK2
00
FCLK_MCLK2
01
MCLK[0] 10
MCLK[1]
MCLK_TX_SAI2
11
1Driven by signals external to the MPC5746C
I2S2_TCR2[MSEL]]
Figure 9-7. SAI clock generation
9.4.3.6 DSPI/SPI clocking
There are four DSPI (DSPI_[0:3]) and four SPI (SPI_[0:3]) modules on the MPC5746C.
DSPI_[0:1] and SPI_[0,3] uses F40 for its baud rate clock, and DSPI_[2:3] and SPI_[1:2]
uses F80 for its baud rate clock as given in the following figure.
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DSPI[2:3]
DSPI[0:1]
DSPI Peripheral Clock
DSPI Peripheral Clock
S40
BIU
S40
BIU
F80
DSPI Baud Clock
F40
DSPI Baud Clock
SPI[3]
SPI[1:2]
SPI Peripheral Clock
SPI Peripheral Clock
S40
BIU
S40
BIU
F80
DSPI Baud Clock
F40
DSPI Baud Clock
SPI[0]
SPI Peripheral Clock
S40
BIU
DSPI Baud Clock
F40
FXOSC
MC_CGM_AC8_SC
Figure 9-8. DSPI/SPI clock generation
9.4.4 Timers Clock
9.4.4.1 RTC clocking
The RTC_CLK for the RTC-API is generated by selecting one of four clocks as shown in
Figure 9-9. If needed, the RTC_CLK can be divided for finer granularity (see RTC Block
Diagram).
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Peripheral clock generation
RTC-API
FXOSC
FIRC
40MHz(max)
SXOSC
RTC_CLK
Divided SIRC
RTC_RTCC[CLKSEL]
Figure 9-9. RTC Clock generation
NOTE
SIRC_DIV if configured for non zero value, will get reset on
any chip reset thus generating 128kHz clock frequency.
9.4.4.2 PIT-RTI clocking
The PIT_RTI contains 16 PIT channels and a single RTI channel. The PIT channels are
clocked from the system clock (F40). The clock source for the RTI is the FXOSC.
FXOSC
F40
RTI
PIT
Figure 9-10. PIT Clock generation
NOTE
Software Guideline: If FXOSC is selected as the RTI clock
source, MC_ME_PCTL91 needs to be configured after
MC_ME_GS[S_FXOSC] = 1. Also, the clock for RTI timers
needs to be enabled (PIT_MCR[MDIS_RTI] = 1) after
MC_ME_GS[S_FXOSC] = 1.
9.4.4.3 STM clocking
FS80 is selected as the source clock for all STM to allow a constant frequency of 80 MHz
while core frequency scales down from 160 MHz to 80 MHz during NLDFS.
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NOTE
STM counter should be enabled only after selecting
STM_2CLK_CR[CSL].
NOTE
If STM is configured in STOP/STANDBY/LPU modes,
FXOSC should be kept ON in target modes (RUNx/DRUN)
also, to exit properly
FS80
STM_Z4
BIU_clk
STM_0 Clock
Prescaler
FXOSC
STM0_2CLK_CR[CSL]
STM_Z2
FS80
BIU_clk
STM_2 Clock
Prescaler
FXOSC
STM2_2CLK_CR[CSL]
Figure 9-11. STM Clock generation
9.4.4.4 SWT clocking
SIRC is always enabled after reset such that the SWT receives the clock during the reset
sequence and avoids a timeout. If a timeout occurs, a destructive reset will be initiated
indicating flash memory initialization fails.
NOTE
SWT must be configured only if ME_GS[S_SIRCON] is 1.
NOTE
SIRC should always be kept ON (in DRUN/RUNx modes) if at
least one SWT is enabled to allow proper mode transitions.
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Peripheral clock generation
SWT0
SIRC
SWT1
SIRC
HSM_SWT
SIRC
Figure 9-12. SWT clock generation
9.4.5 ADC/BCTU/eMIOS clocking
The ADC clock source is FS80. The ADC can reduce the source clock to generate a
40 MHz clock of the correct tolerance. The ADC, BCTU, and eMIOS are in the same
80 MHz peripheral set to avoid clock domain crossing delays. These modules will not be
scaled down across NLDFS modes.
NOTE
The ADC meets the 1 μS conversion time with an 80 MHz
clock source. If the clock frequency is higher than 80 MHz, the
conversion accuracy is reduced. If a lower frequency is used,
conversion time will be longer, but accuracy is not affected.
The minimum ADC clock frequency is 1 MHz (see the
MPC5746C Data Sheet for timing details).
9.4.6 CLKOUT clocking
There are two external clock output pins on the device:
• CLKOUT_0
• CLKOUT_1
CLKOUT_0 clock is available only in RUN, DRUN and STOP modes. However,
CLKOUT_0 pin is available in all modes, including STANDBY and LPU modes.
Both CLKOUT_1 clock and CLKOUT_1 pin are available in all modes, including
STANDBY and LPU modes.
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CLKOUT_1 MUX and divider are in PD0.
CLKOUT_1_MUX
FXOSC divided 0000
FIRC divided
SXOSC
0001
0010
SIRC
0011
RTC_CLK
0100
LPU sys clk
0101
Z2 core clk
FXOSC_ANA_CLK1
FXOSC
0110
0111
1000
FIRC
SXOSC divided
1001
÷ 1...2048
CLKOUT_1
MC_CGM_CLKOUT1_DC0[DIV]
1010
SIRC divided
1011
CAN0_CHI_CLK
1100
CAN0_PE_CLK
1010
PLL_CLKOUT1
1110
Reserved
1111
MC_CGM_CLKOUT1_SC[SELCTL]
CLKOUT_0_MUX
FXOSC
FIRC
PLL_CLKOUT1
S160
RTC_CLK
PLL_CLKOUT2
SXOSC
SIRC
F40 CAN
HSM Core CLK
S40
F40
F80
FS80
0010
0011
0100
0101
0110
0111
Z4 CLK
F80 Flexray
0000
0001
1000
1001
÷ 1...32
CLKOUT_0
MC_CGM_AC6_DC0[DIV]
1010
1011
1100
1010
1110
1111
MC_CGM_AC6_SC[SELCTL]
1. FXOSC_ANA_CLK is an output of analog fast oscillator which is actually fed from XTAL on board.
This has same frequency as FXOSC.
Figure 9-13. CLKOUT clock generation
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MC_CGM registers
9.4.7 HSM clocking
The HSM Core works at a set frequency of half the system clock (S160). The clock
divider for random number generator (TRNG) is located outside the HSM in the CGL, is
controlled by the HSM. The HSM contains an internal PIT/RTI block, which uses the
FIRC as its clock source. The HSM also contains an internal clock monitor on its input
clock.
HSM
S160
FIRC
÷2
HSM_EN
÷ 1...64
HSM_EN
HSM80
HSM_CORE/XBAR/SBI/
INTC/PRAMC
Cache/TAG/RAM
C3
C3_TRNG CH CLK
HSM_PIT CH CLK
HSM_CMU
TRNG divider control
HSM_RTI CH CLK
FIRC
Figure 9-14. HSM clocking
9.4.8 LPU clocking
It is possible to run the Low Power Unit (LPU) from either the FXOSC or FIRC. These
frequencies can be reduced using dividers before they are routed to the peripherals in the
low power domain (for example, LINFlexD, SPI, ADC, and so on).
NOTE
See the Clocking section in the LPU chapter for clocking
details during low power operation.
9.5 MC_CGM registers
The relationship between the output clocks and the MC_CGM registers is shown in
Figure 9-1.
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NOTE
See Clock Generation Module (MC_CGM) for specifics on
register implementation.
9.6 Built-In Self-Test clocking
The device supports user Built-In Self-Test (MBIST ) as part of the functional safety
concept. The configuration is controlled via the STCU2 module. MBIST can run at start
up (before cores exit reset), or initiated by application during run time. It is possible to
run Built-In Self-Test from the FIRC or PLL_PHI1 clock (limited to 40 MHz). At start
up, the selection of the BIST clock is configured in the DCF record, STCU_PLL_CFG
(default is the FIRC). As cores are not running during MBIST, the PLL setup is
controlled with hardware.
NOTE
The STCU2 registers read/write is done on S40 clock.
9.7 System Clock Distribution
The maximum frequency of operation for the device system level clocks is shown in
Table 9-5 and Table 9-6.
The AXBS are clocked from the S160 group. There is no mode where any of the masters
or slaves can work at a frequency higher than the AXBS frequency.
The PBRIDGE clock cannot be scaled below 40 MHz. It is clocked from FS80 group,
there is no mode where any of the slaves can work at a frequency higher than the
PBRIDGE frequency. As there are modules which have their BIU clocked from F40
group (except for PIT and LINFlexD), this limits PBRIDGE to 40 MHz.
Dividers corresponding to fixed frequency groups (for example, F20, F40, F80, F160)
should not be modified in any DFS mode.
NOTE
The user is responsible to verify that these values are not
exceeded.
In Table 9-5 and Table 9-6 the Peripheral clock will also serve
the purpose of BIU clock for the modules in which BIU clock is
not defined
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System Clock Distribution
Table 9-5. Maximum clock frequencies - AXBS master/slave
Module
HCLK
Peripheral
CLK
BIU
Memory
CLK
BAUD_CLK/Auxiliary CLK
Z4
S160
—
—
—
—
Z2
S80
—
—
—
—
DMA
FS80
—
—
FS80
—
HSM
HSM80
HSM80
HSM80
—
See HSM clock diagram for details.
FlexRay
FS80
ENET
F80
F80
F40
F80
Input clock from PAD
PBRIDGE_A, PBRIDGE_B
FS80
FS80
—
—
—
PFLASH_CTRL
S160
—
S80
S160
—
PRAM_CTRL
S160
S80
S80
S160
—
NOTE
In this document, few module refer to ipg_clk as the system
clock. Please refer the following table to see the clock mapping
for each module.
Table 9-6. Maximum clock frequencies - Peripherals
Module
HCLK
Peripheral
CLK
BIU
Memory
CLK
BAUD_CLK/Auxiliary CLK
SSCM
Flash
—
S40
S40
—
—
—
S160
S40
—
—
MC_ME
—
S40
S40
—
—
MC_RGM
—
FIRC
(16 MHz)
S40
—
—
MC_PCU
—
FIRC
(16 MHz)
S40
—
—
MC_CGM
—
—
S40
—
—
FIRC
—
S40
S40
—
—
SIRC
—
S40
S40
—
—
FXOSC
—
S40
S40
—
—
SXOSC
—
S40
S40
—
—
PLL
—
S40
S40
—
—
STCU
—
S40
—
—
—
WKPU
—
S40
S40
—
—
CMU
—
S40
—
—
—
PASS
—
S40
S40
—
—
TDM
—
S40
—
—
—
FCCU
—
S40
—
—
—
PMC_DIG
—
S40
—
—
LINFlex_1 to LINFlex_17
—
F40
—
F80
—
Table continues on the next page...
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Table 9-6. Maximum clock frequencies - Peripherals (continued)
Module
HCLK
Peripheral
CLK
BIU
Memory
CLK
BAUD_CLK/Auxiliary CLK
LINFlex_0
—
F20
—
—
F40
DSPI_2, DSPI_3
—
S40
S40
—
F80
DSPI_0, DSPI_1
—
S40
S40
—
F40
SPI_0
—
S40
S40
—
F40
SPI_1, SPI_2
—
S40
S40
—
F80
SPI_3
—
S40
S40
—
F40
ADC_0,ADC_1
—
FS80
—
—
—
BCTU
—
FS80
FS80
—
—
eMIOS
—
FS80
FS80
—
—
IIC
—
F40
F40
—
—
FlexCAN
—
FS80
FS80
FS80
Refer module clock diagram for details
SAI
—
S40
S40
—
Refer module clock diagram for details
CRC
—
S40
—
—
—
RTC-API
—
—
S40
—
—
PIT-RTI
—
F40
F40
—
—
SWT0
—
—
S40
—
—
SWT1, SWT_HSM
—
—
S80
—
—
STM
—
—
FS80
—
—
DMAMUX_0, DMAMUX_1
—
FS80
FS80
—
—
NPC
—
—
S80
—
—
JTAGC
—
TCK (ext pin)
S40
—
—
—
—
CJTAG
—
TCK (ext pin)
S40
CMP_0 to CMP_3
—
S40
S40
MEMU_0
—
—
F80
—
—
MEMU_1
—
—
FS80
—
—
SIUL
—
F40
F40
—
—
LPU_CTL
—
FIRC
S40
—
—
INTC
—
—
FS80
—
—
SRAM (RAM256K)
—
—
S160
—
—
XBAR_LPU
—
—
S160
—
—
—
9.7.1 JTAG Frequencies
The following table shows the maximum frequencies of the JTAG interface.
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Default clock configuration
Table 9-7. JTAG Frequencies
Configuration
System Clock
configured to 160 MHz
e200z4 Max Internal
JTAG Frequency
40 MHz
e200z2 Max Internal
JTAG Frequency
40 MHz
Maximum External
JTAG Frequency
(TCK/TCK_ALT)
16 MHz
Notes
JTAG usable at 1/4
CPU frequency
9.7.2 Peripheral Clock Restrictions
There are some frequency requirements mandated by the protocol which should be
considered while selecting DFS mode for an application.
• ENET AHB master clock interface should be greater than 50 MHz to support MII
and RMII mode. ENET is sourced from clock node F80.
• ENET timer clock period should always be an integer. It is sourced from clock node
F40 or FXOSC.
• BCLK which is bit clock of SAI and half of audio master clock should never be
greater than BIU clock which is S40 as it will lead to underrun or overflow of FIFO
inside SAI
• ADC conversion rate will drop as its frequency scales down. It is sourced from clock
node FS80.
• FlexCAN protocol engine clock should always be less than its control host interface
clock if MC_CGM_AC9_SC[SELCTL] is 0x0
• Flexray PE clock always need 80 Mhz clock (if FMPLL is clock source) or 40 Mhz
clock (if FXOSC is clock source) to support 10/8/5/2.5 Mbit/s flexray data rates.
9.8 Default clock configuration
• POWER UP:After power is applied to the MPC5746C, the FIRC is the default clock
for the system clock, and all clock sources and clock control blocks are reset to their
default state. See clocking diagrams for default settings of dividers.
• STANDBY/LPU EXIT: System clock is based on configuration done in
ME_DRUN_MC before LPU or STANDBY mode is requested. PLL can be selected
as system source clock for faster low power exit time. Refer Accelerated Low Power
Exit
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9.9 Clock sources
This section provides the overview of the various clock sources.
9.9.1 PLL
The chip has a frequency modulated PLL with two outputs (PHI_0 and PHI_1). The
separate system and peripheral clocks are provided with external dividers (see Figure 9-1
and Figure 9-15).
MC_CGM_AC5_SC[SELCTL]
(default = 0)
EXTAL
XTAL
8-40 MHz
(FXOSC)
1
0
FMPLL
Pre-Divider
(PREDIV)
Phase
Detector
16 MHz
(FIRC)
Charge
Pump
Low Pass
Filter
VCO
Out Divider
Output Enable
(RFDPHI)
(ENPHI)
PHI_0
Out Divider
Output Enable
PHI_1
(RFDPHI1)
Divider
(ENPHI1)
(MFD)
Lock
RFDPHI1
RFDPHI
PREDIV
MFD LOCK
Control/Status
Registers
PLLDIG
Figure 9-15. PLL block diagram
9.9.1.1 PLL input clocks
The clock source for the PLL can be either the external oscillator (FXOSC) or the
16 MHz internal oscillator (FIRC). The clock source is selected by configuring the
MC_CGM_AC5_SC[SELCTL]. The input frequency range of the PLL is 8 – 40 MHz.
The default input source for the PLL is the FIRC (MC_CGM_AC5_SC[SELCTL] = 0),
but the FXOSC should be selected for best system clock accuracy
(MC_CGM_AC5_SC[SELCTL] = 1).
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Clock sources
9.9.1.2 PLL output clocks
The PLL has two output clocks:
• PHI_0
• PHI_1
PHI_0 is the primary output and is used to drive the system clock. It has a maximum
frequency of 160 MHz. PHI_1 is the secondary output clock and has a maximum output
frequency of 80 MHz.
NOTE
The PLL multiplication factor and output divider is software
programmable.
9.9.1.3 PLL register interface
This device has a single digital interface for the PLL. The digital interface provides
register control of all features of the PLL. Details are provided in the PLLDIG memory
map and register definition section.
9.9.1.4 PLLDIG register reset values
All reset values for the PLLDIG registers that are device specific are shown in the
following table. All other register reset values are shown in the PLL Digital Interface
chapter.
Table 9-8. PLLDIG reset values
Register
Reset Value
PLL Calibration Register 3 (PLLDIG_PLLCAL3)
0000_0062h
PLLDIG PLL Control Register (PLLDIG_PLLCR)
0000_0400h
PLLDIG PLL Status Register (PLLDIG_PLLSR)
0000_0000h
PLLDIG PLL Divide Register (PLLDIG_PLLDV)
0C06_0018h
9.9.1.5 PLLDIG initialization information
Coming out of reset the PLL is disabled per the DRUN mode configuration register,
MC_ME_DRUN_MC.
1. Configure PLL and related modules.
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a. With PLL disabled, program PLL clock source in
MC_CGM_AC5_SC[SELCTL]. Default is MC_CGM_AC5_SC[SELCTL] = 0
which selects the FIRC.
b. Program PLLDV[MFD] and PLLDV[RFDPHI].
c. If required, program the PLLFM register with the desired frequency modulation
parameters and enable FM modulation, PLLFM[SSCGBYP] = 0. The PLLFM
register must not be written after PLL enabled and operating in normal mode.
2. Turn on PLL.
a. Configure a mode configuration for turning on PLL, and keeping XOSC on. In a
mode configuration register (for example, MC_ME_DRUN_MC), initialize
MC_ME_<mode>_MC[XOSCON] = 1, MC_ME_<mode>_MC_PLLON] = 1. If
desired, also set MC_ME_<mode>_MC[SYSCLK] needs to be initialized
accordingly for this new mode configuration to use PLL as the sysclk (for
example, MC_ME_RUN0_MC[SYSCLK] = 2 for PLL_PH0).
b. Enter that mode by two writes to MC_ME_MCTL register. First write should
include the new mode and the key (use a single 32-bit write). The second write
should include the same target mode but with the key inverted (again using a
single 32-bit write). This is required even if entering the same mode.
3. Wait for the mode transition to complete.
a. Wait for the mode transition to complete by polling MC_MC_GS[MTRANS] or
enabling an interrupt for flag MC_ME_IS[I_MTC]. A timer, even if it is the
watchdog, should be used to make sure the mode transition completes. Mode
transition will NOT complete until:
• XOSC counter expires (if the new mode configuration changes XOSCON to
1), and
• PLL is locked (if the new mode configuration changes
MC_ME_<mode>_MC[PLLON] = 1)
b. Confirm the desired target mode was entered by checking the status of
MC_ME_GS[S_CURRENT_MODE].
NOTE
See the "Mode Entry Module (MC_ME)" chapter in this
Reference Manual more details.
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Clock sources
9.9.2 Fast External Oscillator (FXOSC)
The external oscillator allows a crystal, or external clock, to be used as the reference for
the MPC5746C. The input frequency range for the FXOSC is 8 – 40 MHz. The FXOSC
clock source can be selected as the clock source for any operating mode (for example,
DRUN, SAFE, and RUN[0:3]). The current operating mode is selected by configuring
MC_ME_MCTL[TARGET_MODE]. Each of these operating modes can have the
FXOSC as the clock source as selected in MC_ME_<mode>_MC for the corresponding
operating mode. The FXOSC is the clock source for the RTI.
See Fast OSC Digital Interface chapter for details.
The Figure 9-16 shows the block diagram for FXOSC clock configuration.
FXOSC_ANA_CLK
FXOSC
(Digital)
FXOSC
(Analog)
FXOSC_ANA_CLK
DIV
FXOSC_DIV_CLK
FXOSC_CLK
Figure 9-16. FXOSC Clock Configuration
9.9.2.1 FXOSC register reset values
All reset values for the FXOSC registers that are device specific are shown in the
following table.
Table 9-9. FXOSC reset values
Register
Reset Value
FXOSC Control Register (FXOSC_CTL)
4030_0000h
NOTE
Reset value for I_OSC field depends on the DCF record for this
field.
9.9.3 Slow external oscillator (SXOSC)
The SXOSC oscillator provides a 32 KHz clock with control and status registers
accessible for application use (see Slow external oscillator for details).
The Figure 9-17 shows the block diagram for SXOSC clock configuration.
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SXOSC
(Digital)
SXOSC_DIV_CLK
SXOSC
(Analog)
DIV
SXOSC_CLK
Figure 9-17. SXOSC Clock Configuration
9.9.3.1 SXOSC register reset values
All reset values for the SXOSC registers that are device specific are shown in the
following table. All other register reset values are shown in the SXOSC chapter.
Table 9-10. FXOSC reset values
Register
Reset Value
SXOSC Control Register (SXOSC_CTL)
0040_0000h
9.9.4 16 MHz internal RC oscillator (FIRC)
The MPC5746C has a 16 MHz internal RC oscillator (FIRC) that is always enabled in
RUN modes, and can be used as the clock source for the PLL. It is the clock source for
the MC_RGM, FCCU, RTC, and SIUL input filters, and can also be used as a clock
source for the ADCs and system clock. The FIRC is the default system clock after reset.
The register interface is used for user trimming of the oscillator (see Internal 16 MHz RC
Oscillator for details).
The Figure 9-18 shows the block diagram for FIRC clock configuration.
FIRC
(Digital)
FIRC
(Analog)
DIV
FIRC_DIV_CLK
FIRC_CLK
Figure 9-18. FIRC Clock Configuration
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Clock sources
9.9.4.1 FIRC register reset values
The reset value of the FIRC Control register (FIRC_CTL) is device-specific and is shown
in the following table.
Table 9-11. FIRC reset values
Register
Reset Value
FIRC Control Register (FIRC_CTL)
00nn_0011h
NOTE
Bits 10-15 are trim bits, with values determined during factory
test to ensure the most accurate clock timing. To maintain
accurate timing, these bits should never be written by
application software.
9.9.5 128 kHz internal RC (SIRC)
This internal RC oscillator provides the 128 kHz clock with high accuracy, low power,
fast stabilization, and fast recovery (see Internal 128 kHz RC oscillator chapter for
details).
The Figure 9-19 shows the block diagram for SIRC clock configuration.
SIRC
(Digital)
SIRC
(Analog)
DIV
SIRC_DIV_CLK
SIRC_CLK
Figure 9-19. SIRC Clock Configuration
9.9.5.1 SIRC register reset values
The reset value of the SIRC Control register (SIRC_CTL) is device-specific and is shown
in the following table.
Table 9-12. SIRC reset values
Register
Reset Value
SIRC Control Register (SIRC_CTL)
00nn_0011h
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NOTE
Bits 8-15 are trim bits, with values determined during factory
test to ensure the most accurate clock timing. To maintain
accurate timing, these bits should never be written by
application software.
9.10 Clock monitoring
The device supports clock monitoring of PLL and FXOSC clock. FIRC is used as
reference clock (see Clock Monitor Unit (CMU) and CMU configuration for details).
9.10.1 CMU configuration
This section explains the CMU configuration.
Figure 9-20 shows the block diagram for the CMU on the MPC5746C.
CMU_CSR[CKSEL1]
CLKMT1 (SIRC)
01
CLKMT2 (SXOSC)
10
CLKMT0_RMN (FIRC)
00,11
CMU_MDR
Frequency Meter
CMU_FDR
CLKMN0_RMT (FXOSC)
CLKMN0_RMT Supervisor
OLR
fCLKMN0_RMT < fCLKMT0_RMN ÷ 2RCDIV
CLKMN0_RMT_ACTIVE
(from MC_ME)
CLKMN1 Supervisor
Fixed
Prescaler
÷4
CLKMN1 (PLL_PHI_0)
(monitored clock)
CMU_HREF
fCLKMN1 > hfref, or
fCLKMN1 < fCLKMT0_RMN ÷ 4
fCLKMN1 < lfref
FHH
FLL
CMU_LFREF
CLKMN1_ACTIVE
(from MC_ME)
Figure 9-20. CMU block diagram
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Clock monitoring
9.10.1.1 Clock input sources
The following table shows the clocks that are monitored by the CMU. These signals are
connected internally on the chip, but are not accessible via pins on the boundary of the
device. FIRC is the reference clock for clock monitor.
Table 9-13. Clock input sources
Clock module
CMU
Monitored clock
FXOSC, FIRC
9.10.1.2 PLL Monitor
Software can program an upper and lower limit for the expected PLL PHI_0 output clock
frequency. If the monitor is enabled, and the measured frequency is above or below the
limits, a flag bit is set in a status register. This will lead to FCCU_NCF[32] fault being
set when the flag bit is set. The default condition of the clock monitor is disabled
(CMU_CSR[CME] = 0). The FIRC is used as the reference clock for the monitor
(CLKMT0_RMN, and CMU_CSR[CKSEL1] = 00b or CMU_CSR[CKSEL1] = 11b).
9.10.1.3 FXOSC monitor
The frequency of the FXOSC is compared to a minimum limit as configured in the CMU.
If the measured FXOSC frequency is below the limit, a flag bit is set in a status register
(CMU_ISR[OLRI]). The OLR signal from the CMU is one of the functional reset sources
of MC_RGM, and an interrupt could be generated (depending on MC_RGM
configuration, see 'Functional' Event Reset DisableAlternate Request Status Register
(MC_RGM_FEAR)). It is not recommended to configure OLR signal from CMU as
interrupt if FXOSC is selected as system clock.
If CMU_ISR[OLRI] is set, then status in CMU_ISR and in RGM_FES would be cleared
by the software routine. However on such a condition, till the time FXOSC is not
corrected, the CMU_ISR[OLRI] would not recur again. Hence the software should
ensure that FXOSC is corrected by polling of MC_ME_GS[FXOSC_ON]. Also, the
software should not attempt any mode transition until ME_GS[FXOSC_ON] is set.
Otherwise the mode transition would hang.
OLR will not be captured in STANDBY mode as CMU is power gated. When MCU is in
Standby mode and counters are working on FXOSC clock and FXOSC is running slow
then expected wake-up can be delayed or prevented without notification. For example, if
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Chapter 9 Clocking Overview
crystal clock dies during STANDBY mode and crystal clock is configured to be ON in
target DRUN mode, then mode transition to DRUN will not complete. However SWT
can be kept running on SIRC and can generate wake-up on timeout to protect against
such cases when FXOSC is not functioning correctly. Additionally, external wakeups can
also always cause a low power exit.
NOTE
The FXOSC monitor is always enabled when the FXOSC and
FIRC are valid (see field descriptions MC_ME_GS[S_FXOSC]
and MC_ME_GS[S_FIRCON] in the Global Status Register
(MC_ME_GS)).
9.10.1.4 FIRC monitor
The frequency of the 16 MHz FIRC (as well as SIRC and SXOSC) can be calibrated with
the CMU using the FXOSC as a reference (CLKMN0_RMT (FXOSC)). This allows
application trimming of the FIRC frequency. The application specifies the duration of the
measurement period in units of FIRC clock periods. The clock monitor provides in a
register the number of references clocks counted during the measurement period, which
can be used to calculate the actual FIRC frequency (see Frequency meter for details).
9.10.1.5 System Clock Monitors
Clock monitoring at the device level is not required for the HSM, as it contains its own
internal monitor.
9.10.1.6 CMU register reset values
All reset values for the CMU registers that are device specific are shown in the following
table. All other register reset values are shown in the CMUchapter.
Table 9-14. CMU reset values
Register
Reset Value
CMU Control Status Register (CMU_CSR)
0000_0006h
CMU Interrupt Status Register (CMU_ISR)
0000_0000h
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Loss of system clock behavior
9.11 Loss of system clock behavior
This device has built-in mechanisms for detecting loss of the oscillator or PLL clocks,
and provides several options for reaction to a loss of clock in the application. See Figure
9-21.
9.11.1 Loss of PLL lock/FXOSC clock
As shown in Figure 9-21, each loss of lock signal from the PLL and the FXOSC failure
signals are monitored by the FCCU. The FCCU can be programmed to generate a short or
long reset sequence when a clock failure occurs, or simply to generate an interrupt. By
default, FCCU is configured to generate Long reset sequence when a clock failure
occurs.There is no automatic system clock switch, and the user is required to program the
switch through the Mode Entry module (MC_ME).
If a long reset is selected the PLL, FXOSC, MC_ME, and MC_CGM are reset to their
default states, and the system clock is switched to the FIRC. If a short reset is selected,
the clock configuration is maintained, but again, the PLL backup clock is the only
available clock to clock the system through an MC_ME mode switch.
NOTE
If PLL lock is lost and PLL clock dies immediately, FCCU will
generate reset but status will not be captured as its BIU_CLK
was not available. This can be debugged if MC_RGM_FES
indicates FCCU as source of reset and no status reported in
FCCU.
NOTE
If FXOSC failure happens, FXOSC registers will reset to its
default state. It is recommended to check S_FXOSC bit of
Global Status Register (MC_ME_GS) before using FXOSC
clock source again.
9.11.2 Loss of FIRC clock
The frequency of the FIRC clock is monitored by the frequency meter in CMU. There is
no automated trigger of an FCCU error condition if the FIRC fails. Since the FIRC is the
boot and backup clock, a failure is a catastrophic failure.
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ME
loss of lock
long reset
FCCU
8 - 40 MHz
External
Oscillator
(FXOSC)
FXOSC failure
short reset
CGM
XOSC
FMPLL
PLL
Chapter 9 Clocking Overview
RGM
System Reset
interrupt requests
INTC
CMU
16 MHz RC
Oscillator
(FIRC)
Figure 9-21. Loss of clock logic
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Loss of system clock behavior
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Chapter 10
Embedded Memories
10.1 Overview
The embedded memory architecture for devices includes:
• Onboard SRAM, including system SRAM
• Onboard system error correction code (ECC) flash memory
• End-to-end ECC (e2eECC) error detection and correction
• Built-in flash memory security features including censorship and a programmable
Hardware Security Module (HSM)
• Embedded memories in the peripherals1 such as, FlexCAN, eDMA, FlexRay, and
ENET.
10.2 System SRAM
MPC5746C devices include 512 KB of general-purpose on-chip ECC SRAM,
configurable for either zero- or one-wait state read operation latency.
For power-sensitive applications it is important to note which ranges of SRAM are
available in each device run mode. See Table 10-1 for overview of SRAM run mode
availability. See the Power Management chapter Introduction for details.
Table 10-1. SRAM run modes
Start Address
End Address
Allocated Size [KB]
Run Mode(s)
0x40000000
0x40001FFF
8 (STANDBY)
All
0x40002000
0x4000FFFF
56
RUN, STOP. Optionally
STANDBY, LPU 1
0x40010000
0x4001FFFF
64
RUN, STOP. Optionally
STANDBY, LPU1
Table continues on the next page...
1.
Refer to the respective module chapter for details.
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System SRAM
Table 10-1. SRAM run modes (continued)
Start Address
End Address
Allocated Size [KB]
Run Mode(s)
0x40020000
0x4003FFFF
128
RUN, STOP. Optionally
STANDBY, LPU1
0x40040000
0x4007FFFF
256
RUN, STOP
1. Can be independently configured to be available during STANDBY or LPU modes.
NOTE
It is recommended to use SMPU to protect the SRAM cuts
which one intends to put in SLEEP mode using the GPR Sleep
Memory register.
10.2.1 SRAM Controller (PRAMC)
Each of the microcontroller's 2 banks of system SRAM has a dedicated Platform RAM
Controller (PRAMC) module. The modules appear in the Peripheral Bridge A memory
map as:
• PRAMC_0
• PRAMC_1
Each PRAMC module controls access to its associated SRAM by bus masters.
• PRAMC_0 corresponds to SRAM address space 0x4000_0000 to 0x4003_FFFF.
• PRAMC_1 corresponds to SRAM address space 0x4004_0000 to 0x4007_FFFF.
Additionally, the PRAMC_0 module is integrated with the flash controller (PFLASH)
module to provide overlay SRAM support.
NOTE
1. PRAMC configuration settings are not global, i.e., each
PRAMC module's settings affect only the SRAM array
associated with that module.
2. Each SRAM array can be configured for either zero- or
one-wait state read operation latency via settings in its
associated PRAMC module's PFCR1 register.
3. If the system frequency is greater than 80 MHz, then the
PRAMCx_PRCR1[FT_DIS] field should be set to 1.
4. See the RAM controller chapter for details on configuring
the SRAM controller.
6. See System memory map for the MPC5746C SRAM map.
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10.2.1.1 SRAM controller (PRAMC) registers
Not all of the PRAMC register fields shown in the RAM Controller (PRAMC) chapter
are applicable to all PRAMC modules. The following sections show the applicable
register fields for each PRAMC module.
10.2.1.1.1
PRAMC_0 valid control register bits
Figure 10-1. PRAMC_0 register definitions
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
W
PRAMC_0_PRCR1
R
0
W
10.2.1.1.2
P1_ P0_
BO_ BO_
DIS DIS
PRI
0
FT_
DIS
PRAMC_1 valid control register bits
Figure 10-2. PRAMC_1 register definitions
Name
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
W
PRAMC_1_PRCR1
R
0
W
P0_
BO_
DIS
0
FT_
DIS
10.2.2 Overlay SRAM
The MPC5746C includes the capability of mapping a portion of system SRAM over
specific regions of on-chip flash memory so that any access to an overlaid flash address is
routed to the overlay SRAM instead. This enables the calibration of constant data without
requiring additional external RAMs and calibration memory interfaces.
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Flash memory
Note
Overlay SRAM is normally used for system development
purposes only. Execution from overlay RAM remapped over
Flash can be enabled or disabled by use of PFCRCR[IRMEM].
The overlay function is implemented using registers in the flash memory controller.
1. Using PFlash Calibration Region Descriptors (PFCRDn) define one or more (up to 8)
overlay regions.
2. Enable individual regions using the appropriate bits in the PFLASH Remap
Descriptor Enable Register (PFDCRDE).
3. Enable overlay using the PFCRCR[GRMEN] field.
NOTE
On the microcontroller, the only overlay RAM target available
is system RAM array0 (0x40000000 – 0x4003FFFF). There are
no restrictions within that range.
See PFlash calibration remap support for details on memory overlay (remapping).
10.3 Flash memory
Flash memory on MPC5746C devices consists of a flash memory controller and a flash
memory array module. The flash controller provides flash configuration and control
functions and manages the interface between the flash memory array and the device
crossbar switch. The following figure shows the memory architecture.
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XBAR
64
64
64
Flash M emor y Controller
4-Entry, 2-Way Mini-Cache
WAY0
WAY1
set0
set1
set2
set3
256 Read
64 Write
3 MB Flash Memory Array
Figure 10-3. MPC5746C flash memory block diagram
The remaining sections give the functional details of the flash controller and flash array,
followed by the memory maps.
10.3.1 Flash memory controller
The MPC5746C flash memory controller acts as an interface between the system bus and
the flash memory array and serves as the interface to the on-chip system SRAM for
calibration remapping.
The flash memory controller contains a four-entry, two-way set-associative mini-cache
that delivers flash read data with a zero-wait state response on lines that reside in the
cache. Each entry contains one flash page, a 32-byte memory value. Read requests that
miss the cache generate the needed flash memory array access.
The flash memory controller contains configuration registers that manage flash
functionality such as read buffering in the mini-cache, access control, calibration RAM
overlay remapping, and read wait state management of the flash memory.
See Flash memory controller for details.
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Flash memory
NOTE
PFLASH_PFCR1[APC] and PFLASH_PFCR1[RWSC] field
values needs to be updated while read accesses to flash are
stopped, that is, the software code which updates the
PFLASH_PFCR1[APC] and PFLASH_PFCR1[RWSC] fields
must be executed from RAM.
High clock speeds require the PFLASH_PFCR1[RWSC] field
setting to a non-zero value to insert one or more wait states into
flash accesses. For more information, refer MPC5746C data
sheet. Operating with RWSC and APC settings outside of those
specified in the data sheet is not supported and may result in
corrupted read data.
10.3.2 Flash memory array
MPC5746C devices include a single 3 MB flash memory array, referred to as "main
space," plus an independent 16 KB block of one-time-programmable (OTP) flash
memory included to support systems that require non-volatile memory for security
features or system initialization information. The independent 16 KB block is referred to
as "UTEST space."
Reads of the embedded flash memory return a 256-bit page of data that may be buffered
in the mini-cache in the flash memory controller. Programming of the flash may be done
by double word (64-bits), page (256-bits), or quad-page (1024-bits). Flash memory is
erased on a block by block basis.
NOTE
Entry to FLASH low power mode while a program/erase
operation is ongoing should be prohibited, or this can result in
unpredictable behavior.
10.3.2.1 Features
• Flash segmentation
• Two 16 KB, four 32 KB, and two 64 KB, and ten 256 KB blocks provided for
third party code
• Eight 16 KB provided for boot code EEPROM emulation
• Two 64 KB and one 16 KB blocks provided for secure code
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• Two 16 KB blocks provided for secure data
• Support for reading-while-writing when the accesses are to different partitions
• Flash memory protection: write protection and OTP function available for each block
• Test and initialization data stored in a non-volatile 16 KB OTP UTest block
• ECC with double bit detection, single bit correction
• Erase suspend, program suspend, and erase-suspended program all supported
10.3.3 Flash organization
The embedded flash memory consists of blocks from 16 KB to 256 KB, divided into
partitions that determine locations for valid read-while-write (RWW) operations. While
the embedded flash memory is performing a "write" (program or erase) to a given
partition, it can simultaneously read from any other partition.
• For program operations, only the address specified by an interlock write determines
the partition being written (block locking and block select registers do not determine
the RWW partitions being written).
• For erase operations, only blocks that are selected and unlocked determine the RWW
partitions being written.
The following figure shows the flash block segmentation and read-while-write
partitioning for devices.
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Flash memory
Read Partition 0
Read Partition 1
16 KB UTest
(0x0040_0000 - 0x0040_3FFF)
16KB HSM code flash
(0x00F8_C000 - 0x00F8_FFFF)
64 KB HSM code block 2
(0x0061_0000 - 0x0061_FFFF)
32 KB code flash
(0x00FC_0000 - 0x00FC_7FFF)
16 KB BAF
(0x0040_4000 - 0x0040_7FFF)
64 KB HSM code block 3
32 KB code flash
(0x00FD_0000 - 0x00FD_7FFF)
32 KB code flash
(0x00FD_8000 - 0x00FD_FFFF)
64 KB code flash
(0x00FE_0000 - 0x00FE_FFFF)
(0x00FF_0000 - 0x00FF_FFFF)
Read Partition 2
Read Partition 3
(0x00F9_0000 - 0x00F9_3FFF)
16 KB code flash
(0x00F9_4000 - 0x00F9_7FFF)
16 KB code flash
(0x00F9_8000 - 0x00F9_BFFF)
16 KB code flash
(0x00F9_C000 - 0x00F9_FFFF)
16 KB code flash
(0x00FA_0000 - 0x00FA_3FFF)
16 KB code flash
(0x00FA_4000 - 0x00FA_7FFF)
16 KB code flash
(0x00FA_8000 - 0x00FA_BFFF)
16 KB code flash
Flexible partitions
for boot and EEPROM
(0x00FA_C000 - 0x00FA_FFFF)
Read Partition 4
Read Partition 5
16 KB HSM data block 1
(0x00F8_0000 - 0x00F8_3FFF)
(0x00F8_4000 - 0x00F8_7FFF)
Read Partition 6
Read Partition 7
5 x 256 KB code flash
Small sectors for
3rd party code
64 KB code flash
16 KB HSM data block 0
(0x0100_0000 - 0x0113_FFFF)
2 x 64 KB secure
code flash
(0x0062_0000 - 0x0062_FFFF)
32 KB code flash
(0x00FC_8000 - 0x00FC_FFFF)
16 KB code flash
Read While Write
partition boundaries
5 x 256 KB code flash
(0x0114_0000 - 0x0127_FFFF)
2 x 16 KB secure data flash
Program code space
Figure 10-4. Flash memory segmentation and read-while-write partitioning
Note
See Table 1 for the flash memory map.
10.3.4 UTest NVM memory space
Devices in the family contain a 16KB area of One-Time Programmable (OTP) flash
memory for storing test information and device configuration data. Most of the device
configuration data is in the form of Device Configuration Format (DCF) records.
• See Introduction for details on DCF record structure, function, and contents.
• See Table 1 for the UTest flash memory map.
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10.3.5 Overlay flash memory
In addition to the ability to use on-chip system RAM for overlay, the microcontroller can
also reroute accesses to on-chip flash memory to other addresses within on-chip flash
memory. The mechanism and controls are similar, with the following exceptions:
• Accesses to special-purpose flash blocks, i.e., UTEST flash, EEPROM, secure flash,
and BAF cannot be rerouted, nor can accesses to other blocks be rerouted to the
UTEST flash, EEPROM, secure flash, or BAF blocks.
• When specifying addresses for overlay flash, i.e., the flash memory addresses that
accesses are to be rerouted to, the mirrored flash address must be used. The mirrored
address range refers to the normal range (0x00F90000 – 0x0127FFFF), with address
field bit[27]2 is set, giving a range of 0x08F90000 - 0x0927FFFF.
See PFlash calibration remap support, for details on memory overlay (remapping).
10.4 End-to-end Error Correction Code (e2eECC)
To support market requirements related to improved functional and transient fault
detection capabilities, this family of automotive microcontrollers includes end-to-end
ECC (e2eECC) support. This e2eECC is structurally different to traditional "ECC at
memory" functionality because it provides robust error detection capabilities from one
endpoint of an information transfer to another endpoint, with temporary information
storage in one or more intermediate components.
Memory protected by ECC/EDC traditionally generates and checks additional error parity
information local to the memory unit to detect and/or correct errors that have occurred on
data stored in the memory. On the other hand, e2eECC generates error protection codes at
the source of data generation. It sends the encoded data and error protection codes to
intermediate storage when a memory write is initiated by a bus master and performs a
data integrity check using the previously stored error protection codes at a data memory
when a read of stored information is requested by a bus master. The intermediate storage
may transform the generated error protection codes into another format for storage and
then regenerate the codes for provision when a request is made to read the stored
information or it may simply store the original protection codes unaltered, depending on
the particular unit.
2.
where the least significant bit of the address field is numbered '0'
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End-to-end Error Correction Code (e2eECC)
Additionally, the error protection codes are generated on the basis of more than just the
data associated with a storage location to protect additional information associated with
an access. In particular, address information corresponding to the access location of the
stored information is combined with the stored data at the data source to generate error
protection codes that cover certain types of addressing errors in the system interconnect
or in the memory unit. The error protection codes may be checked at the memory unit on
a store to ensure that no address information or data has been corrupted while the request
has transitioned through the device from the bus master source. The error protection
codes may also be checked to ensure that address decoding within the storage memory
was performed properly (although not all address decoding errors can be detected this
way) or it may simply store the received data and protection codes at the address it
receives.
On a read request from a bus master, the memory unit retrieves the data information and
error protection codes corresponding to the received address from the storage location or
locations and supplies the data along with the error protection codes to the requesting
device. The requesting device uses a locally stored address value corresponding to the
read request to check the returning data and error protection codes to ensure that no errors
have occurred in either addressing the memory or in the retrieved data. This ensures that
the address sent for the request was not corrupted, the addressed location was actually
accessed (to the extent it is possible to ensure) and the stored data was error free, to the
extent the ECC coding scheme is able to detect. As a result, the fault coverage provided
by the end-to-end check is considerably more robust than the previous implementation of
locally generated and checked/corrected error protection at each memory unit.
A comparison of the traditional and e2eECC approaches is shown in the following table.
Table 10-2. ECC comparison of data write-then-read sequence
Traditional ECC
End-to-End ECC (e2eECC)
Bus master initiates data write
Bus master initiates data write and generates ECC checkbits
based on 29-bit address and 64-bit data fields for the
computational shell or 32-bit data field for the peripheral shell
Data write transfer routed from bus master to appropriate bus Data write transfer (including checkbits) routed from bus
slave
master to appropriate bus slave
For a bus memory slave, generate the ECC checkbits based For a bus memory slave, store data and checkbits into the
on the data value and store data + checkbits into the memory memory
Bus master initiates data read of previously written memory
location
Bus master initiates data read of previously written memory
location
Data read transfer routed from bus master to appropriate bus Data read transfer routed from bus master to appropriate bus
slave
slave
For a bus memory slave, the memory array is accessed, the
controller performs the ECC checkbit decode and syndrome
generation, performs any needed single-bit correction and
drives the read data onto the system bus interconnect
For a bus memory slave, the memory array is accessed, and
the controller passes the read data and associated checkbits
onto the system bus interconnection
Table continues on the next page...
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Table 10-2. ECC comparison of data write-then-read sequence (continued)
Traditional ECC
End-to-End ECC (e2eECC)
The bus master captures the read data and continues
The bus master captures the read data and associated
checkbits, performs the ECC checkbit decode and syndrome
generation, performs any needed single-bit correction and
continues
The scope of differences in the operations "covered" by the ECC checks is readily
apparent with the e2eECC concept providing improved fault detection capabilities in two
important aspects:
• The entire data transaction; from the initiating bus master, through the entire
platform crossbar steering mechanism, to the destination slave target is covered
during write accesses. Likewise, a read is checked from the initiating bus master,
through the crossbar steering mechanism, through the actual memory read and
transmission of the data plus checkbits back to the bus master, where the integrity
and correctness of the entire transaction is checked.
• The selected ECC provides protection of both the address field as well as the data
field, again for improved fault coverage.
Additionally, this particular structure also provides a significant implementation
improvement. The traditional ECC at the memory approach places the checkbit decode
and error syndrome generation with the error/no_error state, affecting whether the system
bus transfer must be stalled (to correct a single bit error or report a noncorrectable event)
or is allowed to complete (for error-free transfers) in a critical timing arc which often sets
the upper limit of the operating frequency of the microcontroller. With the e2eECC
scheme, the checkbit decode and error syndrome logic is located in the requesting bus
master where there are generally more degrees of implementation freedom and the error/
no_error state determination is removed from the system bus cycle termination logic;
producing an improved timing arc and generally higher operating speeds.
Errors that occur within the system interconnect are typically manifested as an incorrect
address, incorrect write data, or incorrect read data to be presented to the slave or back to
the master. Errors occurring within the storage typically manifest themselves eventually
in corrupted read data or checkbits being returned to a requester. While not all possible
errors can be detected this way, this approach provides a substantial improvement versus
traditional methods. Additional on-line diagnostics, or additional hardware, or both
should be able to catch a majority of the errors not covered directly by the e2eECC
scheme.
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Security features
10.5 Security features
The MPC5746C architecture uses a combination of device life cycle monitoring and
password protection to limit the conditions under which debugging interfaces can access
certain areas of flash memory. For more information, refer, Security Reference Manual.
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Chapter 11
Device Configuration Format (DCF) records
11.1 Introduction
Device Configuration Format (DCF) records are used to configure certain registers in the
device during system boot while the reset signal is asserted. An individual DCF record
consists of a pointer to the location of a register internal to the device and the data to be
written to that register.
There are two broad categories of DCF records, TEST DCF Records and UTEST DCF
Records. TEST DCF records are developed by the factory and are used mainly to
program registers involved in trimming trip points for voltage comparators, adjusting
analog to digital voltage supplies, trimming oscillator frequencies, and enabling RAM
repair. However these records can also be used to write any DCF client. The TEST DCF
Records are programmed into TEST flash during production and cannot be modified.
TEST flash is not visible to the user.
The second set of DCF records are UTEST DCF records. Some UTEST DCF records are
written by the factory and programmed during production testing (see DCF_Clients
spreadsheet attached to this document). Others are written by the end user and
programmed at the same time application code is programmed into the flash memory.
User-supplied UTEST DCF records start at the next location in the UTEST memory map
following the UTEST DCF records programmed into the flash memory during factory
production. The user-defined DCF records set up the initial memory map, define which
tests the Self-Test Control Unit (STCU2) will run during the boot sequence, enable the
HSM, assign memory blocks as OTP, assign flash blocks to be associated with specific
password groups and assign flash memory blocks to specific tamper detect regions.
System boot is a complex process requiring a considerable amount of initialization to
take place before releasing reset. Before the device can be used in an application, the user
application code, reset vectors for all of the CPUs and the DCF records must be properly
programmed into their respective flash memories.
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DCF clients
When power is applied to a properly programmed device, the Power Management
Controller (PMC) takes control of the device. After the system power supplies have
reached predefined levels, the Power Management Controller signals the Reset
Generation Module (RGM) to begin the boot sequence. During the boot sequence, the
RGM enables another internal module, the System Status and Control Module (SSCM),
to read the device configuration records and then write the configuration information to
the specified registers. After registers are initialized, the SSCM starts the Self-Test
Control Unit (STCU2), which begins running the tasks enabled by the DCF record
information.
11.2 DCF clients
DCF clients are 32-bit wide hardware registers inside a module, that receive and store the
data from a DCF record. This stored data is used to initialize registers and to configure
features. DCF Clients have a default value before any DCF Records are written, and may
have special writing constraints, such as, ‘Write Once’ or allowing bits to be written from
‘1’ to ‘0’ only or vice versa. DCF clients need not implement all 32 bits. DCF clients
maybe designated ‘TEST DCF record only’, which means that only DCF Records stored
in TEST flash can write to the DCF Client. The DCF Records select the ‘target’ DCF
client by a 30-bit field in the DCF Record consisting of a 15-bit ‘Chip Select’ field and a
15-bit Address field. Each module that includes DCF clients is assigned a Chip Select
during chip definition. The address field is only relevant to the address decoding within
that module and may not necessarily relate to the address of a register visible to software.
11.2.1 Safety features of DCF clients
Depending on its role in the device a client may be equipped with a safety feature or a
combination of safety features.
11.2.1.1 Parity
If a DCF client implements parity checking, then it will receive a parity bit additionally to
it's data in the DCF record. During device operation it will continuously monitor whether
the data it stores matches the parity and report errors to the SSCM.
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11.2.1.2 Triple voting
DCF clients that use the triple voting have three copies of the register. The SSCM will
write to all three registers in a single write cycle. During device operation the DCF client
continuously monitors whether all three copies match and reports errors to the SSCM.
The device will use the majority result, so single errors will not affect device operation.
11.2.1.3 Spreaded triple voting
DCF clients that use spreaded triple voting have three copies of the register which are
individually addressed and where the data is stored in three different formats. The SSCM
will fetch these records independently. During device operation the DCF client
continuously monitors whether all three copies can be resolved from the stored format to
the value and reports errors to the SSCM. The device will use the majority result, so
single errors will not affect device operation.
11.2.1.4 Second write check
This feature is used by DCF clients which receive their records twice - e.g. once before
and once after BIST for clients which retain their value during self test. They will
monitor whether the second write matches the first and report deviations to the SSCM.
11.2.2 DCF client modification rules
Depending on its role in the device a client may implement one or a combination of
modification rules. If a modification rule is in effect, the order in which DCF records are
placed in the record list may be important.
11.2.2.1 Write Once
A DCF client using the Write Once rule can only be written with a single DCF record.
Records appended later in the list will be ignored and not change the value of the client.
11.2.2.2 Write 0 only
A bit in a DCF client can only be written from a 1 to a 0. So, if an earlier DCF record has
set a bit to 0, then an attempt by a later record to set this bit to a 1 will be ignored.
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DCF record structure
11.2.2.3 Write 1 only
A bit in a DCF client can only be written from a 0 to a 1. So, if an earlier DCF record has
set a bit to 1, then an attempt by a later record to set this bit to a 0 will be ignored.
11.3 DCF record structure
A DCF record is a double-word (64-bit) entry consisting of the following:
• Control word: Information to locate the corresponding DCF client internal to the
device (pointer to the location of a register internal to the device)
• Data word: Data to be written to that client
DCF Records select the target DCF client by a 30-bit field in the DCF Record consisting
of a 15-bit ‘Chip Select’ field and a 15-bit Address field. Each module that includes DCF
clients is assigned a Chip Select during chip definition. The address field is only relevant
to the address decoding within that module and may not necessarily relate to the address
of a register visible to software.
Offset
Bit No
0x00
0
1
2
3
4
0x01
5
6
7
8
9
0x02
0x03
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
30
31
62
63
Data[0:31]
Offset
Bit No
0x04
0x05
0x06
0x07
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61
C C C C C C C C C C C C C C C
S S S S S S S S S S S S S S S
14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Address[16:2]
Parity Stop
Figure 11-1. DCF Record Structure
Table 11-1. DCF Record Field Description
Field
Name
Description
0-31
Data[0:31]
32 bits of data that is to be written to the DCF Client
32-46
CSn
Chip Select n
One Chip select is asserted (‘1’) per DCF record to select the target module
for the DCF client. All other Chip Selects should be negated (‘0’).
47-61
Address[16:2]
Address of the DCF client within the selected module.
Table continues on the next page...
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Table 11-1. DCF Record Field Description (continued)
Field
Name
Description
Note: Address decoding for DCF clients may not match the standard software
address map decoding. Details of DCF Client addresses are defined in each
module chapter.
62
Parity
Parity Bit for the DCF Record.
Note:
This bit is NOT implemented for DCF Client written from UTEST.
63
Stop
Stop bit. Indicates the end of the list of DCF Records.
Stop = ‘0’ - NOT the end of the list
Stop = ‘1’ - End of the list
Note:
The Erased state of flash is 0xFFFF_FFFF_FFFF_FFFF.
Therefore the list ends with the first unprogrammed double word. This location
can be programmed with a new record to extend the list.
11.4 DCF records sequence
An individual DCF record consists of information to locate the corresponding DCF client
internal to the device (control word) and the data to be written to that client (data word).
DCF records appear as contiguous series of entries programmed at a specific address
within flash memory. The following structure must be present:
• The first DCF record must be a start record. This record must be placed at the
beginning of a DCF area in flash memory to indicate to the device that the following
records must be processed.
• DCF records containing configuration data must immediately follow the start record
with no blank records between-an unprogrammed record is interpreted as a stop
record and no DCF records following that record are processed. This allows one to
program the records in several sessions, each time appending new records at the end
of the list.
• The end of the configuration records are indicated by the presence of a stop record;
indicated by the stop bit being set. Normally, the stop bit is never set in a valid
UTEST DCF record programmed during production, since this would prevent
appending additional UTEST records. The flash memory location following the last
UTEST DCF record programmed at the factory is an unprogrammed location.
Therefore, that location's contents will be 0xFFFF_FFFF. Thus, the stop bit location
in this unprogrammed flash memory location will be a logic 1, signifying that this is
the last DCF record and it is not to be acted upon.
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DCF records sequence
SSCM recognizes the following record as a start record.
Table 11-2. DCF start record
0x00 (0:31)
0x04 (32:63)
0x05AA_55AF
0x0000_0000
The start bit is set by the factory at the beginning of the UTEST flash memory area.
SSCM recognizes the following record as a stop record.
Table 11-3. DCF stop record
0:31
32:62
63
Ignored
Ignored
1
User-supplied DCF records may be added in a contiguous manner immediately following
the factory-written DCF records. There must never be an unprogrammed record in the
series of DCF records as it will be interpreted as a stop record.
The following table shows the series of DCF records when n data records are stored in
the UTEST flash.
Table 11-4. Series of DCF records in UTEST flash memory
Record type
ADDR offset
DATA
Start record
0x00
0x05AA_55AF
0x04
Data records
0x0000_0000
0x08
WDATA[31:0]
0x0C
CS[14:0]
0x10
ADDR[16:2]
PRTY
STOP=0
PRTY
STOP=0
WDATA[31:0]
0x14
Stop record
STOP=0
CS[14:0]
ADDR[16:2]
...
...
8(n-1) + 0x0
Reserved
8(n-1) + 0x4
Reserved
1
8n + 0x0
8n + 0x4
It is possible for more than one DCF Record to write to the same DCF client. In this case
the later record usually overrides a DCF client value set by a previous record. However,
not all DCF clients allow overwrites; this depends on the DCF client implementation.
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No Start Record
Start Record
Start Record
No Start Record
Data Record - CS1, Ad = 0
Data Record - CS1, Ad = 0
No Start Record
Data Record - CS2, Ad = 0
Data Record - CS2, Ad = 0
No Start Record
Data Record - CS0, Ad = 0
Data Record - CS0, Ad = 0
No Start Record
Stop Record
Data Record - CS2, Ad = 1
overwrite
Chapter 11 Device Configuration Format (DCF) records
Stop Record
Empty Flash
 No action
Initial Programming
Extension
Figure 11-2. Appending DCF records
11.5 Chip configuration records
The DCF Clients Table contains information on DCF clients available in the chip. See the
UTEST-FULL DCF excel attached to this document.
11.5.1 External Regulation Exit Trim Wait (PMCDIG_ERETW)
0
R
1
2
3
4
5
6
7
0
9
10
11
12
13
14
15
DELAY_VAL[2:15]
W
Reset
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
1
0
0
0
0
0
R
DELAY_VAL[16:31]
W
Reset
0
0
0
0
0
0
0
0
1
The following table describes the register functions.
Table 11-5. PMCDIG_ERETW register field descriptions
Field
Description
0-1
This field is reserved.
Reserved
2-15
DELAY_VAL[2:15]
This read-only field is reserved and always has the value zero.
Programmable External Regulation Trim Delay Value
This can be programmed according to the external regulator stablization delay time. This
value will hold no significance where external regulator startup time is fast or external
regulator is turned off during low power modes.
Table continues on the next page...
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Chip configuration records
Table 11-5. PMCDIG_ERETW register field descriptions (continued)
Field
Description
16-31
Programmable External Regulation Trim Delay Value
DELAY_VAL[16:31]
This can be programmed according to the external regulator stablization delay time. This
value will hold no significance where external regulator startup time is fast or external
regulator is turned off during low power modes.
11.5.2 Security and serial boot mode records
For a description for the Flash backdoor password, serial boot mode and security records,
please refer to the SSCM chapter.
11.5.3 STCU configuration records
The STCU provides a large number of configuration records. Please see, Self-Test
Control Unit (STCU2) for more details.
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Chapter 12
Debug Overview
12.1 Introduction
The device contains multiple Nexus clients (Nexus class 3+) that communicate over an
auxiliary port interface compliant to IEEE-ISTO 5001-2012 standard and two sets of
JTAG ports compliant with IEEE 1149.1 standard and 1149.7 cJTAG standard.
Nexus class 3+ module provides real-time development capabilities for e200z2 and
e200z4 core processor in compliance with Class 3 of the IEEE-ISTO 5001-2012
standard, with additional Class 4 features available.
The debug requirements covers instruction and data trace across the 2 host cores,
instruction trace from the instruction trace of Z0 core inside the HSM and data trace of
accesses to system RAM. In addition, compact CJTAG is supported alongside standard
JTAGC.
NOTE
Throughout this manual, the e200Z4204n3 core is referred as
Z4 or e200Z4.
Similarly, the e200z210n3 core is referred as Z2 or e200Z2.
The debug solution is created by the following modules:
• JTAGC - IEEE-1149.1 operations
• CJTAGC for IEEE 1149.7 operations (note full 4-pin JTAG operation is the default
mode of operation)
• JDC - required to support the Challenge Response password authentication protocol
via the HSM module
• e200z43 nexus class 3 module
• e200z2 nexus class 3 module
• Nexus Data Trace client (NXMC) for the SRAM.
• Nexus 2 trace client for Z0 core of HSM
• Nexus Port Controller, capable of supporting 16xMDO full port mode and 12xMDO
reduced port mode
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Introduction
The communication with Nexus Debug Interface (NDI) is handled via the auxiliary port
and the JTAG port.
• The auxiliary port comprises 20 output pins and one input pin. The output pins
include one message clock out (MCKO) pin, 16 message data out (MDO) pins, two
message start/end out (MSEO0, MSEO1) pins, and one event out (EVTO) pin. Event
in (EVTI) is the only input pin for the auxiliary port.
• There are two sets of JTAG ports, each consists of three inputs and one output. Only
BGA324 supports two sets of JTAG ports.These pins include test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock input (TCK). TDI,
TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and are
shared with the NDI through the test access port (TAP) interface. Ownership of the
TAP is achieved by loading the appropriate enable instruction for the desired Nexus
client in the JTAG controller (JTAGC). See Memory map and registers section for
the JTAGC opcodes to access the different Nexus clients.
TDI
TDO
TMS
TCK
0
JTAG
TDI _ALT
TDO_ALT
1
TMS_ALT
TCK_ALT
JTAG_SELECT
Figure 12-1. JTAG Ports
NOTE
For details on JTAG pads, see the device I/O Signal Description
and Input Multiplexing tables attached to this document as an
excel file.
The following peripherals support debug features:
• STM_0, STM_1
• SWT_0, SWT_1, and HSM_SWT
• FCCU
• eMIOS_0, eMIOS_1
• SAI0, SAI1, and SAI2
• ENET
• IIC_0, IIC_1, IIC_2, and IIC_3
• DSPI[3:0]
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Chapter 12 Debug Overview
• FLEXCAN[7:0]
• eDMA controller
• SPI[3:0]
• PIT-RTI
• RTC-API
• SSCM
NOTE
Debugger connection would break after STANDBY exit if Pad
Keeper functionality is enabled in STANDBY modes.
12.2 Features
The debug module of the device compliant with the IEEE-ISTO 5001-2012 standard. The
following features are implemented:
• 29-bit pin interface for high throughput, including two sets of four JTAG pins
• Two modes are supported: full port mode (FPM) and reduced port mode (RPM).
FPM comprises 16 MDO pins. RPM comprises 12 MDO pins, and can be used
to increase the number of GPIOs. Care must be taken as bandwidth will be
limited.
• At ambient temperature, the Nexus Aux port MCKO supports the maximum
frequency of 80 MHz both at FPM and RPM. Otherwise, the maximum
supported frequency is reduced to 40 MHz.
• Auxiliary output port
• One MCKO (Message clock out) pin
• 16 MDO (Message data out) pins
• Two MSEO (Message start/end out) pins
• One EVTO (Event out) pin
• Auxiliary input port uses one EVTI (Event in) pin.
• Two sets of JTAG ports each uses four pins (TDI, TDO, TMS, TCK, TDI_ALT,
TDO_ALT, TMS_ALT, and TCK_ALT)
• The NPC block performs the following functions:
• Control arbitration for ownership of Nexus Auxiliary Output Port between all the
nexus clients
• Nexus Device Identification Register and Messaging
• Generates MCKO enable and frequency division control signals
• Controls sharing of EVTO between different nexus clients.
• Generates an MCKO clock gating control signal to enable gating of MCKO
when the auxiliary output port is idle.
• Control of the device-wide debug mode
• Generates asynchronous reset signal for Nexus blocks
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Debug scheme
• Host processor (e200z4) and secondary processor (e200z2) development support
features:
• IEEE-ISTO 5001-2012 standard class 3+ compliant.
• Program trace via Branch Trace Messaging (BTM), with the option of using
Branch history messaging to enhance message throughput.
• Data trace via data write messaging (DWM) and data read messaging
(DRM). This allows the development tool to trace reads and/or writes to
selected internal memory resources.
• Ownership trace via ownership trace messaging (OTM). OTM facilitates
ownership trace by providing visibility of which process ID or operating
system task is activated. An ownership trace message is transmitted when a
new process/task is activated, allowing development tools to trace ownership
flow.
• Run-time access to the on-chip memory map via the JTAG port.
• Watchpoint messaging (WPM) via the auxiliary port. This allows a
watchpoint to be set, which then sends a watchpoint message each time the
watchpoint is hit. Unlike watchpoint triggering, WPM does not stop the core
or start trace.
• Registers for Program Trace, Data Trace, Ownership Trace and Watchpoint
messaging.
• Additional class 4 features
• Watchpoint trigger enable of program and/or data trace messaging. This is
an extension of WPM to allow a watchpoint to stop or start program or data
trace.
• Processor overrun control
• Cross triggering — The capability for an EVTO (event out) signal from either the
e200z4 or e200z2 Nexus3+ to generate a debug request to the other core, thus
allowing both cores to enter debug mode within a short period of each other.
12.3 Debug scheme
The debug scheme and connectivity is shown in the following figure:
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Chapter 12 Debug Overview
System AXBS
PRAM 0
HSM
e200z0
e200z2
e200z420
e200z4
Nexus2+
Nexus3+
Nexus3+
OnCE
OnCE
OnCE
R/W Register,
R/W data,
halt, step,
continue
N2+ I/F
integrated
into HSM's
core IP
Program,
ownership,
wathcpoint,
trace
Trace buffer
R/W
access
R/W Register,
R/W data,
halt, step,
continue
Program, data,
ownership,
wathcpoint,
trace
N3+ interface
integrated
into core IP
R/W Register,
R/W data,
halt, step,
continue
R/W
access
Program, data,
ownership,
wathcpoint,
trace
N3+ interface
integrated
into core IP
Trace buffer
PRAM 1
R/W
access
Trace buffer
data, trace,
wathcpoint,
Trace buffer
NXMC
IPS I/F
Timestamp
JDC
NPC
JTAGC
Auxiliary Port Control
C-JTAGC
TDI
TDO
TCK
TMS
EVTI
EVTO
MSEO[0..1] MCKO
MDO[0..11]
MDO[12..15]
Figure 12-2. Debug scheme
12.4 Modes of operation
The Nexug debug interface (NDI) block is in reset when the TAP controller state
machine is in the TEST-LOGIC-RESET state. The TEST-LOGIC-RESET state is entered
on the assertion of the power-on reset signal, or through state machine transitions
controlled by TMS. Ownership of the TAP is achieved by loading the appropriate enable
instruction for the desired Nexus client in the JTAG controller (JTAGC) block. The NPC
transitions out of the reset state immediately following negation of power-on reset.
12.4.1 Nexus Reset Mode
In Nexus reset mode, the following actions occur:
• Register values default back to their reset values.
• The message queues are marked as empty.
• The auxiliary output port pins are negated if the NDI controls the pads.
• The TDO output buffer is disabled if the NDI has control of the TAP.
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Modes of operation
• The TDI, TMS, and TCK inputs are ignored.
• The NDI block indicates to the MCU that it is not using the auxiliary output port.
This indication can be used to three-state the output pins or use them for another
function.
12.4.2 Full-port Mode
In the full-port mode (FPM), 16 MDO pins (MDO[0..15]) pins are used to transmit
Nexus messages. All trace features are available by writing to the configuration registers
via the JTAG port. FPM is entered by asserting the MCKO_EN and FPM bits in the Port
Configuration Register (PCR).
12.4.3 Reduced-port Mode
In the reduced-port mode (RPM), the number of MDO pins is reduced from 16 to 12
(MDO[0..11]). All trace features are available by writing to the configuration registers
via JTAG. However, the FIFO overflow errors are more likely to occur in this mode,
especially if the data trace is enabled. RPM is entered by asserting the MCKO_EN bit
and negating the FPM bit in the Port Configuration Register (PCR).
12.4.4 Disabled-Port Mode
In the disabled-port mode, auxiliary output pin port enable signals are negated, thereby
disabling the message transmission. Any debug feature that generates messages cannot be
used. The primary features available are class 1 features and read/write access to the
registers. Class 1 features include the ability to trigger a breakpoint event indication
through EVTO. The NDI is placed in disabled mode upon exit of power-on reset.
12.4.5 Multi mode nexus TAP
In this mode, Nexus Debug interface of e200Z4 and e200Z2 gets connected in a daisy
fashion. This allows the tools to treat each core individually and then start (or stop) all
cores together with a longer scan chain. Note that the HSM is not included in this daisy
chain.
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Chapter 12 Debug Overview
TDI
0
Figure 12-3. Multi mode nexus TAP
12.5 External signal description
The auxiliary and JTAG pin interfaces provide for the transmission of messages from
Nexus modules to the external development tools and for access to Nexus client registers.
The auxiliary/JTAG pin definitions are outlined in the following table:
Table 12-1. Auxiliary/JTAG pin definitions
Name
Port
Function
EVTO
Auxiliary
Event Out pin
EVTI
Auxiliary
Event In pin
MCKO
Auxiliary
Message Clock Out pin (from NPC)
MDO[0:15]
Auxiliary
Message Data Out pins
MSEO[0:1]
Auxiliary
Message Start/End Out pins
TCK
JTAG
Test Clock Input
TDI
JTAG
Test Data Input
TDO
JTAG
Test Data Output
TMS
JTAG
Test Mode Select Input
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Memory Map and Registers
12.6 Memory Map and Registers
The NDI block contains no memory mapped registers. Nexus registers are accessed by
the development tool via the JTAG port using a client select and a register index. The
client select is controlled by loading the correct access instruction into the JTAG
controller. After the desired client TAP is selected, OnCE registers for that core client are
accessible by loading the appropriate value in the RS[0:6] field of the OnCE command
register (OCMD). Other Nexus clients (data trace client on SRAM) use a Nexus access
command to access the Nexus registers of the clients. Nexus is enabled, and the
associated Nexus registers become accessible, by loading the NEXUS_ENABLE
instruction into the RS[0:6] field of the OCMD. When Nexus register access is enabled,
the desired Nexus registers are accessible.
12.7 Functional Description
The block is implemented by integrating the following blocks:
• Nexus Port Controller Block
• Dual Nexus e200z4 Development Interface (OnCE and Nexus3+ subblocks)
• Nexus e200z2 Development Interface (OnCE and Nexus3+ subblocks)
• NPC_HNDSHK module
• NXMC module
NOTE
The TAP controller logic, reset logic, and some miscellaneous
logic are duplicated in all these blocks.
12.7.1 Enabling Nexus Clients for TAP Access
Once the NDI is out of the reset state, the loading of a specific instruction in the JTAG
controller (JTAGC) block is required to grant the NDI ownership of the TAP. Each
Nexus client has its own JTAGC instruction opcode for ownership of the TAP, granting
that client the means to read/write its registers. Once the JTAGC opcode for a client has
been loaded, the client is enabled by loading its NEXUS-ENABLE instruction. Opcodes
for all other instructions supported by Nexus clients can be found in the relevant sections
of this chapter.
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12.7.2 TAP Sharing
Each of the individual Nexus blocks on the MCU implements a TAP controller for
accessing its registers. The JTAGC controls the ownership of the TAP so that the
interface to all of these individual TAP controllers appears to be a single port from
outside the device. Once a Nexus client has been granted ownership of the TAP, any data
input via TDI and TMS is passed to the selected TAP controller, and any TDO output
from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSEDR state was entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while
they are inactive.
12.7.3 Configuring the NDI for Nexus Messaging
The NDI is placed in disabled mode upon exit of power-on reset. If message transmission
via the auxiliary port is desired, a write to the port configuration register (PCR) located in
the NPC is then required to enable the NDI and select the mode of operation. Asserting
MCKO_EN in the PCR places the NDI in enabled mode and enables MCKO. The
frequency of MCKO is selected by writing the MCKO_DIV field. Asserting the FPM bit
selects full-port mode.
When writing to the PCR, the PCR LSB must be written to a logic 0. Setting the LSB of
the PCR enables factory debug mode and prevents the transmission of Nexus messages.
The following table describes the NDI configuration options:
Table 12-2. NDI Configuration Options
MCKO_EN bit of PCR
FPM bit of PCR
Configuration
0
X
Disabled
1
1
Full-Port Mode
1
0
Reduced Port Mode
12.7.4 TCK clock relation with NPC clock
The TCK frequency should always be less than or equal to half of the NPC clock
frequency.
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Functional Description
12.7.5 Programmable MCKO frequency
MCKO is an output clock to the development tools used for the timing of MSEO and
MDO pin functions. MCKO is derived from the system clock, and its frequency is
determined by the value of the MCKO_DIV field in the port configuration register (PCR)
located in the NPC. Possible operating frequencies include NPC_CLK, one-half, onequarter, and one-eighth NPC_CLK speed.
The following table shows the MCKO_DIV encodings. In this table, NPC_CLK
represents the system clock frequency of 80 MHz.
Table 12-3. MCKO_DIV values
MCKO_DIV[2:0]
MCKO Frequency
0b0001
NPC_CLK
0b001
NPC_CLK/2
0b010
Reserved
0b011
NPC_CLK/4
0b100
Reserved
0b101
Reserved
0b110
Reserved
0b111
NPC_CLK/8
1. The NPC_CLK (80MHz) setting for MCKO frequency should only be used if this setting does not violate the maximum
operating frequency of the auxiliary port pins.
NOTE
The Nexus Port Controller Port Configuration Register MCKO
Divider bits (NPC_PCR[MCKO_DIV]) can be set to 0b000 to
select a 1X clock rate as the Nexus Auxiliary output port
frequency for the MCKO and MDO pins. Depending on the
system frequency, this may force the MCKO and MDO pins to
switch at a frequency higher than can be supported by the pins.
This maximum frequency is specified in the device electrical
specification of the Nexus MCKO and MDO pins. Insure that
the maximum operating frequency of the MDO and MCKO
pins is not violated when setting the NPC_PCR[MCKO_DIV]
values.
The following table shows the NPC clock frequencies across DFS modes.
Table 12-4. NPC clock frequencies
Use cases
Full Run
when HSM is enabled
80
when HSM is disabled
80
Table continues on the next page...
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Table 12-4. NPC clock frequencies (continued)
Use cases
when HSM is enabled
when HSM is disabled
LDFS80
40
40
NLDFS80
40
80
NLDFS40
20
40
NLDFS20
10
20
12.7.6 Cross Triggering Control
To enable a debug event in one core to cause a debug event in the other core at
approximately the same time, the EVTO signal from the e200z2 Nexus3+ or e200z4
Nexus3+ is connected to the other core’s DEVT1 input. When enabled in each core’s
Nexus1 DBCR0 register, a pulse of the DEVT1 signal causes a debug event to occur. In
this case, only one external EVTO signal is generated and each core controls whether or
not EVTO causes a debug event to occur.
Cross triggering of breakpoints between cores is supported. As a minimum this should
include the ability to stop and start cores synchronously. i.e., break on one core can stop
other cores immediately and run on one core can trigger other cores to run. Cross
triggering with the HSM is NOT to be supported since it is to be completely independent.
Interconnection of debug mode control signals are shown in the following figure.
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Functional Description
Figure 12-4. Debug Mode Control Interconnections
12.7.7 Time Stamping
The device implements Nexus trace time-stamping support logic module. This provides a
mechanism to insert time-stamping data into the trace stream from each nexus client.
Enable and disable controls of this time-stamping feature is included in the JTAGC, using
some of the available auxiliary data bits of DATA1 register.
The time-stamping should run on the fastest core clock frequency.
• The time-stamping is based upon the full 30-bit time-stamp.
• The time-stamp is required to be reset only upon a power on reset.
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12.8 Nexus Port Controller (NPC)
The Nexus Port Controller (NPC) is that part of the NDI that controls access and
arbitration of the device’s internal Nexus modules. The NPC contains the port
configuration register (PCR) and the device identification register (DID).
The device has two instances of NPC. NPC_0 is responsible for the traces and interaction
with pads and remains in full power domain. NPC_1 exists in always on domain and
interacts with NPC Handshake (NPC HNDSHK). When the system enters into the low
power mode, the NPC_1 and the NPC HNDSHK together follow a protocol handshaking
with the debugger. The handshake enables the load and store of the context appropriately
by the debugger.
NOTE
NPC_0 TAP should be reset on LPU_RUN to DRUN transition
if nexus tracing is required to be enabled in DRUN mode.
The protocol to be followed by the debugger for each low power mode is described in the
following section.
For details, see the NPC chapter.
12.8.1 NPC Handshake module
This module together with the NPC_1 enables debug entry/exit across the low power
modes. The NPC Handshake supports:
• setting and clearing of the PCR sync bit in NPC_1 on low-power mode entry and exit
• putting the core into debug mode on low-power mode exit
• generating a falling edge on the JTAG TDO pad on low-power mode exit
Entry into STOP/STANDBY from RUN modes or Entry into LPU_STOP/
LPU_STANDBY from LPU_RUN mode:
• For the device to be in debug mode on low power exit, the debugger should set the
LP_DBG and LP1_SYNC bit in the NPC_1 PCR register.
• On STOP, STANDBY, LPU_STOP or LPU_STANDBY mode entry, the LPU
controller asserts the LP mode entry request input after it gets an indication from
MC_ME that the clock disable process has completed and before the processor enters
its stopped state. The mode transition will then not proceed until the LP mode entry
acknowledge output has been asserted to the LPU controller.
• The notification to the debugger of a low-power mode entry consists of setting the
NPC_1 PCR [LP1_SYNC] bit by the NPC Handshake module.
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Nexus Port Controller (NPC)
• The debugger acknowledges that the transition into a low-power mode may proceed
by clearing NPC_1 PCR [LP1_SYNC] bit.
• The device enters into the low power modes. In anticipation of the low-power mode
exit notification, the TDO pad is driven to '1'.
Exit from STOP/STANDBY into RUN modes or Exit from LPU_STOP/
LPU_STANDBY into LPU_RUN mode:
• On STOP or LPU_STOP mode exit, the LPU controller asserts the LP mode exit
request input after ensuring that the regulator and memories are in normal mode and
before the processor exits its stopped state. The mode transition will then not proceed
until the LP mode exit request has been acknowledged. The MC_RGM asserts the
exit from standby input when executing a reset sequence due to a STANDBY or
LPU_STANDBY exit. The reset sequence will then not complete until the LP mode
exit request has been acknowledged.
• The notification to the debugger of a low-power mode exit consists of driving the
TDO pad to '0'.
• The debugger acknowledges that the transition from a low-power mode can continue
by setting the NPC_1 PCR [LP1_SYNC] bit.
• Further, the NPC_1 PCR[LP1_sync] bit is de-asserted by the hardware and the LP
mode exit acknowledge output is sent to the LPU controller. The chip comes out of
low power mode with the core in the debug mode.
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Figure 12-5. Low-Power mode debug handshake flow Ddiagram for STOP, STANDBY,
LPU_STOP, LPU_STANDBY
Entry into LPU_RUN mode from RUN modes:
• For the device to be in debug mode on LPU_RUN mode entry, the debugger should
set the NPC_1 PCR [LP_DBG] and NPC_1_PCR[LP1_SYNC].
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Nexus Port Controller (NPC)
• On LPU_RUN mode entry, the LPU controller asserts the LP mode entry request
input after it gets an indication from MC_ME that the clock disable process has
completed and before the processor enters its stopped state. The mode transition will
then not proceed until the LP mode entry acknowledgement has been asserted to the
LPU controller.
• The notification to the debugger of a low-power mode entry consists of setting the
NPC_1 PCR[LP1_SYNC] bit.
• The debugger acknowledges that the transition into a low-power mode may proceed
by clearing the NPC_1 PCR[LP1_SYNC].
• If the target mode is LPU_RUN and not the stop/standby modes, the debugger should
observe '0' on TDO pad and acknowledge that the transition into LPU_RUN mode
can continue by setting the NPC_1 PCR[LP1_SYNC].
• Further, the NPC_1 PCR[LP1_sync] bit is de-asserted by the hardware and the LPU
RUN entry acknowledgement is sent to the LPU controller. The device comes into
LPU_RUN mode with the Z2 core in the debug mode.
For getting Z2 core out of debug mode, see the Core debug support chapter.
Exit from LPU_RUN mode into RUN modes:
• For the device to be in debug mode on RUN mode entry, the debugger should set the
NPC_1 PCR[LP_DBG] and NPC_1_PCR[LP1_SYNC].
• On LPU_RUN mode exit, the LPU controller asserts the LP mode entry request after
it gets an indication from MC_ME that the clock disable process has completed and
before the processor enters its stopped state. The mode transition will then not
proceed until the LP mode entry acknowledgement has been asserted to the LPU
controller.
• The notification to the debugger consists of setting the low-power mode handshake
bit in the NPC_1 PCR[LP1_SYNC].
• The debugger acknowledges by clearing the NPC_1 PCR[LP1_SYNC].
• If the target mode is RUN and not the LPU stop/standby modes, the debugger should
observe '0' on TDO pad and further acknowledge that the transition into RUN mode
can continue by setting the NPC_1 PCR[LP1_sync] bit.
• Further, the NPC_1 PCR[LP1_sync] bit is de-asserted by the hardware and the LP
mode exit acknowledgement is sent to the LPU controller. The device comes into
RUN mode with the Z4 core in the debug mode.
For getting Z4 core out of debug mode, see the Z4 core debug support chapter.
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Figure 12-6. Low-Power mode debug handshake flow diagram for LPU_RUN entry and
exit
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e200z4 core and e200z2 core debug support
12.9 e200z4 core and e200z2 core debug support
Internal debug support in the e200z4 core and e200z2 core allows for software and
hardware debug by providing debug functions, such as instruction and data breakpoints
and program trace modes.
For details, see the e200z4 Core Debug Support chapter and e200z2 Core Debug Support
chapter.
12.10 JTAG Controller (JTAGC)
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format. All Nexus debug
registers are accessed and configured via the JTAG controller.
Sharing of TAP with other TAP controllers via ACCESS_AUX_x instruction (nexus
clients/ other TAPs for debug placed as aux TAPs).
AUX port selection: When ACCESS_AUX_x instruction is loaded, control of the JTAG
pins are transferred to the selected TAP controller. Any data input via TDI and TMS is
passed to the selected TAP controller, and any TDO output from the selected TAP
controller is sent back to the JTAGC to be output on the pins. The JTAGC regains control
of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was entered.
Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
DATA 1 register: It is used for SRAM_MUX support, timestamping support and for
disabling port enables from NPC to aux pads. See JTAGC Control 1 register.
For details, see the JTAGC chapter.
12.11 JTAG ID
The JTAG ID of the device is dependent on SIUL2_MIDR1[MAJOR_MASK] and
SIUL2_MIDR1[MINOR_MASK] register field value.
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SIUL2_MIDR SIUL2_MIDR Version
1[MAJOR_MA 1[MINOR_MA Number
SK]
SK]
4 bit
Design Center PIN
Manufacturer
ID
Constant
JTAG_ID
6 bit
10 bit
11 bit
1 bit
32 bit
0x0
0x1
0x1
0x26
0x84
0xE
0x1
1988401D
0x1
0x1
0x1
0x26
0x85
0xE
0x1
1988501D
12.12 CJTAGC
The CJTAG is based on IEEE 1149.7. It has two wire interface (TCK and TMS) with
default mode as 4-wire interface. Switches to 2-wire with standard switching sequence.
For details, see Switching from Standard Protocol to Advanced Protocol.
Unused ports can be assigned for other purposes once switching is done. No special
configuration required for the device. For details, see CJTAG chapter.
12.13 JDC
The JDC allows movement of data from IPS to JTAG domain registers (and back), but it
does not perform the top level JTAG functions such as aux port sharing or boundary scan
register control. It is currently used to allow communication between CPU and external
tools for things such as security password challenge/response.
For details, see JDC chapter.
12.14 Debug implementation
This section describes the practical implementation of the debug port, its management,
and the multiplexing strategy of its pads. It is required on the device to support the Class
3+ (2012) debug features on the e200Z4 and minimum Class 3 (2012) on the e200Z2.
12.14.1 Debug Capabilities
The device supports the Class 3 and Class 3+ debug features listed in the following table.
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Table 12-5. Nexus3 Debug Requirements
Feature
Class 1
Class 2
Class 3
Class 4
Static debug
X
X
X
X
Set breakpoints/watchpoints
X
X
X
X
Watchpoint messaging
X
X
X
X
Ownership trace
-
X
X
X
Program trace (BTM)
-
X
X
X
Port replacement
-
-
-
-
Data trace (write only)
-
-
X
X
Dynamic memory read/write
-
-
X
X
Data trace (read/write)
-
-
X
X
Data acquisition
-
-
X
X
Overrun Control
-
-
-
X
Memory substitution
-
-
-
-
Complex triggering
-
-
-
-
External memory substitution
-
-
-
-
Enable/disable trace based on a watchpoint
-
-
X
The JTAG and Nexus port will work both at 3.3 V and 5 V, according to the device
power supply.
Boundary scan test is supported.
12.14.2 Debug port
The debug port is composed of a total number of 25 pads. For Nexus 3+ pin description,
see Signal Description chapter.
The reset and ready pins that are often present as extensions to the JTAG port are not
implemented.
12.15 Nexus Class 3+ Auxiliary Port
The Nexus Auxiliary Port provides real-time development class 3+ capabilities in
compliance with the IEEE-ISTO 5001-2012 standard. This development support is
supplied without requiring external address and data pins for internal visibility.
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By default, after power-on reset, Nexus Auxiliary Port circuitry (controller) and the
dedicated pad are disabled to avoid power consumption. It can only be enabled via a
certain sequence given by the debugger. As soon as the Nexus Auxiliary Port is enabled,
the Nexus pads are enabled.
NOTE
A full-port (16 MDOs) and reduced-port mode (12 MDOs) is
supported and controlled via the Port Configuration Register
(PCR) register.
Table 12-6. AUX Port Assignments
Instruction
Codes[5:0]
Instruction Summary
AUX_TAP_NPC_0
100001
Enables access to the NPC controller
AUX_TAP_NPC_1
100010
Enables access to the NPC controller
used for low power handshake
AUX_TAP_MBIST
100100
Enables access to the MBIST TAP
controller
AUX_TAP_JDC
100110
Enables access to the JDC TAP
controller
AUX_TAP_HSM
100111
Enables access to the HSM TAP
controller
AUX_TAP_Z4
101000
Enables access to the Z4 TAP controller
AUX_TAP_Z2
101010
Enables access to the Z2 TAP controller
AUX_TAP_NXMC
110100
Enables access to the NXMC TAP
controller
AUX_TAP_PARALLEL
111100
Enables access to all the cores in daisy
chain manner. For details, see Multi
mode nexus TAP.
12.16 e200z2 Nexus 3
The e200z2 Nexus 3 module provides real-time development capabilities for
corresponding core processors in compliance with the IEEE-ISTO 5001-2012 standard.
This module provides development support capabilities without requiring the use of
address and data pins for internal visibility
A portion of the pin interface (the JTAG port) is also shared with the OnCE / Nexus 1
unit. The IEEE-ISTO 5001-2012 standard defines an extensible auxiliary port which is
used in conjunction with the JTAG port in these processors
For details, see the e200z2 Nexus 3 chapter.
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e200z4 Nexus 3
12.17 e200z4 Nexus 3
The e200z4 modules provide real-time development capabilities for e200z4d processors
in compliance with the IEEE-ISTO 5001-2012 standard. This module provides
development support capabilities without requiring the use of address and data pins for
internal visibility.
The development features supported are Program Trace, Data Trace, Watchpoint
Messaging, Ownership Trace, Data Acquisition Messaging, and Read/Write Access via
the JTAG interface. The Nexus 3 module also supports two Class 4 features: Watchpoint
Triggering and Processor Overrun Control.
For details, see the Z4 Nexus Module chapter.
12.18 Nexus Crossbar Multi-master Client (NXMC)
The Nexus Crossbar Multi-master Client (NXMC) module provides real-time trace
capabilities in compliance with the IEEE-ISTO Nexus 5001-2011 standard. This module
provides development support capabilities for SoCs without requiring address and data
pins for internal visibility. A portion of the pin interface is also compliant with the IEEE
1149.1 JTAG standard.
To provide Nexus data trace messaging from bus masters on the master ports of the
crossbar (XBAR) that do not inherently have a trace client, a Nexus Crossbar MultiMaster Client (NXMC) monitors traffic into the master port of the XBAR. Trace
messages transmitted over the Nexus interface (or stored in trace memory) include which
master generated the message as well as an identifier for the pre-concentrator source of
the message.
• Data Trace Message Formats supported: Data write/ read/ write sync/ read sync/
error messages.
• HSM master accesses filtering feature
• Watchpoint trigger input based messaging
• Watchpoint trigger out
• EVTO EVTI initiates sync message (message with complete address)
• All nexus trace control features just like any other client.
• No peripheral interface supported.
• It is an acceptable restriction that the user can not dynamically switch the input mux
during run-time
• Watchpoints are to be implemented to permit enable/disable of trace
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• The pin list specifies an EVTO pin for watch point signalling, which can be shared
among all core nexus clients and the NXMC
• EVTO from the NXMC should be used for driving cross trigger, just like EVTO
from other cores. NXMC is included in the cross triggering scheme for example, a
watchpoint on a specified data access can trigger system (all other cores) to stop
For details, see the NXMC chapter.
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Chapter 13
Reset and Boot Overview
13.1 Introduction
The chapter describes the global and local reset behavior of the device.
13.1.1 Global Reset
The global reset behavior refers to device reset behavior controlled by the MC_RGM
which affects several modules of the device at the same time. The global reset is linked to
the reset process described in Global Reset Process.
13.1.2 Local Reset
The local reset behavior refers to module reset behavior controlled by the MC_RGM or
dedicated modules which affects only one module at a time. Local resets are described in
the modules chapter.
13.1.3 Reset sources
As long as critical supply voltages are not reliable, the PMC provides the below
mentioned signals to put the whole device into a POWERUP state. For more information,
refer section, Reset Process Sequences
• LVD_FLASH
• LVD_IO_A_LO
• LVD_LV_PD0_hot
• LVD_LV_PD1_hot
• LVD_LV_PD2_hot
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• POR_HV
• POR_LV
NOTE
On any of the above events, MC_RGM_DES[F_POR] will be
set. Refer to PMCDIG_SGSR to detect the exact source of
POWERUP for RGM. PMCDIG_SGSR[POR] indicates the
POWERUP condition for the voltage regulator and
MC_RGM_DES[F_POR] indicates the POWERUP for digital
logic of the chip.
The following table lists the destructive and functional reset sources of the device.
Table 13-1. Destructive reset sources
Reset Source
Mapping
Destructive Reset Source
Status
Reactions
Possible
Bidirectional
External reset
generation/
Software
control
Destructive
Reset
escalation
enabled
1
Reserved
2
HSM destructive reset
OK
Destructive
Yes/Read_only
Yes
3
Software generated destructive reset
OK
Destructive
Yes/Read_only
Yes
4
SSCM Secure reset request
OK
Destructive
Yes/Read_only
Yes
5
func_reset_escalation
OK
Destructive
Yes/Read_only
Yes
6
STCU unrecoverable fault
OK
Destructive
Yes/Read_only
Yes
7
SWT0 (flash initialization error)
OK
Destructive
Yes/Read_only
Yes
8
SWT1 reset request
OK
Destructive
Yes/Read_only
Yes
NOTE
Destructive reset escalation due to selective destructive reset
sources can be disabled by configuring
GPR_CTL[DEST_ESC_CTRL2],
GPR_CTL[DEST_ESC_CTRL1], and GPR_CTL[DEST_ESC_
CTRL0]. For more details see, GPR Chapter.
NOTE
STCU unrecoverable fault as source of destructive reset can be
disabled from UTEST_MISC[SUF_DIS].
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NOTE
No functional reset source can be demoted to Safe mode or
interrupt in the LPU mode.
Table 13-2. Functional Reset Sources
Reset Source
Mapping
Functional Reset Sources
Status
Reactions
Possible
Bidirectional
External reset
generation/
Software
control
Functional
Reset
escalation
enabled
1
Reserved
2
HSM generated functional reset
OK
Short Functional
No/Read_Write
Yes
3
Software generated functional reset
OK
Long/Short/
Functional
No/Read_Write
Yes
4
NMI from WKPU
OK
Long/Short
Functional/Safe
Request
No/Read_Write
Yes
5
JTAG_RST
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
6
Reset generated after self test is
complete
OK
Long Functional
Yes/Read_only
Yes
7
FXOSC frequency out of range from
CMU 1
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
8
Long functional reset source by fault
correction unit
OK
Long Functional
No/Read_Write
Yes
9
Short functional reset source by fault
correction unit
OK
Short Functional
No/Read_Write
Yes
10
Z4 DBRST
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
11
Reserved
12
Z2 DBRST
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
13
LVD_IO_A_HI
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
14
HVD_LV_cold
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
15
Reserved
16
Reserved
17
LVD_LV_PD2_cold
OK
Long/Short
Functional/Safe
Request/Interrupt
No/Read_Write
Yes
1. Reaction for this reset source should never be configured as interrupt or safe mode.
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NOTE
HVD_LV_cold, LVD_LV_PD2_cold, and LVD_IO_A_HI as
source of functional reset can be disabled from
PMC_MISC[REE] bits. Also HVD feature can be disabled/
enabled from UTEST_MISC[HVD_EN]
During power-up, all functional terminal are maintained into a known state as described
within Table 13-3
Table 13-3. Functional terminal state during power-up and reset
TERMINAL TYPE1
POWERUP pad state2
RESET pad state
DEFAULT pad state3
Comments
RESET
strong pull-down
strong pull-down
weak pull-up
functional reset pad.
PORST4
Weak pull down
Weak pull up
weak pull-up
power on reset pad.
GPIO
high impedance
high impedance
high impedance
by default, but
configurable for
STANDBY exit
ANALOG
high impedance
high impedance
high impedance
-
EOUT0, EOUT1
high impedance
high impedance
high impedance
TCK
high impedance
weak pull-up
weak pull-up
-
TMS
high impedance
weak pull-up
weak pull-up
-
TDI
high impedance
weak pull-up
weak pull-up
-
TDO
high impedance
high impedance
high impedance
-
TCK_ALT
high impedance
weak pull-up
weak pull-up
-
TMS_ALT
high impedance
weak pull-up
weak pull-up
-
TDI_ALT
high impedance
weak pull-up
weak pull-up
-
TDO_ALT
high impedance
high impedance
high impedance
-
1. refer to pinout information for terminal type
2. POWERUP state is maintained until supply cross the power-on reset threshold: POR_LV for LV supply, POR_HV for high
voltage supply.
3. before software configuration
4. PORST is not driven internally, so the state needs to be maintained externally on board
13.2 Global Reset Process
This section describes the global reset process.
13.2.1 Overview
The global reset process is a sequence of several reset phases. Each reset phase has a
specific entry condition, a specific exit condition, and a specific device reset behavior,
which is different among the reset phases. The reset phases are executed in a specific
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order, thus building the actual global reset process. There are several modules
contributing to the global reset process. All modules of the device can be affected by the
global reset process.
13.2.2 Reset Process Modules
All modules which can enter, gate, or control the reset process are listed in Table 13-4
together with their type of contribution. The types of contribution are described in Table
13-5.
Table 13-4. Reset Process Modules
Module
Contribution Type
event
gating
control
Reset Generation Module
(MC_RGM)
Yes
Yes
Yes
Power Management Digital
Controller (PMC-Dig)
Yes
Yes
Yes
Mode Entry Module (MC_ME)
Yes
—
—
System Status and
Configuration Module (SSCM)
—
Yes
—
Self-Test Control Unit
Yes
—
—
Flash Memory
—
Yes
—
MC_CGM
—
Yes
—
Software Watchdog Timeout
(SWT0)
Yes
—
—
Table 13-5. Module Contribution Type
Contribution Type
Description
event
The module may generate events which may trigger the entry
into a reset state, if the event configuration in the MC_RGM
allows this.
gating
The module can prevent the exit of a reset state if it has not
reached a certain internal state.
control
The module controls the sequence of the reset process.
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13.2.2.1 Reset Generation Module (MC_RGM)
The MC_RGM is one of the two controlling module for the reset process. The MC_RGM
can receive events from other modules and starts the reset process based on the
configuration for these events. The event configuration defines the reset phase at which
start the reset process starts. The MC_RGM controls the reset process sequence based on
the gating information it receives from the gating modules.
13.2.2.2 Power Management Controller (PMC)
The PMC provides different voltage detect signals for the reset process control.
As long as the supply voltages are not reliable, the PMC provides following signals to
allow the device to enter the various phases of reset process. For details, refer Reset
sources
13.2.2.3 Mode Entry Module (MC_ME)
The MC_ME can generate events to enter the reset process. These events can be triggered
only by application software.
13.2.2.4 System Status and Configuration Module (SSCM)
The SSCM is started automatically during a specific phase of the reset process. The
SSCM fetches DCF records from the flash memory and distributes the read values via an
internal DCF bus to the related modules. As long as the SSCM is still fetching DCF
records, this specific reset phases can not be exited.
13.2.2.5 Self-Test Control Unit (STCU)
The STCU controls the execution of the start-up and shut-down self-test. Depending on
its configuration the STCU is started when PHASE3[DEST] is left or when software
triggers the self-test. The STCU generates a functional event when the self-testing has
been completed.
STCU can also generate a STCU unrecoverable fault (SUF). If this fault occurs during
start-up self test, it is intended to cause the start-up self test to be executed again. This is
done via a ‘destructive’ reset request , if it is not disabled through
UTEST_MISC[SUF_DIS]. If this fault occurs repeatedly, the ‘destructive’ reset escalator
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in the MC_RGM will increment until it finally keeps the chip in reset until the next
power-on reset. This is to prevent a start-up self-test pass that occurs after numerous
failures to allow an unreliable chip to start execution and thus become a safety risk.
If this fault occurs during on-line or shut-down self-test , the handling is done by the
FCCU. In this case, no ‘destructive’ reset request is generated.
13.2.2.6 Fault Collection and Control Unit (FCCU)
The FCCU generates reset events. Refer to Fault inputs for sources of fault. These can be
configured through FCCU register interface for generating reset event.
13.2.2.7 MC_CGM
PHASE3 RESET will not exit if all system dividers are not aligned. This is internally
checked by MC_CGM module.
13.2.2.8 Software Watchdog Timeout (SWT0)
SWT0 becomes active during PHASE2[FUNC]/PHASE2[DEST] RESET to monitor
flash initialization failure. During normal operation, the flash indicates that it has
completed its initialization process and exits PHASE2[FUNC]/PHASE2[DEST] RESET
in reset sequence process.
In order to ensure that this happens within a reasonable time, the SWT is brought out of
reset for PHASE2[FUNC]/PHASE2[DEST] RESET. So, if the SWT times out during this
time, the flash’s initialization sequence was not able to complete. This is also referred as
SWT0 (flash initialization error).
In order to trigger another attempt at initializing the flash, a ‘destructive’ reset is
generated. If it occurs repeatedly, the ‘destructive’ reset escalator in the MC_RGM will
increment until it finally keeps the chip in reset until the next power-on reset. This is to
prevent unnecessary power consumption due to reset cycling.
13.2.3 Reset Process Sequences
This section specifies the reset processes sequences. An overview of the reset process
sequences is given in the following figure. When the reset process has reached the IDLE
state, the device is operational.
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Global Reset Process
POWERUP
PHASE0
event
PHASE1[DEST]
event
PHASE2[DEST]
event
PHASE3[DEST]
event
no_self_test
SELFTEST
event
PHASE1[FUNC]
event
PHASE2[FUNC]
event
PHASE3[FUNC]
event
IDLE
application
event
Figure 13-1. Reset Process Sequences
13.2.4 Reset Process State Transitions
This sections specifies the transitions between the reset states in the reset process. For
each state, the state entry, the state execution, and the state exit is described.
13.2.4.1 POWERUP
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13.2.4.1.1
POWERUP State Entry
This state is entered from any state if at least one of the following events appear
• Power is applied to the unpowered device.
• PMC has detected a low power condition that is lower than the minimum operating
voltage
13.2.4.1.2
POWERUP State Execution
During this state, the PMC is waiting for stable power supply.
PMC will check that all logic domains are above min threshold voltage, referred as LVD,
and then release power up for MC_RGM
Output pins are undriven and inputs are at default value. For details on state of each pad
on reset, refer the device I/O Signal Description and Input Multiplexing tables attached to
this document as an Excel file.
13.2.4.1.3
POWERUP State Duration
There are no bounds on the duration of this state.
13.2.4.1.4
POWERUP State Exit
Table 13-6. POWERUP Next State Table
Next State
Condition
Process/Module Started at Exit
PHASE0
(1) The PORST pin is high in internal
regulation mode and transitions from low
to high when external supply is stable.
Refer to the device datasheet for
specifications.
FIRC
MC_RGM
PMC-Dig
MC_CGM
and
(2) the PMC module indicates all
supplies are in the operational range
NOTE
It is recommended to drive PORST pin when using external
regulation mode, such that when external VDD_LV is not
stable, PORST is driven LOW externally, and once VDD_LV is
stable, PORST is driven HIGH. Alternatively, another equally
robust solution is to connect PORST pin to VDD_HV_A
supply. In this latter case, multiple voltage monitor resets may
be seen during power-up/power-down in presence of a nonmonotonic VDD_LV supply.
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13.2.4.2 PHASE0
13.2.4.2.1
PHASE0 State Entry
This state can be entered whenever a destructive reset source is active. See Reset Sources
section of the Reset Generation Module (MC_RGM) chapter.
13.2.4.2.2
PHASE0 State Execution
All trimming bits are reset to their default values.
13.2.4.2.3
PHASE0 State Duration
The maximum state of this duration depends on when the gates of this phase are released.
Following are the gates which are required to be released
• FIRC stabilization counter should expire. Maximum count is 16 cycles of FIRC
untrimmed clock
13.2.4.2.4
PHASE0 State Exit
Table 13-7. PHASE0 Next State Table
Next State
PHASE1[DEST]
Condition
(1) The MC_RGM indicates that all
sources of enabled destructive reset
events are deasserted,
Process/Module Started at Exit
STCU
and
(2) the FIRC module indicates the
generation of a stable clock,
13.2.4.3 PHASE1[DEST]
13.2.4.3.1
PHASE1[DEST] State Entry
This state can be entered from state
• PHASE0,
• PHASE1[FUNC],
• PHASE2[FUNC],
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• PHASE3[FUNC],
• IDLE.
13.2.4.3.2
PHASE1[DEST] State Execution
There are no state changes in any module, only a counter in the MC_RGM is running.
13.2.4.3.3
PHASE1[DEST] State Duration
The duration of this state is 8 FIRC clock cycles.
13.2.4.3.4
PHASE1[DEST] State Exit
Table 13-8. PHASE1[DEST] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE2[DEST]
8 FIRC clocks passed by after state
entry.
Process/Module Started at Exit
FLASH
- starts initialization sequence
FCCU
- enters configuration state
13.2.4.4 PHASE2[DEST]
13.2.4.4.1
PHASE2[DEST] State Entry
This state can be entered from state
• PHASE1[DEST].
13.2.4.4.2
PHASE2[DEST] State Execution
FLASH executes initialization and confirms that it is ready for access. This information is
used to gate phase2.
13.2.4.4.3
PHASE2[DEST] State Duration
There is no counter in MC_RGM, it is completely gate dependent.
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13.2.4.4.4
PHASE2[DEST] State Exit
Table 13-9. PHASE2[DEST] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE3[DEST]
The FLASH module indicates that it is
ready for access.
Process/Module Started at Exit
SSCM
- starts device configuration and boot
location search
13.2.4.5 PHASE3[DEST]
13.2.4.5.1
PHASE3[DEST] State Entry
This state can be entered only from state
• PHASE2[DEST].
13.2.4.5.2
PHASE3[DEST] State Execution
SSCM runs device configuration and boot location search.
The PMC adjusts its LVD and HVD levels according to the DCF record content after
SSCM confirms that the DCF records are read from Flash.
Gates of phase3
• SSCM confirm DCF records are read from flash.
• HSM's RAM initialization is done.
• MC_CGM confirms that all system clock dividers are aligned.
• Flash is ready for access. This is again a gate for phase3 to ensure that flash is
available when a short functional reset occurs.
13.2.4.5.3
PHASE3[DEST] State Duration
Maximum duration of this phase is determined by the gates. Its duration can be extended
if external reset pin is kept asserted. Minimum phase duration is 40 FIRC clock cycles.
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13.2.4.5.4
PHASE3[DEST] State Exit
Table 13-10. PHASE3[DEST] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
SELFTEST
(1) The FLASH module indicates
availability of full speed array access,
and
(2) the SSCM module indicates device
configuration is done,
Process/Module Started at Exit
BIST on
- FCCU
- CORES
- PERIPHERALS
and
(3) the HSM module indicates that HSM
RAM initialization is done,
and
(4) the CGM module indicates that all
system clock dividers are aligned,
and
(5) the STCU module is configured to
execute a start-up self test.
IDLE
(1) The FLASH module indicates
availability of array access,
Z4A CORE
ALL OTHER PERIPHERALS
and
(2) the SSCM module indicates device
configuration is done,
and
(3) the HSM module indicates that HSM
RAM initialization is done,
and
(4) the CGM module indicates that all
system clock dividers are aligned.
13.2.4.6 SELFTEST
13.2.4.6.1
SELFTEST State Entry
This state can be entered only from state
• PHASE3[DEST],
• IDLE.
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13.2.4.6.2
SELFTEST State Execution
The start-up self test is executed as configured in the STCU by the DCF record content.
13.2.4.6.3
SELFTEST State Exit
Table 13-11. SELFTEST Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE1[FUNC]
STCU module indicates end of self test.
Process/Module Started at Exit
13.2.4.7 PHASE1[FUNC]
13.2.4.7.1
PHASE1[FUNC] State Entry
This state can be entered from states
• SELFTEST,
• PHASE3[FUNC],
• IDLE.
13.2.4.7.2
PHASE1[FUNC] State Execution
There are no state changes in any module, only a counter in the MC_RGM is running.
13.2.4.7.3
PHASE1[FUNC] State Duration
The duration of this state is 8 FIRC clock cycles.
13.2.4.7.4
PHASE1[FUNC] State Exit
Table 13-12. PHASE1[FUNC] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE1[DEST]
The MC_RGM has detected that the
source of the enabled long functional
external reset event is asserted.
Process/Module Started at Exit
Table continues on the next page...
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Table 13-12. PHASE1[FUNC] Next State Table (continued)
Next State
Condition
PHASE2[FUNC]
Process/Module Started at Exit
(1) The MC_RGM indicates that all
FLASH
sources of enabled long functional reset
- starts initialization sequence
events are deasserted,
FCCU
and
-enters configuration state
(2) 8 FIRC clocks passed by after state
entry.
13.2.4.8 PHASE2[FUNC]
13.2.4.8.1
PHASE2[FUNC] State Entry
This state can be entered from state
• PHASE1[FUNC].
13.2.4.8.2
PHASE2[FUNC] State Execution
Flash executes initialization for array access.
13.2.4.8.3
PHASE2[FUNC] State Duration
There is no counter in MC_RGM, it is completely gate dependent.
13.2.4.8.4
PHASE2[FUNC] State Exit
Table 13-13. PHASE2[FUNC] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE1[DEST]
The MC_RGM has detected that the
source of the enabled long functional
external reset event is asserted.
PHASE1[FUNC]
The MC_RGM has detected that the
sources of an enabled long functional
reset event is asserted.
PHASE3[FUNC]
The FLASH module indicates that it is
ready for access.
Process/Module Started at Exit
SSCM
- starts device configuration
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13.2.4.9 PHASE3[FUNC]
13.2.4.9.1
PHASE3[FUNC] State Entry
This state can be entered from states
• PHASE2[FUNC]
• IDLE
13.2.4.9.2
PHASE3[FUNC] State Execution
SSCM runs device configuration, if state was entered from PHASE2[FUNC].
The FCCU executes its configuration sequence if PHASE3[FUNC] was entered via the
SELFTEST state.
The FLASH indicates that it is ready for access.
13.2.4.9.3
PHASE3[FUNC] State Duration
Duration of this phase is determined by the gates. Its duration can be extended if external
reset pin is kept asserted.
13.2.4.9.4
PHASE3[FUNC] State Exit
Table 13-14. PHASE3[FUNC] Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE1[DEST]
The MC_RGM has detected that the
source of the enabled long functional
external reset event is asserted.
PHASE1[FUNC]
The MC_RGM has detected that the
sources of an enabled long functional
reset event is asserted.
IDLE
(1) The FLASH module indicates
availability of array access,
Process/Module Started at Exit
Z4A CORE
ALL OTHER PERIPHERALS
and
(2) the SSCM module indicates device
configuration is done,
and
(3) the HSM module indicates that HSM
RAM initialization is done
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Table 13-14. PHASE3[FUNC] Next State Table
Next State
Condition
Process/Module Started at Exit
and
(4) the CGM module indicates that all
system clock dividers are aligned.
13.2.4.10 IDLE
13.2.4.10.1
IDLE State Entry
The IDLE state can be entered only from states
• PHASE3[DEST]
• PHASE3[FUNC]
13.2.4.10.2
IDLE State Execution
During the IDLE state, the device is fully operational.
13.2.4.10.3
IDLE State Duration
There are no bounds on the duration of this state.
13.2.4.10.4
IDLE State Exit
The IDLE state next state table is shown in Table 13-15 the following table.
Table 13-15. IDLE Next State Table
Next State
Condition
PHASE0
The MC_RGM has detected that the
source of an enabled destructive reset
event is asserted.
PHASE1[DEST]
The MC_RGM has detected that the
source of the enabled long functional
external reset event is asserted.
PHASE1[FUNC]
The MC_RGM has detected that the
source of an enabled long functional
reset event is asserted.
PHASE3[FUNC]
The MC_RGM has detected that the
source of an enabled short functional
reset event is asserted.
SELFTEST
Process/Module Started at Exit
The application has triggered the start of
the shut-down selftest.
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13.2.5 Module Status During Reset Process
This section specifies in Table 13-16 the status of the device modules during the reset
process. The status abbreviation explained in Table 13-17.
Table 13-16. Module Status during reset states
Global Reset State
Module
POWER
UP
PHASE0
PHASE
1[DEST]
PHASE
2[DEST]
PHASE
3[DEST]
SELFTE
ST
PHASE
1[FUNC]
PHASE
2[FUNC]
PHASE
3[FUNC]
IDLE
PMC
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
FIRC
RST
ON
ON
ON
ON
ON
ON
ON
ON
ON
SIRC
RST
RST
ON
ON
ON
ON
ON
ON
ON
ON
MC_RGM
RST
ON
ON
ON
ON
ON
ON
ON
ON
ON
FXOSC
RST
RST
RST
RST
ON
ON
ON
ON
ON
ON
FLASH
RST
RST
RST
ON
ON
ON
RST
ON
ON
ON
FCCU
RST
RST
RST
ON
ON
BIST
RST
ON
ON
ON
RTC
RST
ON
ON
ON
ON
ON
ON
ON
ON
ON
STCU
RST
RST
RST
ON
ON
ON
ON
ON
ON
ON
Z4A
CORE
RST
RST
RST
RST
RST
BIST
RST
RST
RST
ON
OTHERS
RST
RST
RST
RST
RST
BIST
RST
RST
RST
ON
SWT0
RST
RST
RST
ON
RST
ON
RST
ON
RST
ON
Table 13-17. Module Status Glossary
Module Status
Status Description
RST
Module is held in reset by the global reset process
BIST
Module is being tested or held in a non-functional state during
self test execution as controlled by the STCU.
ON
Module is functional.
For information on impact of different phases of reset on individual modules, See
MPC5746C_Module_Reset_Status spreadsheet attached to this document.
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Chapter 13 Reset and Boot Overview
13.3 Boot
This following table lists the various conditions for booting the device.
Table 13-18. Booting conditions
Boot Condition
Booting Core
Boot vector
Power Up
Only Z4a
BAF code entry point - 0040_4100h
Exit from STANDBY/LPU_STANDBY to
DRUN
Any core based on configuration of
MC_ME_CCTLn
MC_ME_CADDRn
Exit from LPU STANDBY to LPU_RUN
Only Z2
SRAM_0 base address - 0x40000000
Entry from RUNx/DRUN to LPU_RUN
Only Z2
SRAM_0 base address - 0x40000000
13.3.1 Power Up
Refer BAF for details.
13.3.2 Exit from STANDBY/LPU_STANDBY to DRUN
MC_ME_CADDRn should be configured prior to entry into STANDBY or LPU modes.
13.3.2.1 Boot from RAM
SRAM location to be loaded in MC_ME_CADDRn. Standby exit to DRUN is faster if
Flash is kept power down by configuring MC_ME_DRUN_MC[FLAON] to 2'b01 prior
to entry into STANDBY or LPU modes.
13.3.2.2 Boot with BAF
Device can boot from BAF location, if the same is configured in MC_ME_CADDRn.
Flash should be powered ON in DRUN if booting vector resides in flash address range.
NOTE
While configuring the device to boot from BAF after standby
exit, it needs to be taken care of that UTEST_MISC[BAF_DIS]
is not set.
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13.3.3 Exit from LPU STANDBY to LPU_RUN
Refer Boot section.
13.3.4 Entry from RUNx/DRUN to LPU_RUN
Refer Boot section.
13.3.5 Interrupt Vector Prefix retention during STANDBY
In the Cores, the Interrupt Vector Prefix Register is used during interrupt processing for
determining the starting address of a software handler used to handle an interrupt.
However to use this IVPR feature on exit from STANDBY modes, the prefix value can
be programmed in GPR_CTL1[IVPR] before STANDBY entry.
This register defines the base location of the interrupt vector table to the two cores z4 and
z2.
When exiting Standby mode with boot vector pointing to RAM location, IVPR of the
cores can be directed to RAM address location.
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Chapter 14
Functional Safety
14.1 Introduction
The MPC5746C is developed according to ISO 26262 and has an integrated safety
concept targeting safety-related systems requiring high safety integrity levels. In order to
support the integration of the MPC5746C into safety-related systems, the following
documentation is available:
• Reference Manual (MPC5746CRM) - Describes the MPC5746C functionality
• Data Sheet (MPC5746CDS) - Describes the operating conditions
• Safety Manual (MPC5746CSM) - Describes the MPC5746C safety concept and
possible safety mechanisms (integrated in MPC5746C, system level hardware or
system level software), as well as measures to reduce dependent failures.
• Dynamic FMEDA - Inductive analysis enabling customization of system level safety
mechanisms, including the resulting safety metrics for ISO 26262 (SPFM, LFM and
PMHF) and IEC 61508 (SFF and Beta IC Factor)
• FMEDA Report - Describes the FMEDA methodology and safety mechanisms
supported in the FMEDA, including source of failure rates, failure modes and
assumptions made during the analysis.
The Dynamic FMEDA and FMEDA report are available upon request. The MPC5746C
is a SafeAssure solution; for further information regarding functional safety, visit
www.nxp.com/safeassure.
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Chapter 15
System Integration Unit Lite2 (SIUL2)
15.1 Introduction
15.1.1 Overview
The SIUL2 provides control over all the electrical pin controls and up to 32 ports with 16
bits of bidirectional, general-purpose input and output signals. One of the most important
functions of the SIUL2 is that it enables the user to select the functions and electrical
characteristics that appear on external device pins. It also controls the multiplexing of
internal signals from one module to another and controls device I/O. It supports up to 32
external interrupts with trigger event configuration.
The module provides dedicated pad control to general-purpose pads that can be
configured as either inputs or outputs. The SIUL2 module provides registers that enable
user software to read values from GPIO pads configured as inputs, and write values to
GPIO pads configured as outputs
• When configured as output, you can write to an internal register to control the state
driven on the associated output pad.
• When configured as input, you can detect the state of the associated pad by reading
the value from an internal register.
• When configured as input and output, the pad value can be read back, which can be
used as a method of checking if the written value appeared on the pad.
To assist software development, GPIO data registers can be accessed using various
mechanisms. These differing mechanisms allow support for port access or for bit
manipulation without the need to use read-modify-write operations or access with Power
Architecture reservation.
• Access to two 16 bit ports in one access
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• Read/write access to a single bit
• A 16-bit Port write with a bit mask, using single 32-bit access.
NOTE
For any unavailable MSCR, transfer error for peripheral access
will not be generated. However, 8- or 16- bit access to any valid
MSCR will result in a transfer error.
The external interrupt sources can be configured at the MCU level to be used with any
chip pad. From 0 to 31 of the interrupt sources can be configured to have a digital filter to
reject short glitches on the inputs. The external interrupt requests map to the REQ pins in
the device packages.
SIUL2 Module
IP Modules
Pad Control and Pin Muxing
MSCRs/
IMCRs
GPIO
IO
MUX
PADS
Data Registers
IPS
Master
IPS BUS
Interrupt
Interrupt
- Configuration
- Glitch Filter
Interrupt
Controller
Figure 15-1. SIUL2 block diagram
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Chapter 15 System Integration Unit Lite2 (SIUL2)
15.1.2 Features
The SIUL2 supports these distinctive features:
• 1 to 32 GPIO ports with data control
• Drive data to up to 16 independent I/O channels
• Sample data from up to 16 independent I/O channels
Two 16-bit registers can be read/written with one access for a 32-bit port, if needed.
External interrupt request support with:
• 0 to 3 system interrupt vectors for 0 to 31 interrupt sources with independent
interrupt masks. For 32 external interrupt sources (REQ pins), four groups have eight
interrupt sources each, and each of the four groups is assigned one system interrupt
vector.
• 0 to 31 programmable digital glitch filters, one for each REQ pin
• Edge detection
Additionally the SIUL2 contains the Multiplexed Signal Configuration Registers that
configure the electrical parameters and settings of up to 264 functional pads. The number
of these registers that is actually implemented varies by device. These registers configure
the following pad features:
• Drive strength
• Open drain/source output enable
• Slew rate control
• Hysteresis control
• Internal pull control and pull selection
• Pin function assignment
• Control of analog path switches
• Safe mode behavior configuration
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15.1.3 Register protection
The System Integration Unit Lite2 uses the Register Protection Scheme to protect the
individual registers from accidental writes. The following registers can be protected:
• SIUL2 Interrupt Request Enable Register 0 (SIUL2_IRER0)
• SIUL2 Interrupt Request Select Register 0 (SIUL2_IRSR0)
• SIUL2 Interrupt Rising-Edge Event Enable Register 0 (SIUL2_IREER0)
• SIUL2 Interrupt Falling-Edge Event Enable Register 0 (SIUL2_IFEER0)
• SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)
• SIUL2 Interrupt Filter Maximum Counter Register (SIUL2_IFMCR0 to
SIUL2_IFMCR31)
• SIUL2 Interrupt Filter Clock Prescaler Register (SIUL2_IFCPR)
• SIUL2 Multiplexed Single Configuration Register (SIUL2_MSCR0 to
SIUL2_MSCR263 and SIUL2_IMCR0 to SIUL2_IMCR511): Only the specific
MSCRs and IMCRs that are actually implemented on a device are protected.
• SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)
• SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDOn)
• SIUL2 Masked Parallel GPIO Pad Data Out Register (SIUL2_MPGPDOn)
A compiled list identifies the protected registers at specific addresses for this device.
Please refer the Register protection configuration.
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Chapter 15 System Integration Unit Lite2 (SIUL2)
15.2 Memory map and register description
This section provides a detailed description of all registers accessible in the SIUL module
in address order. Each description includes a standard register diagram. Details of register
bit and field function follow the register diagrams, in bit order. MIDRn, IFMCRn,
MSCRn, IFCP, MPGPDOn(writes) are 32-bit accessible only registers.
The following table gives an overview on the SIUL2 registers implemented.
NOTE
Undocumented register spaces in the SIUL2 memory map,
including addresses shown as "blank," are reserved. Reserved
registers read as 0, and writes to these registers have no effect.
A transfer error is issued for attempts to access a completely
reserved register space. A write to reserved register bit has no
effect.
SIUL2 memory map
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4
SIUL2 MCU ID Register #1 (SIUL2_MIDR1)
32
R
See section
15.2.1/340
8
SIUL2 MCU ID Register #2 (SIUL2_MIDR2)
32
R
3A00_4300h
15.2.2/341
10
SIUL2 Interrupt Status Flag Register0 (SIUL2_ISR0)
32
w1c
0000_0000h
15.2.3/342
18
SIUL2 Interrupt Request Enable Register0 (SIUL2_IRER0)
32
R/W
0000_0000h
15.2.4/346
20
SIUL2 Interrupt Request Select Register0 (SIUL2_IRSR0)
32
R/W
0000_0000h
15.2.5/349
28
SIUL2 Interrupt Rising-Edge Event Enable Register 0
(SIUL2_IREER0)
32
R/W
0000_0000h
15.2.6/352
30
SIUL2 Interrupt Falling-Edge Event Enable Register 0
(SIUL2_IFEER0)
32
R/W
0000_0000h
15.2.7/355
38
SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)
32
R/W
0000_0000h
15.2.8/358
40
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR0)
32
R/W
0000_0000h
15.2.9/360
44
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR1)
32
R/W
0000_0000h
15.2.9/360
48
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR2)
32
R/W
0000_0000h
15.2.9/360
4C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR3)
32
R/W
0000_0000h
15.2.9/360
50
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR4)
32
R/W
0000_0000h
15.2.9/360
Table continues on the next page...
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Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
54
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR5)
32
R/W
0000_0000h
15.2.9/360
58
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR6)
32
R/W
0000_0000h
15.2.9/360
5C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR7)
32
R/W
0000_0000h
15.2.9/360
60
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR8)
32
R/W
0000_0000h
15.2.9/360
64
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR9)
32
R/W
0000_0000h
15.2.9/360
68
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR10)
32
R/W
0000_0000h
15.2.9/360
6C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR11)
32
R/W
0000_0000h
15.2.9/360
70
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR12)
32
R/W
0000_0000h
15.2.9/360
74
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR13)
32
R/W
0000_0000h
15.2.9/360
78
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR14)
32
R/W
0000_0000h
15.2.9/360
7C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR15)
32
R/W
0000_0000h
15.2.9/360
80
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR16)
32
R/W
0000_0000h
15.2.9/360
84
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR17)
32
R/W
0000_0000h
15.2.9/360
88
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR18)
32
R/W
0000_0000h
15.2.9/360
8C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR19)
32
R/W
0000_0000h
15.2.9/360
90
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR20)
32
R/W
0000_0000h
15.2.9/360
94
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR21)
32
R/W
0000_0000h
15.2.9/360
98
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR22)
32
R/W
0000_0000h
15.2.9/360
9C
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR23)
32
R/W
0000_0000h
15.2.9/360
A0
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR24)
32
R/W
0000_0000h
15.2.9/360
A4
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR25)
32
R/W
0000_0000h
15.2.9/360
A8
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR26)
32
R/W
0000_0000h
15.2.9/360
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
AC
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR27)
32
R/W
0000_0000h
15.2.9/360
B0
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR28)
32
R/W
0000_0000h
15.2.9/360
B4
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR29)
32
R/W
0000_0000h
15.2.9/360
B8
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR30)
32
R/W
0000_0000h
15.2.9/360
BC
SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCR31)
32
R/W
0000_0000h
15.2.9/360
C0
SIUL2 Interrupt Filter Clock Prescaler Register
(SIUL2_IFCPR)
32
R/W
0000_0000h
15.2.10/361
240
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR0)
32
R/W
See section
15.2.11/362
244
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR1)
32
R/W
See section
15.2.11/362
248
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR2)
32
R/W
See section
15.2.11/362
24C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR3)
32
R/W
See section
15.2.11/362
250
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR4)
32
R/W
See section
15.2.11/362
254
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR5)
32
R/W
See section
15.2.11/362
258
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR6)
32
R/W
See section
15.2.11/362
25C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR7)
32
R/W
See section
15.2.11/362
260
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR8)
32
R/W
See section
15.2.11/362
264
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR9)
32
R/W
See section
15.2.11/362
268
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR10)
32
R/W
See section
15.2.11/362
26C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR11)
32
R/W
See section
15.2.11/362
270
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR12)
32
R/W
See section
15.2.11/362
274
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR13)
32
R/W
See section
15.2.11/362
278
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR14)
32
R/W
See section
15.2.11/362
27C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR15)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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295
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
280
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR16)
32
R/W
See section
15.2.11/362
284
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR17)
32
R/W
See section
15.2.11/362
288
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR18)
32
R/W
See section
15.2.11/362
28C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR19)
32
R/W
See section
15.2.11/362
290
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR20)
32
R/W
See section
15.2.11/362
294
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR21)
32
R/W
See section
15.2.11/362
298
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR22)
32
R/W
See section
15.2.11/362
29C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR23)
32
R/W
See section
15.2.11/362
2A0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR24)
32
R/W
See section
15.2.11/362
2A4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR25)
32
R/W
See section
15.2.11/362
2A8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR26)
32
R/W
See section
15.2.11/362
2AC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR27)
32
R/W
See section
15.2.11/362
2B0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR28)
32
R/W
See section
15.2.11/362
2B4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR29)
32
R/W
See section
15.2.11/362
2B8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR30)
32
R/W
See section
15.2.11/362
2BC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR31)
32
R/W
See section
15.2.11/362
2C0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR32)
32
R/W
See section
15.2.11/362
2C4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR33)
32
R/W
See section
15.2.11/362
2C8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR34)
32
R/W
See section
15.2.11/362
2CC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR35)
32
R/W
See section
15.2.11/362
2D0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR36)
32
R/W
See section
15.2.11/362
2D4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR37)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
2D8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR38)
32
R/W
See section
15.2.11/362
2DC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR39)
32
R/W
See section
15.2.11/362
2E0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR40)
32
R/W
See section
15.2.11/362
2E4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR41)
32
R/W
See section
15.2.11/362
2E8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR42)
32
R/W
See section
15.2.11/362
2EC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR43)
32
R/W
See section
15.2.11/362
2F0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR44)
32
R/W
See section
15.2.11/362
2F4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR45)
32
R/W
See section
15.2.11/362
2F8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR46)
32
R/W
See section
15.2.11/362
2FC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR47)
32
R/W
See section
15.2.11/362
300
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR48)
32
R/W
See section
15.2.11/362
304
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR49)
32
R/W
See section
15.2.11/362
308
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR50)
32
R/W
See section
15.2.11/362
30C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR51)
32
R/W
See section
15.2.11/362
310
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR52)
32
R/W
See section
15.2.11/362
314
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR53)
32
R/W
See section
15.2.11/362
318
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR54)
32
R/W
See section
15.2.11/362
31C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR55)
32
R/W
See section
15.2.11/362
320
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR56)
32
R/W
See section
15.2.11/362
324
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR57)
32
R/W
See section
15.2.11/362
328
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR58)
32
R/W
See section
15.2.11/362
32C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR59)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
330
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR60)
32
R/W
See section
15.2.11/362
334
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR61)
32
R/W
See section
15.2.11/362
338
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR62)
32
R/W
See section
15.2.11/362
33C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR63)
32
R/W
See section
15.2.11/362
340
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR64)
32
R/W
See section
15.2.11/362
344
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR65)
32
R/W
See section
15.2.11/362
348
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR66)
32
R/W
See section
15.2.11/362
34C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR67)
32
R/W
See section
15.2.11/362
350
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR68)
32
R/W
See section
15.2.11/362
354
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR69)
32
R/W
See section
15.2.11/362
358
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR70)
32
R/W
See section
15.2.11/362
35C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR71)
32
R/W
See section
15.2.11/362
360
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR72)
32
R/W
See section
15.2.11/362
364
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR73)
32
R/W
See section
15.2.11/362
368
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR74)
32
R/W
See section
15.2.11/362
36C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR75)
32
R/W
See section
15.2.11/362
370
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR76)
32
R/W
See section
15.2.11/362
374
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR77)
32
R/W
See section
15.2.11/362
378
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR78)
32
R/W
See section
15.2.11/362
37C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR79)
32
R/W
See section
15.2.11/362
380
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR80)
32
R/W
See section
15.2.11/362
384
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR81)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
388
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR82)
32
R/W
See section
15.2.11/362
38C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR83)
32
R/W
See section
15.2.11/362
390
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR84)
32
R/W
See section
15.2.11/362
394
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR85)
32
R/W
See section
15.2.11/362
398
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR86)
32
R/W
See section
15.2.11/362
39C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR87)
32
R/W
See section
15.2.11/362
3A0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR88)
32
R/W
See section
15.2.11/362
3A4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR89)
32
R/W
See section
15.2.11/362
3A8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR90)
32
R/W
See section
15.2.11/362
3AC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR91)
32
R/W
See section
15.2.11/362
3B0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR92)
32
R/W
See section
15.2.11/362
3B4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR93)
32
R/W
See section
15.2.11/362
3B8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR94)
32
R/W
See section
15.2.11/362
3BC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR95)
32
R/W
See section
15.2.11/362
3C0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR96)
32
R/W
See section
15.2.11/362
3C4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR97)
32
R/W
See section
15.2.11/362
3C8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR98)
32
R/W
See section
15.2.11/362
3CC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR99)
32
R/W
See section
15.2.11/362
3D0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR100)
32
R/W
See section
15.2.11/362
3D4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR101)
32
R/W
See section
15.2.11/362
3D8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR102)
32
R/W
See section
15.2.11/362
3DC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR103)
32
R/W
See section
15.2.11/362
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
299
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
3E0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR104)
32
R/W
See section
15.2.11/362
3E4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR105)
32
R/W
See section
15.2.11/362
3E8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR106)
32
R/W
See section
15.2.11/362
3EC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR107)
32
R/W
See section
15.2.11/362
3F0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR108)
32
R/W
See section
15.2.11/362
3F4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR109)
32
R/W
See section
15.2.11/362
3F8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR110)
32
R/W
See section
15.2.11/362
3FC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR111)
32
R/W
See section
15.2.11/362
400
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR112)
32
R/W
See section
15.2.11/362
404
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR113)
32
R/W
See section
15.2.11/362
408
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR114)
32
R/W
See section
15.2.11/362
40C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR115)
32
R/W
See section
15.2.11/362
410
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR116)
32
R/W
See section
15.2.11/362
414
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR117)
32
R/W
See section
15.2.11/362
418
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR118)
32
R/W
See section
15.2.11/362
41C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR119)
32
R/W
See section
15.2.11/362
420
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR120)
32
R/W
See section
15.2.11/362
424
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR121)
32
R/W
See section
15.2.11/362
428
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR122)
32
R/W
See section
15.2.11/362
42C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR123)
32
R/W
See section
15.2.11/362
430
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR124)
32
R/W
See section
15.2.11/362
434
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR125)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
438
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR126)
32
R/W
See section
15.2.11/362
43C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR127)
32
R/W
See section
15.2.11/362
440
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR128)
32
R/W
See section
15.2.11/362
444
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR129)
32
R/W
See section
15.2.11/362
448
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR130)
32
R/W
See section
15.2.11/362
44C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR131)
32
R/W
See section
15.2.11/362
450
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR132)
32
R/W
See section
15.2.11/362
454
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR133)
32
R/W
See section
15.2.11/362
458
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR134)
32
R/W
See section
15.2.11/362
45C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR135)
32
R/W
See section
15.2.11/362
460
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR136)
32
R/W
See section
15.2.11/362
464
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR137)
32
R/W
See section
15.2.11/362
468
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR138)
32
R/W
See section
15.2.11/362
46C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR139)
32
R/W
See section
15.2.11/362
470
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR140)
32
R/W
See section
15.2.11/362
474
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR141)
32
R/W
See section
15.2.11/362
478
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR142)
32
R/W
See section
15.2.11/362
47C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR143)
32
R/W
See section
15.2.11/362
480
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR144)
32
R/W
See section
15.2.11/362
484
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR145)
32
R/W
See section
15.2.11/362
488
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR146)
32
R/W
See section
15.2.11/362
48C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR147)
32
R/W
See section
15.2.11/362
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
301
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
490
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR148)
32
R/W
See section
15.2.11/362
494
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR149)
32
R/W
See section
15.2.11/362
498
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR150)
32
R/W
See section
15.2.11/362
49C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR151)
32
R/W
See section
15.2.11/362
4A0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR152)
32
R/W
See section
15.2.11/362
4A4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR153)
32
R/W
See section
15.2.11/362
4A8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR154)
32
R/W
See section
15.2.11/362
4AC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR155)
32
R/W
See section
15.2.11/362
4B0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR156)
32
R/W
See section
15.2.11/362
4B4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR157)
32
R/W
See section
15.2.11/362
4B8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR158)
32
R/W
See section
15.2.11/362
4BC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR159)
32
R/W
See section
15.2.11/362
4C0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR160)
32
R/W
See section
15.2.11/362
4C4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR161)
32
R/W
See section
15.2.11/362
4C8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR162)
32
R/W
See section
15.2.11/362
4CC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR163)
32
R/W
See section
15.2.11/362
4D0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR164)
32
R/W
See section
15.2.11/362
4D4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR165)
32
R/W
See section
15.2.11/362
4D8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR166)
32
R/W
See section
15.2.11/362
4DC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR167)
32
R/W
See section
15.2.11/362
4E0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR168)
32
R/W
See section
15.2.11/362
4E4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR169)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
4E8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR170)
32
R/W
See section
15.2.11/362
4EC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR171)
32
R/W
See section
15.2.11/362
4F0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR172)
32
R/W
See section
15.2.11/362
4F4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR173)
32
R/W
See section
15.2.11/362
4F8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR174)
32
R/W
See section
15.2.11/362
4FC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR175)
32
R/W
See section
15.2.11/362
500
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR176)
32
R/W
See section
15.2.11/362
504
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR177)
32
R/W
See section
15.2.11/362
508
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR178)
32
R/W
See section
15.2.11/362
50C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR179)
32
R/W
See section
15.2.11/362
510
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR180)
32
R/W
See section
15.2.11/362
514
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR181)
32
R/W
See section
15.2.11/362
518
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR182)
32
R/W
See section
15.2.11/362
51C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR183)
32
R/W
See section
15.2.11/362
520
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR184)
32
R/W
See section
15.2.11/362
524
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR185)
32
R/W
See section
15.2.11/362
528
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR186)
32
R/W
See section
15.2.11/362
52C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR187)
32
R/W
See section
15.2.11/362
530
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR188)
32
R/W
See section
15.2.11/362
534
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR189)
32
R/W
See section
15.2.11/362
538
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR190)
32
R/W
See section
15.2.11/362
53C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR191)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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NXP Semiconductors
303
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
540
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR192)
32
R/W
See section
15.2.11/362
544
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR193)
32
R/W
See section
15.2.11/362
548
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR194)
32
R/W
See section
15.2.11/362
54C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR195)
32
R/W
See section
15.2.11/362
550
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR196)
32
R/W
See section
15.2.11/362
554
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR197)
32
R/W
See section
15.2.11/362
558
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR198)
32
R/W
See section
15.2.11/362
55C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR199)
32
R/W
See section
15.2.11/362
560
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR200)
32
R/W
See section
15.2.11/362
564
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR201)
32
R/W
See section
15.2.11/362
568
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR202)
32
R/W
See section
15.2.11/362
56C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR203)
32
R/W
See section
15.2.11/362
570
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR204)
32
R/W
See section
15.2.11/362
574
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR205)
32
R/W
See section
15.2.11/362
578
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR206)
32
R/W
See section
15.2.11/362
57C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR207)
32
R/W
See section
15.2.11/362
580
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR208)
32
R/W
See section
15.2.11/362
584
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR209)
32
R/W
See section
15.2.11/362
588
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR210)
32
R/W
See section
15.2.11/362
58C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR211)
32
R/W
See section
15.2.11/362
590
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR212)
32
R/W
See section
15.2.11/362
594
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR213)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
598
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR214)
32
R/W
See section
15.2.11/362
59C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR215)
32
R/W
See section
15.2.11/362
5A0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR216)
32
R/W
See section
15.2.11/362
5A4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR217)
32
R/W
See section
15.2.11/362
5A8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR218)
32
R/W
See section
15.2.11/362
5AC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR219)
32
R/W
See section
15.2.11/362
5B0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR220)
32
R/W
See section
15.2.11/362
5B4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR221)
32
R/W
See section
15.2.11/362
5B8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR222)
32
R/W
See section
15.2.11/362
5BC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR223)
32
R/W
See section
15.2.11/362
5C0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR224)
32
R/W
See section
15.2.11/362
5C4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR225)
32
R/W
See section
15.2.11/362
5C8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR226)
32
R/W
See section
15.2.11/362
5CC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR227)
32
R/W
See section
15.2.11/362
5D0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR228)
32
R/W
See section
15.2.11/362
5D4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR229)
32
R/W
See section
15.2.11/362
5D8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR230)
32
R/W
See section
15.2.11/362
5DC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR231)
32
R/W
See section
15.2.11/362
5E0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR232)
32
R/W
See section
15.2.11/362
5E4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR233)
32
R/W
See section
15.2.11/362
5E8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR234)
32
R/W
See section
15.2.11/362
5EC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR235)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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NXP Semiconductors
305
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
5F0
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR236)
32
R/W
See section
15.2.11/362
5F4
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR237)
32
R/W
See section
15.2.11/362
5F8
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR238)
32
R/W
See section
15.2.11/362
5FC
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR239)
32
R/W
See section
15.2.11/362
600
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR240)
32
R/W
See section
15.2.11/362
604
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR241)
32
R/W
See section
15.2.11/362
608
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR242)
32
R/W
See section
15.2.11/362
60C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR243)
32
R/W
See section
15.2.11/362
610
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR244)
32
R/W
See section
15.2.11/362
614
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR245)
32
R/W
See section
15.2.11/362
618
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR246)
32
R/W
See section
15.2.11/362
61C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR247)
32
R/W
See section
15.2.11/362
620
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR248)
32
R/W
See section
15.2.11/362
624
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR249)
32
R/W
See section
15.2.11/362
628
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR250)
32
R/W
See section
15.2.11/362
62C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR251)
32
R/W
See section
15.2.11/362
630
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR252)
32
R/W
See section
15.2.11/362
634
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR253)
32
R/W
See section
15.2.11/362
638
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR254)
32
R/W
See section
15.2.11/362
63C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR255)
32
R/W
See section
15.2.11/362
640
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR256)
32
R/W
See section
15.2.11/362
644
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR257)
32
R/W
See section
15.2.11/362
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
648
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR258)
32
R/W
See section
15.2.11/362
64C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR259)
32
R/W
See section
15.2.11/362
650
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR260)
32
R/W
See section
15.2.11/362
654
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR261)
32
R/W
See section
15.2.11/362
658
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR262)
32
R/W
See section
15.2.11/362
65C
SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCR263)
32
R/W
See section
15.2.11/362
A40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR0)
32
R/W
See section
15.2.12/364
A44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR1)
32
R/W
See section
15.2.12/364
A48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR2)
32
R/W
See section
15.2.12/364
A4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR3)
32
R/W
See section
15.2.12/364
A50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR4)
32
R/W
See section
15.2.12/364
A54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR5)
32
R/W
See section
15.2.12/364
A58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR6)
32
R/W
See section
15.2.12/364
A5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR7)
32
R/W
See section
15.2.12/364
A60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR8)
32
R/W
See section
15.2.12/364
A64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR9)
32
R/W
See section
15.2.12/364
A68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR10)
32
R/W
See section
15.2.12/364
A6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR11)
32
R/W
See section
15.2.12/364
A70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR12)
32
R/W
See section
15.2.12/364
A74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR13)
32
R/W
See section
15.2.12/364
A78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR14)
32
R/W
See section
15.2.12/364
A7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR15)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
307
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
A80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR16)
32
R/W
See section
15.2.12/364
A84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR17)
32
R/W
See section
15.2.12/364
A88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR18)
32
R/W
See section
15.2.12/364
A8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR19)
32
R/W
See section
15.2.12/364
A90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR20)
32
R/W
See section
15.2.12/364
A94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR21)
32
R/W
See section
15.2.12/364
A98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR22)
32
R/W
See section
15.2.12/364
A9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR23)
32
R/W
See section
15.2.12/364
AA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR24)
32
R/W
See section
15.2.12/364
AA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR25)
32
R/W
See section
15.2.12/364
AA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR26)
32
R/W
See section
15.2.12/364
AAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR27)
32
R/W
See section
15.2.12/364
AB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR28)
32
R/W
See section
15.2.12/364
AB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR29)
32
R/W
See section
15.2.12/364
AB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR30)
32
R/W
See section
15.2.12/364
ABC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR31)
32
R/W
See section
15.2.12/364
AC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR32)
32
R/W
See section
15.2.12/364
AC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR33)
32
R/W
See section
15.2.12/364
AC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR34)
32
R/W
See section
15.2.12/364
ACC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR35)
32
R/W
See section
15.2.12/364
AD0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR36)
32
R/W
See section
15.2.12/364
AD4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR37)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
AD8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR38)
32
R/W
See section
15.2.12/364
ADC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR39)
32
R/W
See section
15.2.12/364
AE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR40)
32
R/W
See section
15.2.12/364
AE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR41)
32
R/W
See section
15.2.12/364
AE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR42)
32
R/W
See section
15.2.12/364
AEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR43)
32
R/W
See section
15.2.12/364
AF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR44)
32
R/W
See section
15.2.12/364
AF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR45)
32
R/W
See section
15.2.12/364
AF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR46)
32
R/W
See section
15.2.12/364
AFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR47)
32
R/W
See section
15.2.12/364
B00
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR48)
32
R/W
See section
15.2.12/364
B04
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR49)
32
R/W
See section
15.2.12/364
B08
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR50)
32
R/W
See section
15.2.12/364
B0C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR51)
32
R/W
See section
15.2.12/364
B10
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR52)
32
R/W
See section
15.2.12/364
B14
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR53)
32
R/W
See section
15.2.12/364
B18
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR54)
32
R/W
See section
15.2.12/364
B1C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR55)
32
R/W
See section
15.2.12/364
B20
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR56)
32
R/W
See section
15.2.12/364
B24
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR57)
32
R/W
See section
15.2.12/364
B28
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR58)
32
R/W
See section
15.2.12/364
B2C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR59)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
309
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
B30
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR60)
32
R/W
See section
15.2.12/364
B34
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR61)
32
R/W
See section
15.2.12/364
B38
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR62)
32
R/W
See section
15.2.12/364
B3C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR63)
32
R/W
See section
15.2.12/364
B40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR64)
32
R/W
See section
15.2.12/364
B44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR65)
32
R/W
See section
15.2.12/364
B48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR66)
32
R/W
See section
15.2.12/364
B4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR67)
32
R/W
See section
15.2.12/364
B50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR68)
32
R/W
See section
15.2.12/364
B54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR69)
32
R/W
See section
15.2.12/364
B58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR70)
32
R/W
See section
15.2.12/364
B5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR71)
32
R/W
See section
15.2.12/364
B60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR72)
32
R/W
See section
15.2.12/364
B64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR73)
32
R/W
See section
15.2.12/364
B68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR74)
32
R/W
See section
15.2.12/364
B6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR75)
32
R/W
See section
15.2.12/364
B70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR76)
32
R/W
See section
15.2.12/364
B74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR77)
32
R/W
See section
15.2.12/364
B78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR78)
32
R/W
See section
15.2.12/364
B7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR79)
32
R/W
See section
15.2.12/364
B80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR80)
32
R/W
See section
15.2.12/364
B84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR81)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
B88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR82)
32
R/W
See section
15.2.12/364
B8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR83)
32
R/W
See section
15.2.12/364
B90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR84)
32
R/W
See section
15.2.12/364
B94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR85)
32
R/W
See section
15.2.12/364
B98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR86)
32
R/W
See section
15.2.12/364
B9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR87)
32
R/W
See section
15.2.12/364
BA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR88)
32
R/W
See section
15.2.12/364
BA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR89)
32
R/W
See section
15.2.12/364
BA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR90)
32
R/W
See section
15.2.12/364
BAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR91)
32
R/W
See section
15.2.12/364
BB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR92)
32
R/W
See section
15.2.12/364
BB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR93)
32
R/W
See section
15.2.12/364
BB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR94)
32
R/W
See section
15.2.12/364
BBC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR95)
32
R/W
See section
15.2.12/364
BC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR96)
32
R/W
See section
15.2.12/364
BC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR97)
32
R/W
See section
15.2.12/364
BC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR98)
32
R/W
See section
15.2.12/364
BCC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR99)
32
R/W
See section
15.2.12/364
BD0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR100)
32
R/W
See section
15.2.12/364
BD4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR101)
32
R/W
See section
15.2.12/364
BD8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR102)
32
R/W
See section
15.2.12/364
BDC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR103)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
311
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
BE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR104)
32
R/W
See section
15.2.12/364
BE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR105)
32
R/W
See section
15.2.12/364
BE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR106)
32
R/W
See section
15.2.12/364
BEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR107)
32
R/W
See section
15.2.12/364
BF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR108)
32
R/W
See section
15.2.12/364
BF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR109)
32
R/W
See section
15.2.12/364
BF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR110)
32
R/W
See section
15.2.12/364
BFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR111)
32
R/W
See section
15.2.12/364
C00
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR112)
32
R/W
See section
15.2.12/364
C04
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR113)
32
R/W
See section
15.2.12/364
C08
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR114)
32
R/W
See section
15.2.12/364
C0C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR115)
32
R/W
See section
15.2.12/364
C10
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR116)
32
R/W
See section
15.2.12/364
C14
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR117)
32
R/W
See section
15.2.12/364
C18
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR118)
32
R/W
See section
15.2.12/364
C1C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR119)
32
R/W
See section
15.2.12/364
C20
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR120)
32
R/W
See section
15.2.12/364
C24
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR121)
32
R/W
See section
15.2.12/364
C28
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR122)
32
R/W
See section
15.2.12/364
C2C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR123)
32
R/W
See section
15.2.12/364
C30
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR124)
32
R/W
See section
15.2.12/364
C34
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR125)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
C38
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR126)
32
R/W
See section
15.2.12/364
C3C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR127)
32
R/W
See section
15.2.12/364
C40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR128)
32
R/W
See section
15.2.12/364
C44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR129)
32
R/W
See section
15.2.12/364
C48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR130)
32
R/W
See section
15.2.12/364
C4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR131)
32
R/W
See section
15.2.12/364
C50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR132)
32
R/W
See section
15.2.12/364
C54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR133)
32
R/W
See section
15.2.12/364
C58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR134)
32
R/W
See section
15.2.12/364
C5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR135)
32
R/W
See section
15.2.12/364
C60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR136)
32
R/W
See section
15.2.12/364
C64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR137)
32
R/W
See section
15.2.12/364
C68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR138)
32
R/W
See section
15.2.12/364
C6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR139)
32
R/W
See section
15.2.12/364
C70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR140)
32
R/W
See section
15.2.12/364
C74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR141)
32
R/W
See section
15.2.12/364
C78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR142)
32
R/W
See section
15.2.12/364
C7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR143)
32
R/W
See section
15.2.12/364
C80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR144)
32
R/W
See section
15.2.12/364
C84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR145)
32
R/W
See section
15.2.12/364
C88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR146)
32
R/W
See section
15.2.12/364
C8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR147)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
313
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
C90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR148)
32
R/W
See section
15.2.12/364
C94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR149)
32
R/W
See section
15.2.12/364
C98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR150)
32
R/W
See section
15.2.12/364
C9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR151)
32
R/W
See section
15.2.12/364
CA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR152)
32
R/W
See section
15.2.12/364
CA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR153)
32
R/W
See section
15.2.12/364
CA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR154)
32
R/W
See section
15.2.12/364
CAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR155)
32
R/W
See section
15.2.12/364
CB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR156)
32
R/W
See section
15.2.12/364
CB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR157)
32
R/W
See section
15.2.12/364
CB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR158)
32
R/W
See section
15.2.12/364
CBC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR159)
32
R/W
See section
15.2.12/364
CC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR160)
32
R/W
See section
15.2.12/364
CC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR161)
32
R/W
See section
15.2.12/364
CC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR162)
32
R/W
See section
15.2.12/364
CCC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR163)
32
R/W
See section
15.2.12/364
CD0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR164)
32
R/W
See section
15.2.12/364
CD4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR165)
32
R/W
See section
15.2.12/364
CD8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR166)
32
R/W
See section
15.2.12/364
CDC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR167)
32
R/W
See section
15.2.12/364
CE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR168)
32
R/W
See section
15.2.12/364
CE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR169)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
CE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR170)
32
R/W
See section
15.2.12/364
CEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR171)
32
R/W
See section
15.2.12/364
CF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR172)
32
R/W
See section
15.2.12/364
CF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR173)
32
R/W
See section
15.2.12/364
CF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR174)
32
R/W
See section
15.2.12/364
CFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR175)
32
R/W
See section
15.2.12/364
D00
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR176)
32
R/W
See section
15.2.12/364
D04
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR177)
32
R/W
See section
15.2.12/364
D08
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR178)
32
R/W
See section
15.2.12/364
D0C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR179)
32
R/W
See section
15.2.12/364
D10
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR180)
32
R/W
See section
15.2.12/364
D14
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR181)
32
R/W
See section
15.2.12/364
D18
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR182)
32
R/W
See section
15.2.12/364
D1C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR183)
32
R/W
See section
15.2.12/364
D20
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR184)
32
R/W
See section
15.2.12/364
D24
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR185)
32
R/W
See section
15.2.12/364
D28
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR186)
32
R/W
See section
15.2.12/364
D2C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR187)
32
R/W
See section
15.2.12/364
D30
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR188)
32
R/W
See section
15.2.12/364
D34
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR189)
32
R/W
See section
15.2.12/364
D38
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR190)
32
R/W
See section
15.2.12/364
D3C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR191)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
315
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
D40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR192)
32
R/W
See section
15.2.12/364
D44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR193)
32
R/W
See section
15.2.12/364
D48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR194)
32
R/W
See section
15.2.12/364
D4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR195)
32
R/W
See section
15.2.12/364
D50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR196)
32
R/W
See section
15.2.12/364
D54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR197)
32
R/W
See section
15.2.12/364
D58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR198)
32
R/W
See section
15.2.12/364
D5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR199)
32
R/W
See section
15.2.12/364
D60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR200)
32
R/W
See section
15.2.12/364
D64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR201)
32
R/W
See section
15.2.12/364
D68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR202)
32
R/W
See section
15.2.12/364
D6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR203)
32
R/W
See section
15.2.12/364
D70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR204)
32
R/W
See section
15.2.12/364
D74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR205)
32
R/W
See section
15.2.12/364
D78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR206)
32
R/W
See section
15.2.12/364
D7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR207)
32
R/W
See section
15.2.12/364
D80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR208)
32
R/W
See section
15.2.12/364
D84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR209)
32
R/W
See section
15.2.12/364
D88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR210)
32
R/W
See section
15.2.12/364
D8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR211)
32
R/W
See section
15.2.12/364
D90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR212)
32
R/W
See section
15.2.12/364
D94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR213)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
D98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR214)
32
R/W
See section
15.2.12/364
D9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR215)
32
R/W
See section
15.2.12/364
DA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR216)
32
R/W
See section
15.2.12/364
DA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR217)
32
R/W
See section
15.2.12/364
DA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR218)
32
R/W
See section
15.2.12/364
DAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR219)
32
R/W
See section
15.2.12/364
DB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR220)
32
R/W
See section
15.2.12/364
DB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR221)
32
R/W
See section
15.2.12/364
DB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR222)
32
R/W
See section
15.2.12/364
DBC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR223)
32
R/W
See section
15.2.12/364
DC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR224)
32
R/W
See section
15.2.12/364
DC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR225)
32
R/W
See section
15.2.12/364
DC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR226)
32
R/W
See section
15.2.12/364
DCC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR227)
32
R/W
See section
15.2.12/364
DD0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR228)
32
R/W
See section
15.2.12/364
DD4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR229)
32
R/W
See section
15.2.12/364
DD8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR230)
32
R/W
See section
15.2.12/364
DDC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR231)
32
R/W
See section
15.2.12/364
DE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR232)
32
R/W
See section
15.2.12/364
DE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR233)
32
R/W
See section
15.2.12/364
DE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR234)
32
R/W
See section
15.2.12/364
DEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR235)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
317
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
DF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR236)
32
R/W
See section
15.2.12/364
DF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR237)
32
R/W
See section
15.2.12/364
DF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR238)
32
R/W
See section
15.2.12/364
DFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR239)
32
R/W
See section
15.2.12/364
E00
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR240)
32
R/W
See section
15.2.12/364
E04
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR241)
32
R/W
See section
15.2.12/364
E08
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR242)
32
R/W
See section
15.2.12/364
E0C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR243)
32
R/W
See section
15.2.12/364
E10
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR244)
32
R/W
See section
15.2.12/364
E14
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR245)
32
R/W
See section
15.2.12/364
E18
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR246)
32
R/W
See section
15.2.12/364
E1C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR247)
32
R/W
See section
15.2.12/364
E20
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR248)
32
R/W
See section
15.2.12/364
E24
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR249)
32
R/W
See section
15.2.12/364
E28
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR250)
32
R/W
See section
15.2.12/364
E2C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR251)
32
R/W
See section
15.2.12/364
E30
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR252)
32
R/W
See section
15.2.12/364
E34
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR253)
32
R/W
See section
15.2.12/364
E38
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR254)
32
R/W
See section
15.2.12/364
E3C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR255)
32
R/W
See section
15.2.12/364
E40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR256)
32
R/W
See section
15.2.12/364
E44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR257)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
E48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR258)
32
R/W
See section
15.2.12/364
E4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR259)
32
R/W
See section
15.2.12/364
E50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR260)
32
R/W
See section
15.2.12/364
E54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR261)
32
R/W
See section
15.2.12/364
E58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR262)
32
R/W
See section
15.2.12/364
E5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR263)
32
R/W
See section
15.2.12/364
E60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR264)
32
R/W
See section
15.2.12/364
E64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR265)
32
R/W
See section
15.2.12/364
E68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR266)
32
R/W
See section
15.2.12/364
E6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR267)
32
R/W
See section
15.2.12/364
E70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR268)
32
R/W
See section
15.2.12/364
E74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR269)
32
R/W
See section
15.2.12/364
E78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR270)
32
R/W
See section
15.2.12/364
E7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR271)
32
R/W
See section
15.2.12/364
E80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR272)
32
R/W
See section
15.2.12/364
E84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR273)
32
R/W
See section
15.2.12/364
E88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR274)
32
R/W
See section
15.2.12/364
E8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR275)
32
R/W
See section
15.2.12/364
E90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR276)
32
R/W
See section
15.2.12/364
E94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR277)
32
R/W
See section
15.2.12/364
E98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR278)
32
R/W
See section
15.2.12/364
E9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR279)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
319
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
EA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR280)
32
R/W
See section
15.2.12/364
EA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR281)
32
R/W
See section
15.2.12/364
EA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR282)
32
R/W
See section
15.2.12/364
EAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR283)
32
R/W
See section
15.2.12/364
EB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR284)
32
R/W
See section
15.2.12/364
EB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR285)
32
R/W
See section
15.2.12/364
EB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR286)
32
R/W
See section
15.2.12/364
EBC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR287)
32
R/W
See section
15.2.12/364
EC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR288)
32
R/W
See section
15.2.12/364
EC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR289)
32
R/W
See section
15.2.12/364
EC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR290)
32
R/W
See section
15.2.12/364
ECC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR291)
32
R/W
See section
15.2.12/364
ED0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR292)
32
R/W
See section
15.2.12/364
ED4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR293)
32
R/W
See section
15.2.12/364
ED8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR294)
32
R/W
See section
15.2.12/364
EDC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR295)
32
R/W
See section
15.2.12/364
EE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR296)
32
R/W
See section
15.2.12/364
EE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR297)
32
R/W
See section
15.2.12/364
EE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR298)
32
R/W
See section
15.2.12/364
EEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR299)
32
R/W
See section
15.2.12/364
EF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR300)
32
R/W
See section
15.2.12/364
EF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR301)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
EF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR302)
32
R/W
See section
15.2.12/364
EFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR303)
32
R/W
See section
15.2.12/364
F00
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR304)
32
R/W
See section
15.2.12/364
F04
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR305)
32
R/W
See section
15.2.12/364
F08
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR306)
32
R/W
See section
15.2.12/364
F0C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR307)
32
R/W
See section
15.2.12/364
F10
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR308)
32
R/W
See section
15.2.12/364
F14
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR309)
32
R/W
See section
15.2.12/364
F18
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR310)
32
R/W
See section
15.2.12/364
F1C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR311)
32
R/W
See section
15.2.12/364
F20
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR312)
32
R/W
See section
15.2.12/364
F24
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR313)
32
R/W
See section
15.2.12/364
F28
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR314)
32
R/W
See section
15.2.12/364
F2C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR315)
32
R/W
See section
15.2.12/364
F30
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR316)
32
R/W
See section
15.2.12/364
F34
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR317)
32
R/W
See section
15.2.12/364
F38
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR318)
32
R/W
See section
15.2.12/364
F3C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR319)
32
R/W
See section
15.2.12/364
F40
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR320)
32
R/W
See section
15.2.12/364
F44
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR321)
32
R/W
See section
15.2.12/364
F48
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR322)
32
R/W
See section
15.2.12/364
F4C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR323)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
321
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
F50
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR324)
32
R/W
See section
15.2.12/364
F54
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR325)
32
R/W
See section
15.2.12/364
F58
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR326)
32
R/W
See section
15.2.12/364
F5C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR327)
32
R/W
See section
15.2.12/364
F60
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR328)
32
R/W
See section
15.2.12/364
F64
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR329)
32
R/W
See section
15.2.12/364
F68
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR330)
32
R/W
See section
15.2.12/364
F6C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR331)
32
R/W
See section
15.2.12/364
F70
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR332)
32
R/W
See section
15.2.12/364
F74
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR333)
32
R/W
See section
15.2.12/364
F78
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR334)
32
R/W
See section
15.2.12/364
F7C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR335)
32
R/W
See section
15.2.12/364
F80
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR336)
32
R/W
See section
15.2.12/364
F84
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR337)
32
R/W
See section
15.2.12/364
F88
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR338)
32
R/W
See section
15.2.12/364
F8C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR339)
32
R/W
See section
15.2.12/364
F90
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR340)
32
R/W
See section
15.2.12/364
F94
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR341)
32
R/W
See section
15.2.12/364
F98
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR342)
32
R/W
See section
15.2.12/364
F9C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR343)
32
R/W
See section
15.2.12/364
FA0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR344)
32
R/W
See section
15.2.12/364
FA4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR345)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
FA8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR346)
32
R/W
See section
15.2.12/364
FAC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR347)
32
R/W
See section
15.2.12/364
FB0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR348)
32
R/W
See section
15.2.12/364
FB4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR349)
32
R/W
See section
15.2.12/364
FB8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR350)
32
R/W
See section
15.2.12/364
FBC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR351)
32
R/W
See section
15.2.12/364
FC0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR352)
32
R/W
See section
15.2.12/364
FC4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR353)
32
R/W
See section
15.2.12/364
FC8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR354)
32
R/W
See section
15.2.12/364
FCC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR355)
32
R/W
See section
15.2.12/364
FD0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR356)
32
R/W
See section
15.2.12/364
FD4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR357)
32
R/W
See section
15.2.12/364
FD8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR358)
32
R/W
See section
15.2.12/364
FDC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR359)
32
R/W
See section
15.2.12/364
FE0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR360)
32
R/W
See section
15.2.12/364
FE4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR361)
32
R/W
See section
15.2.12/364
FE8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR362)
32
R/W
See section
15.2.12/364
FEC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR363)
32
R/W
See section
15.2.12/364
FF0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR364)
32
R/W
See section
15.2.12/364
FF4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR365)
32
R/W
See section
15.2.12/364
FF8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR366)
32
R/W
See section
15.2.12/364
FFC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR367)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
323
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1000
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR368)
32
R/W
See section
15.2.12/364
1004
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR369)
32
R/W
See section
15.2.12/364
1008
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR370)
32
R/W
See section
15.2.12/364
100C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR371)
32
R/W
See section
15.2.12/364
1010
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR372)
32
R/W
See section
15.2.12/364
1014
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR373)
32
R/W
See section
15.2.12/364
1018
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR374)
32
R/W
See section
15.2.12/364
101C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR375)
32
R/W
See section
15.2.12/364
1020
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR376)
32
R/W
See section
15.2.12/364
1024
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR377)
32
R/W
See section
15.2.12/364
1028
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR378)
32
R/W
See section
15.2.12/364
102C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR379)
32
R/W
See section
15.2.12/364
1030
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR380)
32
R/W
See section
15.2.12/364
1034
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR381)
32
R/W
See section
15.2.12/364
1038
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR382)
32
R/W
See section
15.2.12/364
103C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR383)
32
R/W
See section
15.2.12/364
1040
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR384)
32
R/W
See section
15.2.12/364
1044
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR385)
32
R/W
See section
15.2.12/364
1048
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR386)
32
R/W
See section
15.2.12/364
104C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR387)
32
R/W
See section
15.2.12/364
1050
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR388)
32
R/W
See section
15.2.12/364
1054
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR389)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1058
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR390)
32
R/W
See section
15.2.12/364
105C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR391)
32
R/W
See section
15.2.12/364
1060
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR392)
32
R/W
See section
15.2.12/364
1064
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR393)
32
R/W
See section
15.2.12/364
1068
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR394)
32
R/W
See section
15.2.12/364
106C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR395)
32
R/W
See section
15.2.12/364
1070
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR396)
32
R/W
See section
15.2.12/364
1074
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR397)
32
R/W
See section
15.2.12/364
1078
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR398)
32
R/W
See section
15.2.12/364
107C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR399)
32
R/W
See section
15.2.12/364
1080
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR400)
32
R/W
See section
15.2.12/364
1084
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR401)
32
R/W
See section
15.2.12/364
1088
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR402)
32
R/W
See section
15.2.12/364
108C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR403)
32
R/W
See section
15.2.12/364
1090
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR404)
32
R/W
See section
15.2.12/364
1094
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR405)
32
R/W
See section
15.2.12/364
1098
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR406)
32
R/W
See section
15.2.12/364
109C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR407)
32
R/W
See section
15.2.12/364
10A0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR408)
32
R/W
See section
15.2.12/364
10A4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR409)
32
R/W
See section
15.2.12/364
10A8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR410)
32
R/W
See section
15.2.12/364
10AC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR411)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
325
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
10B0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR412)
32
R/W
See section
15.2.12/364
10B4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR413)
32
R/W
See section
15.2.12/364
10B8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR414)
32
R/W
See section
15.2.12/364
10BC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR415)
32
R/W
See section
15.2.12/364
10C0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR416)
32
R/W
See section
15.2.12/364
10C4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR417)
32
R/W
See section
15.2.12/364
10C8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR418)
32
R/W
See section
15.2.12/364
10CC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR419)
32
R/W
See section
15.2.12/364
10D0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR420)
32
R/W
See section
15.2.12/364
10D4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR421)
32
R/W
See section
15.2.12/364
10D8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR422)
32
R/W
See section
15.2.12/364
10DC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR423)
32
R/W
See section
15.2.12/364
10E0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR424)
32
R/W
See section
15.2.12/364
10E4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR425)
32
R/W
See section
15.2.12/364
10E8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR426)
32
R/W
See section
15.2.12/364
10EC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR427)
32
R/W
See section
15.2.12/364
10F0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR428)
32
R/W
See section
15.2.12/364
10F4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR429)
32
R/W
See section
15.2.12/364
10F8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR430)
32
R/W
See section
15.2.12/364
10FC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR431)
32
R/W
See section
15.2.12/364
1100
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR432)
32
R/W
See section
15.2.12/364
1104
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR433)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1108
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR434)
32
R/W
See section
15.2.12/364
110C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR435)
32
R/W
See section
15.2.12/364
1110
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR436)
32
R/W
See section
15.2.12/364
1114
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR437)
32
R/W
See section
15.2.12/364
1118
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR438)
32
R/W
See section
15.2.12/364
111C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR439)
32
R/W
See section
15.2.12/364
1120
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR440)
32
R/W
See section
15.2.12/364
1124
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR441)
32
R/W
See section
15.2.12/364
1128
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR442)
32
R/W
See section
15.2.12/364
112C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR443)
32
R/W
See section
15.2.12/364
1130
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR444)
32
R/W
See section
15.2.12/364
1134
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR445)
32
R/W
See section
15.2.12/364
1138
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR446)
32
R/W
See section
15.2.12/364
113C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR447)
32
R/W
See section
15.2.12/364
1140
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR448)
32
R/W
See section
15.2.12/364
1144
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR449)
32
R/W
See section
15.2.12/364
1148
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR450)
32
R/W
See section
15.2.12/364
114C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR451)
32
R/W
See section
15.2.12/364
1150
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR452)
32
R/W
See section
15.2.12/364
1154
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR453)
32
R/W
See section
15.2.12/364
1158
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR454)
32
R/W
See section
15.2.12/364
115C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR455)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
327
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1160
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR456)
32
R/W
See section
15.2.12/364
1164
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR457)
32
R/W
See section
15.2.12/364
1168
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR458)
32
R/W
See section
15.2.12/364
116C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR459)
32
R/W
See section
15.2.12/364
1170
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR460)
32
R/W
See section
15.2.12/364
1174
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR461)
32
R/W
See section
15.2.12/364
1178
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR462)
32
R/W
See section
15.2.12/364
117C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR463)
32
R/W
See section
15.2.12/364
1180
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR464)
32
R/W
See section
15.2.12/364
1184
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR465)
32
R/W
See section
15.2.12/364
1188
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR466)
32
R/W
See section
15.2.12/364
118C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR467)
32
R/W
See section
15.2.12/364
1190
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR468)
32
R/W
See section
15.2.12/364
1194
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR469)
32
R/W
See section
15.2.12/364
1198
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR470)
32
R/W
See section
15.2.12/364
119C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR471)
32
R/W
See section
15.2.12/364
11A0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR472)
32
R/W
See section
15.2.12/364
11A4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR473)
32
R/W
See section
15.2.12/364
11A8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR474)
32
R/W
See section
15.2.12/364
11AC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR475)
32
R/W
See section
15.2.12/364
11B0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR476)
32
R/W
See section
15.2.12/364
11B4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR477)
32
R/W
See section
15.2.12/364
Table continues on the next page...
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NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
11B8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR478)
32
R/W
See section
15.2.12/364
11BC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR479)
32
R/W
See section
15.2.12/364
11C0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR480)
32
R/W
See section
15.2.12/364
11C4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR481)
32
R/W
See section
15.2.12/364
11C8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR482)
32
R/W
See section
15.2.12/364
11CC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR483)
32
R/W
See section
15.2.12/364
11D0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR484)
32
R/W
See section
15.2.12/364
11D4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR485)
32
R/W
See section
15.2.12/364
11D8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR486)
32
R/W
See section
15.2.12/364
11DC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR487)
32
R/W
See section
15.2.12/364
11E0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR488)
32
R/W
See section
15.2.12/364
11E4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR489)
32
R/W
See section
15.2.12/364
11E8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR490)
32
R/W
See section
15.2.12/364
11EC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR491)
32
R/W
See section
15.2.12/364
11F0
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR492)
32
R/W
See section
15.2.12/364
11F4
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR493)
32
R/W
See section
15.2.12/364
11F8
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR494)
32
R/W
See section
15.2.12/364
11FC
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR495)
32
R/W
See section
15.2.12/364
1200
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR496)
32
R/W
See section
15.2.12/364
1204
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR497)
32
R/W
See section
15.2.12/364
1208
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR498)
32
R/W
See section
15.2.12/364
120C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR499)
32
R/W
See section
15.2.12/364
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
329
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1210
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR500)
32
R/W
See section
15.2.12/364
1214
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR501)
32
R/W
See section
15.2.12/364
1218
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR502)
32
R/W
See section
15.2.12/364
121C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR503)
32
R/W
See section
15.2.12/364
1220
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR504)
32
R/W
See section
15.2.12/364
1224
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR505)
32
R/W
See section
15.2.12/364
1228
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR506)
32
R/W
See section
15.2.12/364
122C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR507)
32
R/W
See section
15.2.12/364
1230
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR508)
32
R/W
See section
15.2.12/364
1234
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR509)
32
R/W
See section
15.2.12/364
1238
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR510)
32
R/W
See section
15.2.12/364
123C
SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCR511)
32
R/W
See section
15.2.12/364
1300
SIUL2 GPIO Pad Data Output Register (SIUL2_GPDO0_3)
32
R/W
0000_0000h
15.2.13/367
1304
SIUL2 GPIO Pad Data Output Register (SIUL2_GPDO4_7)
32
R/W
0000_0000h
15.2.13/367
1308
SIUL2 GPIO Pad Data Output Register (SIUL2_GPDO8_11)
32
R/W
0000_0000h
15.2.13/367
130C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO12_15)
32
R/W
0000_0000h
15.2.13/367
1310
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO16_19)
32
R/W
0000_0000h
15.2.13/367
1314
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO20_23)
32
R/W
0000_0000h
15.2.13/367
1318
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO24_27)
32
R/W
0000_0000h
15.2.13/367
131C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO28_31)
32
R/W
0000_0000h
15.2.13/367
1320
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO32_35)
32
R/W
0000_0000h
15.2.13/367
1324
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO36_39)
32
R/W
0000_0000h
15.2.13/367
1328
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO40_43)
32
R/W
0000_0000h
15.2.13/367
132C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO44_47)
32
R/W
0000_0000h
15.2.13/367
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
330
NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1330
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO48_51)
32
R/W
0000_0000h
15.2.13/367
1334
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO52_55)
32
R/W
0000_0000h
15.2.13/367
1338
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO56_59)
32
R/W
0000_0000h
15.2.13/367
133C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO60_63)
32
R/W
0000_0000h
15.2.13/367
1340
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO64_67)
32
R/W
0000_0000h
15.2.13/367
1344
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO68_71)
32
R/W
0000_0000h
15.2.13/367
1348
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO72_75)
32
R/W
0000_0000h
15.2.13/367
134C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO76_79)
32
R/W
0000_0000h
15.2.13/367
1350
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO80_83)
32
R/W
0000_0000h
15.2.13/367
1354
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO84_87)
32
R/W
0000_0000h
15.2.13/367
1358
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO88_91)
32
R/W
0000_0000h
15.2.13/367
135C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO92_95)
32
R/W
0000_0000h
15.2.13/367
1360
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO96_99)
32
R/W
0000_0000h
15.2.13/367
1364
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO100_103)
32
R/W
0000_0000h
15.2.13/367
1368
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO104_107)
32
R/W
0000_0000h
15.2.13/367
136C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO108_111)
32
R/W
0000_0000h
15.2.13/367
1370
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO112_115)
32
R/W
0000_0000h
15.2.13/367
1374
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO116_119)
32
R/W
0000_0000h
15.2.13/367
1378
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO120_123)
32
R/W
0000_0000h
15.2.13/367
137C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO124_127)
32
R/W
0000_0000h
15.2.13/367
1380
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO128_131)
32
R/W
0000_0000h
15.2.13/367
1384
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO132_135)
32
R/W
0000_0000h
15.2.13/367
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
331
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1388
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO136_139)
32
R/W
0000_0000h
15.2.13/367
138C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO140_143)
32
R/W
0000_0000h
15.2.13/367
1390
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO144_147)
32
R/W
0000_0000h
15.2.13/367
1394
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO148_151)
32
R/W
0000_0000h
15.2.13/367
1398
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO152_155)
32
R/W
0000_0000h
15.2.13/367
139C
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO156_159)
32
R/W
0000_0000h
15.2.13/367
13A0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO160_163)
32
R/W
0000_0000h
15.2.13/367
13A4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO164_167)
32
R/W
0000_0000h
15.2.13/367
13A8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO168_171)
32
R/W
0000_0000h
15.2.13/367
13AC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO172_175)
32
R/W
0000_0000h
15.2.13/367
13B0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO176_179)
32
R/W
0000_0000h
15.2.13/367
13B4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO180_183)
32
R/W
0000_0000h
15.2.13/367
13B8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO184_187)
32
R/W
0000_0000h
15.2.13/367
13BC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO188_191)
32
R/W
0000_0000h
15.2.13/367
13C0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO192_195)
32
R/W
0000_0000h
15.2.13/367
13C4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO196_199)
32
R/W
0000_0000h
15.2.13/367
13C8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO200_203)
32
R/W
0000_0000h
15.2.13/367
13CC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO204_207)
32
R/W
0000_0000h
15.2.13/367
13D0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO208_211)
32
R/W
0000_0000h
15.2.13/367
13D4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO212_215)
32
R/W
0000_0000h
15.2.13/367
13D8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO216_219)
32
R/W
0000_0000h
15.2.13/367
13DC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO220_223)
32
R/W
0000_0000h
15.2.13/367
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
332
NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
13E0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO224_227)
32
R/W
0000_0000h
15.2.13/367
13E4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO228_231)
32
R/W
0000_0000h
15.2.13/367
13E8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO232_235)
32
R/W
0000_0000h
15.2.13/367
13EC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO236_239)
32
R/W
0000_0000h
15.2.13/367
13F0
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO240_243)
32
R/W
0000_0000h
15.2.13/367
13F4
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO244_247)
32
R/W
0000_0000h
15.2.13/367
13F8
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO248_251)
32
R/W
0000_0000h
15.2.13/367
13FC
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO252_255)
32
R/W
0000_0000h
15.2.13/367
1400
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO256_259)
32
R/W
0000_0000h
15.2.13/367
1404
SIUL2 GPIO Pad Data Output Register
(SIUL2_GPDO260_263)
32
R/W
0000_0000h
15.2.13/367
1500
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI0_3)
32
R
0000_0000h
15.2.14/368
1504
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI4_7)
32
R
0000_0000h
15.2.14/368
1508
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI8_11)
32
R
0000_0000h
15.2.14/368
150C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI12_15)
32
R
0000_0000h
15.2.14/368
1510
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI16_19)
32
R
0000_0000h
15.2.14/368
1514
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI20_23)
32
R
0000_0000h
15.2.14/368
1518
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI24_27)
32
R
0000_0000h
15.2.14/368
151C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI28_31)
32
R
0000_0000h
15.2.14/368
1520
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI32_35)
32
R
0000_0000h
15.2.14/368
1524
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI36_39)
32
R
0000_0000h
15.2.14/368
1528
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI40_43)
32
R
0000_0000h
15.2.14/368
152C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI44_47)
32
R
0000_0000h
15.2.14/368
1530
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI48_51)
32
R
0000_0000h
15.2.14/368
1534
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI52_55)
32
R
0000_0000h
15.2.14/368
1538
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI56_59)
32
R
0000_0000h
15.2.14/368
153C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI60_63)
32
R
0000_0000h
15.2.14/368
1540
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI64_67)
32
R
0000_0000h
15.2.14/368
1544
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI68_71)
32
R
0000_0000h
15.2.14/368
1548
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI72_75)
32
R
0000_0000h
15.2.14/368
154C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI76_79)
32
R
0000_0000h
15.2.14/368
1550
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI80_83)
32
R
0000_0000h
15.2.14/368
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
333
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1554
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI84_87)
32
R
0000_0000h
15.2.14/368
1558
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI88_91)
32
R
0000_0000h
15.2.14/368
155C
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI92_95)
32
R
0000_0000h
15.2.14/368
1560
SIUL2 GPIO Pad Data Input Register (SIUL2_GPDI96_99)
32
R
0000_0000h
15.2.14/368
1564
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI100_103)
32
R
0000_0000h
15.2.14/368
1568
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI104_107)
32
R
0000_0000h
15.2.14/368
156C
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI108_111)
32
R
0000_0000h
15.2.14/368
1570
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI112_115)
32
R
0000_0000h
15.2.14/368
1574
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI116_119)
32
R
0000_0000h
15.2.14/368
1578
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI120_123)
32
R
0000_0000h
15.2.14/368
157C
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI124_127)
32
R
0000_0000h
15.2.14/368
1580
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI128_131)
32
R
0000_0000h
15.2.14/368
1584
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI132_135)
32
R
0000_0000h
15.2.14/368
1588
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI136_139)
32
R
0000_0000h
15.2.14/368
158C
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI140_143)
32
R
0000_0000h
15.2.14/368
1590
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI144_147)
32
R
0000_0000h
15.2.14/368
1594
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI148_151)
32
R
0000_0000h
15.2.14/368
1598
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI152_155)
32
R
0000_0000h
15.2.14/368
159C
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI156_159)
32
R
0000_0000h
15.2.14/368
15A0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI160_163)
32
R
0000_0000h
15.2.14/368
15A4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI164_167)
32
R
0000_0000h
15.2.14/368
15A8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI168_171)
32
R
0000_0000h
15.2.14/368
15AC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI172_175)
32
R
0000_0000h
15.2.14/368
15B0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI176_179)
32
R
0000_0000h
15.2.14/368
Table continues on the next page...
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334
NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
15B4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI180_183)
32
R
0000_0000h
15.2.14/368
15B8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI184_187)
32
R
0000_0000h
15.2.14/368
15BC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI188_191)
32
R
0000_0000h
15.2.14/368
15C0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI192_195)
32
R
0000_0000h
15.2.14/368
15C4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI196_199)
32
R
0000_0000h
15.2.14/368
15C8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI200_203)
32
R
0000_0000h
15.2.14/368
15CC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI204_207)
32
R
0000_0000h
15.2.14/368
15D0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI208_211)
32
R
0000_0000h
15.2.14/368
15D4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI212_215)
32
R
0000_0000h
15.2.14/368
15D8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI216_219)
32
R
0000_0000h
15.2.14/368
15DC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI220_223)
32
R
0000_0000h
15.2.14/368
15E0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI224_227)
32
R
0000_0000h
15.2.14/368
15E4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI228_231)
32
R
0000_0000h
15.2.14/368
15E8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI232_235)
32
R
0000_0000h
15.2.14/368
15EC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI236_239)
32
R
0000_0000h
15.2.14/368
15F0
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI240_243)
32
R
0000_0000h
15.2.14/368
15F4
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI244_247)
32
R
0000_0000h
15.2.14/368
15F8
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI248_251)
32
R
0000_0000h
15.2.14/368
15FC
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI252_255)
32
R
0000_0000h
15.2.14/368
1600
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI256_259)
32
R
0000_0000h
15.2.14/368
1604
SIUL2 GPIO Pad Data Input Register
(SIUL2_GPDI260_263)
32
R
0000_0000h
15.2.14/368
1700
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO0)
16
R/W
0000h
15.2.15/370
Table continues on the next page...
MPC5746C Reference Manual, Rev. 6.1, 01/2019
NXP Semiconductors
335
Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1702
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO1)
16
R/W
0000h
15.2.15/370
1704
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO2)
16
R/W
0000h
15.2.15/370
1706
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO3)
16
R/W
0000h
15.2.15/370
1708
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO4)
16
R/W
0000h
15.2.15/370
170A
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO5)
16
R/W
0000h
15.2.15/370
170C
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO6)
16
R/W
0000h
15.2.15/370
170E
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO7)
16
R/W
0000h
15.2.15/370
1710
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO8)
16
R/W
0000h
15.2.15/370
1712
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO9)
16
R/W
0000h
15.2.15/370
1714
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO10)
16
R/W
0000h
15.2.15/370
1716
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO11)
16
R/W
0000h
15.2.15/370
1718
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO12)
16
R/W
0000h
15.2.15/370
171A
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO13)
16
R/W
0000h
15.2.15/370
171C
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO14)
16
R/W
0000h
15.2.15/370
171E
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO15)
16
R/W
0000h
15.2.15/370
1720
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO16)
16
R/W
0000h
15.2.15/370
1722
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO17)
16
R/W
0000h
15.2.15/370
1724
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO18)
16
R/W
0000h
15.2.15/370
1726
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO19)
16
R/W
0000h
15.2.15/370
1728
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO20)
16
R/W
0000h
15.2.15/370
172A
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO21)
16
R/W
0000h
15.2.15/370
172C
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO22)
16
R/W
0000h
15.2.15/370
Table continues on the next page...
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NXP Semiconductors
Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
172E
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO23)
16
R/W
0000h
15.2.15/370
1730
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO24)
16
R/W
0000h
15.2.15/370
1732
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO25)
16
R/W
0000h
15.2.15/370
1734
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO26)
16
R/W
0000h
15.2.15/370
1736
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO27)
16
R/W
0000h
15.2.15/370
1738
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO28)
16
R/W
0000h
15.2.15/370
173A
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO29)
16
R/W
0000h
15.2.15/370
173C
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO30)
16
R/W
0000h
15.2.15/370
173E
SIUL2 Parallel GPIO Pad Data Out Register
(SIUL2_PGPDO31)
16
R/W
0000h
15.2.15/370
1740
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI0)
16
R
0000h
15.2.16/371
1742
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI1)
16
R
0000h
15.2.16/371
1744
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI2)
16
R
0000h
15.2.16/371
1746
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI3)
16
R
0000h
15.2.16/371
1748
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI4)
16
R
0000h
15.2.16/371
174A
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI5)
16
R
0000h
15.2.16/371
174C
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI6)
16
R
0000h
15.2.16/371
174E
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI7)
16
R
0000h
15.2.16/371
1750
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI8)
16
R
0000h
15.2.16/371
1752
SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDI9)
16
R
0000h
15.2.16/371
1754
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI10)
16
R
0000h
15.2.16/371
1756
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI11)
16
R
0000h
15.2.16/371
1758
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI12)
16
R
0000h
15.2.16/371
175A
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI13)
16
R
0000h
15.2.16/371
175C
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI14)
16
R
0000h
15.2.16/371
175E
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI15)
16
R
0000h
15.2.16/371
1760
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI16)
16
R
0000h
15.2.16/371
1762
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI17)
16
R
0000h
15.2.16/371
Table continues on the next page...
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Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
1764
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI18)
16
R
0000h
15.2.16/371
1766
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI19)
16
R
0000h
15.2.16/371
1768
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI20)
16
R
0000h
15.2.16/371
176A
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI21)
16
R
0000h
15.2.16/371
176C
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI22)
16
R
0000h
15.2.16/371
176E
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI23)
16
R
0000h
15.2.16/371
1770
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI24)
16
R
0000h
15.2.16/371
1772
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI25)
16
R
0000h
15.2.16/371
1774
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI26)
16
R
0000h
15.2.16/371
1776
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI27)
16
R
0000h
15.2.16/371
1778
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI28)
16
R
0000h
15.2.16/371
177A
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI29)
16
R
0000h
15.2.16/371
177C
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI30)
16
R
0000h
15.2.16/371
177E
SIUL2 Parallel GPIO Pad Data In Register
(SIUL2_PGPDI31)
16
R
0000h
15.2.16/371
1780
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO0)
32
W
0000_0000h
15.2.17/371
1784
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO1)
32
W
0000_0000h
15.2.17/371
1788
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO2)
32
W
0000_0000h
15.2.17/371
178C
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO3)
32
W
0000_0000h
15.2.17/371
1790
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO4)
32
W
0000_0000h
15.2.17/371
1794
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO5)
32
W
0000_0000h
15.2.17/371
1798
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO6)
32
W
0000_0000h
15.2.17/371
179C
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO7)
32
W
0000_0000h
15.2.17/371
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2 memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
17A0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO8)
32
W
0000_0000h
15.2.17/371
17A4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO9)
32
W
0000_0000h
15.2.17/371
17A8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO10)
32
W
0000_0000h
15.2.17/371
17AC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO11)
32
W
0000_0000h
15.2.17/371
17B0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO12)
32
W
0000_0000h
15.2.17/371
17B4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO13)
32
W
0000_0000h
15.2.17/371
17B8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO14)
32
W
0000_0000h
15.2.17/371
17BC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO15)
32
W
0000_0000h
15.2.17/371
17C0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO16)
32
W
0000_0000h
15.2.17/371
17C4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO17)
32
W
0000_0000h
15.2.17/371
17C8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO18)
32
W
0000_0000h
15.2.17/371
17CC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO19)
32
W
0000_0000h
15.2.17/371
17D0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO20)
32
W
0000_0000h
15.2.17/371
17D4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO21)
32
W
0000_0000h
15.2.17/371
17D8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO22)
32
W
0000_0000h
15.2.17/371
17DC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO23)
32
W
0000_0000h
15.2.17/371
17E0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO24)
32
W
0000_0000h
15.2.17/371
17E4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO25)
32
W
0000_0000h
15.2.17/371
17E8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO26)
32
W
0000_0000h
15.2.17/371
17EC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO27)
32
W
0000_0000h
15.2.17/371
17F0
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO28)
32
W
0000_0000h
15.2.17/371
17F4
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO29)
32
W
0000_0000h
15.2.17/371
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Memory map and register description
SIUL2 memory map (continued)
Address
offset (hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
17F8
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO30)
32
W
0000_0000h
15.2.17/371
17FC
SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDO31)
32
W
0000_0000h
15.2.17/371
15.2.1 SIUL2 MCU ID Register #1 (SIUL2_MIDR1)
This register holds identification information about the device.
Address: 0h base + 4h offset = 4h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PARTNUM
R
W
Reset
0
1
0
1
0
1
1
1
0
1
0
0
0
1
1
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
PKG
0
MAJOR_MASK
MINOR_MASK
W
Reset
0
*
*
*
*
*
0
0
*
*
*
*
*
*
*
*
* Notes:
• MINOR_MASK field: * indicates Value is set at factory and cannot be changed.
• MAJOR_MASK field: * indicates Value is set at factory and cannot be changed.
• PKG field: * indicates Value is set at factory and cannot be changed.
SIUL2_MIDR1 field descriptions
Field
0–15
PARTNUM
Description
MCU Family 5746
For the full part number this field must be combined with MIDR2.PARTNUM[23:16]
Value is set at factory and cannot be changed.
16
Reserved
17–21
PKG
This field is reserved.
This read-only field is reserved and always has the value 0.
Package Settings
Can be read by software to determine the package type that is used for the particular device:
10100 : 324-ball BGA
01100 : 256-ball BGA
10001 : 176-pin QFP
01000 : 100-ball BGA
Value is set at factory and cannot be changed
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2_MIDR1 field descriptions (continued)
Field
Description
22–23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24–27
MAJOR_MASK
Major Mask Revision
28–31
MINOR_MASK
Minor Mask Revision
Value is set at factory and increments with each revision of device.
Value is set at factory and increments with each revision of device.
15.2.2 SIUL2 MCU ID Register #2 (SIUL2_MIDR2)
Address: 0h base + 8h offset = 8h
Bit
0
R
0
1
2
3
4
5
FLASH_SIZE_1
6
7
8
9
10
11
12
FLASH_SIZE_2
13
14
15
0
W
Reset
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
PARTNUM
R
0
W
Reset
0
1
0
0
0
0
1
1
0
0
0
0
SIUL2_MIDR2 field descriptions
Field
0
Reserved
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
1–4
Maximum Flash size of the MCU family (part1)
FLASH_SIZE_1
Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2:
0111 2M
Value is set at factory and cannot be changed.
All other bit combinations are reserved.
5–8
Maximum Flash size of the MCU family (part2)
FLASH_SIZE_2
Total flash memory size = FLASH_SIZE_1 + FLASH_SIZE_2:
0100 1M
Value is set at factory and cannot be changed.
All other bit combinations are reserved.
9–15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16–23
PARTNUM
ASCII character in MCU Family
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Memory map and register description
SIUL2_MIDR2 field descriptions (continued)
Field
Description
This field specifies the part number suffix, and needs to be combined with MIDR1[PARTNUM] to indicate
the MCU Family.
All other values reserved for future use.
Value is set at factory and cannot be changed.
01000011
24–31
Reserved
Character "C"
This field is reserved.
This read-only field is reserved and always has the value 0.
15.2.3 SIUL2 Interrupt Status Flag Register0 (SIUL2_ISR0)
The Interrupt Status Register contains flag bits that record an event on the external IRQ
pins. When an event as defined in IRQ Rising-Edge Event Enable Register
(SIUL2_IREER0) and IRQ Falling-Edge Event Enable Register (SIUL2_IFEER0)
occurs, the corresponding flag bit is set. The IRQ Flag bit is set regardless of the state of
the corresponding Interrupt Request Enable bit in Interrupt Request Enable Register
(SIUL2_IRER0) - Standard. The IRQ Flag bit remains set until cleared by software. The
IRQ Flag bits are cleared by writing a '1' to the bits. A write of '0' has no effect. The
number of bits implemented is specified by the parameter that defines the number
external IRQ pins.
This register holds the interrupt flags and supports 8-bit, 16-bit, and 32-bit accesses.
R
W
w1c
Reset
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
7
8
9
10
11
12
13
14
15
EIF16
6
EIF17
5
EIF18
4
EIF19
3
EIF20
2
EIF21
1
EIF22
0
EIF23
Bit
EIF31
Address: 0h base + 10h offset = 10h
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
23
24
25
26
27
28
29
30
31
R
EIF15
EIF14
EIF13
EIF12
EIF11
EIF10
EIF9
EIF8
EIF7
EIF6
EIF5
EIF4
EIF3
EIF2
EIF1
EIF0
0
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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SIUL2_ISR0 field descriptions
Field
0
EIF31
Description
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
1–7
Reserved
8
EIF23
This field is reserved.
This read-only field is reserved and always has the value 0.
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
9
EIF22
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
14
EIF17
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
13
EIF18
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
12
EIF19
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
11
EIF20
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
10
EIF21
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
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Memory map and register description
SIUL2_ISR0 field descriptions (continued)
Field
Description
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
15
EIF16
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
16
EIF15
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
21
EIF10
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
20
EIF11
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
19
EIF12
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
18
EIF13
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
17
EIF14
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
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SIUL2_ISR0 field descriptions (continued)
Field
22
EIF9
Description
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
23
EIF8
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
0
1
24
EIF7
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_IRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
0
1
29
EIF2
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
28
EIF3
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
27
EIF4
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
26
EIF5
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
0
1
25
EIF6
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
Table continues on the next page...
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Memory map and register description
SIUL2_ISR0 field descriptions (continued)
Field
Description
0
1
30
EIF1
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
0
1
31
EIF0
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
External Interrupt Status Flag x
This flag can be cleared only by writing 1. Writing 0 has no effect. If enabled (SIUL2_DIRER[x]), EIF[x]
causes an interrupt request.
0
1
No interrupt event has occurred on the pad
An interrupt event as defined by SIUL2_IREER[x] and SIUL2_IFEER[x] has occurred
15.2.4 SIUL2 Interrupt Request Enable Register0 (SIUL2_IRER0)
The Interrupt Request Enable Register enables the interrupt request if the corresponding
External IRQ Flag bit is set in Interrupt Status Flag Register0. The type of request
enabled is determined by the corresponding Interrupt Request Select bit in Interrupt
Request Select Register0. The number of bits implemented is specified by the parameter
that defines the number of external IRQ pins. This register is used to enable the interrupt
messaging to the interrupt controller.
Address: 0h base + 18h offset = 18h
Bit
1
2
3
4
5
6
7
W
EIRE23
EIRE22
EIRE21
EIRE20
EIRE19
EIRE18
EIRE17
EIRE16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
EIRE8
EIRE7
EIRE6
EIRE5
EIRE4
EIRE3
EIRE2
EIRE1
EIRE0
15
EIRE9
14
EIRE10
13
EIRE11
12
EIRE12
11
EIRE13
10
EIRE14
9
EIRE31
0
8
EIRE15
R
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
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SIUL2_IRER0 field descriptions
Field
Description
0
EIRE31
External Interrupt Request Enable x
1–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
EIRE23
External Interrupt Request Enable x
9
EIRE22
External Interrupt Request Enable x
10
EIRE21
External Interrupt Request Enable x
11
EIRE20
External Interrupt Request Enable x
12
EIRE19
External Interrupt Request Enable x
13
EIRE18
External Interrupt Request Enable x
14
EIRE17
External Interrupt Request Enable x
15
EIRE16
External Interrupt Request Enable x
16
EIRE15
External Interrupt Request Enable x
17
EIRE14
External Interrupt Request Enable x
18
EIRE13
External Interrupt Request Enable x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Table continues on the next page...
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Memory map and register description
SIUL2_IRER0 field descriptions (continued)
Field
Description
0
1
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
19
EIRE12
External Interrupt Request Enable x
20
EIRE11
External Interrupt Request Enable x
21
EIRE10
External Interrupt Request Enable x
22
EIRE9
External Interrupt Request Enable x
23
EIRE8
External Interrupt Request Enable x
24
EIRE7
External Interrupt Request Enable x
25
EIRE6
External Interrupt Request Enable x
26
EIRE5
External Interrupt Request Enable x
27
EIRE4
External Interrupt Request Enable x
28
EIRE3
External Interrupt Request Enable x
29
EIRE2
External Interrupt Request Enable x
30
EIRE1
External Interrupt Request Enable x
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2_IRER0 field descriptions (continued)
Field
Description
0
1
31
EIRE0
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
External Interrupt Request Enable x
0
1
Interrupt requests from the corresponding EIF[x] bit are disabled
Set EIF[x] bit causes an interrupt request depending on IRSR register
15.2.5 SIUL2 Interrupt Request Select Register0 (SIUL2_IRSR0)
The IRSR selects the interrupt request. If the corresponding bits are set in Interrupt Status
Flag Register0 and Interrupt Request Enable Register0, then the Interrupt Request Select
bit determines a interrupt request is asserted.
Address: 0h base + 20h offset = 20h
Bit
1
2
3
4
5
6
7
W
DIRSR23
DIRSR22
DIRSR21
DIRSR20
DIRSR19
DIRSR18
DIRSR17
DIRSR16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
W
DIRSR8
DIRSR7
DIRSR6
DIRSR5
DIRSR4
DIRSR3
DIRSR2
DIRSR1
DIRSR0
15
DIRSR9
14
DIRSR10
13
DIRSR11
12
DIRSR12
11
DIRSR13
10
DIRSR14
9
DIRSR31
0
8
DIRSR15
R
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIUL2_IRSR0 field descriptions
Field
Description
0
DIRSR31
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
Interrupt request is selected
Disabled
1–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
DIRSR23
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
Table continues on the next page...
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SIUL2_IRSR0 field descriptions (continued)
Field
Description
0
1
9
DIRSR22
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
10
DIRSR21
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
18
DIRSR13
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
17
DIRSR14
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
16
DIRSR15
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
15
DIRSR16
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
14
DIRSR17
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
13
DIRSR18
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
12
DIRSR19
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
11
DIRSR20
Interrupt request is selected
Disabled
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2_IRSR0 field descriptions (continued)
Field
Description
0
1
19
DIRSR12
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
20
DIRSR11
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
28
DIRSR3
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
27
DIRSR4
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
26
DIRSR5
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
25
DIRSR6
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
24
DIRSR7
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
23
DIRSR8
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
22
DIRSR9
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
21
DIRSR10
Interrupt request is selected
Disabled
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
Table continues on the next page...
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Memory map and register description
SIUL2_IRSR0 field descriptions (continued)
Field
Description
0
1
29
DIRSR2
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
30
DIRSR1
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
31
DIRSR0
Interrupt request is selected
Disabled
Interrupt Request Select Register-Selects external interrupt request when an edge-triggered event occurs
on the corresponding pin.
0
1
Interrupt request is selected
Disabled
15.2.6 SIUL2 Interrupt Rising-Edge Event Enable Register 0
(SIUL2_IREER0)
This register is used to enable the rising-edge triggered events on the corresponding
interrupt pads.
Address: 0h base + 28h offset = 28h
Bit
1
2
3
4
5
6
7
W
IREE23
IREE22
IREE21
IREE20
IREE19
IREE18
IREE17
IREE16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
IREE8
IREE7
IREE6
IREE5
IREE4
IREE3
IREE2
IREE1
IREE0
15
IREE9
14
IREE10
13
IREE11
12
IREE12
11
IREE13
10
IREE14
9
IREE31
0
8
IREE15
R
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
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SIUL2_IREER0 field descriptions
Field
Description
0
IREE31
Enable rising-edge events to cause the EIF[x] bit to be set.
1–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8
IREE23
Enable rising-edge events to cause the EIF[x] bit to be set.
9
IREE22
Enable rising-edge events to cause the EIF[x] bit to be set.
10
IREE21
Enable rising-edge events to cause the EIF[x] bit to be set.
11
IREE20
Enable rising-edge events to cause the EIF[x] bit to be set.
12
IREE19
Enable rising-edge events to cause the EIF[x] bit to be set.
13
IREE18
Enable rising-edge events to cause the EIF[x] bit to be set.
14
IREE17
Enable rising-edge events to cause the EIF[x] bit to be set.
15
IREE16
Enable rising-edge events to cause the EIF[x] bit to be set.
16
IREE15
Enable rising-edge events to cause the EIF[x] bit to be set.
17
IREE14
Enable rising-edge events to cause the EIF[x] bit to be set.
18
IREE13
Enable rising-edge events to cause the EIF[x] bit to be set.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Table continues on the next page...
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Memory map and register description
SIUL2_IREER0 field descriptions (continued)
Field
Description
0
1
Rising-edge event is disabled
Rising-edge event is enabled
19
IREE12
Enable rising-edge events to cause the EIF[x] bit to be set.
20
IREE11
Enable rising-edge events to cause the EIF[x] bit to be set.
21
IREE10
Enable rising-edge events to cause the EIF[x] bit to be set.
22
IREE9
Enable rising-edge events to cause the EIF[x] bit to be set.
23
IREE8
Enable rising-edge events to cause the EIF[x] bit to be set.
24
IREE7
Enable rising-edge events to cause the EIF[x] bit to be set.
25
IREE6
Enable rising-edge events to cause the EIF[x] bit to be set.
26
IREE5
Enable rising-edge events to cause the EIF[x] bit to be set.
27
IREE4
Enable rising-edge events to cause the EIF[x] bit to be set.
28
IREE3
Enable rising-edge events to cause the EIF[x] bit to be set.
29
IREE2
Enable rising-edge events to cause the EIF[x] bit to be set.
30
IREE1
Enable rising-edge events to cause the EIF[x] bit to be set.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Rising-edge event is disabled
Rising-edge event is enabled
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2_IREER0 field descriptions (continued)
Field
Description
0
1
31
IREE0
Rising-edge event is disabled
Rising-edge event is enabled
Enable rising-edge events to cause the EIF[x] bit to be set.
0
1
Rising-edge event is disabled
Rising-edge event is enabled
15.2.7 SIUL2 Interrupt Falling-Edge Event Enable Register 0
(SIUL2_IFEER0)
This register is used to enable falling-edge triggered events on the corresponding
interrupt pads.
NOTE
If both IREE bit and IFEE bit is cleared for the same interrupt
source, the interrupt status flag for the corresponding external
interrupt will never be set.
Address: 0h base + 30h offset = 30h
Bit
1
2
3
4
5
6
7
W
IFEE23
IFEE22
IFEE21
IFEE20
IFEE19
IFEE18
IFEE17
IFEE16
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
W
IFEE8
IFEE7
IFEE6
IFEE5
IFEE4
IFEE3
IFEE2
IFEE1
IFEE0
15
IFEE9
14
IFEE10
13
IFEE11
12
IFEE12
11
IFEE13
10
IFEE14
9
IFEE31
0
8
IFEE15
R
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
SIUL2_IFEER0 field descriptions
Field
Description
0
IFEE31
Enable falling-edge events to cause the EIF[x] bit to be set.
1–7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
Falling-edge event is disabled
Falling-edge event is enabled
Table continues on the next page...
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Memory map and register description
SIUL2_IFEER0 field descriptions (continued)
Field
Description
8
IFEE23
Enable falling-edge events to cause the EIF[x] bit to be set.
9
IFEE22
Enable falling-edge events to cause the EIF[x] bit to be set.
10
IFEE21
Enable falling-edge events to cause the EIF[x] bit to be set.
11
IFEE20
Enable falling-edge events to cause the EIF[x] bit to be set.
12
IFEE19
Enable falling-edge events to cause the EIF[x] bit to be set.
13
IFEE18
Enable falling-edge events to cause the EIF[x] bit to be set.
14
IFEE17
Enable falling-edge events to cause the EIF[x] bit to be set.
15
IFEE16
Enable falling-edge events to cause the EIF[x] bit to be set.
16
IFEE15
Enable falling-edge events to cause the EIF[x] bit to be set.
17
IFEE14
Enable falling-edge events to cause the EIF[x] bit to be set.
18
IFEE13
Enable falling-edge events to cause the EIF[x] bit to be set.
19
IFEE12
Enable falling-edge events to cause the EIF[x] bit to be set.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Table continues on the next page...
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Chapter 15 System Integration Unit Lite2 (SIUL2)
SIUL2_IFEER0 field descriptions (continued)
Field
Description
20
IFEE11
Enable falling-edge events to cause the EIF[x] bit to be set.
21
IFEE10
Enable falling-edge events to cause the EIF[x] bit to be set.
22
IFEE9
Enable falling-edge events to cause the EIF[x] bit to be set.
23
IFEE8
Enable falling-edge events to cause the EIF[x] bit to be set.
24
IFEE7
Enable falling-edge events to cause the EIF[x] bit to be set.
25
IFEE6
Enable falling-edge events to cause the EIF[x] bit to be set.
26
IFEE5
Enable falling-edge events to cause the EIF[x] bit to be set.
27
IFEE4
Enable falling-edge events to cause the EIF[x] bit to be set.
28
IFEE3
Enable falling-edge events to cause the EIF[x] bit to be set.
29
IFEE2
Enable falling-edge events to cause the EIF[x] bit to be set.
30
IFEE1
Enable falling-edge events to cause the EIF[x] bit to be set.
31
IFEE0
Enable falling-edge events to cause the EIF[x] bit to be set.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
Falling-edge event is disabled
Falling-edge event is enabled
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15.2.8 SIUL2 Interrupt Filter Enable Register 0 (SIUL2_IFER0)
This register is used to enable a digital filter counter on the corresponding interrupt pads
to filter out glitches on the inputs. The number of interrupts supporting this feature is
MCU dependent and can be configured between 0 and 31.
Address: 0h base + 38h offset = 38h
Bit
0
1
2
3
4
5
6
7
0
IFE23
IFE22
IFE21
IFE20
IFE19
IFE18
IFE17
IFE16
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
IFE10
14
IFE11
13
IFE12
12
IFE13
11
IFE14
10
Reset
IFE9
IFE8
IFE7
IFE6
IFE5
IFE4
IFE3
IFE2
IFE1
IFE0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
IFE31
9
IFE15
R
8
R
W
Reset
SIUL2_IFER0 field descriptions
Field
0
IFE31
1–7
Reserved
Description
Enable digital glitch filter on the interrupt pad input.
0
1
Filter is disabled
Filter is enabled
This field is reserved.
This read-only field is reserved and always has the value 0.
8
IFE23
Enable digital glitch filter on the interrupt pad input.
9
IFE22
Enable digital glitch filter on the interrupt pad input.
10
IFE21
Enable digital glitch filter on the interrupt pad input.
11
IFE20
Enable digital glitch filter on the interrupt pad input.
0
1
0
1
0
1
0
1
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Table continues on the next page...
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SIUL2_IFER0 field descriptions (continued)
Field
Description
12
IFE19
Enable digital glitch filter on the interrupt pad input.
13
IFE18
Enable digital glitch filter on the interrupt pad input.
14
IFE17
Enable digital glitch filter on the interrupt pad input.
15
IFE16
Enable digital glitch filter on the interrupt pad input.
16
IFE15
Enable digital glitch filter on the interrupt pad input.
17
IFE14
Enable digital glitch filter on the interrupt pad input.
18
IFE13
Enable digital glitch filter on the interrupt pad input.
19
IFE12
Enable digital glitch filter on the interrupt pad input.
20
IFE11
Enable digital glitch filter on the interrupt pad input.
21
IFE10
Enable digital glitch filter on the interrupt pad input.
22
IFE9
Enable digital glitch filter on the interrupt pad input.
23
IFE8
Enable digital glitch filter on the interrupt pad input.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Table continues on the next page...
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Memory map and register description
SIUL2_IFER0 field descriptions (continued)
Field
Description
24
IFE7
Enable digital glitch filter on the interrupt pad input.
25
IFE6
Enable digital glitch filter on the interrupt pad input.
26
IFE5
Enable digital glitch filter on the interrupt pad input.
27
IFE4
Enable digital glitch filter on the interrupt pad input.
28
IFE3
Enable digital glitch filter on the interrupt pad input.
29
IFE2
Enable digital glitch filter on the interrupt pad input.
30
IFE1
Enable digital glitch filter on the interrupt pad input.
31
IFE0
Enable digital glitch filter on the interrupt pad input.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
Filter is disabled
Filter is enabled
15.2.9 SIUL2 Interrupt Filter Maximum Counter Register
(SIUL2_IFMCRn)
These registers are used to configure the filter counter associated with each digital glitch
filter.
Address: 0h base + 40h offset + (4d × i), where i=0d to 31d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30
31
MAXCNT
W
Reset
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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SIUL2_IFMCRn field descriptions
Field
Description
0–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–31
MAXCNT
Maximum Interrupt Filter Counter setting
Filter Period = TCK*MAXCNTx + n*TCK
where (n can be 0 to 4)
MAXCNTx can be 0 to 15 (for MAXCNT<3 filter will behave as all PASS filter)
TCK Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value
T(IRC) Basic Filter Clock Period: 62.5 ns (F=16 MHz)
Also note that Filter delay is 2 TCK clock cycles more than Filter period
15.2.10 SIUL2 Interrupt Filter Clock Prescaler Register
(SIUL2_IFCPR)
This register is used to configure a clock prescaler which is used to select the clock for all
digital filter. Prescaler is applied to the input clock to the SIUL2, which is the system
AIPS clock counters in the SIUL2.
NOTE
The glitch filters need a running internal oscillator clock to
work. If no such clock is available, external interrupts will be
effectively disabled when the glitch filter is enabled on a
interrupt line.
Address: 0h base + C0h offset = C0h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30
31
IFCP
W
Reset
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SIUL2_IFCPR field descriptions
Field
0–27
Reserved
28–31
IFCP
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Interrupt Filter Clock Prescaler setting
Prescaled Filter Clock Period = T(IRC) x (IFCP + 1)
T(IRC) is the internal oscillator period.
IFCP can be 0 to 15
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15.2.11 SIUL2 Multiplexed Signal Configuration Register
(SIUL2_MSCRn)
Selects which source signal is connected to the register's associated destination, which is
a chip pin that is or can be configured as an output.
For the associated chip-pin destination, the register also specifies the pin's electrical
properties.
Port (input)
Internal connections
Destination (module port)
Module 0
Input
buffer
Pin a
Input
buffer
Pin b
Port (output)
Module-port IMCR
Chip-pin MSCR
Port (output)
Output
buffer
Module x
Port (output)
Destination (chip pin)
Figure 15-2. MSCR pin connection
The fields in an MSCR vary depending on its associated destination (chip pin).
For available chip-pin MSCR assignments, pin types, bit availability on each MSCR,
APC support, and SSS values etc. see the I/O Signal Description and Input Multiplexing
Tables (excel file) attached to this document.
This register only supports 32-bit access. Byte and half-word write accesses are not
supported.
Address: 0h base + 240h offset + (4d × i), where i=0d to 263d
Bit
0
1
0
R
2
3
4
0
SRC[1:0]
W
Reset
0*
0*
0*
0*
Bit
16
17
18
19
5
6
7
8
9
10
11
OBE
ODE
SMC
APC
0
0*
0*
0*
0*
1*
0*
20
21
22
23
24
25
0
R
12
13
14
15
0
IBE
HYS
PUS
PUE
0*
0*
0*
1*
0*
0*
26
27
28
29
30
31
0*
0*
0
SSS
W
Reset
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
0*
* Notes:
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• See the Signal Description details for the reset values and the availability of pad setting bits in MSCRs.
SIUL2_MSCRn field descriptions
Field
Description
0–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–3
SRC[1:0]
Slew Rate Control
Used only when the associated destination is a chip pin.
00
01
10
11
4–5
Reserved
6
OBE
Half drive strength with slew rate control
Full drive strength with slew rate control
Half drive strength without slew rate control
Full drive strength without slew rate control
This field is reserved.
This read-only field is reserved and always has the value 0.
GPIO Output Buffer Enable
Applies only to digital pins. Otherwise this bit is reserved.
0
1
Output driver disabled
Output driver enabled
7
ODE
Open Drain Enable
8
SMC
Safe Mode Control
0
1
Used only when the associated destination is a chip pin. Specifies whether the chip disables the pin's
output buffer when the chip enters Safe mode.
0
1
9
APC
Open drain function disabled
Open drain function enabled, when OBE is also 1.
Disable (the output buffer returns to its previous state when the chip leaves Safe mode)
Don't disable
Analog Pad Control
Used only when the associated destination is a chip pin that supports analog I/O. Enables the pin's
analog-input-path switch.
0
1
Disable (the switch is off)
Enable (another module can control the state of the switch)
10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
IBE
Input Buffer Enable
Used only when the associated destination is a chip pin. Enables the associated pin's input buffer.
0
1
13
HYS
Disabled
Enabled
Input Hysteresis
Used only when the associated destination is a chip pin. Enables input hysteresis for the associated pin.
Table continues on the next page...
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Memory map and register description
SIUL2_MSCRn field descriptions (continued)
Field
Description
0
1
14
PUS
Pull Select
Determines whether the pull function is a pullup or pulldown when the pull function is enabled by the PUE
field. Used only when the associated destination is a chip pin.
0
1
15
PUE
Disabled
Enabled
Pulldown
Pullup
Pull Enable
Enables the pull function. Used only when the associated destination is a chip pin.
0
1
Disabled
Enabled
16–23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–31
SSS
Source Signal Select
Selects which source signal is connected to the associated destination (chip pin or module port). This field
has a variable width depending on the number of alternate functions available for that pin/port. For a chip
pin, the source signals are outputs from module ports. For a module port, the source signals are either
outputs from module ports or inputs from chip pins.
See the device I/O Signal Description and Input Multiplexing Tables (excel file) attached to this document.
Locate the paperclip symbol on the left side of the PDF window, and click it. Double-click on the excel file
to open it and select the I/O Signal Description Table tab.
15.2.12 SIUL2 Input Multiplexed Signal Configuration Register
(SIUL2_IMCRn)
Selects which source signal is connected to the register's associated destination, which is
an internal module port that is or can be configured as an input.
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Port (input)
Internal connections
Destination (module port)
Module 0
Input
buffer
Pin a
Input
buffer
Pin b
Port (output)
Module-port IMCR
Chip-pin MSCR
Port (output)
Output
buffer
Module x
Port (output)
Destination (chip pin)
Figure 15-3. IMCR module-port connection(For IMCR0 to IMCR27, IMCR32 to IMCR63,
IMCR68 to IMCR511)
Destination (module port)
Internal connections
Port (input)
Module 0
Port (output)
INV
Input
buffer
Pin a
Input
buffer
Pin b
SSS
Module-port IMCR
Chip-pin MSCR
Port (output)
Output
buffer
Module x
Port (output)
Destination (chip pin)
Figure 15-4. IMCR module-port connection (For IMCR28 to IMCR31 and IMCR64 to
IMCR67)
The fields in an IMCR vary depending on its associated destination (module port).
For IMCR assignments and SSS values, see the I/O Signal Description and Input
Multiplexing Tables (excel file) attached to this document.
Address: 0h base + A40h offset + (4d × i), where i=0d to 511d
Bit
R
W
Reset
0
1
2
3
4
5
6
7
INV
*
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Bit
16
17
18
19
20
21
22
23
24
25
0
R
26
27
28
29
0
0
0
0
0
0
0
0
0
0
0
31
0
0
SSS
W
Reset
30
0
0
0
0
* Notes:
• INV field: INV bit exist only for IMCR28, IMCR29, IMCR30, IMCR31, IMCR64, IMCR65, IMCR66, and IMCR67. For rest of
the IMCRs this field is reserved.
SIUL2_IMCRn field descriptions
Field
0
INV
Description
Invert
This bit is used to invert the source signal.
0
1
Source signal is connected to the associated destination directly either from chip pin or module port.
Source signal is inverted before it is connected to the associated destination directly either from chip
pin or module port.
1–23
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–31
SSS
Source Signal Select
Selects which source signal is connected to the associated destination (chip pin or module port). This field
has a variable width depending on the number of alternate functions available for that pin/port. For a chip
pin, the source signals are outputs from module ports. For a module port, the source signals are either
outputs from module ports or inputs from chip pins.
See the device I/O Signal Description and Input Multiplexing Tables (excel file) attached to this document.
Locate the paperclip symbol on the left side of the PDF window, and click it. Double-click on the excel file
to open it and select the I/O Signal Description Table tab.
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15.2.13 SIUL2 GPIO Pad Data Output Register (SIUL2_GPDOn)
These registers can be used to set or clear a single GPIO pad with a byte access.
Address: 0h base + 1300h offset + (4d × i), where i=0d to 65d
1
2
3
4
5
6
0
R
7
8
9
10
W
11
12
13
14
0
15
PDO_4n1
0
PDO_4n
Bit
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PDO_4n3
W
Reset
0
PDO_4n2
0
R
0
SIUL2_GPDOn field descriptions
Field
Description
0–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
PDO_4n
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
PDO_4n represents PDO[4n], where n is the instance of the register. For example, for the GPDO3
register, PDO_4n represents PDO12.
0
1
Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output
Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output
8–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
PDO_4n1
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
PDO_4n1 represents PDO[4n+1], where n is the instance of the register. For example, for the GPDO3
register, PDO_4n1 represents PDO13.
0
1
Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output
Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output
16–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
PDO_4n2
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
Table continues on the next page...
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SIUL2_GPDOn field descriptions (continued)
Field
Description
PDO_4n2 represents PDO[4n+2], where n is the instance of the register. For example, for the GPDO3
register, PDO_4n2 represents PDO14.
0
1
Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output
Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output
24–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
31
PDO_4n3
Pad Data Out
This bit stores the data to be driven out on the external GPIO pad controlled by this register.
PDO_4n3 represents PDO[4n+3], where n is the instance of the register. For example, for the GPDO3
register, PDO_4n3 represents PDO15.
0
1
Logic low value is driven on the corresponding GPIO pad when the pad is configured as an output
Logic high value is driven on the corresponding GPIO pad when the pad is configured as an output
15.2.14 SIUL2 GPIO Pad Data Input Register (SIUL2_GPDIn)
These registers can be used to read the GPIO pad data with a byte access.
Address: 0h base + 1500h offset + (4d × i), where i=0d to 65d
0
1
2
3
4
5
6
0
R
7
8
9
10
PDI_4n
Bit
11
12
13
14
15
PDI_
4n1
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PDI_
4n2
0
R
PDI_
4n3
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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SIUL2_GPDIn field descriptions
Field
Description
0–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
PDI_4n
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
PDI_4n represents PDI[4n], where n is the instance of the register. For example, for the GPDI3 register,
PDI_4n represents PDI12.
0
1
The value of the data in signal for the corresponding GPIO pad is logic low
The value of the data in signal for the corresponding GPIO pad is logic high
8–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
PDI_4n1
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
PDI_4n1 represents PDI[4n+1], where n is the instance of the register. For example, for the GPDI3
register, PDI_4n1 represents PDI13.
0
1
The value of the data in signal for the corresponding GPIO pad is logic low
The value of the data in signal for the corresponding GPIO pad is logic high
16–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
PDI_4n2
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
PDI_4n2 represents PDI[4n+2], where n is the instance of the register. For example, for the GPDI3
register, PDI_4n2 represents PDI14.
0
1
The value of the data in signal for the corresponding GPIO pad is logic low
The value of the data in signal for the corresponding GPIO pad is logic high
24–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
31
PDI_4n3
Pad Data In
This bit stores the value of the external GPIO pad associated with this register.
PDI_4n3 represents PDI[4n+3], where n is the instance of the register. For example, for the GPDI3
register, PDI_4n3 represents PDI15.
0
1
The value of the data in signal for the corresponding GPIO pad is logic low
The value of the data in signal for the corresponding GPIO pad is logic high
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15.2.15 SIUL2 Parallel GPIO Pad Data Out Register (SIUL2_PGPDOn)
These registers are used to set or clear the respective pads of the device. Parallel port
registers for input (PGPDI) and output (PGPDO) are provided to allow a complete port to
be written or read in one operation, dependent on the individual pad configuration. The
difference between PGPDO and GPDO is that PGPDO registers can be used to set the
values of all output pins assigned to a device port with a single 16-bit register write vs.
the GPDO registers, which are used to set the value on a specific pin with a byte write.
The SIUL2_PGPDO registers access the same physical resource as the SIUL2_PDO and
SIUL2_MPGPDO address locations. Some examples of the mapping:
• PPDO[0][0] = PDO[0]
• PPDO[2][0] = PDO[32]
• PPDO[31][15] = PDO[511]
Address: 0h base + 1700h offset + (2d × i), where i=0d to 31d
Bit
Read
Write
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
PPDO
0
0
0
0
0
0
0
0
SIUL2_PGPDOn field descriptions
Field
0–15
PPDO
Description
Parallel Pad Data Out
Write or read the data register that stores the value to be driven on the pad in output mode. Access to this
register location are coherent with access to the bit-wise GPIO Pad Data Output Registers
(SIUL2_GPDO).The x and bit index define which PPDO register bit is equivalent to which PDO register bit
according to the following equation:
PPDO[x][y] = PDO[(x*16)+y]
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15.2.16 SIUL2 Parallel GPIO Pad Data In Register (SIUL2_PGPDIn)
These registers hold the synchronized input value from the pads. Parallel port registers
for input (PGPDI) and output (PGPDO) are provided to allow a complete port to be
written or read in one operation, dependent on the individual pad configuration.The
difference between PGPDI and GPDI registers is that PGPDI registers can be used to
read the values of all input pins assigned to a device port with a single 16-bit register read
vs. the GPDI registers, which are used to read the value on a specific pin with a byte read.
Address: 0h base + 1740h offset + (2d × i), where i=0d to 31d
Bit
0
1
2
3
4
5
6
7
Read
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
PPDI
Write
Reset
0
0
0
0
0
0
0
0
SIUL2_PGPDIn field descriptions
Field
Description
0–15
PPDI
Parallel Pad Data In
Reads the current pad value. Access to this register location are coherent with access to the bit-wise
GPIO Pad Data Input Registers (SIUL2_GPDI). The x and bit index define which PPDI register bit is
equivalent to which PDI register bit according to the following equation:
PPDI[x][y] = PDI[(x*16)+y]
15.2.17 SIUL2 Masked Parallel GPIO Pad Data Out Register
(SIUL2_MPGPDOn)
This register can be used to selectively modify the pad values associated to PPDO[x]
[0:15]. The MPGPDO[x] register may only be accessed with 32-bit writes. 8-bit or 16-bit
writes will not modify any bits in the register and cause a transfer error response by the
module. Read access will return 0.
Address: 0h base + 1780h offset + (4d × i), where i=0d to 31d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R
0
0
W
MASK
MPPDO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
25
26
27
28
29
30
31
0
0
0
0
0
0
0
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Functional description
SIUL2_MPGPDOn field descriptions
Field
0–15
MASK
Description
Mask Field
Each bit corresponds to one data bit in the MPPDO[x] register at the same bit location.
0b
1b
16–31
MPPDO
The associated bit value in the MPPDO[x] field is ignored
The associated bit value in the MPPDO[x] field is written
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in
output mode. Access to this register location are coherent with access to the bit-wise GPIO Pad Data
Output Registers (PDO).The x and bit index define which MPPDO register bit is equivalent to which PDO
register bit according to the following equation:
MPPDO[x][y] = PDO[(x*16)+y]
15.3 Functional description
15.3.1 General
This section provides a complete functional description of the System Integration Unit
Lite2.
15.3.2 Pad Control
The SIUL2 is capable of controlling the electrical characteristic of up to 264 pads. It
provides a consistent interface for all pads, both on a by-port and a by-bit basis. The
following describes the pad characteristics that can be supported by the SIUL2. Not all of
these features will be supported on all devices or on all pads as this is dependent on the
specific application needs an the pads implemented on the device.
The required controls are:
• Slew rate control
• Offers improved EMC performance.
• Support for a fast and a slow slew rate.
• Drive strength control
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• Offers improved EMC performance.
• Up to 4 different drive strength levels can be supported.
• Pull capability
• Offers flexibility in the device configuration and the elimination of external
hardware in some cases.
• The configuration of the pull on any pad should be independently controlled to
be either pull-up, pull-down or no-pull enabled.
• Input and Out Buffer control
• Hysteresis
• Open drain
• Needed to support different pads muxed (e.g. mux I2C, with non open drain
pads)
• Pad Output Assignment
• This setting defines which chip function has control over the output of the pad.
The setting of each pad out of reset is fixed per MCU, but can be configured individually.
In this way it is possible to select special pull settings or peripheral pad ownership per
design.
It is possible for the user software to configure each pad independently of all other pads
on the device or other pads grouped within a single port. This allows different pad types
to be grouped together in ports and allows the necessary flexibility needed for the pads
individual operation. This is achieved by grouping all of the above functions into a single
register for each pad on the device, and allows each pad to be configured with a single
write to one register and allowing simplified duplication of software for each pad with
indexed changes for each pad.
15.3.3 General Purpose Input and Output Pads (GPIO)
The SIUL2 allows each pad to be configured as either a General Purpose Input or Output
pad (GPIO), and as one or more alternate functions (input or output), the function of
which is determined by the peripheral that will use the pad.
GPIO pads can also optionally be implemented without any alternate function.
The SIUL2 is designed to manage up to 264 GPIO pads organized as ports that can be
accessed for data reads and writes as 32-bit.
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Functional description
All port access are identical with each read or write being performed only at a different
location to access a different port width.
This requires that the registers are arranged in such a way as to support this range of port
widths without having to split reads or writes into multiple accesses.
The module has separate data input and data output registers for all pads, allowing the
possibility of reading back an input or output value of a pad directly. This supports the
ability to validate what is present on the pad rather than simply confirming the value that
was written to the data register by accessing the data input registers.
The data output registers support both read and write operations to be performed.
The data input registers support read access only.
When the pad is configured to use one of its alternate functions, the data input value
reflect the respective value of the pad. If a write operation is performed to the data output
register for a pad configured as an alternate function (non GPIO), this write will not be
reflected by the pad value until re-configured to GPIO. All general purpose pads are
implemented as bidirectional.
Note
In case the bi-directional operation impacts some performances
(e.g. ADC accuracy), or is not required for a specific pad
function it is acceptable to limit the functionality of some pads
to "Input Only"
15.3.4 External Interrupts Requests (REQ Pins)
The SIUL2 supports 0 to 31 external interrupts, which can be allocated to any pad
necessary at the MCU level. This allocation is fixed per MCU.
For the assignments of the external interrupts, see the Signal Description details.
The SIUL2 supports up to 4 interrupt vectors to the interrupt controller of the MCU. Each
interrupt vector can support up to 8 external interrupt sources from the device pads.
For devices with a number of interrupt sources that is smaller than the maximum number,
the MCU can implement either all four interrupt vectors with fewer sources or reduce the
number of vectors as the number of sources are reduced. The following figure shows two
sample scenarios.
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Chapter 15 System Integration Unit Lite2 (SIUL2)
Interrupt Vectors
#0
#1
Flag[15:8]
Interrupt Vectors
#3
Flag[7:0]
#2
Flag[31:24]
#1
Flag[23:16]
#0
Flag[15:8]
Flag[7:0]
Pads
Pads
Figure 15-5. Example of different interrupt to vector mapping at MCU level
All the external interrupt pads within a single group (maximum 8 pads) have equal
priority. It is the responsibility of the user software to search through the group of sources
in the most appropriate way for their application.
The priority of the vectors used by the external interrupt pads is fixed based on the
platform and the interrupt controller and its priority levels, but the allocation of pads to
each group of interrupts can be independently configured by the MCU.
An MCU-specific number of external interrupt lines can have a digital glitch filters
applied to them. The supported range is up to 32.
15.3.4.1 External interrupt initialization
When an external interrupt pin is first enabled, it is possible to get a false interrupt flag.
To prevent a false interrupt request, during pin interrupt initialization, the user must do
the following:
1. Mask interrupts by clearing the EIREn bits in IRER0.
2. Select the pin polarity by setting the appropriate IREEn bits in IREER0 and the
appropriate IFEEn bits in IFEER0 as desired.
3. Configure the appropriate bits in the MSCR[0:511] register for the external interrupt
pin(s) desired as follows:
• Clear the OBE and ODE bits to disable output.
• Set the IBE bit to enable the pin's input buffer.
• If using the internal pullup/pulldown, configure the appropriate PUE and PUS
fields.
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Functional description
Note
MSCR[SSS] bits do not need to be changed for either
MSCR[0:511] or IMCR[0:511] because the external
interrupt pin input is directly connected to the SIUL for
EIRQ pins.
External interrupt pins should never be configured as
outputs (MSCR[ODC] bits are not zeros) when external
interrupt inputs are desired because false interrupts could
be detected (such as from a GPIO configuration).
4. Select the request desired Interrupt by writing the appropriate IRSn bits in IRSR0.
5. Select the desired glitch filter setup for the pins by writing the following:
• Write the Filter Counter setting to the desired value by writing the
MAXCNT[3:0] bits in the IFMCn register for the respective external interrupt
that is being used.
• Set the Filter Clock Prescaler setting from 0 to 15 to the desired value by writing
the IFCP[3:0] bits in the IFCPR register.
• Enable the glitch filter for the desired external interrupt pins by setting the
appropriate IFEn bits in IFER0.
NOTE
The glitch filter clock runs on the internal RC oscillator
clock whereas the SIUL logic runs off of the PBRIDGEx
clock. The IRC clock is at a fixed frequency of 16 MHz.
The PBRIDGEx clock can run as high as 40 MHZ when
core clock is at 160 MHz. The glitch filter is enabled on
IRC clock, so make sure at least one IRC clock occurs after
enabling it before trying to detect glitchless events.
6. Write to EIFn bits in ISR0 to as desired to clear any flags.
7. Enable the interrupt pins by setting the appropriate EIREn bits in IRER0.
15.3.4.2 External interrupt management
The user can enable or disable each interrupt independently using a single rolled up
register, SIUL2_IRER0.
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A pad defined as an external interrupt can be configured by the user to recognize
interrupts with an active rising edge, an active falling edge, or both edges being active. A
setting of having both edge events disabled is reserved and should not be configured. The
user controls the active IRQ edge through the registers SIUL2_IREER and
SIUL2_IFEER.
Each external interrupt supports an individual flag which is held in the Flag register
(ISR0). This register is a clear-by-write-1 register type, preventing inadvertent
overwriting of other flags in the same register.
Refer to the following figure for an overview of the external interrupt implementation.
Interrupt
Controller
Int
Vectors
IRQ_23_16
IRQ_31_24
OR
IRQ_15_08
OR
IRQ_07_00
OR
OR
EIRE[31:0]
Interrupt enable
Glitch filter Prescaler
EIF[31:24]
EIF[23:16]
EIF[15:8]
EIF[7:0]
IFCP[3:0]
Glitch filter Counter_n
Edge Detection
MAXCOUNT[x]
IRQ Glitch Filter enable
IFE[31:0]
Glitch Filter
Interrupt Edge Enable
Rising
IREE[31:0]
Falling
IFEE[31:0]
Pads
Figure 15-6. External interrupt pad diagram
15.3.4.3 External Interrupt request
The EIRQ input pins on the device are sources for interrupt requests. The system has four
possible interrupt vectors available for the EIRQ pins in the SIUL2. The mapping of 32
interrupt request sources to vectors and channels appears in the following table.
Table 15-1. Interrupt source mapping to SIUL2 Interrupt request output for 32 interrupt
sources
Vector/Channel #
Interrupt Vector Source
0
EIRQ[07] | EIRQ[06] | EIRQ[05] | EIRQ[04] | EIRQ[03] | EIRQ[02] | EIRQ[01] | EIRQ[00]
1
EIRQ[15] | EIRQ[14] | EIRQ[13] | EIRQ[12] | EIRQ[11] | EIRQ[10] | EIRQ[09] | EIRQ[08]
2
EIRQ[23] | EIRQ[22] | EIRQ[21] | EIRQ[20] | EIRQ[19] | EIRQ[18] | EIRQ[17] | EIRQ[16]
3
EIRQ[31] | EIRQ[30] | EIRQ[29] | EIRQ[28] | EIRQ[27] | EIRQ[26] | EIRQ[25] | EIRQ[24]
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Chapter 16
Crossbar Switch (AXBS)
16.1 Chip-specific AXBS information
16.1.1 Crossbar Switch configuration
This section summarizes how the AXBS_0 is configured in the chip.
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Chip-specific AXBS information
Master Modules
S0
M0
PFLASH
System Memory protection unit
(SMPU_0)
S2
S4
S3
S5
PRAM_0
PRAM_1
HSM
M7
M6
DMA
PBRIDGE_A
S6
Ethernet
(ENET)
PBRIDGE_B
M3
FlexRay
Crossbar Switch (AXBS_0)
M4
Z2 core
Dbus
M2
Z2 core
I bus
M5
S1
Z4 core
D bus
M1
Z4 core
I bus
Slave Modules
Figure 16-1. AXBS 0 integration
16.1.2 AXBS 0 Master and Slave assignments
This device contains 8 masters connected to the crossbar switch 0 (AXBS_0).
The master and slave assignments are as follows:
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Chapter 16 Crossbar Switch (AXBS)
Table 16-1. AXBS_0 (Key: x = available connection)
Master
Ports
Master
Z4 I bus
Slave Ports
Master Port
0
1
2
3
4
No.
(PFLASH__ (PFLASH_1) (PFLASH_2) (PBRIDGE_ (PBRIDGE_
0)
A)
B)
0
x1
x
x
x
5
6
PRAM_0
PRAM_1
x
x
x
x
x2
x
Z4 D bus
1
FlexRay
2
x
x3
ENET
3
x
x
Z2 I bus
4
x4
x
x
x
x5
x6
x
x
Z2 D bus
5
DMA
6
x
x
x
x
x
7
x7
x
x
x
x
HSM
x
x
1. Slave Port No. 0 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No. 0
(Z4_I) should be given highest priority when accessing Slave Port No. 0 by default.
2. Slave Port No. 5 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
1(Z4_D) should be given highest priority when accessing Slave Port No. 5 by default
3. Slave Port No. 6 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
2(FlexRay) should be given highest priority when accessing Slave Port No. 6 by default
4. Slave Port No. 1 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
4(Z2_I) should be given highest priority when accessing Slave Port No. 1 by default.
5. Slave Port No. 3 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
5(Z2_D) should be given highest priority when accessing Slave Port No. 3 by default
6. Slave Port No. 4 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
5(Z2_D) should be given highest priority when accessing Slave Port No. 4 by default
7. Slave Port No. 2 should be set to “park on last”. Arbitration mode should be set to fixed priority and Master Port No.
7(HSM) should be given highest priority when accessing Slave Port No. 2 by default.
16.1.3 PRS register reset values
The AXBS0_PRSn registers reset to 7654_3210h.
16.1.4 CRS register reset values
The AXBS0_CRSn registers reset to 00FF_0010h.
NOTE
To enable DMA master HPE mode, DMA_TCDn_CSR[BWC]
field must be set to 0x01.
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Introduction
16.2 Introduction
The information found here provides information on the layout, configuration, and
programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows all bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave. A variety of bus arbitration methods and attributes may be programmed on a
slave-by-slave basis.
16.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• Slave arbitration attributes configured on a slave-by-slave basis
• Up to single-clock 64-bit transfer
• Support for burst transfers of up to 16 beats of data
• Low-Power Park mode support
• Master priority elevation
16.3 Memory Map / Register Definition
Each slave port of the crossbar switch contains configuration registers. Read- and writetransfers require two bus clock cycles. The registers can be read from and written to only
in supervisor mode. Additionally, these registers can be read from or written to only by
32-bit accesses.
A bus error response is returned if an unimplemented location is accessed within the
crossbar switch.
The CRSn and PRSn registers can be programmed to be read-only to prevent changes to
their configuration. After being read-only protected, future writes to them will terminate
with an error.
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Chapter 16 Crossbar Switch (AXBS)
NOTE
This section shows the registers for all eight master and slave
ports. If a master or slave is not used on this particular device,
then unexpected results occur when writing to its registers. See
the chip configuration details for the exact master/slave
assignments for your device.
All references to the crossbar switch registers are based on the
physical port connections.
AXBS memory map
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
0
Priority Registers Slave (AXBS_PRS0)
32
R/W
See section
16.3.1/384
10
Control Register (AXBS_CRS0)
32
R/W
See section
16.3.2/387
100
Priority Registers Slave (AXBS_PRS1)
32
R/W
See section
16.3.1/384
110
Control Register (AXBS_CRS1)
32
R/W
See section
16.3.2/387
200
Priority Registers Slave (AXBS_PRS2)
32
R/W
See section
16.3.1/384
210
Control Register (AXBS_CRS2)
32
R/W
See section
16.3.2/387
300
Priority Registers Slave (AXBS_PRS3)
32
R/W
See section
16.3.1/384
310
Control Register (AXBS_CRS3)
32
R/W
See section
16.3.2/387
400
Priority Registers Slave (AXBS_PRS4)
32
R/W
See section
16.3.1/384
410
Control Register (AXBS_CRS4)
32
R/W
See section
16.3.2/387
500
Priority Registers Slave (AXBS_PRS5)
32
R/W
See section
16.3.1/384
510
Control Register (AXBS_CRS5)
32
R/W
See section
16.3.2/387
600
Priority Registers Slave (AXBS_PRS6)
32
R/W
See section
16.3.1/384
610
Control Register (AXBS_CRS6)
32
R/W
See section
16.3.2/387
700
Priority Registers Slave (AXBS_PRS7)
32
R/W
See section
16.3.1/384
710
Control Register (AXBS_CRS7)
32
R/W
See section
16.3.2/387
800
Master General Purpose Control Register (AXBS_MGPCR0)
32
R/W
0000_0000h
16.3.3/389
900
Master General Purpose Control Register (AXBS_MGPCR1)
32
R/W
0000_0000h
16.3.3/389
A00
Master General Purpose Control Register (AXBS_MGPCR2)
32
R/W
0000_0000h
16.3.3/389
B00
Master General Purpose Control Register (AXBS_MGPCR3)
32
R/W
0000_0000h
16.3.3/389
C00
Master General Purpose Control Register (AXBS_MGPCR4)
32
R/W
0000_0000h
16.3.3/389
D00
Master General Purpose Control Register (AXBS_MGPCR5)
32
R/W
0000_0000h
16.3.3/389
E00
Master General Purpose Control Register (AXBS_MGPCR6)
32
R/W
0000_0000h
16.3.3/389
F00
Master General Purpose Control Register (AXBS_MGPCR7)
32
R/W
0000_0000h
16.3.3/389
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Memory Map / Register Definition
16.3.1 Priority Registers Slave (AXBS_PRSn)
The priority registers (PRSn) set the priority of each master port on a per slave port basis
and reside in each slave port. The priority register can be accessed only with 32-bit
accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to
write to it have no effect on PRSn and result in a bus-error response to the master
initiating the write.
Two available masters must not be programmed with the same priority level. Attempts to
program two or more masters with the same priority level result in a bus-error response
and the PRSn is not updated.
NOTE
Valid values for the Mn priority fields depend on which masters
are available on the chip. This information can be found in the
chip-specific information for the crossbar.
• If the chip contains fewer than three masters, only one bit is
valid.
• If the chip contains fewer than five masters, only two bits
are valid.
• If five or more masters are present, all three bits of the
priority field are used.
NOTE
See the chip-specific crossbar information for the reset value of
this register.
Address: 0h base + 0h offset + (256d × i), where i=0d to 7d
Bit
0
R
0
1
2
3
5
0
M7
W
4
6
7
8
9
0
M6
10
11
12
13
0
M5
14
15
M4
Reset
0
0*
0*
0*
0
0*
0*
0*
0
0*
0*
0*
0
0*
0*
0*
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
Reset
0
0
M3
W
0*
0*
0*
0
0
M2
0*
0*
0*
0
0
M1
0*
0*
0*
0
M0
0*
0*
0*
* Notes:
• See the chip-specific crossbar information for the reset value of this register.
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AXBS_PRSn field descriptions
Field
0
Reserved
1–3
M7
4
Reserved
5–7
M6
8
Reserved
9–11
M5
12
Reserved
13–15
M4
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 7 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 6 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
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AXBS_PRSn field descriptions (continued)
Field
16
Reserved
17–19
M3
20
Reserved
21–23
M2
24
Reserved
25–27
M1
28
Reserved
29–31
M0
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
000
001
010
011
100
101
110
111
This master has level 1, or highest, priority when accessing the slave port.
This master has level 2 priority when accessing the slave port.
This master has level 3 priority when accessing the slave port.
This master has level 4 priority when accessing the slave port.
This master has level 5 priority when accessing the slave port.
This master has level 6 priority when accessing the slave port.
This master has level 7 priority when accessing the slave port.
This master has level 8, or lowest, priority when accessing the slave port.
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Chapter 16 Crossbar Switch (AXBS)
16.3.2 Control Register (AXBS_CRSn)
These registers control several features of each slave port and must be accessed using 32bit accesses. After CRSn[RO] is set, the PRSn can only be read; attempts to write to it
have no effect and result in an error response.
NOTE
See the chip-specific crossbar information for the reset value of
this register.
Not all HPEn fields may be active. See the chip-specific
crossbar information for which masters support master highpriority elevation. Setting a field corresponding to a master that
does not support master high-priority elevation has no effect.
Address: 0h base + 10h offset + (256d × i), where i=0d to 7d
Bit
0
1
R
RO
HLP
Reset
0*
0*
0*
Bit
16
17
18
W
2
3
4
5
6
0
0*
0*
0*
0*
0*
0*
19
20
21
22
23
24
0*
0*
0*
0*
9
10
11
12
13
14
15
0*
0*
0*
0*
0*
0*
0*
0*
0*
25
26
27
28
29
30
31
0
ARB
W
0*
8
HPE7 HPE6 HPE5 HPE4 HPE3 HPE2 HPE1 HPE0
0
R
Reset
7
0*
0*
0
PCTL
0*
0
1
0*
PARK
0*
0*
0*
* Notes:
• See the chip-specific crossbar information for the reset value of this register.
AXBS_CRSn field descriptions
Field
0
RO
Description
Read Only
Forces the PRSn and CRSn registers to be read-only. After being set, only a hardware reset clears this
field.
0
1
1
HLP
The CRSn and PRSn registers are writeable
The CRSn and PRSn registers are read-only and cannot be written (attempted writes have no effect
on the registers and result in a bus error response).
Halt Low Priority
Sets the initial arbitration priority for low power mode requests . Setting this bit will not affect the request
for low power mode from attaining highest priority once it has control of the slave ports.
0
1
The low power mode request has the highest priority for arbitration on this slave port
The low power mode request has the lowest initial priority for arbitration on this slave port
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AXBS_CRSn field descriptions (continued)
Field
2–7
Reserved
8
HPE7
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
On this slave port, enable master high-priority elevation for master 7. If enabled, the master is able to
elevate its priority to the highest.
0
1
9
HPE6
On this slave port, enable master high-priority elevation for master 6. If enabled, the master is able to
elevate its priority to the highest.
0
1
10
HPE5
22–23
ARB
Priority elevation for master 1 is disabled on this slave port
Priority elevation for master 1 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 0. If enabled, the master is able to
elevate its priority to the highest.
0
1
16–21
Reserved
Priority elevation for master 2 is disabled on this slave port
Priority elevation for master 2 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 1. If enabled, the master is able to
elevate its priority to the highest.
0
1
15
HPE0
Priority elevation for master 3 is disabled on this slave port
Priority elevation for master 3 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 2. If enabled, the master is able to
elevate its priority to the highest.
0
1
14
HPE1
Priority elevation for master 4 is disabled on this slave port
Priority elevation for master 4 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 3. If enabled, the master is able to
elevate its priority to the highest.
0
1
13
HPE2
Priority elevation for master 5 is disabled on this slave port
Priority elevation for master 5 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 4. If enabled, the master is able to
elevate its priority to the highest.
0
1
12
HPE3
Priority elevation for master 6 is disabled on this slave port
Priority elevation for master 6 is enabled on this slave port
On this slave port, enable master high-priority elevation for master 5. If enabled, the master is able to
elevate its priority to the highest.
0
1
11
HPE4
Priority elevation for master 7 is disabled on this slave port
Priority elevation for master 7 is enabled on this slave port
Priority elevation for master 0 is disabled on this slave port
Priority elevation for master 0 is enabled on this slave port
This field is reserved.
This read-only field is reserved and always has the value 0.
Arbitration Mode
Selects the arbitration policy for the slave port.
00
01
Fixed priority
Round-robin (rotating) priority
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Chapter 16 Crossbar Switch (AXBS)
AXBS_CRSn field descriptions (continued)
Field
Description
10
11
24–25
Reserved
26–27
PCTL
This field is reserved.
This read-only field is reserved and always has the value 0.
Parking Control
Determines the slave port’s parking control. The low-power park feature results in an overall power
savings if the slave port is not saturated; however, this forces an extra latency clock when any master tries
to access the slave port while not in use because it is not parked on any master.
00
01
10
11
28
Reserved
29–31
PARK
Reserved
Reserved
When no master makes a request, the arbiter parks the slave port on the master port defined by the
PARK bit field
When no master makes a request, the arbiter parks the slave port on the last master to be in control
of the slave port
Low-power park. When no master makes a request, the slave port is not parked on a master and the
arbiter drives all outputs to a constant safe state
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Park
Determines which master port the current slave port parks on when no masters are actively making
requests and the PCTL bits are cleared.
NOTE: Select only master ports that are present on the chip. Otherwise, undefined behavior might occur.
000
001
010
011
100
101
110
111
Park on master port M0
Park on master port M1
Park on master port M2
Park on master port M3
Park on master port M4
Park on master port M5
Park on master port M6
Park on master port M7
16.3.3 Master General Purpose Control Register (AXBS_MGPCRn)
The MGPCR controls only whether the master’s undefined length burst accesses are
allowed to complete uninterrupted or whether they can be broken by requests from higher
priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit
accesses.
NOTE
If there are fewer than eight master ports, only the registers
associated with those masters are present. Register addresses
associated with master ports that are not present are reserved.
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Functional Description
Please see this module's chip-specific information for which
master ports are present on this module.
Address: 0h base + 800h offset + (256d × i), where i=0d to 7d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
AULB
W
Reset
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AXBS_MGPCRn field descriptions
Field
0–28
Reserved
29–31
AULB
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Arbitrates On Undefined Length Bursts
Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when
the master is performing undefined length burst accesses.
000
001
010
011
100
101
110
111
No arbitration is allowed during an undefined length burst
Arbitration is allowed at any time during an undefined length burst
Arbitration is allowed after four beats of an undefined length burst
Arbitration is allowed after eight beats of an undefined length burst
Arbitration is allowed after 16 beats of an undefined length burst
Reserved
Reserved
Reserved
16.4 Functional Description
16.4.1 General operation
When a master accesses the crossbar switch, the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar.
If the targeted slave port of the access is busy or parked on a different master port, the
requesting master simply sees wait states inserted until the targeted slave port can service
the master's request. The latency in servicing the request depends on each master's
priority level and the responding slave's access time.
Because the crossbar switch appears to be just another slave to the master device, the
master device has no knowledge of whether it actually owns the slave port it is targeting.
While the master does not have control of the slave port it is targeting, it simply waits.
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After the master has control of the slave port it is targeting, the master remains in control
of the slave port until it relinquishes the slave port by running an IDLE cycle or by
targeting a different slave port for its next access.
The master can also lose control of the slave port if another higher-priority master makes
a request to the slave port. However, if the master is running a fixed- or undefined-length
burst transfer it retains control of the slave port until that transfer completes. Based on
MGPCR[AULB], the master either retains control of the slave port when doing
undefined-length, incrementing burst transfers or loses the bus to a higher-priority
master.
The crossbar terminates all master IDLE transfers, as opposed to allowing the termination
to come from one of the slave buses. Additionally, when no master is requesting access to
a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default
master may be granted access to the slave port.
When a slave bus is being idled by the crossbar, it can park the slave port on the master
port indicated by CRSn[PARK] . This is done to save the initial clock of arbitration delay
that otherwise would be seen if the same master had to arbitrate to gain control of the
slave port. The slave port can also be put into Low Power Park mode to save power, by
using CRSn[PCTL].
16.4.2 Register coherency
The operation of the crossbar is affected as soon as a register is written. The values of the
registers do not track with slave-port-related master accesses, but instead track only with
slave accesses.
The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only
recognized when the master on that master port runs an IDLE cycle, even though the
slave bus cycle to write them will have already terminated successfully. If the
MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings
do not take effect until an IDLE cycle is initiated by the master on that master port.
16.4.3 Arbitration
The crossbar switch supports two arbitration algorithms:
• Fixed priority
• Round-robin
The arbitration scheme is independently programmable for each slave port.
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Functional Description
16.4.3.1 Arbitration during undefined length bursts
Arbitration points during an undefined length burst are defined by the current master's
MGPCR[AULB] field setting. When a defined length is imposed on the burst via the
AULB bits, the undefined length burst is treated as a single or series of single back-toback fixed-length burst accesses.
The following figure illustrates an example:
MGPCR[AULB]
No arbitration
Master-to-slave
transfer
1
1 beat
Arbitration allowed
2
3
4
Lost control
5
6
1 beat
Lost control
No arbitration
7
8
9
10
No arbitration
11
12
12 beat burst
Figure 16-2. Undefined length burst example
In this example, a master runs an undefined length burst and the MGPCR[AULB] bits
indicate arbitration occurs after the fourth beat of the burst. The master runs two
sequential beats and then starts what will be a 12-beat undefined length burst access to a
new address within the same slave port region as the previous access. The crossbar does
not allow an arbitration point until the fourth overall access, or the second beat of the
second burst. At that point, all remaining accesses are open for arbitration until the master
loses control of the slave port.
Assume the master loses control of the slave port after the fifth beat of the second burst.
After the master regains control of the slave port no arbitration point is available until
after the master has run four more beats of its burst. After the fourth beat of the now
continued burst, or the ninth beat of the second burst from the master's perspective, is
taken, all beats of the burst are once again open for arbitration until the master loses
control of the slave port.
Assume the master again loses control of the slave port on the fifth beat of the third now
continued burst, or the 10th beat of the second burst from the master's perspective. After
the master regains control of the slave port, it is allowed to complete its final two beats of
its burst without facing arbitration.
Note
Fixed-length burst accesses are not affected by the AULB bits.
All fixed-length burst accesses lock out arbitration until the last
beat of the fixed-length burst.
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16.4.3.2 Fixed-priority operation
When operating in fixed-priority mode, each master is assigned a unique priority level in
the priority registers (PRSn). If two masters request access to the same slave port, the
master with the highest priority in the selected priority register gains control over the
slave port.
NOTE
In this arbitration mode, a higher-priority master can
monopolize a slave port, preventing accesses from any lowerpriority master to the port.
When a master makes a request to a slave port, the slave port checks whether the new
requesting master's priority level is higher than that of the master that currently has
control over the slave port, unless the slave port is in a parked state. The slave port
performs an arbitration check at every clock edge to ensure that the proper master, if any,
has control of the slave port.
The following table describes possible scenarios based on the requesting master port:
Table 16-2. How the Crossbar Switch grants control of a slave port to a master
When
Then the Crossbar Switch grants control to the
requesting master
Both of the following are true:
At the next clock edge
• The current master is not running a transfer.
• The new requesting master's priority level is higher than
that of the current master.
Both of the following are true:
At the end of the burst transfer or locked transfer
• The current master is running a fixed length burst
transfer or a locked transfer.
• The requesting master's priority level is higher than that
of the current master.
Both of the following are true:
At the next arbitration point for the undefined length burst
• The current master is running an undefined length burst transfer
transfer.
• The requesting master's priority level is higher than that NOTE: Arbitration points for an undefined length burst are
defined in the MGPCR for each master.
of the current master.
The requesting master's priority level is lower than the current At the conclusion of one of the following cycles:
master.
• An IDLE cycle
• A non-IDLE cycle to a location other than the current
slave port
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16.4.3.3 Round-robin priority operation
When operating in round-robin mode, each master is assigned a relative priority based on
the master port number. This relative priority is compared to the master port number (ID)
of the last master to perform a transfer on the slave bus. The highest priority requesting
master becomes owner of the slave bus at the next transfer boundary, accounting for
locked and fixed-length burst transfers. Priority is based on how far ahead the ID of the
requesting master is to the ID of the last master.
After granted access to a slave port, a master may perform as many transfers as desired to
that port until another master makes a request to the same slave port. The next master in
line is granted access to the slave port at the next transfer boundary, or possibly on the
next clock cycle if the current master has no pending access request.
As an example of arbitration in round-robin mode, assume the crossbar is implemented
with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and
master 0, 4, and 5 make simultaneous requests, they are serviced in the order: 4 then 5
then 0.
Parking may continue to be used in a round-robin mode, but does not affect the roundrobin pointer unless the parked master actually performs a transfer. Handoff occurs to the
next master in line after one cycle of arbitration. If the slave port is put into low-power
park mode, the round-robin pointer is reset to point at master port 0, giving it the highest
priority.
16.4.3.4 Priority assignment
Each master port must be assigned a unique 3-bit priority level. If an attempt is made to
program multiple master ports with the same priority level within the priority registers
(PRSn), the crossbar switch responds with a bus error and the registers are not updated.
16.5 Initialization/application information
No initialization is required for the crossbar switch.
Hardware reset ensures that all the register bits used by the crossbar switch are properly
initialized to a valid state. However, settings and priorities may be programmed to
achieve maximum system performance.
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NOTE
• During configuration of the crossbar switch, all other
masters must be idle.
• To prevent reconfiguration of the crossbar switch, write 1
to CRSn[RO].
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Chapter 17
Peripheral Bridge
17.1 Chip-specific PBridge information
17.1.1 PBRIDGE Configuration
The peripheral bridge converts the crossbar switch interface to an interface that can
access a majority of peripherals on the device.
This device contains two identical peripheral bridges: PBRIDGE_A (or AIPS_0) and
PBRIDGE_B (or AIPS_1).
For SMPU Logical Bus Master Number, see table Table 20-1.
17.1.2 Register reset values
The following table shows the device-specific register reset values.
Table 17-1. AIPS0 register reset values
Register
Reset value
Master Privilege Register A (AIPS0_MPRA)
0x7775_0000
Master Privilege Register B (AIPS0_MPRB)
0x7770_0000
Peripheral Access Control Register A (AIPS0_PACRA)
0x5400_4000
Peripheral Access Control Register B (AIPS0_PACRB)
0x4440_4004
Peripheral Access Control Register C (AIPS0_PACRC)
0x4000_4400
Peripheral Access Control Register D (AIPS0_PACRD)
0x0044_0000
Peripheral Access Control Register E (AIPS0_PACRE)
0x0000_0000
Peripheral Access Control Register F (AIPS0_PACRF)
0x4000_0000
Peripheral Access Control Register G (AIPS0_PACRG)
0x0000_0000
Peripheral Access Control Register H (AIPS0_PACRH)
0x0000_0000
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Table 17-1. AIPS0 register reset values (continued)
Register
Reset value
Off-platform Peripheral Access Control Register A
(AIPS0_OPACRA)
0x4444_4045
Off-platform Peripheral Access Control Register B
(AIPS0_OPACRB)
0x0004_4004
Off-platform Peripheral Access Control Register C
(AIPS0_OPACRC)
0x0404_0404
Off-platform Peripheral Access Control Register D
(AIPS0_OPACRD)
0x4440_0040
Off-platform Peripheral Access Control Register E
(AIPS0_OPACRE)
0x0040_4040
Off-platform Peripheral Access Control Register F
(AIPS0_OPACRF)
0x0004_0040
Off-platform Peripheral Access Control Register G
(AIPS0_OPACRG)
0x4044_4000
Off-platform Peripheral Access Control Register H
(AIPS0_OPACRH)
0x0000_0000
Off-platform Peripheral Access Control Register I
(AIPS0_OPACRI)
0x0000_0000
Off-platform Peripheral Access Control Register J
(AIPS0_OPACRJ)
0x0000_4444
Off-platform Peripheral Access Control Register K
(AIPS0_OPACRK)
0x0000_0444
Off-platform Peripheral Access Control Register L
(AIPS0_OPACRL)
0x4444_4000
Off-platform Peripheral Access Control Register M
(AIPS0_OPACRM)
0x0044_4400
Off-platform Peripheral Access Control Register N
(AIPS0_OPACRN)
0x0004_0000
Off-platform Peripheral Access Control Register O
(AIPS0_OPACRO)
0x0000_0000
Off-platform Peripheral Access Control Register P
(AIPS0_OPACRP)
0x0000_0004
Off-platform Peripheral Access Control Register Q
(AIPS0_OPACRQ)
0x0000_0000
Off-platform Peripheral Access Control Register R
(AIPS0_OPACRR)
0x0000_0000
Off-platform Peripheral Access Control Register S
(AIPS0_OPACRS)
0x0000_0000
Off-platform Peripheral Access Control Register T
(AIPS0_OPACRT)
0x0000_0000
Off-platform Peripheral Access Control Register U
(AIPS0_OPACRU)
0x0000_0000
Off-platform Peripheral Access Control Register V
(AIPS0_OPACRV)
0x0000_0000
Off-platform Peripheral Access Control Register W
(AIPS0_OPACRW)
0x0000_0000
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Table 17-1. AIPS0 register reset values (continued)
Register
Reset value
Off-platform Peripheral Access Control Register X
(AIPS0_OPACRX)
0x0000_0000
Off-platform Peripheral Access Control Register Y
(AIPS0_OPACRY)
0x0000_0044
Off-platform Peripheral Access Control Register Z
(AIPS0_OPACRZ)
0x4000_0040
Off-platform Peripheral Access Control Register AA
(AIPS0_OPACRAA)
0x0440_0000
Off-platform Peripheral Access Control Register AB
(AIPS0_OPACRAB)
0x0000_0000
Off-platform Peripheral Access Control Register AC
(AIPS0_OPACRAC)
0x0000_0000
Off-platform Peripheral Access Control Register AD
(AIPS0_OPACRAD)
0x0000_0000
Off-platform Peripheral Access Control Register AE
(AIPS0_OPACRAE)
0x0444_0044
Off-platform Peripheral Access Control Register AF
(AIPS0_OPACRAF)
0x0004_0000
Table 17-2. AIPS1 register reset values
Register
Reset value
Master Privilege Register A (AIPS1_MPRA)
0x7775_0000
Master Privilege Register B (AIPS1_MPRB)
0x7770_0000
Peripheral Access Control Register A (AIPS1_PACRA)
0x5000_0000
Peripheral Access Control Register B (AIPS1_PACRB)
0x0000_0000
Peripheral Access Control Register C (AIPS1_PACRC)
0x0000_0000
Peripheral Access Control Register D (AIPS1_PACRD)
0x0000_0000
Peripheral Access Control Register E (AIPS1_OPACRE)
0x0000_0000
Peripheral Access Control Register F (AIPS1_OPACRF)
0x0000_0000
Peripheral Access Control Register G (AIPS1_OPACRG)
0x0000_0000
Peripheral Access Control Register H (AIPS1_OPACRH)
0x0000_0000
Off-platform Peripheral Access Control Register A
(AIPS1_OPACRA)
0x0000_0000
Off-platform Peripheral Access Control Register B
(AIPS1_OPACRB)
0x0000_0000
Off-platform Peripheral Access Control Register C
(AIPS1_OPACRC)
0x0000_0004
Off-platform Peripheral Access Control Register D
(AIPS1_OPACRD)
0x4000_0000
Off-platform Peripheral Access Control Register E
(AIPS1_OPACRE)
0x0000_0000
Off-platform Peripheral Access Control Register F
(AIPS1_OPACRF)
0x0400_0000
Table continues on the next page...
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Chip-specific PBridge information
Table 17-2. AIPS1 register reset values (continued)
Register
Reset value
Off-platform Peripheral Access Control Register G
(AIPS1_OPACRG)
0x0000_0000
Off-platform Peripheral Access Control Register H
(AIPS1_OPACRH)
0x0000_0000
Off-platform Peripheral Access Control Register I
(AIPS1_OPACRI)
0x0000_0000
Off-platform Peripheral Access Control Register J
(AIPS1_OPACRJ)
0x0000_4444
Off-platform Peripheral Access Control Register K
(AIPS1_OPACRK)
0x0000_0444
Off-platform Peripheral Access Control Register L
(AIPS1_OPACRL)
0x4444_4000
Off-platform Peripheral Access Control Register M
(AIPS1_OPACRM)
0x0044_4400
Off-platform Peripheral Access Control Register N
(AIPS1_OPACRN)
0x0000_0000
Off-platform Peripheral Access Control Register O
(AIPS1_OPACRO)
0x0000_0000
Off-platform Peripheral Access Control Register P
(AIPS1_OPACRP)
0x0000_0004
Off-platform Peripheral Access Control Register Q
(AIPS1_OPACRQ)
0x0000_0000
Off-platform Peripheral Access Control Register R
(AIPS1_OPACRR)
0x0000_0000
Off-platform Peripheral Access Control Register S
(AIPS1_OPACRS)
0x0000_0000
Off-platform Peripheral Access Control Register T
(AIPS1_OPACRT)
0x0000_0000
Off-platform Peripheral Access Control Register U
(AIPS1_OPACRU)
0x0000_0000
Off-platform Peripheral Access Control Register V
(AIPS1_OPACRV)
0x0000_0000
Off-platform Peripheral Access Control Register W
(AIPS1_OPACRW)
0x0000_0000
Off-platform Peripheral Access Control Register X
(AIPS1_OPACRX)
0x0000_0000
Off-platform Peripheral Access Control Register Y
(AIPS1_OPACRY)
0x0000_0000
Off-platform Peripheral Access Control Register Z
(AIPS1_OPACRZ)
0x0000_0000
Off-platform Peripheral Access Control Register AA
(AIPS1_OPACRAA)
0x0040_0000
Off-platform Peripheral Access Control Register AB
(AIPS1_OPACRAB)
0x0000_0000
Off-platform Peripheral Access Control Register AC
(AIPS1_OPACRAC)
0x0000_0000
Table continues on the next page...
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Table 17-2. AIPS1 register reset values (continued)
Register
Reset value
Off-platform Peripheral Access Control Register AD
(AIPS1_OPACRAD)
0x0000_0000
Off-platform Peripheral Access Control Register AE
(AIPS1_OPACRAE)
0x0400_4400
Off-platform Peripheral Access Control Register AF
(AIPS1_OPACRAF)
0x4400_0000
17.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 16 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
17.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Supports a pair of 32-bit transactions for selected 64-bit memory accesses
• Programming model provides memory protection functionality
17.2.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 16 KB boundaries. Each peripheral is
allocated one or more 16-KB block(s) of the memory map.
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17.3 Memory map/register definition
The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted
bus masters. Additionally, these registers must be read from or written to only by a 32-bit
aligned access. The peripheral bridge registers are mapped into the Peripheral Access
Control Register A PACRA[PACR0] address space.
AIPS memory map
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
0
Master Privilege Register A (AIPS_MPRA)
32
R/W
See section
17.3.1/404
4
Master Privilege Register B (AIPS_MPRB)
32
R/W
See section
17.3.2/407
100
Peripheral Access Control Register (AIPS_PACRA)
32
R/W
4444_4444h
17.3.3/409
104
Peripheral Access Control Register (AIPS_PACRB)
32
R/W
4444_4444h
17.3.3/409
108
Peripheral Access Control Register (AIPS_PACRC)
32
R/W
4444_4444h
17.3.3/409
10C
Peripheral Access Control Register (AIPS_PACRD)
32
R/W
4444_4444h
17.3.3/409
110
Peripheral Access Control Register (AIPS_PACRE)
32
R/W
4444_4444h
17.3.3/409
114
Peripheral Access Control Register (AIPS_PACRF)
32
R/W
4444_4444h
17.3.3/409
118
Peripheral Access Control Register (AIPS_PACRG)
32
R/W
4444_4444h
17.3.3/409
11C
Peripheral Access Control Register (AIPS_PACRH)
32
R/W
4444_4444h
17.3.3/409
140
Off-Platform Peripheral Access Control Register
(AIPS_OPACRA)
32
R/W
See section
17.3.4/414
144
Off-Platform Peripheral Access Control Register
(AIPS_OPACRB)
32
R/W
See section
17.3.4/414
148
Off-Platform Peripheral Access Control Register
(AIPS_OPACRC)
32
R/W
See section
17.3.4/414
14C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRD)
32
R/W
See section
17.3.4/414
150
Off-Platform Peripheral Access Control Register
(AIPS_OPACRE)
32
R/W
See section
17.3.4/414
154
Off-Platform Peripheral Access Control Register
(AIPS_OPACRF)
32
R/W
See section
17.3.4/414
158
Off-Platform Peripheral Access Control Register
(AIPS_OPACRG)
32
R/W
See section
17.3.4/414
15C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRH)
32
R/W
See section
17.3.4/414
160
Off-Platform Peripheral Access Control Register
(AIPS_OPACRI)
32
R/W
See section
17.3.4/414
164
Off-Platform Peripheral Access Control Register
(AIPS_OPACRJ)
32
R/W
See section
17.3.4/414
168
Off-Platform Peripheral Access Control Register
(AIPS_OPACRK)
32
R/W
See section
17.3.4/414
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AIPS memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
16C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRL)
32
R/W
See section
17.3.4/414
170
Off-Platform Peripheral Access Control Register
(AIPS_OPACRM)
32
R/W
See section
17.3.4/414
174
Off-Platform Peripheral Access Control Register
(AIPS_OPACRN)
32
R/W
See section
17.3.4/414
178
Off-Platform Peripheral Access Control Register
(AIPS_OPACRO)
32
R/W
See section
17.3.4/414
17C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRP)
32
R/W
See section
17.3.4/414
180
Off-Platform Peripheral Access Control Register
(AIPS_OPACRQ)
32
R/W
See section
17.3.4/414
184
Off-Platform Peripheral Access Control Register
(AIPS_OPACRR)
32
R/W
See section
17.3.4/414
188
Off-Platform Peripheral Access Control Register
(AIPS_OPACRS)
32
R/W
See section
17.3.4/414
18C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRT)
32
R/W
See section
17.3.4/414
190
Off-Platform Peripheral Access Control Register
(AIPS_OPACRU)
32
R/W
See section
17.3.4/414
194
Off-Platform Peripheral Access Control Register
(AIPS_OPACRV)
32
R/W
See section
17.3.4/414
198
Off-Platform Peripheral Access Control Register
(AIPS_OPACRW)
32
R/W
See section
17.3.4/414
19C
Off-Platform Peripheral Access Control Register
(AIPS_OPACRX)
32
R/W
See section
17.3.4/414
1A0
Off-Platform Peripheral Access Control Register
(AIPS_OPACRY)
32
R/W
See section
17.3.4/414
1A4
Off-Platform Peripheral Access Control Register
(AIPS_OPACRZ)
32
R/W
See section
17.3.4/414
1A8
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAA)
32
R/W
See section
17.3.4/414
1AC
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAB)
32
R/W
See section
17.3.4/414
1B0
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAC)
32
R/W
See section
17.3.4/414
1B4
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAD)
32
R/W
See section
17.3.4/414
1B8
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAE)
32
R/W
See section
17.3.4/414
1BC
Off-Platform Peripheral Access Control Register
(AIPS_OPACRAF)
32
R/W
See section
17.3.4/414
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17.3.1 Master Privilege Register A (AIPS_MPRA)
This register specifies eight identical 4-bit fields defining the access-privilege level
associated with a bus master in the device to various peripherals. The register provides
one field per bus master. Each master is assigned a logical master number. See the device
configuration information for details.
Address: 0h base + 0h offset = 0h
4
5
7
8
9
10
11
15
0*
0*
0*
0*
0*
0
0
0
0*
0*
0*
0*
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0*
0*
0*
0*
0*
0*
0*
0*
MPL6
0*
0
MTW6
Reset
Reserved
MTR6
W
0
MPL5
1*
MTW5
1*
MTR5
1*
MPL4
0*
MTW4
Reset
W
MTR4
MPL3
14
MTW3
0
13
MTR3
0
12
MPL1
0
6
MTW1
3
MTR1
0
2
MPL0
R
1
MTW0
0
MTR0
Bit
0*
0*
0*
0
Reserved
0*
0
0
0
* Notes:
• Reset value is chip-dependent. See the AIPS chip-specific information.
AIPS_MPRA field descriptions
Field
0
Reserved
1
MTR0
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 0 Trusted For Read
Determines whether the master is trusted for read accesses.
0
1
2
MTW0
Master 0 Trusted For Writes
Determines whether the master is trusted for write accesses.
0
1
3
MPL0
This master is not trusted for read accesses.
This master is trusted for read accesses.
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 0 Privilege Level
Specifies how the privilege level of the master is determined.
Table continues on the next page...
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AIPS_MPRA field descriptions (continued)
Field
Description
0
1
4
Reserved
5
MTR1
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 1 trusted for read
Determines whether the master is trusted for read accesses.
0
1
6
MTW1
This master is not trusted for read accesses.
This master is trusted for read accesses.
Master 1 trusted for writes
Determines whether the master is trusted for write accesses.
0
1
7
MPL1
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 1 privilege level
Specifies how the privilege level of the master is determined.
0
1
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–11
Reserved
This field is reserved.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
MTR3
Master 3 Trusted For Read
Determines whether the master is trusted for read accesses.
0
1
14
MTW3
Master 3 Trusted For Writes
Determines whether the master is trusted for write accesses.
0
1
15
MPL3
17
MTR4
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 3 Privilege Level
Specifies how the privilege level of the master is determined.
0
1
16
Reserved
This master is not trusted for read accesses.
This master is trusted for read accesses.
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 4 Trusted For Read
Determines whether the master is trusted for read accesses.
Table continues on the next page...
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Memory map/register definition
AIPS_MPRA field descriptions (continued)
Field
Description
0
1
18
MTW4
Master 4 Trusted For Writes
Determines whether the master is trusted for write accesses.
0
1
19
MPL4
21
MTR5
Specifies how the privilege level of the master is determined.
Master 5 Trusted For Read
Determines whether the master is trusted for read accesses.
Determines whether the master is trusted for write accesses.
25
MTR6
Specifies how the privilege level of the master is determined.
Master 6 trusted for read
Determines whether the master is trusted for read accesses.
This master is not trusted for read accesses.
This master is trusted for read accesses.
Master 6 trusted for writes
Determines whether the master is trusted for write accesses.
0
1
27
MPL6
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
26
MTW6
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 5 Privilege Level
0
1
24
Reserved
This master is not trusted for read accesses.
This master is trusted for read accesses.
Master 5 Trusted For Writes
0
1
23
MPL5
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
22
MTW5
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 4 Privilege Level
0
1
20
Reserved
This master is not trusted for read accesses.
This master is trusted for read accesses.
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 6 privilege level
Specifies how the privilege level of the master is determined.
Table continues on the next page...
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AIPS_MPRA field descriptions (continued)
Field
Description
0
1
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29–31
Reserved
This field is reserved.
17.3.2 Master Privilege Register B (AIPS_MPRB)
This register specifies eight identical 4-bit fields defining the access-privilege level
associated with a bus master in the device to various peripherals. The register provides
one field per bus master. Each master is assigned a logical master number. See the device
configuration information for details.
Address: 0h base + 4h offset = 4h
4
5
7
8
9
10
11
0
12
13
14
15
0
MPL9
0
6
MTW9
3
MTR9
0
2
MPL8
R
1
MTW8
0
MTR8
Bit
Reset
0*
0*
0*
0*
0*
0*
0*
0*
0*
0
0
0
0*
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
W
0
Reserved
Reserved
0
Reserved
0
Reserved
Reserved
Reserved
W
Reset
0*
0
0
0
0*
0
0
0
0*
0
0
0
0*
0
0
0
* Notes:
• Reset value is chip-dependent. See the AIPS chip-specific information.
AIPS_MPRB field descriptions
Field
0
Reserved
1
MTR8
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Master 8 trusted for read
Determines whether the master is trusted for read accesses.
Table continues on the next page...
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Memory map/register definition
AIPS_MPRB field descriptions (continued)
Field
Description
0
1
2
MTW8
Master 8 trusted for writes
Determines whether the master is trusted for write accesses.
0
1
3
MPL8
5
MTR9
Specifies how the privilege level of the master is determined.
Master 9 trusted for read
Determines whether the master is trusted for read accesses.
This master is not trusted for read accesses.
This master is trusted for read accesses.
Master 9 trusted for writes
Determines whether the master is trusted for write accesses.
0
1
7
MPL9
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
6
MTW9
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 8 privilege level
0
1
4
Reserved
This master is not trusted for read accesses.
This master is trusted for read accesses.
This master is not trusted for write accesses.
This master is trusted for write accesses.
Master 9 privilege level
Specifies how the privilege level of the master is determined.
0
1
Accesses from this master are forced to user-mode.
Accesses from this master are not forced to user-mode.
8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–11
Reserved
This field is reserved.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–15
Reserved
This field is reserved.
16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17–19
Reserved
This field is reserved.
20
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21–23
Reserved
This field is reserved.
Table continues on the next page...
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AIPS_MPRB field descriptions (continued)
Field
Description
24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25–27
Reserved
This field is reserved.
28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29–31
Reserved
This field is reserved.
17.3.3 Peripheral Access Control Register (AIPS_PACRn)
Each of the on-platform peripherals has a 4-bit PACRn field, which defines the access
levels supported by the given module. Eight PACR fields are grouped together to form a
32-bit PACRx register.
The peripheral assignment for each PACR field is defined by the memory map slot that
the peripheral is assigned to. See the device's memory map details for the assignments for
a particular device.
If a peripheral is absent, the corresponding PACR field is not implemented. Reads or
writes to the location of an unimplemented PACR register (because all eight of its
peripherals are absent) should be avoided to prevent undesired behavior.
The following table shows the top-level structure of PACRs.
Offset
Register
[0:3]
[4:7]
[8:11]
[12:15]
[16:19]
[20:23]
[24:27]
[28:31]
0x100
PACRA
PACR0
PACR1
PACR2
PACR3
PACR4
PACR5
PACR6
PACR7
0x104
PACRB
PACR8
PACR9
PACR10
PACR11
PACR12
PACR13
PACR14
PACR15
0x108
PACRC
PACR16
PACR17
PACR18
PACR19
PACR20
PACR21
PACR22
PACR23
0x10C
PACRD
PACR24
PACR25
PACR26
PACR27
PACR28
PACR29
PACR30
PACR31
0x110
PACRE
PACR32
PACR33
PACR34
PACR35
PACR36
PACR37
PACR38
PACR39
0x114
PACRF
PACR40
PACR41
PACR42
PACR43
PACR44
PACR45
PACR46
PACR47
0x118
PACRG
PACR48
PACR49
PACR50
PACR51
PACR52
PACR53
PACR54
PACR55
0x11C
PACRH
PACR56
PACR57
PACR58
PACR59
PACR60
PACR61
PACR62
PACR63
NOTE
The reset value of PACR0 is 0101b.
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Memory map/register definition
Address: 0h base + 100h offset + (4d × i), where i=0d to 7d
Bit
0
R
0
2
SP0
WP0
Reset
0
1
Bit
16
R
3
4
5
6
TP0
0
SP1
WP1
0
0
0
1
17
18
19
20
0
SP4
WP4
TP4
0
1
0
0
W
W
Reset
1
7
8
9
10
13
14
15
TP2
0
SP3
WP3
TP3
0
0
0
1
0
0
25
26
27
28
29
30
31
0
SP6
WP6
TP6
0
SP7
WP7
TP7
0
1
0
0
0
1
0
0
TP1
0
SP2
WP2
0
0
0
1
21
22
23
24
0
SP5
WP5
TP5
0
1
0
0
11
12
AIPS_PACRn field descriptions
Field
0
Reserved
1
SP0
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
2
WP0
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
3
TP0
5
SP1
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
6
WP1
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
4
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_PACRn field descriptions (continued)
Field
Description
0
1
7
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
8
Reserved
9
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
13
SP3
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
14
WP3
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
12
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
11
TP2
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
10
WP2
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_PACRn field descriptions (continued)
Field
Description
0
1
15
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
16
Reserved
17
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
21
SP5
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
22
WP5
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
20
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
19
TP4
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
18
WP4
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_PACRn field descriptions (continued)
Field
Description
0
1
23
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
24
Reserved
25
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
29
SP7
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
30
WP7
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
28
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
27
TP6
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
26
WP6
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_PACRn field descriptions (continued)
Field
Description
0
1
31
TP7
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
17.3.4 Off-Platform Peripheral Access Control Register
(AIPS_OPACRn)
Each of the on-platform peripherals has a 4-bit OPACRn field, which defines the access
levels supported by the given module. Eight OPACR fields are grouped together to form
a 32-bit OPACRx register.
The peripheral assignment for each OPACR field is defined by the memory map slot that
the peripheral is assigned to. See the device's memory map details for the assignments for
a particular device.
If a peripheral is absent, the corresponding OPACR field is not implemented. Reads or
writes to the location of an unimplemented OPACR register (because all eight of its
peripherals are absent) should be avoided to prevent undesired behavior.
The following table shows the top-level structure of OPACRs.
Offset
Register
[0:3]
[4:7]
[8:11]
[12:15]
[16:19]
[20:23]
[24:27]
[28:31]
0x140
OPACRA
OPACR0
OPACR1
OPACR2
OPACR3
OPACR4
OPACR5
OPACR6
OPACR7
0x144
OPACRB
OPACR8
OPACR9
OPACR10 OPACR11 OPACR12 OPACR13 OPACR14 OPACR15
0x148
OPACRC
OPACR16 OPACR17 OPACR18 OPACR19 OPACR20 OPACR21 OPACR22 OPACR23
0x14C
OPACRD
OPACR24 OPACR25 OPACR26 OPACR27 OPACR28 OPACR29 OPACR30 OPACR31
0x150
OPACRE
OPACR32 OPACR33 OPACR34 OPACR35 OPACR36 OPACR37 OPACR38 OPACR39
0x154
OPACRF
OPACR40 OPACR41 OPACR42 OPACR43 OPACR44 OPACR45 OPACR46 OPACR47
0x158
OPACRG
OPACR48 OPACR49 OPACR50 OPACR51 OPACR52 OPACR53 OPACR54 OPACR55
0x15C
OPACRH
OPACR56 OPACR57 OPACR58 OPACR59 OPACR60 OPACR61 OPACR62 OPACR63
0x160
OPACRI
OPACR64 OPACR65 OPACR66 OPACR67 OPACR68 OPACR69 OPACR70 OPACR71
0x164
OPACRJ
OPACR72 OPACR73 OPACR74 OPACR75 OPACR76 OPACR77 OPACR78 OPACR79
0x168
OPACRK
OPACR80 OPACR81 OPACR82 OPACR83 OPACR84 OPACR85 OPACR86 OPACR87
0x16C
OPACRL
OPACR88 OPACR89 OPACR90 OPACR91 OPACR92 OPACR93 OPACR94 OPACR95
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Offset
Register
[0:3]
[4:7]
[8:11]
[12:15]
[16:19]
[20:23]
[24:27]
[28:31]
0x170
OPACRM
OPACR96 OPACR97 OPACR98 OPACR99 OPACR10 OPACR10 OPACR10 OPACR10
0
1
2
3
0x174
OPACRN
OPACR10 OPACR10 OPACR10 OPACR10 OPACR10 OPACR10 OPACR11 OPACR11
4
5
6
7
8
9
0
1
0x178
OPACRO
OPACR11 OPACR11 OPACR11 OPACR11 OPACR11 OPACR11 OPACR11 OPACR11
2
3
4
5
6
7
8
9
0x17C
OPACRP
OPACR12 OPACR12 OPACR12 OPACR12 OPACR12 OPACR12 OPACR12 OPACR12
0
1
2
3
4
5
6
7
0x180
OPACRQ
OPACR12 OPACR12 OPACR13 OPACR13 OPACR13 OPACR13 OPACR13 OPACR13
8
9
0
1
2
3
4
5
0x184
OPACRR
OPACR13 OPACR13 OPACR13 OPACR13 OPACR14 OPACR14 OPACR14 OPACR14
6
7
8
9
0
1
2
3
0x188
OPACRS
OPACR14 OPACR14 OPACR14 OPACR14 OPACR14 OPACR14 OPACR15 OPACR15
4
5
6
7
8
9
0
1
0x18C
OPACRT
OPACR15 OPACR15 OPACR15 OPACR15 OPACR15 OPACR15 OPACR15 OPACR15
2
3
4
5
6
7
8
9
0x190
OPACRU
OPACR16 OPACR16 OPACR16 OPACR16 OPACR16 OPACR16 OPACR16 OPACR16
0
1
2
3
4
5
6
7
0x194
OPACRV
OPACR16 OPACR16 OPACR17 OPACR17 OPACR17 OPACR17 OPACR17 OPACR17
8
9
0
1
2
3
4
5
0x198
OPACRW
OPACR17 OPACR17 OPACR17 OPACR17 OPACR18 OPACR18 OPACR18 OPACR18
6
7
8
9
0
1
2
3
0x19C
OPACRX
OPACR18 OPACR18 OPACR18 OPACR18 OPACR18 OPACR18 OPACR19 OPACR19
4
5
6
7
8
9
0
1
0x1A0
OPACRY
OPACR19 OPACR19 OPACR19 OPACR19 OPACR19 OPACR19 OPACR19 OPACR19
2
3
4
5
6
7
8
9
0x1A4
OPACRZ
OPACR20 OPACR20 OPACR20 OPACR20 OPACR20 OPACR20 OPACR20 OPACR20
0
1
2
3
4
5
6
7
0x1A8
OPACRAA OPACR20 OPACR20 OPACR21 OPACR21 OPACR21 OPACR21 OPACR21 OPACR21
8
9
0
1
2
3
4
5
0x1AC
OPACRAB OPACR21 OPACR21 OPACR21 OPACR21 OPACR22 OPACR22 OPACR22 OPACR22
6
7
8
9
0
1
2
3
0x1B0
OPACRAC OPACR22 OPACR22 OPACR22 OPACR22 OPACR22 OPACR22 OPACR23 OPACR23
4
5
6
7
8
9
0
1
0x1B4
OPACRAD OPACR23 OPACR23 OPACR23 OPACR23 OPACR23 OPACR23 OPACR23 OPACR23
2
3
4
5
6
7
8
9
0x1B8
OPACRAE OPACR24 OPACR24 OPACR24 OPACR24 OPACR24 OPACR24 OPACR24 OPACR24
0
1
2
3
4
5
6
7
0x1BC
OPACRAF OPACR24 OPACR24 OPACR25 OPACR25 OPACR25 OPACR25 OPACR25 OPACR25
8
9
0
1
2
3
4
5
Address: 0h base + 140h offset + (4d × i), where i=0d to 31d
Bit
0
1
2
3
R
0
SP0
WP0
TP0
0*
1*
0*
0*
W
Reset
4
5
6
7
0
SP1
WP1
TP1
0*
1*
0*
0*
8
9
10
11
0
SP2
WP2
TP2
0*
1*
0*
0*
12
13
14
15
0
SP3
WP3
TP3
0*
1*
0*
0*
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Bit
16
17
18
19
R
0
SP4
WP4
TP4
0*
1*
0*
0*
W
Reset
20
21
22
23
0
SP5
WP5
TP5
0*
1*
0*
0*
24
25
26
27
0
SP6
WP6
TP6
0*
1*
0*
0*
28
29
30
31
0
SP7
WP7
TP7
0*
1*
0*
0*
* Notes:
• Reset value is chip-dependent. See the AIPS chip-specific information.
AIPS_OPACRn field descriptions
Field
0
Reserved
1
SP0
Description
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
2
WP0
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
3
TP0
5
SP1
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this field is set, the
master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field
for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
6
WP1
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
4
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_OPACRn field descriptions (continued)
Field
Description
0
1
7
TP1
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
8
Reserved
9
SP2
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute MPR x [MPL n ], and the MPR x [MPL
n ] control bit for the master must be set. If not, access terminates with an error response and no
peripheral access initiates.
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
13
SP3
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
14
WP3
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
12
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
11
TP2
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
10
WP2
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write access. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_OPACRn field descriptions (continued)
Field
Description
0
1
15
TP3
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
16
Reserved
17
SP4
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
21
SP5
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
22
WP5
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
20
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
19
TP4
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
18
WP4
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
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AIPS_OPACRn field descriptions (continued)
Field
Description
0
1
23
TP5
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
24
Reserved
25
SP6
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
29
SP7
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
0
1
30
WP7
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
0
1
28
Reserved
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
0
1
27
TP6
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This field is reserved.
This read-only field is reserved and always has the value 0.
0
1
26
WP6
This peripheral allows write accesses.
This peripheral is write protected.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
Write Protect
Determines whether the peripheral allows write accesses. When this field is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
Table continues on the next page...
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Functional description
AIPS_OPACRn field descriptions (continued)
Field
Description
0
1
31
TP7
This peripheral allows write accesses.
This peripheral is write protected.
Trusted Protect
Determines whether the peripheral allows accesses from an untrusted master. When this field is set and
an access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
17.4 Functional description
The peripheral bridge functions as a bus protocol translator between the crossbar switch
and the slave peripheral bus.
Support is provided for generating a pair of 32-bit slave accesses when performing
certain 64-bit peripheral accesses.
The peripheral bridge manages all transactions destined for the attached slave devices and
generates select signals for modules on the peripheral bus by decoding accesses within
the attached address space.
17.4.1 Access support
All combinations of access size and peripheral data port width are supported. An access
that is larger than the target peripheral's data width will be decomposed to multiple,
smaller accesses. Bus decomposition is terminated by a transfer error caused by an access
to an empty register area.
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Chapter 18
Decorated Storage Memory Controller (DSMC)
18.1 Introduction
This section details the hardware support for atomic read-modify-write memory
operations. In the Power Architecture, these capabilities are called "decorated storage". It
is supported by capabilities in the processor cores plus instantiations of a Decorated
Storage Memory Controller (DSMC).
The Decorated Storage APU defines instructions for providing load and store operations
to memory addresses that require additional semantics beyond just the reading and
writing of data values to the addressed memory locations. Decorated storage operations
are intended to be used for specific devices or memory targets that require these
additional semantics. A "decoration" is the additional semantic information to be applied
to the decorated storage operation by the DSMC.
Consider the basic mnemonics, syntax and formats for the decorated load instructions.
For loads, the syntax is l[b,h,w]d{cb}x rT,rB,rA where the data size specifier is defined as
8-bit (b = byte), 16-bit (h = halfword) or 32-bit (w = word), and the three register specifiers
include rT as the destination target register, rB as the effective address and rA as the
decoration. The optional {cb} specifier defines a version of the instruction which is treated
as a cache bypass operation.
The syntax for store instruction is st[b,h,w]d{cb}x rS,rB,rA where the same data size
specifiers are used, and the three register specifiers are rS as the source data register, rB as
the effective address and rA as the decoration. The cache bypass attribute is again
specified with the use of the optional {cb} in the instruction mnemonic.
For all decorated loads and stores, the memory effective address is simply defined by the
rB register (hence the "x" mnemonic suffix, signaling an "indexed" addressing mode) and
the decoration is specified by the rA register. The core transmits the contents of the rA
register as the decoration value along with the access address (register rB) to the DSMC.
The decorated load and store instruction formats are shown in the following figure.
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Introduction
Table 18-1. Power Architecture decorated load and store instruction formats
0
1
2
3
4
5
6
7
8
lbdx
0
1
1
1
1
1
rT
rA
rB
1
0
0
0
0
0
0
0
1
1
/
lhdx
0
1
1
1
1
1
rT
rA
rB
1
0
0
0
1
0
0
0
1
1
/
lwdx
0
1
1
1
1
1
rT
rA
rB
1
0
0
1
0
0
0
0
1
1
/
lbdcbx
0
1
1
1
1
1
rT
rA
rB
1
0
0
0
0
0
0
0
1
0
/
lhdcbx
0
1
1
1
1
1
rT
rA
rB
1
0
0
0
1
0
0
0
1
0
/
lwdcbx
0
1
1
1
1
1
rA
rB
1
0
0
1
0
0
0
0
1
0
/
0
1
2
3
4
5
stbdx
0
1
1
1
1
1
rS
rA
rB
1
0
1
0
0
0
0
0
1
1
/
sthdx
0
1
1
1
1
1
rS
rA
rB
1
0
1
0
1
0
0
0
1
1
/
stwdx
0
1
1
1
1
1
rS
rA
rB
1
0
1
1
0
0
0
0
1
1
/
stbdcbx
0
1
1
1
1
1
rS
rA
rB
1
0
1
0
0
0
0
0
1
0
/
sthdcbx
0
1
1
1
1
1
rS
rA
rB
1
0
1
0
1
0
0
0
1
0
/
stwdcbx
0
1
1
1
1
1
rS
rA
rB
1
0
1
1
0
0
0
0
1
0
/
rT
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
The basic decorated load or store memory reference supplements the access address and
attribute information with a 32-bit "decoration". The DSMC decoration defines the
special memory operation to be performed and optionally includes bit specifiers and/or
operand data for the command.
The default format for the 32-bit decoration field defines a 4-bit command in the most
significant bits (decoration[0:3]).
The cache bypass decoration load (l[b,h,w]dcbx) and store (st[b,h,w]dcbx) instructions do
not distinguish between cacheable and cache-inhibited storage attributes, and instead
have semantics to effectively emulate a cache-inhibited operation to storage regardless of
the actual storage attributes. This is desired in order to allow a small portion of an
otherwise cacheable storage area to be treated as non-cacheable using instruction
supplied semantics, regardless of storage attributes provided by a memory management,
protection or other memory control scheme. This allows decoration or other accesses to
be applied to a portion of memory that is normally treated as cacheable according to its
storage attributes, as well as to ensure that any stale copies of storage locations present in
the cache are not used.
The combination of the decorated load and store instruction support in the e200zX cores
plus the decorated storage memory controller in the core platform adds a robust atomic
read-modify-write capability to the Power Architecture. The architecture capability
defined by these core and platform functions is targeted at manipulation of n-bit fields in
peripheral registers (and is consistent with I/O hardware addressing in the Embedded C
standard) as well as software synchronization data structures needed in multi-core
systems (mutexes, semaphores, test-and-set and compare-and-swap structures).
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Chapter 18 Decorated Storage Memory Controller (DSMC)
For additional information on the decorated load and store instructions from the core's
perspective, refer to the appropriate e200zX core reference manual.
18.2 Decorated stores: st[b,h,w]d{cb}x rS,rA,rB
The next sections present descriptions of the specific operations, based on the 4-bit
command field defined in decoration[0:3]. These descriptions include the bit pattern
definitions for the 32-bit decoration value and include pseudo-code detailing the
sequence of operations. The decoration formats are defined using a <command>.<size> syntax
where the operand size specifier is b (byte, 8-bit), h (halfword, 16-bit) or w (word, 32bit). The operand size is specified directly in the decorated instruction executed in the
core, and this attribute is driven to the system bus as part of the decorated data transfer.
Additionally, the write data is taken from the right-justified 8, 16 or 32 bits of the rS
register, that is:
8-bit wdata = rS[24:31]
16-bit wdata = rS[16:31]
32-bit wdata = rS[ 0:31]
Likewise, read data is loaded into the right-justified 8, 16 or 32 bits of the rT register:
8-bit rdata = rT[24:31]
16-bit rdata = rT[16:31]
32-bit rdata = rT[ 0:31]
For the byte and halfword decorated load instructions, the upper bits of the rT register are
zero filled.
The starting bit (SRTBIT) position follows the Power Architecture convention where the
MSB is bit 0 and the LSB is bit 31. The bit field width (BFW) value defines the width
and BFW = 0 specifies the maximum width, that is, the container size.
The basic decorated store includes three data transfer fields sourced from the core: the
access address (rB), the decoration (rA) and the write data (wdata) operand (rS). There
are five operations defined and most of these transactions convert a single core AHB
write bus cycle into an atomic read-modify-write, that is, an indivisible read followed by
write sequence. Support for three basic boolean logic functions (AND, OR, XOR) is
provided along with a compare-and-store operation plus a bit field insert operation. These
operations do not support any type of bit field wrapping.
In the next sections detailing the decorated store operations, the following associations
between the pseudocode variables and the core registers apply.
• decoration = rA
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Decorated stores: st[b,h,w]d{cb}x rS,rA,rB
• accessAddress = rB
• wdata = rS
18.2.1 Bit Field Insert (BFINS) into an 8, 16 or 32-bit memory
container
Table 18-2. Decoration format: BFINS
0
1
2
3
4
5
6
7
8
bfins.b 0
0
0
0
0
0
0
SRTBIT
bfins.h 0
0
0
0
0
0
bfins.w 0
0
0
0
0
SRTBIT
SRTBIT
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
BFW
BFW
BFW
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command inserts a bit field defined by SRTBIT and BFW into the memory
"container" defined by the access size associated with the decorated store instruction
using an atomic read-modify-write sequence.
tmp = mem[accessAddress, size] // memory read
if bfw == 0
then bfw = container
if ((srtbit + bfw) <= container) // generate bit mask
mask = ((1 << bfw) - 1) << (container - (srtbit + bfw))
else
mask = ((1 << bfw) - 1) >> ((srtbit + bfw) - container)
tmp = tmp & ~mask// modify
| wdata & mask
mem[accessAddress, size] = tmp // memory write
The write data operand (wdata) associated with the decorated store instruction contains
the bit field to be inserted. It must be properly aligned within a right-justified container in
the source register (rS), that is, within the lower 8 bits for a byte operation, the lower 16
bits for a halfword or the entire 32 bits for a word operation.
To illustrate, consider the following example of the insertion of the 3-bit field "xyz" into
an 8-bit memory container, initially set to "abcd_efgh". For all cases, the bit field width
(BFW) is 3.
if SRTBIT = 0 and the decorated store rS register[24:31] = xyz-_----,
then destination is "xyzd_efgh"
if SRTBIT = 1 and the decorated store rS register[24:31] = -xyz_----,
then destination is "axyz_efgh"
if SRTBIT = 2 and the decorated store rS register[24:31] = --xy_z---,
then destination is "abxy_zfgh"
if SRTBIT = 3 and the decorated store rS register[24:31] = ---x_yz--,
then destination is "abcx_yzgh"
if SRTBIT = 4 and the decorated store rS register[24:31] = ---_xyz-,
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then destination is "abcd_xyzh"
if SRTBIT = 5 and the decorated store rS register[24:31] = ---_-xyz,
then destination is "abcd_exyz"
if SRTBIT = 6 and the decorated store rS register[24:31] = ---_--xy,
then destination is "abcd_efxy"
if SRTBIT = 7 and the decorated store rS register[24:31] = ---_---x,
then destination is "abcd_efgx"
If the bit field insert operation specifies SRTBIT as 0 and BFW as 0 (indicating the width
matches the container width), then the operation is logically equivalent to a simple
register store operation.
18.2.1.1 Compare-and-Store (CAST)
Table 18-3. Decoration format: CAST
cast.b
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
0
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
cast.h
1
0
0
1
cast.w
1
0
0
1
-
-
-
-
-
-
-
-
CD8
CD16
CD28
This command begins by performing a read of the referenced memory address and
comparing that data with the operand included in the decoration word. If the read data is
equal to the compare operand, the write data associated with the decorated store
instruction is placed into the memory location, else the original read data is rewritten into
the memory location. The write operand is selected from the appropriate data byte lanes
in the same manner as any memory store operation; this implies the write data operand is
right justified in the rS source register.
tmp = mem[accessAddress, size]
// memory read
if (size == 8)
// define compare_operand
compare_operand = CD8
else if (size == 16)
compare_operand = CD16
else compare_operand = {0x0, CD28}// zero-filled data
if (tmp == compare_operand) // compare - "modify"
mem[accessAddress, size] = wdata// memory write
else mem[accessAddress, size] = tmp
Note for the word size operation (cast.w), the data value specified in the low-order 28 bits
of the decoration is zero filled in the most significant bits to create the required 32 bit
compare operand.
18.2.1.1.1
0
Logical AND (AND)
Table 18-4. Decoration format: AND
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Table continues on the next page...
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Decorated stores: st[b,h,w]d{cb}x rS,rA,rB
Table 18-4. Decoration format: AND (continued)
and.
{b,h,w}
1
0
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command performs an atomic read-modify-write of the referenced memory location.
First, the location is read; it is then modified by performing a logical AND operation
using the write operand defined by the rS register; finally, the result of the AND
operation is written back into the referenced memory location.
tmp = mem[accessAddress, size] // memory read
tmp = tmp & wdata
// modify
mem[accessAddress, size] = tmp// memory write
18.2.1.1.2
Logical OR (OR)
Table 18-5. Decoration format: OR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
or.{b,h,w} 1
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command performs an atomic read-modify-write of the referenced memory location.
First, the location is read; it is then modified by performing a logical OR operation using
the write operand defined by the rS register; finally, the result of the OR operation is
written back into the referenced memory location.
tmp = mem[accessAddress, size] // memory read
tmp = tmp | wdata
// modify
mem[accessAddress, size] = tmp// memory write
Logical Exclusive-OR (XOR)
18.2.1.1.3
xor.
{b,h,w}
Table 18-6. Decoration format: XOR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
1
1
1
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command performs an atomic read-modify-write of the referenced memory location.
First, the location is read; it is then modified by performing a logical XOR operation
using the write operand defined by the rS register; finally, the result of the XOR
operation is written back into the referenced memory location.
tmp = mem[accessAddress, size] // memory read
tmp = tmp ^ wdata
// modify
mem[accessAddress, size] = tmp// memory write
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18.2.1.2 Decorated Loads: l[b,h,w]d{cb}x rT,rA,rB
The basic decorated load includes two data transfer fields sourced from the core: the
access address (rB), the decoration (rA) plus the read data (rdata) operand returned from
DSMC to the core and loaded into the destination register (rT). There are 3 operations
defined and two of these transactions convert a single core AHB read bus cycle into an
atomic read-modify-write. Support for a swap function, a load-and-set-1-bit functions are
provided along with a simple load (aka an "extract") operation.
In the next sections detailing the decorated load operations, the following associations
between the pseudocode variables and the core registers apply.
• decoration = rA
• accessAddress = rB
• rdata = rT
18.2.1.2.1
sld.
{b,h,w}
Simple Load (SLD)
Table 18-7. Decoration format: SLD
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command performs a simple memory load of the reference size from the access
address. For this operation, the 12-bit field defined in decoration[4:15] must be zeroes
else the transfer is not performed and error terminated.
rdata = mem[accessAddress, size] // memory read
Support for generic bit field extract operations is best handled using existing core and
compiler capabilities involving standard load instructions followed by left and right shift
operations to emulate these functions.
18.2.1.2.2
Registers-and-memory exchange (SWAP)
Table 18-8. Decoration format: SWAP
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
swap.b
0
1
0
1
-
-
-
-
-
-
-
-
-
-
-
-
swap.h
0
1
0
1
-
-
-
-
-
-
-
-
-
-
-
-
swap.w
0
1
0
1
-
-
-
-
-
-
-
-
WD8
WD16
WD28
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DSMC instantiations
This command loads the contents of the referenced memory location into the core's rT
register and stores the source operand from the core's rA register (the decoration) into the
memory location.
tmp
= mem[accessAddress, size] // memory read
rdata = tmp// rT = rdata = tmp
if (size == 8)
// store_operand - "modify"
store_operand = WD8
else if (size == 16)
store_operand = WD16
else store_operand = {0x0, WD28} // zero-filled write data
mem[accessAddress, size] = store_operand// memory write
Note for the word size operation (swap.w), the data value specified in the low-order 28
bits of the decoration is zero filled in the most significant bits to create the required 32 bit
store operand.
18.2.1.2.3
Load-and-Set-1(Bit) (LAS1)
Table 18-9. Decoration format: LAS1
0
1
2
3
4
5
6
las1.b
0
1
1
0
0
0
0
las1.h
0
1
1
0
0
0
las1.w
0
1
1
0
0
7
8
BIT
BIT
BIT
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
This command first reads the referenced memory location; it then modifies the read
operand by setting the single bit position defined in the decoration (BIT); the modified
data is then written back to the referenced memory location and the original read data
returned to the initiating processor core.
tmp
= mem[accessAddress, size] // memory read
rdata = tmp // rT = rdata = tmp
mask = 1 << (container - bit - 1) // generate bit mask
tmp
= tmp | mask// modify
mem[accessAddress, size] = tmp// memory write
18.3 DSMC instantiations
The decorated storage memory controller which performs these operations is instantiated
multiple times within the core platform and physically resides between the slave ports of
the crossbar and the targeted memory controllers.
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The module includes error checking logic that validates the decoration field is properly
defined (all illegal commands are rejected and the transfer error terminated).
Additionally, the decorated memory controller only operates on aligned, single data
transfers (misalignment and/or bursts are not supported and error terminated if
attempted).
As the DSMC generates the atomic read-modify-write bus transactions to the attached
slave memory controller, the two transactions (read, write) are fully pipelined with no
idle cycles introduced. During these transactions, the AHB hlock control signal is
asserted to the slave during the entire read-modify-write.
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DSMC instantiations
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Chapter 19
Intelligent AHB Gasket (IAHBG)
19.1 Chip-specific IAHBG information
19.1.1 IAHBG configuration
Table 19-1 shows the operating modes implemented in the IAHBG on this chip.
Table 19-1. IAHBG implemented operation modes
Operating mode
(Master:Slave)
Comments
1:1
Master and slave at same operating frequency; gasket performance optimizations on by
default
2:1
Master at twice frequency of slave; gasket performance optimizations on by default
1:2
Slave at twice frequency of master; gasket performance optimizations on by default
4:1
Master at four times frequency of slave; gasket performance optimizations disabled at this time
1:4
Slave at four times frequency of master; gasket performance optimizations disabled at this time
19.1.2 IAHBG clock selection ratios
The IAHBG is used as a bus gasket to connect buses running at different bus clock
speeds. Internal signals generated by the MC_CGL are connected to the IAHBG module
that determine the clock ratio selection. Clock ratio setting for the IAHBG is controlled
using DFS configurations. Refer Dynamic Frequency Scaling for details.
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Introduction
19.1.3 IAHBG features enabled by Platform Configuration
Module (PCM)
The Platform Configuration Module (PCM) is used to enable/disable features of the
IAHBG module. In general, the default setting in the PCM enables IAHBG features for
the highest performance case.
19.2 Introduction
This section details the intelligent bridging gasket between the fast and slow clock
domains. The intelligent operation of the gasket initiates pending reads early and
optimizes bursts to recover some of the performance that is lost on a registered interface
between different clock domains. Pending reads begin even if there is not an hready to
the master. Non-bursted writes only begin when the slave is IDLE, pending writes wait
until IDLE.
The IAHBG complies with the AHBV6lite protocol, including an extension to support
masters that do address retraction during the error termination sequence or abort a burst
read due to an error termination or another non-error termination like cache inhibit
termination.
Table 19-2 lists the available operation modes.
Table 19-2. Operation modes available
Operating mode
(Master:Slave)
Comments
0:0
Flowthru (no register wall)
1:1
Master and slave at same operating frequency; gasket performance optimizations on by
default
2:1
Master at twice frequency of slave; gasket performance optimizations on by default
1:2
Slave at twice frequency of master; gasket performance optimizations on by default
4:1
Master at four times frequency of slave; gasket performance optimizations disabled at this
time
1:4
Slave at four times frequency of master; gasket performance optimizations disabled at this
time
19.3 Timing modes
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19.3.1 1:1
In the 1:1 timing mode the master is running at the same clock frequency as the slave.
The pending read can either be a single or burst transaction.
19.3.2 2:1
In the 2:1 timing mode the master is running at twice the clock frequency of the slave.
The 4:1 mode is not shown because it is very similar to the 2:1 mode. The pending read
can either be a single or burst transaction.
19.3.3 1:2
In the 1:2 timing mode, the slave is running at twice the clock frequency of the master.
The 1:4 mode is not shown because it is very similar to the 1:2 mode. The pending read
can either be a single or burst transaction.
Because the slave is operating at a faster clock frequency than the master, the transactions
from the master must be stored into a queue of data and response attribute registers. At a
certain point during the master burst transactions, the queue is either emptied into the
master for a burst read or it is emptied into the slave for a burst write..
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Timing modes
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Chapter 20
System Memory Protection Unit (SMPU)
20.1 Chip-specific SMPU information
20.1.1 System Memory Protection Unit (SMPU) configuration
This chip contains one instance of the System Memory Protection Unit (SMPU):
• SMPU_0 protects flash, peripherals and RAM.
The following figure explains how SMPU is configured on this chip.
Core
Logical
Master
Transfers
Logical
Master
Register
Access
Transfers
Slave
Slave
SMPU_x
Logical
Master
Slave
Figure 20-1. SMPU configuration
Table 20-1. SMPU Logical Bus Master Number
Master Name
Master ID
e200Z4
0
e200Z2
1
HSM
3
eDMA
4
Ethernet
5
FlexRAY
6
Table continues on the next page...
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Chip-specific SMPU information
Table 20-1. SMPU Logical Bus Master Number (continued)
Master Name
Master ID
Debug e200Z4
8
Debug e200Z2
9
NOTE
Only Z4, Z2, and HSM core provide process identifier to
SMPU.
NOTE
PID miss error does not occur for Debug e200Z4 and Debug
e200Z2.
20.1.1.1 SMPU core exceptions
The core interrupt handling for a SMPU protected access is summarized in the following
table:
SMPU Protected Access
Z4
Z2
Read
Data Storage Exception
Data Storage Exception
Write
See below
Data Storage Exception
Execute
Instruction Storage exception
Instruction Storage exception
The Z4 core interrupt handling for a SMPU protected write access is summarized in the
following table:
MSR[ME]
HDBCR0[DSB]
Exception
0
0
No exception
0
1
Data Storage
1
0
Machine Check
1
1
Data Storage
The Z4 core has a store buffer and when enabled any core store to a SMPU protected
region will be imprecise. For this scenario an imprecise data access will result in a
machine check interrupt, when the machine check interrupt is enabled at Machine State
Register (MSR). For the case when the data storage buffer is disabled the Z4 core will
issue a data storage exception.
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Chapter 20 System Memory Protection Unit (SMPU)
HDBCR0 is the hardware debug cache control register. This register would not normally
be used by a normal user. It is intended to be used only by debugger vendors. Please refer
to the e200z4 Core Reference manual for details.
20.1.2 Default guarded region of cores
The cores on the device treats the following memory region as guarded by default:
• Guarded Region0: Address 0xFC00_0000 to 0xFFFF_FFFF
• Guarded Region1: Address 0xF800_0000 to 0xFBFF_FFFF
20.2 Overview
The System Memory Protection Unit (SMPU) provides hardware access control for
system bus memory references. The SMPU concurrently monitors system bus
transactions and evaluates their appropriateness using preprogrammed region descriptors
that define memory spaces and their access rights. Memory references that have
sufficient access control rights are allowed to complete, while references that are not
mapped to any region descriptor or have insufficient rights are terminated with an access
error response.
20.2.1 Block diagram
A simplified block diagram of the SMPU module is shown in the following figure. The
access signals coming from the crossbar switch slave ports are shown on the left. The
access evaluation macros and region descriptors are in the middle, and the peripheral bus
interface is on the right side.
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Overview
Crossbar slave ports:
Register
access
Access signals
Access
evaluation
macro
Region
descriptor 0
Access
evaluation
macro
Region
descriptor 1
Access
evaluation
macro
Region
descriptor (x-1)
EARn
EDRn
Mux
Figure 20-2. SMPU block diagram
The access evaluation macros determine hits to memory regions and detect violations to
access protections. If a violation is detected, the macros update the appropriate master's
error registers. For details of the access evaluation macro, see Access evaluation macro.
20.2.2 Features
The SMPU feature set includes:
• Support for a maximum of 16 program-visible 192-bit region descriptors, accessible
as six 32-bit words each.
• Each region descriptor defines an arbitrarily-sized space, aligned anywhere in
memory.
• Region sizes can vary from a minimum of 16 bytes to a maximum of (4 GB
– 16 bytes).
• Read/write access control permissions are defined in the region descriptor.
• Global cache-inhibit attribute indicator.
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Chapter 20 System Memory Protection Unit (SMPU)
• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency
issues.
• Priority given to granting permission over denying access for overlapping region
descriptors.
• Detection of access errors if a memory reference does not hit in any memory region,
or if the reference is illegal in all hit memory regions. If an access error occurs, the
reference is terminated with an error response, and the SMPU inhibits the bus cycle
being sent to the targeted slave device.
• Instruction storage (ISI) or data storage (DSI) interrupts generated by aborted core
accesses.
• Error registers (per bus master ID) capture the last faulting address, attributes, and
other information.
• Global SMPU enable/disable control bit.
20.3 Memory map/register definition
The programming model is partitioned into three groups:
• Control registers
• Error capture registers
• Data structure containing the region descriptors
The programming model can be referenced only in supervisor mode using 32-bit
accesses. Attempted references with a different access size, to an undefined (reserved)
address, with a non-supported access type (a write to a read-only register, or a read of a
write-only register), or in user mode generate an error termination.
NOTE
See the chip configuration details for any chip-specific register
information for this module. For example, a specific instance of
the module may support only eight or fewer region descriptors.
SMPU memory map
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
0
Control/Error Status Register 0 (SMPU_CES0)
32
R/W
0000_8008h
20.3.1/445
4
Control/Error Status Register 1 (SMPU_CES1)
32
R/W
0000_8004h
20.3.2/446
100
Error Address Register, Bus Master (SMPU_ERR_ADR0)
32
R
0000_0000h
20.3.3/447
Table continues on the next page...
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Memory map/register definition
SMPU memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
104
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL0)
32
R
0000_0000h
20.3.4/448
108
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL0)
32
R
0000_0080h
20.3.5/449
110
Error Address Register, Bus Master (SMPU_ERR_ADR1)
32
R
0000_0000h
20.3.3/447
114
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL1)
32
R
0000_0000h
20.3.4/448
118
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL1)
32
R
0000_0080h
20.3.5/449
120
Error Address Register, Bus Master (SMPU_ERR_ADR2)
32
R
0000_0000h
20.3.3/447
124
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL2)
32
R
0000_0000h
20.3.4/448
128
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL2)
32
R
0000_0080h
20.3.5/449
130
Error Address Register, Bus Master (SMPU_ERR_ADR3)
32
R
0000_0000h
20.3.3/447
134
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL3)
32
R
0000_0000h
20.3.4/448
138
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL3)
32
R
0000_0080h
20.3.5/449
140
Error Address Register, Bus Master (SMPU_ERR_ADR4)
32
R
0000_0000h
20.3.3/447
144
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL4)
32
R
0000_0000h
20.3.4/448
148
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL4)
32
R
0000_0080h
20.3.5/449
150
Error Address Register, Bus Master (SMPU_ERR_ADR5)
32
R
0000_0000h
20.3.3/447
154
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL5)
32
R
0000_0000h
20.3.4/448
158
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL5)
32
R
0000_0080h
20.3.5/449
160
Error Address Register, Bus Master (SMPU_ERR_ADR6)
32
R
0000_0000h
20.3.3/447
164
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL6)
32
R
0000_0000h
20.3.4/448
168
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL6)
32
R
0000_0080h
20.3.5/449
170
Error Address Register, Bus Master (SMPU_ERR_ADR7)
32
R
0000_0000h
20.3.3/447
174
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL7)
32
R
0000_0000h
20.3.4/448
178
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL7)
32
R
0000_0080h
20.3.5/449
180
Error Address Register, Bus Master (SMPU_ERR_ADR8)
32
R
0000_0000h
20.3.3/447
184
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL8)
32
R
0000_0000h
20.3.4/448
188
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL8)
32
R
0000_0080h
20.3.5/449
Table continues on the next page...
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
190
Error Address Register, Bus Master (SMPU_ERR_ADR9)
32
R
0000_0000h
20.3.3/447
194
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL9)
32
R
0000_0000h
20.3.4/448
198
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL9)
32
R
0000_0080h
20.3.5/449
1A0
Error Address Register, Bus Master (SMPU_ERR_ADR10)
32
R
0000_0000h
20.3.3/447
1A4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL10)
32
R
0000_0000h
20.3.4/448
1A8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL10)
32
R
0000_0080h
20.3.5/449
1B0
Error Address Register, Bus Master (SMPU_ERR_ADR11)
32
R
0000_0000h
20.3.3/447
1B4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL11)
32
R
0000_0000h
20.3.4/448
1B8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL11)
32
R
0000_0080h
20.3.5/449
1C0
Error Address Register, Bus Master (SMPU_ERR_ADR12)
32
R
0000_0000h
20.3.3/447
1C4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL12)
32
R
0000_0000h
20.3.4/448
1C8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL12)
32
R
0000_0080h
20.3.5/449
1D0
Error Address Register, Bus Master (SMPU_ERR_ADR13)
32
R
0000_0000h
20.3.3/447
1D4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL13)
32
R
0000_0000h
20.3.4/448
1D8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL13)
32
R
0000_0080h
20.3.5/449
1E0
Error Address Register, Bus Master (SMPU_ERR_ADR14)
32
R
0000_0000h
20.3.3/447
1E4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL14)
32
R
0000_0000h
20.3.4/448
1E8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL14)
32
R
0000_0080h
20.3.5/449
1F0
Error Address Register, Bus Master (SMPU_ERR_ADR15)
32
R
0000_0000h
20.3.3/447
1F4
Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTL15)
32
R
0000_0000h
20.3.4/448
1F8
Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDL15)
32
R
0000_0080h
20.3.5/449
400
Region Descriptor n, Word 0 (SMPU_RGD0_WRD0)
32
R/W
0000_0000h
20.3.6/450
404
Region Descriptor n, Word 1 (SMPU_RGD0_WRD1)
32
R/W
0000_000Fh
20.3.7/450
408
Region Descriptor n, Word 2 Format 0
(SMPU_RD_0W2_F0)
32
R/W
0000_0000h
20.3.8/451
408
Region Descriptor n, Word 2 Format 1
(SMPU_RD_0W2_F1)
32
R/W
0000_0000h
20.3.9/452
40C
Region Descriptor n, Word 3 (SMPU_RGD0_WRD3)
32
R/W
0000_0000h
20.3.10/454
410
Region Descriptor n, Word 4 (SMPU_RGD0_WRD4)
32
R/W
0000_0000h
20.3.11/456
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Memory map/register definition
SMPU memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
414
Region Descriptor n, Word 5 (SMPU_RGD0_WRD5)
32
R/W
0000_0000h
20.3.12/457
440
Region Descriptor n, Word 0 (SMPU_RGD1_WRD0)
32
R/W
0000_0000h
20.3.6/450
444
Region Descriptor n, Word 1 (SMPU_RGD1_WRD1)
32
R/W
0000_000Fh
20.3.7/450
448
Region Descriptor n, Word 2 Format 0
(SMPU_RD_1W2_F0)
32
R/W
0000_0000h
20.3.8/451
448
Region Descriptor n, Word 2 Format 1
(SMPU_RD_1W2_F1)
32
R/W
0000_0000h
20.3.9/452
44C
Region Descriptor n, Word 3 (SMPU_RGD1_WRD3)
32
R/W
0000_0000h
20.3.10/454
450
Region Descriptor n, Word 4 (SMPU_RGD1_WRD4)
32
R/W
0000_0000h
20.3.11/456
454
Region Descriptor n, Word 5 (SMPU_RGD1_WRD5)
32
R/W
0000_0000h
20.3.12/457
480
Region Descriptor n, Word 0 (SMPU_RGD2_WRD0)
32
R/W
0000_0000h
20.3.6/450
484
Region Descriptor n, Word 1 (SMPU_RGD2_WRD1)
32
R/W
0000_000Fh
20.3.7/450
488
Region Descriptor n, Word 2 Format 0
(SMPU_RD_2W2_F0)
32
R/W
0000_0000h
20.3.8/451
488
Region Descriptor n, Word 2 Format 1
(SMPU_RD_2W2_F1)
32
R/W
0000_0000h
20.3.9/452
48C
Region Descriptor n, Word 3 (SMPU_RGD2_WRD3)
32
R/W
0000_0000h
20.3.10/454
490
Region Descriptor n, Word 4 (SMPU_RGD2_WRD4)
32
R/W
0000_0000h
20.3.11/456
494
Region Descriptor n, Word 5 (SMPU_RGD2_WRD5)
32
R/W
0000_0000h
20.3.12/457
4C0
Region Descriptor n, Word 0 (SMPU_RGD3_WRD0)
32
R/W
0000_0000h
20.3.6/450
4C4
Region Descriptor n, Word 1 (SMPU_RGD3_WRD1)
32
R/W
0000_000Fh
20.3.7/450
4C8
Region Descriptor n, Word 2 Format 0
(SMPU_RD_3W2_F0)
32
R/W
0000_0000h
20.3.8/451
4C8
Region Descriptor n, Word 2 Format 1
(SMPU_RD_3W2_F1)
32
R/W
0000_0000h
20.3.9/452
4CC
Region Descriptor n, Word 3 (SMPU_RGD3_WRD3)
32
R/W
0000_0000h
20.3.10/454
4D0
Region Descriptor n, Word 4 (SMPU_RGD3_WRD4)
32
R/W
0000_0000h
20.3.11/456
4D4
Region Descriptor n, Word 5 (SMPU_RGD3_WRD5)
32
R/W
0000_0000h
20.3.12/457
500
Region Descriptor n, Word 0 (SMPU_RGD4_WRD0)
32
R/W
0000_0000h
20.3.6/450
504
Region Descriptor n, Word 1 (SMPU_RGD4_WRD1)
32
R/W
0000_000Fh
20.3.7/450
508
Region Descriptor n, Word 2 Format 0
(SMPU_RD_4W2_F0)
32
R/W
0000_0000h
20.3.8/451
508
Region Descriptor n, Word 2 Format 1
(SMPU_RD_4W2_F1)
32
R/W
0000_0000h
20.3.9/452
50C
Region Descriptor n, Word 3 (SMPU_RGD4_WRD3)
32
R/W
0000_0000h
20.3.10/454
510
Region Descriptor n, Word 4 (SMPU_RGD4_WRD4)
32
R/W
0000_0000h
20.3.11/456
514
Region Descriptor n, Word 5 (SMPU_RGD4_WRD5)
32
R/W
0000_0000h
20.3.12/457
540
Region Descriptor n, Word 0 (SMPU_RGD5_WRD0)
32
R/W
0000_0000h
20.3.6/450
544
Region Descriptor n, Word 1 (SMPU_RGD5_WRD1)
32
R/W
0000_000Fh
20.3.7/450
548
Region Descriptor n, Word 2 Format 0
(SMPU_RD_5W2_F0)
32
R/W
0000_0000h
20.3.8/451
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
548
Region Descriptor n, Word 2 Format 1
(SMPU_RD_5W2_F1)
32
R/W
0000_0000h
20.3.9/452
54C
Region Descriptor n, Word 3 (SMPU_RGD5_WRD3)
32
R/W
0000_0000h
20.3.10/454
550
Region Descriptor n, Word 4 (SMPU_RGD5_WRD4)
32
R/W
0000_0000h
20.3.11/456
554
Region Descriptor n, Word 5 (SMPU_RGD5_WRD5)
32
R/W
0000_0000h
20.3.12/457
580
Region Descriptor n, Word 0 (SMPU_RGD6_WRD0)
32
R/W
0000_0000h
20.3.6/450
584
Region Descriptor n, Word 1 (SMPU_RGD6_WRD1)
32
R/W
0000_000Fh
20.3.7/450
588
Region Descriptor n, Word 2 Format 0
(SMPU_RD_6W2_F0)
32
R/W
0000_0000h
20.3.8/451
588
Region Descriptor n, Word 2 Format 1
(SMPU_RD_6W2_F1)
32
R/W
0000_0000h
20.3.9/452
58C
Region Descriptor n, Word 3 (SMPU_RGD6_WRD3)
32
R/W
0000_0000h
20.3.10/454
590
Region Descriptor n, Word 4 (SMPU_RGD6_WRD4)
32
R/W
0000_0000h
20.3.11/456
594
Region Descriptor n, Word 5 (SMPU_RGD6_WRD5)
32
R/W
0000_0000h
20.3.12/457
5C0
Region Descriptor n, Word 0 (SMPU_RGD7_WRD0)
32
R/W
0000_0000h
20.3.6/450
5C4
Region Descriptor n, Word 1 (SMPU_RGD7_WRD1)
32
R/W
0000_000Fh
20.3.7/450
5C8
Region Descriptor n, Word 2 Format 0
(SMPU_RD_7W2_F0)
32
R/W
0000_0000h
20.3.8/451
5C8
Region Descriptor n, Word 2 Format 1
(SMPU_RD_7W2_F1)
32
R/W
0000_0000h
20.3.9/452
5CC
Region Descriptor n, Word 3 (SMPU_RGD7_WRD3)
32
R/W
0000_0000h
20.3.10/454
5D0
Region Descriptor n, Word 4 (SMPU_RGD7_WRD4)
32
R/W
0000_0000h
20.3.11/456
5D4
Region Descriptor n, Word 5 (SMPU_RGD7_WRD5)
32
R/W
0000_0000h
20.3.12/457
600
Region Descriptor n, Word 0 (SMPU_RGD8_WRD0)
32
R/W
0000_0000h
20.3.6/450
604
Region Descriptor n, Word 1 (SMPU_RGD8_WRD1)
32
R/W
0000_000Fh
20.3.7/450
608
Region Descriptor n, Word 2 Format 0
(SMPU_RD_8W2_F0)
32
R/W
0000_0000h
20.3.8/451
608
Region Descriptor n, Word 2 Format 1
(SMPU_RD_8W2_F1)
32
R/W
0000_0000h
20.3.9/452
60C
Region Descriptor n, Word 3 (SMPU_RGD8_WRD3)
32
R/W
0000_0000h
20.3.10/454
610
Region Descriptor n, Word 4 (SMPU_RGD8_WRD4)
32
R/W
0000_0000h
20.3.11/456
614
Region Descriptor n, Word 5 (SMPU_RGD8_WRD5)
32
R/W
0000_0000h
20.3.12/457
640
Region Descriptor n, Word 0 (SMPU_RGD9_WRD0)
32
R/W
0000_0000h
20.3.6/450
644
Region Descriptor n, Word 1 (SMPU_RGD9_WRD1)
32
R/W
0000_000Fh
20.3.7/450
648
Region Descriptor n, Word 2 Format 0
(SMPU_RD_9W2_F0)
32
R/W
0000_0000h
20.3.8/451
648
Region Descriptor n, Word 2 Format 1
(SMPU_RD_9W2_F1)
32
R/W
0000_0000h
20.3.9/452
64C
Region Descriptor n, Word 3 (SMPU_RGD9_WRD3)
32
R/W
0000_0000h
20.3.10/454
650
Region Descriptor n, Word 4 (SMPU_RGD9_WRD4)
32
R/W
0000_0000h
20.3.11/456
654
Region Descriptor n, Word 5 (SMPU_RGD9_WRD5)
32
R/W
0000_0000h
20.3.12/457
Table continues on the next page...
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Memory map/register definition
SMPU memory map (continued)
Address
offset (hex)
Register name
Width
Access
(in bits)
Reset value
Section/
page
680
Region Descriptor n, Word 0 (SMPU_RGD10_WRD0)
32
R/W
0000_0000h
20.3.6/450
684
Region Descriptor n, Word 1 (SMPU_RGD10_WRD1)
32
R/W
0000_000Fh
20.3.7/450
688
Region Descriptor n, Word 2 Format 0
(SMPU_RD_10W2_F0)
32
R/W
0000_0000h
20.3.8/451
688
Region Descriptor n, Word 2 Format 1
(SMPU_RD_10W2_F1)
32
R/W
0000_0000h
20.3.9/452
68C
Region Descriptor n, Word 3 (SMPU_RGD10_WRD3)
32
R/W
0000_0000h
20.3.10/454
690
Region Descriptor n, Word 4 (SMPU_RGD10_WRD4)
32
R/W
0000_0000h
20.3.11/456
694
Region Descriptor n, Word 5 (SMPU_RGD10_WRD5)
32
R/W
0000_0000h
20.3.12/457
6C0
Region Descriptor n, Word 0 (SMPU_RGD11_WRD0)
32
R/W
0000_0000h
20.3.6/450
6C4
Region Descriptor n, Word 1 (SMPU_RGD11_WRD1)
32
R/W
0000_000Fh
20.3.7/450
6C8
Region Descriptor n, Word 2 Format 0
(SMPU_RD_11W2_F0)
32
R/W
0000_0000h
20.3.8/451
6C8
Region Descriptor n, Word 2 Format 1
(SMPU_RD_11W2_F1)
32
R/W
0000_0000h
20.3.9/452
6CC
Region Descriptor n, Word 3 (SMPU_RGD11_WRD3)
32
R/W
0000_0000h
20.3.10/454
6D0
Region Descriptor n, Word 4 (SMPU_RGD11_WRD4)
32
R/W
0000_0000h
20.3.11/456
6D4
Region Descriptor n, Word 5 (SMPU_RGD11_WRD5)
32
R/W
0000_0000h
20.3.12/457
700
Region Descriptor n, Word 0 (SMPU_RGD12_WRD0)
32
R/W
0000_0000h
20.3.6/450
704
Region Descriptor n, Word 1 (SMPU_RGD12_WRD1)
32
R/W
0000_000Fh
20.3.7/450
708
Region Descriptor n, Word 2 Format 0
(SMPU_RD_12W2_F0)
32
R/W
0000_0000h
20.3.8/451
708
Region Descriptor n, Word 2 Format 1
(SMPU_RD_12W2_F1)
32
R/W
0000_0000h
20.3.9/452
70C
Region Descriptor n, Word 3 (SMPU_RGD12_WRD3)
32
R/W
0000_0000h
20.3.10/454
710
Region Descriptor n, Word 4 (SMPU_RGD12_WRD4)
32
R/W
0000_0000h
20.3.11/456
714
Region Descriptor n, Word 5 (SMPU_RGD12_WRD5)
32
R/W
0000_0000h
20.3.12/457
740
Region Descriptor n, Word 0 (SMPU_RGD13_WRD0)
32
R/W
0000_0000h
20.3.6/450
744
Region Descriptor n, Word 1 (SMPU_RGD13_WRD1)
32
R/W
0000_000Fh
20.3.7/450
748
Region Descriptor n, Word 2 Format 0
(SMPU_RD_13W2_F0)
32
R/W
0000_0000h
20.3.8/451
748
Region Descriptor n, Word 2 Format 1
(SMPU_RD_13W2_F1)
32
R/W
0000_0000h
20.3.9/452
74C
Region Descriptor n, Word 3 (SMPU_RGD13_WRD3)
32
R/W
0000_0000h
20.3.10/454
750
Region Descriptor n, Word 4 (SMPU_RGD13_WRD4)
32
R/W
0000_0000h
20.3.11/456
754
Region Descriptor n, Word 5 (SMPU_RGD13_WRD5)
32
R/W
0000_0000h
20.3.12/457
780
Region Descriptor n, Word 0 (SMPU_RGD14_WRD0)
32
R/W
0000_0000h
20.3.6/450
784
Region Descriptor n, Word 1 (SMPU_RGD14_WRD1)
32
R/W
0000_000Fh
20.3.7/450
788
Region Descriptor n, Word 2 Format 0
(SMPU_RD_14W2_F0)
32
R/W
0000_0000h
20.3.8/451
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU memory map (continued)
Address
offset (hex)
Width
Access
(in bits)
Register name
Reset value
Section/
page
788
Region Descriptor n, Word 2 Format 1
(SMPU_RD_14W2_F1)
32
R/W
0000_0000h
20.3.9/452
78C
Region Descriptor n, Word 3 (SMPU_RGD14_WRD3)
32
R/W
0000_0000h
20.3.10/454
790
Region Descriptor n, Word 4 (SMPU_RGD14_WRD4)
32
R/W
0000_0000h
20.3.11/456
794
Region Descriptor n, Word 5 (SMPU_RGD14_WRD5)
32
R/W
0000_0000h
20.3.12/457
7C0
Region Descriptor n, Word 0 (SMPU_RGD15_WRD0)
32
R/W
0000_0000h
20.3.6/450
7C4
Region Descriptor n, Word 1 (SMPU_RGD15_WRD1)
32
R/W
0000_000Fh
20.3.7/450
7C8
Region Descriptor n, Word 2 Format 0
(SMPU_RD_15W2_F0)
32
R/W
0000_0000h
20.3.8/451
7C8
Region Descriptor n, Word 2 Format 1
(SMPU_RD_15W2_F1)
32
R/W
0000_0000h
20.3.9/452
7CC
Region Descriptor n, Word 3 (SMPU_RGD15_WRD3)
32
R/W
0000_0000h
20.3.10/454
7D0
Region Descriptor n, Word 4 (SMPU_RGD15_WRD4)
32
R/W
0000_0000h
20.3.11/456
7D4
Region Descriptor n, Word 5 (SMPU_RGD15_WRD5)
32
R/W
0000_0000h
20.3.12/457
20.3.1 Control/Error Status Register 0 (SMPU_CES0)
CESR0 provides error status plus configuration information. A global SMPU enable/
disable bit is also included in this register.
Address: 0h base + 0h offset = 0h
Bit
0
1
2
3
4
5
6
7
8
R
MERR
W
w1c
9
10
11
12
13
14
15
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
HRL
GVLD
R
W
Reset
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
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SMPU_CES0 field descriptions
Field
Description
0–15
MERR
Master n error, where the bus master number matches the bit number
Indicates a captured error in EARn and EDRn. A bit is set when the hardware detects an error and records
the faulting address and attributes. It is cleared by writing one to it. If another error is captured at the exact
same cycle as the write, the flag remains set. A find-first-one instruction (or equivalent) can detect the
presence of a captured error.
0
1
16–27
Reserved
No error has occurred for bus master n.
An error has occurred for bus master n.
This field is reserved.
This read-only field is reserved and always has the value 0.
28–30
HRL
Hardware revision level
31
GVLD
Global Valid (global enable/disable for the SMPU)
Specifies the SMPU’s hardware and definition revision level. It can be read by software to determine the
functional definition of the module.
0
1
SMPU is disabled. All accesses from all bus masters are allowed.
SMPU is enabled.
20.3.2 Control/Error Status Register 1 (SMPU_CES1)
CESR1 provides additional error status plus configuration information.
Address: 0h base + 4h offset = 4h
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MEOVR
R
22
23
24
25
26
27
28
0
29
30
31
NRGD
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
SMPU_CES1 field descriptions
Field
0–15
MEOVR
Description
Master n error overrun, where the bus master number matches the bit number
Each bit in this field signals that another SMPU error for bus master n has occurred before the previous
error was processed. The details of the first error are recorded in the EARn and EDRn registers and no
information on subsequent errors is recorded until the associated CESR0[MERR] flag is cleared.
0
1
No error overrun condition has been detected for bus master n.
An error overrun condition has been detected for bus master n.
16–27
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
28–31
NRGD
Number of region descriptors
Indicates the number of region descriptors implemented in the SMPU. The number of region descriptors is
(4 x NRGD).
Table continues on the next page...
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU_CES1 field descriptions (continued)
Field
Description
0001
0010
0011
0100
0101
0110
4 region descriptors
8 region descriptors
12 region descriptors
16 region descriptors
20 region descriptors
24 region descriptors
20.3.3 Error Address Register, Bus Master (SMPU_ERR_ADRn)
When the SMPU detects an access error on bus master n, the 32-bit reference address is
captured in this read-only register and the corresponding bit in CESR0[MERR] set.
Additional information about the faulting access is captured in the corresponding EDRn
at the same time.
NOTE
The corresponding EARn and EDRn registers contain
information on the original access error; subsequent errors
associated with the given master are recorded as overruns in the
CESR1[MEOVR] field until the CESR0[MERR] flag
associated with the original error is cleared (by writing a 1).
Address: 0h base + 100h offset + (16d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EADDR
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SMPU_ERR_ADRn field descriptions
Field
0–31
EADDR
Description
Error address
Indicates the reference address from bus master n that generated the access error.
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Memory map/register definition
20.3.4 Error Attribute Detail Register, Bus Master
(SMPU_ERR_ADTLn)
When the SMPU detects an access error associated with bus master n, 32 bits of error
detail are captured in this read-only register and the corresponding bit in CESR0[MERR]
isset. Information on the faulting address is captured in the corresponding EARn register
at the same time.
NOTE
The corresponding EARn, EADRn, and EACDRn registers
contain information on the original access error; subsequent
errors associated with the given master are recorded as overruns
in the CESR1[MEOVR] Þeld until the original error is
processed.
Address: 0h base + 104h offset + (16d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
PID[7:0]
R
12
13
14
15
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
R
EATTR
ERW
EMN
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
SMPU_ERR_ADTLn field descriptions
Field
Description
0–7
PID[7:0]
PID of offending access.
8–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
22–23
EATTR
Error attributes
Indicates attribute information about the faulting reference.
00
01
10
11
24
ERW
User mode, instruction access
User mode, data access
Supervisor mode, instruction access
Supervisor mode, data access
Error read/write
Indicates the access type of the faulting reference.
Table continues on the next page...
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU_ERR_ADTLn field descriptions (continued)
Field
Description
0
1
25–31
EMN
Read
Write
Error master number
Indicates the logical bus master number of the faulting reference. This field is used to determine the bus
master that generated the access error.
20.3.5 Error Attribute Control Detail Register, Bus Master
(SMPU_ERR_ACDLn)
When the SMPU detects an access error associated with bus master n, 32 bits of error
detail are captured in this read-only register and the corresponding bit in CESR0[MERR]
is set. Information on the faulting address is captured in the corresponding EARn register
at the same time.
NOTE
The corresponding EARn, EADRn, and EACDRn registers
contain information on the original access error; subsequent
errors associated with the given master are recorded as overruns
in the CESR1[MEOVR] field until the original error is
processed.
Address: 0h base + 108h offset + (16d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
EACD
R
28
29
30
31
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
SMPU_ERR_ACDLn field descriptions
Field
0–23
EACD
Description
Error access control detail
Indicates the region descriptor with the access error, where the region descriptor number matches the bit
number.
If EDRn contains a captured error and EACD is all zeroes, an access did not hit in any region descriptor. If
only a single EACD bit is set, the access error was caused by a single non-overlapping region descriptor.
If two or more EACD bits are set, the access error was caused by an overlapping set of region descriptors.
NOTE: When the address hits in a region but there is a PID miss (the PID is reflected in the Error
Attribute Detail register), the field EACD = 0, if there is no other error. If there is another error, the
EACD will reflect the region of the error (i.e., when it is hit in two regions)
24–31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
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Memory map/register definition
20.3.6 Region Descriptor n, Word 0 (SMPU_RGDn_WRD0)
The first word of the region descriptor defines the byte start address of the memory
region. Writes to this register clear the region descriptor’s valid bit
(RGDn_WORD5[VLD]).
Writes to ANY word of the descriptor clears the valid bit.
Address: 0h base + 400h offset + (64d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
R
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
29
30
31
Reserved
SRTADDR
W
Reset
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SMPU_RGDn_WRD0 field descriptions
Field
Description
0–27
SRTADDR
Start address
28–31
Reserved
This field is reserved.
Defines the start address of the memory region.
20.3.7 Region Descriptor n, Word 1 (SMPU_RGDn_WRD1)
The second word of the region descriptor defines the end address of the memory region.
(RGDn_WORD5[VLD]).
Writes to ANY word of the descriptor clears the valid bit.
Address: 0h base + 404h offset + (64d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
R
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
29
30
31
Reserved
ENDADDR
W
Reset
12
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
SMPU_RGDn_WRD1 field descriptions
Field
0–27
ENDADDR
Description
End address
Defines the end address of the memory region.
NOTE:
1. The SMPU module does not verify that a region's starting address
(SMPU_RGDn_WRD0[SRTADDR]) is less than its ending address
Table continues on the next page...
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Chapter 20 System Memory Protection Unit (SMPU)
SMPU_RGDn_WRD1 field descriptions (continued)
Field
Description
(SMPU_RGDn_WRD1[ENDADDR]). When a region's ending address is a lower address
than the starting address, no error is generated and no hits can be generated for that
region.
2. Both the starting address and the ending address are contained within a defined region. For
example, the SRTADDR and ENDADDR default values (0000_0000h and 0000_000Fh,
respectively) define a 16-byte region starting at address 0000_0000h and containing all
bytes through address 0000_000Fh.
28–31
Reserved
This field is reserved.
20.3.8 Region Descriptor n, Word 2 Format 0 (SMPU_RD_nW2_F0)
RGD_WORD2 has two formats as determined by the RGD_WORD3[FMT] field.
NOTE
RGD_WORD2_FMT0 applies when RGD_WORD3[FMT] = 0.
RGD_WORD2_FMT0 defines the access control rights of the memory region. The
access control rights are defined by separate read and write permissions. For these fields,
the bus master number refers to the logical bus master number.
For the access control rights, there are two flags:
• Read (r) permission refers to the ability to access the referenced memory address
using an operand (data) fetch or an instruction fetch.
• Write (w) permission refers to the ability to update the referenced memory address
using a store (data) operation.
Each field consists of the two flags, with (r) being in the more significant position. For
example, M0P has (r) as bit 0 and (w) as bit 1.
• 00 - No Write or Read
• 01 - Write allowed, no Read
• 10 - Read allowed, no Write
• 11 - Both Read and Write allowed
Writes to this word clear the region descriptor’s valid bit.
Address: 0h base + 408h offset + (64d × i), where i=0d to 15d
Bit
R
W
0
Reset
0
1
2
M0P
3
4
M1P
0
0
5
6
M2P
0
0
7
8
M3P
0
0
9
10
M4P
0
0
11
12
M5P
0
0
13
14
M6P
0
0
15
M7P
0
0
0
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Memory map/register definition
Bit
R
W
16
Reset
0
17
18
M8P
19
20
M9P
0
0
21
22
M10P
0
0
23
24
M11P
0
0
25
26
M12P
0
0
27
28
M13P
0
0
29
30
M14P
0
0
31
M15P
0
0
0
SMPU_RD_nW2_F0 field descriptions
Field
Description
0–1
M0P
Bus master 0 permissions
2–3
M1P
Bus master 1 permissions
4–5
M2P
Bus master 2 permissions
6–7
M3P
Bus master 3 permissions
8–9
M4P
Bus master 4 permissions
10–11
M5P
Bus master 5 permissions
12–13
M6P
Bus master 6 permissions
14–15
M7P
Bus master 7 permissions
16–17
M8P
Bus master 8 permissions
18–19
M9P
Bus master 9 permissions
20–21
M10P
Bus master 10 permissions
22–23
M11P
Bus master 11 permissions
24–25
M12P
Bus master 12 permissions
26–27
M13P
Bus master 13 permissions
28–29
M14P
Bus master 14 permissions
30–31
M15P
Bus master 15 permissions
20.3.9 Region Descriptor n, Word 2 Format 1 (SMPU_RD_nW2_F1)
RGD_WORD2 has two formats as determined by the RGD_WORD3[FMT] field.
NOTE
RGD_WORD2_FMT1 applies when RGD_WORD3[FMT] = 1.
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NOTE
A specific module instance of the SMPU may support only the
FMT0 format. If so, the FMT field is read-only with a fixed
value of 0 and only RGD_WORD2_FMT0 applies.
RGD_WORD2_FMT1 defines pointers for each master to select access control flags
contained in Word3. For these fields, the bus master number refers to the logical bus
master number.
The bit settings are as follows:
• 00: RGDn cannot be accessed by this master, that is, SR=SW=SX=UR=UW=UX=0.
Where 'S' is for supervisor permissions and 'U' for user permissions.
• 01: RGDn access flags are defined in RGDn_WORD3[ACCSET1].
• 10: RGDn access flags are defined in RGDn_WORD3[ACCSET2].
• 11: RGDn access flags are defined in RGDn_WORD3[ACCSET3].
Address: 0h base + 408h offset + (64d × i), where i=0d to 15d
Bit
R
W
0
1
2
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
R
W
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reset
0
M0S
3
4
5
M1S
M8S
0
7
M2S
M9S
0
6
0
9
M3S
M10S
0
8
M4S
M11S
0
0
10
0
12
M5S
M12S
0
11
0
14
M6S
M13S
0
13
M7S
M14S
0
0
15
M15S
0
0
0
SMPU_RD_nW2_F1 field descriptions
Field
Description
0–1
M0S
Bus master 0 permission select
2–3
M1S
Bus master 1 permission select
4–5
M2S
Bus master 2 permission select
6–7
M3S
Bus master 3 permission select
8–9
M4S
Bus master 4 permission select
10–11
M5S
Bus master 5 permission select
12–13
M6S
Bus master 6 permission select
14–15
M7S
Bus master 7 permission select
16–17
M8S
Bus master 8 permission select
Table continues on the next page...
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SMPU_RD_nW2_F1 field descriptions (continued)
Field
Description
18–19
M9S
Bus master 9 permission select
20–21
M10S
Bus master 10 permission select
22–23
M11S
Bus master 11 permission select
24–25
M12S
Bus master 12 permission select
26–27
M13S
Bus master 13 permission select
28–29
M14S
Bus master 14 permission select
30–31
M15S
Bus master 15 permission select
20.3.10 Region Descriptor n, Word 3 (SMPU_RGDn_WRD3)
The third word of the SMPU region descriptor contains the format select (FMT), three
sets of access permissions flags used when FMT = 1, and the cache inhibit bit.
For access permissions used when FMT = 1, there are three flags {read, write, execute}
for each operating mode (supervisor, user). These flags follow the traditional definition:
• Read (r) permission refers to the ability to access the referenced memory address
using an operand (data) fetch.
• Write (w) permission refers to the ability to update the referenced memory address
using a store (data) operation.
• Execute (x) permission refers to the ability to read the referenced memory address
using an instruction fetch.
Each ACCSET field consists of six independent bits, enabling supervisor read, write and
execute permissions {SR, SW, SX} and user read, write and execute permissions {UR,
UW, UX}. If set, the bit allows the given access type to occur; if cleared, an attempted
access of that mode may be terminated with an access error (if not allowed by any other
descriptor) and the access not performed.
The ACCSET bits are in this order: {SR, SW, SX, UR, UW, UX} with SR being in the
most significant position. For example, the SR bit within the ACCSET1 field is register
bit 0.
NOTE
When FMT = 0, the ACCSET fields are not writeable.
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Writes to ANY word of the descriptor clears the valid bit.
Address: 0h base + 40Ch offset + (64d × i), where i=0d to 15d
Bit
R
W
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
R
W
Reset
1
2
3
4
5
6
7
8
ACCSET1
0
10
0
0
11
12
13
0
0
0
0
0
15
0
0
0
0
0
29
30
31
0
FMT
0
14
ACCSET3
0
ACCSET3
0
9
ACCSET2
0
CI
0
0
0
0
SMPU_RGDn_WRD3 field descriptions
Field
Description
0–5
ACCSET1
Access controls, Set 1
6–11
ACCSET2
Access controls, Set 2
12–17
ACCSET3
Access controls, Set 3
18–26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
FMT
Defines a set of access control options for RGD_WORD2_FMT1.
Defines a set of access control options for RGD_WORD2_FMT1.
Defines a set of access control options for RGD_WORD2_FMT1.
Region Descriptor Format
This bit selects the configuration format (FMT0 or FMT1) for this region descriptor.
NOTE: A specific module instance of the SMPU may support only the FMT0 format. If so, the FMT field is
read-only with a fixed value of 0 and only RGD_WORD2_FMT0 applies.
0
1
28–29
Reserved
30
CI
Use format 0: RGD_WORD2_FMT0.
Use format 1: RGD_WORD2_FMT1.
This field is reserved.
This read-only field is reserved and always has the value 0.
Cache Inhibit
Defines the cacheability attribute of the memory region. This bit is returned to the bus master that initiated
the memory reference.
NOTE: An address range specified in an SMPU region descriptor for a cacheable space (that is, CI = 0)
must be defined with a starting address aligned on a 0-modulo-32 byte address and with a
multiple of the 32 byte cache line size factoring into the end address.
For details on operation of CI attribute, please refer to CI note in Putting it all together and error
terminations
0
1
31
Reserved
References to this region can be cached.
References to this region cannot be cached.
This field is reserved.
This read-only field is reserved and always has the value 0.
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20.3.11 Region Descriptor n, Word 4 (SMPU_RGDn_WRD4)
The fifth word of the MPU region descriptor contains the optional process identifier and
mask. If PIDEN is set, the PID and PID MASK of will be included in the hit evaluation
calculation.
Writes to ANY word of the descriptor clears the valid bit.
Address: 0h base + 410h offset + (64d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PID
PID_MASK
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
PIDEN
0
R
W
Reset
0
0
0
0
0
0
0
0
0
SMPU_RGDn_WRD4 field descriptions
Field
0–7
PID
Description
Process Identifier
This field specifies that the optional process identifier is to be included in the determination of whether the
current access hits in the region descriptor. This field is combined with the PIDMASK and included in the
region hit determination if SMPUx_RGDn_WORD4[PIDEN] is set.
8–15
PID_MASK
Process Identifier Mask
16–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
31
PIDEN
Region Descriptor PID Enable
This field provides a masking capability so that multiple process identifiers can be included as part of the
region hit determination. If a bit in the PID_MASK is set, then the corresponding bit of the PID is ignored in
the comparison. This field is combined with the PID and included in the region hit determination if
SMPUx_RGDn_WORD4[PIDEN] is set. For more information on the handling of the PID and PID_MASK.
This flag specifies if the process identifier and mask (defined in SMPUx_RGDn_WORD4) are to be
included in the region hit evaluation
0
1
Do not include PID in the region hit evaluation
Include PID in the region hit evaluation
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20.3.12 Region Descriptor n, Word 5 (SMPU_RGDn_WRD5)
The sixth word of the MPU region descriptor contains the master ID of the master who
has locked the RGD as well as the Lock function and Valid bit. If LCK is set, the master
ID of the master who has locked it will be stored here.
Writes to ANY word of the descriptor clears the valid bit.
Address: 0h base + 414h offset + (64d × i), where i=0d to 15d
Bit
0
1
2
3
4
5
6
7
8
9
10
11
MID
R
12
13
14
15
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
R
W
Reset
0
0
0
0
0
0
0
LCK
0
0
0
0
0
0
0
0
VLD
0
0
SMPU_RGDn_WRD5 field descriptions
Field
0–7
MID
8–27
Reserved
28–29
LCK
Description
Master ID of RGDn owner
If this RGDn is locked through the setting of SMPUx_RGDn_WORD5[LCK], the MID field will reflect the
Master ID of the current RGDn owner.
This field is reserved.
This read-only field is reserved and always has the value 0.
Region Descriptor Lock
This bit allows a master to Lock a region descriptor. Once locked, only that master can modify the Region
descriptor’s contents. This includes all words of the RGD.
NOTE: Setting LCK to 1x in an RGD locks all words of the RGD until system reset, the Valid bit of the
RGD and the Global Valid bit of the SMPU have no effect.
00
01
Unlocked
Locked by the master wrote this register and LCK bit. Attempted writes by other masters are ignored
with an error-free data transfer termination
This value is reserved for future enhancements and should not be used.
Attempted writes to any location in the region descriptor are ignored with an error-free data transfer
termination.
10
11
30
Reserved
31
VLD
This field is reserved.
This read-only field is reserved and always has the value 0.
Valid
Signals the region descriptor is valid. Any write to RGDn_WORD0–4 clears this bit.
0
1
Region descriptor is invalid
Region descriptor is valid
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SMPU_RGDn_WRD5 field descriptions (continued)
Field
Description
20.4 Functional description
In this section, the functional operation of the SMPU is detailed, including the operation
of the access evaluation macro and the handling of error-terminated bus cycles.
20.4.1 Access evaluation macro
The basic operation of the SMPU is performed in the access evaluation macro, a
hardware structure replicated in the connection matrix. The following block diagram
represents an individual macro.
RGDn
start
Access signals
addr
end
permissions
addr
≥
≤
master ID
Determine
hit
privilege level
access type
hit
Detect
violation
error
Combined with the results from other macros for a final evaluation.
Figure 20-3. SMPU access evaluation macro
Each macro uses the information contained in the access signals (the address, the access
type, and the master's ID and privilege level) and the contents of its corresponding region
descriptor (RGDn) to perform two major functions: Hit determination and Violation
determination. The individual hit and error results from each macro are then combined
for a final evaluation; see Putting it all together and error terminations.
20.4.1.1 Hit determination
To determine if the current reference hits in the given region, two magnitude comparators
are used with the region's start and end addresses. The boolean equation for this portion
of the hit determination is:
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region_hit = ((addr[0:31] >= RGDn_Word0[SRTADDR]) & (addr[0:31] <= RGDn_Word1[ENDADDR])) &
RGDn_Word5[VLD]
where addr is the current reference address, RGDn_Word0[SRTADDR] and
RGDn_Word1[ENDADDR] are the start and end addresses, and RGDn_Word5[VLD] is
the valid bit.
NOTE
The SMPU does not verify that ENDADDR > SRTADDR.
NOTE
Region hit determination is based only on an address
comparison of the first byte being accessed; that is, the SMPU
does not check the size of the access to make sure it fits within
an allowed region.
In addition to the algebraic comparison of the reference address
versus the region descriptor’s start and end addresses, the
optional process identifier is examined against the region
descriptor’s PID and PIDMASK fields. Using the hmaster[*]
number to select the appropriate MxPE field from the region
descriptor, a process identifier hit term is formed as:
pid_hit = ~rgdn.mxpe | ((current_pid[0:7] | rgdn.pidmask[0:7]) ==
(rgdn.pid[0:7] | rgdn.pidmask[0:7]))
where rgdn.mxpe is the PID Enable of the RGD, the
current_pid[*] is the selected process identifier from the current
bus master, and rgdn.pid[*] and rgdn.pidmask[*] are the
appropriate process identifier fields from the region descriptor
n. For bus masters that do not output a process identifier, the
SMPU forces the pid_hit term to be asserted. As shown in
Figure 20-2, the access evaluation macro actually forms the
logical complement (hit_b) of the combined region_hit and
pid_hit boolean equations.
20.4.1.2 Violation determination
While the access evaluation macro is determining region hit, the logic is also evaluating
if the current access is allowed by the permissions defined in the region descriptor. Using
the master ID, a set of effective permissions is generated from the appropriate fields in
the region descriptor. The protection violation logic then evaluates the access against the
effective permissions using the specification shown below.
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Table 20-2. Protection violation definition
Access type
Instruction fetch read
Data read
Data write
Access permissions
Protection
r
w
violation?
0
—
Yes, no execute permission
1
—
No, access is allowed
0
—
Yes, no read permission
1
—
No, access is allowed
—
0
Yes, no write permission
—
1
No, access is allowed
20.4.2 Putting it all together and error terminations
For each slave port monitored, the SMPU performs a reduction-AND of all the individual
terms from each access evaluation macro. This expression then terminates the bus cycle
with an error and reports an access error for three conditions:
1. The access does not hit in any region descriptor.
2. The access hits in a single region descriptor and that region has a protection
violation.
3. The access hits in multiple (overlapping) regions and all regions have protection
violations.
As shown in the third condition, granting permission is a higher priority than denying
access for overlapping regions. This approach is more flexible to system software in
region descriptor assignments. For an example of the use of overlapping region
descriptors, see Application information.
NOTE
For Cache-Inhibit (CI), it continues with least restrictive being
higher priority. If there are overlapping regions, and at least one
hitting region has CI=0, then it will not be Cache inhibited. It
should be noted that CI only considers whether or not there is a
hit, not whether there is a hit and permissions. For example, if
two regions hit, one hit has permissions and has CI=1. Another
region hit does not allow permissions, but has CI=0. This
access would be granted, and it would not be cache inhibited.
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NOTE
Aborted core accesses generate instruction storage (ISI) or data
storage (DSI) interrupts (see the documentation related to the
core for details).
20.5 Initialization information
At system startup, load the appropriate number of region descriptors, including setting
RGDn_Word5[VLD]. Setting CESR0[GVLD] enables the module.
If the system requires that all the loaded region descriptors be enabled simultaneously,
first ensure that the entire SMPU is disabled (CESR0[GVLD]=0). Next, load the
appropriate region descriptors (RGDn), including the setting of the RGDn_Word5[VLD]
bits. Finally, set CESR0[GVLD] to enable the entire module.
Note
A region descriptor must be set to allow access to the SMPU
registers if further changes are needed.
20.6 Application information
In an operational system, interfacing with the SMPU is generally classified into the
following activities:
• Creating a new memory region
Load the appropriate region descriptor into an available RGDn, using four sequential
32-bit writes. The hardware assists in the maintenance of the valid bit, so if this
approach is followed, there are no coherency issues with the multi-cycle descriptor
writes.
• Modifying a region descriptor
Load the updates into the region descriptor using sequential 32-bit writes. Writing 1
to RGDn_WRD5[VLD] re-enables the region descriptor. The hardware assists in the
maintenance of the valid bit, so if this approach is followed, there are no coherency
issues with the multi-cycle descriptor writes.
• Removing a region descriptor
Clearing RGDn_WRD5[VLD] deletes an existing region descriptor.
• Accessing the SMPU
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Allocate a region descriptor to restrict SMPU access to supervisor mode from
specific masters as appropriate.
• Detecting an access error
The current bus cycle is terminated with an error response and EARn and EDRn
capture information on the faulting reference. The error-terminated bus cycle
typically initiates an error response in the originating bus master. For example, a
processor core may respond with a bus error exception, while a data movement bus
master may respond with an error interrupt. The processor can retrieve the captured
error address and detail information simply by reading E{A,D}Rn. CESR0[MERR]
signals which error registers contain captured fault data. Once the error information
is retrieved, write a 1 to the appropriate CESR0[MERR] bit to clear it, thereby
rearming the error capture logic associated with the EARn and EDRn registers.
• Overlapping region descriptors
Applying overlapping regions often reduces the number of descriptors required for a
given set of access controls. In the overlapping memory space, the protection rights
of the corresponding region descriptors are logically summed together (the boolean
OR operator).
The following dual-core system example contains four bus masters: the two
processors (CP0, CP1) and two DMA engines (DMA1, a traditional data movement
engine transferring data between RAM and peripherals and DMA2, a second engine
transferring data to/from the RAM only). Consider the following region descriptor
assignments:
Table 20-3. Overlapping region descriptor example
Region description
RGDn
CP0
CP0 code
0
CP1 code
1
CP0 data & stack
2
CP0 → CP1 shared data
2
CP1 → CP0 shared data
4
3
CP1
DMA1
DMA2
rwx
r--
—
—
r--
rwx
—
—
rw-
—
—
—
r--
r--
—
—
CP1 data & stack
4
—
rw-
—
—
Shared DMA data
5
rw-
rw-
rw
rw
SMPU
6
rw-
rw-
—
—
Peripherals
7
rw-
rw-
rw
—
Flash
RAM
Peripheral
space
NOTE
This example uses RGD_WORD2_FMT1 with the following
access control sets defined in RGD_WORD3: r--, rw-, rwx.
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In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map (flash, RAM, and peripheral space). Each region
indicates the specific permissions for each of the four bus masters, and this definition
provides an appropriate set of shared, private, and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.
The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines
a shared data space for passing data from CP0 to CP1 and the access controls are defined
by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-)
permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines
are excluded from this shared processor data region.
The overlapping spaces between RGD3 and RGD4 define another shared data space, this
one for passing data from CP1 to CP0. For this overlapping space, CP0 has (r-- | ---) =
(r--) permission, while CP1 has (rw- | r--) = (rw-) permission. The non-overlapped space
of RGD4 defines a private data and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters.
Finally, the slave peripheral space mapped onto the peripheral bus is partitioned into two
regions: one containing the SMPU's programming model accessible only to the two
processor cores and the remaining peripheral region accessible to both processors and the
traditional DMA1 master.
This simple example is intended to show one possible application of the capabilities of
the SMPU in a typical system.
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Chapter 21
Semaphores2 (SEMA42)
21.1 Introduction
The SEMA42 is a memory-mapped module that provides robust hardware support
needed in multi-core systems for implementing semaphores and provides a simple
mechanism to achieve "lock and unlock" operations via a single write access. The
hardware semaphore module provides hardware-enforced gates as well as other useful
system functions related to the gating mechanisms.
21.1.1 Features
• Supports 16 hardware-enforced gates in a multi-processor configuration
• Gates appear as an 16-entry byte-size array with read and write accesses.
• Processors lock gates by writing "processor_number+1" to the appropriate
gate and must read back the gate value to verify the lock operation was
successful.
• Once locked, the gate is unlocked by a write of zeroes from the locking
processor.
• The number of implemented gates is specified by a hardware configuration
define.
• Each hardware gate appears as a 16-state, 4-bit state machine.
• 16-state implementation
if gate = 0x0, then state = unlocked
if gate = 0x1, then state = locked by processor (master) 0
if gate = 0x2, then state = locked by processor (master) 1
…
if gate = 0xF, then state = locked by processor (master) 14
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• Uses the logical bus master number as a reference attribute plus the specified
data patterns to validate all write operations.
• Once locked, the gate can (and must) be unlocked by a write of zeroes from
the locking processor.
• Secure reset mechanisms are supported to">