NXP TEA1999TS GreenChip synchronous rectifier controller Data Sheet
NXP TEA1999TS is a GreenChip synchronous rectifier controller IC designed for switched-mode power supplies. Its adaptive gate drive feature optimizes efficiency at varying loads. It operates with output voltages between 26V and 0V, making it suitable for battery charging applications with low output voltage. The IC comes in a TSOP6 package and is ideal for flyback power supplies and applications demanding high efficiency.
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TEA1999TS/2
GreenChip synchronous rectifier controller Rev. 1 — 12 September 2018 Product data sheet 1 General description
The TEA1999TS is a member of a new generation of Synchronous Rectifier (SR) controller ICs for switched mode power supplies with adaptive gate drive for maximum efficiency at any load.
The TEA1999TS is a dedicated controller IC for synchronous rectification on the secondary side of flyback converters. It incorporates the sensing stage and driver stage for driving the SR MOSFET, which is rectifying the output of the secondary transformer winding.
The TEA1999TS can generate its own supply voltage for battery charging applications with low output voltage or for applications with high-side rectification.
The TEA1999TS is fabricated in a Silicon-On-Insulator (SOI) process.
2 Features and benefits 2.1 Efficiency features
• •
Adaptive gate drive for maximum efficiency at any load Typical supply current in no-load operation below 250 μA
2.2 Application features
• • • • • • •
Operates in an output voltage range between 26 V and 0 V Drain sense pin capable of handling input voltages up to 120 V Self-supplying for operation with low output voltage Self-supplying for high-side rectification without the use of an auxiliary winding Operates with standard and logic level SR MOSFETs Supports USB BC, QuickCharge, and smart charging applications TSOP6 package
2.3 Control features
• •
Adaptive gate drive for fast turn-off at the end of conduction UnderVoltage LockOut (UVLO) with active gate pull-down
NXP Semiconductors
TEA1999TS/2 GreenChip synchronous rectifier controller
3 Applications
• • •
The TEA1999TS is intended for flyback power supplies. In such applications, it can drive the external synchronous rectifier MOSFET, which replaces the diode for the rectification of the voltage on the secondary winding of the transformer.
It can be used in all power supplies that require a high efficiency, like: Chargers Adapters Flyback power supplies with very low and/or variable output voltage
4 Ordering information
Table 1. Ordering information Type number Package Name
TEA1999TS/2 TSOP6
Description
plastic surface-mounted package (TSOP6); 6 leads
Version
SOT457
5 Marking
Table 2. Marking code Type number
TEA1999TS/2
Marking code
TEA1999 TEA1999TS
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6 Block diagram
CAP XV VOLTAGE LIMITER
TEA1999
Ich(CAP) V AND I REFERENCE ENERGY SAVE CONTROL UNDER VOLTAGE LOCKOUT LOGIC OTP BLANKING turn-on on regulation TURN-ON off regulation SWITCH-OFF DRAIN GATE SOURCE GND -400 mV -25 mV -20 mV +250 mV
Figure 1. TEA1999TS block diagram
aaa-030298
TEA1999TS
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7 Pinning information 7.1 Pinning
terminal 1 index area CAP 1 GND 2 IC 6 DRAIN 5 SOURCE XV 3 aaa-030299
Figure 2. TEA1999TS pin configuration (SOT457)
4 GATE
7.2 Pin description
Table 3. Pin description Symbol Pin
CAP 1 GND XV 2 3 GATE SOURCE 4 5 DRAIN 6
Description
capacitor input for internal supply voltage ground external supply input gate driver output for SR MOSFET source sense input of SR MOSFET drain sense input of SR MOSFET TEA1999TS
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8 Functional description 8.1 Introduction
The TEA1999TS is a controller IC for Synchronous Rectification (SR) in flyback applications. It can drive the external synchronous rectifier MOSFET for the rectification of the voltage on the secondary winding of the transformer.
configuration.
SR low side HV 8 3 GND CTRL 2 6 PRIMARY CONTROLLER 4 5 PROTECT 7 1 DRIVER ISENSE AUX VCC S1 XV DRAIN GATE SOURCE
TEA1999
CAP GND VCC SECONDARY CONTROLLER OPTO GND
aaa-030300
Figure 3. TEA1999TS configuration with low-side rectification
8.2 Start-up and UnderVoltage LockOut (UVLO; CAP and XV pins)
The capacitor on the CAP pin supplies the TEA1999TS. At a low CAP voltage (< 3.7 V), the capacitor is charged via the DRAIN pin with a limited start-up current of typically 15 mA. When the CAP voltage exceeds 3.7 V, the DRAIN pin or the XV pin can charge the capacitor. When the XV voltage < 4.7 V, the capacitor is charged via the DRAIN pin with a typical charge current of 125 mA. When the XV voltage ≥ 4.7 V, the capacitor is charged via the XV pin and an internal regulator. The regulator reduces the voltage difference between the XV and CAP pins to a level below 100 mV.
When the voltage on the CAP pin exceeds V output is actively kept low.
start(CAP) (3.7 V typical), the IC leaves the UVLO state and activates the synchronous rectifier circuitry. When the voltage drops below 3.6 V (typical), the UVLO state is reentered and the SR MOSFET gate driver
8.3 Drain sense (DRAIN pin)
The drain sense pin is an input pin capable of handling input voltages up to 120 V. At positive drain sense voltages, the gate driver is in off-mode with the gate driver pulled down (pin GATE). At negative drain sense voltages, the IC enables the Synchronous Rectification (SR) by sensing the drain source differential voltage.
TEA1999TS
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8.4 Synchronous rectification (DRAIN and SOURCE pins)
The IC senses the voltage difference between the drain sense (DRAIN pin) and the source sense (SOURCE pin) connections. This drain source differential voltage of the SR MOSFET is used to drive the gate of the SR MOSFET.
When this absolute voltage difference is higher than V connections drops to below V act(drv) act(drv) , the corresponding gate driver output turns on the external SR MOSFET. When the external SR MOSFET is switched on, the absolute voltage difference between the drain and the source sense . The regulation phase follows the turn-on phase.
In the regulation phase, the IC regulates the difference between the drain and the source sense inputs to an absolute level of 25 mV. When the absolute difference exceeds 25 mV (V reg(drv) ), the gate driver output increases the gate voltage of the external SR MOSFET until the 25 mV level is reached. The SR MOSFET does not switch off at low current. To avoid that the device switches off because of ringing, a minimum on-time of 1.5 μs (t tact(sr) (min) ) is integrated.
When the absolute difference < 20 mV, the gate driver output decreases the gate voltage of the external SR MOSFET. The voltage waveform on the gate of the SR MOSFET follows the waveform of the current through the SR MOSFET. When the current through the SR MOSFET reaches zero, the SR MOSFET is switched off quickly.
After SR MOSFET switch-off, the drain voltage increases. When the drain voltage exceeds 250 mV, a low ohmic gate pull-down of 3 Ω keeps the gate of the SR MOSFET switched off.
8.5 Gate driver (GATE pin)
The gate driver circuit charges the gate of the external SR MOSFET during the rising part of the current. The driver circuit discharges the gate during the falling part of the current. The gate driver has a source capability of typically 0.70 A. It has a sink capability of typically 0.50 A. The source and sink capabilities allow fast turn-on and fast turn-off of the external SR MOSFET.
The maximum output voltage of the driver is limited to the voltage on the CAP pin. The maximum output voltage ranges between 4.7 V and 10 V, depending on the voltage on the CAP pin. The high output gate voltage drives all MOSFET brands to the minimum on state resistance. In applications where the IC is supplied with 5 V, the maximum output voltage of the driver is 4.90 V, and logic level SR MOSFETs can be used.
The IC is self-supplying in applications with high-side rectification or in battery charging applications with an output voltage < 4.7 V. When the XV pin is connected to ground for driving standard SR MOSFETs, the driver is regulated to 10 V. When the XV pin is connected to the converter output for driving logic-level SR MOSFETs, the driver is regulated to the voltage on the XV pin with a minimum of 4.7 V.
TEA1999TS
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V CAP V G(MAX) 10 V 9 V 4.7 V 0 1 V 5 V 10 V X V 26 V aaa-028212
Figure 4. Maximum gate voltage (V G(max) )
During start-up conditions (V CAP < V start(CAP) ) and UVLO, the driver output voltage is actively pulled low.
When the XV voltage exceeds 10 V, the CAP voltage and V G(max) are limited to typically 10.7 V. The XV voltage is allowed to increase until the 26 V limit is reached.
8.6 Source sense (SOURCE pin)
The IC is equipped with an additional source sense pin (SOURCE). This pin is used for measuring the drain-to-source voltage of the external SR MOSFET. Voltage differences on PCB tracks because of parasitic inductance in combination with large dI/dt values, can cause errors. To minimize these errors, the source sense input must be connected as close as possible to the SOURCE pin of the external SR MOSFET.
8.7 Overtemperature protection (GATE pin)
Overtemperature protection is triggered when the output of the gate driver:
• • •
Has a load that is too high Is short-circuited to ground Is short-circuited to the SOURCE pin The OTP circuit is triggered at 165 °C. It actively pulls down the gate driver output. When the temperature has decreased to 145 °C, the circuit resumes normal operation.
TEA1999TS
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9 Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are measured with respect to ground (pin 2); positive currents flow into the chip. Voltage ratings are valid provided other ratings are not violated; current ratings are valid provided the other ranges are not violated.
Symbol Voltages
V XV V sense(DRAIN)
Parameter
voltage on pin XV sense voltage on pin DRAIN
Conditions Min
−0.4
−0.8
Max
+26 +120
Unit
V V V sense(SOURCE) sense voltage on pin SOURCE −0.4
+0.4
V
General
P tot T stg T j total power dissipation storage temperature junction temperature
ElectroStatic Discharge (ESD)
V ESD electrostatic discharge voltage T amb = 90 °C class 2 human body model charged device model
−55 −40 300 +150 +150 2000 500 mW °C °C V V machine model
200 V [1] [2] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.
Equivalent to discharging a 200 pF capacitor through a 10 Ω series resistor and a 0.75 μH inductor.
10 Recommended operating conditions
Table 5. Recommended operating conditions Symbol Parameter Conditions
V XV V DRAIN voltage on pin XV voltage on pin DRAIN peak voltage in switching application
Min
0 8 -
Typ Max
21 120
Unit
V V
11 Thermal characteristics
Table 6. Thermal characteristics Symbol Parameter
R th(j-a) thermal resistance from junction to ambient R th(j-c) thermal resistance from junction to case
Conditions
JEDEC test board JEDEC test board
Typ
200 115
Unit
K/W K/W TEA1999TS
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12 Characteristics
Table 7. Characteristics
−25 °C < T j < +125 °C; V xv = 5 V; C CAP = 1 μF; C GATE = 10 nF (capacitor between the GATE and the GND pins); all voltages are measured with respect to ground (pin 2); currents are positive when flowing into the IC; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
I
Supply voltage management (XV and CAP pins)
V start(CAP) start voltage on pin CAP V XV = 0 V V stop(CAP) I start(CAP) ch(CAP) stop voltage on pin CAP start current on pin CAP charge current on pin CAP V XV = 0 V V XV = 5 V; V CAP = 0 V; V DRAIN = 12 V power save operation V XV = 0 V; V CAP = 8 V; V DRAIN = 12 V; T j = 25 °C V XV = 2 V; V CAP = 4 V; V DRAIN = 12 V; T j = 25 °C V I(CAP) input voltage on pin CAP V XV = 0 V; V DRAIN = 15 V V XV = 2 V; V DRAIN = 12 V V XV = 5 V V XV = 10 V 3.5
3.4
−24 −120 −160 9.0
4.5
4.8
9.8
3.7
3.6
−15 −80 −110 9.4
4.6
4.9
9.9
3.9
3.8
−8 −50 −50 9.8
4.8
5.0
10.0
V V mA mA mA V V V V t I I(XV) input current on pin XV V XV = 26 V power save operation; V DRAIN = 5.5 V; T j = 25 °C normal operation; without gate charge; V DRAIN step from 5.5 V to −250 mV; T j = 25 °C t act(pwrsave) power-save activation time
Synchronous rectification sense input (DRAIN and SOURCE pins)
V act(drv) V reg(drv) driver activation voltage driver regulation voltage V V SOURCE SOURCE = 0 V; T = 0 V; T j j = 25 °C = 25 °C V swoff t d(act)(drv) d(deact)(drv) switch-off voltage driver activation delay time driver deactivation delay time V SOURCE = 0 V V V SOURCE DRAIN = 0 V; normal operation; time for step-on (2 V to −0.5 V) to rising of V G at 10 % of end value V V SOURCE DRAIN = 0 V; normal operation; time for step-on (−50 mV to 2 V) to falling of V G at 90 % of begin value 10.3
200 1.0
70 −510 −30 180 10.7
240 1.2
100 −470 −25 250 40 40 11.1
280 1.4
130 −430 −20 320 V μA mA μs mV mV mV ns ns t act(sr)(min) minimum synchronous rectification active time V V SOURCE DRAIN = 0 V; normal operation; time for step-on (−700 mV to +100 mV) to falling of V G at 90 % of begin value; without gate charge 1.1
1.4
1.8
μs TEA1999TS
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I
Symbol Gate driver (GATE pin)
I source sink R V pd(G) G(max)
Parameter
source current sink current gate pull-down resistance maximum gate voltage
Temperature protection
T otp(act) activation overtemperature protection temperature T otp(hys) overtemperature protection trip hysteresis
Conditions
peak.current; V XV = 5 V; V ds = −0.5 V; V G = 0 V regulation current; V XV = 5 V; V ds = 0 V; V G = 3 V peak current; V XV = 5 V; V ds = 0.5 V; V G = 4 V V DRAIN = 0.5 V; I G = 100 mA; V XV = 5 V; T j = 25 °C V XV = 0 V V XV = 2 V V XV = 5 V V XV = 10 V V XV = 26 V -
Min
2.6
9.0
4.45
4.8
9.8
10.3
155
Typ
-0.70
100 0.50
3.2
9.4
4.60
4.9
9.9
10.7
165 20
Max
4.0
9.8
4.75
5.0
10.0
11.1
175
Unit
V V V V V A Ω A mA °C °C TEA1999TS
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12.1 Temperature curves 12.1.1 Charge current (CAP pin)
I I ch(CAP) (mA) 0 -30 -60 -90 -120 -150 -40 -10 20 (1) I ch(CAP) at V CAP = 8 V; V XV = 0 V (2) I ch(CAP) at V CAP = 4 V; V XV = 2 V
Figure 5. I ch(CAP) as a function of temperature
12.1.2 Operating current (XV pin)
50 I I 1600 I(XV) (µA) 1200 80
aaa-027364
110 T (°C) 140
aaa-027365
800 400 0 -40 -10 20 (1) I I(XV) - normal operation (2) I I(XV) - power save operation
Figure 6. I I(XV) as a function of temperature
50 80 110 T (°C) 140 TEA1999TS
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12.1.3 Driver regulation voltage
V reg(drv) (mV) 0 -5 -10 -15 -20 -25 -30 -40 -10 20
Figure 7. V reg(drv) as a function of temperature
12.1.4 Gate pull-down resistance
50 R pd(G) (Ω) 5 4 80
aaa-027366
110 T (°C) 140
aaa-027367
3 2 1 0 -40 -10 20
Figure 8. R pd(G) as a function of temperature
50 80 110 T (°C) 140 TEA1999TS
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12.1.5 Switch-off voltage
V 300 swoff (mV) 280 260 240 220 200 -40 -10 20 50
Figure 9. V swoff as a function of temperature
12.1.6 Minimum synchronous rectification active time
80 t t (μs) 1.6
act(sr)(min) 1.2
aaa-027368
140
aaa-030922
0.8
0.4
0 -40 -10 20 50
Figure 10. t act(sr)(min) as a function of temperature
80 140 TEA1999TS
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13 Application information
A flyback switched mode power supply with the TEA1999TS consists of a primary side controller with a primary switch, a transformer, and an output stage. To obtain low conduction loss rectification, an SR MOSFET is used in the output stage. The SR MOSFET can be placed low-side (see
Figure 3 ) or can be placed high-side
(see Figure 11 ). In the high-side application, the TEA1999TS is self-supplying. The
capacitor on the CAP pin supplies the TEA1999TS. When the drain voltage is positive, it is charged via the DRAIN pin.
The gate drive voltage for the synchronous rectifier switch is derived from the voltage difference between the corresponding drain sense and source sense pins.
Special attention must be paid to the connection of the drain sense and source sense pins. The voltages measured on these pins are used for the gate drive voltage. Wrong measurement results in a less efficient gate drive because a gate voltage that is either too low or too high. The connections to these pins must not interfere with the power wiring.
The power wiring conducts currents with high dI/dt values. It can easily cause measurement errors resulting from induced voltages due to parasitic inductances. The separate source sense pins make it possible to sense the source voltage of the external MOSFETs directly, without having to use the current carrying power ground tracks.
SR high side XV DRAIN GATE SOURCE
TEA1999
CAP GND VCC SECONDARY CONTROLLER OPTO GND HV 8 GND CTRL 3 2 6 PRIMARY CONTROLLER 4 5 PROTECT 7 1 DRIVER ISENSE AUX VCC S1
aaa-023939
Figure 11. TEA1999TS configuration with high-side rectification
TEA1999TS
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TEA1999TS/2 GreenChip synchronous rectifier controller • • • • •
Some important guidelines for a good layout: Keep the trace from the DRAIN pin to the MOSFET drain as short as possible.
Keep the trace from the SOURCE pin to the MOSFET source as short as possible.
Keep the area of the loop from the DRAIN pin to the MOSFET drain, to the MOSFET source, and to the SOURCE pin as small as possible. Make sure that the overlap of this loop over the power drain track or the power source track is as small as possible.
Keep the track from the GATE pin to the gate of the MOSFET as short as possible.
Use separate clean tracks for the XV and GND pins. If possible, use a small ground plane underneath the IC, which improves the heat dispersion.
TEA1999TS
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NXP Semiconductors 14 Package outline
Plastic surface-mounted package (TSOP6); 6 leads
D B
TEA1999TS/2 GreenChip synchronous rectifier controller SOT457
E A X y HE v M A
6 5 4
Q pin 1 index
1
e
2
bp
3
w M B A A1 detail X Lp c 0 1 scale 2 mm
DIMENSIONS (mm are the original dimensions) UNIT
mm
A
1.1
0.9
A1
0.1
0.013
bp
0.40
0.25
c
0.26
0.10
D
3.1
2.7
E
1.7
1.3
e
0.95
HE
3.0
2.5
Lp
0.6
0.2
Q
0.33
0.23
v
0.2
w
0.2
y
0.1
OUTLINE VERSION
SOT457
IEC JEDEC REFERENCES JEITA
SC-74
Figure 12. Package outline SOT457 (TSOP6)
TEA1999TS
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NXP Semiconductors 15 Revision history
Table 8. Revision history Document ID Release date
TEA1999TS 20180912
Data sheet status
Product data sheet
TEA1999TS/2 GreenChip synchronous rectifier controller
-
Change notice
-
Supersedes
TEA1999TS
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16 Legal information 16.1 Data sheet status
Document status
Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status
Development Qualification Production
Definition
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
[1] [2] [3] Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft
— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
Short data sheet
— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
Product specification
Product data sheet.
— The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the
16.3 Disclaimers
Limited warranty and liability
— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.
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Applications
— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
Limiting values
— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
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Non-automotive qualified products
— Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of non automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.
Translations
— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.
Security
— While NXP Semiconductors has implemented advanced security features, all products may be subject to unidentified vulnerabilities.
Customers are responsible for the design and operation of their applications and products to reduce the effect of these vulnerabilities on customer’s applications and products, and NXP Semiconductors accepts no liability for any vulnerability that is discovered. Customers should implement appropriate design and operating safeguards to minimize the risks associated with their applications and products.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
GreenChip
— is a trademark of NXP B.V.
TEA1999TS
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 12 September 2018
© NXP B.V. 2018. All rights reserved.
19 / 20
NXP Semiconductors Contents
Applications .........................................................2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ...............................................................4
Pin description ................................................... 4
Functional description ........................................5
Source sense (SOURCE pin) ............................7
Overtemperature protection (GATE pin) ............ 7
Limiting values ....................................................8
Characteristics .................................................... 9
Temperature curves .........................................11
Charge current (CAP pin) ................................11
Operating current (XV pin) .............................. 11
Driver regulation voltage ..................................12
Gate pull-down resistance ............................... 12
Application information ....................................14
Package outline .................................................16
Revision history ................................................ 17
Legal information ..............................................18
TEA1999TS/2 GreenChip synchronous rectifier controller
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.
© NXP B.V. 2018.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 September 2018 Document identifier: TEA1999TS
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