NXP 68HC05K0 Microcontroller Data Sheet

Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC05K1/D
Rev. 2.0
HC 5
MC68HC05K0
MC68HCL05K0
MC68HSC05K0
MC68HC05K1
HCMOS Microcontroller Unit
TECHNICAL DATA
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data — MC68HC05K0 • MC68HC05K1
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . 17
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Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . . 35
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . . 59
Section 7. Parallel Input/Output (I/O). . . . . . . . . . . . . . . . 65
Section 8. Multifunction Timer . . . . . . . . . . . . . . . . . . . . . 77
Section 9. Personality EPROM (MC68HC05K1 Only) . . . 85
Section 10. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . 93
Section 11. Electrical Specifications . . . . . . . . . . . . . . . 111
Section 12. Mechanical Specifications . . . . . . . . . . . . . 127
Section 13. Ordering Information . . . . . . . . . . . . . . . . . 129
Appendix A. MC68HCL05K0. . . . . . . . . . . . . . . . . . . . . . 135
Appendix B. MC68HSC05K0 . . . . . . . . . . . . . . . . . . . . . 141
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
List of Sections
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Technical Data
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
List of Sections
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Technical Data — MC68HC05K0 • MC68HC05K1
Table of Contents
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Section 1. General Description
1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2
OSC1, OSC2, and PB1/OSC3 . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.2.3
2-Pin Resistor-Capacitor (RC) Combination . . . . . . . . . .25
1.6.2.4
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.2.5
External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.6
PB1/OSC3 and PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Section 2. Memory
2.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3
Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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2.5
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.6
Personality EPROM (MC68HC05K1 Only). . . . . . . . . . . . . . . .34
Section 3. Central Processor Unit (CPU)
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Section 4. Interrupts
4.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.2.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .48
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Section 5. Resets
Technical Data
5.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .56
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.4.3
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Section 6. Low-Power Modes
6.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Section 7. Parallel Input/Output (I/O)
7.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3.2
Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.3.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.3.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.3.5
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.4.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.4.4
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
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Section 8. Multifunction Timer
8.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . .78
8.4
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
8.5
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Section 9. Personality EPROM (MC68HC05K1 Only)
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9.3
PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.3.1
PEPROM Bit Select Register . . . . . . . . . . . . . . . . . . . . . . .87
9.3.2
PEPROM Status and Control Register . . . . . . . . . . . . . . . .89
9.4
PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
9.5
PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Section 10. Instruction Set
10.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Technical Data
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10.3.7
10.3.8
Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
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10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .98
10.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .99
10.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .100
10.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .102
10.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
10.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
10.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Section 11. Electrical Specifications
11.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.4
Equivalent Pin Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.5
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .113
11.6
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
11.7
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.8
5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .115
11.9
3.3-Volt DC Electrical Specifications . . . . . . . . . . . . . . . . . . .116
11.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
11.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
11.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .124
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Section 12. Mechanical Specifications
12.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.3
MC68HC05K0/MC68HC05K1P (PDIP) . . . . . . . . . . . . . . . . .128
12.4
MC68HC05K0/MC68HC05K1DW (SOIC) . . . . . . . . . . . . . . .128
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Section 13. Ordering Information
13.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .130
13.4.1 Diskettes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.4.2 EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
13.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .132
13.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .133
13.7
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Appendix A. MC68HCL05K0
Technical Data
A.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.3
1.8–2.4-Volt DC Electrical Characteristics . . . . . . . . . . . . . . .136
A.4
2.5–3.6-Volt DC Electrical Characteristics . . . . . . . . . . . . . . .136
A.5
Low-Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.6
Low-Power Pulldown Current . . . . . . . . . . . . . . . . . . . . . . . . .138
A.7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
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Appendix B. MC68HSC05K0
B.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.3
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . .142
B.4
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
B.5
3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
B.6
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Index
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Freescale Semiconductor, Inc...
Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Table of Contents
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Technical Data — MC68HC05K0 • MC68HC05K1
List of Figures
Freescale Semiconductor, Inc...
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
MC68HC05K0 and MC68HC05K1 Block Diagram. . . . . . . .20
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .22
Crystal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .24
3-Pin Ceramic Resonator Connections . . . . . . . . . . . . . . . .24
2-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . .25
3-Pin RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . .26
External Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . .27
2-1
2-2
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . .32
3-1
3-2
3-3
3-4
3-5
3-6
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .40
4-1
4-2
4-3
4-4
External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . .48
Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
5-1
5-2
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6-1
Stop/Wait/Halt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7-1
Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .66
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Figure
Page
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .67
Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .68
Port A I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .71
Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .72
Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .73
Port B I/O Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
8-1
8-2
8-3
8-4
Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . . .78
Timer Status and Control Register (TSCR) . . . . . . . . . . . . .79
Timer Counter Register (TCNTR) . . . . . . . . . . . . . . . . . . . .81
COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9-1
9-2
9-3
9-4
PEPROM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . . .87
PEPROM Status and Control Register (PESCR) . . . . . . . . .89
Programming Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-13
11-14
Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Typical High-Side Driver Characteristics . . . . . . . . . . . . . .117
Typical Low-Side Driver Characteristics. . . . . . . . . . . . . . .117
Typical Run IDD versus Internal Clock Frequency . . . . . . .118
Typical Wait IDD versus Internal Clock Frequency . . . . . . .118
Typical Stop IDD versus Temperature . . . . . . . . . . . . . . . .119
External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .122
Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .122
Power-On Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .123
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
2-Pin RC Oscillator R versus Frequency
(VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
3-Pin RC Oscillator R versus Frequency
(VDD = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
2-Pin Oscillator R versus Frequency (VDD = 3.0 V) . . . . . .126
3-Pin Oscillator R versus Frequency (VDD = 3.0 V) . . . . . .126
13-1
13-2
Maximum Run Mode IDD versus Frequency. . . . . . . . . . . .138
Maximum Wait Mode IDD versus Frequency . . . . . . . . . . .139
11-12
Technical Data
Title
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data — MC68HC05K0 • MC68HC05K1
List of Tables
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Table
Title
Page
1-1
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4-1
Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .51
7-1
7-2
7-3
Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
PB0 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PB1/OSC3 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
8-1
8-2
Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . . .80
COP Watchdog Recommendations . . . . . . . . . . . . . . . . . . . .83
9-1
PEPROM Bit Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .98
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .99
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .101
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .102
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
13-1
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
A-1
MC68HCL05K0 Order Numbers. . . . . . . . . . . . . . . . . . . . . .139
B-1
MC68HSC05K0 Order Numbers . . . . . . . . . . . . . . . . . . . . .144
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
List of Tables
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 1. General Description
Freescale Semiconductor, Inc...
1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.5
MCU Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2
OSC1, OSC2, and PB1/OSC3 . . . . . . . . . . . . . . . . . . . . . . .22
1.6.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.2.3
2-Pin Resistor-Capacitor (RC) Combination . . . . . . . . . .25
1.6.2.4
3-Pin RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.6.2.5
External Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.3
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.4
IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.5
PA7–PA0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.6.6
PB1/OSC3 and PB0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Technical Data
1.2 Introduction
Freescale Semiconductor, Inc...
The MC68HC05K1 and MC68HC05K0 are members of Motorola’s
low-cost, high-performance M68HC05 Family of 8-bit microcontroller
units (MCU). The M68HC05 Family is based on the customer-specified
integrated circuit (CSIC) design strategy. All MCUs in the family use the
popular M68HC05 central processor unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
On-chip memory includes 504 bytes of user read-only memory (ROM)
and 32 bytes of user random-access memory (RAM).
The MC68HC05K1 has an additional 64-bit personality, erasable,
programmable, read-only memory (PEPROM). In an MC68HC05K1
MCU, the PEPROM cannot be erased and serves as a 64-bit array of
one-time programmable ROM (OTPROM).
Appendix A. MC68HCL05K0 introduces the MC68HCL05K0, a
low-power version of the MC68HC05K0.
Appendix B. MC68HSC05K0 introduces the MC68HSC05K0, a
high-speed version of the MC68HC05K0.
1.3 Features
Features of the MC68HC05K0 and MC68HC05K1 include:
•
M68HC05 CPU
•
Memory-mapped input/output (I/O) registers
•
504 bytes of ROM including eight user vector locations
•
32 bytes of user RAM
•
64-bit PEPROM/OTPROM (MC68HC05K1 only)
•
10 bidirectional input/output (I/O) pins with these features:
– Software programmable pulldown devices
– Four I/O pins with 8-mA current sinking capability
– Four I/O pins with maskable external interrupt capability
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
General Description
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General Description
Mask Options
•
Hardware mask and flag for external interrupts
•
Fully static operation with no minimum clock speed
•
On-chip oscillator with connections for a crystal/ceramic resonator
or for a mask-optional 2-pin or 3-pin resistor-capacitor (RC)
oscillator
•
Computer operating properly (COP) watchdog
•
15-bit multifunction timer with real-time interrupt circuit
•
Power-saving stop, wait/halt, and data-retention modes
•
8 × 8 unsigned multiply instruction
•
Illegal address reset
•
Low-voltage reset
•
16-pin plastic dual in-line package (PDIP)
•
16-pin small outline integrated circuit package (SOIC)
1.4 Mask Options
Table 1-1 shows the available mask options.
Table 1-1. Mask Options
Feature
COP watchdog
Mask Options
Enabled
Disabled
External interrupt pin triggering
Edge triggered
only
Edge and
level triggered
Port A external interrupt function
Enabled
Disabled
Low-voltage reset function
Enabled
Disabled
STOP instruction
Enabled
Convert to halt
Crystal/ceramic
resonator
Resistor-capacitor
Software control
Disabled
Oscillator type
Port A and port B pulldown devices
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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2-pin
3-pin
Technical Data
Freescale Semiconductor, Inc.
Technical Data
1.5 MCU Structure
Figure 1-1 shows the structure of the MC68HC05K0 and
MC68HC05K1.
USER ROM — 504 BYTES
USER RAM — 32 BYTES
ARITHMETIC/LOGIC
UNIT
CPU CONTROL
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
*8-mA sink capability
**External interrupt capability
RESET
STACK POINTER
0 0 0 0 0 0 0 0 1 1 1
PROGRAM COUNTER
0 0 0 0 0 0
CONDITION CODE REGISTER
1 1 1 H I N C Z
PB1/OSC3
PB0
MULTIFUNCTION
TIMER
TIMER
CLOCK
COP WATCHDOG
AND
ILLEGAL ADDRESS
DETECT
LOW-VOLTAGE
DETECT
PORT B
DATA DIRECTION REGISTER B
M68HC05
MCU
REGISTER
VDD
PA6*
ACCUMULATOR
IRQ/VPP
RESET
PA7*
PORT A
DATA DIRECTION REGISTER A
PERSONALITY EPROM/OTPROM— 64 BITS
(MC68HC05K1 ONLY)
CPU
CLOCK
Freescale Semiconductor, Inc...
VPP
VSS
OSC1
OSC2
INTERNAL
OSCILLATOR
fosc
DIVIDE
BY TWO
fop
OSC3
Figure 1-1. MC68HC05K0 and MC68HC05K1 Block Diagram
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
General Description
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General Description
Pin Assignments
1.6 Pin Assignments
Freescale Semiconductor, Inc...
Figure 1-2 shows the MC68HC05K0 and MC68HC05K1 pin
assignments.
RESET
1
16
OSC1
PB1/OSC3
2
15
OSC2
PB0
3
14
VSS
IRQ/VPP
4
13
VDD
PA0
5
12
PA7
PA1
6
11
PA6
PA2
7
10
PA5
PA3
8
9
PA4
Figure 1-2. Pin Assignments
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Technical Data
1.6.1 VDD and VSS
VDD and VSS are the power supply and ground pins. The MCU operates
from a single 3.0-V to 6.0-V power supply.
Freescale Semiconductor, Inc...
Very fast signal transitions occur on the MCU pins, placing high
short-duration current demands on the power supply. To prevent noise
problems, take special care to provide good power supply bypassing at
the MCU. Place bypass capacitors as close to the MCU as possible, as
Figure 1-3 shows.
OSC1
VDD
OSC2
+
MCU
C1
C2
VSS
C1 C2
VSS
VDD
Note:
Actual layout varies according to component dimensions.
Figure 1-3. Bypassing Layout Recommendation
1.6.2 OSC1, OSC2, and PB1/OSC3
The OSC1, OSC2, and PB1/OSC3 pins are the control connections for
the 2-pin or 3-pin on-chip oscillator. The oscillator can be driven by any
of these:
•
Crystal
•
Ceramic resonator
•
Resistor-capacitor (RC) combination
•
External clock signal
The frequency of the internal oscillator is fosc. The MCU divides the
internal oscillator output by two to produce the internal clock with a
frequency of fop.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
General Description
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General Description
Pin Assignments
1.6.2.1 Crystal
Freescale Semiconductor, Inc...
The circuit in Figure 1-4 shows a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable startup and maximum
stability. The load capacitance values used in the oscillator circuit design
should account for all stray layout capacitances. To minimize output
distortion, mount the crystal and capacitors as close as possible to the
pins.
VSS
MCU
2 MΩ
(MASK OPTION)
C3
OSC1
OSC1
XTAL
OSC2
OSC2
C4
VSS
XTAL
27 pF
C3
C4
C1 C2
27 pF
VDD
Figure 1-4. Crystal Connections
NOTE:
Use an AT-cut crystal and not a strip or tuning fork crystal. The MCU may
overdrive or have the incorrect characteristic impedance for a strip or
tuning fork crystal.
To use the crystal-driven oscillator, select the crystal/ceramic resonator
mask option when ordering the MCU. The crystal/ceramic resonator
mask option connects an internal 2-MΩ startup resistor between OSC1
and OSC2.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Technical Data
1.6.2.2 Ceramic Resonator
To reduce cost, use a ceramic resonator in place of the crystal. Use the
circuit in Figure 1-5 for a 2-pin ceramic resonator or Figure 1-6 for a
3-pin ceramic resonator and follow the resonator manufacturer’s
recommendations.
VSS
MCU
2 MΩ
(MASK OPTION)
C3
CER.
RES.
OSC2
OSC1
Freescale Semiconductor, Inc...
OSC1
OSC2
C4
VSS
CERAMIC
RESONATOR
C4
C3
27 pF
C1 C2
27 pF
VDD
VDD
Figure 1-5. 2-Pin Ceramic Resonator Connections
VSS
MCU
2 MΩ
(MASK OPTION)
CER.
RES.
OSC2
OSC1
OSC1
OSC2
VSS
C1 C2
CERAMIC
RESONATOR
VDD
VDD
Figure 1-6. 3-Pin Ceramic Resonator Connections
The external component values required for maximum stability and
reliable starting depend upon the resonator parameters. The load
capacitance values used in the oscillator circuit design should account
for all stray layout capacitances. To minimize output distortion, mount
the resonator and capacitors as close as possible to the pins.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
General Description
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General Description
Pin Assignments
To use the resonator-driven oscillator, select the crystal/ceramic
resonator mask option when ordering the MCU. The crystal/ceramic
resonator mask option connects an internal 2-MΩ startup resistor
between OSC1 and OSC2.
For maximum cost reduction, use the 2-pin RC oscillator configuration
shown in Figure 1-7. The OSC2 signal is a square-type wave, and the
signal on OSC1 is a triangular-type wave. The optimum frequency for
the 2-pin oscillator configuration is 2 MHz.
VSS
MCU
R
OSC2
OSC1
OSC1
Freescale Semiconductor, Inc...
1.6.2.3 2-Pin Resistor-Capacitor (RC) Combination
C3
R C3
OSC2
VSS
C1 C2
VDD
VDD
Figure 1-7. 2-Pin RC Oscillator Connections
To use the 2-pin RC oscillator configuration, select the 2-pin RC
oscillator mask option when ordering the MCU.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
1.6.2.4 3-Pin RC Oscillator
Freescale Semiconductor, Inc...
Another low-cost option is the 3-pin RC oscillator configuration shown in
Figure 1-8. The 3-pin oscillator is more stable than the 2-pin oscillator.
The OSC2 and PB1/OSC3 signals are square-type waves, and the
signal on OSC1 is a triangular-type wave. Short the OSC1 pin to the side
of resistor R, which is connected to capacitor C3. The 3-pin RC oscillator
configuration is recommended for frequencies of 1 MHz down to
100 kHz.
VSS
C3
MCU
R
R
PB1/OSC3
OSC2
OSC1
OSC1
+
PB1/OSC3
OSC2
VSS
C3
C1 C2
VDD
VDD
Figure 1-8. 3-Pin RC Oscillator Connections
To use the 3-pin RC oscillator configuration, select the 3-pin RC
oscillator mask option when ordering the MCU.
NOTE:
Technical Data
In the 3-pin RC oscillator configuration the PEPROM of the
MC68HC05K1 cannot be programmed by user software. If the voltage
on IRQ/VPP is raised above VDD, the oscillator will revert to a 2-pin
oscillator configuration and device operation will be disrupted.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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General Description
Pin Assignments
1.6.2.5 External Clock Signal
An external clock from another complementary metal oxide
semiconductor (CMOS)-compatible device can drive the OSC1 input,
with the OSC2 pin unconnected, as Figure 1-9 shows.
OSC2
OSC1
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MCU
EXTERNAL
CMOS CLOCK
Figure 1-9. External Clock Connections
1.6.3 RESET
A logic 0 on the RESET pin forces the MCU to a known startup state.
See 5.3 Reset Types.
1.6.4 IRQ/VPP
The IRQ/VPP pin has these functions:
•
Applying asynchronous external interrupt signals.
See 4.3 Interrupt Types.
•
Applying the personality EPROM programming voltage
(MC68HC05K1 only). See 9.3 PEPROM Registers.
1.6.5 PA7–PA0
PA7–PA0 are the pins of port A, a general-purpose, bidirectional I/O
port. See 7.3 Port A.
All port A pins have mask-optional pulldown devices that sink
approximately 100 µA. See 7.3.3 Pulldown Register A. If the mask
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Technical Data
option for port A external interrupts is selected, PA3-PA0 serve as
external interrupt pins. See 7.3.4 Port A External Interrupts.
1.6.6 PB1/OSC3 and PB0
PB1/OSC3 and PB0 are the pins of port B, a general-purpose,
bidirectional I/O port. See 7.4 Port B.
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PB1 is the oscillator output for the 3-pin resistor/capacitor (RC) oscillator
mask option. See 1.6.2 OSC1, OSC2, and PB1/OSC3. PB1 and PB0
have mask-optional pulldown devices that sink approximately 100 µA.
See 7.4.3 Pulldown Register B.
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MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 2. Memory
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2.1 Contents
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.3
Input/Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.4
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.5
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.6
Personality EPROM (MC68HC05K1 Only). . . . . . . . . . . . . . . .34
2.2 Introduction
The central processor unit (CPU) can address 1 Kbyte of memory space.
The program counter typically advances one address at a time through
the memory, reading the program instructions and data. The read-only
memory (ROM) portion of memory holds the program instructions, fixed
data, user-defined vectors, and interrupt service routines. The
random-access memory (RAM) portion of memory holds variable data.
Input/output (I/O) registers are memory-mapped so that the CPU can
access their locations in the same way that it accesses all other memory
locations.
Figure 2-1 is a memory map of the microcontroller unit (MCU).
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2.3 Input/Output Section
The first 32 addresses of the memory space, $0000–$001F, are the I/O
section. These are the addresses of the I/O control registers, status
registers, and data registers. Figure 2-2 is a register map of the I/O
section.
2.4 RAM
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The 32 addresses from $00E0 to $00FF serve as both the user RAM and
the stack RAM. The CPU uses five RAM bytes to save all CPU register
contents before processing an interrupt. During a subroutine call, the
CPU uses two bytes to store the return address. The stack pointer
decrements during pushes and increments during pulls.
NOTE:
Technical Data
Be careful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
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Memory
RAM
$0000
$001F
$0020
I/O
32 BYTES
USER ROM
192 BYTES
$00DF
$00E0
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STACK AND RAM
32 BYTES
$00FF
$0100
UNUSED
256 BYTES
$01FF
$0200
USER ROM
496 BYTES
$03EF
$03F0
INTERNAL TEST ROM
AND COP REGISTER
8 BYTES
$03F7
$03F8
$03FF
USER VECTORS
8 BYTES
PORT A DATA REGISTER
PORT B DATA REGISTER
UNUSED
UNUSED
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
UNUSED
UNUSED
TIMER STATUS & CONTROL REGISTER
TIMER COUNTER REGISTER
IRQ STATUS & CONTROL REGISTER
UNUSED
UNUSED
UNUSED
PEPROM SELECT REGISTER(1)
PEPROM STATUS & CONTROL REGISTER(1)
PULLDOWN REGISTER A
PULLDOWN REGISTER B
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
UNUSED
RESERVED
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0000
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
COP REGISTER(2)
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$03F0
$03F1
$03F2
$03F3
$03F4
$03F5
$03F6
$03F7
$03F8
$03F9
$03FA
$03FB
$03FC
$03FD
$03FE
$03FF
1. MC68HC05K1 only
2. Writing a 0 to bit 0 of $03F0 clears the COP watchdog. Reading $03F0 returns ROM data.
Figure 2-1. Memory Map
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Addr.
Register Name
Read:
Port A Data Register
(PORTA) Write:
See page 66.
Reset:
$0000
Read:
Port B Data Register
(PORTB) Write:
See page 71.
Reset:
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$0001
$0002
Unimplemented
$0003
Unimplemented
$0004
$0005
Read:
Data Direction Register B
(DDRB) Write:
See page 72.
Reset:
Unimplemented
$0007
Unimplemented
$0008
Read:
Timer Status and Control
Register (TSCR) Write:
See page 79.
Reset:
$000A
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB1
PB0
Unaffected by reset
0
0
0
0
0
0
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
0
0
0
0
DDRB1
DDRB0
0
0
RT1
RT0
0
0
TOF
RTIF
0
Read: TCR7
Timer Counter Register
(TCNTR) Write:
See page 81.
Reset:
0
Read:
IRQ Status and Control
Register (ISCR) Write:
See page 48.
Reset:
0
Unaffected by reset
Read:
Data Direction Register A
DDRA7
(DDRA) Write:
See page 67.
Reset:
0
$0006
$0009
Bit 7
0
0
TOIE
RTIE
0
0
0
0
TOFR
RTIFR
0
0
0
0
0
1
1
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
0
0
0
0
0
0
0
0
0
0
IRQF
0
0
0
IRQE
IRQR
1
0
0
= Unimplemented
0
0
R
= Reserved
0
U
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 2)
Technical Data
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Memory
RAM
Addr.
Register Name
$000B
Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
0
0
0
0
PEPRZF
↓
$000D
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$000E
$000F
$0010
$0011
$0012
Unimplemented
Read:
PEPROM Bit Select Register
(PEBSR) Write:
See page 87.
Reset:
Read: PEDATA
PEPROM Status and Control
Register (PESCR) Write:
See page 89.
Reset:
U
Read:
Pulldown Register A
(PDRA) Write: PDIA7
See page 68.
Reset:
0
Read:
Pulldown Register B
(PDRB) Write:
See page 73.
Reset:
0
PEPGM
0
0
0
0
0
0
1
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
0
0
0
0
0
0
0
PDIB1
PDIB0
U
U
U
U
U
U
0
0
R
R
R
R
R
R
R
R
0
1
0
Unimplemented
↓
$001E
Unimplemented
Read:
$001F
Reserved
Write:
Reset:
$03F0
COP Register Read:
(COPR)
Write:
See page 56.
Reset:
Unaffected by reset
0
0
0
0
0
COPC
U
U
U
U
U
= Unimplemented
R
= Reserved
U
U
0
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 2)
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2.5 ROM
Addresses $0200–$03EF contain 496 bytes of user ROM. The eight
addresses from $03F8 to $03FF are user ROM locations reserved for
interrupt vectors and reset vectors.
2.6 Personality EPROM (MC68HC05K1 Only)
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In an MC68HC05K1 MCU, the personality EPROM cannot be erased
and serves as a 64-bit array of one-time programmable ROM
(OTPROM).
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 3. Central Processor Unit (CPU)
3.1 Contents
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3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
3.3.4
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.2 Introduction
The central processor unit (CPU) contains five registers and an
arithmetic/logic unit (ALU).
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3.3 CPU Registers
Figure 3-1 shows the five CPU registers. CPU registers are not part of
the memory map.
7
6
5
4
3
2
1
0
ACCUMULATOR (A)
7
6
5
4
3
2
1
0
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INDEX REGISTER (X)
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
1
1
1
15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
4
3
2
1
0
STACK POINTER (SP)
4
3
2
1
0
PROGRAM
COUNTER (PC)
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
CONDITION CODE
REGISTER (CCR)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
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Central Processor Unit (CPU)
CPU Registers
3.3.1 Accumulator
The accumulator (A) shown in Figure 3-2 is a general-purpose 8-bit
register. The accumulator holds operands and results of arithmetic and
non-arithmetic operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
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Write:
Reset:
Unaffected by reset
Figure 3-2. Accumulator (A)
3.3.2 Index Register
In the indexed addressing modes, the CPU uses the byte in the index
register (X) to determine the effective address of the operand. (See
10.3.5 Indexed, No Offset, 10.3.6 Indexed, 8-Bit Offset, 10.3.7
Indexed, 16-Bit Offset.) The 8-bit index register shown in Figure 3-3
can also serve as a temporary data storage location.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 3-3. Index Register (X)
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3.3.3 Stack Pointer
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The stack pointer (SP) shown in Figure 3-4 is a 16-bit register that
contains the address of the next location on the stack. During a reset or
after the reset stack pointer (RSP) instruction, the stack pointer initializes
to $00FF. The address in the stack pointer decrements as data is
pushed onto the stack and increments as data is pulled from the stack.
The 11 most significant bits of the stack pointer are permanently fixed at
00000000111, so the stack pointer produces addresses from $00FF to
$00E0. If subroutines and interrupts use more than 32 stack locations,
the stack pointer wraps around to address $00FF and begins writing
over the previously stored data. A subroutine call uses two stack
locations; an interrupt uses five locations.
Bit 15
14
13
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
4
3
2
1
Bit 0
1
1
1
1
1
Read:
Write:
Reset:
Figure 3-4. Stack Pointer (SP)
Technical Data
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Central Processor Unit (CPU)
CPU Registers
3.3.4 Program Counter
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The program counter (PC) shown in Figure 3-5 is a 16-bit register that
contains the address of the next instruction or operand to be fetched.
The six most significant bits of the program counter are ignored internally
and appear as 000000 when stacked.
Normally, the address in the program counter automatically increments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
Bit 15
14
13
12
11
10
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Loaded with vector from $03FE and $03FF
Figure 3-5. Program Counter
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3.3.5 Condition Code Register
The condition code register (CCR) shown in Figure 3-6 is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
7
6
5
4
3
2
1
0
1
1
1
H
I
N
Z
C
1
1
1
U
1
U
U
U
Read:
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Write:
Reset:
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
Bits 7–5
Bits 7–5 always read as logic 1.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
effect on the half-carry flag.
I — Interrupt Mask Bit
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
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Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logical
operation, or data manipulation produces a negative result. Reset has
no effect on the negative flag.
Z — Zero Flag
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The CPU sets the zero flag when an arithmetic operation, logical
operation, or data manipulation produces a result of $00. Reset has
no effect on the zero flag.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag. Reset
has no effect on the carry/borrow flag.
3.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logical operations defined by the
instruction set. The binary arithmetic circuits decode instructions and set
up the ALU for the selected operation.
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Central Processor Unit (CPU)
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 4. Interrupts
4.1 Contents
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4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.3
Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.1
Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.2
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3.2.1
IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
4.3.2.2
PA3–PA0 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
4.3.2.3
IRQ Status and Control Register . . . . . . . . . . . . . . . . . . .48
4.3.3
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.3.1
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.3.2
Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.4
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.2 Introduction
This section describes how interrupts temporarily change the processing
sequence.
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Technical Data
4.3 Interrupt Types
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These conditions generate interrupts:
•
SWI instruction (software interrupt)
•
A logic 0 applied to the IRQ/VPP pin (external interrupt)
•
A logic 1 applied to one of the PA3–PA0 pins if the port A external
interrupt mask option is selected (external interrupt)
•
A timer overflow (timer interrupt)
•
Expiration of the real-time interrupt period (timer interrupt)
An interrupt temporarily suspends normal program execution to process
a particular event. An interrupt does not stop the execution of the
instruction in progress, but takes effect when the current instruction
completes its execution. Interrupt processing automatically saves the
central processor unit (CPU) registers on the stack and loads the
program counter with a user-defined vector address.
4.3.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.3.2 External Interrupts
These sources can generate external interrupts:
•
IRQ/VPP pin
•
PA3–PA0 pins if the port A external interrupts mask option is
selected
Setting the I bit in the condition code register or clearing the IRQE bit in
the interrupt status and control register disables external interrupts.
See Figure 4-2.
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Interrupts
Interrupt Types
4.3.2.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. The IRQ/VPP pin contains an internal Schmitt trigger as part of
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its input to improve noise immunity. After completing the current
instruction, the CPU tests these bits:
•
IRQF bit in the interrupt status and control register
•
IRQE bit in the interrupt status and control register
•
I bit in the condition code register
If both the IRQF bit and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQF bit
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-1 shows the logic for
external interrupts.
The IRQ/VPP pin is negative-edge triggered only or negative-edge and
low-level triggered, depending on the mask option selected.
When the edge- and level-sensitive trigger mask option is selected:
•
A falling edge or a low level on the IRQ/VPP pin latches an external
interrupt request.
•
As long as the IRQ/VPP pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/VPP pin to multiple wired-OR interrupt
sources.
When the edge-sensitive only trigger mask option is selected:
NOTE:
•
A falling edge of the IRQ/VPP pin latches an external interrupt
request.
•
A subsequent interrupt request can be latched only after the
voltage level on the IRQ/VPP pin returns to logic 1 and then falls
again to logic 0.
If the IRQ/VPP pin is not in use, connect it to the VDD pin.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQ
LEVEL-SENSITIVE TRIGGER
(MASK OPTION)
PA3
VDD
PA2
IRQ
LATCH
EXTERNAL
INTERRUPT
REQUEST
PA1
PA0
PORT A
EXTERNAL INTERRUPTS
ENABLED
IRQR
IRQF
RST
IRQ VECTOR FETCH
IRQE
Freescale Semiconductor, Inc...
R
IRQ STATUS AND CONTROL REGISTER
(MASK OPTION)
INTERNAL DATA BUS
Figure 4-1. External Interrupt Logic
4.3.2.2 PA3–PA0 Pins
The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. The PA3–PA0 pins do not
contain internal Schmitt triggers. An interrupt signal on one of the
PA3–PA0 pins latches an external interrupt request. After completing
the current instruction, the CPU tests these bits:
•
IRQF bit (IRQ latch)
•
IRQE bit in the interrupt status and control register
•
I bit in the condition code register
If both the IRQ latch and the IRQE bit are set and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
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Interrupts
Interrupt Types
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA3–PA0 pins are positive edge triggered only or positive-edge and
high- level triggered, depending on the mask option selected.
Freescale Semiconductor, Inc...
When the positive edge and high level-sensitive trigger mask option is
selected:
•
A rising edge or a high level on a PA3–PA0 pin latches an external
interrupt request if and only if all other PA3–PA0 pins are low and
the IRQ/VPP pin is high.
•
A falling edge or a low level on the IRQ/VPP pin latches an external
interrupt request if and only if all of the PA3–PA0 pins are low.
•
As long as any PA3–PA0 pin is high or the IRQ/VPP pin is low, an
external interrupt request is present, and the CPU continues to
execute the interrupt service routine.
Edge- and level-sensitive triggering allows multiple external interrupt
sources to be wire-ORed to any of the PA3–PA0 pins. As long as any
source is holding a PA3–PA0 pin high, an external interrupt request is
latched, and the CPU continues to execute the interrupt service routine.
When the positive edge-sensitive-only trigger mask option is selected:
•
A rising edge on any one of the PA3–PA0 pins latches an external
interrupt request if all other PA3–PA0 pins are low and the
IRQ/VPP pin is high.
•
A falling edge on the IRQ/VPP pin latches an external interrupt
request if and only if all of the PA3–PA0 pins are low.
•
A subsequent PA3–PA0 pin interrupt request can be latched only
after the voltage level of the previous PA3–PA0 interrupt signal
returns to a logic 0 and then rises again to a logic 1.
•
A subsequent IRQ/VPP pin interrupt request can be latched only
after the voltage level of the previous IRQ/VPP interrupt signal
returns to a logic 1 and then falls again to a logic 0.
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4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR), shown in Figure 4-2,
contains an external interrupt mask, an external interrupt flag, and a flag
reset bit. Unused bits read as logic 0s.
Address:
$000A
Bit 7
Read:
6
5
4
3
2
1
Bit 0
0
0
0
IRQF
0
0
0
IRQE
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Write:
Reset:
IRQR
1
0
0
= Unimplemented
0
0
0
U
0
U = Unaffected
Figure 4-2. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQF bit (IRQ latch) is a clearable, read-only bit that is set when
an external interrupt request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQF bit:
– An external interrupt signal on the IRQ/VPP pin
– An external interrupt signal on pin PA3, PA2, PA1, or PA0 if
PA3–PA0 are enabled by mask option to serve as external
interrupt sources
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
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Interrupts
Interrupt Types
IRQR — Interrupt Request Reset Bit
Writing a logic 1 to this write-only bit clears the IRQF bit. Writing a
logic 0 to IRQR has no effect. Reset has no effect on IRQR.
1 = IRQF bit cleared
0 = No effect
4.3.3 Timer Interrupts
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The multifunction timer can generate these interrupts:
•
Timer overflow interrupt
•
Real-time interrupt
Setting the I bit in the condition code register disables all timer interrupts.
4.3.3.1 Timer Overflow Interrupt
A timer overflow interrupt request occurs if the timer overflow flag (TOF)
becomes set while the timer overflow interrupt enable bit (TOIE) is also
set. See 8.3 Timer Status and Control Register.
4.3.3.2 Real-Time Interrupt
A real-time interrupt request occurs if the real-time interrupt flag, RTIF,
becomes set while the real-time interrupt enable bit, RTIE, is also set.
See 8.3 Timer Status and Control Register.
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4.4 Interrupt Processing
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To begin servicing an interrupt, the CPU:
•
Stores the CPU registers on the stack in the order shown in
Figure 4-3
•
Sets the I bit in the condition code register to prevent further
interrupts
•
Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $03FC and $03FD (software interrupt vector)
– $03FA and $03FB (external interrupt vector)
– $03F8 and $03F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-3.
$00E0 (BOTTOM OF STACK)
$00E1
$00E2
UNSTACKING
ORDER
•
•
•
•
•
•
5
1
4
2
ACCUMULATOR
3
3
INDEX REGISTER
2
4
PROGRAM COUNTER (HIGH BYTE)
1
5
PROGRAM COUNTER (LOW BYTE)
STACKING
ORDER
CONDITION CODE REGISTER
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Interrupt Stacking Order
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Interrupt Processing
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Local
Mask
Global
Mask
Priority
(1 = Highest)
Vector Address
None
None
1
$03FE–$03FF
None
None
Same priority
as instruction
$03FC–$03FD
IRQE bit
I bit
2
$03FA–$03FB
I bit
3
$03F8–$03F9
Power-on
logic
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RESET pin
Reset
COP
watchdog(1)
Low-voltage
detect(2)
Illegal
address
logic
Software
interrupt
(SWI)
User code
IRQ/VPP pin
PA3 pin(3)
External
interrupts
PA2 pin(3)
PA1 pin(3)
PA0 pin(3)
Timer
interrupts
TOF bit
TOIE bit
RTIF bit
RTIE bit
1. The computer operating properly (COP) watchdog is a mask option.
2. The low-voltage reset function is a mask option.
3. Port A interrupt capability is a mask option.
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
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Figure 4-4 shows the sequence of events caused by an interrupt.
FROM
RESET
YES
I BIT SET?
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NO
EXTERNAL
INTERRUPT?
YES
CLEAR IRQF BIT
NO
TIMER
INTERRUPT?
YES
STACK PC, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
NO
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
NO
RTI
INSTRUCTION?
YES
UNSTACK CCR, A, X, PC
NO
EXECUTE INSTRUCTION
Figure 4-4. Interrupt Flowchart
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Section 5. Resets
5.1 Contents
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5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.3
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.3.1
Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
5.3.2
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.3.3
Computer Operating Properly (COP) Reset . . . . . . . . . . . . .56
5.3.4
Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.3.5
Low-Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4
Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4.1
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.4.2
I/O Port Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.4.3
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.4.4
COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.2 Introduction
This section describes the five reset sources and how they initialize the
microcontroller unit (MCU).
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5.3 Reset Types
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address.
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These conditions produce a reset:
•
Initial power-up (power-on reset)
•
A logic 0 applied to the RESET pin (external reset)
•
Timeout of the mask-optional computer operating properly (COP)
watchdog (COP reset)
•
An opcode fetch from an address not in the read-only memory
(ROM) or random-access memory (RAM) (illegal address reset)
•
VDD voltage below LVR trip point (mask-optional low-voltage
reset)
Figure 5-1 is a block diagram of the reset sources.
5.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset. The
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
A 4064 tcyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at a
logic 0 at the end of 4064 tcyc, the MCU remains in the reset condition
until the signal on the RESET pin goes to a logic 1.
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Resets
Reset Types
5.3.2 External Reset
An external reset is generated by applying a logic 0 for 1 1/2 tcyc to the
RESET pin. A Schmitt trigger senses the logic level at the RESET pin.
A COP reset or an illegal address reset pulls the RESET pin low for one
internal clock cycle. A low-voltage reset pulls the RESET pin low for as
long as the low-voltage condition exists.
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NOTE:
To avoid overloading some power supply designs, do not connect the
RESET pin directly to VDD. Use a pullup resistor of 10 kΩ or more.
COP WATCHDOG
(MASK OPTION)
LOW-VOLTAGE RESET
(MASK OPTION)
VDD
POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL ADDRESS BUS
RESET
INTERNAL
CLOCK
S
D
RESET
LATCH
RST
TO CPU AND
SUBSYSTEMS
R
Figure 5-1. Reset Sources
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5.3.3 Computer Operating Properly (COP) Reset
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A timeout of the computer operating properly (COP) watchdog
generates a COP reset. The COP watchdog is part of a software error
detection system and must be cleared periodically to start a new timeout
period. To clear the COP watchdog and prevent a COP reset, write a
logic 0 to bit 0 (COPC) of the COP register at location $03F0.
See 8.5 COP Watchdog.
The COP register, shown in Figure 5-2, is a write-only register that
returns the contents of a ROM location when read.
The COP watchdog function is a mask option.
Address:
Read:
$03F0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
1
0
Write:
Reset:
COPC
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 5-2. COP Register (COPR)
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Writing a logic 1
has no effect. Reset clears the COPC bit.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the ROM (locations
$0200–$03FF) or the RAM (locations $00E0–$00FF) generates an
illegal address reset. An illegal address reset pulls the RESET pin low
for one cycle of the internal clock.
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Resets
Reset States
5.3.5 Low-Voltage Reset
The low-voltage reset circuit is a mask option that generates a reset
signal if the voltage on the VDD pin falls below the LVR trip point. VDD
must be set at 5 V ±10% if the mask option enabling the low-voltage
reset circuit is selected.
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A low-voltage reset pulls the RESET pin low for as long as the
low-voltage condition exists.
NOTE:
When the low-voltage reset is enabled, use a pullup resistor on RESET
because low-voltage reset shorts RESET to ground when it detects a
low VDD. If there is no pullup to limit current, low-voltage reset will short
VDD to ground, causing the chip to possibly remain in reset due to VDD
being pulled down by the short. VDD may also pull current and
permanently damage the chip.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has these effects on the CPU:
•
Loads the stack pointer with $FF
•
Sets the I bit in the condition code register, inhibiting interrupts
•
Sets the IRQE bit in the interrupt status and control register
•
Loads the program counter with the user-defined reset vector from
locations $03FE and $03FF
•
Clears the IRQF bit (IRQ latch)
•
Clears the stop latch, enabling the CPU clock, or exiting the halt
mode
•
Clears the wait latch, waking the CPU from wait mode
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5.4.2 I/O Port Registers
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A reset has these effects on input/output (I/O) port registers:
•
Clears bits DDRA7–DDRA0 in data direction register A so that
port A pins are inputs
•
Clears bits PDIA7–PDIA0 in pulldown register A, turning on port A
pulldown devices (if pulldown devices are enabled by mask
option)
•
Clears bits DDRB1 and DDRB0 in data direction register B so that
port B pins are inputs
•
Clears bits PDIB1 and PDIB0 in pulldown register B, turning on
port B pulldown devices (if pulldown devices are enabled by mask
option)
•
Has no effect on port A or port B data registers
5.4.3 Timer
A reset has these effects on the multifunction timer:
•
Clears the timer status and control register
•
Clears the timer counter register
5.4.4 COP Watchdog
A reset clears the COP watchdog timeout counter.
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Section 6. Low-Power Modes
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
6.3
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
6.5
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.6
Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
6.2 Introduction
This section describes the four low-power modes:
•
Stop mode
•
Wait mode
•
Halt mode
•
Data-retention mode
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6.3 Stop Mode
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The STOP instruction puts the microcontroller unit (MCU) in its lowest
power-consumption mode and has these effects on the MCU:
•
Clears TOF and RTIF, the timer interrupt flags in the timer status
and control register, removing any pending timer interrupts
•
Clears TOIE and RTIE, the timer interrupt enable bits in the timer
status and control register, disabling further timer interrupts
•
Clears the multifunction timer counter register
•
Sets the IRQE bit in the IRQ status and control register to enable
external interrupts
•
Clears the I bit in the condition code register, enabling interrupts
•
Stops the internal oscillator, turning off the central processor unit
(CPU) clock and the timer clock, including the computer operating
properly (COP) watchdog, and holds OSC2 at a logic 1
The STOP instruction does not affect any other registers or any
input/output (I/O) lines.
These conditions bring the MCU out of stop mode:
•
An external interrupt signal on the IRQ/VPP pin — A high-to-low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $03FA and $03FB.
•
An external interrupt signal on a port A external interrupt pin — If
the mask option for the port A external interrupt function is
selected, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
•
Low-voltage reset — A low-voltage detect resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF (if this mask option is selected).
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
When the MCU exits stop mode, processing resumes after a
stabilization delay of 4064 oscillator cycles.
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Low-Power Modes
Wait Mode
6.4 Wait Mode
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The WAIT instruction puts the MCU in an intermediate
power-consumption mode and has these effects on the MCU:
•
Clears the I bit in the condition code register, enabling interrupts
•
Sets the IRQE bit in the IRQ status and control register, enabling
external interrupts
•
Stops the CPU clock, but allows the internal oscillator and timer
clock to continue to run
The WAIT instruction does not affect any other registers or any I/O lines.
These conditions restart the CPU clock and bring the MCU out of wait
mode:
•
An external interrupt signal on the IRQ/VPP pin — A high-to-low
transition on the IRQ/VPP pin loads the program counter with the
contents of locations $03FA and $03FB.
•
An external interrupt signal on a port A external interrupt pin — If
the mask option for the port A external interrupt function is
selected, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
•
A timer interrupt — A timer overflow or a real-time interrupt request
loads the program counter with the contents of locations $03F8
and $03F9.
•
A COP watchdog reset — A timeout of the mask-optional COP
watchdog resets the MCU and loads the program counter with the
contents of locations $03FE and $03FF. Software can enable
real-time interrupts so that the MCU can periodically exit wait
mode to reset the COP watchdog.
•
Low-voltage reset — A low-voltage detect resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF (if this mask option is selected).
•
External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
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6.5 Halt Mode
If the mask option to disable the STOP instruction is selected, a STOP
instruction puts the MCU in halt mode. Halt mode is identical to wait
mode, except that a recovery delay of from 1 to 4064 internal clock
cycles occurs when the MCU exits halt mode. If the mask option to
disable the STOP instruction is selected, the COP watchdog cannot be
turned off inadvertently by a STOP instruction.
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Figure 6-1 shows the sequence of events in stop, wait, and halt modes.
6.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CPU register contents at VDD voltages as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to a logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
continuously during data-retention mode.
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to a logic 1.
Technical Data
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Low-Power Modes
Data-Retention Mode
STOP
STOP
DISABLED?
YES
HALT
WAIT
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
NO
Freescale Semiconductor, Inc...
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
YES
EXTERNAL
RESET?
YES
YES
EXTERNAL
RESET?
EXTERNAL
RESET?
NO
NO
NO
NO
LVR
ENABLED?
LVR
ENABLED?
NO
LVR
ENABLED?
YES
YES
YES
LVR?
YES
YES
LVR?
YES
NO
NO
NO
EXTERNAL
INTERRUPT?
LVR?
NO
YES
EXTERNAL
INTERRUPT?
YES
EXTERNAL
INTERRUPT?
YES
NO
NO
YES
TIMER
INTERRUPT?
NO
YES
TIMER
INTERRUPT?
TURN ON INTERNAL OSCILLATOR
START STABILIZATION DELAY
NO
NO
END OF
STABILIZATION
DELAY?
YES
YES
COP
RESET?
NO
NO
YES
COP
RESET?
NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
Figure 6-1. Stop/Wait/Halt Flowchart
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Low-Power Modes
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Technical Data
Freescale Semiconductor, Inc.
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Low-Power Modes
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 7. Parallel Input/Output (I/O)
7.1 Contents
Freescale Semiconductor, Inc...
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3.1
Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3.2
Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.3.3
Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.3.4
Port A External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.3.5
Port A Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.1
Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.2
Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.4.3
Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7.4.4
Port B Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.2 Introduction
The 10 bidirectional input/output (I/O) pins form two parallel I/O ports.
Each I/O pin is programmable as an input or an output. The contents of
the data direction registers determine the data direction of each I/O pin.
All 10 I/O pins have mask-optional pulldown devices.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
7.3 Port A
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Port A is an 8-bit, general-purpose, bidirectional I/O port with these
features:
•
Programmable pulldown devices (mask option)
•
8-mA current sinking capability (pins PA7–PA4)
•
External interrupt capability (pins PA3–PA0) (mask option)
7.3.1 Port A Data Register
The port A data register (PORTA), shown in Figure 7-1, contains a bit
for each of the port A pins. When a port A pin is programmed to be an
output, the state of its data register bit determines the state of the output
pin. When a port A pin is programmed to be an input, reading the port A
data register returns the logic state of the pin. The port A data register
may be written to while the port is either an input or an output.
Address:
$0000
Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Read:
Write:
Reset:
Unaffected by reset
Figure 7-1. Port A Data Register (PORTA)
PA7–PA0 — Port A Data Bits
These read/write bits are software-programmable. Data direction of
each bit is under the control of the corresponding bit in data direction
register A. Reset has no effect on port A data.
Technical Data
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Parallel Input/Output (I/O)
Port A
7.3.2 Data Direction Register A
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The contents of data direction register A (DDRA), shown in Figure 7-2,
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset initializes all DDRA bits
to logic 0s, configuring all port A pins as inputs. If the pulldown devices
are enabled by mask option, setting a DDRA bit to a logic 1 turns off the
pulldown device for that pin.
Address:
$0004
Bit 7
6
5
4
3
2
1
Bit 0
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE:
Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
7.3.3 Pulldown Register A
Port A pins have mask-optional pulldown devices that sink
approximately 100 µA. Clearing the PDIA7–PDIA0 bits in pulldown
register A turns on the port A pulldown devices. Pulldown register A,
shown in Figure 7-3, can turn on a port A pulldown device only when the
port A pin is an input.
Freescale Semiconductor, Inc...
If the pulldown mask option is selected, reset initializes all port A and port
B pins as inputs with pulldown devices turned on.
Address:
$0010
Bit 7
6
5
4
3
2
1
Bit 0
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
Read:
= Unimplemented
Figure 7-3. Pulldown Register A (PDRA)
PDIA7–PDIA0 — Port A Pulldown Inhibit Bits 7–0
Writing logic 0s to these write-only bits turns on the port A pulldown
devices. Reading pulldown register A returns undefined data. Reset
clears bits PDIA7–PDIA0.
1 = Corresponding port A pin pulldown device turned off
0 = Corresponding port A pin pulldown device turned on
NOTE:
To avoid excessive current draw, connect all unused input pins to VDD
or VSS. Or change I/O pins to outputs by writing to DDRA in user
initialization code. Avoid a floating port A input by clearing its pulldown
register bit before changing its DDRA bit from logic 1 to logic 0.
Because pulldown register A is a write-only register, using the
read-modify-write instruction may result in inadvertently turning bits on
or off.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port A
7.3.4 Port A External Interrupts
If the mask option for port A external interrupts is selected, the PA3–PA0
pins serve as external interrupt pins in addition to the IRQ/VPP pin.
External interrupts can be positive edge-triggered or positive edge- and
high level-triggered.
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/VPP pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL do not test the port A external interrupt pins.
Port A interrupts are not sensitive to the direction of the port pins. Driving
a logic 1 on PA0–PA3 while port interrupts are enabled will cause an
interrupt, even if PA0–PA3 are set to outputs.
7.3.5 Port A Logic
Figure 7-4 shows the port A I/O logic.
READ $0004
WRITE $0004
INTERNAL DATA BUS
Freescale Semiconductor, Inc...
NOTE:
WRITE $0000
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
READ $0000
WRITE $0010
EXTERNAL
INTERRUPT
REQUEST
(PINS PA3–PA0)
PULLDOWN
REGISTER A
BIT PDIAx
RESET
PULLDOWNS ENABLED (ACTIVE LOW)
100-mA
PULLDOWN
DEVICE
(MASK OPTION)
Figure 7-4. Port A I/O Circuit
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Technical Data
When a port A pin is programmed as an output, reading the port bit
actually reads the value of the data latch and not the voltage on the pin
itself. When a port A pin is programmed as an input, reading the port bit
reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its DDR bit. Table 7-1 summarizes the
operations of the port A pins.
Freescale Semiconductor, Inc...
Table 7-1. Port A Pin Functions
Pulldown
Mask
Option
PDIAx
DDRAx
No
X
0
No
X
Yes
Accesses
to PDRA
Control Bits
I/O Pin Mode
Accesses
to DDRA
Accesses
to PORTA
Read
Write
Read/Write
Read
Write
Input, hi-z
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
PA0–PA7
0
0
Input,
pulldown on
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
Yes
0
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
PA0–PA7
Yes
1
0
Input, hi-z
U
PDIA7–PDIA0
DDRA7–DDRA0
Pin
PA0–PA7
Yes
1
1
Output
U
PDIA7–PDIA0
DDRA7–DDRA0
PA0–PA7
PA0–PA7
X = Don’t care
U = Undefined
7.4 Port B
Port B is a 2-bit, general-purpose, bidirectional I/O port with these
features:
•
Programmable pulldown devices (mask option)
•
Oscillator output for 3-pin resistor-capacitor (RC) oscillator mask
option
7.4.1 Port B Data Register
The port B data register (PORTB), shown in Figure 7-5, contains a bit
for each of the port B pins. When a port B pin is programmed to be an
output, the state of its data register bit determines the state of the output
pin. When a port B pin is programmed to be an input, reading the port B
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Parallel Input/Output (I/O)
Port B
data register returns the logic state of the pin. Reset has no effect on port
B data.
Address:
Read:
$0001
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
PB1
PB0
Write:
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Reset:
Unaffected by reset
Alternate
Function:
OSC3
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB1/OSC3 — Port B Data Bit 1
This read/write bit is software programmable. Data direction of PB1 is
under the control of the DDRB1 bit in data direction register B.
When the 3-pin RC oscillator mask option is selected, PB1/OSC3 is
used as an oscillator output. Using the 3-pin RC oscillator
configuration affects port B in these ways:
•
Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
•
Bit DDRB1 in data direction register B can be used as a read/write
storage location without affecting the oscillator. Reset clears
DDRB1.
•
The PB1/OSC3 pulldown device is disabled.
PB0 — Port B Data Bit 0
This read/write bit is software-programmable. Data direction of PB0 is
under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not used
Bits 7–2 always read as logic 0s.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
7.4.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output (see Figure 7-6). Writing a logic 1
to a DDRB bit enables the output buffer for the associated port B pin; a
logic 0 disables the output buffer. A reset initializes all DDRB bits to
logic 0, configuring all port B pins as inputs. Setting a DDRB bit to a
logic 1 turns off the pulldown device for that pin.
Freescale Semiconductor, Inc...
Address:
Read:
$0005
Bit 7
6
5
4
3
2
0
0
0
0
0
0
1
Bit 0
DDRB1
DDRB0
0
0
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
DDRB1 and DDRB0 — Data Direction Bits 1 and 0
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7–2 — Not used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
NOTE:
Technical Data
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
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Parallel Input/Output (I/O)
Port B
7.4.3 Pulldown Register B
Port B pins have mask-optional pulldown devices that sink
approximately 100 µA. Clearing the PDIB1 and PDIB0 bits in pulldown
register B turns on the port B pulldown devices. Pulldown register B can
turn on a port B pulldown device only when the port B pin is an input. See
Figure 7-7.
Freescale Semiconductor, Inc...
If the pulldown mask option is selected, reset initializes all port A and
port B pins as inputs with pulldown devices turned on.
Address:
$0011
Bit 7
6
5
4
3
2
1
Bit 0
PDIB1
PDIB0
0
0
Read:
Write:
Reset:
U
U
U
= Unimplemented
U
U
U
U = Unaffected
Figure 7-7. Pulldown Register B (PDRB)
PDIB1 and PDIB0 — Port B Pulldown Inhibit Bits 1 and 0
Writing logic 0s to these write-only bits turns on the port B pulldown
devices. Reading pulldown register B returns undefined data. Reset
clears PDIB1 and PDIB0.
1 = Corresponding port B pin pulldown device turned off
0 = Corresponding port B pin pulldown device turned on
Bits 7–2 — Not used
Bits 7–2 always read as logic 0s.
NOTE:
To avoid excessive current draw, connect all unused input pins to VDD
or VSS. Or change I/O pins to outputs by writing to DDRB in user
initialization code. Avoid a floating port B input by clearing its pulldown
register bit before changing its DDRB bit from logic 1 to logic 0.
Because pulldown register B is a write-only register, using the
read-modify-write instruction may result in inadvertently turning bits on
or off.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
7.4.4 Port B Logic
Figure 7-8 shows the port B I/O logic.
READ $0005
WRITE $0001
DATA DIRECTION
REGISTER B
BIT (DDRB1)
PORT B DATA
REGISTER
BIT (PB1)
PB1/
OSC3
PULLDOWN
REGISTER B
BIT (PDIB1)
100-mA
PULLDOWN
DEVICE
READ $0001
WRITE $0011
PULLDOWNS ENABLED
(MASK OPTION)
INTERNAL DATA BUS
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WRITE $0005
TO 3-PIN
OSCILLATOR
(ACTIVE LOW)
3-PIN RC OSCILLATOR
(MASK OPTION)
READ $0005
WRITE $0005
WRITE $0001
RC OSCILLATOR
(MASK OPTION)
DATA DIRECTION
REGISTER B
BIT (DDRB0)
PORT B DATA
REGISTER
BIT (PB0)
PB0
READ $0001
WRITE $0011
100-mA
PULLDOWN
DEVICE
PULLDOWN
REGISTER B
BIT (PDIB0)
RESET
Figure 7-8. Port B I/O Circuit
Technical Data
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Parallel Input/Output (I/O)
Port B
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDR bit. Table 7-2 and Table 7-3 summarize the
operation of the port B pins.
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Table 7-2. PB0 Pin Functions
Pulldown
Mask
Option
PDIB0
DDRB0
No
X
0
No
X
Yes
Control Bits
Accesses
to PDRB
PB0
Pin Mode
Accesses
to DDRB
Accesses
to PORTB
Read
Write
Read/Write
Read
Write
Input, hi-z
U
PDIB0
DDRB0
Pin
PB0
1
Output
U
PDIB0
DDRB0
PB0
PB0
0
0
Input,
pulldown on
U
PDIB0
DDRB0
Pin
PB0
Yes
0
1
Output
U
PDIB0
DDRB0
PB0
PB0
Yes
1
0
Input, hi-z
U
PDIB0
DDRB0
Pin
PB0
Yes
1
1
Output
U
PDIB0
DDRB0
PB0
PB0
X = Don’t care
U = Undefined
Table 7-3. PB1/OSC3 Pin Functions
Mask Options
Control Bits
3-Pin Osc.
Pulldowns
PDIB1
DDRB1
No
No
X
0
No
No
X
No
Yes
No
PB1/OSC3
Pin Mode
Accesses
to PDRB
Accesses
to DDRB
Accesses
to PORTB
Read
Write
Read/Write
Read
Write
Input, hi-z
U
PDIB1
DDRB1
Pin
PB1
1
Output
U
PDIB1
DDRB1
PB1
PB1
0
0
Input,
pulldown on
U
PDIB1
DDRB1
Pin
PB1
Yes
0
1
Output
U
PDIB1
DDRB1
PB1
PB1
No
Yes
1
0
Input, hi-z
U
PDIB1
DDRB1
Pin
PB1
No
Yes
1
1
Output
U
PDIB1
DDRB1
PB1
PB1
X = Don’t care
U = Undefined
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Technical Data
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 8. Multifunction Timer
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8.3
Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . .78
8.4
Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
8.5
COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
8.2 Introduction
This section describes the operation of the multifunction timer and the
computer operating properly (COP) watchdog. Figure 8-1 shows the
organization of the timer subsystem.
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Multifunction Timer
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Technical Data
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Technical Data
TIMER CLOCK (fOP)
(fOSC ÷ 2)
÷4
fOP ÷ 22
TIMER COUNTER REGISTER
TOF
fOP ÷ 210
7-BIT COUNTER
fOP ÷ 212
fOP ÷ 2
fOP ÷ 215
fOP ÷ 216
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fOP ÷ 2
POR
14
17
RTI
RATE
SELECT
RTIF
RT0
RT1
RTIE
INTERRUPT
REQUEST
TOIE
Q
COP RESET
S
÷2
÷2
÷2
R
COP CLEAR
RESET
Figure 8-1. Multifunction Timer Block Diagram
8.3 Timer Status and Control Register
The timer status and control register (TSCR), shown in Figure 8-2,
contains these bits:
Technical Data
•
Timer interrupt enable bits
•
Timer interrupt flags
•
Timer interrupt flag reset bits
•
Timer interrupt rate select bits
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Multifunction Timer
Timer Status and Control Register
Address:
Read:
$0008
Bit 7
6
TOF
RTIF
5
4
TOIE
RTIE
Write:
Reset:
0
0
0
0
3
2
0
0
TOFR
RTIFR
0
0
1
Bit 0
RT1
RT0
1
1
= Unimplemented
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Figure 8-2. Timer Status and Control Register (TSCR)
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
interrupt request if TOIE is also set. Clear TOF by writing a logic 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected real-time interrupt
(RTI) output becomes active. RTIF generates a real-time interrupt
request if RTIE is also set. Clear RTIF by writing a logic 1 to the
RTIFR bit. Writing to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as a logic 0. Reset does not affect TOFR.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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Technical Data
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic 0. Reset does not affect RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
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These read/write bits select 1of four real-time interrupt rates, as
shown in Table 8-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and real-time interrupt
period.
Table 8-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period(1)
Number
of Cycles
to COP Reset
COP Timeout
Period(1)
00
214 = 16,384
8.2 ms
217 = 131,072
65.5 ms
01
215 = 32,768
16.4 ms
218 = 262,144
131.1 ms
10
216 = 65,536
32.8 ms
219 = 524,288
262.1 ms
11
217 = 131,072
65.5 ms
220 = 1,048,576
524.3 ms
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
NOTE:
Be careful when altering RT0 or RT1 when a timeout is imminent or
uncertain. If the selected RTx is modified during a cycle when the
counter is switching, an RTIF can be missed or an additional RTIF can
be generated. To avoid this problem, clear the COP just before changing
RT1 and RT0.
The COP timer is the RTI timer divided by eight. However, clearing the
COP clears only the last three dividers. It does not clear the RTI section
of the divider chain. Therefore, the COP timeout period is in the range of
seven to eight times the RTI period.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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Multifunction Timer
Timer Counter Register
8.4 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register shown in Figure 8-3.
Address:
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Read:
$0009
Bit 7
6
5
4
3
2
1
Bit 0
TCR7
TCR6
TCR5
TCR4
TCR3
TCR2
TCR1
TCR0
0
0
0
0
0
0
0
0
Write:
Reset:
= Unimplemented
Figure 8-3. Timer Counter Register (TCNTR)
Power-on clears the entire counter chain and begins clocking the
counter. After 4064 cycles, the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Each count of the timer counter register takes eight oscillator cycles or
four cycles of the internal clock.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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8.5 COP Watchdog
Three counter stages at the end of the timer make up the mask optional
computer operating properly (COP) watchdog (see Figure 8-1). The
COP watchdog is a software error detection system that automatically
times out and resets the MCU if not cleared periodically by a program
sequence. Writing a logic 0 to bit 0 of the COP register, shown in
Figure 8-4, clears the COP watchdog and prevents a COP reset.
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Address:
Read:
$03F0
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
1
0
Write:
Reset:
COPC
U
U
U
= Unimplemented
U
U
U
U
0
U = Unaffected
Figure 8-4. COP Register (COPR)
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $03F0
returns the ROM data at that address.
The COP watchdog is active in the run, wait, and halt modes of
operation. The STOP instruction disables the COP watchdog by clearing
the counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled (converted
to halt) by a mask option.
In applications that have wait cycles longer than the COP timeout period,
the COP watchdog can be disabled by a mask option.
NOTE:
Technical Data
If the voltage on the IRQ/VPP pin exceeds a nominal 1.5 × VDD, the COP
watchdog turns off and remains off until the IRQ/VPP voltage falls below
2 × VDD.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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Multifunction Timer
COP Watchdog
Table 8-2 summarizes recommended conditions for enabling and
disabling the COP watchdog.
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Table 8-2. COP Watchdog Recommendations
STOP
Instruction
(Mask Option)
Wait/Halt Time
Recommended
COP Watchdog Condition
Disabled
Less than COP timeout period
Enabled(1)
Disabled
Greater than COP timeout period
Disabled
1. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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Technical Data
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Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 9. Personality EPROM (MC68HC05K1 Only)
9.1 Contents
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9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9.3
PEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.3.1
PEPROM Bit Select Register (PEBSR) . . . . . . . . . . . . . . . .87
9.3.2
PEPROM Status and Control Register (PESCR) . . . . . . . . .89
9.4
PEPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
9.5
PEPROM Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
9.2 Introduction
This section describes how to program the 64-bit personality erasable,
programmable read-only memory (PEPROM) on the MC68HC05K1
only. Figure 9-1 shows the structure of the PEPROM subsystem.
NOTE:
The PEPROM cannot be erased in parts offered without the windowed
package.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Technical Data
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Technical Data
INTERNAL DATA BUS
0
0
0
0
PEPRZF
PEDATA
RESET
VPP
ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
COL 7
COL 6
COL 5
COL 4
COL 3
COL 2
COL 1
COL 0
ROW 7
8-TO-1 COLUMN DECODER
AND MULTIPLEXER
VPP SWITCH
8-TO-1 ROW DECODER
AND MULTIPLEXER
VPP SWITCH
PEB0
PEB1
PEB2
PEB3
PEB4
PEB5
0
ROW ZERO
DECODER
0
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SINGLE
SENSE
AMPLIFIER
PEPGM
0
PEPROM STATUS/CONTROL REGISTER
PEPROM STATUS/CONTROL REGISTER
RESET
INTERNAL DATA BUS
Figure 9-1. PEPROM Block Diagram
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Personality EPROM (MC68HC05K1 Only)
PEPROM Registers
9.3 PEPROM Registers
Two input/output (I/O) registers control programming and reading of the
PEPROM:
•
PEPROM bit select register (PEBSR)
•
PEPROM status and control register (PESCR)
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9.3.1 PEPROM Bit Select Register
The PEPROM bit select register (PEBSR), shown in Figure 9-2, selects
one of 64 bits in the PEPROM array. Reset clears all the bits in the
PEPROM bit select register.
Address:
$000E
Bit 7
6
5
4
3
2
1
Bit 0
PEB7
PEB6
PEB5
PEB4
PEB3
PEB2
PEB1
PEB0
0
0
0
0
0
0
0
0
Read:
Write:
Reset:
Figure 9-2. PEPROM Bit Select Register (PEBSR)
PEB7 and PEB6 — Not Connected to the PEPROM Array
These read/write bits are available as storage locations. Reset clears
PEB7 and PEB6.
PEB5–PEB0 — PEPROM Bit Select Bits
These read/write bits select one of 64 bits in the PEPROM as shown
in Table 9-1. Bits PEB2–PEB0 select the PEPROM row, and bits
PEB5–PEB3 select the PEPROM column. Reset clears PEB5–PEB0,
selecting the PEPROM bit in row zero, column zero.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
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Table 9-1. PEPROM Bit Selection
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PEBSR
Technical Data
PEPROM Bit Selected
$00
Row 0
Column 0
$01
Row 1
Column 0
$02
Row 2
Column 0
$07
Row 7
Column 0
$08
Row 0
Column 1
$09
Row 1
Column 1
$0A
Row 2
Column 1
$0F
Row 7
Column 1
$10
Row 0
Column 2
$11
Row 1
Column 2
$12
Row 2
Column 2
$37
Row 7
Column 6
$38
Row 0
Column 7
$39
Row 1
Column 7
$3A
Row 2
Column 7
$3B
Row 3
Column 7
$3C
Row 4
Column 7
$3D
Row 5
Column 7
$3E
Row 6
Column 7
$3F
Row 7
Column 7
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Personality EPROM (MC68HC05K1 Only)
PEPROM Registers
9.3.2 PEPROM Status and Control Register
The PEPROM status and control register (PESCR), shown in
Figure 9-3, controls the PEPROM programming voltage. This register
also transfers the PEPROM bits to the internal data bus and contains a
row zero flag.
Address:
$000F
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Bit 7
Read: PEDATA
6
5
0
4
3
2
1
Bit 0
0
0
0
0
PEPRZF
0
0
0
0
1
PEPGM
Write:
Reset:
U
0
0
= Unimplemented
U = Unaffected
Figure 9-3. PEPROM Status and Control Register (PESCR)
PEDATA — PEPROM Data Bit
This read-only bit is the state of the PEPROM sense amplifier and
shows the state of the currently selected bit. Reset does not affect the
PEDATA bit.
1 = PEPROM data logic 1
0 = PEPROM data logic 0
PEPGM — PEPROM Program Control Bit
This read/write bit controls the switches that apply the programming
voltage, VPP, to the selected PEPROM cell. Reset clears PEPGM.
1 = Programming voltage applied
0 = Programming voltage not applied
PEPRZF — PEPROM Row Zero Flag
This read-only bit is set when the PEPROM bit select register selects
the first row (row zero) of the PEPROM array. Selecting any other row
clears PEPRZF. Monitoring PEPRZF can reduce the code needed to
access one byte of PEPROM. Reset sets PEPRZF.
1 = Row zero selected
0 = Row zero not selected
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Technical Data
9.4 PEPROM Programming
Factory-provided software for programming the PEPROM is available
through the Motorola Web site at:
htt://mcu.motsps.com
The circuit shown in Figure 9-4 can be used to program the PEPROM
with the factory-provided programming software.
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NOTE:
The personality EPROM cannot be erased in parts offered without the
windowed package.
To program the PEPROM, VDD must be greater than 4.5 Vdc.
The PEPROM also can be programmed by user software with VPP
applied to the IRQ/VPP pin. This sequence shows how to program each
PEPROM bit:
1. Select a PEPROM bit by writing to PEBSR.
2. Set the PEPGM bit in PESCR.
3. Wait 3 ms.
4. Clear the PEPGM bit.
NOTE:
While the PEPGM bit is set and VPP is applied to the IRQ/VPP pin, do not
access bits that are to be left unprogrammed (erased).
In the 3-pin RC oscillator configuration, the PEPROM cannot be
programmed by user software. If the voltage on IRQ/VPP is raised above
VDD, the oscillator will revert to a 2-pin oscillator configuration and
device operation will be disrupted. The 2-pin RC and crystal
configurations are not affected.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Personality EPROM (MC68HC05K1 Only)
PEPROM Programming
2.2 kΩ
VCC
VCC
2.2 kΩ
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220 Ω
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
STROBE
MC68HC05K1
1
2
3
4
5
6
7
8
D0
D1
INIT
D2
D3
RESET
PB1
PB0
IRQ/VPP
PA0
PA1
PA2
PA3
OSC1
OSC2
VSS
VDD
PA7
PA6
PA5
PA4
16
15
14
13
12
11
10
9
0.1 µF
VCC
D4
D5
D6
D7
ACK
PE
0.1
µF
170 µH
5V
VCC
330 Ω
4.7 Ω
8
1
DR COL
SW COL
7
2
SENSE
SW EMIT
6
3
VCC
CAP
5
4
COMPARE
GND
S1
10 µF
+
10 µF
+
IN5817
0.1 µF
5 kΩ
100 pF
MC34063
100 Ω
15 kΩ
VPP
1.5 kΩ
OPTIONAL VPP GENERATOR
S2
10 µH
0.1 µF
10 µF
100 Ω
+
0.1 µF
10 µF
+
Figure 9-4. Programming Circuit
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Technical Data
9.5 PEPROM Reading
This sequence shows how to read the PEPROM:
1. Select a bit by writing to PEBSR.
2. Read the PEDATA bit in PESCR.
3. Store the PEDATA bit in RAM or in a register.
4. Select another bit by changing PEBSR.
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5. Continue reading and storing the PEDATA bits until the required
personality EPROM data is stored.
Reading the PEPROM is easiest when each PEPROM column contains
one byte. Selecting a row-0 bit selects the first bit, and incrementing the
PEPROM bit select register (PEBSR) selects the next row-1 bit from the
same column. Incrementing PEBSR seven more times selects the
remaining bits of the column and selects the row-0 bit of the next column,
setting the row-0 flag, PEPRZF.
A PEPROM byte that has been read can be transferred to the
personality EPROM bit select register (PEBSR) so that subsequent
reads of the PEBSR quickly yield that PEPROM byte.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Personality EPROM (MC68HC05K1 Only)
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Technical Data — MC68HC05K0 • MC68HC05K1
Section 10. Instruction Set
10.1 Contents
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10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
10.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .98
10.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .99
10.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .100
10.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .102
10.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
10.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
10.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Instruction Set
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Technical Data
10.2 Introduction
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The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 complementary metal oxide semiconductor (CMOS) Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
10.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction.
The eight addressing modes are:
Technical Data
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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Instruction Set
Addressing Modes
10.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
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10.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
10.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
10.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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10.3.5 Indexed, No Offset
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Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used random-access
memory (RAM) or input/output (I/O) location.
10.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
10.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
Technical Data
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Instruction Set
Instruction Types
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
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10.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
10.4 Instruction Types
The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
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Technical Data
10.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 10-1. Register/Memory Instructions
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Instruction
Technical Data
Mnemonic
Add memory byte and carry bit to accumulator
ADC
Add memory byte to accumulator
ADD
AND memory byte with accumulator
AND
Bit test accumulator
BIT
Compare accumulator
CMP
Compare index register with memory byte
CPX
Exclusive OR accumulator with memory byte
EOR
Load accumulator with memory byte
LDA
Load Index register with memory byte
LDX
Multiply
MUL
OR accumulator with memory byte
ORA
Subtract memory byte and carry bit from
accumulator
SBC
Store accumulator in memory
STA
Store index register in memory
STX
Subtract memory byte from accumulator
SUB
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Instruction Set
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Instruction Set
Instruction Types
10.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE:
Do not use read-modify-write operations on write-only registers.
Table 10-2. Read-Modify-Write Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Arithmetic shift left (same as LSL)
ASL
Arithmetic shift right
ASR
Bit clear
BCLR(1)
Bit set
BSET(1)
Clear register
CLR
Complement (one’s complement)
COM
Decrement
DEC
Increment
INC
Logical shift left (same as ASL)
LSL
Logical shift right
LSR
Negate (two’s complement)
NEG
Rotate left through carry bit
ROL
Rotate right through carry bit
ROR
Test for negative or zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and BSET use
only direct addressing.
2. TST is an exception to the read-modify-write sequence because it
does not write a replacement value.
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Technical Data
10.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
Freescale Semiconductor, Inc...
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
Technical Data
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Table 10-3. Jump and Branch Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Branch if carry bit clear
BCC
Branch if carry bit set
BCS
Branch if equal
BEQ
Branch if half-carry bit clear
BHCC
Branch if half-carry bit set
BHCS
Branch if higher
BHI
Branch if higher or same
BHS
Branch if IRQ pin high
BIH
Branch if IRQ pin low
BIL
Branch if lower
BLO
Branch if lower or same
BLS
Branch if interrupt mask clear
BMC
Branch if minus
BMI
Branch if interrupt mask set
BMS
Branch if not equal
BNE
Branch if plus
BPL
Branch always
BRA
Branch if bit clear
Branch never
Branch if bit set
BRCLR
BRN
BRSET
Branch to subroutine
BSR
Unconditional jump
JMP
Jump to subroutine
JSR
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Technical Data
10.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 10-4. Bit Manipulation Instructions
Instruction
Mnemonic
Freescale Semiconductor, Inc...
Bit clear
BCLR
Branch if bit clear
BRCLR
Branch if bit set
BRSET
Bit set
Technical Data
BSET
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Instruction Types
10.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 10-5. Control Instructions
Freescale Semiconductor, Inc...
Instruction
Mnemonic
Clear carry bit
CLC
Clear interrupt mask
CLI
No operation
NOP
Reset stack pointer
RSP
Return from interrupt
RTI
Return from subroutine
RTS
Set carry bit
SEC
Set interrupt mask
SEI
Stop oscillator and enable IRQ pin
STOP
Software interrupt
SWI
Transfer accumulator to index register
TAX
Transfer index register to accumulator
TXA
Stop CPU clock and enable interrupts
WAIT
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Technical Data
10.5 Instruction Set Summary
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
REL
24
rr
3
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
— — ↕
0
b7
Arithmetic Shift Right
↕ — ↕
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ — ↕
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
— — — — —
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
Mn ← 0
ff
ff
Cycles
Description
Opcode
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Operation
Effect
on CCR
Address
Mode
Freescale Semiconductor, Inc...
Source
Form
Operand
Table 10-6. Instruction Set Summary (Sheet 1 of 6)
5
3
3
6
5
5
3
3
6
5
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
PC ← (PC) + 2 + rel ? C = 1
— — — — —
REL
25
rr
3
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
BHI rel
Branch if Higher
BHS rel
Branch if Higher or Same
Technical Data
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
22
rr
3
REL
24
rr
3
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Instruction Set
Instruction Set Summary
Address
Mode
Opcode
Operand
Cycles
Table 10-6. Instruction Set Summary (Sheet 2 of 6)
BIH rel
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
A5 ii
2
B5 dd 3
C5 hh ll 4
D5 ee ff 5
E5 ff
4
F5
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Description
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
Effect
on CCR
H I N Z C
↕ —
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
— — — — —
REL
2C
rr
3
— — — — —
REL
2B
rr
3
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
— — — — —
REL
2D
rr
3
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
— — — — —
REL
26
rr
3
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
— — — — —
REL
2A
rr
3
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
PC ← (PC) + 2 + rel ? Mn = 0
BRCLR n opr rel Branch if Bit n Clear
BRN rel
PC ← (PC) + 2 + rel ? 1 = 0
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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Technical Data
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Technical Data
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
↕ 1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect
on CCR
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory
Byte
Increment Byte
Unconditional Jump
Technical Data
— — ↕
(A) – (M)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
— — ↕
— — ↕
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
— — 0 1 —
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
— — ↕
— — ↕
— — ↕
↕
↕
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Description
Operand
Freescale Semiconductor, Inc...
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
Operation
Opcode
Source
Form
Address
Mode
Table 10-6. Instruction Set Summary (Sheet 3 of 6)
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
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Instruction Set
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Instruction Set
Instruction Set Summary
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
0 — — — 0
INH
42
— — ↕
DIR
INH
INH
IX1
IX
30
40
50
60
70
Negate Byte (Two’s Complement)
NOP
No Operation
— — — — —
INH
9D
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA ii
2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff
4
FA
3
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
↕
DIR
INH
INH
IX1
IX
39
49
59
69
79
Rotate Byte Left through Carry Bit
C
— — 0 ↕
— — ↕
b7
↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
b0
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↕
↕
↕
ff
ff
Cycles
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
— — — — —
DIR
EXT
IX2
IX1
IX
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Description
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Effect
on CCR
Address
Mode
Source
Form
Operand
Table 10-6. Instruction Set Summary (Sheet 4 of 6)
5
3
3
6
5
5
3
3
6
5
1
1
dd
ff
5
3
3
6
5
2
dd
ff
5
3
3
6
5
Technical Data
Freescale Semiconductor, Inc.
Technical Data
Opcode
Operand
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
↕
↕
INH
80
9
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Freescale Semiconductor, Inc...
Source
Form
Operation
Effect
on CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
RTS
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
ff
Cycles
Address
Mode
Table 10-6. Instruction Set Summary (Sheet 5 of 6)
5
3
3
6
5
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
2
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
2
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
B7 dd 4
C7 hh ll 5
D7 ee ff 6
E7 ff
5
F7
4
— 0 — — —
INH
8E
— — ↕
↕ —
DIR
EXT
IX2
IX1
IX
BF dd 4
CF hh ll 5
DF ee ff 6
EF ff
5
FF
4
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
1
0
INH
97
2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Store Index Register In Memory
Subtract Memory Byte from Accumulator
SWI
Software Interrupt
TAX
Transfer Accumulator to Index Register
Technical Data
A ← (A) – (M) – (C)
M ← (A)
M ← (X)
A ← (A) – (M)
X ← (A)
— — ↕
↕
— — — — —
2
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Instruction Set
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Freescale Semiconductor, Inc.
Instruction Set
Opcode Map
Freescale Semiconductor, Inc...
Description
3D
4D
5D
6D
7D
dd
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
— — — — —
INH
9F
2
WAIT
Stop CPU Clock and Enable Interrupts
— 0 — — —
INH
8F
2
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
— — ↕
(M) – $00
A ← (X)
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
↕ —
ff
Cycles
DIR
INH
INH
IX1
IX
Effect
on CCR
H I N Z C
TST opr
TSTA
TSTX
TST opr,X
TST ,X
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
Operand
Operation
Opcode
Source
Form
Address
Mode
Table 10-6. Instruction Set Summary (Sheet 6 of 6)
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
10.6 Opcode Map
See Table 10-7.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Instruction Set
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Technical Data
Technical Data
Instruction Set
For More Information On This Product,
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F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
3
1
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 10-7. Opcode Map
Freescale Semiconductor, Inc...
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
3
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
Freescale Semiconductor, Inc.
Instruction Set
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Freescale Semiconductor, Inc.
Technical Data — MC68HC05K0 • MC68HC05K1
Section 11. Electrical Specifications
Freescale Semiconductor, Inc...
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
11.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.4
Equivalent Pin Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
11.5
Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .113
11.6
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
11.7
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
11.8
5.0-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .115
11.9
3.3-Volt DC Electrical Specifications . . . . . . . . . . . . . . . . . . .116
11.10 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
11.11 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
11.12 Typical Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . .124
11.2 Introduction
This section contains electrical and timing specifications.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
11.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
Freescale Semiconductor, Inc...
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating(1)
Symbol
Value
Unit
VDD
–0.3 to +7.0
V
I
25
mA
TSTG
–65 to +150
°C
Supply voltage
Current drain per pin excluding
VDD and VSS
Storage temperature range
1. Maximum values are not guaranteed operating values.
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 11.8 5.0-Volt DC Electrical Characteristics and
11.9 3.3-Volt DC Electrical Specifications for guaranteed operating
conditions.
11.4 Equivalent Pin Loading
Figure 11-1 shows the equivalent input/output (I/O) pin loading for test
purposes.
VDD
R2
PINS
VDD
PA3–PA0, PB1–PB0
TEST
POINT
4.5 V
PA7–PA4
C
R1
PA3–PA0, PB1–PB0
3.0 V
R1
R2
C
3.26 kΩ
2.38 kΩ
50 pF
470 Ω
2.38 kΩ
50 pF
10.91 kΩ
6.32 kΩ
50 pF
Figure 11-1. Equivalent Test Load
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Electrical Specifications
Operating Temperature Range
11.5 Operating Temperature Range
Rating
Symbol
Freescale Semiconductor, Inc...
Operating temperature range
MC68HC05K0/K1P(1), DW(2)
MC68HC05K0/K1C(3)P, CDW
MC68HC05K0/K1V(4)P, VDW
TA
Value
Unit
0 to +70
–40 to +85
–40 to +105
°C
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. C = Extended temperature range (–40°C to +85°C)
4. V = Automotive temperature range (–40°C to +105°C)
11.6 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Maximum junction temperature
TJ
150
°C
Thermal resistance
MC68HC05K0/K1P(1)
MC68HC05K0/K1DW(2)
θJA
100
140
°C/W
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
11.7 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)
(1)
Freescale Semiconductor, Inc...
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power dissipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < PINT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
K
PD =
(2)
TJ + 273°C
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
5.0-Volt DC Electrical Characteristics
11.8 5.0-Volt DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ
Max
Unit
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
VOH
VDD – 0.8
—
—
V
VOL
—
—
—
—
0.4
0.4
V
Input high voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.3 × VDD
V
—
—
2.0
0.4
7
4
mA
mA
IDD
—
—
—
—
—
0.2
0.7
1
45
0.2
10
10
10
100
10
µA
µA
µA
µA
µA
IOZ
—
—
±10
µA
IIL
50
75
200
µA
—
—
1.0
—
—
4.0
±1
±1
8.0
µA
µA
mA
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Freescale Semiconductor, Inc...
Output high voltage (ILoad = –0.8 mA)
PA7–PA0, PB1/OSC3, PB0
Output low voltage
PA3–PA0, PB1/OSC3, PB0 (ILoad = 1.6 mA)
PA7–PA4 (ILoad = 8.0 mA)
Supply current
Run(2)
Wait(3)
Stop(4)
25°C
0°C to +70°C (Standard)
–40°C to +85°C (Extended)
LVR enabled (25°C)
LVR disabled (25°C)
I/O ports hi-z leakage current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
Input pulldown current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
Input current
IRQ/VPP, OSC1
RESET (pulldown device off)
RESET (pulldown device on)
IIn
Capacitance
Ports (input or output)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
Low-voltage reset threshold
VLVR
2.8
3.5
4.5
V
Oscillator internal resistor (OSC1 to OSC2)
ROSC
1.0
2.0
3.0
MΩ
VPP
17.0
17.5
18.0
V
IPP
—
5
10
mA
PEPROM programming
voltage(5)
PEPROM programming current
1. VDD = 5.0 V ±10%, typical values reflect average measurements at midpoint of voltage range at 25°C
2. Run (operating) IDD measured using external square wave clock source (fosc = 4.2 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
3. Wait IDD measured using external square wave clock source (fosc = 4.2 MHz) All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
5. Programming voltage measured at IRQ/VPP pin
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
11.9 3.3-Volt DC Electrical Specifications
Symbol
Min
Typ(1)
Max
Unit
VOL
VOH
—
VDD – 0.1
—
—
0.1
—
V
Output high voltage (ILoad = –0.4 mA)
PA7–PA0, PB1/OSC3, PB0
VOH
VDD – 0.3
—
—
V
Output low voltage
PA3–PA0, PB1/OSC3, PB0 (ILoad = 0.4 mA)
PA7–PA4 (ILoad = 3.0 mA)
VOL
—
—
—
—
0.3
0.3
V
V
Input high voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input low voltage
PA7–PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
0.8
0.3
2.5
1.0
mA
mA
—
—
—
0.05
0.5
1
5
5
5
µA
µA
µA
Characteristic
Freescale Semiconductor, Inc...
Output voltage
ILoad = 10.0 µA
ILoad = –10.0 µA
Supply current
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
–40°C to +85°C (extended)
IDD
I/O ports hi-z leakage current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices off)
IOZ
—
—
±10
µA
Input pulldown current
PA7–PA0, PB1/OSC3, PB0 (pulldown devices on)
IIL
10
20
100
µA
Input current
IRQ/VPP, OSC1
RESET (pulldown devices off)
RESET (pulldown devices on)
IIn
—
—
0.2
—
—
2.0
±1
±1
4.0
µA
µA
mA
Capacitance
Ports (input or output)
RESET, IRQ/VPP
COut
CIn
—
—
—
—
12
8
pF
Oscillator internal resistor (OSC1 to OSC2)
ROSC
1.0
2.0
3.0
MΩ
1. VDD = 3.3 V ±0.3 V, typical values reflect average measurements at midpoint of voltage range at 25°C
2. Run (operating) IDD measured using external square wave clock source (fosc = 2.0 MHz) with all inputs 0.2 V from rail; no
dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
3. Wait IDD measured using external square wave clock source (fosc = 2.0 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = VDD. Low-voltage reset disabled. All ports configured as inputs. VIL = 0.2 V,
VIH = VDD – 0.2 V.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt DC Electrical Specifications
VDD = 5.0 V
VDD = 3.3 V
0.8
0.8
0.6
0.6
0.5
0.5
VDD – VOH (V)
0.7
0.4
0.3
0.4
(NOTE 3)
0.3
0.2
0.2
0.1
0.1
0
0
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
–1.0
–2.0
IOH (mA)
–3.0
–4.0
–5.0
IOH (mA)
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOH ≥ VDD – 800 mV @ IOH = –0.8 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOH ≥ VDD – 300 mV @ IOH = –0.2 mA.
Figure 11-2. Typical High-Side Driver Characteristics
VDD = 5.0 V
VDD = 3.3 V
0.40
0.40
(NOTE 2)
0.35
0.35
0.30
0.30
0.25
0.25
VOL (V)
VOL (V)
Freescale Semiconductor, Inc...
VDD – VOH (V)
(NOTE 2)
0.7
0.20
0.15
0.20
0.15
0.10
0.10
0.05
0.05
0
(NOTE 3)
0
0
2.0
4.0
6.0
8.0
10.0
0
2.0
4.0
IOL (mA)
6.0
8.0
10.0
IOL (mA)
Notes:
1. Shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances.
Within the limited range of values shown, V versus. I curves are approximately straight lines.
2. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
3. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 11-3. Typical Low-Side Driver Characteristics
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
T = 25°C
3.0
2.5
5.5 V
4.5 V
Freescale Semiconductor, Inc...
SUPPLY CURRENT (mA)
2.0
3.6 V
3.0 V
1.5
1.0
0.5
0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 11-4. Typical Run IDD versus Internal Clock Frequency
T = 25°C
900
800
SUPPLY CURRENT (mA)
700
5.5 V
4.5 V
600
3.6 V
3.0 V
500
400
300
200
100
0
0
0.5
1.0
1.5
2.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 11-5. Typical Wait IDD versus Internal Clock Frequency
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt DC Electrical Specifications
2500
2000
Freescale Semiconductor, Inc...
SUPPLY CURRENT (nA)
5.5 V
4.5 V
1500
3.6 V
3.0 V
1000
500
0
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 11-6. Typical Stop IDD versus Temperature
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
For More Information On This Product,
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
11.10 5.0-Volt Control Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal(2)/ceramic resonator
External clock
Symbol
fosc
Internal operating frequency (fosc ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal(1)/ceramic resonator
External clock
fop
Min
Max
0.1(3)
0.1(2)
0.500
dc
1.2
2.4
4.0
4.0
0.05(2)
0.05(2)
0.250
dc
0.6
1.2
2.0
2.0
Unit
MHz
MHz
2-pin RC oscillator frequency combined stability(4)
fosc = 2.0 MHz; VDD = 5.0 Vdc ±10%; TA = –40°C to +85°C
fosc = 2.0 MHz; VDD = 5.0 Vdc ±10%; TA = 0°C to +40°C
∆fosc
—
—
±25
±15
%
3-pin RC oscillator frequency combined stability(3)
fosc = 1.0 MHz; VDD = 5.0 Vdc ±10%; TA = –40°C to +85°C
fosc = 1.0 MHz; VDD = 5.0 Vdc ±10%; TA = 0°C to +40°C
∆fosc
—
—
±15
±7
%
tcyc
500
—
ns
RC oscillator stabilization time
tRCON
—
1
ms
Crystal oscillator startup time
tOXOV
—
100
ms
Stop recovery startup time
tILCH
—
100
ms
tRL
1.5
—
tcyc
Timer resolution(5)
tRESL
4.0
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
IRQ interrupt pulse period
tILIL
Note(6)
—
tcyc
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
PA3–PA0 interrupt pulse period
tIHIH
Note(5)
—
tcyc
tOH, tOL
200
—
ns
tEPGM
10
15
ms
Cycle time (1 ÷ fop)
RESET pulse width low
OSC1 pulse width
PEPROM programming time per byte(7)
1. VDD = 5.0 Vdc ±10%
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Includes processing tolerances and variations in temperature and supply voltage; excludes tolerances of external R and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc.
7. Programming time per byte is tEPGM which may be accumulated during multiple programming passes.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt Control Timing
11.11 3.3-Volt Control Timing
Characteristic(1)
Freescale Semiconductor, Inc...
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal(2)/ceramic resonator
External clock
Symbol
fosc
Internal operating frequency (fosc ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal(1)/ceramic resonator
External clock
fop
Min
Max
0.1(3)
0.1(2)
0.500
dc
1.2
2.0
2.0
2.0
0.05(2)
0.05(2)
0.250
dc
0.6
1.0
1.0
1.0
Unit
MHz
MHz
2-pin RC oscillator frequency combined stability(4)
fosc = 2.0 MHz; VDD = 3.3 Vdc ±0.3 V; TA = –40°C to +85°C
fosc = 2.0 MHz; VDD = 3.3 Vdc ±0.3 V; TA = 0°C to +40°C
∆fosc
—
—
±35
±20
%
3-pin RC oscillator frequency combined stability(3)
fosc = 1.0 MHz; VDD = 3.3 Vdc ± 0.3 V; TA = –40°C to +85°C
fosc = 1.0 MHz; VDD = 3.3 Vdc ± 0.3 V; TA = 0°C to +40°C
∆fosc
—
—
±15
±10
%
tcyc
1000
—
ns
RC oscillator stabilization time
tRCON
—
1
ms
Crystal oscillator startup time
tOXOV
—
100
ms
Stop recovery startup time
tILCH
—
100
ms
tRL
1.5
—
tcyc
Timer resolution(5)
tRESL
4.0
—
tcyc
IRQ interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
IRQ interrupt pulse period
tILIL
Note(6)
—
tcyc
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
PA3–PA0 interrupt pulse period
tIHIH
Note(5)
—
tcyc
tOH, tOL
200
—
ns
Cycle time (1 ÷ fop)
RESET pulse width low
OSC1 pulse width
1. VDD = 3.3 Vdc ±10%
2. Use only AT-cut crystals.
3. Minimum oscillator frequency with RC oscillator option is limited only by size of external R and C and leakage of external C.
4. Includes processing tolerances and variations in temperature and supply voltage; excludes tolerances of external R and C.
5. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
6. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
tILIL
tILIH
IRQ/VPP PIN
tILIH
IRQ1
.
.
.
IRQn
Freescale Semiconductor, Inc...
IRQ (INTERNAL)
Figure 11-7. External Interrupt Timing
OSC (NOTE 1)
tRL
RESET
tILIH
IRQ/VPP (NOTE 2)
4064 tCYC
IRQ/VPP (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
(NOTE 4)
03FE
03FE
03FE
03FE
03FF
RESET OR INTERRUPT
VECTOR FETCH
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
Figure 11-8. Stop Mode Recovery Timing
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
3.3-Volt Control Timing
VDD
NOTE 1
4064 tCYC
OSC1 PIN
Freescale Semiconductor, Inc...
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
03FE
03FE
03FE
03FE
INTERNAL
DATA BUS
03FE
NEW
PCH
03FF
NEW
PCL
Notes:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 11-9. Power-On Reset Timing
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
03FE
03FE
03FE
03FE
NEW
PCH
INTERNAL
DATA BUS
03FF
NEW
PCL
NEW PC
DUMMY
NEW PC
OP
CODE
tRL
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 11-10. External Reset Timing
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
11.12 Typical Oscillator Characteristics
Parameter
Oscillator Type
Nominal Frequency
VDD = 3.0 V
VDD = 5.0 V
Units
Freescale Semiconductor, Inc...
Frequency Variation
(Part-to-Part)
2-pin RC oscillator
2 MHz
±12
±7
3-pin RC oscillator
1 MHz
±5
±4
%
Frequency Variation
with Temperature
2-pin RC oscillator
2 MHz
–2100
–1600
3-pin RC oscillator
1 MHz
–1100
–1100
ppm/°C
Frequency Variation
with Supply Voltage
2-pin RC oscillator
2 MHz
±1.0
±0.2
3-pin RC oscillator
1 MHz
±0.3
±0.1
%f/%V
Cumulative Frequency
Variations(1)
2-pin RC oscillator
2 MHz
±36
±20
3-pin RC oscillator
1 MHz
±16
±13
%
1. VDD ±10%; TA = –40°C to +85°C
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Electrical Specifications
Typical Oscillator Characteristics
4.0 E+6
15 pF
20 pF
3.5 E+6
30 pF
39 pF
50 pF
2.5 E+6
2.0 E+6
1.5 E+6
1.0 E+6
500.0 E+3
000.0 E+0
5 kΩ
10 kΩ
20 kΩ
30 kΩ
40 kΩ
RESISTANCE
Figure 11-11. 2-Pin RC Oscillator R versus Frequency (VDD = 5.0 V)
2.5 E+6
15 pF
20 pF
30 pF
2.0 E+6
39 pF
EXTERNAL FREQUENCY
Freescale Semiconductor, Inc...
EXTERNAL FREQUENCY
3.0 E+6
50 pF
1.5 E+6
1.0 E+6
500.0 E+3
000.0 E+0
5 kΩ
10 kΩ
20 kΩ
30 kΩ
RESISTANCE
Figure 11-12. 3-Pin RC Oscillator R versus Frequency (VDD = 5.0 V)
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
3.0 E+6
15 pF
20 pF
2.5 E+6
30 pF
2.0 E+6
50 pF
1.5 E+6
1.0 E+6
500.0 E+3
000.0 E+0
5 kΩ
10 kΩ
20 kΩ
30 kΩ
40 kΩ
RESISTANCE
Figure 11-13. 2-Pin Oscillator R versus Frequency (VDD = 3.0 V)
3.0 E+6
15 pF
20 pF
2.5 E+6
30 pF
39 pF
EXTERNAL FREQUENCY
Freescale Semiconductor, Inc...
EXTERNAL FREQUENCY
39 pF
2.0 E+6
50 pF
1.5 E+6
1.0 E+6
500.0 E+3
000.0 E+0
5 kΩ
10 kΩ
20 kΩ
30 kΩ
RESISTANCE
Figure 11-14. 3-Pin Oscillator R versus Frequency (VDD = 3.0 V)
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Electrical Specifications
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Freescale Semiconductor, Inc.
Technical Data — MC68HC05K0 • MC68HC05K1
Section 12. Mechanical Specifications
Freescale Semiconductor, Inc...
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
12.3
MC68HC05K0/MC68HC05K1P (PDIP) . . . . . . . . . . . . . . . . .128
12.4
MC68HC05K0/MC68HC05K1DW (SOIC) . . . . . . . . . . . . . . .128
12.2 Introduction
Package dimensions available at the time of this publication are
provided in this section. The packages are:
•
16-pin plastic dual-in-line package (PDIP)
•
16-pin small outline integrated circuit (SOIC)
To make sure that you have the latest case outline specifications,
contact one of these:
•
Local Motorola sales office
•
Motorola Mfax
– Phone 602-244-6609
– EMAIL [email protected]
•
World Wide Web (wwweb) at http://www.mcu.motsps.com
Follow Mfax or wwweb on-line instructions to retrieve the current
mechanical specifications.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Mechanical Specifications
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
12.3 MC68HC05K0/MC68HC05K1P (PDIP)
-A16
9
1
8
B
INCHES
DIM
F
C
L
Freescale Semiconductor, Inc...
S
-T-
SEATING
PLANE
K
H
M
J
G
D
A
B
C
D
F
G
H
J
K
L
M
S
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0°
10°
0.020
0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0°
10°
0.51
1.01
16 PL
0.25 (0.010) M T A M
12.4 MC68HC05K0/MC68HC05K1DW (SOIC)
-A16
9
-B-
8X
P
0.010 (0.25) M
1
B
DIM
A
B
C
D
F
G
J
K
M
P
R
M
8
J
D 16X
0.010 (0.25) M T A
S
B S
F
R
MILLIMETERS
INCHES
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0°
7°
10.05
10.55
0.25
0.75
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0°
7°
0.395
0.415
0.010
0.029
X 45
C
-TG 14X
Technical Data
K
SEATING
PLANE
M
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Mechanical Specifications
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Freescale Semiconductor, Inc.
Technical Data — MC68HC05K0 • MC68HC05K1
Section 13. Ordering Information
Freescale Semiconductor, Inc...
13.1 Contents
13.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
13.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
13.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .130
13.4.1 Diskettes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
13.4.2 EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
13.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .132
13.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .133
13.7
MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
13.2 Introduction
This section contains instructions for ordering custom-masked read-only
memory (ROM) microcontroller units (MCU).
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
13.3 MCU Ordering Forms
Freescale Semiconductor, Inc...
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit these
items when ordering MCUs:
•
A current MCU ordering form that is completely filled out.
Contact a Motorola sales office for assistance.
•
A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU
•
Customer’s application program on one of the media listed in
13.4 Application Program Media
The current MCU ordering form is also available through the World Wide
Web (wwweb) at http://www.mcu.motsps.com
13.4 Application Program Media
Deliver the application program to Motorola in one of these media:
•
Macintosh®1 3 1/2-inch diskette (double-sided double-density
800 Kbytes or double-sided high-density 1.4 Mbytes)
•
MS-DOS®2 or PC-DOS®3 3 1/2-inch diskette (double-sided
double-density 720 Kbytes or double-sided high-density
1.44 Mbytes)
•
MS-DOS® or PC-DOS® 5 1/4-inch diskette (double-sided
double-density 360 Kbytes or double-sided high-density
1.2 Mbytes)
•
Erasable, programmable read-only memory(s) (EPROM) 2716,
2732, 2764, 27,128, 27,256, or 27,512 (depending on the size of
the memory map of the MCU)
Use positive logic for data and addresses.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft, Inc.
3. PC-DOS is a registered trademark of International Business Machines Corporation.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc.
Ordering Information
Application Program Media
13.4.1 Diskettes
Freescale Semiconductor, Inc...
If submitting the application program on a diskette, clearly label the
diskette with this information:
•
Customer name
•
Customer part number
•
Project or product name
•
Filename of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
NOTE:
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. See the current
MCU ordering form for additional requirements.
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
13.4.2 EPROMs
Freescale Semiconductor, Inc...
If submitting the application program in an EPROM, clearly label the
EPROM with this information:
NOTE:
•
Customer name
•
Customer part number
•
Checksum
•
Project or product name
•
Date
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations. See the current MCU ordering form for additional
requirements.
Submit the application program in one EPROM large enough to contain
the entire memory map. If the memory map has two user ROM areas
with the same addresses, then write the two areas on separate
EPROMs. Label the EPROMs with the addresses they contain.
Pack EPROMs securely in a conductive IC carrier for shipment. Do not
use Styrofoam®1.
13.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
1. Styrofoam is a registered trademark of The Dow Chemical Company.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc.
Ordering Information
ROM Verification Units (RVUs)
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
Freescale Semiconductor, Inc...
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank EPROMs or
preformatted Macintosh or DOS disks. All original pattern media are filed
for contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
13.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity but are not production parts. RVUs are not guaranteed by
Motorola Quality Assurance.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
13.7 MCU Order Numbers
Table 13-1 lists the MC order numbers for the available package types.
Table 13-1. MCU Order Numbers
Freescale Semiconductor, Inc...
Package Type
Operating
Temperature
Ranges
MC Order Number
16-pin plastic dual in-line
package (PDIP)
0°C to 70°C
MC68HC05K0P(1), DW(2)
16-pin plastic dual in-line
package (PDIP)
–40°C to +85°C
MC68HC05K0C(3)P, CDW
16-pin small outline integrated
circuit (SOIC)
–40°C to +105°C
MC68HC05K0V(4)P, VDW
16-pin plastic dual in-line
package (PDIP)
0°C to 70°C
16-pin plastic dual in-line
package (PDIP)
–40°C to +85°C
MC68HC05K1CP, CDW
16-pin small outline integrated
circuit (SOIC)
–40°C to +105°C
MC68HC05K1VP, VDW
MC68HC05K1P, DW
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
3. C = Extended temperature range (–40°C to +85°C)
4. V = Automotive temperature range (–40°C to +105°C)
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Ordering Information
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Freescale Semiconductor, Inc.
Technical Data — MC68HC05K0 • MC68HC05K1
Appendix A. MC68HCL05K0
Freescale Semiconductor, Inc...
A.1 Contents
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A.3
1.8–2.4-Volt DC Electrical Characteristics . . . . . . . . . . . . . . .136
A.4
2.5–3.6-Volt DC Electrical Characteristics . . . . . . . . . . . . . . .136
A.5
Low-Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.6
Low-Power Pulldown Current . . . . . . . . . . . . . . . . . . . . . . . . .138
A.7
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
A.2 Introduction
This appendix introduces the MC68HCL05K0, a low-power version of
the MC68HC05K0. All of the information in this manual applies to the
MC68HCL05K0 with the exceptions given in this appendix.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
A.3 1.8–2.4-Volt DC Electrical Characteristics
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Min
Typ
Max
Unit
Output high voltage
ILoad = –0.1 mA
PA7–PA0, PBB1/OSC3, PB0
VOH
VDD – 0.3
—
—
V
Output low voltage
ILoad = 0.2 mA
PPA3–PA0, PB1/OSC3, PB0
ILoad = 2.0 mA
PPA7–PA4
VOL
—
—
0.3
V
—
—
0.3
Symbol
Min
Typ
Max
Unit
Output high voltage
ILoad = –0.2 mA
PA7–PA0, PBB1/OSC3, PB0
VOH
VDD – 0.3
—
—
V
Output low voltage
ILoad = 0.4 mA
PA3–PA0
ILoad = 5.0 mA
PA7–PA4
VOL
—
—
0.3
V
—
—
0.3
1. VDD = 1.8–2.4 Vdc
A.4 2.5–3.6-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 2.5–3.6 Vdc
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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MC68HCL05K0
Low-Power Supply Current
A.5 Low-Power Supply Current
Characteristic
Symbol
Min
Typ(1)
Max
Unit
—
—
3.0
1.6
4.0
2.5
mA
mA
—
—
0.2
2.0
10
20
µA
µA
—
—
1.0
0.5
2.0
1.0
mA
mA
—
—
0.1
1.0
5.0
10.0
µA
µA
—
—
0.5
250
1.0
500
mA
µA
—
—
0.05
1.0
5.0
10.0
µA
µA
—
—
300
150
700
400
µA
µA
—
—
0.05
0.5
2.0
5.0
µA
µA
Supply current (VDD = 4.5–5.5 Vdc, fop = 2.1 MHz)
Freescale Semiconductor, Inc...
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
Supply current (VDD = 2.5–3.6 Vdc, fop = 1.0 MHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
Supply current (VDD = 2.5–3.6 Vdc, fop = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
Supply current (VDD = 1.8–2.4 Vdc, fop = 500 kHz)
Run(2)
Wait(3)
Stop(4)
25°C
0°C to 70°C (standard)
IDD
1. Typical values reflect average measurements at midpoint of voltage range at 25°C.
2. Run (operating) IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
3. Wait IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less than 50 pF
on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance
linearly affects wait IDD.
4. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
A.6 Low-Power Pulldown Current
Symbol
Min
Typ(1)
Max
Unit
Pulldown current (VDD = 4.5–5.5 Vdc, fop = 2.1 MHz)
PA7–PA0, PB1/OSC3, PB0 (pulldown device on)
IIL
50
100
200
µA
Pulldown current (VDD = 2.5–3.6 Vdc, fop = 1.0 MHz)
PA7–PA0, PB1/OSC3, PB0 (pulldown device on)
IIL
8
30
100
µA
Pulldown current (VDD = 2.5–3.6 Vdc, fop = 500 kHz)
PA7–PA0, PB1/OSC3, PB0 (pulldown device on)
IIL
3
10
50
µA
Pulldown current (VDD = 1.8–2.4 Vdc, fop = 500 kHz)
PA7–PA0, PB1/OSC3, PB0 (pulldown device on)
IIL
3
10
50
µA
1. Typical values reflect average measurements at midpoint of voltage range at 25°C.
2.0
1.8
VDD = 3.6 V
1.6
VDD = 2.4 V
1.4
1.2
RUN IDD (mA)
Freescale Semiconductor, Inc...
Characteristic
1.0
0.8
0.6
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 13-1. Maximum Run Mode IDD versus Frequency
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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MC68HCL05K0
Ordering Information
1.0
0.9
VDD = 3.6 V
0.8
VDD = 2.4 V
Freescale Semiconductor, Inc...
WAIT IDD (mA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure 13-2. Maximum Wait Mode IDD versus Frequency
A.7 Ordering Information
Table A-1 lists order numbers for the available package types.
Table A-1. MC68HCL05K0 Order Numbers
Operating
Temperature Range
Order Number
16-pin plastic dual in-line package (PDIP)
0°C to 70°C
MC68HCL05K0P(1)
16-pin small outline integrated circuit (SOIC)
0°C to 70°C
MC68HCL05K0DW(2)
Package Type
1. P = Plastic dual in-line package (PDIP)
2. DW = Small outline integrated circuit (SOIC)
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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Technical Data
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Technical Data
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HCL05K0
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Freescale Semiconductor, Inc.
Technical Data — MC68HC05K0 • MC68HC05K1
Appendix B. MC68HSC05K0
Freescale Semiconductor, Inc...
B.1 Contents
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.3
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . .142
B.4
5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
B.5
3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
B.6
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
B.2 Introduction
This appendix introduces the MC68HSC05K0, a high-speed version of
the MC68HC05K0. All of the information in this manual applies to the
MC68HSC05K0 with the exceptions given in this appendix.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HSC05K0
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
B.3 High-Speed Supply Current
Characteristic
Symbol
Min
Typ(1)
Max
Unit
—
—
4.5
2.5
6.0
3.25
mA
mA
—
—
0.2
2.0
10
20
µA
µA
—
—
2.0
1.0
4.0
2.0
mA
mA
—
—
0.1
1.0
5.0
10.0
µA
µA
Supply current (VDD = 4.5–5.5 Vdc, fop = 4.0 MHz)
Freescale Semiconductor, Inc...
Run(2)
Wait(3)
Stop(4)
25°C
–40°C to +85°C
IDD
Supply current (VDD = 3.0–3.6 Vdc, fop = 2.1 MHz)
Run
Wait
Stop
25°C
–40°C to +85°C
IDD
1. Typical values at midpoint of voltage range, 25°C only.
2. Run (operating) IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less
than 50 pF on all outputs. CL = 20 pF on OSC2. OSC2 capacitance linearly affects run IDD.
3. Wait IDD measured using external square wave clock source with all inputs 0.2 V from rail. No dc loads. Less than 50 pF
on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V. OSC2 capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = VDD. All ports configured as inputs. VIL = 0.2 V, VIH = VDD – 0.2 V.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HSC05K0
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MC68HSC05K0
5.0-Volt Control Timing
B.4 5.0-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
fosc
Internal operating frequency (fosc ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
fop
Internal clock cycle time (1 ÷ fop)
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
tcyc
Min
Max
Unit
0.02
0.2
0.2
dc
2.0
4.0
8.0
8.0
—
—
—
dc
1.0
2.0
4.0
4.0
1.0
500
250
250
—
—
—
—
µs
ns
ns
ns
MHz
MHz
RC oscillator stabilization time
tRCON
—
500
µs
Crystal oscillator startup time
tOXOV
—
50
ms
STOP recovery time
tILCH
—
50
ms
IRQ pulse width low (edge-triggered)
tILIH
125
—
ns
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
125
—
ns
tOH or tOL
45
—
ns
OSC1 pulse width
1. VDD = 5.0 Vdc ±10%; VSS = 0 Vdc; TA = TL to TH
2. Use only AT-cut crystals.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HSC05K0
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
B.5 3.3-Volt Control Timing
Freescale Semiconductor, Inc...
Characteristic(1)
Symbol
Oscillator frequency
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
fosc
Internal operating frequency (fosc ÷ 2)
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
fop
Internal clock cycle time (1 ÷ fop)
3-pin RC oscillator
2-pin RC oscillator
Crystal oscillator(2)
External clock
tcyc
Min
Max
Unit
0.02
0.2
0.2
dc
1.0
4.0
4.0
4.0
—
—
—
dc
1.0
2.0
2.0
2.0
1.0
500
500
500
—
—
—
—
µs
ns
ns
ns
MHz
MHz
RC oscillator stabilization time
tRCON
—
1.0
ms
Crystal oscillator startup time
tOXOV
—
100
ms
STOP recovery time
tILCH
—
100
ms
IRQ pulse width low (edge-triggered)
tILIH
250
—
ns
PA3–PA0 interrupt pulse width high (edge-triggered)
tIHIL
250
—
ns
tOH or tOL
100
—
ns
OSC1 pulse width
1. VDD = 3.3 Vdc ±10%; VSS = 0 Vdc; TA = TL to TH.
2. Use only AT-cut crystals.
B.6 Ordering Information
Table B-1 lists order numbers for the available package types.
Table B-1. MC68HSC05K0 Order Numbers
Operating
Temperature Range
Order Number
16-pin plastic dual in-line package (PDIP)
0°C to +70°C
MC68HSC05K0P(1)
16-pin small outline integrated circuit (SOIC)
0°C to +70°C
MC68HSC05K0DW(2)
Package Type
1. P = Plastic dual in-line pachage (PDIP)
2. DW = Small outline integrated circuit (SOIC)
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
MC68HSC05K0
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Technical Data — MC68HC05K0 • MC68HC05K1
Freescale Semiconductor, Inc...
Index
A
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94, 95, 98
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
arithmetic logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
block diagram
B
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
C
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
central processor unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
COP enabling/disabling recommendations . . . . . . . . . . . . . . . . .83
mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
CPU
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . . .40
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
stack pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95, 98, 103
accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94, 95, 98
condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . . .100
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . .94, 95, 96, 98
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97, 100
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
D
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Freescale Semiconductor, Inc...
E
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
EPROM (personality EPROM (PEPROM))
bit selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
PEPROM bit select register (PEBSR) . . . . . . . . . . . . . . . . . . . . .87
PEPROM reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
PEPROM status and control register (PESCR) . . . . . . . . . . . . . .89
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
programming circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
EPROM (personality)/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
programming voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
F
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
H
halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
high-speed MC68HSC05K0
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
I
I/O (input/output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
I/O bits
C bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94, 95, 96, 98
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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Freescale Semiconductor, Inc...
Index
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
external interrupt pin triggering mask options . . . . . . . . . . . . . . .19
interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . . .48
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PA3–PA0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
port A external interrupt function mask options . . . . . . . . . . . . . .19
port A external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . .51
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
L
low-power MC68HCL05K0
DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
low-voltage reset
mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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Technical Data
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M
mask option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
I/O (input/output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
personality EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . .34
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
multifunction timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
O
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
MCU order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
ordering information (high-speed part)
MCU order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
ordering information (low-power part)
MCU order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
OSC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
oscillator
ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
external clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124
resistor-capacitor (RC) combination . . . . . . . . . . . . . . . . . . . . . . .25
P
PA7–PA0
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
parallel input/output (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PB1/OSC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PB1/OSC3 and PB0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
personality EPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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Index
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . .67
external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
I/O logic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
port A data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
port A external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
pulldown devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
pulldown register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . .72
I/O logic circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PB1/OSC3 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
port B data register (PORTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
pulldown devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
pulldown register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97, 100
pulldown devices
mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
pulldown register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
pulldown register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
R
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
registers
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
reset
interrupt flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
computer operating properly (COP) . . . . . . . . . . . . . . . . . . . . . . .56
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
effect on CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
effect on I/O port registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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Technical Data
Freescale Semiconductor, Inc.
Technical Data
Freescale Semiconductor, Inc...
effect on timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
low-voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
reset states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
reset/interrupt vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . .51
sources diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
S
STOP instruction
mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
T
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
timer
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
COP enabling/disabling recommendations . . . . . . . . . . . . . . . . .83
COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
timer counter register (TCNTR) . . . . . . . . . . . . . . . . . . . . . . . . . .81
timer status and control register (TSCR) . . . . . . . . . . . . . . . . . . .78
V
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
wait mode
Technical Data
W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Index
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MC68HC05K0/K1 Rev. 2 TECHNICAL DATA
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SEC. 1: GEN. DESCRIPTION
SEC. 10: INSTR. SET
SEC. 2: MEMORY
SEC. 11: ELECTRICAL
SEC. 3: CPU
SEC. 12: MECHANICAL
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SEC. 4: INTERRUPTS
SEC. 13: ORDERING
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SEC. 5: RESETS
APP. A MC68HCL05K0
SEC. 6: LOW-POWER MODES
APP. B MC68HSC05K0
SEC. 7: PARALLEL I/O
INDEX
SEC. 8: TIMER
SEC. 9: EPROM
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