NXP 68HC05P1A Microcontroller Data Sheet

General Release Specification
February 25, 1997
© Freescale Semiconductor, Inc., 2004. All rights reserved.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
CSIC MCU Design Center
Austin, Texas
R E Q U I R E D
MC68HC05P1A
MC68HCL05P1A
MC68HSC05P1A
A G R E E M E N T
HC05P1AGRS/D
REV. 3.0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Freescale Semiconductor
General Release Specification — MC68HC05P1A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . 15
R E Q U I R E D
Freescale Semiconductor, Inc.
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Section 6. Operating Modes. . . . . . . . . . . . . . . . . . . . . . 49
Section 7. Input/Output Ports . . . . . . . . . . . . . . . . . . . . . 55
Section 8. 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Section 9. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . 77
Section 10. Electrical Specifications . . . . . . . . . . . . . . . 95
Section 11. Mechanical Specifications . . . . . . . . . . . . 107
Section 12. Ordering Information . . . . . . . . . . . . . . . . . 109
Appendix A. MC68HCL05P1A. . . . . . . . . . . . . . . . . . . . 113
Appendix B. MC68HSC05P1A. . . . . . . . . . . . . . . . . . . . 119
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A G R E E M E N T
Section 3. CPU Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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List of Sections
General Release Specification
MC68HC05P1A — Rev. 3.0
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Section 1. General Description
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1.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.2
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.1
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2
PB5, PB6, and PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.3
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.4
PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.5
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.6
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .24
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
2.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Single-Chip Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .25
Input/Output (I/O) and Control Registers . . . . . . . . . . . . . . . . .25
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .30
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .30
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A G R E E M E N T
Table of Contents
N O N - D I S C L O S U R E
General Release Specification — MC68HC05P1A
R E Q U I R E D
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A G R E E M E N T
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Table of Contents
Section 3. CPU Core
3.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Optional External Interrupts (PA0–PA7) . . . . . . . . . . . . . . .42
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .43
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Section 5. Resets
5.1
5.2
5.3
5.4
5.4.1
5.4.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Computer Operating Properly (COP) Reset . . . . . . . . . . . .46
Section 6. Operating Modes
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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7.1
7.2
7.3
7.4
7.5
7.6
7.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Section 8. 16-Bit Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Timer Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . .75
Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . .75
Section 9. Instruction Set
9.1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
9.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
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Section 7. Input/Output Ports
N O N - D I S C L O S U R E
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.1.2
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.2
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.5
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54
R E Q U I R E D
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9.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .82
9.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .83
9.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .84
9.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .86
9.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
9.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Section 10. Electrical Specifications
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .98
3.3 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .99
5.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
3.3 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Section 11. Mechanical Specifications
11.1
11.2
11.3
11.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Dual In-Line Package (Case 710). . . . . . . . . . . . . . . . . . . . . .107
Small Outline Integrated Circuit (Case 751F) . . . . . . . . . . . . .108
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Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .110
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .111
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .112
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Appendix A. MC68HCL05P1A
A.1
A.2
A.3
A.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .114
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Appendix B. MC68HSC05P1A
B.1
B.2
B.3
B.4
B.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .120
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
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12.1
12.2
12.3
12.4
12.5
12.6
12.7
N O N - D I S C L O S U R E
Section 12. Ordering Information
R E Q U I R E D
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Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
MC68HC05P1A Block Diagram . . . . . . . . . . . . . . . . . . . . . .17
Single-Chip Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Low Noise Single-Chip Pinout . . . . . . . . . . . . . . . . . . . . . . .19
Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Typical Frequency versus Resistance
for RC Oscillator Mask Option . . . . . . . . . . . . . . . . . . . . .22
2-1
2-2
2-3
Single-Chip Mode Memory Map . . . . . . . . . . . . . . . . . . . . . .26
I/O and Control Registers $0000–$000F . . . . . . . . . . . . . . .27
I/O and Control Registers $0000–$000F . . . . . . . . . . . . . . .28
3-1
3-2
CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4-1
4-2
Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .40
IRQ Function Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .41
5-1
5-2
Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
COP Watchdog Timer Location . . . . . . . . . . . . . . . . . . . . . .47
6-1
STOP/HALT/WAIT Flowchart . . . . . . . . . . . . . . . . . . . . . . . .53
7-1
7-2
7-3
7-4
Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Port C I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Port D I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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R E Q U I R E D
List of Figures
Figure
Title
Page
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
16-Bit Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer Registers (TMRH/TMRL) . . . . . . . . . . . . . . . . . . . . . .66
Alternate Counter Registers (ACRH/ACRL) . . . . . . . . . . . . .66
State Timing Diagram for Timer Overflow . . . . . . . . . . . . . .67
State Timing Diagram for Timer Reset . . . . . . . . . . . . . . . . .67
Output Compare Registers (OCRH/OCRL) . . . . . . . . . . . . .68
Output Compare Software Initialization Example . . . . . . . . .70
State Timing Diagram for Output Compare . . . . . . . . . . . . .70
Input Compare Registers (ICRH/ICRL) . . . . . . . . . . . . . . . .71
State Timing Diagram for Input Capture. . . . . . . . . . . . . . . .72
Timer Control Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .73
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . .74
10-1
PA0–PA7, PB5–PB7, PC2–PC5, PD5, and TCMP
Typical High-Side Driver Characteristics . . . . . . . . . . . .100
PA0–PA7, PC2–PC5, PB0–PB5, PD5, and TCMP
Typical Low-Side Driver Characteristics . . . . . . . . . . . .100
PC0–PC1 Typical High-Side Driver Characteristics . . . . . .101
PC0–PC1 Typical Low-Side Driver Characteristics . . . . . .101
Typical Operating IDD (25 °C). . . . . . . . . . . . . . . . . . . . . . .102
Typical Wait Mode IDD (25 °C) . . . . . . . . . . . . . . . . . . . . . .102
Power-On Reset and External Reset Timing Diagram . . . .105
10-2
10-3
10-4
10-5
10-6
10-7
A-1
A-2
Maximum Run Mode IDD versus
Internal Clock Frequency . . . . . . . . . . . . . . . . . . . . . . .116
Maximum Wait Mode IDD versus
Internal Clock Frequency . . . . . . . . . . . . . . . . . . . . . . .116
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Table Title
Page
4-1
Vector Addresses for Interrupts and Reset . . . . . . . . . . . . . .38
6-1
6-2
Operating Mode Conditions After Reset. . . . . . . . . . . . . . . . .49
COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .54
7-1
7-2
7-3
7-4
Port A I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port B I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port C I/O Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Port D I/O Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
9-1
9-2
9-3
9-4
9-5
9-6
9-7
Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .82
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .83
Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .85
Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .86
Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
12-1
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
A-1
A-2
A-3
A-4
Low-Power Output Voltage (VDD = 1.8–2.4 Vdc) . . . . . . . . .114
Low-Power Output Voltage (VDD = 2.5–3.6 Vdc) . . . . . . . . .114
Low-Power Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . .115
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
B-1
B-2
B-3
B-4
High-Speed Supply Current . . . . . . . . . . . . . . . . . . . . . . . . .120
High-Speed Control Timing (VDD = 5.0 Vdc ± 10%) . . . . . . .121
High-Speed Control Timing (VDD = 3.3 Vdc ± 10%) . . . . . . .121
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
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List of Tables
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R E Q U I R E D
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A G R E E M E N T
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List of Tables
General Release Specification
MC68HC05P1A — Rev. 3.0
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1.1 Contents
1.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.4
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.1
VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.5.2
OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5.2.1
Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.2
Ceramic Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.3
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.5.2.4
External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.6
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.1
PA0–PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.2
PB5, PB6, and PB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.3
PC0–PC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.4
PD5 and PD7/TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.6.5
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.6.6
IRQ (Maskable Interrupt Request) . . . . . . . . . . . . . . . . . . .24
1.2 Introduction
The Freescale MC68HC05P1A microcontroller unit (MCU) is pin
compatible with the MC68HC05P1 with port and interrupt
enhancements available. This device is available in a 28-pin dual in-line
package (DIP) or a small outline integrated circuit (SOIC) package. A
functional block diagram of the MC68HC05P1A is shown in Figure 1-1.
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Section 1. General Description
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1.3 Features
Features of the MC68HC05P1A include:
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General Description
•
Low-Cost, M68HC05 Core
•
28-Pin Dual In-Line Package (DIP) or Small Outline Integrated
Circuit (SOIC) Package
•
On-Chip Crystal/Ceramic Resonator or RC Oscillator (Mask
Option)
•
2320 Bytes of User Read-Only Memory (ROM) Including:
– 48 Bytes of Page-Zero ROM
– 16 Bytes of User Vectors
•
128 Bytes of On-Chip Random Access Memory (RAM)
•
16-Bit Timer with Output Compare and Input Capture
•
Edge/Level-Sensitive Interrupt or Edge-Sensitive Only (Mask
Option)
•
Computer Operating Properly (COP) Watchdog Timer
•
20 Bidirectional Input/Output (I/O) Lines and One Input-Only Line
Including:
– Individual Mask Selectable Pullups/Interrupts on Port A Pins
– High Current Sink and Source on Two I/O Pins (PC0 and PC1)
•
Single-Chip Mode
•
Power-Saving Stop and Wait Modes
•
Stop Conversion to Halt Mode (Mask Option)
NOTE:
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
NOTE:
Any reference to a voltage, current, or frequency specified in the
following sections will refer to the nominal values. The exact values and
their tolerance or limits are specified in Section 10. Electrical
Specifications.
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OSC
÷2
PH2
PC7 (15)
COP
(25) PD7/TCAP
(24)TCMP
÷4
16-BIT TIMER
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
PC6 (16)
PC5 (17)
PORT C
(26) OSC 2
DATA DIRECTION REGISTER
(27) OSC 1
PC4 (18)
PC3 (19)
PC2 (20)
**PC1 (21)
(23) PD5
**PC0 (22)
R E Q U I R E D
General Description
Features
ACCUM
CPU REGISTERS
INDEX REG
0 0 0 0 0 0 0 0 1 1 STK PNTR
PB5 (11)
PROGRAM COUNTER
1 1 1H I NZC
SRAM — 128 BYTES
USER ROM — 2320 BYTES
*PA6 (4)
*PA5 (5)
PORT A
COND CODE REG
*PA7 (3)
*PA4 (6)
*PA3 (7)
*PA2 (8)
*PA1 (9)
*PA0 (10)
POWER
TEST ROM — 32 BYTES
VDD (28)
VSS (14)
( ) — Pin Number
* — Pullup/Interrupt Selectable via Mask Option
** — High Current Source/Sink Capability
Figure 1-1. MC68HC05P1A Block Diagram
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(2) IRQ
PB6 (12)
N O N - D I S C L O S U R E
MC68HC05 CPU
PORT B
DATA DIRECTION REGISTER
(1) RESET
ALU
DATA DIRECTION REGISTER
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PB7 (13)
CPU CONTROL
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R E Q U I R E D
General Description
1.4 Mask Options
The MC68HC05P1A has 12 mask options. The default state of these
mask options and their alternate states are:
1. IRQ is Edge- and Level-Sensitive — Option for Edge-Sensitive
Only
2. Crystal/Ceramic Resonator Oscillator Mode — Option for
Resistor/Capacitor (RC) Mode
3. COP Watchdog Timer Enabled — Option to Disable
4. Stop Instruction Enabled — Option to Convert to Halt
5. Eight (8) Port A Pullups/Interrupts Disabled — Option to
Individually Enable
1.5 Functional Pin Description
The following paragraphs describe the functionality of each pin on the
MC68HC05P1A package. The device also is available with an alternate
pinout where VDD and VSS are adjacent to reduce radio frequency (RF)
emissions. This also improves the ability to decouple VDD and VSS,
which may provide some benefit for conducted RF emissions as well.
The pinouts are shown in Figure 1-2 and Figure 1-3. They are
compatible with the MC68HC05P1 microcontroller unit (MCU).
1.5.1 VDD and VSS
Power is supplied to the MCU through VDD and VSS. VDD is connected
to a regulated +5 volt supply and VSS is connected to ground.
Very fast signal transitions occur on the MCU pins. The short rise and
fall times place very high short-duration current demands on the power
supply. To prevent noise problems, take special care to provide good
power supply bypassing at the MCU. Use bypass capacitors with good
high-frequency characteristics, and position them as close to the MCU
as possible. Bypassing requirements vary, depending on how heavily
the MCU pins are loaded.
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28
VDD
2
27
OSC1
PA7
3
26
OSC2
PA6
4
25
PD7/TCAP
PA5
5
24
TCMP
PA4
6
23
PD5
PA3
7
22
PC0
PA2
8
21
PC1
PA1
9
20
PC2
PA0
10
19
PC3
PB5
11
18
PC4
PB6
12
17
PC5
PB7
13
16
PC6
VSS
14
15
PC7
Figure 1-2. Single-Chip Pinout
RESET
1
28
IRQ
2
27
VDD
PA7
3
26
OSC1
PA6
4
25
OSC2
PA5
5
24
PD7/TCAP
PA4
6
23
TCMP
PA3
7
22
PD5
PA2
8
21
PC0
PA1
9
20
PC1
PA0
10
19
PC2
PB5
11
18
PC3
PB6
12
17
PC4
PB7
13
16
PC5
PC7
14
15
PC6
VSS
Figure 1-3. Low Noise Single-Chip Pinout
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R E Q U I R E D
1
IRQ
A G R E E M E N T
RESET
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General Description
Functional Pin Description
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R E Q U I R E D
General Description
1.5.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the control connections for the on-chip
oscillator. The OSC1 and OSC2 pins can accept:
1. A crystal, as shown in Figure 1-4 (a).
2. A ceramic resonator, as shown in Figure 1-4 (a).
3. An external resistor, as shown in Figure 1-4 (b).
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A G R E E M E N T
4. An external clock signal, as shown in Figure 1-4 (c).
TO VDD OR STOP
OSC1
MCU
OSC2
4.7 MΩ
N O N - D I S C L O S U R E
27 pF
27 pF
(a) Crystal or Ceramic
Resonator Connections
TO VDD OR STOP
OSC1
MCU
OSC2
TO VDD OR STOP
OSC1
MCU
OSC2
R
UNCONNECTED
EXTERNAL CLOCK
(b) RC Oscillator
Connections
(c) External Clock Source
Connections
Figure 1-4. Oscillator Connections
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1.5.2.1 Crystal
The circuit in Figure 1-4 (a) shows a typical oscillator circuit for an ATcut, parallel resonant crystal. Follow the crystal manufacturer’s
recommendations, as the crystal parameters determine the external
component values required to provide maximum stability and reliable
startup. The load capacitance values used in the oscillator circuit design
should include all stray capacitances. Mount the crystal and components
as closely as possible to the pins for startup stabilization and to minimize
output distortion.
1.5.2.2 Ceramic Resonator
In cost-sensitive applications, use a ceramic resonator in place of a
crystal. Use the circuit in Figure 1-4 (a) for a ceramic resonator and
follow the resonator manufacturer’s recommendations, as the resonator
parameters determine the external component values required for
maximum stability and reliable starting. The load capacitance values
used in the oscillator circuit design should include all stray capacitances.
Mount the resonator and components as closely as possible to the pins
for startup stabilization and to minimize output distortion.
1.5.2.3 RC Oscillator
The lowest cost oscillator uses the RC mask option and an external
resistor. With this option, a resistor is connected to the oscillator pins, as
shown in Figure 1-4 (b). The relationship between R and fop is shown in
Figure 1-5. Consult the factory for tolerance limits and design
specifications.
1.5.2.4 External Clock
An external clock from another CMOS-compatible device can be
connected to the OSC1 input, with the OSC2 input not connected, as
shown in Figure 1-4 (c).
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The frequency, fosc, of the oscillator or external clock source is divided
by two to produce the internal PH2 bus clock operating frequency, fop.
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Functional Pin Description
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A G R E E M E N T
Figure 1-5. Typical Frequency versus Resistance for RC Oscillator Mask Option
R E Q U I R E D
General Description
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Driving this input low will reset the MCU to a known startup state. The
RESET pin contains an internal Schmitt trigger to improve its noise
immunity. Refer to Section 5. Resets.
These eight I/O pins comprise port A. The state of any pin is software
programmable, and all port A lines are configured as inputs during
power-on or reset. Eight individual mask options can be chosen to
enable pullups and interrupts (active low) on each port A pin. Refer to
Section 4. Interrupts and Section 7. Input/Output Ports.
1.6.2 PB5, PB6, and PB7
These three I/O pins comprise port B. The state of any pin is software
programmable and all port B lines are configured as inputs during
power-on or reset. Refer to Section 7. Input/Output Ports.
1.6.3 PC0–PC7
These eight I/O pins comprise port C. The state of any pin is software
programmable and all port C lines are configured as inputs during
power-on or reset. PC0 and PC1 are capable of sourcing and sinking
more current than a typical I/O pin. Refer to Section 7. Input/Output
Ports and Section 10. Electrical Specifications.
1.6.4 PD5 and PD7/TCAP
These two pins comprise port D and are shared with the 16-bit timer
subsystem. The state of PD5 is software programmable and is
configured as an input during power-on or reset. PD7 is always an input.
It may be read at any time, regardless of the mode of operation of the
16-bit timer. Refer to Section 7. Input/Output Ports and Section 8. 16Bit Timer.
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1.6.1 PA0–PA7
A G R E E M E N T
1.6 RESET
R E Q U I R E D
General Description
RESET
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1.6.5 TCMP
This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. Refer to Section 8. 16-Bit Timer.
1.6.6 IRQ (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU.
The MCU will complete the current instruction being executed before it
responds to the IRQ interrupt request. When IRQ is driven low, the event
is latched internally to signify an interrupt has been requested. When the
MCU completes its current instruction, the interrupt latch is tested. If the
interrupt latch is set and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU will begin the interrupt sequence.
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General Description
Depending on the mask option selected, the IRQ pin will trigger this
interrupt on either a negative going edge at the IRQ pin and/or while the
IRQ pin is held in the low state. In either case, the IRQ pin must be held
low for at least one tILIH time period. The IRQ input requires an external
resistor connected to VDD for wired-OR operation. If the IRQ pin is not
used, it must be tied to the VDD supply. The IRQ pin contains an internal
Schmitt trigger as part of its input circuitry to improve noise immunity.
Refer to Section 4. Interrupts.
NOTE:
Each of the port A I/O pins may be connected as an OR function with the
IRQ interrupt function by a mask option. This capability allows keyboard
scan applications where the transitions or levels on the I/O pins will
behave the same as the IRQ pin. The edge or level sensitivity selected
by a separate mask option for the IRQ pin also applies to the I/O pins
OR’ed to create the IRQ signal.
NOTE:
If the voltage level applied to the IRQ pin exceeds 1.5 VDD, it may affect
the MCU’s mode of operation. See Section 6. Operating Modes.
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2.1 Introduction
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3
Single-Chip Mode Memory Map . . . . . . . . . . . . . . . . . . . . . . . .25
2.4
Input/Output (I/O) and Control Registers . . . . . . . . . . . . . . . . .25
2.5
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .30
2.6
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2.2 Introduction
The MC68HC05P1A utilizes 13 address lines to access an internal
memory space covering 8 Kbytes. This memory space is divided into
I/O, RAM, and ROM areas.
2.3 Single-Chip Mode Memory Map
When the MC68HC05P1A is in the single-chip mode, the 32 bytes of I/O,
128 bytes of RAM, 2256 bytes of user ROM, 48 bytes of user page zero
ROM, 32 bytes of test ROM, and 16 bytes of user vectors ROM are all
active, as shown in Figure 2-1.
2.4 Input/Output (I/O) and Control Registers
Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers
at locations $0000–$001F. Reading unimplemented bits will return
unknown states, and writing unimplemented bits will be ignored.
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Section 2. Memory
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A G R E E M E N T
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Memory
$0000
$001F
$0020
$004F
$0050
$007F
$0080
$00BF
$00C0
$00FF
$0100
$0000
0000
I/O
32 BYTES
0031
0032
USER ROM
48 BYTES
0079
0080
UNUSED
48 BYTES
I/O REGISTERS
SEE FIGURE 2-2
AND FIGURE 2-3
0127
0128
INTERNAL RAM
128 BYTES
STACK
64 BYTES
$001F
0191
0192
0255
0256
USER ROM
2048 BYTES
2303
2304
$08FF
$0900
UNUSED
5632 BYTES
7935
7936
$1EFF
$1F00
COP CONTROL
REGISTER
$1FF0
8143
8144
RESERVED
$1FF1
RESERVED
$1FF2
8175
8176
RESERVED
$1FF3
RESERVED
$1FF4
8191
RESERVED
$1FF5
RESERVED
$1FF6
USER ROM
208 BYTES
$1FCF
$1FD0
$1FEF
$1FF0
$1FFF
TEST ROM
32 BYTES
USER VECTORS ROM
16 BYTES
RESERVED
$1FF7
TIMER VECTOR (HIGH BYTE)
$1FF8
TIMER VECTOR (LOW BYTE)
$1FF9
IRQ VECTOR (HIGH BYTE)
$1FFA
IRQ VECTOR (LOW BYTE)
$1FFB
SWI VECTOR (HIGH BYTE)
$1FFC
SWI VECTOR (LOW BYTE)
$1FFD
RESET VECTOR (HIGH BYTE)
$1FFE
RESET VECTOR (LOW BYTE)
$1FFF
Figure 2-1. Single-Chip Mode Memory Map
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Bit 7
6
5
4
3
2
1
Bit 0
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
0
0
0
0
0
PB7
PB6
PB5
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
0
1
0
0
0
0
Read:
$0000
Port A Data (PORTA)
Write:
Read:
$0001
Port B Data (PORTB)
Write:
Read:
$0002
Port C Data (PORTC)
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Write:
Read:
$0003
Port D Data (PORTD)
PD5
Write:
Read:
$0004
Port A Data Direction (DDRA)
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Read:
$0005
Port B Data Direction (DDRB)
1
1
1
1
1
U
U
U
U
U
DDRB7 DDRB6 DDRB5
Write:
Read:
$0006
Port C Data Direction (DDRC)
DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Write:
Read:
$0007
Port D Data Direction (DDRD)
0
0
0
0
0
0
0
DDRD5
Write:
Read:
$0008
Unimplemented
Write:
Read:
$0009
Unimplemented
Write:
Read:
$000A
Unimplemented
Write:
Read:
$000B
Unimplemented
Write:
Read:
$000C
Unimplemented
Write:
= Unimplemented
Figure 2-2. I/O and Control Registers $0000–$000F
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A G R E E M E N T
Register Name
N O N - D I S C L O S U R E
Addr.
R E Q U I R E D
Memory
Input/Output (I/O) and Control Registers
Freescale Semiconductor, Inc.
R E Q U I R E D
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
1
Bit 0
IEDG
OLVL
Read:
$000D
Unimplemented
Write:
Read:
$000E
Unimplemented
Write:
Read:
$000F
Unimplemented
N O N - D I S C L O S U R E
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A G R E E M E N T
Write:
= Unimplemented
Figure 2-2. I/O and Control Registers $0000–$000F (Continued)
Addr.
Register Name
Bit 7
6
5
4
3
2
ICIE
OCIE
TOIE
0
0
0
ICF
OCF
TOF
0
0
0
0
0
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Read:
$010D
Unimplemented
Write:
Read:
$0011
Unimplemented
Write:
Read:
$0012
Timer Control Register (TCR)
Write:
Read:
$0013
Timer Status Register (TSR)
Write:
Read: ICRH7
$0014
Input Capture MSB (ICRH)
Write:
Read: ICRL7
$0015
Input Capture LSB (ICRL)
Write:
Read: OCRH7 OCRH6 OCRH5 OCRH4 OCRH3 OCRH2 OCRH1 OCRH0
$0016
Output Compare MSB (OCRH)
Write:
= Unimplemented
R
= Reserved
Figure 2-3. I/O and Control Registers $010D–$001F
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Addr.
Register Name
$0017
Output Compare MSB (OCRL)
Bit 7
6
5
4
3
2
1
Bit 0
Read: OCRL7 OCRL6 OCRL5 OCRL4 OCRL3 OCRL2 OCRL1 OCRL0
Write:
Read: TMRH7 TMRH6 TMRH5 TMRH4 TMRH3 TMRH2 TMRH1 TMRH0
$0018
Timer MSB (TIMRH)
Write:
Read: TMRL7 TMRL6 TMRL5 TMRL4 TMRL3 TMRL2 TMRL1 TMRL0
$0019
Timer LSB (TMRL)
Alternate Counter MSB (ACRH)
Write:
Read: ACRL7 ACRL6 ACRL5 ACRL4 ACRL3 ACRL2 ACRL1 ACRL0
$001B
Alternate Counter LSB (ACRL)
Write:
Read:
$001C
Unimplemented
Write:
Read:
$001D
Unimplemented
Write:
Read:
$001E
Unimplemented
Write:
Read:
$001F
Reserved
R
R
R
R
R
R
R
R
Write:
= Unimplemented
R
= Reserved
Figure 2-3. I/O and Control Registers $010D–$001F (Continued)
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A G R E E M E N T
Read: ACRH7 ACRH6 ACRH5 ACRH4 ACRH3 ACRH2 ACRH1 ACRH0
$001A
N O N - D I S C L O S U R E
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Write:
R E Q U I R E D
Memory
Input/Output (I/O) and Control Registers
Freescale Semiconductor, Inc.
2.5 Random-Access Memory (RAM)
The user RAM consists of 128 bytes (including the stack) at locations
$0080–$00FF. The stack begins at address $00FF. The stack pointer
can access 64 bytes of RAM from $00FF to $00C0.
NOTE:
Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
2.6 Read-Only Memory (ROM)
There are 2256 bytes of user ROM at locations $0100–$08FF and
$1F00–$1FCF, with 48 bytes in user page zero locations $0020–$004F,
and 16 additional bytes for user vectors at locations $1FF0–$1FFF. The
test ROM and test ROM vectors are at locations $1FD0–$1FEF.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Memory
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Section 3. CPU Core
3.1 Contents
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.3.1
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.2
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.3
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.3.4
Program Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.3.5
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.2 Introduction
This section describes the registers of the M68HC05 central processor
unit (CPU). The stop and wait modes, initiated by software instructions,
are also described here.
3.3 CPU Registers
The CPU contains the following registers:
•
Accumulator (A)
•
Index register (X)
•
Stack pointer (SP)
•
Program counter (PC)
•
Condition code register (CCR)
These registers are hard-wired within the CPU and are not part of the
memory map. Figure 3-1 is a block diagram of the M68HC05 CPU.
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
N O N - D I S C L O S U R E
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3.2
R E Q U I R E D
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R E Q U I R E D
CPU Core
CPU
CONTROL
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
INDEX REGISTER
A G R E E M E N T
0
0
0
0
0
0
0
0
1
1
STACK POINTER
PROGRAM COUNTER
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
Figure 3-1. CPU Block Diagram
Figure 3-2 shows the five CPU registers.
12
0
N O N - D I S C L O S U R E
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ARITHMETIC
LOGIC UNIT
(ALU)
15
0
7
ACCUMULATOR
0
A
7
INDEX REGISTER
0
X
7
0
0
0
0
1
5
1
0
12
0
0
SP
STACK POINTER
0
PC
PROGRAM COUNTER
7
CONDITION CODE REGISTER
1
1
1
4
3
2
1
0
H
I
N
Z
C
CCR
CARRY/BORROW BIT
ZERO BIT
NEGATIVE BIT
INTERRUPT MASK
HALF-CARRY BIT
Figure 3-2. Programming Model
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3.3.1 Accumulator
The accumulator (A) is a general-purpose 8-bit register used to hold
operands and results of arithmetic calculations or data manipulations.
7
0
A
R E Q U I R E D
CPU Core
CPU Registers
In indexed addressing with no offset, the index register contains the low
byte of the operand address, and the high byte is assumed to be $00. In
indexed addressing with an 8-bit offset, the CPU finds the operand
address by adding the index register contents to an 8-bit immediate
value. In indexed addressing with a 16-bit offset, the CPU finds the
operand address by adding the index register contents to a 16-bit
immediate value.
7
A G R E E M E N T
The index register (X) is an 8-bit register used for the indexed
addressing value to create an effective address. The index register also
may be used as a temporary storage area.
0
X
3.3.3 Stack Pointer
The stack pointer (SP) contains the address of the next free location on
the stack. During an MCU reset or the reset stack pointer (RSP)
instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented
as data is pulled from the stack.
When accessing memory, the eight most significant bits (MSB) are
permanently set to 00000011. These eight bits are appended to the six
least significant bits (LSB) to produce an address within the range of
$00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal)
locations. If 64 locations are exceeded, the stack pointer wraps around
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3.3.2 Index Register
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N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
CPU Core
and loses the previously stored information. A subroutine call occupies
two locations on the stack; an interrupt uses five locations.
12
0
7
0
0
0
0
50
1
1
SP
3.3.4 Program Counter
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched. Because addresses are often 16-bit
values, the program counter may be thought of as having three
additional upper bits that are always zeros.
15
0
12
0
0
0
PC
Normally, the address in the program counter increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
3.3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which the H, N,
Z, and C bits are used to indicate the results of the instruction just
executed, and the I bit is used to enable or disable interrupts. These bits
can be individually tested by a program, and specific actions can be
taken as a result of their state. Consider the condition code register as
having three additional upper bits that are always ones.
7
1
1
1
4
3
2
1
0
H
I
N
Z
C
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
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I — Interrupt
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the I bit is cleared.
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
R E Q U I R E D
CPU Core
CPU Registers
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was zero.
C — Carry/Borrow
N O N - D I S C L O S U R E
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit is also affected during bit test and branch instructions and during
shifts and rotates.
A G R E E M E N T
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Z — Zero
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A G R E E M E N T
R E Q U I R E D
CPU Core
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4.1 Contents
4.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.3
Reset Interrupt Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.4
Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5.1
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.5.2
Optional External Interrupts (PA0–PA7) . . . . . . . . . . . . . . .42
4.5.3
Input Capture Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.5.4
Output Compare Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.5.5
Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.2 Introduction
The MCU can be interrupted by:
1. Non-maskable Software Interrupt Instruction (SWI)
2. External Asynchronous Interrupt (IRQ)
3. Optional External Asynchronous Interrupt on Each Port A Pin
(IRQ, Enabled by Pullup Mask Option)
4. Input Capture Interrupt (TIMER)
5. Output Compare Interrupt (TIMER)
6. Timer Overflow Interrupt (TIMER)
Interrupts cause the processor to save the register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike
RESET, hardware interrupts do not cause the current instruction
execution to be halted, but are considered pending until the current
instruction is completed.
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A G R E E M E N T
Section 4. Interrupts
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
Interrupts
When the current instruction is completed, the processor checks all
pending hardware interrupts. If interrupts are not masked by the I bit
being clear in the condition code register (CCR) and the corresponding
interrupt enable bit being set, the processor proceeds with interrupt
processing. Otherwise, the next instruction is fetched and executed. The
SWI is executed the same as any other instruction, regardless of the
state of the I bit.
When an interrupt is processed, the CPU puts the register contents on
the stack, sets the I bit in the CCR, and fetches the address of the
corresponding interrupt service routine from the vector table at locations
$1FF0–$1FFF. If more than one interrupt is pending when the interrupt
vector is fetched, the interrupt with the highest vector location, shown in
Table 4-1, will be serviced first.
An RTI instruction is used to signify when the interrupt software service
routine is completed. The RTI instruction causes the CPU state to be
recovered from the stack and normal processing to resume at the next
instruction that was executed when the interrupt took place. Figure 4-1
shows the event sequence that occurs during interrupt processing.
Table 4-1. Vector Addresses for Interrupts and Reset
Register
Flag
Name
Enable
Bit
Interrupt
CPU
Interrupt
Vector
Address
N/A
N/A
N/A
Reset
RESET
$1FFE–$1FFF
N/A
N/A
N/A
Software
SWI
$1FFC–$1FFD
N/A
N/A
N/A
External Interrupt
IRQ
$1FFA–$1FFB
TSR
ICF
ICIE
Timer Input
Capture
TIMER
$1FF8–$1FF9
TSR
OCF
OCIE
Timer Output
Compare
TIMER
$1FF8–$1FF9
TSR
TOF
TOIE
Timer Overflow
TIMER
$1FF8–$1FF9
N/A
N/A
N/A
Unimplemented
N/A
$1FF6-$1FF7
N/A
N/A
N/A
Unimplemented
N/A
$1FF4-$1FF5
N/A
N/A
N/A
Unimplemented
N/A
$1FF2-$1FF3
N/A
N/A
N/A
Unimplemented
N/A
$1FF0-$1FF1
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4.4 Software Interrupt (SWI)
The SWI is an executable instruction. It is also a non-maskable interrupt
since it is executed regardless of the state of the I bit in the CCR. As with
any instruction, interrupts pending during the previous instruction will be
serviced before the SWI opcode is fetched. The interrupt service routine
address for the SWI instruction is specified by the contents of memory
locations $1FFC and $1FFD.
4.5 Hardware Interrupts
All hardware interrupts are maskable by the I bit in the CCR. If the I bit
is set, all hardware interrupts (internal and external) are disabled.
Clearing the I bit enables the hardware interrupts. The hardware
interrupts are explained in the following sections.
4.5.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flops or the level on the IRQ pin is
low, a request is synchronized to the CPU to generate the IRQ interrupt.
If the edge-sensitive only mask option is selected, the output of the
internal edge detector flip-flop is sampled and the input level on the IRQ
pin is ignored. The interrupt service routine address is specified by the
contents of memory locations $1FFA and $1FFB. A block diagram of the
IRQ function is shown in Figure 4-2.
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The reset function is not in the strictest sense an interrupt; however, it is
acted upon in a similar manner, as shown in Figure 4-1. A low level input
on the RESET pin or internally generated RST signal causes the
program to vector to its starting address, which is specified by the
contents of memory locations $1FFE and $1FFF. The I bit in the
condition code register is also set. The MCU is configured to a known
state during a reset, as described in Section 5. Resets.
N O N - D I S C L O S U R E
4.3 Reset Interrupt Sequence
R E Q U I R E D
Interrupts
Reset Interrupt Sequence
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R E Q U I R E D
Interrupts
FROM RESET
Y
IS I BIT
SET?
N
IRQ
INTERRUPT?
Y
CLEAR IRQ
REQUEST
LATCH
N
N O N - D I S C L O S U R E
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A G R E E M E N T
TIMER
INTERRUPT?
Y
N
STACK
PC, X, A, CC
SET
I BIT IN CCR
LOAD PC FROM:
SWI: $1FFC, $1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
Y
N
RTI
INSTRUCTION?
Y
RESTORE REGISTERS
FROM STACK
CC, A, X, PC
N
EXECUTE
INSTRUCTION
Figure 4-1. Interrupt Processing Flowchart
NOTE:
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $1FFA is read). Therefore, another
external interrupt pulse can be latched during the IRQ service routine.
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PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
VDD
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IRQ
LATCH
PA7
DDRA7
PA7 IRQ INHIBIT
(MASK OPTION)
R
TO IRQ
PROCESSING
IN CPU
RST
IRQ VECTOR FETCH
MASK OPTION
(IRQ LEVEL)
Figure 4-2. IRQ Function Block Diagram
NOTE:
When the edge- and level-sensitive mask option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed to avoid the
processor re-entering the IRQ service routine.
The IRQ pin is one source of an IRQ interrupt, and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
Any enabled IRQ interrupt source sets the IRQ latch on the falling edge
of the IRQ pin or a port A pin if port A interrupts have been enabled. If
edge-only sensitivity is chosen by a mask option, only the IRQ latch
output can activate a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
1. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level.
2. Falling edge on any enabled port A interrupt pin with all other
enabled port A interrupt pins and the IRQ pin at a high level.
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A G R E E M E N T
TO BIH & BIL
INSTRUCTION
SENSING
N O N - D I S C L O S U R E
IRQ PIN
R E Q U I R E D
Interrupts
Hardware Interrupts
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A G R E E M E N T
R E Q U I R E D
Interrupts
If level sensitivity is chosen, the active high state of the IRQ input can
also activate an IRQ request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin with all enabled port A interrupt pins
at a high level.
3. Low level on any enabled port A interrupt pin.
4. Falling edge on any enabled port A interrupt pin with all enabled
port A interrupt pins on the IRQ pin at a high level.
This interrupt is serviced by the interrupt service routine located at the
address specified by the contents of $1FFA and $1FFB. The IRQ latch
is automatically cleared by entering the interrupt service routine.
4.5.2 Optional External Interrupts (PA0–PA7)
The IRQ interrupt can be triggered by the inputs on the PA0–PA7 port
pins if enabled by individual mask options. With pullup enabled, each
port A pin can activate the IRQ interrupt function and the interrupt
operation will be the same as for inputs to the IRQ pin. Once enabled by
mask option, each individual port A pin can be disabled as an interrupt
source if its corresponding DDR bit is configured for output mode.
NOTE:
The BIH and BIL instructions apply to the output of the logic OR function
of the enabled PA0–PA7 interrupt pins and the IRQ pin. The BIH and BIL
instructions do not exclusively test the state of the IRQ pin.
NOTE:
If enabled, the PA0–PA7 pins will cause an IRQ interrupt only if these
individual pins are configured as inputs.
4.5.3 Input Capture Interrupt
The input capture interrupt is generated by the 16-bit timer as described
in Section 8. 16-Bit Timer. The input capture interrupt flag is located in
register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear for the input capture interrupt to
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The output compare interrupt is generated by the 16-bit timer as
described in Section 8. 16-Bit Timer. The output compare interrupt flag
is located in register TSR and its corresponding enable bit can be found
in register TCR. The I bit in the CCR must be clear for the output
compare interrupt to be enabled. The interrupt service routine address
is specified by the contents of memory locations $1FF8 and $1FF9.
4.5.5 Timer Overflow Interrupt
The timer overflow interrupt is generated by the 16-bit timer as described
in Section 8. 16-Bit Timer. The timer overflow interrupt flag is located in
register TSR and its corresponding enable bit can be found in register
TCR. The I bit in the CCR must be clear for the timer overflow interrupt
to be enabled. This internal interrupt will vector to the interrupt service
routine located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
N O N - D I S C L O S U R E
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4.5.4 Output Compare Interrupt
A G R E E M E N T
be enabled. The interrupt service routine address is specified by the
contents of memory locations $1FF8 and $1FF9.
R E Q U I R E D
Interrupts
Hardware Interrupts
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R E Q U I R E D
Interrupts
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5.1 Contents
5.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.3
External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4
Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.1
Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.4.2
Computer Operating Properly (COP) Reset . . . . . . . . . . . .46
5.2 Introduction
The MCU can be reset from three sources: one external input and two
internal reset conditions. The RESET pin is an input with a Schmitt
trigger, as shown in Figure 5-1. The CPU and all peripheral modules will
be reset by the RST signal, which is the logical OR of internal reset
functions and is clocked by PH2.
RESET
VDD
OSC
DATA
ADDRESS
POWER-ON
RESET
(POR)
COP
WATCHDOG
(COPR)
RESET
LATCH
RST
TO CPU AND
PERIPHERALS
PH2
Figure 5-1. Reset Block Diagram
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Section 5. Resets
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A G R E E M E N T
R E Q U I R E D
Resets
5.3 External Reset (RESET)
The reset input is the only external reset and is connected to an internal
Schmitt trigger. The external reset occurs whenever the reset input is
driven below the lower threshold and remains in reset until the RESET
pin rises above the upper threshold. The upper and lower thresholds are
given in Section 10. Electrical Specifications.
5.4 Internal Resets
The two internally generated resets are the initial power-on reset (POR)
function and the COP watchdog timer function.
5.4.1 Power-On Reset (POR)
The internal POR is generated at power-up to allow the clock oscillator
to stabilize. The POR is strictly for power turn-on conditions and should
not be used to detect a drop in the power supply voltage. There is a 4064
PH2 clock cycle oscillator stabilization delay after the oscillator becomes
active.
5.4.2 Computer Operating Properly (COP) Reset
When the COP watchdog timer is enabled (by mask option), the internal
COP reset is generated automatically by a timeout of the COP watchdog
timer. This timer is implemented with an 18-stage ripple counter that
provides a timeout period of 65.5 ms when a 4-MHz oscillator is used.
The COP watchdog counter is cleared by writing a logic 0 to bit zero at
location $1FF0.
The COP watchdog timer can be disabled by mask option or by applying
2 × VDD to the IRQ pin. When the IRQ pin is returned to its normal
operating voltage range (between VSS and VDD), the COP watchdog
timer output will be restored if the COP mask option is enabled.
The COP register is shared with the most significant bit (MSB) of an
unimplemented user interrupt vector as shown in Figure 5-2. Reading
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this location returns the MSB of the unimplemented user interrupt vector.
Writing a logic 0 to this location clears the COP watchdog timer.
$1FF0
Register Name
Unimplemented Vector
and COP Watchdog Timer
Bit 7
6
5
4
3
2
1
R
R
R
R
R
R
R
Read:
R
Write:
COPC
R
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Bit 0
= Reserved
N O N - D I S C L O S U R E
Figure 5-2. COP Watchdog Timer Location
A G R E E M E N T
Addr.
R E Q U I R E D
Resets
Internal Resets
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A G R E E M E N T
R E Q U I R E D
Resets
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6.1 Contents
6.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.3
Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1
STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.4.1.1
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.1.2
Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.4.2
WAIT Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.5
COP Watchdog Timer Considerations . . . . . . . . . . . . . . . . . . .54
6.2 Introduction
The MC68HC05P1A uses single-chip mode. The conditions required to
enter this mode are shown in Table 6-1. The mode of operation is
determined by the voltages on the IRQ and PD7/TCAP pins on the rising
edge of the external RESET pin.
Table 6-1. Operating Mode Conditions After Reset
RESET Pin
IRQ Pin
PD7/TCAP
Mode
VSS to VDD
VSS to VDD
Single-Chip
VTST = 2 x VDD
The mode of operation is also determined whenever the internal COP
watchdog timer resets the MCU. When the COP timer expires, the
voltage applied to the IRQ pin affects the mode of operation, while the
voltage applied to PD7/TCAP is ignored if the voltage at the IRQ pin
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Section 6. Operating Modes
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A G R E E M E N T
R E Q U I R E D
Operating Modes
exceeds VTST. In this case, the voltage applied to PD7/TCAP during the
last rising edge on RESET is stored in a latch and used to determine the
mode of operation when the COP watchdog timer resets the MCU.
6.3 Single-Chip Mode
The single-chip mode allows the MCU to function as a self-contained
microcontroller with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU and is not
available externally. Single-chip mode is entered on the rising edge of
RESET if the IRQ pin is within the normal operating voltage range. The
pinout for the single-chip mode is shown in Figure 1-2 . Single-Chip
Pinout.
In the single-chip mode, two 8-bit I/O ports, one 3-bit I/O port, and a
1-bit I/O port are shared with the 16-bit timer subsystem. The 16-bit timer
subsystem also has one input-only pin and one output-only pin.
6.4 Low-Power Modes
The MC68HC05P1A is capable of running in a low-power mode in each
of its configurations. The WAIT and STOP instructions provide two
modes that reduce the power required for the MCU by stopping various
internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP watchdog timer is enabled.
The stop conversion mask option is used to modify the behavior of the
STOP instruction from stop mode to halt mode. The flow of the stop, halt,
and wait modes is shown in Figure 6-1.
6.5 STOP Instruction
The STOP instruction can result in one of two modes of operation,
depending on the stop conversion mask option. If the stop conversion is
not chosen, the STOP instruction will behave like a normal STOP
instruction in the M68HC05 Family and place the MCU in the stop mode.
If the stop conversion is chosen, the STOP instruction will behave like a
WAIT instruction (with the exception of a variable delay at startup) and
place the MCU in halt mode.
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The MCU can be brought out of stop mode only by an external interrupt
or an externally generated reset. When exiting the stop mode, the
internal oscillator will resume after a 4064 PH2 clock cycle oscillator
stabilization delay.
NOTE:
Execution of the STOP instruction without conversion to halt (via mask
option) will cause the oscillator to stop, and therefore disable the COP
watchdog timer. If the COP watchdog timer is used, the stop mode
should be changed to halt mode by selecting the appropriate mask
option.
6.5.0.2 Halt Mode
Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode. (Both halt and wait modes consume more power
than stop mode.)
In halt mode, the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, the processor will exit halt mode
and resume normal operation. Halt mode also can be exited when an
external interrupt or external reset occurs. When exiting the halt mode,
the PH2 clock will resume after a delay of one to 4064 PH2 clock cycles.
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Execution of the STOP instruction without conversion to halt places the
MCU in its lowest-power consumption mode. In stop mode, the internal
oscillator is turned off, halting all internal processing, including the COP
watchdog timer. Execution of the STOP instruction automatically clears
the I bit in the condition code register so that the external interrupt is
enabled. All other registers and memory remain unaltered. All
input/output lines remain unchanged.
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6.5.0.1 Stop Mode
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STOP Instruction
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Operating Modes
This varied delay time is the result of the halt mode exit circuitry testing
the oscillator stabilization delay timer (a feature of stop mode), which has
been free-running (a feature of wait mode).
NOTE:
Halt mode is not intended for normal use. This feature is provided to
keep the COP watchdog timer active in the event a STOP instruction is
inadvertently executed.
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A G R E E M E N T
6.5.1 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode, which
consumes more power than stop mode. In wait mode, the PH2 clock is
halted, suspending all processor and internal bus activity. Internal timer
clocks remain active, permitting interrupts to be generated from the 16bit timer and reset to be generated from the COP watchdog timer.
Execution of the WAIT instruction automatically clears the I bit in the
condition code register, enabling the external interrupt. All other
registers, memory, and input/output lines remain in their previous state.
If the 16-bit timer interrupt is enabled, it will cause the processor to exit
wait mode and resume normal operation. The 16-bit timer may be used
to generate a periodic exit from the wait mode. Wait mode may also be
exited when an external interrupt or reset occurs.
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EXTERNAL OSCILLATOR ACTIVE
AND
INTERNAL TIMER CLOCK ACTIVE
Y
N
STOP EXTERNAL OSCILLATOR,
STOP INTERNAL TIMER CLOCK,
RESET STARTUP DELAY
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EXTERNAL OSCILLATOR
ACTIVE AND
INTERNAL TIMER
CLOCK ACTIVE
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I-BIT IN CCR
STOP INTERNAL PROCESSOR
CLOCK,
CLEAR I-BIT IN CCR
Y
STOP INTERNAL
PROCESSOR CLOCK,
CLEAR I-BIT IN CCR
EXTERNAL
RESET?
N
EXTERNAL
RESET?
Y
Y
Y
EXTERNAL
INTERRUPT?
N
EXTERNAL
INTERRUPT?
N
N
N
Y
Y
TIMER
INTERNAL
INTERRUPT?
RESTART EXTERNAL OSCILLATOR,
RESTART STABILIZATION DELAY
Y
END OF
STABILIZATION
DELAY?
Y
2.
Y
TIMER
INTERNAL
INTERRUPT?
N
Y
RESTART INTERNAL
PROCESSOR CLOCK
EXTERNAL
INTERRUPT?
N
N
N
1.
Y
N
COP
INTERNAL
RESET?
EXTERNAL
RESET?
COP
INTERNAL
RESET?
N
FETCH RESET VECTOR
OR
SERVICE INTERRUPT
a. STACK
b. SET I BIT
c. VECTOR TO INTERRUPT ROUTINE
Figure 6-1. STOP/HALT/WAIT Flowchart
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STOP
TO HALT MASK
OPTION?
WAIT
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HALT
STOP
R E Q U I R E D
Operating Modes
STOP Instruction
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6.6 COP Watchdog Timer Considerations
The COP watchdog timer is active in single-chip mode of operation when
selected by mask option. Executing the STOP instruction without
conversion to halt (via mask option) will cause the COP to be disabled.
Therefore, it is recommended that the STOP instruction be modified to
produce halt mode (via mask option) if the COP watchdog timer will be
enabled.
Furthermore, it is recommended that the COP watchdog timer be
disabled for applications that will use the halt or wait modes for time
periods that will exceed the COP timeout period.
COP watchdog timer interactions are summarized in Table 6-2.
Table 6-2. COP Watchdog Timer Recommendations
IF the Following Condition Exists:
STOP Instruction Modes
Wait Period
THEN the COP Watchdog
Timer Should Be:
Halt Mode Selected
via Mask Option
Wait Period Less Than
COP Timeout
Enable or Disable COP
via Mask Option
Halt Mode Selected
via Mask Option
Wait Period More Than
COP Timeout
Disable COP
via Mask Option
Stop Mode Selected
via Mask Option
Any Length Wait Period
Disable COP
via Mask Option
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7.1 Contents
7.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
7.3
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
7.4
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
7.5
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
7.6
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.7
I/O Port Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
7.2 Introduction
In the single-chip mode, 20 bidirectional input/output (I/O) lines are
arranged as two 8-bit I/O ports (ports A and C), one 3-bit I/O port (port
B), and one 1-bit I/O port (port D). These ports are programmable as
either inputs or outputs under software control of the data direction
registers (DDRs). An input-only pin is associated with port D.
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Section 7. Input/Output Ports
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A G R E E M E N T
R E Q U I R E D
Input/Output Ports
7.3 Port A
Port A is an 8-bit bidirectional port, which can share its pins with the
interrupt system as shown in Figure 7-1. Each port A pin is controlled by
the corresponding bits in a data direction register and a data register.
The port A data register is located at address $0000. The port A data
direction register (DDRA) is located at address $0004. Reset clears the
DDRA, thereby initializing port A as an input port. The port A data
register is unaffected by reset.
READ $0004
WRITE $0004
DATA
DIRECTION
REGISTER BIT
WRITE $0000
DATA
REGISTER BIT
I/O
PIN
OUTPUT
READ $0000
PULLUP
INTERNAL HC05
DATA BUS
RESET
(RST)
MASK OPTION
(PULLUP INHIBIT)
VDD
TO
INTERRUPT
SYSTEM
Figure 7-1. Port A I/O Circuitry
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READ $0005
WRITE $0005
RESET
(RST)
WRITE $0001
DATA
DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0001
INTERNAL HC05
DATA BUS
Figure 7-2. Port B I/O Circuitry
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Port B is a 3-bit bidirectional port that does not share any of its pins with
other subsystems. The port B data register is located at address $0001
and its data direction register (DDR) is located at address $0005. Reset
does not affect the data registers but clears the DDRs, thereby setting
all of the port pins to input mode. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode (see Figure 7-2).
A G R E E M E N T
7.4 Port B
R E Q U I R E D
Input/Output Ports
Port B
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R E Q U I R E D
Input/Output Ports
7.5 Port C
Port C is an 8-bit bidirectional port that does not share any of its pins with
other subsystems. The port C data register is located at address $0002,
and its data direction register (DDR) is located at address $0006. Reset
does not affect the data registers but clears the DDRs, thereby setting
all of the port pins to input mode. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode (see Figure 7-3). Two port C
pins, PC0 and PC1, can source and sink a higher current than a typical
I/O pin. See Section 10. Electrical Specifications regarding current
specifications.
READ $0006
WRITE $0006
RESET
(RST)
WRITE $0002
HIGH CURRENT
CAPABILITY, PC0
AND PC1 ONLY
DATA
DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0002
INTERNAL HC05
DATA BUS
Figure 7-3. Port C I/O Circuitry
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Port D may be used for general I/O applications regardless of the state
of the 16-bit timer. Since PD7 is an input-only line, its state can be read
from the port D data register at any time.
READ $0007
WRITE $0007
RESET
(RST)
WRITE $0003
DATA
DIRECTION
REGISTER BIT
DATA
REGISTER BIT
OUTPUT
I/O
PIN
READ $0003
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Port D is a 2-bit port with one bidirectional pin (PD5) and one input-only
pin (PD7). Pin PD7 is shared with the 16-bit timer. The port D data
register is located at address $0003 and its data direction register (DDR)
is located at address $0007. Reset does not affect the data registers but
clears the DDRs, thereby setting PD5 to input mode. Writing a 1 to DDR
bit 5 sets PD5 to output mode (see Figure 7-4).
A G R E E M E N T
7.6 Port D
R E Q U I R E D
Input/Output Ports
Port D
INTERNAL HC05
DATA BUS
Figure 7-4. Port D I/O Circuitry
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7.7 I/O Port Programming
Each pin on ports A through D (except pin 7 of port D) may be
programmed as an input or an output under software control as shown
in Table 7-1, Table 7-2, Table 7-3, and Table 7-4. The direction of a pin
is determined by the state of its corresponding bit in the associated port
data direction register (DDR). A pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
Table 7-1. Port A I/O Pin Functions
DDRA
I/O Pin
Mode
Accesses to
DDRA @ $0004
Accesses to Data
Register @ $0000
Read/Write
Read
Write
IRQ
Source
0
Input, Hi-Z
DDRA0–DDRA7
I/O Pin
*
Enabled**
1
Output
DDRA0–DDRA7
PA0–PA7
PA0–PA7
Disabled
*Does not affect input, but stored to data register
**If enabled via mask option
Table 7-2. Port B I/O Pin Functions
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R E Q U I R E D
Input/Output Ports
DDRB
I/O Pin
Mode
Accesses to
DDRB @ $0005
Accesses to Data
Register @ $0001
Read/Write
Read
Write
0
Input, Hi-Z
DDRB5–DDRB7
I/O Pin
*
1
Output
DDRB0–DDRB7
PB5–PB7
PB5–PB7
*Does not affect input, but stored to data register
Table 7-3. Port C I/O Pin Functions
DDRC
I/O Pin
Mode
Accesses to
DDRC @ $0006
Accesses to Data
Register @ $0002
Read/Write
Read
Write
0
Input, Hi-Z
DDRC0–DDRA7
I/O Pin
*
1
Output
DDRC0–DDRA7
PC0–PC7
PC0–PC7
*Does not affect input, but stored to data register
General Release Specification
MC68HC05P1A — Rev. 3.0
Input/Output Ports
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DDRD
I/O Pin
Mode
Accesses to
DDRD @ $0007
Accesses to Data
Register @ $0003
Read/Write
Read
Write
0
Input, Hi-Z
DDRD5
I/O Pin
*
1
Output
DDRD5
PD5
PD5
NOTE:
To avoid generating a glitch on an I/O port pin, data should be written to
the I/O port data register before writing a logical 1 to the corresponding
data direction register.
At power-on or reset, all DDRs are cleared, which configures all port pins
as inputs. The DDRs are capable of being written to or read by the
processor. During the programmed output state, a read of the data
register will actually read the value of the output data latch and not the
level on the I/O port pin.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
*Does not affect input, but stored to data register, PD7 is input-only
A G R E E M E N T
Table 7-4. Port D I/O Pin Functions
R E Q U I R E D
Input/Output Ports
I/O Port Programming
MC68HC05P1A — Rev. 3.0
General Release Specification
Input/Output Ports
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N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Input/Output Ports
General Release Specification
MC68HC05P1A — Rev. 3.0
Input/Output Ports
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8.1 Contents
8.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.3
Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
8.4
Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
8.5
Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
8.6
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
8.7
Timer Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
8.8
Timer Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . .75
8.9
Timer Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . .75
8.2 Introduction
The MC68HC05P1A MCU contains a single 16-bit programmable timer
with an input capture function and an output compare function. The 16bit timer is driven by the output of a fixed divide-by-four prescaler
operating from the PH2 clock. The 16-bit timer may be used for many
applications, including input waveform measurement, while
simultaneously generating an output waveform. Pulse widths can vary
from microseconds to seconds depending on the oscillator frequency
selected. The 16-bit timer also is capable of generating periodic
interrupts. See Figure 8-1.
Because the timer has a 16-bit architecture, each function is represented
by two registers. Each register pair contains the high and low byte of that
function. Generally, accessing the low byte of a specific timer function
allows full control of that function; however, an access of the high byte
inhibits that specific timer function until the low byte is also accessed.
MC68HC05P1A — Rev. 3.0
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16-Bit Timer
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A G R E E M E N T
Section 8. 16-Bit Timer
N O N - D I S C L O S U R E
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
INTERNAL HC05 BUS
OUTPUT
COMPARE
OCRH
Freescale Semiconductor, Inc...
N O N - D I S C L O S U R E
BUFFER
INPUT
CAPTURE
PH2
CLOCK
FREERUNNING
COUNTER
OCRL
TMRH
/ACRH
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
ICRH
TMRL
/ACRL
÷4
OVERFLOW
DETECTOR
COMPARE
DETECTOR
ICRL
EDGE
DETECTOR
D
Q
TCAP
TCMP
>
R
TIMER
STATUS
REGISTER
OCF
TOF
RESET
ICF
INTERRUPT
GENERATOR
OCIE
TOIE
TIMER INTERRUPT
ICIE
IEDG
OLVL
TIMER
CONTROL
REGISTER
Figure 8-1. 16-Bit Timer Block Diagram
General Release Specification
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16-Bit Timer
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8.3 Timer
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The key element of the programmable timer is a 16-bit free-running
counter, or timer registers, preceded by a prescaler, which divides the
PH2 clock by four. The prescaler gives the timer a resolution of 2.0
microseconds when a 4-MHz crystal is used. The counter is incremented
to increasing values during the low portion of the PH2 clock cycle.
The double-byte, free-running counter can be read from either of two
locations: the timer registers (TMRH and TMRL) or the alternate counter
registers (ACRH and ACRL). Both locations will contain identical values.
A read sequence containing only a read of the least significant bit (LSB)
of the counter (TMRL/ACRL) will return the count value at the time of the
read. If a read of the counter accesses the most significant bit (MSB) first
(TMRH/ACRH), it causes the LSB (TMRL/ACRL) to be transferred to a
buffer. This buffer value remains fixed after the first MSB byte read even
if the MSB is read several times. The buffer is accessed when reading
the counter LSB (TMRL/ACRL), and thus completes a read sequence of
the total counter value. When reading either the timer or alternate
counter registers, if the MSB is read, the LSB must also be read to
complete the read sequence. See Figure 8-2 and Figure 8-3.
The timer registers and alternate counter registers can be read at any
time without affecting their value. However, the alternate counter
registers differ from the timer registers in one respect: A read of the timer
register MSB can clear the timer overflow flag (TOF). Therefore, the
alternate counter registers can be read at any time without the possibility
of missing timer overflow interrupts due to clearing of the TOF. See
Figure 8-4.
MC68HC05P1A — Rev. 3.0
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16-Bit Timer
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A G R E E M E N T
The I bit in the condition code register (CCR) should be set while
manipulating both the high and low byte registers of a specific timer
function. This prevents interrupts from occurring between the time that
the high and low bytes are accessed.
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
16-Bit Timer
Timer
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
TMRH
Read:
$0018
Bit 7
6
5
4
3
2
1
Bit 0
TMRH7
TMRH6
TMRH5
TMRH4
TMRH3
TMRH2
TMRH1
TMRH0
1
1
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
TMRL
Read:
$0019
Bit 7
6
5
4
3
2
1
Bit 0
TMRL7
TMRL6
TMRL5
TMRL4
TMRL3
TMRL2
TMRL1
TMRL0
1
1
1
1
1
1
0
0
Write:
Reset:
= Unimplemented
Figure 8-2. Timer Registers (TMRH/TMRL)
ACRH
Read:
$001A
Bit 7
6
5
4
3
2
1
Bit 0
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
1
1
1
1
1
1
1
1
Write:
Reset:
= Unimplemented
ACRL
Read:
$001B
Bit 7
6
5
4
3
2
1
Bit 0
ACRL7
ACRL6
ACRL5
ACRL4
ACRL3
ACRL2
ACRL1
ACRL0
1
1
1
1
1
1
0
0
Write:
Reset:
= Unimplemented
Figure 8-3. Alternate Counter Registers (ACRH/ACRL)
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16-Bit Timer
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$FFFE
$FFFF
$0000
$0001
$0002
TIMER
OVERFLOW
FLAG (TOF)
Freescale Semiconductor, Inc...
NOTE: The TOF bit is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by reading the timer status
register (TSR) during the high portion of the PH2 clock followed by reading the LSB of the counter register pair (TCRL).
Figure 8-4. State Timing Diagram for Timer Overflow
The free-running counter is initialized to $FFFC during reset. It is a readonly register. During power-on reset (POR), the counter is initialized to
$FFFC and begins counting after the oscillator startup delay. Because
the counter is 16 bits preceded by a fixed divide-by-four prescaler, the
value in the counter repeats every 262,144 PH2 clock cycles (524,288
oscillator cycles). When the free-running counter rolls over from $FFFF
to $0000, the timer overflow flag bit (TOF) in register TSR is set. When
counter rollover occurs, an interrupt also can be enabled by setting the
timer overflow interrupt enable bit (TOIE) in register TCR.
See Figure 8-5.
PH2 CLOCK
INTERNAL
RESET
16-BIT FREERUNNING
COUNTER
$FFFC
$FFFD
$FFFE
$FFFF
RESET
(EXTERNAL OR
OTHER)
NOTE: The counter and control registers are the only 16-bit timer registers affected by reset.
Figure 8-5. State Timing Diagram for Timer Reset
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16-Bit Timer
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A G R E E M E N T
16-BIT FREERUNNING
COUNTER
N O N - D I S C L O S U R E
PH2
CLOCK
R E Q U I R E D
16-Bit Timer
Timer
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
8.4 Output Compare
The output compare function may be used to generate an output
waveform and/or as an elapsed time indicator. All of the bits in the output
compare register pair OCRH/OCRL are readable and writable and are
not altered by the 16-bit timer’s control logic. Reset does not affect the
contents of these registers. If the output compare function is not utilized,
its registers may be used for data storage. See Figure 8-2.
OCRH
Read:
$0016
Bit 7
6
5
4
3
2
1
Bit 0
OCRH7
OCRH6
OCRH5
OCRH4
OCRH3
OCRH2
OCRH1
OCRH0
Write:
Reset:
Unaffected by Reset
= Unimplemented
OCRL
Read:
$0017
Bit 7
6
5
4
3
2
1
Bit 0
OCRL7
OCRL6
OCRL5
OCRL4
OCRL3
OCRL2
OCRL1
OCRL0
Write:
Reset:
Unaffected by Reset
= Unimplemented
Figure 8-6. Output Compare Registers (OCRH/OCRL)
The contents of the output compare registers are compared with the
contents of the free-running counter once every four PH2 clock cycles.
If a match is found, the output compare flag bit (OCF) is set and the
output level bit (OLVL) is clocked to the output latch. After each
successful comparison, the values in the output compare registers and
output level bit should be changed to control an output waveform or to
establish a new elapsed timeout. An interrupt also can accompany a
successful output compare if the output compare interrupt enable bit
(OCIE) is set.
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16-Bit Timer
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Since neither the output compare flag (OCF) nor the output compare
registers are affected by reset, care must be exercised when initializing
the output compare function. This procedure is recommended:
1. Block interrupts by setting the I bit in the condition code register
(CCR).
2. Write the MSB of the output compare register pair (OCRH) to
inhibit further compares until the LSB is written.
3. Read the timer status register (TSR) to arm the output compare
flag (OCF).
4. Write the LSB of the output compare register pair (OCRL) to
enable the output compare function and to clear its flag (and
interrupt).
5. Unblock interrupts by clearing the I bit in the CCR.
This procedure prevents the output compare flag bit (OCF) from being
set between the time it is read and the time the output compare registers
are updated. A software example is shown in Figure 8-7 and a state
timing diagram is shown in Figure 8-8.
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16-Bit Timer
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A G R E E M E N T
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The output compare output level bit (OLVL) will be clocked to its output
latch regardless of the state of the output compare flag bit (OCF). A valid
output compare must occur before the OLVL bit is clocked to its output
latch (TCMP).
N O N - D I S C L O S U R E
After a CPU write cycle to the MSB of the output compare register pair
(OCRH), the output compare function is inhibited until the LSB (OCRL)
is written. Both bytes must be written if the MSB is written. A write made
only to the LSB will not inhibit the compare function. The free-running
counter increments every four PH2 clock cycles. The minimum time
required to update the output compare registers is a function of software
rather than hardware.
R E Q U I R E D
16-Bit Timer
Output Compare
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
9B
.
.
B6
BE
B7
B6
BF
.
.
9A
.
.
XX
XX
16
13
17
.
.
SEI
.
.
LDA
LDX
STA
LDA
STX
.
.
CLI
.
.
DATAH
DATAL
OCRH
TSR
OCRL
.
.
BLOCK INTERRUPTS
.
.
HI BYTE FOR COMPARE
LO BYTE FOR COMPARE
INHIBIT OUTPUT COMPARE
ARM OCF BIT TO CLEAR
READY FOR NEXT COMPARE
.
.
Figure 8-7. Output Compare Software Initialization Example
PH2
CLOCK
16-BIT FREERUNNING
COUNTER
$FFEB
COMPARE
REGISTER
$FFEC
$FFED
CPU WRITES $FFED
COMPARE
REGISTER
LATCH
$FFEE
$FFEF
$FFED
(NOTE 1)
OUTPUT
COMPARE FLAG
AND OUTPUT PIN
(NOTE 2)
(NOTE 3)
NOTES:
1. The CPU write to the compare register may take place at any time, but a compare only occurs at timer state T01. Thus, up
to a four cycle difference may exist between the write to the compare register and the actual compare.
2. Internal compare takes place during timer state T01.
3. The output compare flag bit (OCF) is set at timer state T11 which follows the comparison match ($FFED in this example).
Figure 8-8. State Timing Diagram for Output Compare
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16-Bit Timer
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ICRH
Read:
$0014
Bit 7
6
5
4
3
2
1
Bit 0
ICRH7
ICRH6
ICRH5
ICRH4
ICRH3
ICRH2
ICRH1
ICRH0
Write:
Reset:
Unaffected by Reset
= Unimplemented
ICRL
Read:
$0015
Bit 7
6
5
4
3
2
1
Bit 0
ICRL7
ICRL6
ICRL5
ICRL4
ICRL3
ICRL2
ICRL1
ICRL0
Write:
Reset:
Unaffected by Reset
= Unimplemented
Figure 8-9. Input Compare Registers (ICRH/ICRL)
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the PH2 clock preceding
the external transition (see Figure 8-10). This delay is required for
internal synchronization. Resolution is affected by the prescaler,
allowing the free-running counter to increment once every four PH2
clock cycles.
The contents of the free-running counter are transferred to the input
capture registers on each proper signal transition regardless of the state
of the input capture flag bit (ICF) in register TSR. The input capture
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A G R E E M E N T
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Two 8-bit read-only registers (ICRH and ICRL) make up the 16-bit input
capture. They are used to latch the value of the free-running counter
after a defined transition is sensed by the input capture edge detector.
(Note that the input capture edge detector contains a Schmitt trigger to
improve noise immunity.) The edge that triggers the counter transfer is
defined by the input edge bit (IEDG) in register TCR. Reset does not
affect the contents of the input capture registers. See Figure 8-2.
N O N - D I S C L O S U R E
8.5 Input Capture
R E Q U I R E D
16-Bit Timer
Input Capture
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
16-Bit Timer
registers always contain the free-running counter value that corresponds
to the most recent input capture.
After a read of the MSB of the input capture register pair (ICRH), counter
transfers are inhibited until the LSB of the register pair (ICRL) is also
read. This characteristic forces the minimum pulse period attainable to
be determined by the time required to execute an input capture software
routine in an application.
Reading the LSB of the input capture register pair (ICRL) does not inhibit
transfer of the free-running counter. Again, minimum pulse periods are
ones which allow software to read the LSB of the register pair (ICRL) and
perform needed operations. There is no conflict between reading the
LSB (ICRL) and the free-running counter transfer, since they occur on
opposite edges of the PH2 clock.
PH2
CLOCK
16-BIT FREERUNNING
COUNTER
$FFEB
$FFEC
$FFED
$FFEE
$FFEF
TCAP
PIN
INPUT
CAPTURE
LATCH
(SEE NOTE)
INPUT
CAPTURE
REGISTER
INPUT
CAPTURE
FLAG
NOTE: Although the input capture pin is sampled at the rate of PH2, the internal function is updated at the rate of PH4.
Figure 8-10. State Timing Diagram for Input Capture
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16-Bit Timer
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$0012
Read:
Write:
Reset:
Bit 7
6
5
ICIE
OCIE
TOIE
0
0
0
4
3
2
0
0
0
0
0
0
1
Bit 0
IEDG
OLVL
U
0
U = Unaffected
Figure 8-11. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable
Bit 7, when set, enables input capture interrupts to the CPU. The
interrupt will occur at the same time bit 7 (ICF) in the TSR register is
set.
OCIE — Output Compare Interrupt Enable
Bit 6, when set, enables output compare interrupts to the CPU. The
interrupt will occur at the same time bit 6 (OCF) in the TSR register is
set.
TOIE — Timer Overflow Interrupt Enable
Bit 5, when set, enables timer overflow (rollover) interrupts to the
CPU. The interrupt will occur at the same time bit 5 (TOF) in the TSR
register is set.
IEDG — Input Capture Edge Select
Bit 1 selects which edge of the input capture signal will trigger a
transfer of the contents of the free-running counter registers to the
input capture registers. Clearing this bit will select the falling edge;
setting it selects the rising edge.
OLVL — Output Compare Output Level Select
Bit 0 selects the output level (high or low) that is clocked into the
output compare output latch at the next successful output compare.
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16-Bit Timer
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A G R E E M E N T
The timer control (TCR) and free-running counter (TMRH, TMRL,
ACRH, and ACRL) registers are the only registers of the 16-bit timer
affected by reset. The output compare port (TCMP) is forced low after
reset and remains low until OLVL is set and a valid output compare
occurs.
N O N - D I S C L O S U R E
8.6 Timer Control Register
R E Q U I R E D
16-Bit Timer
Timer Control Register
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
16-Bit Timer
8.7 Timer Status Register
Reading the timer status register (TSR) satisfies the first condition
required to clear status flags and interrupts. The only remaining step is
to read (or write) the register associated with the active status flag
(and/or interrupt). This method does not present any problems for input
capture or output compare functions.
However, a problem can occur when using a timer interrupt function and
reading the free-running counter at random times to measure an elapsed
time. If the proper precautions are not designed into the application
software, a timer interrupt flag (TOF) could unintentionally be cleared if:
1. The TSR is read when bit 5 (TOF) is set.
2. The LSB of the free-running counter is read, but not for the
purpose of servicing the flag or interrupt.
The alternate counter registers (ACRH and ACRL) contain the same
values as the timer registers (TMRH and TMRL). Registers ACRH and
ACRL can be read at any time without affecting the timer overflow flag
(TOF) or interrupt.
$0013
Read:
Bit 7
6
5
4
3
2
1
Bit 0
ICF
OCF
TOF
0
0
0
0
0
U
U
U
0
0
0
0
0
Write:
Reset:
U = Unaffected
Figure 8-12. Timer Status Register (TSR)
ICF — Input Capture Flag
Bit 7 is set when the edge specified by IEDG in register TCR has been
sensed by the input capture edge detector fed by pin TCAP. This flag
and the input capture interrupt can be cleared by reading register TSR
followed by reading the LSB of the input capture register pair (ICRL).
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TOF — Timer Overflow Flag
Bit 5 is set by a rollover of the free-running counter from $FFFF to
$0000. This flag and the timer overflow interrupt can be cleared by
reading register TSR followed by reading the LSB of the timer register
pair (TMRL).
8.8 Timer Operation During Wait Mode
During wait mode, the 16-bit timer continues to operate normally and
may generate an interrupt to trigger the MCU out of wait mode.
8.9 Timer Operation During Stop Mode
When the MCU enters stop mode, the free-running counter stops
counting (the PH2 clock is stopped). It remains at that particular count
value until stop mode is exited by applying a low signal to the IRQ pin,
at which time the counter resumes from its stopped value as if nothing
had happened. If stop mode is exited via an external RESET (logic low
applied to the RESET pin), the counter is forced to $FFFC.
If a valid input capture edge occurs at the TCAP pin during stop mode,
the input capture detect circuitry will be armed. This action does not set
any flags or wake up the MCU, but when the MCU does wake up, there
will be an active input capture flag (and data) from the first valid edge. If
stop mode is exited by an external reset, no input capture flag or data
will be present even if a valid input capture edge was detected during
stop mode.
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A G R E E M E N T
Bit 6 is set when the contents of the output compare registers match
the contents of the free-running counter. This flag and the output
compare interrupt can be cleared by reading register TSR followed by
writing the LSB of the output compare register pair (OCRL).
N O N - D I S C L O S U R E
OCF — Output Compare Flag
R E Q U I R E D
16-Bit Timer
Timer Operation During Wait Mode
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
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A G R E E M E N T
R E Q U I R E D
16-Bit Timer
General Release Specification
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16-Bit Timer
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General Release Specification — MC68HC05P1A
Section 9. Instruction Set
9.1 Contents
9.3
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
9.3.1
Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.2
Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.3
Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.4
Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
9.3.5
Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.6
Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.7
Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
9.3.8
Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4
Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
9.4.1
Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . .82
9.4.2
Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .83
9.4.3
Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . .84
9.4.4
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . .86
9.4.5
Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
9.5
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
9.6
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
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A G R E E M E N T
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
N O N - D I S C L O S U R E
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9.2
R E Q U I R E D
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Freescale Semiconductor, Inc.
9.2 Introduction
The MCU instruction set has 62 instructions and uses eight addressing
modes. The instructions include all those of the M146805 CMOS Family
plus one more: the unsigned multiply (MUL) instruction. The MUL
instruction allows unsigned multiplication of the contents of the
accumulator (A) and the index register (X). The high-order product is
stored in the index register, and the low-order product is stored in the
accumulator.
9.3 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
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A G R E E M E N T
R E Q U I R E D
Instruction Set
•
Inherent
•
Immediate
•
Direct
•
Extended
•
Indexed, no offset
•
Indexed, 8-bit offset
•
Indexed, 16-bit offset
•
Relative
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9.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
R E Q U I R E D
Instruction Set
Addressing Modes
9.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
9.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Freescale assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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9.3.2 Immediate
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A G R E E M E N T
R E Q U I R E D
Instruction Set
9.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used RAM or I/O location.
9.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
9.3.7 Indexed,16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler
determines the shortest form of indexed addressing.
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When using the Freescale assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
9.4 Instruction Types
The MCU instructions fall into five categories:
•
Register/memory instructions
•
Read-modify-write instructions
•
Jump/branch instructions
•
Bit manipulation instructions
•
Control instructions
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Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
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A G R E E M E N T
9.3.8 Relative
R E Q U I R E D
Instruction Set
Instruction Types
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R E Q U I R E D
Instruction Set
9.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 9-1. Register/Memory Instructions
N O N - D I S C L O S U R E
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A G R E E M E N T
Instruction
Mnemonic
Add Memory Byte and Carry Bit to Accumulator
ADC
Add Memory Byte to Accumulator
ADD
AND Memory Byte with Accumulator
AND
Bit Test Accumulator
BIT
Compare Accumulator
CMP
Compare Index Register with Memory Byte
CPX
EXCLUSIVE OR Accumulator with Memory Byte
EOR
Load Accumulator with Memory Byte
LDA
Load Index Register with Memory Byte
LDX
Multiply
MUL
OR Accumulator with Memory Byte
ORA
Subtract Memory Byte and Carry Bit from Accumulator
SBC
Store Accumulator in Memory
STA
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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9.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
Do not use read-modify-write operations on write-only registers.
Table 9-2. Read-Modify-Write Instructions
Mnemonic
Arithmetic Shift Left (Same as LSL)
ASL
Arithmetic Shift Right
ASR
Bit Clear
BCLR(1)
Bit Set
BSET(1)
Clear Register
CLR
Complement (One’s Complement)
COM
Decrement
DEC
Increment
INC
Logical Shift Left (Same as ASL)
LSL
Logical Shift Right
LSR
Negate (Two’s Complement)
NEG
Rotate Left through Carry Bit
ROL
Rotate Right through Carry Bit
ROR
Test for Negative or Zero
TST(2)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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Instruction
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
9.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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A G R E E M E N T
R E Q U I R E D
Instruction Set
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Mnemonic
Branch if Carry Bit Clear
BCC
Branch if Carry Bit Set
BCS
Branch if Equal
BEQ
Branch if Half-Carry Bit Clear
BHCC
Branch if Half-Carry Bit Set
BHCS
Branch if Higher
BHI
Branch if Higher or Same
BHS
Branch if IRQ Pin High
BIH
Branch if IRQ Pin Low
BIL
Branch if Lower
BLO
Branch if Lower or Same
BLS
Branch if Interrupt Mask Clear
BMC
Branch if Minus
BMI
Branch if Interrupt Mask Set
BMS
Branch if Not Equal
BNE
Branch if Plus
BPL
Branch Always
BRA
Branch if Bit Clear
Branch Never
Branch if Bit Set
BRCLR
BRN
BRSET
Branch to Subroutine
BSR
Unconditional Jump
JMP
Jump to Subroutine
JSR
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Instruction
N O N - D I S C L O S U R E
Table 9-3. Jump and Branch Instructions
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
R E Q U I R E D
Instruction Set
9.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 9-4. Bit Manipulation Instructions
A G R E E M E N T
Instruction
Freescale Semiconductor, Inc...
Bit Clear
Mnemonic
BCLR
Branch if Bit Clear
BRCLR
Branch if Bit Set
BRSET
BSET
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Bit Set
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Table 9-5. Control Instructions
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Instruction
Mnemonic
Clear Carry Bit
CLC
Clear Interrupt Mask
CLI
No Operation
NOP
Reset Stack Pointer
RSP
Return from Interrupt
RTI
Return from Subroutine
RTS
Set Carry Bit
SEC
Set Interrupt Mask
SEI
Stop Oscillator and Enable IRQ Pin
STOP
Software Interrupt
SWI
Transfer Accumulator to Index Register
TAX
Transfer Index Register to Accumulator
TXA
Stop CPU Clock and Enable Interrupts
WAIT
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These instructions act on CPU registers and control CPU operation
during program execution.
N O N - D I S C L O S U R E
9.4.5 Control Instructions
R E Q U I R E D
Instruction Set
Instruction Types
Freescale Semiconductor, Inc.
9.5 Instruction Set Summary
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
↕
IMM
DIR
EXT
IX2
IX1
IX
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 5
E9 ff
4
F9
3
↕
IMM
DIR
EXT
IX2
IX1
IX
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 5
EB ff
4
FB
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 5
E4 ff
4
F4
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
Effect on
CCR
Description
H I N Z C
A ← (A) + (M) + (C)
Add with Carry
A ← (A) + (M)
Add without Carry
Arithmetic Shift Left (Same as LSL)
C
BCC rel
Branch if Carry Bit Clear
↕
↕
— — ↕
0
b7
Arithmetic Shift Right
↕ —
A ← (A) ∧ (M)
Logical AND
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
↕ —
— — ↕
↕
↕
↕
b0
C
b7
— — ↕
↕
↕
b0
PC ← (PC) + 2 + rel ? C = 0
Mn ← 0
— — — — —
REL
ff
ff
Cycles
Operation
Opcode
Source
Form
Operand
Table 9-6. Instruction Set Summary
Address
Mode
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A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
24
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
— — — — —
25
rr
3
BCLR n opr
Clear Bit n
BCS rel
Branch if Carry Bit Set (Same as BLO)
BEQ rel
Branch if Equal
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
REL
27
rr
3
BHCC rel
Branch if Half-Carry Bit Clear
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
BHCS rel
Branch if Half-Carry Bit Set
PC ← (PC) + 2 + rel ? H = 1
— — — — —
REL
29
rr
3
BHI rel
Branch if Higher
PC ← (PC) + 2 + rel ? C ∨ Z = 0 — — — — —
REL
22
rr
3
BHS rel
Branch if Higher or Same
REL
24
rr
3
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? C = 0
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— — — — —
REL
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Operand
Cycles
Branch if IRQ Pin High
PC ← (PC) + 2 + rel ? IRQ = 1
— — — — —
REL
2F
rr
3
BIL rel
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
REL
2E
rr
3
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Freescale Semiconductor, Inc...
Operation
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte
Description
(A) ∧ (M)
PC ← (PC) + 2 + rel ? C = 1
BLO rel
Branch if Lower (Same as BCS)
BLS rel
Branch if Lower or Same
BMC rel
Branch if Interrupt Mask Clear
PC ← (PC) + 2 + rel ? I = 0
BMI rel
Branch if Minus
PC ← (PC) + 2 + rel ? N = 1
BMS rel
Branch if Interrupt Mask Set
PC ← (PC) + 2 + rel ? I = 1
BNE rel
Branch if Not Equal
PC ← (PC) + 2 + rel ? Z = 0
BPL rel
Branch if Plus
PC ← (PC) + 2 + rel ? N = 0
BRA rel
Branch Always
PC ← (PC) + 2 + rel ? 1 = 1
BRCLR n opr rel Branch if Bit n Clear
BRN rel
Branch Never
BRSET n opr rel Branch if Bit n Set
BSET n opr
Set Bit n
Effect on
CCR
H I N Z C
— — ↕
↕ —
IMM
DIR
EXT
IX2
IX1
IX
— — — — —
REL
25
rr
3
PC ← (PC) + 2 + rel ? C ∨ Z = 1 — — — — —
REL
23
rr
3
— — — — —
REL
2C
rr
3
— — — — —
REL
2B
rr
3
— — — — —
REL
2D
rr
3
— — — — —
REL
26
rr
3
— — — — —
REL
2A
rr
3
— — — — —
REL
20
rr
3
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
— — — — —
PC ← (PC) + 2 + rel ? Mn = 0
PC ← (PC) + 2 + rel ? 1 = 0
21
rr
3
PC ← (PC) + 2 + rel ? Mn = 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — ↕
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
Mn ← 1
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
— — — — —
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
— — — — —
REL
AD
rr
6
BSR rel
Branch to Subroutine
CLC
Clear Carry Bit
C←0
— — — — 0
INH
98
2
CLI
Clear Interrupt Mask
I←0
— 0 — — —
INH
9A
2
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A G R E E M E N T
Opcode
BIH rel
Source
Form
N O N - D I S C L O S U R E
Address
Mode
Table 9-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
COM opr
COMA
COMX
COM opr,X
COM ,X
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
INC opr
INCA
INCX
INC opr,X
INC ,X
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Description
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
↕
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
2
B1 dd 3
C1 hh ll 4
D1 ee ff 5
E1 ff
4
F1
3
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
↕
IMM
DIR
EXT
IX2
IX1
IX
A3 ii
2
B3 dd 3
C3 hh ll 4
D3 ee ff 5
E3 ff
4
F3
3
↕ —
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
↕ —
IMM
DIR
EXT
IX2
IX1
IX
A8 ii
2
B8 dd 3
C8 hh ll 4
D8 ee ff 5
E8 ff
4
F8
3
↕ —
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
DIR
EXT
IX2
IX1
IX
BC dd 2
CC hh ll 3
DC ee ff 4
EC ff
3
FC
2
Effect on
CCR
H I N Z C
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One’s Complement)
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Unconditional Jump
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
(X) – (M)
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
Decrement Byte
Increment Byte
(A) – (M)
A ← (A) ⊕ (M)
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
PC ← Jump Address
General Release Specification
— — 0 1 —
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
— — ↕
↕
↕
↕
— — — — —
ff
dd
ff
dd
ff
dd
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 9-6. Instruction Set Summary (Continued)
Address
Mode
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
MC68HC05P1A — Rev. 3.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
Jump to Subroutine
A ← (M)
Load Accumulator with Memory Byte
X ← (M)
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
↕ —
A6 ii
2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff
4
F6
3
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii
2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff
4
FE
3
38
48
58
68
78
dd
↕
DIR
INH
INH
IX1
IX
0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
MUL
Unsigned Multiply
0
C
b7
INH
42
Negate Byte (Two’s Complement)
NOP
No Operation
↕
— — 0 ↕
↕
b0
X : A ← (X) × (A)
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
— — ↕
b0
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0
— — ↕
↕
↕
— — — — —
A ← (A) ∨ (M)
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
— — ↕
C
— — ↕
b7
b0
MC68HC05P1A — Rev. 3.0
DIR
INH
INH
IX1
IX
30
40
50
60
70
INH
9D
ff
ff
5
3
3
6
5
5
3
3
6
5
11
dd
ff
5
3
3
6
5
2
↕ —
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
39
49
59
69
79
dd
↕
DIR
INH
INH
IX1
IX
↕
Cycles
— — ↕
IMM
DIR
EXT
IX2
IX1
IX
— — ↕
C
b7
Logical Shift Right
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff
6
FD
5
H I N Z C
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Description
ff
2
3
4
5
4
3
5
3
3
6
5
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
— — — — —
DIR
EXT
IX2
IX1
IX
Effect on
CCR
N O N - D I S C L O S U R E
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
Opcode
Freescale Semiconductor, Inc...
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Operation
Address
Mode
Source
Form
Operand
Table 9-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Instruction Set Summary
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
— — — — —
INH
9C
2
↕
↕
INH
80
9
— — — — —
INH
81
6
— — ↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A2 ii
2
B2 dd 3
C2 hh ll 4
D2 ee ff 5
E2 ff
4
F2
3
Effect on
CCR
Description
H I N Z C
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Rotate Byte Right through Carry Bit
RSP
Reset Stack Pointer
SP ← $00FF
RTI
Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
Return from Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
C
b7
— — ↕
↕
↕
b0
↕
↕
↕
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator
SEC
Set Carry Bit
C←1
— — — — 1
INH
99
SEI
Set Interrupt Mask
I←1
— 1 — — —
INH
9B
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in Memory
STOP
Stop Oscillator and Enable IRQ Pin
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SWI
Store Index Register In Memory
Subtract Memory Byte from Accumulator
Software Interrupt
A ← (A) – (M) – (C)
M ← (A)
↕
↕ —
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
— 0 — — —
INH
8E
— — ↕
ff
Cycles
Operation
Operand
Source
Form
Opcode
Table 9-6. Instruction Set Summary (Continued)
Address
Mode
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Instruction Set
5
3
3
6
5
2
2
dd
hh ll
ee ff
ff
4
5
6
5
4
2
dd
hh ll
ee ff
ff
↕ —
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
↕
↕
IMM
DIR
EXT
IX2
IX1
IX
A0 ii
2
B0 dd 3
C0 hh ll 4
D0 ee ff 5
E0 ff
4
F0
3
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
— 1 — — —
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
INH
83
M ← (X)
A ← (A) – (M)
General Release Specification
— — ↕
— — ↕
4
5
6
5
4
10
MC68HC05P1A — Rev. 3.0
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero
TXA
Transfer Index Register to Accumulator
WAIT
X ← (A)
A ← (X)
Accumulator
Carry/borrow flag
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
Negative flag
Any bit
97
opr
PC
PCH
PCL
REL
rel
rr
SP
X
Z
#
∧
∨
⊕
()
–( )
←
?
:
↕
—
Cycles
INH
2
dd
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
— — — — —
INH
9F
2
— 0 — — —
INH
8F
2
— — ↕
(M) – $00
Stop CPU Clock and Enable Interrupts
A
C
CCR
dd
dd rr
DIR
ee ff
EXT
ff
H
hh ll
I
ii
IMM
INH
IX
IX1
IX2
M
N
n
— — — — —
Operand
Description
↕ —
ff
4
3
3
5
4
Operand (one or two bytes)
Program counter
Program counter high byte
Program counter low byte
Relative addressing mode
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
Index register
Zero flag
Immediate value
Logical AND
Logical OR
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
If
Concatenated with
Set or cleared
Not affected
9.6 Opcode Map
See Table 9-7 on page 94.
MC68HC05P1A — Rev. 3.0
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Transfer Accumulator to Index Register
H I N Z C
Effect on
CCR
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
TAX
Operation
Opcode
Source
Form
Address
Mode
Table 9-6. Instruction Set Summary (Continued)
R E Q U I R E D
Instruction Set
Opcode Map
General Release Specification
Instruction Set
For More Information On This Product,
Go to: www.freescale.com
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
1
DIR
2
REL
Branch
3
DIR
4
5
INH
6
IX1
Read-Modify-Write
INH
7
IX
INH = Inherent
IMM = Immediate
DIR = Direct
EXT = Extended
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
EOR
IMM 2
2
ADC
IMM 2
2
ORA
IMM 2
2
ADD
IMM 2
2
2
SUB
IMM 2
2
CMP
IMM 2
2
SBC
IMM 2
2
CPX
IMM 2
2
AND
IMM 2
2
BIT
IMM 2
2
LDA
IMM 2
A
IMM
MSB
0
LSB
0
5
SUB
IX2 2
5
CMP
IX2 2
5
SBC
IX2 2
5
CPX
IX2 2
5
AND
IX2 2
5
BIT
IX2 2
5
LDA
IX2 2
6
STA
IX2 2
5
EOR
IX2 2
5
ADC
IX2 2
5
ORA
IX2 2
5
ADD
IX2 2
4
JMP
IX2 2
7
JSR
IX2 2
5
LDX
IX2 2
6
STX
IX2 2
D
IX2
4
SUB
IX1 1
4
CMP
IX1 1
4
SBC
IX1 1
4
CPX
IX1 1
4
AND
IX1 1
4
BIT
IX1 1
4
LDA
IX1 1
5
STA
IX1 1
4
EOR
IX1 1
4
ADC
IX1 1
4
ORA
IX1 1
4
ADD
IX1 1
3
JMP
IX1 1
6
JSR
IX1 1
4
LDX
IX1 1
5
STX
IX1 1
E
IX1
MSB of Opcode in Hexadecimal
4
SUB
EXT 3
4
CMP
EXT 3
4
SBC
EXT 3
4
CPX
EXT 3
4
AND
EXT 3
4
BIT
EXT 3
4
LDA
EXT 3
5
STA
EXT 3
4
EOR
EXT 3
4
ADC
EXT 3
4
ORA
EXT 3
4
ADD
EXT 3
3
JMP
EXT 3
6
JSR
EXT 3
4
LDX
EXT 3
5
STX
EXT 3
C
EXT
Register/Memory
3
SUB
DIR 3
3
CMP
DIR 3
3
SBC
DIR 3
3
CPX
DIR 3
3
AND
DIR 3
3
BIT
DIR 3
3
LDA
DIR 3
4
STA
DIR 3
3
EOR
DIR 3
3
ADC
DIR 3
3
ORA
DIR 3
3
ADD
DIR 3
2
JMP
DIR 3
5
JSR
DIR 3
3
LDX
DIR 3
4
STX
DIR 3
B
DIR
5 Number of Cycles
BRSET0 Opcode Mnemonic
3
DIR Number of Bytes/Addressing Mode
2
6
BSR
REL 2
2
LDX
2
IMM 2
2
TAX
INH
2
CLC
INH 2
2
SEC
INH 2
2
CLI
INH 2
2
SEI
INH 2
2
RSP
INH
2
NOP
INH 2
9
2
STOP
INH
2
2
TXA
WAIT
INH 1
INH
10
SWI
INH
9
RTI
INH
6
RTS
INH
8
INH
Control
INH
LSB of Opcode in Hexadecimal
5
5
3
5
3
3
6
5
BRSET0
BRA
BSET0
NEG
NEGA
NEGX
NEG
NEG
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
BRCLR0
BRN
BCLR0
3
1
DIR 2
DIR 2
REL
5
11
5
3
BRSET1
MUL
BHI
BSET1
3
1
DIR 2
INH
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR1
BLS
BCLR1
COM
COMA
COMX
COM
COM
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
5
5
3
5
3
3
6
5
BRSET2
BCC
BSET2
LSR
LSRA
LSRX
LSR
LSR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR2
BCLR2 BCS/BLO
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET3
BNE
BSET3
ROR
RORA
RORX
ROR
ROR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR3
BEQ
BCLR3
ASR
ASRA
ASRX
ASR
ASR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET4
BHCC
BSET4
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRCLR4
BHCS
BCLR4
ROL
ROLA
ROLX
ROL
ROL
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
5
3
3
6
5
BRSET5
BPL
BSET5
DEC
DECA
DECX
DEC
DEC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRCLR5
BMI
BCLR5
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRSET6
BMC
BSET6
INC
INCA
INCX
INC
INC
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
4
3
3
5
4
BRCLR6
BMS
BCLR6
TST
TSTA
TSTX
TST
TST
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX
5
5
3
BRSET7
BIL
BSET7
1
3
DIR 2
DIR 2
REL
5
5
3
5
3
3
6
5
BRCLR7
BIH
BCLR7
CLR
CLRA
CLRX
CLR
CLR
3
DIR 2
DIR 2
REL 2
DIR 1
INH 1
INH 2
IX1 1
IX 1
0
DIR
Bit Manipulation
Table 9-7. Opcode Map
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
F
IX
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
MSB
LSB
nc...
N O N - D I S C LFreescale
O S U R E Semiconductor,
A G R E E M E IN
T
R E Q U I R E D
Freescale Semiconductor, Inc.
Instruction Set
MC68HC05P1A — Rev. 3.0
Freescale Semiconductor, Inc...
10.1 Contents
10.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
10.3
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.4
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
10.5
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.6
Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
10.7
5.0 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .98
10.8
3.3 Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .99
10.9
5.0 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
10.10 3.3 Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
10.2 Introduction
This section contains the MCU electrical specifications and timing
information.
MC68HC05P1A — Rev. 3.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 10. Electrical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
10.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIN and VOUT within the range
VSS ≤ (VIN or VOUT) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD
Rating
Symbol
Value
Unit
Supply Voltage
VDD
–0.3 to + 7.0
V
Input Voltage
VIN
VSS –0.3 to
VDD ± 0.3
V
I
25
mA
TSTG
–65 to + 150
°C
Current Drain per Pin
Excluding VDD and VSS
Storage Temperature Range
NOTE:
This device is not guaranteed to operate properly at the maximum
ratings. Refer to 10.7 5.0 Volt DC Electrical Characteristics and
10.8 3.3 Volt DC Electrical Characteristics for guaranteed operating
conditions.
10.4 Operating Range
Characteristic
Symbol
Value
Unit
TA
TL to TH
0 to +70
–40 to +85
–40 to +105
°C
Operating Temperature Range
MC68HC05P1A (Standard)
MC68HC05P1A (Extended)
MC68HC05P1A (V)
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
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Freescale Semiconductor, Inc.
10.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
θJA
56
71
°C/W
Thermal Resistance
PDIP
SOIC
R E Q U I R E D
Electrical Specifications
Thermal Characteristics
The average chip-junction temperature, TJ, can be obtained in °C from:
TJ = TA + (PD × θJA)
(1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
A G R E E M E N T
Freescale Semiconductor, Inc...
10.6 Power Considerations
The following is an approximate relationship between PD and TJ
(neglecting PI/O):
PD = K + (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD at equilibrium for a
known TA. Using this value of K, the values of PD and TJ can be
obtained by solving equations (1) and (2) iteratively for any value of TA.
MC68HC05P1A — Rev. 3.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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N O N - D I S C L O S U R E
For most applications, PI/O « PINT and can be neglected.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
10.7 5.0 Volt DC Electrical Characteristics
Characteristic
Symbol
Min
Typ
Max
Unit
Output Voltage
ILoad ≤ 10.0 µA
VOL
VOH
—
VDD –0.1
—
—
0.1
—
V
Output High Voltage
(ILoad = –0.8 mA) PA0–PA7, PC2–PC7, PB7–PB5, TCMP,
PD5
(ILoad = –5.0 mA) PC0–PC1
VOH
VDD –0.8
—
0.4
VDD –0.8
—
0.4
Output Low Voltage
(ILoad = –1.6 mA) PA0–PA7, PB5–PB7,PC2–PC7,
PD5, TCMP
(ILoad = 20 mA) PC0–PC1
VOL
—
—
0.4
—
—
0.4
Input High Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ,
RESET, OSC1
VIH
0.7 × VDD
—
VDD
V
Input Low Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ,
RESET, OSC1
VIL
VSS
—
0.2 × VDD
V
—
—
3.5
1.8
5
3.5
mA
mA
—
—
—
—
1
2
4
6
15
20
30
50
µA
µA
µA
µA
V
V
Supply Current
Run (Note 3)
Wait (Note 4)
Stop (Note 5)
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Extended)
–40 °C to +105 °C (V)
IDD
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB5–PB7, PC0–PC7, PD5
IIL
—
—
±10
µA
Input Pullup Current
PA0–PA7
IIL
5
10
30
µA
Input Current
RESET, IRQ, OSC1, PD5, PD7/TCAP
IIN
—
—
±1
µA
Capacitance
PA7–PA0, PB5–PB0 (Input or Output)
RESET, IRQ, OSC1, OSC2
COUT
CIN
—
—
—
—
12
8
pF
NOTES:
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted
2. All values shown reflect average measurements at midpoint of voltage range at 25 °C.
3. Run (operating) IDD and wait IDD measured using external square wave clock source (fosc= 4.2 MHz), all inputs 0.2 V
from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD: Only timer system active. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
Wait IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = VSS.
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Symbol
VOL
VOH
Min
—
VDD–0.1
Typ
—
—
Max
0.1
—
VDD–0.3
—
—
VDD–0.3
—
—
—
—
0.3
—
—
0.3
VIH
0.7 × VDD
—
VDD
V
VIL
VSS
—
0.2 × VDD
V
—
—
1.0
0.5
2.5
1.4
mA
mA
—
—
—
—
0.5
1
2
5
10
15
20
40
µA
µA
µA
µA
IIL
—
—
±10
µA
IIL
5
—
10
µA
IIN
—
—
±1
µA
COUT
CIN
—
—
—
—
12
8
pF
IIN
1
3
20
µA
VOH
VOL
IDD
Unit
V
V
V
NOTES:
1. VDD= 3.3 Vdc ±10%, VSS= 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted
2. All values shown reflect average measurements at midpoint of voltage range at 25 °C.
3. Run (operating) IDD and wait IDD measured using external square wave clock source (fosc = 2.1 MHz), all inputs
0.2 V from rail; no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD: Only timer system active. Wait, stop IDD: All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V. Wait
IDD is affected linearly by the OSC2 capacitance.
5. Stop IDD measured with OSC1 = VSS.
MC68HC05P1A — Rev. 3.0
General Release Specification
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Characteristic
Output Voltage
ILoad ≤ 10.0 µA
Output High Voltage
(ILoad = –0.2 mA) PA0–PA7, PB5–PB7, PC2–PC7, PD5,
TCMP
(ILoad = –1.5 mA) PC0–PC1
Output Low Voltage
(ILoad = 0.4 mA) PA0–PA7, PB5–PB7, PC2–PC7, PD5,
TCMP
(ILoad = 6.0 mA) PC0–PC1
Input High Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ,
RESET, OSC1
Input Low Voltage
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7, IRQ,
RESET, OSC1
Supply Current
Run (Note 3)
Wait (Note 4)
Stop (Note 5)
25 °C
0 °C to +70 °C (Standard)
–40 °C to +85 °C (Extended)
–40 °C to +105 °C (V)
I/O Ports Hi-Z Leakage Current
PA0–PA7, PB5–PB7, PC0–PC7, PD5, TCAP/PD7
I/O Pullup Current
PA0–PA7
Input Current
RESET, IRQ, OSC1
Capacitance
Ports (as Input or Output)
RESET, IRQ
Input Pullup Current (Pullup Device On)
PA7–PA0
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
10.8 3.3 Volt DC Electrical Characteristics
R E Q U I R E D
Electrical Specifications
3.3 Volt DC Electrical Characteristics
Freescale Semiconductor, Inc.
800 mV
85
°C
°C
NO
MIN
−4
AL
0°
PR
OC
C
ES
SIN
G
E1
NOT
25
400 mV
300 mV
100 mV
0
−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
0
E2
OT
N
EE
VDD = 3.3 V
S
0
−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
IOH
IOH
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOL = –0.8 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOL = –0.2 mA.
Figure 10-1. PA0–PA7, PB5–PB7, PC2–PC5, PD5, and TCMP
Typical High-Side Driver Characteristics
ING
G
SS
CE
RO
LP
OM
−4
0°
C
°C
°C
N
200 mV
25
C
VOL
0°
−4
INA
SE
2
85
RO
NA
MI
°C
°C
25
200 mV
O
EN
250 mV
NO
85
250 mV
TE
300 mV
LP
300 mV
150 mV
150 mV
100 mV
VDD = 5.0 V
100 mV
VDD = 3.3 V
50 mV
50 mV
0
350 mV
CE
350 mV
400 mV
1
SS
OTE
N
SEE
IN
400 mV
VOL
A G R E E M E N T
Freescale Semiconductor, Inc...
400 mV
200 mV
VDD = 5.0 V
100 mV
N O N - D I S C L O S U R E
500 mV
300 mV
200 mV
0
85 °
C
500 mV
600 mV
25 °C
600 mV
700 mV
VDD – VOH
SEE
700 mV
NOM
INAL
PRO
−40
CES
°C
SING
800 mV
VDD – VOH
R E Q U I R E D
Electrical Specifications
0
2.0 mA
4.0 mA
6.0 mA 8.0 mA 10.0 mA
0
0
2.0 mA
4.0 mA
IOL
6.0 mA 8.0 mA 10.0 mA
IOL
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
Figure 10-2. PA0–PA7, PC2–PC5, PB0–PB5, PD5, and TCMP
Typical Low-Side Driver Characteristics
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
800 mV
400 mV
VDD = 5.0 V
700 mV
SEE NOTE 1
500 mV
85
400 mV
°C
ING
SS
CE
AL
300 mV
MIN
O
PR
−40
O
CN
5°
200 mV
°C
250 mV
200 mV
C
5°
ING
SS
E
OC
R
LP
INA
100 mV
2
°C
85
150 mV
−40
M
NO
°C
2
50 mV
0
−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
0
−0.5 mA
IOH
−1.0 mA
−1.5 mA
IOH
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for (VDD – VOH) ≤ 800 mV @ IOL = –5.0 mA.
2. At VDD = 3.3 V, devices are specified and tested for (VDD – VOH) ≤ 300 mV @ IOL = –1.5 mA.
Figure 10-3. PC0–PC1 Typical High-Side Driver Characteristics
400 mV
400 mV
VDD = 5.0 V
300 mV
VOL
250 mV
8
AL
N
MI
200 mV
°C
25
NG
NO
P
C
RO
0
−4
250 mV
°C
50 mV
50 mV
5.0 mA
10.0 mA
20.0 mA
0
ING
SS
C
O
CN
5°
E
OC
R
LP
A
MIN
150 mV
100 mV
0
°
85
200 mV
100 mV
0
SEE NOTE 2
300 mV
SI
ES
C
5°
150 mV
VDD = 3.3 V
350 mV
VOL
350 mV
SEE NOTE 1
−40
°C
2
0
2.0 mA
4.0 mA
IOL
6.0 mA 8.0 mA 10.0 mA
IOL
NOTES:
1. At VDD = 5.0 V, devices are specified and tested for VOL ≤ 400 mV @ IOL = 20 mA.
2. At VDD = 3.3 V, devices are specified and tested for VOL ≤ 300 mV @ IOL = 6.0 mA.
Figure 10-4. PC0–PC1 Typical Low-Side Driver Characteristics
MC68HC05P1A — Rev. 3.0
General Release Specification
Electrical Specifications
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N O N - D I S C L O S U R E
0
A G R E E M E N T
100 mV
Freescale Semiconductor, Inc...
SEE NOTE 2
300 mV
VDD – VOH
VDD – VOH
600 mV
0
VDD = 3.3 V
350 mV
R E Q U I R E D
Electrical Specifications
3.3 Volt DC Electrical Characteristics
Freescale Semiconductor, Inc.
R E Q U I R E D
Electrical Specifications
4500 µA
5.5 V
SUPPLY CURRENT (IDD)
4000 µA
3500 µA
3000 µA
2500 µA
4.5 V
2000 µA
3.6 V
1500 µA
3.0 V
Freescale Semiconductor, Inc...
A G R E E M E N T
1000 µA
500 µA
0
1.8 V
0
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL OPERATING FREQUENCY (fOP)
Figure 10-5. Typical Operating IDD (25 °C)
3000 µA
SUPPLY CURRENT (IDD)
N O N - D I S C L O S U R E
2500 µA
5.5 V
2000 µA
1500 µA
4.5 V
1000 µA
3.6 V
3.0 V
500 µA
1.8 V
0
0
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL OPERATING FREQUENCY (fOP)
Figure 10-6. Typical Wait Mode IDD (25 °C)
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
Symbol
Min
Max
Unit
Frequency of Operation
Crystal Option
External Clock Option
fosc
—
dc
4.2
4.2
MHz
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fop
—
dc
2.1
2.1
MHz
Cycle Time
tcyc
476
—
ns
Crystal Oscillator Startup Time
tOXOV
—
100
ms
Stop Recovery Startup Time (Crystal Oscillator)
tILCH
—
100
ms
RESET Pulse Width
tRL
1.5
—
tcyc
Interrupt Pulse Width Low (Edge-Triggered)
tILIH
125
—
ns
Interrupt Pulse Period
tILIL
Note 2
—
tcyc
tOH, tOL
200
—
ns
OSC1 Pulse Width
NOTES:
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted
2. The minimum period, tILIL, should not be less than the number of cycles it takes to execute the interrupt service routine
plus 19 tcyc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Characteristic
A G R E E M E N T
10.9 5.0 Volt Control Timing
R E Q U I R E D
Electrical Specifications
5.0 Volt Control Timing
MC68HC05P1A — Rev. 3.0
General Release Specification
Electrical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
10.10 3.3 Volt Control Timing
Characteristic
Symbol
Min
Max
Frequency of Operation
Crystal/Ceramic Resonator (Note 2)
RC Oscillator
External Clock Option
fosc
—
dc
—
2.0
2.0
2.0
Internal Operating Frequency (fosc ÷ 2)
Crystal/Ceramic Oscillator
RC Oscillator
External Clock
fop
—
dc
—
2.1
2.1
2.1
Cycle Time (2 ÷ fosc)
tcyc
1000
—
ns
RESET Pulse Width Low (Edge-Triggered)
tRL
1.5
—
tcyc
tRESL
4.0
—
tcyc
IRQ Interrupt Pulse Width Low (Edge-Triggered)
tILIH
250
—
ns
IRQ Interrupt Pulse Period
tILIL
Note 4
—
tcyc
PA3–PA0 Interrupt Pulse Width High (Edge-Triggered)
tIHIL
250
—
tcyc
PA3–PA0 Interrupt Pulse Period
tIHIH
Note 4
—
tcyc
tOH, tOL
400
—
ns
Time Resolution (Note 3)
OSC1 Pulse Width
Unit
MHz
MHz
NOTES:
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise noted
2. Use only AT-cut crystals.
3. The 2-bit timer prescaler is the limiting factor in determining timer resolution.
4. The minimum period, tILIL or tIHIH, should not be less than the number of cycles it takes to execute the interrupt service
routine plus 19 tcyc.
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
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DD
NEW
PCL
1FFF
tCYC
NEW PC
OP
CODE
NEW PC
NOTE 3
tRL
1FFE
1FFE
1FFE
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
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PCH
1FFE
PCL
1FFF
General Release Specification
N O N - D I S C L O S U R E
A G R E E M E N T
NEW PC
OP
CODE
NEW PC
R E Q U I R E D
Figure 10-7. Power-On Reset and External Reset Timing Diagram
NOTES:
1. Internal timing signal and bus information not available externally.
2. OSC1 line is not meant to represent frequency. It is only used to represent time.
3. The next rising edge of the PH2 clock following the rising edge of RESET initiates the reset sequence.
RESET
NEW
PCH
INTERNAL
DATA
BUS1
4064 tCYC
DD THRESHOLD (1-2 V TYPICAL)
1FFE
V
INTERNAL
ADDRESS
BUS1
INTERNAL
PROCESSOR
CLOCK1
OSC12
V
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Electrical Specifications
3.3 Volt Control Timing
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Electrical Specifications
General Release Specification
MC68HC05P1A — Rev. 3.0
Electrical Specifications
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
11.1 Contents
11.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
11.3
Dual In-Line Package (Case 710). . . . . . . . . . . . . . . . . . . . . .107
11.4
Small Outline Integrated Circuit (Case 751F) . . . . . . . . . . . . .108
11.2 Introduction
This section gives the dimensions of the dual in-line package (DIP) and
the small outline integrated circuit (SOIC) package.
11.3 Dual In-Line Package (Case 710)
28
! ! ! #! %% !
$" ! ! ! ! ! !
! ! # ! "
15
B
1
14
A
L
C
N
H
G
F
D
K
M
J
MC68HC05P1A — Rev. 3.0
°
°
°
°
General Release Specification
Mechanical Specifications
For More Information On This Product,
Go to: www.freescale.com
A G R E E M E N T
Section 11. Mechanical Specifications
N O N - D I S C L O S U R E
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
R E Q U I R E D
Mechanical Specifications
11.4 Small Outline Integrated Circuit (Case 751F)
-A28
! ! % ! !
! " !" $" !" ! "
!" #
!" !! $ ! $" !
!
15
14X
-B1
P
14
28X D
!
M
C
-T26X
-T-
G
K
F
J
°
°
°
°
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R X 45°
General Release Specification
MC68HC05P1A — Rev. 3.0
Mechanical Specifications
For More Information On This Product,
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Freescale Semiconductor, Inc...
12.1 Contents
12.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.3
MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
12.4
Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.5
ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.6
ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .112
12.7
MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
12.2 Introduction
This section contains instructions for ordering custom-masked ROM
MCUs.
12.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Freescale representative. Submit these
items when ordering MCUs:
•
A current MCU ordering form that is completely filled out
(Contact your Freescale sales office for assistance.)
•
A copy of the customer specification if the customer specification
deviates from the Freescale specification for the MCU
•
Customer’s application program on one of the media listed in 12.4
Application Program Media
MC68HC05P1A — Rev. 3.0
General Release Specification
Ordering Information
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A G R E E M E N T
Section 12. Ordering Information
N O N - D I S C L O S U R E
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
The current MCU ordering form is also available through the Freescale
Freeware Bulletin Board Service (BBS). The telephone number is (512)
891-FREE. After making the connection, type bbs in lower-case letters.
Then press the return key to start the BBS software.
12.4 Application Program Media
Please deliver the application program to Freescale in one of the following
media:
•
Macintosh1 3 1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
•
MS-DOS2 or PC-DOSTM3 3 1/2-inch diskette (double-sided
720 K or double-sided high-density 1.44 M)
•
MS-DOS or PC-DOSTM 5 1/4-inch diskette (double-sided doubledensity 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with this information:
•
Customer name
•
Customer part number
•
Project or product name
•
File name of object code
•
Date
•
Name of operating system that formatted diskette
•
Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
General Release Specification
MC68HC05P1A — Rev. 3.0
Ordering Information
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Freescale Semiconductor, Inc...
If the memory map has two user ROM areas with the same address,
then write the two areas in separate files on the diskette. Label the
diskette with both file names.
In addition to the object code, a file containing the source code can be
included. Freescale keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the file name of the source code.
12.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Freescale inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Freescale sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Freescale will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Freescale. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
MC68HC05P1A — Rev. 3.0
General Release Specification
Ordering Information
For More Information On This Product,
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A G R E E M E N T
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. Refer to the current
MCU ordering form for additional requirements.Freescale may request
pattern re-submission if non-user areas contain any non-zero code.
N O N - D I S C L O S U R E
NOTE:
R E Q U I R E D
Ordering Information
ROM Program Verification
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
Ordering Information
12.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Freescale manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
application program cannot be changed after the manufacture of the
mask begins. Freescale then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Freescale Quality Assurance.
12.7 MC Order Numbers
Table 12-1 shows the MC order numbers for the available package
types.
Table 12-1. MC Order Numbers
Package Type
Temperature
MC Order Number
28-Pin Plastic Dual In-Line
Package (DIP)
0 °C to +70 °C
MC68HC05P1AP
28-Pin Small Outline Integrated
Circuit (SOIC)
0 °C to +70 °C
MC68HC05P1ADW
General Release Specification
MC68HC05P1A — Rev. 3.0
Ordering Information
For More Information On This Product,
Go to: www.freescale.com
Appendix A. MC68HCL05P1A
A.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
A.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .114
A.4
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
A.2 Introduction
This appendix introduces the MC68HCL05P1A, a low-power version of
the MC68HC05P1A. All of the information in this document applies to the
MC68HCL05P1A with the exceptions given in this appendix.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A.1 Contents
A G R E E M E N T
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
MC68HC05P1A — Rev. 3.0
General Release Specification
MC68HCL05P1A
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
A.3 DC Electrical Characteristics
The data in 10.7 5.0 Volt DC Electrical Characteristics and
10.8 3.3 Volt DC Electrical Characteristics applies to the
MC68HCL05P1A with the exceptions given in Table A-1, Table A-2,
and Table A-3.
Table A-1. Low-Power Output Voltage (VDD = 1.8–2.4 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage (ILoad = –0.1 mA)
PA0–PA7, PB5–PB7, PC2–PC7, PD5, TCMP
VOH
VDD –0.3
—
—
V
Output Low Voltage (ILoad = 0.2 mA)
PA0–PA3, PB5–PB7, PC2–PC7, PD5, TCMP
VOL
—
—
0.3
V
Table A-2. Low-Power Output Voltage (VDD = 2.5–3.6 Vdc)
Characteristic
Symbol
Min
Typ
Max
Unit
Output High Voltage (ILoad = –0.2 mA)
PA0–PA7, PB5–PB7, PC2–PC7, PD5, TCMP
VOH
VDD –0.3
—
—
V
Output Low Voltage (ILoad = 0.4 mA)
PA0–PA3, PB5–PB7, PC2–PC7, PD5, TCMP
VOL
—
—
0.3
V
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
MC68HCL05P1A
General Release Specification
MC68HC05P1A — Rev. 3.0
MC68HCL05P1A
For More Information On This Product,
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Freescale Semiconductor, Inc...
Supply Current (VDD = 4.5–5.5 Vdc, fop = 2.1 MHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to +70 °C (Standard)
Supply Current (VDD = 2.5–3.6 Vdc, fop = 1.0 MHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to +70 °C (Standard)
Supply Current (VDD = 2.5-3.6 Vdc, fop = 500 kHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to +70 °C (Standard)
Supply Current (VDD = 1.8-2.4 Vdc, fop = 500 kHz)
Run (Note 2)
Wait (Note 3)
Stop (Note 4)
25 °C
0 °C to +70 °C (Standard)
Symbol
IDD
IDD
IDD
IDD
Min
Typ(1)
Max
Unit
—
—
3.0
1.6
4.25
2.25
mA
mA
—
—
0.5
2.0
15
25
µA
µA
—
—
1.0
0.7
1.6
1.0
mA
mA
—
—
0.2
2.0
5.0
10.0
µA
µA
—
—
600
350
800
500
—
—
0.2
2.0
5.0
10.0
—
—
300
200
600
400
—
—
0.1
2.0
2
5
µA
µA
NOTES:
1. Typical values reflect average measurements at midpoint of voltage range at 25 °C.
2. Run (operating) IDD and wait IDD measured using external square wave clock source with all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
3. Wait IDD measured using external square wave clock source with all inputs 0.2 V from rail, no dc loads, less than
50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD –0.2 V. OSC2
capacitance linearly affects wait IDD.
4. Stop IDD measured with OSC1 = VSS. All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
MC68HC05P1A — Rev. 3.0
General Release Specification
MC68HCL05P1A
For More Information On This Product,
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A G R E E M E N T
Characteristic
N O N - D I S C L O S U R E
Table A-3. Low-Power Supply Current
R E Q U I R E D
MC68HCL05P1A
Freescale Semiconductor, Inc.
R E Q U I R E D
MC68HCL05P1A
1.6
1.4
VDD = 2.5 to 3.6 V
VDD = 1.8 to 2.4 V
RUN IDD (mA)
1.2
1.0
0.8
0.6
Freescale Semiconductor, Inc...
A G R E E M E N T
0.4
0.2
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0.9
1.0
INTERNAL CLOCK FREQUENCY (MHz)
Figure A-1. Maximum Run Mode IDD versus
Internal Clock Frequency
1.0
N O N - D I S C L O S U R E
0.9
VDD = 2.5 to 3.6 V
VDD = 1.8 to 2.4 V
0.8
WAIT IDD (mA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
INTERNAL CLOCK FREQUENCY (MHz)
Figure A-2. Maximum Wait Mode IDD versus
Internal Clock Frequency
General Release Specification
MC68HC05P1A — Rev. 3.0
MC68HCL05P1A
For More Information On This Product,
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Freescale Semiconductor, Inc.
A.4 MC Ordering Information
Table A-4 provides ordering information for available package types.
Temperature
MC Order Number
28-Pin Plastic Dual In-Line
Package (DIP)
0 °C to +70 °C
MC68HCL05P1AP
28-Pin Small Outline Integrated
Circuit (SOIC)
0 °C to +70 °C
MC68HCL05P1ADW
A G R E E M E N T
Package Type
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
Table A-4. MC Order Numbers
R E Q U I R E D
MC68HCL05P1A
MC68HC05P1A — Rev. 3.0
General Release Specification
MC68HCL05P1A
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
MC68HCL05P1A
General Release Specification
MC68HC05P1A — Rev. 3.0
MC68HCL05P1A
For More Information On This Product,
Go to: www.freescale.com
Appendix B. MC68HSC05P1A
B.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
B.3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .120
B.4
Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
B.5
MC Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
B.2 Introduction
This appendix introduces the MC68HSC05P1A, a high-speed version of
the MC68HC05P1A. All of the information in this document applies to the
MC68HCSC05P1A with the exceptions given in this appendix.
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
B.1 Contents
A G R E E M E N T
General Release Specification — MC68HC05P1A
R E Q U I R E D
Freescale Semiconductor, Inc.
MC68HC05P1A — Rev. 3.0
General Release Specification
MC68HSC05P1A
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
R E Q U I R E D
MC68HSC05P1A
B.3 DC Electrical Characteristics
The data in 10.7 5.0 Volt DC Electrical Characteristics and
10.8 3.3 Volt DC Electrical Characteristics applies to the
MC68HSC05P1A with the exceptions given in Table B-1.
Table B-1. High-Speed Supply Current
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
Characteristic
Symbol
Min
Supply Current (VDD = 4.5–5.5 Vdc, fop = 4.0 MHz)
Run (Note 3)
Wait (Note 4)
Stop (Note 5)
IDD
—
—
Supply Current (VDD = 3.0–3.6 Vdc, fop = 2.1 MHz)
Rum (Note 3)
Wait (Note 4)
Stop (Note 5)
IDD
—
—
—
—
Typ
(Note 1)
6.0
3.5
2.0
2.5
1.3
2.0
Max
Unit
7.0
3.5
20
mA
mA
µA
3.5
2.5
10
mA
mA
µA
NOTES:
1. TA = 0 °C to 70 °C
2. Typical values at midpoint of voltage range, 25 °C only.
3. Run (Operating) IDD and wait IDD measured using external square wave clock source with all inputs 0.2 V from rail;
no dc loads, less than 50 pF on all outputs, CL = 20 pF on OSC2.
4. Wait IDD measured using external square wave clock source with all inputs 0.2 V from rail, no dc loads, less than
50 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. VIL = 0.2 V, VIH = VDD –0.2 V. OSC2
capacitance linearly affects wait IDD.
5. Stop IDD measured with OSC1 = VSS. All ports configured as inputs, VIL = 0.2 V, VIH = VDD –0.2 V.
General Release Specification
MC68HC05P1A — Rev. 3.0
MC68HSC05P1A
For More Information On This Product,
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Freescale Semiconductor, Inc.
Table B-2. High-Speed Control Timing (VDD = 5.0 Vdc ± 10%)
Freescale Semiconductor, Inc...
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal Option
External Clock Option
fosc
—
dc
8.0
8.0
MHz
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fop
—
dc
4.0
4.0
MHz
Internal Clock Cycle Time
tcyc
250
—
ns
Input Capture Pulse Width
tTH, tTL
63
—
ns
tILIH
63
—
ns
tOH, tOL
45
—
ns
Interrupt Pulse Width Low (Edge-Triggered)
OSC1 Pulse Width
Table B-3. High-Speed Control Timing (VDD = 3.3 Vdc ± 10%)
Characteristic
Symbol
Min
Max
Unit
Oscillator Frequency
Crystal Option
External Clock Option
fosc
—
dc
4.2
4.2
MHz
Internal Operating Frequency
Crystal (fosc ÷ 2)
External Clock (fosc ÷ 2)
fop
—
dc
2.1
2.1
MHz
Internal Clock Cycle Time
tcyc
480
—
ns
Input Capture Pulse Width
tTH, tTL
125
—
ns
tILIH
125
—
ns
tOH, tOL
90
—
ns
Interrupt Pulse Width Low (Edge-Triggered)
OSC1 Pulse Width
MC68HC05P1A — Rev. 3.0
General Release Specification
MC68HSC05P1A
For More Information On This Product,
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A G R E E M E N T
The data in 10.9 5.0 Volt Control Timing and 10.10 3.3 Volt Control
Timing applies to the MC68HSC05P1A with the exceptions given in
Table B-2 and Table B-3.
N O N - D I S C L O S U R E
B.4 Control Timing
R E Q U I R E D
MC68HSC05P1A
Freescale Semiconductor, Inc.
B.5 MC Ordering Information
Table B-4 provides ordering information for available package types.
Table B-4. MC Order Numbers
Package Type
Temperature
MC Order Number
28-Pin Plastic Dual In-Line
Package (DIP)
0 °C to +70 °C
MC68HSC05P1AP
28-Pin Small Outline Integrated
Circuit (SOIC)
0 °C to +70 °C
MC68HSC05P1ADW
N O N - D I S C L O S U R E
Freescale Semiconductor, Inc...
A G R E E M E N T
R E Q U I R E D
MC68HSC05P1A
General Release Specification
MC68HC05P1A — Rev. 3.0
MC68HSC05P1A
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
For More Information On This Product,
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Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Home Page:
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email:
[email protected]
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Technical Information Center
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81829 Muenchen, Germany
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+33 1 69 35 48 48 (French)
[email protected]
Japan:
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Headquarters
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Tokyo 153-0064, Japan
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Technical Information Center
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Tai Po, N.T., Hong Kong
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[email protected]
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