NXP 68HC05X32 Microcontroller Data Sheet

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TECHNICAL DATA
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MC68HC05X16
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MC68HC05X16/D
Rev. 1
HC05
MC68HC05X16
MC68HC05X32
MC68HC705X32
TECHNICAL
DATA
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INTRODUCTION
1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
MEMORY AND REGISTERS
3
INPUT/OUTPUT PORTS
4
MOTOROLA CAN MODULE (MCAN)
5
PROGRAMMABLE TIMER
6
SERIAL COMMUNICATIONS INTERFACE
7
PULSE LENGTH D/A CONVERTERS
8
ANALOG TO DIGITAL CONVERTER
9
RESETS AND INTERRUPTS
10
CPU CORE AND INSTRUCTION SET
11
ELECTRICAL SPECIFICATIONS
12
MECHANICAL DATA
13
ORDERING INFORMATION
14
APPENDICES
15
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1
INTRODUCTION
2
MODES OF OPERATION AND PIN DESCRIPTIONS
3
MEMORY AND REGISTERS
4
INPUT/OUTPUT PORTS
5
MOTOROLA CAN MODULE (MCAN)
6
PROGRAMMABLE TIMER
7
SERIAL COMMUNICATIONS INTERFACE
8
PULSE LENGTH D/A CONVERTERS
9
ANALOG TO DIGITAL CONVERTER
10
RESETS AND INTERRUPTS
11
CPU CORE AND INSTRUCTION SET
12
ELECTRICAL SPECIFICATIONS
13
MECHANICAL DATA
14
ORDERING INFORMATION
15
APPENDICES
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MC68HC05X16
MC68HC05X32
MC68HC705X32
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High-density complementary
metal oxide semiconductor
(HCMOS) microcontroller unit
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Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are defined in the
paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, a shaded cell in a register diagram indicates that the bit is
either unused or reserved; ‘u’ is used to indicate an undefined state (on reset).
Unless otherwise stated, a pin labelled as ‘NU’ should be tied to VSS in an electrically
noisy environment. Pins labelled ‘NC’ can be left floating, since they are not bonded
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SECTION 1
INTRODUCTION
SECTION 2
MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3
MEMORY AND REGISTERS
SECTION 4
INPUT/OUTPUT PORTS
SECTION 5
MOTOROLA CAN MODULE (MCAN)
SECTION 6
PROGRAMMABLE TIMER
SECTION 7
SERIAL COMMUNICATIONS INTERFACE
SECTION 8
PULSE LENGTH D/A CONVERTERS
SECTION 9
ANALOG TO DIGITAL CONVERTER
SECTION 10
RESETS AND INTERRUPTS
SECTION 11
CPU CORE AND INSTRUCTION SET
SECTION 12
ELECTRICAL SPECIFICATIONS
SECTION 13
MECHANICAL DATA
SECTION 14
ORDERING INFORMATION
SECTION 15
APPENDICES
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TABLE OF CONTENTS
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Paragraph
Number
TITLE
Page
Number
1
INTRODUCTION
1.1
1.2
Features ................................................................................................................ 1-2
Mask options for the MC68HC05X16 .................................................................... 1-3
2
MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1
Modes of operation................................................................................................ 2-1
2.1.1
Single-chip mode ............................................................................................. 2-1
2.1.2
Bootstrap mode ............................................................................................... 2-2
2.1.2.1
Serial RAM loader ...................................................................................... 2-3
2.1.2.2
Jump to RAM + 1 ....................................................................................... 2-3
2.1.2.3
‘Jump to any address’ ................................................................................ 2-3
2.2
Low power modes ................................................................................................. 2-6
2.2.1
STOP mode ..................................................................................................... 2-6
2.2.2
WAIT mode ...................................................................................................... 2-7
2.2.2.1
Power consumption during WAIT mode ..................................................... 2-8
2.2.3
SLOW mode .................................................................................................... 2-8
2.2.3.1
Miscellaneous register .............................................................................. 2-10
2.3
Pin descriptions ..................................................................................................... 2-11
2.3.1
VDD and VSS .................................................................................................. 2-11
2.3.2
IRQ .................................................................................................................. 2-11
2.3.3
RESET............................................................................................................. 2-11
2.3.4
MDS................................................................................................................. 2-12
2.3.5
TCAP1 ............................................................................................................. 2-12
2.3.6
TCAP2 ............................................................................................................. 2-12
2.3.7
TCMP1............................................................................................................. 2-12
2.3.8
TCMP2............................................................................................................. 2-12
2.3.9
RDI (Receive data in)....................................................................................... 2-12
2.3.10
TDO (Transmit data out) .................................................................................. 2-12
2.3.11
SCLK ............................................................................................................... 2-13
MC68HC05X16
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2.3.12
2.3.12.1
2.3.12.2
2.3.12.3
2.3.12.4
2.3.13
2.3.14
2.3.15
2.3.16
2.3.17
2.3.18
2.3.19
2.3.20
2.3.21
2.3.22
2.3.23
2.3.24
2.3.25
TITLE
Page
Number
OSC1, OSC2 ................................................................................................... 2-13
Crystal........................................................................................................ 2-13
Ceramic resonator ..................................................................................... 2-13
External clock............................................................................................. 2-13
Oscillator division ....................................................................................... 2-15
PLMA ............................................................................................................... 2-15
PLMB ............................................................................................................... 2-15
VPP1 ............................................................................................................... 2-16
VRH ................................................................................................................. 2-16
VRL.................................................................................................................. 2-16
PA0 – PA7/PB0 – PB7/PC0 – PC7 .................................................................. 2-16
NWOI ............................................................................................................... 2-16
PD0/AN0–PD7/AN7......................................................................................... 2-16
VDD1 ............................................................................................................... 2-17
VSS1 ............................................................................................................... 2-17
VDDH .............................................................................................................. 2-17
RX0/RX1.......................................................................................................... 2-17
TX0/TX1 .......................................................................................................... 2-17
3
MEMORY AND REGISTERS
3.1
3.2
3.3
3.4
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.7
3.8
Registers ............................................................................................................... 3-1
RAM ...................................................................................................................... 3-1
ROM ...................................................................................................................... 3-1
Bootstrap ROM...................................................................................................... 3-3
EEPROM............................................................................................................... 3-4
EEPROM control register ................................................................................ 3-4
EEPROM read operation ................................................................................. 3-6
EEPROM erase operation ............................................................................... 3-6
EEPROM programming operation ................................................................... 3-7
Options register (OPTR) .................................................................................. 3-7
EEPROM during STOP mode ............................................................................... 3-8
EEPROM during WAIT mode ................................................................................ 3-8
Miscellaneous register.......................................................................................... 3-11
4
INPUT/OUTPUT PORTS
4.1
4.2
4.3
4.4
4.5
Input/output programming ..................................................................................... 4-1
Ports A and B ........................................................................................................ 4-2
Port C .................................................................................................................... 4-3
Port D .................................................................................................................... 4-4
Port registers ......................................................................................................... 4-4
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Paragraph
Number
TITLE
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Number
4.5.1
Port data registers A and B (PORTA and PORTB) .......................................... 4-4
4.5.2
Port data register C (PORTC).......................................................................... 4-5
4.5.3
Port data register D (PORTD).......................................................................... 4-5
4.5.4
A/D status/control register ............................................................................... 4-5
4.5.5
Data direction registers (DDRA, DDRB and DDRC)........................................ 4-6
4.6
Other port considerations ...................................................................................... 4-6
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5
MOTOROLA CAN MODULE (MCAN)
5.1
TBF – Transmit buffer ............................................................................................ 5-4
5.2
RBF – Receive buffer ............................................................................................ 5-4
5.3
Interface to the MC68HC05X16 CPU.................................................................... 5-4
5.3.1
MCAN control register (CCNTRL) ................................................................... 5-6
5.3.2
MCAN command register (CCOM) .................................................................. 5-7
5.3.3
MCAN status register (CSTAT) ........................................................................ 5-10
5.3.4
MCAN interrupt register (CINT) ....................................................................... 5-12
5.3.5
MCAN acceptance code register (CACC)........................................................ 5-13
5.3.6
MCAN acceptance mask register (CACM) ...................................................... 5-14
5.3.7
MCAN bus timing register 0 (CBT0) ................................................................ 5-14
5.3.8
MCAN bus timing register 1 (CBT1) ................................................................ 5-16
5.3.9
MCAN output control register (COCNTRL)...................................................... 5-18
5.3.10
Transmit buffer identifier register (TBI)............................................................. 5-20
5.3.11
Remote transmission request and data length code register (TRTDL)............ 5-20
5.3.12
Transmit data segment registers (TDS) 1 – 8 .................................................. 5-21
5.3.13
Receive buffer identifier register (RBI) ............................................................. 5-21
5.3.14
Remote transmission request and data length code register (RRTDL) ........... 5-22
5.3.15
Receive data segment registers (RDS) 1 – 8 .................................................. 5-22
5.4
Interface to the MCAN bus .................................................................................... 5-22
5.4.1
Single wire operation ....................................................................................... 5-24
5.5
Sleep mode ........................................................................................................... 5-24
5.5.1
Sleep comparator reference ............................................................................ 5-25
6
PROGRAMMABLE TIMER
6.1
Counter.................................................................................................................. 6-1
6.1.1
Counter register and alternate counter register ............................................... 6-3
6.2
Timer control and status ........................................................................................ 6-4
6.2.1
Timer control register (TCR) ............................................................................ 6-4
6.2.2
Timer status register (TSR) ............................................................................. 6-6
6.3
Input capture.......................................................................................................... 6-7
6.3.1
Input capture register 1 (ICR1) ........................................................................ 6-7
6.3.2
Input capture register 2 (ICR2) ........................................................................ 6-8
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6.4
6.4.1
6.4.2
6.4.3
6.5
6.5.1
6.6
6.7
6.8
TITLE
Page
Number
Output compare..................................................................................................... 6-9
Output compare register 1 (OCR1) ................................................................. 6-9
Output compare register 2 (OCR2) ................................................................. 6-10
Software force compare................................................................................... 6-11
Pulse length modulation (PLM) ............................................................................. 6-11
Pulse length modulation registers A and B (PLMA/PLMB).............................. 6-11
Timer during STOP mode ..................................................................................... 6-12
Timer during WAIT mode ...................................................................................... 6-12
Timer state diagrams............................................................................................. 6-12
7
SERIAL COMMUNICATIONS INTERFACE
7.1
SCI two-wire system features................................................................................ 7-1
7.2
SCI receiver features............................................................................................. 7-3
7.3
SCI transmitter features......................................................................................... 7-3
7.4
Functional description ........................................................................................... 7-3
7.5
Data format............................................................................................................ 7-5
7.6
Receiver wake-up operation.................................................................................. 7-5
7.6.1
Idle line wake-up.............................................................................................. 7-6
7.6.2
Address mark wake-up .................................................................................... 7-6
7.7
Receive data in (RDI) ............................................................................................ 7-6
7.8
Start bit detection .................................................................................................. 7-6
7.9
Transmit data out (TDO)........................................................................................ 7-8
7.10 SCI synchronous transmission.............................................................................. 7-9
7.11 SCI registers.......................................................................................................... 7-10
7.11.1
Serial communications data register (SCDR) .................................................. 7-10
7.11.2
Serial communications control register 1 (SCCR1) ......................................... 7-10
7.11.3
Serial communications control register 2 (SCCR2) ......................................... 7-14
7.11.4
Serial communications status register (SCSR) ............................................... 7-16
7.11.5
Baud rate register (BAUD) ............................................................................... 7-18
7.12 Baud rate selection................................................................................................ 7-20
7.13 SCI during STOP mode......................................................................................... 7-21
7.14 SCI during WAIT mode.......................................................................................... 7-21
8
PULSE LENGTH D/A CONVERTERS
8.1
8.2
8.3
8.4
Miscellaneous register........................................................................................... 8-3
PLM clock selection............................................................................................... 8-4
PLM during STOP mode ....................................................................................... 8-4
PLM during WAIT mode ........................................................................................ 8-4
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Paragraph
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Number
9
ANALOG TO DIGITAL CONVERTER
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9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
A/D converter operation......................................................................................... 9-1
A/D registers.......................................................................................................... 9-3
Port D data register (PORTD).......................................................................... 9-3
A/D result data register (ADDATA) ................................................................... 9-3
A/D status/control register (ADSTAT)............................................................... 9-4
A/D converter during STOP mode......................................................................... 9-5
A/D converter during WAIT mode.......................................................................... 9-6
Port D analog input................................................................................................ 9-6
10
RESETS AND INTERRUPTS
10.1 Resets ................................................................................................................. 10-1
10.1.1
Power-on reset............................................................................................... 10-2
10.1.2
Miscellaneous register .................................................................................. 10-2
10.1.3
RESET pin ..................................................................................................... 10-3
10.1.4
Computer operating properly (COP) watchdog reset .................................... 10-3
10.1.4.1
COP watchdog during STOP mode ......................................................... 10-5
10.1.4.2
COP watchdog during WAIT mode .......................................................... 10-5
10.1.5
Functions affected by reset............................................................................ 10-5
10.2 Interrupts ............................................................................................................. 10-7
10.2.1
Interrupt priorities........................................................................................... 10-9
10.2.2
Nonmaskable software interrupt (SWI) .......................................................... 10-9
10.2.3
Maskable hardware interrupts........................................................................ 10-9
10.2.3.1
Miscellaneous register ............................................................................. 10-10
10.2.3.2
External interrupts.................................................................................... 10-11
10.2.3.3
MCAN interrupt (CIRQ) ............................................................................ 10-11
10.2.3.4
Timer interrupts ........................................................................................ 10-12
10.2.3.5
Serial communications interface (SCI) interrupts..................................... 10-12
10.2.4
Hardware controlled interrupt sequence........................................................ 10-13
11
CPU CORE AND INSTRUCTION SET
11.1 Registers ............................................................................................................. 11-1
11.1.1
Accumulator (A) ............................................................................................. 11-1
11.1.2
Index register (X) ........................................................................................... 11-2
11.1.3
Program counter (PC).................................................................................... 11-2
11.1.4
Stack pointer (SP).......................................................................................... 11-2
11.1.5
Condition code register (CCR)....................................................................... 11-2
11.2 Instruction set ...................................................................................................... 11-3
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11.2.1
Register/memory Instructions........................................................................ 11-4
11.2.2
Branch instructions ........................................................................................ 11-4
11.2.3
Bit manipulation instructions.......................................................................... 11-4
11.2.4
Read/modify/write instructions....................................................................... 11-4
11.2.5
Control instructions........................................................................................ 11-4
11.2.6
Tables ............................................................................................................ 11-4
11.3 Addressing modes............................................................................................... 11-11
11.3.1
Inherent ......................................................................................................... 11-11
11.3.2
Immediate ...................................................................................................... 11-11
11.3.3
Direct ............................................................................................................. 11-11
11.3.4
Extended ....................................................................................................... 11-12
11.3.5
Indexed, no offset .......................................................................................... 11-12
11.3.6
Indexed, 8-bit offset ....................................................................................... 11-12
11.3.7
Indexed, 16-bit offset ..................................................................................... 11-12
11.3.8
Relative.......................................................................................................... 11-13
11.3.9
Bit set/clear .................................................................................................... 11-13
11.3.10 Bit test and branch......................................................................................... 11-13
12
ELECTRICAL SPECIFICATIONS
12.1
12.2
12.3
12.4
12.5
12.6
Absolute maximum ratings .................................................................................. 12-1
DC electrical characteristics ............................................................................... 12-2
A/D converter characteristics .............................................................................. 12-4
Control timing ...................................................................................................... 12-5
MCAN bus interface DC electrical characteristics ............................................... 12-6
MCAN bus interface control timing characteristics .............................................. 12-6
13
MECHANICAL DATA
13.1
13.2
64-pin quad flat pack (QFP) pinout ..................................................................... 13-1
64-pin quad flat pack (QFP) mechanical dimensions.......................................... 13-2
14
ORDERING INFORMATION
14.1
14.2
14.3
EPROMS............................................................................................................. 14-2
Verification media ................................................................................................ 14-2
ROM verification units (RVU) .............................................................................. 14-2
TABLE OF CONTENTS
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Paragraph
Number
TITLE
Page
Number
A
MC68HC05X32
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A.1
A.2
A.3
A.3.1
A.3.2
A.3.3
A.3.4
A.3.5
A.3.6
Features ................................................................................................................A-1
Memory map, register outline and block diagram..................................................A-2
Electrical specifications .........................................................................................A-6
Maximum ratings..............................................................................................A-6
DC electrical characteristics ...........................................................................A-7
A/D converter characteristics...........................................................................A-9
Control timing...................................................................................................A-10
MCAN bus interface DC electrical characteristics .................................................A-11
MCAN bus interface control timing characteristics ................................................A-12
B
MC68HC705X32
B.1
Features ................................................................................................................B-2
B.2
VPP6 .....................................................................................................................B-2
B.3
CANE.....................................................................................................................B-2
B.4
Block diagram, memory map and register outline .................................................B-3
B.5
EPROM .................................................................................................................B-7
B.5.1
EPROM read operation....................................................................................B-7
B.5.2
EPROM program operation .............................................................................B-8
B.5.3
EPROM/EEPROM/ECLK control register ........................................................B-8
B.6
EEPROM options register (OPTR) ........................................................................B-11
B.7
Mask option register (MOR) ..................................................................................B-12
B.8
Bootstrap mode .....................................................................................................B-14
B.8.1
Erased EPROM verification and EEPROM erasure ........................................B-17
B.8.2
EPROM/EEPROM parallel bootstrap...............................................................B-17
B.8.3
Serial RAM loader............................................................................................B-20
B.8.3.1
Jump to start of RAM ($0051) ....................................................................B-20
B.9
Electrical specifications .........................................................................................B-23
B.9.1
Maximum ratings..............................................................................................B-23
B.9.2
DC electrical characteristics ............................................................................B-24
B.9.3
EPROM electrical characteristics ....................................................................B-26
B.9.4
Control timing...................................................................................................B-27
B.9.5
A/D converter characteristics...........................................................................B-28
B.9.6
MCAN bus interface DC electrical characteristics ...........................................B-29
B.9.7
MCAN bus interface control timing characteristics ..........................................B-29
MC68HC05X16
TABLE OF CONTENTS
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Paragraph
Number
TITLE
Page
Number
C
MC68HC05X32
HIGH SPEED OPERATION
C.1
C.2
DC electrical characteristics ..................................................................................C-1
Control Timing .......................................................................................................C-2
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MC68HC05X16
Rev. 1
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LIST OF FIGURES
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Figure
Number
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
3-1
3-2
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
6-1
6-2
6-3
6-4
6-5
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
TITLE
Page
Number
MC68HC05X16 block diagram ............................................................................... 1-4
Bootstrap mode function selection flow chart......................................................... 2-2
MC68HC05X16 ‘jump to any address’ schematic diagram..................................... 2-4
MC68HC05X16 ‘load program in RAM and execute’ schematic diagram............... 2-5
STOP and WAIT flow charts................................................................................... 2-9
Slow mode divider block diagram ........................................................................... 2-10
Oscillator connections ............................................................................................ 2-14
Oscillator divider block diagram.............................................................................. 2-15
Memory map of the MC68HC05X16 ...................................................................... 3-2
MCAN module memory map .................................................................................. 3-3
Standard I/O port structure..................................................................................... 4-2
ECLK timing diagram ............................................................................................. 4-3
Port logic levels ...................................................................................................... 4-7
MCAN block diagram.............................................................................................. 5-1
MCAN frame formats.............................................................................................. 5-2
MCAN module memory map .................................................................................. 5-5
Oscillator block diagram ......................................................................................... 5-15
Segments within the bit time .................................................................................. 5-16
A typical physical interface between the MCAN and the MCAN bus lines ............. 5-23
16-bit programmable timer block diagram .............................................................. 6-2
Timer state timing diagram for reset....................................................................... 6-13
Timer state timing diagram for input capture .......................................................... 6-13
Timer state timing diagram for output compare...................................................... 6-14
Timer state timing diagram for timer overflow......................................................... 6-14
Serial communications interface block diagram ..................................................... 7-2
SCI rate generator division ..................................................................................... 7-4
Data format............................................................................................................. 7-5
SCI examples of start bit sampling technique ........................................................ 7-7
SCI sampling technique used on all bits ................................................................ 7-7
Artificial start following a framing error ................................................................... 7-8
SCI start bit following a break................................................................................. 7-8
SCI example of synchronous and asynchronous transmission .............................. 7-9
SCI data clock timing diagram (M=0) ..................................................................... 7-12
MC68HC05X16
LIST OF FIGURES
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Figure
Number
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7-10
8-1
8-2
8-3
9-1
9-2
10-1
10-2
10-3
10-4
11-1
11-2
12-1
13-1
13-2
A-1
A-2
A-3
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
TITLE
Page
Number
SCI data clock timing diagram (M=1) ......................................................................7-13
PLM system block diagram .....................................................................................8-1
PLM output waveform examples .............................................................................8-2
PLM clock selection ................................................................................................8-4
A/D converter block diagram ...................................................................................9-2
Electrical model of an A/D input pin ........................................................................9-6
Reset timing diagram ............................................................................................10-1
RESET external RC pull-down ..............................................................................10-3
Watchdog system block diagram...........................................................................10-4
Interrupt flow chart ................................................................................................10-8
Programming model ..............................................................................................11-1
Stacking order .......................................................................................................11-2
Timer relationship..................................................................................................12-5
64-pin QFP pinout .................................................................................................13-1
64-pin QFP mechanical dimensions .....................................................................13-2
MC68HC05X32 block diagram............................................................................... A-2
Memory map of the MC68HC05X32 ...................................................................... A-3
Timer relationship................................................................................................... A-11
MC68HC705X32 block diagram............................................................................. B-3
Memory map of the MC68HC705X32 .................................................................... B-5
Modes of operation flow chart ................................................................................ B-15
Timing diagram with handshake............................................................................. B-18
Parallel EPROM loader timing diagram.................................................................. B-18
EPROM parallel bootstrap schematic diagram ...................................................... B-19
RAM load and execute schematic diagram ............................................................ B-21
Parallel RAM loader timing diagram ....................................................................... B-22
Timer relationship................................................................................................... B-27
LIST OF FIGURES
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LIST OF TABLES
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Table
Number
1-1
2-1
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
5-5
5-6
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
9-1
9-2
10-1
10-2
10-3
11-1
11-2
11-3
11-4
11-5
11-6
TITLE
Page
Number
Data sheet appendices........................................................................................... 1-1
Mode of operation selection ................................................................................... 2-1
EEPROM control bits description ........................................................................... 3-6
MC68HC05X16 register outline.............................................................................. 3-9
MCAN register outline ............................................................................................ 3-10
IRQ and WOI sensitivity ......................................................................................... 3-11
I/O pin states .......................................................................................................... 4-2
Synchronization jump width.................................................................................... 5-15
Baud rate prescaler ................................................................................................ 5-15
Time segment values ............................................................................................. 5-17
Output control modes ............................................................................................. 5-18
MCAN driver output levels...................................................................................... 5-19
Data length codes .................................................................................................. 5-21
Method of receiver wake-up ................................................................................... 7-11
SCI clock on SCLK pin ........................................................................................... 7-13
First prescaler stage............................................................................................... 7-18
Second prescaler stage (transmitter) ..................................................................... 7-18
Second prescaler stage (receiver) ......................................................................... 7-19
SCI baud rate selection with CPU clock frequency = fOSC/2.................................. 7-20
SCI baud rate selection with CPU clock frequency = fOSC/8.................................. 7-20
SCI baud rate selection with CPU clock frequency = fOSC/10................................ 7-20
SCI transmit baud rate output for a given prescaler output .................................... 7-21
A/D clock selection ................................................................................................. 9-4
A/D channel assignment ........................................................................................ 9-5
Effect of RESET, POR, STOP and WAIT.............................................................. 10-6
Interrupt priorities ................................................................................................. 10-9
IRQ and WOI sensitivity ....................................................................................... 10-10
MUL instruction .................................................................................................... 11-5
Register/memory instructions............................................................................... 11-5
Branch instructions............................................................................................... 11-6
Bit manipulation instructions................................................................................. 11-6
Read/modify/write instructions ............................................................................. 11-7
Control instructions............................................................................................... 11-7
MC68HC05X16
LIST OF TABLES
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Table
Number
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11-7
11-8
12-1
12-2
12-3
12-4
12-5
12-6
14-1
14-2
A-1
A-2
A-3
A-4
A-5
1-6
1-7
B-1
B-2
B-3
B-4
B-5
B-6
B-7
B-8
B-9
B-10
B-11
B-12
B-13
C-1
C-2
TITLE
Page
Number
Instruction set........................................................................................................11-8
M68HC05 opcode map .........................................................................................11-10
Absolute maximum ratings ....................................................................................12-1
DC electrical characteristics..................................................................................12-2
A/D characteristics ................................................................................................12-4
Control timing ........................................................................................................12-5
MCAN bus interface DC electrical characteristics.................................................12-6
MCAN bus interface control timing characteristics................................................12-6
MC order numbers ................................................................................................14-1
EPROMs for pattern generation ............................................................................14-2
Register outline ...................................................................................................... A-5
Maximum ratings .................................................................................................... A-6
DC electrical characteristics................................................................................... A-7
A/D characteristics ................................................................................................. A-9
Control timing ......................................................................................................... A-10
MCAN bus interface DC electrical characteristics.................................................. A-11
MCAN bus interface control timing characteristics................................................. A-12
Register outline ...................................................................................................... B-4
EPROM control bits description ............................................................................. B-9
EEPROM1 control bits description......................................................................... B-10
Clock divide ratio selection..................................................................................... B-12
Mode of operation selection ................................................................................... B-14
Bootstrap vector targets in RAM ............................................................................ B-20
Maximum ratings .................................................................................................... B-23
DC electrical characteristics................................................................................... B-24
EPROM electrical characteristics........................................................................... B-26
Control timing ......................................................................................................... B-27
A/D characteristics ................................................................................................. B-28
MCAN bus interface DC electrical characteristics.................................................. B-29
MCAN bus interface control timing characteristics................................................. B-29
DC electrical characteristics................................................................................... C-1
Control timing ......................................................................................................... C-2
LIST OF TABLES
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1
1
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INTRODUCTION
The MC68HC05X16 microcomputer (MCU) is a member of Motorola’s MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an on-board controller area network
module (MCAN), complete with interface circuitry, comprising output drivers, input comparators
and a VDD/2 generator. In addition, the device contains an on-chip oscillator, CPU, RAM, ROM,
EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications interface,
programmable timer system and watchdog. The fully static design allows operation at frequencies
down to dc, reducing power consumption to a few micro-amps.
This data sheet is structured such that devices similar to the MC68HC05X16 are described in a
set of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device
MC68HC05X32
MC68HC705X32
MC68HC05X32
Note:
Appendix
Differences from MC68HC05X16
A
32K bytes ROM; increased RAM
32K bytes EPROM; increased RAM; bootstrap firmware
B
replaced
C
32K bytes ROM; increased RAM; high speed operation
Appendix C contains only electrical characteristics exclusive to the high speed
operation of the MC68HC05X32. For all other information concerning this device, refer
to Appendix A.
MC68HC05X16
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1
1.1
Features
Hardware features
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•
Fully static design featuring the industry standard M68HC05 family CPU core
•
On chip crystal oscillator with divide-by -2, -4, -8 or -10, or a software selectable divide-by -32,
-64, -128 or -160 option (SLOW mode)
•
352 bytes of RAM
•
15102 bytes of user ROM plus 16 bytes of user vectors
•
256 bytes of byte erasable EEPROM with internal charge pump and security bit
•
Write/erase protect bit for 224 of the 256 bytes EEPROM
•
Bootstrap firmware
•
Power saving STOP, WAIT and SLOW modes
•
Three 8-bit parallel I/O ports and one 8-bit input-only port; wired-OR interrupt capability on all
port B pins
•
Motorola controller area network (MCAN) with line interface circuitry
•
Software option available to output the internal E-clock to port pin PC2
•
16-bit timer with 2 input captures and 2 output compares
•
Computer operating properly (COP) watchdog timer
•
Serial communications interface system (SCI) with independent transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
•
8 channel A/D converter
•
2 pulse length modulation systems which can be used as D/A converters
•
One interrupt request input plus 4 on-board hardware interrupt sources
•
2.2 MHz bus speed
•
–40 to +125°C temperature range
•
Available in 64-pin quad flat pack (QFP) package
•
Complete development system support available using the MMDS05 or M68MMPFB0508
development station with the M68EML05X32 emulation module or the M68HC05XEVS
evaluation system
INTRODUCTION
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1
1.2
Mask options for the MC68HC05X16
The MC68HC05X16 has six mask options that are programmed during manufacture and must be
specified on the order form.
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•
Oscillator division ratio selection (divide-by-2, -4, -8 or -10)
•
Oscillator start-up delay following power-on or STOP (tPORL) = 16 or 4064 cycles
•
Automatic watchdog enable/disable following a power-on or external reset
•
Watchdog enable/disable during WAIT mode
•
Wired-OR interrupt enable
•
Resistive pull-downs on ports B and/or C
Note:
It is recommended that an external clock is always used if tPORL is set to 16 cycles. This
will prevent any problems arising from oscillator stability when the device is put into
STOP mode.
MC68HC05X16
INTRODUCTION
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1-3
21
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1
RESET
IRQ
COP watchdog
OSC2
OSC1
VDD1
VSS1
VDDH
TX0
TX1
RX0
RX1
Oscillator
÷ 2 / ÷ 4 / ÷ 8 / ÷ 10
Line
interface
576 bytes
bootstrap ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
MCAN
352 bytes
RAM
NWOI
MDS
M68HC05
CPU
Port D
VDD
VSS
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
VRL
15118 bytes
user ROM
(including 16 bytes
user vectors)
Port A
Charge pump
Port B
VPP1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port C
256 bytes
EEPROM
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8-bit
A/D converter
16-bit
programmable
timer
TCMP1
TCMP2
TCAP1
TCAP2
SCI
RDI
SCLK
TDO
PLM
PLMA D/A
PLMB D/A
Figure 1-1 MC68HC05X16 block diagram
INTRODUCTION
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2
2
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MODES OF OPERATION AND
PIN DESCRIPTIONS
2.1
Modes of operation
The MC68HC05X16 MCU has two modes of operation, single-chip mode and bootstrap mode. In
the MC68HC05X16 the single-chip mode is the normal user operating frequency Table 2-1 shows
the conditions required to enter each mode on the rising edge of RESET.
Table 2-1 Mode of operation selection
Note:
2.1.1
MDS
VSS
VDD
AND
OR
IRQ
VSS to VDD
2VDD
TCAP1
VSS to VDD
VSS
TCAP2
X
X
PD3
X
0
PD4
X
0
VDD
VDD
VDD
OR
OR
OR
2VDD
2VDD
2VDD
VDD
VDD
VDD
VSS
VSS
VSS
1
1
0
1
0
1
Mode
Single-chip
Reserved for Motorola use
Bootstrap mode:
Serial RAM loader
Jump to RAM + 1
Jump to any address
On the rising edge of RESET, holding the IRQ pin at 2 x VDD is equivalent to holding
the MDS pin at VDD. The device cannot enter single-chip mode unless MDS is tied to
VSS (or left floating) and IRQ is below VDD.
Single-chip mode
This is the normal user operating mode of the MC68HC05X16. In this mode the device functions
as a self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit
I/O ports and the 8-bit input-only port, available to the user. All address and data activity occurs
within the MCU.
MC68HC05X16
MODES OF OPERATION AND PIN DESCRIPTIONS
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2.1.2
2
Bootstrap mode
To place the part in bootstrap mode, the following conditions must be met during transition of the
RESET pin from low to high:
1) IRQ pin at 2xVDD OR MDS pin at VDD
2) TCAP1 pin at VDD
3) TCAP2 pin at VSS
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PD4 and PD3 are connected according to the values given in Table 2-1 to select the device’s
function from the following three functions:
•
Execute serial RAM loader program
•
Jump to RAM + 1
•
Jump to any address
If the SEC bit in the option register is set, on first entering bootstrap mode the RAM and the EEPROM
are completely erased. The option register which contains the security bit is erased last, before any
program can be executed. The bootstrap software is implemented in the following locations:
•
RAM load and execute from $03B0 to $03FD
•
Vectors and program select from $7F80 to $7FEF
ENTRY
SEC bit active?
YES
Save PD in RAM. Erase
whole EEPROM + RAM
and check EPROM +
SEC bit.
NO
PD3 set
?
NO
NO
Reserved for
Motorola use.
PD4 set
?
YES
Jump to address
defined by ports A, B
and C.
YES
NO
PD4 set
?
Jump to RAM + 1.
YES
Serial RAM bootstrap
loader.
Figure 2-1 Bootstrap mode function selection flow chart
MODES OF OPERATION AND PIN DESCRIPTIONS
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Note:
2.1.2.1
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Oscillator divide-by-two is forced in bootstrap mode; all other mask options are selected
by the customer (see Section 1.2).
2
Serial RAM loader
In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. The first byte loaded is the count of the total number of bytes in the program
plus the count byte. After completion of RAM loading, control can be transferred either to the
second byte in RAM, $0051, by executing a jump to RAM + 1 function, or it can be transferred to
any address by executing a jump to any address function. During the firmware initialization stage,
the SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit). The
baud rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format
required by the RAM loader is available from Motorola.
When the last byte is loaded, the firmware halts operation expecting additional data to arrive. At
this point, the reset switch is placed in the reset position which resets the MCU, but keeps the RAM
program intact. All routines loaded in RAM can now be entered from this state, including the one
which executes the program in RAM (see Section 2.1.2.2 and Section 2.1.2.3).
To load a program in the EEPROM, the ‘load program in RAM and execute’ function is also used.
In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program
which controls the loading of the EEPROM, and when the RAM contents are executed, the MCU
is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-3 shows the schematic diagram of the circuit required for the serial RAM loader.
2.1.2.2
Jump to RAM + 1
After the serial RAM loader program is completed this function can be used to execute a program
loaded in RAM starting at the second RAM address, $0051. It must be noted that the lowest RAM
address, $0050, is used by the RAM loader program to store the total number of bytes in the
program.
2.1.2.3
‘Jump to any address’
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.1.2.1.
To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
execution of the user program. A schematic diagram of the circuit required is shown in Figure 2-2.
MC68HC05X16
MODES OF OPERATION AND PIN DESCRIPTIONS
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P1
2
10 nF
47 mF
GND
+5V
2xVDD
10 kΩ
RESET
VDD
OSC1
RESET
OSC2
0.01 mF
22 pF
4 MHz
22 pF
10 kΩ
IRQ
8 x 10 kΩ
optional (see note)
10 kΩ
PD3
8 x 10 kΩ
10 kΩ
VRH
optional
VRL
VPP1
PLMA
PLMB
SCLK
RDI
Connect as required
for the application
TDO
TCMP2
8 x 10 kΩ
TCAP2
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
TCMP1
VSS
Note:
10 kΩ
TCAP1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
MSB
Select required address
3 x 10 kΩ
PD4
MC68HC05X16
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
LSB
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PD7
PD6
PD5
PD2
PD1
PD0
These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are
kept in input mode during application.
Figure 2-2 MC68HC05X16 ‘jump to any address’ schematic diagram
MODES OF OPERATION AND PIN DESCRIPTIONS
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P1
10 nF
47 mF
2
GND
+5V
2xVDD
10 kΩ
RESET
VDD
OSC1
RESET
OSC2
0.01 mF
22 pF
4 MHz
22 pF
10 kΩ
9600 Bd
RS232
RS232 level translator
suggested:
MC145406 or MAX232
IRQ
10 kΩ
RDI
PD3
TDO
10 kΩ
3 x 10 kΩ
PD4
10 kΩ
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Connect as required
for the application
TCAP1
MC68HC05X16
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PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
VRH
optional
VRL
VPP1
PLMA
PLMB
SCLK
Connect as required
for the application
TCMP2
TCAP2
TCMP1
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD7
PD6
PD5
PD2
PD1
PD0
VSS
Figure 2-3 MC68HC05X16 ‘load program in RAM and execute’ schematic diagram
MC68HC05X16
MODES OF OPERATION AND PIN DESCRIPTIONS
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2.2
2
Low power modes
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.2.1
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STOP mode
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off (providing the MCAN is ‘asleep’, see Section 5.5) halting all internal
processing including timer, serial communications interface and the A/D converter (see flow chart
in Figure 2-4). The MCU will wake up from STOP mode only by receipt of an MCAN external
interrupt or by the detection of a reset (logic low on RESET pin or a power-on reset.
The STOP instruction can be executed (i.e. the oscillator can be turned off) only when the MCAN
module is in SLEEP mode. See Section 5.5.
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 11.1.5). The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
while exiting STOP mode (see Section 2.2.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged. This
continues until a MCAN interrupt, wired-OR interrupt, external interrupt (IRQ) or reset is sensed,
at which time the internal oscillator is turned on. The interrupt or reset causes the program counter
to vector to the corresponding locations ($3FFA, B and $3FFE, F respectively).
When leaving STOP mode, a tPORL internal cycles delay is provided to give the oscillator time to
stabilise before releasing CPU operation. This delay is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up.
Note:
If tPORL is selected to be 16 cycles, it is recommended that an external clock signal is
used to avoid problems with oscillator stability while the device is in STOP mode.
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the modules of the MC68HC05X16.
–
The watchdog timer is reset; see Section 10.1.4.1
–
The EEPROM acts as read-only memory (ROM); see Section 3.6
–
All SCI activity stops; see Section 7.13
–
The timer stops counting; see Section 6.6
–
The PLM outputs remain at current levels; see Section 8.3
–
The A/D converter is disabled; see Section 9.3
–
The I-bit in the CCR is cleared
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2.2.2
WAIT mode
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended and the watchdog is
disabled, but the timer, A/D and SCI and MCAN systems remain active and operate as normal (see
flow chart in Figure 2-4). All other memory and registers remain unaltered and all parallel
input/output lines remain unchanged. The programming or erase mechanism of the EEPROM is
also unaffected, as well as the charge pump high voltage generator.
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2
During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the
miscellaneous register (Section 2.2.3.1) is not affected by WAIT mode. When any interrupt or reset
is sensed, the program counter vectors to the locations containing the start address of the interrupt
or reset service routine.
Any interrupt or reset condition causes the processor to exit WAIT mode.
If an interrupt exit from WAIT mode is performed, the state of the remaining systems will be
unchanged.
If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.
Note:
The stacking corresponding to an eventual interrupt to leave WAIT mode will only be
executed when leaving WAIT mode.
MC68HC05X16
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The following list summarizes the effect of WAIT mode on the modules of the MC68HC05X16.
2
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–
The watchdog timer functions according to the mask option selected; see
Section 10.1.4.2
–
The EEPROM is not affected; see Section 3.7
–
The SCI is not affected; see Section 7.14
–
The timer is not affected; see Section 6.7
–
The PLM is not affected; see Section 8.4
–
The A/D converter is not affected; see Section 9.4
–
The I-bit in the CCR is cleared
–
The MCAN module is unaffected
2.2.2.1
Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power
consumption will be highest when all the systems (A/D, timer, EEPROM, SCI and MCAN) are
active, and lowest when the EEPROM erase and programming mechanism, SCI and A/D are
disabled and the MCAN is in SLEEP mode. The timer cannot be disabled in WAIT mode. It is
important that before entering WAIT mode, the programmer sets the relevant control bits for the
individual modules to reflect the desired functionality during WAIT mode.
Power consumption may be further reduced by the use of SLOW mode. (See Section 2.2.3).
2.2.3
SLOW mode
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see Figure 2-5). This feature allows all the internal
operations to slow down and thus reduces power consumption.
Warning: The SLOW mode function should not be enabled while using the A/D converter or while
erasing/programming the EEPROM unless the internal A/D RC oscillator is turned on.
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STOP
YES
WAIT
2
Watchdog active?
NO
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Stop oscillator and all
clocks.
Clear I bit.
Oscillator active. Timer,
SCI, A/D, EEPROM clocks
active. Processor clocks
stopped. Clear I-bit
NO
Reset ?
NO
CIRQ,
wired-OR, external
interrupt?
NO
Reset ?
YES
YES
NO
WOI ?
YES
YES
YES
Turn on oscillator.
Wait for time delay to
stabilise
NO
Timer interrupt ?
NO
SCI ?
YES
NO
CIRQ ?
Restart processor clock
YES
Generate watchdog
interrupt
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
b. set I-bit
c. vector to interrupt
routine
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
b. set I-bit
c. vector to interrupt
routine
Figure 2-4 STOP and WAIT flow charts
MC68HC05X16
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31
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OSC2
OSC1
pin
2
pin
fOSC
Oscillator
÷ 2, 4,
8 and 10
÷ 16
÷2
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MCAN
SM–bit
(bit 1, $000C)
Control logic
Main internal clock
Note:
The MCAN module clock is unaffected during SLOW mode.
Figure 2-5 Slow mode divider block diagram
2.2.3.1
Miscellaneous register
Miscellaneous
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000C
POR
INTP
INTN
INTE
SFA
SFB
SM
WDOG u001 000u
SM — Slow mode
1 (set)
–
0 (clear) –
The system runs at a bus speed 16 times lower than normal (fOSC/32,
/64, /128 or /160). SLOW mode affects all sections of the device
(including SCI, A/D and timer) except for the MCAN module.
The system runs at normal bus speed (fOSC/2, /4, /8 or /10).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
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2.3
Pin descriptions
2
2.3.1
VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS
is ground.
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It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply bypassing at
the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to
the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.3.2
IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the
INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 10-3.
In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the
Miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in
the miscellaneous register while the I-bit is set. Selecting a different interrupt option will
automatically clear any pending interrupts. Further details of the external interrupt procedure can
be found in Section 10.2.3.2.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. A
high voltage detector is provided on this pin to select modes of operation other than single-chip
mode. See Section 2.1.
2.3.3
RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device
to a known start-up state. An external RC-circuit can be connected to this pin to generate a
power-on reset (POR) if required. In this case, the time constant must be great enough (at least
100ms) to allow the oscillator circuit to stabilise. This input has an internal Schmitt trigger to
improve noise immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the
RESET pin provides an active-low open drain output signal that may be used to reset external
hardware.
MC68HC05X16
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2.3.4
2
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MDS
A pull-down device is activated on this pin each time the RESET pin is pulled low. Even after the
RESET pin is pulled high, the pull-down on the MDS pin will remain active until the pin is pulled
high. In single-chip mode MDS can be connected to VSS or left floating. When MDS is tied to VDD
at the end of reset, it is used to select any mode of operation other than single-chip mode. This
has the same effect as tying IRQ to 2VDD. See Section 2.1.
Note:
2.3.5
Although this pin can be left floating to select single-chip mode, it is advisable to
hard-connect it to VSS, especially in an electrically noisy environment.
TCAP1
The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system.
2.3.6
TCAP2
The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system.
2.3.7
TCMP1
The TCMP1 pin is the output of the output compare 1 function of the timer system.
2.3.8
TCMP2
The TCMP2 pin is the output of the output compare 2 function of the timer system.
2.3.9
RDI (Receive data in)
The RDI pin is the input pin of the SCI receiver.
2.3.10
TDO (Transmit data out)
The TDO pin is the output pin of the SCI transmitter.
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2.3.11
SCLK
2
The SCLK pin is the clock output pin of the SCI transmitter.
2.3.12
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OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or
external clock signal connected to these pins supplies the oscillator clock. The oscillator frequency
(fOSC) is divided by two, four, eight or ten to give the internal bus frequency (fOP). There is also a
software option which introduces an additional divide by 16 into the oscillator clock, giving an
internal bus frequency of fOSC/32, /64, /128 or /160.
2.3.12.1
Crystal
The circuit shown in Figure 2-6(a) is recommended when using either a crystal or a ceramic
resonator. An internal feedback resistor is provided on-chip between OSC1 and OSC2.
Figure 2-6(d) lists the recommended capacitance values. The internal oscillator is designed to
interface with an AT-cut parallel-resonant quartz crystal resonator in the frequency range specified
for fOSC (see Section 12.4). Use of an external CMOS oscillator is recommended when crystals
outside the specified ranges are to be used. The crystal and associated components should be
mounted as close as possible to the input pins to minimise output distortion and start-up
stabilization time. The manufacturer of the particular crystal being considered should be consulted
for specific information.
2.3.12.2
Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications for frequencies up
to 8MHz external. The circuit shown in Figure 2-6(a) is recommended when using either a crystal or a
ceramic resonator. Figure 2-6(d) lists the recommended capacitance and feedback resistance values.
The manufacturer of the particular ceramic resonator being considered should be consulted for specific
information. This option is recommended only for applications that operate at an external clock
frequency of 8MHz or less. Any application requiring an external operating frequency greater that
8MHz should use either a crystal oscillator or an external CMOS compatible clock source.
2.3.12.3
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase, as shown
in Figure 2-6(c). The tOXOV or tILCH specifications (see Section 12.4) do not apply when using an
external clock input. The equivalent specification of the external clock source should be used in
lieu of tOXOV or tILCH.
MC68HC05X16
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L
2
C1
RS
OSC1
OSC2
C0
MCU
OSC1
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OSC2
(b) Crystal equivalent circuit
COSC1
COSC2
MCU
(a) Crystal/ceramic resonator
oscillator connections
OSC1
OSC2
External
clock
NC
(c) External clock source connections
RS(max)
C0
C1
COSC1
COSC2
Q
Crystal
2MHz 4MHz
400
75
5
7
8
12
15 – 40 15 – 30
15 – 30 15 – 25
30 000 40 000
Unit
W
pF
ƒF
pF
pF
—
Ceramic resonator
2 – 4MHz
Unit
10
W
RS(typ)
C0
40
pF
C1
4.3
pF
COSC1
30
pF
COSC2
30
pF
Q
1250
—
(d) Typical crystal and ceramic resonator parameters
Figure 2-6 Oscillator connections
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2.3.12.4
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Oscillator division
The external oscillator can run up to 22MHz. For this reason an additional clock predivider is
provided; its division ratio is selected via a mask option (see Section 1.2). This allows a CPU clock
two, four, eight or ten times slower than the external clock, provided that SLOW mode has not been
entered. If the device is in SLOW mode, a further divide-by-16 oscillator predivider reduces the
CPU clock frequency to a frequency 32, 64, 128 or 160 times slower than the oscillator clock. The
MCAN is directly clocked with the external oscillator frequency divided by two. A block diagram of
the oscillator divider circuit is given in Figure 2-7.
OSC1
OSC2
pin
pin
Mask option
÷2
÷1, ÷2,
÷4, or ÷5
Oscillator
MCAN clock
÷2
fOSC/2, /4, /8 or /10
SM bit
2
MCAN module
÷ 16
fOSC/32, /64,
/128 or /160
Control logic
Main internal clock
Figure 2-7 Oscillator divider block diagram
2.3.13
PLMA
The PLMA pin is the output of pulse length modulation converter A.
2.3.14
PLMB
The PLMB pin is the output of pulse length modulation converter B.
MC68HC05X16
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2.3.15
2
VPP1
The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.3.16
VRH
The VRH pin is the positive reference voltage for the A/D converter.
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2.3.17
VRL
The VRL pin is the negative reference voltage for the A/D converter.
2.3.18
PA0 – PA7/PB0 – PB7/PC0 – PC7
These 24 I/O lines comprise ports A, B and C. The state of any pin is software programmable, and
all the pins are configured as inputs during power-on or reset.
Under software control the PC2 pin can output the internal E-clock (see Section 4.2).
Resistive pull downs are provided on port B and/or port C and can be enabled via a mask option
(see Section 1.2). Wired-OR interrupt capability is provided on all pins of port B (see
Section 10.2.3.3).
2.3.19
NWOI
This pin provides another wired-OR interrupt capability in addition to port B. Wired-OR interrupts
are requested when this pin is pulled high (if wired-OR interrupts are enabled), i.e. interrupt
sensitivity on this pin is complementary to sensitivity on the IRQ pin (see Table 10-3 in
Section 10.2.3.1). When this pin is not in use it is recommended that it be tied to VSS in noisy
conditions. It is not necessary to tie NWOI to VSS when there is a negligible amount of noise
present.
2.3.20
PD0/AN0–PD7/AN7
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D
converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is
disabled which forces the port D pins to be input only port pins (see Section 9.5).
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2.3.21
VDD1
2
This pin is the power input for the input comparator of the MCAN module.
2.3.22
VSS1
This pin is the ground connection for the input comparator of the MCAN bus.
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2.3.23
VDDH
This pin provides the high voltage reference output for the MCAN bus. The output voltage is equal
to VDD÷2.
2.3.24
RX0/RX1
These input pins connect the physical bus lines to the input comparator (receive). When the MCAN
is in SLEEP mode, a dominant level on these pins will wake it up.
2.3.25
TX0/TX1
These output pins connect the output drivers of the MCAN bus to the physical bus lines (transmit).
MCAN bus lines. The bus can have one of two complementary values: dominant or recessive.
During simultaneous transmission of dominant and recessive bits the resulting bus value will be
dominant. For example with a positive logic wired-AND implementation of the bus, the dominant
level would correspond to a logic 0 and the recessive level to a logic 1.
MC68HC05X16
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3
3
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MEMORY AND REGISTERS
The MC68HC05X16 MCU is capable of addressing 16384 bytes of memory and registers with its
program counter. The memory map includes 15118 bytes of user ROM (including user vectors),
576 bytes of bootstrap ROM, 352 bytes of RAM and 256 bytes of EEPROM.
3.1
Registers
All the I/O, control and status registers of the MC68HC05X16 are contained within the first 32-byte
block of the memory map, as shown in Figure 3-1. MCAN registers are contained in the next 30
bytes of memory.
The miscellaneous register is shown in Section 3.8 as this register contains bits which are relevant
to several modules.
3.2
RAM
The user RAM comprises 176 bytes of memory, from $0050 to $00FF. This is shared with a 64 byte
stack area. The stack begins at $00FF and may extend down to $00C0. The user RAM also
comprises 176 bytes from $0250 to $02FF which is completely free for the user.
Note:
3.3
Using the stack area for data storage or temporary work locations requires care to prevent
the data from being overwritten due to stacking from an interrupt or subroutine call.
ROM
The user ROM consists of 15118 bytes of ROM mapped as follows:
•
15102 bytes of user ROM from $0300 to $3DFD
•
16 bytes of user vectors from $3FF0 to $3FFF
MC68HC05X16
MEMORY AND REGISTERS
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Registers
MC68HC05X16
3
$0000
I/O
(32 bytes)
Ports
7 bytes
MCAN
registers
EEPROM/ECLK
control
1 byte
$0020
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$003E
$0050
$00C0
$0100
$0101
$0120
A/D
converter
2 bytes
RAM I
Stack (176 bytes)
OPTR (1 byte)
PLM system
2 bytes
Non protected (31 bytes)
EEPROM
(256 bytes)
Miscellaneous
1 byte
Protected (224 bytes)
$0200
Bootstrap ROM I
(80 bytes)
SCI
5 bytes
$0250
RAM II
176 bytes
Timer
14 bytes
$0300
ROM
(15102 bytes)
$3DFE
$3E00
MCAN
control registers
10 bytes
Bootstrap ROM II
(498 bytes)
CIRQ
$3FF0–1
SCI
$3FF2–3
Timer overflow
$3FF4–5
$3FF6–7 Timer output compare 1& 2 User
Vectors
$3FF8–9 Timer input capture 1& 2
WOI, External IRQ
$3FFA–B
SWI
$3FFC–D
$3FFE–F Reset/power-on reset
MCAN
transmit buffer
10 bytes
MCAN
receive buffer
10 bytes
$0000
$0001
$0002
$0003
$0004
$0005
$0006
E/EEPROM/ECLK control register $0007
$0008
A/D data register
$0009
A/D status/control register
$000A
Pulse length modulation A
Pulse length modulation B $000B
$000C
Miscellaneous register
$000D
SCI baud rate register
$000E
SCI control register 1
$000F
SCI control register 2
$0010
SCI status register
$0011
SCI data register
$0012
Timer control register
$0013
Timer status register
$0014
Capture high register 1
$0015
Capture low register 1
$0016
Compare high register 1
$0017
Compare low register 1
$0018
Counter high register
$0019
Counter low register
$001A
Alternate counter high register
$001B
Alternate counter low register
$001C
Capture high register 2
$001D
Capture low register 2
$001E
Compare high register 2
Compare low register 2
$001F
Port A data register
Port B data register
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
Options register
$0100
Mask options register
$3DFE
Reserved
Figure 3-1 Memory map of the MC68HC05X16
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MCAN register blocks
MCAN registers
$0020
Control register
Command register
Status register
Interrupt register
Acceptance code register
Acceptance mask register
Bus timing register 1
Bus timing register 2
Output control register
Test register
Identifier
RTR-bit, data length code
Data segment byte 1
Data segment byte 2
Data segment byte 3
Data segment byte 4
Data segment byte 5
Data segment byte 6
Data segment byte 7
Data segment byte 8
Identifier
RTR-bit, data length code
Data segment byte 1
Data segment byte 2
Data segment byte 3
Data segment byte 4
Data segment byte 5
Data segment byte 6
Data segment byte 7
Data segment byte 8
MCAN
control registers
10 bytes
$0029
$002A
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MCAN
transmit buffer
10 bytes
$0033
$0034
MCAN
receive buffer
10 bytes
$003D
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$002D
$002E
$002F
$0030
$0031
$0032
$0033
$0034
$0035
$0036
$0037
$0038
$0039
$003A
$003B
$003C
$003D
3
Figure 3-2 MCAN module memory map
3.4
Bootstrap ROM
There are two areas of bootstrap ROM (ROMI and ROMII) located from $0200 to $024F (80 bytes)
and $3DFE to $3FEF (498 bytes) respectively.
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3.5
3
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EEPROM
The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255
bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is
byte erasable.
An internal charge pump provides the EEPROM voltage (VPP1), which removes the need to supply
a high voltage for erase and programming functions. The charge pump is a capacitor/diode ladder
network which will give a very high impedance output of around 20-30 MΩ. The voltage of the
charge pump is visible at the VPP1 pin. During normal operation of the device, where
programming/erasing of the EEPROM array will occur, VPP1 should never be connected to either
VDD or VSS as this could prevent the charge pump reaching the necessary programming voltage.
Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in a
system, it may be tied to VDD; this will protect the EEPROM data but will also increase power
consumption, and therefore it is recommended that the protect bit function is used for regular
protection of EEPROM data (see Section 3.5.5).
In order to achieve a higher degree of security for stored data, there is no capability for bulk or row
erase operations.
The EEPROM control register ($0007) provides control of the EEPROM programming and erase
operations.
Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent
damage to the device.
3.5.1
EEPROM control register
EEPROM/ECLK control
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
$0007
WOIE
CAF
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
WOIE — Wired-OR interrupt enable
This bit is used to enable wired-OR interrupts on the NWOI pin and on all port B pins which have
been programmed as inputs. Wired-OR interrupts can only be enabled if the WOI mask option is
selected (see Section 1.2). WOIE is forced to zero if this mask option is not selected. Power-on
reset clears the WOIE bit.
1 (set)
–
0 (clear) –
Wired-OR interrupts are enabled (provided that wired-OR interrupts
have been selected as a mask option).
Wired-OR interrupts are disabled.
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CAF — MCAN asleep flag
This flag is set by the MCU when the MCAN module enters SLEEP mode. This is the only
indication that the MCAN is asleep (see Section 5.5). The bit is cleared when the MCAN wakes up.
1 (set)
–
0 (clear) –
The MCAN module is in SLEEP mode.
3
The MCAN module is not in SLEEP mode.
ECLK — External clock option bit
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See Section 4.3 for a description of this bit.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
0 (clear) –
An erase operation will take place.
A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
E1LAT — EEPROM programming latch enable bit
1 (set)
–
0 (clear) –
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
Data can be read from the EEPROM. The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set)
–
Internal charge pump generator switched on.
0 (clear) –
Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.
Note:
Not all combinations are shown in Table 3-1, since the E1PGM and E1ERA bits are
cleared when the E1LAT bit is at zero, resulting in a read condition.
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Table 3-1 EEPROM control bits description
E1ERA
0
0
0
1
1
3
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3.5.2
E1LAT E1PGM
Description
0
0
Read condition
1
0
Ready to load address/data for program/erase
1
1
Byte programming in progress
1
0
Ready for byte erase (load address)
1
1
Byte erase in progress
EEPROM read operation
To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.
While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and
the 256 bytes of EEPROM may be read as if it were a normal ROM area. The internal charge pump
generator is automatically switched off since the E1PGM bit is reset.
If a read operation is executed while the E1LAT bit is set (erase or programming sequence), data
resulting from the operation will be $FF.
Note:
When not performing any programming or erase operation, it is recommended that
EEPROM should remain in the read mode (E1LAT = 0)
3.5.3
EEPROM erase operation
To erase the contents of a byte of the EEPROM, the following steps should be taken:
1
Set the E1LAT bit.
2
Set the E1ERA bit (1& 2 may be done simultaneously with the same
instruction).
3
Write address/data to the EEPROM address to be erased.
4
Set the E1PGM bit.
5
Wait for a time tERA1.
6
Reset the E1LAT bit (to logic zero).
While an erase operation is being performed, any access of the EEPROM array will not be
successful.
The erased state of the EEPROM is $FF and the programmed state is $00.
Note:
Data written to the address to be erased is not used, therefore its value is not significant.
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If a second word is to be erased, it is important that the E1LAT bit be reset before restarting the
erasing sequence, otherwise any write to a new address will have no effect. This condition provides
a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
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3.5.4
3
EEPROM programming operation
To program a byte of EEPROM, the following steps should be taken:
1
Set the E1LAT bit.
2
Write address/data to the EEPROM address to be programmed.
3
Set the E1PGM bit.
4
Wait for time tPROG1.
5
Reset the E1LAT bit (to logic zero).
While a programming operation is being performed, any access of the EEPROM array will not be
successful.
Warning: To program a byte correctly, it has to have been previously erased.
If a second word is to be programmed, it is important that the E1LAT bit be reset before restarting
the programming sequence otherwise any write to a new address will have no effect. This condition
provides a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
Note:
3.5.5
224 bytes of EEPROM (address $0120 to $01FF) can be program and erase protected
under the control of bit 1 of the OPTR register detailed in Section 3.5.5.
Options register (OPTR)
This register (OPTR), located at $0100, contains the secure and protect functions for the EEPROM
and allows the user to select options in a non-volatile manner. The contents of the OPTR register
are loaded into data latches with each power-on or external reset.
Address
Options (OPTR)(1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$0100
State
on reset
bit 1
bit 0
EE1P
SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
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EE1P – EEPROM protect bit
3
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In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
of the options register.
1 (set)
–
0 (clear) –
Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM
can be accessed for any read, erase or programming operations
Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful
When this bit is set (erased), the protection will remain until the next power-on or external reset.
EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.
SEC – Security bit
This high security bit allows the user to secure the EEPROM data from external accesses. When
the SEC bit is at ‘0’, the EEPROM contents are secured by preventing any entry to test mode. The
only way to erase the SEC bit to ‘1’ externally is to enter bootstrap mode, at which time the entire
EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect
until the next external or power-on reset.
3.6
EEPROM during STOP mode
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1
high voltage charge pump generator is automatically disabled.
3.7
EEPROM during WAIT mode
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in
normal operating mode. The charge pump is not affected by WAIT mode, therefore it is possible to
wait the tERA1 erase time or tPROG1 programming time in WAIT mode.
Under normal operating conditions, the charge pump generator is driven by the internal CPU
clocks. When the operating frequency is low, e.g. during slow mode (see Figure 3.8) or during
WAIT mode, the clocking should be done by the internal A/D RC oscillator. The RC oscillator is
enabled by setting the ADRC bit of the A/D status/control register at $0009.
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Table 3-2 MC68HC05X16 register outline
Register name
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Address bit 7
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
$0003
$0004
$0005
$0006
$0007
$0008
$0009
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
Miscellaneous
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
Options (OPTR)(3)
bit 6
bit 5
bit 4
PD7
PD6
PD5
PD4
WOIE
CAF
0
0
COCO ADRC ADON
$000A
$000B
$000C POR(1)
$000D SPC1
$000E
R8
$000F
TIE
$0010 TDRE
$0011
$0012
ICIE
$0013 ICF1
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
INTP INTN
SPC0 SCT1
T8
TCIE
RIE
TC
RDRF
OCIE
OCF1
TOIE
TOF
0
bit 3
PD3
bit 2
PC2/
ECLK
PD2
bit 1
bit 0
State on
reset
Undefined
Undefined
Undefined
PD1
3
PD0
Undefined
0000 0000
0000 0000
0000 0000
ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
CH3
CH2
CH1
CH0 0000 0000
0000 0000
0000 0000
INTE SFA
SFB
SM WDOG(2) u001 000u
SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M
WAKE CPOL CPHA LBCL Undefined
ILIE
TE
RE
RWU
SBK 0000 0000
IDLE
OR
NF
FE
1100 000u
0000 0000
FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
ICF2 OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
$001F
$0100
EE1P
Undefined
SEC Not affected
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
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Table 3-3 MCAN register outline
Register name
3
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Control (CCNTRL)
Command (CCOM)
Status (CSTAT)
Interrupt (CINT)
Acceptance code (CACC)(1)
Acceptance mask (CACM)(1)
Bus timing 0 (CBT0)(1)
Bus timing 1 (CBT1)(1)
Output control (COCNTRL)(1)
(reserved)
Transmit buffer identifier (TBI)
RTR-bit, data length code (TRTDL)
Transmit data segment 1 (TDS1)
Transmit data segment 2 (TDS2)
Transmit data segment 3 (TDS3)
Transmit data segment 4 (TDS4)
Transmit data segment 5 (TDS5)
Transmit data segment 6 (TDS6)
Transmit data segment 7 (TDS7)
Transmit data segment 8 (TDS8)
Receive buffer identifier (RBI)
RTR-bit, data length code (RRTDL)
Receive data segment 1 (RDS1)
Receive data segment 2 (RDS2)
Receive data segment 3 (RDS3)
Receive data segment 4 (RDS4)
Receive data segment 5 (RDS5)
Receive data segment 6 (RDS6)
Receive data segment 7 (RDS7)
Receive data segment 8 (RDS8)
Address bit 7
bit 6
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
SPD
RX1
ES
MODE
RX0
BS
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OIE
EIE
COS
TCS
OIF
AC3
AM3
BRP3
TIE
RRB
TBA
EIF
AC2
AM2
BRP2
RIE
AT
DO
TIF
AC1
AM1
BRP1
RR
TR
RBS
RIF
AC0
AM0
BRP0
State on
reset
0u - u uuu1
00u0 0000
TS
RS
uu00 1100
WIF
- - - 0 0000
AC7
AC6
AC5
AC4
Undefined
AM7
AM6
AM5
AM4
Undefined
SJW1 SJW0 BRP5 BRP4
Undefined
SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
COMPSEL SLEEP
$0028 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCM1 OCM0 Undefined
$0029
$002A ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3 Undefined
$002B
ID2
ID1
ID0
RTR DLC3 DLC2 DLC1 DLC0 Undefined
$002C DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$002D DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$002E DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$002F DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0030
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0031
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0032
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0033
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0034 ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3 Undefined
$0035
ID2
ID1
ID0
RTR DLC3 DLC2 DLC1 DLC0 Undefined
$0036
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0037
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0038
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$0039
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$003A DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$003B DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$003C DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
$003D DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 Undefined
(1) These registers can only be accessed when the reset request bit in the control register is set.
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3.8
Miscellaneous register
Address
Miscellaneous
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$000C POR(1) INTP
INTN
INTE
SFA
SFB
SM
bit 0
State
on reset
WDOG(2) u001 000u
(1) The POR bit is set each time there is a power-on reset.
3
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
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POR — Power-on reset bit (see Section 10.1)
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
–
A power-on reset has occurred.
0 (clear) –
No power-on reset has occurred.
INTP, INTN — External interrupt sensitivity options (see Section 10.2)
These two bits allow the user to select which edge the IRQ pin and WOI will be sensitive to (see
Table 3-4). Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset, thus the device is initialised with negative edge and low level sensitivity.
Table 3-4 IRQ and WOI sensitivity
INTP
0
0
1
1
INTN
0
1
0
1
IRQ sensitivity
Negative edge and low level sensitive
Negative edge only
Positive edge only
Positive and negative edge sensitive
WOI interrupt options
Positive edge and high level sensitive
Positive edge only
Negative edge only
Positive and negative edge sensitive
INTE — External interrupt enable (see Section 10.2)
1 (set)
–
External interrupt function (IRQ) enabled.
0 (clear) –
External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
SFA — Slow or fast mode selection for PLMA (see Section 8.1)
1 (set)
–
0 (clear) –
MC68HC05X16
Slow mode PLMA (4096 x timer clock period).
Fast mode PLMA (256 x timer clock period).
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SFB — Slow or fast mode selection for PLMB (see Section 8.1)
1 (set)
–
0 (clear) –
3
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Note:
Slow mode PLMB (4096 x timer clock period).
Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
bit and the SFB bit to the desired values before writing to the PLM registers; not doing
so could temporarily give incorrect values at the PLM outputs.
SM — Slow mode (see Section 2.2.3)
1 (set)
–
0 (clear) –
The system runs at a bus speed 16 times lower than normal
(fOSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
The system runs at normal bus speed (fOSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see Section 10.1.4)
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set)
–
0 (clear) –
Watchdog counter cleared and enabled.
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
MEMORY AND REGISTERS
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INPUT/OUTPUT PORTS
4
In single-chip mode, the MC68HC05X16 has a total of 24 I/O lines, arranged as three 8-bit ports
(A, B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually
programmable as either input or output, under the software control of the data direction registers.
The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is
enabled. To avoid glitches on the output pins, data should be written to the I/O port data register
before writing ones to the corresponding data direction register bits to set the pins to output mode.
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding
DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data latch and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-1.
MC68HC05X16
INPUT/OUTPUT PORTS
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4
M68HC05 internal connections
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Data direction
register bit
DDRn
Latched data
register bit
DATA
Output
buffer
I/O
Pin
O/P
data
buffer
Input
buffer
DDRn
DATA
I/O Pin
Output



1
0
0
1
1
1
Input



0
0
tristate
0
1
tristate
Figure 4-1 Standard I/O port structure
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note
that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states
R/W
0
0
1
1
4.2
DDRn
0
1
0
1
Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in output mode. The output data latch is read.
Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a
data direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
Wired-OR interrupts are provided on all pins of port B. If WOIE is enabled, any combination of high
logic levels on port B pins which are programmed as inputs will trigger an external interrupt. See
Section 10.2.3.2.
INPUT/OUTPUT PORTS
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A mask option is provided to enable resistive pull downs on all port B pins that are programmed
as inputs.
4.3
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Port C
In addition to the standard port functions described for ports A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
4
A mask option is provided to enable resistive pull downs on all port C pins that are programmed
as inputs.
EEPROM/ECLK control
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
$0007
0
0
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
ECLK — External clock option bit
1 (set)
–
0 (clear) –
ECLK CPU clock is output on PC2.
ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in Figure 4-2.
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Figure 4-2 ECLK timing diagram
MC68HC05X16
INPUT/OUTPUT PORTS
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4.4
Port D
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D
converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can
be read at any time, however, if it is read during an A/D conversion sequence noise, may be
injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
a digital read of port D with levels other than VDD or VSS on the port D pins will result in greater
power dissipation during the read cycle.
4
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As port D is an input-only port there is no DDR associated with it. Also, at power up or external
reset, the A/D converter is disabled, thus the port is configured as a standard input-only port.
Note:
It is recommended that all unused input ports and I/O ports be tied to an appropriate
logic level (i.e. either VDD or VSS).
4.5
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.5.1
Port data registers A and B (PORTA and PORTB)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
Undefined
Port B data (PORTB)
$0001
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
The state of the port data registers following reset is not defined.
INPUT/OUTPUT PORTS
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4.5.2
Port data register C (PORTC)
Address
Port C data (PORTC)
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PC2/
ECLK
$0002
State
on reset
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM
CTL/ECLK register is set (see Section 4.3).
4
The state of the port data registers following reset is not defined.
4.5.3
Port data register D (PORTD)
Port D data (PORTD)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0003
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Undefined
All the port D bits are input-only and are shared with the A/D converter. The function of each bit is
determined by the ADON bit in the A/D status/control register.
The state of the port data registers following reset is not defined.
4.5.4
A/D status/control register
A/D status/control
Address
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0009
COCO ADRC ADON
0
CH3
CH2
CH1
CH0
0000 0000
bit 6
ADON — A/D converter on
1 (set)
–
A/D converter is switched on; all port D pins act as analog inputs for
the A/D converter.
0 (clear) –
A/D converter is switched off; all port D pins act as input only pins.
Reset clears the ADON bit, thus configuring port D as an input only port.
MC68HC05X16
INPUT/OUTPUT PORTS
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4.5.5
Data direction registers (DDRA, DDRB and DDRC)
Address
Port A data direction (DDRA)
4
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0004
0000 0000
Port B data direction (DDRB)
$0005
0000 0000
Port C data direction (DDRC)
$0006
0000 0000
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
4.6
Other port considerations
All output ports can emulate ‘open-drain’ outputs. This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
When using a port pin as an ‘open-drain’ output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the ‘open-drain’ is assigned and
the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write
instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause
the ‘open-drain’ pin not to output a ‘zero’ when desired.
Note:
‘Open-drain’ outputs should not be pulled above VDD.
INPUT/OUTPUT PORTS
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Read buffer output
(a)
A
Y
Data direction register bit DDRn
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DDRn
1
1
0
0
A
0
1
0
1
Y
0
1
tri state
tri state


 Normal operation – tri state


1
1
0
0
0
1
0
1
low
—
high
high


 ‘Open-drain’


4
(b)
VDD
VDD
Px0
‘Open-drain’ output
(c)
DDRx, bit 0 = 0
Portx, bit 0 = 0
DDRx, bit 0 = 0
Portx, bit 0 = 0
Figure 4-3 Port logic levels
MC68HC05X16
INPUT/OUTPUT PORTS
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INPUT/OUTPUT PORTS
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MOTOROLA CAN MODULE (MCAN)
The MCAN includes all hardware modules necessary to implement the CAN transfer layer, which
represents the kernel of the CAN bus protocol as defined by BOSCH GmbH, the originators of the
CAN specification. For full details of the CAN protocol please refer to the published specifications.
5
Up to the message level, the MCAN is totally compatible with the full CAN implementation.
Functional differences are related to the object layer only. Whereas a full CAN controller provides
dedicated hardware for handling a set of messages, the MCAN is restricted to receiving and/or
transmitting messages on a message by message basis.
The MCAN will never initiate an overload frame. If the MCAN starts to receive a valid message
(one that passes the acceptance filter) and there is no receive buffer available for it then the
overrun flag in the CPU status register will be set. The MCAN will respond to overload frames
generated by other CAN nodes, as required by the CAN protocol. A summary of all the MCAN
frame formats is given in Figure 5-2 for reference. A diagram of the major blocks of the MCAN is
shown in Figure 5-1.
Bit timing
logic
Interface
management
logic
Line
interface
logic
Transceive
logic
Transmit
buffer
Error
management
logic
Receive
buffer 0
Receive
buffer 1
Bit stream
processor
Microprocessor related logic
Bus line related logic
MCAN
bus
line
Figure 5-1 MCAN block diagram
MC68HC05X16
MOTOROLA CAN MODULE (MCAN)
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d
d
11
12
Arbitration field
Stored in buffers
Acceptance
filtering
Identifier
11
d d d
r d d
4
6
Control field
Data
length
code
4
6
Control field
ID0
RTR
RB1
RB0
DLC3
12
Arbitration field
ID0
RTR
RB1
RB0
DLC3
Reserved bits
8N (0 ≤ N ≤ 8)
Data field
Data frame
16
CRC field
15
CRC
8
(number of bits = 44)
Bit stuffing
Stored in transmit/receive buffers
8
Remote frame
DLC0
DLC0
Start of frame
ID10
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r
7
End of frame
Note:
15
CRC
16
CRC field
(number of bits = 44 + 8N)
r r r r r r r r
CRC Del
Acknowledge
Ack Del
r r r r r r r r
7
End of frame
A remote frame is identical to a
data frame, except that the RTR
bit is recessive, and there is no
data field.
r
CRC Del
Acknowledge
Ack Del
5
Start of frame
ID10
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Figure 5-2 MCAN frame formats
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MOTOROLA CAN MODULE (MCAN)
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INT
8
Suspend
transmit
End of frame
or
error delimiter
or
overload delimiter
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Overload delimiter
Overload flag
d d d d d d d r r r r r r r r
8
Data frame
or
remote frame
Inter-frame space
or
overload frame
Inter-frame space
or
error frame
r r r d
Bus idle
6
Overload frame
r r r r r r r r r r r r r r r r r r r r
Any frame
3
Error delimiter
8
d d r r r r r r r r
≤6
Echo
error flag
Inter-frame space
d d d d d d d
Error flag
6
Start of frame
Data frame
or
remote frame
Error frame
Note:
Note:
Note:
An overload frame can only start
at the end of a frame.
Maximum echo of overload flag
is one bit.
INT = Intermission
Suspend transmission is only for
error passive nodes.
An error frame can start
anywhere in the middle of a
frame.
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5
Figure 5-2 MCAN frame formats (Continued)
MOTOROLA CAN MODULE (MCAN)
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5.1
TBF – Transmit buffer
The transmit buffer is an interface between the CPU and the bit stream processor (BSP) and is
able to store a complete message. The buffer is written by the CPU and read by the BSP. The CPU
may access this buffer whenever transmit buffer access is set to released. On requesting a
transmission (by setting transmission request in the MCAN command register to present) transmit
buffer access is set to locked, giving the BSP exclusive access to this buffer. The transmit buffer is
released after the message transfer has been completed or aborted.
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The TBF is 10 bytes long and holds the identifier (1 byte), the control field (1 byte) and the data
field (maximum length 8 bytes). The buffer is implemented as a single-ported RAM, with mutually
exclusive access by the CPU and the BSP.
5
5.2
RBF – Receive buffer
The receive buffer is an interface between the BSP and the CPU and stores a message received
from the bus line. Once filled by the BSP and allocated to the CPU (by the IML), the receive buffer
cannot be used to store subsequent received messages until the CPU has acknowledged the
reading of the buffer’s contents. Thus, unless the CPU releases a receive buffer within a protocol
defined time frame, future messages to be received may be lost.
To reduce the requirements on the CPU, two receive buffers (RBF0 and RBF1) are implemented.
While one receive buffer is allocated to the CPU, the BSP may write to the other buffer. RBF0 and
RBF1 are each 10 bytes long and hold the identifier (1 byte), the control field (1 byte) and the data
field (maximum length 8 bytes). The buffers are implemented as single-ported RAMs with mutually
exclusive access from the CPU and the BSP. The BSP signals the MCU to read the receive buffer
only when the message being received has an identifier that passes the acceptance filter. Note
that a message being transmitted will be automatically written to the receive buffer if the identifier
passes the acceptance filter. This is because it cannot be known, until after the first byte has been
stored, whether or not the transmitting node will lose arbitration to another node.
5.3
Interface to the MC68HC05X16 CPU
The MCAN handles all the communication transactions flowing across the serial bus. For example,
the CPU merely places a message to be transmitted into the transmit buffer and sets the TR bit.
The MCAN will begin transmitting the message when it has determined that the bus is idle. In the
event of a transmission error, the MCAN will initiate a repeated transmission automatically.
MOTOROLA CAN MODULE (MCAN)
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In a similar manner, the CPU module is notified that a message has been received only if it was
error free. If any error occurs, the MCAN signals the error within the CAN protocol without CPU
intervention.
The MCAN within the MC68HC05X16 is controlled using a block of 30 registers. This comprises
10 control registers, 10 Transmit buffer registers and 10 receive buffer registers. These registers
are memory mapped between $20 and $3D (see Figure 5-3).
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Note:
There is an offset of $20 between the MC68HC05X16 addresses and the MCAN
internal addresses, i.e. MCAN addresses $00 to $1D, as defined in the BOSCH CAN
specification, are mapped to MC68HC05X16 addresses $20 to $3D.
5
MCAN register blocks
MCAN registers
Control register
$0020
MCAN
control registers
10 bytes
Command register
$0021
$0020
$0029
$002A
Status register
$0022
Interrupt register
$0023
Acceptance code register
$0024
Acceptance mask register
$0025
Bus timing register 1
$0026
Bus timing register 2
$0027
Output control register
$0028
Test register
$0029
Identifier
$002A
RTR-bit, data length code
$002B
Data segment byte 1
$002C
Data segment byte 2
$002D
Data segment byte 3
$002E
Data segment byte 4
$002F
Data segment byte 5
$0030
Data segment byte 6
$0031
Data segment byte 7
$0032
Data segment byte 8
$0033
MCAN
transmit buffer
10 bytes
$0033
$0034
MCAN
receive buffer
10 bytes
$003D
Identifier
$0034
RTR-bit, data length code
$0035
Data segment byte 1
$0036
Data segment byte 2
$0037
Data segment byte 3
$0038
Data segment byte 4
$0039
Data segment byte 5
$003A
Data segment byte 6
$003B
Data segment byte 7
$003C
Data segment byte 8
$003D
Figure 5-3 MCAN module memory map
MC68HC05X16
MOTOROLA CAN MODULE (MCAN)
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5.3.1
MCAN control register (CCNTRL)
This register may be read or written to by the MCU; only the RR bit is affected by the MCAN.
Address
5
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OIE
EIE
TIE
RIE
RR
Reset
condition
State
on reset
External reset 0u - u uuu1
MCAN control (CCNTRL)
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$0020 MODE SPD
RR bit set
0u - u uuu1
MODE — Undefined mode
This bit must never be set by the CPU as this would result in the transmit and receive buffers being
mapped out of memory. The bit is cleared on reset, and should be left in this state for normal
operation.
SPD — Speed mode
1 (set)
–
0 (clear) –
Slow – Bus line transitions from both ‘recessive’ to ‘dominant’ and
from ‘dominant’ to ‘recessive’ will be used for resynchronization.
Fast – Only transitions from ‘recessive’ to ‘dominant’ will be used for
resynchronization.
OIE — Overrun interrupt enable
1 (set)
–
0 (clear) –
Enabled – The CPU will get an interrupt request whenever the
Overrun Status bit gets set.
Disabled – The CPU will get no overrun interrupt request.
EIE — Error interrupt enable
1 (set)
–
0 (clear) –
Enabled – The CPU will get an interrupt request whenever the error
status or bus status bits in the CSTAT register change.
Disabled – The CPU will get no error interrupt request.
TIE — Transmit interrupt enable
1 (set)
–
0 (clear) –
Enabled – The CPU will get an interrupt request whenever a
message has been successfully transmitted, or when the transmit
buffer is accessible again following an ABORT command.
Disabled – The CPU will get no transmit interrupt request.
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RIE — Receive interrupt enable
1 (set)
–
0 (clear) –
Enabled – The CPU will get an interrupt request whenever a
message has been received free of errors.
Disabled – The CPU will get no receive interrupt request.
RR — Reset request
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When the MCAN detects that RR has been set it aborts the current transmission or reception of a
message and enters the reset state. A reset request may be generated by either an external reset
or by the CPU or by the MCAN. The RR bit can be cleared only by the CPU. After the RR bit has
been cleared, the MCAN will start normal operation in one of two ways. If RR was generated by
an external reset or by the CPU, then the MCAN starts normal operation after the first occurrence
of 11 recessive bits. If, however, the RR was generated by the MCAN due to the BS bit being set
(see Section 5.3.3) the MCAN waits for 128 occurrences of 11 recessive bits before starting
normal operation.
5
A reset request should not be generated by the CPU during a message transmission. Ensure that
a message is not being transmitted as follows:
if TCS in CSTAT is clear – set AT in CCOM (use STA or STX), read CSTAT.
if TS in CSTAT is set – wait until TS is clear.
Note that a CPU-generated reset request does not change the values in the transmit and receive
error counters.
1 (set)
–
0 (clear) –
Note:
5.3.2
Present – MCAN will be reset.
Absent – MCAN will operate normally.
The following registers may only be accessed when reset request = present: CACC,
CACM, CBT0, CBT1, and COCNTRL.
MCAN command register (CCOM)
This is a write only register; a read of this location will always return the value $FF.
This register may be written only when the RR bit in CCNTRL is clear.
Do not use read-modify-write instructions on this register (e.g. BSET, BCLR).
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MCAN command (CCOM) $0020
RX0
RX1 COMPSEL SLEEP COS
RRB
AT
TR
MC68HC05X16
MOTOROLA CAN MODULE (MCAN)
Reset
condition
State
on reset
External reset 00u0 0000
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RR bit set
00u0 0000
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RX0 — Receive pin 0 (passive) (Refer to Figure 5-6)
1 (set)
–
VDD/2 will be connected to the input comparator. The RX0 pin is
disconnected.
0 (clear) –
The RX0 pin will be connected to the input comparator. VDD/2 is
disconnected.
RX1 — Receive pin 1 (passive) (Refer to Figure 5-6)
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1 (set)
5
Note:
–
VDD/2 will be connected to the input comparator. The RX1 pin is
disconnected.
0 (clear) –
The RX1 pin will be connected to the input comparator. VDD/2 is
disconnected.
If both RX0 and RX1 are set, or both are clear, then neither of the RX pins will be
disconnected.
COMPSEL — Comparator selector
1 (set)
–
0 (clear) –
RX0 and RX1 will be compared with VDD/2 during sleep mode (see
Figure 5-6).
RX0 will be compared with RX1 during sleep mode.
SLEEP — Go to sleep
1 (set)
Note:
–
Sleep – The MCAN will go into sleep mode, as long as there are no
interrupts pending and there is no activity on the bus. Otherwise the
MCAN will issue a wake-up interrupt.
0 (clear) –
Wake-up – The MCAN will function normally. If SLEEP is cleared by
the CPU then the MCAN will waken up, but will not issue a wake-up
interrupt.
If SLEEP is set during the reception or transmission of a message, the MCAN will
generate an immediate wake-up interrupt. (This allows for a more orthogonal software
implementation on the CPU.) This will have no effect on the transfer layer, i.e. no
message will be lost or corrupted.
The CAF flag in the EEPROM control register indicates whether or not sleep mode was
entered successfully.
A node that was sleeping and has been awakened by bus activity will not be able to
receive any messages until its oscillator has started and it has found a valid end of
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frame sequence (11 recessive bits). The designer must take this into consideration
when planning to use the sleep command.
COS — Clear overrun status
1 (set)
–
0 (clear) –
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This clears the read-only data overrun status bit in the CSTAT register
(see Section 5.3.3). It may be written at the same time as RRB.
No action.
RRB — Release receive buffer
When set this releases the receive buffer currently attached to the CPU, allowing the buffer to be
reused by the MCAN. This may result in another message being received, which could cause
another receive interrupt request (if RIE is set). This bit is cleared automatically when a message
is received, i.e. when the RS bit (see Section 5.3.3) becomes set.
1 (set)
–
0 (clear) –
5
Released – receive buffer is available to the MCAN.
No action.
AT — Abort transmission
When this bit is set a pending transmission will be cancelled if it is not already in progress, allowing
the transmit buffer to be loaded with a new (higher priority) message when the buffer is released.
If the CPU tries to write to the buffer when it is locked, the information will be lost without being
signalled. The status register can be checked to see if transmission was aborted or is still in
progress.
1 (set)
–
0 (clear) –
Present – Abort transmission of any pending messages.
No action.
TR — Transmission request
1 (set)
–
0 (clear) –
MC68HC05X16
Present – Depending on the transmission buffer’s content, a data
frame or a remote frame will be transmitted.
No action. This will not cancel a previously requested transmission;
the abort transmission command must be used to do this.
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5.3.3
MCAN status register (CSTAT)
This is a read only register; only the MCAN can change its contents.
MCAN status
(CSTAT)
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5
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0022
BS
ES
TS
RS
TCS
TBA
DO
RBS
Reset condition
State
on reset
External reset 0000 1100
RR bit set
uu00 1100
BS — Bus status
This bit is set (off-bus) by the MCAN when the transmit error counter reaches 256. The MCAN will
then set RR and will remain off-bus until the CPU clears RR again. At this point the MCAN will wait
for 128 successive occurrences of a sequence of 11 recessive bits before clearing BS and
resetting the read and write error counters. While off-bus the MCAN does not take part in bus
activities.
1 (set)
–
0 (clear) –
Off-bus – The MCAN is not participating in bus activities.
On-bus – The MCAN is operating normally.
ES — Error status
1 (set)
–
0 (clear) –
Error – Either the read or the write error counter has reached the
CPU warning limit of 96.
Neither of the error counters has reached 96.
TS — Transmit status
1 (set)
–
0 (clear) –
Transmit – The MCAN has started to transmit a message.
Idle – If the receive status bit is also clear then the MCAN is idle;
otherwise it is in receive mode.
RS — Receive status
1 (set)
–
Receive – The MCAN entered receive mode from idle, or by losing
arbitration during transmission.
0 (clear) –
Idle – If the transmit status bit is also clear then the MCAN is idle;
otherwise it is in transmit mode.
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TCS — Transmission complete status
This bit is cleared by the MCAN when TR becomes set. When TCS is set it indicates that the last
requested transmission was successfully completed. If, after TCS is cleared, but before
transmission begins, an abort transmission command is issued then the transmit buffer will be
released and TCS will remain clear. TCS will then only be set after a further transmission is both
requested and successfully completed.
1 (set)
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–
Complete – Last requested transmission successfully completed.
0 (clear) –
Incomplete – Last requested transmission not complete.
TBA — Transmit buffer access
When clear, the transmit buffer is locked and cannot be accessed by the CPU. This indicates that
either a message is being transmitted, or is awaiting transmission. If the CPU writes to the transmit
buffer while it is locked, then the bytes will be lost without this being signalled.
1 (set)
–
5
Released – The transmit buffer may be written to by the CPU.
0 (clear) –
Locked – The CPU cannot access the transmit buffer.
DO — Data overrun
This bit is set when both receive buffers are full and there is a further message to be stored. In this
case the new message is dropped, but the internal logic maintains the correct protocol. The MCAN
does not receive the message, but no warning is sent to the transmitting node. The MCAN clears
DO when the CPU sets the COS bit in the CCOM register.
Note that data overrun can also be caused by a transmission, since the MCAN will temporarily
store an outgoing frame in a receive buffer in case arbitration is lost during transmission.
1 (set)
–
0 (clear) –
Overrun – Both receive buffers were full and there was another
message to be stored.
Normal operation.
RBS — Receive buffer status
This bit is set by the MCAN when a new message is available. When clear this indicates that no
message has become available since the last RRB command. The bit is cleared when RRB is set.
However, if the second receive buffer already contains a message, then control of that buffer is
given to the CPU and RBS is immediately set again. The first receive buffer is then available for
the next incoming message from the MCAN.
1 (set)
–
0 (clear) –
MC68HC05X16
Full – A new message is available for the CPU to read.
Empty – No new message is available.
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5.3.4
MCAN interrupt register (CINT)
All bits of this register are read only; all are cleared by a read of the register.
This register must be read in the interrupt handling routine in order to enable further interrupts.
Address
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5
MCAN interrupt
(CINT)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
WIF
OIF
EIF
TIF
RIF
Reset condition
State
on reset
External reset - - - 0 0000
$0023
RR bit set
- - - u 0u00
WIF — Wake-up interrupt flag
If the MCAN detects bus activity whilst it is asleep, it clears the SLEEP bit in the CCOM register;
the WIF bit will then be set. WIF is cleared by reading the MCAN interrupt register (CINT), or by
an external reset.
1 (set)
–
0 (clear) –
MCAN has detected activity on the bus and requested wake-up.
No wake-up interrupt has occurred.
OIF — Overrun interrupt flag
When OIE is set then this bit will be set when a data overrun condition is detected. Like all the bits
in this register, OIF is cleared by reading the register, or when reset request is set.
1 (set)
–
0 (clear) –
A data overrun has been detected.
No data overrun has occurred.
EIF — Error interrupt flag
When EIE is set then this bit will be set by a change in the error or bus status bits in the MCAN
status register. Like all the bits in this register, EIF is cleared by reading the register, or by an
external reset.
1 (set)
–
0 (clear) –
There has been a change in the error or bus status bits in CSTAT.
No error interrupt has occurred.
TIF — Transmit interrupt flag
The TIF bit is set at the end of a transmission whenever both the TBA and TIE bits are set. Like all
the bits in this register, TIF is cleared by reading the register, or when reset request is set.
1 (set)
–
0 (clear) –
Transmission complete, the transmit buffer is accessible.
No transmit interrupt has occurred.
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RIF — Receive interrupt flag
The RIF bit is set by the MCAN when a new message is available in the receive buffer, and the RIE
bit in CCNTRL is set. At the same time RBS is set. Like all the bits in this register, RIF is cleared
by reading the register, or when reset request is set.
1 (set)
–
0 (clear) –
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5.3.5
A new message is available in the receive buffer.
No receive interrupt has occurred.
MCAN acceptance code register (CACC)
On reception each message is written into the current receive buffer. The MCU is only signalled to
read the message however, if it passes the criteria in the acceptance code and acceptance mask
registers (accepted); otherwise, the message will be overwritten by the next message (dropped).
Note:
5
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
MCAN acceptance code (CACC)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0024
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Undefined
AC7 – AC0 — Acceptance code bits
AC7 – AC0 comprise a user defined sequence of bits with which the 8 most significant bits of the
data identifier (ID10 – ID3) are compared. The result of this comparison is then masked with the
acceptance mask register. Once a message has passed the acceptance criterion the respective
identifier, data length code and data are sequentially stored in a receive buffer, providing there is
one free. If there is no free buffer, the data overrun condition will be signalled.
On acceptance the receive buffer status bit is set to full and the receive interrupt bit is set (provided
RIE = enabled).
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5.3.6
MCAN acceptance mask register (CACM)
The acceptance mask register specifies which of the corresponding bits in the acceptance code
register are relevant for acceptance filtering.
Note:
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5
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
MCAN acceptance mask (CACM)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0025
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
Undefined
AM0 – AM7 — Acceptance mask bits
When a particular bit in this register is clear this indicates that the corresponding bit in the
acceptance code register must be the same as its identifier bit, before a match will be detected.
The message will be accepted if all such bits match. When a bit is set, it indicates that the state of
the corresponding bit in the acceptance code register will not affect whether or not the message
is accepted.
1 (set)
–
0 (clear) –
5.3.7
Note:
Ignore corresponding acceptance code register bit.
Match corresponding acceptance code register and identifier bits.
MCAN bus timing register 0 (CBT0)
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
MCAN bus timing 0 (CBT0)
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0026
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0 Undefined
SJW1, SJW0 — Synchronization jump width bits
The synchronization jump width defines the maximum number of system clock (tSCL) cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 5-1).
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Table 5-1 Synchronization jump width
SJW1
0
0
1
1
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SJW0
0
1
0
1
Synchronization jump width
1 tSCL cycle
2 tSCL cycles
3 tSCL cycles
4 tSCL cycles
BRP5 – BRP0 — Baud rate prescaler bits
These bits determine the MCAN system clock cycle time (tSCL), which is used to build up the
individual bit timing, according to Table 5-2 and the formula in Figure 5-4.
5
Table 5-2 Baud rate prescaler
BRP5
0
0
0
0
:
:
1
fosc
OSC1
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
Divide by
2
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler value (P)
1
2
3
4
:
:
64
fosc/2
Prescaler (P)
tSCL =
2P
fosc
MCAN module system clock
Divide by
10, 8, 4 or 2
fOP
MCU bus clock
Figure 5-4 Oscillator block diagram
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5.3.8
MCAN bus timing register 1 (CBT1)
This register can only be accessed when the reset request bit in the CCNTRL register is set.
MCAN bus timing 1 (CBT1)
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5
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
$0027
SAMP TSEG22TSEG21TSEG20TSEG13TSEG12TSEG11TSEG10 Undefined
SAMP — Sampling
This bit determines the number of samples of the serial bus to be taken per bit time. When set three
samples per bit are taken. This sample rate gives better rejection of noise on the bus, but
introduces a one bit delay to the bus sampling. For higher bit rates SAMP should be cleared, which
means that only one sample will be taken per bit.
1 (set)
–
0 (clear) –
Three samples per bit.
One sample per bit.
TSEG22 – TSEG10 — Time segment bits
Time segments within the bit time fix the number of clock cycles per bit time, and the location of
the sample point.
BIT_TIME
SYNC_SEG
Transmit point
TSEG 1
1 clock cycle
tSCL
TSEG 2
Sample point
SYNC_SEG
Transmit point
Figure 5-5 Segments within the bit time
SYNC_SEG
System expects transitions to occur on the bus during this period.
Transmit point
A node in transmit mode will transfer a new value to the MCAN bus at this point.
Sample point
A node in receive mode will sample the bus at this point. If the three samples per
bit option is selected then this point marks the position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 5-3.
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of
bus clock cycles (tSCL) per bit (as shown above).
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Table 5-3 Time segment values
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TSEG13
0
0
0
.
.
1
TSEG12 TSEG11 TSEG10
0
0
1
0
1
0
0
1
1
.
.
.
.
.
.
1
1
1
Time segment 1
2 tSCL cycles
3 tSCL cycles
4 tSCL cycles
.
.
16 tSCL cycles
TSEG22 TSEG21 TSEG20
0
0
1
.
.
.
.
.
.
1
1
1
Time segment 2
2 tSCL cycles
.
.
8 tSCL cycles
Calculation of the bit time
5
BIT_TIME = SYNC_SEG + TSEG1 + TSEG2
Note:
TSEG2 must be at least 2 tSCL, i.e. the configuration bits must not be 000. (If three
samples per bit mode is selected then TSEG2 must be at least 3 tSCL.)
TSEG1 must be at least as long as TSEG2.
The synchronization jump width (SJW) may not exceed TSEG2, and must be at least
tSCL shorter than TSEG1 to allow for physical propagation delays.
i.e. in terms of tSCL:
SYNC_SEG = 1
TSEG1 ≥ SJW + 1
TSEG1 ≥ TSEG2
TSEG2 ≥ SJW
and
TSEG2 ≥ 2
(SAMP = 0)
or
TSEG2 ≥ 3
(SAMP = 1)
These boundary conditions result in minimum bit times of 5 tSCL, for one sample, and 7 tSCL, for
three samples per bit.
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5.3.9
MCAN output control register (COCNTRL)
This register allows the setup of different output driver configurations under software control. The
user may select active pull-up, pull-down, float or push-pull output.
Note:
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5
This register can only be accessed when the reset request bit in the CCNTRL register
is set.
Address
MCAN output control (COCNTRL)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0028 OCTP1 OCTN1 OCPOL1 OCTP0 OCTN0 OCPOL0 OCM1 OCM0 Undefined
OCM1 and OCM0 — Output control mode bits
The values of these two bits determine the output mode, as shown in Table 5-4.
Table 5-4 Output control modes
Note:
OCM1
0
0
OCM0
0
1
1
0
1
1
Function
Biphase mode
Not used
Normal mode 1
Bit stream transmitted on both TX0 and TX1
Normal mode 2
TX0 - bit sequence
TX1 - bus clock (txclk)
The transmit clock (txclk) is used to indicate the end of the bit time and will be high during
the SYNC_SEG.
For all the following modes of operation, a dominant bit is internally coded as a zero, a
recessive as a one. The other output control bits are used to determine the actual
voltage levels transmitted to the MCAN bus for dominant and recessive bits.
Biphase mode
If the CAN modules are isolated from the bus lines by a transformer then the bit stream has to be
coded so that there is no resulting dc component. There is a flip-flop within the MCAN that keeps
the last dominant configuration; its direct output goes to TX0 and its complement to TX1. The
flip-flop is toggled for each dominant bit; dominant bits are thus sent alternately on TX0 and TX1;
i.e. the first dominant bit is sent on TX0, the second on TX1, the third on TX0 and so on. During
recessive bits, all output drivers are deactivated (i.e. high impedance).
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Normal mode 1
In contrast to biphase mode the bit representation is time invariant and not toggled.
Normal mode 2
For the TX0 pin this is the same as normal mode 1, however the data stream to TX1 is replaced
by the transmit clock. The rising edge of the transmit clock marks the beginning of a bit time. The
clock pulse will be tSCL long.
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Other output control bits
The other six bits in this register control the output driver configurations, to determine the format
of the output signal for a given data value (see Figure 5-6).
OCTP0/1 – These two bits control whether the P-type output control transistors are enabled.
5
OCTN0/1 – These two bits control whether the N-type output control transistors are enabled.
OCPOL0/1 – These two bits determine the driver output polarity for each of the MCAN bus lines
(TX0, TX1).
TP0/1 and TN0/1 – These are the resulting states of the output transistors.
TD – This is the internal value of the data bit to be transferred across the MCAN bus. (A zero
corresponds to a dominant bit, a one to a recessive.)
The actions of these bits in the output control register are as shown in Table 5-5.
Table 5-5 MCAN driver output levels
Mode
Float
Pull-down
Pull-up
Push-pull
MC68HC05X16
TD
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OCPOLi
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
OCTPi
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
OCTNi
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TPi
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
Off
Off
On
On
Off
TNi
Off
Off
Off
Off
On
Off
Off
On
Off
Off
Off
Off
On
Off
Off
On
TXi output level
Float
Float
Float
Float
Low
Float
Float
Low
Float
High
High
Float
Low
High
High
Low
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5.3.10
Transmit buffer identifier register (TBI)
Transmit buffer identifier (TBI)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$002A
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
Undefined
ID10 – ID3 — Identifier bits
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The identifier consists of 11 bits (ID10 – ID0). ID10 is the most significant bit and is transmitted first
on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for
the smallest binary number. The three least significant bits are contained in the TRTDL register.
The seven most significant bits must not all be recessive.
5.3.11
Remote transmission request and data length code
register (TRTDL)
RTR and data length code (TRTDL)
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$002B
ID2
ID1
ID0
RTR
DLC3
DLC2
DLC1
DLC0 Undefined
ID2 – ID0 — Identifier bits
These bits contain the least significant bits of the transmit buffer identifier.
RTR — Remote transmission request
1 (set)
–
0 (clear) –
A remote frame will be transmitted.
A data frame will be transmitted.
DLC3 – DLC0 — Data length code bits.
The data length code contains the number of bytes (data byte count) of the respective message.
At transmission of a remote frame, the data length code is ignored, forcing the number of bytes to
be 0. The data byte count ranges from 0 to 8 for a data frame. Table 5-6 shows the effect of setting
the DLC bits.
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Table 5-6 Data length codes
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Data length code
DLC2
DLC1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
DLC3
0
0
0
0
0
0
0
0
1
5.3.12
Data byte
count
DLC0
0
1
0
1
0
1
0
1
0
0
1
2
3
4
5
6
7
8
5
Transmit data segment registers (TDS) 1 – 8
Transmit data segment (TDS)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$002C –
$0033
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Undefined
DB7 – DB0 — data bits
These data bits in the eight data segment registers make up the bytes of data to be transmitted.
The number of bytes to be transmitted is determined by the data length code.
5.3.13
Receive buffer identifier register (RBI)
The layout of this register is identical to the TBI register (see Section 5.3.10).
Receive buffer identifier (RBI)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0034
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
Undefined
(Note that there are actually two receive buffer register sets, but switching between them is
handled internally by the MCAN.)
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5.3.14
Remote transmission request and data length code
register (RRTDL)
The layout of this register is identical to the TRTDL register (see Section 5.3.11).
RTR and data length code (RRTDL)
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5.3.15
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0035
ID2
ID1
ID0
RTR
DLC3
DLC2
DLC1
DLC0 Undefined
Receive data segment registers (RDS) 1 – 8
The layout of these registers is identical to the TDSx registers (see Section 5.3.12).
Receive data segment (RDS)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0036 –
$003D
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Undefined
(Note that there are actually two receive buffer register sets, but switching between them is
handled internally by the MCAN.)
5.4
Interface to the MCAN bus
Physically, the MCAN bus may be composed of two wires. The bus can take on one of two values:
dominant or recessive. During simultaneous transmission of dominant and recessive bits by two
or more CAN modules the resulting bus value will be dominant. (For example, with a wired-AND
implementation of the bus, the dominant level would correspond to a logic 0, and the recessive
level to a logic 1.)
The two wires of the MCAN bus are designated CANH and CANL. The voltage levels appearing
on these lines are designated VCANH and VCANL. A simple termination network is required for each
wire. Figure 5-6 shows the physical interface circuitry within the MCAN module, and its connection
to the MCAN bus with a typical low speed (<125 kbaud) hardware interface. (Note that the
suggested values shown in the diagram are subject to change in the future.)
For the voltage and resistor values shown in Figure 5-6 the voltages on the MCAN bus are:
–
Recessive level:
VCANH = 3.25 V
VCANL = 1.75 V
–
Dominant level:
VCANH = 1.00 V
VCANL = 4.00 V
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Termination
network
1.75V 3.25V
TXP0
2 kΩ 2 kΩ
680Ω
TX0
TXN0
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TXP1
680Ω
5
TX1
TXN1
150kΩ
RX0 passive
RX0
Data
+
AC
–
150kΩ
RX1 passive
RX1
+
SC
–
2 x 30kΩ
+
SC
–
&
+
SC
–
CANL
CANH
MCAN bus lines
COMPSEL
VDDH
Wake-up
VDD/2
Internal to the MC68HC05X16 MCAN module
Figure 5-6 A typical physical interface between the MCAN and the MCAN bus lines
MC68HC05X16
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If several CAN modules are driving a dominant level on the bus at the same time then the values
for VCANH and VCANL can go to 0.3 and 4.7 volts respectively. The residual 0.3 V is due to the
voltage drop across the diodes and driver transistors in the transmission circuit.
The receiver part of the network uses two identical voltage divider networks, with a divide ratio of
6:1 (resistor values of 150kΩ and 30kΩ) referenced to VDD/2. This increases the common mode
range of the input comparator on the physical bus lines. If the common mode range of the
comparator at its inputs is 1.5 to 3.5 volts then, for VDD = 5.0 V, the common mode range will be
increased to –3.5 to +8.5 volts on the bus lines.
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5.4.1
Single wire operation
In the event of a bus fault occurring, limited operation of the MCAN bus may still be possible,
depending on the nature of the fault. If the fault is due to a short circuit between the two bus lines
or between one of the lines and ground, battery voltage or some other potential, it is possible to
identify (using a special software procedure) the line on which the fault exists and to switch the
corresponding comparator input from the faulty line to the VDD/2 reference supply. At the same
time the driver transistors to the faulty line should also be switched off. This will allow
communication to continue on the bus. One result of this mode of one wire transmission is a
significant reduction in the common mode range of the input comparator.
Switching to one wire operation is achieved using the control bits RX0-passive and RX1-passive
in the MCAN command register, located at address $21. Setting either of these bits will result in
the corresponding input being disconnected from the bus and connected to VDD/2.
5.5
Sleep mode
If the SLEEP bit in the MCAN command register is set by the processor the MCAN will go to sleep,
unless it is active. If there is activity on the MCAN bus lines, or there is an interrupt pending, the
MCAN is deemed to be active and will not go to sleep; a wake-up interrupt will be generated by
the MCAN in these circumstances. The SLEEP bit may also be cleared by the processor, in which
case no wake-up interrupt will be generated. Note that this bit is write-only by the CPU, and it is
not possible therefore to check whether sleep mode has been entered by reading it. However, the
CAF bit in the EEPROM control register is set when the MCAN is asleep, and cleared when it is
woken up (see Section 3.5.1).
In order to minimize power consumption, the active comparator is switched off and the sleep
comparator circuitry is used to detect activity on the bus. When in sleep mode the MCAN stops its
own clocks, leaving the MCU in normal run mode. (Similarly a STOP instruction will stop the
processor clocks, leaving the MCAN in run mode.) The on-chip oscillator will stop only if the MCAN
is in sleep mode and the MCU executes a STOP instruction. There is a time delay between the
STOP instruction being executed and the oscillator stopping. During this time it is possible that the
MCAN will come out of sleep mode, and hence prevent the oscillator from stopping.
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When a dominant level is detected on the MCAN bus, the MCAN is woken up and a wake-up
interrupt is generated.
Under normal operation the two MCAN bus lines are forced to complementary logic levels. The
level of one of the two wires can be disregarded and replaced by VDD/2 by setting one of the control
bits, RX0 or RX1.
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5.5.1
Sleep comparator reference
When the COMPSEL bit in the MCAN command register ($21) is cleared the sleep comparator
inputs are the same as for the active comparator. However, when the COMPSEL bit is set each
input is compared with VDD/2 (VDDH – see Figure 5-6) to detect a dominant level. For further
details of the active comparator, the sleep comparator and VDDH, refer to Section 12.
MC68HC05X16
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PROGRAMMABLE TIMER
The programmable timer on the MC68HC05X32 consists of a 16-bit read-only free-running
counter, with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry. The
timer can be used for many purposes including measuring pulse length of two input signals and
generating two output signals. Pulse lengths for both input and output signals can vary from
several microseconds to many seconds. In addition, it works in conjunction with the pulse width
modulation (PWM) system to execute two 8-bit D/A PLM (pulse length modulation) conversions,
with a choice of two repetition rates. The timer is also capable of generating periodic interrupts or
indicating passage of an arbitrary multiple of four CPU cycles. A block diagram is shown in
Figure 6-1, and timing diagrams are shown in Figure 6-2, Figure 6-3, Figure 6-4 and Figure 6-5.
6
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (except the PLMA and PLMB which use one 8-bit register for each). These registers
contain the high and low byte of that functional segment. Accessing the low byte of a specific timer
function allows full control of that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full
details of which are contained in this section.
Note:
6.1
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
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Internal bus
8
Internal
processor
clock
High
byte
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Low
byte
Output
compare
register 1
High
byte
Output
compare
register 2
$0016
$0017
8-bit
buffer
Low
byte
High
byte
$001E
$001F
÷4
16-bit
$0018
free-running
$0019
counter
Counter
alternate
register
COP watchdog
counter input
To PLM
6
High
byte
Low
byte
Low
byte
High
byte
Input capture $0014
register 1 $0015
Low
byte
Input capture $001C
register 2 $001D
$001A
$001B
Internal timer bus
Output
compare
circuit 1
Edge
detect
circuit 1
Overflow
detect
circuit
Output
compare
circuit 2
Edge
detect
circuit 2
TCAP2
pin
TCAP1
pin
D
+
C
D
7
6
5
4
3
ICF1
OCF1
TOF
ICF2
OCF2
+
Timer status
register
$0013
ICIE
OCIE
TOIE
FOLV2
FOLV1
OLVL2
IEDG1
OLVL1
C
Q
TCMP2
pin
Latch
Q
TCMP1
pin
Latch
Timer control
register
$0012
Interrupt circuit
Input capture
interrupt vector
$3FF8,9
Output compare
interrupt vector
$3FF6,7
Overflow interrupt
vector
$3FF4,5
Figure 6-1 16-bit programmable timer block diagram
PROGRAMMABLE TIMER
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6.1.1
Counter register and alternate counter register
Address
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bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Timer counter high
$0018
1111 1111
Timer counter low
$0019
1111 1100
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Alternate counter high
$001A
1111 1111
Alternate counter low
$001B
1111 1100
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter
register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read
of the free-running counter or alternate counter register first addresses the more significant byte
(MSB) ($18 or $1A), the LSB is transferred to a buffer. This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times. This buffer is accessed when reading the
free-running counter or alternate counter register LSB and thus completes a read sequence of the
total counter value. In reading either the free-running counter or alternate counter register, if the
MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag (TOF)
is set when the counter register LSB is read then a read of the timer status register (TSR) will clear
the flag.
6
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles. TOF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
In some particular timing control applications it may be desirable to reset the 16-bit free running
counter under software control. When the low byte of the counter ($19 or $1B) is written to, the
counter is configured to its reset value ($FFFC).
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($18 or $1A), then the reset counter operation
terminates the access sequence.
Warning: This operation may affect the function of the watchdog system (see Section 10.1.4).
The PLM results will also be affected while resetting the counter.
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6.2
Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
6.2.1
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Timer control register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
Timer control (TCR)
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
bit 6
bit 5
$0012
ICIE
OCIE
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLV1 0000 00u0
ICIE — Input captures interrupt enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer
status register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
OCIE — Output compares interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer
status register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
TOIE — Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) –
Interrupt disabled.
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FOLV2 — Force output compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note
that this bit does not affect the OCF2 bit of the status register (see Section 6.4.3).
1 (set)
–
0 (clear) –
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OLV2 bit forced to output level latch.
No effect.
FOLV1 — Force output compare 1
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note
that this bit does not affect the OCF1 bit of the status register (see Section 6.4.3).
1 (set)
–
0 (clear) –
OLV1 bit forced to output level latch.
No effect.
6
OLV2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
–
A high output level will appear on the TCMP2 pin.
0 (clear) –
A low output level will appear on the TCMP2 pin.
IEDG1 — Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set)
Note:
–
TCAP1 is positive-going edge sensitive.
0 (clear) –
TCAP1 is negative-going edge sensitive.
There is no need for an equivalent bit for the input capture register 2 as TCAP2 is
negative-going edge sensitive only.
OLV1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
–
A high output level will appear on the TCMP1 pin.
0 (clear) –
A low output level will appear on the TCMP1 pin.
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6.2.2
Timer status register (TSR)
The timer status register ($13) contains the status bits corresponding to the timer interrupt
conditions – ICF1, OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
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6
Address
bit 7
bit 6
bit 5
bit 4
bit 3
$0013
ICF1
OCF1
TOF
ICF2
OCF2
Timer status (TSR)
bit 2
bit 1
bit 0
State
on reset
Undefined
ICF1 — Input capture flag 1
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
the TSR and then the input capture low register 1 ($15).
1 (set)
–
0 (clear) –
A valid input capture has occurred.
No input capture has occurred.
OCF1 — Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then the output compare 1 low register ($17).
1 (set)
–
0 (clear) –
A valid output compare has occurred.
No output compare has occurred.
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set. TOF is cleared by reading the TSR and the counter low register ($19).
1 (set)
–
0 (clear) –
Timer overflow has occurred.
No timer overflow has occurred.
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1
The timer status register is read or written when TOF is set, and
2
The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
PROGRAMMABLE TIMER
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ICF2 — Input capture flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the input capture low register 2 ($1D).
1 (set)
–
A valid (negative) input capture has occurred.
0 (clear) –
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No input capture has occurred.
OCF2 — Output compare flag 2
This bit is set when the output compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then the output compare 2 low register ($1F).
1 (set)
–
A valid output compare has occurred.
0 (clear) –
6.3
No output compare has occurred.
6
Input capture
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers: input capture register 1 (ICR1) and input capture register 2 (ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
6.3.1
Input capture register 1 (ICR1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture high 1
$0014
Undefined
Input capture low 1
$0015
Undefined
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1). When an input capture 1 occurs, the corresponding flag ICF1 in TSR is set.
An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set. The 8 most
significant bits are stored in the input capture high 1 register at $14, the 8 least significant bits in
the input capture low 1 register at $15.
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6
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or
clear. The input capture register 1 always contains the free-running counter value that corresponds
to the most recent input capture 1. After a read of the input capture 1 register MSB ($14), the
counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture 1 register LSB ($15) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
Reset does not affect the contents of the input capture 1 register, except when exiting STOP mode
(see Section 6.6).
6.3.2
Input capture register 2 (ICR2)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Input capture high 2
$001C
Undefined
Input capture low 2
$001D
Undefined
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is
set.The 8 most significant bits are stored in the input capture 2 high register at $1C, the 8 least
significant bits in the input capture 2 low register at $1D.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F) is set
or clear. The input capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register 2 LSB ($1C) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode
(see Section 6.6).
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6.4
Output compare
‘Output compare’ is a technique which may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2).
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Note:
The same output compare interrupt enable bit (OCIE) is used for the two output
compares.
6.4.1
Output compare register 1 (OCR1)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high 1
$0016
Undefined
Output compare low 1
$0017
Undefined
6
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register 1 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF1) in the timer status register is set and the output level (OLVL1) is transferred to pin TCMP1.
The output compare register 1 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare
1 function. The processor can write to either byte of the output compare register 1 without affecting
the other byte. The output level (OLVL1) bit is clocked to the output level register and hence to the
TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear. The minimum time required
to update the output compare register 1 is a function of the program rather than the internal
hardware. Because the output compare flag 1 and the output compare register 1 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
Write to output compare high 1 to inhibit further compares;
–
Read the timer status register to clear OCF1 (if set);
–
Write to output compare low 1 to enable the output compare 1 function.
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The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
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6.4.2
Output compare register 2 (OCR2)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Output compare high 2
$001E
Undefined
Output compare low 2
$001F
Undefined
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output
compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the compare
2 function. The processor can write to either byte of the output compare register 2 without affecting
the other byte. The output level (OLVL2) bit is clocked to the output level register and hence to the
TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear. The minimum time required
to update the output compare register 2 is a function of the program rather than the internal
hardware. Because the output compare flag 2 and the output compare register 2 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
Write to output compare high 2 to inhibit further compares;
–
Read the timer status register to clear OCF2 (if set);
–
Write to output compare low 2 to enable the output compare 2 function.
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The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
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6.4.3
Software force compare
A software force compare is required in many applications. To achieve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOLV2 for OCR2) in the timer control register are used. These bits always read as ‘zero’,
but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the respective
output level (TCMP1 and TCMP2 pins).
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide range of applications including fixed
frequency generation.
Note:
6.5
6
A software force compare will affect the corresponding output pin TCMP1 and/or
TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
Pulse length modulation (PLM)
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM
conversions, with a choice of two repetition rates (see Section 8).
6.5.1
Pulse length modulation registers A and B (PLMA/PLMB)
Address
Pulse length modulation A (PLMA)
MC68HC05X16
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000A
State
on reset
0000 0000
Address
Pulse length modulation B (PLMB)
bit 7
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$000B
bit 1
bit 0
State
on reset
0000 0000
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6.6
Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that particular
count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or
external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the
counter resumes from its stopped value.
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6
Another feature of the programmable timer is that if at least one valid input capture edge occurs at
one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is
armed. This action does not wake the MCU or set any timer flags, but when the MCU does wake-up
there will be an active input capture flag (and data) from that first valid edge which occurred during
STOP mode.
If STOP mode is exited by an external reset then no such input capture flag or data action takes
place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
6.7
Timer during WAIT mode
The timer system is not affected by WAIT mode and continues normal operation. Any valid timer
interrupt will wake-up the system.
6.8
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
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Internal
processor clock
 T00
 T01
Internal 
timer clocks
T10

 T11
16-bit
counter
$FFFC
$FFFD
$FFFE
$FFFF
External reset
or end of POR
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
6
Figure 6-2 Timer state timing diagram for reset
Internal
processor clock
 T00
 T01
Internal 
timer clocks
T10

 T11
16-bit
counter
$F124
$F125
$F126
}
}
Input
edge
$F123
}
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Internal
reset
}
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Internal
capture latch
Input capture
register
$????
$F124
Input capture
flag
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
Figure 6-3 Timer state timing diagram for input capture
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Internal
processor clock
 T00
 T01
Internal 
timer clocks
T10

 T11
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16-bit
counter
$F456
$F457
$F458
$F459
(Note 1)
Output compare
register
CPU writes $F457
(Note 1)
Compare register
latch
6
(Note 2)
Output compare
flag and TCMP1,2
Note:
$F457
The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01. Thus a four cycle difference may exist between the write to the compare register and the actual compare.
Figure 6-4 Timer state timing diagram for output compare
Internal
processor clock
 T00
 T01
Internal 
timer clocks
T10

 T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared by
a read of the timer status register during the internal processor clock high time, followed by a read of the
counter low register.
Figure 6-5 Timer state timing diagram for timer overflow
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SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard
non-return-to-zero (NRZ) format and a variety of baud rates. The SCI transmitter and receiver are
functionally independent and have their own baud rate generator; however they share a common
baud rate prescaler and data format.
The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data
bits, and one stop bit.
The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for
synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock
on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).
Phase and polarity of these clocks are software programmable.
7
Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and
transmit data out (TDO).
‘Baud’ and ‘bit rate’ are used synonymously in the following description.
7.1
SCI two-wire system features
•
Standard NRZ (mark/space) format
•
Advanced error detection method with noise detection for noise duration of up to 1/16th bit time
•
Full-duplex operation (simultaneous transmit and receive)
•
32 software selectable baud rates
•
Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive
baud rates
•
Software selectable word length (eight or nine bits)
•
Separate transmitter and receiver enable bits
•
Capable of being interrupt driven
•
Transmitter clocks available without altering the regular transmitter or receiver functions
•
Four separate enable bits for interrupt control
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Internal bus
SCI interrupt
+
$0011
(See note)
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Transmit
data register
$0011
(See note)
&
&
&
&
$000F
SCCR2
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
Transmit
data shift
register
TDO
pin
+
7
6
5
4
3
2
1
0
Receive
data register
Receive
data shift
register
RDI
pin
SCSR
$0010
7
7
TRDE
TC
6
TE
SBK
5
RDRF
3
OR
4
IDLE
2
NF
1
FE
Wake up
unit
7
Flag
control
Transmitter
control
Receiver
control
Transmitter
clock
Receiver
clock
Clock extraction
SCLK
pin
phase and
polarity control
7
R8
Note:
6
T8
5
4
M
3
WAKE
2
CPOL
1
CPHA
0
LBCL
SCCR1
$000E
The serial communications data register (SCI SCDR) is controlled by the internal
R/W signal. It is the transmit data register when written to and the receive data
register when read.
Figure 7-1 Serial communications interface block diagram
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7.2
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SCI receiver features
•
Receiver wake-up function (idle line or address bit)
•
Idle line detection
•
Framing error detection
•
Noise detection
•
Overrun detection
•
Receiver data register full flag
7.3
SCI transmitter features
•
Transmit data register empty flag
•
Transmit complete flag
•
Send break
7.4
7
Functional description
A block diagram of the SCI is shown in Figure 7-1. Option bits in serial control register1 (SCCR1)
select the ‘wake-up’ method (WAKE bit) and data word length (M bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 7.11.5).
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock (see
Figure 7-2). All data is transmitted least significant bit first. Upon completion of data transmission,
the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or
break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has
been sent, the TC bit will also be set. This will also generate an interrupt if the transmission
complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the
character being transmitted will be completed before the transmitter gives up control of the
TDO pin.
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When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
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An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate
and for SCT0–SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see Figure 7-2). This register
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
Internal processor clock
7
SCP0 – SCP1
prescaler
rate control
(÷ NP)
SCR0 – SCR2
receiver
rate control
(÷ NR)
SCT0 – SCT2
transmitter
rate control
(÷ NT)
÷16
SCP1
SPC0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
7
6
5
4
3
2
1
0
$000D
Baud rate register
Transmitter clock
Note:
Receiver clock
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of
the receiver (sampling). This means that by loading the same value for both the transmitter and receiver
baud rate selector, the same baud rates can be obtained.
Figure 7-2 SCI rate generator division
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7.5
Data format
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Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The
non-return-to-zero (NRZ) data format shown in Figure 7-3 is used and must meet the following
criteria:
–
The idle line is brought to a logic one state prior to transmission/reception of
a character.
–
A start bit (logic zero) is used to indicate the start of a frame.
–
The data is transmitted and received least significant bit first.
–
A stop bit (logic one) is used to indicate the end of a frame. A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.
–
A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit).
Control bit M selects
8 or 9 bit data
7



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Idle line
0
1
2
3
4
5
6
7
0
8
Start
Stop Start
Figure 7-3 Data format
7.6
Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for
systems having more than one receiver. With this function a transmitting device directs messages
to an individual receiver or group of receivers by passing addressing information as the initial
byte(s) of each message. The wake-up function allows receivers not addressed to remain in a
dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves system
performance.
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and is cleared automatically in hardware by one of the two
methods described below.
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7.6.1
Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle
is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
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7.6.2
Address mark wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
7.7
Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate. This time is referred
to as the RT rate in Figure 7-4 and as the receiver clock in Figure 7-2.
The receiver clock generator is controlled by the baud rate register, as shown in Figure 7-1 and
Figure 7-2; however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three
times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),
as shown in Figure 7-5. The value of the bit is determined by voting logic which takes the value of
the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree.
7.8
Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in Figure 7-4). If at least two of these three verification samples
detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A
noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could
be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
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16X internal sampling clock
1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT
RT clock edges for all three examples
Idle
Start
RDI
1
1
1
1
1
1
1
1
1
1
1
Start
qualifiers
0
0
Start
0
0
Start edge
verification samples
Noise
RDI
1
1
1
1
1
1
1
1
1
1
1
Noise
0
0
1
0
0
0
0
Start
RDI
1
1
1
1
1
0
1
1
1
1
1
0
7
Figure 7-4 SCI examples of start bit sampling technique
Previous bit
Present bit
RDI
Samples
Next bit
<
<
<
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16RT 1RT
8RT 9RT 10RT
16RT 1RT
Figure 7-5 SCI sampling technique used on all bits
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 7-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 7-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
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If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see Figure 7-7).
Data
Expected stop
Artificial edge
Data
RDI
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Start bit
Data samples
a) Case 1: receive line low during artificial edge
Data
Expected stop
Start edge
Data
RDI
Start bit
Data samples
7
b) Case 2: receive line high during expected start edge
Figure 7-6 Artificial start following a framing error
Expected stop
Detected as valid start edge
Break
Start bit
RDI













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Data samples
Start
qualifiers
Start edge
verification
samples
Figure 7-7 SCI start bit following a break
7.9
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 7.5 and shown in Figure 7-3. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
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7.10
SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The
SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit
and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be
activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the
user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the
phase of the external clock (see Figure 7-8, Figure 7-9 and Figure 7-10).
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During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers, without
losing any functions of the SCI transmitter which can still talk to other SCI receivers. These options
do not affect the SCI receiver which is independent of the transmitter.
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE = 0), the SCLK and TDO pins go to the high impedance state.
Note:
The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to
ensure that the clocks function correctly. These bits should not be changed while the
transmitter is enabled.
RDI
Data out
TDO
Data in
7
Asynchronous
(e.g. Modem)
SCLK
MC68HC05X16
Data in
Clock
Output port
Synchronous
(e.g. shift register,
display driver, etc.)
Enable
Figure 7-8 SCI example of synchronous and asynchronous transmission
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7.11
SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
7.11.1
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7
Serial communications data register (SCDR)
Address
SCI data (SCDR)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$0011
State
on reset
0000 0000
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written. Figure 7-1 shows this register as two separate registers, RDR and TDR. The RDR
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus. The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in Figure 7-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in Figure 7-1. All data is received with the least significant bit first.
7.11.2
Serial communications control register 1 (SCCR1)
SCI control 1 (SCCR1)
Address
bit 7
bit 6
$000E
R8
T8
bit 5
bit 4
bit 3
bit 1
bit 0
State
on reset
M
WAKE CPOL CPHA
LBCL
Undefined
bit 2
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
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R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial
receive shift register to the SCI receive data register.
T8 — Transmit data bit 8
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This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred
to the ninth bit position of the shift register.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see Table 7-1).
1 (set)
–
Start bit, 9 data bits, 1 stop bit.
0 (clear) –
Start bit, 8 data bits, 1 stop bit.
7
Table 7-1 Method of receiver wake-up
WAKE
M
0
x
1
0
1
1
Method of receiver wake-up
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
x = Don’t care
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See Table 7-1.
1 (set)
–
Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
(if M=0) or the 9th (if M=1) bit received on the Rx line is set.
0 (clear) –
Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)
or 12 (if M=1) consecutive ‘1’s on the Rx line.
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CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 7-9 and
Figure 7-10).
1 (set)
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7
–
Steady high value at SCLK pin outside transmission window.
0 (clear) –
Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin. This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 7-9 and
Figure 7-10).
1 (set)
–
0 (clear) –
SCLK clock line activated at beginning of data bit.
SCLK clock line activated in middle of data bit.
This bit should not be manipulated while the transmitter is enabled.
Idle or preceding
transmission
Stop
M = 0 (8 data bits)
Start
clock
(CPOL = 0, CPHA = 0)
*
clock
(CPOL = 0, CPHA = 1)
*
clock
(CPOL = 1, CPHA = 0)
*
clock
(CPOL = 1, CPHA = 1)
data
Idle or next
transmission
*
0
Start LSB
1
2
3
4
5
6
7
MSB Stop
* LBCL bit controls last data clock
Figure 7-9 SCI data clock timing diagram (M=0)
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Idle or preceding
transmission
Idle or next
Stop transmission
M = 1 (9 data bits)
Start
clock
(CPOL = 0, CPHA = 0)
*
clock
(CPOL = 0, CPHA = 1)
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*
clock
(CPOL = 1, CPHA = 0)
*
clock
(CPOL = 1, CPHA = 1)
*
0
data
1
2
3
4
Start LSB
5
6
7
8
MSB Stop
* LBCL bit controls last data clock
7
Figure 7-10 SCI data clock timing diagram (M=1)
LBCL – Last bit clock
This bit allows the user to select whether the clock associated with the last data bit transmitted
(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if
the LBCL bit is a logic one, and is not output if it is a logic zero.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit
(seeTable 7-2).
This bit should not be manipulated while the transmitter is enabled.
Table 7-2 SCI clock on SCLK pin
MC68HC05X16
Data format
M-bit
LBCL bit
8 bit
8 bit
9 bit
9 bit
0
0
1
1
0
1
0
1
Number of clocks on
SCLK pin
7
8
8
9
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7.11.3
Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
SCI control (SCCR2)
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7
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$000F
TIE
TCIE
RIE
ILIE
TE
RE
RWU
SBK
0000 0000
TIE — Transmit interrupt enable
1 (set)
–
TDRE interrupts enabled.
0 (clear) –
TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
1 (set)
–
TC interrupts enabled.
0 (clear) –
TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set)
–
RDRF and OR interrupts enabled.
0 (clear) –
RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set)
–
IDLE interrupts enabled.
0 (clear) –
IDLE interrupts disabled.
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble. After this latest transmission, and provided the TDRE bit is set (no new data to transmit),
the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This
function allows the user to neatly terminate a transmission sequence.
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After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed and the line will go
idle.
1 (set)
–
Transmitter enabled.
0 (clear) –
Transmitter disabled.
RE — Receiver enable
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1 (set)
–
Receiver enabled.
0 (clear) –
Receiver disabled.
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited.
RWU — Receiver wake-up
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1). When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
7
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit. The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros
and then reverts to idle sending data. If SBK remains set, the transmitter will continually send
whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the
transmitter sends at least one high bit to guarantee recognition of a valid start bit.
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7.11.4
Serial communications status register (SCSR)
SCI status (SCSR)
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7
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
$0010
TDRE
TC
RDRF
IDLE
OR
NF
FE
bit 0
State
on reset
1100 000u
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TDRE — Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
serial communications data register.
TC — Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data
in shift register, no preamble, no break). When TC is set the serial line will go idle (continuous
MARK). The TC bit is cleared by accessing the serial communications status register (with TC set)
followed by writing to the serial communications data register. It does not inhibit the transmitter
function in any way.
RDRF — Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as
appropriate during the same clock cycle. The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE — Idle line detected flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive ‘1’s). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed by a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
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OR — Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in
this case, but additional data received during an overrun condition (including the byte causing the
overrun) will be lost.
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The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
NF — Noise error flag
This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop bit. The NF bit
is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until
the RDRF flag is set. Each data bit is sampled three times as described in Section 7.7.
The NF bit represents the status of the byte in the serial communications data register. For the byte
being received (shifted in) there will be also a ‘working’ noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register. The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can
be used to generate the interrupt.
7
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE — Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive shift
register to the receive data register is inhibited by an overrun. The FE bit is set during the same
cycle as the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag
inhibits further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
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7.11.5
Baud rate register (BAUD)
The baud rate register provides the means to select two different or equivalent baud rates for the
transmitter and receiver.
SCI baud rate (BAUD)
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State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000D
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0 00uu uuuu
SCP1, SCP0 — Serial prescaler select bits
These read/write bits determine the prescale factor, NP, by which the internal processor clock is
divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This
common prescaled output is used as the input to a divider that is controlled by the SCR0–SCR2
bits for the SCI receiver, and by the SCT0–SCT2 bits for the transmitter.
Table 7-3 First prescaler stage
7
SCP1
SCP0
0
0
1
1
0
1
0
1
Prescaler
division ratio (NP)
1
3
4
13
SCT2, SCT1, SCT0 — SCI rate select bits (transmitter)
These three read/write bits select the baud rates for the transmitter. The prescaler output is divided
by the factors shown in Table 7-4.
Table 7-4 Second prescaler stage (transmitter)
SCT2
SCT1
SCT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Transmitter
division ratio (NT)
1
2
4
8
16
32
64
128
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SCR2, SCR1, SCR0 — SCI rate select bits (receiver)
These three read/write bits select the baud rates for the receiver. The prescaler output described
above is divided by the factors shown in Table 7-5.
Table 7-5 Second prescaler stage (receiver)
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SCR2
SCR1
SCR0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Receiver
division ratio (NR)
1
2
4
8
16
32
1
1
1
1
0
1
64
128
7
The following equations are used to calculate the receiver and transmitter baud rates:
f clk
baudTx = ----------------------------------16 • NP • NR
f clk
baudRx = ----------------------------------16 • NP • NR
where:
NP = prescaler divide ratio
NT = transmitter baud rate divide ratio
NR = receiver baud rate divide ratio
baudTx = transmitter baud rate
baudRx = receiver baud rate
fCLK = CPU clock frequency
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7.12
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Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected, depending
on the CPU clock frequency. A particular baud rate may be generated by manipulating the various
prescaler and division ratio bits. Table 7-6, Table 7-7 and Table 7-8 show the highest baud rates that
can be achieved for five typical crystal frequencies, for each of the CPU clock frequency options and
only using the prescaler bits. Table 7-9 shows how lower transmitter or receiver baud rates may be
obtained using a further division ratio provided by the SCI rate select bits. Note that the five
examples given in Table 7-9 are representative samples only.
Table 7-6 SCI baud rate selection with CPU clock frequency = fOSC/2
7
SCP1
SCP0
0
0
1
1
0
1
0
1
Clock
divided
4.194304
by
1
131072
3
43691
4
32768
13
10082
Crystal frequency – fosc (MHz)
4.00
2.4576
2.00
1.8432
125000
41667
31250
9600
76800
25600
19200
5907
62500
20833
15625
4800
57600
19200
14400
4430
Table 7-7 SCI baud rate selection with CPU clock frequency = fOSC/8
SCP1
SCP0
0
0
1
1
0
1
0
1
Clock
divided
by
1
3
4
13
Crystal frequency – fosc (MHz)
16.00
8.00
4.9152
4.194304
2.4576
125000
41667
31250
9600
62500
20833
15625
4800
38400
12800
9600
2954
32768
10082
8192
2521
19200
14400
4430
1477
Table 7-8 SCI baud rate selection with CPU clock frequency = fOSC/10
Note:
SCP1
SCP0
0
0
1
1
0
1
0
1
Clock
divided
by
1
3
4
13
Crystal frequency – fosc (MHz)
20.00
18.432
10.00
6.144
5.0
125000
41667
31250
9600
115200
38400
28800
8861
62500
20833
15625
4800
38400
12800
9600
2954
31250
10417
7813
2400
The clock in the ‘Clock divided by’ column refers to the internal processor clock.
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Table 7-9 SCI transmit baud rate output for a given prescaler output
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Bit 2
0
0
0
0
1
1
1
1
Note:
SCT/SCR bits
Bit 1
Bit 0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Divide
by
1
2
4
8
16
32
64
128
Representative highest prescaler baud rate output
131072
32768
38400
19200
9600
131072
32768
38400
19200
9600
65536
16384
19200
9600
4800
32768
8192
9600
4800
2400
16384
4096
4800
2400
1200
8192
2048
2400
1200
600
4096
1024
1200
600
300
2048
512
600
300
150
1024
256
300
150
75
The examples shown in Table 7-6, Table 7-7, Table 7-8 and Table 7-9 do not apply when
the part is operating in slow mode (see Section 2.2.3).
For the receiver, the internal clock frequency is 16 times higher than the selected baud
rate.
7
7.13
SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter
is shut down. This stops all SCI activity. Both the receiver and the transmitter are unable to operate.
If the STOP instruction is executed during a transmitter transfer, that transfer is halted. When STOP
mode is exited as a result of an external interrupt, that particular transmission resumes.
If the receiver is receiving data when the STOP instruction is executed, received data sampling is
stopped (baud generator stops) and the rest of the data is lost.
Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP
instruction is executed.
7.14
SCI during WAIT mode
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI
interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering
WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication
control register 2 at $000F. This action will result in a reduction of power consumption during WAIT
mode.
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PULSE LENGTH D/A CONVERTERS
The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two
8-bit D/A conversions, with a choice of two repetition rates. (See Figure 8-1.)
Data bus
8
PLMA
D/A
pin
8
PLMA
register
PLMB
register
‘A’ register
buffer
‘B’ register
buffer
‘A’
comparator
‘B’
comparator
8
R
Latch
S
R
Latch
S
Zero detector
Zero detector
8
SFA
bit
‘A’
multiplexer
16
PLMB
D/A
pin
8
‘B’
multiplexer
16
SFB
bit
Timer bus
From timer
Figure 8-1 PLM system block diagram
MC68HC05X16
PULSE LENGTH D/A CONVERTERS
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The D/A converter has two data registers associated with it, PLMA and PLMB.
Address
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8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Pulse length modulation A (PLMA)
$000A
0000 0000
Pulse length modulation B (PLMB)
$000B
0000 0000
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at ‘1’ for 255/256 of the cycle. When the
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion. This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in Figure 8-2.
256 T
$00
255 T
$01 T
128 T
$80
$FF
128 T
255 T
T
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
Figure 8-2 PLM output waveform examples
PULSE LENGTH D/A CONVERTERS
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Note:
Since the PLM system uses the timer counter, PLM results will be affected while resetting
the timer counter. Both D/A registers are reset to $00 during power-on or external reset.
WAIT mode does not affect the output waveform of the D/A converters.
8.1
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Miscellaneous register
Miscellaneous
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$000C
POR
INTP
INTN
INTE
SFA
SFB
SM
WDOG u001 000u
SFA — Slow or fast mode selection for PLMA
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.
1 (set)
–
0 (clear) –
Slow mode PLMA (4096 x timer clock period).
Fast mode PLMA (256 x timer clock period).
SFB — Slow or fast mode selection for PLMB
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.
1 (set)
–
0 (clear) –
Slow mode PLMB (4096 x timer clock period).
8
Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF
bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is
mandatory to set them to the desired values before writing to the PLM registers; not doing so could
temporarily give incorrect values at the PLM outputs.
SM — Slow mode
1 (set)
–
0 (clear) –
The system runs at a bus speed 16 times lower than normal
(fOSC/32). SLOW mode affects all sections of the device, including
SCI, A/D and timer.
The system runs at normal bus speed (fOSC/2).
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in Section 3.8.
MC68HC05X16
PULSE LENGTH D/A CONVERTERS
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8.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see Figure 8-3).
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8
fOSC
÷2
÷32
SM bit = 0
Bus
frequency (fOP)
÷4
Timer
clock
SM bit = 1
x4096
x256
SF bit = 1
PLM
clock
SF bit = 0
Figure 8-3 PLM clock selection
8.3
PLM during STOP mode
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
8.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
PULSE LENGTH D/A CONVERTERS
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ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation
converter and a sixteen channel multiplexer. Eight of the channels are connected to the
PD0/AN0 – PD7/AN7 pins of the MC68HC05X16 and the other eight channels are dedicated to
internal reference points for test functions. The channel input pins do not have any internal output
driver circuitry connected to them because such circuitry would load the analog input signals due
to output buffer leakage current. There is one 8-bit result data register (address $08) and one 8-bit
status/control register (address $09).
The A/D converter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the
reference voltage levels for all analog inputs. These pins are used in preference to the system
power supply lines because any voltage drops in the bonding wires of the heavily loaded supply
pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than
VRH converts to $FF (full scale) with no overflow indication and an input voltage equal to VRL
converts to $00.
The A/D converter can operate from either the bus clock or an internal RC type oscillator. The
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too
low to provide accurate results. When the A/D converter is not being used it can be disconnected,
by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 9.2.3).
9
For further information on A/D converter operation please refer to the M68HC11 Reference
Manual — M68HC11RM/AD.
9.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog converter capacitor
array, a comparator and a successive approximation register (SAR) (see Figure 9-1).
There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2
or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 9.2.3). AN0–AN7
are the only input points for A/D conversion operations; the others are reference points that can be
used for test purposes.
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The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
AN0
VRH
VRL
8-bit capacitive DAC
with sample and hold
AN1
9
AN2
AN3
AN4
AN5
AN6
Analog MUX
(Channel assignment)
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Successive approximation
register (SAR) and control
Result
A/D status/control register (ADSTAT)$09
CH0
CH1
CH2
CH3
0
ADON ADRC COCO
AN7
VRH
(VRH+VRL)/2
VRL
A/D result register (ADDATA) $08
Figure 9-1 A/D converter block diagram
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($08), and
the conversion complete flag, COCO, is set in the A/D status/control register ($09).
Warning: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared; thus the A/D is disabled.
ANALOG TO DIGITAL CONVERTER
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9.2
A/D registers
9.2.1
Port D data register (PORTD)
Port D data (PORTD)
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Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0003
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Undefined
Port D is an input-only port which routes the eight analog inputs to the A/D converter. When the
A/D converter is disabled, the pins are configured as standard input-only port pins, which can be
read via the port D data register.
Note:
9.2.2
When the A/D function is enabled, pins PD0–PD7 will act as analog inputs. Using a pin
or pins as A/D inputs does not affect the ability to read port D as static inputs; however,
reading port D during an A/D conversion sequence may inject noise on the analog
inputs and result in reduced accuracy of the A/D result.
Performing a digital read of port D with levels other than VDD or VSS on the pins will
result in greater power dissipation during the read cycle, and may give unpredictable
results on the corresponding port D pins.
A/D result data register (ADDATA)
Address
A/D data (ADDATA)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$0008
bit 1
bit 0
State
on reset
9
0000 0000
ADDATA is a read-only register which is used to store the results of A/D conversions. Each result
is loaded into the register from the SAR and the conversion complete flag, COCO, in the ADSTAT
register is set.
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9.2.3
A/D status/control register (ADSTAT)
A/D status/control (ADSTAT)
Address
bit 7
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0009
COCO ADRC ADON
0
CH3
CH2
CH1
CH0
0000 0000
bit 6
COCO — Conversion complete flag
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1 (set)
–
COCO is set each time a conversion is complete, allowing the new
result to be read from the A/D result data register ($08). The
converter then starts a new conversion.
0 (clear) –
COCO is cleared by reading the result data register or writing to the
status/control register.
Reset clears the COCO flag.
ADRC — A/D RC oscillator control
The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a
sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.
1 (set)
–
When the ADRC bit is set, the A/D RC oscillator is turned on and, if
ADON is set, the A/D runs from the RC oscillator clock. See Table 9-1.
0 (clear) –
When the ADRC bit is cleared, the A/D RC oscillator is turned-off
and, if ADON is set, the A/D runs from the CPU clock.
When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 12-3). During
this time A/D conversion results may be inaccurate.
Note:
If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.
Power-on or external reset clears the ADRC bit.
Table 9-1 A/D clock selection
ADRC
ADON
0
0
1
1
0
1
0
1
RC
A/D
Comments
oscillator converter
OFF
OFF
A/D switched off.
OFF
ON
A/D using CPU clock.
ON
OFF
Allows the RC oscillator to stabilize.
ON
ON
A/D using RC oscillator clock.
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ADON — A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 (set)
–
A/D converter is switched on.
0 (clear) –
A/D converter is switched off.
When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize
(see Table 12-3). During this time A/D conversion results may be inaccurate.
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Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.
CH3–CH0 — A/D channels 3, 2, 1 and 0
The CH3–CH0 bits allow the user to determine which channel of the A/D converter multiplexer is
selected. See Table 9-2 for channel selection.
Reset clears the CH0–CH3 bits.
Table 9-2 A/D channel assignment
CH3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
9.3
CH2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CH1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CH0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Channel selected
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
VRH pin (high)
(VRH + VRL) / 2
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
9
A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
MC68HC05X16
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9.4
A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
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9
9.5
Port D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 9-2. Sampling time is limited to 12 bus clock cycles. After sampling,
the analog value is stored on the capacitor and held until the end of conversion. During this hold
time, the analog input is disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Input protection device
Analog
input
pin
< 2pF
≥ 50kΩ
+ ~20V
- ~0.7V
400 nA
junction
leakage
≥ 10pF
DAC
capacitance
VRL
Note:
The analog switch is closed during the 12 cycle sample
time only.
Figure 9-2 Electrical model of an A/D input pin
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RESETS AND INTERRUPTS
10.1
Resets
The MC68HC05X32 can be reset in three ways: by the initial power-on reset function, by an active
low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of
these resets will cause the program to go to its starting address, specified by the contents of
memory locations $3FFE and $3FFF, and cause the interrupt mask bit in the condition code
register to be set.
tVDDR
VDD threshold (1-2V typical)
VDD
tOXOV
OSC1
tPORL
tCYC
Internal
processor clock
RESET
(Internal power-on reset)
10
(External hardware reset)
tRL(or tDOGL)
Internal
address bus
Internal
data bus
3DFE
3FFE 3FFF
New
PC
Reset sequence
Mask options
3DFE
3FFE 3FFF
New
PC
Reset sequence
New New Op
PCH PCL code
Mask options
Program
execution
begins
New New Op
PCH PCL code
Program
execution
begins
Figure 10-1 Reset timing diagram
MC68HC05X16
RESETS AND INTERRUPTS
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10.1.1
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10
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high. The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage. This may be accomplished by connecting an external RC
circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great
enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a tPORL delay start-up sequence. tPORL is
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2).
A software distinction between a power-on reset and an external reset can be made using the POR
bit in the miscellaneous register (see Section 10.1.2).
10.1.2
Miscellaneous register
Address bit 7
Miscellaneous
bit 6
bit 5
bit 0
State
on reset
bit 4
bit 3
bit 2
bit 1
$000C POR(1) INTP INTN INTE
SFA
SFB
SM WDOG(2) u001 000u
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled,
0=watchdog disabled.
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
Note:
–
A power-on reset has occurred.
0 (clear) –
No power-on reset has occurred.
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
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10.1.3
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RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger
is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will
resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR
or the COP watchdog, the RESET pin provides an active-low open drain output signal which may
be used to reset external hardware. Current limitation to protect the pull-down device is provided
in case an RC type external reset circuit is used.
Note:
If an external RC is connected to RESET, turning on the RESET pull-down transistor
may discharge the capacitor. The device will then remain in reset until the capacitor has
recharged, after turning off the pull-down device.
VDD
pin
MC68HC05X16
RESET
pin
Figure 10-2 RESET external RC pull-down
10.1.4
10
Computer operating properly (COP) watchdog reset
The watchdog counter system consists of a divide-by-7 counter, preceded by a fixed divide-by-4
and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 10-3. The divide-by-7
counter can be reset by software.
Note:
The input to the watchdog system is derived from the carry output of bit 7 of the free
running timer counter. Therefore, a reset of the timer may affect the period of the
watchdog timeout.
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Main CPU
clock
R
÷ 256
(Bit 7 of free
running counter)
Latch
WDOG bit
Reset
pin
Reset
÷ 7 watchdog
counter
Enable
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fosc/2
÷4
fosc/32 prescaler
10
Power-on
S
+
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Control logic
Schmitt
trigger
Input
protection
Figure 10-3 Watchdog system block diagram
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see Section 1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit in
the miscellaneous register at $000C (see Section 10.1.2). Once enabled, the watchdog system
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set)
–
0 (clear) –
Watchdog enabled and counter cleared.
The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
The divide-by-7 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time tDOG since the last clear or since the enable of the watchdog
counter system. The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than tDOG.
The reset generated by the watchdog system is apparent at the RESET pin (see Figure 10-3). The
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of tDOGL, the RESET pin is released.
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10.1.4.1
COP watchdog during STOP mode
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is
executed while the watchdog system is enabled, then a watchdog reset will occur as if there were
a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will
not be affected, thus there will be no tPORL cycles start-up delay. On start-up, the watchdog will be
configured according to the user specified mask option.
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10.1.4.2
COP watchdog during WAIT mode
The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to
be one of the options below:
Watchdog enabled — the watchdog counter will continue to operate during WAIT mode and a reset
will occur after time tDOG.
Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and
disabled. On exiting WAIT mode the counter resumes normal operation.
10.1.5
Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the
execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.
Table 10-1 shows the resulting action of any type of system reset, but not necessarily in the order
in which they occur.
Note:
Reset action on individual MCAN registers is described in Section 5 and is also
summarised in Table 3-2.
MC68HC05X16
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Table 10-1 Effect of RESET, POR, STOP and WAIT
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10
Function/effect
Timer prescaler cleared
Timer counter set to $FFFC
All timer enable bits cleared (disable)
Data direction registers cleared (inputs)
Stack pointer set to $00FF
Internal address bus forced to restart
Vector $3FFE, $3FFF
Interrupt mask bit (I-bit CCR) set
Interrupt mask bit (I-bit CCR) cleared
Interrupt enable bit (INTE) set
POR bit in miscellaneous register set
STOP latch reset
IRQ latch reset
WAIT latch reset
SCI disabled
SCI status bits cleared (except TDRE
and TC)
SCI interrupt enable bits cleared
SCI status bits TDRE and TC set
Oscillator disabled for 4064 cycles
Timer clock cleared
SCI clock cleared
A/D disabled
SM bit in the miscellaneous register
cleared
Watchdog counter reset
WDOG bit in the miscellaneous register
reset
EEPROM control bits set or cleared (as
per Section 3.5.1)
RESET
x
x
x
x
x
x
x
x
–
x
–
x
x
x
x
POR
x
x
x
x
x
x
x
x
–
x
x
x
x
x
x
WAIT
–
–
–
–
–
–
–
–
x
–
–
–
–
–
–
STOP
–
–
–
–
–
–
–
–
x
–
–
–
–
–
–
x
x
–
–
x
x
–
–
–
x
x
x
x
x
x
x
–
–
–
–
–
–
–
–
x
x
x
x
x
x
–
x
x
x
x
x
x
x
–
x
x
x
–
x
x = Described action takes place
– = Described action does not take
place
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10.2
Interrupts
The MCU can be interrupted by five different sources: three maskable hardware interrupts, one
non maskable software interrupt and one maskable MCAN interrupt:
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•
External signal on the IRQ pin, WOI on port B pins or NWOI pin
•
Serial communications interface (SCI)
•
Programmable timer
•
Software interrupt instruction (SWI)
•
MCAN interrupt (CIRQ)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts. The RTI instruction (return from interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on
the stack.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete. The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on and external reset clear all interrupt enable bits to prevent interrupts during
the reset sequence, but set the INTE bit (see Section 3.8).
10
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Reset
Is I-bit set?
NO
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10
IRQ or WOI
external interrupt?
YES
Clear IRQ
request latch
NO
Timer
internal interrupt?
Stack
PC, X, A, CC
YES
NO
SCI
internal interrupt?
YES
Set I-bit
NO
CIRQ
MCAN interrupt?
NO
Fetch next
instruction
Execute
instruction
YES
Load PC from:
IRQ:
$3FFA-$3FFB
Timer IC: $3FF8-$3FF9
Timer OC: $3FF6-$3FF7
Timer OVF:$3FF4-$3FF5
SCI:
$3FF2-$3FF3
MCAN:
$3FF0-$3FF1
Complete interrupt
routine and execute
RTI
Figure 10-4 Interrupt flow chart
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10.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority level, which means that if more than one
interrupt is pending at the same time, the processor will service the one with the highest priority
first. For example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
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Table 10-2 shows the relative priority of all the possible interrupt sources. Figure 10-4 shows the
interrupt processing flow.
Table 10-2 Interrupt priorities
10.2.2
Source
Reset
Register
—
Flags
—
Software interrupt (SWI)
External interrupt (IRQ) or WOI
Timer input captures
Timer output compares
Timer overflow
—
—
TSR
TSR
TSR
Serial communications
interface (SCI)
SCSR
MCAN
CINT
—
—
ICF1, ICF2
OCF1, OCF2
TOF
TDRE, TC,
OR, RDRF,
IDLE
WIF,OIF,EIF,
TIF, RIF
Vector address Priority
$3FFE, $3FFF highest
$3FFC, $3FFD
$3FFA, $3FFB
$3FF8, $3FF9
$3FF6, $3FF7
$3FF4, $3FF5
$3FF2, $3FF3
$3FF0, $3FF1
lowest
Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
generated after the SWI was fetched. The SWI interrupt service routine address is specified by the
contents of memory locations $3FFC and $3FFD.
10.2.3
10
Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
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10.2.3.1
Miscellaneous register
Address bit 7
Miscellaneous
Note:
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10
bit 6
bit 5
bit 0
State
on reset
bit 4
bit 3
bit 2
bit 1
$000C POR INTP INTN INTE
SFA
SFB
SM WDOG u001 000u
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ and WOI pins are sensitive to as shown
in Table 10-3. Both bits can be written to only while the I-bit is set, and are cleared by power-on or
external reset. Therefore the device is initialised with negative edge and low level sensitivity.
Table 10-3 IRQ and WOI sensitivity
INTP
INTN
0
0
0
1
1
0
1
1
IRQ sensitivity
Negative edge and low level
sensitive
Negative edge only
Positive edge only
Positive and negative edge
sensitive
WOI interrupt sensitivity
Positive edge and high level
sensitive
Positive edge only
Negative edge only
Positive and negative edge
sensitive
Interrupt sensitivity options selected by INTP and INTN of the miscellaneous register apply to
external interrupt signal, EI. EI is an OR function of all enabled WOI pins (port B and NWOI) and
of the inverted value of the IRQ pin. When one WOI pin is high, it masks any subsequent edge or
level on any other EI pin (IRQ, port B or NWOI).
INTE — External interrupt enable
–
External interrupt (IRQ) and wired-OR interrupt (WOI) enabled.
0 (clear) –
External interrupt (IRQ) and wired-OR interrupt (WOI) disabled.
1 (set)
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 10-3 describes the various triggering options available for the IRQ and WOI pins, however it
is important to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is
possible to change the external interrupt options only while the I-bit is set. Any attempt to change
the external interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is
pending, it will automatically be cleared when selecting a different interrupt option.
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If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
interrupt which is not latched); therefore, only one external interrupt pulse can be
latched during tILIL and serviced as soon as the I-bit is cleared.
10.2.3.2
External interrupts
IRQ interrupt
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $3FFA and $3FFB.
Wired-OR interrupt (WOI)
An external WOI capability is provided on all port B I/O pins when they are programmed as inputs,
and on the NWOI pin. A WOI is activated only if WOIE in the EEPROM control register is set and
if wired-OR interrupts have been chosen as an option on the device (see Section 1.2). If wired-OR
interrupts are enabled on a given input pin (NWOI pin or port B pins; refer to Section 2.3.19 and
Section 4.2), an external interrupt is requested when this pin is pulled high. The request is serviced
by the interrupt routine whose start address is contained in memory locations $3FFA and $3FFB.
External and power-on reset clear the WOIE bit. A WOI interrupt will cause the MCU to exit STOP
mode.
The interrupt enable bit (INTE) in the miscellaneous register enables both wired-OR interrupts and
the IRQ interrupt. IRQ and WOI are internally OR-ed before interrupt sensitivity selection (see
Section 10.2.3.1).
10.2.3.3
10
MCAN interrupt (CIRQ)
Several sources can trigger a CIRQ. The MCAN interrupt register at $0023 is used to identify the
source. Each CIRQ source can be individually enabled (except the wake-up interrupt, which is
always enabled) by different bits of the MCAN control register at $0020.
The CIRQ sources are (also see Section 5.3.4):
Receive IRQ: this signals successful reception of a complete message.
Transmit IRQ: this signals successful transmission of a complete message.
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Error IRQ:
this is set when either the error status or bus status bits in the MCAN status register
change state (see Section 5.3.3).
Data overrun: an incoming message on the bus cannot be received because both receive buffers
are tied up.
Wake-up IRQ: this signals activity on the bus while the MCAN is in SLEEP mode. This is the only
nonmaskable CIRQ.
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10
CIRQ interrupts are serviced by the routine located at the address specified by the contents of
$3FF0 and $3FF1.
10.2.3.4
Timer interrupts
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five
most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine defined by $3FF8-$3FF9, OCF1 and OCF2 will vector to the service routine
defined by $3FF6–$3FF7 and TOF will vector to the service routine defined by $3FF4–$3FF5 as
shown in Figure 6-1.
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
$0012. See Section 6.2.1 and Section 6.2.2 for further information.
10.2.3.5
Serial communications interface (SCI) interrupts
There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled. These five interrupt flags are found in the five most significant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
(SCCR2) at address $000F. See Section 7.11.3 and Section 7.11.4.
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $3FF2 and $3FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt flags and the status bits located in the serial communications status
register SCSR (address $0010).
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the flag is set followed by a read or write of an associated
register. Refer to Section 7 for a description of the SCI system and its interrupts.
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10.2.4
Hardware controlled interrupt sequence
The following three functions: reset, STOP and WAIT, are not in the strictest sense interrupts. However,
they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2-4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $3FFE (MSB) and $3FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
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STOP:
The STOP instruction puts the processor to ‘sleep’ and, if the MCAN module is already
in SLEEP mode, it causes the oscillator to be turned off until an external, WOI or CIRQ
interrupt occurs or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external or WOI
interrupt, a timer interrupt or an SCI interrupt. There are no special WAIT vectors for
these individual interrupts.
10
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CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05X16.
11.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 11-1. The interrupt
stacking order is shown in Figure 11-2.
7
0
7
0
Accumulator
Index register
15
7
0
0 0
15
7
0
0 0 0 0 0 0 0 0 1 1
7
0
1 1 1 H I NZ C
Program counter
Stack pointer
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
11
Figure 11-1 Programming model
11.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
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Unstack
Stack
0
Condition code register
Accumulator
Index register
Program counter high
Program counter low
Interrupt
Increasing
memory
address
Return
7
Decreasing
memory
address
Figure 11-2 Stacking order
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11
11.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
11.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
Although the M68HC05 CPU core can address 64K bytes of memory, the actual address range of
the MC68HC05X32 is limited to 16K bytes. The two most significant bits of the program counter
are therefore not used and are permanently set to zero.
11.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011. These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
11.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
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Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
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Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation. This bit is also affected during bit test and branch instructions
and during shifts and rotates.
11.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
–
Register/memory
–
Read/modify/write
–
Branch
–
Bit manipulation
–
Control
11
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the index
register and the low-order product is stored in the accumulator. A detailed definition of the MUL
instruction is shown in Table 11-1.
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11.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register. The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand.
Refer to Table 11-2 for a complete list of register/memory instructions.
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11.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 11-3.
11.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations. The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 11-4.
11.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register. The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 11-5 for a complete list of read/modify/write instructions.
11.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 11-6 for a complete list of control instructions.
11.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 11-7), and an opcode map for the instruction set of the
M68HC05 MCU family (see Table 11-8).
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Table 11-1 MUL instruction
Operation
X:A ¨ X*A
Multiplies the eight bits in the index register by the eight
Description bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
Condition
N : Not affected
codes
Z : Not affected
C : Cleared
Source
MUL
Addressing mode
Cycles
Bytes
Opcode
Form
Inherent
11
1
$42
Table 11-2 Register/memory instructions
Addressing modes
# Cycles
# Bytes
Opcode
Indexed
(16-bit
offset)
# Cycles
# Bytes
Opcode
Indexed
(8-bit
offset)
# Cycles
Opcode
# Cycles
# Bytes
Opcode
# Bytes
Indexed
(no
offset)
Extended
# Cycles
# Bytes
Direct
Opcode
# Cycles
Opcode
Function
# Bytes
Immediate
Mnemonic
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Load A from memory
LDA
A6
2
2
B6
2
3
C6
3
4
F6
1
3
E6
2
4
D6
3
5
Load X from memory
LDX
AE
2
2
BE
2
3
CE
3
4
FE
1
3
EE
2
4
DE
3
5
Store A in memory
STA
B7
2
4
C7
3
5
F7
1
4
E7
2
5
D7
3
6
Store X in memory
STX
BF
2
4
CF
3
5
FF
1
4
EF
2
5
DF
3
6
Add memory to A
ADD
AB
2
2
BB
2
3
CB
3
4
FB
1
3
EB
2
4
DB
3
5
Add memory and carry to A
ADC
A9
2
2
B9
2
3
C9
3
4
F9
1
3
E9
2
4
D9
3
5
Subtract memory
SUB
A0
2
2
B0
2
3
C0
3
4
F0
1
3
E0
2
4
D0
3
5
Subtract memory from A
with borrow
SBC
A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND memory with A
AND
A4
2
2
B4
2
3
C4
3
4
F4
1
3
E4
2
4
D4
3
5
OR memory with A
ORA
AA
2
2
BA
2
3
CA
3
4
FA
1
3
EA
2
4
DA
3
5
Exclusive OR memory with A
EOR
A8
2
2
B8
2
3
C8
3
4
F8
1
3
E8
2
4
D8
3
5
Arithmetic compare A
with memory
CMP
A1
2
2
B1
2
3
C1
3
4
F1
1
3
E1
2
4
D1
3
5
Arithmetic compare X
with memory
B3
2
3
C3
3
4
F3
1
3
E3
2
4
D3
3
5
CPX
A3
2
2
Bit test memory with A
(logical compare)
BIT
A5
2
2
B5
2
3
C5
3
4
F5
1
3
E5
2
4
D5
3
5
Jump unconditional
JMP
BC
2
2
CC
3
3
FC
1
2
EC
2
3
DC
3
4
Jump to subroutine
JSR
BD
2
5
CD
3
6
FD
1
5
ED
2
6
DD
3
7
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Table 11-3 Branch instructions
Function
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11
Branch always
Branch never
Branch if higher
Branch if lower or same
Branch if carry clear
(Branch if higher or same)
Branch if carry set
(Branch if lower)
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit is clear
Branch if interrupt mask bit is set
Branch if interrupt line is low
Branch if interrupt line is high
Branch to subroutine
Mnemonic
BRA
BRN
BHI
BLS
BCC
(BHS)
BCS
(BLO)
BNE
BEQ
BHCC
BHCS
BPL
BMI
BMC
BMS
BIL
BIH
BSR
Relative addressing mode
Opcode # Bytes # Cycles
20
2
3
21
2
3
22
2
3
23
2
3
24
2
3
24
2
3
25
2
3
25
2
3
26
2
3
27
2
3
28
2
3
29
2
3
2A
2
3
2B
2
3
2C
2
3
2D
2
3
2E
2
3
2F
2
3
AD
2
6
Table 11-4 Bit manipulation instructions
Function
Branch if bit n is set
Branch if bit n is clear
Set bit n
Clear bit n
Mnemonic
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
Addressing modes
Bit set/clear
Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
2•n
3
5
01+2•n
3
5
10+2•n
2
5
11+2•n
2
5
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Table 11-5 Read/modify/write instructions
Addressing modes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Opcode
# Bytes
# Cycles
Logical shift left
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
Set bit n
Clear bit n
# Bytes
INC
DEC
CLR
COM
NEG
ROL
ROR
Opcode
Increment
Decrement
Clear
Complement
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Indexed
(8-bit
offset)
# Cycles
Mnemonic
Indexed
(no
offset)
Direct
# Bytes
Function
Inherent
(X)
Opcode
Inherent
(A)
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4C
4A
4F
43
40
49
46
1
1
1
1
1
1
1
3
3
3
3
3
3
3
5C
5A
5F
53
50
59
56
1
1
1
1
1
1
1
3
3
3
3
3
3
3
3C
3A
3F
33
30
39
36
2
2
2
2
2
2
2
5
5
5
5
5
5
5
7C
7A
7F
73
70
79
76
1
1
1
1
1
1
1
5
5
5
5
5
5
5
6C
6A
6F
63
60
69
66
2
2
2
2
2
2
2
6
6
6
6
6
6
6
1
1
1
1
1
2
2
3 58
3 54
3 57
3 5D
11
5
5
1
1
1
1
3
3
3
3
38
34
37
3D
2
2
2
2
5
5
5
4
78
74
77
7D
1
1
1
1
5
5
5
4
68
64
67
6D
2
2
2
2
6
6
6
5
LSL
48
LSR
44
ASR
47
TST
4D
MUL
42
BSET n (n=0–7) 10+2•n
BCLR n (n=0–7) 11+2•n
Table 11-6 Control instructions
MC68HC05X16
Function
Transfer A to X
Transfer X to A
Set carry bit
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Mnemonic
TAX
TXA
SEC
CLC
SEI
CLI
SWI
RTS
Return from interrupt
Reset stack pointer
No-operation
Stop
Wait
RTI
RSP
NOP
STOP
WAIT
Inherent addressing mode
Opcode # Bytes # Cycles
97
1
2
9F
1
2
99
1
2
98
1
2
9B
1
2
9A
1
2
83
1
10
81
1
6
80
9C
9D
8E
8F
1
1
1
1
1
11
9
2
2
2
2
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Table 11-7 Instruction set
Mnemonic
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11
INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
CLR
H
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMP
•
Condition codes
I
N Z C
•
◊ ◊ ◊
•
◊ ◊ ◊
•
◊ ◊ •
•
◊ ◊ ◊
•
◊ ◊ ◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊ ◊ •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
•
•
•
◊
•
•
•
•
•
•
•
•
•
•
•
0
0
•
•
•
•
0 1
•
•
◊
◊
◊
Condition code symbols
Address mode abbreviations
BS
C
H
Bit set/clear
BTB Bit test & branch
Half carry (from bit 3)
◊
IMM Immediate
IX
Indexed (no offset)
Tested and set if true,
cleared otherwise
I
Interrupt mask
•
Not affected
N
Negate (sign bit)
?
Load CCR from stack
DIR Direct
IX1
Indexed, 1 byte offset
Z
Zero
0
Cleared
EXT Extended
IX2
Indexed, 2 byte offset
C
Carry/borrow
1
Set
Not implemented
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Table 11-7 Instruction set (Continued)
Mnemonic
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INH
IMM
DIR
Addressing modes
EXT REL IX
IX1
IX2
BSC BTB
COM
CPX
DEC
EOR
INC
JMP
JSR
LDA
LDX
LSL
LSR
H
•
•
•
•
•
•
•
•
•
•
•
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
RTS
SBC
SEC
SEI
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
0
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
Condition codes
I
N Z C
•
◊ ◊ 1
•
◊ ◊ ◊
•
◊ ◊ •
•
◊ ◊ •
•
◊ ◊ •
•
•
•
•
•
•
•
•
•
◊ ◊ •
•
◊ ◊ •
•
◊ ◊ ◊
•
0 ◊ ◊
•
•
•
•
•
•
•
?
•
•
•
1
•
0
•
•
1
•
•
•
0
•
◊
•
◊
◊
◊
•
?
•
◊
•
•
◊
•
◊
◊
•
•
◊
•
•
•
◊
•
◊
◊
◊
•
?
•
◊
•
•
◊
•
◊
◊
•
•
◊
•
•
0
◊
•
•
◊
◊
•
?
•
◊
1
•
•
•
•
◊
•
•
•
•
•
11
Condition code symbols
Address mode abbreviations
BS
C
H
Bit set/clear
Half carry (from bit 3)
◊
IMM Immediate
BTB Bit test & branch
IX
Indexed (no offset)
Tested and set if true,
cleared otherwise
I
Interrupt mask
•
Not affected
N
Negate (sign bit)
?
Load CCR from stack
DIR Direct
IX1
Indexed, 1 byte offset
Z
Zero
0
Cleared
EXT Extended
IX2
Indexed, 2 byte offset
C
Carry/borrow
1
Set
Not implemented
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BTB 2
5
3
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
5
BTB 2
3
3
3
3
3
3
3
3
3
3
BRCLR7
BRSET7
BRCLR6
BRSET6
BRCLR5
BRSET5
BRCLR4
BRSET4
BRCLR3
BRSET3
3
BRCLR2
BTB 2
5
BTB 2
5
BRSET2
BRCLR1
3
3
BTB 2
5
BRSET1
3
BRCLR0
BTB 2
5
BRSET0
3
5
BSC 2
BCLR7
BSC 2
5
BSC 2
5
BSET7
BCLR6
BSC 2
5
BSC 2
5
BSET6
BCLR5
BSC 2
5
BSC 2
5
BSET5
BCLR4
BSC 2
5
BSC 2
5
BSET4
BCLR3
BSC 2
5
BSC 2
5
BSET3
BCLR2
BSC 2
5
BSC 2
5
BSET2
BCLR1
BSC 2
5
BSC 2
5
BSET1
BCLR0
BSC 2
5
BSET0
5
BIH
BIL
BMS
BMC
BMI
BPL
REL 2
REL
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
BHCS
REL 2
3
REL 2
3
REL 2
3
REL
3
REL 2
3
REL 2
3
REL
3
REL
3
REL 2
3
BHCC
BEQ
BNE
BCS
BCC
BLS
BHI
BRN
BRA
3
BSC
BTB
DIR
EXT
INH
IMM
Bit set/clear
Bit test and branch
Direct
Extended
Inherent
Immediate
IX
IX1
IX2
REL
A
X
Abbreviations for address modes and registers
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
Low
High
Branch
REL
2
0010
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
DIR
3
0011
CLRA
TSTA
INCA
INH 1
3
INH 1
INH 1
3
3
INH 1
INH 1
3
INH 1
3
INH 1
3
DECA
ROLA
LSLA
ASRA
INH 1
3
3
INH 1
INH 1
3
RORA
LSRA
11
INH
3
COMA
MUL
INH 1
NEGA
3
ROLX
CLRX
TSTX
INCX
INH 2
3
INH 2
INH 2
3
3
INH 2
INH 2
3
DECX
INH 2
3
INH 2
3
INH 2
3
3
INH 2
ASRX
LSLX
3
INH 2
3
RORX
LSRX
COMX
INH 2
NEGX
3
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
Read/modify/write
INH
IX1
5
6
0101
0110
Indexed (no offset)
Indexed, 1 byte (8-bit) offset
Indexed, 2 byte (16-bit) offset
Relative
Accumulator
Index register
DIR 1
5
DIR 1
DIR 1
4
5
DIR 1
DIR 1
5
DIR 1
5
DIR 1
5
DIR 1
5
5
DIR 1
DIR 1
5
5
1
DIR 1
5
INH
4
0100
11
Bit manipulation
BTB
BSC
0
1
0000
0001
IX1 1
6
IX1 1
IX1 1
5
6
IX1 1
IX1 1
6
IX1 1
6
IX1 1
6
IX1 1
6
6
IX1 1
IX1 1
6
6
IX1 1
6
CLR
TST
INC
DEC
ROL
LSL
ASR
ROR
LSR
COM
NEG
IX
7
0111
1
WAIT
STOP
SWI
RTS
RTI
1
1
1
1
1
1
1
INH 1
INH
2
2
INH
10
INH
INH
6
9
TXA
NOP
RSP
SEI
CLI
SEC
CLC
TAX
INH
9
1001
Control
Not implemented
IX 1
5
IX
IX
4
5
IX
IX
5
IX
5
IX
5
IX
5
5
IX
IX 1
5
5
1
IX 1
5
INH
8
1000
INH
2
2
INH 2
INH
2
INH 2
2
INH 2
2
INH 2
2
INH 2
2
INH
2
2
2
2
2
2
2
2
2
LDX
BSR
ADD
ORA
ADC
EOR
LDA
BIT
AND
CPX
SBC
CMP
SUB
IMM
A
1010
2
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
3
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Bytes
1
EXT 3
EXT 3
5
EXT 3
4
EXT 3
6
EXT 3
3
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
5
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
EXT 3
4
SUB
F
1111
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
4
IX
3
IX2 2
IX2 2
6
IX2 2
5
IX2 2
7
IX2 2
4
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
6
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
IX2 2
5
5
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
IX1
E
1110
Address mode
0
0000
STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
Register/memory
EXT
IX2
C
D
1100
1101
Cycles
DIR 3
DIR 3
4
DIR 3
3
DIR 3
5
DIR 3
2
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
4
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
DIR 3
3
Mnemonic
Legend
2
IMM 2
REL 2
2
6
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
2
IMM 2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
IMM 2
2
2
DIR
B
1011
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STX
LDX
JSR
JMP
ADD
ORA
ADC
EOR
STA
LDA
BIT
AND
CPX
SBC
CMP
SUB
IX
IX
4
IX
3
IX
5
IX
2
IX
3
IX
3
IX
3
IX
3
IX
4
IX
3
IX
3
IX
3
IX
3
IX
3
IX
3
3
Low
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
High
Opcode in binary
Opcode in hexadecimal
IX1 1
IX1 1
5
IX1 1
4
IX1 1
6
IX1 1
3
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
5
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
IX1 1
4
4
IX
F
1111
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Table 11-8 M68HC05 opcode map
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11.3
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Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term ‘effective address’ (EA) is used in describing the various addressing modes. The effective
address is defined as the address from which the argument for an instruction is fetched or stored.
The ten addressing modes of the processor are described below. Parentheses are used to indicate
‘contents of’ the location or register referred to. For example, (PC) indicates the contents of the
location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon
indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the
M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to
the M68HC05 Applications Guide.
11.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register or accumulator, as well as
the control instruction, with no other arguments are included in this mode. These instructions are
one byte long.
11.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access constants that do not change during
program execution (e.g. a constant used to initialize a loop counter).
EA = PC+1; PC ← PC+2
11.3.3
11
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
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11.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
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EA = (PC+1):(PC+2); PC ← PC+3
Address bus high ← (PC+1); Address bus low ← (PC+2)
11.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC ← PC+1
Address bus high ← 0; Address bus low ← X
11.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations. This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC ← PC+2
Address bus high ← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
11
11.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
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11.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
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EA = PC+2+(PC+1); PC ← EA if branch taken;
otherwise EA = PC ← PC+2
11.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode specifies the address of the byte in which the specified bit is to be set or
cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set
or cleared with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
11.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the first 256 locations of memory. The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
EA1 = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;
otherwise PC ← PC+3
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11
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ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
MC68HC05X16.
12.1
Absolute maximum ratings
Table 12-1 Absolute maximum ratings
Rating
Supply voltage(1)
Input voltage
Input voltage
– bootstrap mode (IRQ pin only)
Operating temperature range
Symbol
VDD
VIN
Value
– 0.5 to +7.0
VSS – 0.5 to VDD + 0.5
Unit
V
V
VIN
VSS – 0.5 to 2VDD + 0.5
V
TA
°C
Storage temperature range
Current drain per pin(2)
(Excluding VDD, VSS, VDD1 and VSS1)
– Source
– Sink
External oscillator frequency
TSTG
TL to TH
–40 to +125
– 65 to +150
°C
25
45
22
mA
mA
MHz
ID
IS
fOSC
(1) All voltages are with respect to VSS.
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
12
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.
MC68HC05X16
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12.2
DC electrical characteristics
Table 12-2 DC electrical characteristics
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12
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Output voltage
ILOAD = – 10 µA
VOH
ILOAD = +10 µA
VOL
Output high voltage (ILOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
VOH
Output high voltage (ILOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
VOH
Output high voltage (ILOAD = – 300µA)
OSC2
VOH
Output low voltage (ILOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
VOL
TDO, SCLK, PLMA, PLMB
Output low voltage (ILOAD = 1.6mA)
RESET
VOL
Output low voltage (ILOAD = – 100µA)
OSC2
VOL
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
VIH
RESET, TCAP1, TCAP2, RDI, MDS, NWOI
Input low voltage
VIL
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
RESET, TCAP1, TCAP2, RDI, MDS, NWOI
Can comparator IDD (IDD1)(3)(4)(5)
Supply current
RUN: CAN active(6)
IDD1
STOP: CAN active
IDD1
(7)
WAIT: CAN asleep
IDD1
STOP: CAN asleep
IDD1
MCU IDD(3)(4)(8)
Supply current in DIV2 mode
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
MCU IDD(3)(5)(8)
Supply current in DIV10 mode
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
IIL
Min
Typ(2)
Max
Unit
VDD – 0.1
—
—
—
—
0.1
V
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.3
—
—
0.1
0.4
—
0.2
0.6
—
0.2
0.4
0.7 VDD
—
VDD
V
VSS
—
0.2VDD
V
—
—
—
—
360
360
32
10
900
900
100
30
µA
µA
µA
µA
—
—
—
—
—
—
—
—
3.6
1.6
1.8
1.5
0.8
0.4
0.5
90
7
3.6
4
3.7
1.4
1.1
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
—
—
—
—
—
—
—
6.6
4.6
4.6
4.5
1.2
0.8
0.5
90
13
8
8.5
8
1.8
1.4
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
±0.2
±1
µA
V
V
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Table 12-2 DC electrical characteristics
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Input current
OSC1=VDD (OSC2=VSS)
IFH
Input current
OSC1=VSS (OSC2=VDD)
IFL
Input current
IRQ, TCAP1, TCAP2, RDI,
IIN
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
Ports (as input or output), RESET, TDO, SCLK
COUT
IRQ, TCAP1, TCAP2, OSC1, RDI
CIN
PD0/AN0–PD7/AN7 (A/D off)
CIN
PD0/AN0–PD7/AN7 (A/D on)
CIN
DC injection current(9)
Port A (PA0–PA7)
|IINJ|
Port B (PB0–PB7)
|IINJ|
Min
Typ(2)
Max
Unit
– 10
—
—
µA
—
—
+10
—
±0.2
±1
µA
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
—
—
—
—
10
10
mA
mA
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25∞C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source, refer to Figure 2-6(c); all inputs 0.2 V
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP/WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
(4) fOSC = 4.4 MHz; fBUS = 2.2 MHz; fCAN = 2.2 MHz
(5) fOSC = 22 MHz; fBUS = 2.2 MHz; fCAN = 11 MHz
(6) These limits are also applicable under the following conditions:
MCU RUN mode/SLOW mode/CAN active
MCU WAIT mode/SLOW mode/CAN active
MCU WAIT mode/CAN active
(7) These limits are also applicable under the following conditions:
MCU WAIT mode/SLOW mode/CAN asleep
(8) These currents are the summation of the MCU current + CAN current (IDD + IDD1)
(9) Current injection is guaranteed but not tested.
Functionality of the MCU is guaranteed during injection of dc current up to the maximum specified level.
The maximum specified current for each port is the sum of the magnitudes of the currents on each side of the
individual port pins.
Some disturbance of the A/D accuracy is possible during an injection event and is dependent on board layout,
power supply decoupling and reference voltage decoupling configurations.
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12.3
A/D converter characteristics
Table 12-3 A/D characteristics
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Parameter
Resolution
Number of bits resolved by the A/D
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
(VRH = VDD and VRL = 0V)
Quantization error
Uncertainty due to converter resolution
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
VRH
Maximum analog reference voltage
VRL
Minimum analog reference voltage
∆VR(1)
Minimum difference between VRH and VRL
Conversion time
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
Zero input reading
Conversion result when VIN = VRL
Full scale reading
Conversion result when VIN = VRH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
b. Internal RC oscillator(2)
Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7
Input leakage(3)
Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH
Min
8
Max
—
Unit
Bit
—
± 0.5
LSB
—
± 0.5
LSB
—
±1
LSB
VRL
VRL
VSS – 0.1
3
VRH
VDD + 0.1
VRH
—
V
V
V
V
—
—
32
32
tCYC
µs
GUARANTEED
00
—
—
FF
Hex
Hex
—
—
—
—
12
12
12
1
tCYC
µs
pF
µA
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 9-2).
12
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12.4
Control timing
Table 12-4 Control timing
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
Frequency of operation
Oscillator frequency
fOSC
MCAN module clock frequency
fCAN
MCU bus frequency
fMCU
Cycle time (see Figure 10-1)
tCYC
Crystal oscillator start-up time (see Figure 10-1)
tOXOV
Stop recovery start-up time (crystal oscillator)
tILCH
A/D converter stabilization time
tADON
External RESET input pulse width
tRL
Power-on RESET output pulse width (mask option)
4064 cycle
tPORL
16 cycle
tPORL
Watchdog RESET output pulse width
tDOGL
Watchdog time-out
tDOG
EEPROM byte erase time
tERA
EEPROM byte program time(1)
tPROG
Timer (see Figure 12-1)
Resolution(2)
tRESL
Input capture pulse width
tTH, tTL
Input capture pulse period
tTLTL
Interrupt pulse width (edge-triggered)
tILIH
Interrupt pulse period
tILIL
OSC1 pulse width
tOH, tOL
Write/erase endurance(5)(6)
—
Data retention(5)(6)
—
Min
Max
Unit
0
0
0
455
—
1.5
22
11
2.2
—
100
100
500
—
MHz
MHz
MHz
ns
ms
ms
µs
tCYC
4064
16
1.5
6144
10
10
—
—
—
7168
10
10
tCYC
tCYC
tCYC
tCYC
ms
ms
4
125
—(3)
125
—(4)
90
10000
10
—
—
—
—
—
—
tCYC
ns
tCYC
ns
tCYC
ns
cycles
years
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (tcyc), this is the limiting
factor in determining the timer resolution.
(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute
the capture interrupt service routine plus 24 tcyc.
(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 21 tcyc.
12
(5) At a temperature of 85°C.
(6) Refer to Reliability Monitor Report (currrent quarterly issue) for current failure rate information.
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure 12-1 Timer relationship
MC68HC05X16
ELECTRICAL SPECIFICATIONS
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12.5
MCAN bus interface DC electrical characteristics
Table 12-5 MCAN bus interface DC electrical characteristics
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12
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus input comparator: pins RX0 and RX1
Input voltage
VIN
Common mode range
CMR
Latch-up trigger current(1)
ILT
Input offset voltage
VOFS
Hysteresis
VHYS
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 mA
DVOUT
Output current
IOUT
Latch-up trigger current(1)
ILT
MCAN bus output driver: pins TX0 and TX1
Source current per pin (VOUT = VDD–1.0V)
IOH
Sink current per pin (VOUT = 1.0V)
IOL
Latch-up trigger current(1)
ILT
(VDD = 5.0 Vdc ± 2%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 µA
DVOUT
Min
Max
Unit
0.5
1.5
–100
–30
1
VDD +0.5
VDD –1.5
+100
+30
22
V
V
mA
mV
mV
–200
–100
–100
+200
+100
+100
mV
µA
mA
–10
10
–100
—
—
+100
mA
mA
mA
Min
Max
Unit
–180
+180
mV
(1) Maximum DC current should comply with maximum ratings.
12.6
MCAN bus interface control timing characteristics
Table 12-6 MCAN bus interface control timing characteristics
(4.5V ≤ VDD ≤ 5.5V, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus output driver
Rise and fall time (CLOAD = 100pF)
TRF
Min
Max
Unit
—
25
ns
ELECTRICAL SPECIFICATIONS
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13
MECHANICAL DATA
64-pin quad flat pack (QFP) pinout
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
VSS
VPP1
NC
NWOI
PB0
PB1
PB2
PB3
PB4
PB5
13.1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PB6
PB7
TX1
TX0
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
MDS
TCAP2
TCAP1
PLMB D/A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PC1
PC0
VDDH
VSS1
RX0
RX1
VDD1
RDI
SCLK
TDO
TCMP2
TCMP1
PD7/AN7
PD6/AN6
PD5/AN5
NU
VRL
VRH
PD4/AN4
VDD
PD3/AN3
PD2/AN2
PD1/AN1
PD0/AN0
NU
NC/CANE
NC/VPP6
OSC1
OSC2
RESET
IRQ
PLMA D/A
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Device
MC68HC05X16, MC68HC05X32
MC68HC705X32
Note:
Pin 26
NC
CANE
Pin 27
NC
VPP6
NC = Not connected
NU = Non-user pin (Should be tied to VSS in
an electrically noisy environment)
Unless otherwise stated, a pin labelled as ‘NU’ should be tied to VSS in an electrically noisy
environment. Pins labelled ‘NC’ can be left floating, since they are not bonded to any part of the
device.
13
Figure 13-1 64-pin QFP pinout
MC68HC05X16
MECHANICAL DATA
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13.2
64-pin quad flat pack (QFP) mechanical dimensions
L
B
33
13
-B-
Case No. 840C
64 lead QFP
B
0.05 A – B
-AL
P
B
32
0.20 M C A – BS D S
49
V
0.20 M H A – BS D S
48
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- A, B, D Detail “A”
F
Detail “A”
64
17
1
N
J
16
-D-
Base
Metal
D
A
0.20 M C A – BS D S
Section B–B
0.05 A – B
0.20 M C A – BS D S
S
0.20 M H A – BS D S
U
T
Detail “C”
M
E
Q
C
-CSeating
Plane
R
Datum
-H- Plane
H
K
G
W
M
X
Dim.
A
B
C
D
E
F
G
H
J
K
L
Min.
Max.
Notes
13.90 14.10
13.90 14.10
2.067 2.457
0.30
0.45
2.00
2.40
0.30
—
0.80 BSC
0.067 0.250
0.130 0.230
0.50
0.66
12.00 REF
1. Datum Plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the
parting line.
2. Datums A–B and –D to be determined at Datum Plane –H–.
3. Dimensions S and V to be determined at seating plane –C–.
4. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at Datum Plane –H–.
5. Dimension D does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 total in excess of the D dimension
at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7. All dimensions in mm.
Dim.
M
N
P
Q
R
S
T
U
V
W
X
Min.
Max.
5°
10°
0.130 0.170
0.40 BSC
2°
8°
0.13
0.30
16.20 16.60
0.20 REF
9°
15°
16.20 16.60
0.042 NOM
1.10
1.30
Figure 13-2 64-pin QFP mechanical dimensions
MECHANICAL DATA
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14
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ORDERING INFORMATION
This section describes the information needed to order the MC68HC05X16 and other family members.
To initiate a ROM pattern for the MCU, you should contact your local field service office, local sales
person or Motorola representative. Please note that you will need to supply details such as: mask
option selections; temperature range; oscillator frequency; package type; electrical test
requirements; and device marking details so that an order can be processed, and a customer
specific part number allocated. Refer to Table 14-1 for appropriate part numbers. The part number
consists of the device title plus the appropriate suffix. For example, the MC68HC05X16 in 64-pin
QFP package at –40 to +85 °C would be ordered as: MC68HC05X16CFU.
Table 14-1 MC order numbers
Note:
Device Title
Package Type
MC68HC05X16
MC68HC05X32
MC68HC705X32
64-pin QFP
64-pin QFP
64-pin QFP
Suffix
0 to 70°C
FU
FU
FU
Suffix
-40 to +85°C
CFU
CFU
CFU
Suffix
-40 to +105°C
VFU
VFU
Contact sales
Suffix
-40 to +125°C
MFU
MFU
Contact sales
The high speed version of the MC68HC05X32 has the same device title as the standard
version. High speed operation is selected via a check box on the order form and will be
confirmed on the listing verification form. See Appendix C for electrical characteristics.
14
MC68HC05X16
ORDERING INFORMATION
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14.1
EPROMS
For the MC68HC05X16, a 16K byte EPROM programmed with the customer’s software (positive
logic for address and data) should be submitted for pattern generation. All unused bytes should be
programmed to $00. The size of EPROM which should be used for all other family members is
listed in Table 14-2.
The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
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Table 14-2 EPROMs for pattern generation
Device
MC68HC05X16
MC68HC05X32
14.2
Size of EPROM
16K byte
32K byte
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and returned with a listing verification form.
The listing should be thoroughly checked and the verification form completed, signed and returned
to Motorola. The signed verification form constitutes the contractual agreement for creation of the
custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from
the data file used to create the custom mask, to aid in the verification process.
14.3
ROM verification units (RVU)
Ten MCUs containing the customer’s ROM pattern will be provided for program verification. These
units will have been made using the custom mask but are for ROM verification only. For
expediency, they are usually unmarked and are tested only at room temperature (25°C) and at
5 Volts. These RVUs are included in the mask charge and are not production parts. They are
neither backed nor guaranteed by Motorola Quality Assurance.
14
ORDERING INFORMATION
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A
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MC68HC05X32
Important note
The following applies to the D53J MC68HC05X32 mask set only:
–
Mask options on the MC68HC05X32 allow the customer to
select POR delay cycles and oscillator DIV ratio. However,
during reset, options of 4064 cycles POR and DIV 10 are
forced, regardless of which options the customer has selected.
Therefore, a power-on reset delay of 40640 oscillator cycles is
forced.
On the D53J mask set, DIV10 is forced in bootstrap mode. On later mask set
revisions, including D69J, DIV2 is forced in bootstrap mode.
The MC68HC05X32 is a device similar to the MC68HC05X16, but with increased RAM and ROM
sizes. The entire MC68HC05X16 data sheet applies to the MC68HC05X32, with the exceptions
outlined in this appendix.
A.1
Features
•
31232 bytes of user ROM plus 16 bytes of user vectors
•
528 bytes of RAM
•
654 bytes of bootstrap ROM
•
Available in 64-pin QFP package
•
High speed operation (4 MHz bus speed) available. See Appendix C for tables of electrical
characteristics.
•
– 40° to +125°C temperature range
MC68HC05X16
15
MC68HC05X32
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Memory map, register outline and block diagram
Charge pump
RESET
IRQ
COP watchdog
OSC2
OSC1
Oscillator
÷ 2 / ÷ 32
31248 bytes
user ROM
(including 16 bytes
user vectors)
654 bytes
Port A
VPP1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Port B
256 bytes
EEPROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Port C
A.2
The electrical characteristics for the MC68HC05X16 should not be used for the
MC68HC05X32. Section A.3.1 to Section A.3.4 contain data specific to this device.
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
bootstrap ROM
VDD1
VSS1
VDDH
TX0
TX1
RX0
RX1
Line
interface
M68HC05
CPU
VDD
VSS
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
VRL
MCAN
528 bytes
RAM
NWOI
MDS
Port D
Note:
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8-bit
A/D converter
16-bit
programmable
timer
TCMP1
TCMP2
TCAP1
TCAP2
SCI
RDI
SCLK
TDO
PLM
PLMA D/A
PLMB D/A
Figure A-1 MC68HC05X32 block diagram
15
MC68HC05X32
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MC68HC05X32
$0000
Register
$0000
I/O and registers
(32 bytes)
Ports
7 bytes
MCAN
registers
(30 bytes)
EEPROM/ECLK
control
1 byte
$0020
$0007
$003E
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$0008
A/D
converter
2 bytes
$0050
$00C0
$0100
$0101
Stack
$000A
RAM I
(176 bytes)
PLM system
2 bytes
OPTR (1 byte)
$000C
Non protected (31 bytes)
Miscellaneous
1 byte
$0120
EEPROM
(256 bytes)
$000D
SCI
5 bytes
Protected (224 bytes)
$0200
Bootstrap ROM I
(80 bytes)
$0012
Timer
14 bytes
$0250
RAM II
352 bytes
$03B0
MCAN
control registers
10 bytes
Bootstrap ROM II
(80 bytes)
$0400
User ROM
(31232 bytes)
MCAN
transmit buffer
10 bytes
$7E00
Bootstrap ROM III
(478 bytes)
$002A
$0034
MCAN
receive buffer
10 bytes
$7FDE
$7FE0
$003E
Bootstrap ROM vectors
(16 bytes)
$7FF0–1
CIRQ
$7FF2–3
SCI
$7FF4–5
Timer overflow
$7FF6–7 Timer output compare 1& 2
$7FF8–9 Timer input capture 1& 2
$7FFA–B
WOI, External IRQ
SWI
$7FFC–D
$7FFE–F
Reset/power-on reset
$0020
$0047
Options register
$0100
User
Vectors
Reserved
Figure A-2 Memory map of the MC68HC05X32
MC68HC05X16
15
MC68HC05X32
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Register
Registe
Port A data register
Port B data register
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
$0000
$0001
$0002
$0003
$0004
$0005
$0006
E/EEPROM/ECLK control register $0007
$0008
A/D data register
A/D status/control register $0009
Pulse length modulation A $000A
Pulse length modulation B $000B
$000C
Miscellaneous register
$000D
SCI baud rate register
$000E
SCI control register 1
$000F
SCI control register 2
$0010
SCI status register
$0011
SCI data register
$0012
Timer control register
$0013
Timer status register
$0014
Capture high register 1
$0015
Capture low register 1
$0016
Compare high register 1
$0017
Compare low register 1
$0018
Counter high register
$0019
Counter low register
Alternate counter high register $001A
Alternate counter low register $001B
$001C
Capture high register 2
$001D
Capture low register 2
$001E
Compare high register 2
$001F
Compare low register 2
$0020
Control register
$0021
Command register
$0022
Status register
$0023
Interrupt register
Acceptance code register $0024
Acceptance mask register $0025
$0026
Bus timing register 0
$0027
Bus timing register 1
$0028
Output control register
$0029
Test register
$002A
Transmit identifier
ATR bit/data length code $002B
Transmit data field (8 bytes) $002C
$0034
Receive identifier
ATR bit/data length code $0035
Receive data field (8 bytes) $0036
$003D
$0000
Ports
7 bytes
$0007
EEPROM/ECLK
control
1 byte
$0008
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A/D
converter
2 bytes
$000A
PLM system
2 bytes
$000C
Miscellaneous
1 byte
$000D
SCI
5 bytes
$0012
Timer
14 bytes
$0020
$002A
$0034
MCAN
control registers
10 bytes
MCAN
transmit buffer
10 bytes
MCAN
receive buffer
10 bytes
$003E
$0047
$0100
Options register
Figure A-2 Memory map of the MC68HC05X32 (Continued)
15
MC68HC05X32
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Table A-1 Register outline
Register name
Address bit 7
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
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bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PD3
PC2/
ECLK
PD2
PD1
PD0
$0000
$0001
$0002
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
A/D data (ADDATA)
A/D status/control (ADSTAT)
Pulse length modulation A (PLMA)
Pulse length modulation B (PLMB)
Miscellaneous
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
Options (OPTR)(3)
$0003
PD7
$0004
$0005
$0006
$0007 WOIE
$0008
$0009 COCO
$000A
$000B
$000C POR(1)
$000D SPC1
$000E
R8
$000F
TIE
$0010 TDRE
$0011
$0012
ICIE
$0013 ICF1
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
PD6
PD5
CAF
0
ADRC ADON
INTP INTN
SPC0 SCT1
T8
TCIE
RIE
TC
RDRF
OCIE
OCF1
TOIE
TOF
PD4
State on
reset
Undefined
Undefined
Undefined
Undefined
0000 0000
0000 0000
0000 0000
0
ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
0
CH3
CH2
CH1
CH0
0000 0000
0000 0000
0000 0000
INTE SFA
SFB
SM WDOG(2) u001 000u
SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M
WAKE CPOL CPHA LBCL Undefined
ILIE
TE
RE
RWU
SBK
0000 0000
IDLE
OR
NF
FE
1100 000u
0000 0000
FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
ICF2 OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
EE1P SEC Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
MC68HC05X16
15
MC68HC05X32
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A.3
Electrical specifications
This section contains the electrical specifications and associated timing information for the
MC68HC05X32.
A.3.1
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15
Maximum ratings
Table A-2 Maximum ratings
Rating
Supply voltage(1)
Input voltage
Input voltage
– bootstrap mode (IRQ pin only)
Operating temperature range
Symbol
VDD
VIN
Value
– 0.5 to +7.0
VSS – 0.5 to VDD + 0.5
Unit
V
V
VIN
VSS – 0.5 to 2VDD + 0.5
V
TA
°C
Storage temperature range
Current drain per pin(2)
(Excluding VDD, VSS, VDD1 and VSS1)
– Source
– Sink
External oscillator frequency
TSTG
TL to TH
– 40 to +125
– 65 to +150
25
45
22
mA
mA
MHz
ID
IS
fOSC
°C
(1) All voltages are with respect to VSS.
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.
MC68HC05X32
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A.3.2
DC electrical characteristics
Table A-3 DC electrical characteristics
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Output voltage
ILOAD = – 10 µA
VOH
ILOAD = +10 µA
VOL
Output high voltage (ILOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
VOH
Output high voltage (ILOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
VOH
Output high voltage (ILOAD = –300µA)
OSC2
VOH
Output low voltage (ILOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
VOL
TDO, SCLK, PLMA, PLMB
Output low voltage (ILOAD = 1.6mA)
RESET
VOL
Output low voltage (ILOAD = –100µA)
OSC2
VOL
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
VIH
RESET, TCAP1, TCAP2, RDI, MDS, NWOI
Input low voltage
VIL
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
RESET, TCAP1, TCAP2, RDI, MDS, NWOI
Can comparator IDD (IDD1)(3)(4)(5)
Supply current in DIV2 mode
RUN: CAN active(6)
IDD1
STOP: CAN active
IDD1
(7)
WAIT: CAN asleep
IDD1
STOP: CAN asleep
IDD1
MCU IDD(3)(4)(8)
Supply current in DIV 2 mode
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
MCU IDD(3)(5)(8)
Supply current in DIV 10 mode
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
IIL
MC68HC05X16
Min
Typ(2)
Max
Unit
VDD – 0.1
—
—
—
—
0.1
V
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.3
—
—
0.1
0.4
—
0.2
0.6
—
0.2
0.4
0.7 VDD
—
VDD
V
VSS
—
0.2VDD
V
—
—
—
—
360
360
32
10
900
900
100
30
µA
µA
µA
µA
—
—
—
—
—
—
—
—
3.6
1.6
1.8
1.5
0.8
0.4
0.5
90
7
3.6
4
3.7
1.4
1.1
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
—
—
—
—
—
—
—
6.6
4.6
4.6
4.5
1.2
0.8
0.5
90
13
8
8.5
8
1.8
1.4
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
±0.2
±1
µA
V
V
15
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Table A-3 DC electrical characteristics
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15
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Input current
OSC1=VDD (OSC2=VSS)
IFH
Input current
OSC1=VSS (OSC2=VDD)
IFL
Input current
IRQ, TCAP1, TCAP2, RDI,
IIN
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
Ports (as input or output), RESET, TDO, SCLK
COUT
IRQ, TCAP1, TCAP2, OSC1, RDI
CIN
PD0/AN0–PD7/AN7 (A/D off)
CIN
PD0/AN0–PD7/AN7 (A/D on)
CIN
DC injection current(9)
Port A (PA0–PA7)
|IINJ|
Port B (PB0–PB7)
|IINJ|
Min
Typ(2)
Max
Unit
–10
—
—
µA
—
—
+10
—
±0.2
±1
µA
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
—
—
—
—
10
10
mA
mA
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source, refer to Figure 2-6(c); all inputs 0.2 V
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP/WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
(4) fOSC = 4.4 MHz; fBUS = 2.2 MHz; fCAN = 2.2 MHz
(5) fOSC = 22 MHz; fBUS = 2.2 MHz; fCAN = 11 MHz
(6) These limits are also applicable under the following conditions:
MCU RUN mode/SLOW mode/CAN active
MCU WAIT mode/SLOW mode/CAN active
MCU WAIT mode/CAN active
(7) These limits are also applicable under the following conditions:
MCU WAIT mode/SLOW mode/CAN asleep
(8) These currents are the summation of the MCU current + CAN current (IDD + IDD1)
(9) Current injection is guaranteed but not tested.
Functionality of the MCU is guaranteed during injection of dc current up to the maximum specified level.
The maximum specified current for each port is the sum of the magnitudes of the currents on each side of the
individual port pins.
Some disturbance of the A/D accuracy is possible during an injection event and is dependent on board layout,
power supply decoupling and reference voltage decoupling configurations.
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A.3.3
A/D converter characteristics
Table A-4 A/D characteristics
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Parameter
Resolution
Number of bits resolved by the A/D
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
(VRH = VDD and VRL = 0V)
Quantization error
Uncertainty due to converter resolution
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
VRH
VRL
∆VR(1)
Conversion time
Maximum analog reference voltage
Minimum analog reference voltage
Minimum difference between VRH and VRL
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
Zero input reading
Conversion result when VIN = VRL
Full scale reading
Conversion result when VIN = VRH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
b. Internal RC oscillator(2)
Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7
Input leakage(3)
Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH
Min
8
Max
—
Unit
Bit
—
± 0.5
LSB
—
± 0.5
LSB
—
±1
LSB
VRL
VRH
V
VRL
VSS – 0.1
3
VDD + 0.1
VRH
—
V
V
V
—
—
32
32
tCYC
µs
GUARANTEED
00
—
—
FF
Hex
Hex
—
—
—
—
12
12
12
1
tCYC
µs
pF
µA
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 9-2).
MC68HC05X16
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A.3.4
Control timing
Table A-5 Control timing
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
Frequency of operation
Oscillator frequency
fOSC
MCAN module clock frequency
fCAN
MCU bus frequency
fMCU
Cycle time (see Figure 10-1)
tCYC
Crystal oscillator start-up time (see Figure 10-1)
tOXOV
Stop recovery start-up time (crystal oscillator)
tILCH
A/D converter stabilization time
tADON
External RESET input pulse width
tRL
Power-on RESET output pulse width (mask option)
4064 cycle
tPORL
16 cycle
tPORL
Watchdog RESET output pulse width
tDOGL
Watchdog time-out
tDOG
EEPROM byte erase time
tERA
EEPROM byte program time(1)
tPROG
Timer (see Figure A-3)
Resolution(2)
tRESL
Input capture pulse width
tTH, tTL
Input capture pulse period
tTLTL
Interrupt pulse width (edge-triggered)
tILIH
Interrupt pulse period
tILIL
OSC1 pulse width
tOH, tOL
Write/erase endurance(5)(6)
—
Data retention(5)(6)
—
Min
Max
Unit
0
0
0
455
—
1.5
22
11
2.2
—
100
100
500
—
MHz
MHz
MHz
ns
ms
ms
µs
tCYC
4064
16
1.5
6144
10
10
—
—
—
7168
10
10
tCYC
tCYC
tCYC
tCYC
ms
ms
4
125
—(3)
125
—(4)
90
10000
10
—
—
—
—
—
—
tCYC
ns
tCYC
ns
tCYC
ns
cycles
years
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (tcyc), this is the limiting
factor in determining the timer resolution.
(3) The minimum period tTLTL should not be less than the number of cycle times it takes to execute
the capture interrupt service routine plus 24 tcyc.
(4) The minimum period tILIL should not be less than the number of cycle times it takes to execute
the interrupt service routine plus 21 tcyc.
(5) At a temperature of 85°C.
(6) Refer to Reliability Monitor Report (currrent quarterly issue) for current failure rate information.
15
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tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure A-3 Timer relationship
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A.3.5
MCAN bus interface DC electrical characteristics
Table 1-6 MCAN bus interface DC electrical characteristics
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus input comparator: pins RX0 and RX1
Input voltage
VIN
Common mode range
CMR
Latch-up trigger current(1)
ILT
Input offset voltage
VOFS
Hysteresis
VHYS
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 µA
DVOUT
Output current
IOUT
Latch-up trigger current(1)
ILT
MCAN bus output driver: pins TX0 and TX1
Source current per pin (VOUT = VDD–1.0V)
IOH
Sink current per pin (VOUT = 1.0V)
IOL
Latch-up trigger current(1)
ILT
(VDD = 5.0 Vdc ± 2%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 µA
DVOUT
Min
Max
Unit
0.5
1.5
–100
–30
1
VDD +0.5
VDD –1.5
+100
+30
22
V
V
mA
mV
mV
–200
–100
–100
+200
+100
+100
mV
mA
mA
–10
10
–100
—
—
+100
mA
mA
mA
Min
Max
Unit
–180
+180
mV
(1) Maximum DC current should comply with maximum ratings.
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A-11
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A.3.6
MCAN bus interface control timing characteristics
Table 1-7 MCAN bus interface control timing characteristics
(4.5V ≤ VDD ≤ 5.5V, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus output driver
Rise and fall time (CLOAD = 100pF)
TRF
Min
Max
Unit
—
25
ns
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MC68HC05X16
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B
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MC68HC705X32
Important note
The following applies to the D59J MC68HC705X32 mask set only.
–
A mask option register (MOR) on the MC68HC705X32 allows
the customer to select POR delay cycles and oscillator DIV
ratio. However, during reset, options of 4064 cycles POR and
DIV10 are forced, regardless of which options the customer has
selected. Therefore, a power-on reset delay of 40640 oscillator
cycles is forced.
On the D59J mask set, the oscillator divide ratio depends on the CANE pin:
CANE = 1
CANE = 0
DIV10 forced in bootloader mode
DIV2 forced in bootloader mode
On later mask set revisions, including G47V, DIV2 is forced in bootloader mode,
regardless of the CANE pin.
The following applies to the D40J and D59J MC68HC705X32 mask sets only:
–
The minimum external RESET input pulse width, tRL
(Table B-10) is 1.5 tCYC
–
Maximum bus speed 2.2 MHz
The MC68HC705X32 is a device similar to the MC68HC05X16, but with 32K bytes of EPROM
instead of 16K bytes of ROM. In addition, the bootstrap routines available in the MC68HC05X16
are replaced by bootstrap routines specific to the MC68HC705X32. The entire MC68HC05X16
data sheet applies to the MC68HC705X32, with the exceptions outlined in this appendix.
MC68HC05X16
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B-1
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B.1
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Features
•
–40 to +125°C operating temperature range
•
31232 bytes user EPROM plus 16 bytes of EPROM user vectors
•
528 bytes of RAM
•
654 bytes bootstrap ROM
•
Simultaneous programming of up to 16 bytes of EPROM
•
4 MHz bus speed
•
Available in 64-pin QFP package
Note:
B.2
The electrical characteristics for the MC68HC05X16 should not be used for the
MC68HC705X32. Section B.9.2 and Section B.9.5 contain data specific to this device.
VPP6
The VPP6 pin is the voltage input for the EPROM in both read and programming modes (see
Section B.5).
B.3
CANE
This pin is the MCAN enable input. If CANE is connected to VDD, the internal MCAN module is
selected and its registers are mapped at addresses $0020 to $003D.
Note:
Although this pin can be left floating to disconnect the MCAN module, it is advisable to
connect it to VSS when the module is not in use.
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B.4
Block diagram, memory map and register outline
VPP6
256 bytes
EEPROM
COP watchdog
OSC2
OSC1
Oscillator
VDD1
VSS1
VDDH
TX0
TX1
RX0
RX1
÷ 2 / ÷ 32
Line
interface
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
MCAN
528 bytes
RAM
NWOI
MDS
M68HC05
CPU
VDD
VSS
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
VRL
654 bytes
bootstrap ROM
Port A
RESET
IRQ
31248 bytes
EPROM
(including 16 bytes
user vectors)
Port B
Charge pump
CANE
Port C
VPP1
Port D
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8-bit
A/D converter
16-bit
programmable
timer
TCMP1
TCMP2
TCAP1
TCAP2
SCI
RDI
SCLK
TDO
PLM
PLMA D/A
PLMB D/A
Figure B-1 MC68HC705X32 block diagram
MC68HC05X16
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Table B-1 Register outline
Register name
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Address bit 7
Port A data (PORTA)
$0000
Port B data (PORTB)
$0001
Port C data (PORTC)
$0002
Port D data (PORTD)
$0003
Port A data direction (DDRA)
$0004
Port B data direction (DDRB)
$0005
Port C data direction (DDRC)
$0006
EEPROM/ECLK control
$0007
A/D data (ADDATA)
$0008
A/D status/control (ADSTAT)
$0009
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
Miscellaneous
$000C
SCI baud rate (BAUD)
$000D
SCI control 1 (SCCR1)
$000E
SCI control 2 (SCCR2)
$000F
SCI status (SCSR)
$0010
SCI data (SCDR)
$0011
Timer control (TCR)
$0012
Timer status (TSR)
$0013
Input capture high 1
$0014
Input capture low 1
$0015
Output compare high 1
$0016
Output compare low 1
$0017
Timer counter high
$0018
Timer counter low
$0019
Alternate counter high
$001A
Alternate counter low
$001B
Input capture high 2
$001C
Input capture low 2
$001D
Output compare high 2
$001E
Output compare low 2
$001F
$0100
Options (OPTR)(3)
Mask option register (MOR)(4) $7FDE
bit 6
PD7
PD6
WOIE
CAF
COCO ADRC
POR(1) INTP
SPC1 SPC0
R8
T8
TIE
TCIE
TDRE
TC
ICIE
ICF1
OCIE
OCF1
WOI
DIV2
State on
reset
Undefined
Undefined
PC2/ECLK
Undefined
PD5
PD4
PD3
PD2
PD1
PD0 Undefined
0000 0000
0000 0000
0000 0000
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
ADON
0
CH3
CH2
CH1
CH0 0000 0000
0000 0000
0000 0000
INTN INTE SFA
SFB
SM WDOG(2) u001 000u
SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
M
WAKE CPOL CPHA LBCL Undefined
RIE
ILIE
TE
RE
RWU
SBK 0000 0000
RDRF IDLE
OR
NF
FE
1100 000u
0000 0000
TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
TOF ICF2 OCF2
Undefined
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
EE1P SEC Not affected
DIV8 RTIM RWAT WWAT PBPD PCPD Not affected
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page
B-1.
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$0000
MC68HC705X32
Register groups
I/O and registers
(32 bytes)
Ports
7 bytes
$0020
$0000
MCAN
registers
(30 bytes)
$0007
EEPROM/ECLK
control
1 byte
$003E
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$0008
A/D
converter
2 bytes
$0050
$00C0
$0100
$0101
RAM I
(176 bytes)
$000A
PLM system
2 bytes
Stack
OPTR (1 byte)
$000C
Non protected (31 bytes)
Miscellaneous
1 byte
$0120
EEPROM
(256 bytes)
$000D
SCI
5 bytes
Protected (224 bytes)
$0200
Bootstrap ROM I
(80 bytes)
$0012
Timer
14 bytes
$0250
RAM II
352 bytes
$03B0
MCAN
control registers
10 bytes
Bootstrap ROM II
(80 bytes)
$0400
User EPROM
(31232 bytes)
MCAN
transmit buffer
10 bytes
$7E00
Bootstrap ROM III
(478 bytes)
$7FDE
$7FDF
$7FE0
$0020
$002A
$0034
MCAN
receive buffer
10 bytes
Mask options register
$003E
Bootstrap ROM vectors
(16 bytes)
$7FF0–1
CIRQ
$7FF2–3
SCI
$7FF4–5
Timer overflow
$7FF6–7 Timer output compare 1& 2
$7FF8–9 Timer input capture 1& 2
$7FFA–B
WOI, External IRQ
$7FFC–D
SWI
$7FFE–F
Reset/power-on reset
$0047
Options register
$0100
Mask options register
$7FDE
EPROM
User
Vectors
Reserved
Figure B-2 Memory map of the MC68HC705X32
MC68HC05X16
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Register groups
Registers
Port A data register
Port B data register
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
$0000
$0001
$0002
$0003
$0004
$0005
$0006
E/EEPROM/ECLK control register $0007
$0008
A/D data register
A/D status/control register $0009
Pulse length modulation A $000A
Pulse length modulation B $000B
$000C
Miscellaneous register
$000D
SCI baud rate register
$000E
SCI control register 1
$000F
SCI control register 2
$0010
SCI status register
$0011
SCI data register
$0012
Timer control register
$0013
Timer status register
$0014
Capture high register 1
$0015
Capture low register 1
$0016
Compare high register 1
$0017
Compare low register 1
$0018
Counter high register
$0019
Counter low register
Alternate counter high register $001A
Alternate counter low register $001B
$001C
Capture high register 2
$001D
Capture low register 2
$001E
Compare high register 2
$001F
Compare low register 2
$0020
Control register
$0021
Command register
$0022
Status register
$0023
Interrupt register
Acceptance code register $0024
Acceptance mask register $0025
$0026
Bus timing register 0
$0027
Bus timing register 1
$0028
Output control register
$0029
Test register
$002A
Transmit identifier
ATR bit/data length code $002B
Transmit data field (8 bytes) $002C
$0034
Receive identifier
ATR bit/data length code $0035
Receive data field (8 bytes) $0036
$003D
$0000
Ports
7 bytes
$0007
EEPROM/ECLK
control
1 byte
$0008
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A/D
converter
2 bytes
$000A
PLM system
2 bytes
$000C
Miscellaneous
1 byte
$000D
SCI
5 bytes
$0012
Timer
14 bytes
$0020
$002A
$0034
MCAN
control registers
10 bytes
MCAN
transmit buffer
10 bytes
MCAN
receive buffer
10 bytes
$003E
$0047
$0100
Options register
$7FDE
Mask options register
Figure B-2 Memory map of the MC68HC705X32 (Continued)
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B.5
EPROM
The MC68HC705X32 memory map is given in Figure B-2. The device has a total of 31248 bytes
of EPROM. 16 bytes are used for the reset and interrupt vectors from address $7FF0 to $7FFF.
The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is
used as an option register and is located at address $7FDE.
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The EPROM can be completely tested before assembly with sequences of both program and
erase. It is finally erased before being typically assembled in a package with no erase window.
Therefore, only programming is possible and the EPROM operates as a PROM.
The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the
user’s software would be loaded into a programming board where VPP6 is controlled by one of the
bootstrap loader routines. It would then be placed in an application where no programming occurs.
In this case the VPP6 pin should be hardwired to VDD.
Warning: A minimum VPP6R voltage must be applied to the VPP6 pin at all times, including
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient temperature (25°C)
only.
B.5.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read
operations. The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’ which
automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading
the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory
content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,
the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin
must be at the VPP6R level. When entering the STOP mode, the EPROM is automatically set to the
read mode.
Note:
An erased byte reads as $00.
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B.5.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.
However, the user program can be used to program some EPROM locations if the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
EPROM will not be available for code execution while the E6LAT bit is set. The VPP6 switching must
occur externally after the E6PGM bit is set, for example under control of a signal generated on a
pin by the programming routine.
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Note:
When the part becomes a PROM, only the cumulative programming of bits to logic ‘1’
is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to sixteen bytes, these bytes must be in the same group
of addresses which share the same most significant address bits; only the four least significant bits
can change.
B.5.3
EPROM/EEPROM/ECLK control register
EPROM/EEPROM/ECLK control
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
bit 6
bit 5
$0007
WOIE
CAF
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
WOIE — Wired-OR interrupt enable bit
1 (set)
–
0 (clear) –
Wired-OR interrupts are enabled, provided the WOI bit in register
MOR is set.
Wired-OR interrupts are disabled.
The WOIE bit can be used to enable the wired-OR interrupts (WOI) on the NWOI pin and on all
port B pins that have been programmed as inputs. WOI is activated if the WOIE bit is set and if the
WOI bit in the mask options register (MOR) is also set (see Section B.7). If WOI is not set then
WOIE is forced to zero. External and power-on resets clear the WOIE bit.
CAF — MCAN asleep flag
This flag is set by the MCU when the MCAN module enters SLEEP mode.This is the only indication
that the MCAN is asleep (see Section 5.5). The bit is cleared when the MCAN wakes up.
1 (set)
–
0 (clear) –
15
The MCAN module is in sleep mode.
The MCAN module is not in sleep mode.
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E6LAT — EPROM programming latch enable bit
1 (set)
–
Address and up to sixteen data bytes can be latched into the EPROM
for further programming providing the E6PGM bit is cleared.
0 (clear) –
Data can be read from the EPROM or firmware ROM; the E6PGM bit
is cleared when E6LAT is ‘0’.
STOP, power-on and external reset clear the E6LAT bit.
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Note:
After the tERA1 erase time or tPROG1 programming time, the E6LAT bit has to be reset
to zero in order to clear the E6PGM bit.
E6PGM — EPROM program enable bit
This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after
E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using
software but clearing E6LAT will always clear E6PGM.
Table B-2 EPROM control bits description
E6LAT E6PGM
Description
0
0
Read/execute in EPROM
1
0
Ready to write address/data to EPROM
1
1
programming in progress
Note:
The E6PGM bit can never be set while the E6LAT bit is at zero.
ECLK — External clock output
See Section 4.3.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
0 (clear) –
An erase operation will take place.
A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
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E1LAT — EEPROM programming latch enable bit
1 (set)
–
0 (clear) –
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
Data can be read from the EEPROM. The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
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Note:
After the tERA1 erase time or tPROG1 programming time, the E1LAT bit has to be reset
to zero in order to clear the E1ERA bit and the E1PGM bit.
1) E1PGM — EEPROM charge pump enable/disable
1 (set)
–
Internal charge pump generator switched on.
0 (clear) –
Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in
Table B-3.
Table B-3 EEPROM1 control bits description
E1ERA
0
0
0
1
1
Note:
E1LAT E1PGM
Description
0
0
Read condition
1
0
Ready to load address/data for program/erase
1
1
Byte programming in progress
1
0
Ready for byte erase (load address)
1
1
Byte erase in progress
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
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B.6
EEPROM options register (OPTR)
Address
Options (OPTR)(1)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
$0100
State
on reset
bit 1
bit 0
EE1P
SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
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EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is split into two parts, both working
from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to $011F) cannot
be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit in the options
register.
1 (set)
–
0 (clear) –
Part 2 of the EEPROM array is not protected; all 256 bytes of
EEPROM can be accessed for any read, erase or programming
operations.
Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful.
When this bit is set (erased), the protection will remain until the next power-on or external reset.
EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.
Note:
The EEPROM1 protect function is disabled while in bootstrap mode.
SEC — Secure bit
This bit allows the EPROM and EEPROM1 to be secured from external access. When this bit is in
the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be
used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1
content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the
EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be
entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its
new value will have no effect until the next power-on or external reset.
1 (set)
–
0 (clear) –
MC68HC05X16
EEPROM/EPROM not protected.
EEPROM/EPROM protected.
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B.7
Mask option register (MOR)
Mask option register (MOR)(1)
bit 2
bit 1
bit 0
State
on reset
Address
bit 7
bit 6
bit 5
bit 4
bit 3
$7FDE
WOI
DIV2
DIV8
RTIM
RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits. However, please read the important note on page B-1.
WOI — Wired-OR interrupt enable
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1 (set)
–
0 (clear) –
Wired-OR interrupts are enabled, provided the WOIE bit in the
EPROM/EEPROM/ECLK control register is set.
Wired-OR interrupts are disabled, irrespective of the WOIE bit in the
EPROM/EEPROM/ECLK control register.
The WOI bit can be used to enable the wired-OR interrupt (WOI) on all port B pins that have been
programmed as inputs. WOI is activated if the WOI bit is set and if the WOIE bit in the OPTR
register is also set.
DIV2, DIV8 — Clock divide ratio selection
The DIV2 and DIV8 bits are used to select the CPU clock divide ratio (see Table B-4). Note that a
divide-by-two clock ratio is forced in bootstrap mode, regardless of the DIV2 and DIV8 values.
Table B-4 Clock divide ratio selection
DIV2
1
1
0
0
DIV8
1
0
1
0
Clock divide ratio
2
4
8
10
RTIM — Reset time
This bit can modify the time tPORL, where the RESET pin is kept low after a power-on reset.
1 (set)
–
0 (clear) –
tPORL = 16 cycles.
tPORL = 4064 cycles.
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset.
1 (set)
–
0 (clear) –
15
The watchdog will be active immediately following power-on or
external reset (except in bootstrap mode).
The watchdog system will be disabled after power-on or external reset.
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WWAT — Watchdog during WAIT mode
This bit can modify the status of the watchdog counter during WAIT mode.
1 (set)
–
0 (clear) –
The watchdog will be active during WAIT mode.
The watchdog system will be disabled during WAIT mode.
PBPD — Port B pull-down
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This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,
RPD, is active on a given pin only while it is an input.
1 (set)
–
0 (clear) –
Pull-down resistors are connected to all 8 pins of port B; the
pull-down, RPD, is active only while the pin is an input.
No pull-down resistors are connected.
PCPD — Port C pull-down
This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down,
RPD, is active on a given pin only while it is an input.
1 (set)
–
0 (clear) –
MC68HC05X16
Pull-down resistors are connected to all 8 pins of port C; the
pull-down, RPD, is active only while the pin is an input.
No pull-down resistors are connected.
15
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B.8
Bootstrap mode
Oscillator divide-by-two is forced in bootstrap mode; all other options stay as programmed in the
mask options register (see Section B.7).
The bootstrap firmware is located in mask ROM at address locations $0200 to $024F, $03B0 to
$3FFF, $7E00 to $7FDD and $7FE0 to $7FEF. This firmware can be used to program the EPROM
and the EEPROM, to check if the EPROM is erased, or to load and execute routines in RAM.
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After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the following conditions must be met during transition of the RESET pin from low to high:
1) IRQ pin at 2xVDD or MDS pin at VDD
2) TCAP1 pin at VDD
3) TCAP2 pin at VSS
The hold time on the IRQ, MDS, TCAP1 and TCAP2 pins is two clock cycles after the external
RESET pin is brought high.
When the MC68HC705X32 is placed in the bootstrap mode, the bootstrap reset vector will be
fetched and the bootstrap firmware will start to execute. Table B-5 shows the conditions required
to enter each level of bootstrap mode on the rising edge of RESET.
The bootstrap program first copies part of itself into RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM.
Table B-5 Mode of operation selection
MDS
IRQ
TCAP1
TCAP2
VSS AND VSS to VDD VSS to VDD
x
VDD
OR
2VDD
VDD
VSS
VDD
OR
2VDD
VDD
VSS
VDD
OR
2VDD
VDD
VSS
VDD
OR
2VDD
VDD
VSS
2VDD
2VDD
VDD
VDD
VSS
VSS
VDD OR
VDD OR
x = Don’t care
15
PD1 PD2 PD3 PD4
Mode
x
x
x
x Single-chip mode
Bootstrap mode:
0
0
0
x EPROM erase check
EPROM erase check, erase EEPROM, parallel
1
0
0
x
EPROM/EEPROM program/verify
0
1
0
x Parallel EEPROM only verify (SEC bit not active)
EPROM erase check, erase EEPROM, parallel EPROM
1
1
0
x
only program/verify
x
1
1
0 Jump to RAM $0051 (SEC bit not active)
x
x
1
1 Serial RAM load and execute (SEC bit not active)
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Bootstrap mode
Parallel E/EEPROM bootstrap
Erased EPROM verification
Y
PD3 set?
N
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Y
SEC bit active?
N
N
PD2 set?
PD4 set?
Y
Y
Serial RAM
load/execute
N
Y
N
PD1 set?
PD2 set?
Y
N
N
Red LED on
Red LED on
Jump to RAM
($0051)
Reserved for
Motorola use
EPROM erased?
Y
Green LED on
Y
SEC bit active?
PD1 set?
Red LED on
N
N
Y
PD4 set?
A
Erase EEPROM1
B
Red LED off
N
C
Figure B-3 Modes of operation flow chart
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C
Y
N
PD2 set?
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Base address = $400
(EPROM only)
Base address = $100
(EPROM and EEPROM)
Y
A
PD2 set?
B
N
Base address = $400
(EPROM only)
Base address = $100
(EPROM and EEPROM)
Data verified?
N
Red LED on
Y
Green LED on
Figure B-3 Modes of operation flow chart (Continued)
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B.8.1
Erased EPROM verification and EEPROM erasure
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see
Figure B-3). Only when the whole EPROM array is verified as erased will the green LED be turned
on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs
until a high level is sensed on PD1.
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If PD1 = 1, the bootstrap program proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0
MHz crystal). It is then checked for complete erasure; if any EEPROM byte is not erased, the
program will stop before erasing the SEC byte. When both EPROM and EEPROM1 are completely
erased and the security bit is cleared the programming operation can be performed. A schematic
diagram of the circuit required for erased EPROM verification is shown in Figure B-6.
B.8.2
EPROM/EEPROM parallel bootstrap
Within this mode there are various subsections which can be utilised by correctly configuring the
port pins shown in Table B-5.
The erased EPROM verification program will be executed first as described in Section B.8.1. When
PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify for the
EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing address order
with non EPROM segments being skipped by the loader. Simultaneous programming is performed
by reading sixteen bytes of data before actual programming is performed, thus dividing the loading
time of the internal EPROM by 16. If any block of 16 EPROM bytes or 1 EEPROM byte of data is
in the erased state, no programming takes place, thus speeding up the execution time.
Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4
and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,
handshake will be provided by PC5 and PC6 according to the timing diagram of Figure B-4 (see
also Figure B-5).
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the EPROM and EEPROM1 content will be
checked against the external data source. If programming is verified the green LED will stay on,
while an error will cause the red LED to be turned on. Figure B-6 is a schematic diagram of a circuit
which can be used to program the EPROM or to load and execute data in the RAM.
Note:
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all $00s
for EPROM data and all $FFs for EEPROM1 data.
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Address
HDSK out
(PC5)
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Data
HDSK in
(PC6)
F29
Data read
Data read
Figure B-4 Timing diagram with handshake
tCOOE
tCOOE
tCOOE
tCDDE
Address
tADE
tADE
tDHE
tADE
tDHE
tADE
tDHE
tDHE
Data
tADE max (address to data delay)
5 machine cycles
tDHA min (data hold time)
14 machine cycles
tCOOE (load cycle time)
117 machine cycles < tCOOE < 150 machine cycles
tCDDE (programming cycle time)
tCOOE + tPROG (5ms nominal for EPROM; 10ms for EEPROM1))
1 machine cycle = 1/(2f0(Xtal))
Figure B-5 Parallel EPROM loader timing diagram
15
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P1
RESET
100kΩ
RUN
1N914
+
100mF
1.0mF
+
red LED
470Ω
0.01mF
470Ω
TCAP1 VRH
VDD
IRQ
OSC1
RESET
OSC2
NC
TCMP1
VPP1
PLMA
PLMB
RDI
VRL
TCAP2
PD7
PD6
PD5
PD3
PD2
PD1
PD0
Boot
green LED
red LED — programming failed
green LED — programming OK
Erase check
green LED — EPROM erased
red LED — EPROM not erased
GND
+5V
VPP
47mF
+
4.0 MHz
22pF
22pF
Verify
EPROM
Erase check & boot
Program
EPROM
EPROM erase
check
MC68HC705X32
MCU
+5V
RAM
27
PGM
28
VCC
A14
26
A13
A0
A1
A2
A3
A4
A5
A6
A7
CE
27C256
D0
D1
D2
D3
D4
D5
D6
D7
25
A8
24
A9
21
A10
23
A11
2
A12
GND
14
10
9
8
7
6
5
4
3
11
12
13
15
16
17
18
19
EPROM
SCLK
TDO
TCMP2
10kΩ
VPP6
12 kΩ
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
4k7Ω
PC7
BC239C
1nF
+
4k7Ω
+5V
100 kΩ
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
HDSK out
PC5
PC6
VSS
OE
1 kΩ
BC309C
1
VPP
1N5819
PD4
20
1
2
3
1kΩ
1N914
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PC4
PC3
PC2
PC1
PC0
Short circuit if
handshake not used
A12
A11
A10
A9
A8
HDSK in
22
Figure B-6 EPROM parallel bootstrap schematic diagram
Warning: A minimum VPP6R voltage must be applied to the VPP6 pin at all times, including
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient temperature (25°C)
only.
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B-19
201
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B.8.3
Serial RAM loader
This mode is similar to the RAM load/execute program for the MC68HC05X32 described in
Section 2.1.2.1, with the additional features listed below. Table B-5 shows the entry conditions
required for this mode.
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If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05X32, i.e. count
byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)
then the code continues to fill RAM II then RAM III. In this case the count byte is ignored and the
program execution begins at $0051 once the total RAM area is filled or if no data is received for 5
milliseconds.
The user must take care when using branches or jumps as his code will be relocated in RAM I, II
and III. If the user intends to use the stack in his program, he should send NOP’s to fill the desired
stack area.
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table B-6). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the users
service-routine address.
Table B-6 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
SWI
B.8.3.1
$0063
$0060
$005D
$005A
$0057
$0054
Jump to start of RAM ($0051)
The Jump to start of RAM program will be executed then the device will be brought out of reset
with PD2 and PD3 at ‘1’ and PD4 at ‘0’.
15
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P1
RESET
100kΩ
RUN
10nF
1kΩ
1.0mF
+
GND
+5V
VPP
+
1N914
1N914
47mF
TCAP1 VRH
VDD
IRQ
47mF
OSC1
RESET
+
Red LED
470Ω
0.01mF
OSC2
PLMA
4.0 MHz
470Ω
22pF
22pF
PLMB
Green LED
PD3
MC68HC705X32
MCU
PD4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
9600 BD
8-bit
no parity
RS232
Connector
22mF
+
8
5
7
3
2
1
2 x 3KΩ
22mF
+
2
6
MAX
232
13
14
15
1
3
4
5
12
11
VPP6
12 kΩ
4k7Ω
PC7
+
22mF
+
22mF
PD0
PD1
PD2
PD5
PD6
PD7
RDI
TDO
VSS
BC239C
1nF
+
4k7Ω
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
+5V
16
10k Ω
BC309C
1 kΩ
1N5819
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PC6
PC5
PC4
PC3
PC2
PC1
PC0
VPP1
TCAP2
TCMP1
TCMP2
SCLK
NC
VRL
VSS
Figure B-7 RAM load and execute schematic diagram
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B-21
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tCR
Address
PC5 out
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15
tHO
tADR
tDHR
Data
PC6 in
PD4
tHI max
tEXR max
Figure B-8 Parallel RAM loader timing diagram
MC68HC705X32
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B.9
Electrical specifications
B.9.1
Maximum ratings
Table B-7 Maximum ratings
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Rating
Supply voltage(1)
Input voltage
Input voltage
– Bootstrap mode (IRQ pin only)
Operating temperature range
Symbol
VDD
VIN
Value
– 0.5 to +7.0
VSS – 0.5 to VDD + 0.5
Unit
V
V
VIN
VSS – 0.5 to 2VDD + 0.5
V
TA
TL to TH
–40 to +125
°C
Storage temperature range
Current drain per pin(2)
(Excluding VDD, VSS, VDD1 and VSS1)
– Source
– Sink
External oscillator frequency
TSTG
– 65 to +150
°C
ID
IS
25
45
22
mA
mA
MHz
fOSC
(1) All voltages are with respect to VSS.
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either VSS or VDD.
MC68HC05X16
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B-23
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B.9.2
DC electrical characteristics
Table B-8 DC electrical characteristics
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15
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Output voltage
ILOAD = – 10 µA
VOH
ILOAD = +10 µA
VOL
Output high voltage (ILOAD = 0.8mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
VOH
Output high voltage (ILOAD = 1.6mA)
TDO, SCLK, PLMA, PLMB
VOH
Output high voltage (ILOAD = –300µA)
OSC2
VOH
Output low voltage (ILOAD = 1.6mA)
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
VOL
Output low voltage (ILOAD = 1.6mA)
RESET
VOL
Output low voltage (ILOAD = –100µA)
OSC2
VOL
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
VIH
RESET, TCAP1, TCAP2, RDI, CANE, MDS, NWOI
Input low voltage
VIL
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ,
RESET, TCAP1, TCAP2, RDI, CANE, MDS, NWOI
Can comparator IDD (IDD1)(3)(4)(5)
Supply current in DIV2 mode
RUN: CAN active(6)
IDD1
STOP: CAN active
IDD1
(7)
WAIT: CAN asleep
IDD1
STOP: CAN asleep
IDD1
MCU IDD(3)(4)(8)
Supply current in DIV 2 mode
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
MCU IDD(3)(5)(8)
Supply current
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET, SCLK
IIL
Min
Typ(2)
Max
Unit
VDD – 0.1
—
—
—
—
0.1
V
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.2
—
VDD – 0.8
VDD – 0.3
—
0.1
0.4
0.2
0.6
0.2
0.4
0.7VDD
—
VDD
V
VSS
—
0.2VDD
V
—
—
—
—
360
360
32
10
900
900
100
30
µA
µA
µA
µA
—
—
—
—
—
—
—
—
7
2.2
2.4
1.9
1.3
0.7
0.5
90
11.4
3.9
4.4
3.2
2.7
0.9
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
—
—
—
—
—
—
—
3.9
1.2
1.4
1.0
1.1
0.6
0.16
90
7
2.9
3.2
2.6
2
1.75
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
—
±0.2
±1
µA
V
V
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Table B-8 DC electrical characteristics (Continued)
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
Input current
OSC1=VDD (OSC2=VSS)
IFH
Input current
OSC1=VSS (OSC2=VDD)
IFL
Input current
IRQ, TCAP1, TCAP2, RDI,
IIN
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
Ports (as input or output), RESET, TDO, SCLK
COUT
IRQ, TCAP1, TCAP2, OSC1, RDI
CIN
PD0/AN0–PD7/AN7 (A/D off)
CIN
PD0/AN0–PD7/AN7 (A/D on)
CIN
DC injection current(9)
Port A (PA0–PA7)
|IINJ|
Port B (PB0–PB7)
|IINJ|
Min
Typ(2)
Max
Unit
–10
—
—
µA
—
—
+10
—
±0.2
±1
µA
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
—
—
—
—
10
10
mA
mA
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source, refer to Figure 2-6(c); all inputs 0.2 V
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP/WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
(4) fOSC = 8 MHz; fBUS = 4 MHz; fCAN = 4 MHz
(5) fOSC = 4.4 MHz; fBUS = 2.2 MHz; fCAN = 2.2 MHz
(6) These limits are also applicable under the following conditions:
MCU RUN mode/SLOW mode/CAN active
MCU WAIT mode/SLOW mode/CAN active
MCU WAIT mode/CAN active
(7) These limits are also applicable under the following conditions:
MCU WAIT mode/SLOW mode/CAN asleep
(8) These currents are the summation of the MCU current + CAN current (IDD + IDD1)
(9) Current injection is guaranteed but not tested.
Functionality of the MCU is guaranteed during injection of dc current up to the maximum specified level.
The maximum specified current for each port is the sum of the magnitudes of the currents on each side of the
individual port pins.
Some disturbance of the A/D accuracy is possible during an injection event and is dependent on board layout,
power supply decoupling and reference voltage decoupling configurations.
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B-25
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B.9.3
EPROM electrical characteristics
Table B-9 EPROM electrical characteristics
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15
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C, fMCU ≤ 4MHz)
Characteristic
Symbol
Min
EPROM
Absolute maximum voltage
VPP6 max
VDD
Programming voltage
VPP6
14.5
Programming current
IPP6
—
Read voltage(A)
VPP6R
VDD – 0.35
Read voltage(B)
VPP6R
VDD – 0.5
Read current
IPP6R
—
EPROM programming time
tPROG
5
Typ(1)
Max
Unit
—
15
50
—
—
100
—
18
16
64
VDD
VDD
150
20
V
V
mA
V
V
µA
ms
(1) Typical values are at mid point of voltage range and at 25°C only.
(A) FMCU > 2.2 MHz
(B) FMCU ≤ 2.2 MHz
Note:
Use of programming times between 5ms and 20ms will not affect the product
reliability.
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B.9.4
Control timing
Table B-10 Control timing
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
Frequency of operation
Oscillator frequency
fOSC
MCAN module clock frequency
fCAN
MCU bus frequency
fMCU
Cycle time (see Figure 10-1)
tCYC
Crystal oscillator start-up time (see Figure 10-1) tOXOV
Stop recovery start-up time (crystal oscillator)
tILCH
A/D converter stabilization time
tADON
External RESET input pulse width
tRL
Power-on RESET output pulse width
4064 cycle
tPORL
16 cycle
tPORL
Watchdog RESET output pulse width
tDOGL
Watchdog time-out
tDOG
EEPROM byte erase time
tERA
EEPROM byte program time(1)
tPROG
Timer (see Figure B-9)
Resolution(2)
tRESL
Input capture pulse width
tTH, tTL
Input capture pulse period
tTLTL
Interrupt pulse width (edge-triggered)
tILIH
Interrupt pulse period
tILIL
OSC1 pulse width
tOH, tOL
Write/erase endurance(5)(6)
—
Data retention(5)(6)
—
Min
Max
Unit
0
0
0
455
—
3.0
22
11
4
—
100
100
500
—
MHz
MHz
MHz
ns
ms
ms
µs
tCYC
4064
16
1.5
6144
10
10
—
—
—
7168
10
10
4
125
—(3)
125
—(4)
90
10000
10
—
—
—
—
—
—
tCYC
tCYC
tCYC
tCYC
ms
ms
tCYC
ns
tCYC
ns
tCYC
ns
cycles
years
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (tcyc), this is the limiting
factor in determining the timer resolution.
(3) The minimum period tTLTL should not be less than the number of cycle times it takes to
execute the capture interrupt service routine plus 24 tcyc.
(4) The minimum period tILIL should not be less than the number of cycle times it takes to
execute the interrupt service routine plus 21 tcyc.
(5) At a temperature of 85°C.
(6) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate
information.
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure B-9 Timer relationship
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B.9.5
A/D converter characteristics
Table B-11 A/D characteristics
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15
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Parameter
Resolution
Number of bits resolved by the A/D
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
(VRH = VDD and VRL = 0V)
Quantization error
Uncertainty due to converter resolution
Absolute accuracy
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
VRH
Maximum analog reference voltage
VRL
Minimum analog reference voltage
∆VR(1)
Minimum difference between VRH and VRL
Conversion time
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
Zero input reading
Conversion result when VIN = VRL
Full scale reading
Conversion result when VIN = VRH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
b. Internal RC oscillator(2)
Sample/hold capacitance Input capacitance on PD0/AN0–PD7/AN7
Input leakage(3)
Input leakage on A/D pins PD0/AN0–PD7/AN7, VRL, VRH
Min
8
Max
—
Unit
Bit
—
± 0.5
LSB
—
± 0.5
LSB
—
±1
LSB
VRL
VRL
VSS – 0.1
3
VRH
VDD + 0.1
VRH
—
V
V
V
V
—
—
32
32
tCYC
µs
GUARANTEED
00
—
—
FF
Hex
Hex
—
—
—
—
12
12
12
1
tCYC
µs
pF
µA
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at ∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 9-2).
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B.9.6
MCAN bus interface DC electrical characteristics
Table B-12 MCAN bus interface DC electrical characteristics
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(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus input comparator: pins RX0 and RX1
Input voltage
VIN
Common mode range
CMR
Latch-up trigger current(1)
ILT
Input offset voltage
VOFS
Hysteresis
VHYS
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 µA
DVOUT
Output current
IOUT
Latch-up trigger current1
ILT
MCAN bus output driver: pins TX0 and TX1
Source current per pin (VOUT = VDD–1.0V)
Sink current per pin (VOUT = 1.0V)
Latch-up trigger current1
IOH
IOL
ILT
(VDD = 5.0 Vdc ± 2%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
VDD ÷ 2 generator: pin VDDH
Output voltage difference to VDD ÷ 2 for
–100 µA < IOUT < +100 µA
DVOUT
Min
Max
Unit
0.5
1.5
–100
–30
1
VDD +0.5
VDD –1.5
+100
+30
22
V
V
mA
mV
mV
–200
–100
–100
+200
+100
+100
mV
µA
mA
–10
10
–100
—
—
+100
mA
mA
mA
Min
Max
Unit
–180
+180
mV
(1) Maximum DC current should comply with maximum ratings.
B.9.7
MCAN bus interface control timing characteristics
Table B-13 MCAN bus interface control timing characteristics
(4.5V ≤ VDD ≤ 5.5V, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
MCAN bus output driver
Rise and fall time (CLOAD = 100pF)
TRF
MC68HC05X16
Min
Max
Unit
—
25
ns
15
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C
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MC68HC05X32
High speed operation
The following table of electrical characteristics applies only to the MC68HC05X32 operating with
a 4 MHz bus speed. For all other information relating to this device (except ordering information,
which can be found in Section 14), please refer to Appendix A.
C.1
DC electrical characteristics
Table C-1 DC electrical characteristics
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic(1)
Symbol
MCU IDD(3)(4)(5)
Supply current
RUN (SM = 0): CAN active
IDD
RUN (SM = 1): CAN active
IDD
WAIT (SM = 0): CAN active
IDD
WAIT (SM =1): CAN active
IDD
WAIT (SM = 0): CAN asleep
IDD
WAIT (SM = 1): CAN asleep
IDD
STOP: CAN active
IDD
STOP: CAN asleep
IDD
Min
Typ(2)
Max
Unit
—
—
—
—
—
—
—
—
5.8
2.1
2.6
2
1.1
0.6
0.5
90
11
5.5
5.5
5
2.2
1.2
1.5
300
mA
mA
mA
mA
mA
mA
mA
µA
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source, refer to Figure 2-6(c); all inputs 0.2 V
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP/WAIT IDD: all ports configured as inputs; VIL = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with
OSC1 = VDD. WAIT IDD is affected linearly by the OSC2 capacitance.
(4) fOSC = 8 MHz; fBUS = 4 MHz; fCAN = 4 MHz.
(5) These currents are the summation of the MCU current + CAN current (IDD + IDD1).
Note:
The 4MHz bus frequency is achievable only in divide by 2 and divide by 4 modes. It is
not possible in divide by 10 mode.
MC68HC05X16
15
MC68HC05X32 HIGH SPEED OPERATION
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C.2
Control Timing
Table C-2 Control timing
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15
(VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +125°C)
Characteristic
Symbol
Frequency of operation
Oscillator frequency
fOSC
MCAN module clock frequency
fCAN
MCU bus frequency
fMCU
Cycle time (see Figure 10-1)
tCYC
Min
Max
Unit
0
0
0
250
16
4
4
—
MHz
MHz
MHz
ns
MC68HC05X32 HIGH SPEED OPERATION
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GLOSSARY
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This section contains abbreviations and specialist words used in this data
sheet and throughout the industry. Further information on many of the terms
may be gleaned from Motorola’s M68HC11 Reference Manual,
M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx
The digits following the ‘$’ are in hexadecimal format.
%xxxx
The digits following the ‘%’ are in binary format.
A/D, ADC
Analog-to-digital (converter).
Bootstrap mode
In this mode the device automatically loads its internal memory from an
external source on reset and then allows this program to be executed.
Byte
Eight bits.
CAN
Controller area network.
CCR
Condition codes register; an integral part of the CPU.
CERQUAD
A ceramic package type, principally used for EPROM and high temperature
devices.
Clear
‘0’ — the logic zero state; the opposite of ‘set’.
CMOS
Complementary metal oxide semiconductor. A semiconductor technology
chosen for its low power consumption and good noise immunity.
COP
Computer operating properly. aka ‘watchdog’. This circuit is used to detect
device runaway and provide a means for restoring correct operation.
CPU
Central processing unit.
D/A, DAC
Digital-to-analog (converter).
EEPROM
Electrically erasable programmable read only memory. aka ‘EEROM’.
EPROM
Erasable programmable read only memory. This type of memory requires
exposure to ultra-violet wavelengths in order to erase previous data. aka
‘PROM’.
ESD
Electrostatic discharge.
MC68HC05X16
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Expanded mode
In this mode the internal address and data bus lines are connected to
external pins. This enables the device to be used in much more complex
systems, where there is a need for external memory for example.
EVS
Evaluation system. One of the range of platforms provided by Motorola for
evaluation and emulation of their devices.
HCMOS
High-density complementary metal oxide semiconductor. A semiconductor
technology chosen for its low power consumption and good noise immunity.
I/O
Input/output; used to describe a bidirectional pin or function.
Input capture
(IC) This is a function provided by the timing system, whereby an external
event is ‘captured’ by storing the value of a counter at the instant the event
is detected.
Interrupt
This refers to an asynchronous external event and the handling of it by the
MCU. The external event is detected by the MCU and causes a
predetermined action to occur.
IRQ
Interrupt request. The overline indicates that this is an active-low signal
format.
K byte
A kilo-byte (of memory); 1024 bytes.
LCD
Liquid crystal display.
LSB
Least significant byte.
M68HC05
Motorola’s family of 8-bit MCUs.
MCU
Microcontroller unit.
MI BUS
Motorola interconnect bus. A single wire, medium speed serial
communications protocol.
MSB
Most significant byte.
Nibble
Half a byte; four bits.
NRZ
Non-return to zero.
Opcode
The opcode is a byte which identifies the particular instruction and operating
mode to the CPU.
Operand
The operand is a byte containing information the CPU needs to execute a
particular instruction.
Output compare
(OC) This is a function provided by the timing system, whereby an external
event is generated when an internal counter value matches a predefined
value.
PLCC
Plastic leaded chip carrier package.
PLL
Phase-locked loop circuit. This provides a method of frequency
multiplication, to enable the use of a low frequency crystal in a high
frequency circuit.
GLOSSARY
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Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
permanently connected to either ground or VDD.
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PWM
Pulse width modulation. This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.
QFP
Quad flat pack package.
RAM
Random access memory. Fast read and write, but contents are lost when
the power is removed.
RFI
Radio frequency interference.
RTI
Real-time interrupt.
ROM
Read-only memory. This type of memory is programmed during device
manufacture and cannot subsequently be altered.
RS-232C
A standard serial communications protocol.
SAR
Successive approximation register.
SCI
Serial communications interface.
Set
‘1’ — the logic one state; the opposite of ‘clear’.
Silicon glen
An area in the central belt of Scotland, so called because of the
concentration of semiconductor manufacturers and users found there.
Single chip mode
In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.
SPI
Serial peripheral interface.
Test mode
This mode is intended for factory testing.
TTL
Transistor-transistor logic.
UART
Universal asynchronous receiver transmitter.
VCO
Voltage controlled oscillator.
Watchdog
see ‘COP’.
Wired-OR
A means of connecting outputs together such that the resulting composite
output state is the logical OR of the state of the individual outputs.
Word
Two bytes; 16 bits.
XIRQ
Non-maskable interrupt request. The overline indicates that this has an
active-low signal format.
MC68HC05X16
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THIS PAGE LEFT BLANK INTENTIONALLY
GLOSSARY
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INDEX
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In this index numeric entries are placed first; page references in italics indicate that the reference
is to a figure.
64-pin QFP mechanical drawing 13-2
64-pin QFP pinout 13-1
A
A – accumulator 11-1
A/D converter
ADSTAT 4-5
block diagram 9-2
clock selection 9-4
AC7-AC0 bits in CACC 5-13
ADDATA – A/D result data register 9-3
addressing modes 11-11 11-13
ADON bit in ADSTAT 4-5 9-5
ADRC bit in ADSTAT 9-4
ADSTAT – A/D status/control register 4-5 9-4
ADON – A/D converter on bit 4-5 9-5
ADRC – A/D RC oscillator control bit 9-4
CH3-CH0 – A/D channel selection bits 9-5
COCO – continuous conversion bit 9-4
alternate counter register 6-3
AM0-AM7 bits in CACM 5-14
AT bit in CCOM 5-9
–
,
,
,
B
BAUD – baud rate register 7-18
SCP1, SCP0 – serial prescaler select bits 7-18
SCR2, SCR1, SCR0 – SCI rate select bits 7-19
SCT2, SCT1, SCT0 – SCI rate select bits 7-18
baud rate selection 7-20
biphase mode 5-18
bit set/clear addressing mode 11-13
bit test and branch addressing mode 11-13
bit time calculation 5-17
block diagrams
A/D converter 9-2
COP watchdog system 10-4
MC68HC05X16 1-4
MC68HC05X32 A-2
MC68HC705X32 B-3
MC68HC05X16
MCAN module 5-1
PLM system 8-1
programmable timer 6-2
SCI 7-2
slow mode divider 2-10
BRP5-BRP0 bits in CBT0 5-15
BS bit in CSTAT 5-10
C
CACC – MCAN acceptance code register 5-13
AC7-AC0 – acceptance code bits 5-13
CACM – MCAN acceptance mask register 5-14
AM0-AM7 – acceptance mask bits 5-14
CAF bit in EEPROM control B-8
CAN – see MCAN
CANE B-2
C-bit in CCR 11-3
CBT0 – MCAN bus timing register 0 5-14
BRP5-BRP0 – baud rate prescalar bits 5-15
SJW1, SJW0 – synchronization jump width bits 5-14
CBT1 – MCAN bus timing register 1 5-16
SAMP – sampling bit 5-16
TSEG22-TSEG10 – time segment bits 5-16
CCNTRL – MCAN control register 5-6
EIE – error interrupt enable bit 5-6
MODE – undefined mode bit 5-6
OIE – overrun interrupt enable bit 5-6
RIE – receive interrupt enable bit 5-7
RR – reset request bit 5-7
SPD – speed mode bit 5-6
TIE – transmit interrupt enable bit 5-6
CCOM – MCAN command register 5-7
AT – abort transmission bit 5-9
COMPSEL – comparator selector bit 5-8
COS – clear overrun status bit 5-9
RRB – release receive buffer bit 5-9
RX0, RX1 – receive pin bits 5-8
SLEEP – go to sleep bit 5-8
TR – transmission request bit 5-9
CCR – condition code register 11-2
ceramic resonator 2-13
CH3-CH0 bits in ADSTAT 9-5
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CINT – MCAN interrupt register 5-12
EIF – error interrupt flag 5-12
OIF – overrun interrupt flag 5-12
RIF – receive interrupt flag 5-13
TIF – transmit interrupt flag 5-12
WIF – wake-up interrupt flag 5-12
CIRQ 10-11
clocks – see oscillator clock
COCNTRL – MCAN output control register 5-18
OCM1, OCM0 – output control mode bits 5-18
COCO bit in ADSTAT 9-4
COMPSEL bit in CCOM 5-8
COP 10-3
block diagram 10-4
COS bit in CCOM 5-9
counter 6-1
alternate counter register 6-3
counter register 6-3
CPHA bit in SCCR1 7-12
CPOL bit in SCCR1 7-12
CPU
A – accumulator 11-1
addressing modes 11-11 11-13
CCR – condition code register 11-2
instruction set 11-3 11-10
PC – program counter 11-2
programming model 11-1
SP – stack pointer 11-2
stacking order 11-2
X – index register 11-2
crystal 2-13
CSTAT – MCAN status register 5-10
BS – bus status bit 5-10
DO – data overrun bit 5-11
ES – error status bit 5-10
RBS – receive buffer status bit 5-11
RS – receive status bit 5-10
TBA – transmit buffer access bit 5-11
TCS – transmission complete status bit 5-11
TS – transmit status bit 5-10
–
,
EE1P bit in OPTR 3-8 B-11
EEPROM
erase operation 3-6
programming operation 3-7
read operation 3-6
EEPROM control register 3-4 B-8
CAF – MCAN asleep flag B-8
E1ERA – erase/programming bit 3-5
E1LAT – programming latch enable bit 3-5
E1PGM – charge pump enable/disable bit 3-5
E6LAT – EPROM program latch enable bit B-9
E6PGM – EPROM program enable bit B-9
ECLK – external clock option bit 3-5 4-3
WOIE – wired-OR interrupt enable bit B-8
EIE bit in CCNTRL 5-6
EIF bit in CINT 5-12
EPROM
MOR B-12
program operation B-8
read operation B-7
ES bit in CSTAT 5-10
extended addressing mode 11-12
external clock 2-13
,
,
–
F
FE bit in SCSR 7-17
flow charts
interrupts 10-8
self check mode (MC68HC05X16) 2-2
STOP and WAIT 2-9
FOLV2, FOLV1 bits in TCR 6-5
H
H-bit in CCR 11-2
I
D
DB7-DB0 bits in TDS 5-21
direct addressing mode 11-11
DIV2, DIV8 bits in MOR B-12
DLC3-DLC0 bits in TRTDL 5-20
DO bit in CSTAT 5-11
E
E1ERA bit in EEPROM control 3-5
E1LAT bit in EEPROM control 3-5
E1PGM bit in EEPROM control 3-5
E6LAT bit in EEPROM control B-9
E6PGM bit in EEPROM control B-9
ECLK bit in EEPROM control 3-5 4-3
,
I-bit in CCR 11-3
ICF1, ICF2 bits in TSR 6-6
ICIE bit in TCR 6-4
ICR1, ICR2 – input capture registers 6-7
ID10-ID3 bits in TBI 5-20
ID2-ID0 bits in TRTDL 5-20
IDLE bit in SCSR 7-16
IEDG1 bit in TCR 6-5
ILIE bit in SCCR2 7-14
immediate addressing mode 11-11
indexed addressing modes 11-12
inherent addressing mode 11-11
input capture 6-7
instruction set 11-3 11-10
tables of instructions 11-5 11-10
INTE bit in Miscellaneous 3-11 10-10
interrupts
–
–
,
INDEX
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CIRQ 10-11
flow chart 10-8
IRQ 10-11
maskable 10-9
nonmaskable 10-9
priorities 10-9
programmable timer 10-12
SCI 10-12
SWI 10-9
WOI 10-11
INTP, INTN bits in Miscellaneous 3-11 10-10
IRQ 2-11 10-11
,
,
EEPROM (MC68HC05X16) 3-4
EPROM (MC68HC705X32) B-7
MCAN memory map 3-3 5-5
memory map (MC68HC05X16) 3-2
memory map (MC68HC05X32) A-3
memory map (MC68HC705X32) B-5
RAM (MC68HC05X16) 3-1
ROM (MC68HC05X16) 3-1
self-check ROM (MC68HC05X16) 3-3
Miscellaneous register 2-10 3-11 8-3
INTE – external interrupt enable bit 3-11 10-10
INTP, INTN – external interrupt sensitivity bits 10-10
INTP, INTN – interrupt sensitivity bits 3-11
POR – power-on reset bit 3-11 10-2
SFA, SFB – slow or fast mode selection bits 3-11 8-3
SM – slow mode selection bit 3-12 8-3
SM slow mode selection bit 2-10
WDOG – watchdog enable/disable bit 3-12 10-4
MODE bit in CCNTRL 5-6
modes of operation
jump to any address 2-3
low power modes 2-3
self-check mode 2-2
serial RAM loader 2-3
single-chip mode 2-1
MOR – mask option register B-12
DIV2, DIV8 – clock divide ratio select bits B-12
PBPD, PCPD – port B and C pull-down bits B-13
RTIM – reset time bit B-12
RWAT – watchdog after reset bit B-12
WOI – wired-OR interrupt enable bit B-12
WWAT – watchdog during WAIT bit B-13
,
,
,
,
,
L
LBCL bit in SCCR1 7-13
low power modes 2-3
SLOW 2-8
WAIT 2-7
,
M
M bit in SCCR1 7-11
mask options
MC68HC05X16 1-3
MC68HC05X16
block diagram 1-4
mask options 1-3
memory map 3-2
register outline 3-9
MC68HC05X32
block diagram A-2
memory map A-3
register outline A-5
MC68HC705X32
block diagram B-3
memory map B-5
register outline B-4
MCAN
biphase mode 5-18
block diagram 5-1
CANE B-2
electrical characteristics 12-6 A-11 B-29
memory map 3-3 5-5
normal mode 1 5-19
normal mode 2 5-19
oscillator block diagram 5-15
output control bits 5-19
RBF 5-4
register outline 3-10
single wire operation 5-24
SLEEP 5-24
TBF 5-4
MDS 2-12
mechanical drawings
64-pin QFP 13-2
memory
,
MC68HC05X16
,
,
,
,
N
N-bit in CCR 11-3
NF bit in SCSR 7-17
normal mode 1 5-19
normal mode 2 5-19
NWOI 2-16
O
OCIE bit in TCR 6-4
OCM1, OCM0 bits in COCNTRL 5-18
OCR1, OCR2 – output compare registers 6-9
OIE bit in CCNTRL 5-6
OIF bit in CINT 5-12
OLV2, OLV1 bits in TCR 6-5
OPTR – EEPROM options register B-11
EE1P – EEPROM protect bit B-11
SEC – secure bit B-11
OPTR – options register 3-7
EE1P – EEPROM protect bit 3-8
SEC – security bit 3-8
OR bit in SCSR 7-17
order numbers 14-1
INDEX
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OSC1, OSC2 2-13
oscillator clock
ceramic resonator 2-13
crystal 2-13
external clock 2-13
OSC1, OSC2 2-13
output compare 6-9
ICR1, ICR2 6-7
OCR1, OCR2 6-9
PLM 6-11
software force compare 6-11
TCR 6-4
timing diagrams 6-12
TSR 6-6
pulse length modulation – see PLM
P
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PA0–7, PB0–7, PC0–7 2-16
PBPD, PCPD bits in MOR B-13
PC – program counter 11-2
PD0/AN0–PD7/AN7 2-16
pinouts
64-pin QFP 13-1
pins
CANE B-2
IRQ 2-11
MDS 2-12
NWOI 2-16
OSC1, OSC2 2-13
PA0–7, PB0–7, PC0–7 2-16
PD0/AN0–PD7/AN7 2-16
PLMA, PLMB 2-15
RDI 2-12 7-6
RESET 2-11 10-3
RX0, RX1 2-17
SCLK 2-13
TCAP1, TCAP2 2-12
TCMP1, TCMP2 2-12
TDO 2-12
TX0, TX1 2-17
VDD, VSS 2-11
VDD1, VSS1 2-17
VDDH 2-17
VPP1 2-16
VPP6 B-2
VRH 2-16
VRL 2-16
PLM 6-11
block diagram 8-1
clock selection 8-4
Miscellaneous register 8-3
PLMA, PLMB – pulse length modulation registers 8-2
PLMA, PLMB pins 2-15
POR bit in Miscellaneous 3-11 10-2
ports
data direction registers 4-6
data registers 4-4
logic levels 4-7
port A 4-2
port B 4-2
port C 4-3
port D 4-4
power-on reset 10-2
programmable timer
block diagram 6-2
counter 6-1
,
,
,
R
R8 bit in SCCR1 7-11
RBF – receive buffer 5-4
RBI – receive buffer identifier register 5-21
RBS bit in CSTAT 5-11
RDI – receive data in 2-12 7-6
RDRF bit in SCSR 7-16
RDS – receive data segment registers 5-22
RE bit in SCCR2 7-15
receiver wake-up 7-5
register outline
MC68HC05X16 3-9
MC68HC05X32 A-5
MC68HC705X32 B-4
MCAN 3-10
relative addressing mode 11-13
RESET 2-11 10-3
resets
COP 10-3
power-on 10-2
RESET pin 2-11 10-3
timing diagram 10-1
RIE bit in CCNTRL 5-7
RIE bit in SCCR2 7-14
RIF bit in CINT 5-13
ROM verification units 14-2
RR bit in CCNTRL 5-7
RRB bit in CCOM 5-9
RRTDL – transmission request/DLC register 5-22
RS bit in CSTAT 5-10
RTIM bit in MOR B-12
RTR bit in TRTDL 5-20
RVU 14-2
RWAT bit in MOR B-12
RWU bit in SCCR2 7-15
RX0, RX1 bits in CCOM 5-8
RX0, RX1 pins 2-17
,
,
,
S
SAMP bit in CBT1 5-16
SBK bit in SCCR2 7-15
SCCR1 – serial communications control register 1 7-10
CPHA – clock phase 7-12
CPOL – clock polarity bit 7-12
LBCL – last bit clock 7-13
M – mode (select character format) 7-11
INDEX
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R8 – receive data bit 8 7-11
T8 – transmit data bit 8 7-11
WAKE – wake-up mode select bit 7-11
SCCR2 – serial communications control register 2 7-14
ILIE – idle line interrupt enable 7-14
RE – receiver enable 7-15
RIE – receiver interrupt enable 7-14
RWU – receiver wake-up 7-15
SBK – send break 7-15
TCIE – transmit complete interrupt enable 7-14
TE – transmitter enable 7-14
TIE – transmit interrupt enable 7-14
SCDR – serial communications data register 7-10
SCI
baud rate selection 7-20
block diagram 7-2
data format 7-5
receiver wake-up 7-5
start bit detection 7-6
timing diagrams 7-12
SCLK 2-13
SCP1, SCP0 bits in BAUD 7-18
SCR2, SCR1, SCR0 bits in BAUD 7-19
SCSR – serial communications status register 7-16
FE – framing error flag 7-17
IDLE – idle line detected flag 7-16
NF – noise error flag 7-17
OR – overrun error flag 7-17
RDRF – receive data register full flag 7-16
TC – transmit complete flag 7-16
TDRE – transmit data register empty flag 7-16
SCT2, SCT1, SCT0 bits in BAUD 7-18
SEC bit in OPTR 3-8 B-11
self-check mode 2-2
SFA, SFB bits in Miscellaneous 3-11 8-3
single-chip mode 2-1
SJW1, SJW0 bits in CBT0 5-14
SLEEP 5-24
SLEEP bit in CCOM 5-8
SLOW 2-8
SM bit in Miscellaneous 2-10 3-12 8-3
software force compare 6-11
SP – stack pointer 11-2
SPD bit in CCNTRL 5-6
,
,
,
,
T
T8 bit in SCCR1 7-11
TBA bit in CSTAT 5-11
TBF – transmit buffer 5-4
TBI – transmit buffer identifier register 5-20
ID10-ID3 – identifier bits 5-20
TC bit in SCSR 7-16
TCAP1, TCAP2 2-12
TCIE bit in SCCR2 7-14
TCMP1, TCMP2 2-12
TCR – timer control register 6-4
FOLV2, FOLV1 – force output compare bits 6-5
ICIE – input capture interrupt enable 6-4
MC68HC05X16
IEDG1 – input edge bit 6-5
OCIE – output compare interrupt enable 6-4
OLV2, OLV1 – output level bits 6-5
TOIE – timer overflow interrupt enable 6-4
TCS bit in CSTAT 5-11
TDO
SCI transmit data out 7-8
TDO – transmit data out 2-12
TDRE bit in SCSR 7-16
TDS – transmit data segment registers 5-21
DB7-DB0 – data bits 5-21
TE bit in SCCR2 7-14
TIE bit in CCNTRL 5-6
TIE bit in SCCR2 7-14
TIF bit in CINT 5-12
timing diagrams
ECLK 4-3
programmable timer 6-12
reset 10-1
SCI data clock 7-12
TOF bit in TSR 6-6
TOIE bit in TCR 6-4
TR bit in CCOM 5-9
TRTDL – transmission request/DLC register 5-20
DLC3-DLC0 – data length code bits 5-20
ID2-ID0 – identifier bits 5-20
RTR – remote transmission request 5-20
TS bit in CSTAT 5-10
TSEG22-TSEG10 bits in CBT1 5-16
TSR – timer status register 6-6
ICF1, ICF2 – input capture flags 6-6
OCF1, OCF2 – output compare flags 6-6
TOF – timer overflow status flag 6-6
TX0, TX1 2-17
V
VDD, VSS 2-11
VDD1, VSS1 2-17
VDDH 2-17
VPP1 2-16
VPP6 B-2
VRH 2-16
VRL 2-16
W
WAIT 2-7
WAKE bit in SCCR1 7-11
watchdog – see COP
WDOG bit in Miscellaneous 3-12 10-4
WIF bit in CINT 5-12
wired-OR interrupt – see WOI
WOI 10-11
WOI bit in MOR B-12
WOIE bit in EEPROM control B-8
WWAT bit in MOR B-13
,
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INTRODUCTION
1
MODES OF OPERATION AND PIN DESCRIPTIONS
2
MEMORY AND REGISTERS
3
INPUT/OUTPUT PORTS
4
MOTOROLA CAN MODULE (MCAN)
5
PROGRAMMABLE TIMER
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SERIAL COMMUNICATIONS INTERFACE
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PULSE LENGTH D/A CONVERTERS
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ANALOG TO DIGITAL CONVERTER
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RESETS AND INTERRUPTS
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ELECTRICAL SPECIFICATIONS
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1
INTRODUCTION
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MODES OF OPERATION AND PIN DESCRIPTIONS
3
MEMORY AND REGISTERS
4
INPUT/OUTPUT PORTS
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MOTOROLA CAN MODULE (MCAN)
6
PROGRAMMABLE TIMER
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SERIAL COMMUNICATIONS INTERFACE
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PULSE LENGTH D/A CONVERTERS
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ANALOG TO DIGITAL CONVERTER
10
RESETS AND INTERRUPTS
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CPU CORE AND INSTRUCTION SET
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ELECTRICAL SPECIFICATIONS
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MECHANICAL DATA
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ORDERING INFORMATION
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APPENDICES
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