Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
SECTION 6
STANDBY RAM MODULE
The standby RAM (SRAM) module consists of a control register block and a 4-Kbyte
array of fast (two bus cycle) static RAM. The SRAM is especially useful for system
stacks and variable storage. The SRAM can be mapped to any address that is a
multiple of the array size so long as SRAM boundaries do not overlap the module control registers (overlap makes the registers inaccessible). Data can be read/written in
bytes, words or long words. SRAM is powered by VDD in normal operation. During
power-down, SRAM contents can be maintained by power from the VSTBY input.
Power switching between sources is automatic.
6.1 SRAM Register Block
There are four SRAM control registers: the RAM module configuration register (RAMMCR), the RAM test register (RAMTST), and the RAM array base address registers
(RAMBAH/RAMBAL). To protect these registers from accidental modification, they are
always mapped to supervisor data space.
The module mapping bit (MM) in the SIM configuration register defines the most significant bit (ADDR23) of the IMB address for each MC68336/376 module. Refer to
5.2.1 Module Mapping for information on how the state of MM affects the system.
The SRAM control register consists of eight bytes, but not all locations are
implemented. Unimplemented register addresses are read as zeros, and writes have
no effect. Refer to D.3 Standby RAM Module for register block address map and register bit/field definitions.
6.2 SRAM Array Address Mapping
Base address registers RAMBAH and RAMBAL are used to specify the SRAM array
base address in the memory map. RAMBAH and RAMBAL can only be written while
the SRAM is in low-power stop mode (RAMMCR STOP = 1) and the base address lock
(RAMMCR RLCK = 0) is disabled. RLCK can be written once only to a value of one.
This prevents accidental remapping of the array.
6.3 SRAM Array Address Space Type
RASP[1:0] in RAMMCR determine the SRAM array address space type. The SRAM
module can respond to both program and data space accesses or to program space
accesses only. This allows code to be executed from RAM, and permits use of program counter relative addressing mode for operand fetches from the array.
In addition, RASP[1:0] specify whether access to the SRAM module can be made in
supervisor mode only, or in either user or supervisor mode. If supervisor-only access
is specified, accesses in user mode are ignored by the SRAM control logic and can be
decoded externally.
MC68336/376
USER’S MANUAL
STANDBY RAM MODULE
Rev. 15 Oct 2000
For More Information
On This Product,
Go to: www.freescale.com
MOTOROLA
6-1
Freescale Semiconductor, Inc.
Table 6-1 shows RASP[1:0] field encodings.
Table 6-1 SRAM Array Address Space Type
RASP[1:0]
Space
00
Unrestricted program and data
01
Unrestricted program
10
Supervisor program and data
11
Supervisor program
Freescale Semiconductor, Inc...
Refer to 4.5 Addressing Modes for more information on addressing modes. Refer to
5.5.1.7 Function Codes for more information concerning address space types and
program/data space access.
6.4 Normal Access
The array can be accessed by byte, word, or long word. A byte or aligned word access
takes one bus cycle or two system clocks. A long word access requires two bus cycles.
Misaligned accesses are not permitted by the CPU32 and will result in an address
error exception. Refer to 5.6 Bus Operation for more information concerning access
times.
6.5 Standby and Low-Power Stop Operation
Standby and low-power modes should not be confused. Standby mode maintains the
RAM array when the main MCU power supply is turned off. Low-power stop mode
allows the central processor unit to control MCU power consumption.
Relative voltage levels of the MCU VDD and VSTBY pins determine whether the SRAM
is in standby mode. SRAM circuitry switches to the standby power source when V DD
drops below specified limits. If specified standby supply voltage levels are maintained
during the transition, there is no loss of memory when switching occurs. The RAM
array cannot be accessed while the SRAM module is powered from VSTBY. If standby
operation is not desired, connect the V STBY pin to VSS.
ISB (SRAM standby current) values may vary while VDD transitions occur. Refer to
APPENDIX A ELECTRICAL CHARACTERISTICS for standby switching and power
consumption specifications.
Setting the STOP bit in RAMMCR switches the SRAM module to low-power stop
mode. In low-power stop mode, the array retains its contents, but cannot be read or
written by the CPU32. STOP can be written only when the CPU32 is operating in
supervisor mode.
The SRAM module will switch to standby mode while it is in low-power stop mode,
provided the operating constraints discussed above are met.
MC68336/376
USER’S MANUAL
STANDBY RAM MODULE
Rev. 15 Oct 2000
For More Information
On This Product,
Go to: www.freescale.com
MOTOROLA
6-2
Freescale Semiconductor, Inc.
6.6 Reset
Reset places the SRAM in low-power stop mode, enables program space access, and
clears the base address registers and the register lock bit. These actions make it possible to write a new base address into the registers.
Freescale Semiconductor, Inc...
When a synchronous reset occurs while a byte or word SRAM access is in progress,
the access is completed. If reset occurs during the first word access of a long-word
operation, only the first word access is completed. If reset occurs during the second
word access of a long-word operation, the entire access is completed. Data being read
from or written to the RAM may be corrupted by asynchronous reset. Refer to 5.7
Reset for more information about resets.
MC68336/376
USER’S MANUAL
STANDBY RAM MODULE
Rev. 15 Oct 2000
For More Information
On This Product,
Go to: www.freescale.com
MOTOROLA
6-3
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
MC68336/376
USER’S MANUAL
STANDBY RAM MODULE
Rev. 15 Oct 2000
For More Information
On This Product,
Go to: www.freescale.com
MOTOROLA
6-4
">
