AMS AS3605 Datasheet
PDF
Document
Advertentie
Advertentie
austriamicrosystems AG is now ams AG The technical content of this austriamicrosystems datasheet is still valid. Contact information: Headquarters: ams AG Tobelbaderstrasse 30 8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 e-Mail: [email protected] Please visit our website at www.ams.com Data Sheet AS3605 Multi-Standard Power Management Unit The device incorporates low dropout regulators (LDOs), a DC/DC converter, a complete battery charger, and an audio power amplifier on one die. am lc s on A te G nt st il The linear analog LDOs feature extremely high performance regarding: Automatic Trickle Charging Programmable Constant Current Charging Programmable Constant Voltage Charging Safety Functions (Low Battery Shutdown) Over- and Under-Temperature Charge Disable Operation without Battery Can Regulate the Current Through the Battery or from the Charger - Charger Input Overvoltage Protection (6V) - Shutdown even with Connected Charger - Charger Resume Operation - Charger Interrupts (Inserted, Removed, Overvoltage, Resume) - No-Battery Detection Momentary Power Loss Detection al id The AS3605 is a highly-integrated CMOS power management device designed specifically for portable devices such as mobile phones, PDAs, CD players, digital cameras and other devices powered by 1-cell Li-Ion battery. It can be used for any mobile phone handset standards such as CDMA, WCDMA, GSM, GPRS, EDGE, UTMS and other Japanese or American standards. Battery Charger - lv 1 General Description - Noise – typ 30µVRMS from 100Hz to 100kHz - Line/Load Regulation – < 1mV static, < 10mV transient - Power Supply Rejection – > 70dB @ 1kHz The integrated Step Down DC/DC Converter does not require an external Schottky diode yet provides very high efficiency (up to 95%) throughout the whole operating range. 5 programmable current sources are included to control LED brightness. A low-distortion audio power amplifier (1 Watt @ 8Ω) supports handsfree operation and HiFi ring-tones. - Battery Supply Short-Interruption Detection (<200ms); (e.g., due to a dropped phone) Five Programmable Current Sources (3x40mA, 2x160mA) - 8-Bit (0.625 to 160mA) - Buzzer, Vibrator, LEDs Charge Pump (1:1 and 1:2 mode) 60mA @3.3V VBAT OTP programmable boot sequence The device also features a battery charger including automatic trickle charging, and programmable constant voltage and current charging. Wide Battery Supply Range 3.0 to 5.5V The AS3605 is controlled via a serial interface and integrates all necessary system specific functions such as Reset, Watchdog, and Power-On Detection. On-Chip Bandgap Tuning for High Accuracy (±1%) ca Output voltages and start-up timings can be programmed via the internal OTP. 2 Key Features ni 8 Programmable High Performance LDOs ch - Four RF Low-Noise LDOs (1.8 to 3.35V, 150mA) - Two Analog Low-Noise LDOs (1.8 to 3.35V, 250mA) - One SIM Low-Power LDO (1.8 or 3.0V, 20mA) - One Low-Power LDO (2.5V, 10mA) Programmable High Efficiency DC/DC Converter Te - Step Down: 0.6 to 3.4V, up to 500mA with 2.2MHz Stereo Audio Power Amplifier Three Programmable General Purpose I/O Pins Integrated Programmable Watchdog (16 to 4080ms) Programmable Reset (0 to 70ms) Shutdown Current typ <10µA (2.5V Always On) Overcurrent and Thermal Protection 1.5 Watt Power Dissipation @TA = 70ºC Packaging QFN40 5x5mm, 0.4mm pitch 3 Application Multi-standard power management for mobile phones, PDAs, and any other 1-cell Li+ powered devices. - 0.5W @ 4Ω – Stereo; 1W @ 8Ω – Bridged - Digital Volume Control, 3dB Steps - Click- and Pop-Less Start-Up and Power-Down www.austriamicrosystems.com 1.00 1 - 73 AS3605 1v2 Data Sheet - A p p l i c a t i o n Figure 1. AS3605 Block Diagram. Option: Audio Amplifier In Differential Mode, Step Down DC/DC Converter as Pre-Regulator for Digital LDOs White LEDs C2 470nF Buzzer CURR5 CURR4 CURR3 23 22 21 Vibrator CURR2 CURR1 CAPP CAPN 24 25 17 16 VBAT Current Sink 3x(0.15-40mA) VBAT_3 AGND AIN_R C24 100nF AOUT_R VCHARGER C26 10µ VGATE AS3605 Power Management Unit 27 20 RF LDO Low Noise 1.8-3.35V 150mA 1W Audio Amplifier 19 RF LDO Low Noise 1.8-3.35V 150mA 28 RF LDO Low Noise 1.8-3.35V 150mA 29 RF LDO Low Noise 1.8-3.35V 150mA 37 Internal LDO 2.5V, 10mA Battery Charger R4 100mΩ VANA_2 C6 1µF 31 VRF_1 C8 1µF 30 VBAT_4 32 VRF_2 33 C9 1µF C10 1µF VRF_3 C11 1µF 38 LiIon ISENSP 11 am lc s on A te G nt st il AIN_L C23 100nF C25 100nF Q1 PBSS301PD VBAT_1 C5 1µF AOUT_L DC Charger Adapter ≤15V VANA_1 C4 1µF 10 Analog LDO Low Noise 1.8-3.35V 250mA ≥8Ω LS1 12 Analog LDO Low Noise 1.8-3.35V 250mA 26 V5_6 C3 1µF Current Sink 2x(0.6-160mA) C22 1µF Audio In 18 lv VBAT Charge Pump 5.2V 60mA al id V5_6 34 VRF_4 C13 1µF 3 V2_5 15 GPIO1 14 GPIO2 13 GPIO3 39 VBAT_2 C7 1µF VANA_1 36 GPIO ISENSN VBAT All caps on VBAT ≥10µF total C27 35 ca POR Li-Ion GND_SENSE 5 ON 6 ni V2_5 or VBAT Serial Interface SDA 8 Te ch SCK 7 C16 1µF Feedback Digital Logic and References Step Down DC/DC Converter 0.6-3.4V, 500mA I/F Boot OTP GND_PAD 9 XRES VANA_1 R5 100kΩ 4 CREF 1 VBUCK 40 LX L2 2.2µH SIM LDO 1.8/3.0V, 20mA 2 VSIM C18 10µF C19 100nF Pad C29 100nF RESET Note: Refer to Table 33 for specifications of external components. www.austriamicrosystems.com 1.00 2 - 73 AS3605 1v2 Data Sheet - A p p l i c a t i o n Figure 2. AS3605 Block Diagram. Option: Audio Amplifier in Stereo Single-Ended Mode, Digital LDOs Separated from Step Down DC/DC Converter White LEDs C2 470nF Buzzer CURR5 CURR4 CURR3 23 22 21 Vibrator CURR2 CURR1 CAPP CAPN 24 25 17 16 VBAT Current Sink 3x(0.15-40mA) VBAT_3 C23 100nF AIN_L IN_L C25 100nF AGND AIN_R IN_R C24 100nF AOUT_R DC Charger Adapter ≤15V VCHARGER C26 10µ Q1 PBSS301PD VGATE AS3605 Power Management Unit 27 20 RF LDO Low Noise 1.8-3.35V 150mA 1W Audio Amplifier 19 RF LDO Low Noise 1.8-3.35V 150mA 28 RF LDO Low Noise 1.8-3.35V 150mA 29 RF LDO Low Noise 1.8-3.35V 150mA 37 Internal LDO 2.5V, 10mA Battery Charger R4 100mΩ VANA_2 C6 1µF 31 VRF_1 C8 1µF 30 VBAT_4 32 VRF_2 33 C9 1µF C10 1µF VRF_3 C11 1µF 38 LiIon ISENSP 11 am lc s on A te G nt st il C21 ≥100µF VBAT_1 C5 1µF AOUT_L ≥4Ω LS3 VANA_1 C4 1µF 10 Analog LDO Low Noise 1.8-3.35V 250mA ≥4Ω LS2 12 Analog LDO Low Noise 1.8-3.35V 250mA 26 V5_6 C3 1µF Current Sink 2x(0.6-160mA) C22 1µF C20 ≥100µF 18 lv VBAT Charge Pump 5.2V 60mA al id V5_6 34 VRF_4 C13 1µF 3 V2_5 15 GPIO1 14 GPIO2 13 GPIO3 39 VBAT_2 C7 1µF VANA_1 36 GPIO ISENSN VBAT All caps on VBAT ≥10µF total C27 35 ca POR Li-Ion GND_SENSE 5 ON 6 ni V2_5 or VBAT Serial Interface SDA 8 Te ch SCK 7 C16 1µF Feedback Digital Logic and References Step Down DC/DC Converter 0.6-3.4V, 500mA I/F Boot OTP GND_PAD 9 XRES VANA_1 R5 100kΩ 4 CREF 1 VBUCK 40 LX L2 2.2µH SIM LDO 1.8/3.0V, 20mA 2 VSIM C18 10µF C19 100nF Pad C29 100nF RESET Note: Refer to Table 33 for specifications of external components. www.austriamicrosystems.com 1.00 3 - 73 AS3605 1v2 Data Sheet - C o n t e n t s Contents 1 2 Key Features............................................................................................................................................................................. 1 3 Application ................................................................................................................................................................................ 1 4 Pin Assignments ....................................................................................................................................................................... 6 4.1 Pin Descriptions.................................................................................................................................................................................... 7 al id 1 General Description .................................................................................................................................................................. 5 Absolute Maximum Ratings ...................................................................................................................................................... 9 6 Electrical Characteristics......................................................................................................................................................... 10 7 Detailed Description................................................................................................................................................................ 11 7.1 Battery Charge Controller................................................................................................................................................................... 11 lv 7.1.1 Charge Controller Operating Modes and Building Blocks ......................................................................................................... 12 7.1.2 Charger Registers...................................................................................................................................................................... 13 7.2 Step Down DC/DC Converter............................................................................................................................................................. Low-Ripple, Low-Noise Operation ............................................................................................................................................. High-Efficiency Operation (Default Setting) ............................................................................................................................... 100% PMOS ON Mode for Low Dropout Regulation................................................................................................................. Low Power Mode ....................................................................................................................................................................... Typical Performance Characteristics xxx................................................................................................................................... Step Down DC/DC Converter Registers................................................................................................................................... am lc s on A te G nt st il 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 Low Dropout Regulators..................................................................................................................................................................... 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 RF and Analog Low Dropout Regulators ................................................................................................................................... SIMCard Low Dropout Regulator............................................................................................................................................... Low Power Low Dropout Regulator ........................................................................................................................................... Typical Performance Characteristics ......................................................................................................................................... LDO Registers ........................................................................................................................................................................... 7.4 Charge Pump ..................................................................................................................................................................................... 16 17 18 19 19 19 20 22 22 23 24 25 26 32 7.4.1 Charge Pump Mode Switching .................................................................................................................................................. 32 7.4.2 Charge Pump Registers ............................................................................................................................................................ 33 7.5 General Purpose Input/Output............................................................................................................................................................ ca GPIO Registers.......................................................................................................................................................................... Programmable Frequency Generator ........................................................................................................................................ Programmable Frequency Generator Registers........................................................................................................................ Interrupt Function....................................................................................................................................................................... Interrupt Registers ..................................................................................................................................................................... ni 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 Current Sinks...................................................................................................................................................................................... 36 37 40 40 41 41 42 7.6.1 Current Sink Registers............................................................................................................................................................... 43 ch 7.7 Audio Amplifier ................................................................................................................................................................................... 47 7.7.1 Audio Amplifier Registers .......................................................................................................................................................... 49 8 System Supervisory Functions ............................................................................................................................................... 51 Te 8.1 Reset .................................................................................................................................................................................................. 8.1.1 8.1.2 8.1.3 8.1.4 Reset Conditions ....................................................................................................................................................................... Reset Registers ......................................................................................................................................................................... Reset Cycle ............................................................................................................................................................................... res_con: Reset Control .............................................................................................................................................................. 8.2 Startup ................................................................................................................................................................................................ 51 51 52 53 53 54 8.2.1 Normal Startup........................................................................................................................................................................... 54 www.austriamicrosystems.com 1.00 4 - 73 AS3605 1v2 Data Sheet - C o n t e n t s 8.2.2 Programmable Startup Sequences............................................................................................................................................ 54 8.2.3 Startup from Battery Charger..................................................................................................................................................... 54 8.3 Protection Functions........................................................................................................................................................................... 54 8.3.1 TMP_SV: Temperature Supervision .......................................................................................................................................... 54 8.3.2 Overtemperature Detection ....................................................................................................................................................... 55 8.3.3 Overtemperature Detection Register ......................................................................................................................................... 55 56 al id 8.4 Watchdog Block.................................................................................................................................................................................. 8.4.1 Watchdog Registers .................................................................................................................................................................. 56 8.5 Internal Reference Circuits ................................................................................................................................................................. 58 8.5.1 Internal Reference Registers ..................................................................................................................................................... 58 59 8.7 Boot Sequence Detection................................................................................................................................................................... 59 lv 8.6 Low Power Mode................................................................................................................................................................................ 8.7.1 ON Detection Register............................................................................................................................................................... 59 8.8 Serial Interface ................................................................................................................................................................................... 60 am lc s on A te G nt st il 8.8.1 Digital Input/Output DC/AC Characteristics ............................................................................................................................... 60 8.8.2 SPI Compatible Serial Interface................................................................................................................................................. 61 2 8.8.3 I C Compatible Serial Interface ................................................................................................................................................. 61 65 10 External Parts List................................................................................................................................................................. 68 11 Package Drawings and Markings.......................................................................................................................................... 69 12 Ordering Information............................................................................................................................................................. 72 Te ch ni ca 9 Register Map........................................................................................................................................................................... www.austriamicrosystems.com 1.00 5 - 73 AS3605 1v2 Data Sheet - P i n A s s i g n m e n t s 4 Pin Assignments VCHARGER VGATE ISENSP ISENSN VRF_4 VRF_3 VRF_2 VRF_1 39 38 37 36 35 34 33 32 31 al id VBAT_2 40 lv LX Figure 3. Pin Assignments (Top View) VBUCK 1 30 VBAT_4 VSIM 2 29 V2_5 3 28 AOUT_R CREF 4 27 AOUT_L GND_SENSE 5 26 VBAT_3 ON 6 25 CURR1 SDA 7 24 CURR2 SCK 8 23 CURR5 XRES 9 22 CURR4 VBAT_1 10 21 CURR3 am lc s on A te G nt st il AGND AS3605 QFN 40pin 12 13 14 15 16 17 18 19 20 GPIO3 GPIO2 GPIO1 CAPN CAPP V5_6 AIN_R AIN_L Te ch ni ca 11 VANA_1 Exposed Pad: VSS VANA_2 41 www.austriamicrosystems.com 1.00 6 - 73 AS3605 1v2 Data Sheet - P i n A s s i g n m e n t s 4.1 Pin Descriptions Table 1. Pin Descriptions Pin Name Pin Number Pin Type VBUCK 1 Analog Input Description Sense input of the DC/DC converter. 2 Analog Output V2_5 3 Analog Output Output voltage of low power LDO V2_5; always connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%); do not load this pin during startup. CREF 4 Analog Pin al id VSIM Output voltage of LDO VSIM; if used, connect a ceramic capacitor of 100nF (±20%). Bypass capacitor for the internal voltage reference; always connect a capacitor of 100nF. lv Caution: Do not load this pin. 5 Analog Pin Sensitive GND for Bandgap Voltage Reference. ON 6 Digital Input Input pin to startup the AS3605 (power on); internal pulldown; sense output in test mode. am lc s on A te G nt st il GND_SENSE SDA SCK XRES 7 Digital Input SDA input/output in I C mode. 8 Digital Input SCK input in I C mode. 9 2 2 Digital Input/Output / Open Drain (device can Bidirectional active low RESET pin; add an external pullup resistor. only pulldown this pin) Supply pin for Analog LDOs VANA_1 and VANA_2 as well as the charge pump; can be connected to VBAT or separate supply (3.0-5.5V). VBAT_1 10 Supply Pin VANA_2 11 Analog Output Output voltage of one of Analog LDO VANA_2; if used as LDO, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). VANA_1 12 Analog Pin Output voltage of Analog LDO VANA_1; if used as LDO, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). GPIO3 13 Digital Input/Output General purpose switchable 5V input/output. GPIO2 14 Digital Input/Output General purpose switchable 5V input/output. GPIO1 15 Digital Input/Output General purpose switchable 5V input/output. CAPN 16 Analog Pin Flying capacitor of the Charge Pump; if used, connect a ceramic capacitor of 470nF (±20%) to this pin. 18 Analog Pin Output voltage of the Charge Pump; if used, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). 19 Analog Input Audio Amplifier right-channel input. 20 Analog Input Audio Amplifier left-channel input; sense output in test mode. ch AIN_L Analog Pin ni V5_6 AIN_R 17 ca CAPP Flying capacitor of the Charge Pump; if used connect a ceramic capacitor of 470nF (±20%) to this pin. 21 Analog Input Analog current sink input. CURR4 22 Analog Input Analog current sink input. CURR5 23 Analog Input Analog current sink input. CURR2 24 Analog Input Analog current sink input. CURR1 25 Analog Input Analog current sink input. VBAT_3 26 Supply Pin AOUT_L 27 Analog Output Audio Amplifier left-channel output. AOUT_R 28 Analog Output Audio Amplifier right-channel output. Te CURR3 www.austriamicrosystems.com Supply pin for Current Sinks, and Audio Amplifier; always connect to VBAT. 1.00 7 - 73 AS3605 1v2 Data Sheet - P i n A s s i g n m e n t s Table 1. Pin Descriptions Pin Name AGND Pin Number 29 Pin Type Analog Pin Description Audio Amplifier reference GND; if the Audio Amplifier is used, connect a capacitor of 100nF (±10%) to this pin. Caution: Do not connect directly to VSS. Supply pad for RF-LDOs VRF_1, VRF_2, VRF_3 and VRF_4; can be connected to VBAT or separate supply (3.0-5.5V). 30 Supply Pin VRF_1 31 Analog Output Output voltage of RF LDO VRF_1; if used, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). VRF_2 32 Analog Output Output voltage of RF LDO VRF_2; if used, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). VRF_3 33 Analog Output Output voltage of RF LDO VRF_3; if used, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). VRF_4 34 Analog Output Output voltage of RF LDO VRF_4; if used, connect a ceramic capacitor of 1µF (±20%) or 2.2µF (+100% / -50%). ISENSN 35 Analog Input Negative sensing input voltage for the external charging current shunt resistor. ISENSP 36 Analog Input Positive sensing input voltage for the external charging current shunt resistor. VGATE 37 Analog Output VCHARGER 38 Analog Input VBAT_2 39 Supply Pin LX 40 Analog Output VSS 41 VSS am lc s on A te G nt st il lv al id VBAT_4 Control pin for the external battery charger MOSFET transistor. High voltage input coming from the Battery Charger; if the Battery Charger is used, connect a ceramic capacitor of 1µF. Supply pin for the Step Down DC/DC Converter and LDO VSIM; always connect to VBAT. Step Down DC/DC Converter switch output to coil Te ch ni ca Ground pad (QFN40: exposed paddle). www.austriamicrosystems.com 1.00 8 - 73 AS3605 1v2 Data Sheet - A b s o l u t e M a x i m u m R a t i n g s 5 Absolute Maximum Ratings Stresses beyond those listed in Table 2 may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Operating Conditions on page 10 is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings Parameter Min Max Unit Comments VIN_HV High Voltage Pins -0.3 18.0 V Applicable for high voltage pins: VCHARGER, VGATE VIN_MV 5V Pins -0.3 7.0 V Applicable for pins 5V pins: VBAT_1 - VBAT_4, V5_6, VBUCK, GPIO1 - GPIO3, CURR1 - CURR5, VANA_1, VANA_2, AIN_L, AIN_R, AOUT_L, AOUT_R, XRES, SCK, SDA, ON, and LX VIN_LV 3.3V Pins -0.3 5.0 V Applicable for 3.3V pins: VRF_1 - VRF_4, VSIM, CAPN, AGND, ISENSP, ISENSN, V2_5, CREF IIN Input Pin Current -25 +25 mA At 25ºC Norm: JEDEC JESD78C Humidity 5 85 % Non-condensing 1.5 W PT for QFN40 package ±1.5 kV Norm: JEDEC JESD22-A114F +110 ºC am lc s on A te G nt st il lv al id Symbol Continuous Power Dissipation (TA = +70ºC) PT Continuous power dissipation Electrostatic Discharge Electrostatic Discharge HBM VESD 1 Temperature Ranges and Storage Conditions Tj Junction Temperature Tstrg Storage Temperature Range -55 +125 ºC Humidity non-condensing 5 85 % 260 ºC Temperature (soldering) Package Body Temperature Moisture Sensitive Level 3 2 Norm IPC/JEDEC J-STD-020 , reflects moisture sensitivity level only Represents a maximum floor live time of 168h Te ch ni ca 1. Depending on actual PCB layout and PCB used. 2. The reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. www.austriamicrosystems.com 1.00 9 - 73 AS3605 1v2 Data Sheet - E l e c t r i c a l C h a r a c t e r i s t i c s 6 Electrical Characteristics Table 3. Operating Conditions Parameter Min Typ Max Unit Notes TAMB Ambient Temperature -40 25 85 ºC VHV High Voltage 0.0 15.0 V Pins VCHARGER, VGATE VBAT Battery Voltage 3.0 3.6 5.5 V For pins VBAT_1 - VBAT_4. During startup from external battery charger adapter, the battery voltage can be below 3.0V. VANA_1 Periphery Supply Voltage for GPIO pins 1.8 OTP 3.35 V Internally generated from VANA_1 VON Activation voltage for ON pin 1.75 V2_5 VBAT V V2_5 Voltage on Pin V2_5 2.4 2.5 2.6 V Internally generated V5_6 Output Voltage of Charge Pump 4.9 5.2 5.6 V 2 x VBAT_1 IBAT Operating Current 195 260 µA low_power_on = 0; only VANA_1 active, ILOWPOWER Low-Power Mode Current Consumption 110 µA With bit low_power_on = 1; only VANA_1 active, no additional external loads. IPOWEROFF Power-Off Mode Current Consumption 10 µA With bit power_off = 1; only V2_5 is active in power OFF mode. Not tested, guaranteed by design lv al id Symbol am lc s on A te G nt st il Normal operating current. With bit Te ch ni ca 20 no additional external loads. www.austriamicrosystems.com 1.00 10 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7 Detailed Description 7.1 Battery Charge Controller The AS3605 device serves as a standalone battery charge controller supporting rechargeable lithium ion (Li+) and) batteries. Requiring only a few external components, a full-featured battery charger with a high degree of flexibility can easily be realized. The main features of the controller are: al id Charge adapter detection Internal voltage regulator Low current (trickle) charging Constant current charging Constant voltage charging lv Overvoltage protection Battery presence indication am lc s on A te G nt st il Operation without battery Figure 4. Charger Application Block Diagram VBAT AS3605 VCHARGER Q1 CHARGER PBSS301PD VCHARGER CCHARGER 10µF RSENSE 100mΩ CVBAT 10µF + LiIon Battery ISENSN VGATE Linear Charger Controller Digital Interface I >3.5mA ch ni ca ISENSP VBAT_sense Te Table 4. Charger External Components Symbol Component Value Note Q1 PNP power transistor PBSS301PD or similar hFE > 200 @ 0.8A RSENSE Current sense resistor 100mΩ ±1%, 125mW for ICHG < 1.5A e.g. Vishay Dale WSL0805 CCHRG Bypass capacitor on charger pin 10µF ±20%, X5R or X7R dielectric CBAT Minimum total capacitance parallel to battery 10µF, X5R or X7R dielectric www.austriamicrosystems.com 1.00 11 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.1.1 Charge Controller Operating Modes and Building Blocks Charge Adapter Detection. The charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied to the VCHARGER pin. If the adapter voltage exceeds the battery voltage at pin VBAT by VCHDET the ChDet bit in the ChargerStatus register will be set. The detection circuit will reset the charge controller (bit ChDet is cleared) as soon as the voltage at the VCHARGER pin drops to only VCHMIN above the battery voltage. In case the AS3605 device is reset the charge controller will also be reset, even if a charge adapter is applied to the VCHARGER pin. al id Low Current (trickle) Charging. Trickle charge mode is started when an external charge adapter has been detected and the battery voltage at pin VBAT is below the VUVLO threshold; bits ChAct and Trickle will be set in the ChargerStatus register. In this mode the charge current will be limited to TrickleCurrent[1:0] (set in the ChargerControl1 register) to prevent undue stress on either the battery or any of the charger components in case of deeply discharged batteries. Once VUVLO has been exceeded, the charger will change over to constant current charging (Trickle is cleared) and switch on the device. Constant Current Charging. Constant current charging is initiated by setting ChEn in the ChargerControl1 register. Note that ChEn is am lc s on A te G nt st il lv set by default to enable operation of the device without a battery connected to the system. The ChAct bit is set when the charger has started, and the charge current will be limited to ConstantCurrent[3:0] (set in the ChargerControl1 register) by the battery charge controller. When the battery approaches full charge, its voltage will exceed the charge termination threshold VCHOFF. VCHOFF depends on the Li4v2 bit in the ChargerControl2 register. The charging action will either be terminated (EOC bit will be set) or a top-off charge will be started (CVM will be set). Constant Voltage Charging. Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been reached. The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during constant current charging and eventually drop below the value set by TrickleCurrent[1:0] in the ChargerControl1 register. If the measured charge current is less than or equal to TrickleCurrent[1:0], the charging cycle is terminated and EOC is set. Battery Presence Indication and Operation Without Battery. After EOC state is reached a timer for NOBAT detection is started. If there is no battery present, the voltage will drop to VNOBAT_REG. Depending on the load on VBAT and the capacitor on VBAT this might take some mseconds to 1 second. If the RESUME mode is enabled (Bit resume_disable=0), the charger will restart charging (ConstantCurrent charging) after 100msec. The 100msec dead time is necessary to get a battery oscillation frequency of below 10Hz, if there is no battery present. If the NOBAT detection timer is below 2 seconds after reaching EOC state, and this happens 2 times in serial, the NOBAT bit in ChargerStatus register is set. If a battery is inserted, then the bit will be reset after the timer exceeds the 2 seconds. Charger Overvoltage Protection. This blocks checks if the charger voltage is above 6.05V or 6.45V if ChOvH is 1. If the status bit ChOv is 1 when ChOvEn is 1, the charger will shut down by clearing the ChEn bit and an interrupt will be generated. Table 5. Charger Parameters Parameter ca Symbol VCHDET Charger detection threshold VCHMIN Te VCHOFF Typ Max 50 75 105 0 20 35 6.2 6.45 6.71 5.81 6.05 6.29 3.1 Undervoltage lockout threshold ch VUVLO VCHARGER overvoltage detection ni VCHOVH Min Charge termination threshold VNOBATREG “No battery” regulation voltage VRESUME_ON Charger resume on threshold www.austriamicrosystems.com 4.20 mV V V 2.8 4.158 Unit 4.242 4.10 3.85 V V 3.75 3.85 V 3.75 1.00 Notes Hysteresis is > 40mV ChOvH = 1 ChOvH = 0 VBAT rising VBAT falling Li+ Battery: Li4v2 = 1 Li+ Battery: Li4v2 = 0 Li+ Battery: Li4v2 = 1 Li+ Battery: Li4v2 = 0 Li4v2 = 1 Li4v2 = 0 12 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 5. Charger Parameters Parameter VRESUME_OFF Charger resume off threshold IGATE_OFF Current into pin GATE, if charger disabled 0 IGATE_ON Current into pin GATE, if charger enabled and operation in low dropout mode (low VCE) 3.5 7.1.2 Min Typ Max Unit 4.02 V 3.92 0.4 5 Notes Li4v2 = 1 Li4v2 = 0 µA VCHARGER=5V mA VCHARGER=5V Charger Registers Addr. LDO_CHG 10h ChargerControl1 14h ChargerControl2 ChargerStatus b7 b6 b5 b4 b3 b2 EOCCurrent[1:0] ChOvEn TrickleCurrent[1:0] ConstantCurrent[3:0] b1 b0 16h ChOv ChOvH NA Li4v2 resume_d isable 35h NA NoBat EOC CVM Trickle NA Page 14 ChEn am lc s on A te G nt st il Name lv Table 6. Charger Register Summary al id Symbol ChAct ChDet 13 14 15 ChargerControl1 Register (Address 14h). ChargerControl1 Addr: 14h Bit Name Default Access 0 ChEn 1b R/W ConstantCurrent[3:0] Te ch 4:1 ni ca Bit www.austriamicrosystems.com OTP R/W Bit Description 0 Disable charging 1 Enable charging 0 0mA + Trickle_current 1 50mA + Trickle_current 2 100mA + Trickle_current 3 150mA + Trickle_current 4 200mA + Trickle_current 5 250mA + Trickle_current 6 300mA + Trickle_current 7 350mA + Trickle_current 8 400mA + Trickle_current 9 450mA + Trickle_current A 500mA + Trickle_current B 550mA + Trickle_current C 600mA + Trickle_current D 650mA + Trickle_current E 700mA + Trickle_current F 750mA + Trickle_current 1.00 13 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n ChargerControl1 Bit 6:5 Bit Name Default TrickleCurrent[1:0] OPT ChOvEn 7 Access R/W 1 R/W Bit Description 0 50mA 1 100mA 2 150mA 3 200 mA 0 Disable the Charger Overvoltage protection 1 Enable the Charger Overvoltage protection LDO_CHG Addr: 10h 3:2 Adjusts EOC current of Charger. Bit Name am lc s on A te G nt st il Bit lv LDO_CHG Register (Address 10h). al id Addr: 14h EOCCurrent[1:0] Default Access 00 R/W Bit Description 00 EOC Current = Trickle Current 01 EOC Current = Trickle Current + 18mA 10 do not use 11 EOC Current = Trickle Current + 33mA ChargerControl2 Register (Address 16h). ChargerControl2 Addr: 16h Bit Name Default Access 2:0 - NA NA 3 resume_disable 0 R/W 4 Li4v2 1 R/W 5 - ni ChOvH ch 6 ca Bit ChOv 1 NA 0 Enable Resume in EOC state 1 Disable Resume in EOC state 0 VCHOFF = 4.1V for Li+ battery cells with coke anode 1 VCHOFF = 4.2V for Li+ battery cells with graphite anode 0 Sets low threshold for Over voltage protection (typ. 6.05V) 1 Sets high threshold for Over voltage protection (typ. 6.45V) NA R/W R Indicates Charger overvoltage condition Te 7 NA Bit Description www.austriamicrosystems.com 1.00 14 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n ChargerStatus Register (Address 35h). ChargerStatus Addr: 35h Read only Bit Name Default Access Bit Description 0 ChDet NA R Bit is set when external charge adapter has been detected 1 ChAct NA R Bit is set when charger is operating 2 - NA 3 Trickle NA R Bit is set when charger is in trickle charge mode 4 CVM NA R Bit is set when charger is in top-off charge mode 5 EOC NA R Bit is set when charging has been terminated. Bit is cleared automatically when ChEn is cleared. 6 NoBat NA R Bit is set when battery detection circuit indicates that no battery is connected to the system. Bit is cleared automatically when a battery is connected or when ChEn is cleared. 7 - am lc s on A te G nt st il lv al id Bit NA Te ch ni ca NA www.austriamicrosystems.com 1.00 15 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.2 Step Down DC/DC Converter The step-down converter is a high-efficiency fixed frequency current mode regulator. By using low resistance internal PMOS and NMOS switches, efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the whole output voltage range, up to an output current of 500mA, with an output capacitor of only 10µF. The implemented current limitation protects the DC/DC Converter and the coil during overload condition. buck_dis_curmin 2.2MHz am lc s on A te G nt st il lv al id Figure 5. Step Down DC/DC Converter Block Diagram 170mA IMIN VBAT2 800mA ILIMIT ISENSP C16 1µF Overvoltage Comparator Ref + 8% + Skip – buck_dis_pon PSW LX Ref - 4% Logic L2 2.2µH + – 100% Duty Cycle NSW VOUT C18 10µF PWM Comparator GND_PAD – Σ VBUCK Skip – Softstart Slope Compensation Te ch ni AS3605 Ref = 0.6V + buck_v ca + ISENSN Zero Comparator www.austriamicrosystems.com 1.00 16 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 7. Step Down DC/DC Converter Parameters Parameter Min Max Unit VIN Input Voltage VOUT Regulated Output Voltage VOUT_TOL Output Voltage Tolerance ILIMIT Current Limit 3.0 5.5 V Pin VBAT_2 0.6 3.4 V Sense pin VBUCK -50 50 mV -3% 3% RPSW PSW On-Resistance 0.5 Ω RNSW NSW On-Resistance 0.5 Ω ILOAD Load Current 500 mA fSW Switching Frequency 2.2 MHz COUT Output Capacitor 10 µF Lx Inductor 2.2 µH h Efficiency 90 % 900 Sense pin VBUCK; Output Voltage > 1.6V mA Supply current into PMOS transistor Ceramic Current Consumption 100 ILOAD = 100mA, VOUT = 2.3V, VBAT = 3V Operating Current; No Load 250 IVDD_DCDC Sense pin VBUCK; Output Voltage < 1.6V am lc s on A te G nt st il 0 Notes lv Typ al id Symbol µA Quiescent Current; Low-Power Mode Shutdown Current 0.1 tMIN_ON Minimum ON Time 80 ns tMIN_OFF Minimum OFF Time 40 ns To allow optimized performance in different applications, there are bit settings possible, to get the best compromise between high efficiency and low input/output ripple. 7.2.1 Low-Ripple, Low-Noise Operation ca Low-ripple, low-noise operation can be enabled by setting bit buck_dis_curmin = 1. In this mode there is no minimum coil current necessary before switching OFF the PMOS. As result, the ON time of the PMOS will be reduced down to tMIN_ON at no or light load conditions, even if the coil current is very small or the coil current is inverted. This results in a very low ripple and noise (but decreased efficiency) at light loads, especially at low input-to-output voltage differences. Te ch ni Note: Because of the inverted coil current in that case the regulator will not operate in pulse skip mode. www.austriamicrosystems.com 1.00 17 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 6. Bit buck_dis_curmin = 1 Operation al id LX Voltage lv Coil Current (1mV=1mA) 7.2.2 am lc s on A te G nt st il VOUT High-Efficiency Operation (Default Setting) High-efficiency operation is enabled by setting bit buck_dis_curmin = 0. In this mode there is a minimum coil current necessary before switching OFF the PMOS. As result there are less pulses at low output load necessary, and therefore the efficiency at low output load is increased. This results in higher ripple, and noisy pulse skip operation up to a higher output current. Figure 7. Bit buck_dis_curmin = 0 Operation ca LX Voltage ch ni Coil Current (1mV=1mA) Te VOUT Note: It is possible to switch between these two modes during operation, i.e.: Bit buck_dis_curmin = 0: System is in idle state. No audio or RF signal. Decreased supply current preferred. Increase ripple doesn't effect system performance. www.austriamicrosystems.com 1.00 18 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Bit buck_dis_curmin = 1: System is operating. Audio signal on and/or RF signal used. Decreased ripple and noise preferred. Increased power supply current can be tolerated. 7.2.3 100% PMOS ON Mode for Low Dropout Regulation For low input-to-output voltage difference bit buck_dis_pon can be set to allow 100% duty cycle of the PMOS transistor, if the output voltage drops by more than 4% below regulation. Low Power Mode al id 7.2.4 Bit buck_lpo can be set all the time. This mode allows internal power down, of not used blocks during pulseskip mode, which results in a better efficiency at light output loads. 7.2.5 Typical Performance Characteristics DCDC buck Efficiency @2MHz, 3.6V VBAT2 am lc s on A te G nt st il 100 95 90 Efficiency [%] lv Figure 8. DC/DC Step-Down Efficiency vs. Output Current (buck_dis_cfm = 0) 85 80 Vbuck @ 1,2V 75 Vbuck @ 1,8V Vbuck @ 2.5V 70 Vbuck @ 1.2V lpo = 1 Vbuck @ 1.8V lpo = 1 65 ca 60 Vbuck @ 2.5V lpo = 1 7.2.6 10 100 1000 Output Current [mA] ni 1 Step Down DC/DC Converter Registers ch The Step Down DC/DC Converter is controlled by the registers listed in Table 8. Table 8. Step Down DC/DC Converter Register Summary Te Name Addr. b7 b6 b5 b4 Step Down Voltage/Test Modes 01h - Reg Power 09h - buck_on ldo_sim_ on Step Down Configuration 17h buck_dis_ buck_ curmin dis_pon buck_lpo - www.austriamicrosystems.com b3 b2 b1 b0 buck_v 1.00 20 ldo_ana2_ ldo_ana1 on _on - buck_ dis_n Page buck_ nsw_on buck_ psw_on 20 20 19 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Step Down Voltage Register (Address 01h). Step Down Voltage/Test Modes Addr: 01h Bit Sets the output voltage of the Step Down DC/DC Converter. Bit Name Default Access Bit Description Controls the voltage selection for the Step Down DC/DC Converter. buck_v 5:0 Boot ROM R/W al id 000000 0.6V (LSB = 50mV) … 111000- 3.4V 111111 - NA NA lv 7:6 Reg Power Register (Address 09h). am lc s on A te G nt st il Reg Power Addr: 09h Enables/disables voltage regulators. Bit Bit Name Default Access Bit Description 0 ldo_ana1_on Boot ROM RW Refer to page 28 1 ldo_ana2_on Boot ROM RW Refer to page 28 3:2 - NA NA 4 ldo_sim_on Boot ROM RW Refer to page 28 Enables the Step Down DC/DC Converter. 5 buck_on 7:6 - Boot ROM R/W NA 0 Step Down DC/DC Converter is OFF. 1 Step Down DC/DC Converter is ON. NA Step Down Configuration Register (Address 17h). Step Down Configuration Addr: 17h ca buck_psw_on ch 0 Bit Name buck_nsw_on Te 1 Default ni Bit Configures the operation mode of the Step Down DC/DC Converter. 0 Access R/W Activate PSW (0.5Ω PMOS) only if buck_on and buck_nsw_on = 0. 0 Default setting. P-Channel switching transistor is controlled by the DC/DC Converter. 1 Turns on P-Channel switching transistor. Bits buck_on and buck_nsw_on must both = 0. Activates NSW (0.5Ω NMOS) only if buck_on = 0 and buck_psw_on = 0. 0 R/W 2 buck_dis_n 0 R/W 3 - 0 RW www.austriamicrosystems.com Bit Description 0 Default setting. N-Channel switching transistor is controlled by the DC/DC Converter. 1 Turns on N-Channel switching transistor. Bits buck_on and buck_psw_on must both = 0. 0 Default setting. Normal operation of The synchronous rectifier. 1 The synchronous rectifier is disabled (NSW is always OFF). 0 1 1.00 20 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Step Down Configuration Addr: 17h Configures the operation mode of the Step Down DC/DC Converter. Bit Bit Name Default Access 4 - 0 R/W Bit Description 0 buck_lpo 0 R/W 0 Low-power mode disabled. 1 Low-power mode enabled. Step down PON feature control. 6 buck_dis_pon 0 R/W 0 PON feature enabled. 100% duty cycle (PMOS always on) if output voltage drops more than 4%. Increased output ripple in that operation. 1 PON feature disabled. Maximum duty cycle = 1 - (tmin_off*fsw) buck_dis_curmin 0 0 current force mode enabled. Inductor current regulated to min 170mA. Higher efficiency in low dropout and low output current operation. Higher output ripple and noise. 1 current force mode disabled. Decreased efficiency in low dropout mode and at low output current. Small output ripple and noise. R/W Te ch ni ca 7 am lc s on A te G nt st il Step down current force mode lv 5 al id 1 www.austriamicrosystems.com 1.00 21 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3 Low Dropout Regulators The Low Dropout Regulators (LDOs) are linear high performance regulators with programmable output voltages. The LDOs can be controlled by either software (voltage, ON/OFF) or hardware (ON/OFF) using highly configurable GPIO1 to GPIO3 pins. The Low Dropout Regulators include the following: RF and Analog Low Dropout Regulators – Described on page 22 Analog LDO Block Diagram – Described on page 22 al id SIMCard Low Dropout Regulator – Described on page 23 Low Power Low Dropout Regulator – Described on page 24 7.3.1 RF and Analog Low Dropout Regulators lv The RF LDOs (VRF_1 - VRF_4) and Analog LDOs (VANA_1 and VANA_2) are designed to supply power to sensitive analog circuits like LNAs, Transceivers, VCOs and other critical RF components of cellular radios. Additionally, these LDOs are suitable for supplying power to audio devices or as a reference for A/D and D/A converters. The design is optimized to deliver the best compromise between quiescent current and regulator performance for battery powered devices. Stability is guaranteed with ceramic output capacitors (see Figure ) of 1µF ±20% (X5R) or 2.2µF +100 / -50% (Z5U). am lc s on A te G nt st il The low ESR of these capacitors ensures low output impedance at high frequencies. Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear mode. Power supply rejection is high enough to suppress ripple on the battery caused by the PA in TDMA systems. The low noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance of the power transistor enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of performance. The LDOs have a built-in discharge function when switched off. Figure 9. Analog LDO Block Diagram High-Gain Low-Bandwidth Amplifier VREF1.8V Low-Noise DC Reference Low-Gain Ultra High-Bandwidth Amplifier VBAT 3.0 to 5.5V + – + VOUT 1.8 to 3.35V 250/150mA Load ni ca – ch 1µF X5R (External) Te GND www.austriamicrosystems.com 1.00 22 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 9. RF and Analog LDO Characteristics VBAT = 3.6V; ILOAD = 150mA; TA = 25ºC; CLOAD = 2.2µF (Ceramic); unless otherwise specified. Symbol Parameter Min VBAT Supply Voltage Range 3 RON On-Resistance PSRR Power Supply Rejection Ratio IOFF Shut Down Current 100 nA IVDD_LDO Supply Current 50 µA Noise Output Noise 50 µVrms tSTART Startup Time 200 µs Max Unit 5.5 V VANA_1, VANA_2 Ω 70 VRF_1, VRF_2, VRF_3, VRF_4 dB 40 30 f = 1kHz f = 100kHz Without load al id 2 lv 1 Notes 10Hz < f < 100kHz am lc s on A te G nt st il Output Voltage VOUT VOUT_TOL Output Voltage Tolerance VLINEREG Line Regulation VLOADREG Load Regulation ILIMIT 7.3.2 Typ Current Limitation 1.8 2.85 1.8 3.35 -50 50 -1 1 -10 10 -1 1 -10 10 VBAT > 3.0V V Full programmable range mV mV mV Static Transient; Slope: tr = 10µs Static Transient; Slope: tr = 10µs 250 400 mA VANA_1, VANA_2 150 180 mA VRF_1, VRF_2, VRF_3, VRF_4 SIMCard Low Dropout Regulator The SIMCard LDO (VSIM) is optimized for SIMCard supply. It is designed to achieve the lowest possible power consumption and still provide reasonable regulation characteristics. To ensure high PSRR and stability, a low-ESR ceramic capacitor of 100nF (min.) must be connected to the output. The LDO has a built-in discharge function when switched off. ca Table 10. LDO VSIM Characteristics VBAT = 3.6V; ILOAD = 20mA; TA = 25ºC; CLOAD = 100nF (Ceramic); unless otherwise specified. Symbol RON Supply Voltage Range 3 Power Supply Rejection Ratio IOFF Shut Down Current IVDD_SIMCARD Supply Current tSTART Startup Time VOUT Output Voltage VOUT_TOL Output Voltage Tolerance VLINEREG Line Regulation Te Typ On-Resistance ch PSRR Min ni VBAT Parameter www.austriamicrosystems.com Max Unit 5.5 V 50 Ω 40 dB 20 100 40 f = 1kHz f = 100kHz nA µA 200 µs 1.8 3.0 V -50 50 mV -10 10 -100 100 1.00 Notes mV VBAT > 3.2V Static Transient; Slope: tr = 10µs 23 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 10. LDO VSIM Characteristics (Continued) VBAT = 3.6V; ILOAD = 20mA; TA = 25ºC; CLOAD = 100nF (Ceramic); unless otherwise specified. Parameter VLOADREG 7.3.3 Load Regulation Min Typ Max -10 10 -100 100 Unit mV Notes Static Transient; Slope: tr = 10µs Low Power Low Dropout Regulator al id Symbol The low-power bootstrap LDO (V2_5) is needed to supply power to the core (analog and digital) of the AS3605. LDO V2_5 is designed to achieve the lowest possible power consumption, and still provide reasonable regulation characteristics. LDO V2_5 has two supply inputs selecting automatically the higher one. This gives the possibility to supply the AS3605 core either with the battery or with the Battery Charger, depending on the conditions. lv To ensure high PSRR and stability, a low-ESR ceramic capacitor of 1µF (min.) must be connected to the output. Note: Levelshifters in both directions (input and output) are placed between digital pins (VANA_1) and the digital core (V2_5) of the device, because of the different power supplies. Symbol VBAT VCHARGER RON am lc s on A te G nt st il Table 11. LDO V2_5 Characteristics VBAT = 3.6V; CLOAD_EXT = 0; TA = 25ºC; CLOAD = 2.2µF (Ceramic); unless otherwise specified. Parameter Min Supply Voltage Range External Charger Adapter voltage Max Unit 2.8 5.5 V 4 15 V On-Resistance IOFF IVDD_LPLDO tSTART VOUT Typ Ω 50 Shut Down Current 100 nA Supply Current 3 µA Startup Time 200 µs 2.6 V 2.4 2.5 Guaranteed per design Guaranteed per design; consider device internal load for measurement Te ch ni ca Output Voltage Notes www.austriamicrosystems.com 1.00 24 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Typical Performance Characteristics Figure 10. Load Regulation of LDOs VANA_1, VANA_2 Figure 11. Output Noise of LDOs VANA_1, VANA_2 5mV VOUT = 2.8V, 10mV/Div 3mV 8mV lv ILoad = 150mA ILoad = 100mA 120mA, Slope: 10μs 1µs al id 7.3.4 1mA am lc s on A te G nt st il 10mA Spectral Distribution at 150mA Output Load X-Axis: 40µs/Div Figure 12. Load Regulation of LDO V2_5 7mV Figure 13. Line Regulation of LDO V2_5 VOUT = 5mV/ VOUT = 1mV/Div ILOAD = 20mA VBAT = 3.1V ILOAD = 1mA ca VBAT = 3.0V 10µs X-Axis: 40µs/Div Te ch ni X-Axis: 25µs/Div www.austriamicrosystems.com 1.00 25 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.3.5 LDO Registers The Low Dropout Regulators are controlled by the registers listed in Table 12. Table 12. Low Dropout Regulators Register Summary Name Addr. b7 b6 b5 b4 b3 b2 b1 b0 Page 02h - ldo_rf1_v 26 LDO_RF2 Voltage 03h - ldo_rf2_v 27 LDO_RF3 Voltage 04h - ldo_rf3_v LDO_RF4 Voltage 05h - ldo_rf4_v LDO_ANA2_Voltage 06h - ldo_ana2_v LDO_ANA1_Voltage 07h LDO_SIM_Voltage 08h Reg Power 09h - 27 27 ldo_ana1_v ldo_sim_v buck_on ldo_sim_ on - 28 28 - ldo_ana2 ldo_ana1 _on _on am lc s on A te G nt st il - 27 lv - al id LDO_RF1 Voltage LDO_GPIO Active LDO_CHG LDO_AD GPIOx ldo_rf4_g ldo_rf3_g ldo_rf2_g ldo_rf1_g ldo_ana2 ldo_buck pio pio pio pio _gpio _gpio 0Fh - - 10h ldo_rf4 _on ldo_rf3 _on 11h LDO_RF GPIOx 12h ldo_rf2 _on ldo_rf1 _on - ldo_rf4_gpio_sel ldo_rf3_gpio_sel 28 29 EOCCurrent[1:0] ana2_sw ana1_sw 29 ldo_ana2_gpio_sel buck_gpio_sel 30 ldo_rf2_gpio_sel ldo_rf1_gpio_sel 31 LDO_RF1 Voltage Register (Address 02h). LDO_RF1 Voltage Addr: 02h 4:0 ca ldo_rf1_v - Default Boot ROM NA Access Bit Description 00000 R/W … 11111 1.8V (LSB = 50mV) 3.35V NA Te ch 7:5 Bit Name ni Bit Sets the voltage for LDO VRF_1. www.austriamicrosystems.com 1.00 26 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_RF2 Voltage Register (Address 03h). LDO_RF2 Voltage Addr: 03h Sets the voltage for LDO VRF_2. Default Access Bit Description 00000 ldo_rf2_v 4:0 Boot ROM R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA LDO_RF3 Voltage Register (Address 04h). LDO_RF3 Voltage Addr: 04h Bit Name Default Access Bit Description am lc s on A te G nt st il Bit Sets the voltage for LDO VRF_3. 00000 4:0 ldo_rf3_v Boot ROM R/W … 11111 7:5 - al id Bit Name lv Bit NA 1.8V (LSB = 50mV) 3.35V NA LDO_RF4 Voltage Register (Address 05h). LDO_RF4 Voltage Addr: 05h Bit Sets the voltage for LDO VRF_4. Bit Name Default Access Bit Description 00000 4:0 ldo_rf4_v Boot ROM R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA ca LDO_ANA2_Voltage Register (Address 06h). LDO_ANA2_Voltage Addr: 06h ni Bit Name ch Bit Sets the voltage for LDO VANA_2. ldo_ana2_v Te 4:0 7:5 - www.austriamicrosystems.com Default Boot ROM Access Bit Description Sets the voltage for LDO VANA_2 R/W 00000 … 11111 NA 1.80V (LSB = 50mV) 3.35V NA 1.00 27 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_ANA1_Voltage Register (Address 07h). LDO_ANA1_Voltage Addr: 07h Bit Sets the voltage for LDO VANA_1. Bit Name Default Access Bit Description Sets the voltage for LDO VANA_1 ldo_ana1_v Boot ROM 00000 R/W … 11111 7:5 - NA 1.8V (LSB = 50mV) 3.35V NA lv LDO_SIM_Voltage Register (Address 08h). LDO_SIM_Voltage Addr: 08h Bit Name 5:0 - am lc s on A te G nt st il Sets the voltage for Digital LDO VSIM. Bit al id 4:0 Default Access NA NA Bit Description Sets the voltage for LDO VSIM. 6 ldo_sim_v 7 - Boot ROM NA R/W 0 1.8V 1 3.0V NA Reg Power Register (Address 09h). Reg Power Addr:09h ldo_ana2_on ch 1 ldo_ana1_on 3:2 - ldo_sim_on Te 4 5 7:6 Default Boot ROM ca 0 Bit Name ni Bit Enables/disables voltage regulators. Boot ROM NA Access R/W Bit Description Enables control of LDO VANA_1. Note: Do not set this bit = 0 or serial interface access will be disabled. 0 LDO VANA_1 is OFF. 1 LDO VANA_1 is ON. Enables control of LDO VANA_2. R/W 0 LDO VANA_2 is OFF. 1 LDO VANA_2 is ON. NA Enables control of LDO VSIM. Boot ROM R/W 0 LDO VSIM is OFF. 1 LDO VSIM is ON. Enables the Step Down DC/DC Converter. buck_on - www.austriamicrosystems.com Boot ROM NA 0 Step Down DC/DC Converter is OFF. 1 Step Down DC/DC Converter is ON. NA 1.00 28 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_GPIO Active Register (Address 0Fh). LDO_GPIO Active Addr: 0Fh Bit Activates GPIO ON/OFF control for voltage regulators. Bit Name Default buck_gpio Boot ROM Access Bit Description Activates GPIO control of Step Down DC/DC Converter. R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit buck_on = 1. al id 0 Activates GPIO control for LDO VANA_2. ldo_ana2_gpio R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_ana2_on = 1. Activates GPIO control for LDO VRF_1. ldo_rf1_gpio R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf1_on = 1. am lc s on A te G nt st il 2 Boot ROM lv 1 Boot ROM Activates GPIO control for LDO VRF_2. 3 ldo_rf2_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf2_on = 1. Activates GPIO control for LDO VRF_3. 4 ldo_rf3_gpio Boot ROM R/W 0 Controlled by software. 1 On when assigned GPIO pin = 1 and bit ldo_rf3_on = 1. Activates GPIO control for LDO VRF_4. 5 ldo_rf4_gpio 7:6 - Boot ROM R/W NA 0 Controlled by software. 1 LDO VRF_4 is on when assigned GPIO pin = 1 and bit ldo_rf4_on = 1. NA LDO_RF Switch Register (Address 10h). LDO_CHG Addr: 10h Enables LDOs and high-side switches. Bit Name 0 ana1_sw ldo_rf1_on Te 4 Access 0 R/W ni ana2_sw ch 1 Default ca Bit www.austriamicrosystems.com 0 R/W Bit Description 0 VANA_1 operates as LDO. 1 VANA_1 is operating as high-side switch (RON=1Ω); valid if ldo_ana1_on = 0. 0 VANA_2 operates as LDO. 1 VANA_2 is operating as high-side switch (RON=1Ω); valid if ldo_ana2_on = 0. Enables control of LDO VRF_1. 0 R/W 0 LDO VRF_1 is OFF. 1 LDO VRF_1 is ON. 1.00 29 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_CHG Addr: 10h Enables LDOs and high-side switches. Bit Bit Name Default Access Bit Description 0 R/W 0 LDO VRF_2 is OFF. 1 LDO VRF_2 is ON. Enables control of LDO VRF_3. ldo_rf3_on 6 0 R/W 0 LDO VRF_3 is OFF. 1 LDO VRF_3 is ON. Enables control of LDO VRF_4. ldo_rf4_on 7 0 R/W anax_sw* ANA LDO Function 0 0 OFF 0 1 1 * Where x = 1-4 LDO VRF_4 is OFF. 1 LDO VRF_4 is ON. am lc s on A te G nt st il ldo_anax_on* 0 lv ldo_rf2_on 5 al id Enables control of LDO VRF_2. 1 Fully ON, RON = 1Ω 0 Linear Voltage Regulator 1 Not Allowed LDO_AD GPIOx Register (Address 11h). LDO_AD GPIOx Addr: 11h Bit Selects GPIO pin for power ON/OFF control for DCDC and VANA_2. Bit Name Default Access Bit Description Valid if GPIO activation bit buck_gpio = 1 buck_gpio_sel 00h R/W ldo_ana2_gpio_sel ch 3:2 ni ca 1:0 R/W GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if GPIO activation bit ldo_ana2_gpio = 1 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting NA Te 7:4 00h 00 www.austriamicrosystems.com 1.00 30 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n LDO_RF GPIOx Register (Address 12h). LDO_RF GPIOx Addr: 12h Bit Selects GPIO pin for power ON/OFF control for RF LDOs VRF_1 - VRF_4. Bit Name Default Access Bit Description ldo_rf1_gpio_sel Boot ROM R/W GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if ldo_rf2_gpio = 1 ldo_rf2_gpio_sel Boot ROM R/W GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting am lc s on A te G nt st il 3:2 00 lv 1:0 00 al id Valid if ldo_rf1_gpio = 1 Valid if ldo_rf3_gpio = 1 5:4 ldo_rf3_gpio_sel Boot ROM R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Valid if ldo_rf4_gpio = 1 ldo_rf4_gpio_sel Boot ROM R/W GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting Te ch ni ca 7:6 00 www.austriamicrosystems.com 1.00 31 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.4 Charge Pump The Charge Pump uses the external flying capacitor C2 (470nF) to generate output voltages higher than the battery voltage. There are two different operating modes of the charge pump itself: 1:1 Bypass Mode al id - Battery input and output are connected by a low-impedance switch - Battery current = output current 1:2 Mode - The output voltage is up to 2 times the battery voltage (without load), but is limited to VCPOUTmax all the time - Battery current = 2 times output current As the battery voltage decreases, the Charge Pump must be switched from 1:1 mode to 1:2 mode in order to provide enough supply for the current sinks. Depending on the actual current, the mode with best overall efficiency can be automatically or manually selected: lv The charge pump mode switching can be done manually or automatically with the following possible software settings: Automatic am lc s on A te G nt st il - Start with 1:1 mode - Switch up automatically to 1:2 mode Manual - Set modes 1:1 and 1:2 by software 7.4.1 Charge Pump Mode Switching If automatic mode switching is enabled (cp_mode_switching = 0) the charge pump monitors the current sinks, which are connected via a LED to the output V5_6. To identify these current sources (sinks), the registers CP mode Switch (register bits curr1_on_cp …curr5_on_cp) should be setup before starting the charge pump (cp_on =1). If any of the voltage on these current sources drops below the threshold (currlv_switch, currhv_switch), the 1:2 mode is selected after the debounce time. The CP will not switch back to 1:1 mode. If the currX_on_cp=0 and the according current sink is connected to the charge pump, the current sink will be functional, but there is no up switching of the charge pump, if the voltage compliance is too low for the current sink to supply the specified current. Te ch ni ca Figure 14. Automatic Mode Switching www.austriamicrosystems.com 1.00 32 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n The Charge Pump requires the external components specified in Table 13. Table 13. Charge Pump External Components Parameter Min CFLY (C2) External Flying Capacitor CSTORE (C3) External Storage Capacitor Typ Max Unit 470 1 4.7 Notes nF Ceramic low-ESR capacitor between pins CAPP and CAPN (see page 2). µF Ceramic low-ESR capacitor between pins V5_6 and VSS (see page 2). Note: Connections to the two external capacitors should be kept as short as possible. Table 14. Charge Pump Parameters VBAT = 3.6V; TAMB = 25ºC; unless otherwise specified. Min ICPOUT Output Current 0 VCPOUTmax Output Voltage RCP Effective Charge Pump Output Resistance currlv_switch if the current sink voltage drops below this threshold it will change from 1:1 to 1:2 mode tdeb start_up debounce time ISHUTDOWN Shutdown Current 7.4.2 Typ Max Unit 60 mA 5.6 V Notes lv Parameter including output ripple am lc s on A te G nt st il Symbol al id Symbol 8.8 Ω VBAT = 3.0V, cp_mode[1:0] = 1:1 31 Ω VBAT = 3.0V, cp_mode[1:0] = 1:2 mV cp_mode_switching = automatic 200 240 µs 2000 0.1 cp_start_debounce = 0 cp_start_debounce = 1 µA Charge Pump Registers Table 15. Charge Pump Register Summary Charge Pump Control Onkey Pulldown CP Mode Switch b7 b6 b5 18h cp_auto_ cp_start_d onkey_pul on ebounce ld_off 36h NA 37h NA b4 b3 cp_freq cp_mode _switchin g b2 b1 cp_mode[1:0] b0 Page cp_on 34 curr5_on curr4_on curr3_on_ curr2_on_ curr1_on_ _cp _cp cp cp cp 35 curr5_low curr4_low curr3_low curr2_low curr1_low _volt _volt _volt _volt _volt 35 Te ch ni Curr Low Voltage Status Addr. ca Name www.austriamicrosystems.com 1.00 33 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Charge Pump Control Onkey Pulldown Register (Address 18h). Charge Pump Control Onkey Pulldown Addr: 18h Sets the operation mode of the Charge Pump. Bit Name Default Access 0 cp_on 0b R/W Bit Description 0 Set CP into 1:1 mode (OFF state) unless cp_auto_on is set. 1 Enable manual mode switching al id Bit CP mode (in manual mode sets this mode, in automatic mode reports the actual mode used) cp_mode[1:0] 00b R/W 01 10 11 1:1 mode 1:2 mode 3 am lc s on A te G nt st il Set the mode switching algorithm lv 00 2:1 cp_mode_switching 0b R/W 0 Automatic mode switching 1 Manual mode switching; register cp_mode[1:0] defines the actual CP mode used. Clock frequency selection cp_freq 4 0b R/W 5 onkey_pulld_off 0b R/W 6 cp_start_debounce 0b R/W cp_auto_on 1b R/W 1 MHz 1 500 kHz 0 pull down on ON-key active 1 pull down on ON-key deactivated 0 Mode switching debounce timer is always 240µs. 1 Upon startup (cp_on set to 1) the mode switching debounce time is first started with 2ms then reduced to 240µs. 0 The CP is swiched ON/OFF with cp_on 1 The CP is automatically switched on if a current sink, which is connected to the CP (defined by registers CP Mode Switch 1&2) is switched ON and detects a low voltage condition. Te ch ni ca 7 0 www.austriamicrosystems.com 1.00 34 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CP Mode Switch Register (Address 36h). CP Mode Switch Addr: 36h Setup which current sinks are connected (via LEDs) to the CP; if set to 1 the corresponding current sink is used for automatic mode selection of the CP. 0 curr1_on_cp 0b 1 curr2_on_cp 0b 2 curr3_on_cp 0b 3 curr4_on_cp 0b 4 curr5_on_cp 5:7 - Access R/W R/W R/W R/W Bit Description 0 Current sink CURR1 is not connected to the CP 1 Current sink CURR1 is connected to the CP 0 Current sink CURR2 is not connected to the CP 1 Current sink CURR2 is connected to the CP 0 Current sink CURR3 is not connected to the CP 1 Current sink CURR3 is connected to the CP 0 Current sink CURR4 is not connected to the CP 1 Current sink CURR4 is connected to the CP al id Default lv Bit Name am lc s on A te G nt st il Bit 0b NA R/W 0 Current sink CURR5 is not connected to the CP 1 Current sink CURR5 is connected to the CP NA Curr Low Voltage Status Register (Address 37h). Curr Low Voltage Status Addr: 37h Indicates the low voltage status of the current sinks. If the currX_low_v bit is set, the voltage on the current sink is too low, to drive the selected output current. Bit Name 0 curr1_low_v 1 curr2_low_v 2 curr3_low_v 3 curr4_low_v NA R NA R NA R NA R curr5_low_v NA R - NA NA Bit Description 0 The voltage of current sink CURR1 > currlv_switch 1 The voltage of current sink CURR1 < currlv_switch 0 The voltage of current sink CURR2 > currlv_switch 1 The voltage of current sink CURR2 < currlv_switch 0 The voltage of current sink CURR3 > currlv_switch 1 The voltage of current sink CURR3 < currlv_switch 0 The voltage of current sink CURR4 > currlv_switch 1 The voltage of current sink CURR4 < currlv_switch 0 The voltage of current sink CURR5 > currlv_switch 1 The voltage of current sink CURR5 < currlv_switch Te ch 5:7 Access ni 4 Default ca Bit www.austriamicrosystems.com 1.00 35 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5 General Purpose Input/Output The general purpose input/output pins (GPIO1 - GPIO3) are highly configurable and independently controlled. Table 16. DC Characteristics Input/Output Pin with Selectable Supply GPIO1:GPIO3 Symbol Parameter Min Max VIH High-Level Input Voltage 0.7 x VANA_1 VIL Low-Level Input Voltage ILEAK Input Leakage Current (if not used as pulldown/pullup) IPULLDOWN Unit Notes V V -5 5 µA to VANA_1 and VSS Pulldown Current (if configured as pulldown) 5 50 µA to VSS IPULLUP Pullup Current (if configured as pullup) -200 -20 µA to V5_6 or VANA_1 as configured VOH High-Level Output Voltage Supply VANA_1 0.8 x VANA_1 VOL Low-Level Output Voltage 0.2 x VANA_1 V CLOAD Capacitive Load 50 pF lv at -2mA am lc s on A te G nt st il V al id 0.3 x VANA_1 at 2mA GPIO1 - GPIO3 can be used to accommodate the following functionality: Software controlled input and output Input pin for the Watchdog Signal input (GPIO1-GPIO3) Interrupt output with configurable interrupt source Configurable frequency and duty cycle output External clock input for Step Up/Down DC/DC Converters and Charge Pump synchronization (GPIO1 only) Active pullup or pulldown; can be combined with other I/O functions Te ch ni ca Output open drain (push or pull type) www.austriamicrosystems.com 1.00 36 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 15. General Purpose I/O Block Diagram VANA_1 Register GPIO Control en_pup en_pdwn en_pmos en_nmos gpio_invert gpio_out_src lv interface al id VANA_1 am lc s on A te G nt st il gpio Frequency Generator sysclk Interrupt f_out MUX GPIOx int Interrupt Sources 7.5.1 GPIO Registers GPIO1 - GPIO3 are controlled by the registers listed in Table 17. Name GPIO1 Control 1Ah ch GPIO3 Control Addr. b7 b6 gpio1_out_src b5 b4 b3 b2 b1 b0 Page gpio1_ invert gpio1_pulls gpio1_ low_curr gpio1_mode 38 1Bh gpio2_out_src gpio2_ invert gpio2_pulls gpio2_low _curr gpio2_mode 38 1Ch gpio3_out_src gpio3_ invert gpio3_pulls gpio3_ low_curr gpio3_mode 39 ni GPIO2 Control ca Table 17. GPIO Register Summary 21h GPIO Frequency Control High Time 22h gpio_h_time 41 GPIO Frequency Control Low Time 23h gpio_l_time 41 Clock Generation 1Eh - Interrupt Enable 1Fh chgov_in chgrmv_in resume_in t_en t_en t_en chdet_ int_en onkey_ int_en ovtmp_ int_en Interrupt Status 20h chgov_i chdet_i onkey_i ovtmp_i Te GPIO Signal www.austriamicrosystems.com - chgrmv_i resume_i gpio3 1.00 gpio2 gpio1 40 ext_clk 41 vchoff_ int_en wdog _int_en 42 vchoff_i wdog_i 43 37 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO1 Control Register (Address 1Ah). GPIO1 Control Addr: 1Ah Bit Configures pin GPIO1. Bit Name Default Access Bit Description Sets the direction for pin GPIO1. 00 gpio1_low_curr R/W 0 01 Output (push and pull) 10 Output (open drain, only push; only NMOS is active) 11 Output (open drain, only pull; only PMOS is active) 0 Fast output slew rate 1 Slow output slew rate R/W al id 2 gpio1_mode Input only lv 1:0 00 4:3 5 gpio1_pulls gpio1_invert am lc s on A te G nt st il Sets pullup/pulldown to pin GPIO1 (independent of bit gpio1_mode setting). 00 R/W 0 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to GPIO1. This is useful for the Watchdog output source to make the output active high or low. R/W Sets the source of pin GPIO1 output. x0 7:6 gpio1_out_src 00 R/W 01 11 Bit gpio1 controlled through the serial interface. Frequency generator defined by bits gpio_h_time and gpio_l_time. Interrupt signal (see Interrupt Function on page 42). GPIO2 Control Register (Address 1Bh). ca GPIO2 Control Addr: 1Bh gpio2_mode Te ch 1:0 Bit Name 2 Default ni Bit Configures pin GPIO2. gpio2_low_curr www.austriamicrosystems.com 00 0 Access Bit Description Sets the direction for pin GPIO2. R/W R/W 00 Input only 01 Output (push and pull) 10 Output (open drain, only push; only NMOS is active) 11 Output (open drain, only pull; only PMOS is active) 0 Fast output slew rate 1 Slow output slew rate 1.00 38 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO2 Control Addr: 1Bh Bit Configures pin GPIO2. Bit Name Default Access Bit Description Sets pullup/pulldown to pin GPIO2 (independent of bit gpio2_mode setting). 00 gpio2_invert R/W 0 R/W 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to pin GPIO2. This is useful for the Watchdog output source to make the output active high or low. am lc s on A te G nt st il Sets the source of pin GPIO2 output. Bit gpio2 (controlled through the serial interface). x0 7:6 al id 5 gpio2_pulls lv 4:3 gpio2_out_src 00 R/W Frequency generator defined by bits gpio_h_time and 01 gpio_l_time. Interrupt signal (see Interrupt Function on page 42). 11 GPIO3 Control Register (Address 1Ch). GPIO3 Control Addr: 1Ch Bit Configures pin GPIO3. Bit Name Default Access Bit Description Sets the direction for pin GPIO3. gpio3_low_curr 00 0 R/W R/W Input only. 01 Output (push and pull). 10 Output (open drain, only push; only NMOS is active). 11 Output (open drain, only pull; only PMOS is active). 0 Fast output slew rate 1 Slow output slew rate Te ch ni 3:2 gpio3_mode ca 1:0 00 www.austriamicrosystems.com 1.00 39 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n GPIO3 Control Addr: 1Ch Bit Configures pin GPIO3. Bit Name Default Access Bit Description Sets pullup/pulldown to pin GPIO3 (independent of bit gpio3_mode setting). 00 gpio3_invert 0 R/W R/W 00 None 01 Pulldown 10 Pullup 11 NA 0 Output signal is not inverted. 1 Inverts any output signal going to pin GPIO3. This is useful for the Watchdog output source to make the output active high or low. am lc s on A te G nt st il Sets the source of pin GPIO3. Bit gpio3 (controlled through the serial interface) x0 7:6 al id 5 gpio3_pulls lv 4 gpio3_out_src 00 R/W Frequency generator defined by bits gpio_h_time and 01 gpio_l_time. Interrupt signal (see Interrupt Function on page 42). 11 GPIO Signal Register (Address 21h). Table 18. GPIO Signal Register (Address 33) GPIO Signal Addr: 21h Reads the logic signal of the GPIO pins, independently of any other GPIO bit setting. Bit Name 0 gpio1 1 gpio2 2 gpio3 7:3 - Default Access NA R Reads the logic signal from pin GPIO1. If gpio1_out_src = 00, this is the output signal at pin GPIO1. NA R Reads the logic signal from pin GPIO2. If gpio2_out_src = 00, this is the output signal at pin GPIO2. NA R Reads the logic signal from pin GPIO3. If gpio3_out_src = 00, this is the output signal at pin GPIO3. ca Bit NA Te ch ni NA Bit Description www.austriamicrosystems.com 1.00 40 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5.2 Programmable Frequency Generator The Programmable Frequency Generator is controlled by bits gpio_h_time and gpio_l_time. It generates a waveform with 0.9 microseconds times gpio_h_time high-level and 0.9 microseconds times gpio_l_time low-level. The accuracy of these timings is ±10%. The frequency of the Programmable Frequency Generator is: f=1/(tCLK*gpio_h_time + tCLK*gpio_l_time) (EQ 1) al id Where: tclk = 1/fCLK = 1/1.1MHz (typ) = 0.909µs (typ) General User-Defined Clock 8-Bit DAC (output should be filtered by an RC filter) (High) Positive and Negative Voltage Generation (see Interrupt Function on page 42) 7.5.3 Programmable Frequency Generator Registers am lc s on A te G nt st il Bit definition for programmable frequency generator registers are given below. lv The purpose of the Programmable Frequency Generator is to have a controlled sweepable frequency or duty cycle source for one of the following: GPIO Frequency Control High Time Register (Address 22h). GPIO Frequency Control High Time Addr: 22h Bit Configures programmable frequency generator. Bit Name Default Access Bit Description Defines the number of system clock cycles (typ 0.9µs), that the programmable frequency generator at the GPIO output(s) is high. 7:0 gpio_h_time 00h R/W 00h 0.909µs FFh 232.7µs GPIO Frequency Control Low Time Register (Address 23h). GPIO Frequency Control Low Time Addr: 23h Default Access gpio_l_time 64h R/W Bit Description Defines the number of system clock cycles (typ 0.9µs), that the programmable frequency generator at the GPIO output(s) is low. 00h 0.909µs FFh 232.7µs Te ch ni 7:0 Bit Name ca Bit Configures programmable frequency generator. www.austriamicrosystems.com 1.00 41 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.5.4 Interrupt Function Any of the GPIO pins (GPIO1 - GPIO3) can be configured as interrupt output pins. To enable this function, the corresponding GPIO control bits must be set to 11b. See gpio1_out_src, gpio2_out_src, or gpio3_out_src. Several signals can be configured as interrupt source using the Interrupt Enable (page 42). A rising edge of an enabled interrupt control signal sets the selected GPIO interrupt output pin = 1. 7.5.5 al id The Interrupt Status (page 43) shows the currently active interrupt signals. Reading this register resets the Interrupt Status (page 43) bits and sets the active GPIO pin (GPIO 1 - GPIO3) = 0. Interrupt Registers Bit definition for Interrupt registers are given below. Interrupt Enable Addr: 1Fh Enables/disables interrupt sources. Default 0 wdog_int_en 1 vchoff_int_en 2 ovtmp_int_en 3 onkey_int_en 4 chdet_int_en 5 resume_int_en 6 chgrmv_int_en 7 chgov_int_en Access Bit Description 0 Disables watchdog alarm as interrupt source signal. 1 Enables watchdog alarm as interrupt source signal. 0 Disables charge termination voltage as interrupt source signal. 1 Enables charge termination voltage as interrupt source signal. 0 Disables ov_temp_110 (device temperature alert at 110ºC). 1 Enables ov_temp_110 (device temperature alert at 110ºC). 0 Disables pin ON (active high). 1 Enables pin ON (active high). 0 Disables charger detection. 1 Enables charger detection. 0 Disables charger-resume interrupt. 1 Enables charger-resume interrupt. 0 Disables charger-removed interrupt. 1 Enables charger-removed interrupt. 0 Disables charger overvoltage interrupt. 1 Enables charger overvoltage interrupt. am lc s on A te G nt st il Bit Name 0 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W ca Bit lv Interrupt Enable Register (Address 1Fh). R/W Te ch ni 1 www.austriamicrosystems.com 1.00 42 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Interrupt Status Register (Address 20h). Interrupt Status Addr: 20h Displays the status of the interrupt inputs. Bit Bit Name Default Access Bit Description 0 wdog_i 0 R 1 vchoff_i 0 R 2 ovtmp_i 0 R 3 onkey_i 0 R 4 chdet_i 0 R Charger detection interrupt, active if ChDet is falling. 5 resume_i 0 R Active if VRESUME is reached (see Table 5). 6 chgrmv_i 0 R Charger detection interrupt, active if ChDet is falling. 7 chgov_i 0 R Charger over voltage interrupt, active if ChOv is rising. Software or hardware watchdog is OFF or has not rolled over. 1 Software or hardware watchdog is rollover. 0 Battery voltage is below VCHOFF (see page 12) threshold. 1 Battery voltage has reached VCHOFF threshold. 0 Device temperature is below 110ºC. 1 110ºC temperature threshold ov_temp_110 has been reached. 0 ON key has not been pressed. 1 ON key has been pressed (rising edge). Te ch ni ca am lc s on A te G nt st il lv al id 0 www.austriamicrosystems.com 1.00 43 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.6 Current Sinks The AS3605 contains 5 general purpose current sinks intended to control backlights, buzzers, and vibrators. All current sinks have an integrated protection (VPROTECT) against overvoltage and can therefore also drive inductive loads. The current sinks can also be used as switches to VSS with configurable impedance as indicated in Table 19. Table 19. Current Source Characteristics Min ICURRx curr1_current = 01h - FFh curr2_current = 01h - FFh ICURRx curr3_current = 01h - FFh curr4_current = 01h - FFh curr5_current = 01h - FFh VPROTECT Maximum voltage at pin CURRx to protect driver transistor Typ Max Unit Notes 0.63 160 mA resolution = 0.6275mA 0.16 40 mA resolution = 0.1569mA VBAT + 2.0V V al id Parameter ISINK ≥ 20mA, guaranteed by design lv Symbol 7.6.1 am lc s on A te G nt st il Note: If a voltage higher than VPROTECT is applied to pins CURR1 - CURR5, a current of more than 20mA will flow into the AS3605. This protects the device from voltage rises caused by inductive loads. Current Sink Registers The current sinks are controlled by the registers listed in Table 20. Table 20. Current Sink Register Summary Name Addr. CURR5 Control GPIO Map CURR1 Value CURR2 Value CURR3 Value CURR4 Value CURR Control b7 19h b4 b3 b2 curr5_gpio b1 b0 curr5_ctrl Page 45 24h curr1_current 45 25h curr2_current 45 26h curr3_current 46 27h curr4_current 46 curr4_ctrl 29h CURR GPIO Map b5 - 28h CURR5 Value b6 2Ah curr3_ctrl curr2_ctrl curr1_ctrl curr5_current curr4_gpio curr3_gpio curr2_gpio curr1_gpio 46 47 47 Te ch ni ca Note: For all current sinks, the currx_on signal is controlled with the currx_ctrl bits. www.austriamicrosystems.com 1.00 44 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR5 Control GPIO Map Register (Address 19h). CURR5 Control GPIO Map Bit 1:0 Bit Name Default curr5_ctrl Access 00b R/W Bit Description 00 Pin CURR5 is turned OFF 01 Pin CURR5 is active 1x GPIO control; pin is active when curr5_gpio = 1 al id Addr: 19h If the bits curr5_ctrl = 1x, the following pin is assigned for turning the CURR5 pin ON and OFF. 7:4 - 00b R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA lv curr5_gpio am lc s on A te G nt st il 3:2 NA NA CURR1 Value Register (Address 24h). CURR1 Value Addr: 24h Bit 7:0 Sets the current / resistance of current source CURR1. Bit Name curr1_current Default Access 00h R/W Bit Description 00h Power Down 01h 0.6275mA … FFh 160mA CURR2 Value Register (Address 25h). CURR2 Value Addr: 25h Access ca Default curr2_current 00h R/W Bit Description 00h Power Down 01h 0.6275mA … FFh 160mA Te ch 7:0 Bit Name ni Bit Sets the current / resistance of current source CURR2. www.austriamicrosystems.com 1.00 45 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR3 Value Register (Address 26h). CURR3 Value Addr: 26h 7:0 Bit Name Default curr3_current Access 00h R/W Bit Description 00h Power Down 01h 0.1569mA al id Bit Sets the current / resistance of current source CURR3. … FFh 40mA CURR4 Value Addr: 27h 7:0 Bit Name Default Access Bit Description am lc s on A te G nt st il Bit Sets the current / resistance of current source CURR4. lv CURR4 Value Register (Address 27h). curr4_current 00h R/W 00h Power Down 01h 0.1569mA … FFh 40mA CURR Control Register (Address 28h). CURR Control Addr: 28h 3:2 curr2_ctrl curr3_ctrl ch 5:4 curr1_ctrl Access 00b 00b 00b curr4_ctrl 00b R/W R/W R/W R/W Bit Description 00 Pin CURR1 is turned OFF. 01 Pin CURR1 is active. 1x GPIO control; pin is active when curr1_gpio =1. 00 Pin CURR2 is turned OFF. 01 Pin CURR2 is active. 1x GPIO control; pin is active when curr2_gpio =1. 00 Pin CURR3 is turned OFF. 01 Pin CURR3 is active. 1x GPIO control; pin is active when curr3_gpio = 1. 00 Pin CURR4 is turned OFF. 01 Pin CURR4 is active. 1x GPIO control; pin is active when curr4_gpio = 1. Te 7:6 Default ca 1:0 Bit Name ni Bit Selects software/ hardware control of current sources. www.austriamicrosystems.com 1.00 46 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n CURR5 Value Register (Address 29h). CURR5 Value Addr: 29h Default curr5_current 00h Access R/W Bit Description 00h Power Down 01h 0.1569mA … FFh 40mA CURR GPIO Map Register (Address 2Ah). CURR GPIO Map Addr: 2Ah Bit Name Default Access Bit Description am lc s on A te G nt st il Bit Selects GPIO pin to control current sources. al id 7:0 Bit Name lv Bit Sets the current. If bits curr1_ctrl = 1x, the following pin is assigned for turning the CURR1 pin ON and OFF. 1:0 curr1_gpio 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr2_ctrl = 1x, the following pin is assigned for turning the CURR2 pin ON and OFF. 3:2 curr2_gpio 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr3_ctrl = 1x, the following pin is assigned for turning the CURR3 pin ON and OFF. 00 ca curr3_gpio R/W ch ni 5:4 curr4_gpio Te 7:6 www.austriamicrosystems.com 00 00 GPIO1 01 GPIO2 10 GPIO3 11 NA If bits curr4_ctrl = 1x, the following pin is assigned for turning the CURR4 pin ON and OFF. R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 NA 1.00 47 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n 7.7 Audio Amplifier The integrated Audio Amplifier provides real CD-quality audio and can be used as a headphone amplifier for portable devices. It is designed to meet the operational and power requirements of portable devices by delivering: 1WRMS continuous power into 8Ω differential at 5V supply 2 x 50mWRMS into 32Ω single-ended at 5V supply Total harmonic distortion is less than 0.1% at 1kHz and the quiescent current does not exceed 8mA. al id The Audio Amplifier provides the following operational features: Power supply rejection is always better than 50dB and allows direct connection to noisy batteries, e.g. in TDMA systems. The internal programmable gain can be used for volume and balance control. Only a few external components are required for AC-coupling and reference bypass. Device stability even with high capacitive loads of 1nF and does not require external snubber networks. Inputs are high-impedance in power-down. am lc s on A te G nt st il Figure 16. Audio Amplifier Block Diagram – Stereo Mode 330kΩ AIN_L Audio In Left 100nF lv An internal smooth-rampup circuit ensures pop- and click-less startup without expensive and bulky external relays. aud_gain <4:0> Startup, Biasing, Control Logic Gain Control – AOUT_L ≥100µF + ≥4Ω AGND ≥4Ω 100nF aud_on ≥100µF + aud_lpo ca 100nF Audio In Right AOUT_R 330kΩ Bit aud_stereo (see page 51) = 1 ch ni AIN_R – Te Note: The value of the audio output decoupling capacitors depends on the speaker impedance and the desired minimum output frequency: C = 1/(2xPxfxR) (EQ 2) Where: f = minimum output cutoff frequency, -3dB point. R = speaker impedance in Ω. C = decoupling capacitance in F. www.austriamicrosystems.com 1.00 48 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Figure 17. Audio Amplifier Block Diagram – Differential Mode AIN_L 330kΩ 100nF aud_gain <4:0> Startup, Biasing, Control Logic Gain Control – AOUT_L + AGND lv ≥8Ω 100nF aud_on + aud_lpo AOUT_R – am lc s on A te G nt st il 100nF al id Audio In AIN_R 165kΩ 165kΩ Bit aud_stereo (see page 51) = 0 Table 21. Audio Amplifier Characteristics Parameter Min VDDH Supply Voltage Range (VBAT_3) 3 PSRR Power Supply Rejection Ratio, Differential 70 PSRR Power Supply Rejection Ratio, SingleEnded 50 IOFF Shut Down Current 5.5 V dB 40 100 4 f = 20kHz f = 1kHz f = 20kHz mA aud_lpo = 1 and aud_ib_red = 00 2.7 aud_lpo = 1 and aud_ib_red = 11 8 aud_lpo = 0 and aud_ib_red = 00 3 mA 8 Ω 4 aud_lpo = 1 and aud_ib_red = 00 aud_lpo = 1 and aud_ib_red = 11 1.7 1.00 f = 1kHz aud_lpo = 0 and aud_ib_red = 00 Differential mode Stereo mode 0.1 % POUT = 1W, RLOAD = 8Ω, f = 1kHz, VBAT = 5.5V; Differential 0.5 % POUT = 1W, RLOAD = 8Ω, f = 20kHz, VBAT = 5.5V; Differential 0.05 % POUT = 50mW, RLOAD =32Ω, f = 1kHz, VBAT = 4V; Single-Ended 0.2 % POUT = 50mW, RLOAD =32Ω, f = 20kHz, VBAT = 4V; Single-Ended Total Harmonic Distortion www.austriamicrosystems.com Notes nA 9 ni ch Te THD+N Output Load Unit 50 Supply Current (Stereo Mode) RLOAD Max dB Supply Current (Differential Mode) IVDDH IVDDH Typ ca Symbol 49 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Table 21. Audio Amplifier Characteristics (Continued) Symbol Parameter Min Typ Max Unit Notes dB VBAT=3.7V, not tested, guaranteed per design dB Programmable gain: AOUT/AIN SNR Signal to Noise Ratio 84 91 A0 Gain -22 0 ΔAx Programmable Gain Step-Size lOV_ON Overcurrent On_limit 591 650 744 mA aud_lpo = 0 and aud_ib_red = 00, and aud_overcur = 1. lov_off Overcurrent Off_limit 397 550 650 mA aud_lpo = 0 and aud_ib_red = 00, and aud_overcur is cleared. lov_hyst Overcurrent Hysteresis 20 3 dB al id Current rising into PMOS driver; when 7.7.1 100 mA Audio Amplifier Registers am lc s on A te G nt st il Bit definition for Audio amplifier registers are given below. lv Current decreasing in PMOS driver; when Audio Control Register (Address 2Bh). Audio Control Addr: 2Bh Bit Configures the Audio Amplifier. Bit Name Default Access Bit Description Activates the Audio Amplifier. aud_on 0 0 R/W 0 Audio amplifier off; inputs AIN_L and AIN_R are highimpedance. 1 Audio amplifier on. Select Low-Power Operation; reduced output power. 1 aud_lpo 0 R/W 0 Use for speakers < 32Ω (nominal impedance) in stereo mode; < 64Ω differential. 1 Use for speakers ≥ 32Ω (nominal impedance) in stereo mode; ≥ 64Ω differential. aud_ib_red 00b R/W ni 3:2 ca Reduced bias current into Audio Amplifier circuit. aud_gain www.austriamicrosystems.com 0000b Use for speakers < 8Ω (nominal impedance) in stereo mode; < 16Ω differential. 01 NA 10 NA 11 Use for speakers ≥ 8Ω (nominal impedance) in stereo mode; ≥ 16Ω differential. Audio Amplifier gain adjust. ch Te 7:4 00 R/W 0000 Output off 1000 0dB 0001 -22dB 1001 +2dB 0010 -19dB 1010 +5dB 0011 -16dB 1011 +8dB 0100 -13dB 1100 +11dB 0101 -10dB 1101 +14dB 0110 -7dB 1110 +17dB 0111 -4dB 1111 +20dB 1.00 50 - 73 AS3605 1v2 Data Sheet - D e t a i l e d D e s c r i p t i o n Audio Control 2 Register (Address 41h). Audio Control 2 Addr: 41h Bit Configures the Audio Amplifier. Bit Name Default Access Bit Description Selects audio mode. 1 aud_overcur 0 R/W R 0 Differential mono mode (connect pin AIN_R to pin AOUT_L) 1 Stereo mode. 0 Normal operation; audio output current below limit of lOV_ON. 1 Audio output current exceeds limit (lOV_ON). al id 1 aud_stereo lv 0 Audio amplifier output pulldown control; active if aud_on=0. aud_pulldwn - R/W 01 0.6mA 10 1.2mA 11 2.5mA NA Na Te ch ni ca 7:4 00b 30µA am lc s on A te G nt st il 3:2 00 www.austriamicrosystems.com 1.00 51 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8 System Supervisory Functions 8.1 Reset XRES is an active low bi-directional pin; an external pullup to LDO VANA_1 has to be added (see Digital Input/Output DC/AC Characteristics on page 61). During each reset cycle the following states are controlled by the AS3605: Pin XRES is Forced to GND al id Programmable Power-off Function Programmable Power-on Sequence and Regulator Voltages Programmable Reset Timer All Register bits Set to Default Values after Power-On (except the Audio Control 2 (page 51), the Interrupt Status (page 43). 8.1.1 lv Note: Programming is controlled by the internal OTP-ROM. Reset Conditions Reset can be activated from 7 different sources: Low Battery Power Off Mode Software Forced Reset am lc s on A te G nt st il Power On (Battery or Charger Insertion) Externally Triggered through the XRES Pin Overtemperature Watchdog Momentary Power Loss Detection Power On (Battery or Charger Insertion). There are two types of voltage dependent resets: VPOR – Monitors the voltage on pin V2_5. LDO V2_5 uses the voltage VCHARGER or VBAT as its source. VRESET – Monitors the voltage on VBAT pins. Pin XRES is only released if V2_5 > VPOR and VBAT > VRESETRISE. Low Battery. A reset is automatically generated if VBAT drops below VRESETFALLING for a minimum period (VRESETMASk). Table 22. Reset Levels Parameter ca Symbol Overall power on reset VRESETRISE Reset level for VBAT rising ni VPOR Min Typ Max Unit 1.5 2.0 2.3 V Monitor voltage on pin V2_5; power on reset for all internal functions. Pin RESET stays low until V2_5 > VPOR 3.1 V Monitor voltage on pin VBAT; rising level. Monitor voltage on pin VBAT; falling level. 1 Reset level for VBAT falling 2.8 V VRESETMASK Mask time for VRESETFALLING 40 µs TPOWERLOSS Interval for recovery of power loss on VBAT 100 250 500 ms Duration for VBAT < VRESETFALLING until a reset 2 cycle is started . If the duration of a power loss on VBAT is below this duration, the system will restart Te ch VRESETFALLING Notes 1. VRESETFALLING is only accepted if the reset condition is longer than VRESETMASK. This guard time is used to avoid a complete reset of the system in case of short drops of VBAT. 2. VRESET signal is debounced with the specified mask time for rising- and falling-slope of VBAT. The default time is 40µs and it can be programmed from 0µs to 200µs with the register reset-mask timer. www.austriamicrosystems.com 1.00 52 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Power Off. Setting bit power_off = 1 puts the AS3605 into ultra low-power mode. To start a complete reset cycle, the AS3605 waits until the external pin ON is pulled high, the Battery Charger is inserted, or level VPOR is reached. Bit power_off is automatically cleared by this reset cycle. During power off state, all circuits are turned off except LDO V2_5, thus the current consumption of the AS3605 is reduced to less than 10µA. The digital part is supplied by LDO V2_5, all other circuits are turned off in this mode, including internal references and oscillator. Note: All registers except the Reset Control on page 53 are set to their default value after power-on. Software Forced Reset. Setting bit force_reset = 1 immediately initiates a reset cycle, and is automatically cleared during a reset. al id External Triggered Reset. If the pin XRES is pulled from high to low by an external source (microprocessor or button) a reset cycle is initiated. Overtemperature Reset. The reset cycle can be started by overtemperature conditions (see page 55). Watchdog Reset. If the Watchdog is armed (bit wtdg_on = 1 and bit wtdg_res_on = 1) and the timer expires, a reset is initiated. Refer to 8.1.2 lv page 57 for information about the Watchdog block. Reset Registers am lc s on A te G nt st il Bit definition for Reset registers are given below. Reset Control Register (Address 3Ah). Reset Control Addr: 3Ah Controls reset and power off. Bit Bit Name 0 force_reset 1 power_off Default Access 0 R/W 0 R/W Bit Description 0 Normal operation. 1 Initiates a complete reset cycle. 0 Normal operation. 1 Initiates power-off mode where all LDOs are turned off except LDO V2_5. The AS3605 waits for a rising edge on pin ON or until the battery charger is detected. Static indication of ON input pin. 2 on_input 0 R 0 ON input pin is low. 1 ON input pin is high (external ON key depressed). 0h ni reset_reason R Te ch 5:3 ca Indicates to the software the reason for the most recent reset. 6 tmp_ pwr_loss 0 R 7 - NA NA www.austriamicrosystems.com 000 VPOR was reached (initial battery or charger insertion) 001 VRESETFALLING was reached (VBAT < 2.75V) 010 Software forced by bit force_reset 011 Software forced by bit power_off and a Battery Charger detected 100 Software forced by bit power_off and ON was pulled high 101 Externally triggered through pin XRES 110 Reset caused by overtemperature T140 111 Reset caused by Watchdog 0 Normal startup. 1 A momentary power loss condition was detected. 1.00 53 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Reset Timer Register (Address 13h). Reset Timer Addr: 13h Bit Sets the RESET timer value. Bit Name Default Access Bit Description OTP R/W 001 RESTIME = 10ms 010 RESTIME = 20ms 011 RESTIME = 30ms 100 RESTIME = 40ms 101 RESTIME = 50ms 110 RESTIME = 60ms 111 RESTIME = 70ms lv res_timer RESTIME = 0ms am lc s on A te G nt st il 2:0 000 al id Set RESTIME Set MASKTIME 5:3 reset_mask_timer 7:6 8.1.3 - Reset Cycle OTP R/W NA 000 MASKTIME = 0µs 001 MASKTIME = 5µs 010 MASKTIME = 10µs 011 MASKTIME = 40µs 100 MASKTIME = 80µs 101 MASKTIME = 120µs 110 MASKTIME = 160µs 111 MASKTIME = 200µs NA During a reset cycle, pin XRES is forced low for at least the time specified by bits res_timer and then all register bits are set to their default values except bit ov_temp_140. 8.1.4 ca During the reset time, a normal startup is initiated (refer to Startup on page 55) and the reset is active until the reset timer (set by bits res_timer) expires. The voltage on pin XRES is then pulled high by the external resistor and the whole system is leaving the reset state. res_con: Reset Control Te ch ni Reset is internally generated from a power on detection circuit (see page 52) and provided to the internal logic as well as externally through the open-drain pin XRES. This pin can also be forced externally by pulling it low. Additionally Reset can be forced by software by setting bit force_reset = 1. www.austriamicrosystems.com 1.00 54 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.2 Startup 8.2.1 Normal Startup During a normal reset cycle (see page 52), after V2_5 is above VPOR and VBAT is above VRESETRISE, a normal startup is initiated as follows: Programmable Startup Sequences The start-up sequnece is factory programmed. For more details please contact austriamicrosystems AG. 8.2.3 Startup from Battery Charger lv 8.2.2 al id 1. The external capacitor on pin CREF is charged to 1.8V. 2. The DC/DC converters and LDOs are sequentially powered up according to the Boot OTP configuration. 3. Depending on the Boot OTP setting (Auto-Shutdown): a) The AS3605 enters shutdown mode if no momentary power loss is detected (only valid through initial start-up, not during a reset cycle). -orb) The Reset-Timer is set by the Boot OTP and the reset is released when the Reset-Timer expires (pin XRES is pulled high). am lc s on A te G nt st il If the voltage on pin VCHARGER is within VSTARTCHARGER, the Battery Charger is started in all cases, even with VBAT = 0V. This allows the battery to be charged (even from deep discharge) and a normal startup to proceed. Table 23. Battery Charger Startup Conditions Symbol VSTARTCHARGER Parameter Min Typ Max Unit Voltage on pin VCHARGER for the AS3605 to start 4.35 5.0 15 V Notes On pin VCHARGER. 8.3 Protection Functions The Step Down DC/DC Converter, and all LDOs have integrated overcurrent protection. Overtemperature protection of the AS3605 is also builtin and can be activated with the serial interface bit temp_pmc_on. The AS3605 has two temperature indicators: ov_temp_110 – Automatically reset if the overtemperature condition is removed. ov_temp_140 – Must be reset via the serial interface with bit rst_ov_temp_140. If ov_temp_140 is set, an automatic reset of the complete AS3605 is initiated. Bit ov_temp_140 is not cleared by this reset cycle to indicate the reason for this (unexpected) shutdown. It must be cleared intentionally by bit rst_ov_temp_140. The cause of this reset is stored in the Reset Control (page 53). This allows a detection of the reset cause, after the device has restarted. 8.3.1 TMP_SV: Temperature Supervision ca The AS3605 includes an integrated temperature sensor, implemented to provide overtemperature protection of the device. It generates flags linked to the two temperature thresholds: ni T110 – 110º threshold. Sets ov_temp_110, signalling the 110º overtemperature condition. Thus software can react and shut down powerconsuming functions in order to decrease the device’s temperature. Te ch T140 – 140º threshold. Reaching this temperature level generates a Reset, when temp_pmc_on is enabled. This sets all regulators into power-down mode and stops battery charging. www.austriamicrosystems.com 1.00 55 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.3.2 Overtemperature Detection Table 24. Overtemperature Detection Parameters Parameter T110 ov_temp_110 Rising Threshold T140 ov_temp_140 Rising Threshold Thyst ov_temp_110 and ov_temp_140 Hysteresis Typ Max Unit 95 110 125 ºC 203 230 257 ºF 125 140 155 ºC 257 284 311 5 lv Overtemperature Control Addr: 3Bh am lc s on A te G nt st il Device temperature supervision. Bit Name ºF ºC Overtemperature Detection Register Overtemperature Control Register (Address 3Bh). Bit Min al id 8.3.3 Symbol Default Access Bit Description Activates/deactivates temperature supervision. Default: Off - all other bits are only valid if set to 1. 0 1 temp_pmc_on ov_temp_110 0 0 R/W R 0 Temperature supervision is disabled. No reset will be generated when the device temperature exceeds 140ºC. 1 Temperature supervision is enabled. 1 Warning flag indicating that the device temperature has exceeded 110ºC. 1 Indicates that the device overtemperature has exceeded 140ºC. This bit is not cleared by the automatic reset caused by this flag. It must be cleared using bit rst_ov_temp_140. ov_temp_140 0 R 3 rst_ov_temp_140 0 R/W Used to clear bit ov_temp_140; first set this bit = 1 and then set it =0. 4 temp_test0 0 R/W Only used for production; must always be set to 00. 5 temp_test1 0 R/W 6 tco_110_a 0 R Only used for production – direct output of T110 comparator. 7 tco_140_a R Only used for production – direct output of T140 comparator. ca 2 Te ch ni 0 www.austriamicrosystems.com 1.00 56 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.4 Watchdog Block The AS3605 includes a Watchdog block to detect a deadlock of the connected controller. If the Watchdog block is active (wtdg_on = 1), it must get a continuous trigger signal within a programmable timer window. If there is no signal for a certain time period from a defined GPIO pin or bit wtdg_sw_sig, the Watchdog block starts either a complete reset – bit wtdg_res_on must be set to 1 – or sets interrupt flag wdog_i. The Watchdog timer window is defined by bits: al id wtdg_min_timer wtdg_max_timer The trigger signal can be configured using bits: wtdg_trigger wtdg_sw_sig – Watchdog is reset by software lv wtdg_gpio_input – Watchdog is reset by hardware (GPIO) 8.4.1 am lc s on A te G nt st il Any of the general purpose input/outputs can be configured as inputs using bit wtdg_gpio_input, and outputs using bits gpio1_out_src, gpio2_out_src, or gpio3_out_src = 11, for the Watchdog. While the GPIO input must be continuously re-triggered in order to avoid a Watchdog interrupt, the GPIO output will generate in interrupt when the Watchdog runs over – wdog_int_en. Watchdog Registers The Watchdog is controlled by the registers listed in Table 25. Table 25. Low Dropout Regulators Register Summary Name Addr Watchdog Control b7 b6 2Eh Watchdog_min Timer Watchdog_max Timer Watchdog Software Signal b5 b4 wtdg_ trigger - b3 wtdg_gpio_input 2Fh wtdg_min_timer 30h wtdg_max_timer 31h b2 b1 b0 Page wtdg_ res_on wtdg_on 57 - wtdg_ sw_sig 58 58 58 Watchdog Control Register (Address 2Eh). Watchdog Control Addr: 2Eh Controls the Watchdog block. Bit Name 0 wtdg_on Access 0 R/W ni wtdg_res_on 1 Bit Description 0 Disables the Watchdog block. 1 Enables the Watchdog block. If the Watchdog expires and this bit = 1, a reset cycle will be started. Refer to page 52 for information about reset cycles. R/W 0 A watchdog overflow does not generate a reset. 1 A watchdog overflow generates a reset. Te ch 1 Default ca Bit www.austriamicrosystems.com 1.00 57 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Watchdog Control Addr: 2Eh Bit Controls the Watchdog block. Bit Name Default Access Bit Description 3:2 wtdg_gpio_input 00 R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 Do not use this setting. Select type of trigger (software or hardware). 7:5 0 - NA R/W 0 Use bit wtdg_sw_sig as trigger signal for the Watchdog. 1 Use the pin defined by bit wtdg_gpio_input as trigger signal for the Watchdog. lv wtdg_trigger NA am lc s on A te G nt st il 4 al id Specifies the input pin of the Watchdog if bit wtdg_trigger = 1. Watchdog_min Timer Register (Address 2Fh). Watchdog_min Timer Addr: 2Fh Sets the minimum Watchdog trigger time. Bit 7:0 Bit Name wtdg_min_timer Default 00h Access R/W Bit Description 00h 0s 01h 16ms … FFh 4.08s Watchdog_max Timer Register (Address 30h). Watchdog_max Timer Addr: 30h Default wtdg_max_timer FFh Access Bit Description 01h R/W 16ms … FFh 4.08s Caution: Do not set these bits = 00h ni 7:0 Bit Name ca Bit Sets the maximum Watchdog trigger time. ch Watchdog Software Signal Register (Address 31h). Addr: 31h Bit Name Te Bit 0 7:1 Watchdog Software Signal Resets the Watchdog block by software. Default Access Bit Description Trigger input by the serial interface if wtdg_trigger = 0 wtdg_sw_sig - www.austriamicrosystems.com 0 NA R/W 0 Force watchdog trigger = low (see Figure 18) 1 Force watchdog trigger = high (see Figure 18) NA 1.00 58 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s Figure 18. Watchdog Timing Diagram tMAX al id tMIN wtdg_trigger tMIN am lc s on A te G nt st il lv tMAX 8.5 Internal Reference Circuits The internal reference circuits (V, I, fCLK) require the external components listed in Table 26. Table 26. Reference External Components Symbol Parameter Min Typ Max Unit Notes -20% 100 +20% nF Ceramic low-ESR capacitor between pins CREF and VSS Parameter Min Typ Max Unit Notes VCEXT Reference voltage -1% 1.8 +1% V Low noise trimmed voltage reference - connected to pin CREF; do not load. fCLK Internal reference clock 1.0 1.1 1.2 MHz CEXT External filter capacitor Table 27. References Characteristics Symbol Trimmed clock reference Te ch ni ca To reduce the current consumption of the AS3605, internal references circuits can be set into a special low-power mode with bit low_power_on. www.austriamicrosystems.com 1.00 59 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.5.1 Internal Reference Registers References Control Register (Address 2Dh). References Control Addr: 2Dh Configures low-power mode. 0 Bit Name low_power_on Default 0 Access Bit Description 0 Standard mode or controlled by GPIO, if low_power_gpio_on = 1. 1 Low-power mode; all parameters except noise (see LDO parameters, section 7.3) are still valid. R/W al id Bit low_power_gpio_on 0 R/W 0 Low-power mode disabled for GPIO control. 1 Low-power mode is activated by GPIO pin (low_power_gpio). low_power_on must be enabled. am lc s on A te G nt st il 1 lv If set and low_power_on = 0 then the low-power mode is controlled by a GPIO pin. Specifies the pin to be used as GPIO control. 3:2 4 low_power_gpio low_power_gpio_pol 7:5 - 00 0 NA R/W 00 GPIO1 01 GPIO2 10 GPIO3 11 GPIO3 0 Low-power mode is activated. If the selected GPIO input, bit low_power_gpio = 1. 1 Low-power mode is activated. If the selected GPIO input, bit low_power_gpio = 0. R/W NA 8.6 Low Power Mode ca Bit low_power_on controls low-power mode. In low-power mode the integrated voltage reference and the temperature supervision comparators operate in pulsed mode. This reduces the quiescent current of the AS3605 by 45µA (typical). Because of the pulsed function, the LDO output noise parameters do not meet the specification in low-power mode but the full functionality is still available. Te ch ni Note: Low-power mode can be activated by hardware using one of the GPIO pins, or by software by setting bit low_power_on = 1. www.austriamicrosystems.com 1.00 60 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.7 Serial Interface 8.7.1 Digital Input/Output DC/AC Characteristics VBAT_1 is used as supply voltage of the pins. Table 28. DC Characteristics Input Pin SCK Parameter Min Max Unit VIH High-Level Input Voltage 1.5 VBAT V VIL Low-Level Input Voltage 0.4 V ILEAK Input Leakage Current -5 5 µA Max Unit Notes al id Symbol to VBAT_1 and GND_PAD Table 29. DC Characteristics Open Drain Pin SDA Parameter Min VIH High-Level Input Voltage 1.5 VIL Low-Level Input Voltage ILEAK Input Leakage Current VOL CLOAD V V am lc s on A te G nt st il 0.4 Notes lv Symbol 5 µA to VBAT_1 and GND_PAD Low-Level Output Voltage 0.2 V at 4.0mA Capacitive Load 50 pF Max Unit -5 Table 30. DC Characteristics Input/Output Open Drain Pin XRES Symbol Parameter Min VIH High-Level Input Voltage 1.5 VIL Low-Level Input Voltage ILEAK Input Leakage Current VOL CLOAD 0.4 V 5 µA to VANA_1 and GND_PAD Low-Level Output Voltage 0.2 V at 4mA Capacitive Load 50 pF External Pullup Resistor 100k Ω -5 Connect to <=VBAT_1 Te ch ni ca RPULLUP Notes V www.austriamicrosystems.com 1.00 61 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 8.7.2 I2C Compatible Serial Interface 2 The following pins are used for the I C interface: SDA = I/O Pin SCK = Input Pin I2C Features. Listed below are I2C features: al id Fast-mode capability (max. SCL-frequency is 400 kHz @ 100pF capacitive load) 7-bit addressing mode Write formats:Single-Byte-Write, Page-Write Read formats:Current-Address-Read, Random-Read, Sequential-Read lv SDA input delay and SCL spike filtering by integrated RC-components I2C Slave Addresses. The AS3605 device address is fixed at 82h for write commands and 83h for read commands. SDA SCK S 1-7 Address 8 R/W 9 ACK 1-7 8 9 Data ACK 1-7 Data 8 9 ACK P Stop Condition Te ch ni ca Start Condition am lc s on A te G nt st il Figure 19. Complete Data Transfer www.austriamicrosystems.com 1.00 62 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s I2C Data Transfer Formats. Definitions used in the serial data transfer format diagrams (Figures 20 - 24) are listed in Table 31. 2 Table 31. I C Data Transfer Byte Definitions Definition R/W (AS3605 Slave) Notes S Start condition after stop R 1 bit Sr Repeated start R 1 bit DW Device address for write R 1000 0010 (82h) DR Device address for read R 1000 0011 (83h) WA Word address R 8 bit A Acknowledge W 1 bit N No acknowledge R 1 bit reg_data Register data/write R data (n) Register data/read R P Stop condition R WA++ Increment word address internally lv 8 bit 1 bit 8 bit am lc s on A te G nt st il 2 Figure 20. I C Byte Write al id Symbol S DW A R WA A During acknowledge reg_data A P Write Register WA++ AS3605 (= slave) receives data AS3605 (= slave) transmits data 2 DW A WA A reg_data 1 A reg_data 2 Write Register WA++ A … Write Register WA++ reg_data n A P Write Register WA++ ch S ni ca Figure 21. I C Page Write Te AS3605 (= slave) receives data AS3605 (= slave) transmits data Byte Write and Page Write formats are used to write data to the slave. The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is free). The devicewrite address is followed by the word address. After the word address any number of data bytes can be sent to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address locations. www.austriamicrosystems.com 1.00 63 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s For reading data from the slave device, the master has to change the transfer direction. This can be done either with a repeated START condition followed by the device-read address, or simply with a new transmission START followed by the device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte transmitted from the slave. In Read Mode any number of subsequent register bytes can be read from the slave. The word address is incremented internally. The following diagrams show some of the serial read formats supported by the AS3605. 2 DW A WA A Sr DR A data Read Register WA++ am lc s on A te G nt st il AS3605 (= slave) receives data AS3605 (= slave) transmits data N P lv S al id Figure 22. I C Random Read Random Read and Sequential Read are combined formats. The repeated START condition is used to change the direction after the data transfer from the master. The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition is followed by the device-write address and the word address. In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the slave transmits register data located by the previous received word address vector. The master responds to the data byte with a not-acknowledge, and issues a STOP condition on the bus. 2 ca Figure 23. I C Sequential Read S DW A WA A Sr DR A data N P Read Register WA++ ch ni AS3605 (= slave) receives data AS3605 (= slave) transmits data Te Sequential Read is the extended form of Random Read, as more than one register-data bytes are transferred subsequently. In difference to the Random Read, for a sequential read the transferred register-data bytes are responded by an acknowledge from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the word-address counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and generate the STOP condition subsequently. www.austriamicrosystems.com 1.00 64 - 73 AS3605 1v2 Data Sheet - S y s t e m S u p e r v i s o r y F u n c t i o n s 2 Figure 24. I C Current Address Read DR A data 1 A Read Register WA++ data 2 … Read Register WA++ A data n Read Register WA++ lv AS3605 (= slave) receives data AS3605 (= slave) transmits data N P al id S Te ch ni ca am lc s on A te G nt st il To keep the access time as small as possible, this format allows a read access without the word address transfer in advance to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address. Analogous to Random Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous to Sequential Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data byte and a subsequent STOP condition. www.austriamicrosystems.com 1.00 65 - 73 AS3605 1v2 Data Sheet - R e g i s t e r M a p 9 Register Map The AS3605 registers along with their addresses and default values are listed in Table 32. Fields marked NA are not used; reading these bits may result in 0s or 1s. Always use 0s, when writing to these bits. Caution: Do not write to addresses not listed in Table 32. Table 32. Register Summary Addr Default b7 b6 b5 b4 b3 b2 b1 b0 al id Register Step Down Voltage/ Test Modes 01h 00h LDO_RF1 Voltage 02h 00h - ldo_rf1_v LDO_RF2 Voltage 03h 00h - ldo_rf2_v LDO_RF3 Voltage 04h 00h - ldo_rf3_v LDO_RF4 Voltage 05h 00h - ldo_rf4_v LDO_ANA2_Voltag e 06h LDO_ANA1_Voltag e 07h LDO_SIM_Voltage 08h Reg Power 09h LDO_GPIO Active 0Fh LDO_RF Switch 10h LDO_AD GPIOx 11h LDO_RF GPIOx 12h Reset Timer 13h ChargerControl1 14h ChargerControl2 16h Step Down Config 17h Charge Pump Control Onkey Pulldown 18h CURR5 Control GPIO Map 19h GPIO1 Control 1Ah 00h gpio1_out_src gpio1_invert gpio1_pulls gpio1_low_ curr gpio1_mode GPIO2 Control 1Bh 00h gpio2_out_src gpio2_invert gpio2_pulls gpio2_low_ curr gpio2_mode GPIO3 Control 1Ch 00h gpio3_out_src gpio3_invert gpio3_pulls gpio3_low_ curr gpio3_mode Interrupt Enable 1Fh FEh Interrupt Status 20h NA GPIO Signal 21h NA buck_v am lc s on A te G nt st il 00h - ldo_ana2_v 00h - ldo_ana1_v 00h NA 00h 00h 00h ldo_sim_v - - buck_on - ldo_rf4_on ldo_rf3_on - ldo_rf2_on ldo_rf1_on 00h ldo_rf4_gpio_sel 00h - ChOvEn 58h ChOv ldo_rf3_gpio_sel TrickleCurrent[1:0] ChOvH ana2_sw ana1_sw buck_gpio_sel ldo_rf2_gpio_sel ldo_rf1_gpio_sel res_timer ConstantCurrent[3:0] ChEn - Li4v2 resume_dis able - buck_lpo - - buck_psw buck_dis_n buck_nsw _on _on cp_freq cp_mode_s witching 00h buck_dis_c buck_dis_p urmin on 00h onkey_pulld cp_auto_on cp_start_de bounce _off 00h ldo_ana2_ ldo_ana1 on _on ldo_ana2_gpio_sel reset_mask_timer ca EDh - EOCCurrent[1:0] - ni www.austriamicrosystems.com ldo_sim_on ldo_rf4_gpi ldo_rf3_gpi Ldo_rf2_gp ldo_rf1_gpi ldo_ana2_ buck_gpio o o io o gpio - 00h ch Te lv - - cp_mode[1:0] curr5_gpio cp_on curr5_ctrl chgov_int_ chgrmv_int resume_int chdet_int_e onkey_int_ ovtmp_int_ eoc_int_e wdog_int_ en _en _en n en en n en chgov _i chgrmv_i resume_i - 1.00 chdet_i onkey_i ovtmp_i eoc_i wdog_i gpio3 gpio2 gpio1 66 - 73 AS3605 1v2 Data Sheet - R e g i s t e r M a p Table 32. Register Summary b7 b6 b5 b4 b3 GPIO Frequency Control High Time 22h 00h gpio_h_time GPIO Frequency Control Low Time 23h 00h gpio_l_time CURR1 value 24h 00h curr1_current CURR2 value 25h 00h curr2_current CURR3 value 26h 00h curr3_current CURR4 value 27h 00h curr4_current CURR control 28h 00h CURR5 value 29h 00h CURR GPIO map 2Ah 00h Audio Control 2Bh References Control 2Dh Watchdog Control 2Eh Watchdog_min Timer 2Fh Watchdog_max Timer 30h Watchdog Software Signal 31h ChargerStatus 35h CP Mode Switch 36h Curr Low Voltage Status 37h Reset Control 3Ah Overtemperature Control 3Bh 00h tco_140_a tco_110_a ASIC ID 1 3Dh 33h 0 0 3Eh 53h 41h 0h b1 curr2_ctrl b0 curr1_ctrl curr3_gpio curr2_gpio curr1_gpio am lc s on A te G nt st il curr4_gpio 00h aud_gain aud_ib_red aud_lpo aud_on 00h NA low_power _gpio_pol low_power_gpio low_power low_powe _gpio_on r_on 02h NA wtdg_trigge r wtdg_gpio_input wtdg_res_ wtdg_on on 00h wtdg_min_timer FFh wtdg_max_timer 00h NA NA - NoBat EOC CVM Trickle - ChAct wtdg_sw_ sig ChDet NA - curr5_on_c curr4_on_c curr3_on_c curr2_on_ curr1_on_ p p p cp cp NA - curr5_low_ curr4_low_ curr3_low_ curr2_low curr1_low volt volt volt _volt _volt NA tmp_ pwr_loss ca 0h ch Audio Control 2 curr3_ctrl curr5_current ni ASIC ID 2 curr4_ctrl b2 al id Addr Default lv Register reset_reason on_input power_off force_res et ov_temp_1 ov_temp_ temp_pm temp_test1 temp_test0 rst_ov_tem p_140 40 110 c_on 1 1 0 0 1 1 Rev - aud_pulldwn aud_overc aud_stere urr o Te Read Only www.austriamicrosystems.com 1.00 67 - 73 AS3605 1v2 Data Sheet - E x t e r n a l P a r t s L i s t 10 External Parts List The recommended specifications for external components (refer to Figure 1 and Figure 2) are listed below. Table 33. External Parts Specification Min Typ C2 Max 470nF Tol. Min Rating Min Remarks ±20% 6.3V Ceramic, X5R (Charge Pump) 0603 0603 C3 1µF 4.7µF ±20% 6.3V Ceramic, X5R (V5_6) C4 1µF 4.7µF ±20% 6.3V Ceramic, X5R (VANA_1) ±20% 6.3V Ceramic, X5R (VBAT_1) C5 1µF Package Min al id Part 0603 0603 C6 1µF 4.7µF ±20% 6.3V Ceramic, X5R (VANA_2) C7 1µF 2.2µF ±20% 6.3V Ceramic, X5R (V2_5) C8 1µF 4.7µF ±20% 6.3V Ceramic, X5R (VRF_1) ±20% 6.3V Ceramic, X5R (VBAT_4) 4.7µF ±20% 6.3V Ceramic, X5R (VRF_2) 4.7µF ±20% 6.3V Ceramic, X5R (VRF_3) 0603 4.7µF ±20% 6.3V Ceramic, X5R (VRF_4) 0603 ±20% 6.3V Ceramic, X5R (VBAT_2) 0603 ±20% 6.3V Ceramic, X5R (VBUCK) ±20% 6.3V Ceramic, X5R (VSIM) ±20% 6.3V Tantalum; L Stereo Decoupling Cap. ±20% 6.3V Tantalum; R Stereo Decoupling Cap. ±20% 6.3V Ceramic, X5R (VBAT_3) 0603 ±20% 6.3V Ceramic, X5R (Decoupling, AIN_L) 0402 ±20% 6.3V Ceramic, X5R (Decoupling, AIN_R) 0402 ±20% 6.3V Ceramic, X5R (AGND) 0402 ±20% 6.3V Ceramic, X5R (VCHARGER) 0603 ±20% 6.3V X5R; all VBAT Caps. Combined 0603 ±20% 6.3V Ceramic, X5R (CREF) 0402 C10 1µF C11 1µF C13 1µF C16 1µF C18 10µF C19 100nF C20 100µF C21 100µF C22 1µF C23 100nF C24 100nF C25 100nF C26 1µF 4.7µF C27 10µF 1206 lv 1µF am lc s on A te G nt st il C9 0603 0603 0603 0603 0402 100nF R4 50mΩ 100mΩ 150mΩ ±1% Shunt resistor 0603 R5 100k ±10% Reset Pullup Resistor 0201 L2 2.2µH ±20% Recommended type: Coiltronics SD-12-2R2 ni PBSS301PD or similar Charger Transistor Te ch Q1 ca C29 www.austriamicrosystems.com 1.00 68 - 73 AS3605 1v2 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s 11 Package Drawings and Markings Te ch ni ca am lc s on A te G nt st il lv al id Figure 25. QFN40 (5x5mm) Drawings and Dimensions www.austriamicrosystems.com 1.00 69 - 73 AS3605 1v2 Data Sheet - P a c k a g e D r a w i n g s a n d M a r k i n g s am lc s on A te G nt st il lv al id Figure 26. QFN Marking Table 34. Package Code YWWZZZ YY year WW X ZZ working week assembly / packaging plant identifier free choice Table 35. Start-up Revision Code xx FF engineering samples, no sequence programmed or sequence programmed on request customer specified sequence programmed during production test Te ch ni ca xx Sequence www.austriamicrosystems.com 1.00 70 - 73 AS3605 1v2 Data Sheet - R e v i s i o n H i s t o r y Revision History Revision Date Owner 1.0 March, 2011 pkm Description first official release Te ch ni ca am lc s on A te G nt st il lv al id Note: Typos may not be explicitly mentioned under revision history. www.austriamicrosystems.com 1.00 71 - 73 AS3605 1v2 Data Sheet - O r d e r i n g I n f o r m a t i o n 12 Ordering Information The devices are available as the standard products shown in Table 36. Table 36. Ordering Information Marking Description Delivery Form Package AS3605-BQFR-FF T1V2-FF Multi Standard PMU - Engineering Samples Tray QFN40 5x5mm AS3605-BQFP-xx T1V2-xx Multi Standard PMU - Production Parts Programmed Tape and Reel (in dry pack) QFN40 5x5mm Technical Support is found at http://www.austriamicrosystems.com/Technical-Support Te ch ni ca am lc s on A te G nt st il For further information and requests, please contact us mailto:[email protected] or find your local distributor at http://www.austriamicrosystems.com/distributor lv Note: All products are RoHS compliant and austriamicrosystems green. Buy our products or get free samples online at ICdirect: http://www.austriamicrosystems.com/ICdirect al id Ordering Code www.austriamicrosystems.com 1.00 72 - 73 AS3605 1v2 Data Sheet - C o p y r i g h t s Copyrights Copyright © 1997-2011, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. al id Disclaimer lv Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. ca am lc s on A te G nt st il The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information ni Headquarters ch austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel: +43 (0) 3136 500 0 Fax: +43 (0) 3136 525 01 Te For Sales Offices, Distributors and Representatives, please visit: http://www.austriamicrosystems.com/contact www.austriamicrosystems.com 1.00 73 - 73 ">
/
Downloaden
Even een vriendelijke herinnering. U kunt het document hier bekijken. Maar het belangrijkste is dat onze AI het al heeft gelezen. Het kan complexe dingen in eenvoudige bewoordingen uitleggen, uw vragen in elke taal beantwoorden en u helpen snel te navigeren, zelfs in de langste of meest ingewikkelde documenten.
Openbare link bijgewerkt
De openbare link naar uw chat is bijgewerkt. You may view and manage your chat links after registration here.
Openbare link document
Advertentie
