AMS AS3654 Datasheet

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austriamicro systems .
AS3654 Preliminary Data Sheet, Confidential
Power
Audio Management
for Portable
Power and
Management
Unit for XMUnit
Satellite
radio Devices
AS3654
Error! Unknown document property name.
Specification, Confidential
1 General Description
-
Wide Battery Supply Range 3.0…5.5V
On-Chip Bandgap Tuning for High Accuracy (±1%)
Current protection
Thermal Protection with internal temperature sensor
0.35μm CMOS Solution
2 Key Features
-
System Control
Audio
-
-
-
Serial Control Interface
On/Off Control Module
Reset Generation for system controller
Programmable Interrupt Controller
-
Low power off mode (9μA; 2.5V LDO on)
-
-
-
Two Digital Audio Inputs (I2S interface)
18 Bit Audio DAC
2.9V low Noise LDO for Audio DAC
Headphone Amplifier Output with GND separation
GND Buffer for Headphone Amplifier
Line/ Headphone output with GND separation
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Power Management Features
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The AS3654 is a highly integrated solution for power supply
generation and monitoring, battery management including
charging. It is controlled via a serial control interface and
integrates all necessary system specific functions such as
clock, reset and interrupt generation, voltage and
temperature monitoring.
-
Supply Voltage Generation
-
-
1 RF Programmable Low Noise LDOs (400mA)
1 RF Programmable Low Noise LDOs (150mA)
2 Programmable Digital Low Power LDOs (200mA)
2 General Purpose PWM DC/DC step up converter
with two programmable current sinks (e.g. for white
led)
3 General Purpose high efficiency DC/DC step down
converter
1 Low noise charge pump with 5V output voltage
1 Ultra Low Power 2.5V LDO (always on)
-
1.6 MHz to 2.3 MHz with 100 kHz steps
3 Applications
-
Power and Audio Management Unit
1 Cell Li+ or 3 Cell NiMH powered devices
Car Battery powered systems with and without
internal battery
4 programmable(6-bit) from 0.625 to 40mA
optional useable as GPIOs
3 programmable high voltage (15V)
(6-bit) from 0.625 to 40mA
ni
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-
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Current sinks
Programmable System clock
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10-bit Successive Approximation ADC
40μs conversation time
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Battery Management
-
Full featured chemistry independent step down
charger with included Gas Gauge and Current
limitation.
-
0.15 Ω Battery switch for start-up during trickle
charging
Integrated USB charger up to 400mA
-
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AS3654
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4 Block Diagram
VBUS
USB
Charger
General
Purpose
ADC
LDO
0.75V-2.5V
Overtemp
Protection
Watchdog
LiIon Battery
Voltage
Monitors /
Reset
Boot ROM
Step Down
Charger
Fuel
Gauge
SDA
AS3654
Power and Audio
Management Unit
Two Wire
Interface
SCL
I2S Input 1
I2S
18bit
DAC
I2S
18bit
DAC
ca
I2S Input 2
LDO
1.85V-3.4V
VRF1
400mA
VRF2
150mA
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Interrupt
Step Down DCDC
(Input 5V-15V/50V)
LDO
0.75V-2.5V
LDO
1.85V-3.4V
VSUPPLY
VCHARGER
ni
GPIO or
Current
Sources
LDO
2.9V
VDAC
Line
Out
LineIn LineOut
Charge
Pump
VCPOUT
5V/100mA
DCDC
Step Up
(Voltage)
VSTEPUP1
DCDC
Step Up
(Voltage or
Current)
VSTEPUP2
Headphone
Out
Headphone
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Four GPIO
or Current
Sources
DCDC
Step Down
VDIG2
200mA
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DCDC
Step Down
VDIG1
200mA
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DCDC
Step Down
3 x 0.6V-3.4V / 500mA
VOUT2
VOUT3
VSUPPLY,
VOUT1-3
VOUT1
VSUPPLY,
VOUT1-3
Figure 1 – AS3654 Application Diagram
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Document Revision History
0V19
all
0V20
all
0V21
all
0V22
- Additional descriptions and updates
- Removed duplicated hp_det bit (register 58, b3)
Typical XON pull up current updated = 5uA,
Charger external components Qpu=BSS84
Added applicationdiagramm, reformatted headings
- Changed VDETECT minimum value to 2mV (dcdc stepup1 load
detection)
- Updated soldering conditions
- Updated pwm_high_time and pwm_low_time settings
- Updated package thickness tolerance from +/-0.1mm to
+0.1/-0.15
Date
Author
21.3.2006
TJE/PTR
24.11.2006
TJE/PTR
12.1.2007
17.12.2007
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Description of Change
TJE/PTR
TJE/PTR
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REV
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AS3654
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Index
Block Diagram ...................................................................................................................................................2
Characteristics ....................................................................................................................................................8
5.1
Absolute Maximum ratings (non operating) ..............................................................................................8
5.2
Operating Conditions .................................................................................................................................9
6 General Description..........................................................................................................................................10
7 Detailed Functional Descriptions .....................................................................................................................11
7.1
Step Up DC/DC Converter.......................................................................................................................11
7.2
Stepup1 load detection and overcurrent protection circuit .......................................................................17
7.3
Current Sinks............................................................................................................................................19
7.3.1
High voltage Current Sinks 40mA (CURR5, DCDC_CURR1 and DCDC_CURR2):.........................................19
7.3.2
Low voltage Current Sink 40mA (CURR1, CURR2, CURR3, CURR4):............................................................20
7.4
General Purpose Input / Output (GPIO) Pins ...........................................................................................21
7.4.1
High Current GPIO Pins (Same pins as Current sinks CURR1…4)..................................................................21
7.5
ADC .........................................................................................................................................................23
7.6
Internal Battery switch (Vsupply , Battery)..............................................................................................25
7.7
Step Down Charger ..................................................................................................................................26
7.8
USB Charger ............................................................................................................................................27
7.9
Battery Charge Controller ........................................................................................................................29
7.9.1
Charge Controller Operating Modes and Building Blocks .................................................................................31
7.9.2
Fuel Gauge........................................................................................................................................................37
7.9.3
Charger Operation.............................................................................................................................................40
7.10 Step Down DC/DC Converter..................................................................................................................41
7.10.1
Typical Performance Characteristics.................................................................................................................45
7.11 Low Dropout Regulators (LDO) ..............................................................................................................46
7.11.1
RF LDO’s (VRF_1 - VRF_2)..............................................................................................................................47
7.11.2
Digital LDO’s (VDIG_1, VDIG_2) ......................................................................................................................48
7.11.3
Low power LDO (V2_5).....................................................................................................................................50
7.12 5V Charge Pump ......................................................................................................................................51
7.13 Audio........................................................................................................................................................53
7.14 Common mode voltage generation of HP_CM, LINE_CM .....................................................................54
7.15 First AudioSet Register ............................................................................................................................54
7.16 Digital Audio Input ..................................................................................................................................55
7.16.1
General..............................................................................................................................................................55
7.16.2
Signal Description .............................................................................................................................................55
7.16.3
Power Save Options..........................................................................................................................................56
7.16.4
Parameter..........................................................................................................................................................56
7.17 Line Input .................................................................................................................................................57
7.17.1
General..............................................................................................................................................................57
7.18 Headphone Output....................................................................................................................................57
7.18.1
Phantom Ground ...............................................................................................................................................57
7.18.2
No-Pop Function ...............................................................................................................................................58
7.18.3
Over-current Protection .....................................................................................................................................58
7.18.4
Headphone Detection........................................................................................................................................58
7.18.5
Power Save Options..........................................................................................................................................58
7.18.6
Register Description ..........................................................................................................................................60
7.19 Line Output ..............................................................................................................................................61
7.19.1
General..............................................................................................................................................................61
7.19.2
No-Pop Function ...............................................................................................................................................61
7.19.3
Power Save Options..........................................................................................................................................61
7.19.4
Parameter..........................................................................................................................................................62
7.19.5
Register Description ..........................................................................................................................................62
7.20 I2C Serial Interface ...................................................................................................................................63
7.21 Reset.........................................................................................................................................................65
7.22 Interrupt Controller ..................................................................................................................................68
7.23 Startup ......................................................................................................................................................71
7.23.1
Programmable Startup Sequences ...................................................................................................................72
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5
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7.23.2
Protection Functions..........................................................................................................................................72
7.23.3
Watchdog ..........................................................................................................................................................73
7.23.4
Internal References (V, I, fclk) ............................................................................................................................75
7.24 ON-Detect ................................................................................................................................................77
8.2
Packaging and Pinout ...............................................................................................................................78
8.2.1
Pin Description ..................................................................................................................................................78
8.3
Registermap..............................................................................................................................................81
8.4
Pinout Drawing (Top view) CTBGA100 9x9mm: ...................................................................................85
8.6
Package and Marking ...............................................................................................................................86
8.6.1
CABGA100_9x9mm 0.8mm pitch(AS 3654) .....................................................................................................86
List of Tables
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Table 1 – Absolute Maximum Ratings...........................................................................................................................................8
Table 2 – Operating conditions......................................................................................................................................................9
Table 3 – DC/DC Converter parameters .....................................................................................................................................12
Table 4 – Step Up DC/DC Bit definitions.....................................................................................................................................16
Table 5 – Step Up Registermap ..................................................................................................................................................17
Table 6 – StepUp1 protection/detection circuit parameters.........................................................................................................17
Table 7 – Low voltage status Bit definitions (stpup1_det and stpup1_oc)..................................................................................18
Table 8 – Step Up protection Registermap .................................................................................................................................18
Table 9 – Current Sinks Characteristics ......................................................................................................................................19
Table 10 – Current Sink Bit definitions ........................................................................................................................................19
Table 11 – Current Sinks Characteristics ....................................................................................................................................20
Table 12 – Current Sink Bit definitions ........................................................................................................................................20
Table 13 – Currentsink registermap ............................................................................................................................................20
Table 14 – High Current GPIO Pin Characteristics (GPIO1…4) .................................................................................................21
Table 15 – GPIO 1…4 Register...................................................................................................................................................21
Table 17 – GPIO Bit Register ....................................................................................................................................................22
Table 18 – PWM Frequency Control High Time Registers........................................................................................................22
Table 19 – PWM Frequency Control Low Time Registers.........................................................................................................22
Table 20 – GPIOs Registermap..................................................................................................................................................23
Table 21 –ADC Characteristics ...................................................................................................................................................23
Table 22 - ADC Bit definitions ....................................................................................................................................................24
Table 23 – ADC register map ......................................................................................................................................................25
Table 24 – Battery switch parameters .........................................................................................................................................25
Table 25 – Battery switch status Bit definitions ...........................................................................................................................25
Table 26 – Battery switch Registermap......................................................................................................................................26
Table 27 – Step down charger parameters .................................................................................................................................26
Table 28 – Step Down Charger control .......................................................................................................................................26
Table 29 – Step down charger Registermap ..............................................................................................................................26
Table 30 – USB-Charger Bit definitions.......................................................................................................................................28
Table 31 – Step down charger Registermap ..............................................................................................................................28
Table 32 – Charger External Components ..................................................................................................................................30
Table 33 – Charger Characteristics.............................................................................................................................................34
Table 34 – Charger Register Overview .......................................................................................................................................35
Table 35 – Charger Status Register ............................................................................................................................................35
Table 36 – Charger Control1 Register.........................................................................................................................................35
Table 37 – Battery Voltage Monitor Register...............................................................................................................................36
Table 38 – Charger Timing Register ...........................................................................................................................................36
Table 39 – Charger Config Register............................................................................................................................................36
Table 40 – Fuel Gauge parameters.............................................................................................................................................37
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Table 41 – Fuel Gauge Register definitions ................................................................................................................................39
Table 42 – Fuel Gauge Bit definitions .........................................................................................................................................39
Table 43 – FG Registermap ........................................................................................................................................................40
Table 44 – Charge Current Regulator parameters ......................................................................................................................40
Table 45 – Charger Register map ...............................................................................................................................................40
Table 46 – Charger Bit definitions ...............................................................................................................................................40
Table 47 – Step Down DC/DC Converter parameters.................................................................................................................43
Table 48 – Step Up DC/DC Bit definitions...................................................................................................................................44
Table 49 – Step down Register map ..........................................................................................................................................46
Table 50 – LDO’s Bit definitions ..................................................................................................................................................46
Table 51 – Analog LDO (VRF_1, VRF_2) Characteristics...........................................................................................................47
Table 52 – LDO_RF Register map ..............................................................................................................................................48
Table 53 – Digital LDO (VDIG_1, VDIG_2) Characteristics.........................................................................................................49
Table 54 – Digital LDO (VDIG_1, VDIG_2) Programming voltage table .....................................................................................49
Table 55 – LDO_DIG Register map ...........................................................................................................................................50
Table 56 – Low power LDO (V2_5) Characteristics ....................................................................................................................50
Table 57 – Charge Pump External Components.........................................................................................................................51
Table 58 – Charge Pump Characteristics....................................................................................................................................51
Table 59 – Charge Pump Bit definitions ......................................................................................................................................52
Table 60 – Charge pump Register map......................................................................................................................................52
Table 61 – common mode voltage, Audio start-up and PSRR....................................................................................................54
Table 62 - AudioSet1 Register ....................................................................................................................................................54
Table 63 - AudioSet2 Register ....................................................................................................................................................54
Table 64 – Low voltage status Register ......................................................................................................................................55
Table 65 – PLL,MCLK Settings ...................................................................................................................................................56
Table 66 - AudioDAC Parameter.................................................................................................................................................56
Table 67 - I2S Parameter ............................................................................................................................................................56
Table 68 – Audio Register map ..................................................................................................................................................57
Table 69 – Low voltage Status register bit ..................................................................................................................................57
Table 70 - Line Inputs Parameter ................................................................................................................................................57
Table 71 - Power Amplifier Parameter.........................................................................................................................................59
Table 72 - HPH_OUT_R Register ...............................................................................................................................................60
Table 73 - HPH_OUT_L Register................................................................................................................................................60
Table 74 – Headphone Register map.........................................................................................................................................60
Table 75 - Line Power-Save Options...........................................................................................................................................61
Table 76 - Line out Block Characteristics ...................................................................................................................................62
Table 77 - LINE_OUT_R Register...............................................................................................................................................62
Table 78 - LINE_OUT_L Register...............................................................................................................................................62
Table 79 – Lineout Register map ...............................................................................................................................................63
Table 80 – I2C SDA,SCL Characteristics...................................................................................................................................63
Table 81 – XRESET,XON Characteristics...................................................................................................................................65
Table 82 – Reset Levels..............................................................................................................................................................66
Table 83 – Reset Register map..................................................................................................................................................67
Table 84 – Reset Bit definitions...................................................................................................................................................67
Table 85 – Interrupt 1 Register....................................................................................................................................................69
Table 86 – Interrupt 2 Register....................................................................................................................................................69
Table 87 – Interrupt mask 1 Register ..........................................................................................................................................69
Table 88 – Interrupt mask 2 Register ..........................................................................................................................................69
Table 89 – Low voltage status Register ......................................................................................................................................70
Table 90 – Interrupt Register map..............................................................................................................................................70
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Table 91 – Charger Startup Conditions .......................................................................................................................................72
Table 92 – Overtemperature Detection .......................................................................................................................................72
Table 93 – Overtemperature detection Regsiter definitions ........................................................................................................72
Table 94 – Overtermperature detection Bit definitions ................................................................................................................73
Table 95 – Watchdog Regsiter definitions...................................................................................................................................74
Table 96 – Watchdog Bit definitions ............................................................................................................................................74
Table 97 – Rrefernce External Components ...............................................................................................................................75
Table 98 – Refererences .............................................................................................................................................................75
Table 99 – Internal References Regsiter definitions....................................................................................................................75
Table 100 – Internal references Bit definitions ............................................................................................................................75
Table 101 – ON-Detect Register definitions ................................................................................................................................77
Table 102 – ON-Detect Bits definitions........................................................................................................................................77
Table 113 – Pinlist CTBGA100,9x9mm (AS3654).......................................................................................................................78
Table 114 – Registermap ............................................................................................................................................................81
List of Figures
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Figure 1 – Blockdiagram AS3654................................................................................................................................................10
Figure 2 – DC/DC step-up Converter 1 .......................................................................................................................................11
Figure 3 – DC/DC step-up Converter 2 .......................................................................................................................................11
Figure 4 – DC/DC step up 2 converter with regulation of LED string on pin DCDC_CURR1 or DCDC_CURR2........................13
Figure 5 – DC/DC step up 1 converter with regulated output voltage of 5V. Feedback is at pin DCDC_FB1............................13
Figure 6 – DC/DC step up converter 1 with regulated output voltage (15V), and switch off function of output voltage, to reduce
shutdown current .........................................................................................................................................................................15
Figure 7 – ADC Timing-diagram..................................................................................................................................................24
Figure 8 – USB Charger Block Diagram......................................................................................................................................27
Figure 9 – Charger Block Diagram with optional reverse polarity and short protection...............................................................29
Figure 10 – Charger Block Diagram for voltages >15V (Protection up to 50V; minimum Vcharger voltage 8V).........................30
Figure 11 – Step down charger Efficiency (Measured) ...............................................................................................................30
Figure 12 – Charger Flow Chart ..................................................................................................................................................32
Figure 13 – Step Down DC/DC Converter Blockdiagram............................................................................................................41
Figure 14 –sdX_dis_curmin=1 operation.....................................................................................................................................42
Figure 15 –sdX_dis_curmin=0 operation.....................................................................................................................................42
Figure 16 – DC/DC step-down Efficiency (sdX_dis_curmin=0, sdX_lpo=0)................................................................................45
Figure 17 –PCB Layout recommendation...................................................................................................................................45
Figure 18 – Analog LDO Blockdiagram .......................................................................................................................................47
Figure 19 – Digital LDO Blockdiagram ........................................................................................................................................49
Figure 20 – Digital LDO Blockdiagram ........................................................................................................................................51
Figure 21 – Audio Blockdiagram .................................................................................................................................................53
Figure 22 – I2S Timing Diagram..................................................................................................................................................56
Figure 23 – I2C Byte-Write:.........................................................................................................................................................64
Figure 24 – I2C Page-Write:........................................................................................................................................................64
Figure 25 – I2C Random-Read: ..................................................................................................................................................64
Figure 26 – I2C Sequential-Read:...............................................................................................................................................65
Figure 27 – I2C Current-Address-Read: ......................................................................................................................................65
Figure 28 – Startup flow chart .....................................................................................................................................................71
Figure 29 – Watchdog timing diagram.........................................................................................................................................74
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5 Characteristics
5.1 Absolute Maximum ratings (non operating)
Table 1 – Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Note
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Stressed beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress
ratings only. Functional operation of the device at these or beyond those under ‘Operating conditions’ is not implied. Exposure
to absolute maximum rating conditions may affect device reliability.
High voltage pins
-0.3
17.0
V
Applicable for high voltage pins (1)
VIN_MV
5V pins
-0.3
7.0
V
Applicable for pins 5V-pins (2)
VIN_LV
3.3V pins
-0.3
5.0
V
Applicable for 3.3V-Pins (3)
Input pin current
-25
+25
mA
At 25 °C, Norm: Jedec 78
Storage Temperature Range
-55
125
°C
5
85
%
Tstrg
Humidity
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VIN_HV
Noncondens.
Norm: MIL 883 E Method 3015
VESD05
Electrostatic discharge 0.5kV
-500
500
V
Applicable for pins: LX1, LX2, LX3,
VSUPPLY_1…VSUPPLY_6
Norm: MIL 883 E Method 3015
VESD1
Pt
Electrostatic discharge 1kV
Applicable for pins: all, except the pins
listed at VESD05
Setup: Note(4)
1
W
TA = 70 degrees
0.72
W
TA = 85 degrees
260
°C
Norm IPC/JEDEC J-STD-020C,
reflects moisture sensitivity level only
TPEAK
235
245
°C
Solder Profile(5)
30
45
s
above 217 °C
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Package Body Temperature
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TBODY
HV pins are
5V pins are
VCHARGER, VGATE, VOFF_B, DCDC_CURR1,DCDC_CURR2
V_USB, CH_SENSE_N, CH_SENSE_P, VSUP_SW1, VSUP_SW2, VBAT_SW1, VBAT_SW2, V_BAT, SCL, SDA,
XRESET, XINT, VSUPPLY_3, CURR1..6, DCDC_GATE1, DCDC_GATE2, DCDC_SENSE_P1,
DCDCSENSE_P2, DCDC_SENSE_N1, DCDC_SENSE_N2, DCDC_FB1, DCDC_FB2, VCL, VCP_OUT, VCP_N,
VCP_P, VCP_IN, VCP_IN, VRF1, VREF1_IN, VRF2, VRF2_IN, VDIG1, VDIG1_IN, VDIG2, VDIG2_IN,
VSUPPLY_1, VSUPPLY_2, LX1, LX2, GND_SW, VSUPPLY_4, LINE_CM, HP_CM_PWR, HP_CM, LOUT_R,
LOUT_L, ALVDD, AVDD, LSP_R, BVSS, LSP_L, AVDD, VSUPPLY_4
ISENSEP, ISENSEN, ADC_IN, RPROGRAM, V2_5, CREF, ON, VI2S, SDI, SCLK, MCLK, LRCLK,AGND, VREF,
LINL,LINR, VDAC
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(1)
(2)
V
Total Power Dissipation
Soldering Conditions
Notes
1000
-1000
(3)
3.3V pins are
(4)
ESD setup
Following pins connected:
VSUPPLY_1...VSUPPLY_6, VCP_IN, VRF1_IN, VRF2_IN, VCURR connected together
VDIG1_IN,VDIG2_IN connected together
AVDD, ALVDD connected together
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(5)
Soldering
VBAT_SW1 and VBAT_SW2 connected together
VSUP_SW1 and VSUP_SW2 connected together
All VSS connected together
austriamicrosystems strongly recommends to use underfill
5.2 Operating Conditions
Parameter
Min
VHV
High Voltage
0.0
VBAT,
VSUPPLY
Battery, Supply Voltage
3.0
V2_5
Voltage on Pin V2_5
2.4
2.5
2.6
V
Internally generated
VCP_OUT
Output Voltage charge pump
4.9
5.2
5.6
V
Voltage generated by charge pump
TAMB
Ambient Temperature
-30
25
85
deg.
ILOWPOWER
Low power mode current
consumption
Note
15.0
V
VCHARGER, VGATE,
DCDC_CURR1,DCDC_CURR2
5.5
V
For pins V_BAT, VSUPPLY1-6
(always connect all VSUPPLY1-6
pins together), VSUP_SW1-2,
VBAT_SW1-2, VRF1_IN, VRF2_IN,
VCP_IN, AVDD, ALVDD, VCURR (1)
7
mA
Current consumption in low power
mode with step down charger on(2)
200
µA
With step down charger off(3)
16
µA
Current consumption in power off
mode (4)
During startup from the AC/DC adapter, the battery voltage can be below 3.0V
with register bit low_power_on = 1, only Rf1=3.3V,Vout2=1.2V,Battery 3.6V,Vcharger=6.0V, no additional external loads
with register bit low_power_on = 0, All regulators switched off, no additional external loads
after setting register bit xon_enable=1 and power_off=1; only V2_5 is active in Power Off mode
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Power Off mode current
consumption
Notes
(1)
(2)
(3)
3.6
Max
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Symbol
IPowerOff
Typ
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Table 2 – Operating conditions
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6 General Description
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Figure 2 – Blockdiagram AS3654
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7 Detailed Functional Descriptions
7.1 Step Up DC/DC Converter
Figure 3 – DC/DC step-up Converter 1
PWM
Logic
osc
Driver
DCDC_GATE1
stpup1_clk_inv
Ramp
1.25V
am
lc s
on A
te G
nt
st
il
DCDC_FB1
stpup1_v
lv
DCDC_SENSE_N1
stpup1_on
al
id
DCDC_SENSE_P1
Current sense
0-15µA
Figure 4 – DC/DC step-up Converter 2
DCDC_SENSE_P2
Current sense
DCDC_SENSE_N2
stpup2_on
osc
stpup2_clk_inv
PWM
Logic
Driver
DCDC_GATE2
Ramp
1.25V
stpup2_fb
DCDC_FB2
Mux
stpup2_v
dcdc_curr1_current
ca
0-15µA
0.5V
DCDC_CURR1
ni
0-37.5mA
0.5V
DCDC_CURR2
dcdc_curr2_current
Te
ch
0-37.5mA
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Table 3 – DC/DC Converter parameters
IVDD
Quiescent Current
VFB1
Feedback voltage for
external resistor divider:
VFB2
Feedback voltage for current
sink regulation
IDCDC_FB
Additional tuning current at
DCDC_FB
0
Accuracy of feedback
current
-4
Current limit voltage at
Rsense
RSW
switch resistance
Iload
Load current
fIN
Switching frequency
Cout
TYP
Max
Unit
Note
μA
Pulse skipping mode
V
for constant voltage control
V
DCDC_CURR1 or DCDC_CURR2
15
μA
adjustable by software in 1µA steps
4
%
@ full scale
mV
(e.g.: 0.65A for 0.15Ω sense
resistor
140
1.20
1.25
1.30
0.5
100
am
lc s
on A
te G
nt
st
il
Vrsense_max
Min
al
id
Parameter
lv
Symbol
1
Ω
ON-resistance of external
switching transistor
50
mA
at 15V output voltage
fclk_int/2
MHz
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
Output capacitor
2.2
μF
ceramic, ±20%
L
Inductor
10
μH
Use inductors with small Cparasitic
(<100pF) to get high efficiency
tMIN_ON
Minimum on time
130
ns
MDC
Maximum duty cycle
91
%
0
ca
DC/DC Step Up converter is a high efficiency current mode PWM regulator, which provides an output voltage up to 20V and a
load current up to 50mA . A constant switching frequency results in a low noise on supply and output voltage.
Feedback selection
ni
For step up DCDC 1, the feedback is always DCDC_FB1.
ch
For step up DCDC 2 following feedback selections are possible:
Stpup2_fb selects the type of feedback for the DCDC_step_up2 converter:
DCDC_CURR1, DCDC_CURR2 or DCDC_FB2 feedback (see Fig.3)
Te
Setting stpup2_fb to 00b enables the feedback on DCDC_FB2, stpup2_fb to 01b enables feedback at pin DCDC_CURR1 ,
setting step_up_fb to 10b enables feedback at pin DCDC_CURR2. The Step-up converter is regulated such that the required
current at the feedback path can be supported.
Always choose the path with the higher voltage drop as feedback to guarantee adequate supply for the other, unregulated
path.
To protect the DCDC output voltage against overvoltage, if a LED string is broken, set stpup2_prot=1. In this mode the output
voltage will be limited by limiting the DCDC_FB voltage to 1.25V (select the external resistor network to adjust this limitation
voltage).
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Figure 5 – DC/DC step up 2 converter with regulation of LED string on pin DCDC_CURR1 or DCDC_CURR2
VSUPPLY
CDCDC_IN2
2.2µF
RSHUNT2
0.15 +/-5%
LDCDC2
10µH; SD12-100 Coiltronics
DCDC_SENSE_P2
Current sense
DCDC_SENSE_N2
DDCDC2
PMEG2010
stpup2_clk_inv
1.5nF
15nF
CDCDC_OUT2
2.2µF/25V
al
id
TDCDC2
Si1304
DCDC_GATE2
Driver
1M
PWM
Logic
osc
100k
stpup2_on
Ramp
stpup2_fb
LEDs
as required
by the
application
DCDC_FB2
lv
1.25V
Mux
0-15µA
stpup2_v
DCDC_CURR1
am
lc s
on A
te G
nt
st
il
dcdc_curr1_current
0.5V
0-37.5mA
0.5V
dcdc_curr2_current
DCDC_CURR2
0-37.5mA
Figure 6 – DC/DC step up 1 converter with regulated output voltage of 5V. Feedback is at pin DCDC_FB1
VSUPPLY
RSHUNT1
0.15 +/-5%
stpup1_on
ca
DCDC_SENSE_N1
PWM
Logic
osc
ni
stpup1_clk_inv
DCDC_GATE1
Driver
LDCDC1
4.7µH; SD12-4R7 Coiltronics
DDCDC1
PMEG2010
TDCDC1
Si1304
R1 1M
DCDC_SENSE_P1
Current sense
CDCDC_IN1
2.2µF
C1
1.5nF
R2
330k
C2
15nF
5V Supply
CDCDC_OUT1
10µF
ch
Ramp
1.25V
DCDC_FB1
stpup1_v
Te
0-15µA
Voltage Feedback : (see Fig.5)
For Step UP DCDC 1 voltage feedback is always selected on pin DCDC_FB1. For Steup UP DCDC 2 set step2_fb to 00 to
enable voltage feedbback at pin DCDC_FB2.
Bit stepX_res (X = 1 or 2) should be set to 1 in voltage feedback mode using two resistors.
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The output voltage is regulated to a constant value, given by:
Vstepup _ out =
R1 + R2
1.25 + I I DCDC _ FB • R1
R2
If R2 is not used, the output voltage is:
Vstepup _ out
Step up regulator output voltage
R1
R2
I Vtuning
Feedback resistor R1
Feedback resistor R2
Examples:
Vstepup_out
Vstepup_out
μA
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R1=1MΩ,R2 not used
6.25
7.25
8.25
9.25
10.25
11.25
12.25
13.25
14.25
15.25
16.25
R1=500kΩ,R2=64kΩ
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
16.5
17
17.5
18
18.5
ca
am
lc s
on A
te G
nt
st
il
Ivtuning
lv
Tuning current on DCDC_FB pin: stpupX_v (0μA to 15μA (1μA steps)) (X= 1 or 2)
al
id
Vstepup _ out = 1.25 + I I DCDC _ FB • R1
Te
ch
ni
Note: The voltage on pin DCDC_CURR1 and DCDC_CURR2 must never exceed 15V
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Figure 7 – DC/DC step up converter 1 with regulated output voltage (15V), and switch off function of output
voltage, to reduce shutdown current
VSUPPLY
Current sense
DCDC_SENSE_N1
LDCDC1 4.7µH
SD12-4R7
Coiltronics
DDCDC1
PMEG2010
stpup1_on
PWM
Logic
osc
DCDC_GATE1
Driver
stpup1_clk_inv
TDCDC1
Si1304 C1
1.5nF
C2
15nF
Ramp
1.25V
DCDC_FB1
stpup1_v
15V Supply
TDCDCOFF1
BSS84
R1
CDCDC_OUT1
2.2µF/25V
R2
18k
am
lc s
on A
te G
nt
st
il
0-15µA
VSUPPLY
al
id
DCDC_SENSE_P1
CDCDC_IN1
2.2µF
lv
RSHUNT1
0.15 +/-5%
Te
ch
ni
ca
As the output voltage is always on, an additional output transistor can be added to reduce shutdown current through R1, R2
and the connected output circuit.
Note: A similar circuit can be used for step up converter 2.
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Table 4 – Step Up DC/DC Bit definitions
Name
Defau
lt
Access
stpupX_on
ROM
R/W
On/Off control of the step up dc/dc converter; (X=1 or 2)
stpupX_clkinv
ROM
R/W
Invert input clock of step up converter; (X=1 or 2)
0
Use positive edge of internal clk
1
Use negative edge of internal clk
al
id
Description
Controls the feedback source
R/W
00
01
10
11
DCDC_FB enabled ( external resistor divider)
DCDC_CURR1 feedback enabled (feedback through white LEDs)
DCDC_CURR2 feedback enabled (feedback through white LEDs)
reserved (don’t use)
lv
ROM
stpup2_fb
Defines the clock frequency of the step up dc/dc converter; (X=1 or 2)
ROM
R/W
fclk_int/2 (0.8 to 1.15 MHz)
fclk_int/4 (0.4 to 0.575 MHz)
0
1
am
lc s
on A
te G
nt
st
il
stpupX_freq
Defines the tuning current at DCDC_fb pin; (X=1 or 2)
ROM
stpupX_v
stpupX_res
ROM
R/W
R/W
0 μA
1 μA
0000
0001
.
1111
15 μA
Gain selection for DCDC step_up: (X=1 or 2)
0 Select 0 if DCDC is used with current feedback
(DCDC_CURR1,DCDC_CURR2) or if DCDC_FB is used with current feedback
only (Only R1,C1 connected; see Fig.6)
1 Select 1 if DCDC_FB1 or DCDC_FB2 is used with external resistor divider (2
resistors)
ROM
RW
0: accurate output voltage, higher ripple (normal operation)
ca
stpupX_fastskip
DCDC converter output voltage at low loads, when pulse skipping is active: ;
X=1 or 2
ni
1: elevated output voltage, less ripple
ROM
RW
ch
stpup2_prot
Te
stpup1_shortpro
t
stpup1_oc_time
out
ROM
DCDC converter 2 overvoltage protection to prevent damage of external NFET, if
DCDC_CURR1 or DCDC_CURR2 feedback selected, and no LED string
connected:
0: Overvoltage protection disabled.
1: Switch off DCDC step up 2 if the voltage on DCDC_FB2 exceeds 1.25V
Enables Protection and Detection circuit for DCDC step up1 – see next section
RW
0: No protection and load detection
1: Short protection and load detection enabled
Controls GPIOx switch off, after overcurrent timeout (5ms) for DCDC step up 1
ROM
RW
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0: disabled
1: enabled
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Table 5 – Step Up Registermap
Default
Step Up DC/DC
Control
15
ROM (00h)
Step Up1 DC/DC
Control
16
ROM (00h)
Step Up2 DC/DC
Control
17
ROM (00h)
Reg Power2 Ctrl
31
ROM
Content
b7
b6
b5
stpup2_r
es
stpup2_f
astskip
stpup1_
oc_time
out
stpup2_
clkinv
stpup2_f
req
stpup1_
shortpro
t
stpup2_
prot
b4
b3
b2
b1
stpup1_r
es
stpup1_f
astskip
stpup1_f
req
stpup1_
clkinv
b0
stpup1_v
stpup2_fb
al
id
Name
Add
r. 1
stpup2_v
stpup2_
on
rf2_sw
rf1_sw
am
lc s
on A
te G
nt
st
il
7.2 Stepup1 load detection and overcurrent protection circuit
stpup1_
on
lv
Register Definition
This circuit protects the DCDC step up1 converter during short circuit and startup, by regulation of the output current.
An additional feature is the detection of a minimum output load of the StepUp converter. It is also possible to use this circuit
without the DCDC step up converter, by using the sense resistor only:
•
•
Detection circuit
If the voltage on Rsense exceeds VDETECT for more than 1msecond, or the DCDC Step up converter is not in Pulseskip
for more than 1 msecond, the stepup1_det bit will be set.
Overcurrent protection
If the Overcurrent voltage VOVCURRENT has been exceeded by more than 5 msec the Bit stpup1_oc will be set and can
only reset, by switching off and on the Protection circuit by writing Stpup1_shortprot 0 – 1.
If stepup1_oc is set the load will be disconnected, if Stpup1_oc_timeout=1
Table 6 – StepUp1 protection/detection circuit parameters
Parameter
VDETECT
Detection Threshold
VOVCURRENT
Overcurrent Threshold rising
VOVhysteresis
Overcurrent Hysteresis
50
mV
tOV_timeout
Overcurrent timeout
5
ms
Interrupt and/or external PMOS
switching off after timeout
fclk_int = 2.2MHz
1
ms
fclk_int = 2.2MHz
ni
Detection denounce time
TYP
Max
Unit
Note
2
12.5
20
mV
For Rsense=0.150Ohm =>
83mA typ.
150
180
215
mV
For Rsense=0.150Ohm =>
1.2A typ.
Te
ch
tdetect
Min
ca
Symbol
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
1
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0.15
Vsupply
DCDC_SENSE_P1
DCDC_SENSE_N1
+
stpup1_det
+
stpup1_oc
15mV
lv
al
id
180mV
am
lc s
on A
te G
nt
st
il
Table 7 – Low voltage status Bit definitions (stpup1_det and stpup1_oc)
Defau
lt
Name
Access
Description
NA
R
stpup1_oc
NA
R
Step up overcurrent status bit
0
VRsense < VOVCURRENT
1
VRsense > VOVCURRENT for more than 5 msec (latched state)
ni
ca
stpup1_det
Step up detection status register
0
VRsense < VDETECT for more than 1msecond, and DCDC Step up
converter is in Pulseskip for more than 1 msecond
1
VRsense > VDETECT for more than 1msecond, or the DCDC Step up
converter is not in Pulseskip for more than 1 msecond
Table 8 – Step Up protection Registermap
Add
r. 2
ch
Register Definition
Name
Te
Low voltage Status
47
Default
40h
Content
b7
b6
stpup1_
det
stpup1_
oc
b5
hpdet
b4
b3
dig2_lv
dig1_lv
b2
sd3_lv
b1
b0
sd2_lv
sd1_lv
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
2
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7.3 Current Sinks
These are general-purpose current sinks intended to control the backlight(s), buzzer and vibrator. The low voltage current sink
has an integrated protection against over voltage and can therefore also drive inductive loads (VPROTECT).
DCDC_CURR1 and DCDC_CURR2, CURR5 are high voltage (15V) current sinks, e.g. for series of white LEDs
CURR1,CURR2, CURR3, CURR4 are four 5V, 40mA current sinks, e.g. for buzzer, vibrator, LEDs
al
id
CURR1, CURR2, CURR3, CURR4 can be used as general propose Input/Output (GPIO) functions optional
7.3.1
High voltage Current Sinks 40mA (CURR5, DCDC_CURR1 and DCDC_CURR2):
lv
Current sinks CURR5 DCDC_CURR1 and DCDC_CURR2 can be controlled individually. The step-up DCDC converter may
supply them with voltages up to15V.
Table 9 – Current Sinks Characteristics
Parameter
Min
Typ
Max
Unit
IDCDC_Curr1,2,5
DCDC_CURR1,2 and
CURR5 current, 00h-3Fh
0
40
mA
IDCDC_protect
Current sink protection
Current
Δ
absolute Accuracy
-20%
+20%
VDCDC_Curr1,
VDCDC_Curr2
Voltage compliance
0.45
15
Note
am
lc s
on A
te G
nt
st
il
Symbol
μA
2
For V(CURRx) > 0.45V
resolution = 0.625mA
Protection Current if stpup2_on=1
and dcdc_currx_current=00h
All Current sinks
V
during normal operation
Table 10 – Current Sink Bit definitions
Name
Default
Access
Description
Defines the current into DCDC_CURRX (X = 1…4)
R/W
ch
0b
00b
R/W
0 Normal current (LSB=0.625mA, max current= 39.375mA)
1 Current reduction by 2 (LSB=0.3125mA, max current= 19.687mA)
On/Off control of the pad DCDC_CURR1,2 and CURR5
R/W
Te
dcdc_currX_ctrl,
curr5_ctrl
00h power down (default state)
01h 0.625mA
…
3Fh 39.375mA
Reduces bias current by 2
ni
dcdc_currX_low_
bias,
curr5_low_bias
(00)h
ca
dcdc_currX_curre
nt, curr5_current
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00 Pad is turned off
01 Pad is active
1X don’t use
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7.3.2
Low voltage Current Sink 40mA (CURR1, CURR2, CURR3, CURR4):
Curr1, Curr2, Curr3, Curr4 can be controlled individually. Each one can sink up to 40mA.
Table 11 – Current Sinks Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Note
Curr1,2,3,4 current, 00h-1Fh
0
40
Δ
absolute Accuracy
-20%
+20%
VCurr1,2,3,4
Voltage compliance
0.2
Vcurr.
mA
resolution = 0.625mA,
each current sink
All Current sinks
during normal operation,
V
lv
ICURR1,2,3,4
al
id
For V(CURRx) > 0.2V
New pin will be added
Name
am
lc s
on A
te G
nt
st
il
Table 12 – Current Sink Bit definitions
Default
Access
Description
Defines the current into CURRX (X = 1…4),
if Register GPIOXmode=011b or 100b
currX_current
(00)h
00h power down (default state)
01h 0.625mA
…
3Fh 39.375mA
R/W
Reduces bias current by 2 for CURRX (X = 1…4)
currX_low_bias
0b
R/W
0 Normal current (LSB=0.625mA, max current= 39.375mA)
1 Current reduction by 2 (LSB=0.3125mA, max current= 19.687mA)
Table 13 – Currentsink registermap
Name
35
Default
Content
b7
00h
ni
DCDC_CURR1 value
Add
r. 3
ca
Register Definition
36
ch
DCDC_CURR2 value
00h
37
00h
CURR2 value
38
00h
CURR3 value
39
00h
CURR4 value
40
00h
Te
CURR1 value
b6
b5
b4
dcdc_cu
rr1_low_
bias
dcdc_cu
rr2_low_
bias
curr1_lo
w_bias
curr2_lo
w_bias
curr3_lo
w_bias
curr4_lo
w_bias
b3
b2
b1
b0
dcdc_curr1_current
dcdc_curr2_current
curr1_current
curr2_current
curr3_current
curr4_current
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
3
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Add
r. 3
Name
Default
CURR5 value
41
00h
CURR control
51
00h
Content
b7
b6
b5
b4
b3
curr5_lo
w_bias
b2
b0
curr5_current
curr5_ctrl
dcdc_curr2_ctrl
7.4 General Purpose Input / Output (GPIO) Pins
7.4.1
b1
High Current GPIO Pins (Same pins as Current sinks CURR1…4)
dcdc_curr1_ctrl
al
id
Register Definition
am
lc s
on A
te G
nt
st
il
lv
The device contains 4 high current GPIO pins, which using the same pins CURR1...4, that are capable of sinking 100mA from
any supply or VSUPPLY voltage. Each of the pins can be configured as open drain NMOS or push-pull output with VCURR
high levels, as high impedance output or as digital input. When configured as output the output source can be a register bit, or
the PWM generator, furthermore the output signal can be inverted. Integrated active clamp circuits can be enabled for the
open drain NMOS output mode by setting GPIOxPulls=11b, thus allowing to use the high current GPIO pins for driving
inductive loads. A pull-up resistor to VCURR can be enabled for the open drain NMOS output mode by setting
GPIOxPulls=10b. When configured as digital input the logic level (GPIOxInvert=’0’) or the inverted logic level (GPIOxInvert=’1’)
of the pin is reflected by bit GPIOxBit in the GPIO Bit register. Moreover, a special function can be selected for each digital
input pin and a pull-up resistor to VCURR or a pull-down resistor can be enabled.
Table 14 – High Current GPIO Pin Characteristics (GPIO1…4)
VVSUPPLY=3.0…5.5V; Tamb=–20…+70°C; unless otherwise specified.
Symbol
Min
Typ
Max
Unit
VVcurr.+0.3
V
Low level output voltage switch
mode
–0.3
+0.35
V
VOL
Low level output voltage
–0.3
+0.4
V
VOH
VIL
VIH
0.8·VVcurr.
–0.3
1.3
ILEAKAGE
High level output voltage
Low level input voltage
High level input voltage
Leakage current
VVcurr.
0.4
VVcurr.
10
V
V
V
μA
Rpull-up
Pull-up resistance
78
kΩ
Rpull-down
161
kΩ
ca
VOLH
ni
VGPIOMAX
Parameter
Maximum voltage on GPIO1…4
pins
IOL=+100mA; digital output
(GPIOxMode=100b and
currentx=3Fh)
IOL=+1mA; digital output
(GPIOxMode=000b ... 010b)
IOH=–1mA; digital push-pull output
digital input
digital input
high impedance
GPIOxMode=x0b;
GPIOxPulls=10b;
VCURR=3.6V
digital input; GPIOxPulls=01b;
VCURR=3.6V
ch
Pull-down resistance
Note
ROM
Te
Table 15 – GPIO 1…4 Register
R/W access;
Bit Symbol
Default Description
000b digital open drain NMOS output 001b digital push-pull output 010b digital
input 011b digital open drain current sink operation Current defined by
CURRx_current
2…0 GPIOxMode
100b digital open drain switch operation On resistance defined by
CURRx_current101b to 111b .high impedance (
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Bit Symbol
4…3
GPIOxIOSF
GPIOxPulls
lv
7…6
al
id
5 GPIOxInvert
Default Description
00b input / output signal is written to or set by GPIOxBit in the GPIO Bit register
01b PWM (O) / WDOG (I)
if used for PWM, pwm_h_time and pwm_l_time define the high and low time
of this output
10b Protection of DCDC stepUp1 GPIO X (O)
11b NA
0 normal polarity of input / output signal
1 inverted polarity of input / output signal
00b no pull-up or pull-down resistor is enabled in all modes
01b pull-down resistor is enabled in digital input mode (clamp disabled)
10b pull-up resistor is enabled for GPIOxMode=000b,010b,011b,100b (clamp
disabled)
11b enable active clamp circuit for GPIOxMode=000b,010b,011b,100b (pull-up/down
disabled)
am
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Table 17 – GPIO Bit Register
Address 58; R/W access; register is reset at power-on-reset only and at each reset cycle.
Bit Symbol
Default Description
This bit determines the output signal of the GPIO1 pin when selected as
0
GPIO1
0
output source
This bit determines the output signal of the GPIO2 pin when selected as
1
GPIO2
0
output source
This bit determines the output signal of the GPIO3 pin when selected as
2
GPIO3
0
output source
This bit determines the output signal of the GPIO4 pin when selected as
3
GPIO4
0
output source
This bit reflects the logic level of the GPIO1 pin when configured as digital
4
GPIO1_in
NA
input pin
This bit reflects the logic level of the GPIO2 pin when configured as digital
5
GPIO2_in
NA
input pin
This bit reflects the logic level of the GPIO3 pin when configured as digital
6
GPIO3_in
NA
input pin
This bit reflects the logic level of the GPIO4 pin when configured as digital
7
GPIO4_in
NA
input pin
ni
ca
Table 18 – PWM Frequency Control High Time Registers
Address 49; R/W access; register is reset at power-on-reset only and at each reset cycle.
Bit Symbol
Default Description
This bit defines the high time of the pwm generator in 2/fclk_int units
0 = 2/ fclk_int
1
= 3/ fclk_int
7-0
pwm_h_time
00h
2 = 4/ fclk_int
…
ch
FFh = 257/ fclk_int
Te
Table 19 – PWM Frequency Control Low Time Registers
Address 49; R/W access; register is reset at power-on-reset only and at each reset cycle.
Bit Symbol
Default Description
This bit defines the low time of the pwm generator in 2/fclk_int units
0 = 2/ fclk_int
1 = 3/ fclk_int
7-0
pwm_l_time
00h
2 = 4/ fclk_int
…
FFh = 257/ fclk_int
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The following settings are not allowed: pwm_h_time - pwm_l_time = 1 or pwm_h_time - pwm_l_time = -1
Table 20 – GPIOs Registermap
Content
Default
b7
b6
b5
b4
gpio1_in
vert
gpio2_in
vert
gpio3_in
vert
gpio4_in
vert
gpio2_in
b3
GPIO 1
18
ROM (07h)
gpio1_pulls
GPIO 2
19
ROM (07h)
gpio2_pulls
GPIO 3
20
ROM (07h)
gpio3_pulls
GPIO 4
21
ROM (07h)
gpio4_pulls
GPIO Signal
PWM Frequency
Control High Time
PWM Frequency
Control Low Time
48
NA
49
00h
pwm_h_time
50
00h
pwm_l_time
gpio3_in
b1
b0
gpio1_iosf
gpio1_mode
gpio2_iosf
gpio2_mode
gpio3_iosf
gpio3_mode
gpio4_iosf
gpio4_mode
gpio1_in
gpio4
gpio3
gpio2
gpio1
am
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st
il
7.5 ADC
gpio4_in
b2
al
id
Name
Add
r. 4
lv
Register Definition
Table 21 –ADC Characteristics
Parameter
Symbol
Resolution
Min
Typ
Max
10
Unit
Bit
Input Voltage Range
Vin
Differential Nonlinearity
DNL
± 0.25
Integral Nonlinearity
INL
± 0.5
LSB
LSB
Input Offset Voltage
Vos
2
LSB
Input Impedance
Rin
Input Capacitance
0
1.8
100
V
1LSB ≈ 1.76mV
Mohms
Cin
9
pF
Power Supply Current
Idd
500
µA
Power Down Current
Idd
100
NA
ca
Note
During conversion only
Transient Parameters (25°C)
Tc
40
Clock Frequency
fc
fclk_int/8
Settling time of S&H
ts
ch
ni
Conversion Time
Te
ADC_IN pull up current
µs
kHz
1
14.25
internal CLK frequency/8
Programmable:
0.2 to 0.2875 MHz
µs
15
15.75
µA
Pull up current, if
adc_idc=1111b
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
4
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Table 22 - ADC Bit definitions
Access
start_conversion
0b
W
adc_on
0b
R/W
000b
R/W
adc_idac
000b
R/W
adc_test
0b
R/W
adc_slow
0b
R/W
result_not_ready
NA
R
D0 - D9
NA
R
Writing a 1 into this bit starts one ADC conversion.
Writing a 1 into this bit activates the ADC and the input multiplexer. The ADC
and the MUX are also activated for a conversion period when start_conversion is
set to ‘1’
Selects an ADC channel
000 ADC_IN (LSB = 1.76mV)
001 not used
010 VBAT (Battery voltage divided by 3) (LSB=5.27mV)
011 Vcharger (Charger voltage divided by 10) (LSB=17. 6mV) clamping at 10V!
100 USB Voltage (USB voltage divided by 3) (LSB=5.27mV)
101 not used
110 vtemp (temperature sensor output voltage) (LSB=1.76mV)
111 ADC test channel
Current source at ADC_IN input
0000 0μA
0001 1μA
...
1111 15 μA
am
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st
il
adc_select
Description
al
id
Default
lv
Name
always 0, don’t change
select ADC sampling frequency
0 275kHz (conversion time: 60us)
1 70kHz (conversion time: 240us)
Indicates end of conversion
0 result is ready
1 conversion is running
ADC result register
Figure 8 – ADC Timing-diagram
ca
I2C Bus start_conversion=1
275kHz
ADC_ON
3
12
13
ch
start_adc
2
ni
Sample
1
Te
result_not ready
D<9:0>
old_Data
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Data not valid
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Data ready
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Table 23 – ADC register map
Name
Add
r. 5
Content
Default
b7
b6
b5
ADC_control
63
00h
start_co
nversion
adc_on
ADC_MSB result
64
NA
result_not
_ready
D9
ADC_LSB result
ADC Idac
65
42
NA
00h
D8
b4
b3
b2
adc_slo
w
adc_test
D7
D6
b1
b0
adc_select
D5
D4
D3
D2
D1
adc_idac
D0
al
id
Register Definition
lv
7.6 Internal Battery switch (Vsupply , Battery)
am
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il
The internal Battery switch enables normal operation of the System during trickle charging of a deeply discharged battery.
The Switch provides the following functions:
ƒ Trickle charging, if Vbattery is smaller than ResVolt. The current is defined in TrickleCurrent[1:0]
PMOS is switched on if Vbattery is greater then ResVolt.
ƒ Current limitation during tricklecharge, to avoid inrush current : Itrickle_Ilimit
ƒ Undervoltage protection of Vsupply during trickle charge. The trickle current is switched of , if Vsupply drops below
Vtrickleoff
ƒ Ideal diode operation in Isolate Battery mode and disable charging mode, if charger is unplugged. This operation is for
the internal battery switch only. External battery switch is open in that mode. Regulation will start, if the VSUPPLY voltage
drops by more then VDiode below the VBattery voltage
Table 24 – Battery switch parameters
Symbol
Parameter
Min
VSupply
Input voltage
3.0
Itrickle_limit
Trickle current limit
400
mA
VDiode
Ideal Diode start voltage
50
mV
Vtrickleoff
Vsupply threshold for trickle
enable
RSW
P-Switch ON resistance
-6%
TYP
3.9
Max
Unit
Note
5.5
V
PIN VSUP_SW1,VSUP_SW2
3%
ca
0.15
V
Trickle current will be switched of, if
vsupply drops below this level
Ω
VSUP_SW=3.6V
Defau
lt
Access
ch
Name
ni
Table 25 – Battery switch status Bit definitions
R
batsw_on
R
Te
batsw_mode
Description
0
1
0
1
Trickle charging, if batsw_on=1. External PMOS switch disabled
Switch on Battery switch, if batsw_on=1. External PMOS switch
enabled.
Battery switch off
Battery switch on (Mode defined by batsw_mode)
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
5
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Table 26 – Battery switch Registermap
Name
ChargerStatus_usb
Add
r. 6
Default
67
Content
b7
b6
b5
b4
NA
b3
b2
b1
b0
batsw_o
n
batsw_
mode
USB_C
hAct
USB_Ch
Det
al
id
Register Definition
7.7 Step Down Charger
am
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lv
The battery charge controller controls the Step Down charger.
During Trickle charge of the deeply discharged battery the step down converter regulates the Vsupply to Vchlimit.
If the Vbattery voltage exceeds ResVoltRise, the internal battery switch is switched on, the Vsupply voltage drops down to
Vbattery immediately, and the step down converter operates as controlled current source to Vsupply. The battery current is
regulated to the value defined in ConstantCurrent register.
In EOC operation (see section Battery Charge Controller), the operation of the step down charger depends on the bit
isolate_battery:
If isolate_battery = 1 and EOC the output is regulated to Vchlimit.
If isolate_battery = 0 and EOC the output is not allowed to drop below VEOC (3.6V).
Table 27 – Step down charger parameters
Symbol
Parameter
Min
TYP
Max
Unit
Note
Vchlimit
Voltage limit of Step down (if not
in current limitation mode)
-3%
ch_vol
tage
3%
V
Vsupply voltage
Vrsense_max
Current limit voltage at Rsense
70
100
130
mV
(e.g.: 1.4A for 0.07Ω sense resistor
typ.)
Cout
Output capacitor
μF
X7R ceramic
L
Inductor
10/22
μH
See table 32 – Charger External
Components
Itrickle_limit
Trickle current limit
400
mA
20
60
ch
ni
ca
Table 28 – Step Down Charger control
Address; R/W access; register is reset at power-on-reset only. Default value after reset: 00h.
Bit Symbol
Default Description
0 fclk_int/4 (use as default, if Vcharger>6V)
0
sdc_frequ
0
1 fclk_int/8 (use as default, if Vcharger<6V)
Table 29 – Step down charger Registermap
Register Definition
Te
Name
Add
r. 7
Default
Content
b7
b6
b5
b4
b3
b2
b1
b0
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
7 Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
6
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Register Definition
Name
Step down charger
control
Add
r. 7
Default
34
Content
b7
00h
b6
b5
b4
b3
sd3_dis
_curmin
sd2_dis
_curmin
sd1_dis
_curmin
b2
b1
b0
sdc_freq
u
al
id
7.8 USB Charger
Figure 9 – USB Charger Block Diagram
usb_chgEn
usb_prio=1 or ChDet=0
50mV
USB_ChAct
Current
Control
end of charge
from fuel gauge
CUSB
10µF
Overvoltage
Protection
VBUS
am
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USB_ChDet
lv
V_USB
usb_current
VSUP_USB
VSUPPLY
(50mA-400mA)
25mA
usb_EOC
(internal signal only)
1
3ms
Debounce
0
EOC
3.6V
(3.9V-4.25V)
VSUP_SW1
EOC=0 or Isolate_bat=1
no_charging
CBAT
47µF
ChVoltEOC
VSUP_SW2
Battery
Charger
Controller
BAT_SW
VBAT_SW1
VBAT_SW2
LiIon Battery
ch
ni
ca
The AS3654 serves an integrated USB charger for Li+ batteres. The USB Charger is a current and voltage limited charger,
which can be used to charge Li+ batteries directly from the USB supply. The voltage limit is set by the register ChVoltEOC
(3.9V – 4.25V in 50mV steps; identical for USB charger and step down charger) and the current limit is set by the register
usb_current (50mA to 400mA in 50mA steps).
For USB charging, it is recommended to start with a current limit of 100mA and after negotiates via the USB bus (this has to
be done by e.g. the uProcessor directly) a different current setting can be set to speed up charging (e.g. 400mA).
If Bit usb_chgEn=1 in the Boot ROM is set, VSUPPLY can start up with USB supply allowing startup from the USB supply.
Te
If ChEn=1 and chdet=1 and usb_prio=0 the usb_charger will be deactivated automatically. (The Battery charger overrides the
USB charger). If usb_prio=1, both chargers (usb charger and step down charger) can operate in parallel (the voltage on
VSUPPLY is always defined by the higher voltage of the two chargers).
End of charge of the USB charger is reached, if the current through the USB charger falls below 25mA. Please note that this
current includes the added current to the battery and the system. If the current to the system is too high, the end of charge
condition should be detected by measuring the current through the battery with the fuel gauge. After this detection, the
no_charging bit should be set. Then the voltage on the battery should be monitored by the ADC to restart the charger if the
voltage on VBAT drops and a new charging cycle should be triggered.
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Table 30 – USB-Charger Bit definitions
Defau
lt
Name
Access
Description
0
ROM
(1b)
no_charging
Normal battery charger operation (usb charger and/or step down
charger)
USB and Step down charger is supplying VSUPPLY, but battery switch
is open
USB charger regulates to ChVoltEOC voltage.
Step down charger regulates to ch_voltage
1
usb_Current
ROM
(001b)
usb_prio
ROM
(0b)
R/W
usb_chgEn
ROM
(1b)
R/W
Sets the USB current.
(000)b 50mA
(001)b 100mA (default)
(010)b 150mA
(011)b 200mA
(100)b 250mA
(101)b 300mA
(110)b 350mA
(111)b 400mA
Sets the USB charger priority
0
USB charging possible if Chdet=0 only (battery step down charger is
off) default
1
USB charging possible with both charger on
lv
R/W
am
lc s
on A
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nt
st
il
USB_Chact
USB_Chdet
al
id
usb_ChargerCurrent
ON/OFF control of USB charger
R
R
set to 1 if charger is active
Set to 1 if charger is detected
Table 31 – Step down charger Registermap
Register Definition
Name
Add
r. 8
07
ChargerStatus_usb
67
ROM (52h)
Content
b7
b6
b5
b4
ext_bats
w_en
No_char
ging
usb_prio
usb_chg
En
NA
ca
USB ChargerControl
Default
b3
b2
b1
b0
USB_C
hAct
USB_Ch
Det
usb_Current
batsw_o
n
batsw_
mode
Te
ch
ni
Charger Detection:
The Charger will be detected by comparison of the V_USB voltage with the Vsupply voltage.
If V_USB is 50mV higher than VSupply voltage, the USB_ChDet is set to 1.
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
8
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AS3654
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7.9 Battery Charge Controller
-
am
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st
il
-
Charge adapter detection
Charging of deeply discharged batteries
Low current (trickle) charging with 60min timeout
Real constant current charging by regulation of the battery current instead of the charge current
Fast charging
2 different top-off charging modes: Pulse charging and constant voltage charging
Fuel gauge enables highly accurate remaining capacity estimation of the battery
Overvoltage protection for charge adapter input and main battery
Battery presence indication
Operation without battery
Reverse polarity and short protection
lv
-
al
id
The AS3654 device serves as a standalone battery charge controller supporting rechargeable lithium ion (Li+) and nickel
metal hydride (NiMH) batteries. Requiring only a few external components, a full-featured battery charger with a high degree of
flexibility can easily be realised. The main features of the controller are:
Te
ch
ni
ca
Figure 10 – Charger Block Diagram with optional reverse polarity and short protection
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am
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al
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Figure 11 – Charger Block Diagram for voltages >15V (Protection up to 50V; minimum Vcharger voltage 8V)
Table 32 – Charger External Components
Symbo
Component
l
Qchg
P-channel MOSFET
Qpu
P-channel MOSFET
Rpup1
Pull-up resistor1
Pull-up resistor2
Lchg
Inductor for charging
Dchg
Rchg
Diode
Current sense resistor charger
Rsense
Current sense resistor
Rfilt1,2
Cfilt
Filter resistor
Filter capacitor
Si1403 or FDC642P or similar
BSS84 or FDG312P or similar
2kΩ ± 5%
100Ω ± 5%
50Ω ± 5%
10μH
22uH
Tbd
70mΩ ± 5%, 125mW
50mΩ ± 1%, 125mW for
IVBAT,DC<1.5A
4.7kΩ ± 1%
1μF ± 20%, X5R or X7R dielectric
1μF ± 20%, X5R or X7R dielectric +
22uF ± 20%, Tantal dielectric
22μF± 20%, X5R or X7R dielectric
47μF± 20%, X5R or X7R dielectric
ni
ca
Rpup2
Value
Cchrg Bypass capacitor on charger pin
ch
Minimum total capacitance
parallel to Vsupply
for Qpu=BSS138
for Qpu=FDG312P
5V or 6V Vcharger input
12V Vcharger input
e.g. Vishay Dale WSL0805 series
e.g. Vishay Dale WSL0805 series
Can be omitted if fuel gauge and
charger functionality is not used
10 μH inductor
22 μH inductor
Te
Cbat
Note
Figure 12 – Step down charger Efficiency (Measured)
VSupply=4.4V
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AS3654
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Step down charger
100
90
80
Vcharger=5V, f=550kHz
Vcharger=6V, f=550kHz
Vcharger=12V, f=550kHz
Vcharger=5V, f=275kHz
Vcharger=6V, f=275kHz
Vcharger=12V, f=275kHz
60
al
id
Efficiency (%)
70
50
40
30
lv
20
0
0,0000
am
lc s
on A
te G
nt
st
il
10
0,2000
0,4000
0,6000
0,8000
1,0000
1,2000
Output current (A)
7.9.1
Charge Controller Operating Modes and Building Blocks
Charge adapter detection
The charge controller uses an integrated detection circuit to determine if an external charge adapter has been applied to the
VCHARGER or V_USB pin. If the adapter voltage exceeds the supply voltage at pin V_SUPPLY5 by VCHDET the ChDet or
USB_CHDet bit in the Charger Status register will be set. The detection circuit will reset the charge controller (ChDet or
USB_CHDet is cleared) as soon as the voltage at the VCHARGER or USB_CHDet pin drops to only VCHMIN above the battery
voltage. In case the AS3654 device is reset the charge controller will also be reset, even if a charge adapter is applied to the
VCHARGER or V_USB pin.
Charging deeply discharged batteries
ca
To be able to charge even completely discharged batteries the AS3654 device contains an internal voltage regulator that uses
the voltage of the external charge adapter at pin VCHARGER or V_USB to generate a bootstrap voltage V2_5V to supply the
internal circuitry necessary for charging. As soon as the battery voltage exceeds 2.5V, the bootstrap regulator is disabled and
the battery voltage will be used to generate the internal supply voltage to supply the charger circuitry.
Low current (trickle) charging
Te
ch
ni
Trickle charge mode is started when an external charge adapter has been detected and ChEn or usb_chgEn is set, and the
battery voltage at pin V_BAT is below the ResVoltRise threshold VRESRISE. ; The Battery switch is open in that case
(batsw_on=1 batsw_mode=0). Bits ChAct and/or USBChAct and Trickle will be set in the Charger Status registers. In this
mode the charge current into the battery will be limited to TrickleCurrent (set in the Charger Current register) by the battery
switch to prevent undue stress on either the battery or any of the charger components in case of deeply discharged batteries.
if Vsupply drops below Vtrickleoff threshold the trickle current is regulated down, to keep the Vsupply voltage up, even with an
current limited charger (e.g.:USB charger). Once VRESRISE has been exceeded, the battery switch will be closed and the charge
controller will proceed to constant current charge mode. The Vsupply voltage of the step down charger will be set to
Vcurr_preset to prevent undervoltage on vsupply during the transition between Trickle and constant current charging. (Trickle
is cleared). In case the battery voltage does not exceed VRESRISE within tTRICKLE,MAX after charging has been started,
trickle_tmax interrupt will be generated and trickle charging will be stopped. Trickle charging can be started again by writing
trickle_tmax=0 in the charger_control1 register.
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Figure 13 – Charger Flow Chart
Non-Charging
Mode
CVM=1
Top-Off Charge
Charger or USB
detected?
ch_det=1 and/or usb_chdet=1
Charger
detected?
YES
ch_act=0;
CVM=0
Bat switch on?
NO
ch_act=ch_det
usb_act=usb_chdet
NO
ch_det=0;
usb_chdet=0;
ch_act=0;
usb_act=0
YES
ChEn=1 or
USBChEn=1?
YES
NO
ChEn=1?
USBChEn=1?
YES
NO
NO
Charger or USB
detected?
NO
NO
usb_act=0
Charging
complete?
YES
ch_act=ch_det;
usb_act=usb_chdet;
Trickle=1;
batsw_mode=0;
batsw_on=1
ch_act=0;
EOC=0;
(CVM=0)
EOC = 1
YES
NO
ch_det=0;
usb_chdet=0;
ch_act=0;
Trickle=0
YES
YES
NO
VBAT>VResVolt?
YES
Switch on
Battery switch
NO
ch_det=0;
usb_chdet=0;
ch_act=0;
Trickle=0
YES
Charger or USB
detected?
YES
ChEn=1 or
USBChEn=1?
YES
bat_sw=1
bat_mode=1
ch_det=0
usb_chdet=0
ch_act=0
usb_act=0
NO
ChEn=0 and
USBeoc=1?
bat_sw=1
bat_mode=1
ch_det=0
ch_act=0
usb_chdet=0
usb_act=0
YES
ch_act=0
usb_act=0
NO
ChEn=1 or
USBChEn=1?
NO
YES
YES
Charger or USB
detected?
YES
YES
ChEn=1 or
USBChEn=1?
YES
YES
autoresume=1 &
chargerresume?
NO
YES
Vsupply<3.6V?
NO
ch_det=0;
usb_chdet=0
ch_act=0
usb_act=0
Charger or USB
detected?
YES
ChEn=1 or
USBChEn=1?
NO
NO
Vsupply<3.6V &
DisOWB=0?
YES
Trickle=0
batsw_on=1
batsw_mode=1
Stby Charger=1
Regulate to 3.6V
YES
NO
NO
autoresume=1 &
chargerresume?
Charger or USB
detected?
NO
YES
Fast Charge /
Constant
Current Charge
ch_act=ch_det;
usb_act=usb_chdet
NO
NO
bat_sw=1
bat_mode=1
ch_det=0
ch_act=0
usb_chdet=0
usb_act=0
bat_sw=0
bat_mode=0
ch_act=0
usb_act=0
batdetect=0
ca
YES
NO
bat_sw=0
bat_mode=0
VBAT>VChVoltEOC?
NO
YES
ch_act=0
usb_act=0
EOC=0
(CVM=0)
NO
NO
BatType=1?
YES
ChEn=1 or
USBChEn=1?
Battery
detect?
isolate_bat=1?
EOC=0
Charger or USB
detected?
bat_sw=0
bat_mode=0
EOC=0
(CVM=0)
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Trickle Charge
EOC=0
(CVM=0)
bat_sw=1
bat_mode=1
ch_act=0;
usb_act=0;
EOC=0;
(CVM=0)
NO
al
id
YES
Active Charging
Mode
ch_det=0;
ch_act=0;
usb_chdet=0;
usb_act=0
CVM=0
lv
NO
ni
YES
ch
Constant current charging
Te
Constant current charging is initiated by setting bit ChEn and/or USBChEn in the Charger Control register, and resetting the
No_charging bit. Note that ChEn and/or USBChEn should be set by default to enable operation of the device without a battery
connected to the system. The ChAct and/or USBChAct bit is set when the charger has started, and the charge current into the
battery will be limited to ConstantCurrent (set in the Charger Current register) by the battery charge controller. When the
battery approaches full charge, its instantaneous voltage will exceed the charge termination threshold VCHOFF. VCHOFF depends
on the battery chemistry selected by bit BatType and on the ChVoltEOC value in case a Li+ battery has been selected
(BatType=’0’). Depending on the battery type, the charging action will either be terminated (BatType=’1’; bit EOC will be set) or
a top-off charge mode will be started (BatType=’0’; bit CVM will be set). By default the charge controller will be configured for
charging lithium based batteries (BatType=’0’), battery type determination must be performed by the system host.
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Pulse charging
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Pulse charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been exceeded for the first time and
bit Pulse is set. If the battery voltage at pin V_BAT is below the VCHOFF threshold the battery switch will be switched on for a
minimum on-time set by TPON in the Charger Timing register. If the battery voltage is below VCHOFF at the end of the minimum
on-time the battery switch will remain switched on until the battery voltage exceeds VCHOFF. At this moment the battery switch
is switched off for at least the minimum off-time set by TPOFF, and the battery switch will only be switched on again when the
battery voltage falls below VCHOFF. Note that unless the Fast bit is set the charge controller will limit the charge current to the
value set by ConstantCurrent in the Charger Current register during on-pulses; if Fast is set, the charge current will not be
limited during on-pulses.
At the beginning of the pulse charging procedure the battery switch will be operated at a duty cycle close to 100%. Towards
the end of the charging cycle the charger will be switched off for long periods of time between short on-pulses. Eventually, the
off-time will become longer than TPOFFMAX, and the charging cycle is terminated (EOC is set). In the following the charge
controller starts the EOC operation.
Constant voltage charging
EOC operation
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Constant voltage charge mode is initiated and the CVM bit will be set when the VCHOFF threshold has been exceeded for the
first time and bit Pulse is not set. In the following the charge controller will act to regulate the battery voltage to a value set by
ChVoltEOC in the Charger Config register.
The charge current is monitored during constant voltage charging. It will be decreasing from its initial value during constant
current charging and eventually drop below the value set by TrickleCurrent in the Charger Current register. If the measured
charge current is less than or equal to TrickleCurrent and the battery voltage is larger than VCHRES, the charging cycle is
terminated and EOC is set . Then the charge controller starts the EOC operation.
For the USB charger, the EOC is set if the voltage through the USB charger drops below 25mA.
If both chargers are operating, both chargers have to reach EOC (End of charge) to continue with EOC operation.
There are two possibilities:
1. if isolate_bat=1 the battery switch will be switch off and the battery charger regulates to its highest voltage Vchlimit. The
USB_charger regulates to its maximum voltage, which is defined by VCHOFF. The advantage of this mode is a longer
lifetime of the Li+ battery, because there is no discharging after the EOC condition. If autoresume=1 and the battery
voltage drops below VCHRES the battery charger continues charging, by checking in trickle charge mode, if there is a
battery connected, and then starting with constant voltage or fast charging.
2. If isolate_bat=0 the battery switch remains closed and the power to the system is supplied by the battery. The battery
charger and the USB charger regulates to VEOC, in case the battery is removed. If autoresume=1 and the battery voltage
drops below VCHRES the battery charger continues charging, by checking in trickle charge mode, if there is a battery
connected, and then starting with constant voltage or fast charging.
Battery Detection and Restart of Charging:
Te
ch
ni
ca
If the battery voltage drops below VCHRES and the bit AutoResume is set, the battery detection is started. The battery switch
will be switched into current source mode and VSUPPLY will be regulated to Vchlimit (Step Down Charger) and VCHOFF (USB
charger) (regulation is performed to the higher of the two voltage settings and depends on the availability of the USB and
VCHARGER supply). The AS3654 measured the battery current with the fuel gauge in this mode. If there is no current, the
AS3654 is kept in this state and the bit NoBat is set. Otherwise the bit NoBat is cleared and the charger and the AS3654
continues with ‘Constant Current Charging’ mode.
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Typical charging cycle
VCHARGER=6V
VSUPPLY=4.4V
VSUPPLY=4.4 (isolate_bat=1)
VSUPPLY=4.2 (isolate_bat=0)
VBAT=4.2
VBAT=Vres_rise (E.g=3.4V)
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VBAT=2V
t
IBAT=ConstantCurrent (e.g 700mA)
I
Constant voltage
IBAT=TrickleCurrent (e.g 200mA)
IBAT=0mA
lv
EOC
CH_DET=0
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CH_DET=1
I2C write
NO_CHARGING=1
NO_CHARGING=0
Table 33 – Charger Characteristics
VVBAT=3.0…5.5V; Tamb=–20…+85°C; unless otherwise specified.
Symbol Parameter
Min
VCHARGER operating range
5.0
VCHDET
VCHMIN
Charge adapter detection
threshold
Maximum load current during
startup on Vsupply
50
0
ISTARTmax
ca
VCHARGER
ni
VUVLO Undervoltage lockout threshold
Charge termination threshold
ch
VCHOFF
Max
15.0
75
20
105
35
5
Unit Note
For input voltage higher than 15V
see above protection circuit; for
chargers with input voltages down
V
to 4.5V see: ‘Application Note for
DC/DC Step down Charger for
Chargers Supplying 4.5V to 5.5V’
Hysteresis is > 40mV; for USB
mV
and step down charger
mA
–3%
2.7…3.4
+3%
–0.06
3.90…4.25
+0.06
V
V
4.7
Charger resume voltage
3.85…4.20
V
Charger constant current preset voltage
VRESRISE
+100mV
V
VEOC
Charger EOC voltage
3.60
V
tTRICKLE,MAX
Trickle charge timeout
60
min
Te
VCHRES
Typ
Vcurr_preset
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Value is set by ResVoltRise in the
Battery Voltage Monitor register
Li+ battery (BatType=’0’); value is
set by ChVoltEOC in the Charger
Config register
NiMH battery (BatType=’1’)
Value is set by ChVoltResume in
the Charger Config register. Do
not set VCHRES higher than
VCHOFF!
If isolate_bat=0; to prevent a
system reset if the battery is
removed in EOC operation
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Table 34 – Charger Register Overview
Default
USB ChargerControl
07
ROM (52h)
ChargerControl1
08
ROM (41h)
Charger Config
ChargerTiming
ChargerStatus
10
11
66
ROM (26h)
ROM (4bh)
NA
ChargerStatus_usb
67
NA
Content
b7
b6
b5
ext_bats No_char
usb_prio
w_en
ging
Isolate_b
trickle_t
Boost
at
max
ChVoltResume
TPOFFMAX
NoBat
EOC
b4
b3
usb_chg
En
Pulse
DisOWB
TPOFF
CVM
b2
b1
b0
usb_Current
Auto
Resume
DisBDet
Trickle
batsw_o
n
Fast
al
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Name
Add
r. 9
BatType
ChVoltEOC
TPON
Resume
ChAct
ChDet
batsw_
USB_C USB_Ch
mode
hAct
Det
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Table 35 – Charger Status Register
Address 5; Read only access; register is reset at power-on-reset only.
Bit Symbol
Default Description
Bit is set when external charge adapter has been detected on pin
0
ChDet
NA
VCHARGER
Bit is set when step down charger is operating (independent of Reg. bit
1
ChAct
NA
no_charging)
2
Resume
NA
Bit is set when battery voltage has dropped below resume level
3
Trickle
NA
Bit is set when charger is in trickle charge mode
4
CVM
NA
Bit is set when charger is in top-off charge mode (constant voltage mode)
Bit is set when charging has been terminated. Bit is cleared automatically
5
EOC
NA
when ChEn is cleared, no_charging ist set or charging is resumed.
Bit is set when battery detection circuit indicates that no battery is connected
to the system. Detection is started after EOC and if bit autoresume=1 only. Bit
6
NoBat
NA
is cleared automatically when a battery is connected, when DisBDet is set
and/or when ChEn is cleared.
Te
ch
ni
ca
Table 36 – Charger Control1 Register
Address 8; R/W access; register is reset at power-on-reset only. Default value after reset: C1h.
Bit Symbol
Default Description
0 Disable step down charger (Independent of bit no_charging)
0
ChEn
ROM(1b)
1 Enable step down charger (default) (Independent of bit no_charging)
0 Li+ battery
1
BatType
ROM(0b)
1 NiMH battery
2
nc
ROM(0b)
0 Charging does not restart automatically in EOC when bit Resume is set.
3
AutoResume
ROM(0b)
1 Charging will restart automatically in EOC when bit Resume is set.
0 Select constant voltage charging mode (default recommended)
4
Pulse
ROM(0b)
1 Select pulse charging mode
0 Read: no timeout reached
Write: reset trickle_tmax state
5
trickle_tmax
ROM(1b)
1 tTRICKLE,MAX timeout reached and trickle charging stopped
0 Don’t use
6
Boost
ROM(1b) 1 Normal operation of Trickle charger use
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
9
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ChEn
lv
Register Definition
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Bit Symbol
7
Default
Description
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Table 37 – Battery Voltage Monitor Register
Address 9; R/W access; register is reset at power-on-reset only. Default value after reset: ROM.
Bit Symbol
Default Description
This value determines the reset level VRESRISE for rising VVBAT. It is
recommended to set this value at least 200mV higher than VRESFALL.
100b VRESRISE=3.1V
VRESRISE=2.7V
ROM 000b
2…0
ResVoltRise
VRESRISE=2.8V
101b VRESRISE=3.2V
(101b) 001b
010b
VRESRISE=2.9V
110b VRESRISE=3.3V
011b
VRESRISE=3.0V
111b VRESRISE=3.4V
This value determines the reset level VRESFALL for falling VVBAT. It is
recommended to set this value at least 200mV lower than VRESRISE.
100b VRESFALL=3.1V
VRESFALL=2.7V
ROM 000b
5…3
ResVoltFall
VRESFALL=2.8V
101b VRESFALL=3.2V
(011b) 001b
010b
VRESFALL=2.9V
110b VRESFALL=3.3V
011b
VRESFALL=3.0V
111b VRESFALL=3.4V
0
A hard reset is generated if Vsupply falls below 2.7V.
ROM
(If VVBAT falls below VRESFALL only an interrupt is generated (if
6
SupResEn
(0b)
enabled) and the uProcessor can shut down the system)
1
Vsupply Voltage below VRESFALL generates a reset
7
ca
Table 38 – Charger Timing Register
Address 11; R/W access; register is reset at power-on-reset only. Recommended value after reset: ROM 4Bh.
Bit Symbol
Default Description
Sets the minimum on-time in pulse charge mode from 137.3ms…1098ms in
2…0
TPON
ROM
steps of 137.3ms. Default is 011b = 549.2ms.
Sets the minimum off-time in pulse charge mode from 68.65ms…549.2ms in
5…3
TPOFF
ROM
steps of 68.65ms. Default is 001b = 137.3ms.
Sets the maximum off-time in pulse charge mode before charging is
terminated.
00b 4 x TPON (yields 1/5 of the charging current in constant current mode)
7…6
TPOFFMAX
ROM 01b 9 x TPON (yields 1/10 of the charging current in constant current mode)
10b 19 x TPON (yields 1/20 of the charging current in constant current mode)
11b no termination (not recommended)
Te
ch
ni
Table 39 – Charger Config Register
Address 10; R/W access; register is reset at power-on-reset only. Recommended value after reset: ROM ,26h.
Bit Symbol
Default Description
Sets the end-of-charge voltage level VCHOFF.
000b
3.90V
100b 4.10V
001b
3.95V
101b 4.15V
2…0
ChVoltEOC
ROM
010b
4.00V
110b 4.20V (default)
011b
4.05V
111b 4.25V
0 Enable battery presence indication(default)
3
DisBDet
ROM
1 Disable battery presence indication. Don’t use
0 Enable “operation without battery” feature(default)
4
DisOWB
ROM
1 Disable “operation without battery” feature. Don’t use
Sets the resume voltage level VCHRES.
3.85V
100b 4.05V
7…5 ChVoltResume
ROM 000b
001b
3.90V(default)
101b 4.10V
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Bit Symbol
7.9.2
Default
Description
010b
3.95V
011b
4.00V
110b 4.15V
111b 4.20V
Fuel Gauge
The fuel gauge circuit enables remaining capacity estimation of the battery by tracking the net current flow into and out of the
battery using a voltage-to-frequency converter.
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Voltage-to-Frequency Converter
lv
The voltage-to-frequency (VFC) converter constantly monitors the voltage drop across an external current sense resistor Rsense
connected in series between the negative battery terminal and ground. The use of an additional external RC lowpass filter is
highly recommended. Using two 4.7kΩ resistors (Rfilt1,2) and a 1μF ceramic capacitor (Cfilt), the filter cut-off is approximately
16.9 Hz. This filter will capture the effect of most spikes, and will thus allow the current accumulators to accurately reflect the
total charge that has gone into or out of the battery.
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The key building block of the VFC is an integrator. It will integrate the voltage VSNS across input pins ISENSP and ISENSN. If
VSNS is positive (battery is charged), the output voltage of the integrator increases; a negative input voltage (battery is
discharged) will cause the integrator output voltage to decrease.
Table 40 – Fuel Gauge parameters
Symbol
Parameter
fCLK
Internal reference clock
fVFC
VISENSP
VISENSN
ZISENSP
ZISENSN
AVFC
FRVFC
Sample frequency
Min
Input voltage
-0.1
Input impedance
4.67
-500
VOFF,COMP
Compensated offset voltage
-50
Max
Unit
Note
fclk_int/2
MHz
internal CLK frequency/2
Programmable: 0.8 to 1.15 MHz
fCLK/59
Hz
0.1
V
MΩ
91.0
3.05
tbd
tbd
ca
VOFF
(Dis)Charge gain
Fundamental rate
Supply voltage gain coefficient
Temperature gain coefficient
Uncompensated offset voltage
Typ
Hz / V
μVh
%/V
% / °C
fCLK = 1.1MHz
500
±10
50
μV
Offset compensation with
CalMod=1 only. Don’t use
CalMod=0
ni
Charge Current Accumulator
Te
ch
The output signals of the charge count dividers are used as inputs for the charge current accumulator that is realised as a 15bit up-down counter with separate inputs for incrementing and decrementing the counter. An additional sign bit indicates the
polarity of the counter value that is maintained in two’s complement format. The current accumulator is updated at a rate
equivalent to one count per 3.05μVh, which is equivalent to one count per 61.03μAh when using a 50mΩ current sense
resistor. It will roll over beyond (7FFF)h when incremented and (0000)h when decremented, and the value given by the
counter will be ambiguous in that case. It is the responsibility of the host to read the counter before rollover occurs.
The content of the charge current accumulator will be transferred into the DeltaCharge register when the UpdReq bit in the
FuelGauge register has been set. The update of the register has to be synchronised to the sample clock fVFC and can take up
to 1.5 clock cycles (max. 2.5μs). After the registers have been updated successfully, the UpdReq bit is cleared automatically
and the charge current accumulator together with the sign bit will be reset.
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Elapsed Time Counter
The sample clock fVFC of the fuel gauge circuit is fed to a 14-bit clock count divider. Its output signal is used as a clocking
signal for the 16-bit elapsed time counter, resulting in an equivalent rate of 1.1379 counts per second (4096.60 counts = 1
hour). The elapsed time counter will rollover beyond (FFFF)h, and the value given by the counter will be ambiguous in that
case. It is the responsibility of the host to read the counter before rollover occurs.
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The content of the elapsed time counter will be transferred into the ElapsedTime register when the UpdReq bit in the
FuelGauge register has been set. The update of the register has to be synchronised to the sample clock fVFC and can take up
to 1.5 clock cycles (max. 2.5μs). After the registers have been updated successfully, the UpdReq bit is cleared automatically
and the elapsed time counter will be reset.
Offset Calibration Mode
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Although the VFC compensates for the offset of the integrator the fuel gauge features an additional offset calibration mode to
enhance the measurement accuracy even further. By setting the CalReq bit in the FuelGauge register the integrator is reset
and the offset calibration mode is activated. The charge count dividers are bypassed during offset calibration to allow a faster
calibration procedure with adequate resolution. The offset is accumulated during 16 clocks of the elapsed time counter, the
resulting offset calibration value FGOffCal has a resolution of 3.05μV and is transferred to the DeltaCharge register. The
CalReq bit is cleared automatically after the calibration has completed successfully and FGOffCal has been written to the
register.
Please note that offset calibration is not possible while the charger is active. If the CalReq bit is set while the charger is active
the calibration will start automatically after the charger has been disabled by clearing the ChEn bit or if the external charge
adapter has been removed. If during an offset calibration procedure the charger is enabled the offset calibration mode is
terminated, the CalReq bit is cleared, the current value of the elapsed time counter is transferred to the ElapsedTime register
and the DeltaCharge register is loaded with (FFFF)h.
Calculation of Battery Status
The host system can calculate all the parameters necessary for estimating the remaining battery capacity by evaluating
ElapsedTime, DeltaCharge and FGOffCal.
Calculating Elapsed Time
The host system can evaluate the change in time Δt by setting the UpdReq bit in the FuelGauge register and reading
ElapsedTime after UpdReq has been automatically cleared. The change in time in seconds is given by:
Δt = ElapsedTime x 3600 / 4096.60 [s]
(1)
ca
Note that the absolute accuracy of Δt is directly related to the absolute accuracy of the internal reference oscillator. To cancel
the error associated with the accuracy of the oscillator, a correction factor CV can be introduced. CV can be evaluated by
comparing the change in time calculated by (1) with some reference value ΔtREF obtained from a RTC or measured during
system calibration. CV is given by:
CV = ΔtREF / Δt
(2)
ni
By multiplying Δt and CV the correct value for the change in time can be calculated:
ΔtCORR = CV x Δt [s]
ch
(3)
Te
Calculating Average Current
The host system can calculate the average current during the last time period by setting the UpdReq bit in the FuelGauge
register and reading DeltaCharge and ElapsedTime after UpdReq has been automatically cleared. Together with FGOffCal
determined during offset calibration mode the average current is given by:
IAVG = DeltaCharge / (Δt x AVFC x Rsense) – FGOffCal x 3.05μV / Rsense [A]
(4)
Δt is the change in time in seconds calculated by (1), AVFC is the gain of the VFC in Hz/V, Rsense is the value of the sense
resistor in Ω and FGOffCal is the offset calibration value. As DeltaCharge and Δt both are proportional to the oscillator
frequency, no correction factor needs to be introduced in the formula.
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Calculating Accumulated Current
Accumulated current is used to calculate the absolute remaining capacity of the battery. It is given by:
IACC = IAVG x ΔtCORR [As]
(5)
Calculating the Remaining Capacity
Remaining capacity is the entire goal of fuel gauging. It is given by:
RC = RC + IACC [As]
(6)
(7)
Table 41 – Fuel Gauge Register definitions
Register Definition
Content
Name
b7
12
68
69
70
71
sign
27
215
27
b6
b5
b4
b3
b2
b1
b0
CalMod
211
23
211
23
CalReq
210
22
210
22
UpdReq
29
21
29
21
FGEn
28
20
28
20
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FuelGauge
DeltaChargeMSB
DeltaChargeLSB
ElapsedTimeMSB
ElapsedTimeLSB
Addr.
lv
TTE = RC / IAVG [s]
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Calculating the Time to Empty
The time to empty is calculated from the average current IAVG given by (4). The longer the time period for which IAVG is
calculated, the more accurate the value for IAVG and therefore the estimated time to empty will be. It is given by:
214
26
214
26
213
25
213
25
212
24
212
24
Table 42 – Fuel Gauge Bit definitions
Name
Default
Access
Description
FuelGauge – ROM default (01)h
FGEn
0b
R/W
0b
R/W
ni
CalReq
0b
R/W
ch
CalMod
R/W
0 Disable Fuel Gauge
1 Enable Fuel Gauge (default)
This bit controls the update of the DeltaCharge and ElapsedTime registers.
When set, the bit is cleared automatically after the registers have been updated
successfully. Bit should not be set to “0” by the host!
0 Update of registers complete (default)
1 Request update of registers
This bit controls the offset calibration. When set, the bit is cleared automatically
after the calibration has completed successfully.
0 Calibration complete OR terminate offset calibration (default)
1 Request offset calibration
Sets the mode for offset calibration
0 Connect inputs to ground internally (default)
1 Use ISENSP and ISENSN (for testing purposes only)
ca
UpdReq
ROM
DeltaCharge – read only
Te
DeltaCharge
(0000)h
R
The register is maintained in two’s complement format with a resolution of
3.05μVh and a full-scale value of ±99.98mVh. When using a 50mΩ current
sense resistor this is equivalent to a resolution of 61.03μAh and a full-scale
value of 1.999Ah. Sign is set for negative values. Register will be updated after
setting bit UpdReq to “1”.
R
The elapsed time count is stored in the register with a resolution of 0.8788s and
a full-scale value of 15.997 hours. Register will be updated after setting bit
UpdReq to “1”.
ElapsedTime – read only
ElapsedTime
(0000)h
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Table 43 – FG Registermap
FuelGauge
Content
Default
12
b6
ext_bats
w_en
No_char
ging
b5
b4
usb_prio
usb_chg
En
ROM (01h)
USB ChargerControl
07
ROM (52h)
ChargerStatus_usb
67
NA
DeltaChargeMSB
DeltaChargeLSB
ElapsedTimeMSB
ElapsedTimeLSB
68
69
70
71
NA
NA
NA
NA
7.9.3
b7
sign
27
215
27
214
26
214
26
213
25
213
25
b3
b2
b1
CalMod
CalReq
UpdReq
FGEn
USB_C
hAct
29
21
29
21
USB_Ch
Det
28
20
28
20
usb_Current
batsw_o
n
211
23
211
23
212
24
212
24
b0
batsw_
mode
210
22
210
22
al
id
Name
Add
r. 10
lv
Register Definition
Charger Operation
am
lc s
on A
te G
nt
st
il
The charger controls the battery current through the internal transistor between VSUP_SW1,2 and VBAT_SW1,2, the step
down charger and the battery switch between VSUPPLY and VBAT. With this control the charger obtain all different operating
modes.
Charge Current Regulator
The regulator is programmed by setting TrickleCurrent and ConstantCurrent in the ChargerCurrent register and yields a
resolution of 0.625mV or 12.5mA when using a sense resistor of 50mΩ.
Table 44 – Charge Current Regulator parameters
Symbol
Parameter
Min
tMEAS
IMEAS,LSB
Measurement period
Resolution of InstCurCnt
Typ
Max
68.65
0.625
Unit
Note
ms
mV
fclk_int = 2.2MHz
Table 45 – Charger Register map
Name
ChargerCurrent
Add
r. 11
13
Content
Default
b7
ca
Register Definition
ROM (2Eh)
b6
b5
ch_voltage
b4
b3
b2
ConstantCurrent
b1
b0
TrickleCurrent
Name
ni
Table 46 – Charger Bit definitions
Default
Access
Description
ch
ChargerCurrent – ROM
Te
TrickleCurrent
ROM
Register address codes
ROM-adr. 25-30…Power1
11 Register address codes
ROM-adr. 25-30…Power1
10
R/W
Sets the trickle current. Default is (01)b = 2.5mV x Rsense-1.
(00)b
1.25mV x Rsense-1
(01)b
2.50mV x Rsense-1
(10)b
5.00mV x Rsense-1 (default)
(11)b
10.0mV x Rsense-1
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
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Specification, Confidential
Name
ConstantCurrent
Default
Access
Description
ROM
R/W
Sets the charging current in constant current mode from (0mV…35mV) x Rsense-1
in steps of 5mV x Rsense-1. Default is (011)b = 15mV x Rsense-1.
R/W
Charger voltage after EOC and isolate_battery=1
(000)b 4.3V
(001)b 4.4V (default)
(010)b 4.5V
(011)b 4.6V
(100)b 4.7V
(101)b 4.8V
(110)b 4.9V
(111)b 5.0V
ROM
7.10
am
lc s
on A
te G
nt
st
il
lv
ch_voltage
al
id
Ch_voltage – ROM
Step Down DC/DC Converter
Figure 14 – Step Down DC/DC Converter Blockdiagram
Imin
sdX_dis_curmin
170mA
800mA
Ilimit
clk
Vsupply
IsenseP
sdX_dis_pon
Ref -4%
Overvoltage
Comp
skip
100% duty
cycle
ca
Ref -10%
LOGIC
Ref +8%
LX
Zero Comp
IsenseN
PWM
Comp
skip
Ref=0.6V
FB
softstart
Slope
Compensation
Te
ch
PGND
step_downX_v
ni
sdX_lv
Functional Description
The step-down converter is a high efficiency fixed frequency current mode regulator. By using low resistance internal PMOS
and NMOS switches efficiency up to 95% can be achieved. The fast switching frequency allows using small inductors, without
increasing the current ripple. The unique feedback and regulation circuit guarantees optimum load and line regulation over the
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whole output voltage range, up to an output current of 500mA, with an output capacitor of only 10μF. The implemented current
limitation protects the DCDC and the coil during overload condition.
To allow optimised performance in different applications, there are bit settings possible, to get the best compromise between
high efficiency and low input, output ripple:
Low ripple, low noise operation:
al
id
Bit settings:
sdX_dis_curmin=1
In this mode there is no minimum coil current necessary before switching off the PMOS. As result, the ON time of the PMOS
will be reduced down to tmin_on at no or light load conditions, even if the coil current is very small or the coil current is
inverted. This results in a very low ripple and noise, but decreased efficiency, at light loads, especially at low input to output
voltage differences. Because of the inverted coil current in that case the regulator will not operate in pulse skip mode.
lv
Figure 15 –sdX_dis_curmin=1 operation
am
lc s
on A
te G
nt
st
il
1: LX voltage, 2:coil current (1mV=1mA) 3: Vout
High efficiency operation (default setting):
ch
ni
ca
Bit settings:
sdX_dis_curmin=0
In this mode there is a minimum coil current necessary before switching off the PMOS. As result there are less pulses at low
output load necessary, and therefore the efficiency at low output load is increased. This results in higher ripple, and noisy
pulse skip operation up to a higher output current.
Figure 16 –sdX_dis_curmin=0 operation
Te
1: LX voltage, 2:coil current (1mV=1mA) 3: Vout
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lv
al
id
Specification, Confidential
am
lc s
on A
te G
nt
st
il
It’s also possible to switch between these two modes during operation:
E.g.:
sdX_dis_curmin=0: System is in idle state. No audio, RF signal. Decreased supply current preferred. Increase ripple doesn’t
effect system performance.
sdX_dis_curmin=1: System is operating. Audio signal on and/or RF signal used. Decreased ripple and noise preferred.
Increased power supply current can be tolerated.
100% PMOS ON mode for low dropout regulation:
For low input to output voltage difference the sdX_dis_pon bit can be set, to allow 100% duty cycle of the PMOS transistor, if
the output voltage drops by more than 4%.
Low power mode:
The sdX_lpo mode bit can be set all the time. This mode allows internal power down, of not used blocks during pulseskip
mode, which results in a better efficiency at light output loads.
Inductor setting:
ni
ca
The step down regulator is optimised for 2.2μH at 2.2MHz and 4.7μH at 1.1MHz
Use the following settings for optimised operation:
sdX_4u7=1 for 4.7μH at 1.1MHz
sdX_4u7=0 for 2.2μH at 2.2MHz
Table 47 – Step Down DC/DC Converter parameters
Parameter
Min
Input voltage
ch
Symbol
Te
VIN
VOUT
Regulated output voltage
VOUT_tol
Output voltage tolerance
ILIMIT
Current limit
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TYP
Max
Unit
Note
3.0
5.5
V
PIN VSUPPLY_1,VSUPPLY_2,
VSUPPLY_3
0.6
3.3
V
-50
+50
mV
output voltage <2.0V
-100
+100
mV
output voltage >2.0V
800
Revision 0.22 / 17.12.2007
mA
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Symbol
Parameter
RPSW
Min
TYP
Max
Unit
Note
P-Switch ON resistance
0.5
Ω
V_SUPPLYx=3.0V
RNSW
N-Switch ON resistance
0.5
Ω
V_SUPPLYx=3.0V
Iload
Load current
500
mA
fSW
Switching frequency
Cout
Output capacitor
Lx
Inductor
ηeff
Efficiency
90
IVDD
0
MHz
sdX_frequ=0, fclk_int =2.2MHz
1.1
MHz
sdX_frequ=1, fclk_int =2.2MHz
10
μF
Ceramic
μH
+/- 10% tolerance
%
Iout=100mA, Vout=2.3V, Vsup.=3V
Current consumption
250
100
0.1
μA
Operating current without load
Low power mode current
Shutdown current
tMIN_ON
Minimum on time
80
ns
tMIN_OFF
Minimum off time
lv
4.7
am
lc s
on A
te G
nt
st
il
2.2
al
id
2.2
40
VLineReg
Line regulation
VLoadReg
Load regulation
tbd
tbd
tbd
tbd
ns
mV
mV
Static
Transient;Slope: tr=10μs
Static
Transient;Slope: tr=10μs
Table 48 – Step Up DC/DC Bit definitions
Name
Default
0
Description
Step down curmin feature control
0: curmin feature enabled: Inductor current regulated to min 170mA.
Higher efficency in low dropout and low output current operation. Higher
output ripple and noise.
1: curmin feature disabled: Decreased efficiency in low dropout mode and
at low output current. Small output ripple and noise.
R/W
ca
sdX_dis_curmin
Access
sdX_dis_pon
R/W
ni
0
Step down pon feature control
0: PON feature enabled: 100% duty cycle (pmos always on) if output
voltage drops more than 4%. Increased output ripple in that operation.
1: PON feature disabled: Maximum dutycycle=1-(tmin_off*fsw)
Set always to 0
0
R/W
Step down low power mode:
0: Increased current consumption in pulseskip mode
1: Decreased current consumption in pulseskip mode
00h
R/W
Switch on/off the step down dc/dc converter
00h
R/W
Inverts the input clock of the step down converter
sdX_psw_on
R/W
Only if buck_on = 0, switch on PSW (0.5Ω PMOS)
sdX_dis_n
R/W
If ‘1’ the synchron rectifier is disabled (NSW is always off)
sdX_4u7
R/W
If ‘1’ optimise operation for 4.7μH inductor
sdX_nsw_on
R/W
Only if buck_on = 0, switch on NSW (0.5Ω NMOS)
ch
sdX_lpo
Te
sdX_on
sdX_clkinvert
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Name
Default
Access
Description
Control the voltage selection for the step down DC/DC converter
sdX_v
000000 0.6 V
… (LSB=50mV)
111000 – 11111 3.4 V
R/W
Select the step down frequency
R/W
0 fclk_int (1.6MHz to 2.3 MHz)
1 fclk_int/2 (0.8MHz to 1.15 MHz)
al
id
sdX_frequ
lv
7.10.1 Typical Performance Characteristics
am
lc s
on A
te G
nt
st
il
Figure 17 – DC/DC step-down Efficiency (sdX_dis_curmin=0, sdX_lpo=0)
Efficiency vs Output Current
100
VIN=3.6V
Different VOUT
95
3.3V
EFFICIENCY [%]
90
3.1V
1.8V
85
1.2V
80
75
70
DCDC stepdown
0..500mA
65
60
1
10
100
OUTPUT CURRENT [mA]
1000
ni
ca
0
Te
ch
Figure 18 –PCB Layout recommendation
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al
id
Specification, Confidential
Table 49 – Step down Register map
Name
Add
r. 12
Reg Power1 Ctrl
23
Step Down Control1
32
Step Down Control2
33
Step down charger
control
34
7.11
Content
am
lc s
on A
te G
nt
st
il
Register Definition
Default
b7
ROM
cp_on
sd2_nsw
_on
sd3_dis_
pon
00h
00h
b6
b5
b4
sd3_on
sd2_on
sd1_on
sd2_dis
_n
sd1_dis
_pon
sd2_dis
_curmin
sd2_ps
w_on
sd2_4u7
sd2_dis
_pon
sd2_dis
_curmin
00h
sdX_lpo
b3
b2
b1
b0
ldo_dig2
_on
sd1_ns
w_on
sd3_ns
w_on
ldo_dig1
_on
ldo_rf2_
on
sd1_dis
_n
sd3_dis
_n
ldo_rf1_
on
sd1_psw
_on
sd3_psw
_on
sdc_freq
u
sd1_4u7
sd3_4u7
sd1_dis
_curmin
Low Dropout Regulators (LDO)
The low dropout regulators are linear high performance regulators with programmable output voltage.
ca
They are controlled by the following registers:
Table 50 – LDO’s Bit definitions
Te
ldo_rfX_v
ldo_digX_v
Acces
R/W
ch
ldo_rfX_on
Default
ni
Name
BootROM
Description
Switch on control of RFX LDO (X = 1,2); Important: Set rfX_sw=0 before
setting ldo_rfX_on=1
Control the voltage selection for LDO’s VRF_1 – VRF_2
R/W
R/W
00000 1.85V
… (LSB=50mV)
11111 3.40V
Control the voltage selection for LDO’s VDIG_1 and VDIG_2
(see Table 54 – Digital LDO (VDIG_1, VDIG_2) Programming voltage table)
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
12
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Acces
Name
Default
Description
rfX_sw
ROM
R/W
If ‘1’ RFx-LDO is operating as High side switch (Ron=1Ω) , valid if ldo_rfX_on=0
rf1_swprot_en
ROM
R/W
If ‘1’ current limitation is enabled, if RFx-LDO is operating as High side switch
rf1_lcurr_en
ROM
R/W
If ‘1’ current limitation Ilimit=Ilimit/2
If ‘0’ current limitation = Ilimit
al
id
7.11.1 RF LDO’s (VRF_1 - VRF_2)
am
lc s
on A
te G
nt
st
il
lv
These LDO’s are designed to supply sensitive analogue circuits like LNA’s, Transceivers, VCO’s and other critical RF
components of cellular radios. Another application is the supply of audio devices or as a reference for AD and DA converters.
The design is optimised to deliver the best compromise between quiescent current and regulator performance for battery
powered devices.
Stability is guaranteed with ceramic output capacitors of 1μF +/-20% (X5R) or 2.2μF +100/-50% (Z5U) for RF2 and 2.2μF +/20% (X5R) or 4.7μF +100/-50% (Z5U) for RF1. The low ESR of these caps ensures low output impedance at high frequencies.
Regulation performance is excellent even under low dropout conditions, when the power transistor has to operate in linear
mode. Power supply rejection is high enough to suppress the PA-ripple on the battery in TDMA systems at the output. The low
noise performance allows direct connection of noise sensitive circuits without additional filtering networks. The low impedance
of the power device enables the device to deliver up to 150mA even at nearly discharged batteries without any decrease of
performance.
Figure 19 – Analog LDO Blockdiagram
High Gain
Low Bandwidth
Amplifier
Vref
1.8V
Low Noise
DC reference
Low Gain
Ultra High Bandwidth
Amplifier
VBAT
3V-5.5V
PMOS
Power Device
1Ω max.
C_comp
(internal)
Vout
1.85-3.4V
150/300mA Load
1μF for RF2,.
2.2μF for RF1
X5R
external
ni
ca
GND
Table 51 – Analog LDO (VRF_1, VRF_2) Characteristics
ch
Vx_IN=4V; ILOAD=150mA; Tamb=25ºC; CLOAD =2.2μF (Ceramic); unless otherwise specified
Symbol
Parameter
Te
Vx_IN
Supply voltage rage
RON
RON
On resistance
On resistance
PSRR
Power supply rejection ratio
IOFF
IVDD
Noise
Shut down current
Supply current
Output noise
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Min
3
Typ
Max
Unit
5.5
V
0.5
1
Ω
Ω
70
40
dB
100
50
50
Revision 0.22 / 17.12.2007
nA
μA
μVrms
Note
VRF_1
VRF_2
f=1kHz
f=100kHz
without load
10Hz < f < 100kHz
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tstart
Min
Typ
Max
Startup time
Vout
Unit
200
μs
1.85
2.85
V
1.85
3.4
V
-50
-1
-10
-1
-10
50
1
10
1
10
mV
Output voltage
Vout_tol
Output voltage tolerance
VLineReg
Line regulation
VLoadReg
Load regulation
ILIMIT_VRF1_H
CURR
ILIMIT_VRF1_L
CURR
mV
800
mA
Current limitation
400
mA
400
2
1
Static
Transient;Slope: tr=10μs
Static
Transient;Slope: tr=10μs
mV
Current limitation
Current limitation
Load capacitor
Load capacitor
VRFX_IN>3.0V, VRF1 @
Iout=300mA, VRF2 @ Iout=150mA
(X=1,2)
VRFX_IN>3.55V, VRF1 @
Iout=300mA, VRF2 @ Iout=150mA
(X=1,2)
mA
μF
μF
5
5
VRF_1, rf1_lcurr_en=0
VRF_1, rf1_lcurr_en=1 and during
startup
VRF_2
ceramic only
ceramic only
am
lc s
on A
te G
nt
st
il
ILIMIT_VRF2
CLOAD_RF1
CLOAD_RF2
Note
al
id
Parameter
lv
Symbol
Table 52 – LDO_RF Register map
Register Definition
Name
Add
r. 13
LDO_RF1 Voltage
03
LDO_RF2 Voltage
04
Reg Power1 Ctrl
23
Default
Content
b7
ROM
b6
b5
rf1_swpr
ot_en
rf1_lcurr
_en
b4
b3
cp_on
sd3_on
sd2_on
b1
b0
ldo_rf2_
on
ldo_rf1_
on
ldo_rf1_v
ROM
ROM
b2
sd1_on
ldo_dig2
_on
ldo_rf2_v
ldo_dig1
_on
7.11.2 Digital LDO’s (VDIG_1, VDIG_2)
Te
ch
ni
ca
The Digital LDO’s can be used in any medium power system or subsystem where quiescent power consumption of the
regulator itself has to be minimised without sacrificing its performance. For its stability a cheap 1uF ceramic capacitor is
required. The 5V charge pump will be switch on automatically, if one of the digital LDO’s are switched on
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
13
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Figure 20 – Digital LDO Blockdiagram
LDOCharge
Pump
Battery
1uF
ceramic
to μP-, DSP- or
memory supply
.
Table 53 – Digital LDO (VDIG_1, VDIG_2) Characteristics
VSUPPLY=4V; ILOAD=200mA; Tamb=25ºC; CLOAD =1uF (Ceramic); unless otherwise specified
Parameter
Min
Typ
Max
Unit
5.5
4
V
Ω
Note
am
lc s
on A
te G
nt
st
il
Symbol
lv
al
id
Vbg
VDIGX_IN
RON
Supply voltage range
On resistance
1
PSRR
Power supply rejection ratio
IOFF
IVDD
tstart
Shut down current
Supply current
Startup time
Vout
Output voltage
0.75
Vout_tol
Output voltage tolerance
VLineReg
Line regulation
VLoadReg
Load regulation
-50
-10
-50
-20
-50
ILIMIT
Current limitation
60
30
dB
100
20
200
2.20
2.5
50
10
50
20
50
400
nA
μA
μs
V
V
mV
mV
mV
f=1kHz
f=100kHz
without load
Vsup.>3.0V, V5_6=5.2V, Iout<200mA
Vsup.>3.0V, V5_6=5.2V, Iout<100mA
Static
Transient;Slope: tr=10μs
Static
Transient;Slope: tr=10μs
mA
0.75
0.80
0.85
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
ni
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
Te
ch
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ca
Table 54 – Digital LDO (VDIG_1, VDIG_2) Programming voltage table
Code (d)
Code (b)
Vout [V]
Code (d)
Code (b)
Vout [V]
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22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
Revision 0.22 / 17.12.2007
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.50
1.60
1.70
1.80
1.90
2.00
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AS3654
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Code (d)
Code (b)
Vout [V]
Code (d)
Code (b)
Vout [V]
16
17
18
19
20
21
010000
010001
010010
010011
010100
010101
1.55
1.60
1.65
1.70
1.75
1.80
38
39
40
41
42
100110
100111
101000
101001
101010
2.10
2.20
2.30
2.40
2.50
b6
b5
Note: full performance for Vout≤2.20V
max. 100mA output current for Vout≤2.50V
don’t use values Vout>2.50V
Table 55 – LDO_DIG Register map
Name
Add
r. 14
Default
05
06
ROM
ROM
Reg Power1 Ctrl
23
ROM
b7
cp_on
sd3_on
b4
sd2_on
b3
sd1_on
b2
b1
b0
ldo_dig1_v
ldo_dig2_v
ldo_dig2 ldo_dig1
_on
_on
ldo_rf2_
on
ldo_rf1_
on
am
lc s
on A
te G
nt
st
il
LDO_DIG1 Voltage
LDO_DIG2 Voltage
Content
lv
Register Definition
al
id
Specification, Confidential
7.11.3 Low power LDO (V2_5)
The Low power LDO V2_5 is needed to supply the chip core (analog and digital) of the device. It is designed to get the lowest
possible power consumption, and still offering reasonable regulation characteristics. The regulator has three supply inputs
selecting automatically the higher one. This gives the possibility to supply the chip core either with the battery or with the
charger depending on the conditions. Bulk switch comparators are used to avoid any parasitic current flow. To ensure high
PSRR and stability, a low-ESR ceramic capacitor of min. 1μF must be connected to the output.
Note: Levelshifters in both directions (input- and output) are placed between digital pins and the digital core of the device.
Table 56 – Low power LDO (V2_5) Characteristics
VBAT=4V; ILOAD_ext=0; Tamb=25ºC; CLOAD =2.2μF (Ceramic); unless otherwise specified
Symbol
Parameter
VBAT
VCHARGER
RON
Min
Typ
2.8
4
Supply voltage rage
5.5
15
50
On resistance
ca
Max
60
40
Unit
V
Ω
Power supply rejection ratio
IOFF
Shut down current
100
nA
IVDD
Supply current
3
μA
200
2.6
50
10
50
10
50
μs
V
mV
ni
PSRR
Startup time
Output voltage
Output voltage tolerance
ch
tstart
Vout
Vout_tol
Line regulation
VLoadReg
Load regulation
Te
VLineReg
2.4
-50
-10
-50
-10
-50
dB
2.5
Note
mV
mV
Guaranteed per design
f=1kHz
f=100kHz
Guaranteed per design, consider
chip internal load for meas.
Static
Transient;Slope: tr=10μs
Static
Transient;Slope: tr=10μs
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
14
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7.12
5V Charge Pump
am
lc s
on A
te G
nt
st
il
lv
al
id
Figure 21 – Digital LDO Blockdiagram
The charge pump uses the pad VCP_IN as input, regulates and doubles its voltage with the help of the flying capacitor
between CAPP and CAPN to its output VCP_OUT. If the bit cp_pulseskip is set, the charge pump operates in pulse skip
mode, and only starts cycles if its output voltage is below this level. In this mode the supply current is reduced.
The charge pump requires the following external components:
Parameter
Min
Typ
Max
Unit
Note
CFLY
External flying capacitor
370
470
850
nF
ni
ca
Table 57 – Charge Pump External Components
Symbol
Ceramic X5R or X7R low-ESR
capacitor between CAPP and CAPN
1.76
2.2
2.64
μF
Ceramic low-ESR capacitor between
VCP_OUT and VSS
A
Peak current
External storage capacitor
ch
CSTORE
1
Te
Dout
Schottky Diode for startup
between VCP_IN and
VCP_OUT
Make the connections of the two external capacitors as short as possible.
Table 58 – Charge Pump Characteristics
Symbol
VCPIN
Parameter
Charge Pump input voltage
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Min
3.0
Typ
Max
5.5
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Unit
Note
V
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Parameter
Min
Typ
fIN
Switching frequency
ICPOUT
Output Current
0.0
VCPOUT
Output Voltage
Output Voltage during
pulseskip
Supply current without load
Charge pump supply current
without load in pulseskip mode
4.9
VCPSKIP
ICP_noload
ICP_pulseskip
Max
Unit
1.1
0.55
Note
MHz
MHz
5.2
100
mA
5.6
V
cp_freq=0, fclk_int=2.2MHz
cp_freq=1, fclk_int=2.2MHz
VCP_IN = 3.2V, Clock = fclk_int/2;
cp_pulseskip=0; fin=1.1MHz
4.92
V
Use with cp_frequ=1 only
2
mA
1.1MHz switching frequency
20
μA
cp_pulseskip=1 and cp_frequ=1
al
id
Symbol
Table 59 – Charge Pump Bit definitions
Default
Access
cp_on
Description
Switch on of the charge pump block, charge pump is automatically activated
when any of the following blocks are active: VDIG1, VDIG2
R/W
Switches on the pulseskip mode of the charge pump
R/W
am
lc s
on A
te G
nt
st
il
cp_pulseskip
lv
Name
ROM
0 Normal fixed frequency mode
1 Pulse skip, low power mode (Set cp_frequ=1 in this mode)
Defines the clock frequency of the step up dc/dc converter
cp_freq
R/W
fclk_int/2 (0.8 to 1.15 MHz)
fclk_int/4 (0.4 to 0.575 MHz)
0
1
Table 60 – Charge pump Register map
Register Definition
Name
Charge Pump
Control
Add
r. 15
Content
b7
b6
b5
b4
ROM (00h)
b3
b2
b1
b0
cp_clkin
v
cp_freq
cp_puls
eskip
Te
ch
ni
ca
14
Default
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
15
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7.13 Audio
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Figure 22 – Audio Blockdiagram
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7.14 Common mode voltage generation of HP_CM, LINE_CM
lv
Maximum achievable PSRR
@ 1kHz (typ)
@ 100Hz (typ)
dB
dB
76
56
90
76
am
lc s
on A
te G
nt
st
il
Table 61 – common mode voltage, Audio start-up and PSRR
Capacitor value for C_hpcm and C_linecm
Startup time
(typ)
uF
msec
0.1
150
1
1500
al
id
The common mode voltage of the Headphone and Lineout is stored in the C_hpcm and C_linecm capacitor. These capacitor
are also responsible for the popless startup, PSRR of the amplifiers and sense path of the GND cancellation circuit.
Startup and PSRR is defined by the value of the external capacitors. The RC limits the maximum achievable PSRR:
R=6MOhm typ, C=0.1...1uF :
7.15 First AudioSet Register
Audio LDO has to be switched on first, and enables all other functions.
The register is R/W; default value is 00h
Table 62 - AudioSet1 Register
Symbol
4
aud_ldo_on
3
gnd_sw_on
2
mux_sel
1
dac_on
0
lin_on
Description
00h
MCLK invert selection
0: Change of LRCLK at falling edge of MCLK
1: Change of LRCLK at rising edge of MCLK
Audio LDO ON control
0: Audio LDO off
1: Audio LDO on
0: GND switch off 0V at pin GND_SW
1: GND switch on Vsupply at pin GND_SW
0: DAC input selected
1:Line input selected
Switch on control of AUDIO DAC
1: DAC enabled (Switch on , if I2S signal valid only)
0: DAC disabled
1: Line input enabled
0: Line input disabled
ca
mclk_invert
Default
ch
ni
Bit
7
6
5
Second AudioSet Register
Te
The register is R/W; default value is 00h
Table 63 - AudioSet2 Register
Bit
7
Symbol
I2S_mclk_en
Default
0h
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Description
0: Generation of the master clock by the internal
PLL
1: Use Pin LRCLK_2 as MCLK_1 input; (the bit I2S_select
is used to switch between MCLK *128 = LRCLK and
MCLK *256 = LRCLK)
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I2S_select
5,4
ibr_hph<1:0>
3
2
NA
dith_on
1,0
ibr_dac<1:0>
0h
0:Select I2S_1 input
1:Select I2S_2 input
Bias current reduction settings for headphone output:
00: 0%
01: 17%
10: 34%
11: 50%
Don’t use
1: add dither to the audio stream
0: no dither added
Bias current reduction settings for DAC:
00: 0%
01: 25%
10: 40%
11: 50%
Table 64 – Low voltage status Register
Symbol
hpdet
Default
NA
Description
Headphone detect status register
am
lc s
on A
te G
nt
st
il
Bit
5
lv
6
al
id
Specification, Confidential
7.16 Digital Audio Input
7.16.1 General
Digital audio data can be fed into the AS3654 via the I2S interface These input data are then used by the 18-bit DAC to
generate the analog audio signal.
The stage is set to mute by default; If the DAC input is not enabled.
7.16.2 Signal Description
The digital audio interface uses the standard I2S format:
-
left justified
MSB first
one additional leading bit
Te
ch
ni
ca
MCLK has to have a fixed ratio of 128 or 256 to LRCK. With a LRCK equal to 32, 44.1 or 48kHz, the MCLK can be generated
by the on-chip PLL (do not use the internal PLL if there is jitter on the LRCLK1 or 2). For lower sample rates the MCLK has to
generated external.
The high going edge of MCLK has to have timing separation from LRCK edges. If the clock generation is so that LRCK
edges are at the same time as MCLK high going edges, the MCLK can be inverted to guarantee a proper DAC function.
This audio input interfaces uses an I2S synchroniser to be able to handle audio sample length of 24bits or less.
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Figure 23 – I2S Timing Diagram
64 cycles
64 cycles
MCLK
LRCK
Left Channel
Right Channel
SCLK
15
16 bit
2
1
0
15
2
1
0
SDATA
17
18 bit
2
1
0
17
2
0
I2S_mclk_en
I2S_select
mclk_invert
0
0
0
0
am
lc s
on A
te G
nt
st
il
lv
Table 65 – PLL,MCLK Settings
1
al
id
SDATA
0
0
1
1
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Description
I2S_1 selected (PLL used)
Internal MCLK synchronised to external LRCLK
I2S_1 selected (PLL used)
Internal LRCLK used, synchronised to external SDI
I2S_2 selected (PLL used)
Internal MCLK synchronised to external LRCLK
I2S_2 selected (PLL used)
Internal LRCLK used, synchronised to external SDI
I2S_1 selected, external MCLK *128 = LRCLK
I2S_1 selected, external MCLK *128 = LRCLK
MCLK input inverted
I2S_1 selected, external MCLK *256 = LRCLK
I2S_1 selected, external MCLK *256 = LRCLK
MCLK input inverted
7.16.3 Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption with the
register ibr_dac<1:0>.
ca
7.16.4 Parameter
ch
ni
Table 66 - AudioDAC Parameter
PARAMETER
ANALOG PERFORMANCE
THD+Noise at FS
Dynamic Range (20Hz-20kHz, -60dBFS) A-weighted
Interchannel Mismatch
MIN
TYP
MAX
UNIT
-85
93
-75
90
dB
dB
dB
0.25
Te
Table 67 - I2S Parameter
I2S Inputs and Outputs VI2S=2.9V
VIL
SCLKx, LRCKx, SDIx (30%VI2S/2)
VIH
SCLKx, LRCKx, SDIx (70%VI2S/2)
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MIN
1.02V
TYP
-
MAX
0.42V
VI2S
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Table 68 – Audio Register map
Name
Add
r. 16
Default
Audio Set1
57
00h
Audio Set2
58
00h
Content
b7
b6
I2S_mcl
k_en
b5
b4
b3
b2
b1
mclk_in
vert
aud_ldo
_on
gnd_sw
_on
mux_sel
dac_on
I2S_sel
ect
ibr_hph
dith_on
Table 69 – Low voltage Status register bit
Low voltage Status
Default
47
40h
7.17 Line Input
7.17.1 General
Content
b7
b6
stpup1_
det
stpup1_
oc
b5
hpdet
b4
b3
b2
dig2_lv
dig1_lv
ibr_dac
b1
sd3_lv
b0
sd2_lv
sd1_lv
lv
Name
Add
r. 17
lin_on
am
lc s
on A
te G
nt
st
il
Register Definition
b0
al
id
Register Definition
AS3654 includes one stereo single ended inputs.
Table 70 - Line Inputs Parameter
PARAMETER
ANALOG PERFORMANCE
Rin
MIN
TYP
50
MAX
UNIT
kOhm
ca
7.18 Headphone Output
ni
The headphone output is designed to provide the audio signal with 2x40mW @ 16Ω or 2x20mW @32Ω, which are typical
values for headphones.
ch
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can
be set from –40.5dB to +6dB.
7.18.1 Phantom Ground
Te
HP_CM_PWR pin is the buffered HP_CM output. It can be used to drive the loads without external de-coupling capacitors
between HPL / HPR and HPCM. If the load is between HPR / HPR and BVSS, 100uF of de-coupling capacitors are
Register address codes
ROM-adr. 25-30…Power1
17 Register address codes
ROM-adr. 25-30…Power1
16
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
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needed. The phantom ground can be switched off to save power if not needed.
7.18.2 No-Pop Function
To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output
stage is disabled. Also the volume settings are set to their default values, and can’t be changed, as long the output stage
is not enabled.
al
id
HP_CM pin, which needs a 100nF to 1uF capacitor outside, gets charged on power-up with 1uA to AVDD/2. After start-up
the DC level of the following pins are the same: HPR=HPL=HP_CM=HP_CM_PWR=AVDD/2. The Start-up time before
releasing mute is about 150ms. To avoid pop-noise 150ms discharging time of HP_CM after a shutdown, have to be
waited before starting up again.
7.18.3 Over-current Protection
am
lc s
on A
te G
nt
st
il
lv
This output stage has an over-current protection, which disables the output for 256ms or 512ms. This value can be set in
the headphone registers. The over-current protection limit of HPR and HPL pin is about 260mA while HP_CM_PWR pin
has a 370mA limit.
7.18.4 Headphone Detection
With a control bit the headphone detection can be enabled. The detection is only working as long the headphone stage is
in power down mode and the load is applied between HPR / HPL and HP_CM_PWR.
7.18.5 Power Save Options
To save power, especially when driving 32 Ohm loads, a reduction of the bias current can be selected.
Bias current reduction settings for headphone output:
00: 0%
01: 17%
10: 34%
Te
ch
ni
ca
11: 50%
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Parameter
TYP
MAX
16
1.13
-20
-66
-60
20
150
50
50
40
Ohm
Vp
dB
dB
dB
dB
dB
dB
dB
dB
mA
mA
μA
ms
lv
60
±0.5
-97
-88
-80
-74
-68
60
90
260
370
UNIT
al
id
MIN
am
lc s
on A
te G
nt
st
il
Table 71 - Power Amplifier Parameter
PARAMETER
ANALOG PERFORMANCE
R_Load at AOUTR and AOUTL single ended
Vout
Gain Step Precision (RLmin-max,20Hz-20kHz)
SINAD no load, LineIn-> HPH, A-weighted
THD @ 1kHz, no load
THD @ 1kHz, 32Ohm, 10mW
THD @ 1kHz, 32Ohm, 20mW
THD @ 1kHz, 16Ohm, 40mW
Channel Separation (32Ohm, dc-coupled)
PSRR (200Hz-20kHz)
Shorted Protection Level
Shorted Protection Level of common mode buffer
IOUT_powerdown
Tpower_up (HP_CM=0.1μF)
100Hz
GND cancellation GND - AUDIO_GND to
1kHz
HP_R, HP_L no load
10kHz
Te
ch
ni
ca
dB
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7.18.6 Register Description
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set. Changing the
bias current or the output driver strength is done via AudioSet2 register. All other headphone driver settings are controlled by
the following two registers.
Right Headphone Register
The register is R/W; default value is 00h
Table 72 - HPH_OUT_R Register
5
Description
headphone over current time out:
speaker over current time out:
11: 0 ms
10: 512 ms
01: 128 ms
00: 256 ms
headphone phantom ground disable
0: normal operation
1: disable common mode buffer
volume settings for right headphone output, adjustable in 32 steps @
1.5dB
00000: -40.5 dB gain
00001: -39 dB gain
..
11110: 4.5 dB gain
11111: 6 dB gain
hpcm_off
am
lc s
on A
te G
nt
st
il
00h
4..0
al
id
Default
lv
Bit
Symbol
7..6
hp_ovc_to
hpr_vol
Left Headphone Register
The register is R/W; default value is 00h
Table 73 - HPH_OUT_L Register
Symbol
hp_mute
6
hp_on
5
hpdeton
4..0
hpl_vol
Default
Description
ni
00h
ch
Te
0: normal operation
1: headphone output set to mute (mute is on during power-up)
0: headphone stage not powered
1: power up headphone stage
0: no headphone detection
1: enable headphone detection
volume settings for left headphone output, adjustable in 32 steps @
1.5dB
00000: -40.5 dB gain
00001: -39 dB gain
..
11110: 4.5 dB gain
11111: 6 dB gain
ca
Bit
7
Table 74 – Headphone Register map
Register Definition
Add
Default
Content
18
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
18
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Name
b7
HPH out R
HPH out L
59
60
00h
00h
b6
hp_ovc_to
hp_mute hp_on
b5
hpcm_off
hpdeton
b4
b3
b2
b1
b0
hpr_vol
hpl_vol
7.19 Line Output
al
id
7.19.1 General
The line output is designed to provide the audio signal on 600 Ω min.
This output stage has an independent gain regulation for left and right channel with 32 steps @ 1.5dB each. The gain can be
set from –40.5dB to +6dB..
lv
7.19.2 No-Pop Function
am
lc s
on A
te G
nt
st
il
To avoiding click and pop noise during power-up and shutdown, the output is automatically set to mute when the output stage
is disabled. Also the volume settings are set to their default values, and can’t be changed, as long the output stage is not
enabled.
LINE_CM pin, which needs a 0.1μF... 1μF capacitor outside gets charged on power-up with 1uA to ALVDD/2. After start-up
the DC level of the following pins are the same: LOUT_L=LOUT_R=LINE_CM= ALVDD/2. The Start-up time before releasing
mute is about 150ms with 0.1μF. To avoid pop-noise 150ms discharging time of LINE_CM after a shutdown, have to be
waited before starting up again.
7.19.3 Power Save Options
To save power, a reduction of the bias current can be selected.
Table 75 - Line Power-Save Options
IDD_LINE (typ.)
2.2mA
1.5mA
Te
ch
ni
ca
IBR_LINE
0
1
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7.19.4 Parameter
TYP
MAX
600
20
150
50
50
40
Ohm
dB
dB
dB
dB
dB
μA
ms
lv
60
-20
±0.5
-97
-88
-80
90
UNIT
al
id
MIN
dB
am
lc s
on A
te G
nt
st
il
Table 76 - Line out Block Characteristics
PARAMETER
ANALOG PERFORMANCE
R_Load at LOUT_L and LOUT_R single ended
Gain Step Precision (RLmin-max,20Hz-20kHz)
SINAD no load, LineIn-> Line out, A-weighted
THD @ 1kHz, no load
THD @ 1kHz, 600Ohm
PSRR (200Hz-20kHz)
IOUT_powerdown
Tpower_up (C_LINECM=100nF)
100Hz
GND cancellation GND - AUDIO_GND to
1kHz
LOUT_R, LOUT_L no load
10k
7.19.5 Register Description
To get an interrupt on an over-current event, the corresponding bit in the Interrupt enable register has to be set. All other
Line/headphone driver settings are controlled by the following two registers.
Right Line Register
The register is R/W; default value is 00h
Table 77 - LINE_OUT_R Register
7,6
ibr_line<1:0>
5
-
4..0
liner_vol
Default
Description
Bias current reduction settings for line output:
00: 0%
01: 17%
10: 34%
11: 50%
reserved
volume settings for right Line output, adjustable in 32 steps @ 1.5dB
00000: -40.5 dB gain
00001: -39 dB gain
..
11110: 4.5 dB gain
11111: 6 dB gain
00h
ca
Name
ni
Bit
ch
Left Line Register
The register is R/W; default value is 00h
Te
Table 78 - LINE_OUT_L Register
Bit
Symbol
7
line_mute
6
line_on
5
-
Default
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Description
0: normal operation
1: Line output set to mute (mute is on during power-up)
0: Line stage not powered
1: power up Line stage
reserved
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4..0
volume settings for left Line output, adjustable in 32 steps @ 1.5dB
00000: -40.5 dB gain
00001: -39 dB gain
..
11110: 4.5 dB gain
11111: 6 dB gain
linel_vol
Register Definition
Name
Add
r. 19
Default
61
00h
Line out L
62
00h
b7
b6
b5
b4
b3
ibr_line
line_mut
line_on
e
b2
liner_vol
linel_vol
b1
b0
am
lc s
on A
te G
nt
st
il
lv
Line out R
Content
al
id
Table 79 – Lineout Register map
7.20 I2C Serial Interface
Table 80 – I2C SDA,SCL Characteristics
Symbol
Parameter
Min
VIL
SCL,SDA Low Level input
voltage
VIH
SCL,SDA High Level input
voltage
Feature List
Max
Unit
-0.3
0.4
V
1.3
VSUPP
LY
V
Note
ca
Fast-mode capability (max. SCL-frequency is 400 kHz)
7+1-bit addressing mode
60h x 8-bit data registers (word address 0x00 - 0x60)
Write formats:
Single-Byte-Write, Page-Write
Read formats:
Current-Address-Read, Random-Read, Sequential-Read
SDA input delay and SCL spike filtering by integrated RC-components
Te
ch
ni
•
•
•
•
•
•
Typ
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
19
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Transfer Formats
Figure 24 – I2C Byte-Write:
DW
A
WA
A
reg_data
S
Sr
DW
DR
WA
A
N
P
white field
grey field
WA++
A P
write register,
WA++
START condition after STOP
repeated START
device address for write
device address for read
word address
acknowledge
no acknowledge
stop condition
slave as receiver
slave as transmitter
increment word address internally
al
id
S
Figure 25 – I2C Page-Write:
DW
A
WA
A
reg_data 1
A
reg_data 2
…
A
reg_data n
am
lc s
on A
te G
nt
st
il
S
lv
AS3654 device address write (DW):80h = 10000000b
AS3654 device address read (DR): 81h = 10000001b
write register
WA++
write register
WA++
A P
write register
WA++
Byte-Write and Page-Write are used to write data to the slave.
The transmission begins with the START condition, which is generated by the master when the bus is in IDLE state (the bus is
free). The device-write address is followed by the word address. After the word address any number of data bytes can be send
to the slave. The word address is incremented internally, in order to write subsequent data bytes on subsequent address
locations.
For reading data from the slave device, the master has to change the transfer direction. This can be done either with a
repeated START condition followed by the device-read address, or simply with a new transmission START followed by the
device-read address, when the bus is in IDLE state. The device-read address is always followed by the 1st register byte
transmitted from the slave. In Read-Mode any number of subsequent register bytes can be read from the slave. The word
address is incremented internally.
The diagrams below show various read formats available:
Figure 26 – I2C Random-Read:
DW
A
WA
A Sr
ca
S
DR
A
data
read register
WA++
N P
WA++
Te
ch
ni
Random-Read and Sequential-Read are combined formats. The repeated START condition is used to change the direction
after the data transfer from the master.
The word address transfer is initiated with a START condition issued by the master while the bus is idle. The START condition
is followed by the device-write address and the word address.
In order to change the data direction a repeated START condition is issued on the 1st SCL pulse after the acknowledge bit of
the word address transfer. After the reception of the device-read address, the slave becomes the transmitter. In this state the
slave transmits register data located by the previous received word address vector. The master responds to the data byte with
a not-acknowledge, and issues a STOP condition on the bus.
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Figure 27 – I2C Sequential-Read:
S
DW
A
WA
A Sr
DR
A
data 1
A
data 2
…
A
data n
N P
WA++
al
id
read register
WA++
lv
Sequential-Read is the extended form of Random-Read, as more than one register-data bytes are transferred subsequently. In
difference to the Random-Read, for a sequential read the transferred register-data bytes are responded by an acknowledge
from the master. The number of data bytes transferred in one sequence is unlimited (consider the behavior of the wordaddress counter). To terminate the transmission the master has to send a not-acknowledge following the last data byte and
generate the STOP condition subsequently.
S
DR
am
lc s
on A
te G
nt
st
il
Figure 28 – I2C Current-Address-Read:
A
data 1
read register
WA++
A
data 2
…
A
read register
WA++
data n
read register
WA++
N P
WA++
To keep the access time as small as possible, this format allows a read access without the word address transfer in advance
to the data transfer. The bus is idle and the master issues a START condition followed by the Device-Read address.
Analogous to Random-Read, a single byte transfer is terminated with a not-acknowledge after the 1st register byte. Analogous
to Sequential-Read an unlimited number of data bytes can be transferred, where the data bytes has to be responded with an
acknowledge from the master. For termination of the transmission the master sends a not-acknowledge following the last data
byte and a subsequent STOP condition.
7.21 Reset
XRESET is a low active bi-directional pin. An external pull-up to the periphery supply has to be added.
ni
ca
During each reset cycle the following states are controlled by the AS3654:
- Pin XRESET is forced to GND
- Programmable Power-off function
- Programmable Power-on sequence and regulator voltages
- Programmable reset timer
- All registers are set to their default values after power-on, except the reset control- and status-registers.
ch
Note:
Programming is controlled by the internal Mask-PROM and the external resistor RPROGRAM
Te
Table 81 – XRESET,XON Characteristics
Symbol
Parameter
Min
VXRESET_IL
XRESET Low Level input
voltage
VXRESET_IH
XRESET High Level input
voltage
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Typ
Max
Unit
Note
-0.3
0.4
V
TBD
1.3
VSUPPLY
V
TBD
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Symbol
Parameter
Min
Typ
Max
Unit
VXON_IL
XON Low Level input
voltage
-0.3
0.3*V2_5
VXON_IH
XON High Level input
0.7*V2_5
V2_5
IXON_PUP
XON Pull up current
Note
μA
5
al
id
Reset Conditions
am
lc s
on A
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nt
st
il
Voltage detection:
lv
Reset can be activated from 7 different sources:
- Power on (battery or charger insertion)
- Low Battery
- Software forced reset
- Power off mode
- External triggered through the pin RESET
- Overtemperature
- Watchdog
There are two types of voltage dependent resets: VPOR and VXRESET. VPOR monitors the voltage on V2_5 and VXRESET monitors
the voltage on VSUPPLY. The linear regulator for V2_5 is always on and uses the voltage VCHARGER, VBAT or V_USB as
its source.
The pin RESET is only released if V2_5 is above VPOR and VSUPPLY is above VXRESETRISE.
Table 82 – Reset Levels
Symbol
Parameter
Min
Typ
Max
Unit
Note
VPOR
Overall power on reset
1.5
2.0
2.3
V
Monitor voltage on V2_5; power on
reset for all internal functions
VXRESETRISE
Reset level for Vsupply
rising
ResVoltr
ise
V
Monitor voltage on Vsupply; rising
level
2.7
V
Monitor voltage on VSupply; falling
level
ResVotf
all
V
if SupResEn=1 only
ms
Duration for VBAT<VXRESETFALLING
until a reset cycle is started 20
Reset level for Vsupply
falling
ca
VXRESETFALLING
Mask time for
VXRESETFALLING
2.0
2.5
3.0
ni
VRESETMASK
ch
VRESETFALLING is only accepted if the reset condition is longer than VRESETMASK. This guard time is used to avoid a complete
reset of the system in case of short drops of VBAT.
Power off:
Te
To put the chip into ultra low power mode, write ‘1’ into xon_enable and ‘1’ into power_off. The chip waits until the external pin
XON is pulled low, the charger is inserted or the level VPOR is reached to start a complete reset cycle. The bit power_off is
automatically cleared by this reset cycle. During power_off state all circuits are shut-off except the Low Power LDO (V2_5).
Thus the current consumption of AS3654 is reduced to less than 15μA. The digital part is supplied by V2_5, all other circuits
are turned off in this mode, including references and oscillator. Except the reset control registers all other registers are set to
their default value after power-on.
20
VRESET signal is debounced with the specified mask time for rising- and falling slope of VBAT.
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Software forced reset
Writing ‘1’ into the register bit force_reset immediately starts a reset cycle. The bit force_reset is automatically cleared by this
reset.
External triggered reset:
al
id
If the pin XRESET is pulled from high to low by an external source (e.g. microprocessor or button) a reset cycle is started as
well.
Overtemperature reset:
The reset cycle can be started by overtemperature conditions. See section ‘Protection Functions’.
Watchdog reset:
Reset Control Bits
am
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nt
st
il
lv
If the watchdog is armed (register bit wtdg_on = 1 and wtdg_res_on = 1) and the timer expires it causes a reset. See section
‘Watchdog’.
Table 83 – Reset Register map
Register Definition
Name
Add
r. 21
Reset Timer
22
Reset Control
72
Content
Default
b7
b6
b5
b4
b3
b2
xon_ena
ble
ROM (0Fh)
00h
reset_reason
b1
b0
res_timer
xon_inp
ut
power_o
ff
force_re
set
Table 84 – Reset Bit definitions
Default
Access
force_reset
0b
R/W
Setting to ‘1’ starts a complete reset cycle
power_off
0b
R/W
Setting to ‘1’ starts a reset cycle, but waits after the Reg_off state for a falling
edge on the pin XON or until the charger is detected
NA
ROM
R
R/W
This flag represents the state of the XON pad directly
This flag enables the XON pad and sets the power on state of the ASIC
0 XON pad disabled. Startup of chip; if VBAT>VRESETRISING
1 XON pad enabled. Startup of chip; if VBAT>VRESETRISING and XON=0
Te
ch
ni
xon_input
xon_enable
Description
ca
Name
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
21
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Name
Default
Access
Description
Flags to indicate to the software the reason for the last reset
R
Set RESTIME
Reset Cycle
R/W
RESTIME=10ms
RESTIME=20ms
RESTIME=35ms
RESTIME=50ms
RESTIME=65ms
RESTIME=80ms
RESTIME=95ms
RESTIME=110ms
am
lc s
on A
te G
nt
st
il
BootROM
res_timer
000
001
010
011
100
101
110
111
al
id
NA
VPOR has been reached (battery or charger insertion from scratch)
VRESETFALLING was reached (battery voltage drop below 2.75V)
software forced by force_reset
software forced by power_off and XON was pulled low
software forced by power_off and charger was detected
external triggered through the pin RESET
reset caused by overtemperature T140
reset caused by watchdog
lv
reset_reason
000
001
010
011
100
101
110
111
During a reset cycle the pin XRESET is forced to low for at least RESTIME and all registers are set to their default values
(except the bit ov_temp_140 and the Boot-Ctrl register). During the reset time a normal startup happens (see section
‘Startup’), the reset is active until the reset timer (set by register bits res_timer<2:0>) expires. Then the voltage on the pin
XRESET is pulled high by the external resistor and the whole system is leaving the reset state.
res_con: Reset Control
ca
Reset is internally generated from a power supply supervisor and provided to internal logic as well as externally through the
open-drain pad XRESET. At this point, it could be also forced externally from an external power supply supervisor. Additionally
Reset can be forced by software.
7.22 Interrupt Controller
Te
ch
ni
The interrupt controller generates an interrupt request for the host controller as soon as one or more of the bits in the Interrupt
1…2 register is set by pulling low pin XINT. All the interrupt sources can be enabled in the Interrupt Mask 1…2 register. The
Interrupt 1…2 registers are cleared automatically after the host controller has read them. To prevent the AS3654 device from
loosing an interrupt event, the register that is read is captured before it is transmitted to the host controller via the serial
interface. As soon as the transmission of the captured value is complete a logical AND operation with the bitwise inverted
captured value is applied to the register to clear all interrupt bits that have already been transmitted. Clearing the read interrupt
bits takes 2 clock cycles, a read access to the same register before the clearing process has completed will yield a value of ‘0’.
Note that an interrupt that has been present at the previous read access will be cleared as well in case it occurs again before
the clearing process has completed.
During a read access to one of the interrupt registers the XINT pin will be released. As soon as the transferred bits of the
interrupt register have been cleared the XINT pin will be pulled low in case a new interrupt has occurred in the meantime. By
doing so the interrupt controller will work correctly with host controllers that are edge- and level-sensitive on their interrupt
request input. Multiple byte read access is recommended to avoid reading the Interrupt 1 register over and over again in
response to a new interrupt that has occurred in the same register (and thus pulling low pin XINT) before the Interrupt 2
register has been read.
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lv
al
id
Table 85 – Interrupt 1 Register
Address 1; Read only access; register is reset at power-on-reset and after each read access. Default value after reset:
00h.
Bit Symbol
Default Description
Bit is set when the following status bits are set or reset:
0
chstate_i
NA
Trickle, CVM, NoBat
1
cheoc_i
NA
Bit is set when the EOC status bits are set or reset:
2
trickle_tmax_i
NA
Bit is set when trickle charge timeout has been expired
3
usb_chdet_i
NA
Bit is set when the USB_ChDet Bit is set or reset.
4
chdet_i
NA
Bit is set when the ChDet Bit is set or reset.
5
Onkey_i
NA
Bit is set when status XON bit is set or reset.
Bit is set when the lower temperature threshold Temp110 of the temperature
6
ovtmp_i
NA
sensor is exceeded for longer than tRESMASK.
Bit is set when the main supply voltage VSUPPLY has dropped below
7
Lowsup
0
VRESFALL for longer than tRESMASK.
am
lc s
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nt
st
il
Table 86 – Interrupt 2 Register
Address 2; Read only access; register is reset at power-on-reset and after each read access. Default value after reset:
00h.
Bit Symbol
Default Description
Bit is set when voltage of step down1 drops below low voltage threshold
0
sd1_lv_i
0
(1msec debounce time default)
Bit is set when voltage of step down2 drops below low voltage threshold
1
sd2_lv_i
0
(1msec debounce time default)
Bit is set when voltage of step down3 drops below low voltage threshold
2
sd3_lv_i
0
(1msec debounce time default)
Bit is set when voltage of LdoDig1 drops below low voltage threshold
3
dig1_lv_i
0
(1msec debounce time default)
Bit is set when voltage of LdoDig2 drops below low voltage threshold
4
dig2_lv_i
0
(1msec debounce time default)
5
hphcurr_i
0
Bit is set when output stage of headphone amplifier exceeds overcurrent limit.
Bit is set when hp_det status bit is set or reset
6
hpdet_i
O
(1msec debounce time default)
Bit is set when stpup1_oc or stpup1_det is set.
7
stpup1_i
O
Te
ch
ni
ca
Table 87 – Interrupt mask 1 Register
Address 29; R/W access; register is reset at power-on-reset only. Default value after reset: FFh.
Bit Symbol
Default Description
0 chstate_int_mask
1b
0
Interrupt is enabled
1
1 cheoc_int_mask
1b
0
Interrupt is enabled
1
trickle_tmax_int_ma
2
1b
0
Interrupt is enabled
1
sk
usb_chdet_int_mas
3
1b
0
Interrupt is enabled
1
k
4 chdet_int_mask
1b
0
Interrupt is enabled
1
5 onkey_int_mask
1b
0
Interrupt is enabled
1
6 ovtmp_int_mask
1b
0
Interrupt is enabled
1
7 LowSup_int_mask
1b
0
Interrupt is enabled
1
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Table 88 – Interrupt mask 2 Register
Address 30; R/W access; register is reset at power-on-reset only. Default value after reset: FFh.
Bit Symbol
Default Description
0 sd1_lv_int_mask
1b
0
Interrupt is enabled
1 Interrupt is disabled
1 sd2_lv_int_mask
1b
0
Interrupt is enabled
1 Interrupt is disabled
2 sd3_lv_int_mask
1b
0
Interrupt is enabled
1 Interrupt is disabled
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Table 89 – Low voltage status Register
Bit Symbol
Default
0
sd1_lv
0b
1
sd2_lv
0b
2
sd3_lv
0b
3
dig1_lv
0b
4
dig2_lv
0b
5
hpdet
0b
stpup1_oc
0b
7
stpup1_det
0b
Interrupt is enabled
Interrupt is enabled
Interrupt is enabled
Interrupt is enabled
Interrupt is enabled
1
1
1
1
1
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Interrupt is disabled
Description
Step down1 low voltage status bit (-10% voltage drop)
Step down2 low voltage status bit (-10% voltage drop)
Step down3 low voltage status bit (-10% voltage drop)
Ldo Dig1 low voltage status bit (-50mV voltage drop)
Ldo Dig2 low voltage status bit (-50mV voltage drop)
Headphone detect status bit
Bit is set by analog part, if overcurrent of DCDC StepUp1 occurs for more
than 4msec(tbd)
Current Detection signal of step up 1
am
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6
Description
0
0
0
0
0
al
id
Default
1b
1b
1b
1b
1b
lv
Bit Symbol
3 dig1_lv_int_mask
4 dig2_lv_int_mask
5 hphcurr_int_mask
6 hpdet_int_mask
7 stpup1_int_mask
deb_time of low voltage and headphone detect and stpup1_oc and stpup1_det signal = 911μSec
Table 90 – Interrupt Register map
Register Definition
Name
Add
r. 22
43
Interrupt Mask2
44
Interrupt Status1
45
Interrupt Status2
46
Low voltage Status
47
Content
b7
b6
b5
LowBat_
int_m
ovtmp_
int_m
onkey_
int_m
chdet_
int_m
stpup1_i
nt_m
LowBat_
i
hpdet_in
t_m
hphcurr
_int_m
dig2_lv_
int_m
ovtmp_i
onkey_i
chdet_i
NA
stpup1_i
hpdet_i
hphcurr
_i
40h
stpup1_
det
stpup1_
oc
hpdet
FFh
FFh
NA
b4
b3
b2
b1
b0
trickle_t
max_int
_m
sd3_lv_i
nt_m
trickle_t
max_i
dig2_lv_
i
usb_chd
et_
int_m
dig1_lv_
int_m
usb_chd
et_i
dig1_lv_
i
cheoc_i
nt_m
chstate_
int_m
sd2_lv_i
nt_m
sd1_lv_i
nt_m
chstate_
i
sd3_lv_i
sd2_lv_i
sd1_lv_i
dig2_lv
dig1_lv
sd3_lv
sd2_lv
sd1_lv
cheoc_i
Te
ch
ni
ca
Interrupt Mask1
Default
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
22
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7.23 Startup
Figure 29 – Startup flow chart
Power on reset
xon_enable=0
batsw_on=0
batsw_mode=0
Reset registers
except
xon_enable
YES
NO
al
id
xon_enable=1 and
(chdet=0 or
USBChdet=0)
XON pin pulled
to GND
NO
YES
VBAT>VResVolt?
YES
Switch on
Battery switch
Charger
detected ?
NO
USB Sup.
detected and
ChDet=0?
am
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nt
st
il
NO
NO
lv
NO
YES
ChEn=1
YES
USB_ChEn=1
batsw_on=1
batsw_mode=1
YES
VSUPPLY>VResVolt?
YES
Startup Device
Active state
0
1
Switch off
X
batsw_on=0
batsw_mode=0
1
1
0
Te
ch
ni
trickle
Switch on
batsw_on
ca
batsw_mode
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NO
YES
power_off=1
YES
batsw_on=0
batsw_mode=0
NO
VSUPPLY<VResVolt?
YES
NO
force_reset=1
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Normal Startup
During a normal reset cycle (see section Reset), but after V2_5 is above VPOR and Vsupply is above VRESETRISE a normal
startup happens:
•
•
•
•
•
al
id
The external capacitor on CREF is charged to 1.8V (internal signal precharge_n, low active)
The 3bit A/D conversion is performed (configuration: ratio of RBOOT/RBIAS, result→boot_ctrl<2:0>)
Startup Statemachine reads out the internal Boot-ROM (address defined by boot_ctrl), Startsequence of Step-Down
Converter and LDO’s controlled by the Boot-ROM
Reset-Timer is set by the Boot-ROM
The reset is released when the Reset Timer expires (external pin XRESET)
7.23.1 Programmable Startup Sequences
lv
see austriamicrosystems AG document
BootGen3654_2v0_050415.xls
Startup from Charger
am
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nt
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If the voltage on pin VCHARGER is within VSTARTCHARGER, the charger is started in any case (even with VBAT = 0V). This
allows the battery to be charged (even from deep discharge) and finally a normal startup to happen.
Table 91 – Charger Startup Conditions
Symbol
Parameter
Min
Typ
Max
Unit
Note
VSTARTCHARGER
Voltage on
VCHARGER for
system to start
4.0
5.0
15
V
on Pin VCHARGER
7.23.2 Protection Functions
ca
All LDO’s, the DCDC step up and DCDC step down have an integrated overcurrent protection. An overtemperature protection
of the chip is also integrated which can be switched on with the serial interface signal temp_pmc_on. The chip has two
signals for the serial interface: ov_temp_110 and ov_temp_140. The flag ov_temp_110 is automatically reset if the
overtemperature condition is removed, whereas ov_temp_140 has to be reset by the serial interface with the signal
rst_ov_temp_140.
If the flag ov_temp_140 is set, an automatic reset of the complete chip is initiated. The flag ov_temp_140 is not affected by
this reset cycle allowing the software to detect the reason for this unexpected shutdown.
Table 92 – Overtemperature Detection
Parameter
Min
Typ
Max
Unit
T110
ov_temp_110 rising threshold
95
110
125
Degrees
ov_temp_140 rising threshold
125
140
155
Degrees
T140
ov_temp_110 and ov_temp_140
hystersis
5
ch
Thyst
ni
Symbol
Note
Degrees
Te
Table 93 – Overtemperature detection Regsiter definitions
Register Definition
Name
Add
r. 23
Default
Content
b7
b6
b5
b4
b3
b2
b1
b0
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
23
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Register Definition
Name
Overtemperature
Control
Add
r. 23
Content
Default
73
00h
b7
b6
b5
b4
b3
b2
b1
b0
tco_140
_a
tco_110
_a
temp_te
st1
temp_te
st0
rst_ov_t
emp_14
0
ov_temp
_140
ov_temp
_110
temp_p
mc_on
Table 94 – Overtermperature detection Bit definitions
Default
Access
Description
temp_pmc_on
0
R/W
ov_temp_110
NA
R
Flag that the overtemperature threshold 1 (T110) has been reached
ov_temp_140
NA
R
Flag that the overtemperature threshold 2 (T140) has been reached – this flag is
not reset by a overtemperature caused reset and has to be reset by
rst_ov_temp_140
rst_ov_temp_140
0
W
If the overtemperature threshold 2 has been reached, the flag ov_temp_140 is
set and a reset cycle is started. ov_temp_140 should be reset by writing 1 and
afterward 0 to rst_ov_temp_140
temp_test0
0
R/W
Only used for production test; always leave at ‘0’
temp_test1
0
R/W
Only used for production test; always leave at ‘0’
tco_110_a
NA
R
Only used for production test – direct output of T110 comparator
tco_140_a
NA
R
Only used for production test – direct output of T140 comparator
lv
al
id
Switch on / off of temperature supervision; default: off – all other bits are only
valid if set to ‘1’
am
lc s
on A
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nt
st
il
Name
TMP_SV: Temperature Supervision
Comment: If one of the bits temp_test0 or temp_test1 is set, the output of the analog block tco_110_a and tco_140_a must
be ignored.
ni
ca
A temperature sensor is implemented to provide over-temperature protection of the chip. It generates two flags linked to the two
temperature thresholds (110 degrees, 140 degrees). Both thresholds have an hysteresis to prevent oscillation effects.
First threshold (110 degrees) tco_110_a sets the flag ov_temp_110, signalling the serial interface part and software the 110
degrees overtemperature condition. Thus software can react and shuts down power consuming functions to decrease
temperature.
Second threshold (140 degrees) tco_140_a activates reset_140_n, which activates XRESET within rescon: this sets all
regulators into power-down mode and stops charging, and performs the reset cycle of the AS3654.
An additional function also implemented within tmp_sv is the generation of a rst_ov_temp_140 flag indicating, that a 140
degrees overtemperature condition caused the last reset of the digital part.
The signal temp_pmc_on=HIGH activates the temperature supervision.
ch
rstovtemp_140 flag
Te
In case of an activated reset (resetpb_n active), the system loses any information about the error which activated the reset
state. Therefore, a flag is implemented, which indicates that the reset was caused by a reset_140_n activation. For the digital
part, this flag is only resetable via the input signal rst_ovtemp_140:
• reset via signal rst_ovtemp_140
• set in case that reset_140_n goes active
7.23.3 Watchdog
The purpose of the watchdog is to detect a deadlock of the software. If the watchdog is active, it must become continuously a
trigger signal within a programmable time window. If there is no signal anymore for a certain time period from a defined pad or
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special serial interface bit, it starts either a complete reset cycle or changes the state of an output pin, which can be used e.g.
as an interrupt to the processor.
al
id
The watchdog is highly configurable by the following register bits:
The complete block can be switched on by wtdg_on = 1 and off by by wtdg_on = 0.
The watchdog time window is defined by the register wtdg_min_timer and wtdg_max_timer.
The trigger signal can be configured by register wtdg_trigger and wtdg_gpio_input. (Pin CURR1-CURR4 (GPIO1-GPIO4) or
register bit)
If the watchdog expires, the system can start automatically a reset cycle if wtdg_reset_on = 1
Any of the general purpose input / outputs can be configured to output the watchdog signal (see section “General Purpose
Input and Outputs”). The Watchdog delivers a signal “wtdg_alarm”, which is normal ‘0’ and goes to ‘1’ in the case of a timeroverflow. This signal can be used as e.g. a reset or interrupt for a processor.
Table 95 – Watchdog Regsiter definitions
Watchdog Control
Watchdog_min
Timer
Watchdog_max
Timer
Watchdog Software
Signal
53
54
55
56
Content
Default
b7
b6
b5
b4
b3
02h
lv
Name
Add
r. 24
b2
b1
b0
wtdg_tri
gger
wtdg_re
s_on
wtdg_on
am
lc s
on A
te G
nt
st
il
Register Definition
00h
wtdg_min_timer
FFh
wtdg_max_timer
wtdg_
sw_sig
00h
Table 96 – Watchdog Bit definitions
Default
Access
wtdg_on
0b
R/W
Switches on the complete watchdog
wtdg_res_on
1b
R/W
If the watchdog expires and wtdg_res_on = 1 a reset cycle will be started – see
section ‘Reset’
wtdg_trigger
0b
R/W
0 Use the register bit wtdg_sw_signal as trigger signal for the watchdog
1 Use the pin defined by wtdg_gpio_input as trigger signal for the watchdog
Wtdg_min_timer
(00)h
R/W
Defines the minimum watchdog trigger time (LSB=7.5ms, range: 0 – 1.9s)
Wtdg_max_timer
(FF)h
R/W
Defines the maximum watchdog trigger time (LSB=7.5ms, range: 7.5ms – 1.9s),
do not set to (00)h
0b
R/W
Trigger input by the serial interface if wtdg_trigger = 0
ni
wtdg_sw_sig
Description
ca
Name
ch
Figure 30 – Watchdog timing diagram
tmin
tmax
Te
wtdg_trigger
tmin
tmax
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
24
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7.23.4 Internal References (V, I, f clk )
The internal reference circuits needs the following external components:
Table 97 – Rrefernce External Components
Symbol
Parameter
Min
Typ
Max
Unit
Note
CEXT
External filter capacitor
-10%
100
+10%
nF
Ceramic low-ESR capacitor between
CREF and VSS
Min
Typ
Max
Unit
Note
+1%
V
Low noise trimmed voltage
reference – connected to Pad
CREF; do not load
+10
%
Trimable by serial interface
Parameter
Reference Voltage
-1%
ΔfCLK
Accuracy of Internal
reference clock
-10
1.8
am
lc s
on A
te G
nt
st
il
VCEXT
lv
Symbol
al
id
Table 98 – Refererences
To reduce the current consumption of the chip, the circuit can be set into a special low power mode with the serial interface bit
‘low_power_on’. All specification parameters except the noise parameters are still valid for this mode.
Table 99 – Internal References Regsiter definitions
Register Definition
Name
References Control
Add
r. 25
52
Content
Default
b7
b6
b5
b4
b3
0ch
b2
b1
b0
low_pow
er_on
clk_int
Table 100 – Internal references Bit definitions
Name
Default
Access
Description
Sets the internal CLK frequency used for fuel gauge, DCDCs, PWM, charge
pump
ca
(000b) – 1.6 MHz
(001b) – 1.7 MHz
(010b) – 1.8 MHz
(011b) – 1.9 MHz
(100b) – 2.0 MHz
(101b) – 2.1 MHz
(110b) – 2.2 MHz (default)
(111b) – 2.3 MHz
0b
R/W
ch
ni
clk_int
Te
low_power_on
0b
All timings and delays are based on 2.2MHz clk_int
R/W
0 Standard mode
1 Low power mode – all specification except noise parameters are still valid
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
25
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Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Additional Voltage ref (unfiltered, high impedance, not low noise): 10mV resolution from 0 – 1.8V with an accuracy of +/-1%
( invalid if prechage_n = 0),
Current references: 1uA +/- 3% generated by a pmos from V2_5 (one for each analog block)
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Low Power Mode
al
id
Use bit low_power_on (reg. References Control) to activate the Low Power Mode. In this mode the on-chip voltage reference
and the temperature supervision comparators are operating in pulsed mode. This reduces the quiescent current of the AS3654
by 45μA (typ.). Because of the pulsed function some specifications are not fulfilled in this mode (e.g. increased noise), but still
the full functionality is available.
Note: Low power mode can be controlled by the serial interface.
7.24 ON-Detect
000
001
010
011
100
101
110
111
open
320kΩ
160kΩ
80kΩ
40kΩ
20kΩ
10kΩ
0Ω
am
lc s
on A
te G
nt
st
il
lv
The startup- and reset sequences of the device are highly configurable. The configuration of these sequences is defined by
the ratio of the internal trimmed bias resistors and RPROGRAM. At the beginning of each reset cycle a 3 bit AD-conversion is
performed. The result of this conversion is used to select 1 of 8 possible address-ranges of an internal mask-programmable
ROM. The information that is stored in this ROM defines the following parameters:
• power-on sequence and voltage levels of 8 voltage regulators
• duration of the reset cycle (8 possible timer values)
The following values of RPROGRAM are required to select the 8 possible address ranges:
Table 101 – ON-Detect Register definitions
Register Definition
Name
Boot_status
Add
r. 26
74
Content
Default
b7
b6
b5
b4
b3
rom_
valid
NA
b2
b1
b0
rom_adr
ca
Table 102 – ON-Detect Bits definitions
Default
Access
rom_adr
(000)b
R
Boot-ROM address
0
R
If ‘1’ Boot-ROM address is valid
Description
Te
ch
rom_valid
ni
Name
Register address codes
ROM-adr. 25-30…Power1
27 Register address codes
ROM-adr. 25-30…Power1
26
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
00 – 31 are identical to Boot-ROM address codes
Control states at startup sequence
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8.2 Packaging and Pinout
8.2.1
Pin Description
Table 113 – Pinlist CTBGA100,9x9mm (AS3654)
Typ
e
Name
Supply
K9
K8
Charger
V_USB
VSUP_USB
P
P
H9
VCHARGER
P
K10
VGATE
A
J10
VOFF_B
A
H10
E9
E10
F10
D10
E6
J8
J9
G8
G7
C2
C3
VSS_CH
P
VBAT_SW1
P
VBAT_SW2
P
VSUP_SW1
P
VSUP_SW2
P
BAT_SW
A
CH_SENSE_N
A
CH_SENSE_P
A
ISENSP
A
ISENSN
A
Serial interface
SCL
DI
SDA
DIO
Control interfaces
XRESET
OD
XINT
OD
J2
XON
V2_5
SCL input in I2C mode
SDA input / output in I2C mode
Vsupply
Vsupply
Bidirectional Reset Pin – add an external pullup resistor to the digital supply
Interrupt Pin - add an external pullup resistor to the digital supply
Input pin to startup the system (power on), internal pullup, apply zenerzapprogramming voltage here
am
lc s
on A
te G
nt
st
il
lv
(Vsupply)
(Vsupply)
IPU
VBAT
VBAT
Vsupply
Vsupply
ca
Internal Refs
VSUPPLY_5
P
Supply for voltage Measurement, always connect to VSUPPLY
V_BAT
P
VBAT
Battery supply for Reference blocks.
RPROGRAM
A
V2_5
Select register setup at startup.
V2_5
P
Internal regulator analogue output
CREF
A
V2_5
Reference voltage bypass capacitor connection
V2_5
RBIAS
A
Internal Bias Reference Resistor (connect 220kΩ resistor)
GND_SENSE
P
VSSA
GND reference for analog blocks (connect to GND plane separate)
ADC_IN
A
V2_5
Analog input for ADC10
Current Sinks
CURR1
A
VCURR
Current sink 1, or GPIO1
CURR2
A
VCURR
Current sink 2, or GPIO2
CURR3
A
VCURR
Current sink 3, or GPIO3
CURR4
A
VCURR
Current sink 4, or GPIO4
CURR5
A
VCURR
Current sink 5
VCURR
A
Supply voltage of GPIOs and current sinks
VSS_CURR
A
VCURR
Ground pad of Current sink
General Purpose DC/DC Converter1 and 2
ch
J7
H8
H6
G10
F9
F8
G9
H7
Vsupply
Vsupply
V2_5
V2_5
USB voltage supply input
Supply output of USB charger (connect to Vsupply)
High voltage input coming from the charger; if the charger is used connect a
ceramic capacitor of 1μF
Switch ON control pin for the external PMOS Fet transistor of the charger step
down converter
Switch OFF control pin for the external PMOS Fet transistor of the charger
step down Buck converter
Ground pad of Step down Charger
Battery switch input1 (battery side)
Battery switch input2 (battery side)
Battery switch input1 (supply side)
Battery switch input2 (supply side)
Battery switch output for external PMOS
Charger step down converter, external shunt resistor negative connection
Charger step down converter, external shunt resistor positive connection
Positive sensing input voltage for the external charging current shunt resistor
Negative sensing input voltage for the external charging current shunt resistor
ni
A2
A1
Description
al
id
Pin
Te
J4
H4
K3
J3
K2
K1
H5
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VRF_1
J6
VRF2_IN
K7
VRF_2
B7
VDIG1_IN
A7
VDIG_1
B6
VDIG2_IN
A6
VDIG_2
D4
E3
E2
F4
K4
J5
B2
B4
B3
A4
A3
Step up DC/DC converter1 external shunt resistor positive connection
Vsupply
Step up DC/DC converter2 external shunt resistor positive connection
Vsupply
Step up DC/DC converter1 external shunt resistor negative connection
Vsupply
Step up DC/DC converter2 external shunt resistor negative connection
Vsupply
Vsupply
Vsupply
Vsupply
Step up DC/DC converter2 control for external mosfet
Step up DC/DC converter2 feedback input
Step up DC/DC converter2 current source 1
Step up DC/DC converter2 current source 2
Vsupply
Supply Pad for RF1 LDO (RF_1), always connect to Supply>3.0V
Output voltage of one of the RF LDO’s; can be used as High-Side Switch, if
used as LDO connect a ceramic capacitor of 1μF (+/-20%) or 2.2μF (+100%/50%)
Supply Pad for RF2 LDO (RF_1), always connect to Supply>3.0V
Output voltage of one of the RF LDO’s; can be used as High-Side Switch, if
used as LDO connect a ceramic capacitor of 1μF (+/-20%) or 2.2μF (+100%/50%)
Supply Pad for DIG1 LDO (VDIG_1)
Output voltage of one of the DIG LDO’s. Connect a ceramic capacitor of 1μF
(+/-20%) or 2.2μF (+100%/-50%)
Supply Pad for DIG2 LDO (VDIG_2)
Output voltage of one of the DIG LDO’s. Connect a ceramic capacitor of 1μF
(+/-20%) or 2.2μF (+100%/-50%)
VRF_IN
P
Vsupply
A
VRF_IN
P
Vsupply
A
VDIG_IN
P
Vsupply
A
VDIG_IN
Charge Pump
VCP_IN
P
VCP_N
A
VCP_P
A
VCP_OUT
A
VSS_CP
A
DCDC Step Down
VSUPPLY_1
P
LX1
A
FB1
A
PGND1
A
VSUPPLY_2
P
LX2
A
FB2
A
PGND2
A
VSUPPLY_3
P
LX3
A
FB3
A
PGND3
A
Audio
VSUPPLY_6
P
VI2S
P
SDI1
IPD
Te
C10
D5
C6
Vsupply
A
ch
D1
F2
G4
E1
G1
G2
G3
F1
H1
H2
H3
J1
Supply for DCDC step up and control interface, always connect to VSUPPLY
Step up DC/DC converter1 feedback input
Step up DC/DC converter1 control for external mosfet
Vsupply
Vsupply
Vsupply
ca
F3
Vsupply
Vsupply
al
id
K5
D3
Description
am
lc s
on A
te G
nt
st
il
K6
VSUPPLY_4
DCDC_FB1
DCDC_GATE1
DCDC_SENSE
A
_P1
DCDC_SENSE
A
_P2
DCDC_SENSE
A
_N1
DCDC_SENSE
A
_N2
DCDC_GATE2
A
DCDC_FB2
A
DCDC_CURR1 A
DCDC_CURR2 A
Linear Regulators
VRF1_IN
P
Supply
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Supply Pad for Charge Pump, always connect to Supply>3.0V
HVS charge pump flying capacitor positive side
HVS charge pump flying capacitor negative side
Charge pump output, connect a ceramic capacitor of 2.2μF (+100%/-50%)
Ground pad of charge pump
Vsupply
Vsupply
Vsupply
Supply Pad for DCDC_Step down converter1, always connect to VSUPPLY
DC/DC step down converter1 output
DC/DC step down converter1 feedback
Power Ground of DCDC step down converter1
Supply Pad for DCDC_Step down converter2, always connect to VSUPPLY
DC/DC step down converter2 output
DC/DC step down converter2 feedback
Power Ground of DCDC step down converter2
Supply Pad for DCDC_Step down converter3, always connect to VSUPPLY
DC/DC step down converter3 output
DC/DC step down converter3 feedback
Power Ground of DCDC step down converter3
VI2S
Supply for VI2S Regulator
Supply Pad for I2S Interface, Connect to VDAC Supply
I2S_1 Data input to DAC
Vsupply
Vsupply
Vsupply
ni
C1
E4
D2
Typ
e
P
A
A
Name
lv
Pin
Vsupply
Vsupply
Vsupply
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A10
VDAC
A
VDAC
B9
HP_CM
A
AVDD
A9
HP_CM_PWR
A
AVDD
C9
LINE_CM
A
ALVDD
D8
C8
C7
A8
B8
B10
D7
E5,F5,
F6,G5
,G6
LOUT_L
LOUT_R
ALVDD
AVDD
HPL
HPR
BVSS
Pin Types:
-
A
A
P
P
A
A
P
ALVDD
ALVDD
AVDD
AVDD
AVDD
VSS
Analog Ground Pads
Digital Input Pin
Digital Input Pin with internal pull-down resistor
Digital Input Pin with internal pull-up resistor
Digital Input / Open Drain Output Pin with internal pull-up resistor
Digital Output Pin
Digital Open Drain Output Pin; requires external pull-up resistor
Digital Input / Output Pin
Analogue Pin
Power Pin
Te
ch
ni
-
I
IPD
IPU
IODPU
O
OD
IO
A
P
I2S_1 Shift clock
I2S_1 Left/Right clock
I2S_2 Data input to DAC
I2S_2 Shift clock
I2S_2 Left/Right clock (or Master clock input for I2S1: DAC (128*Fsdac))
CM voltage bypass capacitor connection (1.45V)
VDAC voltage bypass capacitor connection (2.9V)
Line input left channel.
Line input right channel
Digital output for controlling the external NMOS
2.9V Output voltage of one of DAC LDO; Connect a ceramic capacitor of 1μF
(+/-20%) or 2.2μF (+100%/-50%)
Bypass capacitor connection of common mode voltage of Audio headphone
amplifier (AVDD/2)
Buffered voltage of HP_CM
Bypass capacitor connection of common mode voltage of Audio line out
amplifier (ALVDD/2)
Line out output Left channel
Line out output Right channel
Supply pad of Line out amplifier
Supply pad of headphone amplifier
Headphone output left channel
Headphone output right channel
Power ground of headphone amplifier
ca
-
VI2S
VI2S
VI2S
VI2S
VI2S
VDAC
VDAC
VDAC
VDAC
Vsupply
Description
am
lc s
on A
te G
nt
st
il
VSSA
Supply
al
id
SCLK1
LRCLK1
SDI2
SCLK2
LRCLK2
AGND
VREF
LINL
LINR
GND_SW
Name
lv
C5
D6
C4
A5
B5
F7
E7
E8
D9
B1
Typ
e
IPD
IPD
IPD
IPD
IPD
A
A
A
A
O
Pin
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8.3 Registermap
Table 114 – Registermap
Default
00
ROM
Step Down Voltage2
01
ROM
Step Down Voltage3
02
ROM
LDO_RF1 Voltage
03
ROM
LDO_RF2 Voltage
LDO_DIG1 Voltage
LDO_DIG2 Voltage
04
05
06
ROM
ROM
ROM
USB ChargerControl
07
ChargerControl1
08
09
10
11
12
13
14
15
16
Step Up2 DC/DC
Control
17
GPIO 1
18
GPIO 2
sd1_clki
nv
sd2_clki
nv
sd3_clki
nv
sd1_fre
qu
sd2_fre
qu
sd3_fre
qu
rf1_swpr
ot_en
ROM (52h)
ROM (41h)
ext_bats
w_en
Isolate_b
at
b3
b2
b1
step_down1_v
step_down2_v
step_down3_v
rf1_lcurr
_en
b0
ldo_rf1_v
usb_prio
usb_chg
En
Boost
trickle_t
max
Pulse
SupRes
En
ChVoltResume
TPOFFMAX
ROM (1dh)
ROM (26h)
ROM (4bh)
ROM (01h)
ROM (2Eh)
stpup2_r
es
ROM (00h)
ROM (00h)
stpup2_
prot
ROM (07h)
stpup2_f
astskip
stpup1_
oc_time
out
stpup2_
clkinv
gpio1_pulls
gpio2_pulls
20
ROM (07h)
gpio3_pulls
GPIO 4
21
ROM (07h)
gpio4_pulls
Reset Timer
22
ROM (0Fh)
Reg Power1 Ctrl
23
ROM
cp_on
sd3_on
ch
Auto
Resume
DisOWB
TPOFF
Fast
stpup2_f
req
stpup1_
shortpro
t
DisBDet
stpup1_
clkinv
sd2_on
ChEn
ChVoltEOC
TPON
UpdReq
FGEn
TrickleCurrent
cp_puls
cp_freq
eskip
stpup1_f
req
stpup1_v
stpup2_fb
gpio1_in
vert
gpio2_in
vert
gpio3_in
vert
gpio4_in
vert
BatType
ResVoltRise
CalMod CalReq
ConstantCurrent
cp_clkin
v
stpup1_r stpup1_f
es
astskip
ROM (00h)
ROM (00h)
usb_Current
ResVoltFall
ch_voltage
ROM (07h)
Te
b4
No_char
ging
19
GPIO 3
b5
ldo_rf2_v
ldo_dig1_v
ldo_dig2_v
ni
Step Up1 DC/DC
Control
b6
ca
Battery voltage
monitor
Charger Config
ChargerTiming
FuelGauge
ChargerCurrent
Charge Pump
Control
Step Up DC/DC
Control
b7
am
lc s
on A
te G
nt
st
il
Step Down Voltage1
Content
al
id
Name
Add
r. 28
lv
Register Definition
stpup2_v
gpio1_iosf
gpio1_mode
gpio2_iosf
gpio2_mode
gpio3_iosf
gpio3_mode
gpio4_iosf
gpio4_mode
sd1_on
xon_ena
ble
ldo_dig2
_on
res_timer
ldo_dig1
_on
ldo_rf2_
on
ldo_rf1_
on
Register address codes 00 – 31 are identical to Boot-ROM address codes
ROM-adr. 25-30…Power1 Control states at startup sequence
28
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Reg Power1 Ctrl
Startup 1..6msec
2430
ROM
Reg Power2 Ctrl
31
ROM
Step Down Control1
32
00h
Step Down Control2
33
00h
Step down charger
control
34
00h
DCDC_CURR1 value
35
00h
DCDC_CURR2 value
36
00h
CURR1 value
37
CURR2 value
38
CURR3 value
39
CURR4 value
40
CURR5 value
41
ADC idac
42
43
Interrupt Mask2
44
Interrupt Status1
45
Interrupt Status2
46
Low voltage Status
47
GPIO Signal
PWM Frequency
Control High Time
PWM Frequency
Control Low Time
CURR control
48
b6
sd2_nsw
_on
sd3_dis_
pon
sd2_4u7
sd2_dis
_pon
sd3_dis
_curmin
dcdc_cu
rr1_low_
bias
dcdc_cu
rr2_low_
bias
curr1_lo
w_bias
curr2_lo
w_bias
curr3_lo
w_bias
curr4_lo
w_bias
curr5_lo
w_bias
b5
sd2_dis
_n
sd1_dis
_pon
sd2_dis
_curmin
b4
b3
b2
stpup1_
on
sd2_ps
w_on
stpup2_
on
sd1_ns
w_on
sd3_ns
w_on
sdX_lpo
sd1_4u7
sd3_4u7
sd1_dis
_curmin
dcdc_curr1_current
00h
00h
rf2_sw
rf1_sw
sd1_dis
_n
sd3_dis
_n
sd1_psw
_on
sd3_psw
_on
sdc_freq
u
00h
00h
00h
curr2_current
curr3_current
curr4_current
curr5_current
00h
FFh
FFh
NA
NA
40h
NA
adc_idac
trickle_t
cheoc_i
max_int
nt_m
_m
sd3_lv_i sd2_lv_i
nt_m
nt_m
trickle_t
cheoc_i
max_i
sd1_lv_i
nt_m
chstate_
i
sd3_lv_i
sd2_lv_i
sd1_lv_i
LowBat_
int_m
ovtmp_
int_m
onkey_
int_m
chdet_
int_m
stpup1_i
nt_m
LowBat_
i
hpdet_in
t_m
hphcurr
_int_m
dig2_lv_
int_m
ovtmp_i
onkey_i
chdet_i
stpup1_i
hpdet_i
hphcurr
_i
dig2_lv_
i
usb_chd
et_
int_m
dig1_lv_
int_m
usb_chd
et_i
dig1_lv_
i
hpdet
dig2_lv
dig1_lv
sd3_lv
sd2_lv
sd1_lv
gpio2_in
gpio1_in
gpio4
gpio3
gpio2
gpio1
stpup1_
det
gpio4_in
stpup1_
oc
gpio3_in
pwm_h_time
50
00h
pwm_l_time
51
00h
References Control
52
0ch
clk_int
Watchdog Control
53
02h
wtdg_tri
gger
54
00h
wtdg_min_timer
55
FFh
wtdg_max_timer
ch
00h
Te
b0
curr1_current
49
Watchdog_min
Timer
Watchdog_max
Timer
b1
dcdc_curr2_current
ni
Interrupt Mask1
b7
ca
Name
Content
al
id
Default
am
lc s
on A
te G
nt
st
il
Add
r. 28
lv
Register Definition
www.austriamicrosystems.com (tje/ptr)
curr5_ctrl
Revision 0.22 / 17.12.2007
dcdc_curr2_ctrl
chstate_
int_m
dcdc_curr1_ctrl
low_pow
er_on
wtdg_re
s_on
wtdg_on
82 - 87
AS3654
austriamicrosystems
Specification, Confidential
Default
Content
b7
b6
b5
Watchdog Software
Signal
56
00h
Audio Set1
57
00h
Audio Set2
58
00h
HPH out R
59
00h
hp_ovc_to
HPH out L
Line out R
60
61
00h
00h
Line out L
62
00h
ADC_control
63
00h
hp_mute
hp_on
ibr_line
line_mut
line_on
e
start_co
adc_on
nversion
ADC_MSB result
64
NA
ADC_LSB result
ChargerStatus
65
66
NA
NA
ChargerStatus_usb
67
DeltaChargeMSB
DeltaChargeLSB
ElapsedTimeMSB
ElapsedTimeLSB
68
69
70
71
Reset Control
72
Overtemperature
Control
73
Boot_status
74
Test_enable
Testmux Control N
Testmux Control P
Digital Testmux
75
76
77
78
Testmode control1
79
Testmode control2
80
Testmode control3
81
b4
b3
b2
b1
b0
wtdg_
sw_sig
mclk_in
vert
I2S_mcl
k_en
I2S_sel
ect
result_not
_ready
gnd_sw
_on
ibr_hph
mux_sel
dith_on
hpcm_of
f
hpdeton
hpr_vol
hpl_vol
liner_vol
linel_vol
D8
dac_on
adc_slo
w
adc_test
D7
D6
NoBat
EOC
CVM
214
26
214
26
213
25
213
25
212
24
212
24
NA
NA
NA
NA
NA
sign
27
215
27
00h
00h
reset_reason
tco_140
_a
tco_110
_a
temp_te
st1
NA
00h
00h
00h
00h
adc_select
D5
D4
D3
D2
Resume
batsw_
mode
210
22
210
22
xon_inp
ut
D1
ChAct
USB_C
hAct
29
21
29
21
power_o
ff
D0
ChDet
USB_Ch
Det
28
20
28
20
force_re
set
ca
NoRese
t
00h
rom_test
cp_tm
00h
aud_rtm
adc3_tm
00h
00h
Testmode vsupply_h
84
00h
Te
ch
ni
serial_tm
82
83
ASIC ID 1
ASIC ID 2
Zener Zap lsb
85
86
87
NA
NA
NA
Zener Zap msb
88
NA
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rst_ov_t
emp_14
0
rom_
valid
test_en_code
temp_te
st0
ov_temp
_140
ov_temp
_110
temp_p
mc_on
rom_adr
mux_ ctrl_n
mux_ctrl_p
DigTestMux
00h
Testmode idac
Testmode vsupply_l
Trickle
batsw_o
n
211
23
211
23
lin_on
ibr_dac
am
lc s
on A
te G
nt
st
il
D9
aud_ldo
_on
al
id
Name
Add
r. 28
lv
Register Definition
zzap_for
ce_read
out
sdX_tm
2
batsw_t
m
1
1
0
0
1
0
RefOsc1Mhz1
smc_ihol
smc_ioff
d
Revision 0.22 / 17.12.2007
zzap_te
stmode
quasitri
men
digmux
En
anamux
En
sdX_del
50
aud_17d
ch_sdtm
b_test
idac<7:0>
vsupply<7:0>
stpup_t
m2
charger
_dishyst
stpup_t
m1
charger
_tm
sdX_tm
1
0
1
1
preset_
en
1
atpg_
mode
ext_clk
aud_ltm
vsupply<9:8>
0
1
rev
Vref_Trim
smc_ion
VrefLpTrim
83 - 87
AS3654
austriamicrosystems
Specification, Confidential
Register Definition
Name
Add
r. 28
Default
Content
b7
b6
b5
b4
b3
b2
b1
b0
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Read Only
www.austriamicrosystems.com (tje/ptr)
Revision 0.22 / 17.12.2007
84 - 87
AS3654
austriamicrosystems
Specification, Confidential
8.4 Pinout Drawing (Top view) CTBGA100 9x9mm:
2
3
4
5
6
7
8
9
10
A
SDA
SCL
VSS_CP
VCP_OUT
SCLK2
VDIG2
VDIG1
AVDD
HP_CM_P
WR
VDAC
B
GND_SW
VCP_IN
VCP_P
VCP_N
LRCLK2
VDIG2_IN
VDIG1_IN
HPL
HP_CM
HPR
C
VSUPPLY_
4
XRESET
XINT
SDI2
SCLK1
SDI1
ALVDD
LOUT_R
LINE_CM
VSUPPLY_
6
D
VSUPPLY_
1
DCDC_GA
TE1
DCDC_SE
NSE_P1
DCDC_SE
NSE_N1
VI2S
LRCLK1
BVSS
LOUT_L
E
PGND1
DCDC_GA
TE2
DCDC_SE
NSE_N2
DCDC_FB
1
VSSA
BAT_SW
VREF
F
PGND2
LX1
DCDC_SE
NSE_P2
DCDC_FB
2
VSSA
VSSA
G
VSUPPLY_
2
LX2
FB2
FB1
VSSA
H
VSUPPLY_
3
LX3
FB3
CURR2
J
PGND3
XON
CURR4
K
VCURR
CURR5
CURR3
lv
al
id
1
VSUP_SW
2
LINL
VBAT_SW
1
VBAT_SW
2
AGND
RBIAS
CREF
VSUP_SW
1
VSSA
ISENSEN
SENSEP
GND_SEN
SE
V2_5
VSS_CUR
R
RPROGRA
M
ADC_IN
V_BAT
VCHARGE
R
VSS_CH
CURR1
DCDC_CU
RR2
VRF2_IN
VSUPPLY_
5
CH_SENS
E_N
CH_SENS
E_P
VOFF_B
DCDC_CU
RR1
VRF1
VRF1_IN
VRF2
VSUP_US
B
V_USB
VGATE
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
LINR
www.austriamicrosystems.com (tje/ptr)
Revision 0.22 / 17.12.2007
85 - 87
AS3654
austriamicrosystems
Specification, Confidential
8.6 Package and Marking
ch
ni
ca
am
lc s
on A
te G
nt
st
il
AYWWIZZ
AS3654
al
id
CABGA100_9x9mm 0.8mm pitch(AS 3654)
lv
8.6.1
Te
Marking:
AYWWIZZ
www.austriamicrosystems.com (tje/ptr)
A
Y
WW
I
ZZ
.......
.......
.......
.......
.......
Pb free
year
week
plant identifier
letters of free choice
Revision 0.22 / 17.12.2007
86 - 87
AS3654
austriamicrosystems
Te
ch
ni
ca
am
lc s
on A
te G
nt
st
il
lv
al
id
Specification, Confidential
www.austriamicrosystems.com (tje/ptr)
Revision 0.22 / 17.12.2007
87 - 87
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