AMS AS5030 Position Sensor Datasheet
Below you will find brief product information for AMS AS5030. The product is 8-bit programmable high-speed magnetic rotary encoder that measures the angle of a magnet rotating over the center of the chip. It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single 360º contactless device. The digital angle data is available as a serial bit stream and as a PWM signal. It also provides the strength of the magnetic field as a 6-bit code. The AS5030 is suitable for contactless rotary position sensing, rotary switches (human machine interface), AC/DC motor position control, robotics and encoder for battery operated equipment.
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AS5030
8-Bit Programmable High Speed
Magnetic Rotary Encoder
General Description
The AS5030 is a contactless magnetic rotary encoder for accurate angular measurement over a full turn of 360°.
It is a system-on-chip, combining integrated Hall elements, analog front end and digital signal processing in a single device.
To measure the angle, only a simple two-pole magnet, rotating over the center of the chip is required.
The absolute angle measurement provides instant indication of the magnet’s angular position with a resolution of 8 bit = 256 positions per revolution. This digital data is available as a serial bit stream and as a PWM signal.
In addition to the angle information, the strength of the magnetic field is also available as a 6-bit code.
Data transmission can be configured for 1-wire (PWM), 2-wires
(CLK, DIO) or 3-wires (CLK, DIO, CS).
A software programmable (OTP) zero position simplifies assembly as the zero position of the magnet does not need to be mechanically aligned.
A Power Down Mode together with fast startup- and measurement cycles allows for very low average power consumption and makes the AS5030 also suitable for battery operated equipment.
and
Content Guide appear at end of
datasheet.
Figure 1:
Added Value of Using AS5030
Benefits
•
Complete system-on-chip, no calibration required
•
Multiple data output formats
•
Flexible setup for fitting in almost any application
Key Benefits & Features
The benefits and features of AS5030, 8-Bit Programmable High
Speed Magnetic Rotary Encoder are listed below:
Features
•
360° contactless angular position encoding
•
Two digital 8-bit absolute outputs:
• Serial interface
• Pulse width modulated (PWM) output
•
User programmable zero position
•
Serial read-out of multiple interconnected AS5030 devices using daisy chain mode
ams Datasheet
[v3-00] 2018-Mar-08
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AS5030 −
General Description
Benefits
•
Robust system, tolerant to horizontal misalignment, airgap variations, temperature variations and external magnetic stray fields
Features
•
Wide magnetic field input range: 20mT ~ 80mT
•
Wide temperature range: -40°C to 125°C
•
Small Pb-free package: TSSOP 16
Applications
The AS5030 is suitable for Contactless rotary position sensing,
Rotary switches (human machine interface), AC/DC motor position control, Robotics and Encoder for battery operated equipment.
Figure 2:
Typical Arrangement of AS5030 and Magnet
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AS5030 −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 3:
AS5030 Block Diagram
Sin / Sinn / Cos / Cosn
Hall Array
&
Front-end
Amplifier
Sin
Cos
Power Management
AS5030
Angle
Tracking
ADC &
Angle
Decoder
Zero
Position
Mag
A G C
AGC
OTP
PWM
Decoder
Absolute
Serial
Interface
(SSI )
PWM
DX
DIO
CS
CLK
C2
MagRngn
PROG
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Pin Assignments
AS5030 −
Pin Assignments
Figure 4:
Pin Diagram (Top View)
MagRngn
PROG
VSS test3 test2 test1 test0
TC
1
2
3
4
7
8
5
6
16
15
14
13
12
11
10
9
PWM
C2
C1
VDD
DIO
CS
CLK
DX
Figure 5:
Pin Descriptions
Pin
Number
1
Pin Name
MagRngn
2
3
4
5
6
7
8
PROG
VSS
T3_SINn
T2_SIN
T1_COSn
T0_COS
TC
Pin Type Description
Digital output / tri-state
Supply pin
-
-
-
-
-
Push-Pull output. Is ‘HIGH’ when the magnetic field strength is too weak, e.g. due to missing magnet
Programming voltage input. Must be left open in normal operation.
Maximum load = 20pF (except during programming)
Supply ground
This pin is used for factory testing. For normal operation it must be left unconnected. Inverse SIN
(Sinn) output in SIN/COS output mode
This pin is used for factory testing. For normal operation it must be left unconnected. SIN output in
SIN/COS mode
This pin is used for factory testing. For normal operation it must be left unconnected. Inverse COS
(Cosn) output in SIN/COS mode
This pin is used for factory testing. For normal operation it must be left unconnected. COS output in
SIN/COS mode
Test pin. Connect to VSS or leave unconnected
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AS5030 −
Pin Assignments
Pin
Number
9
10
11
12
13
14
15
16
Pin Name
DX
CLK
CS
DIO
VDD
C1
C2
PWM
Pin Type Description
Digital output
Digital output for 2-wire operation and Daisy Chain mode
Clock input of synchronous serial interface;
Schmitt-Trigger input
Digital input /
Schmitt-Trigger
Bi-directional digital pin
Supply pin
Chip Select for serial data transmission, active high;
Schmitt-Trigger input, external pull-down resistor
(~50k
Ω
) required in read-only mode
Data output / command input for digital serial interface
Digital input
(standard CMOS; no pull-up or pull-down)
Positive supply voltage, 4.5V to 5.5V
Configuration input: Connect to VSS for normal operation, connect to VDD to enable SIN-COS outputs. This pin is scanned at power-on-reset and at wake-up from one of the Ultra-Low Power Modes
Configuration input: Connect to VSS for 3-wire operation, connect to VDD for 2-wire operation. This pin is scanned at power-on-reset and at wake-up from one of the Ultra-Low Power Modes
Digital output
Pulse Width Modulation output, 2μs pulse width per step (2μs ~ 512μs)
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AS5030 −
Absolute Maximum R atings
Absolute Maximum Ratings
Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in Electrical
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 6:
Absolute Maximum Ratings
Symbol
V
DD
V
IN
I scr
ESD
Θ
JA
T strg
T
BODY
RH
NC
MSL
Parameter Min Max Units Comments
Electrical Parameters
Supply voltage -0.3
7 V
Except during OTP programming
Input pin voltage
VSS -
0.5
VDD +
0.5
V
Input current (latch-up immunity)
-100 100 mA JEDEC 78
Electrostatic Discharge
±2 kV Electrostatic discharge MIL 883 E method 3015
Still Air / Single Layer PCB
Package thermal resistance
137
89
°C/W
°C/W Still Air / Multilayer PCB
Temperature Ranges and Storage Conditions
Storage temperature -55 150 °C Min: -67ºF; Max: 302ºF
Body temperature 260 °C
The reflow peak soldering temperature (body temperature) specified is in accordance with
IPC/JEDEC
J-STD-020 “Moisture/Reflow
Sensitivity Classification for
Non-Hermetic Solid State Surface
Mount Devices”.
The lead finish for Pb-free leaded packages is matte tin
(100% Sn).
Relative humidity non-condensing
5 85 %
Moisture sensitivity level 3
Represents a maximum floor time of 168h
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AS5030 −
Electrical Characteristics
Electrical Characteristics
T
AMB
= -40°C to 125°C, VDD5V = 4.5V ~ 5.5V, all voltages referenced to VSS, unless otherwise noted.
Figure 7:
Operating Conditions
Symbol
VDD
Parameter
Positive supply voltage
IDD Operating current
I off
T
AMB
Power-down current
Ambient temperature
Conditions
No load on outputs.
Minimum AGC (strong magnetic field)
No load on outputs.
Maximum AGC (weak or no magnetic field)
Low Power Mode
Ultra-Low Power Mode
-40°F ~ 257°F
Min Typ Max Units
4.5
5.5
V
14 18 mA
18 22
-40
1400 2000
30 120
125
μA
°C
Figure 8:
System Parameters
Symbol
N
T
PwrUp t da t dd t delay
Parameter
Resolution
Conditions Min Typ Max Units
8
1.406
bit
°
Power up time
Propagation delay
Startup from zero; AGC not regulated
Startup from zero until regulated AGC
Startup from Power Down
Mode
Startup from Low Power Mode
Setting 1: No hysteresis, no reset
Setting 2: Hysteresis and reset
Analog signal path; over full temperature range
Tracking rate
Step rate of tracking ADC;
1 step = 1.406°
Signal processing delay
Total signal processing delay, analog + digital (t da
+ t dd
)
0.85
15
1.15
1000
3300
500
46
1500
17
1.45
16.15
18.45
μ s
μs
μs
μs
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Symbol
T
INL cm
TN
POR r
POR f
Hyst
Parameter
Analog filter time constant
Accuracy
Transition noise
Power-on-reset levels
Conditions
Internal low-pass filter
Centered magnet
Within horizontal displacement radius. See
rms (1 sigma)
VDD rising
VDD falling
Hysteresis
|
POR r
- POR f
|
AS5030 −
Electrical Characteristics
Min Typ Max Units
6.6
μs 4.1
-2
12.5
2
°
-3 3
3.5
3.0
500
0.235
4.5
4.5
°
V
V mV
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AS5030 −
Electrical Characteristics
Figure 9:
Magnet Specifications
Symbol
MD
MT
B i v i
B max
B min tk
M
Parameter Conditions
Magnet diameter
Magnet thickness
Diametrically magnetized
Magnetic input range
At chip surface, on a radius of
1mm
Magnet rotation speed To maintain locked state
Magnetic field high detection
Magnetic field low detection
Hall array radius
Vertical distance of magnet
Horizontal magnet displacement radius
T
AMB
=25°C, AGC @ lower limit, 1 sigma = 2.5mT
T
AMB
=25°C, AGC @ upper limit, 1 sigma = 1.5mT
Over x/y chip center
Recommended distance; operation outside this range is possible, accuracy may be reduced
From diagonal package center
From diagonal IC center
NdFeB Material Recommended magnet material and temperature drift
SmCo Material
Min Typ Max Units
6
2.5
mm mm
20
0.5
52
23
1
1
-0.12
-0.035
80
30000
1.8
0.25
0.5
mT rpm mT mm mm mm
%/K
Note(s):
1. Recommended magnet: NdFeB 35H BR = 12000 Gauss, Ø6mm x 2.5mm.
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AS5030 −
Electrical Characteristics
Figure 10:
Magnetic Field Alarm Limits
Symbol
AGC
FF
AGC
0
Parameter
Magnetic field too low alarm limit
Magnetic field too high alarm limit
Magnetic field alarm limit trim range
Temperature coefficient of alarm ranges
Conditions
AGC = FF
H untrimmed, 25°C, 1sigma
AGC = 0
H untrimmed, 25°C, 1sigma
Sensitivity increases with temperature which partly compensates the temperature coefficient of the magnet
Min Typ Max Units
20.3
44.5
100
0.052
23.6
52.2
121 mT mT
%
%/K
Figure 11:
Hall Element Sensitivity Options
Symbol Parameter
sens
Hall element sensitivity setting
Conditions
sens = 00 (default); low sensitivity. See
sens = 01 sens = 10 sens = 11 (high sensitivity)
Min Typ Max Units
100
106
113
121
%
Figure 12:
Programming Parameters
Symbol Parameter
V
PROG
I
PROG
Programming voltage
Tamb
PROG
Programming current
Programming ambient temperature t
PROG
V
R,prog
V
R,unprog
Programming time
Analog readback voltage
Conditions
Static voltage at pin PROG
During programming
Timing is internally generated 2
During analog readback mode at pin PROG
2.2
Min Typ Max Units
8.0
8.5
100
V mA
0 85 °C
4
0.5
3.5
μs
V
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AS5030 −
Electrical Characteristics
DC Characteristics of Digital Inputs and
Outputs
Figure 13:
CMOS Inputs: CLK, CS, DIO, C1, C2
Symbol
VIH
VIL
I
LEAK
Parameter
High level input voltage
Low level input voltage
Input leakage current
Conditions Min
0.7*VDD
Typ Max
0.3*VDD
1
Units
V
V
μA
Figure 14:
CMOS Outputs: DIO, MagRngn, PWM, DX
Symbol
VOH
VOH
CL
Parameter
High level output voltage
Low level output voltage
Capacitive load
Conditions
Source current <4mA
Sink current <4mA
Min
VDD-0.5
Typ Max
0.4
35
Units
V
V pF
Figure 15:
CMOS Tristate Output: DIO
Symbol
IO
Z
Parameter
Tristate leakage current
Conditions
CS = low
Min Typ Max Units
1 μA
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AS5030 −
Electrical Characteristics
Figure 16:
8-Bit PWM Output
Symbol Parameter
N
PWM
PWM resolution
PW
MIN
PW
MAX
PW
P f
PWM
Hyst
PWM pulse width
PWM pulse width
PWM period
PWM frequency
Digital hysteresis
Conditions
Angle = 0° (00
H
)
Angle = 358.6° (FF
H
)
1 / PWM period
At change of rotation direction
Min Typ Max Units
8
2
1.66
2.26
427 578
2.85
731 bit
μs/step
μs
μs
428 734 581
1.72
1
μs kHz bit
Note(s):
1. The tolerance of the absolute PWM pulse width and frequency can be eliminated by using the duty cycle t
ON
/(t
ON
+t
OFF
) for angle measurement, see
.
2. Hysteresis may be temporarily disabled by software, see
Figure 17:
Serial 8-Bit Output 3-Wire Interface
Symbol
f
CLK t
CLK f clk,P
Parameter
Clock frequency
Clock frequency
Conditions
Normal operation
During OTP programming
Min Typ Max Units
166.6
250
6
500
MHz ns kHz
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AS5030 −
Electrical Characteristics
Figure 18:
Serial 8-Bit Output 2-Wire Interface
Symbol
f
CLK t
CLK f clk,P
Parameter
Clock frequency
Clock frequency t
TO
Hyst
Conditions
Normal operation
Synchronization timeout
During OTP programming
Rising edge of CLK to internally generated chip select on pin DX
At change of rotation direction
Min Typ Max
0.1
166.6
250
6
10000
500
Units
MHz ns kHz
16.6
27
1
34.3
ms bit
Note(s):
1. Hysteresis may be temporarily disabled by software.
Figure 19:
General Data Transmission Timings
Symbol
t0 t1 t2 t3 t4 t5 t6 t7 t8
Parameter
Rising CLK to CS
Chip select to positive edge of CLK
Chip select to drive bus externally
Setup time command bit data valid to positive edge of CLK
Hold time command bit data valid after positive edge of CLK
Float time positive edge of
CLK for last command bit to bus float
Bus driving time positive edge of CLK for last command bit to bus drive
Setup time data bit data valid to positive edge of
CLK
Hold time data bit data valid after positive edge of
CLK
Conditions Min
CLK/2 +0
Typ Max
CLK/2 +50
Units
ns
50
0
50
15
CLK/2 +0
CLK/2 +0
CLK/2 +0 ns ns ns ns
CLK/2 +0 ns ns
CLK/2 +30 ns ns
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Symbol
t9 t10 t11 t12 t13 t
TO
Parameter
Hold time chip select positive edge CLK to negative edge of chip select
Bus floating time negative edge of chip select to float bus
Hold time data bit @ write access data valid to positive edge of CLK
Hold time data bit @ write access data valid after positive edge of CLK
Bus floating time negative edge of chip select to float bus
Timeout period in 2-wire mode
(from rising edge of CLK)
Conditions
CLK/2
+50
50
15
20
AS5030 −
Electrical Characteristics
Min Typ Max
50
50
24
See
for the corresponding timing diagram.
Units
ns ns ns ns ns
μs
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AS5030 −
Detailed Description
Detailed Description
Figure 20:
SSI Read/Write Serial Data Transmission
Connecting the AS5030
The following examples show various ways to connect the
AS5030 to an external controller:
Serial 3-Wire R/W Connection
In this mode, the AS5030 is connected to the external controller via three signals:
Chip Select (CS), Clock (CLK) inputs and bi-directional DIO (Data
In/Out) output.
The controller sends commands over the DIO pin at the beginning of each data transmission sequence, such as reading the angle or putting the AS5030 in and out of the reduced power modes.
A pull-down resistor is not required. C1 and C2 are hardware configuration inputs. C1 must always be connected to VSS, C2 selects 3-wire mode (C2 = low) or 2-wire mode (C2 = high).
+ 5 V
VDD
VDD
Micro
Controller
Output
Output
I/O
VSS
VSS
13
VDD
11
CS
10
CLK
12
DI O
AS5030
14
C 1
15
C 2
3
VSS
100 n
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AS5030 −
Detailed Description
Figure 21:
Timing Diagram in 3-Wire SSI R/W Mode
CLK
CS
DIO
DIO
t3 t1
1 t
CLK command phase
2 3
CMD4 CMD3 t4
4 5 data phase
6 7 20 t5 t6
CMD0 t7 t8
D 15 D 14 D1 D0
21 t9
DIO read
t 10
DIO write
Figure 22:
Serial Bit Sequence (16-bit read/write)
C
4
Write Command
C
3
C
2
C
1
C
0
Read / Write Data
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Serial 3-Wire Read-Only Connection
If the AS5030 is only used to provide the angular data (no power down or OTP access) this simplified connection is possible. The
Chip Select (CS) and Clock (CLK) connection is the same as in the R/W mode, but only a digital input pin (not an I/O pin) is required for the DIO connection.
As the first 5 bits of the data transmission are command bits sent to the AS5030, both the microcontroller and the AS5030 are configured as digital inputs during this phase. Therefore, a pull-down resistor must be added to make sure that the AS5030 reads “00000” as the first 5 bits which sets the Read_Angle command.
All further application examples are shown in R/W mode, however read-only mode is also possible, unless otherwise noted.
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AS5030 −
Detailed Description
Figure 23:
SSI Read-Only Serial Data Transmission
+ 5 V
VDD
VDD
Output
Micro
Controller
Output
Input
VSS
VSS
10 k ...
100 k
13
VDD
11
CS
10
CLK
12
DI O
AS5030
C 1
14
C 2
15
VSS
3
100 n
CLK
CS
DIO
DIO
Figure 24:
Timing Diagram in 2-Wire and 3-Wire SSI Mode
t 1
1 command phase
2 3 4 5 data phase
7 8 6 20 21 t9
D 15 D 14 D 13 D 12 D 1 D 0 t 10
DIO read
DIO write
Figure 25:
Serial Bit Sequence (16-bit read/write)
D
20
0
D
19
0
D
18
D
17
0 0
D
16
0
D
15
D
14
C2 lock
Read
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
AGC Angle
D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
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AS5030 −
Detailed Description
Figure 26:
SSI R/W Mode 2-Wire Data Transmission
Serial 2-Wire Connection (R/W Mode)
By connecting the configuration input C2 to VDD, the AS5030 is configured to 2-wire data transmission mode.
Only Clock (CLK) and Data (DIO) signals are required. A Chip
Select (CS) signal is automatically generated by the DX output, when a time-out of CLK occurs (typ. 20μs).
Note(s):
Read-only mode is also possible in this configuration.
+ 5 V
VDD
VSS
VDD
Micro
Controller
Output
I/O
VSS
9
11
10
DX
CS
CLK
12
DI O
15
C 2
13
VDD
AS5030
14
C 1
3
VSS
100n
Figure 27:
Timing Diagram in 2-Wire SSI Mode
CLK
DX
CS t0
DIO read
DIO write
1 t1
2 command phase
3 4 5
CMD4 CMD3 CMD2 CMD1 t6
CMD0
6 t5
D 15
7 data phase
8
D 14 D0 wait cycle
(> 500 ns)
22
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AS5030 −
Detailed Description
Serial 2-Wire Continuous Readout
The termination of each readout sequence by a timeout of CLK after the 22 nd
clock pulse as described in
Connection (R/W Mode) is the safest method to ensure
synchronization, as each timeout of CLK resets the serial interface.
However, it is not mandatory to apply a timeout of CLK and consequently synchronization after each reading. It is also possible to read several consecutive angle values without synchronization by simply continuing the CLK pulses without timeout after the 22 nd
clock. The 23 rd
clock is equal to the 1 st clock of the next measurement, etc.
This is the fastest way to read multiple angle values, as there is no timeout period between the readings. It is still possible to synchronize the serial data transmission by a timeout of CLK after a given number of readouts (e.g. synchronize after every
5 th
reading, etc.).
Figure 28:
Timing Diagram in 2-Wire SSI Continuous Readout
CLK
DX
CS t0
DIO read
DIO write
1 t1
2 command phase
3 4 5
CMD4 CMD3 CMD2 CMD 1 t6
CMD0
6 t5
D 15 data phase
7 8
D 14 D0
22
1st reading
23 24 command phase
25
CMD 4 CMD 3 CMD2
2nd reading
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AS5030 −
Detailed Description
Serial 2-Wire Differential SSI Connection
With the addition of a RS-422 / RS-485 transceiver, a fully differential data transmission, according to the 21-bit SSI interface standard is possible. To be compatible with this standard, the CLK signal must be inverted. This is done by reversing the Data+ and Data- lines of the transceivers.
Note(s):
This type of transmission is read-only.
Figure 29:
2-Wire SSI Read-Only Mode
+ 5 V
VDD
VDD
Micro
Controller
Output
CLK
VSS
Input
DI
VSS
D+
D-
D-
D+
MAX 3081 or similar
D+ D+
DD-
Figure 30:
Timing Diagram in 2-Wire Read-Only Mode (differential transmission)
9
DX
11
CS
10
CLK
15
C2
13
VDD
AS5030
100n
12
DI O
C1
14
VSS
3
CLK
DI
1 2 3 4 5 6 7
D 15 D 14
8 20
D1
21 timeout t
TO
D0
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AS5030 −
Detailed Description
Figure 31:
SSI Read-Only Serial Bit Sequence (21-bit read)
D
20
0
D
19
D
18
0 0
D
17
D
16
0 0
D
15
D
14
C2 lock
Read
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
AGC Angle
D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
1-Wire PWM Connection
This configuration uses the least number of wires: only one line
(PWM) is used for data, leaving the total number of connection to three, including the supply lines. This type of configuration is especially useful for remote sensors.
Ultra-Low Power Mode is not possible in this configuration, as there is no bi-directional data transmission.
If the AS5030 angular data is invalid, the PWM output will remain at low state. Pins that are not shown may be left open.
Note that the PWM output is invalid when the AGC is disabled.
Figure 32:
Data Transmission with Pulse Width Modulated (PWM) Output
+ 5 V
VDD
VDD
Micro
Controller
Input
VSS
VSS
11
CS
13
VDD
AS5030
16
PWM
14
C 1
15
C 2
3
VSS
100 n
ams Datasheet
[v3-00] 2018-Mar-08
The minimum PWM pulse width t
ON
(PWM = high) is 1 LSB @ 0°
(Angle reading = 00
H
).
1LSB = nom. 2.26μs.
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AS5030 −
Detailed Description
The PWM pulse width increases with 1LSB per step. At the maximum angle 358.6° (Angle reading = FF
H
), the pulse width t
ON
(PWM = high) is 256 LSB and the pause width t
OFF
(PWM = low) is 1 LSB.
This leads to a total period (t
ON +
t
OFF
) of 257LSB
Figure 33:
PWM Timing
PWM out
5 V
0 V
2. 26 µs
578. 56 µs
0
291. 54 µs
287. 02 µs
128
578. 56 µs t on
2. 26 µs t off
255
Position
Figure 34:
SSI Read-Only Serial Bit Sequence (21-bit read)
Position
0
127
128
255
Angle
0°
178.59
180°
358.59°
High
1
128
129
256
t_ high
2.26μs
287.02μs
291.54μs
578.56μs
Low
256
129
128
1
t_ low
578.56μs
291.54μs
287.02μs
2.26μs
Duty-Cycle
0.39%
49.4%
50.2%
99.6%
This means that the PWM pulse width is (position + 1) LSB, where position is 0 …255.
The tolerance of the absolute pulse width and -frequency can be eliminated by calculating the angle with the duty cycle rather than with the absolute pulse width:
(EQ1)
angle
[
8
−
bit
]
=
257
t
ON t
ON
+
t
OFF
−
1 results in an 8-bit value from 00
H
to FF
H
,
(EQ2)
angle
[ ]
=
360
256
257
t
ON t
ON
+
t
OFF
−
1
results in a degree value from 0° ~ 358.6°
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AS5030 −
Detailed Description
Note(s):
The absolute frequency tolerance is eliminated by dividing t
ON
by (t
ON
+T
OFF
), as the change of the absolute timing effects both T
ON
and T
OFF
in the same way.
Analog Output
This configuration is similar to the PWM connection (only three lines including supply are required). With the addition of a low-pass filter at the PWM output, this configuration produces an analog voltage that is proportional to the angle.
This filter can be either passive (as shown) or active. The lower the bandwidth of the filter, the less ripple of the analog output can be achieved.
If the AS5030 angular data is invalid, the PWM output will remain at low state and thus the analog output will be 0V. Pins that are not shown may be left open.
Note(s):
The PWM output is invalid when the AGC is disabled.
Figure 35:
Data Transmission with Pulse Width Modulated (PWM) Output
+ 5 V
VDD
100n
11
CS
13
VDD
AS5030
C 1
14
C 2
15
VSS
3
PWM
16
>=4k7
>=1µF
>=4k7
>=1µF
Analog out
VSS
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AS5030 −
Detailed Description
Figure 36:
Relation of PWM/Analog Output with Angle
5 V
0 V
0° 180°
Analog out
360°
PWMout
Angle
Analog Sin/Cos Outputs with External
Interpolator
By connecting C1 to VDD, the AS5030 provides analog Sine and
Cosine outputs (Sin, Cos) of the Hall array front-end for test purposes. These outputs allow the user to perform the angle calculation by an external ADC + μC, e.g. to compute the angle with a high resolution.
In addition, the inverted Sine and Cosine signals (Sinn, Cosn; see dotted lines) are available for differential signal transmission.
The input resistance of the receiving amplifier or ADC should be greater than 100k
Ω
. The signal lines should be kept as short as possible, longer lines should be shielded in order to achieve best noise performance.
The SIN / COS / SINn / COSn signals are amplitude controlled to
~1.3Vp (differential) by the internal AGC controller. The DC bias voltage is 2.25V.
If the SIN(n)- and COS(n)- outputs cannot be sampled simultaneously, it is recommended to disable the automatic gain control as the signal amplitudes may be changing between two readings of the external ADC. This may lead to less accurate results.
ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
Detailed Description
Figure 37:
Sine and Cosine Outputs for External Angle Calculation
+ 5 V
VDD
VDD
D A
Micro
Controller
D A
VSS
VSS
5
4
Sin
Sinn
14
C 1
7
6
Cos
Cosn
13
VDD
AS5030
C 2
15
VSS
3
100n
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AS5030 −
Detailed Description
3-Wire Daisy Chain Mode
The Daisy Chain mode allows connection of more than one
AS5030 to the same controller interface. Independent of the number of connected devices, the interface to the controller remains the same with only three signals: CSn, CLK and DO. In
Daisy Chain mode, the data from the second and subsequent devices is appended to the data of the first device.
The 100nF buffer cap at the supply (shown only for the last device) is recommended for all devices.
The total number of serial bits is: n*21, where n is the number of connected devices: e.g. for 2 devices, the serial bit stream is
42-bits. For three devices it is 63 bits.
Figure 38:
Connection of Devices in 3-Wire Daisy Chain Mode
+5 V
VDD
VDD
Micro
Controller
Output
Output
VSS
I/O
VSS
13
VDD
AS5030
# 1
11
CS
10
CLK
12
DIO
C1
14
C2
15
DX
VSS
3
13
VDD
AS5030
# 2
11
CS
10
CLK
12
DIO
C1
14
C2
15
DX
VSS
3
13
VDD
AS5030
(last device)
11
CS
10
CLK
12
DIO
C1
14
C2
15
DX
VSS
3
100n
Figure 39:
Timing Diagram in 3-Wire Daisy Chain Mode
CLK
1 2 3 4 5 6 7 8 20 21 22 23 24 25 26 27 28 29 41 42 43 44
CS
DIO
CMD 4 CMD 3
CMD 2 CMD1 CMD0 D 15
D 14 D 13 D0 CMD4 CMD 3
CMD 2 CMD 1 CMD 0 D 15
D 14 D 13 D0 CMD 4 CMD 3
CMD2
AS5030 #1 AS5030 #2 AS5030 #3
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AS5030 −
Detailed Description
2-Wire Daisy Chain Mode
The AS5030 can also be connected in 2-wire Daisy Chain mode, requiring only two signals (Clock and Data) for any given number of daisy-chained devices. Note that the connection of all devices except the last device is the same as for the 3-wire connection (see
Figure 38 ). The last device must have pin C2
(#15) set to ‘high’ and feeds the DX signal to CS of the first device.
Again, each device should be buffered with a 100nF cap (shown only for the last device).
The total number of serial bits is: n*21, where n is the number of connected devices. Note that this configuration requires one extra clock (#1) to initiate the generation of the CS signal for the first device. After reading the last device, the communication must be reset back to the first device by introducing a timeout of CLK (no rising edge for >24μs).
Figure 40:
2-Wire Daisy Chain Mode
+ 5 V
VDD
VDD
Micro
Controller
Output
VSS
I/O
VSS
13
VDD
11
CS
AS5030
# 1
DX
10
CLK
12
DI O
C 1
14 15
C 2 VSS
3
13
VDD
AS5030
# 2
11
CS
10
CLK
12
DI O
C 1
14 15
C 2
DX
VSS
3
13
VDD
15
C 2
11
CS
10
CLK
12
DI O
C 1
14
AS5030
(last device)
DX
VSS
3
100n
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AS5030 −
Detailed Description
Figure 41:
Timing Diagram in 2-Wire Daisy Chain Mode
CLK
CS (#1)
1
CS (#2)
CS (#3)
2 3 4 5 6 7 8
DIO
CMD 4 CMD 3 CMD 2 CMD 1 CMD 0 D 15 D 14
21 22 23 24 25 26 27 28 29 42 43 44 45
D 0 CMD 4 CMD 3 CMD 2 CMD 1 CMD 0 D 15 D 14 D 0 CMD 4 CMD 3 CMD 2
AS 5030 # 1 AS5030 # 2 AS5030 # 3
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AS5030 −
Application Information
Application Information
Figure 42:
AS5030 Parameter and Features List
Parameter
Supply voltage
Supply current
Absolute output; Serial
Interface
SSI clock rate
2-wire readout mode
Power down modes
Digital input cells
SIN-COS mode
Maximum speed
Resolution and accuracy
Transition noise
PWM output
Digital output current
OTP programming mode
Magnetic field range
Description
5V ± 10%
Low Power Mode, non-operational: typ. 1.4mA
Ultra-Low Power Mode, non-operational: typ. 30μA
Normal operating mode: typ. 14mA.
21-bit Synchronous Serial Interface (SSI): 5 command bits, 2 data valid bits, 6 data bits for magnetic field strength, 8 data bits for angle.
Configurable for 2-wire (Clock, Data) or 3-wire (Chip Select, Clock, Data) operation
Daisy Chain mode for reading multiple encoders through a 2- or 3-wire interface.
Zero Position Programming (OTP)
≤
6 MHz data clock rate, 250 ~ 500kHz during programming
DIO and CLK signals. 0.1 ~ 6MHz clock rate. Synchronization through time-out of CLK signal.
Activated and deactivated by software commands.
Low Power Mode: power down current = 1.4mA typ.; power up time <150μs
Ultra-Low Power Mode: power down current = 30μA typ.; power up time
<500μs
CLK, CS = Schmitt trigger inputs
Sine, inverse Sine, Cosine and inverse Cosine outputs. 360° per period.
30000 rpm with locked ADC
Resolution = 8-bit (1.406°)
Accuracy
≤
± 2° with centered magnet
0.24°rms (1 sigma)
2.26μs / Step, PWM will be permanently low when angular data is not valid
(e.g. during startup).
4mA @ VDD = 5V (PWM, DIO, DX, MagRngn outputs)
Through serial interface with static programming voltage on pin #2 (PROG)
16-bit OTP programming register. OTP user programming options:
Angular zero position: 8 bit
Hall element sensitivity: 2 bit
Trimmable in four steps with OTP programming (sensitivity) maximum/minimum ratio ~ 2.5:1. Field range window = 20 ~ 80mT
(e.g. maximum sensitivity range = 20 ~ 48mT, minimum sensitivity range = 32 ~ 80mT
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AS5030 −
Application Information
Parameter
Non-valid-range indication
Start-up timings
ESD protection
Operating temperature
Description
By hardware: MagRngn pin indicates locked condition of ADC
By software: LOCK1&2 status bits indicate locked condition of ADC
Start-up time after shutdown < 2ms
Start-up time after power-down from Ultra-Low Power Mode: < 500μs
Start-up time after power-down from Low Power Mode: < 150μs
± 2kV
-40°C ~ 125°C
AS5030 Programming
The AS5030 has an integrated 18-bit OTP ROM for configuration purposes.
OTP Programming Options
The OTP programming options can be set permanently by programming or temporarily by overwriting. Both methods are carried out over the serial interface, but with different commands (WRITE OTP, PROG OTP).
Note(s):
During the 18-bit OTP programming, each bit needs 4 clock pulses to be validated.
• Zero Position Programming
This programming option allows the user to program any rotation angle of the magnet as the new zero position. This useful feature simplifies the assembly process as the magnet does not need to be mechanically adjusted to the electrical zero position. It can be assembled in any rotation angle and later matched to the mechanical zero position by zero position programming.
The 8-bit user programmable zero position can be applied both temporarily (command WRITE OTP, #1F
H
) or permanently (command PROG OTP, #19
H
).
• Magnetic Field Optimization
This programming option allows the user to match the vertical distance of the magnet with the optimum magnetic field range of the AS5030 by setting the sensitivity level.
The 2-bit user programmable sensitivity setting can be applied both temporarily (command WRITE OTP, #1F
H
) or permanently (command PROG OTP, #19
H
).
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AS5030 −
Application Information
Reduced Power Mode Programming Options
These temporary programming options are also carried out over the serial interface.
• Low Power Mode
Low Power Mode is a power saving mode with fast start-up. In Low Power Mode, all internal digital registers are frozen and the power consumption is reduced to max.
1.5mA. The serial interface remains active. Start-up from this mode to normal operation can be accomplished within 150μs. This mode is recommended for applications, where low power, but fast start-up and short reading cycle intervals are required.
• Ultra-Low Power Mode
Ultra-Low Power Mode is a power saving mode with even reduced power-down current consumption. In this mode, all chip functions are frozen and the power consumption is reduced to max. 50μA. The serial interface remains active. Start-up from this mode to normal operation can be accomplished within 500μs. This mode is recommended for applications, where very low average power consumption is required, e.g. for battery operated equipment. For example, in a cycled operation with 10 readings per second, the average power consumption of the AS5030 can be reduced to only 120μA.
AS5030 Read / Write Commands
Data transmission with the AS5030 is handled over the 2-wire or 3-wire interface. The transmission protocol begins with sending a 5-bit command to the AS5030, followed by reading or writing 16 or 18 bits of data:
16-Bit Read Command
Figure 43:
16-Bit Read Command
Command Bin Hex
D
15
RD
ANGLE
00000 00 C2
D
14
lock
D
13
D
12
D
11
D
10
D
9
AGC 5:0
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Angle 7:0
C2
displays status of hardware pin C2 (pin #15)
Lock:
Indicates that the AGC is locked. Data is invalid when this bit is 0
AGC:
6-bit AGC register. Indicates the strength of the magnet
(e.g. for push-button applications)
000000 b indicates a strong magnetic field
111111 b
indicates a weak magnetic field
Ideally, the vertical distance of the magnet should be chosen such that the AGC value is in the middle (around 100000b).
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AS5030 −
Application Information
Angle:
8-bit Angle value; represents the rotation angle of the magnet. One step = 360°/256 = 1.4°.
16-Bit Write Command
These settings are temporary; they cannot be programmed permanently. The settings will be lost when the power supply is removed
Figure 44:
16-Bit Write Command.
Command
EN PROG
Bin
10000
Hex
10 1
D
15
SET PWR
MODE
DIS HYST
DIS AGC
10001
10011
10101
11
13
15
0
D
14
ULP/
LPn
PSM 0
HYS
0
0
0 0
D
13
D
12
0 0
D
11
D
10
1 1 0
D
9
0
D
8
0 0 rst 0 0 0
D
7
1 0
D
6
1
D
5
D
4
0 1
D
3
1
D
2
D
1
1 0
D
0
AGC 5:0 FA
EN PROG:
Command must be sent with a fixed 16-bit code
(8CAE
H
) to enable subsequent OTP access.
ULP/LP
n: Selects the Ultra-Low Power Mode, when bit PSM is set: 0 = Low Power Mode, 1 = Ultra-Low Power Mode
PSM:
Enables power saving modes: 0 = normal operation,
1 = reduced power mode selected by bit ULP/LPn
HYS
: Disables the hysteresis of the digital serial and PWM outputs:
0 (default) = 1-bit hysteresis, 1 = no hysteresis
DIS AGC:
Disables the automatic gain control. The AGC will be frozen to a gain setting written in bits AGC 5:0 (D6:D1), bit FA must be set.
rst
: General Reset: 0 = normal operation, 1 = perform general reset (required after return from reduced power modes)
FA
: Freeze AGC; 0 = normal operation, 1= freeze AGC with the values stored in bits AGC 5:0. The PWM output will be invalid when bit FA is set.
18-Bit OTP Read Commands
Note(s):
To prohibit unintentional access to the OTP register,
OTP PROG/write access is only enabled after the EN PROG command has been sent. OTP access is locked again by sending a RD ANGLE or SET PWR MODE command.
EN PROG need not to be sent before a READ OTP.
During the 18bit OTP read/write transfer, each bit needs 4 clock pulses to be validated.
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AS5030 −
Application Information
Figure 45:
18-Bit OTP Read Commands
Command Bin Hex
D
17
D
16
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
READ OTP
ANALOG
OTP RD
011
11
010
01
0F
09
Reserved for factory settings
Reserved for factory settings sens
1:0 sens
1:0
D
4
D
3
D
2
D
1
D
0
Zero position
7:0
Zero position
7:0
READ OTP
: Reads the contents of the OTP register in digital form. The reserved area may contain any value.
ANALOG OTP RD
: Reads the contents of the OTP register as an analog voltage at pin PROG.
sens
: Reads the sensitivity setting of the Hall elements: 00 = low sensitivity, 11 = high sensitivity.
zero position:
Reads the programmed zero position; the actual angle of the magnet which is displayed as 000.
18-Bit OTP Write Commands
During the 18bit OTP read/write transfer, each bit needs 4 clock pulses to be validated.
Figure 46:
18-Bit OTP Write Commands
Command
WRITE OTP
PROG OTP
Bin
11111
11001
Hex
1F
19
D
17
D
16
D
15
D
14
D
13
copy factory settings obtained from READ OTP command
00000000 reserved for factory settings,
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
sens
1:0 sens
1:0 zero position
7:0 zero position
7:0
WRITE OTP:
Non-permanent (“soft write”) modification of the
OTP register. To set the reserved factory settings area properly, a preceding READ OTP command must be made to receive the correct setting for bits D17:D10. The WRITE OTP command must then set these bits in exactly the same way. Improper setting of the factory settings by a WRITE OTP command may cause malfunction of the chip. The OTP register, including the factory settings can be restored to default by a power-up cycle.
For non-permanent writing, a programming voltage at pin
PROG (#2) is not required. EN_PROG must be sent before
WRITE_OTP to enable OTP.
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AS5030 −
Application Information
PROG OTP:
Permanent modification of the OTP register. An unprogrammed OTP bit contains a ‘0, programmed bits are 1’s.
It is possible to program the OTP in several sequences. However, only a 0 can be programmed to 1. Once programmed, an OTP bit cannot be set back to 0. For subsequent programming, bits that are already programmed should be set to 0 to avoid double programming.
During permanent programming, the factory settings D17:D10 should always be set to zero to avoid modification of the factory settings.
Modifying the factory settings may cause irreversible malfunction of the chip.
For permanent programming, a static programming voltage of
8.0-8.5V must be applied at pin PROG (#2). EN_PROG must be sent before PROG_OTP to enable OTP.
sens:
Sets the sensitivity setting of the Hall elements:
00: gain factor = 1.65 (low sensitivity)
01: gain factor = 1.75
10: gain factor = 1.86
11: gain factor = 2.00 (high sensitivity)
zero position:
Sets the user programmable zero position; the actual angle of the magnet which is displayed as 000.
Figure 47:
Timing Diagram in OTP 18-Bit Read/Write Mode
Command phase
DCLK
CS
DIO t0 t2
DIO t3 t1
HI
DIO t4
HI CMD2 t5 t6
CMD0 t11
D17
D17
Data phase extended t8 t12
D16 t7
D16
D0
D0 t9 t10
READ t13
WRITE
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OTP Programming Connection
Programming of the AS5030 OTP memory does not require a dedicated programming hardware. The programming can be simply accomplished over the serial 3-wire interface (see
Figure 48 ) or the optional 2-wire interface (see
).
For permanent programming (command PROG OTP, #19
H
), a constant DC voltage of 8.0V ~ 8.5V (≥100mA) must be connected to pin #2 (PROG).
ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
Application Information
For temporary OTP write (“soft write”; command WRITE OTP,
#1F
H
), the programming voltage is not required.
To secure unintentional programming, any modification of the
OTP memory is only enabled after a special password
(command #10
H
) has been sent to the AS5030.
Figure 48:
OTP Programming Connection
+ 5 V
VDD
Micro
VDD
Controller
VSS
Output
Output
I/O
8. 0 – 8.5V
11
CS
10
CLK
12
DI O
2
PROG
13
VDD
AS5030
10µF 100n
14
C 1
15
C 2 VSS
3
VSS
100n
Programming in Daisy Chain Mode
Programming in Daisy chain mode is possible for both 3-wire and 2-wire mode (see
and
programming (soft write), no additional connections are required. Programming is executed with the respective programming commands. For permanent programming, the programming voltage must be applied on pin#2 (PROG) of the device to be programmed. It is also possible to apply the programming voltage simultaneously to all devices, as the actual programming is only executed by a software command.
A parallel connection of all PROG-pins allows digital programming verification but does not allow analog programming verification.
If analog programming verification is required, each PROG pin must be selected individually for verification.
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AS5030 −
Application Information
Programming Verification
After programming, the programmed OTP bits may be verified in two ways:
By digital verification:
This is simply done by sending a READ OTP command (#0F
H
).
The structure of this register is the same as for the OTP PROG or OTP WRITE commands.
By analog verification:
By sending an ANALOG OTP READ command (#09
H
), pin PROG becomes an output, sending an analog voltage with each clock, representing a sequence of the bits in the OTP register. A voltage of <500mV indicates a correctly programmed bit (“1”) while a voltage level between 2.2V and 3.5V indicates a correctly unprogrammed bit (“0”). Any voltage level in between indicates improper programming.
Figure 49:
Analog OTP Verification
+ 5 V
VDD
VDD
Output
Micro
Controller
Output
I/O
VSS
V
11
CS
10
CLK
12
DI O
2
PROG
13
VDD
AS5030
C 1
14
C 2
15
VSS
3
100n
VSS
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AS5030 −
Application Information
ams Datasheet
[v3-00] 2018-Mar-08
AS5030 Status Indicators
Refer to
.
C2 Status Bit
This bit represents the hardware connection of the C2 configuration pin (#15) to determine, which hardware configuration is selected for the AS5030 in question.
C2 = low: pin C2 is ‘low’, indicating that the AS5030 is in 3-wire mode or a member of a 2-wire daisy chain connection (except the last).
C2 = high: pin C2 is ‘high’, indicating that the AS5030 is in 2-wire mode and/or the last member of a 2-wire daisy chain connection.
Lock Status Bit
The Lock signal indicates the ADC lock status. If Lock = low (ADC unlocked), the angle information is invalid. To determine a valid angular signal at best performance, the following indicators should be set:
Lock = 1
AGC > 00
H
and < 2F
H
Note(s):
The angle signal may also be valid (Lock = 1), when the
AGC is out of range (00
H
or 2F
H
), but the accuracy of the AS5030 may be reduced due to the out of range condition of the magnetic field strength.
Magnetic Field Strength Indicators
The AS5030 is not only able to sense the angle of a rotating magnet, it can also measure the magnetic field strength (and hence the vertical distance) of the magnet.
This extra feature can be used for several purposes:
•
As a safety feature by constantly monitoring the presence and proper vertical distance of the magnet
•
As a state-of-health indicator, e.g. for a power-up self test
•
As a push-button feature for rotate-and-push types of manual input devices
•
The magnetic field strength information is available in two forms:
Magnetic Field Strength Hardware Indicator:
Pin MagRngn (#1) will be ‘high’, when the magnetic field is too weak. The switching limit is determined by the value of the AGC.
If the AGC value is <3F
H
, the MagRngn output will be ‘low’
(green range), If the AGC is at its upper limit (3F
H
), the MagRngn output will be ‘high’ (red range).
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AS5030 −
Application Information
Magnetic Field Strength Software Indicator:
D13:D7 in the serial data that is obtained by command READ
ANGLE contains the 6-bit AGC information. The AGC is an automatic gain control that adjusts the internal signal amplitude obtained from the Hall elements to a constant level.
If the magnetic field is weak, e.g. with a large vertical gap between magnet and IC, with a weak magnet or at elevated temperatures of the magnet, the AGC value will be ‘high’.
Likewise, the AGC value will be lower when the magnet is closer to the IC, when strong magnets are used and at low temperatures.
The best performance of the AS5030 will be achieved when operating within the AGC range. It will still be operational outside the AGC range, but with reduced performance especially with a weak magnetic field due to increased noise.
Factors Influencing the AGC Value:
In practical use, the AGC value will depend on several factors:
•
The initial strength of the magnet. Aging magnets may show a reducing magnetic field over time which results in an increase of the AGC value. The effect of this phenomenon is relatively small and can easily be compensated by the AGC.
•
The vertical distance of the magnet. Depending on the mechanical setup and assembly tolerances, there will always be some variation of the vertical distance between magnet and IC over the lifetime of the application using the AS5030. Again, vertical distance variations can be compensated by the AGC.
•
The temperature and material of the magnet. The recommended magnet for the AS5030 is a diametrically magnetized, 5-6mm diameter NdFeB
(Neodymium-Iron-Boron) magnet. Other magnets may also be used as long as they can maintain to operate the
AS5030 within the AGC range.
Every magnet has a temperature dependence of the magnetic field strength. The temperature coefficient of a magnet depends on the used material. At elevated temperatures, the magnetic field strength of a magnet is reduced, resulting in an increase of the AGC value. At low temperatures, the magnetic field strength is increased, resulting in a decrease of the AGC value.
The variation of magnetic field strength over temperature is automatically compensated by the AGC.
ams Datasheet
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AS5030 −
Application Information
OTP Sensitivity Adjustment
To obtain best performance and tolerance against temperature or vertical distance fluctuations, the AGC value at normal operating temperature should be in the middle between minimum and maximum, hence it should be around 100000
(20
H
).
To facilitate the “vertical centering” of the magnet+IC assembly, the sensitivity of the AS5030 can be adjusted in the OTP register in 4 steps. A sensitivity adjustment is recommended, when the
AGC value at normal operation is close to its lower limit (around
00
H
). The default sensitivity setting is 00
H
= low sensitivity.
“Push-Button” Feature
Using the magnetic field strength software and hardware indicators described above, the AS5030 provides a useful method of detecting both rotation and vertical distance simultaneously. This is especially useful in applications implementing a rotate-and-push type of human interface (e.g. in panel knobs and switches).
The MagRngn output is ‘high’, when the magnetic field is below the low limit (weak or no magnet) and low when the magnetic field is above the low limit (in-range or strong magnet).
A finer detection of a vertical distance change, for example when only short vertical strokes are made by the push-button, is achieved by memorizing the AGC value in normal operation and triggering on a change from that nominal the AGC value to detect a vertical movement.
Figure 50:
Magnetic Field Strength Indicator
+ 5 V
VDD
VDD
Micro
Controller
Output
Output
I/O
VSS
LED 1
1 k
13
VDD
10
12
1
11
MagRngn
CS
AS5030
CLK
DI O
C 1
14
C 2
15
VSS
3
100n
VSS
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High Speed Operation
The AS5030 is using a fast tracking ADC (TADC) to determine the angle of the magnet. The TADC has a tracking rate of 1.15μs
(typ).
Once the TADC is synchronized with the angle, it sets the LOCK bit in the status register. In worst case, usually at start-up, the
TADC requires a maximum of 127 steps (127 * 1.15μs = 146.05μs) to lock. Once it is locked, it requires only one cycle (1.15μs) to track the moving magnet.
The AS5030 can operate in locked mode at rotational speeds up to 30000 rpm.
In Low Power Mode or Ultra-Low Power Mode, the position of the TADC is frozen. It will continue from the frozen position once it is powered up again. If the magnet has moved during the power down phase, several cycles will be required before the
TADC is locked again. The tracking time to lock in with the new magnet angle can be roughly calculated as:
(EQ3)
t
LOCK
=
1 .
15
μ
s
∗
NewPos
−
OldPos
t
LOCK
= time required to acquire the new angle after power up from one of the reduced power modes [μs]
OldPos = Angle position when one of the reduced power modes is activated [°]
NewPos = Angle position after resuming from reduced power mode [°]
Propagation Delay
The Propagation delay is the time required from reading the magnetic field by the Hall sensors to calculating the angle and making it available on the serial or PWM interface. While the propagation delay is usually negligible on low speeds it is an important parameter at high speeds.
The longer the propagation delay, the larger becomes the angle error for a rotating magnet as the magnet is moving while the angle is calculated. The position error increases linearly with speed.
The main factors contributing to the propagation delay are:
ADC Sampling Rate
For high speed applications, fast ADCs are essential. The ADC sampling rate directly influences the propagation delay. The fast tracking ADC used in the AS5030 with a tracking rate of only 1.15μs (typ.) is a perfect fit for both high speed and high performance.
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AS5030 −
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Chip Internal Low-Pass Filtering
A commonplace practice for systems using analog-to-digital converters is to filter the input signal by an anti-aliasing filter.
The filter characteristic must be chosen carefully to balance propagation delay and noise.
The low-pass filter in the AS5030 has a cut-off frequency of typ.
23.8kHz and the overall propagation delay in the analog signal path is typ. 15.6μs.
Digital Readout Rate
Aside from the chip-internal propagation delay, the time required to read and process the angle data must also be considered. Due to its nature, a PWM signal is not very usable at high speeds, as you get only one reading per PWM period.
Increasing the PWM frequency may improve the situation but causes problems for the receiving controller to resolve the PWM steps. The frequency on the AS5030 PWM output is typ. 1.95kHz with a resolution of 2μs/step.
A more suitable approach for high speed absolute angle measurement is using the serial interface. With a clock rate of up to 6MHz, a complete set of data (21bits) can be read in >3.5μs
Total Propagation Delay of the AS5030
The total propagation delay of the AS5030 is the delay in the analog signal path and the tracking rate of the ADC:
15.6μs + 1.15μs = 16.75μs
If only the SIN-/COS-outputs are used, the propagation delay is the analog signal path delay only (typ. 15.6μs).
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Application Information
(EQ4)
(EQ5)
Position Error Over Speed
The angle error over speed caused by the propagation delay is calculated as:
Δφ pd
= rpm * 6 * 16.75E
-6 in degrees
In addition, the anti-aliasing filter causes an angle error calculated as:
Δφ lpf
= ArcTan [ rpm / ( 60*f
0
) ]
Examples of the overall position error caused by speed, including both propagation delay and filter delay:
Figure 51:
Speed (rpm)
Total Position Error (
∆φ
pd
+
∆φ
l pf
)
100
1000
10000
0.0175°
0.175°
1.75°
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Reduced Power Modes
The AS5030 can be operated in 3 reduced power modes. All 3 modes have in common that they switch off or freeze parts of the chip during intervals between measurements. In Low Power
Mode or Ultra-low Power Mode, the AS5030 is not operational, but due to the fast start-up, an angle measurement can be accomplished very quickly and the chip can be switched to reduced power immediately after a valid measurement has been taken. Depending on the intervals between measurements, very low average power consumption can be achieved using such a strobed measurement mode.
•
Low Power Mode: Reduced current consumption, very fast start-up. Ideal for short sampling intervals (<3ms)
•
Ultra-Low Power Mode: Further reduced current consumption, but slower start-up than Low Power Mode.
Ideal for sampling intervals from 3….200ms.
•
Power Cycle mode: zero power consumption (externally switched off) during sampling intervals, but slower start-up than Ultra-Low Power Mode. Ideal for sampling intervals 200ms.
Low Power Mode and Ultra-Low Power Mode
Figure 52:
Low Power Mode and Ultra-Low Power Mode Connection
C1: optional; see text
VDD
100n
S N
AS5030
VSS C1 C2
CS
CLK
DIO
R1: optional; see text
I on
I off t on t off
VDD on/off
Micro
Controller
+5V
VDD
VSS
VSS
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The AS5030 can be put in Low Power Mode or Ultra-Low Power
Mode by simple serial commands, using the regular connection for 2-wire or 3-wire serial data transmission (see
The required serial command is SET PWR MODE (11
H
):
Figure 53:
Power Mode Configuration
ULP / LPn
1
1
0
0
PSM
0
1
0
1
Mode
Normal Operation
Low Power Mode
Normal Operation
Ultra-Low Power Mode
Note(s):
1. After returning from Low Power mode or Ultra-Low Power mode to normal operation (PSM = 0), if the Hysteresis is enabled (Hys=0), a general reset must be performed: set bit RST and then clear bit RST using command 15
H
.
The two following cases describe the typical loop programmed in the software:
Hys = 0 (1 LSB hysteresis)
1.
Wait for CPU interrupt or delay for next angle read (typ.
<3ms in LP mode, typ>3ms in ULP mode)
2.
Wake up (PSM = 0)
3.
Set Reset (rst = 1)
4.
Clear Reset (rst = 0)
5.
Wait 1.5ms (Low Power Mode)
6.
Check if Lock = 1 then read angle
7.
Enable Low Power Mode or Ultra-Low Power Mode
(PSM=1)
8.
Return to 1
Hys = 1 (No hysteresis)
1.
Wait for CPU interrupt or delay for next angle read (typ.
<3ms in LP mode, typ>3ms in ULP mode)
2.
Wake up (PSM = 0)
3.
Wait 0.01ms (Low Power Mode)
4.
Check if Lock = 1 then read angle
5.
Enable Low Power Mode or Ultra-Low Power Mode
(PSM=1)
6.
Return to 1
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The difference between Low Power Mode and Ultra-Low Power
Mode is the current consumption and the wake-up time to switch back to active operation.
Figure 54:
Current Consumption of Power Modes
Mode
Active Operation
Low Power Mode
Ultra-Low Power
Mode
Current Consumption (typ.)
14 mA
1.4 mA
30 μA
Wake-Up Time to Active Operation
1.0 ms (without AGC)
3.8 ms (with locked AGC)
0.15 ms
0.5 ms
In both Reduced Power Modes, the AS5030 is inactive. The last state, e.g. the angle, AGC value, etc. is frozen and the chip starts from this frozen state when it resumes active operation. This method provides much faster start-up than a “cold start” from zero. If the AS5030 is cycled between active and reduced current mode, a substantial reduction of the average supply current can be achieved. The minimum dwelling time in active mode is the wake-up time. The actual active time depends on how much the magnet has moved while the AS5030 was in reduced power mode. The angle data is valid, when the status bit LOCK has been set. Once a valid angle has been measured, the AS5030 can be put back to reduced power mode. The average power consumption can be calculated as:
(EQ6)
I avg
=
I
× t on
+ t on
I
+ t off
× t off
Sampling interval = t on
+ t off
I avg
: average current consumption
I active
: current consumption in active mode
I power_down
: current consumption in reduced power mode t on
: time period during which the chip is operated in active mode t off
: time period during which the chip is in reduced power mode
Example: Ultra-Low Power Mode; sampling period = one measurement every 10ms.
System constants = I active
= 14mA,
I power_down
= 30μA, t on
(min) = 500μs
(startup from Ultra-Low Power Mode)
(EQ7)
I avg
=
14mA 500
μ s
500 μ
+ 30
μ
A 9.5ms
s 9.5ms
= 729
μ
A
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See
for an overview table of the average current consumption in the various reduced power modes.
Reducing Power Supply Peak Currents
An optional RC-filter (R1/C1) may be added to avoid peak currents in the power supply line when the AS5030 is toggled between active and reduced power mode. R1 must be chosen such that it can maintain a VDD voltage of 4.5V ~ 5.5V under all conditions, especially during long active periods when the charge on C1 has expired. C1 should be chosen such that it can support peak currents during the active operation period. For long active periods, C1 should be large and R1 should be small.
Power Cycling Mode
The power cycling method shown in
cycles the
AS5030 by switching it on and off, using an external PNP transistor high side switch.
This mode provides the least power consumption of all three modes; when the sampling interval is more than 400ms, as the current consumption in off-mode is zero.
It also has the longest start-up time of all modes, as the chip must always perform a “cold start“ from zero, which takes about
1.9 ms.
The optional filter R1/C1 may again be added to reduce peak currents in the 5V power supply line.
Figure 55:
Application Example III: Ultra-low Power Encoder
VDD
I on
0 t on t off
100n
S N
AS5030
VSS C1 C2
CS
CLK
DIO
10k
C1
>1µF
R1 ton toff
VDD on/off
Micro
Controller
+5V
VDD
VSS
VSS
Figure 55 shows an overview of the average supply currents in
the three reduced power modes, depending on the sampling interval. The graphs shows that the Low Power Mode is the best option for sampling intervals <4ms, while the Ultra-Low Power
Mode is the best option for sampling intervals between
4~400ms.
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Application Information
At sampling intervals > 400ms, the power cycling mode is the best method to minimize the average current consumption.
The curves are based on the figures given in
Low Power Mode and Ultra-Low Power Mode .
Figure 56:
Average Current Consumption of Reduced Power Modes
AS5030 av erag e cu rrent consum ption
3,5
3,0
2,5
2,0
1,5
1,0
0,5
0,0
5,0
4,5
4,0
1
Ultra Low P ower Mode
10
Low Power Mode
Power C ycling Mode
100
samp ling interval [m s]
1000
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Accuracy of the Encoder System
This chapter describes which individual factors influence the accuracy of the encoder system and how to improve them.
Accuracy is defined as the difference between measured angle and actual angle. This is not to be confused with resolution, which is the smallest step that the system can resolve.
The two parameters are not necessarily linked together. A high resolution encoder may not necessarily be highly accurate as well.
Quantization Error
There is however a direct link between resolution and accuracy, which is the quantization error:
Figure 57:
Quantization Error of a Low Resolution and a High Resolution System
Quantization
Error
ideal function digitized function low resolution ideal function digitized function high resolution
+½ LSB
-½ LSB error
The resolution of the encoder determines the smallest step size.
The angle error caused by quantization cannot get better than
± ½ LSB. As shown in
Figure 57 , a higher resolution system (right
picture) has a smaller quantization error, as the step size is smaller.
For the AS5030, the quantization error is ± ½ LSB = ± 0.7°
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Application Information
Figure 58:
Typical INL Error Over 360°
INL including quantization error
1,5
1
0,5
0
-0,5
-1
-1,5
0 45 90 135 180
Angle steps
225
INL Average (16x)
270 315 360
Figure 58 shows a typical example of an error curve over a full
turn of 360° at a given X-Y displacement. The curve includes the quantization error, transition noise and the system error. The total error is ~2.2° peak/peak (± 1.1°).
The sawtooth-like quantization error (see also
) can be reduced by averaging, provided that the magnet is in constant motion and there are an adequate number of samples available.
The solid bold line in
shows the moving average of
16 samples. The INL (intrinsic non-linearity) is reduced to from
~± 1.1° down to ~± 0.3°. The averaging however, also increases the total propagation delay, therefore it may be considered for low speeds only or adaptive; depending on speed
.
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64
56
48
40
32
24
16
8
0
0
Vertical Distance of the Magnet
The chip-internal automatic gain control (AGC) regulates the input signal amplitude for the tracking-ADC to a constant value.
This improves the accuracy of the encoder and enhances the tolerance for the vertical distance of the magnet.
Figure 59:
Typical Curves for Vertical Distance Versus ACG Value on Several Untrimmed Samples
Linearity and AGC vs Airgap
500 1000 1500 2000
2,2
2,0
1,8
1,6
1,4
1,2
1,0
2500 sample#1 sample#2 sample#3 sample#4 Linearity [°]
As shown in
Figure 59 , the AGC value (left Y-axis) increases with
vertical distance of the magnet.
Consequently, it is a good indicator for determining the vertical position of the magnet, for example as a push-button feature, as an indicator for a defective magnet or as a preventive warning (e.g. for wear on a ball bearing etc.) when the nominal
AGC value drifts away.
If the magnet is too close or the magnetic field is too strong, the AGC will be reading 0.
If the magnet is too far away (or missing) or if the magnetic field is too weak, the AGC will be reading 63 (3F
H
).
The AS5030 will still operate outside the AGC range, but the accuracy may be reduced as the signal amplitude can no longer be kept at a constant level.
The linearity curve in Figure 59
(right Y-axis) shows that the accuracy of theAS5030 is best within the AGC range, even slightly better at small airgaps (0.4mm ~ 0.8mm).
At very short distances (0mm ~ 0.1mm) the accuracy is reduced, mainly due to nonlinearities in the magnetic field.
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At larger distances, outside the AGC range (~2.0mm ~ 2.5mm and more) the accuracy is still very good, only slightly decreased from the nominal accuracy.
Since the field strength of a magnet changes with temperature, the AGC will also change when the temperature of the magnet changes. At low temperatures, the magnetic field will be stronger and the AGC value will decrease. At elevated temperatures, the magnetic field will be weaker and the AGC value will increase.
Sensitivity Trimming
As the curves for the 4 samples in
show, the AGC value will not show exactly the same value at a given airgap on each part. For example, at 1mm vertical distance, the AGC may read a value between ~11 ~ 24. This is because for normal operation an exact trimming is not required since the AGC is part of a closed loop system.
However, the AS5030 offers an optional user trimming in the
OTP to allow an even tighter AGC tolerance for applications where the information about magnetic field strength is also utilized, e.g. for rotate-and-push types of knobs, etc.
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Choosing the Proper Magnet
Figure 60:
Vertical Magnetic Fields of a Rotating Magnet
typ. 6mm diameter
Vertical field component
N
R1
S
Magnet axis
Magnet axis
N S
Vertical field component
Bz
(20…80mT)
R1 concentric circle; radius 1.0 mm
0
360
Note(s):
1. There is no strict requirement on the type or shape of the magnet to be used with the AS5030. It can be cylindrical as well as square in shape. The key parameter is that the vertical magnetic field B z
, measured at a radius of 1mm from the rotation axis is sinusoidal with a peak amplitude of 20 ~ 80mT.
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Magnet Placement
Ideally, the center of the magnet, the diagonal center of the IC and the rotation axis of the magnet should be in one vertical line.
The lateral displacement of the magnet should be within ±
0.25mm from the IC package center or ± 0.5mm from the IC center, including the placement of the chip within the IC package.
The vertical distance should be chosen such that the magnetic field on the die surface is within the specified limits. The typical distance “z” between the magnet and the package surface is
0.5mm to 1.8mm with the recommended magnet (6mm x
2.5mm). Larger gaps are possible, as long as the required magnetic field strength stays within the defined limits. A magnetic field outside the specified range may still produce acceptable results, but with reduced accuracy. The out-of-range condition will be indicated, when the AGC is at the limits
(AGC= 0: field too strong;
AGC=63=(3F
H
): field too weak or missing magnet.
Figure 61:
Bz Field Distribution Along the X-Axis of a 6mmØ Diametric Magnetized Magnet ams Datasheet
[v3-00] 2018-Mar-08
Figure 61 shows a cross sectional view of the vertical magnetic
field component Bz between the north and south pole of a 6mm diameter magnet, measured at a vertical distance of 1mm. The poles of the magnet (maximum level) are about 2.8mm from the magnet center, which is almost at the outer magnet edges.
The magnetic field reaches a peak amplitude of ~± 106mT at the poles.
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The Hall elements are located at a radius of 1mm (indicated as squares at the bottom of the graph). Due to the side view, the two Hall elements at the Y-axis are overlapping at X = 0mm, therefore only 3 Hall elements are shown.
At 1mm radius, the peak amplitude is ~± 46mT, respectively a differential amplitude of 92mT.
The vertical magnetic field B z
follows a fairly linear pattern up to about 1.5mm radius. Consequently, even if the magnet is not perfectly centered, the differential amplitude will be the same as for a centered magnet.
For example, if the magnet is misaligned in X-axis by -0.5mm, the two X-Hall sensors will measure 70mT (@x = -1.5mm) and
-22mt (@x = -0.5mm). Again, the differential amplitude is 92mT.
At larger displacements however, the B z
amplitude becomes nonlinear, which results in larger errors that mainly affect the accuracy of the system (see also
Figure 62:
Vertical Magnetic Field Distribution of a Cylindrical 6mm Ø Diametric Magnetized Magnet at
1mm Gap
BZ; 6mm magnet @ Z=1mm
Bz [mT]
125
100
75
50
25
0
-25
-50
-75
-100
-125
4
3
2
2
1
X-displacement [mm]
N
0 area of X-Y-misalignment from center: +/- 0.5mm
circle of Hall elements on chip: 1mm radius
-1
-2
-3
-4
S
-2
4
3
2
1
0
-1
Y-displacement [mm]
-3
Figure 62 shows the same vertical field component as
but in a 3-dimensional view over an area of ± 4mm from the rotational axis.
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Lateral Displacement of the Magnet
As shown in the magnet specifications
recommended horizontal position of the magnet axis with respect to the IC package center is within a circle of 0.25mm radius. This includes the placement tolerance of the IC within the package.
Figure 63 shows a typical error curve at a medium vertical
distance of the magnet around 1.2mm (AGC = 24).
The X- and Y- axis of the graph indicate the lateral displacement of the magnet center with respect to the IC center.
At X = Y = 0, the magnet is perfectly centered over the IC. The total displacement plotted on the graph is for ± 1mm in both directions.
The Z-axis displays the worst case INL error over a full turn at each given X-and Y- displacement. The error includes the quantization error of ± 0.7°. For example, the accuracy for a centered magnet is between 1.0 ~ 1.5° (spec = 2° over full temperature range). Within a radius of 0.5mm, the accuracy is better than 2.0° (spec = 3° over temperature).
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Figure 63:
Typical Error Curve of INL Error Over Lateral Displacement (including quantization error)
INL vs. Displacement: AS5030 for AGC24
5,000
4,500
INL [°]
4,000
3,500
3,000
2,500
2,000
1,500
1,000
0,500
0,000
-1000
-750
-500
-250
0
X Displaceme nt [µm]
1000
750
500
250
0
250
500
- 750
750
1000
-1000
-250
-500
Y Displacem ent [µm]
4,500-5,000
4,000-4,500
3,500-4,000
3,000-3,500
2,500-3,000
2,000-2,500
1,500-2,000
1,000-1,500
0,500-1,000
0,000-0,500
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Magnet Size
Figure 63 in this chapter describe a cylindrical
magnet with a diameter of 6mm. Smaller magnets may also be used, but since the poles are closer together, the linear range will also be smaller and consequently the tolerance for lateral misalignment will also be smaller.
If the ± 0.25mm lateral misalignment radius (rotation axis to IC package center) is too tight, a larger magnet can be used. Larger magnets have a larger linear range and allow more misalignment. However at the same time the slope of the magnet is more flat which results in a lower differential amplitude.
This requires either a stronger magnet or a smaller gap between
IC and magnet in order to operate in the amplitude-controlled area (AGC > 0 and AGC < 63).
In any case, if a magnet other than the recommended 6mm diameter magnet is used, two parameters should be verified:
Verify that the magnetic field produces a sinusoidal wave, when the magnet is rotated. Note that this can be done with the
SIN-/COS- outputs of the AS5030, e.g. rotate the magnet at constant speed and analyze the SIN- (or COS-) output with an
FFT-analyzer.
It is recommended to disable the AGC for this test.
Verify that the B z
-Curve between the poles is as linear as possible. This curve may be available from the magnet supplier(s). Alternatively, the SIN- or COS- output of the AS5030 may also be used together with an X-Y- table to get a B z
-scan of the magnet. Furthermore, the sinewave tests described above may be re-run at defined X-and Y- misplacements of the magnet to determine the maximum acceptable lateral displacement range.
It is recommended to disable the AGC for both these tests.
Note(s):
For preferred magnet suppliers, please refer to the
ams
website (Position Sensor section).
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Physical Placement of the Magnet
The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in the drawing below:
Figure 64:
Defined Chip Center and Magnet Displacement Radius
1
3.2mm
3.2mm
2.3975 +/-0.055mm
2.3975 +/-0.055mm
Defined center
R d
Area of recommended maximum magnet misalignment
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Magnet Placement
The magnet’s center axis should be aligned within a displacement radius R d
of 0.25mm from the defined center of the IC.
The magnet may be placed below or above the device. The distance should be chosen such that the magnetic field on the die surface is within the specified limits. The typical distance
“z” between the magnet and the package surface is 0.5mm to
1.5mm, provided the use of the recommended magnet material and dimensions (6mm x 3mm). Larger distances are possible, as long as the required magnetic field strength stays within the defined limits.
However, a magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by MagRngn (pin 1).
Figure 65:
Vertical Placement of the Magnet
N
Die surface
S
Package surface z
0. 23 +/- 0.1mm
0. 77 +/- 0.15mm
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AS5030 −
Pack age Drawings & Mark ings
Package Drawings & Markings
Figure 66:
16-Pin TSSOP Package
The device is available in a 16-Pin TSSOP package.
YYWWMZZ
AS5030
Symbol Min Nom Max
c
D
E
E1
A
A1
A2 b e
L
L1
-
0.05
0.80
0.19
-
-
1.00
-
1.20
0.15
1.05
0.30
0.09
4.90
-
5.00
0.20
5.10
6.40 BSC -
4.30
4.40
4.50
0.65 BSC -
0.45
0.60
0.75
1.00 REF -
R
R1
S
Q
1
Θ
2
Θ
3 aaa bbb ccc ddd
N
Symbol Min Nom Max
-
-
-
-
0.09
0.09
0.20
0º
-
-
-
-
-
12 REF
12 REF
0.10
0.10
0.05
0.20
16
-
-
-
-
-
-
-
8º
-
-
Note(s):
1. Dimensioning & tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
RoHS
Green
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ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
Package Drawings & Markings
Figure 67:
Package Code: YYWWMZZ
YY WW M ZZ
Last two digits of the year Manufacturing week Assembly plant identifier Assembly traceability code
JEDEC Package Outline Standard: MO - 153 AB
Thermal Resistance R th(j-a)
: 89 K/W in still air, soldered on PCB
Recommended PCB Footprint
Figure 68:
PCB Footprint
Recommended Footprint Data
Symbol mm inch
C
D
A
B
E
7.26
4.93
0.36
0.65
4.91
0.286
0.194
0.014
0.0256
0.193
ams Datasheet
[v3-00] 2018-Mar-08
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AS5030 −
Ordering & Contac t Information
Ordering & Contact Information
The devices are available as the standard products shown in
Figure 69:
Ordering Information
Ordering Code
AS5030-ATST
Package
16-Pin TSSOP
Marking
AS5030
Delivery Form Delivery Quantity
Tape & Reel 500 pcs/reel
Buy our products or get free samples online at: www.ams.com/ICdirect
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
ams Datasheet
[v3-00] 2018-Mar-08
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Copyrights & Disclaimer
AS5030 −
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
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ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
ams Datasheet
[v3-00] 2018-Mar-08
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AS5030 −
Revision Information
Revision Information
Changes from 2.4 to current revision 3-00 (2018-Mar-08)
Content was updated to latest
ams
design
Added benefits to Key Features
Updated Figure 69
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
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ams Datasheet
[v3-00] 2018-Mar-08
AS5030 −
Content Guide
Content Guide
ams Datasheet
[v3-00] 2018-Mar-08
1 General Description
4 Pin Assignments
6 Absolute Maximum Ratings
7 Electrical Characteristics
11 DC Characteristics of Digital Inputs and Outputs
15 Detailed Description
15 Serial 3-Wire R/W Connection
16 Serial 3-Wire Read-Only Connection
18 Serial 2-Wire Connection (R/W Mode)
19 Serial 2-Wire Continuous Readout
20 Serial 2-Wire Differential SSI Connection
24 Analog Sin/Cos Outputs with External Interpolator
29 Application Information
30 OTP Programming Options
31 Reduced Power Mode Programming Options
31 AS5030 Read / Write Commands
31 16-Bit Read Command
32 16-Bit Write Command
32 18-Bit OTP Read Commands
33 18-Bit OTP Write Commands
35 Programming in Daisy Chain Mode
37 C2 Status Bit
37 Lock Status Bit
37 Magnetic Field Strength Indicators
39 “Push-Button” Feature
40 Propagation Delay
41 Total Propagation Delay of the AS5030
43 Low Power Mode and Ultra-Low Power Mode
46 Power Cycling Mode
48 Accuracy of the Encoder System
48 Quantization Error
50 Vertical Distance of the Magnet
53 Magnet Placement
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AS5030 −
Content Guide
55 Lateral Displacement of the Magnet
57 Magnet Size
58 Physical Placement of the Magnet
60 Package Drawings & Markings
62 Ordering & Contact Information
63 RoHS Compliant & ams Green Statement
64 Copyrights & Disclaimer
65 Document Status
66 Revision Information
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ams Datasheet
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Key features
360° contactless angular position encoding
Multiple data output formats (serial interface, pulse width modulated (PWM) output)
User programmable zero position
Serial read-out of multiple interconnected AS5030 devices using daisy chain mode
Wide magnetic field input range: 20mT ~ 80mT
Wide temperature range: -40°C to 125°C
Small Pb-free package: TSSOP 16
Frequently asked questions
The AS5030 provides multiple data output formats: serial interface, pulse width modulated (PWM) output
The magnetic field input range is 20mT to 80mT
The operating temperature range is -40°C to 125°C
TSSOP 16
Yes, multiple interconnected AS5030 devices can be read out using daisy chain mode
Yes
No, as it is a complete system-on-chip
