The AMS AS5048A is a magnetic rotary encoder that provides 14-bit high-resolution angle measurement over a full 360-degree range. It features a user-programmable zero position, making it easy to integrate into existing systems. The AS5048A is suitable for various applications, including robotic joint position detection, industrial motor position control, and medical robots and fitness equipment.
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Figure 1:
Added Value of Using AS5048
Benefits
•
No external programmer needed
•
High precision
•
Easy to use
•
Low material costs (no shielding)
AS5048A/AS5048B
The AS5048 is an easy to use 360° angle position sensor with a
14-bit high resolution output.
The IC measures the absolute position of the magnet’s rotation angle and consists of Hall sensors, analog digital converter and digital signal processing. The absolute position information of the magnet is directly accessible over a PWM output and can be read out over a standard SPI or a high speed I²C interface.
AS5048A has a SPI interface, AS5048B I²C interface. Both devices offer a PWM output.
The zero position can be programmed via SPI or I²C command.
This simplifies the assembly of the complete system because the zero position of the magnet does not need to be mechanically aligned. The sensor tolerates misalignment, air gap variations, temperature variations and as well external magnetic fields. This robustness and wide temperature range
(-40°C up to 150°C) of the AS5048 makes the IC ideal for rotation angle sensing in harsh industrial and medical environments.
Several AS5048 ICs can be connected in daisy chain for serial data read out. An internal voltage regulator allows the AS5048 to operate at either 3.3V or 5V supplies.
and
Content Guide appear at end of
datasheet.
The benefits and features of AS5048A/AS5048B, Magnetic
Rotary Encoder (14-Bit Angular Position Sensor) are listed below:
Features
•
Standard SPI or I
2
C interface and PWM
•
14-bit resolution (0.0219°/LSB)
•
Zero position programmable via SPI or I
2
C
•
Immune to external magnetic stray fields
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
General Description
•
Contactless rotary position sensor over 360°
•
Temperature range: -40°C to 150°C
•
3.3V / 5V compliant
•
Package: 14-pin TSSOP (5 x 6.4mm)
The applications of AS5048 include:
•
Robotic joint position detection
•
Industrial motor position control
•
Medical robots and fitness equipment
The functional blocks of this device are shown below:
Figure 2:
AS5048A Block Diagram
VDD3V
VDD5V
LDO
Register
Setting
OTP
AFE
14-bit A/D
14-bit A/D
ATAN
(CORDIC)
AGC
GND
SPI
PWM
AS5048A
SCK
MISO
MOSI
CSn
PWM
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AS5048A/AS5048B −
General Description
Figure 3:
AS5048B Block Diagram
VDD3V
LDO
AFE
VDD5V
AGC
Register
Setting
OTP
ATAN
(CORDIC)
I2C
PWM
AS5048B
SCL
SDA
A1
A2
PWM
GND
ams Datasheet
[v1-11] 2018-Jan-29
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Figure 4:
TSSOP14 Pin Configurations
CSn
CLK
MISO
MOSI
TEST
TEST
TEST
1
2
3
4
5
6
7
12
11
10
9
8
14
13
PWM
GND
VDD3V
VDD5V
TEST
TEST
TEST
AS5048A/AS5048B −
Pin Assignments
The AS5048A/AS5048B pin assignments are described below.
SDA
SCL
A2
A1
TEST
TEST
TEST
1
2
3
4
5
6
7
12
11
10
9
8
14
13
PWM
GND
VDD3V
VDD5V
TEST
TEST
TEST
Figure 5:
TSSOP14 Pin Descriptions for AS5048A
9
10
11
7
8
5
6
Pin AS5048A
1
2
CSn
CLK
3
4
MISO
MOSI
Pin Type Description
Digital input with Schmitt trigger
SPI chip select - active low
SPI clock input
Digital I/O with Schmitt trigger in the input path
Digital input with Schmitt trigger
Analog I/O
SPI master in/slave out
SPI master out/slave in
Test pin should be connected to GND.
TEST
TEST
TEST
TEST
TEST
TEST
VDD5V
Analog I/O
Test pins should be left open during normal operation.
12
13
14
VDD3V
GND
PWM
Supply pad
Digital output – push-pull
Positive Supply Voltage, 3.0 to 5.5 V
3.3V Regulator output; internally regulated from VDD.
Connect to VDD for 3V supply voltage.
10μF capacitor to GND required in 5V operation mode
Negative Supply Voltage (GND)
Pulse Width Modulation output
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AS5048A/AS5048B −
Pin Assignments
Figure 6:
TSSOP14 Pin Description for AS5048B
8
9
6
7
10
11
4
5
2
3
Pin AS5048B
1 SDA
Type
Digital I/O with open drain output
TEST
TEST
TEST
TEST
SCL
A2
A1
TEST
TEST
VDD5V
Digital input with Schmitt trigger
Analog I/O
Analog I/O
12
13
14
VDD3V
GND
PWM
Supply pad
Digital output – push-pull
Description
Data pin I²C interface
I²C clock input
I²C address selection pin 3
I²C address selection pin 4
Test pin should be connected to GND.
Test pins should be left open during normal operation.
Positive Supply Voltage, 3.0 to 5.5 V
3.3V Regulator output; internally regulated from VDD.
Connect to VDD for 3V supply voltage.
10μF capacitor to GND required in 5V operation mode
Negative Supply Voltage (GND)
Pulse Width Modulation output
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AS5048A/AS5048B −
Absolute Maximum Ratings
Stresses beyond those listed under
may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 7:
Absolute Maximum Ratings
Symbol
VDD5V
VDD3V
GND
V
IN
I
SCR
Parameter Min Max
DC supply voltage at VDD pin
Electrical Parameters
-0.3
7
DC voltage at VDD3V pin
DC voltage at GND pin
-0.3
-0.3
5
0.3
Input pin voltage VDD+0.3
ESD
P
T
T
STRG
T
BODY
RH
NC
MSL
Unit
V
V
V
V
Note
Input current (latchup immunity) -100 100 mA Jedec 78
Electrostatic discharge
Electrostatic Discharge
± 2
Power Dissipation
kV
Total power dissipation
(all supplies and outputs)
150 mW
Temperature Ranges and Storage Conditions
MIL 883 E method 3015
Storage temperature -55 150 °C
Package body temperature 260 °C
The reflow peak soldering temperature (body temperature) specified is in accordance with IPC/JEDEC
J-STD-020 “Moisture Solid
State Surface Mount Devices”.
The lead finish from Pb-free leaded packages is matte tin
(100%Sn)
Relative humidity non-condensing
5 85 %
Moisture sensitivity level 3
Represents a maximum floor life time of 168h
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AS5048A/AS5048B −
Electrical Characteristics
All in this specification defined tolerances for external components need to be assured over the whole operation conditions range and also over lifetime.
Figure 8:
Operating Conditions
Symbol Parameter
VDD5V
VDD3V
Positive supply voltage
VDDCORE Positive core supply voltage
T
AMB
I
SUP
Ambient temperature
Supply current
Min
4.5
3
3
-40
Max
5.5
3.6
3.6
150
15
V
V
V
Unit Note
5V Operation via LDO
LDO output voltage
°C
Only for 5V operation.
T_amb_max for 3V is 125°C mA
Figure 9:
DC/AC Characteristics
Symbol
V
IH
V
IL l
LEAK
V
OH
V
OL
C
L
I
OUT
Parameter Min Max
CMOS Digital Input with Schmitt Trigger: CSn, CLK, MOSI and SCL, A1, A2
High level input voltage 0.7 * VDDCORE
Low level input voltage 0.3 * VDDCORE
1 Input leakage current
CMOS Output: PWM, MISO, SDA
High level output voltage VDDCORE - 0.5
Low level output voltage
Capacitive load
Output current
GND+0.4
50
4
Unit
V
V
μA pF mA
V
V
ams Datasheet
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AS5048A/AS5048B −
Electrical Characteristics
VDD5V = 5V, T
AMB
= -40 to 150°C unless noted otherwise.
Figure 10:
System Specification
Symbol
Bz f sample
RES
Noise t prop f
PWM
INL
OPT
@25ºC
INL
OPT+TEMP
INL
DIS+TEMP t startup
Parameter Conditions Min
Magnetic input field
Output sampling rate
Output resolution
Sensor output noise
System propagation delay
PWM frequency
Non-linearity, optimum placement of the magnet
Non-linearity optimum placement of the magnet over the full temperature range
Non-linearity @ displacement of magnet and temperature -40ºC to
150ºC
Startup time
2.73LSB@14bit, rms value
Assuming N35H magnet
(D=8mm, H=3mm) 500μm displacement in x and y z-distance @ 2000μm
30
10.2
90.7
0.907
Typ Max Unit
50
11.25
14
70
12.4
100
1
0.06
110.2
1.102
mT kHz
Bit deg
μs kHz
± 0.8
±1
±1.2
10 deg deg deg ms
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AS5048A/AS5048B −
Functional Description
The AS5048 is a magnetic Hall sensor system manufactured in a CMOS process. A lateral Hall sensor array is used to measure the magnetic field components perpendicular to the surface of the chip. The AS5048 is uses self-calibration methods to eliminate signal offset and sensitivity drifts.
The integrated Hall sensors are placed around the center of the device and deliver a voltage representation of the magnetic flux Bz.
Through Sigma-Delta Analog-to-Digital Converter (ADC) and
Digital Signal-Processing (DSP) algorithms, the AS5048 provides accurate high-resolution absolute angular position information. This is executed by a Coordinate Rotation Digital
Computer (CORDIC) which calculates the angle and the magnitude of the Hall array signals.
The DSP is also used to provide digital information at the outputs that indicate movements of the magnet towards or away from the device’s surface, in the z-axis.
A small diametrically magnetized (two-pole) standard magnet provides the angular position information. Depending on the system requirements different magnet diameters are possible.
Additional flexibility is given by the wide range of the magnetic input range. The AS5048 can be combined with NeFeB, SmCo and alternative magnet materials e.g. hard ferrites. The AS5048 provides a 14-bit binary code representing the angular position of the magnet. The type of output is pre-programmed as SPI version A or I²C version B. Simultaneously a PWM output signal is available in 12 bit format.
A simple programming of the zero position is possible over the interface. No additional programmer is needed. The AS5048 uses one time programmable (OTP) fuses for permanent programming of the user settings. The verification is possible over a simple digital readout of the OTP content.
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AS5048A/AS5048B −
Operation
The AS5048 operates at 5V ±10%, using an internal
Low-Dropout (LDO) voltage regulator. In addition a 3.3V operation is possible. The
VDD3V
output is intended for internal use only.
It must not be loaded with an external load.
Figure 11:
Connections for 5V and 3.3V Supply Voltages
5V Operation
100nF
VDD5V
4.5 - 5.5V
GND
3.3V Operation
LDO
VDD3V
10µF
100nF
10µF
VDD5V
Internal
VDD3.3V
VDD3V
LDO
Internal
VDD3.3V
3.0 - 3.6V
GND
Note(s):
1. The pin
VDD3V
must always be buffered by a 10 μF capacitor in 5V operation. It must not be left floating, as this may cause unstable internal supply voltages which may lead to larger output jitter of the measured angle.
In 3V operation the
VDD3V
must be shorted to
VDD5V.
The ambient temperature T
AMB
is limited to 125°C in this mode.
The 16 bit SPI Interface enables read / write access to the register blocks and is compatible to a standard micro controller interface. The SPI is active as soon as
CSn
is pulled low. The
AS5048A then reads the digital value on the
MOSI
(master out slave in) input with every falling edge of
CLK
and writes on its
MISO
(master in slave out) output with the rising edge. After 16 clock cycles
CSn
has to be set back to a high status in order to reset some parts of the interface core.
The AS5048A only supports slave operation mode. Therefore
CLK
for the communication as well as the
CSn
signal has to be provided by the test equipment. The following picture shows a basic interconnection diagram with one master and an
AS5048A device and a principle schematic of the interface core.
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AS5048A/AS5048B −
Operation
Figure 12:
SPI Connection AS5048A with μC
SPI_CLK
SPI_SS
N
MOSI
(Tester)
MISO
CLK
CSn
MOSI
MISO
RXSR
TXSR
Interface Core
RXSPI
TXSPI
Because the interface has to decode the sent command before it can react and provide data the response of the chip to a specific command applied at a time T can be accessed in the next transmission cycle ending at T + TCOM. The data are sent and read with
MSB first
. Every time the chip is accessed it is sending and receiving data.
Figure 13:
SPI Command/Response Data Flow
MOSI
MSB
Command 1
LSB MSB
Command 2
LSB
T
COM
MSB
Command 3
LSB MSB
Command N
LSB
MISO
NOP
MSB LSB
Transmission 1
MSB
Response 1
LSB
Transmission 2
MSB
Response 2
LSB
Transmission 3
MSB
Response N-1
LSB
Transmission N ams Datasheet
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AS5048A/AS5048B −
Operation
Figure 14:
SPI Timing Diagram
CSn
(Input)
CLK
(Input)
MISO
(Output)
MOSI
(Input) t
L t clk t clkL t clkH t
MISO data[15] t
MOSI data[15] data[14] data[14] t
CSn t
H data[0] t
OZ t
OZ data[0]
Figure 15:
SPI Timing Characteristics
Parameter
t
H
T
CSnH t
MOSI t
MISO t
L
T
CLK t
CLKL t
CLKH
Description
Time between CSn falling edge and CLK rising edge
Serial clock period
Low period of serial clock
High period of serial clock
Time between last falling edge of CLK and rising edge of CSn
High time of CSn between two transmissions
Data input valid to clock edge
CLK edge to data output valid
Min
350
100
50
50
50
350
20
Max Unit
20 ns ns ns ns ns ns ns ns
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AS5048A/AS5048B −
Operation
Figure 16:
Single Slave Mode
µC
MOSI
MISO
SCK
SS/
MOSI
MISO
SCK
AS5048A
SS/
µC
MOSI
MISO
SCK
SS/
1
MOSI
MISO
AS5048A
SCK
SS/
MOSI
0xFFFF
Read angle 1
0xFFFF
Read angle 2
0xFFFF
Read angle 3
0xFFFF
Read angle 4
MISO
Angle 1 Angle 2 Angle 3
SS/
Angle 1 Angle 2 Angle 3
MISO
SS/
Single Slave Mode:
This figure shows the SPI connection to the host μC using Single Slave Mode.
Figure 17:
Multiple Slave, n+3 Wire (Separate ChipSelect)
µC
MOSI
MISO
SCK
SS1/
SS2/
SS3/
MOSI
MISO
AS5048A
SCK
1
SS/
MOSI
MISO
AS5048A
SCK
2
SS/
MOSI
SW Reset
0xFFFF
Read angle 1
MISO
SS1/
SS2/
SS3/
Angle 1
0xFFFF
Read angle 2
Angle 2
0xFFFF
Read angle 3
Angle 3
MOSI
MISO
AS5048A
SCK
3
SS/
Multiple Slave, n+3 Wire (Separate ChipSelect):
This figure shows the SPI connection to the host μC using 3
Wire mode.
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AS5048A/AS5048B −
Operation
Figure 18:
Daisy Chain, 4 Wire
µC
MOSI
MISO
SCK
SS/
MOSI
MISO
SCK
SS/
AS5048A
1
MOSI
MISO
SCK
AS5048A
2
SS/
MOSI
SW Reset
MISO
SS/
SW Reset SW Reset
MOSI
0xFFFF
Read Angle 3
MISO
0xFFFF
Read angle 2
0xFFFF
Read Angle 1
0xFFFF
Read angle 3
Angle 3
SS/
0xFFFF
Read angle 2
Angle 2
0xFFFF
Read angle 1
Angle 1
MOSI
MISO
SCK
AS5048A
3
SS/
Daisy Chain, 4 Wire:
This figure shows the SPI connection to the host μC using Daisy Chain, 4 wire mode.
Every command sent to the AS5048A is represented with the following layout.
Figure 19:
SPI Command Package
Command Package
Bit MSB 14
PAR RWn
PAR
RWn
Address
13 12 11 10 9 8 7 6
Address<13:0>
5
Bit Definition & Description
Parity bit (EVEN)
Indicates read(1) or write(0) command
14 bit address code
4 3 2 1 LSB
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AS5048A/AS5048B −
Operation
The read frame always contains two alarm bits, the parity and error flags and the addressed data of the previous read command.
Figure 20:
SPI Read Package
Read Package
Bit MSB 14 13 12 11 10
PAR EF
9 8 7 6
Data<13:0>
Bit Definition & Description
5
PAR
EF
Data
Parity bit (EVEN)
4 3
Error flag indicating a transmission error in a previous host transmission
14 bit addressed data
2 1 LSB
The write frame is compatible to the read frame and contains two additional bits, parity flag and R flag.
If the previous command was a write command a second package has to be transmitted.
Figure 21:
SPI Write Data Package
Data Package
Bit MSB 14 13 12 11 10
PAR R
9 8 7 6
Data <13:0>
Bit Definition & Description
5
PAR
R
Data
Parity bit (EVEN)
Has to be 0
14 bit data to write to former selected address
4 3 2 1 LSB ams Datasheet
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AS5048A/AS5048B −
Register Description
Figure 22:
SPI Register Map
Address hex
x0000 x0001 x0003
Name
NOP
Clear Error
Flag
Programming
Control
Access
Type
Bit Symbol
R
R
R/W
3
2
1
5
4
7
6
Control and Error Registers
13
NOP :
0
3
2
13
: Not used
1
0
13
:
Parity Error
Command Invalid
Framing Error
Not used
Verify
Not used
Burn
Reserved
0
Programming
Enable
Default
0 n.a.
0
0
Description
No operation dummy information
Error register. All errors are cleared by access
Programming control register.
Programming must be enabled before burning the fuse(s). After programming is a verification mandatory.
See programming procedure.
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AS5048A/AS5048B −
Register Description
Address hex
x0016 x0017 x3FFD
Name
Access
Type
Bit Symbol Default
OTP Register
Zero Position
Hi
OTP Register
Zero Position
Low 6 LSBs
Diagnostics +
Automatic
Gain Control
(AGC)
R/W
+
Programmable Customer Settings
13
Not used :
8
Program
7
:
Zero Position <13>
:
Zero Position <6>
R/W
+
Program
:
6
0
13
Not used
5
:
Zero Position <5>
:
0 Zero Position <0>
Readout Registers
R
7
:
9
8
13
12
11
10
Not used
Comp High
Comp Low
COF
OCF
AGC value<7>
:
0
0 n.a.
0
:
0
0
:
0
0
1
0
0
1
:
0 AGC value<0> 0
Description
Zero Position value high byte
Zero Position remaining
6 lower LSB's
Diagnostics flags
Automatic Gain Control value.
0 decimal represents high magnetic field, 255 decimal represents low magnetic field x3FFE x3FFF
Magnitude R
Angle R
13
:
0
13
:
0
Magnitude<13>
:
Magnitude<0>
Angle <13>
:
Angle<0>
0
0
0
:
:
0
Magnitude output value of the CORDIC
Angle output value including zero position correction
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AS5048A/AS5048B −
SPI Inter face Commands
For a single
READ
command two transmission sequences are necessary. The first package written to the AS5048 contains the
READ
command
(MSB-1 high)
and the address the chip has to access, the second package transmitted to the AS5048 device can be
any command
the chip has to process next. The content of the desired register is available in the
MISO
register of the
master device
at the end of the second transmission cycle.
Figure 23:
READ Command
MOSI
MSB
READ
LSB
T
COM
MSB
Next command
LSB
MISO
MSB
Response -1
LSB
Transmission N
Response on
READ command
MSB LSB
Transmission N+1
A single
WRITE
command takes two transmission cycles. With a
NOP command after the WRITE command you can verify the sent data with three transmission cycles because the data will be send back during the following command.
Figure 24:
WRITE Command
MOSI
MSB
WRITE command
LSB
MISO
MSB
Response-1
LSB
Transmission N
MSB
T
COM
DATA
LSB
MSB
Old register content
LSB
Transmission N+1
MSB
NOP
LSB
MSB
New register content
LSB
Transmission N+2
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AS5048A/AS5048B −
SPI Interface Commands
The
CLEAR ERROR FLAG
command is implemented as
READ
command. This command clears the
ERROR FLAG
which is contained in every
READ
frame. Before the
ERROR FLAG
is cleared the error register content comes back with the information which error type was occurred. On the next new
READ
register the
ERROR FLAG
is cleared.
Figure 25:
CLEAR ERROR FLAG Command
MOSI
MSB
CLEAR ERROR
FLAG
LSB
MISO
MSB
Response-1
EF
LSB
Transmission N
T
COM
MSB
Next command
LSB
MSB
Error register
Content + EF
LSB
Transmission N+1
Next command
MSB
New register
EF cleared
LSB
Transmission N+2
The package necessary to perform a
CLEAR ERROR FLAG
is built up as follows.
Figure 26:
Clear Error Flag Command
CLEAR ERROR FLAG Command
Bit MSB 14 13 12 11 10
PAR 1 0 0 0 0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LSB
1
Possible conditions which force the ERROR FLAG to be set:
•
Wrong parity
•
Wrong number of clocks (no full transmission cycle or too many clocks)
•
Invalid command
•
Frame error
Note(s):
If the error flag is set to high because of a communication problem the flag remains set until it will be cleared by the
CLERAR ERROR FLAG
command.
ams Datasheet
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AS5048A/AS5048B −
SPI Inter face Commands
The
NOP
command represents a dummy write to the AS5048.
Figure 27:
NOP Command
MSB
NOP
LSB MSB
T
COM
NOP
LSB MSB
Next command
LSB
MSB
Response-1
LSB
0x0000
MSB LSB
0x0000
MSB LSB
The NOP command frame looks like follows.
Figure 28:
NOP Command
Bit MSB 14 13 12 11 10
0 0 0 0 0 0
NOP Command
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
LSB
0
The chip’s response on this command is 0x0000
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AS5048A/AS5048B −
I²C Interface
The AS5048B supports 2-wire high-speed I²C protocol in device mode. The host MCU (master) has to initiate the data transfers.
The 7-bit device address of the slave depends on the state of the OTP I²C register 21 (0x15) bit 0… 4 + 2 I²C address selection pin 3 and 4.
Supported modes:
•
Random/Sequential Read
•
Byte/Page Write
•
Standard : 0 to 100kHz clock frequency (slave mode)
•
Fast Mode : 0 to 400kHz clock frequency (slave mode)
•
High Speed: 0 to 3.4MHz clock frequency (slave mode)
The SDA signal is bidirectional and is used to read and write the serial data. The SCL signal is the clock generated by the host
MCU, to synchronize the SDA data in read and write mode. The maximum I²C clock frequency is 3.4MHz, data are triggered on the rising edge of SCL.
Figure 29:
I²C Electrical Specification
Symbol
V
IL
V
IH
V hys
V
OL
I
OL
I
CS t
SP
Parameter Condition
FS-mode+
HS-mode
C
B
=100pF
HS-mode
C
B
=400pF
Min Max Min Max Min Max
LOW-Level Input
Voltage
HIGH-Level Input
Voltage
-0.5
0.3V
DDC
ORE
-0.5
0.3V
DDC
ORE
-0.5
0.3V
DDC
ORE
0.7V
DD
CORE
V
DDCORE
+ 0.5
0.7V
DD
CORE
V
DDCORE
+ 0.5
0.7V
DD
CORE
V
DDCORE
+ 0.5
Hysteresis of Schmitt
Trigger Inputs
V
DDCORE
< 2V
0.1V
DD
CORE
--
0.1V
DD
CORE
--
0.1V
DD
CORE
--
LOW-Level Output
Voltage (open-drain or open-collector) at
3mA Sink Current
V
DDCORE
< 2V
LOW-Level Output
Current
Pull-up current of
SCLH current source
Pulse Width of Spikes that must be suppressed by the
Input Filter
V
OL
= 0.4V
--
20
--
--
0.2V
DDC
ORE
--
--
--
3
--
0.2V
DDC
ORE
--
12
10
--
--
3
--
0.2V
DDC
ORE
--
12
10
Unit
V
V
V
V mA mA ns
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
I²C Inter face
Symbol
I i
Parameter
Input Current at each
I/O Pin
Condition
FS-mode+
HS-mode
C
B
=100pF
HS-mode
C
B
=400pF
Min Max Min Max Min Max
Input
Voltage between
-10
-10 -10
C
B
C
I/O
Total Capacitive Load for each Bus Line
I/O Capacitance
(SDA,SCL)
--
--
550
10
--
--
100
10
--
--
400
10
Unit
μA pF pF
Note(s):
1. Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
2. I/O pins of Fast-mode and Fast-mode Plus devices must not obstruct the SDA and SCL lines if VDD is switched OFF.
Figure 30:
I²C Timing
Symbol Parameter
f t
SCLK
BUF t
HD;STA t t t
LOW
HIGH
SU;STA t
HD;DAT t
SU;DAT t
R
SCL clock
Frequency
Bus Free Time; time between STOP and
START Condition
Hold Time;
(Repeated) START
LOW Period of SCL
Clock
HIGH Period of SCL
Clock
Setup Time for a
Repeated START condition
Data Hold Time
Rise Time of SDA and SCL Signals
Condition
FS-mode
Min
HS-mode
C
B
=100pF C
B
HS-mode
=400pF (5)
Unit
Max Min Max Min Max
-400 -3400 -1700 kHz
500
260
500
260
260
--
--
--
--
--
0 450
50 --
20+0.1C
b
120
500
160
160
60
160
0
10
--
--
--
--
--
--
70
--
--
500
160
320
120
160
0
10
--
--
--
--
--
-ns ns ns ns ns
150
-ns ns
-ns
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ams Datasheet
[v1-11] 2018-Jan-29
AS5048A/AS5048B −
I²C Interface
Symbol
t
F t rCL t rCL1 t fCL t rDA t fDA t
SU;STO
V nL
V nH
Parameter Condition
FS-mode
Min
HS-mode
C
B
=100pF
HS-mode
C
B
=400pF (5)
Unit
Max Min Max Min Max
Fall time of SDA and
SCL signals
Rise time of SCLH signal
Ext. pull-up source of
3mA
Rise time of SCLH signal after repeated START condition and after an acknowledge bit
Ext. pull-up source of
3mA
20+0.1C
b
120
--
--
--
--
Output rise time of
SCLH signal
Ext. pull-up source of
3mA
Output rise time of
SDAH signal
Output rise time of
SDAH signal
Setup Time for
STOP Condition
Noise margin at
LOW level
Noise margin at
HIGH level
--
--
--
260
0.1V
0.2V
DDp
DDp
--
--
--
--
--
--
--
10
10
10
10
10
160
0.1V
DDp
0.2V
DDp
--
40
80
40
80
80
--
--
--
--
20
20
20
20
20
160
0.1V
DDp
0.2V
DDp
--
80
160
80
160
160
--
--
-ns ns ns ns ns ns ns
V
V
Note(s):
1. After this time the first clock is generated.
2. A device must internally provide a minimum hold time (120ns / max 250ns for Fast-mode Plus, 80ns / max 150ns for High-speed mode) for the SDA signal (referred to the V
IHmin
of the SCL) to bridge the undefined region of the falling edge of SCL.
3. A fast-mode device can be used in standard-mode system, but the requirement t
SU;DAT
= 250ns must then e met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
Rmax
+ T
SU;DAT
= 1000 + 250 = 1250ns before the SCL line is released.
4. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used this has to be considered for bus timing.
5. For capacitive bus loads between 100pF and 400pF, the timing parameters must be linearly interpolated
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
I²C Inter face
The following registers / functions are accessible over the serial
I²C interface.
Figure 31:
Register Map I²C
Address hex
x03 x15 x16 x17
Name
Access
Type
Bit Symbol Default Description
Programming
Control
I²C slave address
OTP Register
Zero Position
Hi
OTP Register
Zero Position
Low 6 LSBs
R/W
2
1
4
3
6
5
7
Control OTP
Not used
Verify
Not used
Burn
Reserved
0
Programming control register. Programming must be enabled before burning the fuse(s). After programming is an verification mandatory.
See programming procedure.
R/W
0
Programmable Customer Settings
7
:
5
4
Programming
Enable
Not used
I²C address<4> n.a.
internally inverted
I²C slave address slave address consist of 5 bits
(MSBs) and the hardware setting of Pins A1 and A2
I²C address <4> is the inversion defined as '1'
: :
0
:
I²C address<0> 0
0
R/W
+
Program
7
:
Zero Position <13>
:
Zero Position <6>
:
0
Zero Position value high byte
0
7
Not used n.a.
R/W
+
Program
6
5 Zero Position <5>
:
0
:
Zero Position remaining
6 lower LSB's
:
0 Zero Position <0> 0
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ams Datasheet
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AS5048A/AS5048B −
I²C Interface
Address hex
xFA
Name
Automatic
Gain
Control
Access
Type
Bit
7
Readout Registers
AGC value<7>
: :
R
Symbol
0 AGC value<0> xFB xFC xFD xFE xFF
Diagnostics
Magnitude
Angle
R
R
R
R
R
0
7
5
:
7
6
:
0
0
7
2
1
4
3
7
:
5
:
0
7
6
:
0
Not used
Comp High
Comp Low
COF
OCF
Magnitude<13>
:
Magnitude<6>
Not used
Magnitude<5>
:
Magnitude<0>
Angle<13>
:
Angle<6>
Not used
Angle<5>
:
Angle<0>
Default
n.a.
n.a.
n.a.
0
:
0
0
:
0
0
1
0
0
0
0
0
:
:
0
1
:
0
Description
Automatic Gain Control value.
0 decimal represents high magnetic field 255 decimal represents low magnetic field
Diagnostic flags
Magnitude output value of the CORDIC
Angle output value including zero position correction
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
I²C Inter face
Figure 32:
Slave Address Construction
random read
OTP cotent
(Default)
1 0 0 0 0
A
2
HW
Pins
A
1
Slave Address
X X X X X X X X
Register Address
1 0 0 0 0
A
2
HW
Pins
A
1
Slave Address
X X X X X X X X
Data Byte (n) random write
OTP cotent
(Default)
1 0 0 0 0
A
2
HW
Pins
A
1
Slave Address
X X X X X X X X
Register Address
X X X X X X X X
Data Byte (n)
Note(s):
1. It's important to use a STOP condition only after a complete read or write sequence.
The slave address consists of the hardware setting on pins A1,
A2. The MSB of the slave address (yellow) is internally inverted.
This means that by default the resulting data is ‘1’. A read of the
I²C slave address register 21 will return a ‘0’ at the MSB.
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ams Datasheet
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AS5048A/AS5048B −
PWM Interface
The AS5048 provides a pulse width modulated output (PWM), whose duty cycle is proportional to the measured angle. The
PWM frequency is internally trimmed to an accuracy of ±10% over full temperature range. This tolerance can be cancelled by measuring the complete duty cycle.
The PWM signal consists of different sections:
•
Init:
12 clocks
→
PWM = ‘high’
•
Error_n:
4 clocks
→
PWM = ‘not(system_error)’
•
Data:
4095 clocks
→
PWM = ‘angle_zero’ / ‘low’
(in case of error)
•
Exit:
8 clocks
→
PWM = ‘low’
In case of an error the data section is set to zero.
Figure 33:
PWM Format
Init
Zero degree
16 clocks
Error_n
Figure 34:
PWM Period and Resolution
Parameter
PWM Frequency
PWM Pulse period
Symbol
F_PWM
T_PWM
Data
4095 clocks
Value
1
4119
Exit
8 clocks
Unit
KHz bit
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
Application Information
Programming of the Zero Position
: The absolute angle position can be permanent programmed over the interface.
This could be useful for random placement of the magnet on the rotation axis. A readout at the mechanical zero position can be performed and written back into the IC. With permanent programming the position is non-reversible stored in the IC.
This programming can be performed only once.
To simplify the calculation of the zero position it is only needed to write the value in the IC which was read out before from the angle register.
Programming Sequence with Verification:
To program the zero position is needed to perform following sequence:
1.
Write 0 into OTP zero position register to clear
2.
Read angle information
3.
Write previous read angle position into OTP zero position register
Now the zero position is set.
If you want to burn it to the OTP register send:
4.
Set the Programming Enable bit in the OTP control register
5.
Set the Burn bit to start the automatic programming procedure
6.
Read angle information (equals to 0)
7.
Set the Verify bit to load the OTP data again into the internal registers
8.
Read angle information (equals to 0)
The programming can either be performed in 5V operation using the internal LDO, or in 3V operation but using a minimum supply voltage of 3.3V. In case of 3V operation, also a 10μF capacitor is required on the VDD3 pin.
Programming the I²C Slave address:
For informations of programming the I²C Slave address please refer to our application note covering this topic.
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ams Datasheet
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AS5048A/AS5048B −
Application Information
The AS5048 provides diagnostics functions of the IC and also diagnostic functions of the magnetic input field
Following diagnostic flags are available:
See
register address x3FFD (AS5048A) or
register address 251 dec (AS5048B)
• OCF
(
O
ffset
C
ompensation
F
inished), logic high indicates the finished Offset Compensation Algorithm. After power up the flag remains always to logic high.
• COF
(
C
ORDIC
O
ver
f
low), logic high indicates an out of range error in the CORDIC part. When this bit is set, the angle and magnitude data is invalid. The absolute output maintains the last valid angular value.
• COMP low
, indicates a high magnetic field. It is recommended to monitor in addition the magnitude value.
• COMP high
, indicated a weak magnetic field. It is recommended to monitor the magnitude value.
ams Datasheet
[v1-11] 2018-Jan-29
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AS5048A/AS5048B −
Application Information
The AS5048 works with a variety of different magnets in size and shape. A typical magnet could be 6-8 mm in diameter and
≥2.5mm in height The magnetic field strength perpendicular to the die surface has to be in the range of ±30mT … ±70mT (peak).
The magnet’s field strength should be verified using a gauss-meter. The magnetic flux B
Z
at a given distance, along a concentric circle with a radius of 1.1mm (R1), should be in the range of ±30mT… ±70mT.
Figure 35:
Typical Magnet and Magnetic Flux Distribution
typ. 6-8mm diameter
Vertical field component
N
R1
S
Magnet axis
Magnet axis
N S
Vertical field component
Bv
(30…70mT)
R1 concentric circle; radius 1.1mm
0
360
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ams Datasheet
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AS5048A/AS5048B −
Application Information
The best linearity can be achieved by placing the center of the magnet exactly over the defined center of the chip as shown in the drawing below:
Figure 36:
Defined Chip Center and Magnet Displacement Radius
3.2 mm 3.2 mm
1
2.5 mm
2.5 mm
Defined center
R d
Area of recommended maximum magnet misalignment
The magnet’s center axis should be aligned within a displacement radius R d
of 0.25 mm (larger magnets allow more displacement e.g. 0.5 mm) from the defined center of the IC.
The magnet may be placed below or above the device. The distance should be chosen such that the magnetic field on the die surface is within the specified limits The typical distance “z” between the magnet and the package surface is 0.5mm to
2.5mm, provided the use of the recommended magnet material and dimensions (6mm x 3mm). Larger distances are possible, as long as the required magnetic field strength stays within the defined limits.
However, a magnetic field outside the specified range may still produce usable results, but the out-of-range condition will be indicated by indication flags.
Figure 37:
Vertical Placement of the Magnet
Die surface
S N
Package surface
ams Datasheet
[v1-11] 2018-Jan-29
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Figure 38:
Hall Element Positions
AS5048A/AS5048B −
Application Information
The internal Hall elements are placed in the center of the package on a circle with a radius of 1.1 mm.
Note(s):
1. All dimensions in mm.
2. Die thickness 203
μ m nom.
3. Adhesive thickness 30 ± 15
μ m.
4. Leadframe downset 152 ± 25
μ m.
5. Leadframe thickness 125 ± 8
μ m.
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ams Datasheet
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AS5048A/AS5048B −
Package Drawings & Markings
Package type: TSSOP14
Figure 39:
Package Markings for AS5048A & AS5048B
Figure 40:
Package Code YYWWMZZ
YY
Last two digits of the manufacturing year
WW M
Manufacturing week Plant identifier
ZZ
Letters for free traceability
ams Datasheet
[v1-11] 2018-Jan-29
Page 33
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Figure 41:
14-Lead Thin Shrink Small Outline Package TSSOP-14
AS5048A/AS5048B −
Package Drawings & Mark ings
RoHS
Symbol Min
E
E1 c
D
A
A1
A2 b e
L
L1
0.09
4.90
-
4.30
-
0.05
0.80
0.19
-
0.45
-
Nom Max
-
-
1.00
-
-
5.00
6.40 BSC
4.40
0.65 BSC
0.60
1.00 REF
0.20
5.10
-
4.50
1.20
0.15
1.05
0.30
-
0.75
bbb ccc ddd
N
R
R1
S
θ1
θ2
θ3 aaa
Symbol Min
-
-
-
-
0.09
0.09
0.20
0º
-
-
12 REF
12 REF
0.10
0.10
-
-
-
-
0.05
0.20
14
Nom Max
-
-
-
-
-
-
-
8º
-
-
Note(s):
1. Dimensioning & toleranceing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
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ams Datasheet
[v1-11] 2018-Jan-29
AS5048A/AS5048B −
Ordering & Contact Information
The devices are available as standard products.
Figure 42:
Ordering Information
Ordering Code Package
AS5048A-HTSP
AS5048B-HTSP
TSSOP 14
TSSOP 14
Description
14 –Bit Programmable Magnetic Rotary Encoder with SPI-Interface
14 –Bit Programmable Magnetic Rotary Encoder with I²C-Interface
Delivery Form
Tape & Reel
Tape & Reel
Buy our products or get free samples online at: www.ams.com/ICdirect
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-11] 2018-Jan-29
Page 35
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AS5048A/AS5048B −
RoHS Compliant & ams Green Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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ams Datasheet
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AS5048A/AS5048B −
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
ams Datasheet
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AS5048A/AS5048B −
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
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ams Datasheet
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AS5048A/AS5048B −
Revision Information
Changes from 1-09 (2016-Nov-15) to current revision 1-11 (2018-Jan-29)
1-09 (2016-Nov-15) to 1-10 (2018-Jan-25)
Updated Figure 5
1-10 (2018-Jan-25) to 1-11 (2018-Jan-29)
Updated Figure 6
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
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AS5048A/AS5048B −
Content Guide
Page 40
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AS5048A/AS5048B −
Content Guide
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How is I2C communication configured on the device?
The AS5048B supports a high-speed I²C protocol in device mode, including Random/Sequential Read and Byte/Page Write modes. It accommodates clock frequencies for Standard (up to 100kHz), Fast (up to 400kHz), and High Speed (up to 3.4MHz). The 7-bit slave address is determined by the hardware pins A1 and A2 and the configuration of the internal OTP I²C register 21 (0x15). Data is triggered on the rising edge of the SCL clock signal.
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