AMS TCS34717 Light Sensor Datasheet
โฆษณา
โฆษณา
General Description
TCS3471
Color Light-to-Digital Converter
The TCS3471 family of devices provides red, green, blue, and clear light sensing (RGBC) that detects light intensity under a variety of lighting conditions and through a variety of attenuation materials. An internal state machine provides the ability to put the device into a low power mode in between
RGBC measurements providing very low average power consumption.
The TCS3471 is directly useful in lighting conditions containing minimal IR content such as LED RGB backlight control, reflected
LED color sampler, or fluorescent light color temperature detector. With the addition of an IR blocking filter, the device is an excellent ambient light sensor, color temperature monitor, and general purpose color sensor.
and
Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TCS3471, Color Light-to-Digital
Converter are listed below:
Figure 1:
Added Value Of Using TCS3471
Benefits
•
Enables Accurate Color and Ambient Light
Sensing Under Varying Lighting Conditions
•
Minimizes Motion / Transient Errors
•
Clear-Channel Provides a Reference Allows for
Isolation of Color Content
•
Reduces Micro-Processor Interrupt Overhead
•
Reduces Board Space Requirements While
Simplifying Designs
•
1M:1 Dynamic Range
Features
•
Four Independent Analog-to-Digital Converters
•
A Reference-Channel for Color Analysis (Clear Channel
Photo-diode)
•
Programmable Interrupt Function
•
Area Efficient 2mm x 2.4mm Dual Flat No-Lead (FN)
Package
•
Color Light Sensing
• Programmable Analog Gain, Integration Time, and
Interrupt Function with Upper and Lower Thresholds
• Resolution Up to 16 Bits
• Very High Sensitivity - Ideally Suited for Operation
Behind Dark Glass
• Up to 1,000,000:1 Dynamic Range
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TCS3471 −
General Description
•
Low Power Wait State
• 65
μ
A Typical Current
• Wait Timer is Programmable from
2.4 ms to > 7seconds
•
Sleep Mode - 2.5
μ
A Typical Current
•
I²C Interface Compatible
• Up to 400 kHz (I²C Fast Mode)
•
Dedicated Interrupt Pin
•
Pin and Register Set Compatible with the TCS3x7x Family of Devices
Applications
TCS3471, Color Light-to-Digital Converter is ideal for:
•
Color Temperature Sensing
•
RGB LED Backlight Control
•
Color Display Closed-Loop Feedback Control
•
Ambient Light Sensing for Display Brightness Control
•
Industrial Process Control
•
Medical Diagnostics
End Products and Market Segments
•
HDTVs, Mobile Handsets, Tablets, Laptops, Monitors, PMP
(Portable Media Payers)
•
Medical Instrumentation
•
Consumer Toys
•
Industrial/Commercial Lighting
ams Datasheet
[v1-01] 2018-Mar-27
TCS3471 −
General Description
Functional Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TCS3471 Block Diagram
V
DD
GND
Wait Control
RGBC Control
Clear ADC
Clear
Red
Green
Blue
Red ADC
Green ADC
Blue ADC
Clear Data
Red Data
Green Data
Blue Data
Upper Limit
Lower Limit
Interrupt
INT
SCL
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Pin Assignments
Pin Diagram:
Package Drawing Not to Scale
TCS3471 −
Pin Assignments
Figure 3:
Package FN Dual Flat No-Lead (Top View)
V
DD
1
SCL 2
GND 3
6 SDA
5 INT
4 NC
Figure 4:
Terminal Functions
Terminal
Name
V
DD
SCL
GND
NC
INT
SDA
No.
1
4
5
2
3
6
Type Description
I
O
I/O
Supply voltage.
I²C Serial clock input terminal - clock signal for I²C serial data.
Power supply ground. All voltages are referenced to GND.
Do not connect
Interrupt - open drain.
I²C Serial data I/O terminal - serial data I/O for I²C.
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TCS3471 −
Detailed Description
Detailed Description
The TCS3471 light-to-digital device contains a 4
×
4 photodiode array, integrating amplifiers, ADCs, accumulators, clocks, buffers, comparators, a state machine, and an I²C interface. The
4
×
4 photodiode array is composed of red-filtered, green-filtered, blue-filtered, and clear photodiodes — four of each type. Four integrating ADCs simultaneously convert the amplified photodiode currents to a digital value providing up to 16 bits of resolution. Upon completion of the conversion cycle, the conversion result is transferred to the data registers.
The transfers are double-buffered to ensure that the integrity of the data is maintained. Communication to the device is accomplished through a fast (up to 400 kHz), two-wire I²C serial bus for easy connection to a microcontroller or embedded controller.
The TCS3471 provides a separate pin for level-style interrupts.
When interrupts are enabled and a pre-set value is exceeded, the interrupt pin is asserted and remains asserted until cleared by the controlling firmware. The interrupt feature simplifies and improves system efficiency by eliminating the need to poll a sensor for a light intensity value. An interrupt is generated when the value of an RGBC conversion exceeds either an upper or lower threshold. In addition, a programmable interrupt persistence feature allows the user to determine how many consecutive exceeded thresholds are necessary to trigger an interrupt.
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TCS3471 −
Absolute Maximum R atings
Absolute Maximum Ratings
Stresses beyond those listed under
may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Figure 5:
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)
Symbol
V
V
O
I
O
T
STRG
ESD
HBM
Parameter
Supply voltage
Digital output voltage range
Digital output current
Storage temperature range
ESD tolerance, human body model
Note(s):
1. All voltages are with respect to GND.
Figure 6:
Recommended Operating Conditions
Symbol
V
DD
T
A
Parameter
Supply voltage
Operating free-air temperature
Min
-0.5
-1
-40
±2000
Max
3.8
3.8
20
85
Units
V
V mA
ºC
V
Min Nom Max Unit
3 2.7
-30
3.3
70
V
ºC
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TCS3471 −
Absolute Maximum Ratings
Figure 7:
Operating Characteristics; V
DD
= 3 V, T
A
= 25ºC (unless otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Unit
I
I
I
V
DD
OL
LEAK
LEAK
V
V
IH
IL
Supply current
INT, SDA output low voltage
Leakage current, SDA,
SCL, INT pins
Leakage current, LDR pin
Wait mode
Sleep mode - no I²C activity
3 mA sink current
6 mA sink current
SCL, SDA input high voltage
SCL, SDA input low voltage
TCS34711 & TCS34715
TCS34713 & TCS34717
TCS34711 & TCS34715
TCS34713 & TCS34717
65
2.5 10
-1 +10
0.7 V
DD
1.25
0.3 V
DD
0.54
μA
0 0.4
V
0 0.6
μA
V
V
Figure 8:
Optical Characteristics; V
DD
= 3 V, T
A
= 25ºC, GAIN = 16, ATIME = 0xF6 (unless otherwise noted)
Parameter
Test
Conditions
Red
Channel
Green
Channel
Blue
Channel
Clear Channel
Unit
Min Max Min Max Min Max Min Typ Max
R e
Irradiance responsivtiy
λ
D
= 465 nm
λ
D
= 525 nm
0%
8%
15%
25%
10%
60%
42%
85%
65%
9%
88%
35%
19.2
22.4
24
28
28.8
33.6
λ
D
= 625 nm
85% 110% 0% 15% 5% 25% 27.2
34 40.8
counts/
(
μ
W/cm
2
)
Note(s):
1. The percentage shown represents the ratio of the respective red, green, or blue channel value to the clear channel value.
2. The 465 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength
λ
D
= 465 nm, spectral halfwidth
Δλ
½ = 22 nm, and luminous efficacy = 75 lm/W.
3. The 525 nm input irradiance is supplied by an InGaN light-emitting diode with the following characteristics: dominant wavelength
λ
D
= 525 nm, spectral halfwidth
Δλ
½ = 35 nm, and luminous efficacy = 520 lm/W.
4. The 625 nm input irradiance is supplied by a AlInGaP light-emitting diode with the following characteristics: dominant wavelength
λ
D
= 625 nm, spectral halfwidth
Δλ
½ = 9 nm, and luminous efficacy = 155 lm/W.
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TCS3471 −
Absolute Maximum R atings
Figure 9:
RGBC Characteristics; V
DD
= 3 V, T
A
= 25ºC, AGAIN = 16, AEN = 1 (unless otherwise noted)
Parameter
Dark ADC count value
Test Conditions
Ee = 0, AGAIN = 60×, ATIME= 0xD6
(100 ms)
ADC integration time step size
ADC number of integration steps
ADC counts per step
ADC count value
ATIME = 0xFF
ATIME = 0xC0 (153.6 ms)
Min
0
0
0
Typ Max
1 5
Unit
counts
2.27 2.4 2.56 ms
1024 counts
65535 counts
Gain scaling, relative to 1× gain setting
16× 15
Figure 10:
Wait Characteristics; V
DD
= 3 V, T
A
= 25ºC, Gain = 16, WEN = 1 (unless otherwise noted)
Parameter
Wait step size
Wait number steps
Test
Conditions
WTIME = 0xFF
Channel Min Typ
2.27
1
2.4
Max Unit
2.56
256 ms steps
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TCS3471 −
Absolute Maximum Ratings
Figure 11:
AC Electrical Characteristics; V
DD
= 3 V, T
A
= 25ºC, (unless otherwise noted)
t
(SUSTA) t
(SUSTO) t
(HDDAT) t
(SUDAT) t
(LOW) t
(HIGH) t
F t
R
C i
Symbol
f
(SCL) t
(BUF) t
(HDSTA)
Parameter
Clock frequency (I²C)
Bus free time between start and stop condition
Hold time after (repeated) start condition. After this period, the first clock is generated.
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCL clock low period
SCL clock high period
Clock/data fall time
Clock/data rise time
Input pin capacitance
Test
Conditions
Min Typ Max Unit
0
1.3
400 kHz
μ s
0.6
100
1.3
0.6
0.6
0.6
0
300
300
10
μ s ns
μ s
μ s
μ s
μ s
μ s ns ns pF
Note(s):
1. Specified by design and characterization; not production tested.
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TCS3471 −
Absolute Maximum R atings
Parameter Measurement Information
Figure 12:
Timing Diagrams
SCL
SDA t
(BUF)
P
Stop
Condition
V
IH
V
IL t
(LOW)
V
IH
V
IL t
(HDSTA) t
(HDDAT) t
(R)
S
Start
Condition t
(F) t
(HIGH) t
(SUSTA) t
(SUDAT)
S
Start t
(LOWSEXT) t
(LOWMEXT)
SCL
ACK t
(LOWMEXT)
SCL
ACK
Stop t
(LOWMEXT)
SCL
SDA t
(SUSTO)
P
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TCS3471 −
Typical Operating Characteristics
Typical Operating
Characteristics
Figure 13:
Photodiode Spectral Responsivity
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
Clear
500
Red
Normalized to
@ 755 nm
Green
Blue
700
λ
− Wavelength − nm
900
Clear
T
A
= 25
°
C
1100
Figure 14:
Normalized I
DD
vs.V
DD
and Temperature
110%
108%
106%
104%
102%
100%
98%
96%
94%
92%
2.7
2.8
V
DD
and TEMPERATURE
50 C
2.9
3
V
DD
— V
75 C
0 C
3.1
25 C
3.2
3.3
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TCS3471 −
Typical Operating Characteristics
Figure 15:
Normalized Responsivity vs. Angular Displacement
1.0
0.8
0.6
0.4
0.2
0
−90
-Q +Q
−60 −30 0 30
Q
− Angular Displacement −
°
60
90
Figure 16:
Responsivity Temperature Coefficient
10,000
1000
100
400 500
600 700 800
λ
− Wavelength − nm
900 1000 ams Datasheet
[v1-01] 2018-Mar-27
TCS3471 −
Principles Of Operation
Principles Of Operation
System State Machine
The TCS3471 provides control of RGBC and power management functionality through an internal state machine (
).
After a power-on-reset, the device is in the sleep mode. As soon as the PON bit is set, the device will move to the start state. It will then continue through the Wait and RGBC states. If these states are enabled, the device will execute each function. If the
PON bit is set to 0, the state machine will continue until all conversions are completed and then go into a low power sleep mode.
Figure 17:
Simplified State Diagram
PON = 1 (r 0:b0)
Sleep
PON = 0 (r 0:b0)
Start
Wait
RGBC
Note(s):
In this document, the nomenclature uses the bit field name in italics followed by the register number and bit number to allow the user to easily identify the register and bit that controls the function. For example, the power on (PON) is in register 0, bit 0. This is represented as
PON (r0:b0)
.
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TCS3471 −
Principles O f Operation
RGBC Operation
The RGBC engine contains RGBC gain control (AGAIN) and four integrating analog-to-digital converters (ADC) for the RGBC photodiodes. The RGBC integration time (ATIME) impacts both the resolution and the sensitivity of the RGBC reading.
Integration of all four channels occurs simultaneously and upon completion of the conversion cycle, the results are transferred to the color data registers. This data is also referred to as channel
count
.
The transfers are double-buffered to ensure that invalid data is not read during the transfer. After the transfer, the device automatically moves to the next state in accordance with the configured state machine.
Figure 18:
RGBC Operation
ATIME(r 1)
2.4 ms to 700 ms
AGAIN(r 0x0F, b1:0)
1 , 4 , 16 , 60 Gain
RGBC Control
Clear ADC Clear Data
Clear
Red
Green
Blue
Red ADC Red Data
Green ADC Green Data
Blue ADC Blue Data
CDATAH(r 0x15), CDATA(r 0x14)
RDATAH(r 0x17), RDATA(r 0x16)
GDATAH(r 0x19), GDATA(r 0x18)
BDATAH(r 0x1B), BDATA(r 0x1A)
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The registers for programming the integration and wait times are a 2’s compliment values. The actual time can be calculated as follows:
(EQ1)
ATIME = 256 - Integration Time / 2.4 ms
(EQ2)
Inversely, the time can be calculated from the register value as follows:
Integration Time = 2.4 ms
×
(256 - ATIME)
For example, if a 100ms integration time is needed, the device needs to be programmed to:
256 - (100 / 2.4) = 256 - 42 = 214 = 0xD6
Conversely, the programmed value of 0xC0 would correspond to:
(256 - 0xC0)
×
2.4 = 64
×
2.4 = 154 ms.
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TCS3471 −
Principles Of Operation
Interrupts
The interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defined range. While the interrupt function is always enabled and it’s status is available in the status register (0x13), the output of the interrupt state can be enabled using the RGBC interrupt enable (AIEN) field in the enable register (0x00).
Two 16-bit interrupt threshold registers allow the user to set limits below and above a desired light level range. An interrupt can be generated when the RGBC Clear data (CDATA) falls outside of the desired light level range, as determined by the values in the RGBC interrupt low threshold registers (AILTx) and
RGBC interrupt high threshold registers (AIHTx). It is important to note that the low threshold value must be less than the high threshold value for proper operation.
To further control when an interrupt occurs, the device provides a persistence filter. The persistence filter allows the user to specify the number of consecutive out-of-range RGBC occurrences before an interrupt is generated. The persistence register (0x0C) allows the user to set the persistence (APERS) value. See the
for details on the persistence filter values. Once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see
Figure 19:
Programmable Interrupt
AIHTH(r 07), AIHTL(r 06)
Clear
Upper Limit
Clear
ADC
Clear
Data
Lower Limit
AILTH(r 05), AILTL(r 04)
PPERS(r 0x0C, b3:0)
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State Diagram
Figure 20 shows a more detailed flow for the state machine. The
device starts in the sleep mode. The PON bit is written to enable the device. A 2.4ms delay will occur before entering the start state. If the WEN bit is set, the state machine will cycle through the wait state. If the WLONG bit is set, the wait cycles are extended by 12× over normal operation. When the wait counter terminates, the state machine will step to the RGBC state.
The AEN should always be set. In this case, a minimum of 1 integration time step should be programmed. The RGBC state machine will continue until it reaches the terminal count, at which point the data will be latched in the RGBC register and the interrupt set, if enabled.
Figure 20:
Expanded State Diagram
WLONG = 0
1 to 256 steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
Minimum − 2.4 ms
WLONG = 1
1 to 256 steps
Step: 29 ms
Time: 29 ms − 7.4 s
Minimum − 29 ms
Wait
Check
PON = 1
Sleep
PON = 0
Start
WEN = 1
Wait
1 to 256steps
Step: 2.4 ms
Time: 2.4 ms − 614 ms
ALS
ALS
Check
AEN = 1
ALS
Delay
Time: 2.4 ms
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TCS3471 −
Principles Of Operation
I²C Protocols
Interface and control are accomplished through an I²C serial compatible interface (standard or fast mode) to a set of registers that provide access to device control functions and output data.
The devices support the 7-bit I²C addressing protocol.
The I²C standard provides for three types of bus transaction: read, write, and a combined protocol (
operation, the first byte written is a command byte followed by data. In a combined protocol, the first byte written is the command byte followed by reading a series of bytes. If a read command is issued, the register address from the previous command will be used for data access. Likewise, if the MSB of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. The command byte contains either control information or a 5-bit register address. The control commands can also be used to clear interrupts.
The I²C bus protocol was developed by Philips (now NXP). For a complete description of the I²C protocol, please review the
NXP I²C design specification at http://www.i2c-bus.org/references/ .
Figure 21:
I²C Protocols
1
S
7
Slave Address
1
W
1
A
8
Command Code
1
A
I
2
C Write Protocol
8
Data Byte
1
S
7
Slave Address
1
R
1
A
8
Data
1
A
I
2
C Read Protocol
8
Data
1
S
7
Slave Address
1
W
1
A
8
Command Code
1
A
1
Sr
7
Slave Address
1
R
1
A
8
Data
I
2
C Read Protocol — Combined Format
1
A
1
A
...
1
P
1
A
...
1
P
8
Data
1
A
...
1
P
A
N
P
R
S
Sr
W
Acknowledge (0)
Not Acknowledged (1)
Stop Condition
Read (1)
Start Condition
Repeated Start Condition
Write (0)
...
Continuation of protocol
Master-to-Slave
Slave-to-Master
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Register Description
TCS3471 −
Register Description
The TCS3471 is controlled and monitored by data registers and a command register accessed through the serial interface.
These registers provide for a variety of control functions and can be read to determine results of the ADC conversions. The
register set is summarized in Figure 22
.
Figure 22:
Register Set
Address
0x00
0x01
0x07
0x0C
R/W
R/W
Enables states and interrupts
RGBC ADC time
0x0F CONTROL R/W Gain control register
0x12 ID R ID
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
Register Name
ENABLE
ATIME
AIHTH
PERS
CDATA
CDATAH
RDATA
RDATAH
GDATA
GDATAH
BDATA
BDATAH
R/W
R/W
R/W
RGBC interrupt high threshold high byte
Interrupt persistence filters
R
R
R
R
R
R
R
R
Register Function
Clear ADC low data register
Clear ADC high data register
Red ADC low data register
Red ADC high data register
Green ADC low data register
Green ADC high data register
Blue ADC low data register
Blue ADC high data register
Reset Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0x00
0x00
0x00
ID
0x00
0x00
0x00
0x00
The mechanics of accessing a specific register depends on the specific protocol used. See the section on I²C protocols on the previous pages. In general, the COMMAND register is written first to specify the specific control/status register for the following read/write operations.
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TCS3471 −
Register Description
Figure 23:
Command Register
7
COMMAND
6
TYPE
5
Command Register
The command registers specifies the address of the target register for future write and read operations.
4 3 2
ADD
1 0
Field
COMMAND
TYPE
ADD
Bits Description
7 Select Command Register. Must write as 1 when addressing COMMAND register.
6:5 Selects type of transaction to follow in subsequent data transfers:
FIELD VALUE
00
INTEGRATION TIME
Repeated byte protocol transaction
01
10
Auto-increment protocol transaction
Reserved — Do not use
11 Special function — See description below
Byte protocol will repeatedly read the same register with each data access.
Block protocol will provide auto-increment function to read successive bytes.
4:0 Address field/special function field. Depending on the transaction type, see above, this field either specifies a special function command or selects the specific control-status-register for following write and read transactions. The field values listed below apply only to special function commands:
READ VALUE FIELD VALUE
00000 Normal — no action
00110 other
RGBC interrupt clear
Reserved — Do not write
RGBC Interrupt Clear. Clears any pending RGBC interrupt. This special function is self clearing.
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TCS3471 −
Register Description
Enable Register (0x00)
The Enable register is used primarily to power the TCS3471 device on and off, and enable functions and interrupts as shown in
.
Figure 24:
Enable Register
7 6
Reserved
Field
Reserved
5 4
AIEN
Bits
7:5 Reserved. Write as 0.
3
WEN
2
Reserved
Description
1
AEN
0
PON
Reserved 2 Reserved. Write as 0.
PON
0
Power ON. This bit activates the internal oscillator to permit the timers and
ADC channels to operate. Writing a 1 activates the oscillator. Writing a 0 disables the oscillator. During reads and writes over the I²C interface, this bit is temporarily overridden and the oscillator is enabled, independent of the state of PON.
Note(s):
1. A minimum interval of 2.4 ms must pass after PON is asserted before an RGBC can be initiated.
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TCS3471 −
Register Description
RGBC Timing Register (0x01)
The RGBC timing register controls the internal integration time of the RGBC clear and IR channel ADCs in 2.4 ms increments.
Max RGBC Count = (256 - ATIME) × 1024 up to a maximum of
65535.
Figure 25:
RGBC Timing Register
Field Bits
ATIME 7:0
VALUE INTEG_CYCLES
0xFF 1
0xF6 10
0xD5 42
0xC0 64
0x00 256
Description
TIME MAX COUNT
1024
10240
43008
65535
65535
Wait Time Register (0x03)
Wait time is set 2.4 ms increments unless the WLONG bit is asserted, in which case the wait times are 12x longer. WTIME is programmed as a 2’s complement number.
Figure 26:
Wait Time Register
Field
WTIME
Bits
7:0
Description
REGISTER
VALUE
0xFF
0xAB
WAIT TIME
1
85
TIME (WLONG = 0)
0x00 256
2.4 ms
204 ms
TIME (WLONG = 1)
0.029 s
2.45 s
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Figure 27:
RGBC Interrupt Threshold Register
Register
AILTL
AILTH
AIHTL
AIHTH
Address
0x04
0x05
0x06
0x07
Bits
7:0
7:0
7:0
7:0
TCS3471 −
Register Description
RGBC Interrupt Threshold Registers
(0x04 - 0x07)
The RGBC interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation. If the value generated by the clear channel crosses below the lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin.
Description
RGBC clear channel low threshold lower byte
RGBC clear channel low threshold upper byte
RGBC clear channel high threshold lower byte
RGBC clear channel high threshold upper byte
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TCS3471 −
Register Description
Persistence Register (0x0C)
The persistence register controls the filtering interrupt capabilities of the device. Configurable filtering is provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result that is outside of the values specified by the threshold register for some specified amount of time.
Figure 28:
Persistence Register
7 6
Reserved
5 4 3 2
APERS
1 0
Field Bits Description
Reserved 7:4 Reserved.
Interrupt persistence. Controls rate of interrupt to the host processor.
FIELD VALUE
0000
MEANING
Every
INTERRUPT PERSISTENCE FUNCTION
Every RGBC cycle generates an interrupt
0001
0010
0011
0100
1
2
3
5
1 clear channel value outside of threshold range
2 clear channel consecutive values out of range
3 clear channel consecutive values out of range
5 clear channel consecutive values out of range
APERS 3:0
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
30
35
40
45
10
15
20
25
50
55
60
10 clear channel consecutive values out of range
15 clear channel consecutive values out of range
20 clear channel consecutive values out of range
25 clear channel consecutive values out of range
30 clear channel consecutive values out of range
35 clear channel consecutive values out of range
40 clear channel consecutive values out of range
45 clear channel consecutive values out of range
50 clear channel consecutive values out of range
55 clear channel consecutive values out of range
60 clear channel consecutive values out of range
ams Datasheet
[v1-01] 2018-Mar-27
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TCS3471 −
Register Description
Configuration Register (0x0D)
The configuration register sets the wait long time.
Figure 29:
Configuration Register
7 6 5
Reserved
4
Field
Reserved
Bits
7:2 Reserved. Write as 0.
3 2
Description
1
WLONG
0
Reserved
Reserved
Figure 30:
Control Register
7 6
0 Reserved. Write as 0.
Control Register (0x0F)
The Control register provides eight bits of miscellaneous control to the analog block. These bits typically control functions such as gain settings and/or diode selection.
3 2 5
Reserved
4 1
AGAIN
0
Field
Reserved
Bits
7:2 Reserved. Write bits as 0
RGBC Gain Control.
FIELD VALUE
AGAIN 1:0
Description
RGBC GAIN VALUE
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TCS3471 −
Register Description
ID Register (0x12)
The ID Register provides the value for the part number. The ID register is a read-only register.
Figure 31:
ID Register
7 6 5 4
ID
3 2 1 0
Field
ID
Bit
7:0 Part number identification
Description
0x14 = TCS34711 & TCS34715
0x1D = TCS34713 & TCS34717
Status Register (0x13)
The Status Register provides the internal status of the device.
This register is read only.
Figure 32:
Status Register
7 6
Reserved
5 4
AINT
3 2
Reserved
1 0
AVALID
Field Bit
Reserved 7:5
AINT 4
Reserved 3:1
Description
Reserved.
RGBC clear channel Interrupt.
Reserved. completed an integration cycle.
ams Datasheet
[v1-01] 2018-Mar-27
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Figure 33:
ADC Channel Data Registers
Register
CDATA
CDATAH
RDATA
RDATAH
GDATA
GDATAH
BDATA
BDATAH
Address
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
Bits
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
TCS3471 −
Register Description
RGBC Channel Data Registers (0x14 - 0x1B)
Clear, red, green, and blue data is stored as 16-bit values. To ensure the data is read correctly, a two-byte read I²C transaction should be used with a read word protocol bit set in the command register. With this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte.
The upper register will read the correct value even if additional
ADC integration cycles end between the reading of the lower and upper registers.
Description
Clear data low byte
Clear data high byte
Red data low byte
Red data high byte
Green data low byte
Green data high byte
Blue data low byte
Blue data high byte
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TCS3471 −
Application Information: Hardware
Application Information:
Hardware
Typical Hardware Application
A typical hardware application circuit is shown in
.
A 1-
μ
F low-ESR decoupling capacitor should be placed as close as possible to the V
DD
pin.
Figure 34:
Typical Application Hardware Circuit
1
V
DD
m
F
V
BUS
V
DD
GND
TCS3471
INT
SCL
SDA
R
P
R
P
R
PI
V
BUS
in
Figure 34 refers to the I²C bus voltage, which is either
V
DD
or 1.8 V. Be sure to apply the specified I²C bus voltage shown in the Available Options table for the specific device being used.
The I²C signals and the Interrupt are open-drain outputs and require pull-up resistors. The pull-up resistor (R
P
) value is a function of the I²C bus speed, the I²C bus voltage, and the capacitive load. The
ams
EVM running at 400 kbps, uses 1.5-k
Ω resistors. A 10-k
Ω
pull-up resistor (R
PI
) can be used for the interrupt line.
ams Datasheet
[v1-01] 2018-Mar-27
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Figure 35:
Suggested FN Package PCB Layout
TCS3471 −
Application Information: Hardware
PCB Pad Layouts
Suggested PCB pad layout guidelines for the Dual Flat No-Lead
(FN) surface mount package are shown in
.
Note(s):
Pads can be extended further if hand soldering is needed.
1000
2500
1000
650
650
400
400
1700
Note(s):
1. All linear dimensions are in micrometers.
2. This drawing is subject to change without notice.
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TCS3471 −
Mechanical Data
Mechanical Data
Figure 36:
Package FN — Dual Flat No-Lead Packaging Configuration
PACKAGE FN
TOP VIEW
PIN 1
406
10
END VIEW
650 50
BOTTOM VIEW
2000
75
496 10
PIN OUT
TOP VIEW
Dual Flat No-Lead
2400 75
Photodiode Active Area
295
Nominal
V
DD
1
SCL 2
GND 3
SIDE VIEW
6 SDA
5 INT
4 NC
650
BSC 300
50
203 8
CL
of Solder Contacts and
PIN 1
125 Nominal
CL
of Solder Contacts
CL
750 100
RoHS
Green
Pb
Lead Free
Note(s):
1. All linear dimensions are in micrometers.
2. The die is centered within the package within a tolerance of ± 75
μ m.
3. Package top surface is molded with an electrically nonconductive clear plastic compound having an index of refraction of 1.55.
4. Contact finish is copper alloy A194 with pre-plated NiPdAu lead finish.
5. This package contains no lead (Pb).
6. This drawing is subject to change without notice.
ams Datasheet
[v1-01] 2018-Mar-27
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TCS3471 −
Mechanical Data
Figure 37:
Package FN Carrier Tape
TOP VIEW
4.00
2.00 0.05
4.00
1.50
1.75
B
8.00
+ 0.30
− 0.10
5 Max
2.21 0.05
A o
3.50 0.05
0.50
0.05
DETAIL A
0.254
0.02
A A B
0.83 0.05
K o
DETAIL B
5 Max
2.61 0.05
B o
Green
RoHS
Note(s):
1. All linear dimensions are in millimeters. Dimension tolerance is
±
0.10 mm unless otherwise noted.
2. The dimensions on this drawing are for illustrative purposes only. Dimensions of an actual carrier may vary slightly.
3. Symbols on drawing A o
, B o
, and K o
are defined in ANSI EIA Standard 481-B 2001.
4. Each reel is 178 millimeters in diameter and contains 3500 parts.
5.
ams
packaging tape and reel conform to the requirements of EIA Standard 481-B.
6. In accordance with EIA standard, device pin 1 is located next to the sprocket holes in the tape.
7. This drawing is subject to change without notice.
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TCS3471 −
Manufacturing Information
Manufacturing Information
Figure 38:
Solder Reflow Profile
Parameter
Average temperature gradient in preheating
Soak time
Time above 217°C (T
1
)
Time above 230°C (T
2
)
Time above T peak
−10°C (T
3
)
Peak temperature in reflow
Temperature gradient in cooling
Figure 39:
Solder Reflow Profile Graph
The FN package has been tested and has demonstrated an ability to be reflow soldered to a PCB substrate.
The solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a PCB. Temperature is measured on top of component. The components should be limited to a maximum of three passes through this solder reflow profile.
Reference
t soak t
1 t
2 t
3
T peak
Device
2.5°C/s
2 to 3 minutes
Max 60 s
Max 50 s
Max 10 s
260°C
Max −5°C/s
Not to scale — for reference o
T peak
T
3
T
2
T
1 t
3 t
2 t
1
Time (s) t soak
Note(s):
1. Not to scale — for reference only
ams Datasheet
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TCS3471 −
Manufacturing Information
Moisture Sensitivity
Optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previously absorbed into the package.
To ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. Devices are packed in a sealed aluminized envelope with silica gel to protect them from ambient moisture during shipping, handling, and storage before use.
The FN package has been assigned a moisture sensitivity level of MSL 3 and the devices should be stored under the following conditions:
•
Temperature Range: 5ºC to 50ºC
•
Relative Humidity: 60% maximum
•
Total Time: 12 months from the date code on the aluminized envelope — if unopened
•
Opened Time: 168 hours or fewer
Rebaking will be required if the devices have been stored unopened for more than 12 months or if the aluminized envelope has been open for more than 168 hours. If rebaking is required, it should be done at 50ºC for 12 hours.
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TCS3471 −
Ordering & Contact Information
Ordering & Contact Information
Figure 40:
Ordering Information
Ordering Code
TCS34711FN
TCS34713FN
TCS34715FN
TCS34717FN
Description Device Address Package - Leads
FN−6 I²C Vbus = V
DD
Interface
I²C Vbus = 1.8 V Interface
TCS34711 0x39
TCS34713 0x39
I²C Vbus = V
DD
Interface TCS34715 0x29
I²C Vbus = 1.8 V Interface TCS34717 0x29
FN−6
FN−6
FN−6
Buy our products or get free samples online at: www.ams.com/ICdirect
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
ams Datasheet
[v1-01] 2018-Mar-27
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TCS3471 −
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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TCS3471 −
Copyrights & Disclaimer
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
ams Datasheet
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TCS3471 −
Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
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TCS3471 −
Revision Information
Revision Information
Changes from 1-00 (2016-May-23) to current revision 1-01 (2018-Mar-27)
Updated Figure 40
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision
2. Correction of typographical errors is not explicitly mentioned.
Page
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Content Guide
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TCS3471 −
Content Guide
1 General Description
2 End Products and Market Segments
4 Pin Assignments
5 Detailed Description
6 Absolute Maximum Ratings
10 Parameter Measurement Information
11 Typical Operating Characteristics
13 Principles Of Operation
18 Register Description
21 RGBC Timing Register (0x01)
22 RGBC Interrupt Threshold Registers
23 Persistence Register (0x0C)
24 Configuration Register (0x0D)
26 RGBC Channel Data Registers (0x14 - 0x1B)
27 Application Information: Hardware
27 Typical Hardware Application
29 Mechanical Data
31 Manufacturing Information
33 Ordering & Contact Information
34 RoHS Compliant & ams Green Statement
35 Copyrights & Disclaimer
36 Document Status
37 Revision Information
ams Datasheet
[v1-01] 2018-Mar-27
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