AMS TSL210 Datasheet
إعلان
إعلان
General Description
Figure 1:
Added Value of Using TSL210
Benefits
•
Provides High Density Pixel Count
•
Enables High Resolution Scanning
•
Enables Capacitive Threshold Sensing
•
Provides Full Dynamic Range
TSL210
640 × 1 Linear Sensor Array
The TSL210 Linear Sensor Array consists of five sections of
128 photodiodes, each with associated charge amplifier circuitry, running from a common clock. These sections can be connected to form a contiguous 640 × 1 pixel array. Device pixels measure 120μm (H) by 70μm (W) with 125μm center-to-center pixel spacing. Operation is simplified by internal logic that requires only a serial input (SI1 through SI5) for each section and a common clock for the five sections.
The device is intended for use in a wide variety of applications including contact imaging, mark and code reading, bar-code reading, edge detection and positioning, OCR, level detection, and linear and rotational encoding.
and
Content Guide appear at end of
datasheet.
Key Benefits & Features
The benefits and features of TSL210, 640x1 Linear Sensor Array are listed below:
Features
•
640 x 1 Sensor-Element Organization
•
200 Dots-per-Inch (DPI) Sensor Pitch
•
High Linearity and Uniformity
•
Rail-to-Rail Output Swing
•
Wide Dynamic Range: 2000:1 (66dB)
•
Output Referenced to Ground
•
Low Image Lag: 0.5% Typical
•
Operation to 5MHz
•
Single 5V Supply
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[v1-00] 2016-Jul-19
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TSL210 −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 2:
TSL210 Block Diagram
C L K
SI
Pixel 1
S1
1
2
Integrator
Reset
_
+
1
S2
Sample/
Output
2
3
Pixel
2
Q1
Switch Control Logic
Q2 Q3
Pixel
3
Pixel
128
Analog
Bus
Output
Amplifier
V
DD
AO
GND
R
L
(External
330
Load)
Gain
Trim
Q128
SO
1 2 8 B i t Shift Register
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TSL210 −
Pin Assignments
Pin Assignments
The TSL210 pin assignments are described below.
Figure 3:
Pin Diagram
PACKAGE
(TOP VIEW)
1 V
DD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
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TSL210 −
Pin Assignments
Figure 4:
Terminal Functions
16
17
18
12
13
14
15
6
7
8
9
10
11
2
3
4
5
No.
1
Terminal
Name
V
DD
SO3
SI4
AO4
SO4
SI5
AO5
SO5
CLK
SI1
AO1
SO1
SI2
AO2
SO2
GND
SI3
AO3
I
O
O
I
I
O
O
I
O
O
I
O
O
I
O
O
I/O Description
Supply voltage for both analog and digital circuits
Clock input for all sections. The clock controls the charge transfer, pixel output, and reset.
SI1 defines the start of the data out sequence for section 1.
Analog output of section 1
SO1 provides the signal to drive the SI2 input in serial mode or
end of data
for section 1 in parallel mode
SI2 defines the start of the data out sequence for section 2
Analog output of section 2
SO2 provides the signal to drive the SI3 input in serial mode or
end of data
for section 2 in parallel mode
Ground (substrate). All voltages are referenced to the substrate.
SI3 defines the start of the data out sequence for section 3
Analog output of section 3
SO3 provides the signal to drive the SI4 input in serial mode or
end of data
for section 3 in parallel mode
SI4 defines the start of the data out sequence for section 4
Analog output of section 4
SO4 provides the signal to drive the SI5 input in serial mode or
end of data
for section 4 in parallel mode
SI5 defines the start of the data out sequence for section 5
Analog output of section 5
SO5 provides the signal to drive the SI input of another device for cascading or as an
end of data
indication
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TSL210 −
Detailed Description
Detailed Description
The device consists of five sections of 128 photodiodes
(called pixels - 640 total in the device) arranged in a linear array.
Each section has its own signal input and output lines, and all five sections are connected to a common clock line. Light energy impinging on a pixel generates photocurrent that is then integrated by the active integration circuitry associated with that pixel.
During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity on that pixel and the integration time. The voltage output developed for each pixel is according to the following relationship:
(EQ1)
V out
= V drk
+ R e
E
( t int
) where:
•
V out
is the analog output voltage for white condition
•
V drk
is the analog output voltage for dark condition
•
R e
is the device responsivity for a given wavelength of light given in V/(μJ/cm
2
)
•
E e
is the incident irradiance in μW/cm
2
•
t int
is integration time in seconds
The output and reset of the integrators in each section are controlled by a 128-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage on analog output AO (given above). After being read, the pixel integrator is then reset, and the next integration period begins for that pixel. On the 129 th
clock rising edge, the SO pulse is clocked out on SO signifying the end of the read cycle. The section is then ready for another read cycle. The SO of each section can be connected to SI on the next section in the array
(
Figure 13 ). SO can be used to signify the read is complete.
AO is driven by a source follower that requires an external pulldown resistor (330Ω typical). The output is nominally 0V for no light input, 2V for normal white-level, and 3.4V for saturation light level. When the device is not in the output phase, AO is in a high impedance state.
A 0.1μF bypass capacitor should be connected between V
DD and ground as close as possible to the device.
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Absolute Maximum R atings
Absolute Maximum Ratings
Stresses beyond those listed under
may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under
Characteristics is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Figure 5:
Absolute Maximum Ratings
Symbol
V
DD
V
I
I
IK
I
OK
V
O
I
O
I
O
T
A
T
STRG
ESD
HBM
Parameter
Supply voltage range
Input voltage range
Input clamp current (V
I
< 0 or V
I
> V
DD
)
Output clamp current (V
O
< 0 or V
O
> V
DD
)
Voltage range applied to any output in the high impedance or power-off state
Continuous output current (V
O
= 0 to V
DD
)
Continuous current through V
DD
or GND
Analog output current range
Operating free-air temperature range
Storage temperature range
Lead temperature on connection pad for 10 seconds
ESD tolerance, human body model
Min
-0.3
-0.3
-20
-25
Max
6
V
DD
+ 0.3
20
25
-0.3
-25
-100
-25
-25
-25
V
DD
+ 0.3
25
100
25
85
85
260
±2000
V mA mA mA
°C
°C
°C
V
Unit
V
V mA mA
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Electrical Characteristics
Electrical Characteristics
All limits are guaranteed. The parameters with min and max values are guaranteed with production tests or
SQC (Statistical Quality Control) methods.
Figure 6:
Recommended Operating Conditions (see
Symbol
C
L
R
L
T
A f clock t int t int
V
DD
V
I
V
IH
V
IL
λ
Parameter
Supply voltage
Input voltage
High-level input voltage
Low-level input voltage
Wavelength of light source
Clock frequency
Sensor integration time, serial
Sensor integration time, parallel
Load capacitance
Load resistance
Operating free-air temperature
Min
4.5
0
2
0
400
5
0.128
0.026
300
0
Nom
5
Note(s):
1. SI must go low before the rising edge of the next clock pulse.
Figure 7:
Electrical Characteristics at f
R
L
= 330Ω, E e clock
= 200kHz, V
DD
= 5V, T
A
= 18μW/cm
2
= 25°C, λ p
= 640nm, t int
= 5ms,
Max
5.5
V
DD
V
DD
0.8
1000
5000
100
100
330
4700
70
Unit
ms ms pF
Ω
°C
V
V nm kHz
V
V
Symbol Parameter
V
OUT
V
DRK
PRNU
R e
Analog output voltage
(white, average over 640 pixels)
Analog output voltage
(dark, average over 640 pixels)
Pixel response nonuniformity
Nonlinearity of analog output voltage
Output noise voltage
Responsivity
Test
Conditions
Min Typ Max
1.6
2 2.4
E e
= 0
Units
V
0 0.05
16
±0.4%
1
22
0.15
±20
28
V
%
FS mV rms
V/(μJ/cm
2
)
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TSL210 −
Electrical Characteristics
Symbol
SE
V
SAT
DSNU
IL
I
DD
I
IH
I
IL
V
OH
V
OL
C i(SI)
C i(CLK)
Parameter
Test
Conditions
Saturation exposure
Analog output saturation voltage
Dark signal nonuniformity
All pixels,
E e
Image lag
Supply current
High-level input current
Low-level input current
High level output voltage,
SO1-SO5
Low level output voltage,
SO1-SO5
V
I
= V
DD
V
I
= 0
I
O
= 50μA
I
O
= 4mA
I
O
= 50μA
I
O
= 4mA
Input capacitance, SI
Input capacitance, CLK
Min Typ Max
2.5
4
155
3.4
0.04
0.5
37
4.95
4.6
0.01
0.4
20
50
0.12
50
10
10
0.1
V
V pF pF
Note(s):
2. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640nm.
3. Clock duty cycle is assumed to be 50%.
4. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the device under test when the array is uniformly illuminated.
5. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white).
6. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
7. Minimum saturation exposure is calculated using the minimum V sat
, the maximum V drk
, and the maximum R e
.
8. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
9. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after a pixel is exposed to a white condition followed by a dark condition:|
IL =
--------------------------------------------
V
V
)
– V
– drk
V drk
×
100
Units
nJ/cm
2
V
V
% mA
μA
μA
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TSL210 −
Electrical Characteristics
Figure 8:
Timing Requirements (see
and
)
t su(SI) t h(SI) t w t r
, t f
Symbol Parameter
Setup time, serial input
Hold time, serial input
Pulse duration, clock high or low
Input transition (rise and fall) time
Min
20
0
50
0
Nom Max
500
Note(s):
1. Input pulses have the following characteristics: t r
= 6ns, t f
= 6ns.
2. SI must go low before the rising edge of the next clock pulse.
Figure 9:
Dynamic Characteristics over Recommended Ranges of Supply Voltage and Operating
Free-Air Temperature (see
)
Units
ns ns ns ns
Symbol
t s
Parameter
Analog output settling time to ±1%
Test
Condition
C
L
= 10pF
Min Typ
185
Max Unit
ns
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Typical Operating Characteristics
Typical Operating
Characteristics
Figure 10:
Timing Waveforms (each section)
CLK
SI1
AO
129 Clock Cycles
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hi-Z
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Hi-Z
Figure 11:
Operational Waveforms (each section)
CLK t su(SI)
SI t w 1
AO t s
50% t h(SI)
Pixel 1
2 t s
128
Pixel 128
129
2.5 V
5 V
0 V
5 V
0 V
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TSL210 −
Typical Operating Characteristics
Figure 12:
Photodiode Spectral Responsivity
0.6
0.4
1
T
A
= 25
°
C
0.8
0.2
0
300 400 500 600 700 800
λ
− Wavelength − nm
900 1000 1100 ams Datasheet
[v1-00] 2016-Jul-19
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Application Information
TSL210 −
Application Information
Integration Time
The integration time of the linear array is the period during which light is sampled and charge accumulates on each pixel’s integrating capacitor. The flexibility to adjust the integration period is a powerful and useful feature of the
ams
TSL2xx linear array family. By changing the integration time, a desired output voltage can be obtained on the output pin while avoiding saturation for a wide range of light levels.
Each pixel of the linear array consists of a light-sensitive photodiode. The photodiode converts light intensity to a voltage. The voltage is sampled on the Sampling Capacitor by closing switch S2 (position 1) (see
Figure 2 ). Logic controls the
resetting of the Integrating Capacitor to zero by closing switch
S1 (position 2).
At SI input (Start Integration), pixel 1 is accessed. During this event, S2 moves from position 1 (sampling) to position 3
(holding). This holds the sampled voltage for pixel 1. Switch S1 for pixel 1 is then moved to position 2. This resets (clears) the voltage previously integrated for that pixel so that pixel 1 is now ready to start a new integration cycle. When the next clock period starts, the S1 switch is returned to position 1 to be ready to start integrating again. S2 is returned to position 1 to start sampling the next light integration. Then the next pixel starts the same procedure. The integration time is the time from a specific pixel read to the next time that pixel is read again. If either the clock speed or the time between successive SI pulses is changed, the integration time will vary. After the final (
n
th
) pixel in the array is read on the output, the output goes into a high-impedance mode. A new SI pulse can occur on the (
n
+1) clock causing a new cycle of integration/output to begin. Note that the time between successive SI pulses must not exceed the maximum integration time of 100ms.
The minimum integration time for any given array is determined by time required to clock out all the pixels in the array and the time to discharge the pixels. The time required to discharge the pixels is a constant. Therefore, the minimum integration period is simply a function of the clock frequency and the number of pixels in the array. A slower clock speed increases the minimum integration time and reduces the maximum light level for saturation on the output. The minimum integration time shown in this data sheet is based on the maximum clock frequency of 5MHz.
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TSL210 −
Application Information
The minimum integration time can be calculated from the equation:
(EQ2)
T int min
)
=
maximum clock frequency
× n where: n is the number of pixels
In the case of the TSL210, the minimum integration time would be:
T int min
)
= 200ns
×
640 = 128
μ s
It is important to note that not all pixels will have the same integration time if the clock frequency is varied while data is being output.
It is good practice on initial power up to run the clock (n+1) times after the first SI pulse to clock out indeterminate data from power up. After that, the SI pulse is valid from the time following (n+1) clocks. The output will go into a high-impedance state after the n+1 high clock edge. It is good practice to leave the clock in a low state when inactive because the SI pulse required to start a new cycle is a low-to-high transition.
The integration time chosen is valid as long as it falls in the range between the minimum and maximum limits for integration time. If the amount of light incident on the array during a given integration period produces a saturated output
(Max Voltage output), then the data is not accurate. If this occurs, the integration period should be reduced until the analog output voltage for each pixel falls below the saturation level. The goal of reducing the period of time the light sampling window is active is to lower the output voltage level to prevent saturation. However, the integration time must still be greater than or equal to the minimum integration period.
If the light intensity produces an output below desired signal levels, the output voltage level can be increased by increasing the integration period provided that the maximum integration time is not exceeded. The maximum integration time is limited by the length of time the integrating capacitors on the pixels can hold their accumulated charge. The maximum integration time should not exceed 100ms for accurate measurements.
Although the linear array is capable of running over a wide range of operating frequencies up to a maximum of 5MHz, the speed of the A/D converter used in the application is likely to be the limiter for the maximum clock frequency. The voltage output is available for the whole period of the clock, so the setup and hold times required for the analog-to-digital conversion must be less than the clock period.
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TSL210 −
Application Information
Figure 13:
Connection Diagrams
TSL210 SERIAL
1 V
DD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
R
L
330
Ω
Input
Output
TSL210 PARALLEL
10 SI3
11 AO3
12 SO3
13 SI4
14 AO4
15 SO4
16 SI5
17 AO5
18 SO5
1 V
DD
2 CLK
3 SI1
4 AO1
5 SO1
6 SI2
7 AO2
8 SO2
9 GND
R
L
330
Ω
Input
Output 1
Output 2
Output 3
Output 4
Output 5
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TSL210 −
Package Mechanical Data
Package Mechanical Data
Figure 14:
TSL210 Mechanical Specifications
SIDE VIEW
TOP VIEW
0.158 (4,01)
0.150 (3,81)
CL
0.242 (6,15)
0.222 (5,64)
0.878 (22,30)
0.858 (21,80)
Pixel 1
Pin 1
17
y
0.10 (2,54)
18
y j
0.0272 (0,69)
0.0208 (0,53)
2
y j
0.090 (2,29
)
3.54 (89,92)
3.53 (89,66)
1.869 (47,46)
1.858 (47,20)
3.706 (94,125)
3.696 (93,875)
Pixel 640
0.510 (12,95)
0.490 (12,45)
SIDE VIEW
CROSS SECTION
0.048 (1,22)
0.038 (0,97)
Cover Glass
Bonded Die
0.0272 (0,69)
Bypass Capacitor
0.130 (3,30)
0.120 (3,05)
RoHS
Green
Note(s):
1. All linear dimensions are in inches (millimeters).
2. Pixel centers are located along the center line of the mounting holes.
3. Cover glass index of refraction is 1.52.
4. This drawing is subject to change without notice.
ams Datasheet
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TSL210 −
Ordering & Contac t Information
Ordering & Contact Information
Figure 15:
Ordering Information
Ordering Code
TSL210
Type
640x1 Array
Delivery Form
Tray
Delivery Quantity
20 pcs/tray
Buy our products or get free samples online at: www.ams.com/ICdirect
Technical Support is available at: www.ams.com/Technical-Support
Provide feedback about this document at: www.ams.com/Document-Feedback
For further information and requests, e-mail us at: [email protected]
For sales offices, distributors and representatives, please visit: www.ams.com/contact
Headquarters
ams AG
Tobelbader Strasse 30
8141 Premstaetten
Austria, Europe
Tel: +43 (0) 3136 500 0
Website: www.ams.com
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TSL210 −
RoHS Compliant & ams Green Statement
RoHS Compliant & ams Green
Statement
RoHS:
The term RoHS compliant means that ams AG products fully comply with current RoHS directives. Our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed
0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, RoHS compliant products are suitable for use in specified lead-free processes.
ams Green (RoHS compliant and no Sb/Br):
ams Green defines that in addition to RoHS compliance, our products are free of Bromine (Br) and Antimony (Sb) based flame retardants
(Br or Sb do not exceed 0.1% by weight in homogeneous material).
Important Information:
The information provided in this statement represents ams AG knowledge and belief as of the date that it is provided. ams AG bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. ams AG has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams AG and ams AG suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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Copyrights & Disclaimer
TSL210 −
Copyrights & Disclaimer
Copyright ams AG, Tobelbader Strasse 30, 8141 Premstaetten,
Austria-Europe. Trademarks Registered. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner.
Devices sold by ams AG are covered by the warranty and patent indemnification provisions appearing in its General Terms of
Trade. ams AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein. ams AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with ams AG for current information. This product is intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams AG for each application. This product is provided by ams AG “AS IS” and any express or implied warranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed.
ams AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of ams AG rendering of technical or other services.
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TSL210 −
Document Status
Document Status
Document Status
Product Preview
Preliminary Datasheet
Datasheet
Datasheet (discontinued)
Product Status
Pre-Development
Pre-Production
Production
Discontinued
Definition
Information in this datasheet is based on product ideas in the planning phase of development. All specifications are design goals without any warranty and are subject to change without notice
Information in this datasheet is based on products in the design, validation or qualification phase of development.
The performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice
Information in this datasheet is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade
Information in this datasheet is based on products which conform to specifications in accordance with the terms of ams AG standard warranty as given in the General Terms of
Trade, but these products have been superseded and should not be used for new designs
ams Datasheet
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TSL210 −
Revision Information
Revision Information
Changes from 039D (2011-Aug) to current revision 1-00 (2016-Jul-19)
Content of TAOS datasheet was converted to latest
ams
design
Added Figure 1
Added Figure 15
Note(s):
1. Page and figure numbers for the previous version may differ from page and figure numbers in the current revision.
2. Correction of typographical errors is not explicitly mentioned.
Page
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TSL210 −
Content Guide
Content Guide
1 General Description
1 Key Benefits & Features
2 Block Diagram
3 Pin Assignments
5 Detailed Description
6 Absolute Maximum Ratings
7 Electrical Characteristics
10 Typical Characteristics
12 Application Information
12 Integration Time
15 Mechanical Information
16 Ordering & Contact Information
17 RoHS Compliant & ams Green Statement
18 Copyrights & Disclaimer
19 Document Status
20 Revision Information
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تم تحديث الرابط العام
رابط عام للمستند
إعلان