NXP PN736X NFC Cortex-M0 microcontroller Data Sheet

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PN736X

NFC Cortex-M0 microcontroller

Rev. 3.3 — 7 September 2017

406333

Product data sheet

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1 General description

The PN736X family is a family of 32-bit ARM Cortex-M0-based NFC microcontrollers offering high performance and low power consumption. It has a simple instruction set and memory addressing along with a reduced code size compared to existing architectures.

PN736Xoffers an all in one solution, with features such as NFC, microcontroller, and software in a single chip. It operates at CPU frequencies of up to 20 MHz. It is part of the

PN7462AU product family which offers a common set of features, library and tools.

The peripheral complement of the PN736X microcontroller includes 160/80 kB of flash memory, 12 kB of SRAM data memory and 4 kB EEPROM. It also includes one host interface with either high-speed mode I

C-bus, SPI, USB or high-speed UART, and two master interfaces, SPI and Fast-mode Plus I

C-bus. Four general-purpose counter/ timers, a random number generator, one CRC coprocessor and up to 21 general-purpose

I/O pins are also available.

The PN736X NFC microcontroller offer a one chip solution to build contactless applications. It is equipped with a highly integrated high-power output NFC-IC for contactless communication at 13.56 MHz enabling EMV-compliance on RF level, without additional external active components.

PN736X supports the following operating modes:

•

ISO/IEC 14443-A and B, MIFARE

•

JIS X 6319-4 (comparable with FeliCa scheme)

•

ISO/IEC 15693, ICODE, ISO/IEC 18000-3 mode 3

•

NFC protocols - tag reader/writer, P2P

•

ISO/IEC 14443- type A card emulation

•

EMVCo compliance

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PN736X

NFC Cortex-M0 microcontroller

2 Features and benefits

2.1 Integrated contactless interface frontend

•

High RF output power frontend IC for transfer speed up to 848 kbit/s

•

NFC IP1 and NFC IP2 support

•

Full NFC tag support (type 1, type 2, type 3, type 4A and type 4B)

•

P2P active and passive, target and initiator

•

Card emulation ISO14443 type A

•

ISO/IEC 14443 type A and type B

•

MIFARE classic card

•

ISO/IEC 15693, and ISO/IEC 18000-3 mode 3

•

Low-power card detection

•

Dynamic Power Control (DPC) support

•

Compliance with EMV contactless protocol specification

•

Compliance with NFC standards

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2.2 Cortex-M0 microcontroller

•

Processor core

–

ARM Cortex: 32-bit M0 processor

–

Built-in Nested Vectored Interrupt Controller (NVIC)

–

Non-maskable interrupt

–

24-bit system tick timer

–

Running frequency of up to 20 MHz

–

Clock management to enable low power consumption

•

Memory

–

Flash: 160 (PN7362) / 80 kB (PN7360)

–

SRAM: 12 kB

–

EEPROM: 4 kB

–

40 kB boot ROM included, including USB mass storage primary boot loader for code download

•

Debug option

–

Serial Wire Debug (SWD) interface

•

Peripherals

–

Host interface:

–

USB 2.0 full speed with USB 3.0 hub connection capability

–

HSUART for serial communication, supporting standards speeds from 9600 bauds to

115200 bauds, and faster speed up to 1.288 Mbit/s

–

SPI with half-duplex and full duplex capability with speeds up to 7 Mbit/s

–

C supporting standard mode, fast mode and high-speed mode with multiple address support

–

Master interface:

–

SPI with half-duplex capability from 1 Mbit/s to 6.78 Mbit/s

–

C supporting standard mode, fast mode, fast mode plus and clock stretching

•

Up to 21 General-Purpose I/O (GPIO) with configurable pull-up/pull-down resistors

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•

GPIO1 to GPIO12 can be used as edge and level sensitive interrupt sources

•

Power

–

Two reduced power modes: standby mode and hard power-down mode

–

Supports suspend mode for USB host interface

–

Processor wake-up from hard power-down mode, standby mode, suspend mode via host interface, GPIOs, RF field detection

–

Integrated PMU to adjust internal regulators automatically, to minimize the power consumption during all possible power modes

–

Power-on reset

–

RF supply: external, or using an integrated LDO (TX LDO, configurable with 3 V, 3.3

V, 3.6 V, 4.5 V, and 4.75 V)

–

Pad voltage supply: external 3.3 V or 1.8 V, or using an integrated LDO (3.3 V supply)

•

Timers

–

Four general-purpose timers

–

Programmable Watchdog Timer (WDT)

•

CRC coprocessor

•

Random number generator

•

Clocks

–

Crystal oscillator at 27.12 MHz

–

Dedicated PLL at 48 MHz for the USB

–

Integrated HFO 20 MHz and LFO 365 kHz

•

General

–

HVQFN64 package

–

Temperature range: -40 °C to +85 °C

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3 Applications

•

Physical access control

•

Gaming

•

USB NFC reader, including dual interface smart card readers

•

Home banking, payment readers EMVCo compliant

•

High integration devices

•

NFC applications

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4 Quick reference data

Table 1. Quick reference data

Operating range: -40 °C to +85 °C unless specified; contactless interface: internal LDO not used

Symbol

DDP(VBUS)

Parameter

power supply voltage on pin VBUS

Conditions

card emulation, passive target

(PLM) all RF modes

Min

2.3

2.7

Typ

DD(PVDD)

DDP(VBUS)

DD(TVDD)

P max

T amb

PVDD supply voltage power supply current on pin VBUS all RF modes

1.8 V

3.3 V in hard power-down mode; T

= 25 °C; V

DDP(VBUS)

RST_N = 0

= 5.5 V; stand by mode; T = 25 °C;

DDP(VBUS)

= 3.3 V; external

PVDD LDO used stand by mode; T = 25 °C;

DDP(VBUS)

= 5.5 V; internal

PVDD LDO used suspend mode, USB interface;

DDP(VBUS)

= 5.5 V; external

PVDD supply; T = 25 °C

TVDD supply current on pin TVDD_IN; maximum supported current by the contactless interface maximum power dissipation ambient temperature JEDEC PCB

1.65

-40 -

1.8

3.3

120

Max

5.5

1.95

3.6

250

1050

+85

Unit

μA

μA mA mW

°C

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5 Ordering information

The PN736X family includes the following products:

PN7362AU: Full memory available, no contact interface, no Auxillary interface.

PN7360AU: Memory limited to 80 kB, and no contact interface, no Auxillary interface.

The table below lists the ordering information for these two products.

Table 2. Ordering information

Type number Package

Name

PN7360AUHN

PN7362AUHN

Description

HVQFN64 plastic thermal enhanced very thin quad flat package; no leads; 64 terminals; body 9 × 9 × 0.85 mm

Version

SOT804-4

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6 Block diagram

SWD

ARM-CORTEX M0 system bus master

SRAM

12 kB slave

EEPROM

4 kB

FLASH

160 / 80 kB

ROM

40 kB slave

CODE PATCH slave master

AHB LITE master slave

PN736X

NFC Cortex-M0 microcontroller

USB

I2C

SPI

HSU

HOST INTERFACES

CLIF

SPI MASTER

I2C MASTER

POWER, CLOCK

AND RESET

CLOCK GENERATORS

HFO LFO

USB PLL

MAIN LDO

PMU

PVDD LDO

TX LDO

TEMPERATURE SENSOR

TIMERS

TIME 0, 1, 2, 3

WATCHDOG

RNG

CRC

GPIO

XTAL

aaa-025625

Figure 1. Block diagram

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7 Pinning information

7.1 Pinning

terminal 1 index area l2CM_SDA

GPIO14

GPIO15

GPIO16 n.c.

ATX_A

ATX_B

ATX_C

ATX_D

PVDD_IN

DVDD

DWL_REQ

IRQ

SWDCLK

SWDIO

GPIO1

PN736XAU

GND

VBUSP n.c.

n.c.

GNDP

PVDD_OUT

VBUS

RST_N

XTAL2

XTAL1

VDD

VUP_TX

TVDD_OUT

ANT2

ANT1

TVDD_IN

TX1

aaa-025629

Transparent top view

Figure 2. Pin configuration

Important note: the inner leads below the package are internally connected to the PIN.

Special care needs to be taken during the design so that no conductive part is present under these PINs, which could cause short cuts.

7.2 Pin description

All IO pins can carry up to 4 alternate functions, but not every IO pins has 4 alternate functions assigned. The following table will provide an overview. On all pins where function rank is mentioned, the functionality is assigned to the first function.

Table 3. Pin description

Symbol Pin

I2CM_SDA

GPIO14

Description

C-bus serial data I/O master / GPIO13

First function: NA

Second function: GPIO14

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Symbol

GPIO15

GPIO16

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

RXN

RXP

VMID

TX2

TVSS

TX1

TVDD_IN

ANT1

ANT2

TVDD_OUT

ATX_A

ATX_B

ATX_C

ATX_D

PVDD_IN

DVDD

DWL_REQ

IRQ

SWDCLK

SWDIO

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

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Pin

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PN736X

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Description

First function: NA

Second function: GPIO15

First function: NA

Second function: GPIO16 not connected

SPI slave select input (NSS_S) / I

C-bus serial clock input (SCL_S) / HSUART RX

SPI slave data input (MOSI_S) / I

C-bus serial data I/O (SDA_S) / HSUART TX

USB D+ / SPI slave data output (MISO_S) / I

C-bus address bit0 input / HSUART RTS

USB D- / SPI clock input (SCK_S) / I

C-bus address bit1 input / HSUART CTS pad supply voltage input digital core logic supply voltage input entering in download mode interrupt request output

SW serial debug line clock

SW serial debug line input/output general-purpose I/O / SPI master select2 output general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O general-purpose I/O receiver input receiver input receiver reference voltage input antenna driver output ground for antenna power supply antenna driver output antenna driver supply voltage input antenna connection for load modulation in card emulation and P2P passive target modes antenna connection for load modulation in card emulation and P2P passive target modes antenna driver supply, output of TX_LDO

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Pin

Die pad

Symbol

VUP_TX

VDD

XTAL1

XTAL2

RST_N

VBUS

PVDD_OUT

GNDP

VBUSP

GNDC

USB_VBUS

PVDD_M_IN

SPIM_SSN

SPI_SCLK

SPIM_MOSI

SPIM_MISO

I2CM_SCL

GND

Description

supply of the contactless TX_LDO

1.8 V regulator output for digital blocks

27.12 MHz clock input for crystal

27.12 MHz clock input for crystal reset pin main supply voltage input of microcontroller output of PVDD_LDO for pad voltage supply

Ground not connected not connected

Connected to VBUS not connected not connected not connected not connected not connected connected to the ground not connected not connected not connected used for USB VBUS detection pad supply voltage input for master interfaces

SPI master select 1 output / GPIO17

SPI master clock output / GPIO18

SPI master data output / GPIO19

SPI master data input / GPIO20

C-bus serial clock output master / GPIO21

Ground

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8 Functional description

8.1 ARM Cortex-M0 microcontroller

The PN736X is an ARM Cortex-M0-based 32-bit microcontroller, optimized for low-cost designs, high energy efficiency, and simple instruction set.

The CPU operates on an internal clock, which can be configured to provide frequencies such as 20 MHz, 10 MHz, and 5 MHz.

The peripheral complement of the PN736X includes a 160 kB flash memory, a 12 kB

SRAM, and a 4 kB EEPROM. It also includes one configurable host interface (Fast-mode

Plus and high-speed I

Plus I

2 interface.

C, SPI, HSUART, and USB), two master interfaces (Fast-mode

C, SPI), 4 timers, 12 general-purpose I/O pins, and one 13.56 MHz contactless

8.2 Memories

8.2.1 On-chip flash programming memory

The PN736X contains160 / 80 kB on-chip flash program memory depending on the version. The flash can be programmed using In-System Programming (ISP) or In-

Application Programming (IAP) via the on-chip boot loader software.

The flash memory is divided into two instances of 80 kB each, with each sector consisting of individual pages of 64 bytes.

8.2.1.1 Memory mapping

The flash memory mapping is described in

Figure 3 .

0x0021 6FFF

RESERVED

KBytes

0x0022 AFFF

0x0022 A7FF

FLASH user application

KBytes user application

158

KBytes

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PN7360

Figure 3. Flash memory mapping

0x0020 3000

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8.2.2 EEPROM

The PN736X embeds 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory.

The EEPROM can be programmed using In-System Programming (ISP).

8.2.2.1 Memory mapping

0x201FFF

3.5

KBytes user space

512

Bytes

RESERVED

0x201200

0x201000

aaa-021125

Figure 4. EEPROM memory mapping

8.2.3 SRAM

The PN736X contains a total of 12 kB on-chip static RAM memory.

8.2.3.1 Memory mapping

The SRAM memory mapping is shown in

Figure 5 .

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RAM_Sys_End = 0x00102FFF

RAM_Sys_Start = 0x00102F00

PN736X

NFC Cortex-M0 microcontroller

RAM_SYSTEM

RESERVED

256

Bytes

RAM USER RW

12000

Bytes

RAM_User_Start = 0x00100020

RAM_User_RO_Start = 0x100000

RESERVED

Bytes

aaa-021126

Figure 5. SRAM memory mapping

8.2.4 ROM

The PN736X contains 40 kB of on-chip ROM memory. The on-chip ROM contains boot loader, USB mass storage primary download and the following Application Programming

Interfaces (APIs):

•

In-Application Programming (IAP) support for flash

•

Lifecycle management of debug interface, code write protection of flash memory and

USB mass storage primary download

•

USB descriptor configuration

•

Configuration of timeout and source of pad supply

8.2.5 Memory map

The PN736X incorporates several distinct memory regions.

Figure 6 shows the PN736X

memory map, from the user program perspective, following reset.

The APB peripheral area is 512 kB in size, and is divided to allow up to 32 peripherals.

Only peripherals from 0 to 15 are accessible. Each peripheral is allocated 16 kB, which simplifies the address decoding for the peripherals. APB memory map is described in

Figure 7 .

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4 GB 0xFFFF FFFF

0xE0FF FFFF

PRIVATE PERIPHERAL BUS

0xE000 0000

RESERVED

0x4007 FFFF

APB PERIPHERAL

1 GB

0x4000 0000

RESERVED

0x0022 AFFF

80 kB FLASH

0x0020 3000

RESERVED

0x0020 1FFF

4 kB EEPROM

0x0020 1000

EEPROM REG

2 MB

0x0020 0000

RESERVED

0x0010 2FFF

12 kB SRAM

0x0010 0000

1 MB

RESERVED

0x0000 9FFF

40 kB ROM

0 MB

PN7360

Figure 6. PN736X memory map

0x0000 0000

PN736X

NFC Cortex-M0 microcontroller

4 GB 0xFFFF FFFF

1 GB

2 MB

1 MB

0 MB

PRIVATE PERIPHERAL BUS

0xE0FF FFFF

0xE000 0000

RESERVED

APB PERIPHERAL

0x4007 FFFF

0x4000 0000

RESERVED

160 kB FLASH

0x0022 AFFF

0x0020 3000

RESERVED

4 kB EEPROM

0x0020 1FFF

0x0020 1000

EEPROM REG

0x0020 0000

RESERVED

12 kB SRAM

0x0010 2FFF

0x0010 0000

RESERVED

0x0000 9FFF

40 kB ROM

PN7362

0x0000 0000

aaa-025628

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APB ID

16 to 31

APB IF name Connected IP

Reserved

SPIMASTER_APB

I2CMASTER_APB

Reserved

USB_APB

PCR_APB

HOST_APB

TIMERS_APB

RNG_APB

SPI Master IF

I2C Master IF

HostIF (USB) IP

PowerClockResetModule IP

HostIF (I2C/SPI/HSU/BufMgt) IP

Timer IP

RNG IP

Reserved

CLOCKGEN_APB

CRC_APB

PMU_APB

CL_APB

Reserved

Clock Gen module

CRC IP

PMU modules

Contactless IP

0x4004 8000

0x4004 0000

0x4003 C000

0x4003 8000

0x4003 4000

0x4003 0000

0x4002 C000

0x4002 8000

0x4002 4000

0x4002 0000

0x4001 C000

0x4001 8000

0x4001 4000

0x4001 0000

0x4000 C000

0x4000 8000

0x4000 4000

0x4000 0000

aaa-021127

Figure 7. APB memory map

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8.3 Nested Vectored Interrupt Controller (NVIC)

Cortex-M0 includes a Nested Vectored Interrupt Controller (NVIC). The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.

8.3.1 NVIC features

•

System exceptions and peripheral interrupts control

•

Support 32 vectored interrupts

•

Four interrupt priority levels with hardware priority level masking

•

One Non-Maskable Interrupt (NMI) connected to the watchdog interrupt

•

Software interrupt generation

8.3.2 Interrupt sources

The following table lists the interrupt sources available in the PN736X microcontroller.

Table 4. Interrupt sources

EIRQ# Source Description

0 timer 0/1/2/3 general-purpose timer 0/1/2/3 interrupt

CLIF

EECTRL host IF reserved contactless interface module interrupt

EEPROM controller reserved reserved

TX or RX buffer from I

C, SPI, HSU, or USB module

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NMI

[1]

EIRQ# Source

8 -

Description

reserved reserved

WDT

PMU

SPI master TX or RX buffer from SPI master module

C master TX or RX buffer from I

C master module

PCR power management unit (temperature sensor, over current, overload, and VBUS level)

PCR

PCR high temperature from temperature sensor 0 and 1; interrupt to CPU from PCR to indicate wake-up from suspend mode; out of standby; out of suspend; event on GPIOs configured as inputs interrupt common GPIO1 to GPIO12

PCR interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO1 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO2

PCR

PCR interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO3 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO4

PCR interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO5

PCR

PCR interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO6 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO7 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO8 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO9 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO10 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO11 interrupt (rise/fall/both-edge/level-high/level-low interrupt as programmed) GPIO12 reserved reserved reserved reserved reserved reserved watchdog interrupt is connected to the non-maskable interrupt pin

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[1] The NMI is not available on an external pin.

8.4 GPIOs

The PN736X has 12 general-purpose I/O (GPIO) with configurable pull-up and pull-down resistors, plus six additional GPIOs multiplexed with SPI master and I

C-bus master.

Pins can be dynamically configured as inputs or outputs. GPIO read/write are made by the FW using dedicated registers that allow reading, setting or clearing inputs. The value of the output register can be read back, as well as the current state of the input pins.

8.4.1 GPIO features

•

Dynamic configuration as input or output

•

3.3 V and 1.8 V signaling

•

Programmable weak pull-up and weak pull-down

•

Independent interrupts for GPIO1 to GPIO12

•

Interrupts: edge or level sensitive

•

GPIO1 to GPIO12 can be programmed as wake-up sources

•

Programmable spike filter (3 ns)

•

Programmable slew rate (3 ns and 10 ns)

•

Hysteresis receiver with disable option

8.4.2 GPIO configuration

The GPIO configuration is done through the PCR module (power, clock, and reset).

8.4.3 GPIO interrupts

GPIO1 to GPIO12 can be programmed to generate an interrupt on a level, a rising or falling edge or both.

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8.5 CRC engine 16/32 bits

The PN7362 has a configurable 16/32-bit parallel CRC coprocessor.

The 16-bit CRC is compliant to X.25 (CRC-CCITT, ISO/IEC 13239) standard with a generator polynome of:

The 32-bit CRC is compliant to the ethernet/AAL5 (IEEE 802.3) standard with a generator polynome of:

CRC calculation is performed in parallel, meaning that one CRC calculation is performed in one clock cycle. The standard CRC 32 polynome is compliant with FIPS140-2.

Note

: No final XOR calculation is performed

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Following are the CRC engine features:

•

Configurable CRC preset value

•

Selectable LSB or MSB first

•

CRC 32 calculation based on 32-bit, 16-bit, and 8-bit words

•

CRC16 calculation based on 32-bit, 16-bit, and 8-bit words

•

Supports bit order reverse

8.6 Random Number Generator (RNG)

The PN736X integrates a random number generator. It consists of an analog True

Random Number Generator (TRNG), and a digital Pseudo Random Number Generator

(PRNG). The TRNG is used for loading a new seed in the PRNG.

The random number generator features:

•

8-bit random number

•

Compliant with FIPS 140-2

•

Compliant with BSI AIS20 and SP800-22

8.7 Master interfaces

8.7.1 I

C master interface

The PN736X contains one I

Section 8.8.2

C master and one I

C slave controller. This chapter describes the master interface. For more information on the I C slave controller, refer to

The I

C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line

(SCL) and a Serial Data Line (SDA). Each device has a unique address. The device can operate either as a receive-only device (such as LCD driver) or a transmitter with the capability to both receive and send information (such as memory).

8.7.1.1 I

C features

The I

C master interface supports the following features:

•

Standard I

C compliant bus interface with open-drain pins

•

Standard-mode, fast mode and fast mode plus (up to 1 Mbit/s).

•

Support I

C master mode only.

•

Programmable clocks allowing versatile rate control.

•

Clock stretching

•

7-bit and 10-bit I

C slave addressing

•

LDM/STM instruction support

•

Maximum data frame size up to 1024 bytes

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8.7.2 SPI interface

The PN736X contains one SPI master controller and one SPI slave controller.

The SPI master controller transmits the data from the system RAM to the SPI external slaves. Similarly, it receives data from the SPI external slaves and stores them into the

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system RAM. It can compute a CRC for received frames and automatically compute and append CRC for outgoing frames (optional feature).

8.7.2.1 SPI features

The SPI master interface provides the following features:

•

SPI master interface: synchronous, half-duplex

•

Supports Motorola SPI frame formats only (SPI block guide V04.0114 (Freescale) specification)

•

Maximum SPI data rate of 6.78 Mbit/s

•

Multiple data rates such as 1, 1.51, 2.09, 2.47, 3.01, 4.52, 5.42 and 6.78 Mbit/s

•

Up to two slaves select with selectable polarity

•

Programmable clock polarity and phase

•

Supports 8-bit transfers only

•

Maximum frame size: 511 data bytes payload + 1 CRC byte

•

Optional 1 byte CRC calculation on all data of TX and RX buffer

•

AHB master interface for data transfer

8.8 Host interfaces

The PN736X embeds four different interfaces for host connection: USB, HSUART, I

2 and SPI.

The four interfaces share the buffer manager and the pins; see

Table 5 .

Table 5. Pin description for host interface

Name SPI I

ATX_A

ATX_B

ATX_C

ATX_D

NSS_S

MOSI_S

MISO_S

SCK_S

SCL_S

SDA_S

C_ADR0

C_ADR1

USB

HSU

HSU_RX

HSU_TX

HSU_RTS_N

HSU_CTS_N

The interface selection is done by configuring the Power Clock Reset (PCR) registers.

Note:

The host interface pins should not be kept floating.

8.8.1 High-speed UART

The PN736X has a high-speed UART which can operate in slave mode only.

Following are the HSUART features:

•

Standard bit-rates are 9600, 19200, 38400, 57600, 115200, and up to 1.288 Mbit/s

•

Supports full duplex communication

•

Supports only one operational mode: start bit, 8 data bits (LSB), and stop bits

•

The number of "stop bits" programmable for RX and TX is 1 stop bit or 2 stop bits

•

Configurable length of EOF (1-bit to 122-bits)

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Table 6. HSUART baudrates

Bit rate (kBd)

9.6

19.2

38.4

57.6

115.2

230.4

460.8

921.6

1288 K

8.8.2 I

C host interface controller

The PN736X contains one I

C master and one I

C master controller, refer to

Section 8.7.1

C slave controller. This section describes the slave interface used for host communication. For more information on the

The I

C-bus is bidirectional and uses only two wires: a Serial Clock Line (SCL) and a

Serial Data Line (SDA). I

C standard mode (100 kbit/s), fast mode (400 kbit/s and up to 1

Mbit/s), and high-speed mode (3.4 Mbit/s) are supported.

8.8.2.1 I

C host interface features

The PN736X I

C slave interface supports the following features:

•

Support slave I

C bus

•

Standard mode, fast mode (extended to 1 Mbit/s support), and high-speed modes

•

Supports 7-bit addressing mode only

•

Selection of the I

C address done by two pins

–

It supports multiple addresses

–

The upper bits of the I the NXP identifier for I

C slave address are hard-coded. The value corresponds to

C blocks. The value is 0101 0XXb.

•

General call (software reset only)

•

Software reset (in standard mode and fast mode only)

Table 7. I

C interface addressing

C_ADR1 I

C_ADR0 I

C address (R/W = 0, write) I

C address (R/W = 0, read)

0 × 28

0 × 29

0 × 2A

0 × 28

0 × 29

0 × 2A

1 1 0 × 2B 0 × 2B

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8.8.3 SPI host/Slave interface

The PN736X host interface can be used as SPI slave interface.

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The SPI slave controller operates on a four wire SSI: Master In Slave Out (MISO), Master

Out Slave In (MOSI), Serial Clock (SCK), and Not Slave Select (NSS). The SPI slave select polarity is fixed to positive polarity.

8.8.3.1 SPI host interface features

The SPI host/slave interface has the following features:

•

SPI speeds up to 7 Mbit/s

•

Slave operation only

•

8-bit data format only

•

Programmable clock polarity and phase

•

SPI slave select polarity selection fixed to positive polarity

•

Half-duplex in HDLL mode

•

Full-duplex in native mode

If no data is available, the MISO line is kept idle by making all the bits high (0xFF).

Toggling the NSS line indicates a new frame.

Note

: Programmable echo-back operation is not supported.

Table 8. SPI configuration connection

CPHA switch: Clock phase: Defines the sampling edge of MOSI data

•

CPHA = 1: Data are sampled on MOSI on the even clock edges of SCK, after NSS goes low

•

CPHA = 0: Data are sampled on MOSI on the odd clock edges of SCK, after NSS goes low

CPOL switch: Clock polarity

•

IFSEL1 = 0: The clock is idle low, and the first valid edge of SCK is a rising one

•

IFSEL1 = 0: The clock is idle high, and the first valid edge of SCK is a falling one

8.8.4 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and up to 127 peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot-plugging and dynamic configuration of devices. The host controller initiates all transactions. The

PN736X USB interface consists of a full-speed device controller with on-chip PHY

(physical layer) for device functions.

8.8.4.1 Full speed USB device controller

The PN736X embeds a USB device peripheral, compliant with USB 2.0 specification, full speed. It is interoperable with USB 3.0 host devices.

The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, and endpoint buffer memory. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer.

The status of a completed USB transfer or error condition is indicated via status registers.

If enabled, an interrupt is generated.

Following are the USB interface features:

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•

Fully compliant with USB 2.0 specification (full speed)

•

Dedicated USB PLL available

•

Supports 14 physical (7 logical) endpoints including one control endpoint

•

Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types

•

Single or double buffering allowed

•

Support wake-up from suspend mode on USB activity and remote wake-up

•

Soft-connect supported

8.9 Contactless interface - 13.56 MHz

The PN736X embeds a high power 13.56 MHz RF frontend. The RF interface implements the RF functionality like antenna driving, the receiver circuitry, and all the low-level functionalities. It helps to realize an NFC forum or an EMVCo compliant reader.

The PN736X allows different voltages for the RF drivers. For information related to the

RF interface supply, refer Section 8.15

The PN736X uses an external oscillator, at 27.12 MHz. It is a clock source for generating

RF field and its internal operation.

Key features of the RF interface are:

•

ISO/IEC 14443 type A & B compliant

•

MIFARE functionality, including MIFARE classic encryption in read/write mode

•

ISO/IEC 15693 compliant

•

NFC Forum - NFCIP-1 & NFCIP-2 compliant

–

P2P, active and passive mode

–

reading of NFC forum tag types 1, 2, 3, 4, and 5

•

FeliCa

•

ISO/IEC 18000-3 mode 3

•

EMVCo contactless 2.3.1 and 2.5

–

RF level can be achieved without the need of booster circuitry (for some antenna topologies the EMV RF-level compliance might physically not be achievable)

•

Card mode - enabling the emulation of an ISO/IEC 14443 type A card

–

Supports Passive Load Modulation (PLM) and Active Load Modulation (ALM)

•

Low Power Card Detection (LPCD)

•

Adjustable RX-voltage level

A minimum voltage of 2.3 V helps to use card emulation, and P2P passive target functionality in passive load modulation.

A voltage above 2.7 V enables all contactless functionalities.

8.9.1 RF functionality

8.9.1.1 ISO/IEC14443 A/MIFARE functionality

The physical level of the communication is shown in Figure 8

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(1)

ISO/IEC 14443 A

READER

ISO/IEC 14443 A CARD

(2)

001aam268

1. Reader to Card: 100 % ASK; modified miller coded; transfer speed 106 kbit/s to 848 kbit/s

2. Card to Reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s

Figure 8. ISO/IEC 14443 A/MIFARE read/write mode communication diagram

The physical parameters are described in Table 9

Table 9. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer

Communication direction

Signal type Transfer speed

106 kbit/s 212 kbit/s

reader to card (send data from the PN736X to a card) f c

= 13.56 MHz reader side modulation bit encoding

100 % ASK modified miller encoding

100 % ASK modified miller encoding card to reader (PN736X receives data from a card) bit rate (kbit/s) f c

/ 128 card side modulation sub carrier load modulation subcarrier frequency f c

/ 16 bit encoding Manchester encoding f c

/ 64 sub carrier load modulation f c

/ 16

BPSK

424 kbit/s

100 % ASK modified miller encoding f c

/ 32 sub carrier load modulation f c

/ 16

BPSK

848 kbit/s

100 % ASK modified miller encoding f c

/ 16 sub carrier load modulation f c

/ 16

BPSK

Figure 9 shows the data coding and framing according to ISO/IEC 14443 A/MIFARE.

ISO/IEC 14443 A framing at 106 kBd start

8-bit data start bit is 1 odd parity

8-bit data odd parity

ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd start

8-bit data start bit is 0 burst of 32 subcarrier clocks odd parity

8-bit data odd parity

8-bit data even parity even parity at the end of the frame

001aak585

Figure 9. Data coding and framing according to ISO/IEC 14443 A card response

The internal CRC coprocessor calculates the CRC value based on the selected protocol.

In card mode for higher baudrates, the parity is automatically inverted as end of communication indicator.

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8.9.1.2 ISO/IEC14443 B functionality

The physical level of the communication is shown in Figure 10 .

(1)

ISO/IEC 14443 B

READER

ISO/IEC 14443 B CARD

(2)

001aal997

1. Reader to Card: NRZ; transfer speed 106 kbit/s to 848 kbit/s

2. Card to reader: Subcarrier load modulation Manchester coded or BPSK, transfer speed 106 kbit/s to 848 kbit/s

Figure 10. ISO/IEC 14443 B read/write mode communication diagram

The physical parameters are described in Table 10

Table 10. Communication overview for ISO/IEC 14443 B reader/writer

Communication direction

Signal type Transfer speed

106 kbit/s 212 kbit/s

f reader to card (send data from the PN736X to a card) c

= 13.56 MHz reader side modulation

10 % ASK 10 % ASK card to reader (PN736X receives data from a card) bit encoding bit rate [kbit/s] 128/f c card side modulation sub carrier load modulation sub carrier frequency bit encoding

NRZ f c

/ 16

BPSK

NRZ

64/f c sub carrier load modulation f c

/ 16

BPSK

424 kbit/s

10 % ASK

NRZ

32/f c sub carrier load modulation f c

/ 16

BPSK

848 kbit/s

10 % ASK

NRZ

16/f c sub carrier load modulation f c

/ 16

BPSK

8.9.1.3 FeliCa functionality

The FeliCa mode is a general reader/writer to card communication scheme, according to

the FeliCa specification. The communication on a physical level is shown in Figure 11 .

FeliCa READER

(PCD)

1. PCD to PICC 8-30 % ASK

Manchester Coded, baudrate 212 to 424 kbaud

2. PICC to PCD, > Load modulation

Manchester Coded, baudrate 212 to 424 kbaud

Figure 11. FeliCa read/write communication diagram

The physical parameters are described in Table 11

FeliCa CARD

(PICC)

001aam271

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Table 11. Communication overview for FeliCa reader/writer

Communication direction

Signal type Transfer speed FeliCa FeliCa higher transfer speeds

212 kbit/s 424 kbit/s

reader to card (send data from the PN736X to a card) f c

= 13.56 MHz card to reader (PN736X receives data from a card) reader side modulation bit encoding bit rate card side modulation bit encoding

8 % to 30 % ASK

Manchester encoding f c

/ 64 load modulation

Manchester encoding

8 % to 30 % ASK

Manchester encoding f c

/ 32 load modulation

Manchester encoding

Note

: The PN736X does not manage FeliCa security aspects.

PN736X supports FeliCa multiple reception cycles.

PayLoad XXX Status

32 byte

RFU [31:24] RFU [23:16]

RFU

[15:13]

RFU

[7:5]

Len [4:0]

4 byte

aaa-021253

Figure 12. Multiple reception cycles - data format

8.9.1.4 ISO/IEC 15693 functionality

The physical level of the communication is shown in Figure 13 .

ISO / IEC 15693

READER

(1)

(2)

ISO / IEC 15693

CARD

aaa-021138

1. Reader to Card: 1/256 and 1/4 encoding

2. Card to Reader: Manchester coding

Figure 13. ISO/IEC 15693 read/write mode communication diagram

The physical parameters are described in Table 12

Table 12. Communication overview for ISO/IEC 15693 reader to label

Communication direction

Signal type f

Transfer speed c

/ 8192 kbit/s

reader to label (send data from the PN736X to a card) reader side modulation 10 % to 30 % ASK or

100 % ASK bit encoding bit length

1/256

4.833 μs

f c

/ 512 kbit/s

10 % to 30 % ASK or 90 % to

100 % ASK

1/4

302.08 μs

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Table 13. Communication overview for ISO/IEC 15693 label to reader

Communication direction

Signal type Transfer speed

6.62 kbit/s 13.24 kbit/s

[1]

label to reader

(PN736X receives data from a card) f

= 13.56 MHz c card side modulation not supported not supported bit length (μs) bit encoding subcarrier frequency (MHz)

[1] Fast inventory (page) read command only (ICODE proprietary command).

26.48 kbit/s

single (dual) sub carrier load modulation ASK

52.96 kbit/s

single sub carrier load modulation ASK

37.76

18.88

Manchester coding Manchester coding f c

/ 32 f c

/ 32 pulse modulated carrier

~9.44 µs

~18.88 µs

0 1 2 3 4 .

. 2 . . .

. . . .

~4,833 ms

. . . . .

2 2

5 5

4 5

001aam272

Figure 14. Data coding according to ISO/IEC 15693 standard mode reader to label

8.9.1.5 ISO/IEC18000-3 mode 3 functionality

The ISO/IEC 18000-3 mode 3 is not described in this document. For a detailed explanation of the protocol, refer to the ISO/IEC 18000-3 standard.

PN736X supports the following features:

•

TARI = 9.44 μs or 18.88 μs

•

Downlink: Four subcarrier pulse Manchester and two subcarrier pulse Manchester

•

Subcarrier: 423 kHz (f c

/ 32) with DR = 0 kHz and 847 kHz (f c

/ 16) with DR = 1

8.9.1.6 NFCIP-1 modes

The NFCIP-1 communication differentiates between an active and a passive communication mode.

•

In active communication mode, both initiator and target use their own RF field to transmit data

•

In passive communication mode, the target answers to an initiator command in a load modulation scheme. The initiator is active in terms of generating the RF field

•

The initiator generates RF field at 13.56 MHz and starts the NFCIP-1 communication

•

In passive communication mode, the target responds to initiator command in load modulation scheme. In active communication mode, it uses a self-generated and selfmodulated RF field.

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PN736X supports NFCIP-1 standard. PN736X supports active and passive communication mode at transfer speeds of 106 kbit/s, 212 kbit/s, and 424 kbit/s, as defined in the NFCIP-1 standard.

Initial command host

NFC INITIATOR NFC TARGET host powered to generate RF field host

NFC INITIATOR powered for digital processing

1. initiator starts communication at selected transfer speed response powered for digital processing

NFC TARGET host

2. target answers at the same transfer speed powered to generate RF field

001aan216

Figure 15. Active communication mode

Table 14. Communication overview for active communication mode

Communication direction

Transfer speed

106 kbit/s 212 kbit/s

initiator to target target to initiator according to ISO/IEC 14443

A 100 % ASK, modified miller coded according to

FeliCa, 8-30 %

ASK Manchester coded

424 kbit/s

according to

FeliCa, 8-30 %

ASK Manchester coded

Note

: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.

1. initiator starts communication at selected transfer speed host

NFC INITIATOR NFC TARGET host powered to generate RF field

2. targets answers using load modulated data at the same transfer speed powered for digital processing

001aan217

Figure 16. Passive communication mode

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Table 15. Communication overview for passive communication mode

Communication direction

Transfer speed

106 kbit/s 212 kbit/s 424 kbit/s

initiator to target according to ISO/IEC

14443 A 100 % ASK, modified miller coded according to

FeliCa, 8-30 % ASK

Manchester coded according to

FeliCa, 8-30 % ASK

Manchester coded target to initiator according to ISO/IEC

14443 A @106 kB modified miller coded according to FeliCa, >

12 % ASK Manchester coded according to FeliCa, >

12 % ASK Manchester coded

The NFCIP-1 protocol is managed in the PN736X customer application firmware.

Note

: Transfer speeds above 424 kbit/s are not defined in the NFCIP-1 standard.

ISO/IEC14443 A card operation mode

PN736X can be addressed as a ISO/IEC 14443 A card. It means that PN736X can generate an answer in a load modulation scheme according to the ISO/IEC 14443 A interface description.

Note

: PN736X components do not support a complete card protocol. The PN736X customer application firmware handles it.

The following table describes the physical layer of a ISO/IEC14443 A card mode:

Table 16. ISO/IEC14443 A card operation mode

Communication direction ISO/IEC 14443 A (transfer speed: 106 kbit per second)

reader/writer to PN736X modulation on reader side 100 % ASK

PN736X to reader/writer bit coding modified miller bit length 128/f c modulation on PN736X side sub carrier load modulation subcarrier frequency bit coding f c

/ 16

Manchester coding

NFCIP-1 framing and coding

The NFCIP-1 framing and coding in active and passive communication mode is defined in the NFCIP-1 standard.

PN736X supports the following data rates:

Table 17. Framing and coding overview

Transfer speed Framing and coding

106 kbit/s according to the ISO/IEC 14443 A/MIFARE scheme

212 kbit/s

424 kbit/s according to the FeliCa scheme according to the FeliCa scheme

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NFCIP-1 protocol support

The NFCIP-1 protocol is not elaborated in this document. The PN736X component does not implement any of the high-level protocol functions. These high-level protocol functions are implemented in the microcontroller. For detailed explanation of the protocol, refer to the NFCIP-1 standard. However, the datalink layer is according to the following policy:

•

Speed shall not be changed while there is continuous data exchange in a transaction.

•

Transaction includes initialization, anticollision methods, and data exchange (in a continuous way means no interruption by another transaction).

In order not to disturb current infrastructure based on 13.56 MHz, the following general rules to start NFCIP-1 communication are defined:

1. By default, NFCIP-1 device is in target mode. It means that its RF field is switched off.

2. The RF level detector is active.

3. Only if the application requires, the NFCIP-1 device switches to initiator mode.

4. An initiator shall only switch on its RF field if the RF level detector does not detect external RF field during a time of T

IDT

5. The initiator performs initialization according to the selected mode.

8.9.2 Contactless interface

8.9.2.1 Transmitter (TX)

The transmitter is able to drive an antenna circuit connected to outputs TX1 and TX2 with a 13.56 MHz carrier signal. The signal delivered on pins TX1 and pin TX2 is a 13.56

MHz carrier, modulated by an envelope signal for energy and data transmission. It can be used to drive an antenna directly, using a few passive components for matching and filtering. For a differential antenna configuration, either TX1 or TX2 can be configured to put out an inverted clock.

100 % modulation and several levels of amplitude modulation on the carrier can be performed to support 13.56 MHz carrier-based RF-reader/writer protocols. The standards

ISO/IEC14443 A and B, FeliCa and ISO/IEC18092 define the protocols.

The PN736X embeds an overshoot and undershoot protection. It is used to configure additional signals on the transmitter output, for controlling the signal shape at the antenna output.

envelope

TVDD clk_highside hs_gate

TVDD

TX1 clk_lowside ls_gate<14:0>

M1<

PRE-DRIVERS

aaa-021254

Figure 17. PN736X output driver

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8.9.2.2 Receiver (RX)

In reader mode, the response of the PICC device is coupled from the PCB antenna to the differential input RXP/RXN. The reader mode receiver extracts this signal by first removing the carrier in passive mixers (direct conversion for I and Q). It then filters and amplifies the baseband signal before converting to digital values. The conversion to digital values is done with two separate ADCs, for I and Q channels. Both I and Q channels have a differential structure, which improves the signal quality.

The I/Q mixer mixes the differential input RF-signal down to the baseband. The mixer has a bandwidth of 2 MHz.

The down-mixed differential RX input signals are passed to the BBA and a band-pass filter. For considering all the protocols (type A/B, FeliCa), the high-pass cut-off frequency of BBA is configured between 45 kHz and 250 kHz. The configuration is done in four different steps. The low-pass cut-off frequency is greater than 2 MHz.

The output of band-pass filter is further amplified with a gain factor which is configurable between 30 dB and 60 dB. The baseband amplifier (BBA)/ADC I-channel and Q-channel can be enabled separately. It is required for ADC-based card mode functionality as only the I-channel is used in this case.

BBA

RXP

DATA

VMID

AGC

I-CLK

MIX

CLK

Q-CLK

BBA

RXN

DATA

aaa-021388

Figure 18. Receiver block diagram

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VMID

A resistive divider between AVDD and GND generates VMID. The resistive divider is connected to the VMID pin. An external blocking capacitor of typical value 100 nF is connected.

Automatic Gain Control (AGC)

The contactless interface AGC is used to control the amplitude of 13.56 MHz sine-wave input signal received. The signal is received at the antenna connected between the pins

RXP and RXN. A comparator is used to compare the peak value of the input signal with a reference voltage.

A voltage divider circuit is used to generate the reference voltage. An external resistor

(typically 3.3 kΩ) is connected to the RX input, which forms a voltage divider with an onchip variable resistor. The voltage divider circuit so formed has a 10-bit resolution.

Note:

The comparator monitors the RXP signal only.

By varying the on-chip resistor, the amplitude of the input signal can be modified. The value of on-chip resistor is increased or decreased, depending on the output of the sampled comparator. The on-chip resistor value is adjusted until the peak of the input

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signal matches the reference voltage. Thus, the AGC circuit automatically controls the amplitude of the RX input.

The internal amplitude controlling resistor in the AGC has a default value of 10 KΩ. It means that, when the resistor control bits in AGC_VALUE_REG <9:0> are all 0, the resistance is 10 KΩ. As the control bits are increased, resistors are switched in parallel to the 10 KΩ resistor. It lowers the resultant resistance value to 5 kΩ (AGC_VALUE_REG

<9:0>, all bits set to 1).

Mode detector

The mode detector is a functional block of the PN736X which senses for an RF field generated by another device. The mode detector facilitates to distinguish between type

A and FeliCa target mode. The host responds depending on the recognized protocol generated by an initiator peer device.

Note

: The PN736X emulates type A cards and peer-to-peer active target modes according to ISO / IEC18092.

8.9.3 Low-Power Card Detection (LPCD)

The low-power card detection is an energy saving feature of the PN736X. It detects the presence of a card without starting a communication. Communication requires more energy to power the card and takes time, increasing the energy consumption.

It is based on antenna detuning detection. When a card comes close to the reader, it affects the antenna tuning, which is detected by PN736X.

The sensitivity can be varied for adjusting to various environment and applications constraints.

Remark: Reader antenna detuning may have multiple sources such as cards and metal near the antenna. Hence it is important to adjust the sensitivity with care to optimize the detection and power consumption. As the generated field is limited, distance for card detection might be reduced compared to normal reader operation. Performances depend on the antenna and the sensitivity used.

8.9.4 Active Load Modulation (ALM)

When PN736X is used in card emulation mode or P2P passive target mode, it modulates the field emitted by the external reader or NFC passive initiator.

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PN7462AU

CARD TYPE A EMULATION

P2P PASSIVE TARGET

(1)

(2)

aaa-021139

1. Type A reader or NFC passive initiator generate the RF and sends commands

2. PN736X modulates the field of reader for sending its answer

Figure 19. Communication in card emulation of NFC passive target

To modulate the field, PN736X offers two possibilities:

•

Passive Load Modulation (PLM): The PN736X modifies the antenna characteristics, which are detected by the reader through antenna coupling.

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•

Active Load Modulation (ALM): The PN736X generates a small field, in phase opposition with the field emitted by the reader. This modulation is detected by the reader reception stage.

The modulation type to use depends on the external reader and the antenna of PN736X and the application.

8.9.5 Dynamic Power Control (DPC)

The PN736X supports the Dynamic Power Control (DPC) feature.

A lookup table is used to configure the output voltage and to control the transmitter current. In addition to the control of the transmitter current, wave shaping settings can be controlled as well, depending on the selected protocol and the measured antenna load.

8.9.5.1 RF output control

The DPC controls the RF output current and output voltage depending on the loading condition of the antenna.

8.9.5.2 Adaptive Waveform Control (AWC)

The DPC includes the Adaptive Waveform Control (AWC) feature.

Depending on the level of detected detuning on the antenna, RF wave shaping related register settings can be automatically updated, according to the selected protocol. A lookup table is used to configure the modulation index, the rise time and the fall time.

8.10 Timers

The PN736X includes two 12-bit general-purpose timers (on LFO clock domain) with match capabilities. It also includes two 32-bit general-purpose timers (on HFO clock domain) and a Watchdog Timer (WDT).

The timers and WDT can be configured through software via a 32-bit APB slave interface.

Table 18. Timer characteristics

Name Clock source

Frequency Counter length

Timer 0

Timer 1

Timer 2

Timer 3

LFO/2

HFO

182.5 kHz 12 bit

20 MHz

32 bit

Watchdog LFO/128 2.85 kHz 10 bit

Resolutio n

300 μs

50 ns

21.5 ms

Maximum delay

1.2 s

214 s

22 s

Chaining

Yes

8.10.1 Features of timer 0 and timer 1

•

12-bit counters

•

One match register per timer, no capture registers and capture trigger pins are needed

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•

One common output line gathering the four timers (Timer 0, Timer 1, Timer 2, and

Timer 3)

•

Interrupts

•

Timer 0 and timer 1 can be concatenated (multiplied)

•

Timer 0 and timer 1 have two count modes: single-shot or free-running

•

Timer 0 and timer 1 timeout interrupts can be individually masked

•

Timer 0 and timer 1 clock source is LFO clock (LFO/2 = 182.5 kHz)

Remark:

The timers are dedicated for RF communication.

8.10.2 Features of timer 2 and timer 3

•

32-bit counters

•

1 match register per timer, no capture registers and capture trigger pins are needed

•

1 common output line gathering four timers (Timer 0, Timer 1, Timer 2, and Timer 3)

•

Interrupts

•

Timer 2 and timer 3 have two count modes: single-shot and free-running

•

Timer 2 and timer 3 timeout interrupts can be individually masked

•

Timer 2 and timer 3 clock source is the system clock

8.11 System tick timer

The PN736X microcontroller includes a system tick timer (SYSTICK) that generates a dedicated SYSTICK exception at a fixed time interval (10 ms).

8.12 Watchdog timer

If the microcontroller enters an erroneous state, the watchdog timer resets the microcontroller. When the watchdog timer is enabled, if the user program fails to

"feed" (reload) the watchdog timer within a predetermined time, it generates a system reset.

The watchdog timer can be enabled through software. If there is a watchdog timeout leading to a system reset, the timer is disabled automatically.

•

10-bit counter

•

Based on a 2.85 kHz clock

•

Triggers an interrupt when a predefined counter value is reached

•

Connected to the ARM subsystem NMI (non-maskable interrupt)

•

If the watchdog timer is not periodically loaded, it resets PN736X

8.13 Clocks

The PN736X clocks are based on the following clock sources:

•

27.12 MHz external quartz

•

27.12 MHz crystal oscillator

•

Internal oscillator: 20 MHz High Frequency Oscillator (HFO)

•

Internal oscillator: 365 kHz Low Frequency Oscillator (LFO)

•

Internal PLL at 48 MHz for the USB interface

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XTAL1

XTAL2

Figure 20

indicates the clocks used by each IP.

PLL I/P

BUFFER

PLL_INPUT_BUFFER_BYPASS

XTAL_SEL_EXTERNAL_CLOCK clif_pll_in_sel dk_input_buffer clk_xtal tie `'0'' tie `'0''

11 pll_clkin

CLIF_PLL_REF_CLK_SELECT[1:0]

CLIF PLL pll_bypass pll_clkout

10 pll_clkout2

00 pll_clkin

11 pll_clkout2

CLIF_DIG clk_pll_27m12

CLIF_ANA clk_xtal

XTAL

CLIF_PLL_CLOCK_SELECT[1:0] usb_pll_in_sel tie `'0'' tie `'0'' clk_xtal clk_input_buffer

00 usb_pll_clkin

USB_PLL_REF_CLK_SELECT[1:0]

USB PLL clk_usb_48 MHz

00 tie `'0''

01 tie `'0''

USB_PLL_CLKOUT_SELECT[1:0]

Figure 20. Clocks and IP overview

usb_pll_clkout

PCR clk_pll_27m12

1 clk_ip_27m12 usb_pll_clkin

PCR_CLK_CFG2.EXT_CLK_SEL

/2 usb_pll_clkout_div2

aaa-021248

8.13.1 Quartz oscillator (27.12 MHz)

The 27.12 MHz quartz oscillator is used as a reference for all operations where the stability of the clock frequency is important for reliability. It includes contactless interface,

SPI and I

C master interfaces, USB PLL for the USB interface, and HSUART.

Regular and low-power crystals can be used. Figure 21 shows the circuit for generating

stable clock frequency. The quartz and trimming capacitors are off-chip.

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PN7462AU

XTAL1 crystal

27.12 MHz

XTAL2

C C

aaa-021140

Figure 21. Crystal oscillator connection

Table 19

describes the levels of accuracy and stability required on the crystal.

Table 19. Crystal requirements

Symbol Parameter

f xtal crystal frequency

Δf xtal crystal frequency accuracy

Conditions

ISO/IEC and FCC compliancy

Min

[1]

-50

Typ

27.12

Max

+50

Unit

MHz ppm

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Symbol Parameter

ESR

P drive equivalent series resistance load capacitance drive power

Conditions Min Typ Max Unit

100

Ω pF

μW

[1] This requirement is according to FCC regulations requirements. The frequency should be +/- 14 kHz to meet ISO/IEC

14443 and ISO/IEC 18092.

8.13.2 USB PLL

The PN736X integrates a dedicated PLL to generate a low-noise 48 MHz clock, by using the 27.12 MHz from the external crystal. The 48 MHz clock generated is used as the

USB main clock.

Following are the USB PLL features:

•

Low-skew, peak-to-peak cycle-to-cycle jitter, 48 MHz output clock

•

Low power in active mode, low power-down current

•

On-chip loop filter, external RC components not needed

8.13.3 High Frequency Oscillator (HFO)

The PN736X has an internal low-power High Frequency Oscillator (HFO) that generates a 20 MHz clock. The HFO is used to generate the system clock. The system clock default value is 20 MHz, and it can be configured to 10 MHz and 5 MHz for reducing power consumption.

8.13.4 Low Frequency Oscillator (LFO)

The PN736X has an internal low-power Low Frequency Oscillator (LFO) that generates a 365 kHz clock. The LFO is used by EEPROM, POR sequencer, contactless interface, timers, and watchdog.

8.13.5 Clock configuration and clock gating

In order to reduce the overall power consumption, the PN736X facilitates adjustment of system clock. It integrates clock gating mechanisms.

The system clock can be configured to the following values: 20 MHz, 10 MHz, and 5

MHz.

The clock of the following blocks can be activated or deactivated, depending on the peripherals used:

•

Contactless interface

•

Host interfaces

C master interface

•

SPI master interface

•

CRC engine

•

Timers

•

Random generator

•

System clock

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•

EEPROM

•

Flash memory

8.14 Power management

8.14.1 Power supply sources

The PN736X is powered using the following supply inputs:

•

VBUS: main supply voltage for internal analog modules, digital logic and memories

•

TVDD_IN: supply for the contactless interface

•

PVDD_IN: pad voltage reference and supply of the host interface (HSU, USB, I

SPI) and the GPIOs

C, and

•

PVDD_M_IN: pad voltage reference and supply for the master interface (SPI and I

•

DVDD: supply for the internal digital blocks

8.14.2 PN736X Power Management Unit (PMU)

The integrated Power Management Unit (PMU) provides supply for internal analog modules, internal digital logic and memories, pads. It also provides supply voltages for the contactless interface.

It automatically adjusts internal regulators to minimize power consumption during all possible power states.

The power management unit embeds a mechanism to prevent the IC from overheat, overconsumption, or overloading the DC-to-DC converter:

•

TXLDO 5 V monitoring

•

Temperature sensor

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Digital logic and memories

MILDO internal analog blocks

DVDD

VDD mandatory

VBUS

PVDD_LDO pad supply

TX_LDO master interface pads

PVDD_OUT

PVDD_IN

PVDD_M_IN optional

TVDD_OUT VUP_TX

TVDD_IN

RF transmitter

aaa-025627

Figure 22. PN736X LDOs and power pins overview

PN736X embeds five Low Drop-Out regulators (LDO) for ensuring the stability of power supply, while the application is running.

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•

MLDO (main LDO): It provides1.8 V supply for internal analog, digital and memory modules

•

TXLDO: This LDO can be used to supply the RF transmitter

•

PVDD_LDO: PVDD_LDO provides 3.3 V that can be used for all pads supply

Some are used while some are optional, like the TX_LDO which is proposed for the RF interface. It is up to the application designer to decide whether LDOs should be used.

8.14.2.1 Main LDO

The Main LDO (MLDO) provides a 1.8 V supply for all internal, digital and memory modules. It takes input from VBUS. MLDO includes a current limiter that avoids damage to the output transistors.

Output supply is available on VDD pin which must be connected externally to the DVDD pin.

Following are the main LDO features:

•

Main Low-Drop-Out (MLDO) voltage regulator powered by VBUS (external supply)

•

Current limiter to avoid damaging the output transistors

8.14.2.2 PVDD_LDO

The PVDD_LDO provides 3.3 V supply, that can be used for all digital pads. It may also be used to provide 3.3 V power to external components, avoiding an external LDO. It is supplied by VBUS, and requires a minimum voltage of 4 V to be functional. It delivers a maximum of 30 mA.

The output pin for PVDD_LDO is PVDD_OUT.

PVDD_LDO is used to provide the necessary supply to PVDD_IN and PVDD_M_IN (pad supply for master interfaces).

When an external supply is used, PVDD_OUT must be connected to the ground.

When the LDO output is connected to the ground, the PN736X chip switches off the

PVDD_LDO.

The PVDD_LDO has a low-power mode, which is used automatically by the PN736X when the chip is in standby mode or suspend mode. It facilitates supply to HOST pads and GPIOS, and to detect wake-up signals coming from these interfaces.

Following are the PVDD_LDO features:

•

Low-Drop-Out voltage regulator powered by V

DDP(VBUS)

(external supply)

•

Supports soft-start mode to limit inrush current during the initial charge of the external capacitance when the LDO is powered up

•

Current limiter to avoid damaging the output transistors

Note

: When PVDD_LDO is used, there must not be any load current drawn from

PVDD_LDO during the soft start of the PVDD_LDO.

8.14.2.3 TXLDO

The PN736X consists of an internal transmitter supply LDO. The TXLDO can be used to maintain a constant output voltage for the RF interface.

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The TXLDO is designed to protect the chip from voltage ripple introduced by the power supply on the pin VUP_TX. It is powered through the pin VUP_TX.

The programmable output voltages are: 3.0 V, 3.3 V, 3.6 V, 4.5 V, and 4.75 V.

For a given output voltage, VUP_TX shall always be higher than 0.3 V. In other words, to supply a 3 V output, the minimum voltage to be applied on VUP_TX is 3.3 V. If the voltage is not sufficient, then the voltage at the pin TVDD_OUT follows the voltage at the pin VUP_TX, lowered of 0.3 V.

When it is not used, TVDD_OUT shall be connected to TVDD_IN, and TX_LDO shall be turned off.

Following are the TXLDO features:

•

Low-Drop-Out (TXLDO) voltage regulator

•

Current load up to 180 mA

•

Supports soft-start mode to limit inrush current during the initial charge of the external capacitance

•

Current limiter to avoid damaging the output transistors

8.14.3 Power modes

The PN736X offers four different power modes, that enable the user to optimize its energy consumption. They are:

•

Hard power-down mode

•

Standby mode

•

USB suspend mode

•

Active mode

8.14.3.1 Active mode

In active mode, all functionalities are available and all IPs can be accessed. It is possible to configure the various clocks (IP clock, system clock) using register settings so that chip consumption is reduced. If IPs are not used, they can be disabled.

8.14.3.2 Standby mode

In standby mode, only a reduced part of the digital and the analog is active. It reduces the chip power consumption. The possible wake-up sources are still powered.

The LFO clock is used to lower the energy needs.

Active part in standby mode

: Main LDO is active, in a low-power mode, plus all configured wake-up sources.

Depending on the application requirements, it is possible to configure PVDD_LDO in active mode, low-power mode or shut down mode when PN736X is going to standby mode. PVDD_LDO is active in a low-power mode by default.

Entering in standby mode

: The application code triggers standby mode.

The PN736X has two internal temperature sensors. If these sensors detect an overheat, the PN736X is put into standby mode by the application firmware. The chip leaves the standby mode when both temperature sensors indicate that the temperature has come below the configured limit.

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Limitations

: Standby mode is not possible in the following cases:

•

A host communication is in progress

•

A wake-up condition is fulfilled. For example, external RF field presence is a wake-up source, and PN736X detects a field

•

The RF field detector is a possible wake-up source, and the RF field detector is disabled

•

PVDD is

not

present

8.14.3.3 Suspend mode

In suspend mode, clock sources are stopped except LFO. It reduces the chip power consumption.

Entering in suspend mode

: An interrupt indicates to the application firmware when no activity has been detected on the USB port for more that 3 ms. The application code triggers the suspend mode.

Limitations

: Suspend mode is prevented in the following cases:

•

A host communication is in progress

•

A wake-up condition is fulfilled. For example, external RF field presence is a wake-up source, and PN736X detects a field

•

The RF field detector is a possible wake-up source, and the RF field detector is disabled

•

No voltage at pin PVDD

8.14.3.4 Wake-up from standby mode and suspend mode

PN736X can be woken-up from standby mode, and suspend mode, using the following means:

•

Host Interface: SPI, HSUART, I

(SPI, HSUART, and I

C, and USB if already selected before standby mode

C) or suspend mode (USB).

•

RF field detection (presence of a reader or an NFC device in reader mode or P2P initiator)

•

GPIO

•

Wake-up counter, for example to timely check for the presence of any contactless card

•

Current overconsumption on the PVDD_OUT, voltage above 5 V on TVDD_IN

•

Temperature sensor: When the PN736X goes in to standby mode because of overheating, and when the temperature goes below the sensor configured value, PN736X wakes-up automatically. Each temperature sensor can be configured separately.

It is possible to configure the sources as enabled or disabled.

8.14.3.5 Hard Power-Down (HPD) mode

The PN736X Hard Power-Down (HPD), reduces the chip power consumption, by powering down most of the chip blocks. All clocks and LDOs are turned off, except the main LDO which is set in low-power mode.

Entering in HPD mode

: If the RST_N pin is set to low, the PN736X enters in to Hard

Power Down (HPD) mode. It also enters in to HPD mode if the V

DDP(VBUS)

goes below the critical voltage necessary for the chip to work (2.3 V) and the auto HPD feature is enabled.

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Exiting the HPD mode

: The PN736X leaves the HPD mode, when both RST_N pin is set to high level and the V

DDP(VBUS)

voltage is above 2.3 V.

8.14.4 Voltage monitoring

The voltage monitoring mode detects whether the voltage is within the operational conditions to enable a proper operation of the RF interface. The following power supplies are monitored: VBUS (two voltage monitors), VBUS_P (one voltage monitor).

Section 9.1.2

discusses about the minimum voltages necessary for contactless interface operation.

Table 20. Threshold configuration for voltage monitor

Voltage monitor Threshold 1 Threshold 2

VBUSMON1

VBUSMON2

2.3 V

2.7 V

4.0 V

VBUSP 2.7 V 3.0 V

Threshold 3

n.a.

[1]

n.a.

[1]

3.9 V

[1] n.a. means not applicable.

8.14.4.1 VBUS monitor

The PN736X includes up to two levels (2.3 V or 2.7 V) for monitoring the voltage on the VBUS pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the PCR. This signal may be enabled for interrupt in the interrupt enable register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Two threshold levels (2.3 V or 2.7 V) can be selected to cause a forced Hard Power-Down (HPD) of chip.

8.14.4.2 VBUSP monitor

The PN736X includes three levels (2.7 V, 3.0 V, and 3.9 V) for monitoring the voltage on the VBUSP pin.

8.14.4.3 PVDD LDO supply monitor

The PN736X includes up to two levels (VBUSMON2: 2.7 V or 4.0 V) for monitoring the voltage on the PVDD LDO input supply. If supply voltage is 4.0 V or above, PVDD

LDO can be enabled. The software has to check whether the voltage is sufficient before enabling the LDO.

8.14.5 Temperature sensor

The PN736X power management unit provides temperature sensors, associated to the

TX_LDO. It detects problems that would result in high power consumption and heating, which could damage the chip and the user device.

Triggering levels are configurable. Following temperatures can be chosen: 135 °C, 130

°C, 125 °C, and 120 °C. By default, the temperature sensor is set to 120 °C.

When one of the temperature sensors detects an increase in temperature above the configured level, an interrupt is generated. The application can then decide to go

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into standby or suspend mode. The PN registers indicate which temperature sensor generated the interrupt.

When the temperature goes below the configured threshold temperature, PN736X wakes up automatically.

8.15 System control

8.15.1 Reset

PN736X has six possible sources for reset. The list of sources is described in

Table 21

Table 21. Reset sources

Source Description

software - PCR soft reset from the PCR peripheral software - ARM

C interface watchdog

VBUS voltage software reset form the ARM processor

C Standard 3.0 defines a method to reset the chip via an I

C command

[1]

reset the chip if the watchdog threshold is not periodically reloaded power-on reset sequence; if the voltage is above 2.3 V, reset the chip

[1] This feature can be disabled.

The watchdog reset, I

C reset and soft resets from PCR and ARM processor resets the chip except the PCR and the ARM debug interface. The Power-On Reset (POR) resets the complete chip including the PCR and ARM debug interface.

Upon reset, the processor executes the first instruction at address 0, which is initially the reset vector mapped from the boot block. At that point, all the processor and peripheral registers are initialized to predetermined values.

8.15.2 Brown-Out Detection (BOD)

The PN736X includes up to two levels for monitoring the voltage on the VBUS pin. If this voltage falls below one of the selected voltages (2.3 V or 2.7 V), the BOD asserts an interrupt signal to the PCR. This signal can be enabled for interrupt in the interrupt enable register in the PCR, to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. Two threshold levels (2.3 V and 2.7 V) can be selected to cause a forced Hard Power-Down (HPD) of the chip.

8.15.3 APB interface and AHB-Lite

All APB peripherals are connected to one APB bus.

The AHB-Lite connects the AHB masters. The AHB masters include the CPU bus of the

ARM Cortex-M0, host interface, contactless interface, SPI interface to the flash memory.

It also includes EEPROM memory, SRAM, ROM, and AHB to APB bridge.

8.15.4 External interrupts

PN736X enables the use of 12 GPIOs as edge or level sensitive inputs (GPIO1 to

GPIO12).

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8.16 SWD debug interface

The Cortex-M0 processor-based devices use serial wire ARM CoreSight

Debug technology. The PN736X is configured to support four break points and two watch points.

The SWD interface can be disabled for having code (or data) read/write access protection. A dedicated SWD disable bit is available in the protected area of the

EEPROM memory. Once the SWD interface is disabled, it is not possible to enable it anymore.

8.16.1 SWD interface features

•

Run control of the processor allowing to start and stop programs

•

Single step one source or assembler line

•

Set breakpoints while the processor is running

•

Read/write memory contents and peripheral registers on-the-fly

•

"Printf" like debug messages through the SWD interface

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9 Application design-in information

9.1 Power supply connection

The following table indicates the power sources for all the PN736X power inputs.

Table 22. Power supply connection

Power inputs

Power sources

VBUS external source

Comment

VBUSP

TVDD_IN

PVDD_IN external source; connected to

VBUS external supply or using the

TX_LDO external supply or using

PVDD_LDO

PVDD_M_IN external supply or using

PVDD_LDO

DVDD connected to the VDD output chosen according to the expected performances

(RF power when TX_LDO is used, global power consumption)

VBUSP is connected to VBUS, with the addition of a decoupling capacitor external supply can be used (up to 5.5 V) to increase RF power

PVDD_LDO can be used, when V

DDP(VBUS)

> 4

V. It makes a regulated 3.3 V supply available to GPIO and host interface pads, without the addition of an external LDO for 1.8 V, external supply is used

PVDD_LDO can be used, when V

DDP(VBUS)

> 4

V. It makes a regulated 3.3 V supply available to GPIO and host interface pads, without the addition of an external LDO external supply is used for 1.8 V

VDD provides 1.8 V stabilized supply, out of the

MAIN_LDO

1. When external supply and PVDD_OUT are not used, PVDD_OUT must be connected to the ground, with a ground resistance of less than 10 Ω.

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9.1.1 Powering up the microcontroller

(1)

GND

TVSS

GNDC

GNDP

VBUS

VBUSP

PN7462AU

VDD

DVDD

DDP(VBUS)

1 µF

(2)

VBUS

VBUSP

(3)

DDP(VBUS)

1 µF

VBUS

VBUSP

DDP(VBUS)

1 µF

PN7462AU

PVDD_OUT

PVDD_IN

PVDD_M_IN

1 µF

PN7462AU

PVDD_OUT

PVDD_IN

PVDD_M_IN external supply

1 µF

aaa-025630

1. Powering up the microcontroller and the digital blocks (DVDD).

2. Two possibilities for powering the pad interfaces (PVDD_IN and PVDD_M_IN).

Remark:

The capacitance must be chosen so that the capacitance value is correct at 5 V

Figure 23. Powering up the PN736X microcontroller

The schematics in

Figure 23

describe the power supply of the chip (V

DDP(VBUS)

), including the digital blocks supply (DVDD). It indicates two possibilities to supply the pads, using the internal LDO, or using an external supply. The internal LDO requires that

DDP(VBUS)

> 4 V. It avoids the requirement of a separate LDO when V sufficient voltage.

DDP(VBUS)

has a

Power supply is available to pads through PVDD_IN (host interface). Similarly, power supply is available to master interface pads through PVDD_M_IN. When PVVD _LDO is used, maximum total current available from PVDD_OUT for the pads supply is 30 mA.

When an external source is used for PVDD_IN and PVDD_M_IN, PVDD_OUT must be connected to the ground, with a ground resistance of less than 10 Ω.

9.1.2 Powering up the contactless interface

Powering of contactless interface is done though TVDD_IN. Internal LDO (TXLDO) or external supply can be used.

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(1)

VBUS antenna supply

TX2

TX1

PN7462AU

VUP_TX

TVSS

TVDD_OUT

TVDD_IN

(2)

PN7462AU

supply

470 nF

VBUS antenna supply

TX2

TX1

PN7462AU

VUP_TX

TVSS

TVDD_OUT

TVDD_IN

6.8 µF

PN7462AU

470 nF supply

6.8 µF

aaa-021143

The capacitance value must be chosen so that the capacitance value is correct at 5 V.

1. Using TXLDO

2. Without using TXLDO

Figure 24. Powering up the contactless interface using a single power supply

antenna supply

(1)

TX2

TX1

PN7462AU

VBUS

PN7462AU

supply

470 nF

VUP_TX

1 µF

PN7462AU

RF transmitter supply antenna supply

TVDD_OUT

(2)

VBUS

TX2

TX1

PN7462AU

VUP_TX

PN7462AU

supply

470 nF

TVDD_OUT

TVSS

TVDD_IN

6.8 µF

TVSS

TVDD_IN

6.8 µF

PN7462AU

RF transmitter supply

aaa-021144

The capacitance value must be chosen so that the capacitance value is correct at 5 V.

1. Using TXLDO.

2. Without using TXLDO.

Figure 25. Powering up the contactless interface using an external RF transmitter supply

Note:

The TVDD_OUT pin must not be left floating. It should be at the same voltage as the TVDD_IN pin.

The power design must be designed properly to be able to deliver a clean power supply voltage.

In any case (external TVDD or internal TX_LDO internal supply), TVDD_IN supply must be stable before turning on the RF field. The capacitor shall be 6.8 μF or higher (up to 10

μF)

Every noise level on top of the supply voltage can disturb the RF communication performance of the PN736X. Therefore, special attention must be paid to the filtering circuit.

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When powering up the device through the USB interface, TVDD capacitor value shall be chosen so that the maximum capacitance on VBUS remains as per the USB specification.

9.2 Connecting the USB interface

PN7462AU

USB_VBUS

USB_DP

USB_DM

Cp = 10 nF(1)

Rs = 1 kΩ

USB connector

PN736X

Product data sheet

COMPANY PUBLIC

aaa-021147

1. C p

is optional.

Figure 26. USB interface on a bus-powered device

When the USB interface is not used, the USB_VBUS pin shall be connected to the ground.

9.3 Connecting the RF interface

ANT1

RX1

C3=1 nF

Cant

TX1

C1 antenna

C0 C2

TVSS

PN7462AU

C0 C2

TX2 antenna

RX2

ANT2

VMID

C3=1 nF

Cant

C=100 nF

Figure 27. RF interface - example of connection to an antenna

aaa-021150

9.4 Unconnected I/Os

When not used, the following pins need to be "not connected":

•

I2C Master interface: I2CM_SDA, I2CM_SCL

•

SPI Master interface: SPIM_SSN, SPIM_SCLK, SPIM_MOSI, SPIM_MISO

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PN736X

NFC Cortex-M0 microcontroller

Pads have to be configured in GPIO mode, pad input and out put driver need to be disabled.

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PN736X

NFC Cortex-M0 microcontroller

10 Limiting values

Table 23. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

ESD electrostatic discharge voltage

Conditions

Human Body Model (HBM) on all pins

Charged Device Model (CDM) on all pins non-operating T stg

T j(max)

P tot storage temperature maximum junction temperature total power dissipation reader mode; V

DDP(VBUS)

= 5.5 V

[1] EIA/JESD22-A114-D.

Min

[1]

-2

[1]

-1

-55

Max Unit

+2 kV

+150

+125

1050 kV

°C

°C mW

Table 24. Limiting values for GPIO1 to GPIO12

Symbol Parameter

V i input voltage

Conditions

Table 25. Limiting values for I

C master pins (i2cm_sda, i2cm_scl)

Symbol Parameter Conditions

V i input voltage

Min

-0.3

Max

4.2

Unit

Min

-0.3

Max

4.2

Unit

Table 26. Limiting values for SPI master pins ( spim_nss, spim_miso, spim_mosi and spi_clk)

Symbol Parameter Conditions Min

V i input voltage -0.3

Max

4.2

Unit

Table 27. Limiting values for host interfaces atx_a, atx_b, atx_c, atx_d in all configurations (USB, HSUART, SPI and

Symbol Parameter Conditions Min Max Unit

V i input voltage -0.3

4.2

Table 28. Limiting values for crystal oscillator

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter

IH high-level input voltage

Conditions

XTAL1, XTAL2

Min

Max

2.2

Unit

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PN736X

NFC Cortex-M0 microcontroller

Table 29. Limiting values for power supply

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

DDP(VBUS)

DDP(VBUSP) power supply voltage on pin VBUS power supply voltage on pin VBUSP

pin supply voltage for host interface and GPIOs (on pin PVDD_IN)

DD(PVDD)

PVDD supply voltage

pin supply voltage for master interfaces (on pin PVDD_M_IN)

DD(PVDD)

PVDD supply voltage on pin PVDD_M_IN; power supply for master interfaces

RF interface LDO (pin VUP_TX)

on pin PVDD_IN; power supply for host interfaces and GPIOs

I(LDO)

LDO input voltage

RF transmitter (pin TVDD_IN)

DD(TVDD)

TVDD supply voltage for RF interface LDO for RF interface transmitter

[1]

Min

-0.3

-0.3

-0.3

-0.3

-0.3

Max

4.2

Unit

[1] Maximum/minimum voltage above the maximum operating range and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter life time of the device.

Table 30. Limiting values for RF interface

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V i

Parameter

input voltage

Conditions

on pins RXN and RXP

Min

Max

2.2

Unit

1. Maximum/minimum voltage above the maximum operating range and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter life time of the device.

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11 Recommended operating conditions

Table 31. Operating conditions

Symbol

T amb

DDP(VBUS)

Parameter

ambient temperature power supply voltage on pin VBUS

Conditions

JDEC PCB - 0.5

external PVDD supply, card emulation and passive target

(PLM) external PVDD supply, reader mode, NFC initiator and passive/ active target mode (ALM and

PLM) internal PVDD_LDO supply, reader mode, NFC initiator and passive/active target mode (ALM and PLM)

host interface and GPIOs pin power supply (pin PVDD_IN)

DD(PVDD)

PVDD supply voltage for digital pins

1.8 V pin supply

3.3 V pin supply

SPI master and I

C master interfaces pin power supply (on pin PVDD_M_IN)

DD(PVDD)

PVDD supply voltage for master pins

1.8 V pin supply

3.3 V pin supply

RF interface LDO (pin VUP_TX)

I(LDO)

LDO input voltage TX_LDO supply for powering up

RF interface

RF interface transmitter

DD(TVDD)

TVDD supply current on pin TVDD_IN

PN736X

NFC Cortex-M0 microcontroller

Min Typ Max Unit

-40 25 85 °C

2.3

5.5

2.7

1.65

1.8

3 3.3

1.95

3.6

1.65

1.8

3 3.3

1.95

3.6

3 5 5.5

5.5

250 mA

PN736X

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12 Thermal characteristics

Table 32. Thermal characteristics

Symbol Parameter

R th(j-a) thermal resistance from junction to ambient

Conditions

in free air with exposed pad soldered on a four-layer JEDEC PCB

Typ

Unit

°K/W

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13 Characteristics

13.1 Static characteristics

Table 33. Static characteristics for RST_N input pin

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter Conditions Min

C in high-level input voltage low-level input voltage high-level input current V i

= V

DDP(VBUS) low-level input current V i

= 0 V input capacitance -

-1

1.1

Table 34. Static characteristics for IRQ output pin

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter Conditions Min

R pull-down high-level output voltage low-level output voltage load capacitance extra pull down

< 3 mA

< 3 mA extra pull-down is activated in HDP

PVDD_IN

0.4

0.45

Typ

PN736X

NFC Cortex-M0 microcontroller

Max

DDP(VBUS)

0.4

Unit

μA

μA pF

Max

PVDD_IN

0.4

0.8

Unit

V pF

MΩ

Table 35. Static characteristics for DWL_REQ

Symbol Parameter Conditions

IH high-level input voltage VV

PVDD_IN

= 1.8 V

L high-level input voltage VV

PVDD_IN

= 1.8 V high-level input voltage VV

PVDD_IN

= 3.3 V high-level input voltage VV

PVDD_IN

= 3.3 V high-level input current V

= PVDD_IN low-level input current V

= 0 V load capacitance

-1

Min

0.65 ×

PVDD_IN

Typ

Max

0.35 ×

PVDD_IN

0.8

Unit

μA

μA pF

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V hys

13.1.1 GPIO static characteristics

Table 36. Static characteristics for GPIO1 to GPIO21

Symbol Parameter Conditions

OH high-level output voltage

< 3 mA

IH low-level output voltage high-level input voltage

< 3 mA

PVDD_IN

= 3.3 V

PVDD_IN

= 1.8 V

R pd

R pu

OSH

OSL low-level input voltage V

PVDD_IN

= 3.3 V

PVDD_IN

= 1.8 V hysteresis voltage

OFF-state output current pull-down resistance pull-up resistance short circuit current output high

PVDD_IN

= 1.8 V and

= 3.3 V

= 0 V; V

PVDD_IN

; on-chip pullup/pull-down resistors disabled

PVDD_IN

= 3.3 V

PVDD_IN

= 1.8 V

PVDD_IN

= 3.3 V

PVDD_IN

= 1.8 V

Drive high; cell connected to ground;

PVDD_IN

= 3.3 V

Drive low; cell connected to

PVDD_IN; V

PVDD_IN

1.8 V

= short circuit current output low

= V

PVDD_IN

= 3.3

= V

PVDD_IN

= 1.8

low-level input current V

= 0 V high-level input current V

= V

PVDD_IN high-level output current

= V

PVDD_IN low-level output current

= 0 V

-1

Min

PVDD_IN

0.4

0 -

Typ

0.65 ×

PVDD_IN

0.1 ×

PVDD_IN

PN736X

NFC Cortex-M0 microcontroller

120

Max

PVDD_IN

0.4

0.8

0.35 ×

PVDD_IN

1000

Unit

V nA kΩ kΩ kΩ kΩ mA mA mA mA

µA

µA mA mA

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NFC Cortex-M0 microcontroller

13.1.2 Static characteristics for I

C master

Table 37. Static characteristics for I

CM_SDA, I

CM_SCL - S

Symbol Parameter Conditions

OH high-level output voltage

< 3 mA

IL low-level output voltage load capacitance

High-level input voltage low-level input voltage

Min

0.7 ×

PVDD_M_IN

0.7 ×

PVDD_M_IN

Typ

C in high-level input current V

= V

PVDD_M_IN low-level input current V

= 0 V input capacitance -

-1 -

13.1.3 Static characteristics for SPI master

Table 38. Static characteristics for SPIM_MOSI

Symbol Parameter Conditions

L high-level output voltage I

< 3 mA low-level output voltage I

< 3 mA load Capacitance -

Min

PVDD_M_IN

- 0.4

0 -

Typ Max

PVDD_M_IN

0.4

Max

PVDD_M_IN

Unit

0.4

V pF

0.3 ×

PVDD_M_IN

μA

μA pF

Unit

V pF

Table 39. Static characteristics for SPIM_NSS

Symbol Parameter Conditions

L high-level output voltage I

< 3 mA low-level output voltage I

< 3 mA load Capacitance

Min

PVDD_M_IN

- 0.4

0 -

Typ Max

PVDD_M_IN

0.4

Unit

V pF

Table 40. Static characteristics for SPIM_MISO

Symbol Parameter Conditions

IH high-level input voltage low-level input voltage high-level input voltage low-level input voltage high-level input current low-level input current

PVDD_M_IN

= 1.8 V

PVDD_M_IN

= 1.8 V

PVDD_M_IN

= 3.3 V

PVDD_M_IN

= 3.3 V

V i

= V

PVDD_M_IN

V i

= 0 V

PN736X

Product data sheet

COMPANY PUBLIC

-1

Min

0.65 × V

PVDD_M_IN

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0.35 × V

PVDD_M_IN

0.8

µA

Unit

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Symbol Parameter

C in input capacitance

Conditions

Min

PN736X

NFC Cortex-M0 microcontroller

Typ Max

5 -

Unit

Table 41. Static characteristics for SPI_SCLK

Symbol Parameter Conditions

L high-level output voltage I

< 3 mA low-level output voltage I

< 3 mA load capacitance -

Min

PVDD_M_IN

- 0.4

0 -

Typ Max

PVDD_M_IN

0.4

Unit

V pF

13.1.4 Static characteristics for host interface

Table 42. Static characteristics for ATX_ used as SPI_NSS, ATX_ used as I

2 used as SPI_MOSI

CADR0, ATX_ used as SPI_SCK, ATX_

Symbol Parameter Conditions Min Typ Max Unit

C in high-level input voltage low-level input voltage high-level input voltage low-level input voltage high-level input current low-level input current input capacitance

PVDD_IN

= 1.8 V

PVDD_IN

= 1.8 V

PVDD_IN

= 3.3 V

PVDD_IN

= 3.3 V

V i

= V

PVDD_IN

V i

= 0 V

-1

0.65 × V

PVDD_M_IN

5 -

0.35 × V

PVDD_M_IN

0.8

µA

µA pF

Table 43. Static characteristics of ATX_ used as I

CSDA, ATX_ used as I

CSCL

Symbol Parameter Conditions Min

C in

IH high-level output voltage I

< 3 mA low-level output voltage I

< 3 mA load capacitance high-level input voltage low-level input voltage high-level input current low-level input current

Input capacitance

V i

= V

PVDD_IN

V i

= 0 V

-1

0.7 × V

PVDD_IN

0.7 × V

PVDD_IN

Typ Max

PVDD_IN

0.4

0.3 × V

PVDD_IN

μA

μA pF

Unit

V pF

Table 44. Static characteristics of ATX_ used as SPIMISO

Symbol Parameter Conditions

OL high-level output voltage I

< 3 mA low-level output voltage I

< 3 mA

PN736X

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Min

PVDD_IN

- 0.4

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PVDD_IN

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Unit

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Symbol Parameter

L load capacitance

Conditions

Min

Table 45. USB characteristics

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter Conditions Min

DDP(VBUS)

V th(rs)se

C trans

DRV

OFF-state output current 0 V < V i

< 3.3 V power supply voltage on pin VBUS

(D+) - (D-) differential input sensitivity voltage differential common mode voltage range includes V

range single-ended receiver switching threshold voltage low-level output voltage for low-speed or fullspeed; R

3.6 V

of 1.5 kΩ to high-level output voltage driven; for low- speed or full-speed;

of 15 kΩ to GND transceiver capacitance pin to GND driver output impedance for driver which is not high-speed capable with 33 Ω series resistor; steady state drive

-10

0.2

0.8

2.8

CRS output signal crossover voltage

1.3

PN736X

NFC Cortex-M0 microcontroller

Typ Max

5.5

2.5

0.3

PVDD_IN

Unit

Table 46. Static characteristics of HSU_TX and HSU RTS pin

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter

Conditions

high-level output voltage I

< 3 mA

Min

PVDD_IN

- 0.4

L low-level output voltage I

< 3 mA load capacitance -

Typ Max

PVDD_IN

0.4

Unit

V pF

Table 47. Static characteristics of HSU_RX, HSU_CTS

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter Conditions Min

IL high-level input voltage V

PVDD_M_IN

= 1.8 V low-level input voltage V

PVDD_M_IN

= 1.8 V -

0.65 × V

PVDD_IN

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0.35 × V

PVDD_IN

Unit

56 / 80

Unit

μA

V pF

NXP Semiconductors

PN736X

NFC Cortex-M0 microcontroller

Symbol Parameter

Conditions

high-level input voltage V

PVDD_M_IN

= 3.3 V low-level input voltage V

PVDD_M_IN

= 3.3 V high-level input current low-level input current load capacitance -

-1

Min

Typ Max

0.8

13.1.5 Clock static characteristics

Table 48. Static characteristics of XTAL pin (XTAL1, XTAL2)

T amb

= -40 °C to +85°C

Symbol Parameter

[1]

Conditions

Input clock characteristics on XTAL1 when using PLL

V i(p-p) peak-to-peak input voltage

XTAL pin characteristics XTAL PLL input

IH high-level input current V i

= V

IL low-level input current V i

= 0 V

V i

AL input voltage input voltage amplitude

C in input capacitance all power modes

Pin characteristics for 27.12 MHz crystal oscillator

C in input capacitance pin XTAL1

C in input capacitance pin XTAL2 -

Min

0.2

-1

200

Typ

[2]

Max

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.

1.65

13.1.6 Static characteristics - power supply

Table 49. Static characteristics for power supply

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter pin supply: PVDD_LDO

Conditions

O(LDO)

LDO output voltage V

DDP(VBUS)

<= 30 mA

>= 4.0 V, I

PVDDOUT

DD(PVDD_OUT) maximum supply current for pin PVDD_OUT

pin supply for host interface and GPIOs (on pin PVDD_IN)

DD(PVDD)

PVDD supply current

pin supply for master interfaces (on pin PVDD_M_IN)

DD(PVDD)

PVDD supply current

PN736X

Product data sheet

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Min

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406333

Typ

3.3

Max

3.6

Unit

V mA

μA

V mV pF pF pF

Unit

25 mA

57 / 80

μA

μA pF

Unit

NXP Semiconductors

Symbol Parameter Conditions contactless interface: TX_LDO (pins VUP_TX, TVDD_OUT)

I(LDO)

LDO input voltage

L(LDO)(max)

O(LDO) maximum LDO load current

LDO output voltage DC output voltage (target: 3.0 V)

5.5 V > V

I(LDO)

> 3.3 V

DC output voltage (target: 3.0 V)

3.3 V > V

I(LDO)

> 2.7 V

DC output voltage (target: 3.3 V)

5.5 V > V

I(LDO)

> 3.6 V

DC output voltage (target: 3.3 V)

3.6 V > V

I(LDO)

> 2.7 V

DC output voltage (target: 3.6 V)

5.5 V > V

I(LDO)

> 3.9 V

DC output voltage (target: 3.6 V)

3.9 V > V

I(LDO)

> 2.7 V

DC output voltage (target: 4.5 V)

5.5 V > V

I(LDO)

> 5.0 V

O(LDO)

LDO output current

DC output voltage (target: 4.7 V)

5.5 V > V

I(LDO)

> 5.0 V

I(LDO)

= 5.5 V

Contactless interface: RF transmitter (on pin TVDD_IN)

DD(TVDD)

TVDD supply current maximum current supported by the RF transmitter

Min

3.4

2.8

3.1

4.3

4.55

Typ Max

3.95

5.5

180

3.25

3.55

4.9

5.2

180

I(LDO)

0.3

3.3

I(LDO)

0.3

3.6

I(LDO)

0.3

4.5

4.75

250

PN736X

NFC Cortex-M0 microcontroller

Unit

V mA

V mA mA

Table 50. Static characteristics for voltage monitors

T amb

= -40 °C to +85 °C

Symbol Parameter Conditions

(th)HL negative-going threshold voltage

VBUS monitor; set to 2.3 V set to 2.7 V

V hys

(th)HL hysteresis voltage

PN736X

Product data sheet

COMPANY PUBLIC

negative-going threshold voltage set to 4.0 V

VBUS monitor set to 2.3 V set to 2.7 V set to 4.0 V

VBUSP monitor set to 2.7 V set to 3.0 V

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406333

Min

2.15

2.6

3.6

100

2.45

2.68

Typ

2.3

2.75

3.8

150

2.56

2.825

Max

2.45

2.95

3.9

200

100

2.65

2.95

58 / 80

Unit

V mV mV mV

NXP Semiconductors

PN736X

NFC Cortex-M0 microcontroller

Symbol

V hys

Parameter

hysteresis voltage

Conditions

set to 3.9 V

VBUSP monitor set to 2.7 V set to 3.0 V set to 3.9 V

Min

3.7

Typ

3.9

Max

4.1

Unit

V mV mV mV

13.1.7 Static characteristics for power modes

Table 51. Static characteristics for power modes

T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter

DDP(VBUS) power supply current on pin VBUS

Conditions

active mode; V

DDP(VBUS)

IP clocks disabled

= 5.5 V, external PVDD, external TVDD, all code while(1){} executed from flash; active mode; V

DDP(VBUS)

IP clocks enabled

= 5.5 V, external PVDD, external TVDD, all code while(1){} executed from flash; suspend mode; V

DDP(VBUS) external PVDD, T = 25 °C

= 5.5 V,

BUS

= 5.5 V, T = 25 °C, internal

PVDD LDO, including D+ and Dpull-up standby mode; V

DDP(VBUS) external PVDD supply; T amb

= 3.3 V;

= 25 °C standby mode; V

V internal

DDP(VBUS)

PVDD supply; T amb

= 5.5 V;

= 25 °C hard power down; V

DDP(VBUS)

5.5 V; RST_N = 0 V; T amb

= 25 °C

Min

13.1.8 Static characteristics RF interface

Table 52. Static characteristics for RF interface

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter pins ANT1 and ANT2

Conditions

Z impedance between ANT1 and ANT2; low impedance

pins RXN and RXP

PN736X

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406333

120

360

250

440

Typ

Typ Max

6.5

8.5

Max

17 Ω

Unit

mA mA

μA

µA

Unit

59 / 80

NXP Semiconductors

Symbol Parameter Conditions

V i(dyn)

C in

Z dynamic input voltage input pin capacitance on pins RXN and RXP on pins RXN and RXP

V det impedance detection voltage between pins RX to VMID; reader, card emulation and

P2P modes card emulation and target modes; configuration for 19 mV threshold

pins TX1 and TX2

OH high-level output voltage pins TX1 and TX2; T

3.1 V and I

VDD_IN

= 30 mA

OL low-level output voltage pins TX1 and TX2; T

VDD_IN

3.1; I

= 30 mA

= low-level output resistance

= V

TVDD

- 100 mV;

CWGsN = 01h

= V

TVDD

- 100 mV;

CWGsN = 0Fh

OH high-level output resistance

= V

TVDD

- 100 mV

13.2 Dynamic characteristics

Table 53. Dynamic characteristics for IRQ output pin

Data are given for T amb

= -40 °C to +85 °C; unless otherwise specified

Symbol Parameter Conditions

t f fall time t f t r t r fall time rise time rise time high speed; C

PVDD_IN

= 12 pF;

= 3.3 V high speed; C

PVDD_IN

= 12 pF;

= 1.8 V slow speed; C

PVDD_IN

= 12 pF;

= 3.3 V slow speed; C

PVDD_IN

= 12 pF;

= 1.8 V high speed: C

PVDD_IN

= 12 pF;

= 3.3 V high speed: C

PVDD_IN

= 12 pF;

= 1.8 V slow speed: C

PVDD_IN

= 12 pF;

= 3.3 V slow speed: C

PVDD_IN

= 12 pF;

= 1.8 V

Min

PN736X

NFC Cortex-M0 microcontroller

Typ

Max Unit

- 0.05 V pF

15 kΩ

TVDD_IN

- 150

30 mV

(p-p)

200

Ω mV mV

Typ

Min

3.5

Max

3.5

ns ns ns ns ns ns

Unit

ns ns

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13.2.1 Flash memory dynamic characteristics

Table 54. Dynamic characteristics for flash memory

Symbol Parameter Conditions

t prog

Endu t ret programming time endurance retention time

1 page (64 bytes); slow clock

Min

200

13.2.2 EEPROM dynamic characteristics

Table 55. Dynamic characteristics for EEPROM

Symbol Parameter Conditions

t prog programming time 1 page (64 bytes)

Endu t ret endurance retention time

13.2.3 GPIO dynamic characteristics

Min

300

Typ

500

Typ

2.8

500

80 % 80 % t f

50 % 50 %

20 % gnde

20 % t r

Figure 28. Output timing measurement condition for GPIO

aaa-021151

Max

2.5

Unit

ms kcycles years

Unit

Kcycles years

Table 56. Dynamic characteristics for GPIO1 to GPIO21

T amb

= -40 °C to +85 °C

Symbol Parameter Conditions

t r rise time t f fall time

= 12 pF; PVDD = 1.8 V; slow speed

= 12 pF; PVDD = 1.8 V; fast speed

= 12 pF; PVDD = 3.3 V; slow speed

= 12 pF; PVDD = 3.3 V; fast speed

= 12 pF; PVDD = 1.8 V; slow speed

= 12 pF; PVDD = 1.8 V; fast speed

= 12 pF; PVDD = 3.3 V; slow speed

= 12 pF; PVDD = 3.3 V; fast speed

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1.0

3.0

1.0

Min

2.0

1.0

3.0

1.0

2.0

Max

10.0

3.5

10.0

3.5

10.0

3.5

10.0

3.5

ns ns ns

Unit

ns ns ns ns ns

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NFC Cortex-M0 microcontroller

13.2.4 Dynamic characteristics for I

C master

DA t

SDA t

SU;STA t

HD;STA t

HIGH t

HD;DAT

SCL t

LOW t

SU;DAT

aaa-021152

Figure 29. I

C-bus pins clock timing

Table 57. Timing specification for fast mode plus I

T amb

= -40 °C to +85 °C

Symbol Parameter Conditions

SCL t

SU;STA t

HD;STA t

LOW t

HIGH

SCL clock frequency set-up time for a

(repeated) START condition hold time (repeated)

START condition low period of the SCL clock high period of the SCL clock fast mode plus; C b

< 100 pF fast mode plus; C b

< 100 pF t

SU;DAT t

HD;DAT t r(SDA) t f(SDA)

V hys data set-up time data hold time

SDA rise time

SDA fall time hysteresis of Schmitt trigger inputs fast mode plus; C b

< 100 pF fast mode plus; C b

< 100 pF

Min

260

Max

260

500

260

0.1 ×

PVDD_M_IN

120

120 ns ns ns ns ns ns ns

Unit

MHz ns

Table 58. Timing specification for fast mode I

T amb

= -40 °C to +85 °C

Symbol Parameter

SCL t

SU;STA

SCL clock frequency set-up time for a (repeated) START condition

Conditions

fast mode; C b

< 400 pF fast mode; C b

< 400 pF t

HD;STA hold time (repeated) START condition fast mode; C b

< 400 pF

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600

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Max

400

Unit

kHz ns ns

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NXP Semiconductors

Symbol Parameter

LOW t

HIGH t

SU;DAT t

HD;DAT t r(SDA) t f(SDA)

V hys

Conditions

low period of the SCL clock high period of the SCL clock fast mode; C b

< 400 pF fast mode; C b

< 400 pF data set-up time data hold time fast mode; C b

< 400 pF fast mode; C b

< 400 pF

SDA rise time

SDA fall time fast mode plus; C b

< 100 pF fast mode plus; C b

< 100 pF hysteresis of Schmitt trigger inputs fast mode; C b

< 400 pF

13.2.5 Dynamic characteristics for SPI

T cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI t v(Q)

DATA VALID

MISO

DATA VALID t

DATA VALID

PN736X

NFC Cortex-M0 microcontroller

Min

1.3

600

100

0.1 ×

PVDD_IN

Max

900

250

250 ns ns ns ns

Unit

μs ns t h(Q)

CPHA = 1

MOSI t v(Q)

DATA VALID DATA VALID t

DS t

DATA VALID

MISO

DATA VALID

Figure 30. SPI master timing

t h(Q)

CPHA = 0

002aae829

Table 59. Dynamic characteristics and Timing specification for SPI master interface

Symbol Parameter Conditions

SCK t

SCK frequency data set-up time controlled by the host

Min

25 t

DH t v(Q) data hold time data output valid time t h(Q) data output hold time

Dynamic characteristics for SPI_SCLK, SPIM_NSS, SPIM_MOSI

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6.78

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Unit

MHz ns

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Symbol Parameter

t f fall time t r t f t r rise time fall time rise time

Conditions

= 12 pF; high speed; V

PVDD_IN

= 3.3 V

= 12 pF; slow speed; V

PVDD_IN

= 3.3

= 12 pF; high speed; V

PVDD_IN

= 3.3 V

= 12 pF; slow speed; V

PVDD_IN

= 3.3

= 12 pF; high speed; V

PVDD_IN

= 1.8 V

= 12 pF; slow speed; V

PVDD_IN

= 1.8

= 12 pF; high speed; V

PVDD_IN

= 1.8 V

= 12 pF; slow speed; V

PVDD_IN

= 1.8

13.2.6 Dynamic characteristics of host interface

DA t

HD;DAT

Min

SDA t

SU;STA t

HD;STA t

HIGH t

SU;DAT

3.5

Max

3.5

SCL t

LOW

aaa-021153

Figure 31. I

C-bus pins clock timing

ns ns ns ns ns ns

Unit

ns ns

Table 60. Timing specification for I2C high speed

T amb

= -40 °C to +85 °C

Symbol Parameter Conditions

f scl t

SU;STA t

HD;STA clock frequency set-up time for a (repeated)

START condition hold time (repeated) START condition high speed; C b

< 100 pF high speed; C b

< 100 pF t

LOW t

HIGH t

SU;DAT t

HD;DAT t r(SDA) t f(SDA) low period of the SCL clock high speed; C b

< 100 pF high period of the SCL clock high speed; C b

< 100 pF data set-up time high speed; C b

< 100 pF data hold time

SDA rise time high speed; C b

< 100 pF high speed; C b

< 100 pF

SDA fall time high speed; C b

< 100 pF

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160

Max

3.4

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Unit

MHz ns ns ns ns ns

μs ns ns

NXP Semiconductors

Symbol Parameter

V hys hysteresis of Schmitt trigger inputs

Conditions

high speed; C b

< 100 pF

PN736X

NFC Cortex-M0 microcontroller

Min

0.1 ×

PVDD_IN

Max Unit

Table 61. Dynamic characteristics for the I

C slave interface: ATX_B used as I

C_SDA, ATX_A used as I

C_SCL

Symbol Parameter Conditions Min Typ Max Unit

t f fall time C

= 100 pF, R pull-up

= 2 K, standard and fast mode

30 250 ns

10 80 ns t r rise time

= 100 pF, R pull-up

= 1 K, high speed

= 100 pF, R pull-up

= 2 K, standard and fast mode

30 250 ns

= 100 pF, R pull-up

= 1 K, high speed

10 100 ns

T cy(clk)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI

MISO

DATA VALID t v(Q)

DATA VALID t

DS t

DATA VALID

DATA VALID t h(Q)

CPHA = 1

MOSI

MISO

DATA VALID t v(Q)

DATA VALID t

DS t

DATA VALID

DATA VALID t h(Q)

CPHA = 0

002aae830

Figure 32. SPI slave timings

Table 62. Dynamic characteristics for SPI slave interface

Symbol Parameter Conditions

SCK

SCK frequency controlled by the host

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Symbol Parameter

DS t

DH t v(Q) t h(Q) data set-up time data hold time data output valid time data output hold time

Conditions

PN736X

NFC Cortex-M0 microcontroller

Min

25 -

Max

Unit

ns ns ns ns

Table 63. Dynamic characteristics for SPI slave interface: ATX_C as SPI_MISO

Symbol Parameter Conditions

t f fall time t r t f t r rise time fall time rise time

= 12 pF; high speed;

PVDD_IN

= 3.3 V

= 12 pF; slow speed;

PVDD_IN

= 3.3 V

= 12 pF; high speed;

PVDD_IN

= 3.3 V

= 12 pF; slow speed;

PVDD_IN

= 3.3 V

= 12 pF; high speed;

PVDD_IN

= 1.8 V

= 12 pF; slow speed;

PVDD_IN

= 1.8 V

= 12 pF; high speed;

PVDD_IN

= 1.8 V

= 12 pF; slow speed;

PVDD_IN

= 1.8 V

Min Typ Max Unit

1 3.5

3 10 ns

3.5

ns ns ns ns ns ns

Table 64. Dynamic characteristics for HSUART ATX_ as HSU_TX, ATX_ as HSU_RTS

Symbol Parameter Conditions

[1]

Min Typ Max Unit

t f fall time t r t f t r rise time fall time rise time high speed; V

PVDD_IN

= 3.3 V slow speed; V

PVDD_IN

= 3.3 V high speed; V

PVDD_IN

= 3.3 V slow speed; V

PVDD_IN

= 3.3 V high speed; V

PVDD_IN

= 1.8 V slow speed; V

PVDD_IN

= 1.8 V high speed; V

PVDD_IN

= 1.8 V slow speed; V

PVDD_IN

= 1.8 V

3.5

10 ns ns ns ns ns ns ns ns

[1] C

=12 pF maximum.

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Table 65. Dynamic characteristics for USB interface

= 50 pF; R pu

= 1.5 kΩ on D+ to VBUS

Symbol Parameter Conditions

t r t f t

FRFM

CRS t

FEOPT t

FDEOP rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition

10 % to 90 %

10 % to 90 % t r

/ t f

T = 25 °C; see

Figure 33

T = 25 °C; see

Figure 33

JR1 t

JR2 t

FEOPR receiver jitter to next transition T = 25 °C receiver jitter for paired transitions 10 % to 90 %; T = 25 °C receiver SE0 interval of EOP

must accept as EOP; see Figure

Min Typ Max Unit

4 -

109 ns ns

1.3

160

-2

-18.5

-9 -

82 -

175

+18.5 ns

+9 ns ns

V ns ns

PERIOD differential data lines crossover point crossover point extended source EOP width: t

FEOPT differential data to

SE0/EOP skew n × T

PERIOD

+ t

FDEOP

Figure 33. USB interface differential data-to-EOP transition skew and EOP width

receiver EOP width: t

EOPR1

, t

EOPR2

002aab561

13.2.7 Clock dynamic characteristics

Table 66. Dynamic characteristics for internal oscillators

T amb

= -40 °C to +85 °C

Symbol Parameter

[1]

Conditions

low frequency oscillator

osc(int) internal oscillator frequency

high frequency oscillator

f osc(int) internal oscillator frequency

DDP(VBUS)

= 3.3 V

DDP(VBUS)

= 3.3 V

Min Typ

[2]

Max Unit

300

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.

365

400

22 kHz

MHz

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Table 67. Dynamic characteristics for PLL

T amb

= -40 °C to +85°C

Symbol Parameter

[1]

Δf frequency deviation

Conditions

deviation added to

CLK_XTAL1 frequency on RF frequency generated using

PLL

Min Typ

-50

[1] Parameters are valid over operating temperature range unless otherwise specified.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C) with nominal supply voltages.

[2]

Max Unit

50 ppm

13.2.8 Dynamic characteristics for power supply

Table 68. Dynamic characteristics for power supply

Symbol Parameter Conditions

DC-to-DC internal oscillator

f osc(int) internal oscillator frequency DC-to-DC converter -

Min Typ Max Unit

3.39

MHz

13.2.9 Dynamic characteristics for boot and reset

Table 69. Dynamic characteristics for boot and reset

Symbol Parameter Conditions

t wL(RST_N) t boot

RST_N Low pulse width time boot time external PVDD supply; supply is stable at reset internal PVDD_LDO supply; supply is stable at reset

Min Typ Max Unit

320

μs

µs

2.2

13.2.10 Dynamics characteristics for power mode

Table 70. Power modes - wake-up timings

Symbol Parameter

t wake wake-up time

Conditions

standby mode suspend mode

[1]

Min Typ Max Unit

500 μs

150 μs

[1] Wake-up timings are measured from the wake-up event to the point in which the user application code reads the first instruction.

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14 Marking

Table 71. Marking codes

Type number Marking code

PN736X

Line A PN7362AU-00

Line B

Line C

Line D

Line E

Diffusion Batch ID, Assembly Sequence ID

Characters: Diffusion and assembly location, date code, product version

(indicated by mask version), product life cycle status. This line includes the following elements at 8 positions:

1. Diffusion center code: Z

2. Assembly center code: S

3. RHF-2006 indicator: D "Dark Green"

4. Year code (Y) 1

5. Year code (Y) 2

6. Week code (W) 1

7. Week code (W) 2

8. HW version

Empty

14.1 Package marking drawing

Terminal 1 index area

Figure 34. Marking PN736X in HVQFN64

aaa-021255

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15 Package outline

HVQFN64: plastic thermal enhanced very thin quad flat package; no leads;

64 terminals; body 9 x 9 x 0.85 mm

D B A terminal 1 index area

E A

PN736X

NFC Cortex-M0 microcontroller

SOT804-4

c detail X

E t

17 e

E h

E s e

1/2 e b

33 v w e

A B

1/2 e e

2 y

C y

1 48 terminal 1 index area

64 49

D s

D h

D t

0 2.5

scale

Dimensions

Unit A A

1 b c D

(1)

D h

D s

D t

(1)

E h

E s mm max nom min

1.00

0.85

0.80

0.05

0.02

0.00

0.30

0.21

0.18

0.2

9.1

9.0

8.9

5.25

5.10

4.95

0.19

0.14

0.09

0.50

0.45

0.40

9.1

9.0

8.9

5.25

5.10

4.95

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

0.19

0.14

0.09

Outline version

IEC JEDEC

References

JEITA

SOT804-4 - - - - - - -

5 mm

E t

0.50

0.45

0.40

0.5

1 e

7.5

L L

0.5

0.4

0.3

0.25

European projection

X v w y

0.1 0.05 0.05

10-05-26

10-05-27 y

0.1

sot804-4_po

Issue date

Figure 35. Package outline HVQFN64

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Footprint information for reflow soldering of HVQFN64 package

D P

Ø 0.3 drilled vias (41x)

SPx

0.105

PN736X

NFC Cortex-M0 microcontroller

SOT804-4

0.125

SPy

Hy Gy SPy tot SLy By Ay

0.065

SPx tot

0.065

SLx

0.29

0.24

solder land

Recommended stencil thickness: 0.1 mm solder land plus solder paste occupied area detail X solder paste deposit

Dimensions in mm

P Ax

0.50

10.00

Ay Bx

10.00 8.20

solder resist opening

By SLx SLy

8.20

5.10

SPx SPy

0.70

SPx tot

3.50

SPy tot

3.50

0.90

0.29

9.25

Hx Hy

10.25

0.85 0.9

sot804-4_fr

Figure 36. Footprint information for reflow soldering of HVQFN64

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16 Packing information

Moisture Sensitivity Level (MSL) evaluation has been performed according to JEDEC

J-STD-020C. MSL for this package is level 3 which means 260 °C Pb-free convection reflow maximum temperature peak.

Dry packing is required with following floor conditions: 168 hours out of bag floor life at maximum ambient temperature 30 °C/60 % RH.

For information on packing, refer to the PIP relating to this product at http:// www.nxp.com.

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17 Abbreviations

NVIC

P2P

PLL

PLM

SPI

ISP

LDO

LPCD

NFC

NRZ

SWD

UART

USB

ASK

BPSK

CLIF

CRC

DPC

EEPROM

GPIO

IAP

Table 72. Abbreviations

Acronym Description

ADC Analog to Digital Convertor

ALM Active Load Modulation

Amplitude Shift Keying

Binary Phase Shift Keying

Contactless Interface

Cyclic Redundancy Check

Dynamic Power Control

Electrically Erasable Programmable Read-Only Memory

General-Purpose Input Output

Inter-Interchanged Circuit

Integrated Circuit

In-Application Programming

In-System Programming

Low DropOut

Low-Power Card Detection

Near Field Communication

Non-Return to Zero

Nested Vectored Interrupt Controller

Peer-to-Peer

Phase-Locked Loop

Passive Load Modulation

Serial Peripheral Interface

Serial Wire Debug

Universal Asynchronous Receiver Transmitter

Universal Serial Bus

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18 Revision history

Table 73. Revision history

Document ID Release date

PN736X v. 3.3

20170907

Modifications:

PN736X v. 3.2

Modifications:

PN746X_736X v.3.1

Modifications:

PN746X_736X v.3.0

Data sheet status

Product data sheet -

Change notice Supersedes

PN736X v.3.2

•

Removed chapter 8.9 "I/O auxiliary - ISO/IEC 7816 UART" which is not available on the product.

•

Updated Pin description, removed pin fuinctionality INT_AUX , CLK_AUX and IO_AUX

•

Updated Section 9.4

"Unconnected I/O's", removed description of AUX interface INT_AUX,

IO_AUX, CLK_AUX which is not available on the product

PN746X_736X v.3.1

20161213 Product data sheet

•

Product name title and Descriptive title updated

•

Editorial changes

20160405 Product data sheet

PN746X_736X v.3.0

•

Descriptive title updated

•

Section 1 "General description"

: updated

20160330 Product data sheet -

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19 Legal information

19.1 Data sheet status

Document status

[1][2]

Objective [short] data sheet

Preliminary [short] data sheet

Product [short] data sheet

Product status

Development

Qualification

Production

[3]

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions

Draft

— The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Suitability for use

— NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Short data sheet

— A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification

— The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Applications

— Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limited warranty and liability

— Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

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Limiting values

— Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale

— NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

Right to make changes

— NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

No offer to sell or license

— Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

All information provided in this document is subject to legal disclaimers.

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Quick reference data

— The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Export control

— This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products

— Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.

NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP

Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations

— A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

19.4 Licenses

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

RATP/Innovatron

Technology

This NXP Semiconductors IC is ISO/IEC

14443 Type B software enabled and is licensed under Innovatron’s Contactless

Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC in systems and/or end-user equipment.

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the

Near Field Communication (NFC) standards ISO/IEC 18092 and ISO/

IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other products, whether hardware or software.

19.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

C-bus

— logo is a trademark of NXP B.V.

MIFARE

— is a trademark of NXP B.V.

ICODE and I-CODE

— are trademarks of NXP B.V.

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Tables

Tab. 1.

Quick reference data .........................................5

Tab. 2.

Ordering information ..........................................6

Tab. 3.

Pin description ...................................................8

Tab. 4.

Interrupt sources ............................................. 15

Tab. 5.

Pin description for host interface .....................19

Tab. 6.

HSUART baudrates .........................................20

Tab. 7.

I2C interface addressing ................................. 20

Tab. 8.

SPI configuration .............................................21

Tab. 9.

Communication overview for ISO/IEC 14443

A/MIFARE reader/writer .................................. 23

Tab. 10. Communication overview for ISO/IEC 14443

B reader/writer .................................................24

Tab. 11. Communication overview for FeliCa reader/ writer ................................................................25

Tab. 12. Communication overview for ISO/IEC 15693 reader to label .................................................25

Tab. 13. Communication overview for ISO/IEC 15693 label to reader .................................................26

Tab. 14. Communication overview for active communication mode ...................................... 27

Tab. 15. Communication overview for passive communication mode ...................................... 28

Tab. 16. ISO/IEC14443 A card operation mode ............28

Tab. 17. Framing and coding overview ......................... 28

Tab. 18. Timer characteristics ....................................... 32

Tab. 19. Crystal requirements ....................................... 34

Tab. 20. Threshold configuration for voltage monitor .... 40

Tab. 21. Reset sources ................................................. 41

Tab. 22. Power supply connection ................................ 43

Tab. 23. Limiting values ................................................ 48

Tab. 24. Limiting values for GPIO1 to GPIO12 ............. 48

Tab. 25. Limiting values for I2C master pins

(i2cm_sda, i2cm_scl) .......................................48

Tab. 26. Limiting values for SPI master pins

( spim_nss, spim_miso, spim_mosi and spi_clk) ............................................................ 48

Tab. 27. Limiting values for host interfaces atx_a, atx_b, atx_c, atx_d in all configurations

(USB, HSUART, SPI and I2C) ........................ 48

Tab. 28. Limiting values for crystal oscillator .................48

Tab. 29. Limiting values for power supply ..................... 49

Tab. 30. Limiting values for RF interface .......................49

Tab. 31. Operating conditions ....................................... 50

Tab. 32. Thermal characteristics ................................... 51

Tab. 33. Static characteristics for RST_N input pin ....... 52

Tab. 34. Static characteristics for IRQ output pin .......... 52

Tab. 35. Static characteristics for DWL_REQ ................52

Tab. 36. Static characteristics for GPIO1 to GPIO21 .....53

Tab. 37. Static characteristics for I2CM_SDA,

I2CM_SCL - S .................................................54

Tab. 38. Static characteristics for SPIM_MOSI ............. 54

Tab. 39. Static characteristics for SPIM_NSS ............... 54

Tab. 40. Static characteristics for SPIM_MISO ............. 54

Tab. 41. Static characteristics for SPI_SCLK ................ 55

Tab. 42. Static characteristics for ATX_ used as

SPI_NSS, ATX_ used as I2CADR0, ATX_ used as SPI_SCK, ATX_ used as SPI_MOSI .. 55

Tab. 43. Static characteristics of ATX_ used as

I2CSDA, ATX_ used as I2CSCL ..................... 55

Tab. 44. Static characteristics of ATX_ used as

SPIMISO ..........................................................55

Tab. 45. USB characteristics .........................................56

Tab. 46. Static characteristics of HSU_TX and HSU

RTS pin ........................................................... 56

Tab. 47. Static characteristics of HSU_RX,

HSU_CTS ........................................................56

Tab. 48. Static characteristics of XTAL pin (XTAL1,

XTAL2) ............................................................ 57

Tab. 49. Static characteristics for power supply ............ 57

Tab. 50. Static characteristics for voltage monitors ....... 58

Tab. 51. Static characteristics for power modes ............59

Tab. 52. Static characteristics for RF interface ..............59

Tab. 53. Dynamic characteristics for IRQ output pin ..... 60

Tab. 54. Dynamic characteristics for flash memory .......61

Tab. 55. Dynamic characteristics for EEPROM .............61

Tab. 56. Dynamic characteristics for GPIO1 to

GPIO21 ............................................................61

Tab. 57. Timing specification for fast mode plus I2C .....62

Tab. 58. Timing specification for fast mode I2C ............ 62

Tab. 59. Dynamic characteristics and Timing specification for SPI master interface ..............63

Tab. 60. Timing specification for I2C high speed ...........64

Tab. 61. Dynamic characteristics for the I2C slave interface: ATX_B used as I2C_SDA, ATX_A used as I2C_SCL ............................................65

Tab. 62. Dynamic characteristics for SPI slave interface ...........................................................65

Tab. 63. Dynamic characteristics for SPI slave interface: ATX_C as SPI_MISO ...................... 66

Tab. 64. Dynamic characteristics for HSUART ATX_ as HSU_TX, ATX_ as HSU_RTS ....................66

Tab. 65. Dynamic characteristics for USB interface ...... 67

Tab. 66. Dynamic characteristics for internal oscillators .........................................................67

Tab. 67. Dynamic characteristics for PLL ......................68

Tab. 68. Dynamic characteristics for power supply ....... 68

Tab. 69. Dynamic characteristics for boot and reset ......68

Tab. 70. Power modes - wake-up timings ..................... 68

Tab. 71. Marking codes .................................................69

Tab. 72. Abbreviations ...................................................73

Tab. 73. Revision history ...............................................74

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Figures

Block diagram ................................................... 7

Pin configuration ............................................... 8

Flash memory mapping ...................................11

EEPROM memory mapping ............................12

SRAM memory mapping ................................. 13

PN736X memory map .....................................14

APB memory map ...........................................15

ISO/IEC 14443 A/MIFARE read/write mode

Fig. 9.

communication diagram .................................. 23

Data coding and framing according to ISO/

IEC 14443 A card response ............................23

Fig. 10.

ISO/IEC 14443 B read/write mode communication diagram .................................. 24

Fig. 11.

FeliCa read/write communication diagram ...... 24

Fig. 12.

Multiple reception cycles - data format ............25

Fig. 13.

ISO/IEC 15693 read/write mode communication diagram .................................. 25

Fig. 14.

Data coding according to ISO/IEC 15693 standard mode reader to label ........................ 26

Fig. 15.

Active communication mode ........................... 27

Fig. 16.

Passive communication mode .........................27

Fig. 17.

PN736X output driver ......................................29

Fig. 18.

Receiver block diagram ...................................30

Fig. 19.

Communication in card emulation of NFC passive target ..................................................31

Fig. 20.

Clocks and IP overview ...................................34

Fig. 21.

Crystal oscillator connection ............................34

Fig. 22.

PN736X LDOs and power pins overview ........ 36

Fig. 23.

Powering up the PN736X microcontroller ........44

Fig. 24.

Powering up the contactless interface using a single power supply ..................................... 45

Fig. 25.

Powering up the contactless interface using an external RF transmitter supply ................... 45

Fig. 26.

USB interface on a bus-powered device ......... 46

Fig. 27.

RF interface - example of connection to an antenna ............................................................46

Fig. 28.

Output timing measurement condition for

GPIO ................................................................61

Fig. 29.

I²C-bus pins clock timing .................................62

Fig. 30.

SPI master timing ............................................63

Fig. 31.

I2C-bus pins clock timing ................................ 64

Fig. 32.

SPI slave timings ............................................ 65

Fig. 33.

USB interface differential data-to-EOP transition skew and EOP width ....................... 67

Fig. 34.

Marking PN736X in HVQFN64 ........................69

Fig. 35.

Package outline HVQFN64 ............................. 70

Fig. 36.

Footprint information for reflow soldering of

HVQFN64 ........................................................71

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2.1

2.2

General description ............................................ 1

Features and benefits .........................................2

Integrated contactless interface frontend ...........2

Cortex-M0 microcontroller ................................. 2

Applications .........................................................4

Quick reference data .......................................... 5

Ordering information .......................................... 6

Block diagram ..................................................... 7

7.1

7.2

Pinning information ............................................ 8

Pinning ...............................................................8

Pin description ................................................... 8

Functional description ......................................11

8.1

8.2

ARM Cortex-M0 microcontroller ...................... 11

Memories ......................................................... 11

8.2.1

On-chip flash programming memory ............... 11

8.2.1.1

Memory mapping .............................................11

8.2.2

EEPROM ......................................................... 12

8.2.2.1

Memory mapping .............................................12

8.2.3

SRAM ...............................................................12

8.2.3.1

Memory mapping .............................................12

ROM .................................................................13

Memory map ....................................................13

Nested Vectored Interrupt Controller (NVIC) ....15

NVIC features .................................................. 15

Interrupt sources ..............................................15

GPIOs .............................................................. 17

GPIO features ..................................................17

GPIO configuration .......................................... 17

GPIO interrupts ................................................17

CRC engine 16/32 bits .................................... 17

Random Number Generator (RNG) .................18

Master interfaces ............................................. 18

8.7.1

I2C master interface ........................................ 18

8.7.1.1

I2C features ..................................................... 18

8.7.2

SPI interface .................................................... 18

8.7.2.1

SPI features .....................................................19

8.8

8.8.1

Host interfaces .................................................19

High-speed UART ............................................19

8.8.2

I2C host interface controller .............................20

8.8.2.1

I2C host interface features .............................. 20

8.8.3

SPI host/Slave interface .................................. 20

8.8.3.1

SPI host interface features .............................. 21

8.8.4

USB interface .................................................. 21

8.8.4.1

Full speed USB device controller .................... 21

8.9

8.9.1

Contactless interface - 13.56 MHz ...................22

RF functionality ................................................22

8.9.1.1

ISO/IEC14443 A/MIFARE functionality ............22

8.9.1.2

ISO/IEC14443 B functionality .......................... 24

8.9.1.3

FeliCa functionality .......................................... 24

8.9.1.4

ISO/IEC 15693 functionality .............................25

8.9.1.5

ISO/IEC18000-3 mode 3 functionality ..............26

8.9.1.6

NFCIP-1 modes ...............................................26

8.9.2

Contactless interface ....................................... 29

8.9.2.1

Transmitter (TX) .............................................. 29

8.9.2.2

Receiver (RX) .................................................. 30

8.9.3

Low-Power Card Detection (LPCD) .................31

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Active Load Modulation (ALM) ........................ 31

Dynamic Power Control (DPC) ........................32

8.9.5.1

RF output control .............................................32

8.9.5.2

Adaptive Waveform Control (AWC) ................. 32

Timers ..............................................................32

Features of timer 0 and timer 1 ....................... 32

Features of timer 2 and timer 3 ....................... 33

System tick timer ............................................. 33

Watchdog timer ............................................... 33

Clocks .............................................................. 33

Quartz oscillator (27.12 MHz) ..........................34

USB PLL ..........................................................35

High Frequency Oscillator (HFO) .................... 35

Low Frequency Oscillator (LFO) ......................35

Clock configuration and clock gating ............... 35

Power management .........................................36

8.14.1

8.14.2

Power supply sources ..................................... 36

PN736X Power Management Unit (PMU) ........36

8.14.2.1 Main LDO ........................................................ 37

8.14.2.2 PVDD_LDO ......................................................37

8.14.2.3 TXLDO .............................................................37

8.14.3

Power modes ...................................................38

8.14.3.1 Active mode .....................................................38

8.14.3.2 Standby mode ................................................. 38

8.14.3.3 Suspend mode ................................................ 39

8.14.3.4 Wake-up from standby mode and suspend mode ................................................................39

8.14.3.5 Hard Power-Down (HPD) mode ...................... 39

8.14.4

Voltage monitoring ...........................................40

8.14.4.1 VBUS monitor ..................................................40

8.14.4.2 VBUSP monitor ............................................... 40

8.14.4.3 PVDD LDO supply monitor ..............................40

8.14.5

8.15

Temperature sensor ........................................ 40

System control .................................................41

Reset ................................................................41

Brown-Out Detection (BOD) ............................ 41

APB interface and AHB-Lite ............................ 41

External interrupts ............................................41

SWD debug interface ...................................... 42

SWD interface features ................................... 42

Application design-in information ...................43

Power supply connection .................................43

Powering up the microcontroller ...................... 44

Powering up the contactless interface ............. 44

Connecting the USB interface ......................... 46

Connecting the RF interface ............................46

Unconnected I/Os ............................................46

Limiting values ..................................................48

Thermal characteristics ....................................51

Characteristics .................................................. 52

Static characteristics ........................................52

GPIO static characteristics .............................. 53

Static characteristics for I2C master ................ 54

Static characteristics for SPI master ................54

Static characteristics for host interface ............ 55

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Clock static characteristics .............................. 57

Static characteristics - power supply ............... 57

Static characteristics for power modes ............ 59

Static characteristics RF interface ................... 59

Dynamic characteristics ...................................60

Flash memory dynamic characteristics ............61

EEPROM dynamic characteristics ...................61

GPIO dynamic characteristics ......................... 61

Dynamic characteristics for I2C master ........... 62

Dynamic characteristics for SPI .......................63

Dynamic characteristics of host interface ........ 64

Clock dynamic characteristics ......................... 67

13.2.8

13.2.9

Dynamic characteristics for power supply ........68

Dynamic characteristics for boot and reset ......68

13.2.10 Dynamics characteristics for power mode ....... 68

14 Marking ...............................................................69

Package marking drawing ............................... 69

Package outline .................................................70

Packing information ..........................................72

Abbreviations .................................................... 73

Revision history ................................................ 74

Legal information ..............................................75

PN736X

NFC Cortex-M0 microcontroller

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 7 September 2017

Document identifier: PN736X

Document number: 406333

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