Semtech SX1303 Data Sheet LoRa® Gateway Datasheet
Semtech SX1303 Data Sheet
The Semtech SX1303 is a LoRa® baseband processor with integrated RF front-end for gateways. It is a highly integrated device that simplifies the design of LoRa gateways and reduces the overall system cost. The SX1303 supports all LoRaWAN® classes and features a high-speed 500 kHz LoRa demodulator, making it ideal for high-traffic applications. Other key features of the SX1303 include:
- Fine timestamping for network-based geolocation
- Direct interface to Semtech transceivers (SX1255, SX1257, and SX1250)
- Single 32 MHz clock source
- Low power consumption
- Serialized production with a globally unique 64-bit number
The SX1303 is an ideal solution for LoRa gateway applications that require high performance, low power consumption, and low cost.
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SX1303
LoRa Gateway Baseband Processor
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General Description
The SX1303 is a new generation of baseband LoRa®
chip for gateways. It excels in reducing current consumption, simplifies the thermal design of gateways, and reduces the
Bill Of Materials costs, yet it is capable of handling a higher amount of traffic than preceding devices.
The high-speed baseband digital engines are clocked from a single 32 MHz clock source, and the chip embeds the capability to support SF5 and SF6 unlike previous generations. The architecture has been reworked to reduce power consumption very significantly; it makes it easier to embed the SX1303 in highly-integrated environments where power dissipation might be a challenge.
The SX1303 supports Fine Timestamp capability, when network-based geo-location is required.
The SX1303 is also serialized in production, with a globally unique 64-bit number.
Key Features
•
Fine timestamp
•
LoRaWAN, Class A/B/C, all regions
•
Multi-SF 125 kHz LoRa® reception with Fine Timestamp
•
High-speed 250 / 500 kHz LoRa demodulator
•
(G)FSK demodulator
•
Direct interface to Semtech transceivers
•
SX1255, SX1257 and SX1250
•
Single 32 MHz clock
Ordering Information
Part Number
SX1303IMLTRT
Delivery
Tape and Reel
Order Quantity
3000
QFN68 Package, operating range from -40 to +85°C
Pb-free, Halogen free, RoHS/WEEE compliant product
SX1303
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Revision History
Version
Rev 1.0
Rev 1.1
Rev 1.2
ECO
ECO-051672
ECO-053422
ECO-053763
Date Modifications
April 2020 First Release
September 2020 Edit the link to the HAL/Packet Forwarder repository
October 2020 Update title to “LoRa Gateway Baseband Processor”
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Table of Contents
SX1303
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SX1303
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List of Figures
SX1303
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List of Tables
SX1303
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1. Introduction
packets expected in the IOT networks.
1.1 RF Front End Interface
The SX1303 is intended to be used with various RF Front End chips (RF to IQ), such as Semtech’s SX1255/57. Details on the
interface and compatibility is available on Section 4. "RF Front End Interface" on page 16 .
1.2 Power Distribution
The SX1303 is supplied on two different domains, 1.2 V for the core of the baseband processing, and 3 to 3.6V for the host
and RF interface. For details, see Section 5. "Power Distribution" on page 18 .
1.3 Clocking
1.4 Detection Engine, Modems and Timestamping
The SX1303 can detect at any time, any packet in a combination of 8 different spreading factors (SF5 to SF12) and 10 channels. Details on the modems and their assignment are found in
Section 7. "Detection Engine - Modems" on page 20 .
A number of modems can also provide Fine Timestamp capability for geo-positioning purposes.
1.5 Digital Interface and Control
1.6 Application Programming Interface
An example API is made available as source code with the HAL library and the Packet Forwarder example software. Details
are available in Section 9. "Application Programming Interface" on page 23 .
1.7 Application Information
Semtech has designed, validated, and released multiple reference design with the SX1302, which is 100% hardware compatible with the SX1303. The performance tabulated in this document is obtained on the said reference designs.
Details of the Core Cell reference design are posted in
Section 10. "Application Information" on page 24 .
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2. Pin Connections
2.1 Pinout
Table 2-1: Pinout
Pin Name
19
20
17
18
15
16
13
14
21
22
23
11
12
9
10
7
8
5
6
Pin
Number
(0)
3
4
1
2
GND
HOST_CSN
HOST_MISO
HOST_MOSI
HOST_SCK
VCC_CORE
GND
RESET
PPS
GND
RADIO_CTRL[0]
RADIO_CTRL[1]
RADIO_CTRL[2]
RADIO_CTRL[3]
VCC_IO
GND
RADIO_CTRL[4]
RADIO_CTRL[5]
RADIO_B_CSN
RADIO_B_MOSI
SP_VALID
RADIO_B_SCK
RADIO_CTRL[6]
VCC_CORE
Direction
Input
Input
Power
Output
Output
Output
Output
Power
Power
Input
Output
Input
Input
Power
Power
Power
Output
Output
Output
Output
Input
Output
Output
Power
Description SX1250
Ground
External HOST SPI CSN pin
External HOST SPI MISO pin
External HOST SPI MOSI pin
External HOST SPI SCK pin
Core supply
Ground
Asynchronous Reset Input
PPS input from GPS
Ground
Radio A Enable LDO
Radio A Enable LNA and control switch
Radio A Enable PA and control switch
Radio A Reset
IO supply
NRESET
Ground
Radio A PA gain_0
Radio A PA gain_1
Radio B SPI CSN pin
Radio B SPI MOSI pin
Stream synchronization for FPGA
Radio B SPI SCK pin
Radio B Enable LDO
Core supply
NSS
MOSI
SCK
NSS
MOSI
SCK
SX1255/57
RESET
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Table 2-1: Pinout
Pin Name Pin
Number
46
47
44
45
42
43
40
41
50
51
48
49
38
39
36
37
34
35
32
33
30
31
28
29
26
27
24
25
VCC_CORE
RADIO_A_IQ[3]
RADIO_A_MISO
RADIO_A_CLK_I
RADIO_A_IQ[0]
RADIO_A_IQ[1]
GND
VCC_IO
RADIO_A_IQ[4]
RADIO_A_IQ[2]
GPIO[11]
GPIO[10]
GND
GND
RADIO_CTRL[7]
RADIO_CTRL[8]
RADIO_CTRL[9]
RADIO_CTRL[10]
VCC_IO
RADIO_CTRL[11]
RADIO_B_IQ[3]
RADIO_B_MISO
RADIO_B_CLK_I
RADIO_B_IQ[0]
RADIO_B_IQ[1]
RADIO_B_IQ[4]
RADIO_B_IQ[2]
GND
Direction
Power
I/O - NS
Input
Input
I/O - NS
I/O - NS
Power
Power
I/O - NS
I/O - NS
In/out
In/out
I/O - NS
Input
Input
I/O - NS
I/O - NS
I/O - NS
I/O - NS
Power
Power
Power
Output
Output
Output
Output
Power
Output
Description SX1250
Ground
Ground
Radio B Enable LNA and control switch
Radio B Enable PA and control switch
Radio B Reset
Radio B PA gain_0
IO supply
Radio B PA gain_1
NRESET
DIO4
MISO
BUSY
DIO1
DIO2
DIO5
DIO3
Ground
Core supply
DIO4
MISO
BUSY
DIO1
DIO2
Ground
IO supply
DIO5
DIO3
General purpose IO
General purpose IO
SX1255/57
RESET
I_OUT
MISO
CLK_OUT
Q_OUT
I_IN
Q_IN
CLK_IN
I_OUT
MISO
CLK_OUT
Q_OUT
I_IN
Q_IN
CLK_IN
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Table 2-1: Pinout
Pin Name Pin
Number
68
(0)
66
67
64
65
62
63
60
61
58
59
56
57
54
55
52
53
GPIO[9]
GPIO[8]
GPIO[7]
GND
VCC_CORE
GPIO[6]
GPIO[5]
GPIO[4]
GPIO[3]
VCC_IO
GND
GPIO[2]
GPIO[1]
RADIO_A_SCK
GPIO[0]
RADIO_A_MOSI
RADIO_A_CSN
GND
Direction
In/out
Power
Power
In/out
In/out
Output
Input
Output
Output
Power
In/out
In/out
In/out
Power
Power
In/out
In/out
In/out
Description
General purpose IO
General purpose IO
General purpose IO
Ground
Core supply
General purpose IO
General purpose IO
General purpose IO
General purpose IO
IO supply
Ground
General purpose IO
General purpose IO
Radio A SPI SCK pin
General purpose IO
Radio A SPI MOSI pin
Radio A SPI CSN pin
Ground
SX1250 SX1255/57
SCK
MOSI
NSS
SCK
MOSI
NSS
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2.2 Package View
ϱϮ ϭϴ
Figure 2-1: Pin Locations, Top View
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3. Specifications
All measured performances and conditions are listed in this chapter. Quantitative indications left in other chapters are for the ease of reading and are indicative only.
The following specifications are given for the typical operating conditions of VCC_IO = VBAT = 3.3 V, temperature = 25 °C
(85°C for maximum values), reference oscillator frequency = 32 MHz, RF centre frequency = 868 MHz. All RF impedances are
matched using the reference design, see Section 10.2 "Reference Block Diagram" on page 24
and co-channel rejection are given for a single tone interferer and referenced to sensitivity level +6 dB.
3.1 ESD Notice
The SX1303 has built-in ESD and latch-up protection.
It should however be handled with all the necessary ESD precautions to avoid any permanent damage.
Table 3-1: ESD and Latch-Up Notice
Symbol
ESD_HBM
ESD_CDM
LU
Description
Class 2 of ANSI/ESDA/JEDEC Standard JS-001-2014
(Human Body Model)
ESD Charged Device Model, JEDEC standard
JESD22-C101, class C4
Latch-up, JEDEC standard JESD78 B, class I level A
Min
-
-
-
Typ
-
-
-
Max
2
500
100
Unit
kV
V mA
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3.2 Absolute Minimum and Maximum Ratings
Table 3-2: Minimum and Maximum Ratings
Symbol
V
CCIO,ABSMAX
V
CCcore,ABSMAX
T
STORE
T
REFLOW
MSL
Description
IO power supply to VSS
Core power supply to VSS
Storage temperature
Peak reflow temperature
Humidity rating
Min
-0.5
-0.5
-40
Max
4.0
1.5
+125
260
MSL1
3.3 Operating Range
Table 3-3: Operating Range
Symbol
V
CCIO,OP
V
CCCORE,OP
T
A,OP
Description
IO supply operating conditions
Core supply operating conditions
Operating temperature
Minimum
3.0
1.1
-40
Typical
3.3
1.2
25
Maximum
3.6
1.3
+85
Unit
V
V
°C
°C
Unit
V
V
°C
3.4 Electrical Specifications
The reference design described in
Section 10. "Application Information" on page 24
is used to measure this performance.
Table 3-4: Performances
Symbol
IDD_8CH_CO
RE
IDD_8CH_IO
IDD_8CH_AV
G_CORE
IDD_8CH_PE
AK_CORE
IDD_8CH_AV
G_IO
Description
Average consumption when all correlators are active
(no packet detected, no modem activated), on VCC_CORE
Average consumption when all correlators are active
(no packet detected, no modem activated), on VCC_IO
Average consumption when all correlators are active, and 16 modems are active, on VCC_CORE
Peak
1
consumption when all correlators are active, and 16 modems are active, on VCC_CORE
Average consumption when all correlators are active, and 16 modems are active, on VCC_IO
Min Typ Max Unit
-
-
-
-
15
1
17
28
1
77
85
-
-
mA mA mA mA mA
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Table 3-4: Performances
Symbol
IDD_TX_COR
E
IDD_TX_IO
IDD_OFF_CO
RE
IDD_OFF_IO
Description
Sending data on SX1250 using SF6, average, on VCC_CORE
Sending data on SX1250 using SF6, average, on VCC_IO
OFF current, clock is disabled, on VCC_CORE
Min
-
-
-
Typ
7.2
1.4
3.2
Max
-
-
-
Unit
mA mA mA
FERR
On VCC_IO
Frequency Offset Tolerance, less than 3dB degradation
2
-
10
-
-
+/-0.25*
BW uA
Hz
1. Average and Peak current concepts are explained in
3.5 Digital I/O Specifications
Table 3-5: Digital I/O Specifications
Symbol
VIH
VIL
VOH
VOL
Description
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Conditions
-
I max
= -8 mA
I max
= 8mA
Min
0.7*VCC_IO
-0.3
VCC_IO - 0.6
0
Typ
-
-
-
-
Max
VCC_IO + 0.3
0.3*VCC_IO
VCC_IO
0.4
Unit
V
V
V
V
All inputs are floating and should be driven to a proper potential to avoid current leakage in low-power modes. GPIO[i] pins have a selectable internal 100 kOhms pull-down resistor, when configured as inputs, and they are disabled at Reset.
3.6 Example Reference Design Performance
Disclaimer:
the performance specifications listed below are only indicative, and obtained on the reference design described in
Section 10.2 "Reference Block Diagram" on page 24
.
Sensitivity is specified with a PER=10%, receiving 12 Byte packets, all under nominal temperature and voltage conditions.
It is measured with a SX1250 front-end, an LNA with 18dB of gain and 1.5 dB of Noise Figure.
Table 3-6: Reference Design Performance
Symbol
S_SF5_125
S_SF6_125
S_SF7_125
S_SF8_125
Description
SF5 Sensitivity, LoRa 125 kHz bandwidth
SF6 Sensitivity, LoRa 125 kHz bandwidth
SF7 Sensitivity, LoRa 125 kHz bandwidth
SF8 Sensitivity, LoRa 125 kHz bandwidth
Min Typ Max Unit
-
-
-
-121
-123.5
-127
-129 -
-
-
dBm dBm dBm dBm
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Table 3-6: Reference Design Performance
Symbol
S_SF9_125
S_SF10_125
S_SF11_125
S_SF12_125
S_FSK_50
S_SF9_250
Description
SF9 Sensitivity, LoRa 125 kHz bandwidth
SF10 Sensitivity, LoRa 125 kHz bandwidth
SF11 Sensitivity, LoRa 125 kHz bandwidth
SF12 Sensitivity, LoRa 125 kHz bandwidth
50 kbps, GFSK modulation
SF9 Sensitivity, LoRa 250 kHz bandwidth
Min Typ Max Unit
-
-
-
-
-
-132.5
-135.5
-138
-141
-111
-126.5
-
-
-
-
-
dBm dBm dBm dBm dBm dBm
A complete performance report of the reference design published in
Section 10.2 "Reference Block Diagram" on page 24 is
posted on www.semtech.com.
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4. RF Front End Interface
The SX1303 can accommodate any of the following RF front-end devices: SX1250, SX1255 and SX1257, all of which are
Semtech products. For any other device, hardware logic could be used on the interface for translation purposes.
The roles of these devices is to down-convert the RF signal to baseband (direct conversion or low-IF), and digitize it to feed the IQ samples to the SX1303 baseband chip.
The interconnection to the front-end device is organized as follows. Here, the SX1250 is taken as an example:
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I(t)
2
Q(t)
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Gain Control Interface
4
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Modulator input
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Sigma-delta clock sync
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Figure 4-2: Transmit Interconnection
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The table hereafter summarizes the characteristics of the three front-end devices currently supported with the SX1303:
Table 4-1: Semtech RF Front-end Summary
Part #
SX1255
SX1257
SX1250
Frequency Band Receive BW Output Power
400 - 510 MHz
862 - 1020 MHz
150 - 960 MHz
1 MHz
1 MHz
1 MHz
About 0 dBm
About 0 dBm
+22 dBm
Rx NF
5 dB
5 dB
10 dB
Comment
5x5 mm package, 20 mA Rx
5x5 mm package, 20 mA Rx
4x4 mm package, 5 mA Rx
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5. Power Distribution
The SX1303 needs two powers rails: VCC_IO and VCC_CORE. VCC_IO sets the voltage level for all of the digital interfaces of the chip (SPI, GPIO and IQ interface), whilst VCC_CORE supplies current to the baseband engine. VCC_CORE can be derived from a higher voltage source with a high-efficiency
DC-DC buck converter, as it is only 1.2 V. An optimized power
management strategy is proposed in Semtech’s reference designs, and one example of displayed in
"Reference Block Diagram" on page 24 .
The following currents can be measured, and should be used to design the power supply in the system:
Table 5-1: Current Consumption
Average current
Peak current
Average current
Peak current
Average current
Peak current
Conditions
Temperature
25°C
25°C
60°C
60°C
85°C
85°C
VCC_CORE
@ 1.2 V
17 mA
28 mA
48 mA
55 mA
77 mA
85 mA
During a reception phase, the current observed won’t be always the same, but will spike up during certain phases of the reception. Therefore, the
average current
should be used to compute the total energy consumption of the SX1303 based gateway, however the
peak current
will be the relevant metric to size the power supply components.
To ensure proper control of all digital IOs during the power-up and power-down sequences of the SX1303, VCC_CORE shall be enabled
before
VCC_IO at start-up, and disabled
after
VCC_IO at shut-down.
Start-up Shut-down
VCC_CORE VCC_CORE
VCC_IO VCC_IO
Δt1
Figure 5-1: VCC_CORE and VCC_IO Sequencing
Δt1 and Δt2 must be equal to or greater than 0.
Δt2
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6. Clocking
The SX1303 uses the 32 MHz clock source from its companion RF Front-end (for example, Semtech’s SX1250) to clock the entire system. This clock is injected on pin 43 (RADIO_A_CLK_I). It is advised to use a GPS-precision TCXO (0.5 ppm), in order to have a maximum “capture range” for the receiver, allowing lower precision reference clock, which are cheaper, on the end-devices.
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7. Detection Engine - Modems
The SX1303 offers Fine Timestamp capability, which can be used with Semtech’s differential time of arrival technology. A holistic detection engine can capture any
LoRa® traffic in the pre-defined frequency plan, assigning the detected packets
to the pool of available modems for demodulation. Two modes are proposed for the modem assignment strategy, when timestamps are used:
•
Higher Capacity:
Up to 8 packets at any given time can be received for any Spreading Factor. These packets are timestamped, with the exception of packets at SF11 and SF12 (data only).
•
Timestamp for all Spreading Factors:
Up to 8 packets at Spreading Factor SF5-12 can be received at any time, including, at most, 4 packets at SF11 and/or SF12.
All these packets will be timestamped.
1 high-speed multi-BW
modem (125, 250 or 500 kHz), handling a single declared SF, and 1 FSK modem is also available.
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8. Digital Interface and Control
The transceiver is controlled via a serial interface (
) and a set of general purpose input/output (DIOs).
8.1 Host SPI Interface
= 0 and
CPHA = 0 in Motorola/Freescale nomenclature.
An address byte followed by a data byte is sent for a write access whereas an address byte is sent and a read byte is received for the read access. The CSN pin goes low at the beginning of the frame and goes high after the data byte.
MOSI is generated by the master on the falling edge of SCK
and is sampled by the slave (i.e. this SPI interface) on the rising edge of
SCK . MISO is generated by the slave on the falling edge of SCK.
A transfer is always started by the CSN pin going low.
is high impedance when CSN is high.
The host terminates an SPI transaction by raising the CSN signal, it does not explicitly send the command length as a parameter. The host must not raise CSN within the bytes of a transaction.
8.1.1 HOST SPI Timings
CSN t
DELAY
SCK t
SCK t
SETUP t
HOLD
MOSI t
DOEN
MISO t
SCKH t
SCKL t
DOV t
QUIET t
DODIS t
CSH
Figure 8-1: SPI Timing Diagram
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8.1.2 SPI Timings
All timings are given in next table for Max load cap of 10 pF.
Table 8-1: SPI Timing Requirements
Minimum Symbol Description
t
Timing constraints in SPI inputs
SPI,SCK
SCK period t
SPI,SCKH
SCK high duration t
SPI,SCKL t
SPI,SCKR t
SPI,SCKF
SCK low duration
SCK rise time (10% VCC_IO ->90% VCC_IO)
SCK fall time (90% VCC_IO ->10% VCC_IO) t
SPI,DELAY t
SPI,QUIET t
SPI,CSH
SCK lead time
SCK trail time
Time between two successive CSN chip select
CSN rise time (10% VCC_IO ->90% VCC_IO) t
SPI,CSR t
SPI,CSF t
SPI,SETUP t
SPI,DODIS t
SPI,DOV
CSN fall time (90% VCC_IO ->10% VCC_IO)
Data in setup time t
SPI,HOLD
Data in hold time
SPI output timing specification t
SPI,DOEN
SPI output enable time
SPI output disable time
SCK out falling edge to MISO delay
100
40
40
0
0
40
40
250
0
0
5
5
0
0
Typical Maximum
2.5
2.5
2.5
2.5
10
10
15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
9. Application Programming Interface
Through
interface, the SX1303 is fully controlled by its host, whether it is a MCU (smal-size cell) or a Linux MPU for higher-end gateways.
Semtech fully abstracts the complexity of the SX1303 and its companions chips by delivering two libraries as open-source code:
•
SX1303 HAL (Hardware Abstraction layer), incorporating all of the required code to initialize, calibrate, run and exchange radio packets with the gateway board
•
SX1303 Packet Forwarder, which is a simple example application of how a gateway can be connected to a host. The host, in a LoRaWAN network, is typically cloud-based, but can also be co-located with the gateway in case of small-scale networks
All of these open-sourced libraries are available from Github on https://github.com/Lora-net/sx1302_hal
9.1 Globally Unique EUI
The SX1303 chip is serialized in production, with a globally unique 64-bit number. It may be used by the application for identification and security purposes.
This 64-bit EUI can be retrieved with the function
lgw_get_eui()
available in the HAL library.
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
10. Application Information
The Core cell reference design represents a compact reference implementation of the SX1303, along with its power management, clocks, Front End Module, RF matching and filtering.
10.1 Geographical Designs
The suitability of the SX1303-based reference designs to national radio frequency regulations depends on the RF front-end device being used. With the SX1250/55/57 front-ends provided by Semtech, the expectation is:
•
Up to +27 dBm supported in the USA, Canada or other FCC-type countries
•
Up the +27 dBm in Europe and other ITU 1 regions
•
Up to +21 dBm in Japan where the phase noise requirement is more stringent
10.2 Reference Block Diagram
The application block diagram is shown below:
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ZĞƐĞƚ
^W/ ůŬͺϯϮͺD,nj
/ͬY
ŶĂďůĞ͕>EĂĐƚŝǀĞ͕WĂĐƚŝǀĞ͕WŐĂŝŶ dyK ^yϭϯϬϯ
ZĞƐĞƚ
^W/
,K^d
Wͬ>E
ŶĂďůĞ͕>EĂĐƚŝǀĞ͕WĂĐƚŝǀĞ͕WŐĂŝŶ
^yϭϮϱϬ
ZĞƐĞƚ
^W/ ůŬͺϯϮͺD,nj
/ͬY
KƉƚŝŽŶĂů'W^
Figure 10-1: Application Design Block Diagram
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
10.3 Reference Design Layout
Figure 10-2: Reference Design PCB Layout
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
11. Packaging Information
11.1 Package Outline Drawing
The transceiver is delivered in a 7x7mm QFN package with 0.35mm pitch:
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
Figure 11-1: QFN 7x7 Package Outline Drawing
www.semtech.com
11.2 Package Marking
Figure 11-2: SX1303 Package Marking
11.3 Land Pattern
The recommended land pattern is as follows:
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
Figure 11-3: QFN 7x7mm Land Pattern
www.semtech.com
11.4 Reflow Profiles
Reflow process instructions are available from the Semtech website, at the following address:
http://www.semtech.com/quality/ir_reflow_profiles.html
The transceiver uses a QFN68 7x7mm package, also named MLP package.
11.5 Tape and Reel Specification
Pin #1
Figure 11-4: Tape and Reel Specification
Table 11-1: Tape and Reel Specification
Carrier Tape (mm) Reel
Package
Size
Tape
Width
1
(W)
2
Pitch
(P)
A
O
3
B
O
K
O
4
Reel
Size
[in]
Reel
Width
[mm]
Min.
Trailer
Length
[mm]
Min.
Leader
Length
[mm]
7 x 7 16 12 7.3
1. Tolerance for tape width is +/- 0.3 mm
2. Single Sprocket holes, pocket pitch range +/-0.1 mm
3. Range from nominal values for Ao and Bo is +/-0.2 mm
4. Range is +/-0.1 mm
7.3
1.1
13 16.4
400 400
QTY per
Reel
3000
11.6 Thermal Impedance
The thermal impedance of this package is:
•
28.3 °C/W when used in still air (natural convection)
•
21.6 °C/W when used with an air speed of 1 m/s
•
19.5 °C/W when used with an air speed of 2.5 m/s
This measurement is made with a 1.6 mm 4-layer PCB of 87 cm
2
, metallized over 55 cm
2
, with 16 vias of 0.3 mm diameter.
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
Glossary
List of Acronyms and their Meaning
Acronym
GFSK
GMSK
IF
IRQ
LDO
LNA
CSN
CW
DC-DC
DIO
DSB
FEC
FLRC
FSK
CPOL
CPHA
CR
CRC
BT
BW
CAD
CMD
ACR
ADC
AFC
AGC
API
β
BR
Meaning
Adjacent Channel Rejection
Analog-to-Digital Converter
Automatic Frequency Correction
Automatic Gain Control
Application Programming Interface
Modulation Index
Bit Rate
Bandwidth-Time bit period product
BandWidth
Channel Activity Detection
Command Transaction
Clock Polarity
Clock Phase
Coding Rate
Cyclical Redundancy Check
Chip Select active low
Continuous Wave
Direct Current to Direct Current converter
Digital Input / Output
Double Side Band
Forward Error Correction
Fast Long Range Communication
Frequency Shift Keying
Gaussian Frequency Shift Keying
Gaussian Minimum Shift Keying
Intermediate Frequencies
Interrupt Request
Low-Dropout
Low-Noise Amplifier
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
SNR
SPI
STDBY
TCXO
UART
XOSC
PLL
PRNG
RFU
RTC
RTSN
SCK
SF
SN
PA
PDU
PER
PID
NESN
NOP
NRZ
OOK
LSB
MD
MIC
MISO
MOSI
MSB
MSK
List of Acronyms and their Meaning
Acronym
LO
LoRa®
Meaning
Local Oscillator
Long Range Communication
the LoRa® Mark is a registered trademark of the Semtech Corporation
Least Significant Bit
More Data
Message Integrity Check
Master Input Slave Output
Master Output Slave Input
Most Significant Bit
Minimum-Shift Keying
Next Expected Sequence Number
No Operation
Non-Return-to-Zero
On-Off Keying
Power Amplifier
Protocol Data Unit
Packet Error Rate
Product Identification
Phase-Locked Loop
Pseudo-Random Number Generation
Reserved for Future Use
Real-Time Clock
Request to Send
Serial Clock
Spreading Factor
Sequence Number
Signal to Noise Ratio
Serial Peripheral Interface
Standby
Temperature Compensated Crystal Oscillator
Universal Asynchronous Receiver/Transmitter
Crystal Oscillator
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
www.semtech.com
Important Notice
Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. Semtech warrants performance of its products to the specifications applicable at the time of sale, and all sales are made in accordance with Semtech’s standard terms and conditions of sale.
SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS, OR IN NUCLEAR APPLICATIONS IN WHICH THE FAILURE COULD BE REASONABLY EXPECTED TO
RESULT IN PERSONAL INJURY, LOSS OF LIFE OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. INCLUSION OF SEMTECH PRODUCTS IN
SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use
Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise.
The Semtech name and logo are registered trademarks of the Semtech Corporation. The LoRa® Mark is a registered trademark of the
Semtech Corporation. All other trademarks and trade names mentioned may be marks and names of Semtech or their respective companies. Semtech reserves the right to make changes to, or discontinue any products described in this document without further notice. Semtech makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose. All rights reserved.
© Semtech 2020
Contact Information
Semtech Corporation
Wireless & Sensing Products
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com
SX1303
Datasheet
DS.SX1303.W.APP
Rev 1.2
Oct 2020
31
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Key features
Supports all LoRaWAN® classes
High-speed 500 kHz LoRa demodulator
Fine timestamping for network-based geolocation
Direct interface to Semtech transceivers (SX1255, SX1257, and SX1250)
Single 32 MHz clock source
Low power consumption
Serialized production with a globally unique 64-bit number
Frequently asked questions
The SX1303 is a LoRa® baseband processor with integrated RF front-end for gateways. It supports all LoRaWAN® classes, features a high-speed 500 kHz LoRa demodulator, and has a low power consumption.
The SX1303 simplifies the design of LoRa gateways and reduces the overall system cost. It is an ideal solution for LoRa gateway applications that require high performance, low power consumption, and low cost.
The SX1303 is ideal for LoRa gateway applications that require high performance, low power consumption, and low cost. These applications include smart city, industrial, and home automation.
