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MVME162P2
VME Embedded Controller
Installation and Use
V162P2A/IH2
Edition of November 2000
© Copyright 2000 Motorola, Inc.
All rights reserved.
Printed in the United States of America.
Motorola
® and the Motorola logo are registered trademarks of Motorola, Inc.
MC68040™ and MC68060™ are trademarks of Motorola, Inc.
IndustryPack™ and IP™ are trademarks of GreenSpring Computers, Inc.
All other products mentioned in this document are trademarks or registered trademarks of their respective holders.
Safety Summary
The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Ground the Instrument.
To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground
(safety ground) at the power outlet. The power jack and mating plug of the power cable meet International
Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.
Do Not Operate in an Explosive Atmosphere.
Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes.
Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.
Keep Away From Live Circuits Inside the Equipment.
Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Service personnel should not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits before touching components.
Use Caution When Exposing or Handling a CRT.
Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent
CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves.
Do Not Substitute Parts or Modify Equipment.
Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local
Motorola representative for service and repair to ensure that all safety features are maintained.
Observe Warnings in Manual.
Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.
Warning
To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its components.
Flammability
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers.
EMI Caution
!
Caution
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Lithium Battery Caution
This product contains a lithium battery to power the clock and calendar circuitry.
!
Caution
Danger of explosion if battery is replaced incorrectly. Replace battery only with the same or equivalent type recommended by the equipment manufacturer. Dispose of used batteries according to the manufacturer’s instructions.
!
Attention
Il y a danger d’explosion s’il y a remplacement incorrect de la batterie.
Remplacer uniquement avec une batterie du même type ou d’un type
équivalent recommandé par le constructeur. Mettre au rebut les batteries usagées conformément aux instructions du fabricant.
!
Vorsicht
Explosionsgefahr bei unsachgemäßem Austausch der Batterie. Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ. Entsorgung gebrauchter Batterien nach Angaben des Herstellers.
CE Notice (European Community)
Motorola Computer Group products with the CE marking comply with the EMC Directive
(89/336/EEC). Compliance with this directive implies conformity to the following
European Norms:
EN55022 “Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment”; this product tested to Equipment Class B
EN50082-1:1997 “Electromagnetic Compatibility—Generic Immunity Standard, Part
1. Residential, Commercial and Light Industry”
System products also fulfill EN60950 (product safety) which is essentially the requirement for the Low Voltage Directive (73/23/EEC).
Board products are tested in a representative system to show compliance with the above mentioned requirements. A proper installation in a CE-marked system will maintain the required EMC/safety performance.
In accordance with European Community directives, a “Declaration of Conformity” has been made and is on file within the European Union. The “Declaration of Conformity” is available on request. Please contact your sales representative.
Notice
While reasonable efforts have been made to assure the accuracy of this document,
Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Computer Group website. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Motorola, Inc.
It is possible that this publication may contain reference to or information about Motorola products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.
Limited and Restricted Rights Legend
If the documentation contained herein is supplied, directly or indirectly, to the U.S.
Government, the following notice shall apply unless otherwise agreed to in writing by
Motorola, Inc.
Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
1995) and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252.227-7014 (Jun. 1995).
Motorola, Inc.
Computer Group
2900 South Diablo Way
Tempe, Arizona 85282
Contents
CHAPTER 1 Hardware Preparation and Installation
SRAM Backup Power Source (J14) .................................................................1-10
General-Purpose Readable Switch (S4 Pin 5) ..................................................1-16
vii
CHAPTER 2 Startup and Operation
CNFG - Configure Board Information Block .................................................... 3-9
CHAPTER 4 Functional Description
viii
EPROM and Flash Memory ......................................................................4-11
Battery-Backed-Up RAM and Clock................................................................4-12
Serial Communications Interface ..............................................................4-13
Programmable Tick Timers .......................................................................4-16
Software-Programmable Hardware Interrupts...........................................4-16
Special Considerations for Elevated-Temperature Operation ...........................A-3
ix
APPENDIX C Network Controller Data
APPENDIX D Disk/Tape Controller Data
APPENDIX E Related Documentation
x
List of Figures
Figure 2-1. MVME162P2/Firmware System Startup ................................................2-3
xi
xii
List of Tables
Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs ....................................1-13
Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs ....................................1-13
Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs ....................................1-14
Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs........................................1-14
Table 1-7. EPROM/Flash Mapping —
1M x 8 EPROMs, Onboard Flash Disabled .....................................................1-14
Table 5-1. Remote Reset Connector J2 Pin Assignments ..........................................5-2
Table 5-3. DB15 Ethernet Connector Pin Assignments.............................................5-4
Table 5-6. VMEbus Connector P1 Pin Assignments .................................................5-7
Table 5-7. VMEbus Connector P2 Pin Assignment...................................................5-8
Table B-1. Troubleshooting MVME162P2 Boards ................................................. B-1
Table E-1. Motorola Computer Group Documents ................................................. E-1
xiii
xiv
About This Manual
MVME162P2 VME Embedded Controller Installation and Use provides instructions for hardware preparation and installation; a board-level hardware overview; and firmware-related general information and startup instructions for the MVME162P-242 series of embedded controllers, known collectively as the ‘‘MVME162P2’’ because they are equipped with the “Petra” chip and accommodate up to two IP modules.
The “Petra” chip that distinguishes MVME162P2 embedded controllers is an application-specific integrated circuit (ASIC) which combines the functions previously covered by the MC2 chip, the IP2 chip, and the
MCECC chip in a single ASIC. As of the publication date, the information presented in this manual applies to the following MVME162P2 models:
Model Number Characteristics
MVME162P-242L 25MHz 68LC040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP
MVME162P-242LE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet
MVME162P-242LSE 25MHz 68LC040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,
SCSI/Ethernet
MVME162P-242
MVME162P-242E
MVME162P-242SE
25MHz 68040, 16MB SDRAM w/parity, 4 SIO, 2 DMA IP
25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP, Ethernet
25MHz 68040, 16MB SDRAM w/ECC, 4 SIO, 2 DMA IP,
SCSI/Ethernet
If the part number of your board includes a "PA" (for example:
MVME162PA-242L), your board is equipped with a second-generation
Petra ASIC. All other particulars of the board remain the same.
This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in the Related Documentation section in Appendix E.
xv
Summary of Changes
This is the second edition of MVME162P2 Installation and Use. It supersedes the June 2000 edition and incorporates the following updates.
Date Description of Change
October 2000
In the description of the snoop control switch on page 1-18 , entries in the table
concerning boards equipped with the MC68060 processor have been corrected.
October 2000 Several jumper drawings and configuration descriptions in Chapters 1 and 2 have been updated to reflect the current board layout and shipping configuration.
October 2000 In the descriptions of the MC2 and MCECC DRAM size switches on pages
and
1-21 , the importance of executing env;d after modifying switch
settings has been emphasized.
Overview of Contents
Chapter 1, Hardware Preparation and Installation
, provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162P2 VME Embedded Controller.
Chapter 2, Startup and Operation , provides information on powering up
the MVME162P2 VME Embedded Controller after its installation in a system and describes the functionality of the switches, status indicators, and I/O ports.
, describes the basics of 162Bug and its architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on using the debugger and special commands.
Chapter 4, Functional Description , describes the MVME162P2 VME
Embedded Controller on a block diagram level.
, summarizes the pin assignments for the various groups of interconnect signals on the MVME162P2.
xvi
Appendix A, Specifications , lists the general specifications for the
MVME162P2 Embedded Controller. Subsequent sections of the appendix detail cooling requirements and EMC regulatory compliance.
Appendix B, Troubleshooting , includes simple troubleshooting steps to
follow in the event that you have difficulty with your MVME162P2 VME
Embedded Controller.
Appendix C, Network Controller Data , describes the VMEbus network
controller modules that are supported by the 162Bug firmware.
Appendix D, Disk/Tape Controller Data
, describes the VMEbus disk/tape controller modules that are supported by the 162Bug firmware.
Appendix E, Related Documentation , provides all documentation related
to the MVME162P2.
Comments and Suggestions
Motorola welcomes and appreciates your comments on its documentation.
We want to know what you think about our manuals and how we can make them better. Mail comments to:
Motorola Computer Group
Reader Comments DW164
2900 S. Diablo Way
Tempe, Arizona 85282
You can also submit comments to the following e-mail address: [email protected]
In all your correspondence, please list your name, position, and company.
Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
xvii
Conventions Used in This Manual
The following typographical conventions are used in this document: bold is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.
italic is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.
courier is used for system output (for example, screen displays, reports), examples, and system prompts.
<Enter>, <Return> or <CR>
<CR> represents the carriage return or Enter key.
CTRL represents the Control key. Execute control characters by pressing the
Ctrl key and the letter simultaneously, for example, Ctrl-d.
A character precedes a data or address parameter to specify the numeric format, as follows:
$ Specifies a hexadecimal character
0x Specifies a hexadecimal number
% Specifies a binary number
& Specifies a decimal number
An asterisk (
∗
) following a signal name for signals that are level significant denotes that the signal is true or valid when the signal is low. An asterisk
(
∗
) following a signal name for signals that are edge significant denotes that the actions initiated by that signal occur on high to low transition. xviii
1
Hardware Preparation and
Installation
1
Introduction
This chapter provides unpacking instructions, hardware preparation guidelines, and installation instructions for the MVME162P2 VME
Embedded Controller.
Getting Started
This section supplies an overview of startup procedures applicable to the
MVME162P2. Equipment requirements, directions for unpacking, and
ESD precautions that you should take complete the section.
Overview of Installation Procedure
The following table lists the things you will need to do to use this board and tells where to find the information you need to perform each step. Be sure to read this entire chapter, including all Cautions and Warnings, before you begin.
Table 1-1. Startup Overview
What you need to do...
Unpack the hardware.
Reconfigure jumpers or switches on the MVME162P2 board as necessary.
Ensure that IP modules are properly installed on the
MVME162P2 board.
Install the MVME162P2 board in a chassis.
Connect a display terminal.
Refer to...
Guidelines for Unpacking on page 1-3 .
Preparing the Board on page 1-4
.
IP Installation on page
MVME162P2 Installation on page 1-23 .
Serial Connections on page
.
1-1
1
Hardware Preparation and Installation
Table 1-1. Startup Overview (Continued)
What you need to do...
Connect any other equipment you will be using.
Power up the system.
Note that the firmware initializes and tests the board.
Initialize the system clock.
Examine and/or change environmental parameters.
Program the board as needed for your applications.
Refer to...
Connector Pin Assignments in Chapter 5.
For more information on optional devices and equipment, refer to the documentation provided with the equipment.
Applying Power on page
Solving Startup Problems on page
Bringing Up the Board on page
You may also wish to obtain the 162Bug Firmware User’s
Manual, listed in the Related Documentation appendix.
Debugger Commands on page 3-6 .
Modifying the Environment on page 3-8 .
Programmer’s Reference Guide, listed in the Related
Documentation appendix.
Equipment Required
The following equipment is necessary to complete an MVME162P2 system:
❏ VME system enclosure
❏ System console terminal
❏ Operating system (and / or application software)
❏ Disk drives (and / or other I/O) and controllers
1-2 Computer Group Literature Center Web Site
Getting Started
Guidelines for Unpacking
Note If the shipping carton is damaged upon receipt, request that the carrier’s agent be present during the unpacking and inspection of the equipment.
Unpack the equipment from the shipping carton. Refer to the packing list and verify that all items are present. Save the packing material for storing and reshipping of equipment.
!
Caution
Avoid touching areas of integrated circuitry; static discharge can damage circuits.
ESD Precautions
This section applies to all hardware installations you may perform that involve the MVME162P2 board.
Use ESD
Wrist Strap
Motorola strongly recommends the use of an antistatic wrist strap and a conductive foam pad when you install or upgrade the board. Electronic components can be extremely sensitive to ESD. After removing the board from the chassis or from its protective wrapper, place the board flat on a grounded, static-free surface, component side up. Do not slide the board over any surface.
If no ESD station is available, you can avoid damage resulting from ESD by wearing an antistatic wrist strap (available at electronics stores). Place the strap around your wrist and attach the grounding end (usually a piece of copper foil or an alligator clip) to an electrical ground. An electrical ground can be a piece of metal that literally runs into the ground (such as an unpainted metal pipe) or a metal part of a grounded electrical appliance.
An appliance is grounded if it has a three-prong plug and is plugged into a three-prong grounded outlet. You cannot use the chassis in which you are installing the MVME162P2 itself as a ground, because the enclosure is unplugged while you work on it.
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Hardware Preparation and Installation
!
Warning
Turn the system’s power off before you perform these procedures. Failure to turn the power off before opening the enclosure can result in personal injury or damage to the equipment. Hazardous voltage, current, and energy levels are present in the chassis. Hazardous voltages may be present on power switch terminals even when the power switch is off. Never operate the system with the cover removed. Always replace the cover before powering up the system.
Preparing the Board
To produce the desired configuration and ensure proper operation of the
MVME162P2, you may need to reconfigure hardware to some extent before installing the board.
Most options on the MVME162P2 are under software control: By setting bits in control registers after installing the module in a system, you can modify its configuration. (The MVME162P2 registers are described in
Chapter 3 under ENV – Set Environment, and/or in the MVME1X2P2 VME
Embedded Controller Programmer's Reference Guide as listed under
“Related Documentation” in Appendix E.)
Some options, though, are not software-programmable. Such options are either set by configuration switches or are controlled through physical installation or removal of header jumpers on the base board.
1-4 Computer Group Literature Center Web Site
Preparing the Board
MVME162P2 Configuration
Figure 1-1 illustrates the placement of the jumper headers, connectors,
configuration switches, and various other components on the
MVME162P2. Manually configurable jumper headers and configuration switches on the MVME162P2 are listed in the following table.
Table 1-2. MVME162P2 Configuration Settings
Function
VME System Controller (J1) on page 1-7
IP Bus Strobe (J11) on page 1-7
SCSI Termination (J12) on page 1-8
IP Bus Clock (J13) on page 1-9
SRAM Backup Power Source (J14) on page 1-10
Flash Write Protection (J16) on page 1-11
EPROM/Flash Configuration (J20) on page 1-11
MC2 DRAM Size (S3) on page 1-15
General-Purpose Readable Switch (S4 Pin 5) on page 1-16
IP DMA Snoop Control (S5 Pins 1/2) on page 1-18
IP Reset Mode (S5 Pin 3) on page 1-19
Flash Write Enable Mode (S5 Pin 4) on page 1-20
MCECC DRAM Size (S6) on page 1-21
Factory Default
2-3
No Jumper
Jumper On
1-2
1-3, 2-4
Jumper On
5-6, 9-11, 8-10
Off-Off-Off
On
On-On
On
On
On-Off-On
J15 (also J24, if present) is a PLD programming header for lab or factory use. It has no user function.
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1
Hardware Preparation and Installation
MVME162
FAIL RUN
FUSES SCON
ABORT
RESET
1-6
Figure 1-1. MVME162P2 Board Layout
Computer Group Literature Center Web Site
Preparing the Board
VME System Controller (J1)
The MVME162P2 board is factory-configured in "automatic" system controller mode with a jumper across J1 pins 2-3. In this configuration, the
MVME162P2 determines whether it is the system controller by its position on the bus. If the board is located in the first slot from the left, it configures itself as the system controller. When the board is operating as system controller, the SCON LED is turned on.
If you want the MVME162P2 to function as system controller in all cases, move the jumper to pins 1-2. If the MVME162P2 is not to be system controller under any circumstances, remove the jumper from J1.
J1
Note On MVME162P2 boards without the optional VMEbus interface
(i.e., with no VMEchip2 ASIC), the jumper may be installed or removed with no effect on normal operation.
J1 J1
3 2 1 3 2 1 3 2 1
System Controller Auto System Controller
(factory configuration)
Not System Controller
IP Bus Strobe (J11)
Some IP bus implementations make use of the Strobe
∗
signal (pin AA19 on the Petra ASIC) as an input to the IP modules from the Petra IP2 sector.
Other IP interfaces require that the strobe be disconnected.
With a jumper installed between J11 pins 1-2, a programmable frequency source is connected to the Strobe
∗
signal on the IP bus (for details, refer to the Petra/IP2 chip programming model in the Programmer’s Reference
Guide).
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1
Hardware Preparation and Installation
If the jumper is removed from J11, the strobe line is available for a sideband type of messaging between IP modules. The Strobe
∗
signal is not connected to any active devices on the board, but it may be connected to a pull-up resistor.
J11
2
1
IP Strobe disconnected
(Factory configuration)
J11
2
1
IP Strobe connected
SCSI Termination (J12)
The MVME162P2 provides terminators for an SCSI bus. The SCSI terminators are enabled/disabled by a jumper on header J12. The SCSI terminators may be configured as follows.
J12
1 2
J12
1 2
Onboard SCSI Bus Terminators disabled Onboard SCSI Bus Terminators enabled
(Factory configuration)
Note If the MVME162P2 is to be located at either end of an SCSI bus, the SCSI bus terminators must be enabled.
1-8 Computer Group Literature Center Web Site
Preparing the Board
IP Bus Clock (J13)
J13 selects the speed of the IP bus clock. The IP bus clock speed may be
8MHz or it may be set synchronous to the processor bus clock (25MHz for the MC68040 and MC68LC040). The default factory configuration has a jumper installed on pins 1-2, denoting an 8MHz clock.
If the jumper is installed on J13 pins 2-3, the IP bus clock speed matches that of the processor bus clock (25MHz), allowing the IP module to pace the MPU. Whether the setting is 8MHz or the processor bus clock speed, all IP ports operate at the same speed.
!
Caution
The setting of the IP32 bit in the Control/Status registers (Petra IP2 sector, register at offset $1D, bit 0) must correspond to that of the jumper. The bit is cleared (0) for 8MHz, or set (1) to match the processor bus clock speed.
If the jumper and the CSR bit are not configured the same, the board may not run properly.
J13
1 2 3
J13
1 2 3
Bus Clock = 8MHz
(Factory configuration)
Bus Clock = Processor Bus Clock
(from MPU Bus Clock)
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Hardware Preparation and Installation
SRAM Backup Power Source (J14)
Header J14 determines the source for onboard static RAM backup power.
The MVME162P2 is factory-configured to use VMEbus +5V standby voltage as a backup power source for the SRAM (i.e., jumpers are installed across pins 1-3 and 2-4). To select the onboard battery as the backup power source, install the jumpers across pins 3-5 and 4-6.
Note For MVME162P2s without the optional VMEbus interface (i.e., without the VMEchip2 ASIC), you must select the onboard battery as the backup power source.
!
Caution
Removing all jumpers may temporarily disable the SRAM. Do not remove all jumpers from J14, except for storage.
J14 J14 J14
6 6 6 5 5 5
2 1
Primary Source Onboard Battery
Secondary Source Onboard Battery
6
J14
5
2 1
Backup Power Disabled
(For storage only)
6
2 1
Primary Source VMEbus +5V STBY
Secondary Source VMEbus +5V STBY
(Factory configuration)
J14
5
2 1 2 1
Primary Source VMEbus +5V STBY
Secondary Source Onboard Battery
Primary Source Onboard Battery
Secondary Source VMEbus +5V STBY
1-10 Computer Group Literature Center Web Site
Preparing the Board
Flash Write Protection (J16)
When the Flash write-enable jumper is installed (factory configuration),
Flash memory can be written to via the normal software routines. When the jumper is removed, Flash memory is not writable.
J16
2
1
Flash write-protected
J16
2
1
Flash write-enabled
(Factory configuration)
1
EPROM/Flash Configuration (J20)
The MVME162P2 can be ordered with 2MB of Flash memory and two
EPROM sockets ready for the installation of the EPROMs, which may be ordered separately. The EPROM locations are standard JEDEC 32-pin DIP sockets. The EPROM sockets accommodate four jumper-selectable densities (128 Kbit x 8; 256 Kbit x 8; 512 Kbit x 8 — the default configuration; 1 Mbit x 8) and also permit disabling of the Flash memory.
Header J20 provides eight jumper locations to configure the EPROM sockets.
http://www.motorola.com/computer/literature 1-11
1
Hardware Preparation and Installation
16
J20
15 16
J20
15
16
J20
15
2 1
CONFIGURATION 1: 128K x 8 EPROMs
J20
16 15
2
CONFIGURATION 2: 256K x 8 EPROMs
2 1
1
CONFIGURATION 3: 512K x 8 EPROMs
(FACTORY DEFAULT)
J20
16 15
2 1
CONFIGURATION 4: 1M x 8 EPROMs
2 1
CONFIGURATION 5: 1M x 8 EPROMs
ONBOARD FLASH DISABLED
1-12 Computer Group Literature Center Web Site
Preparing the Board
The next five tables show the address range for each EPROM socket in all five configurations. GPI3 (S4, switch segment 5) is a control bit in the
MC2 General-Purpose Inputs register in the Petra ASIC that determines whether reset code is fetched from Flash memory or from EPROMs. (For particulars on GPI3, refer to the Programmer’s Reference Guide.)
Table 1-3. EPROM/Flash Mapping — 128K x 8 EPROMs
GPI3
Set to OFF
Set to ON
1
0
Address Range Device Accessed
$FF800000 - $FF81FFFF EPROM A (XU1)
$FF820000 - $FF83FFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
$FFA00000 - $FFA1FFFF EPROM A (XU1)
$FFA20000 - $FFA3FFFF EPROM B (XU2)
Table 1-4. EPROM/Flash Mapping — 256K x 8 EPROMs
GPI3
Set to OFF
Set to ON
1
0
Address Range Device Accessed
$FF800000 - $FF83FFFF EPROM A (XU1)
$FF840000 - $FF87FFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
$FFA00000 - $FFA3FFFF EPROM A (XU1)
$FFA40000 - $FFA7FFFF EPROM B (XU2)
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1
Hardware Preparation and Installation
Table 1-5. EPROM/Flash Mapping — 512K x 8 EPROMs
GPI3
Set to OFF
Set to ON
1
0
Address Range Device Accessed
$FF800000 - $FF87FFFF EPROM A (XU1)
$FF880000 - $FF8FFFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
$FFA00000 - $FFA7FFFF EPROM A (XU1)
$FFA80000 - $FFAFFFFF EPROM B (XU2)
Table 1-6. EPROM/Flash Mapping — 1M x 8 EPROMs
GPI3
Set to OFF
Set to ON
1
0
Address Range Device Accessed
$FF800000 - $FF8FFFFF EPROM A (XU1)
$FF900000 - $FF9FFFFF EPROM B (XU2)
$FFA00000 - $FFBFFFFF Onboard Flash
$FF800000 - $FF9FFFFF Onboard Flash
$FFA00000 - $FFAFFFFF EPROM A (XU1)
$FFB00000 - $FFBFFFFF EPROM B (XU2)
Table 1-7. EPROM/Flash Mapping — 1M x 8 EPROMs, Onboard Flash
Disabled
GPI3
Set to OFF
Set to ON
1
0
Address Range Device Accessed
$FF800000 - $FF8FFFFF EPROM A (XU1)
$FF900000 - $FF9FFFFF EPROM B (XU2)
Not used Onboard Flash
Not used Onboard Flash
$FF800000 - $FF8FFFFF EPROM A (XU1)
$FF900000 - $FF9FFFFF EPROM B (XU2)
1-14 Computer Group Literature Center Web Site
Preparing the Board
MC2 DRAM Size (S3)
.
MVME162P2 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is configurable to emulate either of the following memory models:
❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the functionality of the “parity memory controller” found in MC2 ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs. Board firmware will initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the Petra ASIC is supporting MVME162P2 functionality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.
S3 comes into play in the MC2 memory controller model. S3 is a foursegment slide switch whose lower three segments establish the size of the parity DRAM (segment 4 is not used.) Refer to the illustration and table below for specifics.
S3
ON
4
OFF
1
16MB
(factory configuration)
MC2 DRAM SIZE
2734 0004
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Hardware Preparation and Installation
Table 1-8. MC2 DRAM Size Settings
S3
Segment 1
ON
OFF
OFF
OFF
OFF
S3
Segment 2
ON
ON
ON
OFF
OFF
S3
Segment 3
ON
ON
OFF
ON
OFF
MC2 DRAM
Size
1MB
4MB
8MB
Disabled
16MB
Notes As shown in the table, the Petra/MC2 interface supports parity
DRAM emulations up to 16MB. For sizes beyond 16MB, it is necesary to use the MCECC memory model.
For access to the MCECC registers, you must first disable the
MC2 interface by setting S3 to 001 (Off/Off/On). Further details on selecting the MCECC emulation can be found under
.
If you modify the switch settings, you will need to execute env;d
<CR> so that the firmware recognizes the new memory defaults.
General-Purpose Readable Switch (S4 Pin 5)
Switch S4 is similar in function to the general-purpose readable jumper headers found on earlier MVME162/172 series boards. S4 provides eight software-readable switch segments. These switches can be read as bits in a register (at address $FFF4202C) in the MC2 General-Purpose Inputs register in the Petra ASIC (refer to the Programmer’s Reference Guide for details). Bit GPI7 is associated with switch segment 1; bit GPI0 is associated with switch segment 8. The bit values are read as a 0 when the switch is on, and as a 1 when the switch is off. The MVME162P2 is shipped from the factory with S4 set to all 0s (all switches set to ON ), as diagrammed below.
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Preparing the Board
If the MVME162Bug firmware is installed, four bits are user-definable
(i.e., switch segments 1-4). If the MVME162Bug firmware is not installed, seven bits are user-definable (i.e., segments 1-4 and segments 6-8).
Note Switch segment 5 (GPI3) is reserved to select either the Flash memory map (switch set to ON ) or the EPROM memory map
(switch set to OFF ). GPI3 is not user-definable.
S4
OFF
GPI7
GPI6
GPI5
GPI4
GPI3
GPI2
GPI1
GPI0
Flash Selected
(factory configuration)
162 BUG Installed (default)
ON
1
5
8
USER-DEFINABLE
USER-DEFINABLE
USER-DEFINABLE
USER-DEFINABLE
ON=FLASH; OFF=EPROM
REFER TO DEBUG MANUAL
REFER TO DEBUG MANUAL
REFER TO DEBUG MANUAL
User Code Installed
USER-DEFINABLE
USER-DEFINABLE
USER-DEFINABLE
USER-DEFINABLE
ON=FLASH; OFF=EPROM
REFER TO DEBUG MANUAL
REFER TO DEBUG MANUAL
REFER TO DEBUG MANUAL
2735 0004
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1
Hardware Preparation and Installation
IP DMA Snoop Control (S5 Pins 1/2)
Segments 1 and 2 of switch S5 define the state of the snoop control bus
when an IP DMA controller is local bus master. As shown in Table 1-9 , S5
segment 1 controls Snoop Control signal 1 on the MC680x0 processor. S5 segment 2 controls Snoop Control signal 0. Setting a segment to ON produces a logical 0; setting it to OFF produces a logical 1.
S5
ON
4
OFF
Snoop inhibited
(factory configuration)
1
2736 0004 (1-3)
S5 varies in function according to the type of processor installed. For
MVME162P2 boards with an MC68040 processor, setting segments 1 and
2 of switch S5 to OFF or leaving both segments set to ON (the factory configuration) inhibits snooping. Enabling snooping requires one of two possible ON / OFF combinations, according to the operation desired.
MVME172P2 boards with an MC68060 processor have different snoop functionality.
The following table lists the snoop operations represented by the settings of S5 with both types of processor. For further details, refer to the
MC68040 or MC68060 microprocessor user’s manuals listed in the
Related Documentation appendix.
Table 1-9. Switch S5 Snoop Control Encoding
S5-1
(SC1)
On
On
Off
Off
S5-2
(SC0)
Requested Snoop Operation
MC68040 MC68060
On Snoop disabled Snoop enabled
Off Source dirty, sink byte/word/longword Snoop disabled
On Source dirty, invalidate line
Off Snoop disabled (Reserved)
Snoop enabled
Snoop disabled
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Preparing the Board
IP Reset Mode (S5 Pin 3)
Segment 3 of switch S5 defines the IP controller model (IP1 or IP2) to be emulated when the board comes up. With S5 segment 3 set to ON (the factory configuration), the board initializes in IP2 mode. With S5 segment
3 set to OFF , the board initializes in IP1 mode.
S5
ON
4
OFF
IP2 reset mode
(factory configuration )
1
2736 0004 (2-3)
In IP2 mode, IP resets occur only in response to a direct software write or to a power-up reset; the IP reset control bit is not self-clearing.
In IP1 mode, the IP reset control bit clears itself after after a 1msec interval. IP resets may occur in response to a software write, a power-up reset, or a local bus reset. For details, refer to the Programmer’s Reference
Guide listed under “Related Documentation” in Appendix E.
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Hardware Preparation and Installation
Flash Write Enable Mode (S5 Pin 4)
Segment 4 of switch S5 defines the Flash memory controller model (MC1 or MC2) to be emulated when enabling or disabling Flash memory accesses on the MVME162P2 board. With S5 segment 4 set to ON (the factory configuration), the board initializes in MC2 mode. With S5 segment 4 set to OFF , the board initializes in MC1 mode.
S5
ON
4
OFF
MC2 Flash write enable mode
(factory configuration )
1
2736 0004 (3-3)
In MC2 mode, writes to Flash memory are enabled or inhibited by a control bit at memory location $FFF42042. With the control bit set to 1 ,
Flash memory is write-enabled.
In MC1 mode, writes to Flash memory are enabled by a memory access to any location in the range $FFFCC000-$FFFCFFF. Writes to Flash memory are disabled by a memory access to any location in the range
$FFFC8000-$FFFCBFFF. For details, refer to the Programmer’s
Reference Guide listed under “Related Documentation” in Appendix E.
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Preparing the Board
MCECC DRAM Size (S6)
MVME1X2P2 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME162P2’s 16/32MB synchronous SDRAM is configurable to emulate either of the following memory models:
❏ 1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
❏ 4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
The two memory controllers modeled in the Petra ASIC duplicate the functionality of the “parity memory controller” found in MC2 ASICs as well as that of the “single-bit error correcting/double-bit error detecting” memory controller found in MCECC ASICs. Board firmware will initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will enable the parity (MC2) memory controller model. If the Petra ASIC is supporting MVME1X2P2 functionality, firmware will enable either the parity or the MCECC memory controller model, depending on the board configuration. Board configuration is a function of switch settings and resistor population options.
S6 comes into play in the MCECC memory controller model. S6 is a foursegment slide switch whose lower three segments establish the size of the
ECC DRAM (segment 4 is not used.) Refer to the illustration and table below for specifics.
S6
ON
4
OFF
16MB MCECC DRAM
(factory configuration )
1
2737 0004
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1
Hardware Preparation and Installation
Table 1-10. MCECC DRAM Size Settings
S6
Segment 1
ON
ON
ON
ON
OFF
S6
Segment 2
ON
ON
OFF
OFF
ON
S6
Segment 3
ON
OFF
ON
OFF
ON
MCECC
DRAM Size
4MB
8MB
16MB
32MB
64MB
Notes For the MCECC memory model to be enabled, the MC2 emulation must be disabled. You disable the MC2 memory model by setting the MC2 DRAM size select switch (S3) to
110 (Off/Off/On). Refer to MC2 DRAM Size (S3)
for further details.
The factory default setting for S6 is 16MB (On/Off/On). If you modify the switch settings, you will need to execute
env;d <CR> so that the firmware recognizes the new memory defaults.
Installation Instructions
This section covers:
❏ Installation of IndustryPacks (IPs) on the MVME162P2
❏ Installation of the MVME162P2 in a VME chassis
❏ System considerations relevant to the installation. Ensure that an
EPROM device is installed as needed. Before installing
IndustryPacks, ensure that the serial ports and all header jumpers and configuration switches are set as appropriate.
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Installation Instructions
IP Installation on the MVME162P2
The MVME162P2 accommodates up to two IndustryPack (IP) modules.
Install the IP modules on the MVME162P2 as follows:
1. Each IP module has two 50-pin connectors that plug into two corresponding 50-pin connectors on the MVME162P2: J5/J6, J7/J8.
See Figure 2-1 for the MVME162P2 connector locations.
– Orient the IP module(s) so that the tapered connector shells mate properly. Plug IP_a into connectors J5 and J6; plug IP_b into J7 and J8. If a double-sized IP is used, plug IP_ab into J5, J6, J7, and J8.
2. Two additional 50-pin connectors (J3 and J4) are provided behind the MVME162P2 front panel for external cabling connections to the
IP modules. There is a one-to-one correspondence between the signals on the cabling connectors and the signals on the associated
IP connectors (i.e., J4 has the same IP_a signals as J5; J3 has the same IP_b signals as J7.
– Connect user-supplied 50-pin cables to J3 and J4 as needed.
(Because of the varying requirements for each different kind of
IP, Motorola does not supply these cables.)
– Bring the IP cables out the narrow slots in the MVME162P2 front panel and attach them to the appropriate external equipment, depending on the nature of the particular IP(s).
MVME162P2 Installation
With EPROM and IP modules installed and headers or switches properly configured, proceed as follows to install the MVME162P2 in a VME chassis:
1. Turn all equipment power OFF and disconnect the power cable from the AC power source.
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Hardware Preparation and Installation
!
Caution
Inserting or removing modules while power is applied could result in damage to module components.
!
Warning
Dangerous voltages, capable of causing death, are present in this equipment. Use extreme caution when handling, testing, and adjusting.
2. Remove the chassis cover as instructed in the user’s manual for the equipment.
3. Remove the filler panel from the card slot where you are going to install the MVME162P2.
– If you intend to use the MVME162P2 as system controller, it must occupy the leftmost card slot (slot 1). The system controller must be in slot 1 to correctly initiate the bus-grant daisy-chain and to ensure proper operation of the IACK daisy-chain driver.
– If you do not intend to use the MVME162P2 as system controller, it can occupy any unused double-height card slot.
4. Slide the MVME162P2 into the selected card slot. Be sure the module is seated properly in the P1 and P2 connectors on the backplane. Do not damage or bend connector pins.
5. Secure the MVME162P2 in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize
RF emissions.
6. On the chassis backplane, remove the INTERRUPT ACKNOWLEDGE
(IACK) and BUS GRANT (BG) jumpers from the header for the card slot occupied by the MVME162P2.
Note Some VME backplanes (e.g., those used in Motorola "Modular
Chassis" systems) have an autojumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs.
7. Connect the appropriate cable(s) to the panel connectors for the serial ports, SCSI port, and LAN Ethernet port.
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Installation Instructions
– Note that some cables are not provided with the MVME162P2 and must be made or purchased by the user. (Motorola recommends shielded cable for all peripheral connections to minimize radiation.)
8. Connect the peripheral(s) to the cable(s).
9. Install any other required VMEmodules in the system.
10. Replace the chassis cover.
11. Connect the power cable to the AC power source and turn the equipment power ON.
System Considerations
The MVME162P2 draws power from VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper 8 address lines in extended addressing mode. The
MVME162P2 may not operate properly without its main board connected to VMEbus backplane connectors P1 and P2.
Whether the MVME162P2 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and 32 bits of data (A32/D32).
However, it handles A16 or A24 devices in the address ranges indicated in the VMEchip2 chapter of the Programmer’s Reference Guide. D8 and/or
D16 devices in the system must be handled by the MC680x0/MC68LC0x0 software. For specifics, refer to the memory maps in the Programmer’s
Reference Guide.
The MVME162P2 contains shared onboard DRAM whose base address is software-selectable. Both the onboard processor and offboard VMEbus devices see this local DRAM at base physical address $00000000, as programmed by the MVME162Bug firmware. This may be changed via software to any other base address. Refer to the Programmer’s Reference
Guide for more information.
If the MVME162P2 tries to access offboard resources in a nonexistent location and is not system controller, and if the system does not have a global bus timeout, the MVME162P2 waits forever for the VMEbus cycle to complete. This will cause the system to lock up. There is only one http://www.motorola.com/computer/literature 1-25
1
1
Hardware Preparation and Installation situation in which the system might lack this global bus timeout: when the
MVME162P2 is not the system controller and there is no global bus timeout elsewhere in the system.
Multiple MVME162P2s may be installed in a single VME chassis. In general, hardware multiprocessor features are supported.
Note If you are installing multiple MVME162P2s in an MVME945 chassis, do not install an MVME162P2 in slot 12. The height of the IP modules may cause clearance difficulties in that slot position.
Other MPUs on the VMEbus can interrupt, disable, communicate with, and determine the operational status of the processor(s). One register of the
GCSR (global control/status register) set in the VMEchip2 ASIC includes four bits that function as location monitors to allow one MVME162P2 processor to broadcast a signal to any other MVME162P2 processors. All eight registers of the GCSR set are accessible from any local processor as well as from the VMEbus.
The following circuits are protected by solid-state fuses that open during overload conditions and reset themselves once the overload is removed:
❏ IndustryPack +5V (R58)
❏ IndustryPack +12V (R75)
❏ IndustryPack –12V (R101)
❏ Remote reset connector +5V (R90)
❏ SCSI terminator +5V (R157)
❏ LAN AUI +12V (R245)
The FUSES LED illuminates to indicate that all fuses are functioning correctly. If a solid-state fuse opens, you will need to remove power for several minutes to let the fuse reset to a closed or shorted condition.
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Installation Instructions
Serial Connections
The MVME162P2 uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports:
❏ CTS, DCD, RTS, and DTR control signals
❏ TXD and RXD transmit/receive data signals
Because the serial clocks are omitted in the MVME162P2 implementation, serial communications are strictly asynchronous. The Z85230s are interfaced as DTE (data terminal equipment) with EIA-232-D signal levels. The serial ports are routed to four RJ-45 connectors on the front panel. The MVME162P2 hardware supports asynchronous serial baud rates of 110b/s to 38.4Kb/s.
For the pin assignments of the RJ-45 connectors on the front panel, refer to Chapter 5, Pin Assignments. For additional information on the
MVME162P2 serial communications interface, refer to the Z85230 Serial
Communications Controller Product Brief listed under Manufacturer’s
Documents in Appendix E, Related Documentation. For additional information on the EIA-232-D interface, refer to the EIA-232-D Standard.
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Hardware Preparation and Installation
1-28 Computer Group Literature Center Web Site
2
Startup and Operation
2
Introduction
This chapter provides information on powering up the MVME162P2 VME
Embedded Controller after its installation in a system, and describes the functionality of the switches, status indicators, and I/O ports.
For programming information, consult the MVME1X2P2 VME Embedded
Controller Programmer’s Reference Guide.
Front Panel Switches and Indicators
There are two switches (ABORT and RESET ) and four LEDs ( FAIL, RUN,
FUSES, SCON ) located on the MVME162P2 front panel.
Table 2-1. MVME162P2 Front Panel Controls
Control/Indicator
Abort Switch ( ABORT )
Reset Switch ( RESET )
Function
Sends an interrupt signal to the processor. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME162P2 Flash memory.
The interrupter connected to the Abort switch is an edge-sensitive circuit, filtered to remove switch bounce.
Resets all onboard devices. Also drives a SYSRESET
∗
signal if the
MVME162P2 is system controller. SYSRESET
∗
signals may be generated by the Reset switch, a power-up reset, a watchdog timeout, or by a control bit in the Local Control/Status Register
(LCSR) in the VMEchip2 ASIC. For further details, refer to
Chapter 4, Functional Description.
2-1
2
Startup and Operation
Table 2-1. MVME162P2 Front Panel Controls
Control/Indicator
FAIL LED (DS1, red)
Function
Board failure. Lights if a fault occurs on the MVME162P2 board.
RUN LED (DS2, green) CPU activity. Indicates that one of the local bus masters is executing a local bus cycle.
FUSES LED (DS3, green) Fuse OK. Indicates that +5Vdc, +12Vdc, and –12Vdc power is available to the LAN and SCSI interfaces and IP connectors.
SCON LED (DS4, green) System controller. Lights when the VMEchip2 ASIC is functioning as VMEbus system controller.
Initial Conditions
After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system. Applying power to the system (as well as resetting it) triggers an initialization of the
MVME162P2’s MPU, hardware, and firmware along with the rest of the system.
The Flash-resident firmware initializes the devices on the MVME162P2 board in preparation for booting the operating system. The firmware is shipped from the factory with a set of defaults appropriate to the board. In most cases there is no need to modify the firmware configuration before you boot the operating system. For specifics in this regard, refer to Chapter
3 and to the user documentation for the MVME162Bug firmware.
2-2 Computer Group Literature Center Web Site
Applying Power
Applying Power
When you power up (or when you reset) the system, the firmware executes some self-checks and proceeds to the hardware initialization. The system startup flows in a predetermined sequence, following the hierarchy inherent in the processor and the MVME162P2 hardware. The figure below charts the flow of the basic initialization sequence that takes place during system startup.
2
Power-up/reset initialization STARTUP
INITIALIZATION
POST
Initialization of devices on the MVME162P2 module/system
Power-On Self-Test diagnostics
BOOTING Firmware-configured boot mechanism, if so configured. Default is no boot.
MONITOR Interactive, command-driven on-line debugger, when terminal connected.
Figure 2-1. MVME162P2/Firmware System Startup http://www.motorola.com/computer/literature 2-3
2
Startup and Operation
Pre-Startup Checklist
Before you power up the MVME162P2 system, be sure that the following conditions exist:
1. Jumpers and/or configuration switches on the MVME162P2 VME
Embedded Controller and associated equipment are set as required for your particular application.
2. The MVME162P2 board is installed and cabled up as appropriate for your particular chassis or system, as outlined in Chapter 1.
3. The terminal that you plan to use as the system console is connected to the console port (serial port 1) on the MVME162P2 module.
4. The terminal is set up as follows:
– Eight bits per character
– One stop bit per character
– Parity disabled (no parity protection)
– Baud rate 9600 baud (the default baud rate of many serial ports at power-up)
5. Any other device that you wish to use, such as a host computer system and/or peripheral equipment, is cabled to the appropriate connectors.
After you complete the checks listed above, you are ready to power up the system.
2-4 Computer Group Literature Center Web Site
Bringing up the Board
Bringing up the Board
The MVME162P2 comes with MVME162Bug firmware installed. For the firmware to operate properly with the board, you must follow the steps below.
!
Caution
Inserting or removing boards with power applied may damage board components.
Turn all equipment power OFF. Refer to
MVME162P2 Configuration on page 1-5 and verify that jumpers and switches are configured as necessary
for your particular application.
1. Configuration switch S4 on the MVME162P2 contains eight segments, which all affect the operation of the firmware. They are read as a register (at location $FFF4202C) in the Petra MC2 sector.
(The MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide has additional information on the Petra MC2 emulation.) The bit values are read as a 0 when the corresponding switch segment is set to ON , or as a 1 when that segment is set to
OFF .
The default configuration for S4 has S4 set to all 0s (all switch segments set to ON ). The 162Bug firmware reserves/defines the four
lower order bits (GPI0 to GPI3, switch segments 5-8). Table 2-2
describes the bit assignments on S4.
2. Configure header J1 as appropriate for the desired system controller functionality (always system controller, never system controller, or self-regulating) on the MVME162P2.
3. Header J11 enables or disables the IP bus strobe function on the
MVME162P2. The factory configuration puts no jumper on J11, disabling the Strobe
∗
signal to the Petra/IP2 chip. Verify that this setting is appropriate for your application.
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Startup and Operation
2
Table 2-2. Software-Readable Switches
Bit No.
S4 Segment
GPI0 8
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
7
6
5
4
3
2
1
Function
When set to 1 (high), instructs the debugger to use local static RAM for its work page (variables, stack, vector tables, etc.).
When set to 1 (high), instructs the debugger to use the default setup/operation parameters in ROM instead of the user setup/operation parameters in NVRAM. The effect is the same as pressing the RESET and ABORT switches simultaneously.
This feature can be helpful in the event the user setup is corrupted or does not meet a sanity check. Refer to the ENV command description for the Flash/ROM defaults.
Reserved for future use.
When set to 0 (low), informs the debugger that it is executing out of
Flash memory. When set to 1 (high), it informs the debugger that it is executing out of the PROM.
Open to your application.
Open to your application.
Open to your application.
Open to your application.
4. Header J12 enables/disables the SCSI terminators provided on the
MVME162P2. If the board is to be located at either end of an SCSI bus, the SCSI bus terminators must be enabled. The factory configuration has a jumper installed on J12, enabling SCSI termination. Verify that this setting is appropriate for your application.
5. Header J13 configures the IP bus clock for either 8MHz or the processor bus clock speed (25MHz for the MC68040 and
MC68LC040). The factory configuration has a jumper installed on
J13 pins 1-2, denoting an 8MHz clock. Verify that this setting is appropriate for your application.
6. The jumpers on header J14 establish the SRAM backup power source on the MVME162P2. The factory configuration uses
VMEbus +5V standby voltage as the primary and secondary power
2-6 Computer Group Literature Center Web Site
Bringing up the Board source (the onboard battery is disconnected). Verify that this configuration is appropriate for your application.
7. Header J16 defines the state of Flash memory write protection. The factory configuration has the jumper installed, permitting writes to
Flash. Verify that this setting is appropriate for your application.
8. The EPROM/Flash configuration header, J20, should be jumpered between pins 5-6, 9-11, and 8-10. This sets it up for a 512Kbit x 8
EPROM density, the factory default.
9. Verify that the settings of configuration switches S3 (MC2 DRAM size), S5 (IP DMA snoop control, IP Reset mode, and Flash Write
Enable mode), and S6 (MCECC DRAM size) are appropriate for your memory controller emulation.
10. Refer to the setup procedure for your particular chassis or system for details concerning the installation of the MVME162P2.
11. Connect the terminal to be used as the 162Bug system console to the default EIA-232-D port at Serial Port 1 on the front panel of the
MVME162P2. Set the terminal up as follows:
– Eight bits per character
– One stop bit per character
– Parity disabled (no parity)
– Baud rate 9600 baud (the power-up default)
After power-up, you can reconfigure the baud rate of the debug port by using the 162Bug Port Format (PF) command.
Note Whatever the baud rate, some form of hardware handshaking
— either XON/XOFF or via the RTS/CST line — is desirable if the system supports it. If you get garbled messages and missing characters, you should check the terminal to make sure that handshaking is enabled.
12. If you have equipment (such as a host computer system and/or a serial printer) to connect to the other EIA-232-D port connectors, connect the appropriate cables and configure the port(s) as detailed
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Startup and Operation in Step
11 above. After power-up, you can reconfigure the port(s)
by programming the MVME162P2 Z85230 Serial Communications
Controllers (SCCs) or by using the 162Bug PF command.
13. Power up the system. 162Bug executes some self-checks and displays the debugger prompt
162-Bug>
if the firmware is in Board mode.
However, if the ENV command has placed 162Bug in System mode, the system performs a self-test and tries to autoboot. Refer to the ENV and MENU commands ( Table 3-2 ).
If the confidence test fails, the test is aborted when the first fault is encountered. If possible, an appropriate message is displayed, and control then returns to the menu.
14. Before using the MVME162P2 after the initial installation, set the date and time using the following command line structure:
162-Bug>
SET [mmddyyhhmm]|[<+/-CAL>;C]
For example, the following command line starts the real-time clock and sets the date and time to 10:37 a.m., November 7, 2000:
162-Bug>
SET 1107001037
The board’s self-tests and operating systems require that the realtime clock be running.
Note
If you wish to execute the debugger out of Flash and Flash does not contain 162Bug, you may copy the EPROM version of 162Bug to Flash memory. To copy the EPROM version of
162Bug to Flash memory, first verify that a jumper is in place on J16 to enable Flash writes, set switch S4 segment 5 to ON , and make sure that 162Bug is in Bug mode. Then copy the
EPROM contents to Flash memory with the PFLASH command as follows:
162-Bug> PFLASH FF800000:80000 FFA00000
2-8 Computer Group Literature Center Web Site
Bringing up the Board
Then remove the jumper from J16 (if you wish to disable subsequent Flash writes) and slide switch S4 segment 5 back to
OFF . (162Bug always executes from memory location FF800000; the setting of S4 determines whether that location is in EPROM or Flash.)
Autoboot
Autoboot is a software routine that is contained in the 162Bug
Flash/EPROM to provide an independent mechanism for booting an operating system. This autoboot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing a boot media is found or the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. Controllers, devices, and their LUNs are listed in Appendix D.
At power-up, Autoboot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:
Autoboot in progress... To abort hit <BREAK>
A delay follows this message so that you can abort the Autoboot process if you wish. Then the actual I/O begins: the program designated within the volume ID of the media specified is loaded into RAM and control passes to it. If you want to gain control without Autoboot during this time, however, you can press the <BREAK> key or the software ABORT or
RESET switches.
The Autoboot process is controlled by parameters contained in the ENV command. These parameters allow the selection of specific boot devices and files, and allow programming of the Boot delay. Refer to the ENV command description in Chapter 3 for more details.
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Startup and Operation
!
Caution
Although you can use streaming tape to autoboot, the same power supply must be connected to the tape drive, the controller, and the MVME162P2. At power-up, the tape controller will position the streaming tape to the load point where the volume ID can correctly be read and used.
However, if the MVME162P2 loses power but the controller does not, and the tape happens to be at load point, the necessary command sequences (attach and rewind) cannot be given to the controller and the autoboot will not succeed.
ROMboot
As shipped from the factory, 162Bug occupies an EPROM installed in
XU2. This leaves the remaining EPROM socket (XU1) and the Flash memory available for your use.
Note You may wish to contact your Motorola sales office for assistance in using these resources.
The ROMboot function is configured/enabled via the ENV command
(refer to Chapter 3) and is executed at power-up (optionally also at reset).
You can also execute the ROMboot function via the RB command, assuming there is valid code in the memory devices (or optionally elsewhere on the board or VMEbus) to support it. If ROMboot code is installed, a user-written routine is given control (if the routine meets the format requirements).
One use of ROMboot might be resetting the SYSFAIL
∗
line on an unintelligent controller module. The NORB command disables the function.
For a user’s ROMboot module to gain control through the ROMboot linkage, four conditions must exist:
❏ Power has just been applied (but the ENV command can change this to also respond to any reset).
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Bringing up the Board
❏ Your routine is located within the MVME162P2 Flash/PROM memory map (but the ENV command can change this to any other portion of the onboard memory, or even offboard VMEbus memory).
❏ The ASCII string "BOOT" is found in the specified memory range.
❏ Your routine passes a checksum test, which ensures that this routine was really intended to receive control at powerup.
For complete details on using the ROMboot function, refer to the
Debugging Package for Motorola 68K CISC CPUs User’s Manual.
Network Boot
Network Auto Boot is a software routine in the 162Bug Flash/EPROM which provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device. The Network Auto
Boot routine automatically scans for controllers and devices in a specified sequence until a valid bootable device containing boot media is found or until the list is exhausted. If a valid bootable device is found, a boot from that device is started. The controller scanning sequence goes from the lowest controller Logical Unit Number (LUN) detected to the highest LUN detected. (Refer to Appendix C for default LUNs.)
At power-up, Network Boot is enabled and (provided that the drive and controller numbers encountered are valid) the following message is displayed upon the system console:
Network Boot in progress... To abort hit <BREAK>
After this message, there is a delay to let you abort the Auto Boot process if you wish. Then the actual I/O is begun: the program designated within the volume ID of the media specified is loaded into RAM and control passes to it. If you want to gain control without Network Boot during this time, however, you can press the <BREAK> key or use the software
ABORT or RESET switches.
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Startup and Operation
Network Auto Boot is controlled by parameters contained in the NIOT and ENV commands. These parameters allow the selection of specific boot devices, systems, and files, and allow programming of the Boot delay.
Refer to the ENV command description in Chapter 3 for more details.
Restarting the System
You can initialize the system to a known state in three different ways:
Reset, Abort, and Break. Each method has characteristics which make it more suitable than the others in certain situations.
A special debugger function is accessible during resets. This feature instructs the debugger to use the default setup/operation parameters in
ROM instead of your own setup/operation parameters in NVRAM. To activate this function, you press the RESET and ABORT switches at the same time. This feature can be helpful in the event that your setup/operation parameters are corrupted or do not meet a sanity check.
Refer to the ENV command description in Chapter 3 for the ROM defaults.
Reset
Powering up the MVME162P2 initiates a system reset. You can also initiate a reset by pressing and quickly releasing the RESET switch on the
MVME162P2 front panel, or reset the board in software.
For details on resetting the MVME162P2 board through software, refer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.
Both “cold” and “warm” reset modes are available. By default, 162Bug is in “cold” mode. During cold resets, a total system initialization takes place, as if the MVME162P2 had just been powered up. All static variables
(including disk device and controller parameters) are restored to their default states. The breakpoint table and offset registers are cleared. The target registers are invalidated. Input and output character queues are cleared. Onboard devices (timer, serial ports, etc.) are reset, and the two serial ports are reconfigured to their default state.
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Restarting the System
During warm resets, the 162Bug variables and tables are preserved, as well as the target state registers and breakpoints.
Note that when the MVME162P2 comes up in a cold reset, 162Bug runs in Board mode. Using the Environment (ENV) or MENU commands can make 162Bug run in System mode. Refer to Chapter 3 for specifics.
You will need to reset your system if the processor ever halts, or if the
162Bug environment is ever lost (vector table is destroyed, stack corrupted, etc.).
2
Abort
Aborts are invoked by pressing and releasing the ABORT switch on the
MVME162P2 front panel. When you invoke an abort while executing a user program (running target code), a snapshot of the processor state is stored in the target registers. This characteristic makes aborts most appropriate for terminating user programs that are being debugged.
If a program gets caught in a loop, for instance, aborts should be used to regain control. The target PC, register contents, etc., help to pinpoint the malfunction.
Pressing and releasing the ABORT switch generates a local board condition which may interrupt the processor if enabled. The target registers, reflecting the machine state at the time the ABORT switch was pressed, are displayed on the screen. Any breakpoints installed in your code are removed and the breakpoint table remains intact. Control returns to the debugger.
Break
Pressing and releasing the <BREAK> key on the terminal keyboard generates a "power break”. Breaks do not produce interrupts. The only time that breaks are recognized is while characters are being sent or received by the console port. A break removes any breakpoints in your code and keeps the breakpoint table intact. If the function was entered using SYSCALL, Break also takes a snapshot of the machine state. This machine state is then accessible to you for diagnostic purposes. http://www.motorola.com/computer/literature 2-13
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Startup and Operation
In many cases, you may wish to terminate a debugger command before its completion (for example, during the display of a large block of memory).
Break allows you to terminate the command.
Diagnostic Facilities
The 162Bug package includes a set of hardware diagnostics for testing and troubleshooting the MVME162P2. To use the diagnostics, switch directories to the diagnostic directory.
If you are in the debugger directory, you can switch to the diagnostic directory with the debugger command Switch Directories (SD). The diagnostic prompt 162-Diag> appears. Refer to the Debugging Package
for Motorola 68K CISC CPUs User’s Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them.
Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode. The documentation for such diagnostics includes restart information.
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162Bug Firmware
3
Introduction
The 162Bug firmware is the layer of software just above the hardware. The firmware supplies the appropriate initialization for devices on the
MVME162P2 board upon power-up or reset.
This chapter describes the basics of 162Bug and its architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on using the debugger and special commands. A list of
162Bug commands appears at the end of the chapter.
For complete user information about 162Bug, refer to the Debugging
Package for Motorola 68K CISC CPUs User’s Manual and to the
MVME162Bug Diagnostics User’s Manual, listed under Related
Documentation.
162Bug Overview
The firmware for the M68000-based (68K) series of board and system level products has a common genealogy, deriving from the Bug firmware currently used on all Motorola M68000-based CPUs. The M68000 firmware version implemented on the MVME162P2 MC68040- or
MC68LC040-based embedded controller is known as MVME162Bug, or
162Bug. It includes diagnostics for testing and configuring IndustryPack modules.
162Bug is a powerful evaluation and debugging tool for systems built around MVME162P2 CISC-based microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation. The 162Bug firmware provides a high degree of functionality, user friendliness, portability, and ease of maintenance.
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162Bug Firmware
162Bug includes:
❏ Commands for display and modification of memory
❏ Breakpoint and tracing capabilities
❏ A powerful assembler/disassembler useful for patching programs
❏ A “self-test at power-up” feature which verifies the integrity of the system
In addition, the TRAP #15 system calls make various 162Bug routines that handle I/O, data conversion, and string functions available to user programs.
162Bug consists of three parts:
❏ A command-driven user-interactive software debugger, described in this chapter. It is referred to here as “the debugger” or “162Bug”.
❏ A command-driven diagnostic package for the MVME162P2 hardware, referred to here as “the diagnostics”.
❏ A user interface or debug/diagnostics monitor that accepts commands from the system console terminal.
When using 162Bug, you operate out of either the debugger directory or the diagnostic directory.
❏ If you are in the debugger directory, the debugger prompt 162-Bug> is displayed and you have all of the debugger commands at your disposal.
❏ If you are in the diagnostic directory, the diagnostic prompt
162-
Diag> is displayed and you have all of the diagnostic commands at your disposal as well as all of the debugger commands.
Because 162Bug is command-driven, it performs its various operations in response to user commands entered at the keyboard. When you enter a command, 162Bug executes the command and the prompt reappears.
However, if you enter a command that causes execution of user target code
(for example, GO), then control may or may not return to 162Bug, depending on the outcome of the user program.
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162Bug Implementation
If you have used one or more of Motorola’s other debugging packages, you will find the CISC 162Bug very similar. Some effort has also been made to improve the consistency of interactive commands. For example, delimiters between commands and arguments may be commas or spaces interchangeably.
162Bug Implementation
Physically, 162Bug is contained in a single 27C040 DIP EPROM installed in socket XU2, providing 512KB (128K longwords) of storage.
Optionally, the 162Bug firmware can be loaded and executed in a
28F016SA Flash memory chip. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the memory devices) is tested for an expected zero. Users are cautioned against modification of the memory devices unless precautions for re-checksumming are taken.
Note MVME162P2 boards ordered without the VMEbus interface are shipped with Flash memory blank (the factory uses the
VMEbus to program the Flash memory with debugger code).
To use the 162Bug package, be sure that switch S4 segment
5 is configured to select the EPROM memory map.
If you subsequently wish to run the debugger from Flash memory, you must first initialize Flash memory with the
PFLASH command, then reconfigure S4. Refer to Step 14
(Note) under
Bringing up the Board on page 2-5 for further
details.
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162Bug Firmware
Memory Requirements
The program portion of 162Bug is approximately 512KB of code, consisting of download, debugger, and diagnostic packages and contained entirely in Flash memory or EPROM.
The 162Bug firmware executes from address $FF800000 whether in Flash or EPROM. If you set switch S4 segment 5 to ON , the address spaces of the
Flash and EPROM are swapped. For MVME162P-242 series boards
(MVME162P2), the factory ship configuration except in the no-VMEbus case has switch S4 segment 5 set to OFF (162Bug operating out of Flash).
The 162Bug initial stack completely changes 8KB of SRAM memory at addresses $FFE0C000 through $FFE0DFFF, at power-up or reset.
.
Table 3-1. Memory Offsets with 162Bug
Type of Memory Present
4/8/16/32MB synchronous DRAM (SDRAM). Appears as parity memory at 1/8/16MB, ECC at 32MB.
Default DRAM
Base Address
$00000000
Default SRAM
Base Address
$FFE00000
(onboard SRAM)
The synchronous DRAM can be modeled as ECC or parity type, as indicated above.
The 162Bug requires 2KB of NVRAM for storage of board configuration, communication, and booting parameters. This storage area begins at
$FFFC16F8 and ends at $FFFC1EF7.
162Bug requires a minimum of 64KB of contiguous read/write memory to operate. The ENV command controls where this block of memory is located. Regardless of where the onboard RAM is located, the first 64KB is used for 162Bug stack and static variable space and the rest is reserved as user space. Whenever the MVME162P2 is reset, the target PC is initialized to the address corresponding to the beginning of the user space, and the target stack pointers are initialized to addresses within the user space, with the target Interrupt Stack Pointer (ISP) set to the top of the user space.
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Using 162Bug
Using 162Bug
162Bug is command-driven; it performs its various operations in response to commands that you enter at the keyboard. When the
162-Bug> prompt appears on the terminal screen, the debugger is ready to accept debugger commands. When the
162-Diag> prompt appears on the screen, the debugger is ready to accept diagnostics commands.
To switch from one mode to the other, enter SD (Switch Directories). To examine the commands in the directory that you are currently in, use the
Help command (HE).
What you key in is stored in an internal buffer. Execution begins only after the carriage return is entered. This allows you to correct entry errors, if necessary, with the control characters described in the Debugging Package
for Motorola 68K CISC CPUs User’s Manual, Chapter 1.
After the debugger executes the command you have entered, the prompt reappears. However, if the command causes execution of user target code
(for example GO), then control may or may not return to the debugger, depending on what the user program does.
For example, if a breakpoint has been specified, then control returns to the debugger when the breakpoint is encountered during execution of the user program. Alternatively, the user program could return to the debugger by means of the System Call Handler routine RETURN (described in the
Debugging Package for Motorola 68K CISC CPUs User’s Manual,
Chapter 5, listed in Appendix E, Related Documentation).
A debugger command is made up of the following parts:
❏ The command name, either uppercase or lowercase (e.g., MD or
md).
❏ A port number (if the command is set up to work with more than one port).
❏ Any required arguments, as specified by the command.
❏ At least one space before the first argument. Precede all other arguments with either a space or a comma.
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162Bug Firmware
❏ One or more options. Precede an option or a string of options with a semicolon (;). If no option is entered, the command’s default option conditions are used.
Debugger Commands
The 162Bug debugger commands are summarized in the following table.
The commands are described in detail in the Debugging Package for
Motorola 68K CISC CPUs User’s Manual.
Table 3-2. Debugger Commands
CNFG
CS
DC
DMA
DS
DU
ECHO
ENV
BM
BO
BR
NOBR
BS
BV
CM
NOCM
BC
BF
BH
BI
Command
AB
NOAB
AS
Description
Automatic Bootstrap Operating System
No Autoboot
One Line Assembler
Block of Memory Compare
Block of Memory Fill
Bootstrap Operating System and Halt
Block of Memory Initialize
Block of Memory Move
Bootstrap Operating System
Breakpoint Insert
Breakpoint Delete
Block of Memory Search
Block of Memory Verify
Concurrent Mode
No Concurrent Mode
Configure Board Information Block
Checksum
Data Conversion
DMA Block of Memory Move
One Line Disassembler
Dump S-records
Echo String
Set Environment to Bug/Operating System
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Debugger Commands
Table 3-2. Debugger Commands (Continued)
MS
MW
NAB
NBH
NBO
NIOC
NIOP
NIOT
MAL
NOMAL
MAW
MAR
MD
MENU
MM
MMD
NPING
OF
PA
Command
GD
GN
GO
GT
HE
IOC
IOI
IOP
IOT
IRQM
LO
MA
NOMA
MAE
Description
Go Direct (Ignore Breakpoints)
Go to Next Instruction
Go Execute User Program
Go to Temporary Breakpoint
Help
I/O Control for Disk
I/O Inquiry
I/O Physical (Direct Disk Access)
I/O "Teach" for Configuring Disk Controller
Interrupt Request Mask
Load S-records from Host
Macro Define/Display
Macro Delete
Macro Edit
Enable Macro Expansion Listing
Disable Macro Expansion Listing
Save Macros
Load Macros
Memory Display
Menu
Memory Modify
Memory Map Diagnostic
Memory Set
Memory Write
Automatic Network Boot Operating System
Network Boot Operating System and Halt
Network Boot Operating System
Network I/O Control
Network I/O Physical
Network I/O Teach
Network Ping
Offset Registers Display/Modify
Printer Attach
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162Bug Firmware
Table 3-2. Debugger Commands (Continued)
SET
SYM
NOSYM
SYMS
T
TA
TC
TIME
TM
TT
VE
VER
WL
Command
NOPA
PF
NOPF
PFLASH
PS
RB
NORB
RD
REMOTE
RESET
RL
RM
RS
SD
Description
Printer Detach
Port Format
Port Detach
Program FLASH Memory
Put RTC Into Power Save Mode for Storage
ROMboot Enable
ROMboot Disable
Register Display
Connect the Remote Modem to CSO
Cold/Warm Reset
Read Loop
Register Modify
Register Set
Switch Directories
Set Time and Date
Symbol Table Attach
Symbol Table Detach
Symbol Table Display/Search
Trace
Terminal Attach
Trace on Change of Control Flow
Display Time and Date
Transparent Mode
Trace to Temporary Breakpoint
Verify S-Records Against Memory
Display Revision/Version
Write Loop
Modifying the Environment
You can use the factory-installed debug monitor, 162Bug, to modify certain parameters contained in the MVME162P2’s Non-Volatile RAM
(NVRAM), also known as Battery Backed-Up RAM (BBRAM).
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Modifying the Environment
❏ The Board Information Block in NVRAM contains various entries that define operating parameters of the board hardware. Use the
162Bug command CNFG to change those parameters.
❏ Use the 162Bug command ENV to change configurable 162Bug parameters in NVRAM.
The CNFG and ENV commands are both described in the Debugging
Package for Motorola 68K CISC CPUs User’s Manual, listed in Appendix
E, Related Documentation. Refer to that manual for general information about their use and capabilities.
The following paragraphs present supplementary information on CNFG and ENV that is specific to the 162Bug firmware, along with the parameters that you can modify with the ENV command.
CNFG - Configure Board Information Block
Use this command to display and configure the Board Information Block which resides within the NVRAM. The board information block contains various elements that correspond to specific operational parameters of the
MVME162P2 board. (Note that although no memory mezzanine is present on MVME1X2P2 series boards, the on-board memory is modeled as such for backward compatibility.)
The board structure for the MVME162P2 is as follows:
162-Bug> cnfg
Board (PWA) Serial Number = " "
Board Identifier = " "
Artwork (PWA) Identifier = " "
MPU Clock Speed = " "
Ethernet Address = 0001AF200000
Local SCSI Identifier = " "
Parity Memory Mezzanine Artwork (PWA) Identifier = " "
Parity Memory Mezzanine (PWA) Serial Number = " "
Static Memory Mezzanine Artwork (PWA) Identifier = " "
Static Memory Mezzanine (PWA) Serial Number = " "
ECC Memory Mezzanine #1 Artwork (PWA) Identifier = " "
ECC Memory Mezzanine #1 (PWA) Serial Number = " "
ECC Memory Mezzanine #2 Artwork (PWA) Identifier = " " http://www.motorola.com/computer/literature 3-9
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162Bug Firmware
ECC Memory Mezzanine #2 (PWA) Serial Number = " "
Serial Port 2 Personality Artwork (PWA) Identifier = " "
Serial Port 2 Personality Module (PWA) Serial Number = " "
IndustryPack A Board Identifier = " "
IndustryPack A (PWA) Serial Number = " "
IndustryPack A Artwork (PWA) Identifier = " "
IndustryPack B Board Identifier = " "
IndustryPack B (PWA) Serial Number = " "
IndustryPack B Artwork (PWA) Identifier = " "
IndustryPack C Board Identifier = " "
IndustryPack C (PWA) Serial Number = " "
IndustryPack C Artwork (PWA) Identifier = " "
IndustryPack D Board Identifier = " "
IndustryPack D (PWA) Serial Number = " "
IndustryPack D Artwork (PWA) Identifier = " "
162-Bug>
The parameters that are quoted are left-justified character (ASCII) strings padded with space characters, and the quotes (") are displayed to indicate the size of the string. Parameters that are not quoted are considered data strings, and data strings are right-justified. The data strings are padded with zeros if the length is not met.
The Board Information Block is factory-configured before shipment.
There is no need to modify block parameters unless the NVRAM is corrupted.
Refer to the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for the actual location and other information about the
Board Information Block. Refer to the Debugging Package for Motorola
68K CISC CPUs User's Manual for a CNFG description and examples.
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ENV - Set Environment
ENV - Set Environment
Use the ENV command to view and/or configure interactively all 162Bug operational parameters that are kept in Non-Volatile RAM (NVRAM).
Refer to the Debugging Package for Motorola 68K CISC CPUs User’s
Manual for a description of the use of ENV. Additional information on registers in the MVME162P2 that affect these parameters appears in your
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.
Listed and described below are the parameters that you can configure using ENV. The default values shown are those that were in effect when this document was published.
Note In the event of difficulty with the MVME162P2, you may wish to use env;d <CR> to restore the factory defaults as a troubleshooting aid (see Appendix B).
Configuring the 162Bug Parameters
The parameters that can be configured using ENV are:
Table 3-3. ENV Command Parameters
ENV Parameter and Options
Bug or System environment [B/S]
Field Service Menu Enable [Y/N]
Remote Start Method Switch
[G/M/B/N]
Probe System for Supported I/O
Controllers [Y/N]
Default
B
N
B
Y
Meaning of Default
Bug mode
Do not display field service menu.
Use both methods [Global Control and Status
Register (GCSR) in the VMEchip2, and
Multiprocessor Control Register (MPCR) in shared RAM] to pass and execute cross-loaded programs.
Accesses will be made to the appropriate system buses (e.g., VMEbus, local MPU bus) to determine presence of supported controllers.
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162Bug Firmware
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
Negate VMEbus SYSFAIL
∗
Always [Y/N]
Default
N
N
Meaning of Default
Negate VMEbus SYSFAIL
∗
after successful completion or entrance into the bug command monitor.
No local SCSI bus reset on debugger startup. Local SCSI Bus Reset on
Debugger Startup [Y/N]
Local SCSI Bus Negotiations
Type [A/S/N]
Industry Pack Reset on Debugger
Startup [Y/N]
Ignore CFGA Block on a Hard
Disk Boot [Y/N]
Auto Boot Enable [Y/N]
Auto Boot at power-up only [Y/N]
Auto Boot Controller LUN
A
Y
Y
N
Y
00
Asynchronous negotiations.
IP modules are reset on debugger startup.
Auto Boot Device LUN
Auto Boot Abort Delay
Auto Boot Default String
[Y(NULL String)/(String)]
ROM Boot Enable [Y/N]
ROM Boot at power-up only
[Y/N]
ROM Boot Enable search of
VMEbus [Y/N]
ROM Boot Abort Delay
00
15
N
Y
N
00
Configuration Area (CFGA) Block contents are disregarded at boot (hard disk only).
Auto Boot function is disabled.
Auto Boot is attempted at power-up reset only.
Specifies LUN of disk/tape controller module currently supported by the Bug. Default is $0.
Specifies LUN of disk/tape device currently supported by the Bug. Default is $0.
The time in seconds that the Auto Boot sequence will delay before starting the boot.
The delay gives you the option of stopping the boot by use of the Break key. The time span is
0-255 seconds.
You may specify a string (filename) to pass on to the code being booted. Maximum length is
16 characters. Default is the null string.
ROMboot function is disabled.
ROMboot is attempted at power-up only.
VMEbus address space will not be accessed by
ROMboot.
The time in seconds that the ROMboot sequence will delay before starting the boot.
The delay gives you the option of stopping the boot by use of the Break key. The time span is
0-255 seconds.
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ENV - Set Environment
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
ROM Boot Direct Starting
Address
Default Meaning of Default
FF800000 First location tested when the Bug searches for a ROMboot module.
ROM Boot Direct Ending Address FFDFFFFC Last location tested when the Bug searches for a ROMboot module.
Network Auto Boot Enable [Y/N] N Network Auto Boot function is disabled.
Y Network Auto Boot at power-up only [Y/N]
Network Auto Boot Controller
LUN
00
Network Auto Boot is attempted at power-up reset only.
Specifies LUN of a disk/tape controller module currently supported by the Bug. Default is $0.
Network Auto Boot Device LUN
Network Auto Boot Abort Delay
00
5
Specifies LUN of a disk/tape device currently supported by the Bug. Default is $0.
The time in seconds that the Network Boot sequence will delay before starting the boot.
The delay gives you the option of stopping the boot by use of the Break key. The time span is
0-255 seconds.
Network Autoboot Configuration
Parameters Pointer (NVRAM)
00000000 The address where the network interface configuration parameters are to be saved in
NVRAM; these are the parameters necessary to perform an unattended network boot.
Memory Search Starting Address 00000000 Where the Bug begins to search for a work page (a 64KB block of memory) to use for vector table, stack, and variables. This must be a multiple of the debugger work page, modulo
$10000 (64KB). In a multi-controller environment, each MVME162P2 board could be set to start its work page at a unique address to allow multiple debuggers to operate simultaneously.
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162Bug Firmware
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
Memory Search Ending Address
Memory Search Increment Size
Memory Search Delay Enable
[Y/N]
Memory Search Delay Address
Memory Size Enable [Y/N]
Memory Size Starting Address
Default Meaning of Default
00100000 Top limit of the Bug’s search for a work page.
If no 64KB contiguous block of memory is found in the range specified by Memory
Search Starting Address and Memory Search
Ending Address parameters, the bug will place its work page in the onboard static RAM on the
MVME162P2. Default Memory Search Ending
Address is the calculated size of local memory.
00010000 Multi-CPU feature used to offset the location of the Bug work page. This must be a multiple of the debugger work page, modulo $10000
(64KB). Typically, Memory Search Increment
Size is the product of CPU number and size of the Bug work page. Example: first CPU $0 (0 x
$10000), second CPU $10000 (1 x $10000), etc.
N No delay before the Bug begins its search for a work page.
FFFFD20F Default address is $FFFFD20F. This is the
MVME162P2 GCSR GPCSR0 as accessed through VMEbus A16 space; it assumes the
MVME162P2 GRPAD (group address) and
BDAD (board address within group) switches are set to "on". This byte-wide value is initialized to $FF by MVME162P2 hardware after a System or Power-On reset. In a multi-
162P2 environment, where the work pages of several Bugs reside in the memory of the primary (first) MVME162P2, the non-primary
CPUs will wait for the data at the Memory
Search Delay Address to be set to $00, $01, or
$02 (refer to the Memory Requirements section in Chapter 3 for the definition of these values) before attempting to locate their work page in the memory of the primary CPU.
Y Memory is sized for Self-Test diagnostics.
00000000 Default Starting Address is $0.
3-14 Computer Group Literature Center Web Site
ENV - Set Environment
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
Memory Size Ending Address
Note
Memory Configuration Defaults.
The default configuration for Dynamic RAM mezzanine boards will position the mezzanine with the largest memory size to start at the address selected with the ENV parameter "Base Address of
Dynamic Memory". The Base Address parameter defaults to 0. The smaller sized mezzanine will follow immediately above the larger in the memory map. If mezzanines of the same size and type are present, the first (closest to the board) is mapped to the selected base address. If mezzanines of the same size but different type (parity and ECC) are present, the parity type will be mapped to the selected base address and the ECC type mezzanine will follow. The SRAM does not default to a location in the memory map that is contiguous with Dynamic RAM.
Base Address of Dynamic
Memory
00000000 Beginning address of Dynamic Memory
(Parity and/or ECC type memory). Must be a multiple of the Dynamic Memory board size, starting with 0. Default is $0.
Size of Parity Memory
Default Meaning of Default
00100000 Default Ending Address is the calculated size of local memory.
Size of ECC Memory Board 0
Size of ECC Memory Board 1
Base Address of Static Memory
Size of Static Memory
00100000 The size of the Parity type dynamic RAM mezzanine, if any. The default is the calculated size of the Dynamic memory mezzanine board.
00000000 The size of the first ECC type memory mezzanine. The default is the calculated size of the memory mezzanine.
00000000 The size of the second ECC type memory mezzanine. The default is the calculated size of the memory mezzanine.
FFE00000 The beginning address of SRAM. The default is FFE00000 for the onboard 128KB SRAM, or E1000000 for the 2MB SRAM mezzanine.
If only 2MB SRAM is present, it defaults to address 00000000.
00080000 The size of the SRAM type memory present.
The default is the calculated size of the onboard SRAM or an SRAM type mezzanine.
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162Bug Firmware
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options Default Meaning of Default
ENV asks the following series of questions to set up the VMEbus interface for the MVME162 series modules. You should have a working knowledge of the VMEchip2 as given in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference Guide in order to perform this configuration. Also included in this series are questions for setting ROM and Flash access time.
The slave address decoders are used to allow another VMEbus master to access a local resource of the MVME162P2. There are two slave address decoders set. They are set up as follows:
Slave Enable #1 [Y/N]
Slave Starting Address #1
Slave Ending Address #1
Slave Address Translation
Address #1
Slave Address Translation Select
#1
Slave Control #1
Y Yes, set up and enable Slave Address Decoder
#1.
00000000 Base address of the local resource that is accessible by the VMEbus. Default is the base of local memory, $0.
000FFFFF Ending address of the local resource that is accessible by the VMEbus. Default is the end of calculated memory.
00000000 This register allows the VMEbus address and the local address to differ. The value in this register is the base address of the local resource that is associated with the starting and ending address selection from the previous questions.
Default is 0.
00000000 This register defines which bits of the address are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.
03FF Defines the access restriction for the address space defined with this slave address decoder.
Default is $03FF.
Slave Enable #2 [Y/N]
Slave Starting Address #2
Slave Ending Address #2
Slave Address Translation
Address #2
N Do not set up and enable Slave Address
Decoder #2.
00000000 Base address of the local resource that is accessible by the VMEbus. Default is 0.
00000000 Ending address of the local resource that is accessible by the VMEbus. Default is 0.
00000000 Works the same as Slave Address Translation
Address #1. Default is 0.
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ENV - Set Environment
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
Slave Address Translation Select
#2
Slave Control #2
Master Enable #1 [Y/N]
Master Starting Address #1
Master Ending Address #1
Master Control #1
Master Enable #2 [Y/N]
Master Starting Address #2
Master Ending Address #2
Master Control #2
Master Enable #3 [Y/N]
Default Meaning of Default
00000000 Works the same as Slave Address Translation
Select #1. Default is 0.
0000
Y
Defines the access restriction for the address space defined with this slave address decoder.
Default is $0000.
Yes, set up and enable Master Address
Decoder #1.
02000000 Base address of the VMEbus resource that is accessible from the local bus. Default is the end of calculated local memory (unless memory is less than 16MB; then this register is always set to 01000000).
EFFFFFFF Ending address of the VMEbus resource that is accessible from the local bus. Default is the end of calculated memory.
0D
N
Defines the access characteristics for the address space defined with this master address decoder. Default is $0D.
Do not set up and enable Master Address
Decoder #2.
00000000 Base address of the VMEbus resource that is accessible from the local bus. Default is
$00000000.
00000000 Ending address of the VMEbus resource that is accessible from the local bus. Default is
$00000000.
00 Defines the access characteristics for the address space defined with this master address decoder. Default is $00.
Depends on calculated size of local
RAM
Yes, set up and enable Master Address
Decoder #3. This is the default if the board contains less than 16MB of calculated RAM.
Do not set up and enable the Master Address
Decoder #3. This is the default for boards containing at least 16MB of calculated RAM.
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162Bug Firmware
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
Master Starting Address #3
Master Ending Address #3
Master Control #3
Master Enable #4 [Y/N]
Master Starting Address #4
Master Ending Address #4
Master Address Translation
Address #4
Master Address Translation Select
#4
Master Control #4
Default Meaning of Default
00000000 Base address of the VMEbus resource that is accessible from the local bus. If enabled, the value is calculated as one more than the calculated size of memory. If not enabled, the default is $00000000.
00000000 Ending address of the VMEbus resource that is accessible from the local bus. If enabled, the default is $00FFFFFF, otherwise $00000000.
00 Defines the access characteristics for the address space defined with this master address decoder. If enabled, the default is $3D, otherwise $00.
N Do not set up and enable Master Address
Decoder #4.
00000000 Base address of the VMEbus resource that is accessible from the local bus. Default is $0.
00000000 Ending address of the VMEbus resource that is accessible from the local bus. Default is $0.
00000000 This register allows the VMEbus address and the local address to differ. The value in this register is the base address of the VMEbus resource that is associated with the starting and ending address selection from the previous questions. Default is 0.
00000000 This register defines which bits of the address are significant. A logical "1" indicates significant address bits, logical "0" is nonsignificant. Default is 0.
00 Defines the access characteristics for the address space defined with this master address decoder. Default is $00.
Y Yes, Enable the Short I/O Address Decoder. Short I/O (VMEbus A16) Enable
[Y/N]
Short I/O (VMEbus A16) Control 01 Defines the access characteristics for the address space defined with the Short I/O address decoder. Default is $01.
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ENV - Set Environment
Table 3-3. ENV Command Parameters (Continued)
ENV Parameter and Options
F-Page (VMEbus A24) Enable
[Y/N]
F-Page (VMEbus A24) Control
Default
Y
02
Meaning of Default
Yes, Enable the F-Page Address Decoder.
ROM Access Time Code
Flash Access Time Code
MCC Vector Base
VMEC2 Vector Base #1
VMEC2 Vector Base #2
VMEC2 GCSR Group Base
Address
VMEC2 GCSR Board Base
Address
VMEbus Global Time Out Code
Local Bus Time Out Code
VMEbus Access Time Out Code
04
03
05
06
07
D2
00
01
02
02
Defines the access characteristics for the address space defined with the F-Page address decoder. Default is $02.
Defines the ROM access time. The default is
$04, which sets an access time of five clock cycles of the local bus.
Defines the Flash access time. The default is
$03, which sets an access time of four clock cycles of the local bus.
Base interrupt vector for the component specified. Default: MC2chip = $05, VMEchip2
Vector 1 = $06, VMEchip2 Vector 2 = $07.
Specifies group address ($FFFFXX00) in Short
I/O for this board. Default = $D2.
Specifies base address ($FFFFD2XX) in Short
I/O for this board. Default = $00.
Controls VMEbus timeout when the
MVME162P2 is system controller. Default $01
= 64
µ s.
Controls local bus timeout. Default $02 = 256
µ s.
Controls the local-bus-to-VMEbus access timeout. Default $02 = 32 ms.
Configuring the IndustryPacks
ENV asks the following series of questions to set up IndustryPack modules
(IPs) on MVME162P2s.
The MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide describes the base addresses and the IP register settings. Refer to that manual for information on setting base addresses and register bits.
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162Bug Firmware
IP A Base Address
IP B Base Address
IP C Base Address
IP D Base Address
= 00000000?
= 00000000?
= 00000000?
= 00000000?
Base address for mapping IP modules. Only the upper 16 bits are significant.
IP D/C/B/A Memory Size = 00000000?
Define the memory size requirements for the IP modules:
Bits IP Register Address
31-24 D FFFBC00F
23-16 C
15-08 B
07-00 A
FFFBC00E
FFFBC00D
FFFBC00C
IP D/C/B/A General Control = 00000000?
Define the general control requirements for the IP modules:
Bits IP Register Address
31-24 D FFFBC01B
23-16 C
15-08 B
07-00 A
FFFBC01A
FFFBC019
FFFBC018
IP D/C/B/A Interrupt 0 Control = 00000000?
Define the interrupt control requirements for the IP modules, channel 0:
Bits IP Register Address
31-24 D FFFBC016
23-16 C
15-08 B
07-00 A
FFFBC014
FFFBC012
FFFBC010
3-20 Computer Group Literature Center Web Site
ENV - Set Environment
IP D/C/B/A Interrupt 1 Control = 00000000?
Define the interrupt control requirements for the IP modules, channel 1:
Bits IP Register Address
31-24 D FFFBC017
23-16
15-08
C
B
07-00 A
FFFBC015
FFFBC013
FFFBC011
!
Caution
If you have specified environmental parameters that will cause an overlap condition, a warning message will appear before the environmental parameters are saved in NVRAM. The important information about each configurable element in the memory map is displayed, showing where any overlap conditions exist. This allows you to quickly identify and correct an undesirable configuration before it is saved.
If an undesirable configuration already exists, you may wish to restore the factory defaults with env;d <CR>.
ENV warning example:
WARNING: Memory MAP Overlap Condition Exists
S-Address E-Address Enable Overlap M-Type Memory-MAP-Name
$00000000 $FFFFFFFF Yes Yes Master Local Memory (Dynamic RAM)
$FFE00000 $FFE7FFFF Yes Yes Master Static RAM
$01000000 $EFFFFFFF Yes
$00000000 $00000000 No
$00000000 $00FFFFFF Yes
$00000000 $00000000 No
$F0000000 $FF7FFFFF Yes
Yes
No
Yes
No
Yes
Master
Master
VMEbus Master #1
VMEbus Master #2
Master VMEbus Master #3
Master VMEbus Master #4
Master VMEbus F Pages (A24/A32)
$FFFF0000 $FFFFFFFF Yes
$FF800000 $FFBFFFFF Yes
$FFF00000 $FFFEFFFF Yes
$00000000 $00000000 No
$00000000 $00000000 No
$00000000 $00000000 No
Yes
Yes
Yes
No
No
No
Master VMEbus Short I/O (A16)
Master Flash/PROM
Master Local I/O
Master Industry Pack A
Master Industry Pack B
Master Industry Pack C
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162Bug Firmware
$00000000 $00000000 No
$00000000 $00000000 No
$00000000 $00000000 No
No
No
No
Master Industry Pack D
Slave VMEbus Slave #1
Slave VMEbus Slave #2
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4
Functional Description
4
Introduction
This chapter describes the MVME162P2 VME embedded controller on a block diagram level. The Summary of Features provides an overview of the MVME162P2, followed by a detailed description of several blocks of
shows a block diagram of the overall board architecture.
Detailed descriptions of other MVME162P2 blocks, including programmable registers in the ASICs and peripheral chips, can be found in the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide (part number VME1X2P2A/PG). Refer to that manual for a functional description of the MVME162P2 in greater depth.
Summary of Features
The following table summarizes the features of the MVME162P2 VME embedded controller.
Table 4-1. MVME162P2 Features
Feature
Microprocessor
Form factor
Memory
Flash memory
EPROM
Real-time clock
Description
MVME162P2: 25MHz MC68040 or MC68LC040 processor
6U VMEbus
16/32MB synchronous DRAM (SDRAM), configurable to emulate
1/4/8/16/MB parity-protected DRAM or 4/8/16/32MB ECC-protected
DRAM
512KB SRAM with battery backup
MVME162P2: One Intel 28F016SA 1MB or 2MB 8-bit Flash device
Two 32-pin JEDEC standard PLCC EPROM sockets
8KB NVRAM with RTC, battery backup, and watchdog function (SGS-
Thomson M48T58)
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Functional Description
Table 4-1. MVME162P2 Features (Continued)
Feature
Switches
Status LEDs
Timers
Interrupts
VME I/O
Serial I/O
Ethernet I/O
IP interface
SCSI I/O
VMEbus interface
Description
RESET and ABORT switches on front panel
Four: Board Fail (FAIL) , CPU Activity (RUN) , System Controller ( SCON ),
Fuse Status ( FUSES )
Four 32-bit tick timers and watchdog timer in Petra ASIC
Two 32-bit tick timers and watchdog timer in VMEchip2 ASIC
Eight software interrupts (on versions with VMEchip2 ASIC)
VMEbus P2 connector
Four EIA-232-D serial ports via front panel
Optional Ethernet transceiver interface with DMA via DB15 connector on front panel
Two IndustryPack interface channels with DMA via 3M connectors behind front panel
Optional SCSI interface with DMA via front panel
VMEbus system controller functions
VMEbus-to-local-bus interface (A24/A32, D8/D16/D32/block transfer
[D8/D16/D32/D64])
Local-bus-to-VMEbus interface (A16/A24/A32, D8/D16/D32)
VMEbus interrupter
VMEbus interrupt handler
Global Control/Status Register (GCSR) for interprocessor communications
DMA for fast local memory/VMEbus transfers (A16/A24/A32,
D16/D32/D64)
4-2 Computer Group Literature Center Web Site
Summary of Features
Processor and Memory
The MVME162P2 is based on the MC68040/MC68LC040 microprocessor. The boards are built with 16MB or 32MB shared DRAM
(SDRAM). Various versions of the MVME162P2 have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected
DRAM or 4MB, 8MB, 16MB, or 32MB of ECC-protected DRAM.
All boards are available with 512KB of SRAM (with battery backup); time-of-day clock (with battery backup); an optional Ethernet transceiver interface; four serial ports with EIA-232-D interface; six tick timers with watchdog timer(s); two EPROM sockets; 1MB or 2MB Flash memory
(one Flash device); two IndustryPack (IP) interfaces with DMA; optional
SCSI bus interface with DMA; and an optional VMEbus interface (local bus to VMEbus/VMEbus to local bus, with A16/A24/A32, D8/D16/D32 bus widths and a VMEbus system controller).
I/O Implementation
Peripheral input/output (I/O) signals on the MVME162P2 are routed through the front panel.
The I/O connections for the four serial ports are implemented with four
RJ45 connectors on the front panel. In addition, the panel has cutouts for routing of flat cables to the optional IndustryPack modules.
SCSI devices are interfaced via an industry-standard 68-pin panel connector. The Ethernet interface uses a DB15 connector.
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Functional Description
ASICs
The following ASICs are used on the MVME162P2:
❏ VMEchip2 ASIC (VMEbus interface). Provides two tick timers, a watchdog timer, programmable map decoders for the master and slave interfaces, and a VMEbus-to/from-local-bus DMA controller as well as a VMEbus-to/from-local-bus non-DMA programmed access interface, a VMEbus interrupter, a VMEbus system controller, a VMEbus interrupt handler, and a VMEbus requester.
Processor-to-VMEbus transfers are D8, D16, or D32. VMEchip2
DMA transfers to the VMEbus, however, are D16, D32, D16/BLT,
D32/BLT, or D64/MBLT.
❏ Petra ASIC. Combines the functions previously covered by the
MC2 chip, the MCECC chip, and the IP2 chip in a single ASIC.
– MC2 function. Provides a parity DRAM emulation. Also supplies four tick timers and interfaces to the LAN chip, SCSI chip, serial port chip, BBRAM, EPROM/Flash, and SRAM.
– MCECC function. Provides an ECC DRAM emulation.
– IP2 function. Provides control and status information for up to two single-wide or one double-wide IndustryPack module, which can be plugged into the MVME162P2 main board.
Block Diagram
The block diagram in
illustrates the
MVME162P2’s overall architecture.
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Block Diagram
4
Figure 4-1. MVME162P2 Block Diagram http://www.motorola.com/computer/literature 4-5
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Functional Description
Functional Description
This section contains a functional description of the major blocks on the
MVME162P2.
Data Bus Structure
The local bus on the MVME162P2 is a 32-bit synchronous bus that is based on the MC68040 bus, and which supports burst transfers and snooping. The various local bus master and slave devices use the local bus to communicate. The local bus is arbitrated by priority type; the priority of the local bus masters from highest to lowest is: 82596CA LAN, 53C710
SCSI, VMEbus, and MPU. As a general rule, any master can access any slave; not all combinations pass the common sense test, however. Refer to the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide and to the user’s guide for each device to determine its port size, data bus connection, and any restrictions that apply when accessing the device.
Microprocessor
MVME162P2 models may be ordered with an MC68040 or MC68LC040 microprocessor.
The MC68040 has on-chip instruction and data caches and a floating-point processor. (A floating-point coprocessor is the major difference between the MC68040 and MC68LC040.) Refer to the MC68040 user’s manual for more information.
MC68 xx040 Cache
The MVME162P2 local bus masters (VMEchip2, processor, 53C710
SCSI controller, and 82596CA Ethernet controller) have programmable control of the snoop/caching mode. The IP DMA local bus master’s snoop control function is governed by the settings of switch S5 segments 1 and 2
(refer to
IP DMA Snoop Control (S5 Pins 1/2) on page 1-18
). S5 determines the value of the snoop control signal for all IP DMA transfers.
This includes the IP DMA which executes when the DMA control registers are updated while the IP DMA is operating in command chaining mode.
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Functional Description
The MVME162P2 local bus slaves that support the snoop/caching mode are defined in the “Local Bus Memory Map” section of the MVME1X2P2
VME Embedded Controller Programmer’s Reference Guide.
Note As outlined in
, the snoop capabilities of the
MC68xx040 processor differ from those of the MC68xx060 used on MVME172P2 series boards. Application software must take these differences into account.
No-VMEbus-Interface Option
In support of possible future configurations in which the MVME162P2 might be offered as an embedded controller without the VMEbus interface, certain logic in the VMEchip2 has been duplicated in the Petra chip. (For the location of the overlapping logic, refer to Chapter 1 in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide.) As long as the VMEchip2 ASIC is present, the redundant logic is inhibited in the Petra chip. The enabling signals for these functions are controlled by software and Petra chip hardware initialization.
Memory Options
The following memory options are available on the different versions of
MVME162P2 boards.
DRAM
MVME162P2 boards are built with 16MB or 32MB shared DRAM
(SDRAM). Depending on build options chosen at the time of manufacture, various versions of the MVME162P2 have the SDRAM configured to model 1MB, 4MB, 8MB, or 16MB of parity-protected DRAM or 4MB,
8MB, 16MB, or 32MB of ECC-protected DRAM.
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Functional Description
The SDRAM memory array itself is always a single-bit error correcting and multi-bit error detection memory, irrespective of which interface model you use to access the SDRAM. When the MC2 (parity) memory controller interface is used to access the SDRAM, single-bit errors are undetectable to users and multi-bit errors are defined to be parity errors.
Firmware will initialize the memory controller to maintain backward compatibility with MVME162LX or -FX products. If the Petra ASIC is supporting MVME162FX functionality, the parity memory controller model will be enabled by default. If the Petra ASIC is supporting
MVME162LX functionality, firmware will enable either the parity or the
ECC memory controller model, depending on board configuration. (The board configuration is a function of switch settings and resistor population options.)
User code can modify Petra register settings to operate in either mode.
User code can also modify map decoder/switch settings to enable the maximum amount of memory available. The minimum SDRAM configuration is 16MB.
For specifics on SDRAM performance and for detailed programming information, refer to the chapters on MC2 and MCECC memory controller emulations in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide.
SRAM
The MVME162P2 implementation includes a 512KB SRAM (static
RAM) option. SRAM architecture is single non-interleaved. SRAM performance is described in the section on the SRAM memory interface in the chapter on the MC2 memory controller emulation in the MVME1X2P2
VME Embedded Controller Programmer’s Reference Guide. An onboard battery supplies VCC to the SRAM when main power is removed. The
SRAM arrays are not parity protected.
The battery backup function for the onboard SRAM is provided by a cointype Panasonic CR2032 device (or equivalent) that supports primary and secondary power sources. In the event of a main board power failure, the
CR2032 checks power sources and switches to the source with the higher voltage.
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Functional Description
If the voltage of the backup source is lower than two volts, the CR2032 blocks the second memory cycle; this allows software to provide an early warning to avoid data loss. Because the second access may be blocked during a power failure, software should do at least two accesses before relying on the data.
The MVME162P2 provides jumpers (on J14) that allow either power source of the CR2032 to be connected to the VMEbus +5V STDBY pin or to one cell of the onboard battery. For example, the primary system backup source may be a battery connected to the VMEbus +5V STDBY pin and the secondary source may be the onboard battery. If the system source should fail or the board is removed from the chassis, the onboard battery takes over.
!
Caution
For proper SRAM operation, some jumper combination must be installed on the Backup Power Source Select header (refer to the jumper information in Chapter 1). If one of the jumpers is set to select the battery, a battery must be installed on the MVME162P2. The SRAM may malfunction if inputs to the CR2032 are left unconnected.
The SRAM is controlled by the Petra MC2 sector, and the access time is programmable. Refer to the description of the Petra MC2 emulation in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide for more detail.
About the Battery
The power source for the onboard SRAM is a coin-type Panasonic
CR2032 device (or equivalent) with two lithium cells. The battery is socketed for easy removal and replacement. Small capacitors are provided so that the battery can be quickly replaced without data loss.
The service life of the battery is very dependent on the ambient temperature of the board and the power-on duty cycle. The lithium battery supplied on the MVME162P2 should provide at least two years of backup time with the board powered off and with an ambient temperature of 40
°
C. If the power-on duty cycle is 50% (the board is powered on half of the time), the battery lifetime is four years. At lower ambient temperatures, the backup time is correspondingly longer.
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Functional Description
If you intend to place the board in storage, putting the M48T58 in powersave mode by stopping the oscillator will prolong battery life. This is especially important at high ambient temperatures. To enter power-saving mode, execute the 162Bug PS command (refer to Debugger Commands in
Chapter 3) or its equivalent application-specific command. When restoring the board to service, execute the 162Bug SET command (set
mmddyyhhmm) after installation to restart the oscillator and initialize the clock.
The MVME162P2 is shipped with the battery disconnected (i.e., with
VMEbus +5V standby voltage selected as both primary and secondary power source). In order to use the battery as a power source, whether primary or secondary, it is necessary to reconfigure the jumpers on J14 before installing the board. Refer to
SRAM Backup Power Source (J14) on page 1-10
for available jumper configurations.
The power leads from the battery are exposed on the solder side of the board. The board should not be placed on a conductive surface or stored in a conductive bag unless the battery is removed.
!
Warning
Lithium batteries incorporate inflammable materials such as lithium and organic solvents. If lithium batteries are mistreated or handled incorrectly, they may burst open and ignite, possibly resulting in injury and/or fire.
When dealing with lithium batteries, carefully follow the precautions listed below in order to prevent accidents.
❏ Do not short circuit.
❏ Do not disassemble, deform, or apply excessive pressure.
❏ Do not heat or incinerate.
❏ Do not apply solder directly.
❏ Do not use different models, or new and old batteries together.
❏ Do not charge.
❏ Always check proper polarity.
4-10 Computer Group Literature Center Web Site
Functional Description
To remove the battery from the module, carefully pry the battery from its socket.
Before installing a new battery, ensure that the battery pins are clean. Note the battery polarity and press the battery into the socket. When the battery is in the socket, no soldering is required.
EPROM and Flash Memory
The MVME162P2 implementation includes 1MB or 2MB Flash memory.
Flash memory is a single Intel device (28F016SA on the MVME162P2) organized in a 1MB x 8 or 2Mb x 8 configuration. For information on programming Flash, refer to the Intel documents listed under
Manufacturer’s Documents in the Related Documentation appendix.
The Flash write enable signal is controlled by:
❏ A bit in the Flash Access Time Control register in the Petra ASIC
❏ A board-level configuration jumper (J16) and configuration switch
(S5, segment 4) which determine the status of Flash write protection on the board
Refer to the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for specifics.
The EPROM locations are standard JEDEC 32-pin PLCC sockets that accommodate three jumper-selectable densities (256 Kb x 8; 512 Kb x 8, the factory default; 1 Mb x 8). The setting of a configuration switch (line
GPI3, segment 5 on S4), allows reset code to be fetched either from Flash memory (S4 segment 5 set to OFF ) or from EPROMs (S4 segment 5 set to
ON ).
Note that MVME162P2 models ordered without the VMEbus interface are shipped with Flash memory blank (the factory uses the VMEbus to program the Flash memory with debugger code). To use the debugger firmware, be sure that configuration switch S4 is set for the EPROM memory map. Refer to chapters 1 and 3 for further details.
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Functional Description
Battery-Backed-Up RAM and Clock
An M48T58 RAM and clock chip is used on the MVME162P2. This chip provides a time-of-day clock, oscillator, crystal, power fail detection, memory write protection, 8KB of RAM, and a battery in one 28-pin package. The clock provides seconds, minutes, hours, day, date, month, and year in BCD 24-hour format. Corrections for 28-, 29- (leap year), and
30-day months are made automatically. No interrupts are generated by the clock. Although the M48T58 is an 8-bit device, the interface provided by the Petra chip supports 8-, 16-, and 32-bit accesses to the M48T58. Refer to the description of the Petra MC2 function in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide and to the M48T58 data sheet for detailed programming guidance and battery life information.
VMEbus Interface and VMEchip2
The VMEchip2 ASIC provides the local-bus-to-VMEbus interface, the
VMEbus-to-local-bus interface, and the DMA controller functions of the local VMEbus. The VMEchip2 also provides the VMEbus system controller functions. Refer to the VMEchip2 description in the
MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide for detailed programming information.
Note that the Abort switch logic in the VMEchip2 is not used. The GPI inputs to the VMEchip2 which are located at $FFF40088 bits 7-0 are not used. Instead, the Abort switch interrupt is integrated into the Petra MC2 sector at location $FFF42043. The GPI inputs are integrated into the Petra
MC2 sector at location $FFF4202C, bits 23-16.
I/O Interfaces
The MVME162P2 provides onboard I/O for many system applications.
The I/O functions include serial ports, IndustryPack (IP) interfaces, and optional interfaces for LAN Ethernet transceivers and SCSI mass storage devices.
4-12 Computer Group Literature Center Web Site
Functional Description
Serial Communications Interface
The MVME162P2 uses two Zilog Z85230 serial port controllers to implement the four serial communications interfaces. Each interface supports CTS, DCD, RTS, and DTR control signals, as well as the TXD and RXD transmit/receive data signals.
Because the serial clocks are omitted in the MVME162P2 implementation, serial communications are strictly asynchronous. The MVME162P2 hardware supports serial baud rates of 110b/s to 38.4Kb/s.
The Z85230 supplies an interrupt vector during interrupt acknowledge cycles. The vector is modified based upon the interrupt source within the
Z85230. Interrupt request levels are programmed via the Petra MC2 function (the MC2 emulation can handle up to four Z85230 chips). Refer to the Z85230 data sheet listed listed under Manufacturer’s Documents in the Related Documentation appendix, and to the MC2 programming model in the MVME1X2P2 VME Embedded Controller Programmer’s Reference
Guide, for information.
The Z85230s are interfaced as DTE (data terminal equipment) with EIA-
232-D signal levels. The four serial ports are routed to four RJ45 connectors on the MVME162P2 front panel.
IndustryPack (IP) Interfaces
The IP2 function in the Petra ASIC supports four IndustryPack (IP) interfaces; the MVME162P2 board itself accommodates up to two IP modules. The IP modules are accessible from the front panel. The IP2 function as implemented on the MVME162P2 also includes two DMA channels (one for each IP, or two for a double-wide IP), 32 or 30MHz (32
MHz for MC68LC0x0 or 30 MHz for MC680x0) or 8MHz IndustryPack clock selection (jumper selectable), and one programmable timebase strobe which is connected to the two interfaces. Refer to the IP2
Programming Model in the MVME1X2P2 VME Embedded Controller
Programmer's Reference Guide for details of the IP interface. Refer to
Chapter 5, Pin Assignments for the pin assignments of the IP connectors.
4 http://www.motorola.com/computer/literature 4-13
4
Functional Description
Notes MVME162P2 boards do not monitor power supply +5 Vdc power and assert IP reset if the power falls too low. Instead, IP reset is handled by the ENV command of the 162Bug debugger, as described in Chapter 3. The IP reset is also driven active by the power-up reset signal.
Two IP modules plugged into the same MVME162P2 board can
not use the Strobe
∗
signal unless the jumper is removed from J11.
This will disconnect the Strobe
∗
output from the Petra/IP2 ASIC.
Ethernet Interface
The MVME162P2 uses the Intel 82596CA LAN coprocessor to implement the optional Ethernet transceiver interface. The 82596CA accesses local
RAM using DMA operations to perform its normal functions. Because the
82596CA has small internal buffers and the VMEbus has an undefined latency period, buffer overrun may occur if the DMA is programmed to access the VMEbus. Therefore, the 82596CA should not be programmed to access the VMEbus.
Every MVME162P2 that is built with an Ethernet interface is assigned an
Ethernet Station Address. The address is $0001AF2xxxxx, where xxxxx is the unique 5-nibble number assigned to the board (i.e., every
MVME162P2 has a different value for xxxxx).
Each board has an Ethernet Station Address displayed on a label attached to the VMEbus P2 connector. In addition, the six bytes including the
Ethernet address are stored in the BBRAM configuration area. That is,
0001AF2xxxxx is stored in the BBRAM. The upper four bytes (0001AF2x) are read at $FFFC1F2C; the lower two bytes (xxxx) are read at
$FFFC1F30. The MVME162 debugger has the capability to retrieve or set the Ethernet address.
If the data in BBRAM is lost, use the number on the label on backplane connector P2 to restore it.
The Ethernet transceiver interface is located on the MVME162P2 main board, and the industry-standard DB15 connector is located on its front panel.
4-14 Computer Group Literature Center Web Site
Functional Description
Support functions for the 82596CA LAN coprocessor are provided by the
Petra MC2 sector. Refer to the 82596CA user’s guide and to the description of the MC2 function in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide for detailed programming information.
SCSI Interface
The MVME162P2 may have provision for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices. The optional SCSI interface is implemented using the NCR
53C710 SCSI I/O controller.
Support functions for the 53C710 are provided by the Petra MC2 sector.
Refer to the NCR 53C710 user’s guide and to the description of the MC2 function in the MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide for detailed programming information.
SCSI Termination
It is important that the SCSI bus be properly terminated at both ends.
In the case of the MVME162P2, terminators for the SCSI bus are present on the main board. The SCSI terminators are enabled or disabled by a jumper on header J12. If the SCSI bus ends at the MVME162P2, a jumper must be installed at J12.
The FUSES LED on the MVME162P2 front panel monitors +5V power to the SCSI bus TERM power line in addition to LAN power and
IndustryPack power; the FUSES LED illuminates when all fuses on the
MVME162P2 are operational. (The fuses are solid-state circuit breakers that reset when the short which trips them is removed.) Because any device on the SCSI bus can provide power to the TERM power line, the FUSES
LED does not directly indicate the condition of the fuse.
Local Resources
The MVME162P2 includes many resources for the local processor. These include tick timers, software-programmable hardware interrupts, a watchdog timer, and a local bus timeout. http://www.motorola.com/computer/literature 4-15
4
4
Functional Description
Programmable Tick Timers
Six 32-bit programmable tick timers with 1
µ s resolution are available: two in the VMEchip2 ASIC and four in the Petra/MC2 chip. The tick timers may be programmed to generate periodic interrupts to the processor. Refer to the VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide for detailed programming information.
Watchdog Timer
A watchdog timer function is provided in both the Petra/MC2 chip and the
VMEchip2 ASIC. When the watchdog timer is enabled, it must be reset by software within the programmed interval or it times out. The watchdog timer can be programmed to generate a SYSRESET signal, a local reset signal, or a board fail signal if it times out. Refer to the VMEchip2 and
Petra/MC2 descriptions in the MVME1X2P2 VME Embedded Controller
Programmer’s Reference Guide for detailed programming information.
The watchdog timer logic is duplicated in the VMEchip2 and Petra/MC2
ASICs. Because the watchdog timer function in the VMEchip2 is a superset of that function in the Petra/MC2 chip (system reset function), the timer in the VMEchip2 is to be used in all cases except for versions of the
MVME162P2 which do not include the VMEbus interface (i.e., boards ordered with a "No VMEbus Interface" option).
Software-Programmable Hardware Interrupts
The VMEchip2 ASIC supplies eight software-programmable hardware interrupts. These interrupts allow software to create a hardware interrupt.
Refer to the VMEchip2 description in the MVME1X2P2 VME Embedded
Controller Programmer’s Reference Guide for detailed programming information.
Local Bus Timeout
The MVME162P2 provides timeout functions in the VMEchip2 ASIC and the Petra/MC2 chip for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by software for 8
4-16 Computer Group Literature Center Web Site
Functional Description
µ sec, 64
µ sec, 256
µ sec, or infinity. The local bus timer does not operate during VMEbus bound cycles. VMEbus bound cycles are timed by the
VMEbus access timer and the VMEbus global timer. Refer to the
VMEchip2 and Petra/MC2 descriptions in the MVME1X2P2 VME
Embedded Controller Programmer’s Reference Guide for detailed programming information.
The access timer logic is duplicated in the VMEchip2 and Petra/MC2
ASICs. Because the local bus timer in the VMEchip2 can detect an offboard access and the Petra/MC2 local bus timer cannot, the timer in the
VMEchip2 ASIC is used in all cases except for versions of the
MVME162P2 which do not include the VMEbus interface (i.e., boards ordered with a "No VMEbus Interface" option).
Local Bus Arbiter
The local bus arbiter implements a fixed priority (see Table 4-2 ).
Table 4-2. Local Bus Arbitration Priority
Device Priority
LAN 0
Industry Pack DMA 1
SCSI 2
VMEbus
MC680x0/MC68LC0x0
3
4
Note
Highest
...
Next Lowest
Lowest
4 http://www.motorola.com/computer/literature 4-17
4
Functional Description
Connectors
The MVME162P2 has two 96-position DIN connectors: P1 and P2. P1 rows A, B, C, and P2 row B provide the VMEbus interconnection. P2 rows
A and C are not used.
The serial ports on the MVME162P2 are connected to four 8-pin RJ45 female connectors ( J17) on the front panel. The two IP modules connect to the MVME162P2 by two pairs of 50-pin connectors. Two additional 50pin connectors behind the front panel are for external connections to IP signals. The Ethernet LAN connector (J9) is a 15-pin socket connector mounted on the front panel. The SCSI connector (J23) is a 68-pin socket connector mounted on the front panel.
Pin assignments for the connectors on the MVME162P2 are listed in
Chapter 5.
Remote Status and Control
The remote reset connector, J2, is a 20-pin connector located behind the front panel of the MVME162P2. It provides system designers with flexibility in accessing critical indicator and reset functions. When the board is enclosed in a chassis and the front panel is not visible, this connector allows the Reset, Abort, and LED functions to be extended to the control panel of the system, where they are visible. Alternatively, it allows a system designer to construct a RESET / ABORT /LED panel that can be located remotely from the MVME162P2.
4-18 Computer Group Literature Center Web Site
5
Pin Assignments
5
Connector Pin Assignments
This chapter summarizes the pin assignments for the following groups of interconnect signals on the MVME162P2:
Connector
Remote Reset connector
IndustryPack A and B connectors
Ethernet port, DB15
Serial ports, RJ45
SCSI connector
VMEbus connector P1
VMEbus connector P2
Location
J2
J4/5/6, J3/7/8
J9
J17
J23
P1
P2
Table
The tables in this chapter furnish pin assignments only. For detailed descriptions of the interconnect signals, consult the support information for the MVME162P2 (available through your Motorola sales office).
5-1
5
Pin Assignments
Remote Reset Connector - J2
The MVME162P2 has a 20-pin connector (J2) mounted behind the front panel. When the MVME162P2 board is enclosed in a chassis and the front panel is not visible, this connector enables you to extend the reset, abort and LED functions to the control panel of the system, where they remain accessible.
Table 5-1. Remote Reset Connector J2 Pin Assignments
9
11
13
15
17
19
5
7
1
3
+5V Fused
P12VLED
∗
VMELED
∗
RUNLED
∗
FAILSTAT
∗
SCONLED
∗
RESETSW
∗
GND
GPIO2
No connection
LANLED
∗
SCSILED
∗
No connection
STSLED
∗
No connection
ABORTSW
∗
GND
GPIO1
GPIO3
GND
10
12
14
16
6
8
2
4
18
20
IndustryPack A and B Connectors
Up to two IndustryPack (IP) modules may be installed on the
MVME162P2. For each IP module, there are two 50-pin plug connectors on the board: module A, J5/6; module B, J7/8. For external cabling to the
IP modules, two 50-pin IDC connectors (module A, J4; module B, J3) are provided behind the MVME162P2 front panel. The pin assignments are the same for both types of connector.
5-2 Computer Group Literature Center Web Site
IndustryPack A and B Connectors
+5V
IDSEL
∗
MEMSEL
∗
INTSEL
∗
IOSEL
∗
IPA1
IPA2
IPA3
IPA4
IPA5
IPA6
No Connection
GND
RESET
∗
IPD1
IPD3
IPD5
IPD7
IPD9
IPD11
IPD13
IPD15
BS1
∗
+12V
GND 25
27
29
31
17
19
21
23
9
11
13
15
5
7
1
3
41
43
45
47
49
33
35
37
39
Table 5-2. IndustryPack Interconnect Signals
CLK
IPD0
IPD2
IPD4
IPD6
IPD8
IPD10
IPD12
IPD14
BS0
∗
–12V
+5V
18
20
22
24
GND
R/W
∗
DMAREQ0
∗
DMAREQ1
∗
DMACK
∗
26
28
30
32
34
No Connection 36
DMAEND
∗
ERROR
∗
INT_REQ0
∗
INT_REQ1
∗
STROBE
∗
ACK
∗
38
40
42
44
46
48
GND 50
10
12
14
16
6
8
2
4
5 http://www.motorola.com/computer/literature 5-3
5
Pin Assignments
Ethernet Connector - J9
The MVME162P2’s Ethernet interface is implemented with a DB15 connector located on the front panel of the board. The pin assignments for this connector are listed in the following table.
Table 5-3. DB15 Ethernet Connector Pin Assignments
9
11
13
15
5
7
1
3
GND
T+
R+
No Connection
C–
GND
+12V
No Connection
C+
GND
GND
GND
T–
R–
GND
10
12
14
6
8
2
4
Serial Connector - J17
A four-segment RJ45 connector located on the front panel of the
MVME162P2 provides the interface to the four asynchronous serial ports.
The pin assignments for each segment in the connector are as follows.
Table 5-4. Serial Connector Pin Assignments
7
8
5
6
3
4
1
2
DCDn
RTSn
Ground
TXDn
RXDn
Ground
CTSn
DTRn
5-4 Computer Group Literature Center Web Site
SCSI Connector - J23
SCSI Connector - J23
Connector J23 is a standard 68-pin SCSI connector mounted on the front
panel of the MVME162P2 embedded controller. Table 5-5 lists the pin
assignments for J23.
VMEbus Connectors (P1, P2)
Two three-row 96-pin DIN type connectors, P1 and P2, supply the interface between the base board and the VMEbus. P1 provides power and
VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the IEEE P1014-1987 VMEbus Specification. P2 Row B supplies the base board with power, with the upper 8 VMEbus address lines, and with an additional 16 VMEbus data lines. P2 rows A and C are not used in the MVME162P2 implementation. The pin assignments for P1and P2 are
5 http://www.motorola.com/computer/literature 5-5
5
Pin Assignments
5-6
GND
GND
GND
GND
GND
GND
GND
GND
+5.0V TERMPWR
No Connection
GND
GND
GND
GND
GND
GND
GND
DB
∗
(12)
DB
∗
(14)
DPH
∗
DB
∗
(1)
DB
∗
(3)
DB
∗
(5)
DB
∗
(7)
GND
+5.0V TERMPWR
No Connection
ATN
∗
BSY
∗
RST
∗
SEL
∗
REQ
∗
DB
∗
(8)
DB
∗
(10)
Table 5-5. SCSI Connector J23 Pin Assignments
57
59
61
63
49
51
53
55
65
67
41
43
45
47
33
35
37
39
25
27
29
31
17
19
21
23
9
11
13
15
5
7
1
3
58
60
62
64
50
52
54
56
66
68
42
44
46
48
34
36
38
40
26
28
30
32
18
20
22
24
10
12
14
16
6
8
2
4
GND
GND
GND
GND
GND
GND
GND
GND
+5.0V TERMPWR
GND
GND
GND
GND
GND
GND
GND
GND
GND
ACK
∗
MSG
∗
DC
∗
IO
∗
DB
∗
(9)
DB
∗
(11)
GND
DB
∗
(13)
DB
∗
(15)
DB
∗
(0)
DB
∗
(2)
DB
∗
(4)
DB
∗
(6)
DBP
∗
GND
+5.0V TERMPWR
Computer Group Literature Center Web Site
VMEbus Connectors (P1, P2)
29
30
31
32
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
Row A
VA3
VA2
VA1
–12V
+5V
VD4
VD5
VD6
VD7
VD0
VD1
VD2
VD3
VA7
VA6
VA5
VA4
GND
VSYSCLK
GND
VDS1
∗
VDS0
∗
VWRITE
∗
GND
VDTACK
∗
GND
VAS
∗
GND
VIACK
∗
VIACKIN
∗
VIACKOUT
∗
VAM4
Table 5-6. VMEbus Connector P1 Pin Assignments
VAM1
VAM2
VAM3
GND
Not Used
Not Used
GND
VIRQ7
∗
VIRQ6
∗
VIRQ5
∗
VIRQ4
∗
VIRQ3
∗
VIRQ2
∗
VIRQ1
∗
Not Used
+5V
Row B
VBBSY
∗
VBCLR
∗
VACFAIL
∗
VBGIN0
∗
VBGOUT0
∗
VBGIN1
∗
VBGOUT1
∗
VBGIN2
∗
VBGOUT2
∗
VBGIN3
∗
VBGOUT3
∗
VBR0
∗
VBR1
∗
VBR2
∗
VBR3
∗
VAM0
29
30
31
32
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
Row C
VA15
VA14
VA13
VA12
VA11
VA10
VA9
VA8
+12V
+5V
VA23
VA22
VA21
VA20
VA19
VA18
VA17
VA16
VD8
VD9
VD10
VD11
VD12
VD13
VD14
VD15
GND
VSYSFAIL
∗
VBERR
∗
VSYSRESET
∗
VLWORD
∗
VAM5
5 http://www.motorola.com/computer/literature 5-7
5
Pin Assignments
Table 5-7. VMEbus Connector P2 Pin Assignment
29
30
31
32
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
ROW B
VD26
VD27
VD28
VD29
VD30
VD31
GND
+5V
VD19
VD20
VD21
VD22
VD23
GND
VD24
VD25
VA29
VA30
VA31
GND
+5V
VD16
VD17
VD18
+5V
GND
Not Used
VA24
VA25
VA26
VA27
VA28
ROW A
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
29
30
31
32
25
26
27
28
21
22
23
24
17
18
19
20
13
14
15
16
9
10
11
12
7
8
5
6
3
4
1
2
ROW C
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
5-8 Computer Group Literature Center Web Site
A
Specifications
A
Board Specifications
The following table lists the general specifications for the MVME162P2
VME embedded controller. The subsequent sections detail cooling requirements and EMC regulatory compliance.
A complete functional description of the MVME162P2 boards appears in
Chapter 4. Specifications for the optional IndustryPack modules can be found in the documentation for those modules.
Table A-1. MVME162P2 Specifications
Characteristics
Power requirements
(with EPROM; without
IPs)
Specifications
+5Vdc (±5%), 1.75A typical, 2.25A maximum
+12 Vdc (± 5%), 100 mA maximum
–12 Vdc (± 5%), 100 mA maximum
Operating temperature –5° C to 55° C ( 23° F to 131° F) exit air with forced-air cooling
(refer also to Cooling Requirements and Special Considerations for
Elevated-Temperature Operation)
Storage temperature
Relative humidity
–40° C to +85° C ( –40° F to 185° F)
5% to 90% (noncondensing)
Vibration (operating)
Altitude (operating)
Physical dimensions
(base board only)
2 Gs RMS, 20Hz-2000Hz random
5000 meters (16,405 feet)
Height Double-high VME board, 9.2 in. (233 mm)
Front panel width 0.8 in. (20 mm)
Front panel height
Depth
10.3 in. (262 mm)
6.3 in. (160 mm)
A-1
A
Specifications
Cooling Requirements
The Motorola MVME162P2 VME Embedded Controller is specified, designed, and tested to operate reliably with an incoming air temperature range of –5° to 55° C (23° to 131° F) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis. Twenty-five-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed directly under the
VME card cage. The incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the module under test. Test software is executed as the module is subjected to ambient temperature variations. Case temperatures of critical, high power density integrated circuits are monitored to ensure that component vendors’ specifications are not exceeded.
While the exact amount of airflow required for cooling depends on the ambient air temperature and the type, number, and location of boards and other heat sources, adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients. Under more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55° C with increased airflow. It is important to note that there are several factors, in addition to the rated CFM of the air mover, which determine the actual volume and speed of air flowing over a module.
A-2 Computer Group Literature Center Web Site
Cooling Requirements
Special Considerations for Elevated-Temperature Operation
The following information is for users whose applications for the
MVME162P2 may subject it to high temperatures.
The MVME162P2 uses commercial-grade devices. Therefore, it can operate in an environment with ambient air temperatures ranging from 0°
C to 70° C. Several factors influence the ambient temperature seen by components on the MVME162P2. Among them are inlet air temperature; air flow characteristics; number, types, and locations of IP modules; power dissipation of adjacent boards in the system, etc.
A temperature profile of a comparable board (the MVME172LX embedded controller) was developed in an MVME954A six-slot VME chassis. Two such boards, each loaded with two GreenSpring
IndustryPack modules, were placed in the chassis with one 36W load board installed between them. The chassis was placed in a thermal chamber that maintained an ambient temperature of 55° C. Measurements showed that the fans in the chassis supplied an airflow of approximately 65
LFM over the MVME172LX boards. Under these conditions, a rise in temperature of approximately 10° C between the inlet and exit air was observed. The junction temperatures of selected high-power devices on the
MVME172LXs were calculated (from case temperature measurements) and were found to be within manufacturers’ specified tolerances.
!
Caution
For elevated-temperature operation, perform similar measurements and calculations to determine the actual operating margin for your specific environment.
To facilitate elevated-temperature operation:
1. Position the MVME162P2 in the chassis to allow for maximum airflow over the component side of the board.
2. Do not place boards with high power dissipation next to the
MVME162P2.
3. Use low-power IP modules only.
A http://www.motorola.com/computer/literature A-3
A
Specifications
EMC Regulatory Compliance
The MVME162P2 was tested without IndustryPacks in an
EMC-compliant chassis and meets the requirements for Class B equipment. Compliance was achieved under the following conditions:
❏ Shielded cables on all external I/O ports.
❏ Cable shields connected to chassis ground via metal shell connectors bonded to a conductive module front panel.
❏ Conductive chassis rails connected to chassis ground. This provides the path for connecting shields to chassis ground.
❏ Front panel screws properly tightened.
❏ All peripherals EMC-compliant.
For minimum RF emissions, it is essential that the conditions above be implemented. Failure to do so could compromise the FCC compliance of the equipment containing the module.
The MVME162P2 is a board-level product and meant to be used in standard VME applications. As such, it is the responsibility of the OEM to meet the regulatory guidelines as determined by its application.
A-4 Computer Group Literature Center Web Site
B
Troubleshooting
B
Solving Startup Problems
In the event of difficulty with your MVME162P2 VME embedded controller, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) The selftests may not run in all user-customized environments.
Table B-1. Troubleshooting MVME162P2 Boards
Condition
I. Nothing works, no display on the terminal.
Possible Problem
A. If the RUN (or
FUSE ) LED is not lit, the board may not be getting correct power.
B. If the LEDs are lit, the board may be in the wrong slot.
C. The “system console” terminal may be configured incorrectly.
Try This:
1. Make sure the system is plugged in.
2. Check that the board is securely installed in its backplane or chassis.
3. Check that all necessary cables are connected to the board, per this manual.
4. Check for compliance with System Considerations, as described in this manual.
5. Review the Installation and Startup procedures, as described in this manual. They include a step-by-step powerup routine. Try it.
1. For VMEmodules, the processor module (controller) should be in the first (leftmost) slot.
2. Also check that the “system controller” function on the board is enabled, per this manual.
Configure the system console terminal as described in this manual.
B-1
B
Troubleshooting
Table B-1. Troubleshooting MVME162P2 Boards
Condition
II. There is a display on the terminal, but input from the keyboard has no effect.
III. Debug prompt
162-Bug> does not appear at powerup, and the board does not autoboot.
IV. Debug prompt
162-Bug> appears at powerup, but the board does not autoboot.
Possible Problem
A. The keyboard may be connected incorrectly.
B. Board jumpers may be configured incorrectly.
C. You may have invoked flow control by pressing a HOLD or PAUSE key, or by typing:
<CTRL>-S
A. Debugger
EPROM/Flash may be missing.
B. The board may need to be reset.
A. The initial debugger environment parameters may be set incorrectly.
B. There may be some fault in the board hardware.
Try This:
Recheck the keyboard connections and power.
Check the board jumpers as described in this manual.
Press the HOLD or PAUSE key again.
If this does not free up the keyboard, type in:
<CTRL>-Q
1. Disconnect all power from your system.
2. Check that the proper debugger device is installed.
3. Remove the jumper from J21, pins 9-10. This enables use of the EPROM instead of the Flash memory.
4. Reconnect power.
5. Restart the system by “double-button reset”: press the
RESET and ABORT switches at the same time; release
RESET first, wait seven seconds, then release ABORT .
6. If the debug prompt appears, go to step IV or step V, as indicated. If the debug prompt does not appear, go to step
VI.
1. Start the onboard calendar clock and timer. Type: set mmddyyhhmm <CR> where the characters indicate the month, day, year, hour, and minute. The date and time will be displayed.
!
Caution
Performing the next step (env;d) will change some parameters that may affect your system’s operation.
(continues>)
B-2 Computer Group Literature Center Web Site
Solving Startup Problems
Table B-1. Troubleshooting MVME162P2 Boards
Condition
IV. Continued
Possible Problem
V. The debugger is in system mode and the board autoboots, or the board has passed self-tests.
A. No apparent problems — troubleshooting is done.
Try This:
2. At the command line prompt, type in:
env;d <CR>
This sets up the default parameters for the debugger environment.
3. When prompted to Update Non-Volatile RAM, type in: y <CR>
4. When prompted to Reset Local System, type in: y <CR>
5. After the clock speed is displayed, immediately (within five seconds) press the Return key:
<CR> or
BREAK to exit to the System Menu. Then enter a 3 for “Go to
System Debugger” and Return:
3 <CR>
Now the prompt should be:
162-Diag>
6. You may need to use the cnfg command (see your board
Debugger Manual) to change clock speed and/or Ethernet
Address, and then later return to: env <CR> and step 3.
7. Run the selftests by typing in: st <CR>
The tests take as long as 10 minutes, depending on RAM size. They are complete when the prompt returns. (The onboard self-test is a valuable tool in isolating defects.)
8. The system may indicate that it has passed all the selftests. Or, it may indicate a test that failed. If neither happens, enter: de <CR>
Any errors should now be displayed. If there are any errors, go to step VI. If there are no errors, go to step V.
No further troubleshooting steps are required.
B http://www.motorola.com/computer/literature B-3
B
Troubleshooting
Table B-1. Troubleshooting MVME162P2 Boards
Condition
VI. The board has failed one or more of the tests listed above, and cannot be corrected using the steps given.
Possible Problem
A. There may be some fault in the board hardware or the on-board debugging and diagnostic firmware.
Try This:
1. Document the problem and return the board for service.
2. Phone 1-800-222-5640.
TROUBLESHOOTING PROCEDURE COMPLETE.
B-4 Computer Group Literature Center Web Site
C
Network Controller Data
C
Network Controller Modules Supported
The 162Bug firmware supports the following VMEbus network controller modules. The default address for each module type and position is shown to indicate where the controller must reside to be supported by the 162Bug.
The controllers are accessed via the specified CLUN and DLUNs listed here. The CLUN and DLUNs are used in conjunction with the debugger commands NBH, NBO, NIOP, NIOC, NIOT, NPING, and NAB; they are also used with the debugger system calls .NETRD, .NETWR,
.NETFOPN, .NETFRD, .NETCFIG, and .NETCTRL.
Controller
Type
MVME162P2
MVME376
MVME376
MVME376
MVME376
MVME376
MVME376
MVME374
MVME374
MVME374
MVME374
MVME374
MVME374
CLUN DLUN
$10
$11
$12
$13
$14
$15
$00
$02
$03
$04
$05
$06
$07
$00
$00
$00
$00
$00
$00
$00
$00
$00
$00
$00
$00
$00
Address
$FFF46000
$FFFF1200
$FFFF1400
$FFFF1600
$FFFF5400
$FFFF5600
$FFFFA40
0
$FF000000
$FF100000
$FF200000
$FF300000
$FF400000
$FF500000
Interface
Type
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
Ethernet
C-1
C
Network Controller Data
C-2 Computer Group Literature Center Web Site
D
Disk/Tape Controller
Data
D
Controller Modules Supported
The following VMEbus disk/tape controller modules are supported by the
162Bug. The default address for each controller type is First Address. The controller can be addressed by First CLUN during execution of the BH ,
BO , or IOP commands, or during execution of the .DSKRD or .DSKWR
TRAP #15 calls. Note that if another controller of the same type is used, the second one must have its address changed by its onboard jumpers and/or switches, so that it matches Second Address and can be called up by
Second CLUN.
Controller Type
CISC Embedded Controller
First
CLUN
$00 (Note 1)
First
Address
--
Second
CLUN
--
Second
Address
--
$11 (Note 2) $FFFFB000 $12 (Note 2) $FFFFAC00 MVME320 - Winchester/Floppy
Controller
MVME323 - ESDI Winchester
Controller
MVME327A - SCSI Controller
MVME328 - SCSI Controller
MVME328 - SCSI Controller
MVME328 - SCSI Controller
$08
$02
$06
$16
$18
$FFFFA000
$FFFFA600
$FFFF9000
$FFFF4800
$FFFF7000
$09
$03
$07
$17
$19
$FFFFA200
$FFFFA700
$FFFF9800
$FFFF5800
$FFFF7800
MVME350 - Streaming Tape
Controller
$04 $FFFF5000 $05 $FFFF5100
Notes :
1. If an MVME162P2 with an SCSI port is used, the MVME162P2 module has CLUN 0.
2. For MVME162P2s, the first MVME320 has CLUN $11; the second MVME320 has CLUN $12.
D-1
D
Disk/Tape Controller Data
Default Configurations
Note SCSI Common Command Set (CCS) devices are the only ones tested by Motorola Computer Group.
CISC Embedded Controllers -- 7 Devices
Controller LUN
0
Address
$XXXXXXXX
Device LUN
40
50
60
00
10
20
30
Device Type
SCSI Common Command Set (CCS), which may be any of these:
- Fixed direct access
- Removable flexible direct access
(TEAC style)
- CD-ROM
- Sequential access
MVME320 -- 4 Devices
Controller LUN
11
Address
$FFFFB000
12 $FFFFAC00
Device LUN
2
3
0
1
Device Type
Winchester hard drive
Winchester hard drive
5-1/4" DS/DD 96 TPI floppy drive
5-1/4" DS/DD 96 TPI floppy drive
D-2 Computer Group Literature Center Web Site
Default Configurations
MVME323 -- 4 Devices
Controller LUN
8
Address
$FFFFA000
9 $FFFFA200
Device LUN
2
3
0
1
Device Type
ESDI Winchester hard drive
ESDI Winchester hard drive
ESDI Winchester hard drive
ESDI Winchester hard drive
MVME327A -- 9 Devices
Controller LUN
2
Address
$FFFFA600
3 $FFFFA700
Device LUN
40
50
60
00
10
20
30
80
81
Device Type
SCSI Common Command Set
(CCS), which may be any of these:
- Fixed direct access
- Removable flexible direct access
(TEAC style)
- CD-ROM
- Sequential access
Local floppy drive
Local floppy drive
D http://www.motorola.com/computer/literature D-3
D
Disk/Tape Controller Data
MVME328 -- 14 Devices
Controller LUN
6
Address
$FFFF9000
7
16
17
18
$FFFF9800
$FFFF4800
$FFFF5800
$FFFF7000
Device LUN
20
28
30
00
08
10
18
60
68
70
40
48
50
58
Device Type
SCSI Common Command Set
(CCS), which may be any of these:
- Removable flexible direct access
(TEAC style)
- CD-ROM
- Sequential access
Same as above, but these will only be available if the daughter card for the second
SCSI channel is present.
19 $FFFF7800
MVME350 -- 1 Device
Controller LUN
4
5
Address
$FFFF5000
$FFFF5100
Device LUN
0
Device Type
QIC-02 streaming tape drive
D-4 Computer Group Literature Center Web Site
IOT Command Parameters
IOT Command Parameters
The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328 and MVME162P2.
IOT Parameter
Floppy Types and Formats
DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT
Sector Size
0- 128 1- 256 2- 512
3-1024 4-2048 5-4096 =
Block Size:
0- 128 1- 256 2- 512
3-1024 4-2048 5-4096 =
Sectors/Track
Number of Heads =
Number of Cylinders =
Precomp. Cylinder =
Reduced Write Current
Cylinder =
Step Rate Code =
Single/Double DATA
Density =
Single/Double TRACK
Density =
Single/Equal_in_all Track
Zero Density =
1
1
10
2
50
50
50
0
D
D
S
2
2
28
1
8
28
28
0
D
D
E
2
1
9
2
28
28
28
0
D
D
E
2
0
D
D
E
Slow/Fast Data Rate =
Other Characteristics
S S S S
Number of Physical Sectors
Number of Logical Blocks
(100 in size)
0A00
09F8
0280
0500
02D0
05A0
05A0
0B40
Number of Bytes in Decimal 653312 327680 368460
Media Size/Density 5.25/DD 5.25/DD 5.25/DD
737280
3.5/DD
Notes
1. All numerical parameters are in hexadecimal unless otherwise noted.
2. The DSDD5 type floppy is the default setting for the debugger.
1
9
2
50
50
50
2
2
50
1
F
50
50
0
D
D
E
F
0960
12C0
PS2
2
1
12
2
50
50
50
0
D
D
E
F
0B40
1680
SHD
2
0
D
D
E
F
1680
2D00
1228800 1474560 2949120
5.25/HD 3.5/HD 3.5/ED
1
24
2
50
50
50
D http://www.motorola.com/computer/literature D-5
D
Disk/Tape Controller Data
D-6 Computer Group Literature Center Web Site
E
Related Documentation
E
MCG Documents
The Motorola Computer Group publications listed below are referenced in this manual. You can obtain paper or electronic copies of MCG publications by:
❏ Contacting your local Motorola sales office
❏ Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature
..
Table E-1. Motorola Computer Group Documents
Document Title
Motorola
Publication Number
V1X2P2A/PG MVME1X2P2 VME Embedded Controller Programmer’s
Reference Guide
MVME162Bug Diagnostics User's Manual
Debugging Package for Motorola 68K CISC CPUs User’s
Manual (Parts 1 and 2)
Single Board Computers SCSI Software User’s Manual
V162DIAA/UM
68KBUG1/D
68KBUG2/D
SBCSCSI/D
To locate and view the most up-to-date product information in PDF or
HTML format, visit http://www.motorola.com/computer/literature .
E-1
E
Related Documentation
Manufacturers’ Documents
For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
Table E-2. Manufacturers’ Documents
Document Title and Source
Publication
Number
M68000FR
M68040UM
M68000 Family Reference Manual
MC68040 Microprocessor User’s Manual
Literature Distribution Center for Motorola
Telephone: 1-800- 441-2447
FAX: (602) 994-6430 or (303) 675-2150
E-mail: [email protected]
Web: http://www.mot.com/SPS
82596CA Local Area Network Coprocessor Data Sheet
82596CA Local Area Network Coprocessor User’s Manual
28F016SA Flash Memory Data Sheet
Intel Corporation
Web: http://developer.intel.com/design
SYM 53C710 (was NCR 53C710) SCSI I/O Processor Data Manual
SYM 53C710 (was NCR 53C710) SCSI I/O Processor Programmer’s Guide
Symbios Logic Inc.
1731 Technology Drive, Suite 600
San Jose, CA 95110
NCR Managed Services Center — Telephone: 1-800-262-7782
Web: http://www.lsilogic.com/products/symbios
M48T58(B) TIMEKEEPER
™
and 8K x 8 Zeropower
™
RAM Data Sheet
SGS-Thomson Microelectronics Group
Marketing Headquarters (or nearest Sales Office)
1000 East Bell Road
Phoenix, Arizona 85022
Telephone: (602) 867-6100
Web: http://www.st.com/stonline/books
290218
296853
209435
NCR53C710DM
NCR53C710PG
M48T58
E-2 Computer Group Literature Center Web Site
Related Specifications
Table E-2. Manufacturers’ Documents (Continued)
Document Title and Source
Publication
Number
Z85230pb.pdf
Z85230 Serial Communications Controller Product Brief
Zilog Inc.
210 Hacienda Avenue
Campbell, CA 95008-6609
Web: http://www.zilog.com/products
E
Related Specifications
For additional information, refer to the following table for manufacturers’ data sheets or user’s manuals. As a further help, sources for the listed documents are also provided. Please note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
Table E-3. Related Specifications
Document Title and Source
Publication
Number
ANSI/VITA 1-1994 VME64 Specification
VITA (VMEbus International Trade Association )
7825 E. Gelding Drive, Suite 104
Scottsdale, AZ 85260
Telephone: (602) 951-8866
Web: http://www.vita.com
NOTE: An earlier version of the VME specification is available as:
Versatile Backplane Bus: VMEbus
Institute of Electrical and Electronics Engineers, Inc.
Publication and Sales Department
345 East 47th Street
New York, New York 10017-21633
Telephone: 1-800-678-4333
ANSI/IEEE
Standard 1014-1987 http://www.motorola.com/computer/literature E-3
E
Related Documentation
Table E-3. Related Specifications (Continued)
Document Title and Source
OR
Microprocessor system bus for 1 to 4 byte data
Bureau Central de la Commission Electrotechnique Internationale
3, rue de Varembé
Geneva, Switzerland
Publication
Number
IEC 821 BUS
ANSI Small Computer System Interface-2 (SCSI-2), Draft Document X3.131-
198X, Revision 10c
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112-5704
IndustryPack Logic Interface Specification, Revision 1.0
VITA (VMEbus International Trade Association )
7825 E. Gelding Drive, Suite 104
Scottsdale, AZ 85260
Telephone: (602) 951-8866
Web: http://www.vita.com
Interface Between Data Terminal Equipment and Data Circuit-Terminating
Equipment Employing Serial Binary Data Interchange (EIA-232-D)
Global Engineering Documents
Suite 400
1991 M Street, NW
Washington, DC 20036
Telephone: 1-800-854-7179
Telephone: (303) 397-7956
X3.131-198X Rev.
10c
ANSI/VITA 4-1995
ANSI/EIA-232-D
Standard
E-4 Computer Group Literature Center Web Site
Index
Numerics
162Bug disk/tape controller data
firmware
implementation
network controller data
overview
27C040 EPROM
53C710 SCSI controller
A abort process
ABORT switch
aborting program execution
address ranges, EPROM
address/data configurations
addressing modes
altitude (operating)
ambient air temperature (effect on cooling)
arguments, firmware command
autojumpering (VME backplane)
B backplane jumpers
backward compatibility
batteries
baud rate, default
BBRAM (battery-backed-up RAM) and clock
block diagram
board
dimensions
features
installation
preparation
storage, preparation for
booting the system
,
BREAK key
break process
C
cables, I/O ports
cache memory
CISC embedded controller(s)
command identifier, firmware 3-5 command line input 3-5
commands, firmware
CNFG (Configure Board Information
ENV (Set Bug/Operating System
Environment)
IN-1
I
N
D
E
X
Index conductive chassis rails (EMC compliance)
configurable items, MVME162P2 board
configuration switches
S3 (MC2 DRAM size)
S4 (as software-readable switch)
S4 (EPROM/Flash selection)
,
S5 (Flash Write Enable mode)
,
,
S5 (IP DMA snoop control)
S5 (IP reset mode)
,
configuration switches, location of
Configure Board Information Block (CNFG) firmware command
configuring
162Bug parameters
IP base addresses
VMEbus interface
connector pin assignments
IndustryPack (IP)
control/status registers
controller LUN (CLUN)
,
controller modules (disk/tape)
controller modules (network) C-1
cooling requirements
CSR bit IP32 (IP bus clock)
D data bus structure, MVME162P2
data circuit-terminating equipment (DCE)
data sheets
date and time, setting
DCE (data circuit-terminating equipment)
debugger
firmware (162Bug)
prompt
device LUN (DLUN)
,
diagnostic facilities
dimensions, base board
direct memory access (DMA) 4-13
directories, switching
disk/tape controller modules supported
DLUN (device LUN)
,
DMA (direct memory access) 4-13
DRAM (dynamic RAM) base address
options
E
EIA-232-D ports
EMC regulatory compliance
ENV command parameters
environmental parameters
address ranges
sockets
,
EPROM/Flash selection
ESD (electrostatic discharge), precautions
ESDI Winchester hard drive
Ethernet
controller modules supported C-1
signals
IN-2 Computer Group Literature Center Web Site
F features, hardware
firmware
Flash memory
,
write-protect header (J16)
,
flexible diskettes (controller data)
floppy diskettes
floppy drives (disk/tape controller)
forced air cooling
front panel switches and indicators
functional description
fuses, solid-state
G
GCSR (global control/status registers)
general-purpose readable switch (S4)
global control/status registers (GCSR)
grounding
H handshaking, hardware
hard disk drive
hardware features
initialization
preparation
high-temperature operation
humidity, relative
I
I/O interfaces
IACK* (interrupt acknowledge) signal
indicators, front panel
IndustryPack (IP)
bus strobe select header (J11) 1-7 ,
interface functions
IP1/IP2 reset mode
signals
IndustryPack modules base addresses of
configuration
configuring
general control register
initial conditions
installation considerations
interconnect signals
interrupt acknowledge signal (IACK*)
interrupt control registers
Interrupt Stack Pointer (ISP)
interrupts, hardware
IOT command parameters
IP (IndustryPack)
IP2 interface function
IP32 CSR bit (IP bus clock) 1-9
ISP (Interrupt Stack Pointer)
J
J2 connector
jumper headers
J1 (system controller selection) 1-7 ,
J12 (SCSI termination)
,
J13 (IP bus clock)
J14 (SRAM backup power) 1-10 , 2-6
J16 (Flash memory write protection)
,
J20 (EPROM/Flash configuration)
http://www.motorola.com/computer/literature IN-3
I
N
D
E
X
I
N
D
E
X
Index
jumper headers, location of 1-5
jumpers, backplane
L
LAN
controller modules supported C-1
interface
LEDs (light-emitting diodes)
local bus
bus arbiter
bus timeout
resources for the processor 4-15
Local Area Network (LAN) interface 4-14
location monitors, processor
logical unit number (LUN) (see CLUN or
LUN (logical unit number) (see CLUN or
M mapping, EPROM/Flash
MC68040 or MC68LC040 cache memory
MPU
MCECC memory model
memory controller emulations (MC1/MC2)
memory requirements
microprocessor options
modifying switch settings 1-16 ,
MPU options
MVME162Bug documentation
MVME162P2 as network controller
board specifications
cooling requirements
EMC regulatory compliance
features
I/O interfaces
installation
regulatory compliance
MVME320 disk/tape controllers
MVME323 disk/tape controller
MVME327A disk/tape controller D-3
MVME328 disk/tape controller
MVME350 controller
MVME374 network controller
MVME376 network controller
N network boot process
network controller modules
non-volatile RAM (NVRAM)
no-VMEbus-interface option
,
O operating parameters
operating temperature
option fields, in firmware command
P
Petra ASIC control of Flash access time
MCECC function
SCSI controller support
pin assignments, connector
port number(s)
power requirements
powering up the board
power-save mode
preparing the board
processor
cache memory
IN-4 Computer Group Literature Center Web Site
programmable tick timers
Q
QIC-02 streaming tape drive
R regulatory compliance
related specifications
relative humidity
remote control/status connector (J2) 4-18
,
RESET switch
resetting the system
minimizing
ROMboot process
S
SCC (serial communications controller)
SCSI common command set (CCS) devices
controller (53C710)
direct access devices
interface
sequential access devices
signals
termination
terminator configuration
SD command
SDRAM (shared DRAM) options
sequential access devices
serial communication parameters
communications controller (SCC)
communications interface
ports
Set Bug/Operating System Environment
setting date and time
,
shielded cables
size of base board
slave address decoders, VMEbus 3-16
snoop control
software-programmable hardware interrupts
software-readable switch (S4) 1-16
specifications
MVME162P2
related
SRAM (static RAM) backup power source selection (J14)
battery options
options
startup overview
static variable space (firmware) 3-4
storage temperature
streaming tape drive
switch settings, modifying
switches, configuration
S3 (MC2 DRAM size)
S4 (EPROM/Flash selection)
S5 (Flash Write Enable mode)
S5 (IP DMA snoop control)
S5 (IP reset mode)
switches, front panel
switching directories
system considerations
controller function
controller jumper (J1)
reset
System Fail (SYSFAIL*) signal
http://www.motorola.com/computer/literature IN-5
I
N
D
E
X
Index
I
N
D
E
X
T temperature operating
storage
terminal configuration
input/output control
tick timers
timeout
local bus
troubleshooting procedures B-1
U
user-configurable switches 1-15 ,
,
V vibration tolerance (operating)
VMEbus
interface
signals
VMEchip2 ASIC
W watchdog timers
Winchester hard drive
X
XON/XOFF handshaking
Z
Z85230 serial communications controller
(SCC)
IN-6 Computer Group Literature Center Web Site
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