Broadcom BCM81724 Product Brief Specification

Below you will find brief information for BCM81724. This single-chip PHY supports 8x56-Gb/s PAM-4 to 16x25-Gb/s NRZ reverse gearbox, enabling high-density line-card applications from 1G to 400G. Its features include forward error correction, integrated AC-coupling capacitors, and eye monitoring per lane, making it suitable for ASIC-to-module and line-card interfaces.

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BCM81724 Reverse Gearbox Product Brief | AI Chat & PDF Download | Manualzz

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Key features

  • 8x56-Gb/s PAM-4 to 16x25-Gb/s NRZ reverse gearbox

  • Supports PAM-4 and NRZ data formats

  • Retimer, Forward, and Reverse Gearbox modes

  • Supports 1G to 400G line-card applications

  • Forward error correction (FEC)

  • Eye monitoring per lane

  • Low-power 16-nm CMOS design

Frequently asked questions

The BCM81724 supports both PAM-4 and NRZ data formats.

The BCM81724 supports Retimer, Forward, and Reverse Gearbox modes.

The BCM81724 is suitable for ASIC-to-module interfaces and high-density line-card applications from 1G to 400G.

On-chip clock synthesis is performed by a low-cost 156.25-MHz reference clock by high-frequency, low-jitter phase-locked loops (PLLs).

The BCM81724 is available in a 19 mm × 19 mm, 0.8-mm pitch, 484-ball BGA, RoHS-compliant package.

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