Compaq Deskpro EN Series Technical Reference Manual
Mainos
Mainos
Technical Reference Guide
For
Compaq Deskpro Personal Computers
Covers Deskpro EN and Deskpro Workstation AP230 Models Featuring
Intel Celeron and Pentium III Processors
And the
Intel 815E Chipset
This document is designed to fit into a standard 3-ring binder. Provided below is a title block that can be copied and/or cut out and placed into a slip or taped onto the edge of the binder.
Deskpro Personal Computers
Featuring Intel Celeron and Pentium III Processors and the Intel 815E Chipset
TRG
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Technical Reference Guide
NOTICE
The information in this document is subject to change without notice.
COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR
EDITORIAL ERRORS OR OMISSIONS HEREIN; NOR FOR INCIDENTAL OR
CONSEQUENTIAL DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE,
OR USE OF THIS MATERIAL. IT IS THE RESPONSIBILITY OF MANUFACTURERS TO
ENSURE THAT DEVICES DESIGNED TO BE USED WITH COMPAQ PRODUCTS
COMPLY WITH FCC CLASS B EMISSIONS REQUIREMENTS.
This guide contains information protected by copyright. Except for use in connection with the described Compaq product, no part of this document may be photocopied or reproduced in any form without prior written consent from Compaq Computer Corporation.
2000 Compaq Computer Corporation
All rights reserved. Published in the USA
Compaq, Deskpro, LTE, Contura, Presario, ProLinea
Registered U.S. Patent and Trademark Office
Product names mentioned in this document may be trademarks and/or registered trademarks of other companies.
“Celeron,” “Pentium” and “MMX” are registered trademarks of Intel Corporation.
“Microsoft,” “MS-DOS,” “Windows,” and “Windows NT” are registered trademarks of Microsoft Corporation.
For more information regarding specifications and Compaq-specific parts please contact Compaq
Computer Corporation.
Technical Reference Guide for
Compaq Deskpro Personal Computers
First Edition - July 2000
Second Edition – September 2000
Third Edition – April 2001
Document Number 12YJ-0700C-WWEN
Compaq Deskpro Personal Computers
Third Edition - April 2001 i
Technical Reference Guide ii Compaq Deskpro Personal Computers
Third Edition –- April 2001
Technical Reference Guide
TABLE OF CONTENTS
CHAPTER 1 INTRODUCTION....................................................................................................................
1.1
ABOUT THIS GUIDE ..................................................................................................................1-1
1.1.1
ONLINE VIEWING..............................................................................................................1-1
1.1.2
HARDCOPY ..........................................................................................................................1-2
1.2
ADDITIONAL INFORMATION SOURCES ..............................................................................1-2
1.3
MODEL NUMBERING CONVENTION....................................................................................1-2
1.4
SERIAL NUMBER ......................................................................................................................1-2
1.5
NOTATIONAL CONVENTIONS................................................................................................1-3
1.5.1
1.5.2
VALUES ...............................................................................................................................1-3
RANGES ...............................................................................................................................1-3
1.5.3
1.5.4
REGISTER NOTATION AND USAGE ..............................................................................1-3
BIT NOTATION ...................................................................................................................1-3
1.6
COMMON ACRONYMS AND ABBREVIATIONS ..................................................................1-4
CHAPTER 2 SYSTEM OVERVIEW............................................................................................................
2.1
INTRODUCTION .........................................................................................................................2-1
2.2
FEATURES AND OPTIONS .......................................................................................................2-2
2.2.1
2.2.2
STANDARD FEATURES ....................................................................................................2-2
OPTIONS ..............................................................................................................................2-3
2.3
MECHANICAL DESIGN .............................................................................................................2-4
2.3.1
CABINET LAYOUTS ..........................................................................................................2-5
2.3.2
2.3.3
CHASSIS LAYOUTS ...........................................................................................................2-7
BOARD LAYOUTS............................................................................................................2-10
2.4
SYSTEM ARCHITECTURE ......................................................................................................2-12
2.4.1
PROCESSORS ....................................................................................................................2-14
2.4.2
2.4.3
CHIPSET .............................................................................................................................2-16
SUPPORT COMPONENTS................................................................................................2-16
2.4.4
2.4.5
2.4.6
2.4.7
2.4.8
SYSTEM MEMORY ..........................................................................................................2-17
MASS STORAGE ...............................................................................................................2-17
SERIAL AND PARALLEL INTERFACES.......................................................................2-17
UNIVERSAL SERIAL BUS INTERFACE........................................................................2-17
NETWORK INTERFACE CONTROLLER.......................................................................2-17
2.4.9
GRAPHICS SUBSYSTEM.................................................................................................2-18
2.4.10
AUDIO SUBSYSTEM........................................................................................................2-19
2.5
SPECIFICATIONS .....................................................................................................................2-19
CHAPTER 3 PROCESSOR/MEMORY SUBSYSTEM..............................................................................
3.1
INTRODUCTION .........................................................................................................................3-1
3.2
PROCESSOR ................................................................................................................................3-2
3.2.1
3.2.2
CELERON PROCESSOR.....................................................................................................3-2
PENTIUM III PROCESSOR.................................................................................................3-3
3.2.3
PROCESSOR UPGRADING................................................................................................3-4
3.3
MEMORY SUBSYSTEM.............................................................................................................3-5
3.4
SUBSYSTEM CONFIGURATION..............................................................................................3-8
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CHAPTER 4 SYSTEM SUPPORT................................................................................................................
4.1
INTRODUCTION .........................................................................................................................4-1
4.2
PCI BUS OVERVIEW ..................................................................................................................4-2
4.2.1
4.2.2
4.2.3
4.2.4
PCI BUS TRANSACTIONS.................................................................................................4-3
PCI BUS MASTER ARBITRATION...................................................................................4-6
OPTION ROM MAPPING ...................................................................................................4-7
PCI INTERRUPTS................................................................................................................4-7
4.2.5
4.2.6
4.2.7
4.2.8
PCI POWER MANAGEMENT SUPPORT .........................................................................4-7
PCI SUB-BUSSES ................................................................................................................4-7
PCI CONFIGURATION .......................................................................................................4-8
PCI CONNECTOR................................................................................................................4-9
4.3
AGP BUS OVERVIEW ..............................................................................................................4-10
4.3.1
4.3.2
BUS TRANSACTIONS ......................................................................................................4-10
AGP CONFIGURATION ...................................................................................................4-13
4.3.3
AGP CONNECTOR............................................................................................................4-14
4.4
SYSTEM RESOURCES .............................................................................................................4-15
4.4.1
4.4.2
INTERRUPTS .....................................................................................................................4-15
DIRECT MEMORY ACCESS............................................................................................4-19
4.5
SYSTEM CLOCK DISTRIBUTION..........................................................................................4-22
4.6
REAL-TIME CLOCK AND CONFIGURATION MEMORY ..................................................4-23
4.6.1
4.6.2
CLEARING CMOS.............................................................................................................4-23
CMOS ARCHIVE AND RESTORE...................................................................................4-24
4.6.3
STANDARD CMOS LOCATIONS ...................................................................................4-24
4.7
SYSTEM MANAGEMENT........................................................................................................4-33
4.7.1
SECURITY FUNCTIONS ..................................................................................................4-33
4.7.2
4.7.3
POWER MANAGEMENT .................................................................................................4-35
SYSTEM STATUS .............................................................................................................4-35
4.7.4
THERMAL SENSING AND COOLING ...........................................................................4-36
4.8
REGISTER MAP AND MISCELLANEOUS FUNCTIONS .....................................................4-38
4.8.1
4.8.2
4.8.3
SYSTEM I/O MAP .............................................................................................................4-38
82801 ICH2 GENERAL PURPOSE FUNCTIONS............................................................4-39
LPC47B357 I/O CONTROLLER FUNCTIONS................................................................4-40
CHAPTER 5 INPUT/OUTPUT INTERFACES...........................................................................................
5.1
INTRODUCTION .........................................................................................................................5-1
5.2
ENHANCED IDE INTERFACE...................................................................................................5-1
5.2.1
5.2.2
IDE PROGRAMMING .........................................................................................................5-1
IDE CONNECTOR ...............................................................................................................5-3
5.3
DISKETTE DRIVE INTERFACE ................................................................................................5-4
5.3.1
DISKETTE DRIVE PROGRAMMING ...............................................................................5-5
5.3.2
DISKETTE DRIVE CONNECTOR .....................................................................................5-7
5.4
SERIAL INTERFACE ..................................................................................................................5-8
5.4.1
5.4.2
RS-232 INTERFACE ............................................................................................................5-8
COM1 PORT HEADER........................................................................................................5-9
5.4.3
SERIAL INTERFACE PROGRAMMING...........................................................................5-9
5.5
PARALLEL INTERFACE..........................................................................................................5-11
5.5.1
STANDARD PARALLEL PORT MODE ..........................................................................5-11
5.5.2
5.5.3
5.5.4
5.5.5
ENHANCED PARALLEL PORT MODE..........................................................................5-12
EXTENDED CAPABILITIES PORT MODE ....................................................................5-12
PARALLEL INTERFACE PROGRAMMING ..................................................................5-13
PARALLEL INTERFACE CONNECTOR ........................................................................5-15 iv Compaq Deskpro Personal Computers
Third Edition –- April 2001
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5.6
KEYBOARD/POINTING DEVICE INTERFACE ....................................................................5-16
5.6.1
KEYBOARD INTERFACE OPERATION ........................................................................5-16
5.6.2
5.6.3
POINTING DEVICE INTERFACE OPERATION ............................................................5-18
KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING............................5-18
5.6.4
KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR...................................5-21
5.7
UNIVERSAL SERIAL BUS INTERFACE................................................................................5-22
5.7.1
5.7.2
USB DATA FORMATS .....................................................................................................5-22
USB PROGRAMMING ......................................................................................................5-24
5.7.3
5.7.4
USB CONNECTOR ............................................................................................................5-25
USB CABLE DATA ...........................................................................................................5-25
5.8
AUDIO SUBSYSTEM................................................................................................................5-26
5.8.1
FUNCTIONAL ANALYSIS...............................................................................................5-26
5.8.2
AC97 AUDIO CONTROLLER ..........................................................................................5-28
5.8.3
5.8.4
5.8.5
5.8.6
AC97 LINK BUS ................................................................................................................5-28
AUDIO CODEC..................................................................................................................5-29
AUDIO PROGRAMMING.................................................................................................5-30
AUDIO SPECIFICATIONS................................................................................................5-31
5.9
NETWORK INTERFACE CONTROLLER...............................................................................5-32
5.9.1
WAKE ON LAN SUPPORT...............................................................................................5-33
5.9.2
5.9.3
ALERT ON LAN SUPPORT..............................................................................................5-33
POWER MANAGEMENT SUPPORT...............................................................................5-34
5.9.4
5.9.5
5.9.6
5.9.7
NIC PROGRAMMING.......................................................................................................5-35
NIC CONNECTOR .............................................................................................................5-36
NIC SPECIFICATIONS......................................................................................................5-36
NIC UPGRADING/CHANGING .......................................................................................5-37
CHAPTER 6 EMBEDDED GRAPHICS SUBSYSTEM .............................................................................
6.1
INTRODUCTION .........................................................................................................................6-1
6.2
INTEL 815E-BASED GRAPHICS SUBSYSTEM.......................................................................6-2
6.2.1
FUNCTIONAL DESCRIPTION...........................................................................................6-2
6.2.2
6.2.3
6.2.4
6.2.5
DISPLAY MODES ...............................................................................................................6-4
MEMORY MANAGEMENT ...............................................................................................6-4
815E-BASED GRAPHICS PROGRAMMING ....................................................................6-5
UPGRADING 815E-BASED GRAPHICS ...........................................................................6-5
6.3
NVIDIA GRAPHICS SUBSYSTEM............................................................................................6-6
6.3.1
DISPLAY MODES ...............................................................................................................6-7
6.3.2
6.3.3
NVIDIA GRAPHICS PROGRAMMING.............................................................................6-7
NVIDIA GRAPHICS UPGRADING....................................................................................6-7
6.4
MONITOR POWER MANAGEMENT CONTROL....................................................................6-8
6.5
MONITOR CONNECTOR ...........................................................................................................6-8
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CHAPTER 7 POWER SUPPLY AND DISTRIBUTION............................................................................
7.1
INTRODUCTION .........................................................................................................................7-1
7.1
POWER SUPPLY ASSEMBLY/CONTROL ...............................................................................7-1
7.1.1
7.1.1
POWER SUPPLY ASSEMBLY ...........................................................................................7-2
POWER CONTROL .............................................................................................................7-3
7.1
POWER DISTRIBUTION ............................................................................................................7-5
7.1.1
3.3/5/12 VDC DISTRIBUTION ...........................................................................................7-5
7.1.1
LOW VOLTAGE DISTRIBUTION .....................................................................................7-7
7.1
SIGNAL DISTRIBUTION............................................................................................................7-8
CHAPTER 8 BIOS ROM ...............................................................................................................................
8.1
INTRODUCTION .........................................................................................................................8-1
8.2
ROM FLASHING .........................................................................................................................8-2
8.2.1
UPGRADING........................................................................................................................8-2
8.2.2
CHANGEABLE SPLASH SCREEN....................................................................................8-3
8.3
BOOT FUNCTIONS .....................................................................................................................8-4
8.3.1
8.3.2
8.3.3
8.3.4
BOOT DEVICE ORDER ......................................................................................................8-4
NETWORK BOOT (F12) SUPPORT...................................................................................8-4
MEMORY DETECTION AND CONFIGURATION ..........................................................8-5
BOOT ERROR CODES........................................................................................................8-5
8.4
SETUP UTILITY ..........................................................................................................................8-6
8.5
CLIENT MANAGEMENT FUNCTIONS..................................................................................8-12
8.5.1
8.5.2
8.5.3
SYSTEM ID AND ROM TYPE .........................................................................................8-14
EDID RETRIEVE ...............................................................................................................8-14
TEMPERATURE STATUS ................................................................................................8-14
8.5.4
DRIVE FAULT PREDICTION ..........................................................................................8-15
8.6
PNP SUPPORT ...........................................................................................................................8-15
8.6.1
SMBIOS ..............................................................................................................................8-16
8.7
POWER MANAGEMENT FUNCTIONS..................................................................................8-17
8.7.1
8.7.2
INDEPENDENT PM SUPPORT ........................................................................................8-17
ACPI SUPPORT..................................................................................................................8-19
8.7.3
APM 1.2 SUPPORT ............................................................................................................8-19
8.8
USB LEGACY SUPPORT..........................................................................................................8-23
A.
APPENDIX A ERROR MESSAGES AND CODES ............................................................................
A.1
INTRODUCTION ........................................................................................................................ A-1
A.2
BEEP/KEYBOARD LED CODES .............................................................................................. A-1
A.3
POWER-ON SELF TEST (POST) MESSAGES......................................................................... A-2
A.4
SYSTEM ERROR MESSAGES (1 XX XX ) .................................................................................. A-3
A.5
MEMORY ERROR MESSAGES (2 XX XX )................................................................................ A-4
A.6
KEYBOARD ERROR MESSAGES (30 X XX )............................................................................ A-4
A.7
PRINTER ERROR MESSAGES (4 XX XX ) ................................................................................. A-5
A.8
VIDEO (GRAPHICS) ERROR MESSAGES (5 XX XX ).............................................................. A-5
A.9
DISKETTE DRIVE ERROR MESSAGES (6 XX XX ) ................................................................. A-6
A.10
A.11
A.12
SERIAL INTERFACE ERROR MESSAGES (11
SYSTEM STATUS ERROR MESSAGES (16 XX -
XX
XX
XX )....................................................... A-6
MODEM COMMUNICATIONS ERROR MESSAGES (12 XX XX ) ...................................... A-7
)............................................................ A-8
A.13
A.14
HARD DRIVE ERROR MESSAGES (17 XX XX ) ................................................................... A-8
HARD DRIVE ERROR MESSAGES (19 XX XX ) ................................................................... A-9 vi Compaq Deskpro Personal Computers
Third Edition –- April 2001
Technical Reference Guide
A.15
A.16
A.17
A.18
A.19
A.20
VIDEO (GRAPHICS) ERROR MESSAGES (24 XX XX )........................................................ A-9
AUDIO ERROR MESSAGES (3206XX ).............................................................................. A-10
DVD/CD-ROM ERROR MESSAGES (33 XX XX )................................................................ A-10
NETWORK INTERFACE ERROR MESSAGES (60 XX XX )............................................... A-10
SCSI INTERFACE ERROR MESSAGES (65 XX XX , 66 XX XX , 67 XX XX )......................... A-11
POINTING DEVICE INTERFACE ERROR MESSAGES (8601XX )................................. A-11
APPENDIX B ASCII CHARACTER SET ...................................................................................................
B.1
INTRODUCTION ........................................................................................................................ B-1
APPENDIX C KEYBOARD...........................................................................................................................
C.1
INTRODUCTION ........................................................................................................................ C-1
C.2
KEYSTROKE PROCESSING ..................................................................................................... C-2
C.2.1
C.2.2
C.2.3
C.2.4
PS/2-TYPE KEYBOARD TRANSMISSIONS ................................................................... C-3
USB-TYPE KEYBOARD TRANSMISSIONS ................................................................... C-4
KEYBOARD LAYOUTS .................................................................................................... C-5
KEYS.................................................................................................................................... C-8
C.2.5
C.2.6
KEYBOARD COMMANDS ............................................................................................. C-11
SCAN CODES ................................................................................................................... C-11
C.3
CONNECTORS.......................................................................................................................... C-16
APPENDIX D COMPAQ/NVIDIA TNT2 PRO AGP GRAPHICS CARD...............................................
D.1
INTRODUCTION ........................................................................................................................ D-1
D.2
FUNCTIONAL DESCRIPTION.................................................................................................. D-2
D.3
DISPLAY MODES ...................................................................................................................... D-3
D.4
SOFTWARE SUPPORT INFORMATION ................................................................................. D-4
D.5
POWER MANAGEMENT AND CONSUMPTION................................................................... D-4
D.6
CONNECTORS............................................................................................................................ D-5
D.6.1
MONITOR CONNECTOR .................................................................................................. D-5
APPENDIX E COMPAQ/NVIDIA QUADRO2 AGP GRAPHICS CARDS.............................................
E.1
INTRODUCTION ........................................................................................................................ E-1
E.2
FUNCTIONAL DESCRIPTION.................................................................................................. E-2
E.3
DISPLAY MODES ...................................................................................................................... E-3
E.4
SOFTWARE SUPPORT INFORMATION ................................................................................. E-4
E.5
POWER MANAGEMENT AND CONSUMPTION................................................................... E-4
E.6
CONNECTORS............................................................................................................................ E-5
E.6.1
MONITOR CONNECTOR E-5
Compaq Deskpro Personal Computers
Third Edition - April 2001 vii
Technical Reference Guide
APPENDIX F COMPAQ/MATROX MILLENNIUM AGP GRAPHICS CARDS..................................
F.1
INTRODUCTION .........................................................................................................................F-1
F.2
FUNCTIONAL DESCRIPTION...................................................................................................F-2
F.3
DISPLAY MODES .......................................................................................................................F-3
F.4
SOFTWARE SUPPORT INFORMATION ..................................................................................F-4
F.5
POWER MANAGEMENT AND CONSUMPTION....................................................................F-4
F.6
CONNECTORS.............................................................................................................................F-5
F.6.1
MONITOR CONNECTOR F-5
APPENDIX G COMPAQ/ADAPTEC SCSI HOST ADAPTER ..............................................................
G.1
INTRODUCTION ...................................................................................................................... G-1
G.2
FUNCTIONAL DESCRIPTION................................................................................................ G-2
G.3
SCSI ADAPTER PROGRAMMING......................................................................................... G-3
G.3.1
G.3.2
SCSI ADAPTER CONFIGURATION .............................................................................. G-3
SCSI ADAPTER CONTROL ............................................................................................G-3
G.4
SPECIFICATIONS .................................................................................................................... G-3
G.5
SCSI CONNECTORS ................................................................................................................ G-4
G.5.1
G.5.2
EXTERNAL 50-PIN ULTRA SCSI CONNECTOR ......................................................... G-4
INTERNAL 50-PIN ULTRA SCSI CONNECTOR .......................................................... G-5
G.5.3
INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR G-6 viii Compaq Deskpro Personal Computers
Third Edition –- April 2001
Technical Reference Guide
LIST OF FIGURES
F IGURE 2–1. C OMPAQ D ESKPRO P ERSONAL C OMPUTERS WITH M ONITORS ................................................2-1
F IGURE 2–2. C OMPAQ D ESKPROS , F RONT V IEWS ........................................................................................2-5
F IGURE 2–3. C OMPAQ D ESKPROS , R EAR V IEWS ..........................................................................................2-6
F IGURE 2–4. S MALL F ORM F ACTOR C HASSIS L AYOUT , T OP V IEW .............................................................2-7
F IGURE 2–5. S LIM D ESKTOP C HASSIS L AYOUT , T OP V IEW .........................................................................2-8
F IGURE 2–6. C ONFIGURABLE M INITOWER C HASSIS L AYOUT , L EFT S IDE V IEW (M INITOWER
CONFIGURATION )....................................................................................................................................2-9
F IGURE 2–7.
S MALL F ORM F ACTOR B OARD L AYOUTS .............................................................................2-10
F IGURE 2–8.
S LIM D ESKTOP OR C ONFIGURABLE M INITOWER S YSTEM B OARD L AYOUT .........................2-11
F IGURE 2–9. C OMPAQ D ESKPRO A RCHITECTURE , B LOCK DIAGRAM ..........................................................2-13
F IGURE 2–10. P ROCESSOR A SSEMBLY A ND M OUNTING ............................................................................2-14
F IGURE 3–1. P ROCESSOR /M EMORY S UBSYSTEM A RCHITECTURE ...............................................................3-1
F IGURE 3–2. C ELERON P ROCESSOR I NTERNAL A RCHITECTURE ..................................................................3-2
F IGURE 3–3. P ENTIUM III P ROCESSOR I NTERNAL A RCHITECTURE ..............................................................3-3
F IGURE 3–4. S YSTEM M EMORY M AP ...........................................................................................................3-7
F IGURE 4-1. PCI B US D EVICES AND F UNCTIONS ..........................................................................................4-2
F IGURE 4-2. C ONFIGURATION C YCLE ..........................................................................................................4-4
F IGURE 4-3. PCI C ONFIGURATION S PACE M APPING ....................................................................................4-5
F IGURE 4-4. PCI B US C ONNECTOR (32-B IT T YPE ) ......................................................................................4-9
F IGURE 4-5. AGP 1X D ATA T RANSFER (P EAK T RANSFER R ATE : 266 MB/ S ) ...........................................4-11
F IGURE 4-6. AGP 2X D ATA T RANSFER (P EAK T RANSFER R ATE : 532 MB/ S ) ...........................................4-12
F IGURE 4-7. AGP 4X D ATA T RANSFER (P EAK T RANSFER R ATE : 1064 MB/ S ) .........................................4-12
F IGURE 4-8. U NIVERSAL AGP B US C ONNECTOR .......................................................................................4-14
F IGURE 4-9. M ASKABLE I NTERRUPT P ROCESSING , B LOCK D IAGRAM .......................................................4-15
F
IGURE
4-10. C
ONFIGURATION
M
EMORY
M
AP
..........................................................................................4-23
F IGURE 4-11. S MALL F ORM F ACTOR F AN C ONTROL B LOCK D IAGRAM .....................................................4-37
F IGURE 4-12. S LIM D ESKTOP /C ONFIGURABLE M INITOWER F AN C ONTROL B LOCK D IAGRAM ..................4-37
F IGURE 5-1. 40-P IN P RIMARY IDE C ONNECTOR ( ON SYSTEM BOARD ). .......................................................5-3
F IGURE 5-2. 34-P IN D ISKETTE D RIVE C ONNECTOR . ....................................................................................5-7
F IGURE 5-3. S ERIAL I NTERFACE C ONNECTOR (M ALE DB-9 AS VIEWED FROM REAR OF CHASSIS )..............5-8
F IGURE 5-4. COM1 S ERIAL I NTERFACE H EADER (S MALL F ORM F ACTOR SYSTEM BOARD ONLY )..............5-9
F IGURE 5-5. P ARALLEL I NTERFACE C ONNECTOR (F EMALE DB-25 AS VIEWED FROM REAR OF CHASSIS ) .5-15
F IGURE 5-6. 8042-T O -K EYBOARD T RANSMISSION OF C ODE ED H , T IMING D IAGRAM ..............................5-16
F IGURE 5-7. K EYBOARD OR P OINTING D EVICE I NTERFACE C ONNECTOR ..................................................5-21
F IGURE 5-8. USB I/F, B LOCK D IAGRAM ...................................................................................................5-22
F IGURE 5-9. USB P ACKET F ORMATS .........................................................................................................5-23
F IGURE 5-10. U NIVERSAL S ERIAL B US C ONNECTOR .................................................................................5-25
F IGURE 5-11. A UDIO S UBSYSTEM F UNCTIONAL B LOCK D IAGRAM ...........................................................5-27
F IGURE 5-12. AC’97 L INK B US P ROTOCOL ...............................................................................................5-28
F IGURE 5-13. AD1881 A UDIO C ODEC F UNCTIONAL B LOCK D IAGRAM ....................................................5-29
F IGURE 5-14. N ETWORK I NTERFACE C ONTROLLER B LOCK D IAGRAM ......................................................5-32
F IGURE 5-15. E THERNET TPE C ONNECTOR (RJ-45, VIEWED FROM CARD EDGE ) ......................................5-36
F IGURE 5-16. R EMOTE S YSTEM A LERT I MPLEMENTATION (G ENERIC R EPRESENTATION ).........................5-37
F IGURE 5-17. RSA L OGIC , B LOCK D IAGRAM ............................................................................................5-37
F IGURE 6-1. 815E-B ASED G RAPHICS , B LOCK DIAGRAM .............................................................................6-2
F IGURE 6-2. 82815 GMCH I NTEGRATED G RAPHICS S UBSYSTEM ..............................................................6-3
F IGURE 6-3. NVIDIA TNT2 P RO G RAPHICS S UBSYSTEM .............................................................................6-6
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Technical Reference Guide
F IGURE 7–1. P OWER D ISTRIBUTION AND C ONTROL , B LOCK D IAGRAM ......................................................7-1
F IGURE 7–2. S MALL F ORM F ACTOR P OWER C ABLE D IAGRAM ...................................................................7-5
F IGURE 7–3. S LIM D ESKTOP /C ONFIGURABLE M INITOWER P OWER C ABLE D IAGRAM .................................7-6
F IGURE 7–4. L OW V OLTAGE S UPPLY AND D ISTRIBUTION D IAGRAM ..........................................................7-7
F IGURE 7–5. S MALL F ORM F ACTOR S IGNAL D ISTRIBUTION D IAGRAM .......................................................7-8
F IGURE 7–6. S LIM D ESKTOP /C ONFIGURABLE M INITOWER S IGNAL D ISTRIBUTION D IAGRAM ...................7-9
F IGURE 7–7. H EADER P INOUTS ..................................................................................................................7-10
F IGURE B–1. ASCII C HARACTER S ET ........................................................................................................ B-1
F IGURE C–1. K EYSTROKE P ROCESSING E LEMENTS , B LOCK D IAGRAM ...................................................... C-2
F IGURE C–2. PS/2 K EYBOARD -T O -S YSTEM T RANSMISSION , T IMING D IAGRAM ....................................... C-3
F
IGURE
C–3. U.S. E
NGLISH
(101-K
EY
) K
EYBOARD
K
EY
P
OSITIONS
......................................................... C-5
F IGURE C–4. N ATIONAL (102-K EY ) K EYBOARD K EY P OSITIONS .............................................................. C-5
F IGURE C–5. U.S. E NGLISH W INDOWS (101W-K EY ) K EYBOARD K EY P OSITIONS .................................... C-6
F IGURE C–6. N ATIONAL W INDOWS (102W-K EY ) K EYBOARD K EY P OSITIONS ......................................... C-6
F IGURE C–7. 7-B UTTON E ASY A CCESS K EYBOARD L AYOUT ..................................................................... C-7
F IGURE C–8. 8-B UTTON E ASY A CCESS K EYBOARD L AYOUT ..................................................................... C-7
F IGURE C–9. PS/2 K EYBOARD C ABLE C ONNECTOR (M ALE ).................................................................... C-16
F IGURE C–10. USB K EYBOARD C ABLE C ONNECTOR (M ALE ) ................................................................. C-16
F IGURE D-1. C OMPAQ /NVIDIA TNT2 P RO AGP G RAPHICS C ARD (P/N 198998-B21) L AYOUT ............. D-1
F IGURE D-2. NVIDIA TNT2 P RO G RAPHICS C ARD B LOCK DIAGRAM ....................................................... D-2
F IGURE D-3. VGA M ONITOR C ONNECTOR , (F EMALE DB-15, AS VIEWED FROM REAR ). ............................. D-5
F IGURE E-1. C OMPAQ /NVIDIA Q UADRO 2 EX/MXR AGP G RAPHICS C ARD L AYOUT ............................. E-1
F IGURE E-2. NVIDIA Q UADRO 2 MXR G RAPHICS C ARD B LOCK DIAGRAM .............................................. E-2
F IGURE E-3. VGA M ONITOR C ONNECTOR (F EMAL DB-15, AS VIEWED FROM REAR )................................ E-2
F IGURE F-1. C OMPAQ /M ATROX M ILLIENNIUM AGP G RAPHICS C ARD L AYOUT ........................................F-1
F IGURE F-2. M ATROX M ILLENNIUM G RAPHICS C ARD B LOCK DIAGRAM ....................................................F-2
F IGURE F-3. VGA M ONITOR C ONNECTOR (F EMAL DB-15, AS VIEWED FROM REAR ) .................................F-2
F IGURE G–1. C OMPAQ /A DAPTEC 29160N SCSI H OST A DAPTER C ARD L AYOUT (PCA# 157342-001).... G-1
F IGURE G–2. C OMPAQ /A DAPTEC U LTRA SCSI A DAPTER C ARD B LOCK D IAGRAM ................................... G-2
F IGURE G–3. E XTERNAL U LTRA SCSI C ONNECTOR (50PIN )..................................................................... G-4
F IGURE G–4. I NTERNAL 50-P IN U LTRA SCSI C ONNECTOR ........................................................................ G-5
F IGURE G–5. U LTRA 160 SCSI C ONNECTOR (68-P IN H EADER T YPE )........................................................ G-6 x Compaq Deskpro Personal Computers
Third Edition –- April 2001
Technical Reference Guide
LIST OF TABLES
T ABLE 1–1. A CRONYMS AND A BBREVIATIONS ............................................................................................1-3
T ABLE 2-1. F EATURE D IFFERENCE M ATRIX ................................................................................................2-2
T ABLE 2-2. C HIPSET C OMPARISON ............................................................................................................2-16
T ABLE 2-3. S UPPORT C OMPONENT F UNCTIONS ..........................................................................................2-16
T ABLE 2-4. G RAPHICS S UBSYSTEM C OMPARISON .....................................................................................2-18
T ABLE 2-5. E NVIRONMENTAL S PECIFICATIONS .........................................................................................2-19
T ABLE 2-6. E LECTRICAL S PECIFICATIONS .................................................................................................2-19
T ABLE 2-7. P HYSICAL S PECIFICATIONS .....................................................................................................2-20
T ABLE 2-8. D ISKETTE D RIVE S PECIFICATIONS ..........................................................................................2-20
T ABLE 2-9. 48 X CD-ROM D RIVE S PECIFICATIONS ...................................................................................2-21
T ABLE 2-10. H ARD D RIVE S PECIFICATIONS ...............................................................................................2-21
T ABLE 3–1. C ELERON P ROCESSOR S TATISTICAL C OMPARISON ...................................................................3-2
T ABLE 3–2. P ENTIUM III P ROCESSOR S TATISTICAL C OMPARISON ..............................................................3-3
T ABLE 3–3. SPD A DDRESS M AP (SDRAM DIMM)......................................................................................3-6
T ABLE 3–4. H OST /PCI B RIDGE C ONFIGURATION R EGISTERS (GMCH, F UNCTION 0)..................................3-8
T ABLE 4-1. PCI D EVICE C ONFIGURATION A CCESS .....................................................................................4-4
T ABLE 4-2. S YSTEM B OARD PCI D EVICE I DENTIFICATION .........................................................................4-5
T ABLE 4-3. PCI B US M ASTERING D EVICES .................................................................................................4-6
T ABLE 4-4. LPC B RIDGE C ONFIGURATION R EGISTERS (ICH2, F UNCTION 0) ..............................................4-8
T ABLE 4-5. PCI B US C ONNECTOR P INOUT ..................................................................................................4-9
T ABLE 4-6. PCI/AGP B RIDGE C ONFIGURATION R EGISTERS (MCH, F UNCTION 1) ....................................4-13
T ABLE 4-7. AGP B US C ONNECTOR P INOUT ................................................................................................4-14
T
ABLE
4-8. M
ASKABLE
I
NTERRUPT
P
RIORITIES AND
A
SSIGNMENTS
.........................................................4-16
T ABLE 4-9. M ASKABLE I NTERRUPT C ONTROL R EGISTERS ........................................................................4-17
T ABLE 4-10. D EFAULT DMA C HANNEL A SSIGNMENTS ............................................................................4-19
T ABLE 4-11. DMA P AGE R EGISTER A DDRESSES .......................................................................................4-20
T ABLE 4-12. DMA C ONTROLLER R EGISTERS ............................................................................................4-21
T ABLE 4-13. C LOCK G ENERATION AND D ISTRIBUTION .............................................................................4-22
T ABLE 4-14. C ONFIGURATION M EMORY (CMOS) M AP ............................................................................4-24
T ABLE 4-15. S YSTEM B OOT /ROM F LASH S TATUS LED I NDICATIONS ......................................................4-35
T ABLE 4-16. S YSTEM O PERATIONAL S TATUS LED I NDICATIONS ..............................................................4-36
T ABLE 4-17. S YSTEM I/O M AP ..................................................................................................................4-38
T ABLE 4-18. 82801 ICH2 GPIO R EGISTER U TILIZATION ..........................................................................4-39
T ABLE 4-19 LPC47B357 C ONTROL R EGISTERS .........................................................................................4-40
T ABLE 4-20. LPC47B357 GPIO R EGISTER U TILIZATION ..........................................................................4-41
T ABLE 5–1. IDE PCI C ONFIGURATION R EGISTERS .....................................................................................5-2
T ABLE 5–2. IDE B US M ASTER C ONTROL R EGISTERS ..................................................................................5-2
T ABLE 5–3. 40-P IN P RIMARY IDE C ONNECTOR P INOUT .............................................................................5-3
T ABLE 5–4. D ISKETTE D RIVE C ONTROLLER C ONFIGURATION R EGISTERS ..................................................5-5
T ABLE 5–5. D ISKETTE D RIVE I NTERFACE C ONTROL R EGISTERS .................................................................5-6
T ABLE 5–6. 34-P IN D ISKETTE D RIVE C ONNECTOR P INOUT .........................................................................5-7
T ABLE 5–7. DB-9 S ERIAL C ONNECTOR P INOUT ..........................................................................................5-8
T ABLE 5–8. S ERIAL I NTERFACE C ONFIGURATION R EGISTERS .....................................................................5-9
T ABLE 5–9. S ERIAL I NTERFACE C ONTROL R EGISTERS ..............................................................................5-10
T ABLE 5–10. P ARALLEL I NTERFACE C ONFIGURATION R EGISTERS ............................................................5-13
T ABLE 5–11. P ARALLEL I NTERFACE C ONTROL R EGISTERS .......................................................................5-14
T ABLE 5–12. DB-25 P ARALLEL C ONNECTOR P INOUT ...............................................................................5-15
T ABLE 5–13. 8042-T O -K EYBOARD C OMMANDS .......................................................................................5-17
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Technical Reference Guide
T ABLE 5–14. K EYBOARD I NTERFACE C ONFIGURATION R EGISTERS ..........................................................5-18
T ABLE 5–15. CPU C OMMANDS T O T HE 8042 ...........................................................................................5-20
T ABLE 5–16. K EYBOARD /P OINTING D EVICE C ONNECTOR P INOUT ...........................................................5-21
T ABLE 5–17. USB I NTERFACE C ONFIGURATION R EGISTERS .....................................................................5-24
T ABLE 5–18. USB C ONTROL R EGISTERS ...................................................................................................5-24
T ABLE 5–19. USB C ONNECTOR P INOUT ....................................................................................................5-25
T ABLE 5–20. USB C ABLE L ENGTH D ATA .................................................................................................5-25
T ABLE 5–21. AC’97 A UDIO C ONTROLLER PCI C ONFIGURATION R EGISTERS ...........................................5-30
T ABLE 5–22. AC’97 A UDIO C ODEC C ONTROL R EGISTERS ........................................................................5-30
T ABLE 5–23. A UDIO S UBSYSTEM S PECIFICATIONS ....................................................................................5-31
T ABLE 5–24. AOL E VENTS ........................................................................................................................5-33
T ABLE 5–25. NIC C ONTROLLER PCI C ONFIGURATION R EGISTERS ..........................................................5-35
T
ABLE
5–26. NIC C
ONTROL
R
EGISTERS
....................................................................................................5-35
T ABLE 5–27. 82559 NIC O PERATING S PECIFICATIONS .............................................................................5-36
T ABLE 5–28. R EMOTE S YSTEM A LERT E VENTS .........................................................................................5-38
T ABLE 6-1. I NTEL G RAPHICS D ISPLAY M ODES ............................................................................................6-4
T ABLE 6-2. 815-B ASED G RAPHICS C ONTROLLER PCI C ONFIGURATION R EGISTERS ...................................6-5
T ABLE 6-3. NVIDIA TNT2 P RO G RAPHICS D ISPLAY M ODES ......................................................................6-7
T ABLE 6-4. M ONITOR P OWER M ANAGEMENT C ONDITIONS ........................................................................6-8
T ABLE 6-5. DB-15 M ONITOR C ONNECTOR P INOUT .....................................................................................6-8
T ABLE 8-1. B OOT B LOCK C ODES ...................................................................................................................8-2
T ABLE 8-2. B OOT E RROR C ODES ...................................................................................................................8-5
T ABLE 8-3. S ETUP U TILITY F UNCTIONS .......................................................................................................8-6
T ABLE 8-4. C LIENT M ANAGEMENT F UNCTIONS (INT15) ..........................................................................8-12
T ABLE 8-5. P N P BIOS F UNCTIONS ............................................................................................................8-15
T ABLE 8-6. APM BIOS F UNCTIONS ............................................................................................................8-20
T ABLE A–1. B EEP /K EYBOARD LED C ODES ............................................................................................... A-1
T ABLE A–2. P OWER -O N S ELF T EST (POST) M ESSAGES ............................................................................ A-2
T ABLE A–3. S YSTEM E RROR M ESSAGES .................................................................................................... A-3
T ABLE A–4. M EMORY E RROR M ESSAGES .................................................................................................. A-4
T ABLE A–5. K EYBOARD E RROR M ESSAGES ............................................................................................... A-4
T ABLE A–6. P RINTER E RROR M ESSAGES .................................................................................................... A-5
T ABLE A–7. V IDEO (G RAPHICS ) E RROR M ESSAGES ................................................................................... A-5
T ABLE A–8. D ISKETTE D RIVE E RROR M ESSAGES ...................................................................................... A-6
T ABLE A–9. S ERIAL I NTERFACE E RROR M ESSAGES ................................................................................... A-6
T ABLE A–10. S ERIAL I NTERFACE E RROR M ESSAGES ................................................................................. A-7
T ABLE A–11. S YSTEM S TATUS E RROR M ESSAGES ..................................................................................... A-8
T ABLE A–12. H ARD D RIVE E RROR M ESSAGES ........................................................................................... A-8
T ABLE A–13. H ARD D RIVE E RROR M ESSAGES ........................................................................................... A-9
T ABLE A–14. H ARD D RIVE M ESSAGES ....................................................................................................... A-9
T ABLE A–15. A UDIO E RROR M ESSAGES ................................................................................................... A-10
T ABLE A–16. DVD/CD-ROM D RIVE E RROR M ESSAGES ........................................................................ A-10
T ABLE A–17. N ETWORK I NTERFACE E RROR M ESSAGES .......................................................................... A-10
T ABLE A–18. SCSI I NTERFACE E RROR M ESSAGES .................................................................................. A-11
T
ABLE
A–19. P
OINTING
D
EVICE
I
NTERFACE
E
RROR
M
ESSAGES
.............................................................. A-11
T ABLE C–1. K EYBOARD TO -S YSTEM C OMMANDS ................................................................................... C-11
T ABLE C–2. K EYBOARD S CAN C ODES ...................................................................................................... C-12
T ABLE D-1. NVIDIA TNT2 P RO G RAPHICS D ISPLAY M ODES ................................................................... D-3
T ABLE D-2. M ONITOR P OWER M ANAGEMENT C ONDITIONS ...................................................................... D-4 xii Compaq Deskpro Personal Computers
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Technical Reference Guide
T ABLE D-3. DB-15 M ONITOR C ONNECTOR P INOUT ................................................................................... D-5
T ABLE E-1. NVIDIA Q UADRO 2 EX/MXR G RAPHICS D ISPLAY M ODES .................................................... E-3
T ABLE E-2. M ONITOR P OWER M ANAGEMENT C ONDITIONS ....................................................................... E-4
T ABLE E-3. DB-15 M ONITOR C ONNECTOR ................................................................................................ E-5
T ABLE F-1. M ATROX M ILLENNIUM G RAPHICS D ISPLAY M ODES ................................................................F-3
T ABLE F-2. M ONITOR P OWER M ANAGEMENT C ONDITIONS ........................................................................F-4
T ABLE F-3. DB-15 M ONITOR C ONNECTOR .................................................................................................F-5
T ABLE G–1. SCSI H OST A DAPTER C ARD C ONTROL R EGISTER M APPING ................................................... G-3
T ABLE G–2. U LTRA SCSI H OST A DAPTER C ARD S PECIFICATIONS .............................................................. G-3
T
ABLE
G–3. E
XTERNAL
50-P
IN
U
LTRA
SCSI C
ONNECTOR
P
INOUT
............................................................. G-4
T ABLE G–4. I NTERNAL 50-P IN U LTRA SCSI C ONNECTOR P INOUT .............................................................. G-5
T ABLE G–5. U LTRA 160 SCSI C ONNECTOR P INOUT .................................................................................... G-6
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Technical Reference Guide
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xiv Compaq Deskpro Personal Computers
Third Edition –- April 2001
Technical Reference Guide
Chapter 1
INTRODUCTION
1.
Chapter 1 INTRODUCTION
1.1
ABOUT THIS GUIDE
This guide provides technical information about Compaq Deskpro EN and Deskpro Workstation
AP230 Personal Computers that feature Intel Celeron and Pentium III processors and the Intel
815E chipset. This document describes in detail the system’s design and operation for programmers, engineers, technicians, and system administrators, as well as end-users wanting detailed information.
The chapters of this guide primarily describe the hardware and firmware elements and primarily deal with the system board and the power supply assembly. The appendices contain general data such as error codes and information about standard peripheral devices such as keyboards, graphics cards, and communications adapters.
This guide can be used either as an online document or in hardcopy form.
1.1.1 ONLINE VIEWING
Online viewing allows for quick navigating and convenient searching through the document. A color monitor will also allow the user to view the color shading used to highlight differential data.
A softcopy of the latest edition of this guide is available for downloading in .pdf file format at the
URL listed below: http://www.compaq.com/support/techpubs/technical_reference_guides/index.html
Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe
Systems, Inc. at the following URL: http://www.adobe.com
When viewing with Adobe Acrobat Reader, click on the ( the navigation pane for quick access to any section in the guide.
) icon in the tool bar to display
1.1.2 HARDCOPY
A hardcopy of this guide may be obtained by printing from the .pdf file. The document is designed for printing in an 8 ½ x 11-inch format. Note that printing in black and white will lose color shading properties.
Compaq Deskpro Personal Computers
Third Edition – April 2001
1-1
Chapter 1 Introduction
1.2
ADDITIONAL INFORMATION SOURCES
For more information on components mentioned in this guide refer to the indicated manufacturers’ documentation, which may be available at the following online sources:
♦
Compaq Computer Corporation: http://www.compaq.com
♦
Intel Corporation: http://www.intel.com
♦
Standard Microsystems Corporation: http://www.smsc.com
♦
Texas Instruments Inc.: http://www.ti.com
♦
USB user group: http://www.usb.org
1.3
MODEL NUMBERING CONVENTION
The model numbering convention for Compaq Deskpro units is as follows:
ENX/XNNN/NNX/N/NNNx
Removable storage: b = CD/CDRW, c = CD, d = DVD, r = CDRW, z = ZIP
Memory (in MB)
OS type: 2 = Windows 2000; 6 = Dual install. Windows NT 4.0 or 2000)
Chipset type (b = 810E, e = 815E)
Hard drive size (in GB)
Processor speed (3 digits, in MHz; 2 digits, in GHz)
Processor type: C = Celeron; P = Pentium
Form factor: S = Small form factor, L = slim desktop, C = Convertible minitower
1.4
SERIAL NUMBER
The unit’s serial number is located on a sticker placed on the exterior cabinet. The serial number may also be read with the Compaq Diagnostics or Compaq Insight Manager utilities.
1-2 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
1.5
NOTATIONAL CONVENTIONS
The notational guidelines used in this guide are described in the following subsections.
1.5.1 VALUES
Hexadecimal values are indicated by a numerical or alpha-numerical value followed by the letter
“h.” Binary values are indicated by a value of ones and zeros followed by the letter “b.”
Numerical values that have no succeeding letter can be assumed to be decimal unless otherwise stated.
1.5.2 RANGES
Ranges or limits for a parameter are shown using the following methods:
Example A:
Example B:
Bits <7..4> = bits 7, 6, 5, and 4.
IRQ3-7, 9 = IRQ signals 3 through 7, and IRQ signal 9
1.5.3 REGISTER NOTATION AND USAGE
This guide uses standard Intel naming conventions in discussing the microprocessor’s (CPU) internal registers. Registers that are accessed through programmable I/O using an indexing scheme are indicated using the following format:
03C5.17h
Index port
Data port
In the example above, register 03C5.17h is accessed by writing the index port value 17h to the index address (03C4h), followed by a write to or a read from port 03C5h.
1.5.4 BIT NOTATION AND BYTE VALUES
Bit designations are labeled between brackets (i.e., “bit <0 >”). Binary values are shown with the most significant bit (MSb) on the far left, least significant bit (LSb) at the far right. Byte values in hexadecimal are also shown with the MSB on the left, LSB on the right.
Compaq Deskpro Personal Computers
Third Edition – April 2001
1-3
Chapter 1 Introduction
1.6
COMMON ACRONYMS AND ABBREVIATIONS
Table 1-1 lists the acronyms and abbreviations used in this guide.
Table 1–1. Acronyms and Abbreviations
Table 1-1.
Acronyms and Abbreviations
Acronym/Abbreviation Description
A ampere
ACPI Advanced Configuration and Power Interface
A/D analog-to-digital
AGP
API
Accelerated graphics port application programming interface
APIC Advanced Programmable Interrupt Controller
APM advanced power management
AOL Alert-On-LAN™
ASIC
AT
ATA
ATAPI application-specific integrated circuit
1) attention (modem commands) 2) 286-based PC architecture
AT attachment (IDE protocol)
AT attachment w/packet interface extensions
AWG American Wire Gauge (specification)
BIOS
BNC bps or b/s
BTO
CAS
CD-ROM
CDS
CGA basic input/output system
Bayonet Neill-Concelman (connector type) bits per second
Built to order column address strobe compact disk read-only memory compact disk system color graphics adapter cm centimeter
CMOS complimentary metal-oxide semiconductor (configuration memory)
Cntlr controller
Cntrl control codec compressor/decompressor
CPQ Compaq
CPU
CRIMM
CRT
CSM central processing unit
Continuity (blank) RIMM cathode ray tube
Compaq system management / Compaq server management
Continued
1-4 Compaq Deskpro Personal Computers
Third Edition – April 2001
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
DCH
DDC
DIMM
DIN
DIP dpi
DRAM
EDID
EDO
EEPROM
DOS compatibility hole
Display Data Channel dual inline memory module
Deutche IndustriNorm (connector type) dual inline package dots per inch dynamic random access memory extended display identification data extended data out (RAM type) electrically eraseable PROM
EPP
ESCD
EV
FIFO enhanced parallel port
Extended System Configuration Data (format)
Environmental Variable (data) first in / first out
FPM
FPU fast page mode (RAM type)
Floating point unit (numeric or math coprocessor)
FPS Frames per second ft Foot/feet
GB gigabyte
GMCH Graphics/memory controller hub
GND ground
GPIO
GPOC
GART general purpose I/O general purpose open-collector
Graphics address re-mapping table
GUI graphics user interface h hexadecimal
HW hardware hex hexadecimal
Hz Hertz (cycles-per-second)
ICH
IDE
IEEE
I/O controller hub integrated drive element
Institute of Electrical and Electronic Engineers
I/F interface
Technical Reference Guide
Continued
Compaq Deskpro Personal Computers
Third Edition – April 2001
1-5
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description in inch
INT interrupt
I/O input/output
IPL initial program loader
IrDA InfraRed Data Association
Kb / KB kilobits / kilobytes (x 1024 bits / x 1024 bytes)
Kb/s kilobits per second kg kilogram
KHz kilohertz kV kilovolt lb pound
LAN local area network
LCD liquid crystal display
LPC
LSb / LSB
Low pin count least significant bit / least significant byte m Meter
MCH Memory controller hub
MPEG Motion Picture Experts Group ms millisecond
MSb / MSB most significant bit / most significant byte mux multiplex
MVA
MVW motion video acceleration motion video window
NIC network interface card/controller ns nanosecond
NT
NTSC
NVRAM nested task flag
National Television Standards Committee non-volatile random access memory
PAL 1.) programmable array logic 2.) phase altering line
PCI
PCMCIA peripheral component interconnect
Personal Computer Memory Card International Association
Continued
1-6 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
PFC
PIN
Power factor correction personal identification number
PROM programmable read-only memory
PTR pointer
RAM
RAS random access memory row address strobe rcvr receiver
RDRAM (Direct) Rambus DRAM
RPM
RTC revolutions per minute real time clock
R/W Read/Write
SCSI small computer system interface
SDRAM Synchronous Dynamic RAM
SECAM
SGRAM
SIMD
SIMM
SMART
SMI
SMM
SMRAM
SPD
SPDIF
SPN
SPP sequential colour avec memoire (sequential color with memory)
Synchronous Graphics RAM
Single instruction multiple data single in-line memory module
Self Monitor Analysis Report Technology system management interrupt system management mode system management RAM serial presence detect
Sony/Philips Digital Interface (IEC-958 specification)
Spare part number standard parallel port
STN super twist pneumatic
SW software
Continued
Compaq Deskpro Personal Computers
Third Edition – April 2001
1-7
Chapter 1 Introduction
Table 1-1. Acronyms and Abbreviations Continued
Acronym/Abbreviation Description
TAD
TAFI telephone answering device
Temperature-sensing And Fan control Integrated circuit
TPE
TPI twisted pair ethernet track per inch
TV television
TX transmit
UART universal asynchronous receiver/transmitter
URL Uniform resource locator us /
µ s microsecond
UTP unshielded twisted pair
V volt
VESA
VGA
VLSI
Video Electronic Standards Association video graphics adapter very large scale integration
W watt
WOL Wake-On-LAN
ZIF zero insertion force (socket)
1-8 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
Chapter 2
SYSTEM OVERVIEW
2. Chapter 2 SYSTEM OVERVIEW
2.1
INTRODUCTION
Compaq Deskpro Personal Computers (Figure 2-1) deliver an outstanding combination of manageability, serviceability, and consistency for enterprise environments. Based on Intel
Celeron and Pentium III processors with the Intel 815E Chipset, these systems emphasize performance along with industry compatibility. These models feature architectures incorporating the PCI bus. All models are easily upgradable and expandable to keep pace with the needs of the office enterprise.
Compaq Deskpro EN
Small Form Factor
Compaq Deskpro EN Slim Desktop
Compaq Deskpro EN
Configurable Minitower
Figure 2–1. Compaq Deskpro Personal Computers with Monitors
This chapter includes the following topics:
♦
Features and options (2.2)
♦
Mechanical design (2.3)
♦
System architecture (2.4)
♦
Specifications (2.5) page 2-2 page 2-4 page 2-8 page 2-13
Compaq Deskpro
Workstation AP230
Configurable Minitower
Compaq Deskpro Personal Computers
Third Edition - April 2001
2-1
Chapter 2 System Overview
2.2
FEATURES AND OPTIONS
This section describes the standard features and available options.
2.2.1 STANDARD FEATURES
The following standard features are included on all models:
♦
Intel Pentium III or Celeron processor in FC-PGA370 package
♦
Intel 815E Chipset
♦
Instantly Available PC
♦
Three DIMM sockets for system memory
♦
3.5 inch, 1.44-MB diskette drive
♦
48x Max CD-ROM drive
♦
IDE controller w/UATA/100 mode support
♦
Hard drive fault prediction
♦
Two serial, two USB, one parallel, and one network interface
♦
APM 1.2 power management support
♦
Plug ’n Play compatible (with ESCD support)
♦
Intelligent Manageability support
♦
Energy Star compliant
♦
Security features including:
•
Flash ROM Boot Block
•
Diskette drive disable, boot disable, write protect
•
Power-on password
•
Administrator password
•
Serial/parallel port disable
♦
PS/2 Compaq Easy-Access keyboard w/Windows support
♦
PS/2 Compaq Scroll Mouse
Table 2-1 shows the differences in features between the Deskpro series’ based on form factor:
Table 2-1. Feature Difference Matrix
Table 2-1.
Feature Difference Matrix (by Form Factor)
Series
Chassis type
Drive bays
Audio [2]
Front panel audio access
AGP slot
# of PCI slots
Smart Cover Sensor/Lock
Power Supply
Small Form Factor
Deskpro EN
Compaq Proprietary
3
Premier Sound
Yes
No
3
Yes
120 watt
Slim Desktop
Deskpro EN
ATX
5
Business Audio
No
Yes
5
Yes
200 watt
Configurable Minitower [1]
Deskpro EN / Wkstn. AP230
ATX
5
Business Audio
No
Yes
5
No
200 watt
NOTES:
[1] Unit may be configured as desktop or minitower.
[2] Systems with integrated AC97 sound. All systems are also available without integrated
AC97 sound circuitry (legacy beep-audio only).
2-2 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
2.2.2 OPTIONS
The following items are available as options for all models and may be included in the standard configuration of some models:
♦
♦
System Memory: PC133 64-MB DIMM (non-ECC)
PC133 128-MB DIMM (non-ECC)
PC133 256-MB DIMM (non-ECC)
Hard drives/controllers: 10- or 15-GB UATA/66 hard drive
20-GB UATA/100 hard drive
♦
Removeable media drives: 8x/4x/32x CD-RW drive
10x/40x Max DVD-ROM drive
LS-120 Super Disk drive
PCI DXR DVD Decoder kit
♦
Graphics Monitors: Compaq P700 17” CRT
Compaq P900 19” CRT
Compaq P1100 21” CRT
Compaq TFT5010 15” Flat Panel
Compaq TFT8020 18” Flat Panel
Compaq Deskpro Personal Computers
Third Edition - April 2001
2-3
Chapter 2 System Overview
2.3
MECHANICAL DESIGN
These systems are available in three form factors:
♦
Small Form Factor (SFF) – a small-footprint desktop designed for environments where both performance and space are critical issues.
♦
Slim Desktop (SDT) – a low-profile ATX-type desktop that satisfies expandability needs.
♦
Configurable Minitower (CMT) – an ATX-type unit providing the most expandability and being adaptable to desktop or floor-standing placement.
The following subsections describe the mechanical (physical) aspects of the Compaq Deskpro models.
!
CAUTION: Voltages are present within the system unit whenever the unit is plugged into a live AC outlet, regardless of the “Power On” condition. Always disconnect the power cable from the power outlet and/or from the system unit before handling the system unit in any way.
NOTE: The following information is intended primarily for identification purposes only. Before servicing these systems refer to the applicable Maintenance And
Service Guide. Service personnel should review training materials also available on these products.
2-4 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
2.3.1 CABINET LAYOUTS
2.3.1.1
Front Views
5 6 9 2 5 6 9
1 2
1 2 3 4 10 11 7 8
Deskpro EN Small Form Factor
6
5
4
7 8
2
1
1 3 4 7 8
Deskpro EN Slim Desktop
6
5
4
9
8
7
3
2
1
3 4 5 6 9
Deskpro EN
Configurable Minitower
(as a Desktop)
Item
1
Description
Power on LED
Deskpro EN
Configurable Minitower
(as a Minitower)
3
4
5
6
7
8
9
Hard Drive Activity LED
CD-ROM drive headphone jack
CD-ROM drive volume control
CD-ROM drive activity LED
1.44-MB diskette drive activity LED
1.44-MB diskette drive eject button
CD-ROM drive open/close button
10 Microphone In Jack [1]
11 Headphone Out Jack [1]
NOTE: [1] Systems with integrated AC97 audio.
Figure 2–2. Compaq Deskpros, Front Views
Deskpro Workstation AP230
Configurable Minitower
(as a Minitower)
Compaq Deskpro Personal Computers
Third Edition - April 2001
2-5
9
8
7
3
Chapter 2 System Overview
2.3.1.2
Rear Views
2 4 5 6 9 11 12
1 8 12 13 6 10 9 3 7
Small Form Factor
6 9 11 12
2 1 3 4 5 7 8 10 13 14
Slim Desktop
7
8
10
13
14
1
2
3
4
5
6
9
11
12
1 2 3 4 5 7 8 10 13 14
Configurable Minitower
(as a Desktop)
Item Description
5
6
7
1
2
3
4
AC line In Connector (115V/230V)
Line voltage switch
USB I/F connectors (top, port B; bot. , port A)
PS/2 keyboard I/F connector
PS/2 mouse I/F connector
Parallel I/F connector
Monitor connector
Configurable Minitower
(as a Minitower)
Item Desription
8
9
10
11
12
13
14
Serial I/F connector, COM1
Serial I/F connector, COM2
Network I/F connector w/status LEDs
Audio microphone Input jack [1]
Audio line output jack [1]
Audio line input jack [1]
Monitor connector [2]
NOTES:
[1] Systems with integrated AC97 audio.
[2] Present on configurations including separate AGP graphics card.
Figure 2–3. Compaq Deskpros, Rear Views
2-6 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
2.3.2 CHASSIS LAYOUTS
This section describes the internal layouts of the chassis. For detailed information on servicing the chassis refer to the multimedia training CD-ROM and/or the maintenance and service guide for these systems.
The chassis layout for the Small Form Factor is shown in Figure 2-4. Service features include:
♦
Easily-removable card cage assembly.
♦
Tilting drive bay assembly (for easy access to processor and memory sockets).
Slot 3
Slot 2
Slot 1
PCI Conn. 3
PCI Conn. 2
PCI Conn. 1
Slots On Backplane,
Rear View
Card Cage
Assembly
Back
Smart Cover Lock
Solenoid
Power Supply
System Board
Upper Drive Bays
(Tilting Assembly)
Speaker Assembly [1]
Lower Drive Bay
Front
NOTE:
[1] Installed on systems with integrated AC97 audio.
Figure 2–4. Small Form Factor Chassis Layout, Top View
Compaq Deskpro Personal Computers
Third Edition - April 2001
2-7
Chapter 2 System Overview
Figure 2-5 shows the layout for the Slim Desktop. Service features include:
♦
Tilting upper drive bay assembly (for easy access to all drive bays).
♦
Easy access to expansion slots and all socketed system board components.
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
System Board
AGP Slot [1]
Back
Auxiliary Chassis Fan [2]
Smart Cover Lock Solenoid
Power Supply
Processor
Smart Cover Sensor Switch
Upper Drive Bays
(Tilting Assembly)
Speaker [3]
Lower Drive Bays
Front
NOTES:
[1] AGP slot may be populated with AGP graphics card or GPA/AIMM card on some configurations.
[2] Auxiliary chassis fan installed on systems with 933 MHz (or faster) processor.
[3] Installed on systems with integrated AC97 audio.
Figure 2–5. Slim Desktop Chassis Layout, Top View
2-8 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
Figure 2-5 shows the layout for the Configurable Minitower in the minitower configuration.
Features include:
♦
Externally accessible drive bay assembly may be configured for minitower (vertical) or desktop (horizontal) position.
♦
Easy access to expansion slots and all socketed system board components.
Drive Lock
Power Supply
Processor
Auxiliary
Chassis Fan [1]
System Board
Back
AGP Slot [2]
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
PCI Slot 5
Externally Accessible
Drive Bays
Internal
Drive Bays
Front
Speaker [3]
NOTES:
[1] Auxiliary chassis fan installed on systems with 933 MHz or faster processor.
[2] AGP slot may be populated with graphics card or GPA/AIMM card on some configurations.
[3] Installed systems with integrated AC97 audio.
Figure 2–6. Configurable Minitower Chassis Layout, Left Side View (Minitower configuration)
Compaq Deskpro Personal Computers
Third Edition - April 2001
2-9
Chapter 2 System Overview
2.3.3 BOARD LAYOUTS
1 2 3 2 4 5 6 7 8 9 10 11 12 13
35 23 24 34 33 32 31 30 29 28 27 26 25 24
4
5
6
7
8
9
10
Riser Board PCA# 010636
Item Description
1 SCSI hard drive LED connector
System Board PCA# 010633, 010700, or 011035
Item Description
19 Power supply connector
2
3
PCI bus expansion connectors
AOL/SOS connector
20
21
Secondary IDE connector
Primary IDE connector
Riser card connector
PS/2 mouse connector
PS/2 keyboard connector
Monitor connector
Top: USB port B; Bottom: USB port A
Serial port COM2 connector
Network interface connector
22
23
24
25
26
27
28
Diskette drive connector
CD-ROM audio connector (right angle)
CD-ROM audio connector (vertical)
Headphone output jack [3]
Microphone input jack [3]
PCB speaker [4]
CMOS battery
11
12
13
14
15
16
17
Parallel port LPT1 connector
Audio line in jack [3]
Audio line out jack [3]
Serial port COM1 header [1]
Smart Cover Lock solenoid connector
Firmware Hub (BIOS ROM)
Password jumper [2]
29
30
31
32
33
34
35
Processor socket
Hard drive activity LED
Power button
Power LED
DIMM sockets
CMOS memory clear button
Smart Cover Sensor switch
18 Speaker connector [3] -- --
NOTES:
NVIDIA graphics components installed on PCA# 010633 only.
[1] Header connects to COM1 DB-9 connector on I/O panel via cable assembly.
[2] Jumper installed, password enabled. Jumper removed, password is cleared.
[3] Not installed on PCA# 011035.
[4] Installed on PCA# 011035 only.
Figure 2–7.
Small Form Factor Board Layouts
21
22
23
14
15
16
17
18
19
20
2-10 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
1 2 3 4 5 6 7 8 9 10 11 12
13
32
31
30
29
14
15
28 27 26 25 24 23 22 21 20 19 18 17 16
System Board PCA# 010630, or 011032
6
7
8
9
10
11
12
Item Description
1 PCI bus expansion connectors
2
3
4
5
AGP connector
Chassis fan connector
Smart Cover Lock solenoid connector
Top-to-bottom: Mic in, line out, line in [3]
Network interface connector
Top: serial COM2; bottom: serial COM1
Monitor connector
Parallel port LPT1 connector
Mouse connector
Keyboard connector
Top: USB port B; Bottom: USB port A
Item Description
17 Diskette drive connector
18
19
20
21
22
23
24
25
26
27
28
Primary IDE connector
Secondary IDE connector
Power Button/LED connector [1]
CMOS clear memory button
Aux 3.3 VDC LED
Power button diagnostic LED
Password jumper [2]
AOL/SOS connector
CD-ROM audio input connector
Smart Cover Sensor connector
Speaker connector
14
15
16
NOTE:
Processor fan connector
DIMM sockets
Power supply connector
30
31
32
Aux 5 VDC LED
Firmware hub (BIOS ROM)
CMOS battery
[1] Connector for power, IDE HD LED, and SCSI HD LEDs.
[2] Jumper installed, password enabled. Jumper removed, password cleared.
[3] Installed on PCA# 010630 only.
Figure 2–8.
Slim Desktop or Configurable Minitower System Board Layout
Compaq Deskpro Personal Computers 2-11
Third Edition - April 2001
Chapter 2 System Overview
2.4
SYSTEM ARCHITECTURE
The Compaq Deskpro systems covered in this guide feature an architecture based on the Intel
Pentium III or Celeron processor working with the Intel 815E chipset (Figure 2-9). All models use
SDRAM for system memory, provide AGP 4X graphics support, and include PCI bus expansion capability. Standard configurations for Deskpro EN models include Celeron and Pentium III processors. Standard configurations for Deskpro Workstation AP230 models include Pentium III processors.
The 815E chipset includes the 82815 GMCH designed to support a Pentium III or Celeron processor with FSB speeds of either 66-, 100- or 133-MHz. The GMCH also includes an SDRAM controller supporting up to three PC133 DIMMs.
Two standard graphics configurations are available: The 82815 GMCH includes a i740-equivalent
AGP 4X graphics controller that is implemented in the “integrated” configuration while an
NVIDIA TNT Pro AGP 4X graphics controller is used for the “external” configuration.
All systems feature AC’97-compatible audio subsystems and include microphone and line inputs and headphone and/or line outputs. The Deskpro EN Slim Form Factor system features Compaq
Premier Sound components while Slim Desktop and Configurable Minitower systems provide a business audio solution.
The 815E chipset also includes the 82801BA I/O Controller Hub (ICH2) that integrates two IDE controllers with ATA100 support, two USB interfaces, and a PCI bus controller. Also integrated into the 82801BA is an 82562-equivalent network interface controller. An SMC LPC47B357
Super I/O Controller provides serial, parallel, keyboard, mouse, and diskette drive interface functions.
The Small Form Factor system uses a 120-watt power supply while Slim Desktop and
Configurable Minitower systems feature 200-watt power supplies.
Below is a matrix defining the standard configuration differences between the Deskpro EN and the
Deskpro Workstation AP230 models.
Processor
Graphics
Embedded AC97 Audio
Hard Drive Type
Deskpro EN
Celeron or Pentium III
Integrated Direct AGP or NVIDIA TNT2 Pro
Select models
UATA-100
Deskpro Workstation AP230
Pentium III
One of the following AGP 4X cards in AGP slot:
Matrox Millennium G450,
NVIDIA Quadro2 EX, or NVIDIA Quadro2 MXR
All models
UATA-100 or SCSI Ultra 160
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Third Edition – April 2001
Technical Reference Guide
Monitor
Monitor
RGB
4-MB
Display Cache
RGB
Direct AGP
Graphics
Controller or
AGP 4X
Graphics
Controller
AGP
4X
I/F
Pentium III
Or
Celeron [1]
Processor
66-/100-/133- MHz FSB
815E Chipset
82815
GMCH
SDRAM
Cntlr.
PC100/133
Memory
Bus SDRAM
System
Memory
Hub Link
Bus
IDE
Hard Drive
CD
Audio
Audio
Subsystem [2]
Beep
Audio
AC’97
Link Bus
Pri. IDE
Cntlr.
Sec. IDE
82801BA
ICH2
Cntlr.
NIC
USB
Cntlr.
82802
FWH
LPC
Bus
Serial
I/F (2)
Parallel
I/F
LPC47B357 I/O Controller
Keyboard/
Mouse I/F
Diskette
I/F
33-MHz
32-Bit PCI Bus
SCSI
Hard Drive
Power
Supply
Adaptec
29160N
SCSI
Adapter Card
PCI Slots
NOTES:
Resident on system board in SFF units. Separate AGP card in SDT and CMT units.
Select Deskpro Workstation AP230 models only.
[1] Select Deskpro EN models only.
[2] All Deskpro Workstation AP230 models and select Deskpro EN models.
Figure 2–9. Compaq Deskpro Architecture, Block diagram
Compaq Deskpro Personal Computers 2-13
Third Edition - April 2001
Chapter 2 System Overview
2.4.1 PROCESSORS
The Compaq Deskpro EN Series include models based on Celeron and Pentium III processors. All
Compaq Deskpro Workstation AP230 models feature the Pentium III processor. These processors are backward-compatible with software written for the Pentium II, Pentium MMX, Pentium Pro,
Pentium, and x86 microprocessors. Both processor architectures include a floating-point unit, first and secondary caches, and enhanced performance for multimedia applications through the use of multimedia extension (MMX) instructions.
These systems employ a PGA370 zero-insertion-force (ZIF) socket designed for mounting a “Flip-
Chip” (FC-PGA370) processor package (Figure 2-10).
Heat Sink
Retaining Clip
Heat Sink
Retaining Bar
Heat Sink for
MHz Processors
Lock/Unlock
Handle
(Shown in unlock position)
FC-PGA370
Package
Heat Sink for
GHz Processors
PGA370
Socket
Figure 2–10. Processor Assembly And Mounting
The PGA370 socket allows easy changing/upgrading of the processor. Raising the Lock/Unlock handle of the socket in the vertical position allows the processor package to be removed or inserted into the socket. Lowering the Lock/Unlock handle in the down (horizontal) position locks the processor package in place. These systems support processors fitted with passive heat sink or processor fitted with a heat sink/fan assembly with a power cable that attaches to a fan-power header provided on the system board.
NOTE: These systems support processors using the FC-PGA370 package only. The
PPGA370 package, while physically installable, will not work in these systems.
2-14 Compaq Deskpro Personal Computers
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Technical Reference Guide
2.4.1.1
Celeron Processor
The Celeron processor provides economical performance and is compatible with software written for previous generation processors such as Pentium II, Pentium MMX, Pentium, and x86 processors. Featuring a Pentium-type core architecture, the Celeron processor integrates a dual-
ALU CPU with a floating-point unit, 32-KB first-level cache, and 128-KB second level cache, all of which operate at full processing (CPU) speed. The Celeron processor includes MMX technology for enhanced multimedia performance and, on 566-MHz and faster versions, include streaming SIMD extensions (SSE) for enhancing 3D graphics and speech processing performance.
Standard configurations may include a Celeron processor of 566- 600-, 633-, 667-, or 700-MHz with a 66-MHz front side bus (FSB).
2.4.1.2
Pentium III Processor
The Intel Pentium III processor offers maximum performance for select Compaq Deskpros. The
Pentium III processor is compatible with software written for Celeron, Pentium II, Pentium MMX,
Pentium, and x86 processors. Standard configurations include a 667-, 733-, 800-, 866-, or 933-
MHz or 1.0-GHz Pentium III processor with a 133-MHz front side bus.
The Pentium III processor core integrates a dual-ALU CPU with a floating-point unit, a 32-KB first-level cache, and a 256-KB second level cache, all operating at CPU speed. The Pentium III processor includes MMX technology for enhanced multimedia performance. Also included are 70 additional streaming SIMD extensions (SSE) for enhancing 3D graphics and speech processing performance.
The Pentium III processor also includes the following features:
♦
Improved speculative instruction processing
♦
Identification number
Compaq Deskpro Personal Computers 2-15
Third Edition - April 2001
Chapter 2 System Overview
2.4.2 CHIPSET
The Intel 815E chipset consists of a Graphics Memory Controller Hub (GMCH), an enhanced I/O controller hub (ICH2), and a firmware hub (FWH). Table 2-2 lists the integrated functions provided by the chipset.
Table 2-2. Chipset Comparison
Component Type
82815 GMCH
82801BA ICH2
82802 FWH
Table 2-2.
815E Chipset Functions
Function
AGP 4X interface
Direct AGP graphics controller
SDRAM controller supporting 3 PC133 DIMMs
66-/100-/133-MHz FSB
PCI bus I/F
LPC bus I/F
SMBus I/F
IDE I/F with UATA/100 support
AC ’97 controller
RTC/CMOS
IRQ controller
Power management logic
USB I/F (2)
Network interface controller
Loaded with Compaq BIOS
Random number generator
2.4.3 SUPPORT COMPONENTS
Input/output functions not provided by the chipset are handled by other support components.
Some of these components also provide “housekeeping” and various other functions as well. Table
2-3 shows the functions provided by the support components.
Table 2-3. Support Component Functions
Component Name
LPC47B357 I/O Controller
AD1885 Audio Codec [1]
Table 2-3.
Support Component Functions
Function
Keyboard and pointing device I/F
Diskette I/F
Serial I/F (COM1and COM2)
Parallel I/F (LPT1, LPT2, or LPT3)
AGP, PCI reset generation
ISA serial IRQ converter
Power button logic
GPIO ports
Audio mixer
Digital-to-analog converter
Analog-to-digital converter
Analog I/O
NOTE:
[1] Systems with embedded AC97 audio.
2-16 Compaq Deskpro Personal Computers
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Technical Reference Guide
2.4.4 SYSTEM MEMORY
These systems support and come configured with PC133 SDRAM and provide three DIMM sockets with at least one socket populated with a single- or double-sided memory module. Up to
512 megabytes of memory may be installed using one, two, or three DIMMs.
NOTE: There are restrictions on PC133 operation.
These restrictions are described in Chapter 3 “Processor/Memory Subsystem.”
2.4.5 MASS STORAGE
All models include a 3.5 inch 1.44-MB diskette drive installed as drive A. Most models also include a CD-ROM and either a 10-, 15-, or 20-GB hard drive. Standard hard drives feature Drive
Protection System (DPS) support. All systems provide two (one primary, one secondary) PCI bus-mastering Enhanced IDE (EIDE) controllers integrated into the chipset. Each controller provides UATA/100 support for two drives for a total of four IDE devices, although the form factor will determine the actual number of drive spaces available.
2.4.6 SERIAL AND PARALLEL INTERFACES
All models include two serial ports and a parallel port accessible at the rear of the chassis. Each serial port is RS-232-C/16550-compatible and supports standard baud rates up to 115,200 as well as two high-speed baud rates of 230K and 460K , and utilize DB-9 connectors. The parallel interface is Enhanced Parallel Port (EPP1.9) and Enhanced Capability Port (ECP) compatible, and supports bi-directional data transfers through a DB-25 connector.
2.4.7 UNIVERSAL SERIAL BUS INTERFACE
All models feature two Universal Serial Bus (USB) ports that provide a 12Mb/s interface for peripherals. The USB provides hot plugging/unplugging (Plug ’n Play) functionality.
2.4.8 NETWORK INTERFACE CONTROLLER
All models feature a Network Interface Controller (NIC) integrated on the system board.
Equivalent to the Intel 82559 10/100 NIC, the controller provides automatic selection of 10BASE-
T or 100BASE-TX operation with a local area network and includes power-down, wake-up, and
Alert-On-LAN features. An RJ-45 connector with integrated status LEDs is provided on the rear panel.
Compaq Deskpro Personal Computers 2-17
Third Edition - April 2001
Chapter 2 System Overview
2.4.9 GRAPHICS SUBSYSTEM
Two types of graphics subsystems are offered as standard in these systems; integrated and external. The 82815 GMCH component includes an AGP 4X interface and a Direct AGP graphics controller. The “integrated” configuration uses the controller within the 82815 GMCH to drive an
RGB monitor. The “external” configuration features an AGP graphics controller that, due to its presence on the AGP bus, disables the GMCH's integrated controller.
NOTE: Small Form Factor units do not have an AGP slot and are shipped as using the integrated Direct AGP graphics solution or with an embedded NVIDIA TNT2 Pro graphics controller. The customer must choose which graphics solution at the time of purchase.
The Slim Desktop and Configurable Minitower units feature an AGP slot that is used for either mounting a AGP graphics card or for mounting a GPA/AIMM card that supports the integrated i740 controller. The AGP slot includes both Type 1 and Type 2 retention mechanisms. Dualmonitor support is possible by adding a PCI graphics card to either configuration.
Table 2-4 lists the key features of the standard graphics subsystems employed in these systems:
Table 2-4. Standard Graphics Subsystem Comparison
Std. Config. In
Recommended for:
Bus Type
Mem. Amount
Mem. Type
DAC Speed
Max. 2D Res. @
# of colors
Software
Compatibility
Aux. I/O
Outputs
Upgrade path
Integrated
GMCH's
Controller
EN
Hi 2D,
Entry 3D
Direct AGP
4 MB [1]
SDRAM
230 MHz
1600x1200
@ 256
Direct Draw,
Direct 3D,
Active Movie,
Media Player
None
1 RGB
Add
AGP card [3]
Table 2-4.
Standard AGP Graphics Comparison
NVIDIA
TNT2 PRO
EN [2]
Hi 2D,
Entry 3D
AGP 2X/4X
16 MB
SGRAM
300 MHz
1920x1200
@ 16.7M
Quick Draw,
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
VESA I/F
1 RGB
Add
AGP card [3]
NVIDIA
Quadro2 EX
NVIDIA
Quadro2 MXR
Wkstn. AP230 Wkstn. AP230
Entry 3D
AGP 2X/4X
Hi 2D,
Entry 3D
AGP 2X/4X
32 MB
SDRAM
350 MHz
1920x1200
@ 16.7M
32 MB
SDRAM
350 MHz
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
1920x1200
@ 16.7M
Quick Draw,
DCI/DirectX,
Direct Draw,
Direct Show,
MPEG 1/2,
Indeo
VESA I/F
1 RGB
Replace
AGP card
VESA I/F
1 RGB, 1 DVI
Replace
AGP card
NOTES:
[1] Display cache resident on Deskpro EN SFF system board.
Installed as a GPA/AIMM on Deskpro EN SDT/CMT systems.
[2] Controller and memory resident on Deskpro EN SFF system board.
Separate card on Deskpro EN SDT/CMT systems.
[3] Deskpro EN SFF systems "upgradeable" with PCI graphics card only.
[4] Primary RAMDAC. Secondary RAMDAC operates @ 200 MHz.
2-18 Compaq Deskpro Personal Computers
Matrox
Millennium
G450
Wkstn. AP230
Multi-monitor
Hi 2D
AGP 2X/4X
32 MB
DDR SDRAM
350 MHz [4]
2048x768
@ 65K
Quick Draw,
DCI/DirectX,
Direct Draw,
MPEG 1/2,
OpenGL,
Direct 3D
VESA I/F
2 RGB
Replace
AGP card
Third Edition – April 2001
Technical Reference Guide
Compaq Deskpro Personal Computers 2-19
Third Edition - April 2001
Chapter 2 System Overview
2.4.10 AUDIO SUBSYSTEM
Models that feature an embedded AC’97 audio system uses the integrated AC97 audio controller of the chipset and an AC’97-compliant audio codec. These systems include microphone and line inputs and headphone and line outputs. The AC’97-equipped Slim Desktop and Configurable
Minitower models include a 3-watt output amplifier driving an internal speaker. The AC’97equipped Small Form Factor models feature Compaq Premier Sound consisting of a five-level equalizer designed to compensate for chassis acoustics and a low-distortion 5-watt amplifier driving a speaker for optimum sound. Models that do not include integrated AC’97 circuitry provide legacy PC-beep audio support and may be upgraded with the installation of a PCI audio card.
2.5
SPECIFICATIONS
This section includes the environmental, electrical, and physical specifications for the Compaq
Deskpro EN Series Personal Computers. Where provided, metric statistics are given in parenthesis. All specifications subject to change without notice.
Table 2-5. Environmental Specifications
Table 2-5.
Environmental Specifications (Factory Configuration)
Ambient Air Temperature
Shock (w/o damage)
Vibration
Humidity
50 o
to 95 o
F (10 o
to 35 o
C, max. rate of change < 10
°
C/Hr)
5 Gs [1]
0.000215 G 2 /Hz, 10-300 Hz
10-90% Rh @ 28 o
C max. wet bulb temperature
10,000 ft (3048 m) [2]
-24 o
to 140 o
F (-30 o
to 60 o
C, max. rate of change < 20
°
C/Hr )
20 Gs [1]
0.0005 G 2 /Hz, 10-500 Hz
5-95% Rh @ 38.7
o
C max. wet bulb temperature
30,000 ft (9,144 m) [2] Maximum Altitude
NOTE:
[1] Peak input acceleration during an 11 ms half-sine shock pulse.
[2] Maximum rate of change: 1500 ft/min.
Table 2-6. Electrical Specifications
Table 2-6.
Electrical Specifications
Input Line Voltage:
Nominal:
Maximum:
Input Line Frequency Range:
Nominal:
Maximum:
Power Supply:
Maximum Continuous Power
Small Form Factor
Slim Desktop or Configurable Minitower
Maximum Line Current Draw
Small Form Factor
Slim Desktop or Configurable Minitower
100 - 127 VAC
90 - 132 VAC
50 - 60 Hz
47 - 63 Hz
120 watts
200 watts
4.0 A
6.0 A
200 - 240 VAC
180 - 264 VAC
50 - 60 Hz
47 - 63 Hz
120 watts
200 watts
2.0 A
3.0 A
2-20 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
Table 2-7. Physical Specifications
Parameter
Height
Width
Depth
Weight (nom.) [1]
Maximum Supported Weight [2]
Table 2-7.
Physical Specifications
Small
Form Factor
3.8 in (9.70 cm)
Slim
Desktop
Configurable
Minitower [3]
5.38 in (13.67 cm) 17.65 in (44.83 cm)
12.5 in (31.75 cm) 17.65 in (44.83 cm) 6.60 in (16.76 cm)
14.6 in (37.10 cm) 17.11 in (43.46 cm) 17.11 in (43.46 cm)
20 lb (9.1 kg)
100 lb (45.5 kg)
26 lb (12 kg)
100 lb (45.5 kg)
26 lb (12 kg)
100 lb (45.5 kg)
NOTES:
[1] System weight may vary depending on installed drives/peripherals.
[2] Assumes reasonable article(s) such as a display monitor and/or another system unit.
[3] Minitower configuration. For desktop configuration, swap Height and Width dimensions.
Table 2-8. Diskette Drive Specifications
Table 2-8.
Diskette Drive Specifications
(Compaq SP# 179161-001)
Parameter Measurement
Media Type
Height
Bytes per Sector
Sectors per Track:
High Density
Low Density
Tracks per Side:
High Density
Low Density
Read/Write Heads
Average Access Time:
Track-to-Track (high/low)
Average (high/low)
Settling Time
Latency Average
3.5 in 1.44 MB/720 KB diskette
1/3 bay (1 in)
512
18
9
80
80
2
3 ms/6 ms
94 ms/173ms
15 ms
100 ms
Compaq Deskpro Personal Computers 2-21
Third Edition - April 2001
Chapter 2 System Overview
Table 2-9. 48x CD-ROM Drive Specifications
Table 2-9.
48x CD-ROM Drive Specifications
(SP# 187217-B21)
Parameter Measurement
Interface Type
Transfer Rate:
Max. Sustained
Burst
Media Type
Capacity:
Mode 1, 12 cm
Mode 2, 12 cm
8 cm
Center Hole Diameter
Disc Diameter
Disc Thickness
Track Pitch
Laser
Beam Divergence
Output Power
Type
Wave Length
Average Access Time:
Random
Full Stroke
Audio Output Level
Cache Buffer
IDE
4800 KB/s
16.6 MB/s
Mode 1,2, Mixed Mode, CD-DA,
Photo CD, Cdi, CD-XA
550 MB
640 MB
180 MB
15 mm
8/12 cm
1.2 mm
1.6 um
53.5 +/- 1.5
°
53.6 0.14 mW
GaAs
790 +/- 25 nm
<100 ms
<150 ms
0.7 Vrms
128 KB
Table 2-10. Hard Drive Specifications
Parameter
Drive Size
Table 2-10.
Hard Drive Specifications
10.0 GB
3.5”
Drive Protection System Support?
Transfer Rate (max)
Typical Seek Time (w/settling) [1]
Single Track
Average
Full Stroke
Disk Format (logical):
# of Cylinders
# of Data Heads
# of Sectors per Track
Rotation Speed
Drive Fault Prediction
NOTE:
Yes
66.6 MB/s
1.7 ms
8.5 ms
15 ms
16383
16
63
7200 RPM
SMART III
Actual times may vary depending on specific drive installed.
All EMEA units feature Quiet Drives.
15.0 GB
3.5”
Yes
66.6 MB/s
2.0 ms
9.5 ms
21 ms
16383
16
63
7200 RPM
SMART III
20.0 GB
5.25”
Yes
100 MB/s
1.0 ms
9.0 ms
20 ms
16383
16
63
7200 RPM
SMART III
2-22 Compaq Deskpro Personal Computers
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Technical Reference Guide
Compaq Deskpro Personal Computers 2-23
Third Edition - April 2001
Technical Reference Guide
Chapter 3
PROCESSOR/
MEMORY SUBSYSTEM
3.
Chapter 3 PROCESSOR/MEMORY SUBSYSTEM
3.1
INTRODUCTION
This chapter describes the processor/cache memory subsystem of Compaq Deskpro Personal
Computers covered in this guide. These systems feature a Celeron or Pentium III processor and the 815E chipset (Figure 3-1). The 815E chipset supports up to three SDRAM DIMMs.
64-Bit FSB
Processor
Cntl
Direct AGP
Graphics
Cntlr.
FSB I/F
82815
GMCH
Hub I/F
SDRAM
Cntlr.
133-MHz
Memory Bus
J1
DIMM
In
Socket
System Memory
J2
Socket
J3
Socket
May be populated with optional DIMM
Covered in Chapter 6
Covered in Chapter 4
Figure 3–1. Processor/Memory Subsystem Architecture
This chapter includes the following topics:
♦
Processor [3.2]
♦
Memory subsystem [3.3] page 3-2 page 3-5
♦
Subsystem configuration {3.4] page 3-8
Compaq Deskpro Personal Computers 3-1
Third Edition - April 2001
Chapter 3 Processor/Memory Subsystem
3.2
PROCESSOR
The Compaq Deskpro EN is shipped with either a Celeron or Pentium III processor. The Compaq
Deskpro Workstation AP230 is shipped with a Pentium III processor.
3.2.1 CELERON PROCESSOR
The Celeron processor (Figure 3-2) uses a dual-ALU CPU with branch prediction and MMX support, floating point unit (FPU) for math coprocessing, a 32-KB primary (L1) cache, and a 128-
KB secondary (L2) ECC cache. All internal functions, except for the front side bus interface (FSB
I/F), operate at processor speed.
CPU
Celeron Processor
FPU 32-KB
L1
Cache
FSB
I/F
128-KB
L2
Cache
Core processing speed Host bus speed
Figure 3–2. Celeron Processor Internal Architecture
The Celeron processor is software-compatible with earlier generation Pentium II, Pentium MMX,
Pentium, and x86 processors. The MMX support provided by the Celeron consists of 57 special instructions for accelerating multimedia communications applications. Such applications often involve computing-intensive loops that can take up as much as 90 percent of the CPU’s execution time. Using a parallel-processing technique called single-instruction multiple-data (SIMD), MMX logic processes data 64 bits at a time. Specific applications that can benefit from MMX technology include 2D/3D graphics, audio, speech recognition, video codecs, and data compression.
These systems support the Celeron processors listed in the following table:
Table 3–1. Celeron Processor Statistical Comparison
Table 3-1.
Celeron Processor Statistical Comparison
Processor
Celeron 566
Celeron 600 [1]
Celeron 633
Celeron 667
Celeron 700
Celeron 733 [1]
Celeron 766 [1]
Part
Marking
SL4PC
SL4PB
SL4PA
SL4P9
SL4P8
SL4P7
SL4P6
Core/L1/L2
Speed
533 MHz
566 MHz
633 MHz
667 MHz
700 MHz
733 MHz
766 MHz
NOTES:
FSB of all processors operates at 66 MHz.
Statistics are for C-step processors.
[1] Standard configuration processor
Core Voltage
(VccP)
1.50 VDC
1.50 VDC
1.65 VDC
1.65 VDC
1.65 VDC
1.65 VDC
1.65 VDC
Max. Power
Consumption
11.9 W
12.6 W
17.0 W
17.5 W
18.3 W
19.1 W
20.0 W
3-2 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
3.2.2 PENTIUM III PROCESSOR
The Pentium III processor’s architecture (Figure 3-3) includes the same core functionality as described previously for the Celeron processor but includes a larger, 8-way set-associative L2
ECC cache, additional processing features, and higher processing speeds.
CPU
Pentium III
FPU 32-KB
L1
Cache
FSB
I/F
256-KB
L2
Cache or
Core processing speed Host bus speed
Figure 3–3. Pentium III Processor Internal Architecture
The following table lists the key statistics of supported Pentium III processors:
Table 3–2. Pentium III Processor Statistical Comparison
Table 3-2.
Pentium III Processor Statistical Comparison
Processor
Pentium III 600
Pentium III 667
Pentium III 733 [1]
Pentium III 800 [1]
Pentium III 866 [1]
Pentium III 933 [1]
Pentium III 1.0 [1]
Part
Marking
SL4CJ
SL4CG
SL4CD
SL4CB
SL4C9
N/A
Core/L1/L2
Speed
600 MHz
733 MHz
800 MHz
866 MHz
933 MHz
1.01 GHz
NOTE:
FSB of all processors operates at 133 MHz.
Statistics are for C-step processors.
[1] Standard configuration processor.
Core Voltage
(VccP)
SL4CL 533-MHz 1.65
1.65 VDC
1.65 VDC
1.65 VDC
1.65 VDC
1.65 VDC
1.70 VDC
Max. Power
Consumtion
W
17.5 W
18.3 W
20.8 W
22.9 W
24.5 W
26.1 W
The Pentium III processor is software-compatible with Celeron, Pentium II, Pentium MMX,
Pentium, and x86 processors. The Pentium III processor also features 70 FPU-based streaming
SIMD extensions (SSE) that, when implemented by appropriate software, can enhance 3D transforming and speech processing operations. Operating system requirements for SSE support are as follows:
Operating System
Windows 95
Windows 98, OSR0
Windows 98, OSR1
Windows 2000
Windows NT 4.0
Level of SSE Support
No SSE support
SSE support though ISV and OpenGL 6.1 applications only
SSE support though ISV, OpenGL, and DirectX applications
SSE support with ISV, OpenGL, and DirectX applications
SSE support requires driver and Service Pack 4 (SP5 recommended)
Compaq Deskpro Personal Computers 3-3
Third Edition - April 2001
Chapter 3 Processor/Memory Subsystem
3.2.3 PROCESSOR UPGRADING
3.2.3.1
Physical Considerations In Upgrading
All units use the PGA370 ZIF mounting socket and ship with a processor in a Flip-Chip (FC-
PGA370) package installed with a passive heat sink.
!
CAUTION: These systems are specifically designed for processors using the FC-PGA370 package. Other processor packages (such as the PPGA370 package) will physically fit the socket but are not compatible due to electrical and thermal issues.
The FC-PGA370 package consists of the processor die mounted “upside down” on the substrate.
This arrangement allows the heat sink to come in direct contact with the processor die. The heat sink and attachment clip are specially designed provide maximum heat transfer from the processor component.
!
CAUTION: For proper heat dissipation, attachment of the heat sink to the processor is critical on these systems. Improper attachment of the heat sink will likely result in a thermal condition. Although the system is designed to detect thermal conditions and automatically shut down, such a condition could still result in damage to the system .
Refer to the applicable Maintenance and Service Guide for detailed processor removal/replacement procedures.
3.2.3.2
Electrical Considerations In Upgrading
These systems are designed to support the processors listed in Tables 3-1 and 3-2 on the previous pages. Faster processors are not supported nor recommended. Upgrading the processor may require the connection of a power cable from the processor’s heat sink-mounted fan to a header on the system board.
The processor core voltage and operating frequency are automatically set early in power cycle process. No DIP switch settings are involved in replacing the processor.
3.2.3.3
Software Considerations In Upgrading
Although the Celeron and Pentium III processors are software-compatible, it is recommended that the replacement processor be either of the same family as the existing processor (i.e., Celeron for
Celeron, or Pentium for Pentium) or an upgrade (Pentium III for a Celeron). A “downgrade”
(going from a Pentium III to a Celeron) may result in problems with resident software that has been “tuned’ to take advantage of the Pentium III processor’s special features and performance.
3-4 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
3.3
MEMORY SUBSYSTEM
The system boards for these systems provide three 168-pin SDRAM DIMM sockets that accommodate single- or double-sided DIMMs and can handle a maximum of 512 megabytes of
SDRAM. These systems support (and are shipped with) PC133 SDRAM for system memory, providing a maximum throughput of 1 GB/s.
NOTE: For 133-MHz SDRAM operation to occur, all of the following criteria must be met:
1.
The processor’s FSB must operate at 133-MHz.
2.
All installed DIMMs must be PC133-compliant.
3.
The total number of DIMM “sides” is no greater than four: a.
One double-sided and two single-sided DIMMs or b.
Three single-sided DIMMs or c.
Two double-sided DIMMs (with remaining socket empty).
The BIOS will automatically switch the SDRAM speed to 100 MHz if all of the above criteria are not met.
If using memory modules from third party suppliers the following DIMM type is recommended:
Unbuffered 133-MHz SDRAM (PC133)
CAS latency (CL) 2 or 3
Data access time (clock-to-data out) of < 9.0 ns
The SPD format supported by these systems complies with the JEDEC specification for 128-byte
EEPROMs. This system also provides support for 256-byte EEPROMs to include additional
Compaq-added features such as part number and serial number. The SPD format as supported in this system (SPD rev. 1) is shown in Table 3-3.
The key SPD bytes that BIOS checks for compatibility are 2, 9, 10, 18, 23, 24, and 126. If BIOS detects EDO or ECC DIMMs a “memory incompatible” message will be displayed and the system will halt. This system is designed for using non-ECC DIMMs only. Refer to chapter 8 for a description of the BIOS procedure of interrogating DIMMs.
An installed mix of DIMM types (PC100 and PC133, CL 2 and CL 3) is acceptable but operation will be constrained to the level of the DIMM with the lowest performance specification.
If an incompatible DIMM is detected the NUM LOCK will blink for a short period of time during
POST and an error message may or may not be displayed before the system hangs.
Compaq Deskpro Personal Computers 3-5
Third Edition - April 2001
Chapter 3 Processor/Memory Subsystem
The SPD address map is shown below.
Table 3–3. SPD Address Map (SDRAM DIMM)
Table 3-3.
SPD Address Map (SDRAM DIMM)
Byte
0
1
17
18
19
20
21
10
11
12
13
14
15
16
22
23
24
2
3
4
5
6, 7
8
9
No. of Bytes Written Into EEPROM
Total Bytes (#) In EEPROM
Memory Type
No. of Row Addresses On DIMM
No. of Column Addresses On DIMM
No. of Module Banks On DIMM
Data Width of Module
Voltage Interface Standard of DIMM
Cycletime @ Max CAS Latency (CL)
Access From Clock
Config. Type (Parity, Nonparity, etc.)
Refresh Rate/Type
Width, Primary DRAM
Error Checking Data Width
Min. Clock Delay
Burst Lengths Supported
No. of Banks For Each Mem. Device
CAS Latencies Supported
CS# Latency
Write Latency
DIMM Attributes
Memory Device Attributes
Min. CLK Cycle Time at CL X-1
Max. Acc. Time From CLK @ CL X-1
[1]
[2]
[3]
[4]
25
26
27
28
29
30, 31
32..61
62
63
Min. CLK Cycle Time at
CL X-2
Max. Acc. Time From
CLK @ CL X-2
Min. Row Prechge. Time
Min. Row Active to Delay
Min. RAS to CAS Delay
Reserved
Superset Data
SPD Revision
Checksum Bytes 0-62
[4]
[4] [5] 73-90
91, 92
93, 94
[6]
64-71
72
JEP-106E ID Code
DIMM OEM Location
OEM’s Part Number
OEM’s Rev. Code
Manufacture Date
95-98 OEM’s Assembly S/N
99-125 OEM Specific Data
[4]
[4]
[4]
[4]
[7]
[7]
126
127
133-145
146
147
Intel frequency check
Reserved
128-131 Compaq header “CPQ1”
132 Header checksum
Unit serial number
DIMM ID
Checksum
Reserved
[7]
[7]
NOTES:
[1] Programmed as 128 bytes by the DIMM OEM
[2] Must be programmed to 256 bytes.
[3] High order bit defines redundant addressing: if set (1), highest order RAS# address must be
re-sent as highest order CAS# address.
[4] Refer to memory manufacturer’s datasheet
[5] MSb is Self Refresh flag. If set (1), assembly supports self refresh.
[6] Back-to-back random column addresses.
[7] Field format proposed to JEDEC but not defined as standard at publication time.
[8] Field specified as optional by JEDEC but required by this system.
[9] Compaq usage. This system requires that the DIMM EEPROM have this
space available for reads/writes.
[10] Serial # in ASCII format (MSB is 133). Intended as backup identifier in case vender data is
invalid.
Can also be used to indicate s/n mismatch and flag system adminstrator of possible system
Tampering.
[11] Contains the socket # of the module (first module is “1”). Intended as backup identifier (refer to
note [10]).
[8]
[8]
[8]
[8]
[8]
[8]
[8]
[9]
[9]
[9] [10]
[9] [11]
[9]
[9]
[7]
[7]
[7]
[7]
[7]
3-6 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
Figure 3-4 shows the system memory map.
4 GB
Host,
PCI, AGP Area
FFFF FFFFh
FFE0 0000h
FFDF FFFFh
High BIOS Area
(2 MB)
PCI Memory
(18 MB)
FEC1 0000h
FEC0 FFFFh APIC Config. Space
(64 KB)
FEC0 0000h
FEBF FFFFh
PCI Memory
Expansion
(3060 MB)
2000 0000h
1FFF FFFFh
512 MB
Host/PCI Memory
Expansion
(496 MB)
Host, PCI,
ISA Area
0100 0000h
00FF FFFFh
0010 0000h
000F FFFFh
000F 0000h
000E FFFFh
000E 0000h
000D FFFFh
Extended Memory
(15 MB)
System BIOS Area
(64 KB)
Extended BIOS
Area
Option ROM
(128 KB)
16 MB
1 MB
000C 0000h
000B FFFFh
DOS Compatibility
Area
000A 0000h
0009 FFFFh
Graphics/SMRAM
RAM (128 KB)
640 KB
Fixed Mem. Area
(128 KB)
0008 0000h
0007 FFFFh
512 KB
Base Memory
(512 KB)
0000 0000h
NOTE: All locations in memory are cacheable. Base memory is always mapped to DRAM. The next 128 KB fixed memory area can, through the north bridge, be mapped to DRAM or to PCI space. Graphics RAM area is mapped to PCI or AGP locations.
Figure 3–4. System Memory Map
Compaq Deskpro Personal Computers 3-7
Third Edition - April 2001
Chapter 3 Processor/Memory Subsystem
3.4
SUBSYSTEM CONFIGURATION
The 82815 GMCH component provides the configuration function for the processor/memory subsystem. Table 3-4 lists the configuration registers used for setting and checking such parameters as memory control and PCI bus operation. These registers reside in the PCI
Configuration Space and accessed using the methods described in Chapter 4, section 4.2.
Table 3–4. Host/PCI Bridge Configuration Registers (GMCH, Function 0)
PCI Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
Table 3-4.
Host/PCI Bridge Configuration Registers (GMCH, Device 0)
Register
Vender ID
Device ID
Command
Status
Reset
Value
PCI Config.
Addr.
8086h 6A, 6Bh
1130h 6C..6Fh
0006h 70h
[1] 71h
R egister
DRAM Control Reg.
Memory Buffer Strength
Multi-Transaction Timer
CPU Latency Timer
0A..0Bh
0Dh
0Eh
10..13h
50, 51h
53h
55..56h
57h
58h
59..5Fh
60..67h
68h
NOTES:
Class Code
Latency Timer
Header Type
Aperture Base Config.
PAC Config. Reg.
Data Buffer Control
DRAM Row Type
DRAM Control
DRAM Timing
PAM 0..6 Registers
DRAM Row Boundary
Fixed DRAM Hole
--
00h 91h
00h 92h
[2]
00h
83h
90h
93h
A0..A3h
A4..A7h
00h A8..ABh
01h B0..B3h
00h B4h
00h B8..BBh
01h BCh
00h BDh
Error Command
Error Status Register 0
Error Status Register 1
Reset Control
AGP Capability Identifier
AGP Status
AGP Command
AGP Control
Aperture Size
Aperture Translation Table
Aperture I/F Timer
Low Priority Timer
Refer to Intel Inc. documentation for detailed description of registers.
Assume unmarked locations/gaps as reserved.
[1] = 0090h for AGP (external graphics) implementation; = 0080h for GFX (internal i740)
implementation.
[2] = 8 for AGP; = 0 for GFX.
Reset
Value
00h
N/A
N/A
00h
00h
0000h
0000h
00h
00h
00h
55h
00h
10h
02h
00h
00h
00h
3-8 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
Chapter 4
SYSTEM SUPPORT
4. Chapter 4 SYSTEM SUPPORT
4.1
INTRODUCTION
This chapter covers subjects dealing with basic system architecture and covers the following topics:
♦
PCI bus overview (4.2)
♦
AGP bus overview (4.3)
♦
System resources (4.4)
♦
System clock distribution (4.5) page 4-2 page 4-10 page 4-15 page 4-22
♦
Real-time clock and configuration memory (4.6) page 4-23
♦
System management (4.7) page 4-33
♦
Register map and miscellaneous functions (4.8) page 4-38
This chapter covers functions provided by off-the-shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to the systems covered in this guide. For detailed information on specific components, refer to the applicable manufacturer’s documentation.
Compaq Deskpro Personal Computers
Third Edition - April 2001
4-1
Chapter 4 System Support
4.2
PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation in this particular system. For detailed information regarding PCI bus operation, refer to the PCI Local Bus Specification Revision 2.2.
These systems implement a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2) operating at 33 MHz. The PCI bus handles address/data transfers through the identification of devices and functions on the bus. A device is typically defined as a component or slot that resides on the PCI bus (although some components such as the GMCH and ICH2 are organized as multiple devices). A function is defined as the end source or target of the bus transaction. A device may contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the 815E chipset components and is not physically accessible. The AGP bus that services the AGP slot (or resident AGP controller on the Small Form Factor) is designated as PCI bus #1. All PCI slots and the NIC function internal to the 82801BA reside on PCI bus #2.
82815 GMCH Component
Mem. Cntlr.
Function
PCI
Bus #0
AGP
Bridge
Function
Hub Link I/F
Hub Link Bus
Hub Link I/F
PCI Bus #1
(AGP Bus)
AGP Connector
82801BA ICH2 Component
PCI Bus #0
PCI Bridge
Function
PCI
Bus #2 NIC
I/F
Function
PCI
Bus #2
EIDE
Controller
Function
PCI Connector 1
PCI Connector 2
PCI Connector 3
PCI Connector 4
PCI Connector 5
Slim Desktop and Configurable Minitower models only.
Figure 4-1. PCI Bus Devices and Functions
USB
I/F
Function
SMBus
Controller
Function
LPC
Bridge
Function
AC97
Audio
Function
4-2 Compaq Deskpro Personal Computers
Third Edition – April 2001
Technical Reference Guide
4.2.1 PCI BUS TRANSACTIONS
The PCI bus consists of a 32-bit path (AD31-00 lines) that uses a multiplexed scheme for handling both address and data transfers. A bus transaction consists of an address cycle and one or more data cycles, with each cycle requiring a clock (PCICLK) cycle. High performance is realized during burst modes in which a transaction with contiguous memory locations requires that only one address cycle be conducted and subsequent data cycles are completed using auto-incremented addressing. Four types of address cycles can take place on the PCI bus; I/O, memory, configuration, and special. Address decoding is distributed (left up to each device on the PCI bus).
4.2.1.1
I/O and Memory Cycles
For I/O and memory cycles, a standard 32-bit address decode (AD31..0) for byte-level addressing is handled by the appropriate PCI device. For memory addressing, PCI devices decode the
AD31..2 lines for dword-level addressing and check the AD1,0 lines for burst (linearincrementing) mode. In burst mode, subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly (four bytes at a time).
4.2.1.2
Configuration Cycles
Devices on the PCI bus must comply with PCI protocol that allows configuration of that device by software. In this system, configuration mechanism #1 (as described in the PCI Local Bus specification Rev. 2.1) is employed. This method uses two 32-bit registers for initiating a configuration cycle for accessing the configuration space of a PCI device. The configuration address register (CONFIG_ADDRESS) at 0CF8h holds a value that specifies the PCI bus, PCI device, and specific register to be accessed. The configuration data register (CONFIG_DATA) at
0CFCh contains the configuration data.
PCI Configuration Address Register
I/O Port 0CF8h, R/W, (32-bit access only)
Bit Function
0 = Disabled
1 = Enable
30..24 Reserved - read/write 0s
23..16 Bus Number. Selects PCI bus
15..11 PCI Device Number. Selects PCI
device for access
10..8 Function Number. Selects function of
selected PCI device.
7..2
1,0
Register Index. Specifies config. reg.
Configuration Cycle Type ID.
00 = Type 0
01 = Type 1
PCI Configuration Data Register
I/O Port 0CFCh, R/W, (8-, 16-, 32-bit access)
Bit Function
Compaq Deskpro Personal Computers
Third Edition - April 2001
4-3
Chapter 4 System Support
Two types of configuration cycles are used. A Type 0 (zero) cycle is targeted to a device on the
PCI bus on which the cycle is running. A Type 1 cycle is targeted to a device on a downstream
PCI bus as identified by bus number bits <23..16>. With three or more PCI buses, a PCI bridge may convert a Type 1 to a Type 0 if it’s destined for a device being serviced by that bridge or it may forward the Type 1 cycle unmodified if it is destined for a device being serviced by a downstream bridge. Figure 4-2 shows the configuration cycle format and how the loading of
0CF8h results in a Type 0 configuration cycle on the PCI bus. The Device Number (bits <15..11> determines which one of the AD31..11 lines is to be asserted high for the IDSEL signal, which acts as a “chip select” function for the PCI device to be configured. The function number (CF8h, bits <10..8>) is used to select a particular function within a PCI component.
Register 0CF8h
Results in:
3
Reserved
2 2 1 1
Bus
Number
Device
Number
1 1
Function
Number
8 7 2 1 0 [1]
Register
Index
AD31..0
(w/Type 00
Config. Cycle)
IDSEL (only one signal line asserted)
Function
Number
Register
Index
NOTES:
[1] Bits <1,0> : 00 = Type 0 Cycle, 01 = Type 1 cycle
Type 01 cycle only. Reserved on Type 00 cycle.
Figure 4-2. Configuration Cycle
Table 4-1 shows the standard configuration of device numbers and IDSEL connections for components and slots residing on a PCI bus.
Table 4-1. PCI Device Configuration Access
PCI Component
82815 GMCH:
Memory Controller
AGP Bridge
Direct AGP Graphics Cntlr.
AGP slot
82801BA ICH2:
PCI Bridge
LPC Bridge
EIDE Controller
USB I/F #1
SMBus Controller
USB I/F #2
AC97 Audio Controller
AC97 Modem Controller
Network Interface Controller
PCI Connector 1 (slot 1)
PCI Connector 2 (slot 2)
PCI Connector 3 (slot 3)
PCI Connector 4 (slot 4)
PCI Connector 5 (slot 5)
NOTES:
Table 4-1.
PCI Component Configuration Access
Notes Function # Device #
[2]
[2]
[2]
[2,3]
[2,3]
[3]
[1]
[1]
0
0
0
2
3
4
5
0
0
1
6
0
0
0
0
0
0
0
0 (00h)
1 (01h)
2 (02h)
0 (00h)
30 (1Eh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
31 (1Fh)
8 (08h)
4 (04h)
9 (09h)
10 (0Ah)
11 (0Bh)
13 (0Dh)
PCI
Bus #
2
2
2
0
0
0
0
0
0
0
0
2
2
2
0
0
0
1
IDSEL
Wired to:
--
--
--
AD24
AD25
AD26
AD27
AD29
[2] PCI bus number given is for standard configuration.
[3] Slim Desktop and Configurable Minitower models only.
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Configuration
Space
Header
31
The register index (CF8h, bits <7..2>) identifies the 32-bit location within the configuration space of the PCI device to be accessed. All PCI devices can contain up to 256 bytes of configuration data (Figure 4-3), of which the first 64 bytes comprise the configuration space header.
24 23 16 15 8 7 0
Register
Index
FCh
31 24 23 16 15 8 7 0
Register
Index
FCh
Device-Specific Area Device-Specific Area
Min. Lat.
Min. GNT Int. Pin
Reserved
Reserved
Expansion ROM Base Address
Int. Line
Subsystem ID Subsystem Vendor ID
Card Bus CIS Pointer
Base Address Registers
40h
3Ch
38h
34h
30h
2Ch
28h
Bridge Control Int. Pin
Expansion ROM Base Address
Int. Line
Reserved
I/O Limit Upper 16 Bits I/O Base Upper 16 Bits
Prefetchable Limit Upper 32 Bits
Prefetchable Base Upper 32 Bits
Prefetch. Mem. Limit Prefetch. Mem. Base
2 nd
Memory Limit
Secondary Status
Lat.Tmr
Sub. Bus #
Memory Base
I/O Limit
Sec. Bus #
I/O Base
Pri. Bus #
Base Address Registers
40h
3Ch
38h
34h
30h
2Ch
28h
24h
20h
1Ch
18h
BIST Hdr. Type
Class Code
Status
Device ID
Lat. Timer Line Size
Revision ID
Command
Vendor ID
10h
0Ch
08h
04h
00h
BIST Hdr. Type
Class Code
Status
Device ID
Lat. Timer Line Size
Revision ID
Command
Vendor ID
10h
0Ch
08h
04h
00h
PCI Configuration Space Type 0 PCI Configuration Space Type 1
Data required by PCI protocol
Not required
Figure 4-3. PCI Configuration Space Mapping
Each PCI device is identified with a vendor ID (assigned to the vendor by the PCI Special Interest
Group) and a device ID (assigned by the vendor). The device and vendor IDs for the devices on the system board are listed in Table 4-2.
Table 4-2. System Board PCI Device Identification
PCI Device
Table 4-2.
System Board PCI Device Identification
Vendor ID Device ID
82815 GMCH:
Memory Controller
AGP Bridge
Direct AGP Controller
82801 ICH2:
PCI Bridge
LPC Bridge
EIDE Controller
USB I/F #2
SMBus Controller
AC97 Audio Controller
Network Interface Controller
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
1130h
1131h
1132h
244Eh
2440h
244Bh
2444h
(Hidden)
2445h
2449h
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Chapter 4 System Support
4.2.2 PCI BUS MASTER ARBITRATION
The PCI bus supports a bus master/target arbitration scheme. A bus master is a device that has been granted control of the bus for the purpose of initiating a transaction. A target is a device that is the recipient of a transaction. The Request (REQ), Grant (GNT), and FRAME signals are used by PCI bus masters for gaining access to the PCI bus. When a PCI device needs access to the PCI bus (and does not already own it), the PCI device asserts it’s REQn signal to the PCI bus arbiter (a function of the system controller component). If the bus is available, the arbiter asserts the GNTn signal to the requesting device, which then asserts FRAME and conducts the address phase of the transaction with a target. If the PCI device already owns the bus, a request is not needed and the device can simply assert FRAME and conduct the transaction. Table 4-3 shows the grant and request signals assignments for the devices on the PCI bus.
Table 4-3. PCI Bus Mastering Devices
Table 4-3.
PCI Bus Mastering Devices
REQ/GNT Line Device
REQ0/GNT0
REQ1/GNT1
REQ2/GNT2
REQ3/GNT3
REQ4/GNT4
GREQ/GGNT
NOTE:
PCI Connector Slot 1
PCI Connector Slot 2
PCI Connector Slot 3
PCI Connector Slot 4 [1]
PCI Connector Slot 5 [1]
[1] Slim Desktop and Configurable Minitower models only.
PCI bus arbitration is based on a round-robin scheme that complies with the fairness algorithm specified by the PCI specification. The bus parking policy allows for the current PCI bus owner
(excepting the PCI/ISA bridge) to maintain ownership of the bus as long as no request is asserted by another agent. Note that most CPU-to-DRAM and AGP-to-DRAM accesses can occur concurrently with PCI traffic, therefore reducing the need for the Host/PCI bridge to compete for
PCI bus ownership.
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4.2.3 OPTION ROM MAPPING
During POST, the PCI bus is scanned for devices that contain their own specific firmware in
ROM. Such option ROM data, if detected, is loaded into system memory’s DOS compatibility area (refer to the system memory map shown in chapter 3).
4.2.4 PCI INTERRUPTS
Eight interrupt signals (INTA- thru INTH-) are available for use by PCI devices. These signals may be generated by on-board PCI devices or by devices installed in the PCI slots. For more information on interrupts including PCI interrupt mapping refer to the “System Resources” section
4.4.
4.2.5 PCI POWER MANAGEMENT SUPPORT
This system complies with the PCI Power Management Interface Specification (rev 1.0). The PCI
Power Management Enable (PME-) signal is supported by the chipset and allows compliant PCI and AGP peripherals to initiate the power management routine.
4.2.6 PCI SUB-BUSSES
The chipset implements two data busses that are supplementary in operation to the PCI bus:
4.2.6.1
Hub Link Bus
The chipset implements a Hub Link bus between the GMCH and the ICH2. This bus is transparent to software and is not accessible for expansion purposes.
4.2.6.2
LPC Bus
The 82801 ICH2 implements a Low Pin Count (LPC) bus for handling transactions to and from the 47B357 Super I/O Controller as well as the 82802 Firmware Hub (FWH). The LPC bus transfers data a nibble (4 bits) at a time at a 33-MHz rate. Generally transparent in operation, the only consideration required of the LPC bus is during the configuration of DMA channel modes
(see section 4.4.3 “DMA”).
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Chapter 4 System Support
4.2.7 PCI CONFIGURATION
PCI bus operations require the configuration of certain parameters such as PCI IRQ routing, DMA channel configuration, RTC control, port decode ranges, and power management options. These parameters are handled by the LPC I/F bridge function (PCI function #0, device 31) of the ICH2 component and configured through the PCI configuration space registers listed in Table 4-4.
Configuration is provided by BIOS at power-up but re-configurable by software.
Table 4-4. LPC Bridge Configuration Registers (ICH2, Function 0)
PCI
Config.
Addr. Register
00, 01h Vendor ID
02, 03h Device ID
04, 05h Command
06, 07h Status
Table 4-4.
LPC Bridge Configuration Registers
(ICH2, Function 0, Device 31)
Reset
Value
8086h
2440h
000Fh
0280h
PCI
Config.
Addr.
8Ah
90, 91h
A0-CFh
D0-D3h
0A-0Bh Class Code
0Eh Header Type
40-43h ACPI Base Address
44h ACPI Control
4E, 4Fh BIOS Control
54h TCO Control
58-5Bh GPIO Base Address
5Ch GPIO Control
60-63h INTA-D Routing Cntrl.
64h Serial IRQ Control
68-6B
88h
INTE-F Routing Cntrl.
Dev. 31 Error Config.
NOTE:
0106h
80h
1
00h
0000h
00h
1
00h
80h [1]
10h
80h [1]
00h
[1] Value for each byte.
Assume unmarked locations/gaps as reserved.
D8h
E0h
E1h
E2h
E3h
E4, E5h
E6, E7h
E8-EBh
EC, EDh
EE, EFh
F0h
F2h
Register
Device 31 Error Status
PCI DMA Configuration
Power Management
General Control
RTC Configuration
LPC COM Port Dec. Range
LPC FDD & LPT Dec. Rge
LPC Audio Dec. Range
FWH Decode Enable
LPC I/F Decode Range 1
LPC I/F Enables
FWH Select 1
LPC I/F Decode Range 2
FWH Select 2
FWH Decode Enable 2
Function Disable Register
Reset
Value
00h
0000h
0’s
F00h
00h
00h
00h
80h
FFh
0000h
0000h
00112233
0000h
5678h
0Fh
00h
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4.2.8 PCI CONNECTOR
B94
B62 B52 B49
B1
A94
A62 A52 A49
A1
Figure 4-4. PCI Bus Connector (32-Bit Type)
Table 4-5. PCI Bus Connector Pinout
Table 4-5.
PCI Bus Connector Pinout
Pin B Signal
01 -12
A Signal Pin B Signal
32 AD17
A Signal
AD16
Pin B Signal A Signal
63 Reserved GND
02 TCK C/BE7-
03 GND TMS 34 GND FRAME- 65 C/BE6- C/BE5-
04 TDO TDI
05 +5 VDC +5 VDC
35 IRDY-
36 +3.3 VDC
GND
TRDY-
06 +5 37 DEVSEL- GND
66 C/BE4-
67 GND
68 AD63
07 INTB- INTC- 38 GND STOP- 69 AD61
+5
PAR64
AD62
GND
08 INTD- +5 VDC 70 +5 AD60
09 PRSNT1- Reserved 40 PERR-
10 RSVD +5
SDONE
VDC SBO- 72 AD57
AD58
GND
11 PRSNT2- Reserved 42 SERR- GND 73 GND AD56
14 RSVD
15 GND
16 CLK
17 GND
18 REQ- GND 49 GND AD09
19 +5
+3.3
RST-
+5
GNT-
46 GND
48 AD10
50 Key
VDC 76 GND
AD13
AD11
GND
Key
77 AD51
78 AD49
79 +5 AD48
80 AD47
81 AD45
AD52
AD50
GND
AD46
GND
AD31 AD30 51 GND AD44
21 AD29 +3.3 C/BE0- 83 AD43
22 GND AD28 53 AD07 +3.3
AD42
AD06 85 AD40
24 AD25 GND 55 AD05 AD04
25 +3.3 56 AD03 GND
86 AD39
87 AD37
AD38
GND
26 C/BE3- IDSEL
27 AD23
28 GND
+3.3
AD22
57 GND
59 +5
AD02
AD00
VDC
88 +5 AD36
89 AD35
90 AD33
AD34
GND
91 AD32
30 AD19 GND 61 +5 VDC 92 Reserved Reserved
31 +3.3 62 +5 93 Reserved GND
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Chapter 4 System Support
4.3
AGP BUS OVERVIEW
NOTE: The Small Form Factor system features an on-board AGP graphics adapter and does not provide an accessible AGP slot. All Slim Desktop and Configurable Minitower systems provide an AGP slot and may implement either an on-board AGP graphics adapter with a GPA/AIMM card or separate AGP graphics card. For a detailed description of AGP bus operations refer to the AGP Interface Specification Rev. 2.0 available at the following AGP forum web site: http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet highperformance interface for graphics adapters, especially those designed for 3D operations. The
AGP interface is designed to give graphics adapters dedicated pipelined access to system memory for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapter only requires enough memory for frame buffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also behave as a “PCI” target during fast writes from the GMCH or MCH.
Key differences between the AGP interface and the PCI interface are as follows:
♦
Address phase and associated data transfer phase are disconnected transactions. Addressing and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request for data and the transfer of data may be separated by other operations.
♦
Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus, commands involving I/O and configuration are not required or allowed. The system memory address space used in AGP operations is the same linear space used by PCI memory space commands, but is further specified by the graphics address re-mapping table (GART) of the north bridge component.
♦
Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries. If a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data that is discarded by the target.
♦
Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data transfers. These actions are separate from each other.
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4.3.1.1
Data Request
Requesting data is accomplished in one of two ways; either multiplexed addressing (using the AD lines for addressing/data) or demultiplexed (“sideband”) addressing (using the SBA lines for addressing only and the AD lines for data only). Even though there are only eight SBA lines (as opposed to the 32 AD lines) sideband addressing maximizes efficiency and throughput by allowing the AD lines to be exclusively used for data transfers. Sideband addressing occurs at the same rate (1X, 2X, or 4X) as data transfers. The differences in rates will be discussed in the next section describing data transfers. Note also that sideband addressing is limited to 48 bits (address bits 48-63 are assumed zero). The GMCH component supports both SBA and AD addressing , but the method and rate is selected by the AGP graphics adapter.
4.3.1.2
Data Transfers
Data transfers use the AD lines and occur as the result of data requests described previously. Each transaction resulting from a request involves at least eight bytes, requiring the 32 AD lines to handle at least two transfers per request. The 82815E GMCH supports three transfer rates: 1X, 2X, and 4X. Regardless of the rate used, the speed of the bus clock is constant at 66 MHz. The following subsections describe how the use of additional strobe signals makes possible higher transfer rates.
AGP 1X Transfers
During a AGP 1X transfer the 66-MHz CLK signal is used to qualify the control and data signals.
Each 4-byte data transfer is synchronous with one CLK cycle so it takes two CLK cycles for a minimum 8-byte transfer (Figure 4-5 shows two 8-byte transfers). The GNT- and TRDY- signals retain their traditional PCI functions. The ST0..3 signals are used for priority encoding, with “000” for low priority and “001” indicating high priority. The signal level for AGP 1X transfers may be
3.3 or 1.5 VDC.
T1 T2 T3 T4 T5 T6 T7
CLK
AD
GNT-
TRDY-
ST0..2
00x
D1A D1B xxx xxx
D2A xxx
D2B xxx xxx
Figure 4-5. AGP 1X Data Transfer (Peak Transfer Rate: 266 MB/s)
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Chapter 4 System Support
AGP 2X Transfers
During AGP 2X transfers, clocking is basically the same as in 1X transfers except that the 66-
MHz CLK signal is used to qualify only the control signals. The data bytes are latched by an additional strobe (AD_STBx) signal so that an 8-byte transfer occurs in one CLK cycle (Figure 4-
6). The first four bytes (DnA) are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes (DnB) are latched on the rising edge of AD_STBx. The signal level for
AGP 2X transfers may be 3.3 or 1.5 VDC.
T1 T2 T3 T4 T5 T6 T7
CLK
AD
AD_STB
GNT-
TRDY-
ST0..2
D1A D1B D2A D2B D3A D3B D4A D4B
00x xxx xxx xxx xxx xxx
Figure 4-6. AGP 2X Data Transfer (Peak Transfer Rate: 532 MB/s)
AGP 4X Transfers
The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock cycle. As in
2X transfers the 66-MHz CLK signal is used only for qualifying control signals while strobe signals are used to latch each 4-byte transfer on the AD lines. As shown in Figure 4-7, 4-byte block DnA is latched by the falling edge of AD_STBx while DnB is latched by the falling edge of
AD_STBx-. The signal level for AGP 4X transfers is 1.5 VDC.
CLK
AD
AD_STB
AD_STBx-
ST0..2
xxx
T1 T2
D1A
00x
D1B D2A D2B
T3
D3A D3B D4A D4B xxx
T4 xxx
Figure 4-7. AGP 4X Data Transfer (Peak Transfer Rate: 1064 MB/s)
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4.3.2 AGP CONFIGURATION
AGP bus operations require the configuration of certain parameters involving system memory access by the AGP graphics adapter. The AGP bus interface is configured as a PCI device integrated within the north bridge (GMCH, device 1) component. The AGP function is, from the
PCI bus perspective, treated essentially as a PCI/PCI bridge and configured through PCI configuration registers (Table 4-6). Configuration is accomplished by BIOS during POST.
NOTE: Configuration of the AGP bus interface involves functions 0 and 1 of the
GMCH. Function 0 registers (listed in Table 3-4) include functions that affect basic control (GART) of the AGP.
Table 4-6. PCI/AGP Bridge Configuration Registers (MCH, Function 1)
Table 4-6.
PCI/AGP Bridge Function Configuration Registers
(GMCH, Function 1)
PCI
Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
0A, 0Bh
0Eh
18h
19h
1Ah
Register
Vendor ID
Device ID
Command
Status
Revision ID
Class Code
Header Type
Primary Bus Number
Secondary Bus Number
Subordinate Bus Number
Reset
PCI
Config.
Value Addr.
8086h 1Bh
1131h 1Ch
0000h 1Dh
0020h 1E, 1Fh
00h 20, 21h
0406h 22, 23h
01h 24, 25h
00h
00h
26, 27h
3Eh
00h 3F-FFh
Register
Sec. Master Latency Timer
I/O Base Address
I/O Limit Address
Sec. PCI/PCI Status
Memory Base Address
Reset
Value
00h
F0h
00h
02A0h
FFF0h
Memory Limit Address 0000h
Prefetch Mem. Base Addr. FFF0h
Prefetch Mem. Limit Addr. 0000h
PCI/PCI Bridge Control 00h
Reserved 00h
NOTE:
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed register descriptions.
The AGP graphics adapter (actually its resident controller) is configured as a standard PCI device.
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Chapter 4 System Support
4.3.3 AGP CONNECTOR
B94 A1 A66
A94
B1 B66
Figure 4-8. Universal AGP Bus Connector
Table 4-7. AGP Bus Connector Pinout
Table 4-7.
AGP Bus Connector Pinout
Pin A Signal B Signal Pin A Signal B Signal
VDC OVRCNT- GND
Pin A Signal B Signal
45 VDD3 VDD3
Det- 24 NC
03 NC VDD 25 VDD3 VDD3 47 STOP- VDDQ
04 USBN USBP 26 PAD30 PAD31 48 PME- PERR-
05 GND GND 27 PAD28 PAD29 49 GND GND
06 INTA- INTB- 28 VDD3 VDD3 50 PAR SERR-
07 RESET CLK 29 PAD26 PAD27 51 PAD15 CBE1-
08 GNT- REQ- 30 PAD24 PAD25 52 VDDQ VDDQ
09 VDD3
10 ST1
VDD3
ST0
31 GND GND 53 PAD13 PAD14
11 NC ST2 33 CBE3- PAD23 55 GND GND
12 PIPE- RBF- 34 VDDQ VDDQ 56 PAD09 PAD10
13 GND GND 35 PAD22 PAD21 57 CBE0- PAD08
14 WBF- NC 36 PAD20 PAD19 58 VDDQ VDDQ
15 SBA1 SBA0 37 GND GND
16 VDD3 VDD3 38 PAD18 PAD17 60 PAD06 PAD07
17 SBA3 SBA2 39 PAD16 CBE2- 61 GND GND
18 SB_STB- SB_STB 40 VDDQ VDDQ 62 PAD04 PAD05
19 GND GND 41 FRAME- IRDY- 63 PAD02 PAD03
20 SBA5 SBA4 42 NC VDD3 VDDQ
21 SBA7 DBA6 43 GND GND 65 PAD00 PAD01
NOTES;
NC = Not connected
VDDQ = 3.3 VDC when TYPE DET- is left open by AGP 1X/2X card.
VDDQ = 1.5 VDC when TYPE DET- is grounded by AGP 4X card.
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4.4
SYSTEM RESOURCES
This section describes the availability and basic control of major subsystems, otherwise known as resource allocation or simply “system resources.” System resources are provided on a priority basis through hardware interrupts and DMA requests and grants.
4.4.1 INTERRUPTS
The microprocessor uses two types of hardware interrupts; maskable and nonmaskable. A maskable interrupt can be enabled or disabled within the microprocessor by the use of the STI and
CLI instructions. A nonmaskable interrupt cannot be masked off within the microprocessor, although it may be inhibited by hardware or software means external to the microprocessor.
4.4.1.1
Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-H
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the interrupt
(INTR-) input to the microprocessor. The microprocessor halts execution to determine the source of the interrupt and then services the peripheral as appropriate.
Figure 4-9 shows the routing of PCI and ISA interrupts. Most IRQs are routed through the I/O controller, which contains a serializing function. A serialized interrupt stream is applied to the
82801 ICH2.
I/O &
SM Functions
IRQ3..7,
9..12,
14,15
IDE
Hard Drives
IRQ14,15
INTA-..H-
PCI Peripherals
LPC47B357
I/O Cntlr.
Interrupt
Serializer
Serial IRQ
82801
ICH2
Interrupt
Processing
INTR-
APIC bus
Processor
Figure 4-9. Maskable Interrupt Processing, Block Diagram
Interrupts may be processed in one of two modes (selectable through the F10 Setup utility):
♦
8259 mode
♦
APIC mode
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Chapter 4 System Support
8259 Mode
The 8259 mode handles interrupts IRQ0-IRQ15 in the legacy (AT-system) method using 8259equivalent logic. Table 4-8 lists the standard source configuration for maskable interrupts and their priorities in 8259 mode. If more than one interrupt is pending, the highest priority (lowest number) is processed first.
Table 4-8. Maskable Interrupt Priorities and Assignments
Table 4-8.
Maskable Interrupt Priorities and Assignments
Priority Signal Label Source (Typical)
1 IRQ0 Interval timer 1, counter 0
2
3
IRQ1
IRQ8-
Keyboard
Real-time clock
4
5
6
7
8
9
10
11
12
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ3
IRQ4
Unused
Unused
Unused
Mouse
Coprocessor (math)
IDE primary I/F
IDE secondary I/F
Serial port (COM2)
Serial port (COM1)
14 IRQ6 Diskette drive controller
NOT AVAILABLE (Cascade from interrupt controller 2) --
APIC Mode
IRQ2
The Advanced Programmable Interrupt Controller (APIC) mode provides enhanced interrupt processing with the following advantages:
♦
Eliminates the processor’s interrupt acknowledge cycle by using a separate (APIC) bus
♦
Programmable interrupt priority
♦
Additional interrupts (total of 24)
The APIC mode accommodates eight PCI interrupt signals (INTA-..INTH-) for use by PCI devices. The PCI interrupts are evenly distributed to minimize latency and wired as follows:
ICH2
Int. Cntlr.
PCI
Slot 1
PCI
Slot 2
PCI
Slot 3
PCI
Slot 4
PCI
Slot 5
INTC- INTD-
INTB- -- -- -- -- --
AGP
Slot
--
--
NIC
I/F [1]
USB
I/F #2
Direct AGP
Cntlr. [2]
-- -- INTA-
-- -- INTB-
Wired INTD-
INTE- -- -- -- --
--
---
INTA- INTB-
INTB-
INTA-
INTC-
INTA-
INTB-
--
--
--
-- --
-- --
-- --
--
-- -- --
INTA- -- --
--
--
INTH- -- -- -- --
NOTES:
-- -- -- INTC-
[1] Connection internal to the ICH2. Will be reported by BIOS as using INTA but is NOT shared with
other functions using INTA.
[2] Internal graphics controller of the 82815 GMCH, internally wired.
Deskpro SDT and CMT systems only.
--
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The PCI interrupts can be configured by PCI Configuration Registers 60h..63h to share the standard ISA interrupts (IRQn).
NOTE: The APIC mode is supported by the Windows NT and Windows 2000 operating systems. Systems running the Windows 95 or 98 operating system will need to run in
8259 mode.
Maskable Interrupt processing is controlled and monitored through standard AT-type I/O-mapped registers. These registers are listed in Table 4-9.
Table 4-9. Maskable Interrupt Control Registers
Table 4-9.
Maskable Interrupt Control Registers
I/O Port Register
020h Base Address, Int. Cntlr. 1
021h
0A0h
0A1h
Initialization Command Word 2-4, Int. Cntlr. 1
Base Address, Int. Cntlr. 2
Initialization Command Word 2-4, Int. Cntlr. 2
The initialization and operation of the interrupt control registers follows standard AT-type protocol.
4.4.1.2
Non-Maskable Interrupts
Non-maskable interrupts cannot be masked (inhibited) within the microprocessor itself but may be maskable by software using logic external to the microprocessor. There are two non-maskable interrupt signals: the NMI- and the SMI-. These signals have service priority over all maskable interrupts, with the SMI- having top priority over all interrupts including the NMI-.
NMI- Generation
The Non-Maskable Interrupt (NMI-) signal can be generated by one of the following actions:
♦
Parity errors detected on a PCI bus (activating SERR- or PERR-).
♦
Microprocessor internal error (activating IERRA or IERRB)
The SERR- and PERR- signals are routed through the ICH2 component, which in turn activates the NMI to the microprocessor.
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Chapter 4 System Support
The NMI Status Register at I/O port 061h contains NMI source and status data as follows:
NMI Status Register 61h
Bit Function
0 = No NMI from system board parity error.
1 = NMI requested, read only
5
4
3
2
1
0
0 = No NMI from IOCHK-
1 = IOCHK- is active (low), NMI requested, read only
Interval Timer 1, Counter 2 (Speaker) Status
Refresh Indicator (toggles with every refresh)
IOCHK- NMI Enable/Disable:
0 = NMI from IOCHK- enabled
1 = NMI from IOCHK- disabled and cleared (R/W)
System Board Parity Error (PERR/SERR) NMI Enable:
0 = Parity error NMI enabled
1 = Parity error NMI disabled and cleared (R/W)
Speaker Data (R/W)
Inteval Timer 1, Counter 2 Gate Signal (R/W)
0 = Counter 2 disabled
1 = Counter 2 enabled
Functions not related to NMI activity.
After the active NMI has been processed, status bits <7> or <6> are cleared by pulsing bits <2> or
<3> respectively.
The NMI Enable Register (070h, <7>) is used to enable/disable the NMI signal. Writing 80h to this register masks generation of the NMI-. Note that the lower six bits of register at I/O port 70h affect RTC operation and should be considered when changing NMI- generation status.
SMI- Generation
The SMI- (System Management Interrupt) is typically used for power management functions.
When power management is enabled, inactivity timers are monitored. When a timer times out,
SMI- is asserted and invokes the microprocessor’s SMI handler. The SMI- handler works with the
APM BIOS to service the SMI- according to the cause of the timeout.
Although the SMI- is primarily used for power managment the interrupt is also employed for the
QuickLock/QuickBlank functions as well.
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4.4.2 DIRECT MEMORY ACCESS
Direct Memory Access (DMA) is a method by which a device accesses system memory without involving the microprocessor. Although the DMA method has been traditionally used to transfer blocks of data to or from an ISA I/O device, PCI devices may also use DMA operation as well.
The DMA method reduces the amount of CPU interactions with memory, freeing the CPU for other processing tasks.
NOTE: This section describes DMA in general. For detailed information regarding
DMA operation, refer to the data manual for the Intel 82801BA I/O Controller Hub.
The 82801 ICH2 component includes the equivalent of two 8237 DMA controllers cascaded together to provide eight DMA channels, each (excepting channel 4) configurable to a specific device. Table 4-10 lists the default configuration of the DMA channels.
Table 4-10. Default DMA Channel Assignments
Table 4-10.
Default DMA Channel Assignments
DMA Channel
Controller 1 (byte transfers)
0
1
2
3
Controller 2 (word transfers)
4
5
6
7
Device ID
Spare
Audio subsystem
Diskette drive
ECP LPT1
Cascade for controller 1
Spare
Spare
Spare
All channels in DMA controller 1 operate at a higher priority than those in controller 2. Note that channel 4 is not available for use other than its cascading function for controller 1. The DMA controller 2 can transfer words only on an even address boundary. The DMA controller and page register define a 24-bit address that allows data transfers within the address space of the CPU.
In addition to device configuration, each channel can be configured (through PCI Configuration
Registers) for one of two modes of operation:
♦
LPC DMA
♦
PC/PCI DMA
The LPC DMA mode uses the LPC bus to communicate DMA channel control and is implemented for devices using DMA through the LPC47B357 I/O controller such as the diskette drive controller.
The PC/PCI DMA mode uses the REQ#/GNT# signals to communicate DMA channel control and is used by PCI expansion devices.
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Chapter 4 System Support
The DMA logic is accessed through two types of I/O mapped registers; page registers and controller registers.
4.4.2.1
DMA Page Registers
The DMA page register contains the eight most significant bits of the 24-bit address and works in conjunction with the DMA controllers to define the complete (24-bit)address for the DMA channels. Table 4-11 lists the page register port addresses.
Table 4-11. DMA Page Register Addresses
Table 4-11.
DMA Page Register Addresses
DMA Channel
Controller 1 (byte transfers)
Ch 0
Ch 1
Ch 2
Ch 3
Controller 2 (word transfers)
Ch 4
Ch 5
Ch 6
Ch 7
Refresh
Page Register I/O Port
087h
083h
081h
082h n/a
08Bh
089h
08Ah
08Fh [see note]
NOTE:
The DMA memory page register for the refresh channel must be
programmed with 00h for proper operation.
The memory address is derived as follows:
24-Bit Address - Controller 1 (Byte Transfers)
8-Bit Page Register 8-Bit DMA Controller
A23..A16
A15..A00
24-Bit Address - Controller 2 (Word Transfers)
8-Bit Page Register
A23..A17
16-Bit DMA Controller
A16..A01, (A00 = 0)
Note that address line A16 from the DMA memory page register is disabled when DMA controller
2 is selected. Address line A00 is not connected to DMA controller 2 and is always 0 when wordlength transfers are selected.
By not connecting A00, the following applies:
♦
The size of the the block of data that can be moved or addressed is measured in 16-bits
(words) rather than 8-bits (bytes).
♦
The words must always be addressed on an even boundary.
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DMA controller 1 can move up to 64 Kbytes of data per DMA transfer. DMA controller 2 can move up to 64 Kwords (128 Kbytes) of data per DMA transfer. Word DMA operations are only possible between 16-bit memory and 16-bit peripherals.
The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM memory space. Refresh operations are used to refresh memory on the 32-bit memory bus and the ISA bus. The refresh address is provided on lines SA00 through SA08. Address lines
LA23..17, SA18,19 are driven low.
The remaining address lines are in an undefined state during the refresh cycle. The refresh operations are driven by a 69.799-KHz clock generated by Interval Timer 1, Counter 1. The refresh rate is 128 refresh cycles in 2.038 ms.
4.4.2.2
DMA Controller Registers
Table 4-12 lists the DMA Controller Registers and their I/O port addresses. Note that there is a set of registers for each DMA controller.
Table 4-12. DMA Controller Registers
Register
Table 4-12.
DMA Controller Registers
Controller 1 Controller 2 R/W
Write Single Mask Bit
Write All Mask Bits
Software DRQx Request
Base and Current Address - Ch 0
Current Address - Ch 0
Base and Current Word Count - Ch 0
Current Word Count - Ch 0
Base and Current Address - Ch 1
Current Address - Ch 1
Base and Current Word Count - Ch 1
Current Word Count - Ch 1
Base and Current Address - Ch 2
Current Address - Ch 2
Base and Current Word Count - Ch 2
Current Word Count - Ch 2
Base and Current Address - Ch 3
Current Address - Ch 3
Base and Current Word Count - Ch 3
Current Word Count - Ch 3
Temporary (Command)
Reset Pointer Flip-Flop (Command)
Master Reset (Command)
Reset Mask Register (Command)
002h
003h
003h
004h
004h
005h
005h
006h
00Ah
00Fh
009h
000h
000h
001h
001h
002h
006h
007h
007h
00Dh
00Ch
00Dh
00Eh
0C4h
0C6h
0C6h
0C8h
0C8h
0CAh
0CAh
0CCh
0D4h
0DEh
0D2h
0C0h
0C0h
0C2h
0C2h
0C4h
0CCh
0CEh
0CEh
0DAh
0D8h
0DAh
0DCh
R
W
R
W
R
W
R
W
R
W
R
W
W
W
W
W
R
W
R
R
W
W
W
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Chapter 4 System Support
4.5
SYSTEM CLOCK DISTRIBUTION
These systems use an Intel CK-type clock generator and crystal for generating the clock signals required by the system board components. Table 4-13 lists the system board clock signals and how they are distributed.
Table 4-13. Clock Generation and Distribution
Table 4-13.
Clock Generation and Distribution
66, 100, or 133 MHz
100 or 133 MHz
66 MHz
48 MHz
33 MHz
14.31818 MHz
NOTES:
CK
CK
CK
CK
Processor, GMCH
DIMM sockets
ICH2, AGP Graphics Cntlr. [1]
ICH2, I/O Cntlr.
CK Processor, ICH2, PCI Slots
Crystal CK
[1] Routed to on-board controller on Deslpro EN SFF.
Routed to AGP slot on Slim Desktop and Configurable Minitower.
Certain clock outputs are turned off during reduced power modes to conserve energy. Clock output control is handled through the SMBus interface by BIOS.
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4.6
REAL-TIME CLOCK AND CONFIGURATION MEMORY
The Real-time clock (RTC) and configuration memory (also referred to as “CMOS”) functions are provided by the 82801 ICH2 component and is MC146818-compatible. As shown in the following figure, the 82801 ICH2 component provides 256 bytes of battery-backed RAM divided into two
128-byte configuration memory areas. The RTC uses the first 14 bytes (00-0Dh) of the standard memory area. All locations of the standard memory area (00-7Fh) can be directly accessed using conventional OUT and IN assembly language instructions through I/O ports 70h/71h, although the suggested method is to use the INT15 AX=E823h BIOS call.
82801
07h
06h
05h
04h
03h
02h
01h
0Dh
0Ch
0Bh
0Ah
09h
08h
00h
Register D
Register C
Register B
Register A
Year
Month
Date of Month
Day of Week
Hours (Alarm)
Hours (Timer)
Minutes (Alarm)
Minutes (Timer)
Seconds (Alarm)
Seconds (Timer)
Extended Config.
Memory Area
(128 bytes)
Standard Config.
Memory Area
(114 bytes)
RTC Area
(14 bytes)
FFh
80h
7Fh
0Eh
0Dh
00h
CMOS
Figure 4-10. Configuration Memory Map
A lithium 3-VDC battery is used for maintaining the RTC and configuration memory while the system is powered down. During system operation a wire-Ored circuit allows the RTC and configuration memory to draw power from the power supply. The battery is located in a battery holder on the system board and has a life expectancy of four to eight years. When the battery has expired it is replaced with a Renata CR2032 or equivalent 3-VDC lithium battery.
4.6.1
CLEARING CMOS
The contents of configuration memory (including the Power-On Password) can be cleared by the following procedure:
1.
Turn off the unit.
2.
Disconnect the AC power cord from the outlet and/or system unit.
3.
Remove the chassis hood (cover) and insure that no LEDs on the system board are illuminated.
4.
Press and release the CMOS clear button on the system board.
5.
Replace the chassis hood (cover).
6.
Reconnect the AC power cord to the outlet and/or system unit.
7.
Turn the unit on.
To clear only the Power-On Password refer to section 4.7.1.1.
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Chapter 4 System Support
4.6.2 CMOS ARCHIVE AND RESTORE
During the boot sequence the BIOS saves a copy of NVRAM (CMOS contents, password(s) and other system variables) in a portion of the flash ROM. Should the system become un-usable, the last good copy of NVRAM data can be restored with the Power Button Override function. This function is invoked with the following procedure:
1.
With the unit powered down, press and release the power button.
2.
Immediately after releasing the power button in step 1, press and hold the power button until the unit powers down. This action will be recorded as a Power Button Override event.
With the next startup sequence the BIOS will detect the occurrence of the Power Button Override event and will load the backup copy of NVRAM from the ROM to the CMOS.
NOTE: The Power Button Override feature does not allow quick cycling of the system
(turning on then off). If the power cord is disconnected during the POST routine, the splash screen image may become corrupted, requiring a re-flashing of the ROM (refer to chapter 8, BIOS ROM).
4.6.3 STANDARD CMOS LOCATIONS
Table 4-14 and the following paragraphs describe standard configuration memory locations 0Ah-
3Fh. These locations are accessible through using OUT/IN assembly language instructions using port 70/71h or BIOS function INT15, AX=E823h.
Table 4-14. Configuration Memory (CMOS) Map
Table 4-14.
Configuration Memory (CMOS) Map
Location Function Location Function
00-0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
Real-time clock
Diagnostic status
System reset code
Diskette drive type
Reserved
Hard drive type
Security functions
Equipment installed
Base memory size, low byte/KB
Base memory size, high byte/KB
Extended memory, low byte/KB
Extended memory, high byte/KB
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh-2Fh
30h-31h
19h
1Ah
1Bh
1Ch
1Dh
Hard drive 1, primary controller
Hard drive 2, primary controller
Hard drive 1, secondary controller
32h
33h
Hard drive 2, secondary controller 35h
Enhanced hard drive support
1Eh Reserved
1Fh Power management functions
34h
36h
40-FFh
NOTES:
System board ID
System architecture data
Auxiliary peripheral configuration
Speed control external drive
Expanded/base mem. size, IRQ12
Miscellaneous configuration
Hard drive timeout
System inactivity timeout
Monitor timeout, Num Lock Cntrl
Additional flags
Checksum of locations 10h-2Dh
Total extended memory tested
Century
Miscellaneous flags set by BIOS
International language
APM status flags
ECC POST test single bit
Feature Control/Status
Assume unmarked gaps are reserved.
Higher locations (>3Fh) contain information that should be accessed using the INT15, AX=E845h
BIOS function (refer to Chapter 8 for BIOS function descriptions).
RTC Control Register A, Byte 0Ah
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Bit Function
7 Update in Progress. Read only.
0 = Time update will not occur before 2444 us
1 = Time update will occur within 2444 us
6..4 Divider Chain Control. R/W.
00x = Oscillator disabled.
010 = Normal operation (time base frequency = 32.768 KHz).
11x = Divider chain reset.
3..0 Periodic Interrupt Control. R/W. Specifies the periodic interrupt interval.
0000 = none 1000 = 3.90625 ms
0001 = 3.90625 ms 1001 = 7.8125 ms
0010 = 7.8125 ms 1010 = 15. 625 ms
0011 = 122.070 us 1011 = 31.25 ms
0100 = 244.141 us 1100 = 62.50 ms
0101 = 488.281 us 1101 = 125 ms
0110 = 976.562 us 1110 = 250 ms
0111 = 1.953125 ms 1111 = 500 ms
RTC Control Register B, Byte 0Bh
Bit Function
7
6
Time Update Enable/disable
0 = Normal operation, 1 = Disable time updating for time set
Periodic Interrupt Enable/Disable.
0 = Disable, 1 = Enable interval specified by Register A
5
4
3
2
Alarm Interrupt Enable/disable
0 = Disabled, 1 = Enabled
End-of-Update Interrupt Enable/Disable
0 = Disabled, 1 = Enabled
Reserved (read 0)
Time/Date Format Select
0 = BCD format, 1 = Binary format
0
0 = 12-hour mode, 1 = 24-hour mode
Automatic Daylight Savings Time Enable/Disable
0 = Disable
1 = Enable (Advance 1 hour on 1 st Sunday in April, retreat 1 hour on last Sunday in
October).
RTC Status Register C, Byte 0Ch
Bit Function
7 If set, interrupt output signal active (read only)
6
5
If set, indicates periodic interrupt flag
If set, indicates alarm interrupt
4 If set, indicates end-of-update interrupt
3..0 Reserved
RTC Status Register D, Byte 0Dh
Bit Function
7 RTC Power Status
0 = RTC has lost power
1 = RTC has not lost power
6..0 Reserved
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Chapter 4 System Support
Configuration Byte 0Eh, Diagnostic Status
Default Value = 00h
This byte contains diagnostic status data.
Configuration Byte 0Fh, System Reset Code
Default Value = 00h
This byte contains the system reset code.
Configuration Byte 10h, Diskette Drive Type
Bit Function
7..4 Primary (Drive A) Diskette Drive Type
3..0 Secondary (Drive B) Diskette Drive Type
Valid values for bits <7..4> and bits <3..0>:
0000 = Not installed
0001 = 360-KB drive
0010 = 1.2-MB drive
0011 = 720-KB drive
0100 = 1.44-MB/1.25-MB drive
0110 = 2.88-MB drive
(all other values reserved)
Configuration Byte 12h, Hard Drive Type
Bit Function
7..4 Primary Controller 1, Hard Drive 1 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 19h)
3..0 Primary Controller 1, Hard Drive 2 Type:
0000 = none 1000 = Type 8
0001 = Type 1 1001 = Type 9
0010 = Type 2 1010 = Type 10
0011 = Type 3 1011 = Type 11
0100 = Type 4 1100 = Type 12
0101 = Type 5 1101 = Type 13
0110 = Type 6 1110 = Type 14
0111 = Type 7 1111 = other (use bytes 1Ah)
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Configuration Byte 13h, Security Functions
Default Value = 00h
Bit Function
7 Reserved
6 QuickBlank Enable After Standby:
0 = Disable
1 = Enable
0 = Not present
1 = Present
4 Reserved
3 Diskette Boot Enable:
0 = Enable
1 = Disable
1
0
0 = Disable
1 = Enable
Network Server Mode/Security Lock Override:
0 = Disable
1 = Enable
Password State (Set by BIOS at Power-up)
0 = Not set
1 = Set
Configuration Byte 14h, Equipment Installed
Default Value (standard configuration) = 03h
Bit Function
7,6 No. of Diskette Drives Installed:
00 = 1 drive 10 = 3 drives
01 = 2 drives 11 = 4 drives
5..2 Reserved
0
0 = Coprocessor not installed
1 = Coprocessor installed
Diskette Drives Present
0 = No diskette drives installed
1 = Diskette drive(s) installed
Configuration Bytes 15h and 16h, Base Memory Size
Default Value = 280h
Bytes 15h and 16h hold a 16-bit value that specifies the base memory size in 1-KB (1024) increments. Valid base memory sizes are 512 and 640 kilobytes .
Configuration Bytes 17h and 18h, Extended Memory Size
Bytes 17h and 18h hold a 16-bit value that specifies the extended memory size in 1-KB increments.
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Chapter 4 System Support
Configuration Bytes 19h-1Ch, Hard Drive Types
Byte 19h contains the hard drive type for drive 1 of the primary controller if byte 12h bits <7..4> hold 1111b. Byte 1Ah contains the hard drive type for drive 2 of the primary controller if byte 12h bits <3..0> hold 1111b. Bytes1Bh and 1Ch contain the hard drive types for hard drives 1 and 2 of the secondary controller.
Configuration Byte 1Dh, Enhanced IDE Hard Drive Support
Default Value = F0h
Bit Function
7 EIDE - Drive C (83h)
6
5
4
EIDE - Drive D (82h)
EIDE - Drive E (81h)
EIDE - Drive F (80h)
3..0 Reserved
Values for bits <7..4> :
0 = Disable
1 = Enable for auto-configure
Configuration Byte 1Fh, Power Management Functions
Default Value = 00h
Bit Function
7..4 Reserved
3 Slow Processor Clock for Low Power Mode
0 = Processor runs at full speed
1 = Processor runs at slow speed
2 Reserved
1 Monitor Off Mode
0 = Turn monitor power off after 45 minutes in standby
1 = Leave monitor power on
0 Energy Saver Mode Indicator (Blinking LED)
0 = Disable
1 = Enable
Configuration Byte 24h, System Board Identification
Default Value = 7Eh
Configuration memory location 24h holds the system board ID.
Configuration Byte 25h, System Architecture Data
Default Value = 0Bh
Bit Function
7..4 Reserved
3 Unmapping of ROM:
0 = Allowed
1 = Not allowed
2 Reserved
1,0 Diagnostic Status Byte Address
00 = Memory locations 80C00000h-80C00004h
01 = I/O ports 878h-87Ch
11 = neither place
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Configuration Byte 26h, Auxiliary Peripheral Configuration
Default Value = 00h
Bit Function
7,6 I/O Delay Select
00 = 420 ns (default)
01 = 300 ns
10 = 2600 ns
11 = 540 ns
5
4
Alternative A20 Switching
0 = Disable port 92 mode
1 = Enable port 92 mode
Bi-directional Print Port Mode
0 = Disabled
1 = Enabled
2
1
0
0 = Color
1 = Monochrome
Hard Drive Primary/Secondary Address Select:
0 = Primary
1 = Secondary
Diskette I/O Port
0 = Primary
1 = Secondary
Diskette I/O Port Enable
0 = Primary
1 = Secondary
Configuration Byte 27h, Speed Control/External Drive
Default Value = 00h
Bit Function
0 = Max MHz
1 = Fast speed
6..0 Reserved
Configuration Byte 28h, Expanded and Base Memory, IRQ12 Select
Default Value = 00h
Bit Function
0 = Mouse
1 = Expansion bus
00 = 640 KB
01 = 512 KB
10 = 256 KB
11 = Invalid
4..0 Internal Compaq Memory:
00000 = None
00001 = 512 KB
00010 = 1 MB
00011 = 1.5 MB
.
.
11111 = 15.5 MB
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Chapter 4 System Support
Configuration Byte 29h, Miscellaneous Configuration Data
Default Value = 00h
Bit Function
7..5 Reserved
4 Primary Hard Drive Enable (Non-PCI IDE Controllers)
0 = Disable
1 = Enable
3..0 Reserved
Configuration Byte 2Ah, Hard Drive Timeout
Default Value = 02h
Bit Function
7..5 Reserved
4..0 Hard Drive Timeout (index to SIT timeout record)
Configuration Byte 2Bh, System Inactivity Timeout
Default Value = 23h
Bit Function
7 Reserved
6,5 Power Conservation Boot
00 = Reserved
01 = PC on
10 = PC off
11 = Reserved
4..0 System Inactive Timeout. (Index to SIT system timeout record)
00000 = Disabled
Configuration Byte 2Ch, ScreenSave and NUMLOCK Control
Default Value = 00h
Bit Function
7 Reserved
5
0 = Numlock off at power on
1 = Numlock on at power on
Screen Blank Control:
0 = No screen blank
1 = Screen blank w/QuickLock
4..0 ScreenSave Timeout. (Index to SIT monitor timeout record)
000000 = Disabled
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Configuration Byte 2Dh, Additional Flags
Default Value = 00h
Bit Function
7..5 Reserved
3
0 = Test memory on power up only
1 = Test memory on warm boot
POST Error Handling (BIOS Defined)
0 = Display “Press F1 to Continue” on error
1 = Skip F1 message
2..0 Reserved
Configuration Byte 2Eh, 2Fh, Checksum
These bytes hold the checksum of bytes 10h to 2Dh.
Configuration Byte 30h, 31h, Total Extended Memory Tested
This location holds the amount of system memory that checked good during the POST.
Configuration Byte 32h, Century
This location holds the Century value in a binary coded decimal (BCD) format.
Configuration Byte 33h, Miscellaneous Flags
Default Value = 80h
Bit Function
7 Memory Above 640 KB
0 = No, 1 = Yes
6 Reserved
5
4
Weitek Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
Standard Numeric Coprocessor Present:
0 = Not installed, 1 = Installed
3..0 Reserved
Configuration Byte 34h, International Language Support
Default Value = 00h
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Chapter 4 System Support
Configuration Byte 35h, APM Status Flags
Default Value = 11h
Bit Function
7..6 Power Conservation State:
00 = Ready
01 = Standby
10 = Suspend
11 = Off
5,4 Reserved
1
0
0 = Disconnected, 1 = Connected
0 = Disconnected, 1 = Connected
Real Mode Connection
0 = Disconnected, 1 = Connected
Power Management Enable:
0 = Disabled
1 = Enabled
Configuration Byte 36h, ECC POST Test Single Bit Errors
Default Value = 01h
Bit Function
7 Row 7 Error Detect
6 Row 6 Error Detect
5
4
3
2
Row 5 Error Detect
Row 4 Error Detect
Row 3 Error Detect
Row 2 Error Detect
1
0
Row 1 Error Detect
Row 0 Error Detect
0 = No single bit error detected.
1 = Single bit error detected.
Configuration Byte 37h-3Fh, Power-On Password
These eight locations hold the power-on password.
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4.7
SYSTEM MANAGEMENT
This section describes functions having to do with security, power management, temperature, and overall status. These functions are handled by hardware and firmware (BIOS) and generally configured through the Setup utility.
4.7.1 SECURITY FUNCTIONS
These systems include various features that provide different levels of security. Note that this subsection describes only the hardware functionality (including that supported by Setup) and does not describe security features that may be provided by the operating system and application software.
4.7.1.1
Power-On Password
These systems include a power-on password, which may be enabled or disabled (cleared) through a jumper on the system board. The jumper controls a GPIO input to the 82801 ICH2 that is checked during POST. The password is stored in configuration memory (CMOS) and if enabled and then forgotten by the user will require that either the password be cleared (preferable solution and described below) or the entire CMOS be cleared (refer to section 4.6).
To clear the password, use the following procedure:
1.
Turn off the system and disconnect the AC power cord from the outlet and/or system unit.
2.
Remove the cover (hood) as described in the appropriate User Guide or Maintainance And
Service Guide. Insure that all system board LEDs are off (not illuminated).
3.
Locate the password header/jumper (labeled E49 on these systems) and move the jumper from pins 1 and 2 and place on (just) pin 2 (for safekeeping).
4.
Replace the cover.
5.
Re-connect the AC power cord to the AC outlet and/or system unit.
6.
Turn on the system. The POST routine will clear and disable the password.
7.
To re-enable the password feature, repeat steps 1-6, replacing the jumper on pins 1 and 2 of header E49.
4.7.1.2
Setup Password
The Setup utility may be configured to be always changeable or changeable only by entering a password. The password is held on CMOS and, if forgotten, will require that CMOS be cleared
(refer to section 4.6).
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Chapter 4 System Support
4.7.1.3
Cable Lock Provision
These systems include a chassis cutout (on the rear panel) for the attachment of a cable lock mechanism.
4.7.1.4
I/O Interface Security
The serial, parallel, USB, and diskette interfaces may be disabled individually through the Setup utility to guard against unauthorized access to a system. In addition, the ability to write to or boot from a removable media drive (such as the diskette drive) may be enabled through the Setup utility. The disabling of the serial, parallel, and diskette interfaces are a function of the
LPC47B357 I/O controller. The USB ports are controlled through the 82801 ICH2.
4.7.1.5
Chassis Security
The Small Form Factor and Slim Desktop systems feature Smart Cover (hood) Sensor and Smart
Cover (hood) Lock mechanisms to inhibit unauthorized tampering of the system unit.
Smart Cover Sensor
The Small Form Factor and Slim Desktop systems include a plunger switch that, when the cover
(hood) is removed, closes and grounds an input of the 82801 ICH2. The battery-backed logic will record this “intrusion” event by setting a specific bit. This bit will remain set (even if the cover is replaced) until the system is powered up and the user completes the boot sequence successfully, at which time the bit will be cleared. Through Setup, the user can set this function to be used by
Alert-On-LAN and or one of three levels of support for a “cover removed” condition:
Level 0 - Cover removal indication is essentially disabled at this level. During POST, status bit is cleared and no other action is taken by BIOS.
Level 1 - During POST the message “The computer’s cover has been removed since the last system start up” is displayed and time stamp in CMOS is updated.
Level 2 - During POST the “The computer’s cover has been removed since the last system start up” message is displayed, time stamp in CMOS is updated, and the user is prompted for the administrator password.
Smart Cover Lock
The Small Form Factor and Slim Desktop systems include a solenoid-operated locking bar that, when activated, prevents the cover (hood) from being removed. The GPIO ports 44 and 45 of the
LPC47B357 I/O controller provide the lock and unlock signals to the solenoid. A locked hood may be bypassed by removing special screws that hold the locking mechanism in place. The special screws are removed with the Compaq Smart Cover Lock Failsafe Key (Compaq p/n xxxxxx).
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4.7.2 POWER MANAGEMENT
This system provides baseline hardware support of ACPI- and APM-compliant firmware and software. Key power-consuming components (processor, chipset, I/O controller, and fan) can be placed into a reduced power mode either automatically or by user control. The system can then be brought back up (“wake-up”) by events defined by the ACPI specification. The ACPI wake-up events supported by this system are listed as follows:
ACPI Wake-Up Event
Power Button
RTC Alarm
Wake On LAN (w/NIC)
Serial Port Ring
System Wakes From
Suspend or soft-off
Suspend or soft-off
Suspend or soft-off
Suspend or soft-off
4.7.3 SYSTEM STATUS
These systems provide a visual indication of system boot and ROM flash status through the keyboard LEDs and operational status using bi-colored power and hard drive activity LEDs as indicated in Tables 4-15 and 4-16 respectively.
NOTE: The LED indications listed in Table 4-15 are valid only for PS/2-type keyboards. A USB keyboard will not provide LED status for the listed events, although audible (beep) indications will occur.
Table 4-15. System Boot/ROM Flash Status LED Indications
Table 4-15.
System Boot/ROM Flash Status LED Indications
Event
System memory failure [1]
Graphics controller failure [2]
System failure prior to graphics cntlr. initialization
[3]
ROMPAQ diskette not present, faulty, or drive prob.
Password prompt
Invalid ROM detected - flash failed
Keyboard locked in network mode
Successful boot block ROM flash
NOTES:
[1] Accompanied by 1 short, 2 long audio beeps
[2] Accompanied by 1 long, 2 short audio beeps
[3] Accompanied by 2 long, 1 short audio beeps
NUM Lock
LED
Blinking
Off
Off
On
Off
Blinking [4]
Blinking [5]
On [6]
CAPs Lock
LED
Off
Blinking
Off
Off
On
Blinking [4]
Blinking [5]
On [6]
Scroll Lock
LED
Off
Off
Blinking
Off
Off
Blinking [4]
Blinking [5]
On [6]
[4] All LEDs will blink in sync twice, accompanied by 1 long and three short audio beeps
[5] LEDs will blink in sequence (NUM Lock, then CAPs Lock, then Scroll Lock)
[6] Accompanied by rising audio tone.
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Table 4-16. System Operational Status LED Indications
Table 4-16.
System Operational Status LED Indications
System Status
S0: System on (normal operation)
S1: Suspend
S3: Suspend to RAM
S4: Suspend to disk
S5: Soft off
Processor not seated
CPU thermal shutdown
ROM error
Power supply crowbar activated
System off
Power
LED
Steady green
Blinks green @ 1 Hz
Blinks green @ 1 Hz
Blinks green @ 0.5 Hz
Off - clear
Steady red
Blinks red @ 4 Hz
Blinks red @ 1 Hz
Blinks red @ .5 Hz
Off
Hard Drive
LED
Green w/HD activity
Off
Off
Off
Off
Off
Off
Off
Off
Off
4.7.4 THERMAL SENSING AND COOLING
All systems feature a variable-speed fan as part of the power supply assembly. All systems also provide a system board connection for a processor’s heat sink-mounted fan (standard on all Small
Form Factor and on some Slim Desktop and Configurable Minitower units). Slim Desktop and
Configurable Minitower systems provide an auxiliary chassis fan. All fans are controlled through temperature sensing logic both on the system board and in the power supply, with slight differences between the Small Form Factor (Figure 4-11) and the Slim Desktop / Configurable
Minitower (Figure 4-12) systems.
An ASIC monitors a thermal diode internal to the processor and provides a Fan CMD signal that the Speed Control logic uses to vary the speed of the fan(s) through the negative terminal of the fan(s). The turning off of the fan(s) as the result from the system being placed into a Sleep condition is initiated by the ASIC asserting the Fan Off- signal, which results in the On/Off
Control logic shutting off the +12 volts to the fan(s).
The main differences between the system types are as follows:
♦
In the Small Form Factor system the processor fan (if installed) is controlled only by the
ASIC and not affected by a power supply thermal condition
♦
In the Slim Desktop/Configurable Minitower systems all fans are speed-controlled by the
ASIC through the power supply so that a thermal condition of the processor or power supply will affect all fans simultaneously.
Typical cooling conditions include the following:
1.
Normal – Low fan speed.
2.
Hot processor – ASIC directs Speed Control logic to increase speed of fan(s).
3.
Hot power supply – Power supply increases speed of fan(s).
4.
Sleep state – Fan(s) turned off. Hot processor or power supply will result in starting fan(s).
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High and low thermal parameters are programmed into the ASIC by BIOS during POST. If the high thermal parameter is reached then the fan(s) will be turned on full speed and the Thermsignal will be asserted. The asserted Therm- signal can, with the proper software setup, be used by the 82801 ICH2 to initiate an AOL message for transmission over a network (refer to Network
Interface Controller subsection in Chapter 5).
NOTE: These systems do not support thermister-based fans used on earlier products.
+12 VDC
Processor
ICH2
Speed
Control
Fan
Sense [1]
SMBus
Sensing
ASIC
Fan CMD
Fan Off-
NOTES:
Therm-
Interrupt
82801
ICH2
[1] Will be +12 VDC if fan is connected.
Heat Sink Fan Header
P70
(-)
1
(+)
2
3 Power Supply Assembly
P1
13
10
Fan
SPD
Fan
Off
Speed
Control
On/Off
Control
(-)
(+)
PS Fan
Figure 4-11. Small Form Factor Fan Control Block Diagram
Processor
Chassis Fan
Header
(+)
4
(-)
3
2
Heat Sink Fan Header
P70
(-)
1
(+)
2
3
ICH2
SMBus
Sensing
ASIC
Fan
Sense [1]
Fan CMD
Fan Off-
On/Off
Control
P1
24
12
Fan
Sink
Fan
SPD
Fan
Off
Power Supply Assembly
Speed
Control
8
NOTES:
Therm- 82801
ICH2
[1] Will be +12 VDC if chassis or boxed fan is connected and turned on.
On/Off
Control
(-)
(+)
PS Fan
Figure 4-12. Slim Desktop/Configurable Minitower Fan Control Block Diagram
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Chapter 4 System Support
4.8
REGISTER MAP AND MISCELLANEOUS FUNCTIONS
This section contains the system I/O map and information on general-purpose functions of the
ICH2 and I/O controller.
4.8.1 SYSTEM I/O MAP
Table 4-17 lists the fixed addresses of the input/output (I/O) ports.
Table 4-17. System I/O Map
Table 4-17.
System I/O Map
I/O Port Function
0020..002Dh
002E, 002Fh
Interrupt Controller 1
Index, Data Ports to LPC47B357 I/O Controller (primary)
004E, 004Fh
0050..0052h
0060..0067h
Index, Data Ports to LPC47B357 I/O Controller (secondary)
Timer / Counter
Microcontroller, NMI Controller (alternating addresses)
0092h
00A0..00B1h
00B2h, 00B3h
Port A, Fast A20/Reset Generator
Interrupt Controller 2
APM Control/Status Ports
0170..0177h
01F0..01F7h
0278..027Fh
02E8..02EFh
02F8..02FFh
0370..0377h
0376h
0378..037Fh
IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
IDE Controller 1 (active only if standard I/O space is enabled for secondary drive)
Parallel Port (LPT2)
Serial Port (COM4)
Serial Port (COM2)
Diskette Drive Controller Secondary Address
IDE Controller 2 (active only if standard I/O space is enabled for primary drive)
Parallel Port (LPT1)
03BC..03BEh
03E8..03EFh
03F0..03F5h
03F6h
03F8..03FFh
Parallel Port (LPT3)
Serial Port (COM3)
Diskette Drive Controller Primary Addresses
IDE Controller 1 (active only if standard I/O space is enabled for sec. drive)
Serial Port (COM1)
04D0, 04D1h
0678..067Fh
0778..077Fh
07BC..07BEh
0CF8h
0CF9h
0CFCh
NOTE:
Interrupt Controller
Parallel Port (LPT2)
Parallel Port (LPT1)
Parallel Port (LPT3)
PCI Configuration Address (dword access only )
Reset Control Register
PCI Configuration Data (byte, word, or dword access)
Assume unmarked gaps are unused, reserved, or used by functions that employ variable I/O address mapping. Some ranges may include reserved addresses.
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4.8.2 82801 ICH2 GENERAL PURPOSE FUNCTIONS
The 82801 ICH2 component includes a number of single and multi-purpose pins available as general-purpose input/output (GPIO) ports. The GPIO ports are configured (enabled/disabled) during POST by BIOS through the PCI configuration registers of the ICH2’s LPC I/F Bridge
(82801, function 0). The GPIO ports are controlled through 64 bytes of I/O space that is mapped during POST. Table 4-18 lists the utilization of the ICH2’s GPIO ports in these systems.
Table 4-18 lists the GPIO registers for the LPC47B357.
Table 4-18. 82801 ICH2 GPIO Register Utilization
Table 4-18.
82801 ICH2 GPIO Register Utilization
GPIO Port # Function
2 IRQE-
3 IRQF-
4 IRQG-
5 IRQH-
7 --
8 --
12 TAFI ASIC Interrupt
13 SMI
18 --
19 --
20 --
21 --
22 --
23 --
24 --
25 --
27 --
Direction
I
I
I
I
I
I
I
NC
NC
I
I
NC
NC
NC
NC
NC
NC
NC
NC
NC
I
NOTE:
NC = not connected
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Chapter 4 System Support
4.8.3 LPC47B357 I/O CONTROLLER FUNCTIONS
The LPC47B357 I/O controller contains various functions such as the keyboard/mouse interfaces, diskette interface, serial interfaces, and parallel interface. While the control of these interfaces uses standard AT-type I/O addressing (as described in chapter 5) the configuration of these functions uses indexed ports unique to the LPC47B357. In these systems, hardware strapping selects I/O addresses 02Eh and 02Fh at reset as the Index/Data ports for accessing the logical devices within the LPC47B357.
Table 4-19 lists the PnP standard control registers for the LPC47B357.
Table 4-19 LPC47B357 Control Registers
Table 4-19.
LPC47B357 I/O Controller Control Registers
Index Function
03h Reserved
07h Logical Device (Interface) Select:
00h = Diskette Drive I/F
01h = Reserved
02h = Reserved
03h = Parallel I/F
04h = Serial I/F (UART 1/Port A)
05h = Serial I/F (UART 2/Port B)
06h = Reserved
07h = Keyboard I/F
08h = Reserved
09h = Reserved
0Ah = Runtime Registers (GPIO Config.)
0Bh = Reserved
20h Super I/O ID Register (SID)
21h Revision
22h
23h
Logical Device Power Control
Logical Device Power Management
24h PLL / Oscillator Control
25h Reserved
26h Configuration Address (Low Byte)
27h Configuration Address (High Byte)
28-2Fh Reserved
NOTE:
00h
00h
56h
--
00h
00h
04h
For a detailed description of registers refer to appropriate SMC documentation.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The desired interface
(logical device) is initiated by firmware selecting logical device number of the 47B347 using the following sequence:
1.
Write 07h to I/O register 2Eh.
2.
Write value of logical device to I/O register 2Fh.
3.
Write 30h to I/O register 2Eh.
4.
Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase.
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4.8.3.1
LPC47B357 GPIO Utilization
The LPC47B357 I/O Controller provides 62 general-purpose pins that can be individually configured for specific purposes. These pins are configured through the Runtime registers (logical device 0Ah) during the system’s configuration phase of the boot sequence by the BIOS.
Table 4-20 lists the GPIO registers for the LPC47B357. Note that not all ports are listed as this table defines only the custom implementation of GPIO ports. Refer to SMC documentation for standard usage of unlisted GPIO ports.
Table 4-20. LPC47B357 GPIO Register Utilization
Table 4-20.
LPC47B357 GPIO Port Utilization
GPIO Function Direction
10
11
Board rev 1
Board rev 0
12 --
13 PME-
14 WOL
15 Events
16
17
20
Fan sense
LED test
Pri. IDE 80-pin Cable Detect
21 Sec. IDE 80-pin Cable Detect
22 --
30
31
32
33
34
23
24
25
Backplane board ID 0
BIOS fail for AOL
Backplane board ID 1
26 Processor Present
27 --
PS LED Color Grn
PS LED Blink
Thermal Trip
2 MB Media ID
FWH Write Protect
35 FWH Reset
36 Diskette A
37 Diskette Select A
I
I
I
NC
I
O
I
I
I
I
I
42
43
45
60
61
62
63
64
66
67
70
ICH2 SCI
--
Hood Unlock [1]
PCI Slot Reset
AGP Slot Reset
PWR Button In
SLP S3
SLP S5
PWR Button Out
PS On
Remote Off
I 71 Backplane Detect 1
NC 72 Backplane 2
O 73 --
O
I
I
O
74
75
76
85
NIC PHY Disable
--
--
Pwr SEL
O 86 S3 3.3 VDC On
O -- --
O -- --
NOTE:
[1] Not implemented on Configurable Minitower models.
O
NC
I
I
O
O
O
I
I
I
I
NC
O
NC
NC
O
O
O
I
I
!
O
--
--
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Chapter 4 System Support
4.8.3.2
I/O Controller Miscellaneous Functions
The systems covered in this guide utilize the following specialized functions built into the LPC
47B357 I/O Controller:
♦
Power/Hard drive LED control – The I/O controller provides color and blink control for the front panel LEDs used for indicating system events as listed below:
System Status
S0: System on (normal operation)
S1: Suspend
S3: Suspend to RAM
S4: Suspend to disk
S5: Soft off
Backplane board not seated
Processor not seated
CPU thermal shutdown
ROM error
Power supply crowbar activated
System off
Power LED
Steady green
Blinks green @ 1 Hz
Blinks green @ 1 Hz
Blinks green @ 0.5 Hz
Off - clear
Steady red
Steady red
Blinks red @ 4 Hz
Blinks red @ 1 Hz
Blinks red @ 0.5 Hz
Off
HD LED
Green w/HD activity
Off
Off
Off
Off
Steady red
Off
Off
Off
Off
Off
♦
Intruder sensing – Used on Small Form Factor and Slim Desktop models, battery-backed Dlatch logic internal to the LPC47B357 is connected to the hood sensor switch to record hood
(cover) removal.
♦
Hood lock/unlock – Used on Small Form Factor and Slim Desktop models, logic internal to the LPC47B34x controls the lock bar mechanism.
♦
I/O security – The parallel, serial, and diskette interfaces may be disabled individually by software and the LPC47B357’s disabling register locked. If the disabling register is locked, a system reset through a cold boot is required to gain access to the disabling (Device Disable) register.
♦
Processor present/speed detection – One of the battery-back general-purpose inputs (GPI26) of the LPC47B357 detects if the processor has been removed. The occurrence of this event is passed to the ICH2 that will, during the next boot sequence, initiate the speed selection routine for the processor. The speed selection function replaces the manual DIP switch configuration procedure required on previous systems.
♦
Legacy/ACPI power button mode control – The LPC47B357 receives the pulse signal from the system’s power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to chapter 7 for more information regarding power management.
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Technical Reference Guide
Chapter 5
INPUT/OUTPUT INTERFACES
5. Chapter 5 INPUT/OUTPUT INTERFACES
5.1
INTRODUCTION
This chapter describes the standard (i.e., system board) interfaces that provide input and output
(I/O) porting of data and specifically discusses interfaces that are controlled through I/O-mapped registers. The following I/O interfaces are covered in this chapter:
♦
Enhanced IDE interface (5.2)
♦
Diskette drive interface (5.3)
♦
Serial interfaces (5.4)
♦
Parallel interface (5.5)
♦
Keyboard/pointing device interface (5.6)
♦
Universal serial bus interface (5.7)
♦
Audio subsystem (5.8)
♦
Network interface controller (5.9) page 5-1 page 5-4 page 5-8 page 5-11 page 5-16 page 5-22 page 5-26 page 5-32
5.2
ENHANCED IDE INTERFACE
The enhanced IDE (EIDE) interface consists of primary and secondary controllers integrated into the 82801 ICH2 component of the chipset. Two 40-pin IDE connectors (one for each controller) are included on the system board. Each controller can be configured independently for the following modes of operation:
♦
Programmed I/O (PIO) mode – CPU controls drive transactions through standard I/O mapped registers of the IDE drive.
♦
8237 DMA mode – CPU offloads drive transactions using DMA protocol with transfer rates up to 16 MB/s.
♦
Ultra ATA/100 mode – Preferred bus mastering source-synchronous protocol providing transfer rates of 100 MB/s.
NOTE: These systems include 80-conductor data cables required for UATA/66 and /100 modes.
5.2.1 IDE PROGRAMMING
The IDE interface is configured as a PCI device during POST and controlled through I/O-mapped registers at runtime.
Compaq Deskpro Personal Computers 5-1
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Chapter 5 Input/Output Interfaces
Hard drives types not found in the ROM’s parameter table are automatically configured as to
(soft)type by DOS as follows:
Primary controller: drive 0, type 65; drive 1, type 66
Secondary controller: drive 0, type 68; drive 1, type 15
Non-DOS (non-Windows) operating systems may require using Setup (F10) for drive configuration.
5.2.1.1 IDE Configuration Registers
The IDE controller is configured as a PCI device with bus mastering capability. The PCI configuration registers for the IDE controller function (PCI device #31, function #1) are listed in
Table 5-1.
Table 5–1. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82801, Device 31/Function 1)
PCI Conf.
Addr.
02-03h
04-05h
06-07h
Register
Device ID
PCI Command
PCI Status
09h Programming
0Ah Sub-Class
0Bh
0Dh
0Eh
Base Class Code
Master Latency Timer
Header Type
NOTE:
Reset
Value
PCI Conf.
Addr. Register
BMIDE Base Address
Subsystem Vender ID
Subsystem ID
Reset
Value
0’s
1 244Bh 20-23h
0000h
0280h
2C, 2Dh
2E, 2Fh
0000h
0000h
80h 40-43h Pri./Sec. IDE Timing
0’s
0’s
44h Slave 00h
01h
00h
00h
48h
4A-4Bh
54h
Assume unmarked gaps are reserved and/or not used.
Sync. DMA Control
Sync. DMA Timing
EIDE I/O Config.Register
00h
0000h
00h
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the registers listed in Table 5-2.
These registers occupy 16 bytes of variable I/O space set by software and indicated by PCI configuration register 20h in the previous table.
Table 5–2. IDE Bus Master Control Registers
I/O Addr.
Offset
00h
02h
04h
08h
0Ah
0Ch
NOTE:
Table 5-2.
IDE Bus Master Control Registers
Size
(Bytes)
1
1
4
1
2
4
Register
Bus Master IDE Command (Primary)
Bus Master IDE Status (Primary)
Default
Value
00h
00h
Bus Master IDE Descriptor Pointer (Pri.)
Bus Master IDE Command (Secondary)
0000 0000h
00h
Bus Master IDE Status (Secondary) 00h
Bus Master IDE Descriptor Pointer (Sec.) 0000 0000h
Unspecified gaps are reserved, will return indeterminate data, and should not be written to.
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Technical Reference Guide
5.2.2 IDE CONNECTOR
This system uses a standard 40-pin connector for the primary IDE device and connects (via a cable) to the hard drive installed in the right side drive bay. Note that some signals are re-defined for UATA/33 and UATA/66 modes, which require a special 80-conductor cable (supplied) designed to reduce cross-talk. Device power is supplied through a separate connector.
Figure 5-1. 40-Pin Primary IDE Connector (on system board).
Table 5–3. 40-Pin Primary IDE Connector Pinout
Table 5-3.
40-Pin Primary IDE Connector Pinout
Pin Signal
8
9
10
11
12
13
14
2 GND Ground
3 DD7 Data Bit <7>
4
5
6
7
DD8
DD6
DD9
DD5
Data Bit <8>
Data Bit <6>
Data Bit <9>
Data Bit <5>
DD10
DD4
DD11
DD3
DD12
DD2
DD13
Data Bit <10>
Data Bit <4>
Data Bit <11>
Data Bit <3>
Data Bit <12>
Data Bit <2>
Data Bit <13>
15
16
17
DD1
DD14
DD0
18
19
DD15
GND
20 --
Data Bit <1>
Data Bit <14>
Data Bit <0>
Data Bit <15>
Ground
Key
30
31
32
33
34
23
24
25
26
27
28
29
IOW-
GND
IOR-
GND
IORDY
CSEL
DAK-
GND
IRQn
IO16-
DA1
DSKPDIAG
35
36
37
DA0
DA2
CS0-
38
39
CS1-
HDACTIVE-
40 GND
Ground
I/O Write [1]
Ground
I/O Read [2]
Ground
I/O Channel Ready [3]
Cable Select
DMA Acknowledge
Ground
Interrupt Request [4]
16-bit I/O
Address 1
Pass Diagnostics
Address 0
Address 2
Chip Select
Chip Select
Drive Active (front panel LED) [5]
Ground
NOTES:
[1] On UATA/33 and higher modes, re-defined as STOP.
[2] On UATA/33 and higher mode reads, re-defined as DMARDY-.
On UATA/33 and higher mode writes, re-defined as STROBE.
[3] On UATA/33 and higher mode reads, re-defined as STROBE-.
On UATA/33 and higher mode writes, re-defined as DMARDY-.
[4] Primary connector wired to IRQ14, secondary connector wired to IRQ15.
[5] Pin 39 is used for spindle sync and drive activity (becomes SPSYNC/DACT-)
when synchronous drives are connected.
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Chapter 5 Input/Output Interfaces
5.3
DISKETTE DRIVE INTERFACE
The diskette drive interface supports up to two diskette drives, each of which use a common cable connected to a standard 34-pin diskette drive connector. All models come standard with a 3.5-inch
1.44-MB diskette drive installed as drive A. The drive designation is determined by which connector is used on the diskette drive cable. The drive attached to the end connector is drive A while the drive attached to the second (next to the end) connector) is drive B.
On all models, the diskette drive interface function is integrated into the LPC47B357 super I/O component. The internal logic of the I/O controller is software-compatible with standard 82077type logic. The diskette drive controller has three operational phases in the following order:
♦
Command phase - The controller receives the command from the system.
♦
Execution phase - The controller carries out the command.
♦
Results phase - Status and results data is read back from the controller to the system.
The Command phase consists of several bytes written in series from the CPU to the data register
(3F5h/375h). The first byte identifies the command and the remaining bytes define the parameters of the command. The Main Status register (3F4h/374h) provides data flow control for the diskette drive controller and must be polled between each byte transfer during the Command phase.
The Execution phase starts as soon as the last byte of the Command phase is received. An
Execution phase may involve the transfer of data to and from the diskette drive, a mechnical control function of the drive, or an operation that remains internal to the diskette drive controller.
Data transfers (writes or reads) with the diskette drive controller are by DMA, using the DRQ2 and DACK2- signals for control.
The Results phase consists of the CPU reading a series of status bytes (from the data register
(3F5h/375h)) that indicate the results of the command. Note that some commands do not have a
Result phase, in which case the Execution phase can be followed by a Command phase.
During periods of inactivity, the diskette drive controller is in a non-operation mode known as the
Idle phase.
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5.3.1 DISKETTE DRIVE PROGRAMMING
Programming the diskette drive interface consists of configuration, which occurs typically during
POST, and control, which occurs at runtime.
5.3.1.1 Diskette Drive Interface Configuration
The diskette drive controller must be configured for a specific address and also must be enabled before it can be used. Address selection and enabling of the diskette drive interface are affected by firmware through the PnP configuration registers of the 47B357 I/O controller during POST.
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data) after the configuration phase has been activated by writing 55h to I/O port 2Eh. The diskette drive I/F is initiated by firmware selecting logical device 0 of the 47B357 using the following sequence:
1.
Write 07h to I/O register 2Eh.
2.
Write 00h to I/O register 2Fh (this selects the diskette drive I/F).
3.
Write 30h to I/O register 2Eh.
4.
Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase. The diskette drive I/F configuration registers are listed in the following table:
Table 5–4. Diskette Drive Controller Configuration Registers
Table 5-4.
Diskette Drive Interface Configuration Registers
Index
Address Function
30h Activate
60-61h Base Address
70h
74h
Interrupt Select
DMA Channel Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
01h
03F0h
06h
02h
02h
00h
R/W FFh
R/W 00h
R/W 00h
For detailed configuration register information refer to the SMSC data sheet for the LPC47B357
I/O component.
5.3.1.2 Diskette Drive Interface Control
The BIOS function INT 13 provides basic control of the diskette drive interface. The diskette drive interface can be controlled by software through the LPC47B357’s I/O-mapped registers listed in Table 5-5. The diskette drive controller of the LPC47B357 operates in the PC/AT mode in these systems.
Table 5–5. Diskette Drive Interface Control Registers
Table 5-5.
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Chapter 5 Input/Output Interfaces
Pri.
Addr.
3F2h
3F3h
3F4h
Sec.
Addr.
Diskette Drive Interface Control Registers
Register
<7> Interrupt pending
<6> Reserved (always 1)
<5> STEP pin status (active high)
<4> TRK 0 status (active high)
<3> HDSEL status (0 = side 0, 1 = side 1)
<2> INDEX status (active high)
<1> WR PRTK status (0 = disk is write protected)
<0> Direction (0 = outward, 1 = inward)
<7,6> Reserved (always 1’s)
<5> DOR bit 0 status
<4> Write data toggle
<3> Read data toggle
<2> WGATE status (active high)
<1,0> MTR 2, 1 ON- status (active high)
372h Digital Output Register (DOR):
<7,6> Reserved
<5,4> Motor 1, 0 enable (active high)
<3> DMA enable (active high)
<2> Reset (active low)
<1,0> Drive select (00 = Drive 1, 01 = Drive 2, 10 = Reserved, 11 = Tape drive)
373h Tape Drive Register (available for compatibility)
374h Main Status Register (MSR):
<7> Request for master (host can transfer data) (active high)
<6> Transfer direction (0 – write, 1 = read)
<5> non-DMA execution (active high)
<4> Command busy (active high)
<3,2> Reserved
<1,0> Drive 1, 2 busy (active high)
Data Rate Select Register (DRSR):
<7> Software reset (active high)
<6> Low power mode enable (active high)
<5> Reserved (0)
<4..2> Precompensation select (default = 000)
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1
Mb/s)
<7..0> Data
3F6h 376h Reserved
3F7h 377h Digital Input Register (DIR):
<7> DSK CHG status (records opposite value of pin)
<6..0> Reserved (0’s)
Configuration Control Register (CCR):
<7..2> Reserved
<1,0> Data rate select (00 = 500 Kb/s, 01 = 300 Kb/s, 10 = 250 Kb/s, 11 = 2/1
Mb/s)
NOTE: The most recently written data rate value to either DRSR or CCR will be in effect.
R/W
R
R
R/W
R/W
W
R
R/W
--
R
W
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5.3.2 DISKETTE DRIVE CONNECTOR
This system uses a standard 34-pin connector (refer to Figure 5-2 and Table 5-6 for the pinout) for diskette drives. Drive power is supplied through a separate connector.
2 4
1
6
5
8
7
10 12 14 16 18 20 22 24 26 28 30 32 34
9 11 13 15 17 19 21 23 25 27 29 31 33
Figure 5-2. 34-Pin Diskette Drive Connector.
Table 5–6. 34-Pin Diskette Drive Connector Pinout
Table 5-6.
34-Pin Diskette Drive Connector Pinout
Pin Signal
1
2
GND Ground
LOW DEN- Low density select
3 --- (KEY)
18
19
20
DIR-
GND
STEP-
7
8
9
10
11
4 MEDIA ID- Media identification
5 GND Ground
Drive 4 select
SEL-
GND
INDEX-
GND
MTR 1 ON-
Ground
Media index is detected
Ground
Activates drive motor
13
15
16
17
GND Ground
Drive 2 select
SEL-
GND Ground
Drive 1 select
SEL-
GND Ground
MTR 2 ON- Activates drive motor
GND Ground
21
23
24
25
26
27
28
29
30
31
32
33
34
GND
GND
WR ENABLE-
GND
TRK 00-
GND
WR PRTK-
GND
RD DATA-
GND
SIDE SEL-
GND
DSK CHG-
Drive head direction control
Ground
Drive head track step control
Ground
Ground
Enable for WR DATA-
Ground
Heads at track 00 indicator
Ground
Media write protect status
Ground
Data and clock read off disk
Ground
Head select (side 0 or 1)
Ground
Drive door opened indicator
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Chapter 5 Input/Output Interfaces
5.4
SERIAL INTERFACE
All models include two serial interfaces to transmit and receive asynchronous serial data with external devices. The serial interface function is provided by the LPC47B357 I/O controller component that includes two NS16C550-compatible UARTs.
Each UART supports the standard baud rates up through 115200, and also special high speed rates of 239400 and 460800 baud. The baud rate of the UART is typically set to match the capability of the connected device. While most baud rates may be set at runtime, baud rates 230400 and
460800 must be set during the configuration phase.
5.4.1 RS-232 INTERFACE
On the legacy-light system, the UART is associated with a DB-9 connector that complies with
EIA standard RS-232-C. The DB-9 connector is shown in the following figure and the pinout of the connector is listed in Table 5-5.
Figure 5-3. Serial Interface Connector (Male DB-9 as viewed from rear of chassis)
Table 5–7. DB-9 Serial Connector Pinout
Table 5-7.
DB-9 Serial Connector Pinout
Pin Signal
1 CD
2
3
4
RX Data
TX Data
DTR
Carrier Detect
Receive Data
Transmit Data
Data Terminal Ready
5 GND Ground
6
7
8
9
DSR
RTS
CTS
RI
-- --
Data Set Ready
Request To Send
Clear To Send
Ring Indicator
--
The standard RS-232-C limitation of 50 feet (or less) of cable between the DTE (computer) and
DCE (modem) should be followed to minimize transmission errors. Higher baud rates may require shorter cables.
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5.4.2 COM1 PORT HEADER
The Small Form Factor system board includes a header that connects to the COM1 port’s DB-9 connector on the rear chassis I/O panel through a cable assembly. The header pinout is shown in the following figure:
CD 1
RX Data 2
TX Data 3
DTR 4
Gnd 5
6 DSR
7 RTS
8 CTS
9 RI
Figure 5-4. COM1 Serial Interface Header (Small Form Factor system board only)
5.4.3 SERIAL INTERFACE PROGRAMMING
Programming the serial interfaces consists of configuration, which occurs during POST, and control, which occurs during runtime.
5.4.3.1 Serial Interface Configuration
The serial interface must be configured for a specific address range (COM1, COM2, etc.) and also must be activated before it can be used. Address selection and activation of the serial interface are affected through the PnP configuration registers of the LPC47B357 I/O controller.
The serial interface configuration registers are listed in the following table:
Table 5–8. Serial Interface Configuration Registers
Index
Address Function
30h Activate
60h
61h
Table 5-8.
Serial Interface Configuration Registers
Base Address MSB
Base Address LSB
NOTE:
Refer to LPC47B357 data sheet for detailed register information.
R/W
R/W
R/W
R/W
R/W
R/W
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Chapter 5 Input/Output Interfaces
5.4.3.2 Serial Interface Control
The BIOS function INT 14 provides basic control of the serial interface. The serial interface can be directly controlled by software through the I/O-mapped registers listed in Table 5-9.
Table 5–9. Serial Interface Control Registers
Table 5-9.
Serial Interface Control Registers
COM1
Addr.
3F8h
COM2
Addr.
Register
2F8h Receive Data Buffer
3F9h
Transmit Data Buffer
Baud Rate Divisor Register 0 (when bit 7 of Line Control Reg. Is set)
2F9h Baud Rate Divisor Register 1 (when bit 7 of Line Control Reg. Is set)
Interrupt Enable Register
3FAh 2FAh Interrupt ID Register
FIFO Control Register
3FBh 2FBh Line Control Register
3FCh 2FCh Modem Control Register
3FDh 2FDh Line Status Register
R/W
R
W
W
W
R/W
R
W
R/W
R/W
R
R
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5.5
PARALLEL INTERFACE
The legacy-light models include a parallel interface for connection to a peripheral device that has a compatible interface, the most common being a printer. The parallel interface function is integrated into theLPC47B277 I/O controller component and provides bi-directional 8-bit parallel data transfers with a peripheral device. The parallel interface supports three main modes of operation:
♦
Standard Parallel Port (SPP) mode
♦
Enhanced Parallel Port (EPP) mode
♦
Extended Capabilities Port (ECP) mode
These three modes (and their submodes) provide complete support as specified for an IEEE 1284 parallel port.
5.5.1 STANDARD PARALLEL PORT MODE
The Standard Parallel Port (SPP) mode uses software-based protocol and includes two sub-modes of operation, compatible and extended, both of which can provide data transfers up to 150 KB/s.
In the compatible mode, CPU write data is simply presented on the eight data lines. A CPU read of the parallel port yields the last data byte that was written.
The following steps define the standard procedure for communicating with a printing device:
1.
The system checks the Printer Status register. If the Busy, Paper Out, or Printer Fault signals are indicated as being active, the system either waits for a status change or generates an error message.
2.
The system sends a byte of data to the Printer Data register, then pulses the printer STROBE signal (through the Printer Control register) for at least 500 ns.
3.
The system then monitors the Printer Status register for acknowledgment of the data byte before sending the next byte.
In extended mode, a direction control bit (CTR 37Ah, bit <5>) controls the latching of output data while allowing a CPU read to fetch data present on the data lines, thereby providing bi-directional parallel transfers to occur.
The SPP mode uses three registers for operation: the Data register (DTR), the Status register
(STR) and the Control register (CTR). Address decoding in SPP mode includes address lines A0 and A1.
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5.5.2 ENHANCED PARALLEL PORT MODE
In Enhanced Parallel Port (EPP) mode, increased data transfers are possible (up to 2 MB/s) due to a hardware protocol that provides automatic address and strobe generation. EPP revisions 1.7 and
1.9 are both supported. For the parallel interface to be initialized for EPP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with EPP mode. If compatible, then EPP mode can be used. In EPP mode, system timing is closely coupled to EPP timing. A watchdog timer is used to prevent system lockup.
Five additional registers are available in EPP mode to handle 16- and 32-bit CPU accesses with the parallel interface. Address decoding includes address lines A0, A1, and A2.
5.5.3 EXTENDED CAPABILITIES PORT MODE
The Extended Capabilities Port (ECP) mode, like EPP, also uses a hardware protocol-based design that supports transfers up to 2 MB/s. Automatic generation of addresses and strobes as well as Run
Length Encoding (RLE) decompression is supported by ECP mode. The ECP mode includes a bidirectional FIFO buffer that can be accessed by the CPU using DMA or programmed I/O. For the parallel interface to be initialized for ECP mode, a negotiation phase is entered to detect whether or not the connected peripheral is compatible with ECP mode. If compatible, then ECP mode can be used.
Ten control registers are available in ECP mode to handle transfer operations. In accessing the control registers, the base address is determined by address lines A2-A9, with lines A0, A1, and
A10 defining the offset address of the control register. Registers used for FIFO operations are accessed at their base address + 400h (i.e., if configured for LPT1, then 378h + 400h = 778h).
The ECP mode includes several sub-modes as determined by the Extended Control register. Two submodes of ECP allow the parallel port to be controlled by software. In these modes, the FIFO is cleared and not used, and DMA and RLE are inhibited.
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5.5.4 PARALLEL INTERFACE PROGRAMMING
Programming the parallel interface consists of configuration, which typically occurs during POST, and control, which occurs during runtime.
5.5.4.1 Parallel Interface Configuration
The parallel interface must be configured for a specific address range (LPT1, LPT2, etc.) and also must be enabled before it can be used. When configured for EPP or ECP mode, additional considerations must be taken into account. Address selection, enabling, and EPP/ECP mode parameters of the parallel interface are affected through the PnP configuration registers of the
LPC47B357 I/O controller. Address selection and enabling are automatically done by the BIOS during POST but can also be accomplished with the Setup utility and other software.
The parallel interface configuration registers are listed in the following table:
Table 5–10. Parallel Interface Configuration Registers
Table 5-10.
Parallel Interface Configuration Registers
Index
Address Function
30h Activate
60h Base Address MSB
61h Base Address LSB
74h
F1h
DMA Channel Select
Mode Register 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
Value
00h
00h
00h
00h
04h
00h
00h
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Chapter 5 Input/Output Interfaces
5.5.4.2 Parallel Interface Control
The BIOS function INT 17 provides simplified control of the parallel interface. Basic functions such as initialization, character printing, and printer status are provide by subfunctions of INT 17.
The parallel interface is controllable by software through a set of I/O mapped registers. The number and type of registers available depends on the mode used (SPP, EPP, or ECP). Table 5-11 lists the parallel registers and associated functions based on mode.
Table 5–11. Parallel Interface Control Registers
Table 5-11.
Parallel Interface Control Registers
I/O
Address Register
Base Data
Base + 1h Printer Status
Base + 2h
Base + 3h
Base + 4h
Base + 5h
Base + 6h
Control
Address
Data Port 0
Data Port 1
Data Port 2
Base + 7h
Base + 400h
Base + 400h
Base + 400h
Base + 400h
Base + 401h
Base + 402h
Data Port 3
Parallel Data FIFO
ECP Data FIFO
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
SPP
Mode
Ports
LPT1,2,3
LPT1,2,3
--
--
--
--
--
--
--
--
--
--
--
Base Address:
LPT1 = 378h
LPT2 = 278h
LPT3 = 3BCh
EPP
Mode
Ports
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
LPT1,2
--
--
--
--
--
--
ECP
Mode
Ports
LPT1,2,3
LPT1,2,3
--
--
--
--
--
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
LPT1,2,3
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5.5.5 PARALLEL INTERFACE CONNECTOR
Figure 5-5 and Table 5-12 show the connector and pinout of the parallel interface connector. Note that some signals are redefined depending on the port’s operational mode.
Figure 5-5. Parallel Interface Connector (Female DB-25 as viewed from rear of chassis)
Table 5–12. DB-25 Parallel Connector Pinout
Table 5-12.
DB-25 Parallel Connector Pinout
Pin Signal
1
2
3
STB-
D0
D1
Strobe / Write [1]
Data 0
Data 1
4 D2 Data 2
5 D3 Data
14
15
16
17
LF-
ERR-
INIT-
SLCTIN-
Line Feed [2]
Error [3]
Initialize Paper [4]
Select In / Address. Strobe [1]
18 GND Ground
6 D4
7 D5
8 D6
9 D7
10
11
12
13
ACK-
BSY
PE
SLCT
Data
Data
Data
Data
Acknowledge / Interrupt [1]
Busy / Wait [1]
Paper End / User defined [1] 25
Select / User defined [1] --
19 GND Ground
20 GND Ground
21 GND Ground
22 GND Ground
23
24
GND
GND
Ground
Ground
GND
--
Ground
--
NOTES:
[1] Standard and ECP mode function / EPP mode function
[2] EPP mode function: Data Strobe
ECP modes: Auto Feed or Host Acknowledge
[3] EPP mode: user defined
ECP modes:Fault or Peripheral Req.
[4] EPP mode: Reset
ECP modes: Initialize or Reverse Req.
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Chapter 5 Input/Output Interfaces
5.6
KEYBOARD/POINTING DEVICE INTERFACE
The keyboard/pointing device interface function is provided by the LPC47B357 I/O controller component, which integrates 8042-compatible keyboard controller logic (hereafter referred to as simply the “8042”) to communicate with the keyboard and pointing device using bi-directional serial data transfers. The 8042 handles scan code translation and password lock protection for the keyboard as well as communications with the pointing device. This section describes the interface itself. The keyboard is discussed in the Appendix C.
5.6.1
KEYBOARD INTERFACE OPERATION
The data/clock link between the 8042 and the keyboard is uni-directional for Keyboard Mode 1 and bi-directional for Keyboard Modes 2 and 3. (These modes are discussed in detail in Appendix
C). This section describes Mode 2 (the default) mode of operation.
Communication between the keyboard and the 8042 consists of commands (originated by either the keyboard or the 8042) and scan codes from the keyboard. A command can request an action or indicate status. The keyboard interface uses IRQ1 to get the attention of the CPU.
The 8042 can send a command to the keyboard at any time. When the 8042 wants to send a command, the 8042 clamps the clock signal from the keyboard for a minimum of 60 us. If the keyboard is transmitting data at that time, the transmission is allowed to finish. When the 8042 is ready to transmit to the keyboard, the 8042 pulls the data line low, causing the keyboard to respond by pulling the clock line low as well, allowing the start bit to be clocked out of the 8042.
The data is then transferred serially, LSb first, to the keyboard (Figure 5-6). An odd parity bit is sent following the eighth data bit. After the parity bit is received, the keyboard pulls the data line low and clocks this condition to the 8042. When the keyboard receives the stop bit, the clock line is pulled low to inhibit the keyboard and allow it to process the data.
Start
Bit
0
D0
(LSb)
1
D1
0
D2
1
D3
1
D4
0
D5
1
D6
1
D7
(MSb)
1
Parity Stop
Bit
1 0
Data
Clock
Th Tcy Tcl Tch
Parameter Minimum Maximum
Tcy (Cycle Time) 0 us 80 us
Tcl (Clock Low) 25 us 35 us
Tch (Clock High) 25 us 45 us
Th (Data Hold) 0 us 25 us
Tss (Stop Bit Setup) 8 us 20 us
Tsh (Stop Bit Hold) 15 us 25 us
Figure 5-6. 8042-To-Keyboard Transmission of Code EDh, Timing Diagram
Tss Tsh
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Control of the data and clock signals is shared by the 8042and the keyboard depending on the originator of the transferred data. Note that the clock signal is always generated by the keyboard.
After the keyboard receives a command from the 8042, the keyboard returns an ACK code. If a parity error or timeout occurs, a Resend command is sent to the 8042.
Table 5-13 lists and describes commands that can be issued by the 8042 to the keyboard.
Table 5–13. 8042-To-Keyboard Commands
Command
Set/Reset Status Indicators
Echo
Invalid Command
Table 5-13.
8042-To-Keyboard Commands
Select Alternate Scan Codes
Value
EDh
EEh
EFh/F1 h
F0h
Description
Enables LED indicators. Value EDh is followed by an option byte that specifies the indicator as follows:
Bits <7..3> not used
Bit <2>, Caps Lock (0 = off, 1 = on)
Bit <1>, NUM Lock (0 = off, 1 = on)
Bit <0>, Scroll Lock (0 = off, 1 = on)
Keyboard returns EEh when previously enabled.
These commands are not acknowledged.
Read ID
Set Typematic Rate/Display
Enable
Default Disable
Set Default
Set Keys - Typematic
Set Keys - Make/Brake
Set Keys - Make
Set Keys - Typematic/Make/Brake
Set Type Key - Typematic
Set Type Key - Make/Brake
Set Type Key - Make
Resend
Reset
Note:
[1] Used in Mode 3 only.
F2h
F3h
F4h
F5h
F6h
F7h
F8h
F9h
FAh
FBh
FCh
FDh
FEh
FFh
Instructs the keyboard to select another set of scan codes and sends an option byte after ACK is received:
01h = Mode 1
02h = Mode 2
03h = Mode 3
Instructs the keyboard to stop scanning and return two keyboard ID bytes.
Instructs the keyboard to change typematic rate and delay to specified values:
Bit <7>, Reserved - 0
Bits <6,5>, Delay Time
00 = 250 ms
01 = 500 ms
10 = 750 ms
11 = 1000 ms
Bits <4..0>, Transmission Rate:
00000 = 30.0 ms
00001 = 26.6 ms
00010 = 24.0 ms
00011 = 21.8 ms
:
11111 = 2.0 ms
Instructs keyboard to clear output buffer and last typematic key and begin key scanning.
Resets keyboard to power-on default state and halts scanning pending next 8042 command.
Resets keyboard to power-on default state and enable scanning.
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and sets default scan code set. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
Clears keyboard buffer and prepares to receive key ID. [1]
8042 detected error in keyboard transmission.
Resets program, runs keyboard BAT, defaults to Mode 2.
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Chapter 5 Input/Output Interfaces
5.6.2 POINTING DEVICE INTERFACE OPERATION
The pointing device (typically a mouse) connects to a 6-pin DIN-type connector that is identical to the keyboard connector both physically and electrically. The operation of the interface (clock and data signal control) is the same as for the keyboard. The pointing device interface uses the
IRQ12 interrupt.
5.6.3 KEYBOARD/POINTING DEVICE INTERFACE PROGRAMMING
Programming the keyboard interface consists of configuration, which occurs during POST, and control, which occurs during runtime.
5.6.3.1 8042 Configuration
The keyboard/pointing device interface must be enabled and configured for a particular speed before it can be used. Enabling and speed parameters of the 8042 logic are affected through the
PnP configuration registers of the LPC47B357 I/O controller. Enabling and speed control are automatically set by the BIOS during POST but can also be accomplished with the Setup utility and other software.
The keyboard interface configuration registers are listed in the following table:
Table 5–14. Keyboard Interface Configuration Registers
Table 5-14.
Keyboard Interface Configuration Registers
Index
Address Function
30h Activate
70h Primary Interrupt Select
72h
F0h
Secondary Interrupt Select
Reset and A20 Select
R/W
R/W
R/W
R/W
R/W
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Technical Reference Guide
5.6.3.2 8042 Control
The BIOS function INT 16 is typically used for controlling interaction with the keyboard. Subfunctions of INT 16 conduct the basic routines of handling keyboard data (i.e., translating the keyboard’s scan codes into ASCII codes). The keyboard/pointing device interface is accessed by the CPU through I/O mapped ports 60h and 64h, which provide the following functions:
♦
Output buffer reads
♦
Input buffer writes
♦
Status reads
♦
Command writes
Ports 60h and 64h can be accessed using the IN instruction for a read and the OUT instruction for a write. Prior to reading data from port 60h, the “Output Buffer Full” status bit (64h, bit <0>) should be checked to ensure data is available. Likewise, before writing a command or data, the
“Input Buffer Empty” status bit (64h, bit <1>) should also be checked to ensure space is available.
I/O Port 60h
I/O port 60h is used for accessing the input and output buffers. This register is used to send and receive data from the keyboard and the pointing device. This register is also used to send the second byte of multi-byte commands to the 8042 and to receive responses from the 8042 for commands that require a response.
A read of 60h by the CPU yields the byte held in the output buffer. The output buffer holds data that has been received from the keyboard and is to be transferred to the system.
A CPU write to 60h places a data byte in the input byte buffer and sets the CMD/ DATA bit of the
Status register to DATA. The input buffer is used for transferring data from the system to the keyboard. All data written to this port by the CPU will be transferred to the keyboard except bytes that follow a multibyte command that was written to 64h
I/O Port 64h
I/O port 64h is used for reading the status register and for writing commands. A read of 64h by the CPU will yield the status byte defined as follows:
Bit Function
7..4 General Purpose Flags.
3 CMD/DATA Flag (reflects the state of A2 during a CPU write).
0 = Data
1 = Command
2
1
General Purpose Flag.
Input Buffer Full. Set (to 1) upon a CPU write. Cleared by
IN A, DBB instruction.
0 Output Buffer Full (if set). Cleared by a CPU read of the buffer.
A CPU write to I/O port 64h places a command value into the input buffer and sets the
CMD/DATA bit of the status register (bit <3>) to CMD.
Table 5-15 lists the commands that can be sent to the 8042 by the CPU. The 8042 uses IRQ1 for gaining the attention of the CPU.
Table 5–15. CPU Commands To The 8042
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Chapter 5 Input/Output Interfaces
Table 5-15.
CPU Commands To The 8042
Value Command Description
20h
60h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ADh
AEh
C0h
C2h
C3h
D0h
D1h
D2h
D3h
D4h
E0h
F0h-
FFh
Put current command byte in port 60h.
Load new command byte.
Test password installed. Tests whether or not a password is installed in the 8042:
If FAh is returned, password is installed.
If F1h is returned, no password is installed.
Load password. This multi-byte operation places a password in the 8042 using the following manner:
1. Write A5h to port 64h.
2. Write each character of the password in 9-bit scan code (translated) format to port 60h.
3. Write 00h to port 60h.
Enable security. This command places the 8042 in password lock mode following the A5h command.
The correct password must then be entered before further communication with the 8042 is allowed.
Disable pointing device. This command sets bit <5> of the 8042 command byte, pulling the clock line of the pointing device interface low.
Enable pointing device. This command clears bit <5> of the 8042 command byte, activating the clock line of the pointing device interface.
Test the clock and data lines of the pointing device interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
Initialization. This command causes the 8042 to inhibit the keyboard and pointing device and places
55h into the output buffer.
Test the clock and data lines of the keyboard interface and place test results in the output buffer.
00h = No error detected
01h = Clock line stuck low
02h = Clock line stuck high
03h = Data line stuck low
04h = Data line stuck high
Disable keyboard command (sets bit <4> of the 8042 command byte).
Enable keyboard command (clears bit <4> of the 8042 command byte).
Read input port of the 8042. This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h.
Poll Input Port High. This command directs the 8042 to place bits <7..4> of the input port into the upper half of the status byte on a continous basis until another command is received.
Poll Input Port Low. This command directs the 8042 to place bits <3..0> of the input port into the lower half of the status byte on a continous basis until another command is received.
Read output port. This command directs the 8042 to transfer the contents of the output port to the output buffer so that they can be read at port 60h.
Write output port. This command directs the 8042 to place the next byte written to port 60h into the output port (only bit <1> can be changed).
Echo keyboard data. Directs the 8042 to send back to the CPU the next byte written to port 60h as if it originated from the keyboard. No 11-to-9 bit translation takes place but an interrupt (IRQ1) is generated if enabled.
Echo pointing device data. Directs the 8042 to send back to the CPU the next byte written to port
60h as if it originated from the pointing device. An interrupt (IRQ12) is generated if enabled.
Write to pointing device. Directs the 8042 to send the next byte written to 60h to the pointing device.
Read test inputs. Directs the 8042 to transfer the test bits 1 and 0 into bits <1,0> of the output buffer.
Pulse output port. Controls the pulsing of bits <3..0> of the output port (0 = pulse, 1 = don’t pulse).
Note that pulsing bit <0> will reset the system.
5.6.4 KEYBOARD/POINTING DEVICE INTERFACE CONNECTOR
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The legacy-light model provides separate PS/2 connectors for the keyboard and pointing device.
Both connectors are identical both physically and electrically. Figure 5-7 and Table 5-16 show the connector and pinout of the keyboard/pointing device interface connectors.
Figure 5-7. Keyboard or Pointing Device Interface Connector
(as viewed from rear of chassis)
Table 5–16. Keyboard/Pointing Device Connector Pinout
Table 5-16.
Keyboard/Pointing Device Connector Pinout
Pin Signal
1 DATA
2 NC
Data
3 GND Ground
4 + 5 VDC
5 CLK
6 NC
Power
Clock
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Chapter 5 Input/Output Interfaces
5.7
UNIVERSAL SERIAL BUS INTERFACE
The Universal Serial Bus (USB) interface provides asynchronous/isochronous data transfers of up to 12 Mb/s with compatible peripherals such as keyboards, printers, or modems. This high-speed interface supports hot-plugging of compatible devices, making possible system configuration changes without powering down or even rebooting systems.
NOTE: It is recommended to run the Windows 98 (or later) operating system when using USB peripherals, especially a USB keyboard and USB mouse. Problems may be encountered when using USB devices with a system running Windows 95, although some peripherals (such as a modem and/or a camera) may operate satisfactorily.
As shown in Figure 5-8, the USB interface is provided by the 82801 ICH2 component and a USB hub component. All models provide two front-panel accessible series-A USB ports. For more information on the USB interface refer to the following web site: http://www.usb.org
82801
ICH2
USB
I/F #2
Tx/Rx Data
Tx/Rx Data
Rear Panel
USB Port A
USB Port B
Figure 5-8. USB I/F, Block Diagram
5.7.1 USB DATA FORMATS
The USB I/F uses non-return-to-zero inverted (NRZI) encoding for data transmissions, in which a
1 is represented by no change (between bit times) in signal level and a 0 is represented by a change in signal level. Bit stuffing is employed prior to NRZ1 encoding so that in the event a string of 1’s is transmitted (normally resulting in a steady signal level) a 0 is inserted after every six consecutive 1’s to ensure adequate signal transitions in the data stream.
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The USB transmissions consist of packets using one of four types of formats (Figure 5-9) that include two or more of seven field types.
♦
Sync Field – 8-bit field that starts every packet and is used by the receiver to align the incoming signal with the local clock.
♦
Packet Identifier (PID) Field – 8-bit field sent with every packet to identify the attributes (in.
out, start-of-frame (SOF), setup, data, acknowledge, stall, preamble) and the degree of error correction to be applied.
♦
Address Field – 7-bit field that provides source information required in token packets.
♦
Endpoint Field – 4-bit field that provides destination information required in token packets.
♦
Frame Field – 11-bit field sent in Start-of-Frame (SOF) packets that are incremented by the host and sent only at the start of each frame.
♦
Data Field – 0-1023-byte field of data.
♦
Cyclic Redundancy Check (CRC) Field – 5- or 16-bit field used to check transmission integrity.
Token Packet
SOF Packet
Data Packet
Handshake Packet
Sync Field
(8 bits)
Sync Field
(8 bits)
Sync Field
(8 bits)
Sync Field
(8 bits)
PID Field
(8 bits)
PID Field
(8 bits)
PID Field
(8 bits)
PID Field
(8 bits)
Addr.
Field
ENDP.
Field
Frame Field
(11 bits)
Data Field
(0-1023 bytes)
CRC Field
(5 bits)
CRC Field
(5 bits)
CRC Field
(16 bits)
Figure 5-9. USB Packet Formats
Data is transferred LSb first. A cyclic redundancy check (CRC) is applied to all packets (except a handshake packet). A packet causing a CRC error is generally completely ignored by the receiver.
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5.7.2 USB PROGRAMMING
Programming the USB interface consists of configuration, which typically occurs during POST, and control, which occurs at runtime.
5.7.2.1 USB Configuration
PCI
Config.
Addr.
00, 01h
02, 03h
04, 05h
06, 07h
08h
09h
0Ah
0Bh
The USB interface functions as a PCI device (31) within the 82801 component (function 2) and is configured using PCI Configuration Registers as listed in Table 5-17.
Table 5–17. USB Interface Configuration Registers
Register
Vender ID
Device ID
PCI Command
PCI Status
Revision ID
Programming I/F
Sub Class Code
Base Class Code
Table 5-17.
USB Interface Configuration Registers
Reset
Value
PCI
Config.
Addr. Register
8086h 0Eh
2444h 20-23h
0000h 2C, 2Dh
0280h 3Ch
00h 3Dh
00h 60h
03h C0, C1h
0Ch C4h
Reset
Value
Header Type
I/O Space Base Address
Sub. Vender ID
Interrupt Line
00h
1
00h
00h
Interrupt Pin 03h
Serial Bus Release No. 10h
USB Leg. Kybd./Ms. Cntrl. 2000h
USB Resume Enable 00h
5.7.2.2 USB Control
The USB is controlled through I/O registers as listed in table 5-18.
Table 5–18. USB Control Registers
Table 5-18.
USB Control Registers
I/O Addr. Register
00, 01h
02, 03h
04, 05h
06, 07
08, 0B
0Ch
10, 11h
12, 13h
Command
Status
Interupt Enable
Frame Number
Frame List Base Address
Start of Frame Modify
Port 1 Status/Control
Port 2 Status/Control
Default Value
0000h
0000h
0000h
0000h
0000h
40h
0080h
0080h
00h
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5.7.3 USB CONNECTOR
The USB interface provides two series-A connectors on the front panel and, on legacy-free models, three series-A USB connectors on the rear panel.
1 2 3 4
Figure 5-10. Universal Serial Bus Connector
Table 5–19. USB Connector Pinout
Pin Signal
1 Vcc +5 VDC
Table 5-19.
USB Connector Pinout
3 USB+
4 GND
Data (plus)
Ground
5.7.4 USB CABLE DATA
The recommended cable length between the host and the USB device should be no longer than sixteen feet for full-channel (12 MB/s) operation, depending on cable specification (see following table).
Table 5–20. USB Cable Length Data
Conductor Size
20 AWG
22 AWG
24 AWG
26 AWG
28 AWG
NOTE:
Table 5-20.
USB Cable Length Data
Resistance
0.036
Ω
0.057
Ω
0.091
Ω
0.145
Ω
0.232
Ω
Maximum Length
16.4 ft (5.00 m)
9.94 ft (3.03 m)
6.82 ft (2.08 m)
4.30 ft (1.31 m)
2.66 ft (0.81 m)
For sub-channel (1.5 MB/s) operation and/or when using sub-standard cable shorter lengths may be allowable and/or necessary.
The shield, chassis ground, and power ground should be tied together at the host end but left unconnected at the device end to avoid ground loops.
Color code:
Data + Green
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Chapter 5 Input/Output Interfaces
5.8
AUDIO SUBSYSTEM
The systems covered in this guide come configured with one of two levels of audio support:
♦
Legacy PC-beep audio support
♦
Embedded AC’97 audio support
5.8.1 FUNCTIONAL ANALYSIS
A block diagram of the audio subsystem is shown in Figure 5-11. Systems without embedded
AC’97 support provide only legacy PC-beep audio and have the speaker (board-mounted on the
Small Form Factor, chassis-mounted on the Desktop EN Slim Desktop/Configurable Minitower) driven directly by the audio output of the ICH2 as shown in the upper third of the diagram. These systems may be upgraded by adding a PCI audio card.
Systems with embedded AC’97 audio support use the AC’97 Audio Controller of the 82801 ICH2 component to access and control an Analog Devices AD1885 Audio Codec, which provides the analog-to-digital (ADC) and digital-to-analog (DAC) conversions as well as the mixing functions.
All control functions such as volume, audio source selection, and sampling rate are controlled through software over the PCI bus through the AC97 Audio Controller of the 82801 ICH2.
Control data and digital audio streams (record and playback) are transferred between the Audio
Controller and the Audio Codec over the AC97 Link Bus.
Slim Desktop and Configurable Minitower systems implement Business Audio, which has the codec analog output applied to a 3-watt amplifier that drives a 16-ohm speaker. Small Form Factor systems feature Premier Sound, which includes a 6-level equalizer that compensates for chassis acoustics and a low-distortion 8-watt amplifier driving a speaker.
The analog interfaces allowing connection to external audio devices include:
Mic In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for connection of a condenser microphone with an impedance of 10-K ohms. This is the default recording input after a system reset.
Line In - This input uses a three-conductor (stereo) mini-jack that is specifically designed for connection of a high-impedance (10k-ohm) audio source such as a tape deck.
Headphones Out - This input uses a three-conductor (stereo) mini-jack that is designed for connecting a set of 16-ohm (nom.) stereo headphones or powered speakers. Plugging into the
Headphones jack mutes the signal to the internal speaker and, on SFF systems, the Line Out jack as well..
Line Out (SFF only) - This output uses a three-conductor (stereo) mini-jack for connecting left and right channel line-level signals (20-K ohm impedance). A typical connection would be to a tape recorder’s Line In (Record In) jacks, an amplifier’s Line In jacks, or to powered speakers that contain amplifiers. Plugging into the Line Out mutes the internal speaker.
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82801
ICH2
PC Beep Audio
+
-
Speaker
82801 ICH2
PCI
Bus
AC’97
Audio
Cntlr.
Legacy PC-Beep Audio (Deskpro EN Models Only)
PC Beep Audio
AC97
Link Bus
L+R
Audio TDA
7056
Mic In
Line In
CD ROM
Audio
Bias
(L)
(R)
AD1885
Audio
Codec
CD Audio (L)
CD Audio (R)
HP Out Audio (L/R) (L)
(R)
+
-
Internal
Speaker
Headphones/
Line Out
82801 ICH2
PCI
Bus
AC’97
Audio
Cntlr.
Embedded AC’97 Audio (Slim Desktop/Configurable Minitower)
Embedded AC’97 Audio (Small Form Factor)
PC Beep Audio
AC97
Link Bus
Equalizer
Mic In
Audio
Bias
Mono
Audio LA
4301
+
-
Internal
Speaker
Line In
CD ROM
(L)
(R)
CD Audio (L)
CD Audio (R)
AD1885
Audio
Codec
Line
Sense
Line Out Audio (L/R)
HP
Sense
HP Out Audio (L/R)
(L)
(R)
(L)
(R)
Line
Out
Headphones
Out
Figure 5-11. Audio Subsystem Functional Block Diagram
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Chapter 5 Input/Output Interfaces
5.8.2 AC97 AUDIO CONTROLLER
The AC97 Audio Controller is a PCI device (device 31/function 5) that is integrated into the
82801 ICH component and supports the following functions:
♦
Read/write access to audio codec registers
♦
16-bit stereo PCM output @ up to 48 KHz sampling
♦
16-bit stereo PCM input @ up to 48 KHz sampling
♦
Acoustic echo correction for microphone
♦
AC’97 Link Bus
♦
ACPI power management
5.8.3 AC97 LINK BUS
The audio controller and the audio codec communicate over a five-signal AC97 Link Bus (Figure
5-12). The AC97 Link Bus includes two serial data lines (SD OUT/SD IN) that transfer control and PCM audio data serially to and from the audio codec using a time-division multiplexed
(TDM) protocol. The data lines are qualified by a 12.288 MHz BIT_CLK signal driven by the audio codec. Data is transferred in frames synchronized by the 48-KHz SYNC signal, which is derived from the clock signal and driven by the audio controller. The SYNC signal is high during the frame’s tag phase then falls during T17and remains low during the data phase. A frame consists of one 16-bit tag slot followed by twelve 20-bit data slots. When asserted (typically during a power cycle), the RESET- signal (not shown) will reset all audio registers to their default values.
T1 T2 T18 T19 T38 T39 T58
BIT_CLK
(12.288 MHz)
SYNC
(48 KHz)
SD OUT or SD IN
Codec
Ready
Bit 15 Bit 14 Bit 0 Bit 19 Bit 18 Bit 0 Bit 19 Bit 18 Bit 0 Bit 19
Slot 0
(Tag)
Slot 1
(Data)
Slot 2
(Data)
Slot Description
0 Bit 15: Frame valid bit
Bits 14-3: Slots 1-12 valid bits
Bits 2-0: Codec ID
1 Command address: Bit 19, R/W; Bits 18..12, reg. Index; Bits 11..0, reserved.
3
4
Bits 19-4: PCM audio data, left channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
Bits 19-4: PCM audio data, right channel (SD OUT, playback; SD IN, record)
Bits 3-0 all zeros
5 Modem codec data (not used in this system)
6-11 Reserved
Figure 5-12. AC’97 Link Bus Protocol
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5.8.4 AUDIO CODEC
The audio codec provides pulse code modulation (PCM) coding and decoding of audio information as well as the selection and/or mixing of analog channels. As shown in Figure 5-13, analog audio from a microphone, tape, or CD can be selected and, if to be recorded (saved) onto a disk drive, routed through an analog-to-digital converter (ADC). The resulting left and right PCM record data are muxed into a time-division-multiplexed (TDM) data stream (SD IN signal) that is routed to the audio controller. Playback (PB) audio takes the reverse path from the audio controller to the audio codec as SD OUT data and is decoded and processed by the digital-toanalog converter (DAC). The codec supports simultaneous record and playback of stereo (left and right) audio. The Sample Rate Generator may be set for sampling frequencies up to 48 KHz.
Analog audio may then be routed through 3D stereo enhancement processor or bypassed to the output selector (SEL). The integrated analog mixer provides the computer control-console functionality handling multiple audio inputs.
Audio
Format
Analog
Output
Circuits
(L)
(R)
S
E
L
Mic In
Line In (L)
Line In (R)
CD In (L)
CD In (R)
3D Proc.
3D Proc.
Σ
/Mixer o r c t
S e l e
Left
Audio
Right
Audio
Rec
Gain
Rec
Gain
(L)
(L)
(R)
(R)
SW
PB
Gain
PB
Gain
ADC
Rec
Data (L)
ADC
Rec
Data (R)
SD IN
DAC
Sample
Rate
Gen.
PB
Data (L)
AC97
Link
I/F
SD Out
PB
Data (R)
DAC
Audio
Controller
Figure 5-13. AD1885 Audio Codec Functional Block Diagram
All inputs and outputs are two-channel stereo except for the microphone input, which is inputted as a single-channel but mixed internally onto both left and right channels. The microphone input is the default active input. All block functions are controlled through index-addressed registers of the codec.
5.8.5 AUDIO PROGRAMMING
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Audio subsystem programming consists configuration, typically accomplished during POST, and control, which occurs during runtime.
5.8.5.1 Audio Configuration
The audio subsystem is configured according to PCI protocol through the AC’97 audio controller function of the 82801 ICH2. Table 5-21 lists the PCI configuration registers of the audio subsystem.
Table 5–21. AC’97 Audio Controller PCI Configuration Registers
Table 5-21.
AC’97 Audio Controller
PCI Configuration Registers (82801 Device 31/Function 5)
PCI
Conf.
Addr.
Register
00-01h Vender ID
06-07h PCI Status
08h Revision ID
09h Programming
0Ah Sub-Class
0Bh Base Class Code
Value on
Reset
PCI
Conf.
Addr. Register
8086h 14-17h Native Audio Bus Mstr. Addr.
2445h 18-1Bh Reserved
0000h 1C-2Bh Reserved
0280h 2C-2Dh Subsystem Vender ID
XXh 2E-2Fh Subsystem ID
04h 3Dh Interrupt Pin
10-13h Native Audio Mixer Base Addr. 1 -- --
Value on
Reset
1
1h
1h
0000h
0000h
--
00h
02h
0’s
--
5.8.5.2 Audio Control
The audio subsystem is controlled through a set of indexed registers that physically reside in the audio codec . The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described. The audio codec’s control registers
(Table 5-22) are mapped into 64 kilobytes of variable I/O space.
Table 5–22. AC’97 Audio Codec Control Registers
Offset
Addr. / Register
00h Reset
02h Master Vol.
04h Reserved
06h Mono Mstr. Vol.
08h Reserved
0Ah PC Beep Vol.
0Ch Phone In Vol.
0Eh Mic Vol.
10h Line In Vol.
12h CD Vol.
Table 5-22.
AC’97 Audio Codec Control Registers
Value
On
Reset
Offset
Addr. / Register
0100h 14h Video Vol.
8000h 16h Aux Vol.
X 18h PCM Out Vol.
8000h 1Ah Record Sel.
X 1Ch Record Gain
8000h 1Eh Reserved
8008h 20h Gen. Purpose
8008h 22h 3D Control
8808h 24h Reserved
8808h 26h Pwr Mgnt.
Value
On
Reset
Offset
Addr. / Register
Value
On
Reset
8808h 28h Ext. Audio ID. 0001h
8808h 2Ah Ext. Audio Ctrl/Sts 0000h
8808h 2Ch PCM DAC SRate
0000h 32h PCM ADC SRate
8000h 34h Reserved
X 72h Reserved
BB80h
BB80h
X
X
0000h 74h Serial Config.
0000h 76h Misc. Control Bits
X 7Ch Vender ID1
000xh 7Eh Vender ID2
7x0xh
0404h
4144h
5340h
5.8.6 AUDIO SPECIFICATIONS
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The specifications for the integrated AC97 audio subsystem are listed in Table 5-23.
Table 5–23. Audio Subsystem Specifications
Table 5-23.
AC97 Audio Subsystem Specifications
Paramemter Measurement
Sampling Rate 5.51 KHz to 44 KHz
Nominal Input Voltage:
Mic In (w/+20 db gain)
Line In
Impedance:
Mic In
Line In
Line Out
Signal-to-Noise Ratio (input to Line Out)
Max. Power Output (with 10% THD):
Small Form Factor
Slim Desktop/Configurable Minitower
Input Gain Attenuation Range
Master Volume Range
Frequency Response:
Codec
Speaker (Small Form Factor)
.283 Vp-p
2.83 Vp-p
1 K ohms (nom)
10 K ohms (min)
800 ohms
90 db (nom)
8 watts (into 8 ohms)
3 watts (into 16 ohms)
46.5 db
-94.5 db
20-20 KHz
450 - 4000 Hz
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5.9
NETWORK INTERFACE CONTROLLER
These systems include a network interface controller (NIC) consisting of a 82562-equivalent controller integrated into the 82801BA ICH2 component coupled with a physical interface (PHY) component and an RJ-45 jack with integral status LEDs (Figure 5-14). The support firmware is contained in the system (BIOS) ROM. The NIC can operate in half- or full-duplex modes, and provides auto-negotiation of both mode and speed. Half-duplex operation features an Intelproprietary collision reduction mechanism while full-duplex operation follows the IEEE 802.3x
flow control specification. Transmit and receive FIFOs of 3 kilobytes each reduce the chance of overrun while waiting for bus access.
Active/
Link
(Green)
RJ-45
Connector
82801 ICH2
Network
Interface
Function
TX/RX
LAN
PHY
I/F
TX/RX
Speed
(Yellow)
LED Function
Green Activity/Link: Indicates network activity and link pulse reception.
Yellow Speed: Indicates link detection in 100 MB/s mode
(always on if 100Base-Tx is forced).
Figure 5-14. Network Interface Controller Block Diagram
The Network Interface Controller includes the following features:
♦
Fast Ethernet controller with 32-bit architecture and 3-KB TX/RX buffers.
♦
Dual-mode support with auto-switching between 10BASE-T and 100BASE-TX.
♦
Power down and Wake up support in both APM and ACPI environments (PME- and WOL).
♦
Alert-on-LAN (AOL v1.0) support.
♦
Link and Activity LED indicator drivers
♦
AOL support for upgrade card
The controller features high and low priority queues and provides priority-packet processing for networks that can support that feature. The controller’s micro-machine processes transmit and receive frames independently and concurrently. Receive runt (under-sized) frames are not passed on as faulty data but discarded by the controller, which also directly handles such errors as collision detection or data under-run.
The NIC uses 3.3 VDC auxiliary power, which allows the controller to support Wake-On-LAN
(WOL) and Alert-On-LAN (AOL) functions while the main system is powered down.
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NOTE: For the WOL and AOL features to function as described in the following paragraphs, the system unit must be plugged into a live AC outlet. Controlling unit power through a switchable power strip will, with the strip turned off, disable WOL and
AOL functionality.
5.9.1 WAKE ON LAN SUPPORT
The NIC supports the Wired-for-Management (WfM) standard of Wake-On-LAN (WOL) that allows the system to be booted up from a powered-down or low-power condition upon the detection of special packets received over a network. The NIC receives 3.3 VDC auxiliary power while the system unit is powered down in order to process special packets. The detection of a
Magic Packet by the NIC results in the PME- signal on the PCI bus to be asserted, initiating system wake-up from an ACPI S1 or S3 state.
5.9.2 ALERT ON LAN SUPPORT
Alert-On-LAN (AOL) support allows the NIC to communicate the occurrence of certain events over a network even while the system unit is powered off. In a system-off (powered down) condition the network function of the 82801 ICH2 component receives auxiliary +3.3 VDC power
(derived from the +5 VDC auxiliary power from the power supply assembly). Certain events
(listed in Table 5-24) will result in the network function of the ICH2 to transmit an appropriate pre-constructed message over the network to a system management console.
Reportable AOL events are listed in the following table:
Table 5–24. AOL Events
Table 5-24.
AOL Events
Event Description
BIOS Failure
OS Problem
System fails to boot successfully.
System fails to load operating system after POST.
Missing/Faulty Processor Processor fails to fetch first instruction.
Thermal Condition
Heartbeat
Thermal ASIC reports high temperature.
Indication of system’s network presence (sent approximately every 30 seconds in normal operation).
The AOL implementation requirements are as follows:
1.
Intel PRO/100 VM Network Connection drivers 3.80 or later (available from Compaq).
2.
Intel Alert-On-LAN Utilities, version 2.5 (available from Compaq).
3.
Management console running one of the following: a.
HP OpenView Network Node Manager 6.x
b.
Intel LANDesk Client Manager c.
Sample Application Console from the Intel AOL Utilities (item #2 above)
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Chapter 5 Input/Output Interfaces
5.9.3 POWER MANAGEMENT SUPPORT
The NIC features Wired-for-Management (WfM) support providing system wake up from network events (WOL) as well as generating system status messages (AOL) and supports both APM and
ACPI power management environments. The controller receives 3.3 VDC (auxiliary) power as long as the system is plugged into a live AC receptacle, allowing support of wake-up events occuring over a network while the system is powered down or in a low-power state.
5.9.3.1 APM Environment
The Advanced Power Management (APM) functionality of system wake up is implemented through the system’s APM-compliant BIOS and the controller’s Magic Packet-compliant hardware. This environment bypasses operating system (OS) intervention allowing a plugged in unit to be turned on remotely over the network (i.e., “remote wake up”). In APM mode the controller will respond upon receiving a Magic Packet, which is a packet where the node’s address is repeated 16 times. Upon Magic packet detection, the controller initiates the boot sequence.
5.9.3.2 ACPI Environment
The Advanced Configuration and Power Interface (ACPI) functionality of system wake up is implemented through an ACPI-compliant OS and is the default power management mode. The following wakeup events may be individually enabled/disabled through the supplied software driver:
♦
Magic Packet – Packet with node address repeated 16 times in data portion
NOTE: The following functions are supported in NDIS5 drivers but implemented through remote management software applications (such as LanDesk).
♦
Individual address match – Packet with matching user-defined byte mask
♦
Multicast address match – Packet with matching user-defined sample frame
♦
ARP (address resolution protocol) packet
♦
Flexible packet filtering – Packets that match defined CRC signature
The PROSet Application software (pre-installed and accessed through the System Tray or
Windows Control Panel) allows configuration of operational parameters such as WOL and duplex mode.
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5.9.4 NIC PROGRAMMING
Programming the NIC consists of configuration, which occurs during POST, and control, which occurs at runtime.
5.9.4.1 Configuration
The network interface function is a PCI device and configured though PCI configuration space registers using PCI protocol described in chapter 4. The PCI configuration registers are listed in the following table:
Table 5–25. NIC Controller PCI Configuration Registers
PCI
Conf.
Addr.
Table 5-25.
NIC Controller PCI Configuration Registers (ICH2 Device 8/Function 0)
Register
Value on
Reset
PCI
Conf.
Addr. Register
00-01h Vender ID
02-03h Device ID
04-05h PCI Command
06-07h PCI Status
08h Revision ID
09-0Bh Class Code
0Dh Latency Timer
0Eh Header Type
10-13h Cntrl. Reg. Base Addr. (Mem)
14-17h Cntrl. Reg. Base Addr. (I/O)
2C, 2Dh Subsystem Vender ID
NOTE:
8086h
2449h
0000h
0290h
Xxh
1
2E, 2Fh
34h
3Ch
3Dh
3Eh
Assume unmarked gaps are reserved and/or not used.
Subsystem ID
Capabilities Pointer
Interrupt Line
Interrupt Pin
Min. Grant
0002h 3E, 3Fh Max. Latency
00h DCh Capability ID
00h
8
DDh Next Item Pointer
DE, DFh Pwr. Mgmt. Functions
E0, E1h Pwr. Mgmt. Cntrl./Sts
0000h E3h Data
Value on
Reset
0000h
DCh
00h
01h
08h
38h
01h
00h
FE21h
0000h
--
5.9.4.2 Control
The 82562 controller is controlled though registers that may be mapped in system memory space or variable I/O space. The registers are listed in the following table:
Table 5–26. NIC Control Registers
Offset
Addr. / Register
00h SCB Status
02h SCB Command
04h SCB General Pointer
08h PORT
0Ch Flash Control Reg.
0Eh EEPROM Control Reg.
10h Mgmt. Data I/F Cntrl. Reg.
14h Rx Direct Mem. Access Byte Cnt.
18h Early Receive Interrupt
Table 5-26.
NIC Control Registers
No. of
Bytes
2
2
4
4
2
2
4
4
1
Offset
Addr. / Register
19h Flow Control Register
1Bh PMDR
1Ch General Control
1Dh General Status
1E-2Fh Reserved
30h Function Event Register
34h Function Event Mask Register
38h Function Present State Register
20h Force Event Register
Not implemented in these systems (CardBus registers).
Compaq Deskpro Personal Computers
No. of
Bytes
2
1
1
1
10
4
4
4
4
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Chapter 5 Input/Output Interfaces
5.9.5 NIC CONNECTOR
Figure 5-15 shows the RJ-45 connector used for the NIC interface. This connector includes the two status LEDs as part of the connector assembly.
Speed LED Activity LED
Pin Description
1 Transmit+
2 Transmit-
3 Receive+
6 Receive-
8 7 6 5 4 3 2 1
Figure 5-15. Ethernet TPE Connector (RJ-45, viewed from card edge)
5.9.6 NIC SPECIFICATIONS
Table 5–27. 82559 NIC Operating Specifications
Table 5-27.
NIC Specifications
Parameter
Modes Supported 10BASE-T half duplex @ 10 MB/s
10Base-T full duplex @ 20 MB/s
100BASE-TX half duplex @ 100 MB/s
Standards Compliance
100Base-TX full duplex @ 200 MB/s
IEEE 802.2
IEEE 802.3 & 802.3u
IEEE Intel priority packet (801.1p)
OS Driver Support MS-DOS
MS Windows 3.1
MS Windows 95 (pre-OSR2), 98, and 2000
Professional
MS Windows NT 3.51 & 4.0
Novell Netware 3.x, 4.x, 5x
Novell Netware/IntraNetWare
SCO UnixWare 7
Boot ROM Support
F12 BIOS Support
Bus Inteface
Power Management Support
OpenServer
Intel PRO/100 Boot Agent (PXE 3.0, RPL)
Yes
PCI 2.2
APM, ACPI, PCI Power Management Spec.
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5.9.7 NIC UPGRADING/CHANGING
The integrated NIC may be used in conjunction with another NIC card in a PCI slot. These systems provide AOL support for NIC cards that are AOL-compliant to the extent described previously in section 5.9.2. These systems also provide Remote System Alert (RSA) support for such NIC cards as the 3Com 3C905C-TX NIC card. The RSA function is similar to AOL in that the unit provides, even while powered off, system status alert messages to a network console. Note that NIC cards implementing the RSA method do not use the PCI/SMBus for receiving alert information and therefore require, in addition to the PCI connection, an auxiliary cable connection with the system as shown in Figure 5-16.
NIC Card in PCI Slot
Network
Cable
AOL/SOS Cable
AOL/SOS
Header P12
System or
Backplane
Figure 5-16. Remote System Alert Implementation (Generic Representation)
In the Remote System Alert implementation, the NIC card receives event notification directly from the system’s thermal and hood sensors and the LPC47B357 I/O controller over an AOL/SOS cable connection (Figure 5-17). During system-off conditions the NIC card receives auxiliary power from the 3.3 VDC auxiliary power rail on the PCI bus.
Hood Sensor
System or Backplane Board
47B34x
I/O Cntlr.
Thermal
ASIC
BIOS Fail
NC
OS Fail
Intrusion
NC
NC
Fan
Fan Alert
Fan Therm.
AOL/SOS
Header
1
7
Optional NIC Card
SOS
PCI
Connector
PCI
Bus
PCI
Bus
Not connected on Configurable Minitower models.
Figure 5-17. RSA Logic, Block Diagram
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Chapter 5 Input/Output Interfaces
Reportable RSA events are listed in the following table:
Table 5–28. Remote System Alert Events
Event
BIOS Failure
Thermal Condition
Chassis Intrusion [1]
Heartbeat
Table 5-28.
Remote System Alert Events
Description
System fails to boot successfully.
Thermal ASIC reports high temperature. Some systems may generate an alert message when increasing fan speed.
Smart Cover Sensor detected cover removal. This event is battery backed, meaning that should the unit be unplugged (from AC power) during cover removal, notification will occur after AC power is restored.
Indication of system’s network presence (sent approximately every 30 seconds in normal operation).
NOTE:
[1] Not supported on Configurable Minitower models.
The current Remote System Alert implementation requirements are as follows:
1.
3Com Etherlink 3C905C-TX NIC.
2.
7-pin AOL/SOS cable.
3.
3Com EtherDisk Driver 5.x or later (available from Compaq).
4.
Client-side utility software (included with driver).
5.
Server-side utility software (called 3Com Remote System Alert Manager on the compaq.com
web site ).
6.
Management console running one of the following: a.
HP OpenView Network Node Manager 6.x
b.
Microsoft Systems Management Server (SMS), version 1.2
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Chapter 6
EMBEDDED GRAPHICS SUBSYSTEMS
6.
Chapter 6 Embedded Graphics Subsystem
6.1
INTRODUCTION
This chapter describes graphics subsystems that are embedded on the system board. Two standard graphics controller configurations are available:
♦
815E-based graphics controller implementation - The graphics controller integrated into the
82815 GMCH is implemented and used to drive a video monitor.
♦
NVIDIA graphics controller implementation (Small Form Factor only) - The graphics controller integrated into the 82815 GMCH is inhibited and an NVIDIA graphics controller on the system board is used to drive a video monitor.
Both graphics subsystems employ the AGP interface allowing the use of system memory as well as local RAM to provide efficient, economical 2D and 3D performance.
In Small Form Factor systems, the graphics controller of either implementation is resident
(embedded) on the system board and no AGP slot is available. Upgrading or modifying the graphics controller on these systems is accomplished by adding a PCI graphics card.
In Slim Desktop and Configurable Minitower systems an AGP slot is provided. Upgrading these systems is accomplished by simply replacing the GPA/AIMM or AGP graphics controller card in the AGP slot. Separate AGP graphics cards are described in the Appendices.
This chapter covers the following subjects:
♦
Intel 815E-based graphics subsystem (6.2)
♦
NVIDIA-based graphics subsystem (6.3)
♦
Monitor power management (6.4)
♦
Monitor connector (6.5) page 6-2 page 6-6 page 6-8 page 6-8
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6-1
Chapter 6 Embedded Graphics Subsystems
6.2
INTEL 815E-BASED GRAPHICS SUBSYSTEM
The Intel 815E chipset integrates a graphics controller into its 82815 GMCH component (Figure
6-1).
4 MB SDRAM
Display Cache
AGP Bus
RGB
Monitor
82815 GMCH
FSB
I/F
Direct AGP
Graphics
Controller
SDRAM
Controller
Hub Link
I/F
Described in Chapter 3
Described in Chapter 4
Figure 6-1. 815E-Based Graphics, Block diagram
6.2.1 FUNCTIONAL DESCRIPTION
The graphics controller (Figure 6-2) integrated into the 82815 GMCH component includes 2D and
3D accelerator engines working with a deeply-pipelined pre-processor. The controller supports perspective-correct texture mapping, bilinear and anisotropic Mip-mapping, Alpha blending,
Gouraud shading, and fogging.
The controller uses a “Direct AGP” interface that allows the Intel graphics controller to use a portion of system memory for instructions, textures, and frame (display) buffering. Using a process called Dynamic Video Memory Technology (DVMT), the controller dynamically allocates display and texture memory amounts according to the needs of the application.
The controller also uses four megabytes of SDRAM (soldered down in the Deskpro EN SFF, separate GPA card in the Deskpro SDT/CMT) as a display cache especially suited for 3D operation. The additional Display Cache allows the graphics controller to simultaneously render graphics to the Z-buffer (in the display cache) while processing textures in a portion of system memory.
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Monitor
Connector
HSync
HSync
RGB
RAM
DAC
82815 GMCH
Direct AGP Graphics Controller
2D
Engine
3D
Engine
Pipelined
Preprocessor
AGP
I/F
FSB I/F &
SDRAM
Cntlr.
AGP Bus
4 MB SDRAM
Display Cache
Figure 6-2. 82815 GMCH Integrated Graphics Subsystem
The integrated graphics controller includes special enhancements for 2D operations. Motion compensation logic is included to improve performance during software decoding of MPEG2 video. Hardware cursor and overlay engines relieve software processing and provide independent gamma correction, saturation, and brightness control.
The 230-MHz RAMDAC can support a variable-scan rate monitor up to a maximum resolution of
1600 x 1200 with 256 colors. Video BIOS for the controller is held in the system BIOS ROM and copied into systems memory at runtime for maximum performance.
6.2.1.1 Feature Summary
♦
Accelerated driver support for Windows 3.1/95/98/2000, Windows NT 4.0, OS/2
♦
MS ActiveMovie and Media Player support for Win95
♦
Direct 3D support
♦
MS Direct Draw 5/6 support
♦
AGP 2X interface
♦
DDC2B compliant
♦
Accelerator engine support for:
•
3-ROP BitBLT
•
Line Draw
•
Color expansion
•
Video color conversion/scaling
•
Motion video
•
Triangle setup
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Chapter 6 Embedded Graphics Subsystems
6.2.2 DISPLAY MODES
The Intel graphics controller supports the following 2D display modes:
Table 6-1. 815E-Based Graphics Display Modes
Table 6-1.
815E-Based Graphics Display Modes
Resolution
640 x 480
640 x 480
640 x 480
720 x 480
720 x 480
720 x 480
720 x 576
720 x 576
720 x 576
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 720
1280 x 720
1280 x 720
1280 x 960
1280 x 960
1280 x 960
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 900
1600 x 900
1600 x 1200
Bits per pixel
16
24
8
16
24
8
16
24
8
16
24
8
8
16
24
8
16
24
8
16
24
8
16
24
8
16
24
8
16
8
Color Depth
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
256
6.2.3 MEMORY MANAGEMENT
The 815E-based graphics controller uses a specific amount of system memory allocated as follows:
Video BIOS – 512 or 1024 kilobytes. An OS report of available system memory will be the total amount installed LESS this amount.
Graphics Memory – Prior to the PV 4.x driver being loaded, the graphics memory will be one megabyte for supporting standard VGA modes. After driver load, memory allocation will be set by the Dynamic Video Memory Technology (DVMT) for rendering, Z-buffering, and displaying according to need and total system memory availablility. Assuming the presence of 4 megabytes of display cache (standard on these systems) the following amounts will be allocated:
♦ w/Windows 98 and 32 megabytes of system memory – 9 megabytes
♦ w/Windows 98, NT 4.0, or 2000 and 64/128 megabytes of system memory – 12 megabytes
Refresh Rate
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
75, 85
75, 85
75, 85
60, 75, 85
60, 75, 85
60, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 75, 85
60, 75, 85
60, 75, 85
60, 75, 85
60, 75, 85
60, 75, 85
60, 70, 72, 75, 85
60, 70, 72, 75, 85
60, 70, 75, 85
60, 75, 85
60, 75, 85
60, 70, 72, 75, 85
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6.2.4 815E-BASED GRAPHICS PROGRAMMING
The 815E-based graphics controller is configured using PCI configuration registers listed in Table
6-2.
Table 6-2. 815E-Based Graphics Controller PCI Configuration Registers
Table 6-2.
815E-Based Graphics Controller PCI Configuration Registers
(GMCH, Function 2)
PCI
Config.
Addr.
00, 01h
02, 03h
Register
Vendor ID
Device ID
04, 05h
06, 07h
Command
Status
08h Revision ID
0A, 0Bh Class Code
0Eh
0Fh
Header Type
BIST
10-13h
14-17h
Memory Range Addr.
Mem. Mapped Range Addr.
2C, 2Dh Subsys. Vendor ID
NOTE:
Reset
Value
8086h 2E, 2Fh
1132h 30-33h
0004h 34h
02B0h 3Ch
02h 3Dh
0003h 3Eh
01h
00h
8
0’s
PCI
Config.
Addr.
3Fh
DC, DDh
DE, DFh
E0, E1h
0000h E2-FFh
Register
Subsystem ID
Vid. BIOS Base Addr.
Capabilities Pointer
Interrupt Line
Interrupt Pin
Min. Grant
Max. Latency
Pwr. Mgmt. Capabilities
Pwr. Mgmt. Capabilites
Pwr. Mgmt. Control
Reserved
Assume unmarked locations/gaps as reserved. Refer to Intel documentation for detailed register descriptions.
The graphics controller is controlled through memory-mapped registers by the appropriate software driver.
Reset
Value
0000h
0’s
DCh
00h
01h
00h
00h
0001h
0022h
0000h
--
6.2.5 UPGRADING 815E-BASED GRAPHICS
The method of upgrading the 815E-based graphics controller is dependent on the system type.
Small Form Factor: No AGP slot is provided for upgrading the AGP graphics. Since PCI graphics adapters are generally considered inferior to AGP types, a true "upgrade" is not possible on these systems. However, dual-monitor support is possible by adding a PCI-type graphics card.
Compaq Deskpro EN Slim Desktop/Configurable Minitower: Upgrading the AGP graphics is facilitated by replacing the existing GPA card with an AGP graphics adapter card. During POST, the BIOS will detect the presence of the AGP graphics adapter on the AGP bus and disable the
815E-based graphics controller. Dual monitor support is possible by adding a PCI graphics card.
Compaq Deskpro Personal Computers
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6-5
Chapter 6 Embedded Graphics Subsystems
6.3
NVIDIA GRAPHICS SUBSYSTEM
The NVIDIA TNT2 Pro AGP graphics controller is available in select Deskpro EN series configurations as the premium graphics solution. This solution is resident on the system board in
Compaq Deskpro EN Small Form Factor systems and as a separate AGP card in Compaq Deskpro
EN Slim Desktop and Configurable Minitower systems. This subsection describes only the on- board NVIDIA graphics subsystem used on Small Form Factor systems. The NVIDIA graphics card used in Deskpro EN Slim Desktop/Configurable Minitower systems is
described in Appendix d.
82815
GMCH
AGP
Bus
AGP 4X
I/F
NVIDIA TNT2 Graphics Controller
2D/VGA
Engine
Video
Scalar
3D Array
Engine
Memory
I/F
CRT
Controller
300-MHz
RAM
DAC
128-bit
166-MHz
Data Bus
16 MB
SDRAM
Frame Buffer
HSync
VSync
Monitor
Connector
RGB
Figure 6-3. NVIDIA TNT2 Pro Graphics Subsystem
The NVIDIA TNT2 Pro supports AGP 4X protocol, providing a peak transfer rate of 1GB/s. The controller achieves high 3D performance with special rendering techniques such as single-cycle multi-texturing and parallel triangle processing. The controller utilizes a portion of system memory for texturing, instructions, and control while employing 16 megabytes of SDRAM for the frame (display) buffer. Video BIOS is included in the system BIOS ROM and copied into system memory at runtime.
Key features of the NVIDIA-based subsystem include:
♦
300-MHz DAC
♦
QuickDraw, DirectX 6, PC98/99, Broadcast PC, DirectShow, OpenGL compatible
♦
2D accelerator with:
•
Programmable, transparent BitBLT
•
Full acceleration MS DirectDraw support
•
High speed 32-bit VGA core
♦
3D accelerator with:
•
Ultra-pipelined floating point engine
•
Hardware dithering including LUT textures
♦
Video support features including:
•
Color conversion and scaling
•
30-FPS DVD performance
♦
Universal driver compatibility allows easy upgrading to other NVIDIA controllers
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6.3.1 DISPLAY MODES
Resolution
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
1600 x 1200
1800 x 1440
1800 x 1440
1800 x 1440
1920 x 1080
1920 x 1080
1920 x 1080
1920 x 1200
The graphics modes supported by the NVIDIA controller are listed in Tables 6-3.
Table 6-3. NVIDIA TNT2 Pro Graphics Display Modes
Table 6-3.
NVIDIA TNT2 Pro Graphics Display Modes
Bits per pixel
8
16
24
8
16
24
8
16
24
8
16
24
8
16
24
8
16
24
8
16
24
8
16
24
8
Color Depth
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
Max. Refresh Frequency (Hz)
85
85
85
85
85
85
85
85
85
85
85
85
75
85
85
85
85
85
85
85
85
85
85
85
85
6.3.2 NVIDIA GRAPHICS PROGRAMMING
The NVIDIA graphics controller is configured through PCI configuration registers and controlled through memory-mapped registers by an appropriate software driver.
6.3.3 NVIDIA GRAPHICS UPGRADING
The method of upgrading the NVIDIA graphics controller is determined by the system type.
Compaq Deskpro EN Small Form Factor: No AGP slot is provided for upgrading the NVIDIA graphics on Deskpro EN SFF models, which have the NVIDIA graphics controller embedded on the system board. Since PCI graphics adapters are generally considered inferior to AGP types, a true "upgrade" is not possible on these systems. However, dual-monitor support is possible by adding a PCI-type graphics card.
Compaq Deskpro EN Slim Desktop/Configurable Minitower: Upgrading the AGP graphics is facilitated by replacing the existing nVIDIA graphics card with another AGP graphics adapter card. During POST, the BIOS will detect the presence of the AGP graphics adapter in the AGP slot and inhibit the integrated controller of the 82815 GMCH. Dual monitor support is possible by adding a PCI graphics card.
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Chapter 6 Embedded Graphics Subsystems
6.4
MONITOR POWER MANAGEMENT CONTROL
The embedded graphics controllers provide monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table 6-4 lists the monitor power conditions.
Table 6-4. Monitor Power Management Conditions
HSYNC VSYNC
Active Active
Active Inactive
Inactive Inactive
Table 6-4.
Monitor Power Management Conditions
Power Mode
On
Suspend
Off
Description
Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
6.5
MONITOR CONNECTOR
A DB-15 connector is provided on the rear chassis for connection to an analog monitor. The pinout for this connector is shown in Figure 6-3 and Table 6-5.
9
Figure 6-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table 6-5. DB-15 Monitor Connector Pinout
Table 6-5.
DB-15 Monitor Connector Pinout
6
7
8
Pin Signal
1 R Red Analog
2 G
3
4
B
NC
Green Analog
Not Connected
5 GND Ground
R GND
G GND
B GND
Red Analog Ground
Blue Analog Ground
Green Analog Ground
9 PWR
10 GND
11
12
NC
SDA
13 HSync
14 VSync
15
--
SCL
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Vertical Sync
DDC2-B Clock
--
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Third Edition - April 2001
Technical Reference Guide
Chapter 7
POWER and SIGNAL
DISTRIBUTION
7.
Chapter 7 POWER SUPPLY AND DISTRIBUTION
7.1
INTRODUCTION
This chapter describes the power supply and method of general power and signal distribution.
Topics covered in this chapter include:
♦
Power supply assembly/control (7.2) page 7-1
♦
Power distribution (7.3) page 7-5
♦
Signal distribution (7.4) page 7-8
7.1
POWER SUPPLY ASSEMBLY/CONTROL
This system features a power supply assembly that is controlled through programmable logic
(Figure 7-1).
Front Bezel
Power On/Off
System/Backplane Board
Power On
Slots, Chipsets, Logic
& Voltage Regulators
110/230 VAC
Mains
110/230 VAC
Select SW
110 VAC
230 VAC
PS
On
Fan
Off
Fan
Spd
+5
AUX
+3.3
AUX
Power Supply
Assembly
+5 VDC
-5 VDC
+12 VDC
-12 VDC
Figure 7–1. Power Distribution and Control, Block Diagram
Drives
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Chapter 7 Power and Signal Distribution
7.1.1 POWER SUPPLY ASSEMBLY
The power supply assembly is contained in a single unit that features a selectable input voltage:
90-132 VAC and 180-264 VAC. Small Form Factor systems use a 120-watt supply while all other systems employ a 200-watt supply. Tables 7-1 and 7-2 list the specifications of the power supplies.
Table 7–1. 120-Watt Power Supply Assembly Specifications
Table 7-1.
120-Watt Power Supply Assembly Specifications (P/N 165997)
Input Line Voltage:
110 VAC Setting
220 VAC Setting
Range/
Tolerance
90 - 132
VAC
180-264
VAC
47 - 63 Hz
Min. Current
Loading [1]
--
--
--
Max.
Current
--
--
--
Surge
Current [2]
--
--
-- Line Frequency
Steady State Input (VAC) Current
+3.3 VDC Output
+5 VDC Output
+3 AUX Output
+5 AUX Output
+12 VDC Output
-12 VDC Output
+/- 5%
+/- 5 %
+/- 5 %
+/- 4 %
+/- 5 %
+/- 10 %
0.60 A
0.50 A
0.20 A
0.20 A
0.00 A
0.00 A
11.0 A
11.0 A
1.00 A
2.40 A
3.00 A
0.15 A
11.0 A
11.0 A
1.00 A
2.40 A
3.50 A
0.15 A
NOTES:
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 tolerance +/- 10%.
Table 7–2. 200-Watt Power Supply Assembly Specifications
Max.
Ripple
--
--
--
50 mV
65 mV
50 mV
65 mV
120 mV
200 mV
Table 7-2.
200-Watt Power Supply Assembly Specifications (P/N 161071 or 386461)
Input Line Voltage:
110 VAC Setting
220 VAC Setting
Line Frequency
Steady State Input (VAC) Current
+3.3 VDC Output
+3.3 AUX
+5 VDC Output
-5 VDC Output
+5 AUX Output
+12 VDC Output
-12 VDC Output
NOTES:
Range/
Tolerance
90 - 132
VAC
180-264
VAC
47 - 63 Hz
+/- 4%
+/-5 %
+/- 5 %
+/- 10 %
+/- 4 %
+/- 5 %
+/- 10 %
Min. Current
Loading [1]
--
--
--
1.40 A
0.00
1.40 A
0.00 A
0.00 A
0.07 A
0.00 A
Max.
Current
--
--
--
18.0 A [3]
2.00 A
20.0 A [3]
0.15 A
1.70 A
6.50 A
0.15 A
Surge
Current [2]
--
--
--
18.0 A
2.00 A
20.0 A
0.15 A
1.70 A
8.50 A
0.15 A
Max.
Ripple
--
--
--
50 mV
50 mV
50 mV
100 mV
50 mV
120 mV
200 mV
[1] Minimum loading requirements must be met at all times to ensure normal operation
and specification compliance.
[2] Surge duration no longer than 10 seconds and +12 tolerance +/- 10%.
[3] Maximum combined power provided by +3.3 and +5 VDC outputs should not exceed 135 watts.
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Technical Reference Guide
7.1.2 POWER CONTROL
The power supply assembly is controlled digitally by the PS On signal (Figure 7-1). When PS On is asserted, the Power Supply Assembly is activated and all voltage outputs are produced. When
PS On is de-asserted, the Power Supply Assembly is off and all voltages (except +3.3 AUX and
+5 AUX) are not generated. Note that the +3.3 AUX and +5 AUX voltages are always produced as long as the system is connected to a live AC source.
7.1.2.1 Power Button
The PS On signal is typically controlled through the Power Button which, when pressed and released, applies a negative (grounding) pulse to the power control logic. The resultant action of pressing the power button depends on the state and mode of the system at that time and is described as follows:
System State
Off
On, ACPI Disabled
On, ACPI Enabled
Pressed Power Button Results In:
Negative pulse, of which the falling edge results in power control logic asserting PS
On signal to Power Supply Assembly, which then initializes. ACPI four-second counter is not active.
Negative pulse, of which the falling edge causes power control logic to de-assert the
PS On signal. ACPI four-second counter is not active.
Pressed and Released Under Four Seconds:
Negative pulse, of which the falling edge causes power control logic to
generate SMI-, set a bit in the SMI source register, set a bit for button status,
and start four-second counter. Software should clear the button status bit
within four seconds and the Suspend state is entered. If the status bit is
not cleared by software in four seconds PS On is de-asserted and the
power supply assembly shuts down (this operation is meant as a guard if
the OS is hung).
Pressed and Held At least Four Seconds Before Release:
If the button is held in for at least four seconds and then released, PS On is
negated, de-activating the power supply.
7.1.2.2 Power LED Indications
A dual-color LED is used to indicate system power status. The front panel (bezel) power LED provides a visual indication of key system conditions listed as follows:
Power LED
Steady green
Blinking green @ 1 Hz
Blinking green @ 2 Hz
Blinking green @ 4 Hz
Steady red
Blinks red @ 2 Hz
Blinks red @ 1 Hz
Blinks red @ 4 Hz
Condition
Normal full-on operation (S0)
Suspend mode (S1)
Sleep (suspend to RAM) state (S3)
Sleep (suspend to Disk) state (S4)
Processor not seated
Power supply crowbar activated
BIOS ROM error
Thermal condition: processor has overheated and shut down
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Chapter 7 Power and Signal Distribution
7.1.2.3 Wake Up Events
The PS On signal can be activated with a power “wake-up” of the system due to the occurrence of a magic packet, serial port ring, or PCI power management (PME) event. These events can be individually enabled through the Setup utility to wake up the system from a sleep (low power) state.
NOTE: Wake-up functionality requires that certain circuits receive auxiliary power while the system is turned off. The system unit must be plugged into a live AC outlet for wake up events to function. Using an AC power strip to control system unit power will disable wake-up event functionality.
The wake up sequence for each event occurs as follows:
Wake-On-LAN
The network interface controller (NIC) can be configured for detection of a “Magic Packet” and wake the system up from sleep mode through the assertion of the PME- signal on the PCI bus.
Refer to Chapter 5, “Network Support” for more information.
Modem Ring
A ring condition on serial port A (COM1) or serial port B (COM2) can be detected by the power control logic and, if so configured, cause the PS On signal to be asserted.
Power Management Event
A power management event that asserts the PME- signal on the PCI bus can be enabled to cause the power control logic to generate the PS On. Note that the PCI card must be PCI ver. 2.2
compliant to support this function.
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Technical Reference Guide
7.2
POWER DISTRIBUTION
7.2.1 3.3/5/12 VDC DISTRIBUTION
The power supply assembly includes a multi-connector cable assembly that routes +3.3 VDC, +5
VDC, -5 VDC, +12 VC, and -12 VDC to the system board as well as to the individual drive assemblies. Figure 7-2 shows the power supply cabling for the Deskpro EN SFF series.
P3, 4
Power Supply
Assembly
(p/n 165997)
P4 P3
P2
Drive
Assemblies
P1
System
Board
1 2 3 4
P2
4 3 2 1
P1
8
1
9
2
10 11 12 13 14
3 4 5 6 7
Pin 7 Conn. # Pin 1 Pin 2 Pin 3 Pin 4 Pin 5
P1 [1] +3.3
AUX
-12 FO
P2 +5
PS On +5 AUX
P3 +12 GND
NOTES:
[1] This row represents pins 8-14 of connector P1.
All + and - values are VDC .
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
FO = Fan off
FS = Fan speed
Pin 6
FS +12 VDC
Figure 7–2. Small Form Factor Power Cable Diagram
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Chapter 7 Power and Signal Distribution
Figure 7-3 shows the power supply cabling for Deskpro EN SDT/CMT series units.
P6
P4
P7
P5
P2
To
Drive
Assemblies
P7
4 3 2 1
P2-P6
Power Supply
Assembly
(SP# 161071 or 386461)
P1
To
System
Board
1 2 3 4
P1
13 14 15 16 17 18 19 20 21 22 23 24
1 2 3 4 5 6 7 8 9 10 11 12
Conn. # Pin 1
P1 [1] +3.3
Pin 2
-12
Pin 3 Pin 4 Pin 5
Rtn
Pin 6
PS On RTN RSRTN
NOTES:
[1] This row represents pins 13-24 of connector P1.
All + and - values are VDC .
RTN = Return (signal ground)
GND = Power ground
RS = Remote sense
FO = Fan off
FSpd = Fan speed
FS = Fan Sink
Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12
+5 +3.3Aux
RTN -5 +5 +5 +3.3RS FS
Figure 7–3. Slim Desktop/Configurable Minitower Power Cable Diagram
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Technical Reference Guide
7.2.2 LOW VOLTAGE DISTRIBUTION
Voltages less than 3.3 VDCincluding processor core (VccP) voltage are produced through regulator circuitry on the system board.
+5 AUX
+5 VDC
S3 Mode
RAM PWR
Circuit
3.3 VDC
DIMMs
AGP Bus
Type Det-
AGP PWR
VDDQ [1]
AGP Bus
+5 VDC
LM317
Regulator
Circuit
2.5 VDC
+3.3 VDC
Pull-Up Logic
Power Supply
+3.3 VDC
Regulator
Circuit
VTT (+1.5)
Processor
Processor
+5 VDC
+12 VDC
VID0
VID1
VID2
VID3
Regulator
Circuit
VccP (see text)
NOTE:
[1] VDDQ = 1.5 for AGP 4X cards (Type Det- grounded), 3.3 for AGP 1X/2X cards (Type Det- left open).
Figure 7–4. Low Voltage Supply and Distribution Diagram
The VccP regulator produces the VccP (processor core) voltage according to the strapping of signals VID3..0 by the processor. The possible voltages available are listed as follows:
VID 3..0 VccP VID 3..0 VccP
Refer to Chapter 3 for a listing of the core voltages set by the Celeron (Table 3-1) and Pentium III
(Table 3-2) processors.
Compaq Deskpro Personal Computers 7-7
Third Edition - April 2001
Chapter 7 Power and Signal Distribution
7.3
SIGNAL DISTRIBUTION
Figures 7-4 and 7-5 show general signal distribution between the main subassemblies of the system units.
System
Board
(PCA # 010633,
010700, 011035,
011308, or 011311)
Riser
Card
Conn
J50
Conn.
P200
Spkr.
Conn. P6
Power
Conn P1
PCI
Bus
AOL/SOS
CD Audio
SCSI
LED
CD Audio
Conn P7
Riser Card
(PCA #
010636)
Cover
Sense
Audio
3/5/12 VDC, 3/5 AUX
Fan Cntrl., PS On
L/R Audio
Solenoid
Smart Cover Lock/Unlock
Power
Supply
Assembly
IDE I/F
Pri. IDE
Conn P20
IDE
Hard Drive
5, 12 VDC
NOTES:
Sec. IDE
Conn P21
CD Audio
Conn P7
Dsk.
Conn P10
Mouse
Conn J67
Kybd
Conn J66
COM1
Conn P89
IDE I/F
L/R Audio
CD-ROM
Mouse or
Dsk I/F Diskette Drive
Keyboard
COM1 (Serial A)
DB-9 Conn. [1]
5, 12 VDC
5, 12 VDC
[1] Connector mounted on rear chassis panel.
PCA #010633 and 010700 only. PCA #011035 has speaker mounted on system board.
Figure 7–5. Small Form Factor Signal Distribution Diagram
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Technical Reference Guide
Chassis Fan
Graphics
Controller
Audio
AGP
Bus
Fan
PWR
AGP
Connector
Conn.
P8
System
Board
(PCA # 010630,
011032, or 011305)
Conn.
P6
Conn.
P214
Conn.
P215
Conn.
P5 [1]
Conn.
P1
Pri. IDE
Conn. P20
Cover
Sense
Smart Cover
Lock/Unlock
Pwr Btn, Pwr/HD LED
3/5/12 VDC, 3/5AUX
IDE I/F
Fan Cntrl., PS On
IDE
Data, Cntl
Cover Sensor
Solenoid
IDE
Hard Drive
CD-ROM
Sec. IDE
Conn. P21
Audio
Conn. P7
Dsk.
Conn. P10
PCI
Slot Conn.
Mouse
Conn. J67
Kybd
Conn. J66
L/R Audio
Dskt.
Data, Cntl
Diskette Drive
PCI
Bus
Adaptec
29160N
SCSI
Adapter Card
Mouse
Keyboard
Slim Desktop Only
Front Bezel Board (PCA# 180706)
Power On
Power On/Off
HD Activity
Power
Supply
Assembly
5, 12 VDC
5, 12 VDC
5, 12 VDC
SCSI
Bus or
SCSI
Hard Drive
Configurable Minitower
Only
Power On
Power On/Off
HD Activity
NOTES:
Models with 933 MHz or faster processor.
Models with AGP graphics controller card.
Select Workstation AP230 models only.
[1] See Figure 7-8 for header pinout.
Figure 7–6. Slim Desktop/Configurable Minitower Models Signal Distribution Diagram
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Chapter 7 Power and Signal Distribution
Power Button/LED Header P5
(Slim Desktop/Configurable Minitower only)
1 HD LED anode
3 HD LED cathode
4 PWR LED anode
5 PWR LED cathode
6 PWR button (gnd)
7 PWR button (+)
8 SCSI HD LED [1]
9 SCSI HD LED [1]
CD Audio Header P7
1 Ground
2 Audio (left channel)
3 Ground
4 Audio (right channel)
AOL/SOS Header P12
BIOS Fail 1
Intrusion 3
Fan Alert 5
Ground 7
2 OS Fail
4 Thermal
6 Pwr
Serial Port A/COM1 Header P16
(Small Form Factor only)
NOTE:
Carrier Detect
RX Data 2
TX Data 3
Data Terminal Ready 4
Ground 5
6 Data Set Ready
7 Request to Send
8 Clear to Send
9 Ring Indicate
No polarity consideration required for connection to speaker header P6 or SCSI HD LED header P29.
[1] Separate cable connection for these two pins (equivalent of header P29 on other systems).
Figure 7–7. Header Pinouts
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Technical Reference Guide
Chapter 8
BIOS ROM
8.
Chapter 8 BIOS ROM
8.1
INTRODUCTION
The Basic Input/Output System (BIOS) of the computer is a collection of machine language programs stored as firmware in read-only memory (ROM). The BIOS ROM includes such functions as Power-On Self Test (POST), PCI device initialization, Plug ‘n Play support, power management activities, and the Setup utility. The firmware contained in the BIOS ROM supports the following operating systems and specifications:
♦
DOS 6.2
♦
Windows 3.1 (and Windows for Workgroups 3.11)
♦
Windows 95, 98, and 2000
♦
Windows NT 3.5 and 4.0
♦
OS/2 ver 2.1 and OS/2 Warp
♦
SCO Unix
♦
DMI 2.1
♦
Intel Wired for Management (WfM) ver. 2.2
♦
Alert-On-LAN (AOL) and Wake-On-LAN (WOL)
♦
ACPI and OnNow
♦
APM 1.2
♦
SMBIOS 2.3.1
♦
PC98/99 and NetPC
♦
Boot Integrity Services (BIS)
♦
Video BIOS on systems with 815E-based graphics or integrated nVIDIA AGP graphics
♦
Intel PXE boot ROM for the integrated LAN controller
♦
BIOS Boot Specification 1.01
♦
Enhanced Disk Drive Specification 3.0
♦
“El Torito” Bootable CD-ROM Format Specification 1.0
♦
ATAPI Removeable Media Device BIOS Specification 1.0
The BIOS ROM is a 512KB Intel Firmware Hub (or Firmware Hub-compatible) part. The runtime portion of the BIOS resides in a 128KB block from E0000h to FFFFFh.
This chapter includes the following topics:
♦
ROM flashing (8.2)
♦
Boot functions (8.3)
♦
Setup utility (8.4)
♦
Client management functions (8.5)
♦
PnP support (8.6)
♦
Power management functions (8.7)
♦
USB legacy support (8.8) page 8-2 page 8-4 page 8-6 page 8-13 page 8-15 page 8-17 page 8-24
Compaq Deskpro Personal Computers 8-1
Third Edition - April 2001
Chapter 8 BIOS ROM
8.2
ROM FLASHING
The system BIOS firmware is contained in a flash ROM device that can be re-written with BIOS code (using the ROMPAQ utility or a remote flash program) allowing easy upgrading, including changing the splash screen displayed during the POST routine.
8.2.1 UPGRADING
Upgrading the BIOS is not normally required but may be necessary if changes are made to the unit’s operating system, hard drive, or processor. All BIOS ROM upgrades are available directly from Compaq. Flashing is done either locally with a ROMPaq diskette or remotely using the network boot function (described in the section 8.3.2).
This system includes 64 KB of write-protected boot block ROM that provides a way to recover from a failed remote flashing of the system BIOS ROM. If the BIOS ROM fails the flash check, the boot block code provides the minimum amount of support necessary to allow booting the system from the diskette drive and re-flashing the system ROM with a ROMPAQ diskette. Note that if an administrator password has been set in the system the boot block will prompt for this password by illuminating the caps lock keyboard LED and displaying a message if video support is available. A PS/2 keyboard must be used during bootblock operation.
Since video may not be available during the initial boot sequence the boot block routine uses the
Num Lock, Caps Lock, and Scroll Lock LEDs of the PS/2 keyboard to communicate the status of the ROM flash as follows:
Table 8-1. Boot Block Codes
Num Lock
LED
On
Cap Lock
LED
Off
Table 8-1.
Boot Block Codes
Scroll Lock
LED Meaning
Off Boot failed. Reset required for retry.
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Technical Reference Guide
8.2.2 CHANGEABLE SPLASH SCREEN
The splash screen (image displayed during POST) is stored in the BIOS ROM and may be replaced with another image of choice by using the Image Flash utility (Flashi.exe). The Image
Flash utility allows the user to browse directories for image searching and pre-viewing.
Background and foreground colors can be chosen from the selected image’s palette.
The splash screen image requirements are as follows:
♦
Format:
♦
Size:
Windows bitmap with 4-bit RLE encoding
424 (width) x 320 (height) pixels
♦
Colors: 16 (4 bits per pixel)
♦
File Size: < 64 KB
The Image Flash utility can be invoked at a command line for quickly flashing a known image as follows:
>\Flashi.exe [Image_Filename] [Background_Color] [Foreground_Color]
The utility checks to insure that the specified image meets the splash screen requirements listed above or it will not be loaded into the ROM.
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Chapter 8 BIOS ROM
8.3
BOOT FUNCTIONS
The BIOS supports various functions related to the boot process, including those that occur during the Power On Self-Test (POST) routine.
8.3.1 BOOT DEVICE ORDER
The default boot device order is as follows:
1.
CD-ROM drive (EL Torito CD images)
2.
Diskette drive (A)
3.
Hard drive (C)
4.
Network boot
The order can be changed in the ROM-based Setup utility (accessed by pressing F10 when so prompted during POST).
8.3.2 NETWORK BOOT (F12) SUPPORT
The BIOS supports booting the system to a network server. The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST. Booting to a network server allows for such functions as:
♦
Flashing a ROM on a system without a functional operating system (OS).
♦
Installing an OS.
♦
Installing an application.
These systems include, as standard, an integrated Intel 82562-equivalent NIC with Preboot
Execution Environment (PXE) ROM and can boot with a NetPC-compliant server.
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8.3.3 MEMORY DETECTION AND CONFIGURATION
This system uses the Serial Presence Detect (SPD) method of determining the installed DIMM configuration. The BIOS communicates with an EEPROM on each DIMM through the SMBus to obtain data on the following DIMM parameters:
♦
Presence
♦
Size
♦
Type
♦
Timing/CAS latency
♦
PC133 capability
NOTE: Refer to Chapter 3, “Processor/Memory Subsystem” for the SPD format and DIMM data specific to this system.
The BIOS performs memory detection and configuration with the following steps:
1.
Program the buffer strength control registers based on SPD data and the DIMM slots that are populated.
2.
Determine the common CAS latency that can be supported by the DIMMs.
3.
Determine the memory size for each DIMM and program the GMCH accordingly.
4.
Enable refresh
5.
Determine if the memory configuration will allow for 133MHz memory operation and program the memory clock and GMCH (see note below)
NOTE: The presence of PC133-compliant DIMMS will be indicated by BIOS reading 75h from byte 9 and 64h or 85h from byte 126. For PC133 operation to occur the FSB of the processor must be running at 133 MHz and all installed DIMMs must be PC133-compliant and total no more than four “sides.” Refer to Chapter 3 for more details on PC133 operation.
8.3.4 BOOT ERROR CODES
The BIOS provides visual and audible indications of a failed system boot by using the keyboard
LEDs and the system speaker. The error conditions are as follows:
Table 8-2. Boot Error Codes
Visual [1]
Table 8-2. Boot Error Codes
Audible Meaning
Num Lock LED blinks
Scroll Lock LED blinks
Caps Lock LED blinks
1 short, 2 long beeps System memory not present or incompatible.
2 long, 1 short beeps Hardware failure before graphics initialization.
1 long, 2 short beeps Graphics controller not present or failed to initialize.
1 long, 3 short beeps ROM failure. Num, Caps, Scroll Lock LEDs blink
Num, Caps, Scroll Lock LEDs blink in sequence
NOTE: none
[1] Provided with PS/2 keyboard only.
Network service mode
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Chapter 8 BIOS ROM
8.4
SETUP UTILITY
Storage
The Setup utility (stored in ROM) allows the user to configure system functions involving security, power management, and system resources. The Setup utility is ROM-based and invoked when the F10 key is pressed during the time the F10 prompt is displayed in the lower right-hand corner of the screen during the POST routine. Highlights of the Setup utility are described in the following table.
NOTE: Support for Computer Setup options may vary depending on your specific hardware configuration.
Table 8-3. Setup Utility Functions
Table 8-3.
Setup Utility Functions
Heading Option Description
About
Set Time and Date
Save to Diskette
Restore from Diskette
Set Defaults and Exit
Ignore Changes and Exit
Save Changes and Exit
Device Configuration
Product name
Processor type/speed/stepping
Cache size (L1/L2)
Installed memory size and frequency
System ROM (includes family name and version)
System board revision
Chassis serial number
Asset tracking number
Integrated MAC for embedded, enabled NIC (if applicable)
Displays copyright notice.
Allows you to set system time and date.
Saves system configuration, including CMOS, to a blank, formatted 1.44-MB diskette.
Restores system configuration, including CMOS, from a diskette.
Restores factory default settings, which includes clearing any established passwords.
Exits Computer Setup without applying or saving any changes.
Saves changes to system configuration and exits
Computer Setup.
Lists all installed storage devices. The following options appear when a device is selected:
Diskette Type (For legacy diskette drives only)
Identifies the highest capacity media type accepted by the diskette drive. Options are 3.5" 1.44 MB,
3.5" 720 KB, 5.25" 1.2 MB, 5.25" 360 KB, and Not
Installed.
Drive Emulation (LS-120 and ZIP drives only)
Allows you to select a drive emulation type for a storage device. (For example, a Zip drive can be made bootable by selecting hard disk or diskette emulation.)
Transfer Mode (IDE devices only)
Specifies the active data transfer mode. Options
(subject to device capabilities) are PIO 0, Max PIO,
Enhanced DMA, Ultra DMA 0, and Max UDMA.
Continued
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Table 8-3. Setup Utility Functions Continued
Heading Option
Storage
(continued)
Device
Configuration
(continued)
Storage Options
Description
Translation Mode (IDE disks only)
Lets you select the translation mode to be used for the device. This enables the BIOS to access disks partitioned and formatted on other systems and may be necessary for users of older versions of Unix (e.g., SCO Unix version 3.2).
Options are Bit-Shift, LBA Assisted, User, and None.
CAUTION: Ordinarily, the translation mode selected automatically by the BIOS should not be changed. If the selected translation mode is not compatible with the translation mode that was active when the disk was partitioned and formatted, the data on the disk will be inaccessible.
Translation Parameters (IDE Disks only)
Allows you to specify the parameters (logical cylinders, heads, and sectors per track) used by the BIOS to translate disk I/O requests (from the operating system or an application) into terms the hard drive can accept. Logical cylinders may not exceed 1024. The number of heads may not exceed 256. The number of sectors per track may not exceed 63. These fields are only visible and changeable when the drive translation mode is set to User.
Multisector Transfers (IDE ATA devices only)
Specifies how many sectors are transferred per multi-sector
PIO operation. Options (subject to device capabilities) are
Disabled, 8, and 16.
Quiet Drive (available on select drives only)
Performance - Allows the drive to operate at maximum performance.
Quiet (will not be displayed if not supported by drive)-
Reduces noise from the drive during operation. When set to
Quiet, the drive will not operate at maximum performance.
Removable Media Boot
Enables/disables ability to boot the system from removable media.
Note: After saving changes to Removable Media Boot, the computer will restart. Turn the computer off, then on, manually.
Removable Media Write
Enables/disables ability to write data to removable media.
Note: This feature applies only to legacy diskette, IDE LS-120
Superdisk, and IDE PD-CD drives.
Primary IDE Controller
Allows you to enable or disable the primary IDE controller.
Secondary IDE Controller
Allows you to enable or disable the secondary IDE controller.
Diskette MBR Validation
Allows you to enable or disable strict validation of the diskette
Master Boot Record (MBR).
Note: If you use a bootable diskette image that you know to be valid, and it does not boot with Diskette MBR Validation enabled, you may need to disable this option in order to use the diskette.
Continued
Compaq Deskpro Personal Computers 8-7
Third Edition - April 2001
Chapter 8 BIOS ROM
Table 8-3. Setup Utility Functions Continued
Heading Option
Storage
(continued)
DPS Self-Test
Security
Boot Order
Setup Password
Power-On Password
Password Options
Description
Allows user to execute self-tests on IDE hard drives capable of performing the Drive Protection System
(DPS) self-tests.
Note: This selection will only appear when at least one drive capable of performing the IDE DPS self-tests is attached to the system
Allows user to specify the order in which attached peripheral devices (such as diskette drive, hard drive,
CD-ROM, or network interface card) are checked for a bootable operating system image. Each device on the list may be individually excluded from or included for consideration as a bootable operating system source.
Note: MS-DOS drive lettering assignments may not apply after a non-MS-DOS operating system has started.
To boot one time from a device other than the default device specified in Boot Order, restart the computer and press F9 when the F10=Setup message appears on the screen. When POST is completed, a list of bootable devices is displayed. Use the arrow keys to select a device and press the Enter key.
Allows user to set and enable setup (administrator) password.
Note: If the setup password is set, it is required to change Computer Setup options, flash the ROM, and make changes to certain plug and play settings under
Windows. Also, this password must be set in order to use some Compaq remote security tools.
See the Troubleshooting Guide for more information.
Allows user to set and enable power-on password.
See the Troubleshooting Guide for more information.
Allows user to:
Enable/disable network server mode.
Note: This selection will appear only if a power-on password is set.
Specify whether password is required for warm boot
(CTRL+ALT+DEL).
Note: This selection is available only when Network
Server Mode is disabled.
See the Desktop Management Guide for more information.
Enable/disable the Smart Cover Lock
Enable/disable Smart Cover Sensor.
Notify User alerts the user that the sensor has detected that the cover has been removed. Setup
Password requires that the setup password be entered to boot the computer if the sensor detects that the cover has been removed.
Feature supported on select models only. Refer to the
Desktop Management Guide for more information.
Continued
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Technical Reference Guide
Table 8-3. Setup Utility Functions Continued
Heading Option
Security
(continued)
Master Boot Record Security
Save Master Boot Record
Restore Master Boot Record
Device Security
Description
Allows user to enable or disable Master Boot
Record (MBR) Security. When enabled, the BIOS rejects all requests to write to the MBR on the current bootable disk. Each time the computer is powered on or rebooted, the BIOS compares the
MBR of the current bootable disk to the previouslysaved MBR. If changes are detected, you are given the option of saving the MBR on the current bootable disk, restoring the previously-saved MBR, or disabling MBR Security. You must know the setup password, if one is set.
Note: Disable MBR Security before intentionally changing the formatting or partitioning of the current bootable disk. Several disk utilities (such as
FDISK and FORMAT) attempt to update the MBR.
If MBR Security is enabled and disk accesses are being serviced by the BIOS, write requests to the
MBR are rejected, causing the utilities to report errors. If MBR Security is enabled and disk accesses are being serviced by the operating system, any MBR change will be detected by the
BIOS during the next reboot, and an MBR Security warning message will be displayed.
Saves a backup copy of the Master Boot Record of the current bootable disk.
Note: Only appears if MBR Security is enabled.
Restores the backup Master Boot Record to the current bootable disk.
Note: Only appears if all of the following conditions are true:
MBR Security is enabled
A backup copy of the MBR has been previously saved
The current bootable disk is the same disk from which the backup copy of the MBR was saved.
Enables/disables serial, parallel, and USB ports and audio security.
Network Service Boot
System IDs
Enables/disables the computer’s ability to boot from an operating system installed on a network server.
(Feature available on NIC models only; the network controller must reside on the PCI bus or be embedded on the system board.)
Allows user to set:
Asset tag (16-byte identifier) and Ownership Tag
(80-byte identifier displayed during POST) -
Refer to the Desktop Management guide for
more information
Chassis serial number or Universal Unique
Identifier (UUID) number - If current number is
invalid (these ID numbers are normally set in the
factory and are used to uniquely identify the system)
Keyboard locale setting (e.g., English or
German) for System ID entry.
Continued
Compaq Deskpro Personal Computers 8-9
Third Edition - April 2001
Chapter 8 BIOS ROM
Table 8-3. Setup Utility Functions Continued
Heading Option
Power Energy Saver
Advanced
(Advanced users only)
Timeouts
Energy Saver Options
Power-On Options
Onboard Devices
PCI Devices
Description
Allows user to set the energy saver mode
(advanced, disable, or minimal).
Note: In the minimal energy saver mode setting, the hard drive and system do not go into energy saver mode, but the setting allows you to press the power button to suspend the system.
This option is not available under ACPI-enabled operating systems.
Allows user to disable or manually select timeout values for the system and/or all attached IDE hard drives.
Note: This option has no effect under ACPI-enabled operating systems. This selection will only appear when energy saver mode is set to advanced.
Allows user to set:
Power button configuration (on/off or sleep/wake) under
APM-enabled operating systems
Power LED blink in suspend mode
(enable/disable). This option is not available under
ACPI-enabled operating systems.
Note: Energy Saver Options will not appear if the energy saver mode is disabled.
Allows user to set:
POST mode (QuickBoot, FullBoot, or FullBoot every 1-30
days)
POST messages (enable/disable)
Safe POST (enable/disable)
F10 prompt (enable/disable)
F12 prompt (enable/disable)
Option ROM prompt (enable/disable)
Remote wakeup boot sequence (remote
server/local hard drive)
After power loss (off/on)
If you connect your computer to an electric power strip, and would like to turn on power to the computer using the switch on the power strip, set this option to on.
Note: If you turn off power to your computer using the switch on a power strip, you will not be able to use the suspend/sleep feature or the
Remote Management features.
UUID (Universal Unique Identifier) (enable/disable)
Allows you to set resources for or disable onboard system devices (diskette controller, serial port, parallel port).
Lists currently installed PCI devices and their IRQ settings.
Allows you to reconfigure IRQ settings for these devices or to disable them entirely.
Continued
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Technical Reference Guide
Table 8-3. Setup Utility Functions Continued
Heading Option
Advanced
(continued)
Bus Options
Device Options
PCI VGA Configuration
Description
Allows user to enable or disable:
PCI bus mastering, which allows a PCI device to take control of the PCI bus
PCI VGA palette snooping, which sets the VGA palette snooping bit in PCI configuration space; this is only needed with more than one graphics controller installed
PCI SERR# Generation.
Allows user to set:
Printer mode (bi-directional, EPP & ECP, output only)
Num Lock state at power-on (off/on)
PME (power management event) wakeup events (enable/disable)
Processor cache (enable/disable)
Processor Number (enable/disable) for Pentium
III processors.
ACPI S3 support (enable/disable). S3 is an
ACPI (advanced configuration and power interface) sleep state that some add-in hardware options may not support.
AGP Aperture size (options vary depending on platform) allows you to modify the size of your AGP aperture size window.
Appears only if there are multiple PCI video adapters in the system. Allows users to specify which VGA controller will be the “boot” or primary
VGA controller.
Compaq Deskpro Personal Computers 8-11
Third Edition - April 2001
Chapter 8 BIOS ROM
8.5
CLIENT MANAGEMENT FUNCTIONS
Table 8-4 lists the client management BIOS functions supported by the systems covered in this guide. These functions, designed to support intelligent manageability applications, are Compaqspecific unless otherwise indicated.
Table 8-4. Client Management Functions (INT15)
Table 8-4.
Client Management Functions (INT15)
AX Function Mode
E800h
E813h
E814h
E816h
Get system ID
Get monitor data
Get system revision
Get temperature status
E817h
E818h
E819h
Get drive attribute
Get drive off-line test
Get chassis serial number
E820h [1] Get system memory map
E81Ah Write chassis serial number
E81Bh
E81Eh
E827h
Get hard drive threshold
Get hard drive ID
DIMM EEPROM Access
NOTE:
[1] Industry standard function.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real, 16-, & 32-bit Prot.
Real
Real
Real, 16-, & 32-bit Prot.
Real
Real
Real
Real
Real, 16-, & 32-bit Prot.
All 32-bit protected-mode functions are accessed by using the industry-standard BIOS32 Service
Directory. Using the service directory involves three steps:
1.
Locating the service directory.
2.
Using the service directory to obtain the entry point for the client management functions.
3.
Calling the client management service to perform the desired function.
The BIOS32 Service Directory is a 16-byte block that begins on a 16-byte boundary between the physical address range of 0E0000h-0FFFFFh. The format is as follows:
Offset No. Bytes
00h
04h
08h
09h
0Ah
0Bh
4
4
1
1
1
5
Description
Service identifier (four ASCII characters)
Entry point for the BIOS32 Service Directory
Revision level
Length of data structure (no. of 16-byte units)
Checksum (should add up to 00h)
Reserved (all 0s)
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To support Windows NT an additional table to the BIOS32 table has been defined to contain 32bit pointers for the DDC locations. The Windows NT extension table is as follows:
; Extension to BIOS SERVICE directory table (next paragraph) db db
2
“$DDC”
; number of entries in table
; DDC POST buffer sig
The service identifier for client management functions is “$CLM.” Once the service identifier is found and the checksum verified, a FAR call is invoked using the value specified at offset 04h to retrieve the CM services entry point. The following entry conditions are used for calling the
Desktop Management service directory:
INPUT:
EAX
EBX (31..8)
= Service Identifier [$CLM]
= Reserved
OUTPUT:
EBX (7..0)
CS
= Must be set to 00h
= Code selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
It must have the same base. CS is execute/read.
DS
SS
It must have the same base. DS is read only.
= Stack selector must provide at least 1K of stack space and be 32-bit.
(I/O permissions must be provided so that the BIOS can support as necessary)
= Data selector set to encompass the physical page holding
entry point as well as the immediately following physical page.
EBX
ECX
EDX
00h, requested service is present
80h, requested service is not present
81h, un-implemented function specified in BL
86h and CF=1, function not supported
= Physical address to use as the selector BASE for the service
= Value to use as the selector LIMIT for the service
= Entry point for the service relative to the BASE returned in EBX
The following subsections provide a brief description of key Client Management functions.
Compaq Deskpro Personal Computers 8-13
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Chapter 8 BIOS ROM
8.5.1 SYSTEM ID AND ROM TYPE
Applications can use the INT 15, AX=E800h BIOS function to identify the type of system. This function will return the system ID in the BX register. These systems have the following IDs and
ROM family types:
System
Small Form Factor:
w/815E-based graphics
w/NVIDIA graphics
Slim Desktop/Configurable Minitower
System ID
688h
680h
684h
ROM Family
686P2
686P3
686P2
PnP ID
CPQ0004
CPQ0003
CPQ0005
The ROM family and version numbers can be verified with the Setup utility or the Compaq
Insight Manager or Diagnostics applications.
8.5.2 EDID RETRIEVE
The BIOS function INT 15, AX=E813h is a tri-modal call that retrieves the VESA extended display identification data (EDID). Two subfunctions are provided: AX=E813h BH=00h retrieves the EDID information while AX=E813h BX=01h determines the level of DDC support.
Input:
AX
BH
= E813h
= 00 Get EDID .
BH = 01 Get DDC support level
If BH = 00 then
DS:(E)SI = Pointer to a buffer (128 bytes) where ROM will return block
If 32-bit protected mode then
DS:(E)SI = Pointer to $DDC location
Output:
(Successful)
If BH
CX
= 0:
DS:SI=Buffer with EDID file.
= Number of bytes written
AH
If BH
BH
BL
(Failure)
=00h Completion of command
= 1:
= System DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
= Monitor DDC support
<0>=1 DDC1 support
<1>=1 DDC2 support
<2>=1 Screen blanked during transfer
AH = 86h or 87h
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8.5.3 TEMPERATURE STATUS
The BIOS includes a function (INT15, AX=E816h) to retrieve the status of a system’s interior temperature. This function allows an application to check whether the temperature situation is at a
Normal, Caution, or Critical condition.
8.5.4 DRIVE FAULT PREDICTION
The Compaq BIOS directly supports Drive Fault Prediction for IDE-type hard drives. This feature is provided through two Client Management BIOS calls. Function INT 15, AX=E817h is used to retrieve a 512-byte block of drive attribute data while the INT 15, AX=E81Bh is used to retrieve the drive’s warranty threshold data. If data is returned indicating possible failure then the following message is displayed:
“ 1720-SMART Hard Drive detects imminent failure ”
8.6
PNP SUPPORT
The BIOS includes Plug ’n Play (PnP) support for PnP version 1.0A. Table 8-5 lists the PnP functions supported.
Table 8-5. PnP BIOS Functions
Table 8-5.
PnP BIOS Functions
Function Register
00h
01h
02h
Get number of system device nodes
Get system device node
Set system device node
50h
51h
Get SMBIOS Structure Information
Get Specific SMBIOS Structure
The BIOS call INT 15, AX=E841h, BH=01h can be used by an application to retrieve the default settings of PnP devices for the user. The application should use the following steps for the display function:
1.
Call PnP function 01(get System Device Node) for each devnode with bit 1 of the control flag set (get static configuration) and save the results.
2.
Call INT 15, AX=E841h, BH=01h.
3.
Call PnP “Get Static Configuration” for each devnode and display the defaults.
4.
If the user chooses to save the configuration, no further action is required. The system board devices will be configured at the next boot. If the user wants to abandon the changes, then the application must call PnP function 02 (Set System Device Node) for each devnode (with bit 1 of the control flag set for static configuration) with the results from the calls made prior to invoking this function.
Compaq Deskpro Personal Computers 8-15
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Chapter 8 BIOS ROM
8.6.1 SMBIOS
In support of the DMI specification the PnP functions 50h and 51h are used to retrieve the
SMBIOS data. Function 50h retrieves the number of structures, size of the largest structure, and
SMBIOS version. Function 51h retrieves a specific structure. This system supports SMBIOS version 2.3.1 and the following structure types:
Type Data
0 BIOS Information
1
3
System Information
System Enclosure or Chassis
8
9
4
7
Processor Information
Cache Information
Port Connector Information
System Slots
13
15
16
17
19
BIOS Language Information
System Event Log Information
Physical Memory Array
Memory Devices
Memory Array Mapped Addresses
20
31
Memory Device Mapped Addresses
Boot Integrity Service Entry Point
32 System Boot Information
128 OEM Defined Structure with Intel Alert-On-LAN (AOL) Information
NOTE: System information on these systems is handled exclusively through the
SMBIOS. The System Information Table (SIT) method (and it’s associated BIOS functions) used on previous systems is no longer supported.
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Technical Reference Guide
8.7
POWER MANAGEMENT FUNCTIONS
The BIOS ROM provides three types of power management support: independent PM support;
APM support, and ACPI support.
8.7.1 INDEPENDENT PM SUPPORT
The BIOS can provide power management (PM) of the system independently from an operating system that doesn’t support APM (including DOS, Unix, NT & older versions of OS/2). In the
Independent PM environment the BIOS and hardware timers determine when to switch the system to a different power state. State switching is not reported to the OS.
8.7.1.1 Staying Awake In Independent PM
There are two "Time-out to Standy" timers used in independent PM: the System Timer and the IDE Hard Drive Timer.
System Timer
In POST, the BIOS enables a timer in the ICH that generates an SMI once per minute. When the
BIOS detects the SMI it checks status bits in the ICH for device activity. If any of the device activity status bits are set at the time of the 1-minute SMI, BIOS resets the time-out minute countdown. The system timer can be configured through the Setup utility for counting down 0, 5,
10, 15, 20, 30, 40, 50, 60, 120, 180, or 240 minutes. The following devices are checked for activity:
♦
Keyboard
♦
Mouse
♦
Serial port(s)
♦
Parallel port
♦
IDE primary controller
NOTE: The secondary controller is NOT included. This is done to support autosense of a CD-ROM insertion (auto-run) in case Windows or NT is running.
Note also that SCSI drive management is the responsibility of the SCSI driver.
Any IDE hard drive access resets the hard drive timer.
IDE Hard Drive Timer
During POST, an inactivity timer each IDE hard drive is set to control hard drive spin down.
Although this activity is independent of the system timer, the system will not go to sleep until the primary IDE controller has been inactive for the system time-out time. The hard drive timer can be configured through the Setup utility for being disabled or counting down 10, 15, 20, 30, 60,
120, 180, or 240 minutes, after which time the hard drive will spin down.
Compaq Deskpro Personal Computers 8-17
Third Edition - April 2001
Chapter 8 BIOS ROM
8.7.1.2 Going to Sleep in Independent PM
When a time-out timer expires, Standby for that timer occurs.
System Standby
When the system acquires the Standby mode the BIOS performs two duties:
1.
Blanks the screen.
2.
Turns off Vsync (to reduce CRT heater voltage).
Since the hard drive inactivity timer is in the drive and triggered by drive access, the system can be in Standby with the hard drives still spinning (awake).
NOTE: The BIOS does not turn the fan(s) off (as on previous products).
IDE Hard Drive Standby
During hard drive standby the platters stop spinning. Depending on drive type, some hard drives will also cut power to some of the drive electronics that are not needed. The drives can be in this state with the system still awake.
8.7.1.3 Suspend
Suspend is not supported in the Independent PM mode.
8.7.1.4 System OFF
When the system is turned Off but still plugged into a live AC outlet the NIC, ICH2, and I/O components continue to receive auxiliary power in order to power-up as the result of a Magic
Packet™ being received over a network. Some NICs are able to wake up a system from Standby in PM, most require their Windows/NT driver to reset them after one wake-up.
8.7.1.5 Waking Up in Independent PM
Activity of either of the following devices will cause the system to wake up with the screen restored:
♦
Keyboard
♦
Mouse (if driver installed)
The hard drive will not spin up until it is accessed. Any hard drive access will cause it to wake up and resume spinning. Since the BIOS returns to the currently running software, it is possible for the drive to spin up while the system is in Standby with the screen blanked.
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Technical Reference Guide
8.7.2 ACPI SUPPORT
This system meets the hardware and firmware requirements for being ACPI compliant.
This system supports the following ACPI functions:
♦
PM timer
♦
Power button
♦
Power button override
♦
RTC alarm
♦
Sleep/Wake logic (S1,S3, S4 (Windows 2000), S5)
♦
C1 state (Halt)
♦
PCI Power Management Event (PME)
8.7.3 APM 1.2 SUPPORT
Advanced Power Management (APM) is an extension of power management. In APM, the O/S decides when a transition to another power state should occur. If going to Standby or Suspend, it notifies all APM-aware drivers requesting approval for the state change. If all drivers approve (the
BIOS is not involved in this process) each is instructed to go to that state, then the BIOS is told to go to that state. All versions of Windows, later versions of OS/2 and Linux support APM. . The
BIOS ROM for these systems support APM 1.2
The APM functions are initialized when the O/S loads. An INT 15h call is made to see if APM is supported by the BIOS, and at what level (1.0, 1.1 or 1.2). After that, the O/S gets a 32-bit address from the BIOS ROM so it can subsequently make 32 bit protected mode calls to access the different APM functions in the ROM.
Table 8-6 lists all the APM calls that the O/S can make to the BIOS. These functions are the major difference between PM and APM.
Compaq Deskpro Personal Computers 8-19
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Chapter 8 BIOS ROM
Table 8-6. APM BIOS Functions
APM BIOS Function
APM Installation Check
APM Real Mode Interface
Connect
APM Protected Mode 16-bit
APM Protected Mode 32-bit
APM Interface Disconnect
CPU Idle
CPU Busy
Set Power State
Enable/Disable Power
Management
Restore Power-On Defaults
Get Power Status
Get PM Event
Get Power State
Enable/Disable Device PM
APM Driver Version
Engage/Disengage PM
Get Capabilities
Get/Set/Disable Resume
Timer
Enable/Disable Resume on
Ring
Enable/Disable Timer Based
Request
Table 8-6.
APM BIOS Functions
Description
Allows the O/S to determine if the system's BIOS supports the APM functionality and if so, which version of the specification it supports. The APM version number returned from this call is the highest level of APM supported by the BIOS.
Establishes the cooperative interface between the O/S and the
BIOS. The BIOS provides OEM-defined power management functionality before the interface is established. Once the interface is established, the BIOS and the O/S Driver coordinate power management activities. The BIOS rejects an interface connect request if any real or protected mode connection already exists.
Initializes the 16-bit protected mode interface between the O/S and the BIOS. This interface allows a protected mode caller to invoke the BIOS functions without first switching into real or virtual-86 mode. This function must be invoked in real mode. This is not currently used by any O/S.
Iinitializes the 32-bit protected mode interface between the O/S and the BIOS. This interface allows a protected mode O/S to invoke the
BIOS functions without the need to first switch into real or virtual-86 mode. This function must be invoked in real mode.
Breaks the cooperative connection between the BIOS and the O/S, and returns control of the power management policy to the BIOS.
Power management parameter values (timer values, enable/disable settings, etc.) in effect at the time of the disconnect remain in effect.
The O/S uses this call to tell BIOS that the system is idle.
Informs the BIOS that the O/S has determined that the system is now busy. The BIOS should restore the CPU clock rate to full speed.
Sets the system or device specified in the power device ID into the requested power state.
Enables or disables all APM BIOS automatic power management.
When disabled, the BIOS does not automatically power manage devices, enter the Standby State, enter the Suspend State, or take power saving steps in response to CPU Idle calls.
Re-initializes all power-on defaults.
This call returns the system current power status.
Returns the next pending PM event, or indicates if no PM events are pending.
Returns the device power state when a specific device ID is used.
Enables or disables APM BIOS automatic power management for a specified device. When disabled, the APM BIOS does not automatically power manage the device.
The O/S uses this call to indicate its level of APM support to the
BIOS. The BIOS returns the APM connection version number.
Engages or disengages cooperative power management of the system or device.
Returns the features which this particular APM 1.2 BIOS implementation supports.
This call gets, sets, or disables the system resume timer.
Enables or disables the system's resume on ring indicator functionality. It also returns the enabled/disabled status.
Enables or disables the BIOS's generation of global Standby and global Suspend requests based on inactivity timers.
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Technical Reference Guide
8.7.3.1 Staying Awake in APM
There are two "Time-out to Standby" timers used in APM: the System Timer and the IDE had Drive Timer.
System Timer
In POST, the ROM enables a timer in the ICH2 that generates an SMI once per minute.
When the ROM gets the SMI it checks status bits in the ICH2 for activity at any of the following devices:
♦
Keyboard
♦
Mouse
♦
Serial port(s)
♦
Parallel port
♦
IDE primary controller
NOTE: The secondary controller is NOT included in order to support autosense of a CD-ROM insertion (auto-run) in case Windows or NT is running.
Note also that management of SCSI drives is the responsibility of the SCSI driver. Any IDE hard drive access resets the hard drive timer.
If any of the activity status bits are set when the ROM gets the 1-minute SMI, it resets its time-out minute countdown according to the value (0 (default), 5, 10, 15, 20, 30, 40, 50,
60, 120, 180, or 240 minutes) selected in the Setup utility (F10).
IDE Hard Drive Timer
During POST, an inactivity timer in the IDE hard drive controller is set to control hard drive spin down. This activity is independent of the system timer. The BIOS will not inform the O/S that it is time to go to sleep until there has been no IDE primary activity for the system time-out time. The IDE hard drive will spin down when its timer expires according to the countdown time (0 (disabled), 10, 15, 20, 30, 60, 120, 180, or 240 minutes) selected in the Setup utility (F10).
NOTE: The O/S (Win98 and later) can use the "Enable/Disable Timer Based Request"
APM BIOS call to disable the system timer the BIOS uses so that the O/S can have direct control of the timing.
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Chapter 8 BIOS ROM
8.7.3.2 Going to Sleep in APM
There are three levels of system sleep in APM: System/Hard Drive Standby, System
Suspend, and System Off.
System/Hard Drive Standby
System Standby is achieved only by a system timer time-out, at such time the following occurs:
1.
All APM-aware device drivers put their respective devices into “Device Standby.”
2.
The O/S makes a BIOS call to go into System Standby.
NOTE: The BIOS ROM of these systems will not turn the fan(s) off as on previous systems).
If the hard drive timer times out due to inactivity the hard drive motor stops spinning the platters. Depending on drive type, some drives can cut power to some of the drive electronics that are not needed during standby. The drive(s) can be in this state with the system still awake. Since the hard drive timer is in the hard drive controller and triggered by drive access, the system can be in Standby with the hard drive(s) still spinning
(awake).
System Suspend
System Suspend is invoked by pressing and releasing the power switch in under four seconds (pressing and holding the switch longer that four seconds will turn the system off).. The system does not time-out from Standby into Suspend.
Upon invoking Suspend, the following actions occur:
1.
All APM-aware device drivers put their associated devices into “Device Standby.”
2.
The O/S makes a BIOS call to go into Standby, and the BIOS: a.
Spins down the IDE drives b.
Halts the processor. The processor remains halted until the next 55ms tick from the RTC.
c.
At the 55ms tick of the RTC the processor executes a BIOS routine to check to see if anything has happened to wake the system up. If not, the processor is halted again.
d.
Steps B and C are repeated until a wake-up event occurs.
NOTE: These systems will not turn the fan(s) off as in previous systems.
8-22 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
System OFF
There are two ways to turn the system off:
1.
Press and hold the power button for longer than 4 seconds (not recommended unless absolutely necessary).
2.
Software shut-down as directed by the O/S. This, being the normal procedure, allows a NIC driver to re-arm the NIC for a Magic Packet™.
8.7.3.3 Waking Up in APM
Any of the following activities will cause the system to wake up:
♦
Keyboard
♦
Mouse
♦
Ring Indicate
♦
RTC alarm
♦
Magic Packet
The hard drive will not spin up until it is accessed. Any hard drive access will cause it to wake up and resume spinning. Since the BIOS returns to the currently running software, it is possible for the drive to spin up while the system is in Standby with the screen blanked.
8.8
USB LEGACY SUPPORT
The BIOS ROM checks the USB port, during POST, for the presence of a USB keyboard. This allows a system with only a USB keyboard to be used during ROM-based setup and also on a system with an OS that does not include a USB driver.
On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data from the device and convert it to PS/2 data. The data will be passed to the keyboard controller and processed as in the PS/2 interface. Changing the delay and/or typematic rate of a USB keyboard though BIOS function INT 16 is not supported.
Compaq Deskpro Personal Computers 8-23
Third Edition - April 2001
Chapter 8 BIOS ROM
This page is intentionally blank.
8-24 Compaq Deskpro Personal Computers
Third Edition - April 2001
Technical Reference Guide
Appendix A
ERROR MESSAGES AND CODES
A.
Appendix A ERROR MESSAGES AND CODES
A.1
INTRODUCTION
This appendix lists the error codes and a brief description of the probable cause of the error.
NOTE: Errors listed in this appendix are applicable only for systems running Compaq
BIOS.
NOTE: Not all errors listed in this appendix may be applicable to a particular system model and/or configuration.
A.2
BEEP/KEYBOARD LED CODES
Table A–1. Beep/Keyboard LED Codes
Beeps
1 short, 2 long
1 long, 2 short
2 long, 1 short
1 long, 3 short
None
None
None
None
None
NOTE:
[1] PS/2 keyboard only.
Table A-1.
Beep/Keyboard LED Codes
Probable Cause LED [1]
NUM lock blinking
CAP lock blinking
Scroll lock blinking
(None)
All three blink in sequence
NUM lock steady on
CAP lock steady on
All three blink together
All three steady on
Base memory failure.
Video/graphics controller failure.
System failure (prior to video initialization).
Boot block executing
Keyboard locked in network mode.
ROMPAQ diskette not present, bad, or drive not ready.
Password prompt.
ROM flash failed.
Successful ROM flash.
Changed – November 2000
Compaq Personal Computers A-1
Appendix A Error Messages and Codes
A.3
POWER-ON SELF TEST (POST) MESSAGES
Table A–2. Power-On Self Test (POST) Messages
Table A-2.
Power-On Self Test (POST) Messages
Error Message
Invalid Electronic Serial Number
Network Server Mode Active (w/o kybd)
101-Option ROM Checksum Error
102-system Board Failure
150-Safe POST Active
162-System Options Not Set
163-Time & Date Not Set
164-Memory Size Error
201-Memory Error
213-Incompatible Memory Module
216-Memory Size Exceeds Max
301-Keyboard Error
303-Keyboard Controller Error
304-Keyboard/System Unit Error
404-Parallel Port Address Conflict
510-Slpash Image Corrupt
601-Diskette Controller Error
912-Computer Cover Removed
Since Last System Start Up
917-Expansion Riser Not Detected
1720-SMART Hard Drive Detects
Imminent Failure
1721-SMART SCSI Hard Drive
Detects Imminent Failure
1801-Microcode Patch Error
1998-Master Boot Record Backup
Has Been Lost
1999-Master Boot Record Has
Changed. Press Any Key To Enter
Setup to Restore the MBR.
2000-Master boot Record hard drive has changed
Probable Cause
Chassis serial number is corrupt. Use Setup to enter a valid number.
System is in network mode.
A device’s option ROM has failed/is bad.
Failed ESCD write, A20, timer, or DMA controller.
An option ROM failed to execute on a previous boot.
Invalid checksum, RTC lost power, or invalid configuration.
Date and time information in CMOS is not valid.
Memory has been added or removed.
Memory test failed.
BIOS detected installed DIMM(s) as being not compatible.
Installed memory exceeds the maximum supported by the system.
Keyboard interface test failed (improper connection or stuck key).
Keyboard buffer failed empty (8042 failure or stuck key).
Keyboard controller failed self-test.
Current parallel port address is conflicting with another device.
Corrupted splash screen image. Restore default image w/ROMPAQ.
Diskette drive removed since previous boot.
Cover (hood) removal has been detected by the Smart Cover
Sensor.
Expansion (backplane) board not seated properly.
SMART circuitry on an IDE drive has detected possible equipment failure.
SMART circuitry on a SCSI drive has detected possible equipment failure.
A processor is installed for which the BIOS ROM has no patch.
Check for ROM update.
Backup copy of the hard drive master boot record is corrupted. Use
Setup to restore the backup from the hard drive.
If Master Boot Record Security is enabled, this message indicates that the MBR has changed since the backup was made.
The hard drive has been changed. Use Setup to create a backup of the new hard drive.
A-2 Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
A.4
SYSTEM ERROR MESSAGES (1xx-xx)
Table A–3. System Error Messages
Table A-3.
System Error Messages
Message Probable Cause
101
102
103
104-01
104-02
104-03
105-01
105-02
105-03
105-04
105-05
105-06
105-07
105-08
105-09
105-10
105-11
105-12
105-13
105-14
Option ROM error
System board failure (see note)
System board failure
Master int. cntlr. test fialed
Slave int. cntlr. test failed
Int. cntlr. SW RTC inoperative
Port 61 bit <6> not at zero
Port 61 bit <5> not at zero
Port 61 bit <3> not at zero
Port 61 bit <1> not at zero
Port 61 bit <0> not at zero
Port 61 bit <5> not at one
Port 61 bit <3> not at one
Port 61 bit <1> not at one
Port 61 bit <0> not at one
Port 61 I/O test failed
Port 61 bit <7> not at zero
Port 61 bit <2> not at zero
No int. generated by failsafe timer
NMI not triggered by failsafe timer
106-01
107-01
108-02
Keyboard controller test failed
CMOS RAM test failed
CMOS interrupt test failed
Message Probable Cause
110-01
110-02
110-03
111-01
112-01
112-02
112-03
112-04
112-05
112-06
112-07
112-08
112-09
112-10
112-11
112-12
113-01
114-01
116-xx
162-xx
163-xx
164-xx
199-00
Programmable timer load data test failed
Programmable timer dynamic test failed
Program timer 2 load data test failed
Refresh detect test failed
Speed test Slow mode out of range
Speed test Mixed mode out of range
Speed test Fast mode out of range
Speed test unable to enter Slow mode
Speed test unable to enter Mixed mode
Speed test unable to enter Fast mode
Speed test system error
Unable to enter Auto mode in speed test
Unable to enter High mode in speed test
Speed test High mode out of range
Speed test Auto mode out of range
Speed test variable speed mode inop.
Protected mode test failed
Speaker test failed
Way 0 read/write test failed
Sys. options failed (mismatch in drive type)
Time and date not set
Memory size
Installed devices test failed
108-03
109-01
109-02
109-03
CMOS not properly initialized (int.test)
CMOS clock load data test failed
CMOS clock rollover test failed
CMOS not properly initialized (clk test)
NOTE: A 102 message code may be caused by one of a variety of processor-related problems that may be solved by replacing the processor, although system board replacement may be needed.
Changed – November 2000
Compaq Personal Computers A-3
Appendix A Error Messages and Codes
A.5
MEMORY ERROR MESSAGES (2xx-xx)
Table A–4. Memory Error Messages
Table A-4.
Memory Error Messages
200-04
200-05
200-06
200-07
200-08
201-01
202-01
202-02
202-03
203-01
203-02
203-03
204-01
204-02
204-03
204-04
204-05
205-01
205-02
205-03
206-xx
210-01
210-02
210-03
211-01
211-02
211-03
213-xx
214-xx
215-xx
Real memory size changed
Extended memory size changed
Invalid memory configuration
Extended memory size changed
CLIM memory size changed
Memory machine ID test failed
Memory system ROM checksum failed
Failed RAM/ROM map test
Failed RAM/ROM protect test
Memory read/write test failed
Error while saving block in read/write test
Error while restoring block in read/write test
Memory address test failed
Error while saving block in address test
Error while restoring block in address test
A20 address test failed
Page hit address test failed
Walking I/O test failed
Error while saving block in walking I/O test
Error while restoring block in walking I/O test
Increment pattern test failed
Memory increment pattern test
Error while saving memory during increment pattern test
Error while restoring memory during increment pattern test
Memory random pattern test
Error while saving memory during random memory pattern test
Error while restoring memory during random memory pattern test
Incompatible DIMM in slot x
Noise test failed
Random address test
A.6
KEYBOARD ERROR MESSAGES (30x-xx)
A-4
Table A–5. Keyboard Error Messages
Table A-5.
Keyboard Error Messages
Message Probable Cause
300-xx
301-01
301-02
301-03
301-04
301-05
302-xx
302-01
303-01
303-02
303-03
303-04
Failed ID test
Kybd short test, 8042 self-test failed
Kybd short test, interface test failed
Kybd short test, echo test failed
Kybd short test, kybd reset failed
Kybd short test, kybd reset failed
Failed individual key test
Kybd long test failed
Message
303-05
303-06
303-07
303-08
303-09
304-01
304-02
304-03
LED test, 8042 self-test failed
LED test, reset test failed
LED test, reset failed
304-04
304-05
304-06
LED test, LED command test failed --
Probable Cause
LED test, LED command test failed
LED test, LED command test failed
LED test, LED command test failed
LED test, command byte restore test failed
LED test, LEDs failed to light
Keyboard repeat key test failed
Unable to enter mode 3
Incorrect scan code from keyboard
No Make code observed
Cannot /disable repeat key feature
Unable to return to Normal mode
--
Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
A.7
PRINTER ERROR MESSAGES (4xx-xx)
Table A–6. Printer Error Messages
Table A-6.
Printer Error Messages
Message
401-01
402-01
402-02
402-03
402-04
402-05
402-06
402-07
402-08
402-09
402-10
Probable Cause
Printer failed or not connected
Printer data register failed
Printer control register failed
Data and control registers failed
Loopback test failed
Message Probable Cause
402-11
402-12
402-13
402-14
402-15
Loopback test and data reg. failed 402-16
Loopback test and cntrl. reg. failed 402-01
Loopback tst, data/cntrl. reg. failed 403-xx
Interrupt test failed
Interrupt test and data reg. failed
Interrupt test and control reg. failed
404-xx
498-00
--
Interrupt test, data/cntrl. reg. failed
Interrupt test and loopback test failed
Int. test, LpBk. test., and data register failed
Int. test, LpBk. test., and cntrl. register failed
Int. test, LpBk. test., and data/cntrl. reg. failed
Unexpected interrupt received
Printer pattern test failed
Printer pattern test failed
Parallel port address conflict
Printer failed or not connected
--
A.8
VIDEO (GRAPHICS) ERROR MESSAGES (5xx-xx)
Table A–7. Video (Graphics) Error Messages
Table A-7.
Video (Graphics) Error Messages
Message Probable Cause
501-01
502-01
503-01
504-01
505-01
506-01
507-01
Video controller test failed
Video memory test failed
Video attribute test failed
Video character set test failed
80x25 mode, 9x14 cell test failed
80x25 mode, 8x8 cell test failed
40x25 mode test failed
See Table A-14 for additional graphics messages.
Message
508-01
509-01
510-01
511-01
512-01
514-01
516-01
Probable Cause
320x200 mode, color set 0 test failed
320x200 mode, color set 1 test failed
640x200 mode test failed
Screen memory page test failed
Gray scale test failed
White screen test failed
Noise pattern test failed
Changed – November 2000
Compaq Personal Computers A-5
Appendix A Error Messages and Codes
A.9
DISKETTE DRIVE ERROR MESSAGES (6xx-xx)
Table A–8. Diskette Drive Error Messages
Table A-8.
Diskette Drive Error Messages
Message Probable Cause Message Probable Cause
6xx-01
6xx-02
6xx-03
6xx-04
6xx-05
6xx-06
6xx-07
6xx-08
6xx-09
6xx-10
Exceeded maximum soft error limit
Exceeded maximum hard error limit
Previously exceeded max soft limit
Previously exceeded max hard limit
Failed to reset controller
Fatal error while reading
Fatal error while writing
Failed compare of R/W buffers
Failed to format a tract
Failed sector wrap test
600-xx = Diskette drive ID test
601-xx = Diskette drive format
602-xx = Diskette read test
603-xx = Diskette drive R/W compare test
604-xx = Diskette drive random seek test
605-xx = Diskette drive ID media
606-xx = Diskette drive speed test
607-xx = Diskette drive wrap test
608-xx = Diskette drive write-protect test
6xx-20
6xx-21
6xx-22
6xx-23
6xx-24
6xx-25
6xx-26
6xx-27
6xx-28
--
Failed to get drive type
Failed to get change line status
Failed to clear change line status
Failed to set drive type in ID media
Failed to read diskette media
Failed to verify diskette media
Failed to read media in speed test
Failed speed limits
Failed write-protect test
--
609-xx = Diskette drive reset controller test
610-xx = Diskette drive change line test
611-xx = Pri. diskette drive port addr. conflict
612-xx = Sec. diskette drive port addr. conflict
694-00 = Pin 34 not cut on 360-KB drive
697-00 = Diskette type error
698-00 = Drive speed not within limits
699-00 = Drive/media ID error (run Setup)
A.10 SERIAL INTERFACE ERROR MESSAGES (11xx-xx)
Table A–9. Serial Interface Error Messages
Table A-9.
Serial Interface Error Messages
Message Probable Cause
1101-01 UART DLAB bit failure
1101-02 Line input or UART fault
1101-03 Address line fault
1101-04 Data line fault
1101-05 UART cntrl. signal failure
1101-06 UART THRE bit failure
1101-07 UART Data RDY bit failure
1101-08 UART TX/RX buffer failure
1101-09 Interrupt circuit failure
1101-10 COM1 set to invalid INT
1101-11 COM2 set to invalid INT
1101-12 DRVR/RCVR cntrl. signal failure
Message Probable Cause
1101-13
1101-14
1109-01
1109-02
1109-03
1109-04
1109-05
1109-06
1150-xx
1151-xx
1152-xx
1155-xx
UART cntrl. signal interrupt failure
DRVR/RCVR data failure
Clock register initialization failure
Clock register rollover failure
Clock reset failure
Input line or clock failure
Address line fault
Data line fault
Comm port setup error (run Setup)
COM1 address conflict
COM2 address conflict
COM port address conflict
A-6 Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
A.11 MODEM COMMUNICATIONS ERROR MESSAGES (12xx-xx)
Table A–10. Serial Interface Error Messages
Table A-10.
Serial Interface Error Messages
Message Probable Cause Message Probable Cause
1201-XX Modem internal loopback test
1201-01 UART DLAB bit failure
1201-02 Line input or UART failure
1201-03 Address line failure
1201-04 Data line fault
1204-03
1204-04
1204-05
1204-06
1204-07
Data block retry limit reached [4]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
1201-05 UART control signal failure
1201-06 UART THRE bit failure
1201-07 UART DATA READY bit failure
1201-08 UART TX/RX buffer failure
1204-08
1204-09
1204-10
1204-11
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
1205-XX Modem auto answer test 1201-09 Interrupt circuit failure
1201-10
1201-11
COM1 set to invalid inturrupt
COM2 set to invalid
1205-01
1205-02
1201-12 DRVR/RCVR control signal failure 1205-03
1201-13 UART control signal interrupt failure
1205-04
Time-out waiting for SYNC [5]
Time-out waiting for response [5]
Data block retry limit reached [5]
RX exceeded carrier lost limit
1201-14
1202-01
1202-02
DRVR/RCVR data failure
1201-15 Modem detection failure
1201-16 Modem ROM, checksum failure
1201-17 Tone detect failure
1202-XX Modem internal test
Time-out waiting for SYNC [1]
Time-out waiting for response [1]
1205-05
1205-06
1205-07
1205-08
1205-09
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
Modem exceeded maximum redial limit
1205-10 Line quality prevented remote response
1205-11 Modem time-out waiting for remote connection
1206-XX Dial multi-frequency tone test 1202-03 Data block retry limit reached [1]
1202-11
1202-12
1202-13
1202-21
1202-22
Time-out waiting for SYNC [2]
Time-out waiting for response [2]
Data block retry limit reached [2]
Time-out waiting for SYNC [3]
Time-out waiting for response [3]
1202-23 Data block retry limit reached [3]
1203-XX Modem external termination test
1206-17 Tone detection failure
1210-XX Modem direct connect test
1210-01
1210-02
1210-03
1210-04
1210-05
1203-01 Modem external TIP/RING failure 1210-06
1203-02 Modem external data TIP/RING fail 1210-07
1203-03 Modem line termination failure 1210-08
Time-out waiting for SYNC [6]
Time-out waiting for response [6]
Data block retry limit reached [6]
RX exceeded carrier lost limit
TX exceeded carrier lost limit
Time-out waiting for dial tone
Dial number string too long
Modem time-out waiting for remote response
1204-XX Modem auto originate test
1204-01 Time-out waiting for SYNC [4]
1204-02 Time-out waiting for response [4]
1210-09
1210-10
1210-11
Modem exceeded maximum redial limit
Line quality prevented remote response
Modem time-out waiting for remote connection
NOTES:
[1] Local loopback mode
[2] Analog loopback originate mode
[3] Analog loopback answer mode
[4] Modem auto originate test
[5] Modem auto answer test
[6] Modem direct connect test
Changed – November 2000
Compaq Personal Computers A-7
Appendix A Error Messages and Codes
A.12 SYSTEM STATUS ERROR MESSAGES (16xx-xx)
Table A–11. System Status Error Messages
Table A-11.
System Status Error Messages
A.13 HARD DRIVE ERROR MESSAGES (17xx-xx)
Table A–12. Hard Drive Error Messages
Table A-12.
Hard Drive Error Messages
Message Probable Cause
1700-xx = Hard drive ID test
1701-xx = Hard drive format test
1702-xx = Hard drive read test
1703-xx = Hard drive read/write compare test
1704-xx = Hard drive random seek test
1705-xx = Hard drive controller test
1706-xx = Hard drive ready test
1707-xx = Hard drive recalibrate test
1708-xx = Hard drive format bad track test
1709-xx = Hard drive reset controller test
1710-xx = Hard drive park head test
1714-xx = Hard drive file write test
1715-xx = Hard drive head select test
1716-xx = Hard drive conditional format test
1717-xx = Hard drive ECC test
Message Probable Cause
17xx-01 Exceeded max. soft error limit
17xx-02 Exceeded max. Hard error limit
17xx-51
17xx-52
17xx-03 Previously exceeded max. soft error limit 17xx-53
17xx-04 Previously exceeded max.hard error limit 17xx-54
17xx-05 Failed to reset controller
17xx-06 Fatal error while reading
17xx-07 Fatal error while writing
17xx-08 Failed compare of R/W buffers
17xx-09 Failed to format a track
17xx-10 Failed diskette sector wrap during read
17xx-19 Cntlr. failed to deallocate bad sectors
17xx-55
17xx-56
17xx-57
17xx-58
17xx-59
17xx-60
17xx-62
17xx-40 Cylinder 0 error
17xx-41 Drive not ready
17xx-42 Failed to recalibrate drive
17xx-63
17xx-65
17xx-66
17xx-43 Failed to format a bad track
17xx-44 Failed controller diagnostics
17xx-67
17xx-68
17xx-45 Failed to get drive parameters from ROM 17xx-69
17xx-46 Invalid drive parameters from ROM 17xx-70
17xx-47 Failed to park heads
17xx-48 Failed to move hard drive table to RAM
17xx-49 Failed to read media in file write test
17xx-50 Failed I/O write test
17xx-71
17xx-72
17xx-73
--
Failed I/O read test
Failed file I/O compare test
Failed drive/head register test
Failed digital input register test
Cylinder 1 error
Failed controller RAM diagnostics
Failed controller-to-drive diagnostics
Failed to write sector buffer
Failed to read sector buffer
Failed uncorrectable ECC error
Failed correctable ECC error
Failed soft error rate
Exceeded max. bad sectors per track
Failed to initialize drive parameter
Failed to write long
Failed to read long
Failed to read drive size
Failed translate mode
Failed non-translate mode
Bad track limit exceeded
Previously exceeded bad track limit
--
1719-xx = Hard drive power mode test
1720-xx = SMART drive detects imminent failure
1721-xx = SCSI hard drive imminent failure
1724-xx = Net work preparation test
1736-xx = Drive monitoring test
1771-xx = Pri. IDE controller address conflict
1772-xx = Sec. IDE controller address conflict
1780-xx = Disk 0 failure
1781-xx = Disk 1 failure
1782-xx = Pri. IDE controller failure
1790-xx = Disk 0 failure
1791-xx = Disk 1 failure
1792-xx = Se. controller failure
1793-xx = Sec. Controller or disk failure
1799-xx = Invalid hard drive type
A-8 Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
A.14 HARD DRIVE ERROR MESSAGES (19xx-xx)
Table A–13. Hard Drive Error Messages
Table A-13.
Hard Drive Error Messages
Message Probable Cause
19xx-01 Drive not installed
19xx-02 Cartridge not installed
19xx-03 Tape motion error
19xx-04 Drive busy erro
19xx-05 Track seek error
19xx-06 Tape write-protect error
19xx-07 Tape already Servo Written
19xx-08 Unable to Servo Write
19xx-09 Unable to format
19xx-10 Format mode error
19xx-11 Drive recalibration error
19xx-12 Tape not Servo Written
19xx-13 Tape not formatted
19xx-14 Drive time-out error
19xx-15 Sensor error flag
19xx-16 Block locate (block ID) error
19xx-17 Soft error limit exceeded
19xx-18 Hard error limit exceeded
19xx-19 Write (probably ID ) error
19xx-20 NEC fatal error
Message
19xx-21
19xx-22
19xx-23
19xx-24
19xx-25
19xx-26
19xx-27
19xx-28
19xx-30
19xx-31
19xx-32
19xx-33
19xx-34
19xx-35
19xx-36
19xx-37
19xx-38
19xx-39
19xx-40
19xx-91
Probable Cause
Got servo pulses second time but not first
Never got to EOT after servo check
Change line unset
Write-protect error
Unable to erase cartridge
Cannot identify drive
Drive not compatible with controller
Format gap error
Exception bit not set
Unexpected drive status
Device fault
Illegal command
No data detected
Power-on reset occurred
Failed to set FLEX format mode
Failed to reset FLEX format mode
Data mismatch on directory track
Data mismatch on track 0
Failed self-test
Power lost during test
1900-xx = Tape ID test failed
1901-xx = Tape servo write failed
1902-xx = Tape format failed
1903-xx = Tape drive sensor test failed
1904-xx = Tape BOT/EOT test failed
1905-xx = Tape read test failed
1906-xx = Tape R/W compare test failed
1907-xx = Tape write-protect failed
A.15 VIDEO (GRAPHICS) ERROR MESSAGES (24xx-xx)
Table A–14. Video (Graphics) Error Messages
Table A-14.
Video (Graphics) Error Messages
Message Probable Cause Message Probable Cause
2402-01 Video memory test failed
2403-01 Video attribute test failed
2404-01 Video character set test failed
2405-01 80x25 mode, 9x14 cell test failed
2406-01 80x25 mode, 8x8 cell test failed
2407-01 40x25 mode test failed
2408-01 320x200 mode color set 0 test failed
2409-01 320x200 mode color set 1 test failed
2410-01 640x200 mode test failed
2411-01 Screen memory page test failed
2412-01 Gray scale test failed
2418-02
2419-01
2420-01
2421-01
2422-01
2423-01
2424-01
2425-01
2431-01
EGA shadow RAM test failed
EGA ROM checksum test failed
EGA attribute test failed
640x200 mode test failed
640x350 16-color set test failed
640x350 64-color set test failed
EGA Mono. text mode test failed
EGA Mono. graphics mode test failed
640x480 graphics mode test failed
2432-01 320x200 256-color set test failed
2448-01 Advanced VGA controller test failed
2414-01 White screen test failed
2416-01 Noise pattern test failed
2451-01
2456-01
132-column AVGA test failed
AVGA 256-color test failed
2417-01 Lightpen text test failed, no response
2417-02 Lightpen text test failed, invalid response
2458-xx
2468-xx
AVGA BitBLT test failed
AVGA DAC test failed
2417-03 Lightpen graphics test failed, no resp. 2477-xx AVGA data path test failed
2417-04 Lightpen graphics tst failed, invalid resp. 2478-xx AVGA BitBLT test failed
2418-01 EGA memory test failed 2480-xx AVGA linedraw test failed
Compaq Personal Computers A-9
Changed – November 2000
Appendix A Error Messages and Codes
A.16 AUDIO ERROR MESSAGES (3206-xx)
Table A–15. Audio Error Messages
Table A-15.
Audio Error Message
3206-xx Audio subsystem internal error
A.17 DVD/CD-ROM ERROR MESSAGES (33xx-xx)
Table A–16. DVD/CD-ROM Drive Error Messages
Table A-16.
DVD/CD-ROM Drive Error Messages
3301-xx
3305-XX
Drive test failed
Seek test failed
See Table A-18 for additional messages.
A.18 NETWORK INTERFACE ERROR MESSAGES (60xx-xx)
Table A–17. Network Interface Error Messages
Table A-17.
Network Interface Error Messages
Message Probable Cause Message Probable Cause
6000-xx Pointing device interface error
6014-xx Ethernet configuration test failed
6016-xx Ethernet reset test failed
6028-xx Ethernet int. loopback test failed
6029-xx Ethernet ext. loopback test failed
6054-xx
6056-xx
6068-xx
6069-xx
6089-xx
Token ring configuration test failed
Token ring reset test failed
Token ring int. loopback test failed
Token ring ext. loopback test failed
Token ring open
A-10 Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
A.19 SCSI INTERFACE ERROR MESSAGES (65xx-xx, 66xx-xx, 67xx-xx)
Table A–18. SCSI Interface Error Messages
Table A-18.
SCSI Interface Error Messages
Message Probable Cause Message Probable Cause
6nyy-02 Drive not installed
6nyy-03 Media not installed
6nyy-05 Seek failure
6nyy-06 Drive timed out
6nyy-07 Drive busy
6nyy-08 Drive already reserved
6nyy-09 Reserved
6nyy-10 Reserved
6nyy-11 Media soft error
6nyy-12 Drive not ready
6nyy-13 Media error
6nyy-14 Drive hardware error
6nyy-15 Illegal drive command
6nyy-16 Media was changed
6nyy-17 Tape write-protected
6nyy-18 No data detected
6nyy-21 Drive command aborted
6nyy-24 Media hard error
6nyy-25 Reserved
6nyy-30 Controller timed out
6nyy-31 Unrecoverable error
6nyy-32 Controller/drive not connected n = 5, Hard drive
= 6, CD-ROM drive
= 7, Tape drive.
6nyy-33
6nyy-34
6nyy-35
6nyy-36
6nyy-39
6nyy-40
6nyy-41
6nyy-43
6nyy-44
6nyy-50
6nyy-51
6nyy-52
6nyy-53
6nyy-54
6nyy-60
6nyy-61
6nyy-65
6nyy-91
6nyy-92
6nyy-99 yy = 00, ID
= 03, Power check
= 05, Read
= 06, SA/Media
= 08, Controller
= 23, Random read
= 28, Media load/unload
Illegal controller command
Invalid SCSI bus phase
Invalid SCSI bus phase
Invalid SCSI bus phase
Error status from drive
Drive timed out
SSI bus stayed busy
ACK did not deassert
Parity error
Data pins bad
Data line 7 bad
MSG, C/D, or I/O lines bad
BSY never went busy
BSY stayed busy
Controller CONFIG-1 register fault
Controller CONFIG-2 register fault
Media not unloaded
Over temperature condition
Side panel not installed
Autoloader reported tape not loaded properly
A.20 POINTING DEVICE INTERFACE ERROR MESSAGES (8601-xx)
Table A–19. Pointing Device Interface Error Messages
Table A-19.
Pointing Device Interface Error Messages
Message Probable Cause Message Probable Cause
8601-01 Mouse ID fails
8601-02 Left mouse button is inoperative
8601-03 Left mouse button is stuck closed
8601-07
8601-08
8601-09
8601-04 Right mouse button is inoperative 8601-10
8601-05 Right mouse button is stuck closed 8602-xx
8601-06 Left block not selected --
Right block not selected
Timeout occurred
Mouse loopback test failed
Pointing device is inoperative
I/F test failed
--
Changed – November 2000
Compaq Personal Computers A-11
Appendix A Error Messages and Codes
This page is intentionally blank.
A-12 Compaq Personal Computers
Changed - November 2000
Technical Reference Guide
Appendix B
ASCII CHARACTER SET
B.
Appendix B ASCII CHARACTER SET
B.1
INTRODUCTION
This appendix lists, in Table B-1, the 256-character ASCII code set including the decimal and hexadecimal values. All ASCII symbols may be called while in DOS or using standard text-mode editors by using the combination keystroke of holding the Alt key and using the Numeric Keypad to enter the decimal value of the symbol. The extended ASCII characters (decimals 128-255) can only be called using the Alt + Numeric Keypad keys.
NOTE: Regarding keystrokes, refer to notes at the end of the table. Applications may interpret multiple keystroke accesses differently or ignore them completely.
Figure B–1. ASCII Character Set
Table B-1.
ASCII Character Set
Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol
2 02 34
3 03
♥
35 23 # 67 43 C 99 63 c
4 04
♦
5 05
♣
6 06
♠
7 07
●
8 08
❍
36 24 $ 68 44 D 100
37 25 % 69 45 E 101
38 26 & 70 46 F 102
39 27 ‘ 71 47 G 103
40 28 ( 72 48 H 104 d e f g h
10 0A 42 2A * 74 4A J 106 j
11 0B 43 2B + 75 4B K 107 k
12 0C 44 2C ` 76 4C L 108 l
13 0D 45 2D - 77 4D M 109
14 0E 46 2E . 78 4E N 110
15 0F 47 2F / 79 4F O 111
16 10
4
17 11
3
18 12
↕
48 30 0 80 50 P 112
49 31 1 81 51 Q 113
50 32 2 82 52 R 114 p q r
19 13 !! 51 33 3 83 53 S 115 s
20 14 ¶ 52 34 4 84 54 T 116 t
22 16
0
23 17
↕
24 18
↑
25 19
↓
26 1A
→
27 1B
←
54 36 6 86 56 V 118
55 37 7 87 57 W 119
56 38 8 88 58 X 120
57 39 9 89 59 Y 121
58 3A : 90 5A Z 122
59 3B ; 91 5B [ 123 v w x y z
{
28 1C 60 3C < 92 5C \ 124 |
29 1D
↔
30 1E
▲
31 1F
▼
61 3D = 93 5D ] 125
62 3E > 94 5E ^ 126
63 3F ? 95 5F _ 127 7F
}
~
[1]
Continued
Compaq Personal Computers B-1
Changed - July 2000
Appendix B ASCII Character Set
Table B-1. ASCII Code Set (Continued)
128 80 Ç
129 81 ü
130 82 é
131 83 â
132 84 ä
133 85 à
134 86 å
135 87 ç
136 88 ê
137 89 ë
138 8A è
139 8B ï
140 8C î
141 8D ì
142 8E Ä
143 8F Å
144 90 É
145 91 æ
146 92 Æ
147 93 ô
148 94 ö
149 95 ò
150 96 û
151 97 ù
152 98 ÿ
153 99 Ö
154 9A Ü
155 9B ¢
156 9C £
157 9D ¥
158 9E
₧
159 9F ƒ
NOTES:
[1] Symbol not displayed.
160 A0 á
161 A1 í
162 A2 ó
163 A3 ú
164 A4 ñ
165 A5 Ñ
166 A6 ª
167 A7 º
168 A8 ¿
169 A9
⌐
170 AA ¬
171 AB ½
172 AC ¼
173 AD ¡
174 AE «
175 AF »
176 B0
░
177 B1
▒
178 B2
▓
179 B3
│
180 B4
┤
181 B5
╡
182 B6
╢
183 B7
╖
184 B8
╕
185 B9
╣
186 BA
║
187 BB
╗
188 BC
╝
189 BD
╜
190 BE
╛
191 BF
┐
Dec # Keystroke(s)
1-26 Ctrl A thru Z respectively
192 C0
└
193 C1
┴
194 C2
195 C3
196 C4
197 C5
198 C6
199 C7
200 C8
201 C9
202 CA
203 CB
204 CC
205 CD
206 CE
207 CF
208 D0
209 D1
210 D2
211 D3
212 D4
213 D5
214 D6
215 D7
216 D8
217 D9
218 DA
219 DB
220 DC
221 DD
┬
├
─
┼
╞
╟
╚
╔
╩
╦
╠
═
╬
╧
╨
╤
╥
╙
╘
╒
╓
╫
╪
┘
┌
█
▄
▌
222 DE
▐
223 DF
▀
224 E0
α
225 E1 ß
226 E2
Γ
227 E3
π
228 E4
Σ
229 E5
σ
230 E6 µ
231 E7
232 E8
τ
Φ
233 E9
234 EA
Θ
Ω
235 EB
236 EC
δ
∞
237 ED
238 EE
φ
ε
239 EF
240 F0
∩
≡
241 F1 ±
242 F2
≥
243 F3
≤
244 F4
⌠
245 F5
⌡
246 F6 ÷
247 F7
≈
248 F8 °
249 F9
·
250 FA ·
251 FB
√
252 FC ⁿ
253 FD ²
254 FE
■
255 FF Blank
33-43 Shift and key w/corresponding symbol
48-57 Key w/corresponding symbol, numerical keypad w/Num Lock active
58 Shift and key w/corresponding symbol
60 Shift and key w/corresponding symbol
62-64 Shift and key w/corresponding symbol
65-90 Shift and key w/corresponding symbol or key w/corresponding symbol and
Caps Lock active
94, 95 Shift and key w/corresponding symbol
97-126 Key w/corresponding symbol or Shift and key w/corresponding symbol
and Caps Lock active
128-255 Alt and decimal digit(s) of desired character
B-2 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
Appendix C
KEYBOARD
C.
Appendix C KEYBOARD
C.1
INTRODUCTION
This appendix describes the Compaq keyboard that is included as standard with the system unit.
The keyboard complies with the industry-standard classification of an “enhanced keyboard” and includes a separate cursor control key cluster, twelve “function” keys, and enhanced programmability for additional functions.
This appendix covers the following keyboard types:
♦
Standard enhanced keyboard.
♦
Space-Saver Windows-version keyboard featuring additional keys for specific support of the
Windows operating system.
♦
Easy Access keyboard with additional buttons for internet accessibility functions.
Only one type of keyboard is supplied with each system. Other types may be available as an option.
NOTE: This appendix discusses only the keyboard unit. The keyboard interface is a function of the system unit and is discussed in Chapter 5, Input/Output Interfaces.
Topics covered in this appendix include the following:
♦
Keystroke processing (C.2)
♦
Connectors (C.3) page C-2 page C-16
Changed –- July 2000
Compaq Personal Computers C-1
Appendix C Keyboard
C.2
KEYSTROKE PROCESSING
A functional block diagram of the keystroke processing elements is shown in Figure C-1. Power
(+5 VDC) is obtained from the system through the PS/2-type interface. The keyboard uses a
Z86C14 (or equivalent) microprocessor. The Z86C14 scans the key matrix drivers every 10 ms for pressed keys while at the same time monitoring communications with the keyboard interface of the system unit. When a key is pressed, a Make code is generated. A Break code is generated when the key is released. The Make and Break codes are collectively referred to as scan codes. All keys generate Make and Break codes with the exception of the Pause key, which generates a Make code only.
Num
Lock
Caps
Lock
Scroll
Lock
Keyswitch
Matrix
Matrix
Drivers
Matrix
Receivers
Keyboard
Processor
Data/
CLK
Keyboard
Interface
(System Unit)
Figure C–1. Keystroke Processing Elements, Block Diagram
When the system is turned on, the keyboard processor generates a Power-On Reset (POR) signal after a period of 150 ms to 2 seconds. The keyboard undergoes a Basic Assurance Test (BAT) that checks for shorted keys and basic operation of the keyboard processor. The BAT takes from
300 to 500 ms to complete.
If the keyboard fails the BAT, an error code is sent to the CPU and the keyboard is disabled until an input command is received. After successful completion of the POR and BAT, a completion code (AAh) is sent to the CPU and the scanning process begins.
The keyboard processor includes a 16-byte FIFO buffer for holding scan codes until the system is ready to receive them. Response and typematic codes are not buffered. If the buffer is full (16 bytes held) a 17 th byte of a successive scan code results in an overrun condition and the overrun code replaces the scan code byte and any additional scan code data (and the respective key strokes) are lost. Multi-byte sequences must fit entirely into the buffer before the respective keystroke can be registered.
C-2 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
C.2.1 PS/2-TYPE KEYBOARD TRANSMISSIONS
The PS/2-type keyboard sends two main types of data to the system; commands (or responses to system commands) and keystroke scan codes. Before the keyboard sends data to the system
(specifically, to the 8042-type logic within the system), the keyboard verifies the clock and data lines to the system. If the clock signal is low (0), the keyboard recognizes the inhibited state and loads the data into a buffer. Once the inhibited state is removed, the data is sent to the system.
Keyboard-to-system transfers (in the default mode) consist of 11 bits as shown in Figure C-2.
Tcy
Tcl
Tch
Clock
Data
Start
Bit
Th-b-t
(LSb)
Dat a
Dat a
Dat a
Dat a
Dat a
Dat a
Dat a
(MSb)
Dat a
Parity
Bit
Stop
Bit
Tcy (clock cycle)
Tcl (clock low)
Tch (clock high)
Th-b-t (high-before-transmit)
60 us
30 us
30 us
--
--
41 us
--
20 us
Figure C–2. PS/2 Keyboard-To-System Transmission, Timing Diagram
80 us
50 us
40 us
--
The system can halt keyboard transmission by setting the clock signal low. The keyboard checks the clock line every 60 us to verify the state of the signal. If a low is detected, the keyboard will finish the current transmission if the rising edge of the clock pulse for the parity bit has not occurred. The system uses the same timing relationships during reads (typically with slightly reduced time periods).
The enhanced keyboard has three operating modes:
♦
Mode 1 - PC-XT compatible
♦
Mode 2 - PC-AT compatible (default)
♦
Mode 3 - Select mode (keys are programmable as to make-only, break-only, typematic)
Modes can be selected by the user or set by the system. Mode 2 is the default mode. Each mode produces a different set of scan codes. When a key is pressed, the keyboard processor sends that key’s make code to the 8042 logic of the system unit. The When the key is released, a release code is transmitted as well (except for the Pause key, which produces only a make code). The 8042type logic of the system unit responds to scan code reception by asserting IRQ1, which is processed by the interrupt logic and serviced by the CPU with an interrupt service routine. The service routine takes the appropriate action based on which key was pressed.
Changed –- July 2000
Compaq Personal Computers C-3
Appendix C Keyboard
C.2.2 USB-TYPE KEYBOARD TRANSMISSIONS
The USB-type keyboard sends essentially the same information to the system that the PS/2 keyboard does except that the data receives additional NRZI encoding and formatting (prior to leaving the keyboard) to comply with the USB I/F specification (discussed in chapter 5 of this guide).
Packets received at the system’s USB I/F and decoded as originating from the keyboard result in an SMI being generated. An SMI handler routine is invoked that decodes the data and transfers the information to the 8042 keyboard controller where normal (legacy) keyboard processing takes place.
C-4 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
C.2.3 KEYBOARD LAYOUTS
Figures C-3 through C-8 show the key layouts for keyboards shipped with Compaq systems.
Actual styling details including location of the Compaq logo as well as the numbers lock, caps lock, and scroll lock LEDs may vary.
C.2.3.1
Standard Enhanced Keyboards
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
39 40 41 42 43 44 45 46 47 48 49 50 51
31
30
59
92
75
60 61
93
62 63 64 65
94
66 67 68 69
76 77 78 79 80 81 82 83 84 85
95
70 71
86
96
32 33 34
52 53 54
87
97 98 99
35 36 37 38
55 56 57
72 73 74
58
88 89 90
100 101
91
Figure C–3. U.S. English (101-Key) Keyboard Key Positions
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 31
39
75
59
40 41 42 43 44 45 46 47 48 49 50 51
60 61 62 63 64 65 66 67 68 69 70
103
71
104
76 77 78 79 80 81 82 83 84 85 86
92 93 94 95 96
32 33 34
52 53 54
87
97 98 99
35 36 37 38
55 56 57
72 73 74
58
88 89 90
100
101
91
Figure C–4. National (102-Key) Keyboard Key Positions
Changed –- July 2000
Compaq Personal Computers C-5
Appendix C Keyboard
C.2.3.2
Windows Enhanced Keyboards
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29
39 40 41 42 43 44 45 46 47 48 49 50 51
31
30
59 60 61 62 63 64 65 66 67 68 69 70 71
92
75
110
76 77 78 79 80 81 82 83 84 85
93 94 95 111 112
86
96
32 33 34
52 53 54
87
97 98 99
35 36 37 38
55 56 57
72 73 74
58
88 89 90
100
101
91
Figure C–5. U.S. English Windows (101W-Key) Keyboard Key Positions
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
17 18 19 20 21 22 23 24 25 26 27 28 29 31
39 40 41 42 43 44 45 46 47 48 49 50 51
75
59
104
60 61 62 63 64 65 66 67 68 69 70 103
76 77 78 79 80 81 82 83 84 85 86
71
92 110 93 94 95 111 112 96
32 33 34
52 53 54
87
97 98 99
35 36 37 38
55 56 57
72 73 74
58
88 89 90
100 101
91
Figure C–6. National Windows (102W-Key) Keyboard Key Positions
C-6 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
C.2.3.3
Easy Access Keyboards
The Easy Access keyboard is a Windows Enhanced-type keyboard that includes special buttons allowing quick internet navigation. Depending on system, either a 7-button or an 8-button layout may be supplied.
The 7-button Easy Access Keyboard uses the layout shown in Figure C-7 and is available with either a legacy PS/2-type connection or a Universal Serial Bus (USB) type connection.
Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7
NOTE:
Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Figure C–7. 7-Button Easy Access Keyboard Layout
The 8-button Easy Access Keyboard uses the layout shown in Figure C-8 and uses the PS/2-type connection.
Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8
NOTE:
Main key positions same as Windows Enhanced (Figures C-5 or C-6).
Figure C–8. 8-Button Easy Access Keyboard Layout
Changed –- July 2000
Compaq Personal Computers C-7
Appendix C Keyboard
C.2.4 KEYS
All keys generate a make code (when pressed) and a break code (when released) with the exception of the Pause key (pos. 16), which produces a make code only. All keys with the exception of the Pause and Easy Access keys are also typematic, although the typematic action of the Shift , Ctrl , Alt , Num Lock , Scroll Lock , Caps Lock , and Ins keys is suppressed by the
BIOS. Typematic keys, when held down longer than 500 ms, send the make code repetitively at a
10-12 Hz rate until the key is released. If more than one key is held down, the last key pressed will be typematic.
C.2.4.1
Special Single-Keystroke Functions
The following keys provide the intended function in most applications and environments.
Caps Lock - The Caps Lock key (pos. 59), when pressed and released, invokes a BIOS routine that turns on the caps lock LED and shifts into upper case key positions 40-49, 60-68, and 76-82. When pressed and released again, these keys revert to the lower case state and the
LED is turned off. Use of the Shift key will reverse which state these keys are in based on the
Caps Lock key.
Num Lock - The Num Lock key (pos. 32), when pressed and released, invokes a BIOS routine that turns on the num lock LED and shifts into upper case key positions 55-57, 72-74, 88-90,
100, and 101. When pressed and released again, these keys revert to the lower case state and the
LED is turned off.
The following keys provide special functions that require specific support by the application.
Print Scrn - The Print Scrn (pos. 14) key can, when pressed, generate an interrupt that initiates a print routine. This function may be inhibited by the application.
Scroll Lock - The Scroll Lock key (pos. 15) when pressed and released, , invokes a BIOS routine that turns on the scroll lock LED and inhibits movement of the cursor. When pressed and released again, the LED is turned off and the function is removed. This keystroke is always serviced by the BIOS (as indicated by the LED) but may be inhibited or ignored by the application.
Pause - The Pause (pos. 16) key, when pressed, can be used to cause the keyboard interrupt to loop, i.e., wait for another key to be pressed. This can be used to momentarily suspend an operation. The key that is pressed to resume operation is discarded. This function may be ignored by the application.
The Esc , Fn (function), Insert , Home , Page Up / Down , Delete , and End keys operate at the discretion of the application software.
C.2.4.2
Multi-Keystroke Functions
C-8 Compaq Personal Computers
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Technical Reference Guide
Shift - The Shift key (pos. 75/86), when held down, produces a shift state (upper case) for keys in positions 17-29, 30, 39-51, 60-70, and 76-85 as long as the Caps Lock key (pos. 59) is toggled off. If the Caps Lock key is toggled on, then a held Shift key produces the lower (normal) case for the identified pressed keys. The Shift key also reverses the Num Lock state of key positions
55-57, 72, 74, 88-90, 100, and 101.
Ctrl - The Ctrl keys (pos. 92/96) can be used in conjunction with keys in positions 1-13, 16, 17-
34, 39-54, 60-71, and 76-84. The application determines the actual function. Both Ctrl key positions provide identical functionality. The pressed combination of Ctrl and Break (pos. 16) results in the generation of BIOS function INT 1Bh. This software interrupt provides a method of exiting an application and generally halts execution of the current program.
Alt - The Alt keys (pos. 93/95) can be used in conjunction with the same keys available for use with the Ctrl keys with the exception that position 14 ( SysRq ) is available instead of position 16
( Break ). The Alt key can also be used in conjunction with the numeric keypad keys (pos. 55-57,
72-74, and 88-90) to enter the decimal value of an ASCII character code from 1-255. The application determines the actual function of the keystrokes. Both Alt key positions provide identical functionality. The combination keystroke of Alt and SysRq results in software interrupt
15h, AX=8500h being executed. It is up to the application to use or not use this BIOS function.
The Ctrl and Alt keys can be used together in conjunction with keys in positions 1-13, 17-34, 39-
54, 60-71, and 76-84. The Ctrl and Alt key positions used and the sequence in which they are pressed make no difference as long as they are held down at the time the third key is pressed. The
Ctrl , Alt, and Delete keystroke combination (required twice if in the Windows environment) initiates a system reset (warm boot) that is handled by the BIOS.
C.2.4.3
Windows Keystrokes
Windows-enhanced keyboards include three additional key positions. Key positions 110 and 111
(marked with the Windows logo ) have the same functionality and are used by themselves or in combination with other keys to perform specific “hot-key” type functions for the Windows operating system. The defined functions of the Windows logo keys are listed as follows:
Window Logo
Window Logo + F1
Window Logo + TAB
Window Logo + E
Open Start menu
Display pop-up menu for the selected object
Activate next task bar button
Explore my computer
Window Logo + F Find document
Window Logo + CTRL + F Find computer
Window Logo + M
Shift + Window Logo + M
Minimize all
Undo minimize all
Window Logo + R
Window Logo + PAUSE
Window Logo + 0-9
Display Run dialog box
Perform system function
Reserved for OEM use (see following text)
The combination keystroke of the Window Logo + 1-0 keys are reserved for OEM use for auxiliary functions (speaker volume, monitor brightness, password, etc.).
Key position 112 (marked with an application window icon ) is used in combination with other keys for invoking Windows application functions.
C.2.4.4
Easy Access Keystrokes
Compaq Personal Computers C-9
Changed –- July 2000
Appendix C Keyboard
The Easy Access keyboards (Figures C-7 and C-8) include additional keys (also referred to as buttons) used to streamline internet access and navigation.
These buttons, which can be re-programmed to provide other functions, have the default functionality described below:
7-Button Easy Access Keyboard:
Button # Description Default Function
Emoney 2
3
4
Go to community
Extra web site
Go to favorite web site
Compaq web site
AltaVista web site
5 Internet Search
6 Instant expenses
7 E-commerce Shopping
8-Button Easy Access Keyboard:
4
5
6
7
8
Button # Description
1 Go to favorite web site
2
3
Go to AltaVista
Search
Check Email
Business Community
Market Monitor
Meeting Center
News/PC Lock
Default Function
Customer web site of choice
AltaVista web site
AltaVista search engine
Launches user Email
Industry specification info
Launches Bloomberg market monitor
Links to user’s project center
News retrieval service
All buttons may be re-programmed by the user through the Easy Access utility.
C-10 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
C.2.5 KEYBOARD COMMANDS
Table C-1 lists the commands that the keyboard can send to the system (specifically, to the 8042type logic).
Table C–1. Keyboard-to-System Commands
BAT Completion
BAT Failure
Echo
Acknowledge (ACK)
Resend
Keyboard ID
Table C-1.
Keyboard-to-System Commands
Command
Key Detection Error/Over/run
Value
00h [1]
FFh [2]
AAh
FCh
EEh
Description
Indicates to the system that a switch closure couldn’t be identified.
Indicates to the system that the BAT has been successful.
Indicates failure of the BAT by the keyboard.
Indicates that the Echo command was received by the keyboard.
FAh Issued by the keyboard as a response to valid system inputs (except the Echo and Resend commands).
Issued by the keyboard following an invalid input. FEh
83ABh Upon receipt of the Read ID command from the system, the keyboard issues the ACK command followed by the two IDS bytes.
Note:
[1] Modes 2 and 3.
[2] Mode 1 only.
C.2.6 SCAN CODES
The scan codes generated by the keyboard processor are determined by the mode the keyboard is operating in.
♦
Mode 1: In Mode 1 operation, the keyboard generates scan codes compatible with 8088-
/8086-based systems. To enter Mode 1, the scan code translation function of the keyboard controller must be disabled. Since translation is not performed, the scan codes generated in
Mode 1 are identical to the codes required by BIOS. Mode 1 is initiated by sending command
F0h with the 01h option byte. Applications can obtain system codes and status information by using BIOS function INT 16h with AH=00h, 01h, and 02h.
♦
Mode 2: Mode 2 is the default mode for keyboard operation. In this mode, the 8042 logic translates the make codes from the keyboard processor into the codes required by the BIOS.
This mode was made necessary with the development of the Enhanced III keyboard, which includes additional functions over earlier standard keyboards. Applications should use BIOS function INT 16h, with AH=10h, 11h, and 12h for obtaining codes and status data. In Mode 2, the keyboard generates the Break code, a two-byte sequence that consists of a Make code immediately preceded by F0h (i.e., Break code for 0Eh is “F0h 0Eh”).
♦
Mode 3: Mode 3 generates a different scan code set from Modes 1 and 2. Code translation must be disabled since translation for this mode cannot be done.
Changed –- July 2000
Compaq Personal Computers C-11
Appendix C Keyboard
Table C–2. Keyboard Scan Codes
Key
Pos.
Legend
1 Esc
2 F1
3 F2
4 F3
5 F4
6 F5
7 F6
8 F7
9 F8
10 F9
11 F10
12 F11
13 F12
14 Print Scrn
15
16
22
23
24
25
26
17
18
19
20
21
`
1
2
3
4
5
6
7
8
9
27
28
29
0
-
=
30
31
\
Backspace
32 Insert
33
34
36
Scroll Lock
Pause
Home
Page Up
/
37 *
38 -
39 Tab
40 Q
Table C-2.
Keyboard Scan Codes
Mode 1
Make / Break Codes (Hex)
Mode 2
01/81
3B/BB
3C/BC
3D/BD
3E/BE
3F/BF
40/C0
41/C1
42/C2
43/C3
44/C4
57/D7
58/D8
E0 2A E0 37/E0 B7 E0 AA
E0 37/E0 B7 [1] [2]
54/84 [3]
46/C6
E1 1D 45 E1 9D C5/na
E0 46 E0 C6/na [3]
29/A9
02/82
03/83
04/84
05/85
06/86
07/87
08/88
09/89
0A/8A
0B/8B
0C/8C
0D/8D
2B/AB
0E/8E
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 52/E0 D2 E0 AA [6]
E0 47/E0 D2
E0 AA E0 52/E0 D2 E0 2A [4]
E0 2A E0 47/E0 C7 E0 AA [6]
E0 49/E0 C7
E0 AA E0 49/E0 C9 E0 2A [4]
E0 2A E0 49/E0 C9 E0 AA [6]
45/C5
E0 35/E0 B5
E0 AA E0 35/E0 B5 E0 2A [1]
37/B7
4A/CA
0F/8F
10/90
E0 2A E0 7C/E0 F0 7C E0 F0 12
E0 7C/E0 F0 7C [1] [2]
84/F0 84 [3]
7E/F0 7E
E1 14 77 E1 F0 14 F0 77/na
E0 7E E0 F0 7E/na [3]
0E/F0 E0
16/F0 16
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5D/F0 5D
66/F0 66
E0 70/E0 F0 70
E0 F0 12 E0 70/E0 F0 70 E0 12 [5]
E0 12 E0 70/E0 F0 70 E0 F0 12 [6]
E0 6C/E0 F0 6C
E0 F0 12 E0 6C/E0 F0 6C E0 12 [5]
E0 12 E0 6C/E0 F0 6C E0 F0 12 [6]
E0 7D/E0 F0 7D
E0 F0 12 E0 7D/E0 F0 7D E0 12 [5]
E0 12 E0 7D/E0 F0 7D E0 F0 12 [6]
E0 4A/E0 F0 4A
E0 F0 12 E0 4A/E0 F0 4A E0 12 [1]
5F/na
62/na
0E/F0 0E
46/F0 46
1E/F0 1E
26/F0 26
25/F0 25
2E/F0 2E
36/F0 36
3D/F0 3D
3E/F0 3E
46/F0 46
45/F0 45
4E/F0 4E
55/F0 55
5C/F0 5C
66/F0 66
67/na
6E/na
6F/na
76/na
77/na
7E/na
84/na
0D/na
15/na
Continued
Mode 3
08/na
07/na
0F/na
17/na
1F/na
27/na
2F/na
37/na
3F/na
47/na
4F/na
56/na
5E/na
57/na
([x] Notes listed at end of table.)
C-12 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
55
56
57
58
59
7
8
9
+
Caps Lock
60 A
61 S
62 D
63 F
64 G
65 H
66 J
67 K
68 L
69 ;
70 ‘
71 Enter
72
73
4
5
74 6
75 Shift (left)
76 Z
77 X
78 C
79 V
80 B
Table C-2. Keyboard Scan Codes (Continued)
Key
Pos Legend Mode 1
Make / Break Codes (Hex)
Mode 2
41 W
42 E
43 R
44 T
45 Y
46 U
47 I
48 O
49 P
50 [
51 ]
52 Delete
11/91
12/92
13/93
14/94
15/95
16/96
17/97
18/98
19/99
1A/9A
1B/9B
E0 53/E0 D3
E0 AA E0 53/E0 D3 E0 2A [4]
E0 2A E0 53/E0 D3 E0 AA [6]
24/F0 24
53 End
54 Page Down
E0 AA E0 4F/E0 CF E0 2A [4]
E0 2A E0 4F/E0 CF E0 AA [6]
E0 51/E0 D1
E0 AA E0 51/E0 D1 E0 2A [4]
E0 @a E0 51/E0 D1 E0 AA [6]
E0 71/E0 F0 71
E0 F0 12 E0 71/E0 F0 71 E0 12
[5]
E0 12 E0 71/E0 F0 71 E0 F0 12
[6]
E0 69/E0 F0 69
E0 F0 12 E0 69/E0 F0 69 E0 12
[5]
E0 12 E0 69/E0 F0 69 E0 F0 12
[6]
E0 7A/E0 F0 7A
E0 F0 12 E0 7A/E0 F0 7A E0 12
[5]
E0 12 E0 7A/E0 F0 7A E0 F0 12
[6]
6C/F0 6C [6]
75/F0 75 [6]
7D/F0 7D [6]
79/F0 79 [6]
58/F0 58
47/C7 [6]
48/C8 [6]
49/C9 [6]
4E/CE [6]
3A/BA
1E/9E
1F/9F
20/A0
21/A1
22/A2
23/A3
24/A4
25/A5
26/A6
27/A7
28/A8
1C/9C
4B/CB [6]
4C/CC [6]
4D/CD [6]
2A/AA
2C/AC
2D/AD
2E/AE
2F/AF
30/B0
6B/F0 6B [6]
73/F0 73 [6]
74/F0 74 [6]
12/F0 12
Mode 3
24/F0 24
64/F0 64
65/F0 65
6D/F0 6D
6C/na [6]
75/na [6]
7D/na [6]
7C/F0 7C
14/F0 14
6B/na [6]
73/na [6]
74/na [6]
12/F0 12
Continued
([x] Notes listed at end of table.)
Changed –- July 2000
Compaq Personal Computers C-13
Appendix C Keyboard
Table C-2. Keyboard Scan Codes (Continued)
Key
Pos.
Legend Mode 1
Make / Break Codes (Hex)
Mode 2
88
89
90
91
81 N
82 M
83 ,
84 .
85 /
86 Shift (right)
87
1
2
3
Enter
31/B1
32/B2
33/B3
34/B4
35/B5
36/B6
E0 48/E0 C8
E0 AA E0 48/E0 C8 E0 2A [4]
E0 2A E0 48/E0 C8 E0 AA [6]
4F/CF [6]
50/D0 [6]
51/D1 [6]
E0 1C/E0 9C
59/F0 59
E0 75/E0 F0 75
E0 F0 12 E0 75/E0 F0 75 E0 12 [5]
E0 12 E0 75/E0 F0 75 E0 F0 12 [6]
69/F0 69 [6]
72/F0 72 [6]
7A/F0 7A [6]
E0 5A/F0 E0 5A
14/F0 14
11/F0 11
92
93
Ctrl (left)
Alt (left)
94 (Space)
95
96
Alt (right)
Ctrl (right)
97
98
1D/9D
38/B8
39/B9
E0 38/E0 B8
E0 1D/E0 9D
E0 AA E0 4B/E0 CB E0 2A [4]
E0 2A E0 4B/E0 CB E0 AA [6]
E0 50/E0 D0
E0 AA E0 50/E0 D0 E0 2A [4]
E0 2A E0 50/E0 D0 E0 AA [6]
99
100
101
111
0
.
102 na
103 na
104 na
110 (Win95) [7]
(Win95) [7]
112 (Win
Apps)
[7]
E0 AA E0 4D/E0 CD E0 2A [4]
E0 2A E0 4D/E0 CD E0 AA [6]
52/D2 [6]
53/D3 [6]
7E/FE
2B/AB
36/D6
E0 5B/E0 DB
E0 AA E0 5B/E0 DB E0 2A [4]
E0 2A E0 5B/E0 DB E0 AA [6]
E0 5C/E0 DC
E0 AA E0 5C/E0 DC E0 2A [4]
E0 2A E0 5C/E0 DC E0 AA [6]
E0 5D/E0 DD
E0 AA E0 5D/E0 DD E0 2A [4]
E0 2A E0 5D E0 DD E0 AA [6]
Mode 3
59/F0 59
63/F0 63
69/na [6]
72/na [6]
7A/na [6]
79/F0
79[6]
11/F0 11
19/F0 19
E0 11/F0 E0 11
E0 14/F0 E0 14
E0 6B/Eo F0 6B
E0 F0 12 E0 6B/E0 F0 6B E0 12[5]
E0 12 E0 6B/E0 F0 6B E0 F0 12[6]
E0 72/E0 F0 72
E0 F0 12 E0 72/E0 F0 72 E0 12[5]
E0 12 E0 72/E0 F0 72 E0 F0 12[6]
E0 74/E0 F0 74
E0 F0 12 E0 74/E0 F0 74 E0 12[5]
E0 12 E0 74/E0 F0 74 E0 F0 12[6]
70/F0 70 [6]
71/F0 71 [6]
39/na
58/na
61/F0 61
60/F0 60
6A/F0 6A
70/na [6]
71/na [6]
E0 1F/E0 F0 1F
E0 F0 12 E0 1F/E0 F0 1F E0 12 [5]
E0 12 E0 1F/E0 F0 1F E0 F0 12 [6]
E0 2F/E0 F0 27
E0 F0 12 E0 27/E0 F0 27 E0 12 [5]
E0 12 E0 27/E0 F0 27 E0 F0 12 [6]
E0 2F/E0 F0 2F
E0 F0 12 E0 2F/E0 F0 2F E0 12 [5]
E0 12 E0 2F/E0 F0 2F E0 F0 12 [6
8B/F0 8B
8C/F0 8C
8D/F0 8D
Continued
([x] Notes listed at end of table.)
C-14 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
Table C-2. Keyboard Scan Codes (Continued)
Key
Pos.
Legend
Btn 1 [8]
Btn 2 [8]
Btn 3 [8]
Btn 4 [8]
Btn 5 [8]
Btn 6 [8]
Btn 7 [8]
Btn 1 [9]
Btn 2 [9]
Btn 3 [9]
Btn 4 [9]
Btn 5 [9]
Btn 6 [9]
Btn 7 [9]
Btn 8 [9]
Mode 1
E0 1E/E0 9E
E0 26/E0 A6
E0 25/E0 A5
E0 23/E0 A3
E0 21/E0 A1
E0 12/E0 92
E0 32/E0 B2
E0 23/E0 A3
E0 1F/E0 9F
E0 1A/E0 9A
E0 1E/E0 9E
E0 13/E0 93
E0 14/E0 94
E0 15/E0 95
E0 1B/E0 9B
Make / Break Codes (Hex)
Mode 2
E0 1C/E0 F0 1C
E0 4B/E0 F0 4B
E0 42/E0 F0 42
E0 33/E0 F0 33
E0 2B/E0 F0 2B
E0 24/E0 F0 24
E0 3A/E0 F0 3A
E0 33/E0 F0 33
E0 1B/E0 F0 1B
E0 54/E0 F0 54
E0 1C/E0 F0 1C
E0 2D/E0 F0 2D
E0 2C/E0 F0 2C
E0 35/E0 F0 35
E0 5B/E0 F0 5B
NOTES:
All codes assume Shift, Ctrl, and Alt keys inactive unless otherwise noted.
NA = Not applicable
[1] Shift (left) key active.
[2] Ctrl key active.
[3] Alt key active.
[4] Left Shift key active. For active right Shift key, substitute AA/2A make/break codes for B6/36 codes.
[5] Left Shift key active. For active right Shift key, substitute F0 12/12 make/break codes
for F0 59/59 codes.
[6] Num Lock key active.
[7] Windows keyboards only.
[8] 7-Button Easy Access keyboard.
[9] 8-Button Easy Access keyboard.
Mode 3
95/F0 95
9C/F0 9C
9D/F0 9D
9A/F0 9A
99/F0 99
96/F0 96
97/F0 97
9A/F0 9A
80/F0 80
99/F0 99
95/F0 95
0C/F0 0C
9D/F0 9D
96/F0 96
97/F0 97
Changed –- July 2000
Compaq Personal Computers C-15
Appendix C Keyboard
C.3
CONNECTORS
Two types of keyboard interfaces are used in Compaq systems: PS/2-type and USB-type. System units that provide a PS/2 connector will ship with a PS/2-type keyboard but may also support simultaneous connection of a USB keyboard. Systems that do not provide a PS/2 interface will ship with a USB keyboard. For a detailed description of the PS/2 and USB interfaces refer to chapter 5 “Input/Output” of this guide. The keyboard cable connectors and their pinouts are described in the following figures:
Pin Function
1 Data
3 Ground
5 Clock
3
5
1 2
6
4
Figure C–9. PS/2 Keyboard Cable Connector (Male)
Pin Function
4 Ground
Figure C–10. USB Keyboard Cable Connector (Male)
4 3 2 1
C-16 Compaq Personal Computers
Changed - July 2000
Technical Reference Guide
Appendix D
COMPAQ/NVIDIA TNT2 PRO
AGP GRAPHICS CARD
D.
Appendix D Compaq/NVIDIA TNT2 Pro AGP Graphics Card
D.1
INTRODUCTION
This appendix describes the Compaq/NVIDIA TNT2 Pro AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot. The Compaq/NVIDIA TNT2 Pro graphics card
(P/N 189998-B21) provides high 2D performance as well as 3D capabilities.
Feature Connector
Analog
Monitor
Connector
SGRAM SGRAM
NVIDIA
TNT2
Controller
SGRAM
SGRAM
Figure D-1. Compaq/NVIDIA TNT2 Pro AGP Graphics Card (P/N 198998-B21) Layout
This appendix covers the following subjects:
♦
Functional description (D.2)
♦
Display modes (D.3)
♦
Software support information (D.4)
♦
Monitor power management (D.5)
♦
Connectors (D.6) page D-2 page D-3 page D-4 page D-4 page D-5
D.2
FUNCTIONAL DESCRIPTION
Original - July 2000
Compaq Personal Computers D-1
Appendix D Compaq/NVIDIA TNT2 Pro AGP Graphics Card
The NVIDIA TNT2 Pro-SD Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
16 megabytes of on-board SGRAM stores the main display image.
Card
Edge
Connector
AGP
Bus
AGP 4X
I/F
NVIDIA TNT2 Graphics Controller
2D/VGA
Engine
Video
Scalar
3D Array
Engine
Memory
I/F
CRT
Controller
300-MHz
RAM
DAC
128-bit
166-MHz
Data Bus
VSync
HSync
RGB
16 MB
SGRAM
Analog
Monitor
Connector
BIOS
ROM
Figure D-2. NVIDIA TNT2 Pro Graphics Card Block diagram
The NVIDIA TNT2 Pro Graphics Card includes the following features:
♦
16-MB SGRAM frame buffer using 128-bit 166-MHz access
♦
AGP 4X transfers with sideband addressing
♦
2D drawing engine
♦
3D rendering engine
♦
300-MHz RAMDAC
♦
32-bit Z/stencil buffer eliminates hidden screen portions for faster loading
♦
32-bit color for increased image quality
♦
30-fps full-screen DVD playback
♦
Dual-monitor support with a PCI graphics card
D-2 Compaq Personal Computers
Original - July 2000
Technical Reference Guide
D.3
DISPLAY MODES
The graphics display modes supported by the NVIDIA TNT2 Pro Graphics are listed in Table D-
1.
Table D-1. NVIDIA TNT2 Pro Graphics Display Modes
Resolution
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
1600 x 1200
1800 x 1440
1800 x 1440
1800 x 1440
1920 x 1080
1920 x 1080
1920 x 1080
1920 x 1200
Table D-1.
NVIDIA TNT2 Pro Graphics Display Modes
24
8
16
24
8
16
24
8
16
24
8
Bits per pixel
8
16
24
8
16
24
8
16
24
8
16
24
8
16
Color Depth
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
Max. Refresh Frequency (Hz)
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
85
75
Original - July 2000
Compaq Personal Computers D-3
Appendix D Compaq/NVIDIA TNT2 Pro AGP Graphics Card
D.4
SOFTWARE SUPPORT INFORMATION
The NVIDIA TNT2 Pro graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as:
♦
Windows 98, 95
♦
Windows NT 4.0, 3.51
♦
Windows 3.11, 3.1
♦
OS/2
♦
Quick Draw
♦
MS Direct Draw and Direct X
♦
Direct 3D
♦
OpenGL
D.5
POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table I-2 lists the monitor power conditions.
Table D-2. Monitor Power Management Conditions
HSYNC VSYNC
Active Active
Active Inactive
Inactive Inactive
Table D-2.
Monitor Power Management Conditions
Power Mode
On
Suspend
Off
Description
Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
The graphics card’s maximum power consumption on the AGP bus is listed below:
Maximum current draw @ 3.3 VDC: 3.0 A
Maximum current draw @ 5.0 VDC: 50 mA
Maximum current draw @ 1.5 VDC: 10 mA
Maximum power consumption: 10.2 watts
D-4 Compaq Personal Computers
Original - July 2000
Technical Reference Guide
D.6
CONNECTORS
There are two connectors associated with the graphics subsystem; the display/monitor connector and the Feature connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide.
The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner.
D.6.1 MONITOR CONNECTOR
9
Figure D-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table D-3. DB-15 Monitor Connector Pinout
Table D-3.
DB-15 Monitor Connector Pinout
6
7
8
Pin Signal
1 R Red Analog
2 G
3
4
B
NC
Green Analog
Not Connected
5 GND Ground
R GND
G GND
B GND
Red Analog Ground
Green Analog Ground
Blue Analog Ground
9 PWR
10 GND
11
12
NC
SDA
13 HSync
14 VSync
15
--
SCL
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Vertical Sync
DDC2-B Clock
--
Original - July 2000
Compaq Personal Computers D-5
Appendix D Compaq/NVIDIA TNT2 Pro AGP Graphics Card
This page is intentionally blank.
D-6 Compaq Personal Computers
Original - July 2000
Technical Reference Guide
Appendix E
COMPAQ/NVIDIA QUADRO2 EX/MXR
AGP GRAPHICS CARDS
E.
Appendix E Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics
Cards
E.1
INTRODUCTION
This appendix describes the Compaq/NVIDIA Quadro2 EX and MXR AGP Graphics Cards used in the standard configuration on some models and also available as an option. These cards (layout shown in the following figure) installs in a system’s AGP slot and provide high 2D performance as well as entry-level 3D capabilities.
Feature Connector
DVI
Monitor
Connector
Analog
Monitor
Connector
SDRAM SDRAM
NVIDIA
NV11GL
Controller
SDRAM
SDRAM
NOTES:
NVIDIA Quadro2 EX Graphics Card PCA# 221411-001
NVIDIA Quadro2 MXR Graphics Card PCA #xxxxxx-xx1
NVIDIA Quadro2 MXR Graphics Card only
Figure E-1. Compaq/NVIDIA Quadro2 EX or MXR AGP Graphics Card (PCA# 221411-001)
Layout
This appendix covers the following subjects:
♦
Functional description (D.2)
♦
Display modes (D.3)
♦
Software support information (D.4)
♦
Monitor power management (D.5)
♦
Connectors (D.6) page D-2 page D-3 page D-4 page D-4 page D-5
Changed - April 2001
Compaq Personal Computers E-1
Appendix J Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
E.2
FUNCTIONAL DESCRIPTION
The NVIDIA Quadro2 MXR Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
32 megabytes of on-board SDRAM stores the main display image.
Card
Edge
Connector
AGP
Bus
BIOS
ROM
AGP 4X
I/F
NVIDIA NV11GL Graphics Controller
Video
Scalar
Memory
I/F
CRT
Controller
2D/VGA
Engine
3D Array
Engine
350-MHz
RAM
DAC
128-bit
166-MHz
Data Bus 32 MB
SDRAM
Frame Buffer
VSync
HSync
Analog
Monitor
Connector
RGB
Digital Video
Interface
Figure E-2. NVIDIA Quadro2 EX/MXR Graphics Card Block diagram
DVI
DVI
Monitor
Connector
(Quadro MXR only)
The NVIDIA Quadro2 EX/MXR Graphics Cards include the following features:
♦
32-MB SDRAM frame buffer using 128-bit 183-MHz access
♦
AGP 4X transfers with sideband addressing
♦
2D drawing engine
♦
3D rendering engine
♦
350-MHz RAMDAC
♦
32-bit Z/stencil buffer eliminates hidden screen portions for faster loading
♦
32-bit color for increased image quality
♦
30-fps full-screen DVD playback
♦
Dual-monitor support with a PCI graphics card
♦
DVI monitor support (Quadro MXR only)
The NVIDIA Quadro2 MXR provides, in addition to the RGB monitor connector, a digital video interface (DVI) connector that can directly drive a DVI monitor or another RGB monitor through an adapter.
E-2 Compaq Personal Computers
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Technical Reference Guide
E.3
DISPLAY MODES
The 2D graphics display modes supported by the NVIDIA Quadro2 MXR Graphics are listed in
Table E-1.
Table E-1. NVIDIA Quadro2 MXR Graphics Display Modes
Table E-1.
NVIDIA Quadro2 EX/MXR Graphics Display Modes
Resolution
1600 x 1000
1600 x 1000
1600 x 1000
1600 x 1200
1600 x 1200
1600 x 1200
1600 x 1280
1600 x 1280
1600 x 1280
1920 x 1080
1920 x 1080
1920 x 1080
1920 x 1200
1920 x 1200
1920 x 1200
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1280 x 1024
1280 x 1024
1280 x 1024
Bits per pixel
16
32
8
16
32
8
16
32
8
16
32
8
8
16
32
8
16
8
16
32
8
16
32
32
8
16
32
8
16
32
Color Depth
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
Max. Refresh
Frequency (Hz) [1]
200
200
200
170
170
170
150
150
150
120
120
120
100
100
100
100
240
240
240
240
240
240
100
100
85
85
85
85
85
85
NOTE:
[1] Values reflect hardware capability. May be restricted to lower frequency by operating system.
Memory Used
For Texture
N/A
22.6 MB
13.3 MB
N/A
20.8 MB
9.5 MB
N/A
20.0 MB
8.0 MB
N/A
19.9 MB
7.7 MB
N/A
18.5 MB
5.0 MB
N/A
N/A
28.4 MB
N/A
N/A
26.4 MB
N/A
N/A
22.8 MB
N/A
N/A
20.3 MB
N/A
N/A
16.6 MB
Changed - April 2001
Compaq Personal Computers E-3
Appendix J Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
E.4
SOFTWARE SUPPORT INFORMATION
The NVIDIA Quadro2 MXR graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as:
♦
Windows 3.1, 95, 98, 2000, ME
♦
Windows NT 4.0, 3.51
♦
Whistler
♦
Linux
♦
OS/2
♦
Quick Draw
♦
MS Direct Draw and Direct X
♦
Direct 3D
♦
OpenGL
E.5
POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table E-2 lists the monitor power conditions.
Table E-2. Monitor Power Management Conditions
HSYNC VSYNC
Active Active
Active Inactive
Inactive Inactive
Table E-2.
Monitor Power Management Conditions
Power Mode
On
Suspend
Off
Description
Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to timeout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
E-4 Compaq Personal Computers
Changed - April 2001
Technical Reference Guide
E.6
CONNECTORS
There are two connectors associated with the graphics subsystem; the display/monitor connector and the Feature connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide.
The DB-15 disply/monitor connector is provided for connection of a compatible RGB/analog monitor. The Feature connector allows the attachment of an optional card such as a video tuner.
E.6.1 MONITOR CONNECTOR
5 4 3 2 1
15
10 9 8 7 6
14 13 12 11
Figure E-3. VGA Monitor Connector, (Female DB-15, as viewed from rear).
Table E-3. DB-15 Monitor Connector Pinout
Table E-3.
DB-15 Monitor Connector Pinout
6
7
8
Pin Signal
1 R Red Analog
2 G
3
4
B
NC
Green Analog
Not Connected
5 GND Ground
R GND
G GND
B GND
Red Analog Ground
Green Analog Ground
Blue Analog Ground
9 PWR
10 GND
11
12
NC
SDA
13 HSync
14 VSync
15
--
SCL
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Vertical Sync
DDC2-B Clock
--
Changed - April 2001
Compaq Personal Computers E-5
Appendix J Compaq/NVIDIA Quadro2 EX/MXR AGP Graphics Cards
This page is intentionally blank.
E-6 Compaq Personal Computers
Changed - April 2001
Technical Reference Guide
Appendix F
COMPAQ/Matrox Millennium G450
AGP GRAPHICS CARD
F.
Appendix F Compaq/Matrox Millennium G450 AGP Graphics
Card
F.1
INTRODUCTION
This appendix describes the Compaq/Matrox Millennium G450 AGP Graphics Card used in the standard configuration on some models and also available as an option. This card (layout shown in the following figure) installs in a system’s AGP slot. The Compaq/Matrox Millennium G450 graphics card (SP# 203626-001) provides high 2D performance and entry-level 3D capabilities.
This card features a dual-RAMDAC design for driving two analog displays.
Feature Connector
RGB Monitor
Connectors
SD
RAM
SD
RAM
MGA
Dual-RAMDAC
Controller
SDRAM
SDRAM
Figure F-1. Compaq/Matrox Millennium G450 AGP Graphics Card Layout (PCA# 202901-001)
This appendix covers the following subjects:
♦
Functional description (F.2)
♦
Display modes (F.3)
♦
Software support information (F.4)
♦
Monitor power management (F.5)
♦
Connectors (F.6) page F-2 page F-3 page F-4 page F-4 page F-5
Original - November 2000
Compaq Personal Computers F-1
Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.2
FUNCTIONAL DESCRIPTION
The Matrox Millennium G450-SD Graphics Card provides high performance 2D and 3D display imaging. The card’s AGP design provides an economical approach to 3D processing by offloading 3D effects such as texturing, z-buffering and alpha blending to the system memory while
32 megabytes of on-board SDRAM stores the main display image.
Card
Edge
Connector
AGP
Bus
BIOS
ROM
AGP 4X
I/F
MGA Graphics Controller
Video
Scalar
Memory
I/F
350-MHz
RAMDAC
2D/VGA
Engine
3D Array
Engine
CRT
Controller
200-MHz
RAMDAC
Figure F-2. Matrox Millennium G450 Graphics Card Block diagram
128-bit
166-MHz
Data Bus
32 MB
SDRAM
Frame Buffer
RGB
H/VSync
H/VSync
Analog
Monitor
Connector 1
RGB
Analog
Monitor
Connector 2
The Matrox Millennium G450 Graphics Card includes the following features:
♦
64-MB SDRAM frame buffer using 128-bit 166-MHz access
♦
AGP 4X transfers with sideband addressing
♦
2D drawing engine with:
•
128-bit BitBLTs, rectangle/polygon fills, line draws
•
Hardware cursor
•
8-/16-/32-bpp mode acceleration
♦
Dual-head features:
•
Two analog monitor (RGB) ports
•
DVD max mode
•
DualHead zoom mode
•
DualHead clone mode
•
DualHead TV output mode
♦
3D accelerator with:
•
Hardware transform and lighting
•
Anistropic filtering
•
Specular lighting diffuse, flat and Gouraud shading
•
16-/24-bit Z-buffering
♦
360-MHz primary RAMDAC, 200-MHz secondary RAMDAC
♦
VESA compliancy:
•
Dual DDC2B monitor support
•
VIP 2.0 interface
•
DPMS, EPA Energy Star, and ACPI-compliant power management
F-2 Compaq Personal Computers
Original - November 2000
Technical Reference Guide
F.3
DISPLAY MODES
The graphics display modes supported by the Matrox Millennium G450 Graphics are listed in
Table F-1.
Table F-1. Matrox Millennium G450 Graphics Display Modes
Table F-1.
Matrox Millennium G450 Graphics Display Modes
Resolution Bits per pixel Color Depth
Max. Vertical
Refresh Freq. [1]
Supporting
RAMDAC
NOTE:
32
8
16
24
32
24
32
8
16
24
16
24
32
8
16
8
16
24
32
8
16
24
32
8
16
24
8
8
16
24
32
8
16
24
8
16
24
8
16
640 x 480
640 x 480
640 x 480
640 x 480
800 x 600
800 x 600
800 x 600
800 x 600
1024 x 768
1024 x 768
1024 x 768
1024 x 768
1152 x 864
1152 x 864
1152 x 864
1152 x 864
1280 x 960
1280 x 960
1280 x 960
1280 x 960
1280 x 1024
1280 x 1024
1280 x 1024
1280 x 1024
1600 x 1200
1600 x 1200
1600 x 1200
1600 x 1200
1800 x 1440
1800 x 1440
1800 x 1440
1856 x 1392
1856 x 1392
1856 x 1392
1920 x 1440
1920 x 1440
1920 x 1440
2048 x 768
2048 x 768
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
16.7M
256
65K
[1] Value reflects hardware capabilities only. May be restricted by operating system.
85 Hz
85 Hz
75 Hz
75 Hz
75 Hz
75 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
85 Hz
75 Hz
75 Hz
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary, Secondary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Primary
Original - November 2000
Compaq Personal Computers F-3
Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.4
SOFTWARE SUPPORT INFORMATION
The Matrox Millennium G450 graphics card is fully compatible with software written for legacy video modes (VGA, EGA, CGA) and needs no driver support for those modes.
Drivers are provided with or available for the card to provide extended mode support for the current operating systems and programming environments such as:
♦
Windows 2000
♦
Windows NT 4.0
♦
Autodesk AutoCAD R14 and 2000
♦
Kintex 3D Studio Max
♦
2D GDI
♦
MS DirectDraw DX6-7, ActiveX, DirectX, Direct3D,
♦
OpenGL 1.1 and 1.2
F.5
POWER MANAGEMENT AND CONSUMPTION
This controller provides monitor power control for monitors that conform to the VESA display power management signaling (DPMS) protocol. This protocol defines different power consumption conditions and uses the HSYNC and VSYNC signals to select a monitor’s power condition. Table F-2 lists the monitor power conditions.
Table F-2. Monitor Power Management Conditions
HSYNC VSYNC
Active Active
Active Inactive
Inactive Inactive
Table F-2.
Monitor Power Management Conditions
Power Mode
On
Suspend
Off
Description
Monitor is completely powered up. If activated, the inactivity counter counts down during system inactivity and if allowed to tiemout, generates an SMI to initiate the Suspend mode.
Monitor’s high voltage section is turned off and CRT heater
(filament) voltage is reduced from 6.6 to 4.4 VDC. The Off mode inactivity timer counts down from the preset value and if allowed to timeout, another SMI is generated and serviced, resulting in the monitor being placed into the Off mode. Wake up from
Suspend mode is typically a few seconds.
Monitor’s high voltage section and heater circuitry is turned off.
Wake up from Off mode is a little longer than from Suspend.
Power consumption of this card on the PCI bus is listed in the following table:
Voltage
Maximum Current Drain
Maximum Power Consumption
VddQ
(1.5 VDC)
.05 A
0.75 W
Total maximum power consumption for this card is 9.1 watts.
Vcc3
(3.3 VDC)
2.4 A
7.99 W
Vcc5
(5.0 VDC)
0.2 A
1.04 W
F-4 Compaq Personal Computers
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Technical Reference Guide
F.6
CONNECTORS
There are three connectors associated with the graphics subsystem; two display/monitor connectors and the Feature connector.
NOTE: The graphic card’s edge connector mates with the AGP slot connector on the system board. This interface is described in chapter 4 of this guide.
F.6.1 MONITOR CONNECTOR
The display/monitor connector is provided for connection of a compatible RGB/analog monitor.
5 4 3 2 1
10 9 8 7 6
15 14 13 12 11
Figure F-3. VGA Monitor Connector, (One of two female DB-15, as viewed from rear).
Table F-3. DB-15 Monitor Connector Pinout
Table F-3.
DB-15 Monitor Connector Pinout
Pin Signal
1 R Red Analog
2 G
3
4
B
NC
Green Analog
Not Connected
5 GND Ground
6
7
8
R GND
G GND
B GND
Red Analog Ground
Green Analog Ground
Blue Analog Ground
9 PWR
10 GND
11 NC
12 SDA
13 HSync
14
15
--
VSync
SCL
--
NOTES:
[1] Fuse automatically resets when excessive load is removed.
+5 VDC (fused) [1]
Ground
Not Connected
DDC2-B Data
Vertical Sync
DDC2-B Clock
--
Original - November 2000
Compaq Personal Computers F-5
Appendix H Compaq/Matrox Millennium G450 AGP Graphics Card
F.6.2 VIDEO FEATURE CONNECTOR
The Video Feature connector allows a video peripheral such as a TV tuner card to provide video input to the graphics card. This interface is compliant with VESA VIP specification 1.1.
2 / Y1
26 / Y13
1 / Z1 25 / Z13
Figure F-4. Feature Connector (26-Pin Header)
Table F–4. Video In Connector Pinout
Pin
1 / Z1
3 / Z2
5 / Z3
7 / Z4
9 / Z5
11 / Z6
13 / Z7
15 / Z8
17 / Z9
19 / Z10
21 / Z11
23 / Z12
25 / Z13
Signal
GND
GND
GND
HAD1
HAD0
HCTL
SCL
GND
GND
GND
GND
VIRQ
SDA
Table F-4.
Video In Connector Pinout
Description Pin Signal
Ground
Ground
Ground
External Sync
External Clock
Serial Clock
Ground
Ground
Ground
Ground
Serial Data
2 / Y1
4 / Y2
6 / Y3
8 / Y4
10 / Y5
12 / Y6
14 / Y7
16 / Y8
18 / Y9
20 / Y10
22 / Y11
24 / Y12
26 / Y13
P0
P1
P2
P3
P4
P5
P6
P7
DCLK
NC
NC
--
GND
Pixel Data 0
Pixel Data 1
Pixel Data 2
Pixel Data 3
Pixel Data 4
Pixel Data 5
Pixel Data 6
Pixel Data 7
Pixel Data Clock
Not Connected
Not Connected
Key
Ground
F-6 Compaq Personal Computers
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Technical Reference Guide
Appendix G
COMPAQ/ADAPTEC 29160N SCSI HOST ADAPTER
G.
Appendix G Compaq/Adaptec SCSI Host Adapter
G.1
INTRODUCTION
The Compaq/Adaptec 29160N SCSI Host Adapter (Compaq SP# 158364-001) is a PCI peripheral that provides high performance interfacing with compatible SCSI peripherals, typically SCSI hard drives. The card installs in a PCI slot and supports full bus mastering capability.
This appendix covers the following subjects:
♦
Functional description (G.2)
♦
SCSI adapter programming (G.3)
♦
Specifications (G.4)
♦
SCSI connectors (G.5) page G-2 page G-3 page G-3 page G-4
Internal
Wide-Ultra SCSI Connector
Internal
Ultra SCSI Connector
External
Ultra
SCSI Connector AIC7892
Figure G–1. Compaq/Adaptec 29160N SCSI Host Adapter Card Layout (PCA# 157342-001)
Original - December 2000
Compaq Personal Computers G-1
Appendix K Compaq/Adaptec 29160N SCSI Host Adapter
G.2
FUNCTIONAL DESCRIPTION
A block diagram of the SCSI Adapter is shown in Figure L-2. The adapter’s architecture is based on the AIC-7892 SCSI controller working off the 32-bit, 66-/33-MHz PCI bus. Providing full bus mastering capability, the adapter supports data transfers up to 266 MB/s using the burst mode rate on a 66-MHz 32-bit PCI bus. The AIC-7892 controller is an Ultra160 controller with an on-board
20-MIPS SCSI sequencer that can process SCSI commands without intervention from the host microprocessor. The sequencer uses micro-code that is downloaded from the host during initialization. Single-ended SCSI drivers are built into the controller and a 1-K data FIFO and an internal 4-KB SRAM memory. An LED is provided to indicate SCSI bus activity.
The AIC7892 provides a memory interface that is used by the Serial EEPROM and the BIOS
ROM. The serial EEPROM stores non-volatile configuration data and the BIOS ROM (which is a flash ROM) contains additional configuration data and SCSI functions. The programmable array logic (PAL) controls the Serial EEPROM-to-AIC7892 interface.
PAL
Chip
SCSI
Activity
Serial
EEPROM
PCI
Slot
PCI Bus
BIOS
ROM
AIC7892
SCSI
Controller
40-MHz
Clock
Active Ultra160
SE Term.
AIC3860
Transceiver
Chip
Int. SCSI Connector (SE)
Ext. SCSI Connector (SE)
Int. SCSI Connector (SE/LVD)
Active Ultra160
SE/LVD Term.
Figure G–2. Compaq/Adaptec Ultra SCSI Adapter Card Block Diagram
The AIC7892 controller supports dual-mode low-voltage differential (LVD) SCSI I/O up to the
Ultra160 data rate of 160 Mbytes. Both single-ended (SE) and LVD devices can co-exist on the
SCSI bus, although operation will default to the SE mode. In SE mode, transfer rates are limited to the speed of the slower device. High-voltage differential (HVD) devices are supported for rates up to Ultra speeds.
The AIC7892 also supports cyclic redundancy check (CRC) codes, an improvement over parity checking used earlier.
G-2 Compaq Personal Computers
Original - December 2000
Technical Reference Guide
G.3
SCSI ADAPTER PROGRAMMING
G.3.1 SCSI ADAPTER CONFIGURATION
The Adaptec SCSI Host Adapter Card is a PCI device and configured using PCI protocol and PCI
Configuration Space registers (PCI addresses 00h-FFh) as discussed in Chapter 4 of this guide.
Configuration is accomplished by BIOS during POST and re-configurable with software. The vender ID and device ID for the adapter are as follows:
Vender ID (PCI config. addr. 00h): 9005h
Device ID (PCI config, addr. 02h): 0080h
G.3.2 SCSI ADAPTER CONTROL
Control of the SCSI host adapter is affected through I/O mapped registers mapped as listed in
Table G-1.
Table G–1. SCSI Host Adapter Card Control Register Mapping
I/O Addr. n00h-n1Fh n60h-n7Fh
Table G-1.
Ultra SCSI Host Adapter Card
Control Register Mapping
Function
SCSI Register Array
Phase Engine (Sequencer) n = prefix address supplied by the BASEADR0 PCI Config. Reg.
G.4
SPECIFICATIONS
The operating specifications are listed in Table G-2.
Table G–2. Ultra SCSI Host Adapter Card Specifications
Table G-2.
Ultra SCSI Host Adapter Card Specifications
Operating Voltage
Maximum Current Draw
Operating Temperature
+5 VDC
2 A
32
°
F (0
°
C) to 131
°
F (55
°
C)
Original - December 2000
Compaq Personal Computers G-3
Appendix K Compaq/Adaptec 29160N SCSI Host Adapter
G.5
SCSI CONNECTORS
This SCSI card provides two internal header-type connectors (one 50-pin, one 68-pin) and one external D-type connector (50-pin).
G.5.1 EXTERNAL 50-PIN ULTRA SCSI CONNECTOR
The card provides one external 50-pin D-type Ultra SCSI connector. External cabling should meet
T-10 SPI-2 standards (50-conductor, round shielded).
Pin 1
Figure G–3. External Ultra SCSI Connector (50-pin)
Table G–3. External 50-Pin Ultra SCSI Connector Pinout
Table G-3.
External Ultra SCSI Connector Pinout
3
4
GND Ground
GND Ground
28 2
29 3
23 GND Ground
G-4 Compaq Personal Computers
48 C-/D Control/Data Transfer Indicator
Original - December 2000
Technical Reference Guide
G.5.2 INTERNAL 50-PIN ULTRA SCSI CONNECTOR
The card provides one internal 50-pin header-type Ultra SCSI connector. Internal cabling to this connector should consists of an unshielded connector with a 50-conductor flat cable as specified in
ANSI standard X3T9.2/375R.
Pin 49
Pin 1
Pin 50 Pin 2
Figure G–4. Internal 50-Pin Ultra SCSI Connector
Table G–4. Internal 50-Pin Ultra SCSI Connector Pinout
Table G-4.
Internal 50-Pin Ultra SCSI Connector Pinout
Control/Data Indicator
Original - December 2000
Compaq Personal Computers G-5
Appendix K Compaq/Adaptec 29160N SCSI Host Adapter
G.5.3 INTERNAL 68-PIN ULTRA160 SCSI CONNECTOR
The card provides one internal 68-pin Ultra160 SCSI connector. This connection is designed for a
68-conductor unshielded Twist ‘N Flat cable as specified in the T-10 SPI-2 standard.
Pin 34 Pin 1
Pin 35 Pin 68
Figure G–5. Ultra 160 SCSI Connector (68-pin header type)
Table G–5. Ultra160 SCSI Connector Pinout
Table G-5.
Ultra160 SCSI Connector Pinout
3
4
GND Ground
GND Ground
G-6 Compaq Personal Computers
Original - December 2000
INDEX
I.
3D effects, D-2, E-2, F-2 abbreviations, 1-4
AC97 link bus, 5-28
Accelerated Graphics Port (AGP), 4-10
ACPI, 5-34 acronyms, 1-4
AGP, 4-10
Alert-On-LAN, 5-33
AOL, 5-33
AOL requirements, 5-33, 5-38
APIC, 4-16
APM, 5-34
APM BIOS support, 8-19 arbitration, PCI bus master, 4-6
ASCII character set, B-1 audio, 5-26 audio controller (AC97), 5-28 audio subsystem, 2-19 backplane, 2-7 battery replacement, 4-23
BIOS, ROM, 8-1 blinking LED, 7-3 boot block ROM, 8-2 cable lock, 4-34
CAS latency, 3-5
Celeron processor, 2-14, 2-15, 3-2 chassis fan, 4-37 chipsets, 2-16
Client Management, 8-12
CMOS, 4-23
CMOS, archive, 4-24
CMOS, clearing, 4-23
CMOS, restoring, 4-24 codec, audio, 5-29
Configuration Cycle, 4-4 configuration cycle (PCI), 4-4 configuration memory, 4-23 configuration space (PCI), 4-5
Connector
AGP bus, 4-14
Audio, CD, 5-27 audio, headphones out, 5-26 audio, line in, 5-26 audio, line out, 5-26
Audio, Mic In, 5-26
Audio, Speaker, 5-27 diskette drive interface, 5-7 display (VGA monitor), 6-8, D-5, E-5, F-5
IDE interface, 5-3
IDE/diskette drive power, 7-5 keyboard/pointing device interface, 5-21
Network RJ-45, 5-36 parallel interface, 5-15
PCI bus, 4-9 serial interface (RS-232), 5-8, 5-9
Ultra SCSI (50-pin D-type), G-4
Ultra SCSI (50-pin header type), G-5
Universal Serial Bus interface, 5-25
VGA pass-through (feature), F-6
Wide Ultra SCSI (68-pin header type), G-6 cooling, 4-36 core voltage, 3-2, 3-3, 7-7
DIMM, 3-5
DIMM detection, 8-5
DIMM support , 8-15 diskette drive interface, 5-4 display modes, 815E-based, 6-4 display modes, Matrox Millennium G450, F-3 display modes, NVIDIA graphics, 6-7 display modes, NVIDIA Quadro2 EX/MXR, E-3 display modes, NVIDIA TNT2 Pro, D-3
DMA, 4-19
DMI, 8-16 drive fault prediction, 8-15 dual-head support, F-2
East Access keys, C-10
Easy Access keyboards, C-7 effects, 3D, D-2, E-2, F-2
EIDE interface, 5-1
Enhanced Parallel Port (EPP), 5-12 events, wake up, 7-4 expansion card cage, 2-7
Extended Capabilities Port (ECP), 5-12 fan boxed processor, 4-37 chassis, 4-37 power supply, 4-37
FC-PGA370 (package), 3-4 feature connector, F-6 features, standard, 2-2 flash ROM, 8-2 flip-chip package, 3-4 general purpose I/O, 4-39
GPIO, 3-2, 3-3, 4-39
I/O controller, 4-41 graphics card, Matrox Millennium G450, F-1
graphics card, NVIDIA Quadro2 EX/MXR, E-1 graphics card, NVIDIA TNT Pro, D-1 graphics subsystem, 2-18, 6-1 graphics, 3D, D-2, E-2, F-2 graphics, 815E-based, 6-2 graphics, NVIDIA, 6-6
Hard drive activity indicator, 4-42 headphones, 5-26 heat sink (processor), 2-15
Hub link bus, 4-7
I/O controller (LPC47B34x), 4-40
I/O map, 4-38
IDE interface, 5-1
IDSEL, 4-4 index addressing, 1-3 interface audio, 2-19, 5-26 diskette drive, 5-4
IDE, 5-1 keyboard/pointing device, 5-16 parallel, 2-17, 5-11 serial, 2-17, 5-8
USB, 2-17, 5-22 interrupts maskable (IRQn), 4-15 nonmaskable (NMI, SMI), 4-17 interrupts, PCI, 4-7 key (keyboard) functions, C-8 keyboard, C-1 keyboard (micro)processor, C-2 keyboard layouts, C-5 keyboard, USB, C-4 keyboards, Easy Access, C-7 keys, Easy Access, C-10 keys, Windows, C-9
LED, 5-32
LED indications, 4-35, 7-3
LED, HD, 4-42
LED, Power, 4-42 low voltages, 7-7
LPC bus, 4-7
LPC47B34x I/O controller, 4-40
Magic Packet, 5-34 mass storage, 2-17 memory detection, 8-5 memory management (graphics), 6-4 memory map, 3-7 memory, system, 3-5 memory, system (RAM), 2-17 microphone, 5-26
MMX, 3-2 monitor power control, 6-8, D-4, E-4, F-4 mouse interface, 5-18 network interface controller, 5-32 network support, 5-32
NIC, 5-32
NIC upgrading, 5-37 notational conventions, 1-2, 1-3
NUM lock, 3-5 option ROM, 4-7 options, 2-3 parallel interface, 2-17, 5-11 password, clearing, 4-23 password, power-on, 4-33
PCI bus, 2-17, 4-2
PCI Configuration Space, 4-5
PCI interrupts, 4-7
Pentium II, 2-16
Pentium II processor, 2-14
Pentium III processor, 3-3
PHY, 5-32 pinouts, header (connector), 7-10
Plug ’n Play, 2-2, 2-17, 8-15
Plug 'n Play BIOS function, 8-15 power button, 7-3
Power Button Override, 4-24 power consumption, graphics card, D-4 power distribution, 7-5
Power indicator, 4-42 power management
ACPI, 4-35 network interface controller (NIC), 5-34
PCI, 4-7 power management BIOS function, 8-17 power supply, 7-1 power supply assembly, 7-2 power-on password, 4-33
PPGA370, 3-2 processor
Celeron, 2-15, 3-2
Pentium III, 2-15, 3-3 processor upgrading, 3-4 processor, Celeron, 2-14, 3-2 processor, Pentium II, 2-14 programming 815E-based graphics, 6-5 programming NVIDIA graphics, 6-7
RAM, 2-17 reference sources, 1-2 remote flashing, 8-2 remote wake up, 5-34 restoring CMOS, 4-24
ROM BIOS, 8-1
ROM flashing, 8-2
ROM, option, 4-7
RS-232, 5-8, 5-9
RTC, 4-23 scan codes (keyboard), C-11
SCSI Host card, Adaptec 29160N, G-1
SDRAM, 3-5, F-2 security functions, 4-33 security, chassis, 4-34 security, interface, 4-34
sensor, thermal, 4-36 serial interface, 2-17, 5-8
SGRAM, D-2, E-2 sideband addressing, 4-11 signal distribution, 7-8, 7-10
SIMD, 3-2, 3-3
Smart Cover Lock, 4-34
Smart Cover Sensor, 4-34
SMBIOS, 8-16
SMI, 4-18 speaker, 5-26 specifications electrical , 2-19 environmental , 2-19 physical, 2-20 power supply, 7-8, 7-9, 7-10
Specifications
8x CD-ROM Drive, 2-21
Audio subsystem, 5-31
Diskette Drive, 2-20
Hard Drive, 2-22
SCSI Host Adapter, G-3 specifications, system, 2-19
SSE, 3-3 status, LED, 4-35 system board, 2-10, 2-11 system ID, 8-6, 8-14 system memory, 2-17, 3-5 system resources, 4-15 system ROM, 8-1 system status indications, 4-35
TAFI, 4-37 temperature status, 8-14 thermal sensing, 4-36 typematic, C-8
UART, 5-8
Universal Serial Bus (USB) interface, 5-22 upgrading 815E-based graphics, 6-5 upgrading NVIDIA graphics, 6-7 upgrading, BIOS, 8-2 upgrading, NIC, 5-37 upgrading, processor, 3-4
USB interface, 5-22
USB keyboard, C-4
USB legacy support, 8-23
USB ports, 2-17
VESA connector, F-6 voltage, core, 3-2, 3-3, 7-7 wake up (power), 7-4 wake up events, 7-4 wake up, remote, 5-34
Wake-On-LAN, 5-33, 7-4
Windows keys, C-9
WOL, 5-33, 7-4
ZIF socket, 2-15
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