IBM PD78083 Network Card User manual
Oglas
Oglas
©
µ
PD78083 SUBSERIES
8-BIT SINGLE-CHIP MICROCONTROLLER
µ
PD78081
µ
PD78081(A)
µ
PD78082
µ
PD78082(A)
µ
PD78P083
µ
PD78P083(A)
µ
PD78P081(A2)
Document No. U12176EJ2V0UM00 (2nd edition)
(O. D. No. IEU-886)
Date Published May 1997 N
Printed in Japan
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Sun OS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of XEROX Corporation.
NEWS and NEWS-OS are trademarks of SONY Corporation.
OSF/Motif is a trademark of Open Software Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
License not needed:
µ
PD78P083DU
The customer must judge the need for license:
µ
PD78081CU-
×××
, 78081GB-
×××
-3B4, 78081GB-
×××
-3BS-MTX
µ
PD78081GB(A)-
×××
-3B4, 78081GB(A2)-
×××
-3B4
µ
PD78082CU-
×××
, 78082GB-
×××
-3B4, 78082GB-
×××
-3BS-MTX
µ
PD78082GB(A)-
×××
-3B4
µ
PD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX
µ
PD78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
Major Revision in This Edition
Page Description
Throughout The following products have been already developed
µ
PD78081CU-
×××
, 78081GB-
×××
-3B4, 78082CU-
×××
, 78082GB-
×××
-3B4, 78P083CU, 78P083DU,
78P083GB-3B4 p. 9 p. 13 p. 19 p. 72
The following products have been added
µ
PD78081GB-
×××
-3BS-MTX, 78082GB-
×××
-3BS-MTX, 78P083GB-3BS-MTX, 78081GB(A)-
×××
-3B4,
78082GB(A)-
×××
-3B4, 78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX, 78081GB(A2)-
×××
-3B4
Changes supply voltage to V
DD
= 1.8 to 5.5V.
1.6 78K/0 Series Development has been changed.
1.9 Differences between the
µ
PD78081, 78082, and 78P083, the
µ
PD78081(A), 78082(A), and
78P083(A), and the
µ
PD78081(A2) has been added.
Cautions regarding the use of functions in common with 2.2.5 (2) (d) ASCK has been added.
Cautions concerning the Write to OSMS Command has been added to 5.3 (2) Oscillation mode select register (OSMS).
p. 73 p. 108 p. 110 p. 113
Cautions concerning external clock input in 5.4.1 Main system clock oscillator has been changed.
Figure 7-3. Watchdog Timer Mode Register Format, notes and cautions have been added.
Description of 7.4.2 Interval timer operation has been changed.
Cautions with regard to rewriting TCL0 to other than same data has been added to 8.3 (1) Timer clock
select register 0 (TCL0).
p. 120 The HSC bit has been added to the A/D Converter Mode
Register in Figure10-1. A/D Converter Block Diagram. p. 122, 193 10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby function, and Cautions have been added.
p. 137 Figure 11-1. Serial Interface Channel 2 Block Diagram has been corrected.
p. 146, 155 11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/receive clock by means of main system
clock have been added.
76800 bps has been added to baud rate generated from the main system clock.
p. 161 p. 165 p. 168 p. 206 p. 205 p. 214 p. 232 p. 231
Figure 11-10. Receive Error Timing has been corrected.
11.4.3 (1) (c) Baud rate generator control register (BRGC) has been added.
11.4.3 (3) MSB/LSB switching as start bit has been added.
15.1 Memory Size Switching Register has been changed from W to R/W.
Items and cautions have been added to Table 15-1. Differences between the
µ
PD78P083 and Mask ROM
Versions.
A description of the QTOP microcontroller has been added to 15.5 Screening of One-Time PROM
Versions.
Figure A-1. Development Tool Configuration has been changed.
p. 239 p. 240 p. 244 p. 249
APPENDIX A DEVELOPMENT TOOLS
The following Development Tools have been added:
IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0
A.4 OS for IBM PC has been added.
Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added.
B.1 Real-time OS has been added.
APPENDIX D REVISION HISTORY has been added.
The mark shows major revised points.
PREFACE
Readers
Purpose
Organization
This manual has been prepared for user engineers who want to understand the functions of the
µ
PD78083 subseries and design and develop its application systems and programs.
Caution In the
µ
PD78083 Subseries, the
µ
PD78P083DU is not designed to maintain the reliability required for use in customers’ mass-produced equipment.
Please use this device only for experimentation or for evaluation of functions.
This manual is intended for users to understand the functions described in the
Organization below.
The
µ
PD78083 subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 Series).
µ
PD78083 Subseries
User’s Manual
(This Manual)
Pin functions
Internal block functions
Interrupt
Other on-chip peripheral functions
78K/0 Series
User’s Manual
Instruction
CPU functions
Instruction set
Explanation of each instruction
How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers.
For those who will be using this as a manual for the
µ
PD78081(A), 78082(A),
78P083(A) and 78081(A2):
→
The
µ
PD78081, 78082, 78P083 are explained as being representative devices.
In case this is used as a manual for the
µ
PD78081(A), 78082(A), 78P083(A), or 78081(A2), please reread the product names as follows.
µ
PD78081
→ µ
PD78081(A) or
µ
PD78081(A2)
µ
PD78082
→ µ
PD78082(A)
µ
PD78P083
→ µ
PD78P083(A)
When you want to understand the functions in general:
→
Read this manual in the order of the contents.
To know the
µ
PD78083 Subseries instruction function in detail:
→
Refer to the 78K/0 Series User's Manual: Instructions (IEU-1372)
How to interpret the register format:
→
For the circled bit number, the bit name is defined as a reserved word in
RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.
To learn the function of a register whose register name is known:
→
Refer to Appendix C Register Index.
To know the electrical specifications of the
µ
PD78083 Subseries:
→
Refer to separately available Data Sheet.
Legend
To know application examples of the functions provided in the
µ
PD78083 Subseries:
→
Refer to Application Note separately provided.
Data representation weight : High digits on the left and low digits on the right
Active low representations :
×××
(line over the pin and signal names)
Note : Description of note in the text.
Caution
Remarks
Numeral representations
: Information requiring particular attention
: Additional explanatory material
: Binary ...
××××
or
××××
B
Decimal ...
××××
Hexadecimal ...
××××
H
Examples of use in this manual are prepared for “Standard” quality level devices for general electronic equipment. In the case of examples of use in this manual for devices which meet “Special” quality level requirements, please use each device only after studying each part that is actuall to be used, the circuitry and the quality level of each component before use.
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
Related documents for
µ
PD78054 subseries
Document name
µ
PD78083 Subseries User’s Manual
µ
PD78081, 78082 Data Sheet
µ
PD78P083 Data Sheet
µ
PD78081(A), 78082(A), 78081(A2) Data Sheet
µ
PD78P083(A) Data Sheet
µ
PD78083 Subseries Special Function Register Table
78K/0 Series User’s Manual—Instruction
78K/0 Series Instruction Table
78K/0 Series Instruction Set
78K/0 Series Application Note Basics (III)
Document No.
Japanese English
U12176J
U11415J
This Manual
U11415E
U11006J U11006E
In preparation To be prepared
U12175J
IEM-5599
U12175E
—
IEU-849
U10903J
U10904J
IEA-767
IEU-1372
—
—
U10182E
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design.
Development Tool Documents (User’s Manuals)
RA78K Series Assembler Package
RA78K Series Structured Assembler Preprocessor
RA78K0 Assembler Package
CC78K Series C Compiler
CC78K/0 C Compiler
ID78K0 Integrated Debugger EWS Base
ID78K0 Integrated Debugger PC Base
ID78K0 Integrated Debugger Windows™ Base
SD78K/0 Screen Debugger
PC-9800 Series (MS-DOS) Base
SD78K/0 Screen Debugger
IBM PC/AT™ (PC DOS) Base
Document name
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
PG-1500 PROM Programmer
PG-1500 Controller PC-9800 Series (MS-DOS™) Base
PG-1500 Controller IBM PC Series (PC DOS™) Base
IE-78000-R
IE-78000-R-A
IE-78000-R-BK
IE-78078-R-EM
EP-78083
SM78K0 System Simulator Windows™ Base
SM78K Series System Simulator
Operation
Language
Document No.
Japanese English
EEU-809
EEU-815
EEU-817
Structured assembly language U11789J
EEU-1399
EEU-1404
EEU-1402
U11789E
Assembly language
Operation
Operation
Language
U11801J
U11802J
EEU-656
EEU-655
U11801E
U11802E
EEU-1280
EEU-1284
Operation
Language
Programming know-how
U11517J
U11518J
EEA-618
EEU-777
U11940J
EEU-704
EEU-5008
EEU-810
U11517E
U11518E
EEA-1208
—
EEU-1335
EEU-1291
U10540E
U11376E
U10057J
EEU-867
U10775J
EEU-5003
U10181J
U10092J
U10057E
EEU-1427
U10775E
EEU-1529
U10181E
U10092E
Reference
External component user open interface specifications
Reference
Reference
Guide
Introduction
Reference
Introduction
Reference
U11151J
U11539J
U11649J
EEU-852
U10952J
EEU-5024
U11279J
—
—
U11649E
U10539E
—
EEU-1414
U11279E
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design.
Documents for Embedded Software (User’s Manual)
78K/0 Series Real-Time OS
Document name
Basics
Installation
Document No.
Japanese English
U11537J
U11536J
OS for 78K/0 Series MX78K0
Fuzzy Knowledge Data Creation Tool
Technicals
Basics
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System—Translator
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module
U11538J
EEU-5010
EEU-829
EEU-862
EEU-858
78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Debugger EEU-921
—
—
—
—
EEU-1438
EEU-1444
EEU-1441
EEU-1458
Other Documents
Document name
IC PACKAGE MANUAL
Semiconductor Device Mounting Technology Manual
Quality Grade on NEC Semiconductor Devices
Reliability Quality Control on NEC Semiconductor Devices
Electric Static Discharge (ESD) Test
Semiconductor Devices Quality Assurance Guide
Microcontroller Related Product Guide—Third Party Manufacturers
Document No.
Japanese English
C10943X
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
C10535E
C11531E
C10983E
—
C11893E
—
Caution: The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design.
CONTENTS
CHAPTER 1 OUTLINE .....................................................................................................................
1.1
Features .............................................................................................................................
1.2
Applications ......................................................................................................................
1.3
Ordering Information ........................................................................................................
1.4
Quality Grade ....................................................................................................................
1.5
Pin Configuration (Top View) ...........................................................................................
1.6
78K/0 Series Development ...............................................................................................
1.7
Block Diagram ...................................................................................................................
1.8
Outline of Function ...........................................................................................................
1.9
Differences between the
µ
PD78081, 78082 and 78P083, the
µ
PD78081(A), 78082(A) and 78P083(A), and the
µ
PD78081(A2) ...........................................................................
CHAPTER 2 PIN FUNCTION ...........................................................................................................
2.1
Pin Function List ...............................................................................................................
2.1.1
Normal operating mode pins ...............................................................................................
2.1.2
PROM programming mode pins (
µ
PD78P083 only) ............................................................
2.2
Description of Pin Functions ...........................................................................................
2.2.1
P00 to P03 (Port 0) ..............................................................................................................
2.2.2
P10 to P17 (Port 1) ..............................................................................................................
2.2.3
P30 to P37 (Port 3) ..............................................................................................................
2.2.4
P50 to P57 (Port 5) ..............................................................................................................
2.2.5
P70 to P72 (Port 7) ..............................................................................................................
2.2.6
P100 to P101 (Port 10) ........................................................................................................
2.2.7
AV
REF
..................................................................................................................................
2.2.8
AV
DD
....................................................................................................................................
2.2.9
AV
SS
....................................................................................................................................
2.2.10
RESET .................................................................................................................................
2.2.11
X1 and X2 ............................................................................................................................
2.2.12
V
DD
......................................................................................................................................
2.2.13
V
SS
......................................................................................................................................
2.2.14
V
PP
(
µ
PD78P083 only) .........................................................................................................
2.2.15
IC (Mask ROM version only) ................................................................................................
2.2.16
NC (44-pin plastic QFP versions only) .................................................................................
2.3
Pin Input/Output Circuits and Recommended Connection of Unused Pins ...............
CHAPTER 3 CPU ARCHITECTURE ................................................................................................
3.1
Memory Spaces.................................................................................................................
3.1.1
Internal program memory space ..........................................................................................
3.1.2
Internal data memory space ................................................................................................
3.1.3
Special Function Register (SFR) area .................................................................................
3.1.4
Data memory addressing ....................................................................................................
3.2
Processor Registers .........................................................................................................
3.2.1
Control registers ..................................................................................................................
3.2.2
General registers .................................................................................................................
20
20
20
20
20
21
19
20
20
20
17
18
18
19
21
22
15
15
15
16
17
17
25
25
28
29
29
29
33
33
36
9
11
3
4
12
2
2
1
1
13
– i –
3.2.3
Special Function Register (SFR) .........................................................................................
3.3
Instruction Address Addressing .....................................................................................
3.3.1
Relative Addressing .............................................................................................................
3.3.2
Immediate addressing .........................................................................................................
3.3.3
Table indirect addressing .....................................................................................................
3.3.4
Register addressing .............................................................................................................
3.4
Operand Address Addressing .........................................................................................
3.4.1
Implied addressing ..............................................................................................................
3.4.2
Register addressing .............................................................................................................
3.4.3
Direct addressing .................................................................................................................
3.4.4
Short direct addressing ........................................................................................................
3.4.5
Special-Function Register (SFR) addressing ......................................................................
3.4.6
Register indirect addressing ................................................................................................
3.4.7
Based addressing ................................................................................................................
3.4.8
Based indexed addressing ..................................................................................................
3.4.9
Stack addressing .................................................................................................................
CHAPTER 4 PORT FUNCTIONS ....................................................................................................
4.1
Port Functions ...................................................................................................................
4.2
Port Configuration ............................................................................................................
4.2.1
Port 0 ...................................................................................................................................
4.2.2
Port 1 ...................................................................................................................................
4.2.3
Port 3 ...................................................................................................................................
4.2.4
Port 5 ...................................................................................................................................
4.2.5
Port 7 ...................................................................................................................................
4.2.6
Port 10 .................................................................................................................................
4.3
Port Function Control Registers .....................................................................................
4.4
Port Function Operations .................................................................................................
4.4.1
Writing to input/output port ...................................................................................................
4.4.2
Reading from input/output port ............................................................................................
4.4.3
Operations on input/output port ...........................................................................................
CHAPTER 5 CLOCK GENERATOR ................................................................................................
5.1
Clock Generator Functions ..............................................................................................
5.2
Clock Generator Configuration .......................................................................................
5.3
Clock Generator Control Register ...................................................................................
5.4
System Clock Oscillator ...................................................................................................
5.4.1
Main system clock oscillator ................................................................................................
5.4.2
Scaler ...................................................................................................................................
5.5
Clock Generator Operations ............................................................................................
5.6
Changing CPU Clock Settings .........................................................................................
5.6.1
Time required for CPU clock switchover ..............................................................................
5.6.2
CPU clock switching procedure ...........................................................................................
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 ..............................................................
6.1
8-Bit Timer/Event Counters 5 and 6 Functions ..............................................................
6.2
8-Bit Timer/Event Counters 5 and 6 Configurations ......................................................
6.3
8-Bit Timer/Event Counters 5 and 6 Control Registers .................................................
57
58
59
60
53
53
55
55
62
63
67
67
67
67
37
40
40
41
42
43
44
44
50
51
52
52
45
46
47
49
75
76
77
77
78
69
69
69
71
73
73
79
80
82
84
– ii –
6.4
8-Bit Timer/Event Counters 5 and 6 Operations ............................................................
6.4.1
Interval timer operations ......................................................................................................
6.4.2
External event counter operation .........................................................................................
6.4.3
Square-wave output ............................................................................................................
90
90
93
94
6.4.4
PWM output operations .......................................................................................................
96
6.5
Cautions on 8-Bit Timer/Event Counters 5 and 6 ..........................................................
100
CHAPTER 7 WATCHDOG TIMER ...................................................................................................
103
7.1
Watchdog Timer Functions ..............................................................................................
103
7.2
Watchdog Timer Configuration .......................................................................................
105
7.3
Watchdog Timer Control Registers .................................................................................
106
7.4
Watchdog Timer Operations ............................................................................................
109
7.4.1
Watchdog timer operation ....................................................................................................
109
7.4.2
Interval timer operation ........................................................................................................
110
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT .....................................................................
111
8.1
Clock Output Control Circuit Functions .........................................................................
111
8.2
Clock Output Control Circuit Configuration ...................................................................
112
8.3
Clock Output Function Control Registers ......................................................................
113
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................
115
9.1
Buzzer Output Control Circuit Functions .......................................................................
115
9.2
Buzzer Output Control Circuit Configuration .................................................................
115
9.3
Buzzer Output Function Control Registers ....................................................................
116
CHAPTER 10 A/D CONVERTER .......................................................................................................
119
10.1 A/D Converter Functions ..................................................................................................
119
10.2 A/D Converter Configuration ...........................................................................................
119
10.3 A/D Converter Control Registers .....................................................................................
122
10.4 A/D Converter Operations ................................................................................................
126
10.4.1
Basic operations of A/D converter .......................................................................................
126
10.4.2
Input voltage and conversion results ...................................................................................
128
10.4.3
A/D converter operating mode .............................................................................................
129
10.5 A/D Converter Cautions ...................................................................................................
131
CHAPTER 11 SERIAL INTERFACE CHANNEL 2 ............................................................................
135
11.1 Serial Interface Channel 2 Functions ..............................................................................
135
11.2 Serial Interface Channel 2 Configuration .......................................................................
136
11.3 Serial Interface Channel 2 Control Registers .................................................................
140
11.4 Serial Interface Channel 2 Operation ..............................................................................
148
11.4.1
Operation stop mode ...........................................................................................................
148
11.4.2
Asynchronous serial interface (UART) mode ......................................................................
11.4.3
3-wire serial I/O mode .........................................................................................................
150
163
CHAPTER 12 INTERRUPT FUNCTION ............................................................................................
171
12.1 Interrupt Function Types ..................................................................................................
171
12.2 Interrupt Sources and Configuration ..............................................................................
172
12.3 Interrupt Function Control Registers ..............................................................................
175
– iii –
12.4 Interrupt Servicing Operations ........................................................................................
181
12.4.1
Non-maskable interrupt request acknowledge operation ....................................................
181
12.4.2
Maskable interrupt request acknowledge operation ............................................................
12.4.3
Software interrupt request acknowledge operation .............................................................
12.4.4
Multiple interrupt servicing ...................................................................................................
12.4.5
Interrupt request reserve .....................................................................................................
184
187
187
191
CHAPTER 13 STANDBY FUNCTION ................................................................................................
193
13.1 Standby Function and Configuration ..............................................................................
193
13.1.1
Standby function ..................................................................................................................
193
13.1.2
Standby function control register .........................................................................................
194
13.2 Standby Function Operations ..........................................................................................
195
13.2.1
HALT mode ..........................................................................................................................
195
13.2.2
STOP mode .........................................................................................................................
198
CHAPTER 14 RESET FUNCTION .....................................................................................................
201
14.1 Reset Function ..................................................................................................................
201
CHAPTER 15
µ
PD78P083 .................................................................................................................
205
15.1 Memory Size Switching Register .....................................................................................
206
15.2 PROM Programming .........................................................................................................
207
15.2.1
Operating modes .................................................................................................................
207
15.2.2
PROM write procedure ........................................................................................................
209
15.2.3
PROM reading procedure ....................................................................................................
213
15.3 Erasure Procedure (
µ
PD78P083DU Only) .......................................................................
214
15.4 Opaque Film Masking the Window (
µ
PD78P083DU Only).............................................
214
15.5 Screening of One-Time PROM Versions .........................................................................
214
CHAPTER 16 INSTRUCTION SET ....................................................................................................
215
16.1 Legends Used in Operation List ......................................................................................
216
16.1.1
Operand identifiers and description methods ......................................................................
216
16.1.2
Description of “operation” column ........................................................................................
217
16.1.3
Description of “flag operation” column .................................................................................
217
16.2 Operation List ....................................................................................................................
218
16.3 Instructions Listed by Addressing Type .........................................................................
226
APPENDIX A DEVELOPMENT TOOLS ............................................................................................
231
A.1
Language Processing Software ......................................................................................
233
A.2
PROM Programming Tools ..............................................................................................
234
A.2.1
Hardware .............................................................................................................................
234
A.2.2
Software ...............................................................................................................................
234
A.3
Debugging Tools ...............................................................................................................
235
A.3.1
Hardware .............................................................................................................................
235
A.3.2
Software (1/3) ......................................................................................................................
A.3.2
Software (2/3) ......................................................................................................................
236
237
A.3.2
Software (3/3) ......................................................................................................................
238
A.4
OS for IBM PC ...................................................................................................................
239
– iv –
A.5
System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series
In-Circuit Emulator ............................................................................................................
240
APPENDIX B EMBEDDED SOFTWARE ..........................................................................................
243
B.1
Real-time OS ......................................................................................................................
244
B.2
Fuzzy Inference Development Support System .............................................................
245
APPENDIX C REGISTER INDEX ......................................................................................................
247
C.1 Register Index .....................................................................................................................
247
APPENDIX D REVISION HISTORY ..................................................................................................
249
– v –
Fig. No.
2-1
4-5
4-6
4-7
4-8
4-1
4-2
4-3
4-4
4-9
4-10
4-11
3-5
3-6
3-7
3-8
3-1
3-2
3-3
3-4
3-9
3-10
3-11
3-12
6-5
6-6
6-7
6-8
6-9
6-1
6-2
6-3
6-4
5-1
5-2
5-3
5-4
5-5
5-6
5-7
FIGURE (1/4)
Title
Pin Input/Output Circuit of List ............................................................................................
Page
23
Memory Map (
µ
PD78081) ..................................................................................................
Memory Map (
µ
PD78082) ..................................................................................................
Memory Map (
µ
PD78P083) ................................................................................................
Data Memory Addressing (
µ
PD78081) ...............................................................................
Data Memory Addressing (
µ
PD78082) ...............................................................................
Data Memory Addressing (
µ
PD78P083) ............................................................................
Program Counter Configuration .........................................................................................
Program Status Word Configuration ...................................................................................
Stack Pointer Configuration ................................................................................................
Data to be Saved to Stack Memory ....................................................................................
Data to be Reset from Stack Memory ................................................................................
General Register Configuration ..........................................................................................
31
32
33
33
25
26
27
30
35
35
35
36
Port Types ..........................................................................................................................
P00 Block Diagram .............................................................................................................
P01 to P03 Block Diagram .................................................................................................
P10 to P17 Block Diagram .................................................................................................
P30 to P37 Block Diagram .................................................................................................
P50 to P57 Block Diagram .................................................................................................
P70 Block Diagram .............................................................................................................
P71 and P72 Block Diagram ..............................................................................................
P100 to P101 Block Diagram .............................................................................................
Port Mode Register Format ................................................................................................
Pull-Up Resistor Option Register Format ...........................................................................
58
59
60
61
53
56
56
57
62
65
66
Block Diagram of Clock Generator .....................................................................................
Processor Clock Control Register Format ..........................................................................
Oscillation Mode Selection Register Format ......................................................................
Main System Clock Waveform due to Writing to OSMS .....................................................
External Circuit of Main System Clock Oscillator ...............................................................
Examples of Oscillator with Bad Connection (1/2) .............................................................
CPU Clock Switching .........................................................................................................
8-Bit Timer/Event Counters 5 and 6 Block Diagram ...........................................................
Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ...................
Timer Clock Select Register 5 Format ................................................................................
Timer Clock Select Register 6 Format ................................................................................
8-Bit Timer Mode Control Register 5 Format ......................................................................
8-Bit Timer Mode Control Register 6 Format ......................................................................
Port Mode Register 10 Format ...........................................................................................
8-Bit Timer Mode Control Register Settings for Interval Timer Operation ..........................
Interval Timer Operation Timings .......................................................................................
73
74
78
70
71
72
87
88
89
90
91
82
83
85
86
– vi –
7-1
7-2
7-3
8-1
8-2
8-3
8-4
Fig. No.
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
6-19
6-20
9-1
9-2
9-3
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
11-1
11-2
11-3
11-4
11-5
11-6
FIGURE (2/4)
Title
8-Bit Timer Mode Control Register Setting for External Event Counter Operation .............
External Event Counter Operation Timings (with Rising Edge Specification) ....................
8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..............
8-Bit Timer Mode Control Register Settings for PWM Output Operation ...........................
PWM Output Operation Timing (Active high setting) ..........................................................
PWM Output Operation Timings (CRn0 = 00H, active high setting) ...................................
PWM Output Operation Timings (CRn0 = FFH, active high setting) ..................................
PWM Output Operation Timings (CRn0 changing, active high setting) ..............................
8-Bit Timer Registers 5 and 6 Start Timing .........................................................................
External Event Counter Operation Timing ..........................................................................
Timing after Compare Register Change during Timer Count Operation ............................
Page
100
100
101
97
97
98
99
93
93
94
96
Watchdog Timer Block Diagram .........................................................................................
Timer Clock Select Register 2 Format ................................................................................
Watchdog Timer Mode Register Format .............................................................................
105
107
108
Remote Controlled Output Application Example ................................................................
Clock Output Control Circuit Block Diagram .......................................................................
Timer Clock Select Register 0 Format ................................................................................
Port Mode Register 3 Format .............................................................................................
111
112
113
114
Buzzer Output Control Circuit Block Diagram ....................................................................
Timer Clock Select Register 2 Format ................................................................................
Port Mode Register 3 Format .............................................................................................
115
117
118
A/D Converter Block Diagram ............................................................................................
A/D Converter Mode Register Format ................................................................................
A/D Converter Input Select Register Format ......................................................................
External Interrupt Mode Register 1 Format ........................................................................
A/D Converter Basic Operation ..........................................................................................
Relations between Analog Input Voltage and A/D Conversion Result ................................
A/D Conversion by Hardware Start ....................................................................................
A/D Conversion by Software Start ......................................................................................
Example of Method of Reducing Current Dissipation in Standby Mode .............................
Analog Input Pin Disposition ..............................................................................................
A/D Conversion End Interrupt Request Generation ...........................................................
Handling of AVDD Pin .........................................................................................................
120
123
124
125
127
128
129
130
131
132
133
Serial Interface Channel 2 Block Diagram .........................................................................
Baud Rate Generator Block Diagram .................................................................................
Serial Operating Mode Register 2 Format ..........................................................................
Asynchronous Serial Interface Mode Register Format .......................................................
Asynchronous Serial Interface Status Register Format .....................................................
Baud Rate Generator Control Register Format (1/2) .........................................................
137
138
140
141
143
144
– vii –
Fig. No.
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-14
12-15
12-1
12-1
12-2
12-3
12-4
12-5
12-6
12-7
13-1
13-2
13-3
13-4
13-5
14-1
14-2
14-3
14-4
15-1
15-2
15-3
15-4
15-5
FIGURE (3/4)
Title
Baud Rate Generator Control Register Format (2/2) .........................................................
Asynchronous Serial Interface Transmit/Receive Data Format ..........................................
Asynchronous Serial Interface Transmission Completion Interrupt Request Timing ..........
Asynchronous Serial Interface Reception Completion Interrupt Request Timing ...............
Receive Error Timing ..........................................................................................................
State of the Receive Buffer Register (RXB) when Reception is Interrupted, and
Generation/Non Generation of an Interrupt Request (INTSR) ...........................................
3-Wire serial I/O Mode Timing ............................................................................................
Circuit of Switching in Transfer Bit Order ...........................................................................
Page
145
157
159
160
161
162
168
169
Basic Configuration of Interrupt Function (1/2) ...................................................................
Basic Configuration of Interrupt Function (2/2) ...................................................................
Interrupt Request Flag Register Format .............................................................................
Interrupt Mask Flag Register Format ..................................................................................
Priority Specify Flag Register Format .................................................................................
External Interrupt Mode Register 0 Format ........................................................................
External Interrupt Mode Register 1 Format ........................................................................
Program Status Word Configuration ...................................................................................
Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment ............
Non-Maskable Interrupt Request Acknowledge Timing ......................................................
Non-Maskable Interrupt Request Acknowledge Operation ................................................
Interrupt Request Acknowledge Processing Algorithm .......................................................
Interrupt Request Acknowledge Timing (Minimum Time) ...................................................
Interrupt Request Acknowledge Timing (Maximum Time) ..................................................
Example of Multiple Interrupt (1/2) .....................................................................................
Example of Multiple Interrupt (2/2) .....................................................................................
Interrupt Request Hold .......................................................................................................
182
182
183
185
186
186
189
190
192
173
174
176
177
178
179
179
180
Oscillation Stabilization Time Select Register Format ........................................................
HALT Mode Clear upon Interrupt Generation .....................................................................
HALT Mode Release by RESET Input ................................................................................
STOP Mode Release by Interrupt Generation ....................................................................
Release by STOP Mode RESET Input ...............................................................................
194
196
197
199
200
Block Diagram of Reset Function .......................................................................................
Timing of Reset Input by RESET Input ...............................................................................
Timing of Reset due to Watchdog Timer Overflow .............................................................
Timing of Reset Input in STOP Mode by RESET Input ......................................................
201
202
202
202
Memory Size Switching Register Format ...........................................................................
Page Program Mode Flowchart ..........................................................................................
Page Program Mode Timing ...............................................................................................
Byte Program Mode Flowchart ...........................................................................................
Byte Program Mode Timing ................................................................................................
206
209
210
211
212
– viii –
Fig. No.
15-6
A-1
A-2
A-3
FIGURE (4/4)
Title
PROM Read Timing ...........................................................................................................
Page
213
Development Tool Configuration ........................................................................................
EV-9200G-44 Drawing (For Reference Only) .....................................................................
EV-9200G-44 Footprint (For Reference Only) ....................................................................
232
241
242
– ix –
Table. No.
1-1
6-1
6-2
6-3
6-4
6-5
6-6
7-1
7-2
7-3
7-4
7-5
8-1
9-1
10-1
11-1
11-2
11-3
11-4
11-5
11-6
11-7
4-1
4-2
4-3
5-1
5-2
2-1
3-1
3-2
3-2
TABLE (1/2)
Title
Differences between the
µ
PD78081, 78082 and 78P083, the
µ
PD78081(A), 78082(A) and 78P083(A), and the
µ
PD78081(A2) ............................................................................
Page
13
Type of Input/Output Circuit of Each Pin ............................................................................
22
Vector Table ........................................................................................................................
Special-Function Register List (1/2) ..................................................................................
Special-Function Register List (2/2) ...................................................................................
Port Functions ....................................................................................................................
Port Configuration ..............................................................................................................
Port Mode Register and Output Latch Settings when Using Dual-Fucntions .....................
Clock Generator Configuration ...........................................................................................
Maximum Time Required for CPU Clock Switchover .........................................................
54
55
64
28
38
39
69
77
Timer/Event Counter Types and Functions ........................................................................
8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................
8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................
8-Bit Timer/Event Counters 5 and 6 Configurations ...........................................................
8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................
8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................
Watchdog Timer Overrun Detection Times .........................................................................
Interval Times .....................................................................................................................
Watchdog Timer Configuration ...........................................................................................
Watchdog Timer Overrun Detection Time ..........................................................................
Interval Timer Interval Time ................................................................................................
103
104
105
109
110
79
80
81
82
92
95
Clock Output Control Circuit Configuration ........................................................................
112
Buzzer Output Control Circuit Configuration ......................................................................
115
A/D Converter Configuration ..............................................................................................
119
Serial Interface Channel 2 Configuration ...........................................................................
Serial Interface Channel 2 Operating Mode Settings .........................................................
136
142
Relation between Main System Clock and Baud Rate .......................................................
146
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 147
Relation between Main System Clock and Baud Rate .......................................................
155
Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) 156
Receive Error Causes ........................................................................................................
161
– x –
Table. No.
12-1
12-2
12-3
12-4
13-1
13-2
13-3
13-4
14-1
14-1
15-1
15-2
15-3
16-1
A-1
A-2
TABLE (2/2)
Title
Interrupt Source List ...........................................................................................................
Various Flags Corresponding to Interrupt Request Sources ..............................................
Times from Maskable Interrupt Request Generation to Interrupt Service ..........................
Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing .......................
Page
172
175
184
188
HALT Mode Operating Status .............................................................................................
Operation after HALT Mode Release .................................................................................
STOP Mode Operating Status ............................................................................................
Operation after STOP Mode Release .................................................................................
195
197
198
200
Hardware Status after Reset (1/2) ......................................................................................
Hardware Status after Reset (2/2) ......................................................................................
203
204
Differences between the
µ
PD78P083 and Mask ROM Versions .......................................
Examples of Memory Size Switching Register Settings .....................................................
PROM Programming Operating Modes .............................................................................
205
206
207
Operand Identifiers and Description Methods ....................................................................
216
System-Up Method from Other In-Circuit Emulator to IE-78000-R ....................................
System-Up Method from Other In-Circuit Emulator to IE-78000-R-A .................................
240
240
– xi –
[MEMO]
– xii –
CHAPTER 1 OUTLINE
CHAPTER 1 OUTLINE
1.1 Features
On-chip ROM and RAM
Type
Part Number
µ
PD78081
µ
PD78082
µ
PD78P083
Program Memory
(ROM)
8 Kbytes
16 Kbytes
24 Kbytes (Note)
Data Memory
(Internal High-Speed RAM)
256 bytes
384 bytes
512 bytes (Note)
Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).
Instruction execution time changeable from high speed (0.4
µ s: In main system clock 5.0 MHz operation) to low speed (12.8
µ s: In main system clock 5.0 MHz operation)
Instruction set suited to system control
• Bit manipulation possible in all address spaces
• Multiply and divide instructions
33 I/O ports
8-bit resolution A/D converter: 8 channels
Serial interface: 1 channel
• 3-wire serial I/O/UART mode: 1 channel
Timer: 3 channels
• 8-bit timer/event counter : 2 channels
• Watchdog timer : 1 channel
Vectored Interrupt Source : 13
Supply voltage: V
DD
= 1.8 to 5.5 V
1
CHAPTER 1 OUTLINE
1.2 Applications
µ
PD78081, 78082, 78P083:
Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc.
µ
PD78081(A), 78082(A), 78P083(A), 78081(A2):
Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc.
1.3 Ordering Information
Part number
µ
PD78081CU-
×××
µ
PD78081GB-
×××
-3B4
µ
PD78081GB-
×××
-3BS-MTX
µ
PD78082CU-
×××
µ
PD78082GB-
×××
-3B4
µ
PD78082GB-
×××
-3BS-MTX
µ
PD78P083CU
µ
PD78P083DU
µ
PD78P083GB-3B4
µ
PD78P083GB-3BS-MTX
µ
PD78081GB(A)-
×××
-3B4
µ
PD78082GB(A)-
×××
-3B4
µ
PD78P083CU(A)
µ
PD78P083GB(A)-3B4
µ
PD78P083GB(A)-3BS-MTX
Note
µ
PD78081GB(A2)-
×××
-3B4
Package
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
42-pin ceramic shrink DIP (with window) (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
Internal ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
Mask ROM
One-Time PROM
EPROM
One-Time PROM
One-Time PROM
Mask ROM
Mask ROM
One-Time PROM
One-Time PROM
One-Time PROM
Mask ROM
Note Under development
Remark
×××
indicates ROM code suffix.
2
CHAPTER 1 OUTLINE
1.4 Quality Grade
Part number Package
µ
PD78081CU-
×××
µ
PD78081GB-
×××
-3B4
µ
PD78081GB-
×××
-3BS-MTX
µ
PD78082CU-
×××
µ
PD78082GB-
×××
-3B4
µ
PD78082GB-
×××
-3BS-MTX
µ
PD78P083CU
µ
PD78P083DU
µ
PD78P083GB-3B4
µ
PD78P083GB-3BS-MTX
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
42-pin ceramic shrink DIP (with window) (600 mil)
44-pin plastic QFP (10
44-pin plastic QFP (10
×
×
10 mm)
10 mm)
µ
PD78081GB(A)-
×××
-3B4
µ
PD78082GB(A)-
×××
-3B4
µ
PD78P083CU(A)
µ
PD78P083GB(A)-3B4
µ
PD78P083GB(A)-3BS-MTX
Note
µ
PD78081GB(A)-
×××
-3B4
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
44-pin plastic QFP (10
×
10 mm)
Note Under planning
Remark
×××
indicates ROM code suffix.
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Quality grade
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Not applicable
Standard
Standard
Special
Special
Special
Special
Special
Special
3
CHAPTER 1 OUTLINE
1.5 Pin Configuration (Top View)
(1) Normal operating mode
42-pin plastic shrink DIP (600 mil)
µ
PD78081CU-
×××
, 78082CU-
×××
, 78P083CU, 78P083CU(A)
42-pin ceramic shrink DIP (with window) (600 mil)
µ
PD78P083DU
P34
P35/PCL
P36/BUZ
P37
P00
P01/INTP1
P02/INTP2
P03/INTP3
RESET
IC (V
PP
)
X2
X1
V
DD
AV
DD
P55
P56
P57
P30
P31
P32
P33
14
15
16
17
18
19
8
9
10
11
12
13
20
21
1
4
5
2
3
6
7
29
28
27
26
25
24
35
34
33
32
31
30
23
22
42
41
40
39
38
37
36
V
SS
P54
P53
P52
P51
P50
P100/TI5/TO5
P101/TI6/TO6
P70/R
X
D/SI2
P71/T
X
D/SO2
P72/ASCK/SCK2
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AV
SS
AV
REF
Cautions 1. Be sure to connect IC (Internally Connected) pin to V
SS
directly.
2. Connect AV
DD
pin to V
DD
.
3. Connect AV
SS
pin to V
SS
.
Remark Pin connection in parentheses is intended for the
µ
PD78P083.
4
CHAPTER 1 OUTLINE
• 44-pin plastic QFP (10
×
10 mm)
µ
PD78081GB-
×××
-3B4, 78081GB-
×××
-3BS-MTX
µ
PD78082GB-
×××
-3B4, 78082GB-
×××
-3BS-MTX
µ
PD78P083GB-3B4, 78P083GB-3BS-MTX
µ
PD78081GB(A)-
×××
-3B4, 78082GB(A)-
×××
-3B4
µ
PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX
Note
µ
PD78P081GB(A2)-
×××
-3B4
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
P72/ASCK/SCK2
P71/TxD/SO2
P70/RxD/SI2
P101/TI6/TO6
P100/TI5/TO6
5
6
3
4
7
8
1
44 43 42 41 40 39 38 37 36 35 34
33
2 32
9
10
25
24
11
12 13 14 15 16 17 18 19 20 21 22
23
31
30
29
28
27
26
P03/INTP3
P02/INTP2
P01/INTP1
P00
P37
P36/BUZ
P35/PCL
P34
P33
P32
NC
Note Under development
Cautions 1. Be sure to connect IC (Internally Connected) pin to V
SS directly.
2. Connect AV
DD
pin to V
DD
.
3. Connect AV
SS
pin to V
SS
.
4. Connect NC pin to V
SS
for noise protection (It can be left open).
Remark Pin connection in parenthesis is intended for the
µ
PD78P083.
5
CHAPTER 1 OUTLINE
Pin Identifications
ANI0 to ANI7
ASCK
AV
DD
AV
REF
AV
SS
BUZ
IC
INTP1 to INTP3
NC
P00 to P03
P10 to P17
P30 to P37
P50 to P57
P70 to P72
: Analog Input
: Asynchronous Serial Clock
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
: Buzzer Clock
: Internally Connected
: Interrupt from Peripherals
: Non-connection
: Port 0
: Port 1
: Port 3
: Port 5
: Port 7
P100, P101
PCL
RESET
RxD
SCK2
SI2
SO2
TI5, TI6
TO5 to TO6
TxD
V
DD
V
PP
V
SS
X1, X2
: Port 10
: Programmable Clock
: Reset
: Receive Data
: Serial Clock
: Serial Input
: Serial Output
: Timer Input
: Timer Output
: Transmit Data
: Power Supply
: Programming Power Supply
: Ground
: Crystal (Main System Clock)
6
CHAPTER 1 OUTLINE
(2) PROM programming mode
• 42-pin plastic shrink DIP (600 mil)
µ
PD78P083CU, 78P083CU(A)
• 42-pin ceramic shrink DIP (with window) (600 mil)
µ
PD78P083DU
A5
A6
A7
OE
CE
PGM
A8
(L)
(L)
A9
RESET
V
PP
Open
(L)
V
DD
V
DD
12
13
14
15
16
17
18
19
20
21
3
4
1
2
5
6
7
8
9
10
11
31
30
29
28
27
26
25
24
23
22
42
41
40
39
38
37
36
35
34
33
32
D7
D6
D5
D4
D3
D2
D1
D0
V
SS
V
SS
V
SS
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
Cautions 1. (L)
2. V
SS
: Individually connect to V
SS
via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open : Do not connect anything.
7
8
CHAPTER 1 OUTLINE
• 44-pin plastic QFP (10
×
10 mm)
µ
PD78P083GB-3B4, 78P083GB-3BS-MTX
µ
PD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX
Note
D7
A14
A13
A12
A11
A10
D2
D3
D4
D5
D6
4
5
1
44 43 42 41 40 39 38 37 36 35 34
33
2
3
32
31
30
29
8
9
6
7
10 24
11
12 13 14 15 16 17 18 19 20 21 22
23
28
27
26
25
A9
(L)
(L)
A8
PGM
(L)
Note Under development
Cautions 1. (L)
2. V
SS
: Connect individually to V
SS
via a pull-down resistor.
: Connect to the ground.
3. RESET : Set to the low level.
4. Open : Do not connect anything.
A0 to A14
CE
D0 to D7
OE
PGM
: Address Bus
: Chip Enable
: Data Bus
: Output Enable
: Program
RESET
V
DD
V
PP
V
SS
: Reset
: Power Supply
: Programming Power Supply
: Ground
CHAPTER 1 OUTLINE
1.6 78K/0 Series Development
The following shows the 78K/0 Series products development. Subseries names are shown inside frames.
78K/0 series
100-pin
100-pin
100-pin
100-pin
80-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
Mass-produced products
Products under development
Y Subseries supports the I
2
C bus specifications.
Control
µPD78075B
µPD78078
µPD78070A
µPD780018
Note
µPD780058
µPD78058F
µPD78054
µPD780034
µPD780024
µPD78014H
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD78075BY
µPD78078Y
µPD78070AY
µPD780018Y
Note
µPD780058Y
Note
µPD78058FY
µPD78054Y
µPD780034Y
µPD780024Y
µPD78018FY
µPD78014Y
µPD78002Y
Low EMI noise version of the µPD78078
Timer is added to the µPD78054 and its external interface is enhanced.
ROM-less versions of the µPD78078
Serial I/O of the µPD78078 is enhanced and only selected functions are provided.
Serial I/O-enhanced versions of the µPD78054; Low EMI noise version
Low EMI noise version of the µPD78054
UART and D/A converter are added to the µPD78014 and I/O is enhanced.
A/D-enhanced version of the µPD780024
Serial I/O-enhanced versions of the µPD78018F; Low EMI noise version
Low EMI noise version of the µPD78018F
Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities available.
A/D converter and 16-bit timer are added to the µPD78002.
A/D converter is added to the µPD78002.
Basic subseries for control applications
On-chip UART, and operable at low voltage (1.8 V).
64-pin
64-pin
100-pin
100-pin
80-pin
80-pin
Inverter control
µPD780964
µPD780924
FIP® driving
µPD780208
µPD780228
µPD78044H
µPD78044F
A/D-enhanced version of the µPD780924
On-chip inverter control circuit and UART incorporated; Low EMI noise version
I/O and FIP C/D of the µPD78044F are enhanced. Total display outputs : 53 pins
I/O and FIP C/D of the µPD78044H are enhanced. Total display outputs : 48 pins
N-ch open-drain I/O is added to the µPD78044F. Total display outputs : 34 pins
Basic subseries for FIP driving. Total display outputs: 34 pins
100-pin
100-pin
100-pin
LCD driving
µPD780308
µPD78064B
µPD78064
µPD780308Y
µPD78064Y
SIO of the µPD78064 is enhanced, and ROM and RAM are expanded.
Low EMI noise version of the µPD78064
Basic subseries for driving LCDs and with on-chip UART.
80-pin
IEBus
TM supported
µPD78098 IEBus controller is added to the µPD78054.
64-pin
LV
µPD78P0914
Note Under planning
PWM output, LV digital code decoder and Hsync counter are incorporated.
9
CHAPTER 1 OUTLINE
The following table shows the differences among subseries functions.
Control
Function
Subseries name
ROM capacity
Timer
8-bit 16-bit Watch WDT
8-bit 10-bit 8-bit
A/D A/D D/A
Serial interface I/O
V
DD
MIN.
value
External expansion
µ
PD78075B 32K to 40K 4 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch) 88 1.8 V Available
µ
PD78078 48K to 60K
µ
PD78070A —
µ
PD780018 48K to 60K — 2 ch (Time division
3-wire: 1 ch)
61
88
2.7 V
µ
PD780058 24K to 60K 2 ch 2 ch 3 ch (Time division
UART: 1 ch)
68 1.8 V
µ
PD78058F 48K to 60K
µ
PD78054 16K to 60K
µ
PD780034 8K to 32K
µ
PD780024
µ
PD78014H
µ
PD78018F 8K to 60K
µ
PD78014 8K to 32K
µ
PD780001 8K
µ
PD78002 8K to 16K
µ
PD78083
— —
1 ch
—
—
8 ch
—
8 ch
8 ch
—
—
3 ch (UART: 1 ch) 69
3 ch (UART: 1 ch, Time division 3-wire: 1 ch)
2 ch
1 ch
51
53
39
53
1 ch (UART: 1 ch) 33
2.7 V
2.0 V
1.8 V
2.7 V
1.8 V
—
Available
—
Inverter control
µ
PD780964 8K to 32K 3 ch Note — 1 ch — 8 ch — 2 ch (UART: 2 ch) 47
µ
PD780924 8 ch —
FIP driving
µ
PD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch — — 2 ch 74
2.7 V
2.7 V
Available
—
µ
PD780228 48K to 60K 3 ch — — 1 ch 72 4.5 V
LCD driving
µ
PD78044H 32K to 48K 2 ch 1 ch 1 ch
µ
PD78044F 16K to 40K 2 ch
68 2.7 V
µ
PD780308 48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch — — 3 ch (Time division 57 2.0 V
UART: 1 ch)
—
IEBus supported
µ
PD78064B 32K
µ
PD78064 16K to 32K
2 ch (UART: 1 ch)
µ
PD78098 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch — 2 ch 3 ch (UART: 1 ch) 69 2.7 V Available
LV
µ
PD78P0914 32K
Note 10 bits timer: 1 channel
6 ch — — 1 ch 8 ch — — 2 ch 54 4.5 V Available
10
CHAPTER 1 OUTLINE
1.7 Block Diagram
P100/TI5/TO5
P101/TI6/TO6
8-bit TIMER/
EVENT COUNTER 5
8-bit TIMER/
EVENT COUNTER 6
WATCHDOG
TIMER
SERIAL
INTERFACE 2
78K/0
CPU
CORE
ROM
PORT 0
PORT 1
PORT 3
SI2/R
X
D/P70
SO2/T
X
D/P71
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
AV
DD
AV
SS
AV
REF
INTP1/P01-
INTP3/P03
BUZ/P36
PCL/P35
A/D
CONVERTER
RAM
PORT 5
PORT 7
INTERRUPT
CONTROL
BUZZER OUTPUT
CLOCK OUTPUT
CONTROL
PORT 10
SYSTEM
CONTROL
V
DD
V
SS
IC
(V
PP
)
Remarks 1. The internal ROM and high-speed RAM capacities depend on the product.
2. Pin connection in parentheses is intended for the
µ
PD78P083.
P00
P01-P03
P10-P17
P30-P37
P50-P57
P70-P72
P100, P101
RESET
X1
X2
11
CHAPTER 1 OUTLINE
1.8 Outline of Function
Part Number
Item
Internal memory ROM
Memory space
General register
Instruction cycle
High-speed RAM
Instruction set
I/O ports
A/D converter
Serial interface
Timer
Timer output
Clock output
Buzzer output
Vectored interrupt
Maskable
Non-maskable source Software
Supply voltage
Operating ambient temperature
Package
µ
PD78081
µ
PD78082
µ
PD78083
Mask ROM
8 Kbytes
256 bytes
16 Kbytes
384 bytes
PROM
24 Kbytes
512 bytes
Note
Note
64 Kbytes
8 bits
×
32 registers (8 bits
×
8 registers
×
4 banks)
Instruction execution time variable function is integrated.
0.4
µ s/0.8
µ s/1.6
µ s/3.2
µ s/6.4
µ s/12.8
µ s (@5.0-MHz operation with main system clock)
• 16-bit operation
• Multiply/divide (8 bits
×
8 bits, 16 bits
÷
8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
Total
• CMOS input
: 33
: 1
• CMOS input/output : 32
• 8-bit resolution
×
8 channels
• 3-wire serial I/O/UART mode selectable: 1 channel
• 8-bit timer/event counter: 2 channels
• Watchdog timer: 1 channel
2 pins (8-bit PWM output enable)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock)
1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz
(@ 5.0-MHz operation with main system clock)
Internal : 8 external : 3
Internal : 1
1
V
DD
= 1.8 to 5.5 V
T
A
= –40 to +85
°
C
• 42-pin plastic shrink DIP (600 mil)
• 44-pin plastic QFP (10
×
10 mm)
• 42-pin ceramic shrink DIP (with window) (600 mil) (
µ
PD78P083 only)
Note Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size switching register (IMS).
12
CHAPTER 1 OUTLINE
1.9
Differences between the
µ
PD78081, 78082 and 78P083, the
µ
PD78081(A), 78082(A) and
78P083(A), and the
µ
PD78081(A2)
Table 1-1 Differences between the
µ
PD78081, 78082 and 78P083, the
µ
PD78081(A), 78082(A) and
78P083(A), and the
µ
PD78081(A2)
µ
PD78081(A2)
Item
Quality grade
Part Number
µ
PD78081
µ
PD78082
µ
PD78P083
Standard
µ
PD78081(A)
µ
PD78082(A)
µ
PD78P083(A)
Special
Supply voltage V
DD
= 1.8 to 5.5 V
Operating ambient temperature T
A
= –40 to +85
°
C
Electrical specifications Please refer to the individual data sheets.
V
DD
= 4.5 to 5.5 V
T
A
= –40 to +125
°
C
13
[MEMO]
CHAPTER 1 OUTLINE
14
CHAPTER 2 PIN FUNCTION
CHAPTER 2 PIN FUNCTION
2.1 Pin Function List
2.1.1 Normal operating mode pins
(1) Port pins
Pin Name
P00
P01
P02
P03
P10-P17
P30-P34
P35
P36
P37
P50-P57
P70
P71
P72
P100
P101
Input/Output
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Port 0
4-bit input/output port
Function
Input only
Input/output is specifiable bit-wise. When used as the input port, it is possible to connect a pull-up resistor by software.
Port 1
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software. Note
Port 3
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Port 5
8-bit input/output port
A maximum of 7 out of 8 ports can drive LEDs directly.
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Port 7
3-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Port 10
2-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
After Reset Alternate Function
Input
Input
—
INTP1
INTP2
INTP3
Input
Input
Input
Input
Input
ANI0-ANI7
PCL
BUZ
—
—
—
SI2/RxD
SO2/TxD
SCK2/ASCK
TI5/TO5
TI6/TO6
Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode. The on-chip pull-up resistor is automatically disabled.
15
CHAPTER 2 PIN FUNCTION
TxD
ASCK
TI5
TI6
TO5
TO6
PCL
BUZ
Pin Name
INTP1
INTP2
INTP3
SI2
SO2
SCK2
RxD
ANI0-ANI7
AV
REF
AV
DD
AV
SS
RESET
X1
X2
V
DD
V
PP
V
SS
IC
NC
(2) Pins other than port pins
Output
Output
Input
Input
–
–
Input
Input
–
–
–
Input/Output
Input
Function After Reset Alternate Function
External interrupt request input by which the active edge Input P01
(rising edge, falling edge, or both rising and falling edges) can be specified.
P02
P03
Input
Output
Serial interface serial data input.
Serial interface serial data output.
Input/output Serial interface serial clock input/output.
Input Asynchronous serial interface serial data input.
Input
Input
Input
Input
P70/RxD
P71/TxD
P72/ASCK
P70/SI2
Output
Input
Input
Output
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input.
External count clock input to 8-bit timer (TM5).
External count clock input to 8-bit timer (TM6).
8-bit timer output. (also used for 8-bit PWM output)
Clock output. (for main system clock trimming)
Buzzer output.
A/D converter analog input.
A/D converter reference voltage input.
A/D converter analog power supply. Connected to V
DD
.
A/D converter ground potential. Connected to V
SS
.
System reset input.
Main system clock oscillation crystal connection.
Input
Input
Input
Input
Input
Input
Input
–
–
–
–
–
–
–
–
P71/SO2
P72/SCK2
P100/TO5
P101/TO6
P100/TI5
P101/TI6
P35
P36
P10-P17
–
–
–
–
–
–
–
–
–
–
–
Positive power supply.
High-voltage applied during program write/verification.
Connected directly to V
SS
in normal operating mode.
Ground potential.
Internal connection. Connect directly to V
SS
.
Does not internally connected. Connect to V
SS
.
(It can be left open)
–
–
–
–
–
–
2.1.2 PROM programming mode pins (
µ
PD78P083 only)
Pin Name
RESET
V
PP
A0 to A14
D0 to D7
CE
OE
PGM
V
DD
V
SS
Input/Output
Input
Function
PROM programming mode setting.
When +5 V or +12.5 V is applied to the V
PP
pin or a low level voltage is applied to the
Input
Input
RESET pin, the PROM programming mode is set.
High-voltage application for PROM programming mode setting and program write/verify.
Address bus
Input/output Data bus
Input
Input
Input
—
—
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input in PROM programming mode
Positive power supply
Ground potential
16
CHAPTER 2 PIN FUNCTION
2.2 Description of Pin Functions
2.2.1 P00 to P03 (Port 0)
These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input.
The following operating modes can be specified bit-wise.
(1) Port mode
P00 functions as input-only port and P01 to P03 function as input/output ports.
P01 to P03 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor option register L (PUOL).
(2) Control mode
INTP1 to INTP3 function as external interrupt request input pins which are capable of specifying the valid edges
(rising edge, falling edge, and both rising and falling edges).
2.2.2 P10 to P17 (Port 1)
These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports.
They can be specified bit-wise as input or output ports with a port mode register 1 (PM1). If used as input ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L
(PUOL).
(2) Control mode
These ports function as A/D converter analog input pins (ANI0-ANI7). The on-chip pull-up resistor is automatically disabled when the pins specified for analog input.
17
CHAPTER 2 PIN FUNCTION
2.2.3 P30 to P37 (Port 3)
These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock output and buzzer output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).
(2) Control mode
These ports function as clock output, and buzzer output.
(a) PCL
Clock output pin.
(b) BUZ
Buzzer output pin.
2.2.4 P50 to P57 (Port 5)
These are 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register
5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL). A maximum of 7 out of 8 ports can drive LEDs directly.
18
CHAPTER 2 PIN FUNCTION
2.2.5 P70 to P72 (Port 7)
This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/ output and clock input/output functions.
The following operating modes can be specified bit-wise.
(1) Port mode
Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).
(2) Control mode
Port 7 functions as serial interface data input/output and clock input/output.
(a) SI2, SO2
Serial interface serial data input/output pins
(b) SCK2
Serial interface serial clock input/output pin.
(c) RxD, TxD
Asynchronous serial interface serial data input/output pins.
(d) ASCK
Asynchronous serial interface serial clock input pin.
Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires.
For the setting, see the operation mode setting list in Table 11-2 “Serial Interface Channel
2 Operating Mode Settings”
2.2.6 P100 to P101 (Port 10)
These are 2-bit input/output ports. Besides serving as input/output ports, they function as timer input/output.
The following operating modes can be specified bit-wise.
(1) Port mode
These ports function as 2-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 10 (PM10). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register H (PUOH).
(2) Control mode
These ports function as timer input/output.
(a) TI5, TI6
Pin for external clock input to the 8-bit timer/event counter 5 and 6.
(b) TO5, TO6
Timer output pins.
19
CHAPTER 2 PIN FUNCTION
2.2.7 AV
REF
A/D converter reference voltage input pin.
When A/D converter is not used, connect this pin to V
SS
.
2.2.8 AV
DD
Analog power supply pin of A/D converter. Always use the same voltage as that of the V
DD
pin even when A/D converter is not used.
2.2.9 AV
SS
This is a ground voltage pin of A/D converter. Always use the same voltage as that of the V
SS
pin even when A/
D converter is not used.
2.2.10 RESET
This is a low-level active system reset input pin.
2.2.11 X1 and X2
Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2.
2.2.12 V
DD
Positive power supply pin
2.2.13 V
SS
Ground potential pin
2.2.14 V
PP
(
µ
PD78P083 only)
High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to V
SS in normal operating mode.
20
CHAPTER 2 PIN FUNCTION
2.2.15 IC (Mask ROM version only)
The IC (Internally Connected) pin is provided to set the test mode to check the
µ
PD78083 Subseries at delivery.
Connect it directly to the V
SS
with the shortest possible wire in the normal operating mode.
When a voltage difference is produced between the IC pin and V
SS
pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.
Connect IC pins to V
SS
pins directly.
V
SS
IC
As short as possible
2.2.16 NC (44-pin plastic QFP versions only)
Not internally connected. Please connect to Vss (open is also possible)
21
CHAPTER 2 PIN FUNCTION
2.3
Pin Input/Output Circuits and Recommended Connection of Unused Pins
Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1.
For the configuration of each type of input/output circuit, see Figure 2-1.
Table 2-1. Type of Input/Output Circuit of Each Pin
Pin Name
P00
P01/INTP1
P02/INTP2
P03/INTP3
P10/ANI0-P17/ANI7
P30-P32
P33, P34
P35/PCL
P36/BUZ
P37
P50-P57
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
P100/TI5/TO5
P101/TI6/TO6
RESET
AV
REF
AV
DD
AV
SS
V
PP
(
µ
PD78P083)
NC (44-pin plastic QFP version)
IC (Mask ROM version)
11
5-A
8-A
5-A
2
5-A
8-A
5-A
8-A
8-A
2
8-A
Input/Output
Circuit Type
–
Input/Output
Input
Input/Output
Input/Output
Input
–
Recommended Connection for Unused Pins
Connect to V
SS
.
Independently connect to V
SS
via a resistor.
Independently connect to V a resistor.
Connect to V
SS
.
Connect to V
DD
.
Connect to V
SS
.
SS
.
–
Connect directly to V
SS
.
Connect to V
SS
(can also leave open)
Connect directly to V
DD
or V
SS
via
22
Type 5-A pull-up enable data output disable input enable
Type 2
IN
CHAPTER 2 PIN FUNCTION
Figure 2-1. Pin Input/Output Circuit of List
Type 8-A pull-up enable
Schmitt-Triggered Input with
Hysteresis Characteristics data output disable
V
DD
V
DD
P-ch
P-ch
IN/OUT
N-ch
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
Type 11
V
DD pull-up enable data
V
DD
P-ch
P-ch
IN/OUT output disable
N-ch
P-ch comparator
+
–
N-ch
V
REF
(Threshold voltage) input enable
23
[MEMO]
CHAPTER 2 PIN FUNCTION
24
CHAPTER 3 CPU ARCHITECTURE
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Spaces
Figures 3-1 to 3-3 shows memory maps.
Figure 3-1. Memory Map (
µ
PD78081)
FFFFH
F F 0 0 H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256
×
8 bits
General Registers
32
×
8 bits
Internal High-speed RAM
256
×
8 bits
Data memory space
Program memory space
F E 0 0 H
FDFFH
2 0 0 0 H
1 F F F H
0 0 0 0 H
Unusable
Internal ROM
8192
×
8 bits
1 F F F H
1 0 0 0 H
0 F F F H
Program Area
CALLF Entry Area
0 8 0 0 H
0 7 F F H
Program Area
0 0 8 0 H
0 0 7 F H
CALLT Table Area
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
Vector Table Area
25
26
Data memory space
Program memory space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-2. Memory Map (
µ
PD78082)
FFFFH
F F 0 0 H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256
×
8 bits
General Registers
32
×
8 bits
FD80H
FD7FH
4 0 0 0 H
3 F F F H
0 0 0 0 H
Internal High-speed RAM
384
×
8 bits
Unusable
Internal ROM
16384
×
8 bits
3 F F F H
1 0 0 0 H
0 F F F H
Program Area
CALLF Entry Area
0 8 0 0 H
0 7 F F H
Program Area
0 0 8 0 H
0 0 7 F H
CALLT Table Area
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
Vector Table Area
Data memory space
Program memory space
CHAPTER 3 CPU ARCHITECTURE
Figure 3-3. Memory Map (
µ
PD78P083)
FFFFH
F F 0 0 H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256
×
8 bits
General Registers
32
×
8 bits
FD00H
FCFFH
6 0 0 0 H
5 F F F H
0 0 0 0 H
Internal High-speed RAM
512
×
8 bits
Unusable
Internal PROM
24576
×
8 bits
5 F F F H
1 0 0 0 H
0 F F F H
Program Area
CALLF Entry Area
0 8 0 0 H
0 7 F F H
Program Area
0 0 8 0 H
0 0 7 F H
CALLT Table Area
0 0 4 0 H
0 0 3 F H
0 0 0 0 H
Vector Table Area
27
CHAPTER 3 CPU ARCHITECTURE
3.1.1 Internal program memory space
The internal program memory is mask ROM with a 8192
×
8-bit configuration in the
µ
PD78081, and a 16384
×
8-bit configuration in the
µ
PD78082, and PROM with a 24576
×
8-bit configuration in the
µ
PD78P083.
The internal program memory space stores programs and table data. Normally, they are addressed with a program counter (PC).
The internal program memory is divided into the following three areas.
(1) Vector table area
The 64-byte area 0000H to 003FH is reserved as a vector table area. The RESET input and program start addresses for branch upon generation of each interrupt request are stored in the vector table area. Of the
16-bit address, low-order 8 bits are stored at even addresses and high-order 8 bits are stored at odd addresses.
Table 3-1. Vector Table
Vector Table Address
0000H
0004H
0008H
000AH
000CH
0018H
001AH
001CH
0028H
002AH
002CH
003EH
Interrupt Request
RESET input
INTWDT
INTP1
INTP2
INTP3
INTSER
INTSR/INTCSI2
INTST
INTAD
INTTM5
INTTM6
BRK
(2) CALLT instruction table area
The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).
(3) CALLF instruction entry area
The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).
28
CHAPTER 3 CPU ARCHITECTURE
3.1.2 Internal data memory space
The internal high speed RAM configuration is 256
×
8-bit in the
µ
PD78081, 384
×
8-bit in the
µ
PD78082 and 512
×
8-bit in the
µ
PD8P083. In this area, four banks of general registers, each bank consisting of eight 8-bit registers, are allocated in the 32-byte area FEE0H to FEFFH.
The internal high-speed RAM can also be used as a stack memory area.
3.1.3 Special Function Register (SFR) area
An on-chip peripheral hardware special-function register (SFR) is allocated in the area FF00H to FFFFH. (Refer to Table 3-2. Special-Function Register List in 3.2.3 Special Function Register (SFR)).
Caution Do not access addresses where the SFR is not assigned.
3.1.4 Data memory addressing
The method to specify the address of the instruction to be executed next, or the address of a register or memory to be manipulated when an instruction is executed is called addressing.
The address of the instruction to be executed next is addressed by the program counter PC (for details, refer to
3.3 Instruction Address Addressing).
To address the memory that is manipulated when an instruction is executed, the
µ
PD78083 Subseries is provided with many addressing modes with a high operability. Especially at addresses corresponding to data memory area, particular addressing modes are possible to meet the functions of the special function registers (SFRs) and general registers. This area is between FE00H and FFFFH for the
µ
PD78081, FD80H and FFFFH for the
µ
PD78082, and between FD00H and FFFFH for the
µ
PD78P083. The data memory space is the entire 64K-byte space (0000H to
FFFFH). Figure 3-4 to 3-6 show the data memory addressing modes. For details of each addressing, refer to 3.4
Operand Address Addressing.
29
30
CHAPTER 3 CPU ARCHITECTURE
Figure 3-4. Data Memory Addressing (
µ
PD78081)
FFFFH
F F 2 0 H
F F 1 F H
F F 0 0 H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256
×
8 bits
General Registers
32
×
8 bits
Internal High-speed RAM
256
×
8 bits
F E 2 0 H
FE1FH
F E 0 0 H
FDFFH
Unusable
2 0 0 0 H
1 F F F H
Internal ROM
8192
×
8 bits
0 0 0 0 H
SFR Addressing
Register Addressing
Short Direct
Addressing
Direct Addressing
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing
CHAPTER 3 CPU ARCHITECTURE
Figure 3-5. Data Memory Addressing (
µ
PD78082)
FFFFH
F F 2 0 H
F F 1 F H
F F 0 0 H
FEFFH
FEE0H
FEDFH
Special Function
Registers (SFRs)
256
×
8 bits
General Registers
32
×
8 bits
Internal High-speed RAM
384
×
8 bits
F E 2 0 H
FE1FH
FD80H
FD7FH
Unusable
4 0 0 0 H
3 F F F H
Internal ROM
16384
×
8 bits
0 0 0 0 H
SFR Addressing
Register Addressing
Short Direct
Addressing
Direct Addressing
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing
31
32
FFFFH
F F 2 0 H
F F 1 F H
F F 0 0 H
FEFFH
FEE0H
FEDFH
Figure 3-6. Data Memory Addressing (
µ
PD78P083)
Special Function
Registers (SFRs)
256
×
8 bits
CHAPTER 3 CPU ARCHITECTURE
General Registers
32
×
8 bits
Internal High-speed RAM
512
×
8 bits
SFR Addressing
Register Addressing
F E 2 0 H
FE1FH
FD00H
FCFFH
Unusable
Short Direct
Addressing
Direct Addressing
Register Indirect
Addressing
Based Addressing
Based Indexed
Addressing
6 0 0 0 H
5 F F F H
Internal PROM
24576
×
8 bits
0 0 0 0 H
CHAPTER 3 CPU ARCHITECTURE
3.2 Processor Registers
The
µ
PD78083 subseries units incorporate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter, a program status word and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-7. Program Counter Configuration
15 0
PC
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically reset upon execution of the RETB, RETI and POP PSW instructions.
RESET input sets the PSW to 02H.
Figure 3-8. Program Status Word Configuration
7
IE Z RBS1 AC RBS0 0 ISP
0
CY
33
34
CHAPTER 3 CPU ARCHITECTURE
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except the non-maskable interrupt are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupts is controlled with an inservice priority flag (ISP), an interrupt mask flag for various interrupt sources, and a priority specify flag.
The interrupt enable flag is reset to 0 when the DI instruction is executed or when an interrupt request is acknowledged, and set to 1 when the EI instruction is executed.
(b) Zero flag (Z)
When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0 and RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored.
(d) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
(e) In-service priority flag (ISP)
This flag manages the priority of acknowledgeable maskable vectored interrupts. When ISP = 0, the vectored interrupt request whose priority is specified by the priority specify flag registers (PR0L, PR0H, and PR1L) (Refer to 12.3 (3) Priority specify flag registers (PR0L, PR0H, and PR1L)) to be low is disabled. Whether the interrupt request is actually acknowledged is controlled by the status of the interrupt enable flag (IE).
(f) Carry flag (CY)
This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution.
CHAPTER 3 CPU ARCHITECTURE
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area (FE00H-FEFFH for the
µ
PD78081, FD80H-FEFFH for the
µ
PD78082, and FD00H-FEFFH for the
µ
PD78P083) can be set as the stack area.
Figure 3-9. Stack Pointer Configuration
15 0
SP
The SP is decremented ahead of write (save) to the stack memory and is incremented after read (reset) from the stack memory.
Each stack operation saves/resets data as shown in Figures 3-10 and 3-11.
Caution Since RESET input makes SP contents indeterminate, be sure to initialize the SP before instruction execution.
Figure 3-10. Data to be Saved to Stack Memory
PUSH rp Instruction CALL, CALLF, and
CALLT Instruction
Interrupt and
BRK Instruction
SP SP _ 2
SP _ 2 Register Pair Lower
SP _ 1 Register Pair Upper
SP SP _ 2
SP _ 2
SP _ 1
SP SP
PC7-PC0
PC15-PC8
SP SP _ 3
SP _ 3
SP _ 2
SP _ 1
SP
PC7-PC0
PC15-PC8
PSW
Figure 3-11. Data to be Reset from Stack Memory
POP rp Instruction RET Instruction
RETI and RETB
Instruction
SP Register Pair Lower
SP + 1 Register Pair Upper
SP SP + 2
SP
SP + 1
SP SP + 2
PC7-PC0
PC15-PC8
SP
SP + 1
SP + 2
SP SP + 3
PC7-PC0
PC15-PC8
PSW
35
CHAPTER 3 CPU ARCHITECTURE
3.2.2 General registers
A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L and H).
Each register can also be used as an 8-bit register. Two 8-bit registers can be used in pairs as a 16-bit register
(AX, BC, DE and HL).
They can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) and absolute names
(R0 to R7 and RP0 to RP3).
Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interruption request for each bank.
Figure 3-12. General Register Configuration
(a) Absolute Name
16-Bit Processing
FEFFH
FEF8H
FEF0H
FEE8H
BANK0
BANK1
BANK2
BANK3
RP3
RP2
RP1
RP0
8-Bit Processing
R7
R6
R5
R4
R3
R2
R1
R0
FEE0H
15 0 7 0
(b) Function Name
16-Bit Processing
FEFFH
FEF8H
FEF0H
FEE8H
BANK0
BANK1
BANK2
BANK3
HL
DE
BC
AX
8-Bit Processing
H
E
B
L
D
C
A
X
FEE0H
15 0 7 0
36
CHAPTER 3 CPU ARCHITECTURE
3.2.3 Special Function Register (SFR)
Unlike a general register, each special-function register has special functions.
It is allocated in the FF00H to FFFFH area.
The special-function register can be manipulated like the general register, with the operation, transfer and bit manipulation instructions. Manipulatable bit units, 1, 8 and 16, depend on the special-function register type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved with assembler for the 1-bit manipulation instruction operand (sfr.bit).
This manipulation can also be specified with an address.
• 8-bit manipulation
Describe the symbol reserved with assembler for the 8-bit manipulation instruction operand (sfr).
This manipulation can also be specified with an address.
• 16-bit manipulation
Describe the symbol reserved with assembler for the 16-bit manipulation instruction operand (sfrp).
When addressing an address, describe an even address.
Table 3-2 gives a list of special-function registers. The meaning of items in the table is as follows.
• Symbol
Symbols indicating the addresses of special function register. These symbols are reserved words for the RA78K/
0 and defined by header file sfrbit.h for the CC78K/0, and can be used as the operands of instructions when the RA78K/0, ID78K0, and SD78K/0 are used.
• R/W
Indicates whether the corresponding special-function register can be read or written.
R/W : Read/write enable
R : Read only
W : Write only
• Manipulatable bit units
√
indicates bit units (1, 8 or 16 bits) in which the register can be manipulated. — indicates that the register cannot be manipulated in the indicated bit units.
• After reset
Indicates each register status upon RESET input.
37
CHAPTER 3 CPU ARCHITECTURE
FF80H
FF84H
FFE0H
FFE1H
FFE2H
FFE4H
FFE5H
FFE6H
FFE8H
FFE9H
Address
FF21H
FF23H
FF25H
FF27H
FF2AH
FF40H
FF42H
FF50H
FF00H
FF01H
FF03H
FF05H
FF07H
FF0AH
FF1FH
FF20H
FF51H
FF52H
FF53H
FF54H
FF55H
FF56H
FF57H
FF70H
FF71H
FF72H
FF73H
FF74H
Table 3-2. Special-Function Register List (1/2)
Special-Function Register (SFR) Name Symbol R/W
Port0
Port1
Port3
Port5
Port7
Port10
A/D conversion result register
Port mode register 0
Port mode register 1
Port mode register 3
Port mode register 5
Port mode register 7
Port mode register 10
Timer clock select register 0
Timer clock select register 2
Compare Register 50
8-bit timer register 5
Timer clock select register 5
8-bit timer mode control register 5
Compare Register 60
8-bit timer register 6
Timer clock select register 6
8-bit timer mode control register 6
Asynchronous serial interface mode register
Asynchronous serial interface status register
Serial operating mode register 2
Baud rate generator control register
Transmit shift register
Receive buffer register
A/D converter mode register
A/D converter input select register
Interrupt request flag register 0L
Interrupt request flag register 0H
Interrupt request flag register 1L
Interrupt mask flag register 0L
Interrupt mask flag register 0H
Interrupt mask flag register 1L
Priority order specify flag register 0L
Priority order specify flag register 0H
TM5
TCL5
TMC5
CR60
TM6
TCL6
TMC6
ASIM
ASIS
CSIM2
BRGC
TXS SIO2
RXB
ADM
ADIS
IF0 IF0L
IF0H
IF1L
MK0 MK0L
MK0H
MK1L
PR0 PR0L
PR0H
PM1
PM3
PM5
PM7
PM10
TCL0
TCL2
CR50
P0
P1
P3
P5
P7
P10
ADCR
PM0
R/W
R
R/W
R
R/W
R
R/W
R
R/W
W
R
R/W
√
—
√
√
√
√
√
√
√
√
Manipulatable Bit Unit
1 bit 8 bits 16 bits
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
—
—
—
—
√
—
—
—
√
√
√
√
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
After Reset
00H
Undefined
FFH
00H
FFH
√
√
√
√
√
√
√
√
√
√
—
—
√
—
√
—
√
01H
00H
FFH
38
CHAPTER 3 CPU ARCHITECTURE
FFEAH
FFECH
FFEDH
FFF0H
FFF2H
FFF3H
FFF7H
FFF9H
FFFAH
FFFBH
Address
Table 3-2. Special-Function Register List (2/2)
Special-Function Register (SFR) Name
Priority order specify flag register 1L
External interrupt mode register 0
External interrupt mode register 1
Memory size switching register
Oscillation mode selection register
Pull-up resistor option register H
Pull-up resistor option register L
Watchdog timer mode register
Oscillation stabilization time select register
Processor clock control register
Symbol
PR1L
INTM0
INTM1
IMS
OSMS
PUOH
PUOL
WDTM
OSTS
PCC
R/W
R/W
W
R/W
Manipulatable Bit Unit
16 bits 1 bit
√
—
—
—
—
√
√
√
—
√
8 bits
√
√
√
√
√
√
√
√
√
√
—
—
—
—
—
—
—
—
—
—
After Reset
FFH
00H
(Note)
00H
04H
Note The value after reset depends on products.
µ
PD78081 : 82H,
µ
PD78082 : 64H,
µ
PD78P083 : 46H.
39
CHAPTER 3 CPU ARCHITECTURE
3.3 Instruction Address Addressing
An instruction address is determined by program counter (PC) contents. The contents of PC are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing. (For details of instructions, refer to 78K/0 USER'S MANUAL:
Instruction (IEU-1372).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (–128 to +127) and bit 7 becomes a sign bit.
In the relative addressing modes, execution branches in a relative range of –128 to +127 from the first address of the next instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
α
PC
+
8 7 6
S
0
...
PC indicates the start address of the instruction after the BR instruction.
0 jdisp8
PC
15 0
When S = 0, all bits of
α
are 0.
When S = 1, all bits of
α
are 1.
40
CHAPTER 3 CPU ARCHITECTURE
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and branched.
This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.
The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space. The CALLF !addr11
instruction branches to an area of addresses 0800H through 0FFFH.
[Illustration]
In the case of CALL !addr16 and BR !addr16 instructions
7 0
CALL or BR
Low Addr.
High Addr.
0
PC
15
In the case of CALLF !addr11 instruction
7 6 fa
10–8
4 3
CALLF fa
7–0
0
8 7
PC
15 11 10
0 0 0 0 1
8 7 0
41
CHAPTER 3 CPU ARCHITECTURE
3.3.3 Table indirect addressing
[Function]
Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched.
Before the CALLT [addr5] instruction is executed, table indirect addressing is performed. This instruction references an address stored in the memory table at addresses 40H through 7FH, and can branch in the entire memory space.
[Illustration]
Operation Code
7 6
1 1
5 ta
4–0
1 0
1
Effective Address
15
0
8 7
0 0 0 0 0 0 0 0
6 5
1
1 0
0
Effective Address+1
7 Memory (Table)
Low Addr.
High Addr.
0
PC
15 8 7 0
42
CHAPTER 3 CPU ARCHITECTURE
3.3.4 Register addressing
[Function]
Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7 0 7 0 rp A X
PC
15 8 7 0
43
CHAPTER 3 CPU ARCHITECTURE
3.4 Operand Address Addressing
The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution.
3.4.1 Implied addressing
[Function]
The register which functions as an accumulator (A and AX) in the general register is automatically (illicitly) addressed.
Of the
µ
PD78083 Subseries instruction words, the following instructions employ implied addressing.
Instruction
MULU
DIVUW
ADJBA/ADJBS
ROR4/ROL4
Register to be Specified by Implied Addressing
A register for multiplicand and AX register for product storage
AX register for dividend and quotient storage
A register for storage of numeric values which become decimal correction targets
A register for storage of digit data which undergoes digit rotation
[Operand format]
Because implied addressing can be automatically employed with an instruction, no particular operand format is necessary.
[Description example]
In the case of MULU X
With an 8-bit
×
8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing.
44
CHAPTER 3 CPU ARCHITECTURE
3.4.2 Register addressing
[Function]
This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
[Operand format]
Identifier r rp
Description
X, A, C, B, E, D, L, H
AX, BC, DE, HL
'r' and 'rp' can be described with function names (X, A, C, B, E, D, L, H, AX, BC, DE and HL) as well as absolute names (R0 to R7 and RP0 to RP3).
[Description example]
MOV A, C; when selecting C register as r
Operation code 0 1 1 0 0 0 1 0
Register specify code
INCW DE; when selecting DE register pair as rp
Operation code 1 0 0 0 0 1 0 0
Register specify code
45
CHAPTER 3 CPU ARCHITECTURE
3.4.3 Direct addressing
[Function]
This addressing directly addresses the memory indicated by the immediate data in an instruction word.
[Operand format]
Identifier addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !0FE00H; when setting !addr16 to FE00H
Operation code 1 0 0 0 1 1 1 0 OP code
0 0 0 0 0 0 0 0 00H
1 1 1 1 1 1 1 0 FEH
[Illustration]
7 0
OP code saddr16 (low) saddr16 (high)
Memory
46
CHAPTER 3 CPU ARCHITECTURE
3.4.4 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.
The fixed space to which this address is applied is a 256-byte space of addresses FE20H through FF1FH. An internal high-speed RAM and a special-function register (SFR) are mapped at FE20H to FEFFH and FF00H to
FF1FH, respectively.
The SFR area (FF00H through FF1FH) to which short direct addressing is applied is a part of the entire SFR area. To this area, ports frequently accessed by the program, and the compare registers and capture registers of timer/event counters are mapped. These SFRs can be manipulated with a short byte length and a few clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. Refer to [Illustration] on next page.
[Operand format]
Identifier saddr saddrp
Description
Label of FE20H to FF1FH immediate data
Label of FE20H to FF1FH immediate data (even address only)
47
CHAPTER 3 CPU ARCHITECTURE
[Description example]
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H
Operation code 0 0 0 1 0 0 0 1 OP code
0 0 1 1 0 0 0 0 30H (saddr-offset)
0 1 0 1 0 0 0 0 50H (immediate data)
[Illustration]
7 0
OP code saddr-offset
Short Direct Memory
Effective Address
15
1 1 1 1 1 1 1
8 7
α
When 8-bit immediate data is 20H to FFH,
α
= 0
When 8-bit immediate data is 00H to 1FH,
α
= 1
0
48
CHAPTER 3 CPU ARCHITECTURE
3.4.5 Special-Function Register (SFR) addressing
[Function]
The memory-mapped special-function register (SFR) is addressed with 8-bit immediate data in an instruction word.
This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
[Operand format]
Identifier sfr sfrp
Special-function register name
Description
16-bit manipulatable special-function register name (even address only)
[Description example]
MOV PM0, A; when selecting PM0 (FF20H) as sfr
Operation code 1 1 1 1 0 1 1 0 OP code
0 0 1 0 0 0 0 0 20H (sfr-offset)
[Illustration]
7 0
OP code sfr-offset
SFR
Effective Address
15
1 1 1 1 1 1 1 1
8 7 0
49
CHAPTER 3 CPU ARCHITECTURE
3.4.6 Register indirect addressing
[Function]
This addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
— [DE], [HL]
Description
[Description example]
MOV A, [DE]; when selecting [DE] as register pair
1 0 0 0 0 1 0 1 Operation code
[Illustration]
DE
16
D
8 7
E
7 Memory
Contents of addressed memory are transferred.
7 0
A
0
0
Memory address specified by register pair DE
50
CHAPTER 3 CPU ARCHITECTURE
3.4.7 Based addressing
[Function]
This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1). Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
— [HL + byte]
Description
[Description example]
MOV A, [HL + 10H]; when setting byte to 10H
Operation code 1 0 1 0 1 1 1 0
0 0 0 1 0 0 0 0
51
CHAPTER 3 CPU ARCHITECTURE
3.4.8 Based indexed addressing
[Function]
This addressing addresses the memory by adding the contents of the HL register, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition.
The HL, B, and C registers to be accessed are registers in the register bank specified by the register bank select flags (RBS0 and RBS1). The addition is performed by extending the contents of the B or C register to 16 bits as a positive number. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier
— [HL + B], [HL + C]
Description
[Description example]
In the case of MOV A, [HL + B]
Operation code
3.4.9 Stack addressing
1 0 1 0 1 0 1 1
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call and RETURN instructions are executed or the register is saved/reset upon generation of an interrupt request.
Stack addressing enables to address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Operation code 1 0 1 1 0 1 0 1
52
CHAPTER 4 PORT FUNCTIONS
CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The
µ
PD78083 Subseries units incorporate an input port and thirty-two input/output ports. Figure 4-1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. Besides port functions, the ports can also serve as on-chip hardware input/output pins.
Figure 4-1. Port Types
P50
Port 5
P00
P03
P10
Port 0
Port 7
Port 10
P57
P70
P72
P100
P101
P17
P30
Port 1
Port 3
P37
53
CHAPTER 4 PORT FUNCTIONS
Table 4-1. Port Functions
Pin Name
P00
P01
P02
P03
P10-P17
P30-P34
P35
P36
P37
P50-P57
P70
P71
P72
P100
P101
Input/Output
Input Port 0
Function
Input only
Input/output 4-bit input/output port Input/output is specifiable bit-wise. When
Input/output Port 1
8-bit input/output port
Dual-Function Pin
—
INTP1 used as the input port, it is possible to connect INTP2 a pull-up resistor by software.
INTP3
ANI0-ANI7
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Input/output Port 3
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
PCL
BUZ
—
—
— Input/output Port 5
8-bit input/output port
A maximum of 7 out of 8 ports can drive LEDs directly.
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Input/output Port 7
3-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
Input/output Port 10
2-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect a pull-up resistor by software.
SI2/RxD
SO2/TxD
SCK2/ASCK
TI5/TO5
TI6/TO6
54
CHAPTER 4 PORT FUNCTIONS
4.2 Port Configuration
A port consists of the following hardware:
Item
Control register
Port
Pull-up resistor
Table 4-2. Port Configuration
Configuration
Port mode register (PMm: m = 0, 1, 3, 5, 7, 10)
Pull-up resistor option register (PUOH, PUOL)
Total: 33 ports (1 input, 32 inputs/outputs)
Total: 32 (software specifiable)
4.2.1 Port 0
Port 0 is an 4-bit input/output port with output latch. P01 to P03 pins can specify the input mode/output mode in
1-bit units with the port mode register 0 (PM0). P00 pin is input-only port. When P01 to P03 pins are used as input ports, an on-chip pull-up resistor can be used to them in 3-bit units with a pull-up resistor option register L (PUOL).
Dual-functions include external interrupt request input.
RESET input sets port 0 to input mode.
Figures 4-2 and 4-3 show block diagrams of port0.
Caution Because port 0 also serves for external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. Thus, when the output mode is used, set the interrupt mask flag to 1.
55
56
CHAPTER 4 PORT FUNCTIONS
Figure 4-2. P00 Block Diagram
RD
P00
Figure 4-3. P01 to P03 Block Diagram
WR
PUO
PUO0
RD
Selector
WR
PORT
Output Latch
(P01 to P03)
WR
PM
PM01-PM03
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 0 read signal
WR : Port 0 write signal
V
DD
P-ch
P01/INTP1
P03/INTP3
CHAPTER 4 PORT FUNCTIONS
4.2.2 Port 1
Port 1 is an 8-bit input/output port with output latch. It can specify the input mode/output mode in 1-bit units with a port mode register 1 (PM1). When P10 to P17 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Dual-functions include an A/D converter analog input.
RESET input sets port 1 to input mode.
Figure 4-4 shows a block diagram of port 1.
Caution A pull-up resistor cannot be used for pins used as A/D converter analog input.
Figure 4-4. P10 to P17 Block Diagram
V
DD
WR
PUO
PUO1
P-ch
RD
Selector
WR
PORT
Output Latch
(P10 to P17)
P10/ANI0
P17/ANI7
WR
PM
PM10-PM17
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 1 read signal
WR : Port 1 write signal
57
CHAPTER 4 PORT FUNCTIONS
4.2.3 Port 3
Port 3 is an 8-bit input/output port with output latch. P30 to P37 pins can specify the input mode/output mode in
1-bit units with the port mode register 3 (PM3). When P30 to P37 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
Dual-functions include clock output and buzzer output.
RESET input sets port 3 to input mode.
Figure 4-5 shows a block diagram of port 3.
Figure 4-5. P30 to P37 Block Diagram
V
DD
WR
PUO
PUO3
P-ch
RD
Selector
WR
PORT
Output Latch
(P30 to P37)
P30
P34,
P35/PCL,
P36/BUZ,
P37
WR
PM
PM30-PM37
Alternate Function
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 3 read signal
WR : Port 3 write signal
58
CHAPTER 4 PORT FUNCTIONS
4.2.4 Port 5
Port 5 is an 8-bit input/output port with output latch. P50 to P57 pins can specify the input mode/output mode in
1-bit units with the port mode register 5 (PM5). When P50 to P57 pins are used as input ports, an on-chip pull-up resistor can be used to them in 8-bit units with a pull-up resistor option register L (PUOL).
A maximum of 7 out of 8 ports can drive LEDs directly.
RESET input sets port 5 to input mode.
Figure 4-6 shows a block diagram of port 5.
Figure 4-6. P50 to P57 Block Diagram
V
DD
WR
PUO
PUO5
P-ch
RD
Selector
WR
PORT
Output Latch
(P50 to P57)
P50-P57
WR
PM
PM50-PM57
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 5 read signal
WR : Port 5 write signal
59
CHAPTER 4 PORT FUNCTIONS
4.2.5 Port 7
This is a 3-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 7 (PM7). When pins P70 to P72 are used as input port pins, an on-chip pull-up resistor can be used as a 3-bit unit by means of pull-up resistor option register L (PUOL).
Dual-functions include serial interface channel 2 data input/output and clock input/output.
RESET input sets the input mode.
Port 7 block diagrams are shown in Figures 4-7 and 4-8.
Caution When used as a serial interface, set the input/output and output latch according to its functions.
For the setting method, refer to Table 11-2 Serial Interface Channel 2 Operating Mode Settings.
Figure 4-7. P70 Block Diagram
V
DD
WR
PUO
PUO7
P-ch
RD
Selector
WR
PORT
Output Latch
(P70)
P70/SI2/RxD
WR
PM
PM70
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 7 read signal
WR : Port 7 write signal
60
CHAPTER 4 PORT FUNCTIONS
Figure 4-8. P71 and P72 Block Diagram
V
DD
WR
PUO
RD
PUO7
Selector
WR
PORT
Output Latch
(P71 and P72)
WR
PM
PM71, PM72
Alternate Function
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 7 read signal
WR : Port 7 write signal
P-ch
P71/SO2/TxD,
P72/SCK2/ASCK
61
CHAPTER 4 PORT FUNCTIONS
4.2.6 Port 10
This is an 2-bit input/output port with output latches. Input mode/output mode can be specified bit-wise by means of port mode register 10 (PM10). When pins P100 to P101 are used as input port pins, an on-chip pull-up resistor can be used as an 2-bit unit by means of pull-up resistor option register H (PUOH).
These pins are dual function pins and serve as timer inputs/outputs.
RESET input sets the input mode.
The port 10 block diagram is shown in Figure 4-9.
Figure 4-9. P100 to P101 Block Diagram
V
DD
WR
PUO
PUO10
P-ch
RD
Selector
WR
PORT
Output Latch
(P100 to P101)
P100/TI5/TO5,
P101/TI6/TO6
WR
PM
PM100 to PM101
Alternate
Functions
PUO : Pull-up resistor option register
PM : Port mode register
RD : Port 10 read signal
WR : Port 10 write signal
62
CHAPTER 4 PORT FUNCTIONS
4.3 Port Function Control Registers
The following two types of registers control the ports.
• Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10)
• Pull-up resistor option register (PUOH, PUOL)
(1) Port mode registers (PM0, PM1, PM3, PM5, PM7, PM10)
These registers are used to set port input/output in 1-bit units.
PM0, PM1, PM3, PM5, PM7, PM10 are independently set with a 1-bit or 8-bit memory manipulation instruction
RESET input sets registers to FFH.
When port pins are used as the dual-function pins, set the port mode register and output latch according to
Table 4-3.
Cautions 1. P00 pin is input-only pin.
2. As port 0 has a dual function as external interrupt request input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag should be set to
1 beforehand.
63
64
CHAPTER 4 PORT FUNCTIONS
Table 4-3. Port Mode Register and Output Latch Settings when Using Dual-Functions
P101
Pin Name
P01 to P03
P10 to P17 Note
P35
P36
P100
Dual-functions
Name Input/Output
INTP1 to INTP3
ANI0 to ANI7
PCL
BUZ
TI5
TO5
TI6
TO6
Input
Input
Output
Output
Input
Output
Input
Output
PM
××
1
0
1
0
0
0
1
1
P
××
0
×
0
×
0
×
×
0
Note If a read instruction is performed to these pins when they are used as an alternate function, read data is to be undefined.
Caution When port 7 is used for serial interface, the I/O latch or output latch must be set according to its function. For the setting methods, see Table 11-2 “Serial Interface Channel 2 Operating Mode
Settings.”
Remarks
×
: don’t care
PM
××
: port mode register
P
××
: port output latch
CHAPTER 4 PORT FUNCTIONS
Figure 4-10. Port Mode Register Format
Symbol
PM0
7
1
6
1
5
1
4
1
3 2 1 0
PM03 PM02 PM01 1
Address
FF20H
After
Reset
FFH
R/W
R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H
PM3 PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30 FF23H
FFH
FFH
R/W
R/W
PM5 PM57 PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H
PM7 1 1 1 1 1 PM72 PM71 PM70 FF27H
FFH R/W
FFH R/W
PM10 1 1 1 1 1 1 PM101 PM100 FF2AH FFH R/W
PMmn
0
Pmn Pin Input/Output Mode Selection
(m = 0, 1, 3, 5, 7, 10 : n = 0 to 7)
Output mode (output buffer ON)
1 Input mode (output buffer OFF)
Caution Set 1 to the bits 0, 4 to 7 of PM0, bits 3 to 7 of PM7 and bits 2 to 7 of PM10.
65
66
CHAPTER 4 PORT FUNCTIONS
(2) Pull-up resistor option register (PUOH, PUOL)
This register is used to set whether to use an internal pull-up resistor at each port or not. A pull-up resistor is internally used at bits which are set to the input mode at a port where on-chip pull-up resistor use has been specified with PUOH, PUOL. No on-chip pull-up resistors can be used to the bits set to the output mode or to the bits used as an analog input pin, irrespective of PUOH or PUOL setting.
PUOH and PUOL are set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets this register to 00H.
Cautions 1. P00 pin does not incorporate a pull-up resistor.
2. When port 1 is used as dual-function pin, an on-chip pull-up resistor cannot be used even if 1 is set in PUOL bit 1 (PUO1).
Figure 4-11. Pull-Up Resistor Option Register Format
Symbol
PUOH 0 0
5
0
5
4
0
4
PUOL PUO7 0 PUO5 0
3
0
3
PUO3
2 1
PUO10 0
2 1
0
0
0
0 PUO1 PUO0
Address
FFF3H
FFF7H
After
Reset
00H
00H
R/W
R/W
R/W
PUOm
Pm Internal Pull-up Resistor Selection
(m = 0, 1, 3, 5, 7, 10)
0 Internal pull-up resistor not used
1 Internal pull-up resistor used
Caution Set 0 to the bits 0, 1, 3 to 7 of PUOH and bits 2, 4, 6 of PUOL.
CHAPTER 4 PORT FUNCTIONS
4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to input/output port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is OFF, the pin status does not change.
Once data is written to the output latch, it is retained until data is written to the output latch again.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined except for the manipulated bit.
4.4.2 Reading from input/output port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not change.
4.4.3 Operations on input/output port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
(2) Input mode
The output latch contents are undefined, but since the output buffer is OFF, the pin status does not change.
Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit.
67
[MEMO]
CHAPTER 4 PORT FUNCTIONS
68
CHAPTER 5 CLOCK GENERATOR
CHAPTER 5 CLOCK GENERATOR
5.1 Clock Generator Functions
The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillator is available.
Main system clock oscillator
This circuit oscillates at frequencies of 1 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction.
5.2 Clock Generator Configuration
The clock generator consists of the following hardware.
Oscillator
Table 5-1. Clock Generator Configuration
Item
Control register
Configuration
Processor clock control register (PCC)
Oscillation mode selection register (OSMS)
Main system clock oscillator
69
70
CHAPTER 5 CLOCK GENERATOR
X1
X2
Figure 5-1. Block Diagram of Clock Generator
Prescaler
Main
System
Clock
Oscillator f
X
Scaler f
X
2
STOP
Prescaler f
XX f
XX
2 f
XX
2
2 f
XX
2
3 f
XX
2
4
Standby
Control
Circuit
3
MCS
Oscillation Mode
Selection Register
PCC2 PCC1 PCC0
Processor Clock Control Register
Internal Bus
Clock to
Peripheral
Hardware
CPU Clock
(f
CPU
)
CHAPTER 5 CLOCK GENERATOR
5.3 Clock Generator Control Register
The clock generator is controlled by the following two registers:
• Processor clock control register (PCC)
• Oscillation mode selection register (OSMS)
(1) Processor clock control register (PCC)
The PCC sets whether to use CPU clock selection and the ratio of division.
The PCC is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets the PCC to 04H.
Figure 5-2. Processor Clock Control Register Format
Symbol
PCC 0 0
5
0
4
0
3
0
2 1 0
PCC2 PCC1 PCC0
Address
FFFBH
After
Reset
04H
R/W
R/W
PCC2 PCC1 PCC0
CPU CIock Selection (f
CPU
)
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0 f f
XX
XX
/2 f
XX
/2 f
XX
/2 f
XX
/2
2
3
4
MCS=1 f x
(0.4 s) f x
/2 (0.8 s) f x
/2
2 f x
/2
3 f x
/2
4
Other than above Setting prohibited
Caution Set 0 to the bits 3 to 7.
MCS=0 f x
/2 (0.8 s) f x
/2
2 f x
/2
3 f x
/2
4 f x
/2
5
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillator frequency
3. MCS : Bit 0 of oscillation mode selection register (OSMS)
4. Figures in parentheses indicate minimum instruction execution time : 2f
CPU
when operating at f
X
= 5.0 MHz.
71
72
CHAPTER 5 CLOCK GENERATOR
(2) Oscillation mode selection register (OSMS)
This register specifies whether the clock output from the main system clock oscillator without passing through the scaler is used as the main system clock, or the clock output via the scaler is used as the main system clock.
OSMS is set with 8-bit memory manipulation instruction.
RESET input sets OSMS to 00H.
Symbol
OSMS
7
0
6
0
Figure 5-3. Oscillation Mode Selection Register Format
5
0
4
0
3
0
2
0
1
0
0
MCS
Address
FFF2H
After
Reset
00H
R/W
W
MCS Main System Clock Scaler Control
0 Scaler used
1 Scaler not used
Cautions 1. Writing to OSMS should be performed only immediately after reset signal release and before peripheral hardware operation starts. As shown in Figure 5-4 below, writing data (including same data as previous) to OSMS cause delay of main system clock cycle up to 2/f x
during the write operation. Therefore, if this register is written during the operation, in peripheral hardware which operates with the main system clock, a temporary error occurs in the count clock cycle of timer, etc. In addition, because the oscillation mode is changed by this register, the clocks for peripheral hardware as well as that for the CPU are switched.
Figure 5-4. Main System Clock Waveform due to Writing to OSMS
Write to OSMS
(MCS 0)
Max. 2/f
X f
XX
Operating at f
XX
= f
X
/2 (MCS = 0) Operating at f
XX
= f
X
/2 (MCS = 0)
2. When writing “1” to MCS, V
DD
must be 2.7 V or higher before the write execution.
Remarks f xx
: Main system clock frequency (fx or fx/2) f x
: Main system clock oscillation frequency
CHAPTER 5 CLOCK GENERATOR
5.4 System Clock Oscillator
5.4.1 Main system clock oscillator
The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 5.0 MHz) connected to the X1 and X2 pins.
External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.
Figure 5-5 shows an external circuit of the main system clock oscillator.
Figure 5-5. External Circuit of Main System Clock Oscillator
(a) Crystal and ceramic oscillation (b) External clock
IC
X2
X2
Crystal or
Ceramic Resonator
X1
External
Clock
µ
PD74HCU04
X1
Cautions 1. Do not execute the STOP instruction if an external clock is used. This is because the X2 pin is connected to V
DD
via a pull-up register.
2. When using a main system clock oscillator, carry out wiring in the broken line area in Figure
5-5 to prevent any effects from wiring capacities.
●
●
●
●
Minimize the wiring length.
Do not allow wiring to intersect with other signal conductors. Do not allow wiring to come near changing high current.
Set the potential of the grounding position of the oscillator capacitor to that of V
SS
. Do not ground to any ground pattern where high current is present.
Do not fetch signals from the oscillator.
Figure 5-6 shows examples of oscillator having bad connection.
73
74
CHAPTER 5 CLOCK GENERATOR
Figure 5-6. Examples of Oscillator with Bad Connection (1/2)
(a) Wiring of connection circuits is too long
(b) Signal conductors intersect with each other
PORTn
(n = 0, 1, 3, 5, 7, 10)
IC X2 X1 IC X2 X1
(c) Changing high current is too near a signal conductor
(d) Current flows through the grounding line of the ocsillator (potential at points A, B, and C fluctuate)
V
DD
IC X2 X1
IC X2 X1
Pnm
High
Current
A B
High
Current
C
CHAPTER 5 CLOCK GENERATOR
Figure 5-6. Examples of Oscillator with Bad Connection (2/2)
(c) Signals are fetched
IC X2 X1
5.4.2 Scaler
The scaler divides the main system clock oscillator output (f
XX
) and generates various clocks.
75
CHAPTER 5 CLOCK GENERATOR
5.5 Clock Generator Operations
The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode.
• Main system clock f
XX
• CPU clock f
CPU
• Clock to peripheral hardware
The following clock generator functions and operations are determined with the processor clock control register
(PCC) and the oscillation mode selection register (OSMS).
(a) Upon generation of RESET signal, the lowest speed mode of the main system clock (12.8
µ s when operated at 5.0 MHz) is selected (PCC = 04H, OSMS = 00H). Main system clock oscillation stops while low level is applied to RESET pin.
(b) The six types of CPU clocks (0.4
µ s. 0.8
µ s, 1.6
µ s, 3.2
µ s, 6.4
µ s, 12.8
µ s : 5.0 MHz) can be selected by setting the PCC and OSMS.
(c) Two standby modes, the STOP and HALT modes, are available.
(d) The main system clock is divided and supplied to the peripheral hardware. Thus, the peripheral hardware also stops if the main system clock is stopped. (Except external input clock operation)
76
CHAPTER 5 CLOCK GENERATOR
5.6 Changing CPU Clock Settings
5.6.1 Time required for CPU clock switchover
The CPU clock can be switched over by means of bits 0 to 2 (PCC0 to PCC2) of the processor clock control register
(PCC).
The actual switchover operation is not performed directly after writing to the PCC, but operation continues on the pre-switchover clock for several instructions (see Table 5-2).
Table 5-2. Maximum Time Required for CPU Clock Switchover
Set Values before
Switchover
Set Values After Switchover
PCC2 PCC1 PCC0
PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
0 0 0 16 instructions 16 instructions 16 instructions 16 instructions
0 0 1 8 instructions 8 instructions 8 instructions 8 instructions
0 1 0 4 instructions 4 instructions 4 instructions 4 instructions
0 1 1 2 instructions 2 instructions 2 instructions
1 0 0 1 instruction 1 instruction 1 instruction 1 instruction
2 instructions
Remark One instruction is the minimum instruction execution time with the pre-switchover CPU clock.
77
CHAPTER 5 CLOCK GENERATOR
5.6.2 CPU clock switching procedure
This section describes CPU clock switching procedure.
Figure 5-7. CPU Clock Switching
V
DD
RESET
CPU Clock
Minimum
Speed
Operation
Maximum Speed
Operation
Wait (26.2 ms : 5.0 MHz)
Internal Reset Operation
(1) The CPU is reset by setting the RESET signal to low level after power-on. After that, when reset is released by setting the RESET signal to high level, main system clock starts oscillation. At this time, oscillation stabilization time (2
17
/f
X
) is secured automatically.
After that, the CPU starts executing the instruction at the minimum speed of the main system clock (12.8
µ s when operated at 5.0 MHz).
(2) After the lapse of a sufficient time for the V
DD
voltage to increase to enable operation at maximum speeds, the processor clock control register (PCC) and oscillation mode selection register (OSMS) are rewritten and the maximum-speed operation is carried out.
78
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
The timers incorporated into the
µ
PD78083 subseries are outlined below.
(1) 8-bit timers/event counters 5 and 6 (TM5 and TM6)
This can be used to serve as an interval timer, an external event counter, square wave output with any selected frequency PWM, etc. It cannot be used as a 16-bit timer/event counter (See CHAPTER 6 8-BIT TIMER/EVENT
COUNTERS 5 AND 6).
(2) Watchdog timer (WDTM)
WDTM can perform the watchdog timer function or generate non-maskable interrupt requests, maskable interrupt requests and RESET at the preset time intervals (See CHAPTER 7 WATCHDOG TIMER).
(3) Clock output control circuit
This circuit supplies a clock obtained by dividing the main system clock, to other devices (See CHAPTER 8
CLOCK OUTPUT CONTROL CIRCUIT).
(4) Buzzer output control circuit
This circuit outputs the buzzer frequency obtained by dividing the main system clock (See CHAPTER 9
BUZZER OUTPUT CONTROL CIRCUIT).
Table 6-1 Timer/Event Counter Types and Functions
Type
Function
Interval timer
External event counter
Timer output
PWM output
Square-wave output
Interrupt request
8-bit Timer/Event Counters 5 and 6
2 channels
√
√
√
√
√
Watchdog Timer
1 channel
Note
—
—
—
—
√
Note Watchdog timer can perform either the watchdog timer function or the interval timer function.
79
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.1 8-Bit Timer/Event Counters 5 and 6 Functions
The 8-bit timer/event counters 5 and 6 (TM5 and TM6) have the following functions.
• Interval timer
• External event counter
• Square-wave output
• PWM output
(1) 8-bit interval timer
Interrupt requests are generated at the preset time intervals.
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Minimum Interval Time
MCS = 1 MCS = 0
—
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Table 6-2. 8-Bit Timer/Event Counters 5 and 6 Interval Times
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Maximum Interval Time
MCS = 1
—
MCS = 0
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Resolution
MCS = 1 MCS = 0
—
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. Values in parentheses when operated at f
X
= 5.0 MHz.
80
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(2) External event counter
The number of pulses of an externally input signal can be measured.
(3) Square-wave output
A square wave with any selected frequency can be output.
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Minimum pulse width
MCS = 1 MCS = 0
—
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Table 6-3. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Maximum pulse width
MCS = 1
—
MCS = 0
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Resolution
MCS = 1 MCS = 0
—
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. Values in parentheses when operated at f
X
= 5.0 MHz.
(4) PWM Output
TM5 and TM6 can generate 8-bit resolution PWM output.
81
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.2 8-Bit Timer/Event Counters 5 and 6 Configurations
The 8-bit timer/event counters 5 and 6 consist of the following hardware.
Table 6-4. 8-Bit Timer/Event Counters 5 and 6 Configurations
Timer register
Register
Item
Timer output
Configuration
8 bits
×
2 (TM5, TM6)
Compare register: 8 bits
×
2 (CR50, CR60)
2 (TO5, TO6)
Control register Timer clock select register 5 and 6 (TCL5, TCL6)
8-bit timer mode control register 5 and 6 (TMC5, TMC6)
Port mode register 10 (PM10)
Figure 6-1. 8-Bit Timer/Event Counters 5 and 6 Block Diagram
Internal Bus
2f xx
-f xx
/2 9 f xx
/2 11
TI5/P100/TO5,
TI6/P101/TO6
4
8-Bit Compare Register
(CRn0)
Match
8-Bit Timer Register n
(TMn)
OVF
Clear
Selector
2
Output Control
Circuit Note
INTTMn
TO5/P100/TI5,
TO6/P101/TI6
6
TCL n3
TCL n2
TCL n1
TCL n0
Timer Clock
Select Register n
TCEn
TMC n6
LVSn LVRn
TMC n1
TOEn
Internal Bus
8-Bit Timer Mode
Control Register n
Note Refer to Figures 6-2 for details of configurations of 8-bit timer/event counters 5 and 6 output control circuits.
Remark n = 5, 6
82
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
RESET
LVRn
LVSn
TMCn1
TMCn6
INTTMn
TCEn
INTTMn
OVFn
Figure 6-2. Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit
TMCn1 TMCn6
R
S
INV
Q
PWM Output Circuit
Timer Output F/F2
R
Q
S
Level
Invert
P100, P101
Output Latch
TO5/P100/TI5,
TO6/P101/TI6
PM100,
PM101 Note
TOEn
Note PM100 : Bit 0 of port mode register 10 (PM10)
PM101 : Bit 1 of PM10
Remarks 1. The section in the broken line is an output control circuit.
2. n = 5, 6
83
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(1) Compare registers 50 and 60 (CR50, CR60)
These are 8-bit registers to compare the value set to CR50 to the 8-bit timer register 5 (TM5) count value, and the value set to CR60 to the 8-bit timer register 6 (TM6) count value, and, if they match, generate an interrupt request (INTTM5 and INTTM6, respectively).
CR50 and CR60 are set with an 8-bit memory manipulation instruction. They cannot be set with a 16-bit memory manipulation instruction. The 00H to FFH values can be set.
RESET input sets CR50 and CR60 to 00H.
Caution When using the PWM mode, please set the CRn0 value before setting TMCn (n=5, 6) to the
PWM mode.
(2) 8-bit timer registers 5 and 6 (TM5, TM6)
These are 8-bit registers to count count pulses.
TM5 and TM6 are read with an 8-bit memory manipulation instruction.
RESET input sets TM5 and TM6 to 00H.
6.3 8-Bit Timer/Event Counters 5 and 6 Control Registers
The following three types of registers are used to control the 8-bit timer/event counter 5 and 6.
• Timer clock select register 5 and 6 (TCL5, TCL6)
• 8-bit timer mode control register 5 and 6 (TMC5, TMC6)
• Port mode register 10 (PM10)
(1) Timer clock select register 5 (TCL5)
This register sets count clocks of 8-bit timer register 5.
TCL5 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL5 to 00H.
84
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Figure 6-3. Timer Clock Select Register 5 Format
Symbol
TCL5
7
0
6
0
5
0
4 3 2 1 0
0 TCL53 TCL52 TCL51 TCL50
Address After Reset
FF52H 00H
R/W
R/W
TCL53 TCL52 TCL51 TCL50
8-Bit Timer Register 5 Count Clock Selection
MCS=1
0 0 0 0 TI5 falling edge Note
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1 1 1
Other than above
1
1 TI5 rising edge Note
0 2f
XX
Setting prohibited
1
0
1
0
1
0
1
0
1
0 f
XX f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7 f
XX
/2
8 f
XX
/2
9 f
XX
/2
11 f
X
(5.0 MHz) f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
11
(2.4 kHz)
Setting prohibited
MCS=0 f
X f
X
/2 f
X
/2
2 f
X
/2
3 f
X
/2
4 f
X
/2
5 f
X
/2
6 f
X
/2
7 f
X
/2
8 f
X
/2
9 f
X
/2
10 f
X
/2
12
(5.0 MHz)
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
Note The timer output (PWM output) cannot be used in cases where the clock is being input from an external source.
Caution When rewriting TCL5 to other data, stop the timer operation beforehand.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. TI5 : 8-bit timer register 5 input pin
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X
= 5.0 MHz
85
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(2) Timer clock select register 6 (TCL6)
This register sets count clocks of 8-bit timer register 6.
TCL6 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL6 to 00H.
Symbol
TCL6
7
0
6
0
5
0
Figure 6-4. Timer Clock Select Register 6 Format
4 3 2 1 0
0 TCL63 TCL62 TCL61 TCL60
Address After Reset
FF56H 00H
TCL63 TCL62 TCL61 TCL60
8-bit Timer Register 6 Count Clock Selection
MCS=1 MCS=0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
Other than above
0
1
0
1
0
1
0
1
0
0
1
0 TI6 falling edge
Note
1 TI6 rising edge
Note
1 f
2f
XX
XX f
Setting prohibited
X
(5.0 MHz) f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7 f
XX
/2
8 f
XX
/2
9 f
XX
/2
11
Setting prohibited f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
11
(2.4 kHz) f
X f
X
/2
5 f
X
/2
6 f
X
/2
7 f
X
/2
8 f
X
/2
9 f
X
/2
10 f
X
/2
12 f
X
/2 f
X
/2
2 f
X
/2
3 f
X
/2
4
(5.0 MHz)
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz)
(1.2 kHz)
Note When clock is input from the external, timer output (PWM output) cannot be used.
Caution When rewriting TCL6 to other data, stop the timer operation beforehand.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. TI6 : 8-bit timer register 6 input pin
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X
= 5.0 MHz
86
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(3) 8-bit timer mode control register 5 (TMC5)
This register enables/stops operation of 8-bit timer register 5, sets the operating mode of 8-bit timer register
5 and controls operation of 8-bit timer/event counter 5 output control circuit.
It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, the active level in PWM mode, inversion enabling/disabling in modes other than PWM mode and 8-bit timer/event counter 5 timer output enabling/ disabling.
TMC5 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC5 to 00H.
Symbol 7 6 5
TMC5 TCE5 TMC56 0
Figure 6-5. 8-Bit Timer Mode Control Register 5 Format
4 3 2 1 0
0 LVS5 LVR5 TMC51 TOE5
Address After Reset
FF53H 00H
R/W
R/W
TOE5
0
8-Bit Timer/Event Counter 5 Output Control
Output disabled (Port mode)
1 Output enabled
TMC51
0
1
In PWM Mode In Other Modes
Active level selection Timer output F/F1 control
Active high
Active low
Inversion operation disabled
Inversion operation enabled
LVS5 LVR5
0
0
1
1
0
1
0
1
8-Bit Timer/Event Counter 5 Timer
Output F/F1 Status Setting
No change
Timer output F/F1 reset (0)
Timer output F/F1 set (1)
Setting prohibited
TMC56 8-Bit Timer/Event Counter 5 Operating Mode Selection
0 Clear & start mode on match of TM5 and CR50
1 PWM mode (free-running)
TCE5
0
8-Bit Timer Register 5 Operation Control
Operation stop (TM5 clear to 0)
1 Operation enable
Cautions 1. Timer operation must be stopped before setting TMC5.
2. If LVS5 and LVR5 are read after data are set, they will be 0.
3. Set 0 to the bits 4 and 5.
87
88
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(4) 8-bit timer mode control register 6 (TMC6)
This register enables/stops operation of 8-bit timer register 6, sets the operating mode of 8-bit timer register
6 and controls operation of 8-bit timer/event counter 6 output control circuit.
It sets R-S type flip-flop (timer output F/F 1,2) setting/resetting, active level in PWM mode, inversion enabling/ disabling in modes other than PWM mode and 8-bit timer/event counter 6 timer output enabling/disabling.
TMC6 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TMC6 to 00H.
Figure 6-6. 8-Bit Timer Mode Control Register 6 Format
Symbol 7 6 5
TMC6 TCE6 TMC66 0
4 3 2 1 0
0 LVS6 LVR6 TMC61 TOE6
Address After Reset R/W
FF57H 00H R/W
TOE6
0
1
8-Bit Timer/Event Counter 6 Output Control
Output disabled (Port mode)
Output enabled
TMC61
0
1
In PWM Mode In Other Modes
Active level selection Timer output F/F1 control
Active high
Active low
Inversion operation disabled
Inversion operation enabled
LVS6 LVR6
0
0
1
1
0
1
0
1
8-Bit Timer/Event Counter 6 Timer
Output F/F1 Status Setting
No change
Timer output F/F1 reset (0)
Timer output F/F1 set (1)
Setting prohibited
TMC66 8-Bit Timer/Event Counter 6 Operating Mode Selection
0 Clear & start mode on match of TM6 and CR60
1 PWM mode (free-running)
TCE6 8-Bit Timer Register 6 Operation Control
0 Operation Stop (TM6 clear to 0)
1 Operation Enable
Cautions 1. Timer operation must be stopped before setting TMC6.
2. If LVS6 and LVR6 are read after data are set, they will be 0.
3. Set 0 to the bits 4 and 5.
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(5) Port mode register 10 (PM10)
This register sets port 10 input/output in 1-bit units.
When using the P100/TI5/TO5 and P101/TI6/TO6 pins for timer output, set PM100, PM101, and output latches of P100 and P101 to 0.
PM10 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM10 to FFH.
Symbol
PM10
7
1
6
1
5
1
4
1
Figure 6-7. Port Mode Register 10 Format
3
1
2
1
1 0
PM101 PM100
Address After Reset R/W
FF2AH FFH R/W
PM10n P10n Pin Input/Output Mode Selection (n = 0, 1)
0 Output mode (output buffer ON)
1 Input mode (output buffer OFF)
Caution Set 1 to the bits 2 to 7.
89
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.4 8-Bit Timer/Event Counters 5 and 6 Operations
6.4.1 Interval timer operations
By setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-8, it can be operated as an interval timer. The 8-bit timer/event counters 5 and 6 operate as interval timers which generate interrupt requests repeatedly at intervals of the count value preset to 8-bit compare registers 50 and 60 (CR50 and CR60).
When the count values of the 8-bit timer registers 5 and 6 (TM5 and TM6) match the values set to CR50 and CR60, counting continues with the TM5 and TM6 values cleared to 0 and the interrupt request signals (INTTM5 and INTTM6) are generated.
Count clock of TM5 can be selected with the timer clock select register 5 (TCL5). Count clock of TM6 can be selected with the timer clock select register 6 (TCL6).
Figure 6-8. 8-Bit Timer Mode Control Register Settings for Interval Timer Operation
TMCn
TCEn TMCn6
1 0 0 0
LVSn LVRn TMCn1 TOEn
0/1 0/1 0/1 0/1
Clear and start on match of TMn and CRn0
TMn operation enable
Remarks 1. 0/1 : Setting 0 or 1 allows another function to be used simultaneously with the interval timer.
See 6.3 (3), (4) for details.
2. n = 5, 6
90
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Figure 6-9. Interval Timer Operation Timings t
Count Clock
TMn Count Value 00 01
CRn0 N
N 00
Clear
01
N
N 00
Clear
01
N
TCEn
Count start
INTTMn
Interrupt Request
Acknowledge
Interrupt Request
Acknowledge
TOn
N
N
Interval Time Interval Time Interval Time
Remarks 1. Interval time = (N + 1)
×
t : N = 00H to FFH
2. n = 5, 6
91
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Table 6-5. 8-Bit Timer/Event Counters 5 and 6 Interval Times
Minimum Interval Time Maximum Interval Time Resolution
TCLn3 TCLn2 TCLn1 TCLn0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
Other than above
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MCS = 1 MCS = 0 MCS = 1 MCS = 0 MCS = 1 MCS = 0
TIn input cycle
TIn input cycle
Setting prohibited
2
1/f
×
X
(200 ns)
1/f
X
(400 ns)
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
8 ×
TIn input cycle
2
8 ×
TIn input cycle
Setting prohibited
2
8 ×
1/f
X
(51.2
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
(102.4
µ
X s)
2
9 ×
1/f
X
2
10 ×
1/f
X
(102.4
µ s) (204.8
µ s)
TIn input edge cycle
TIn input edge cycle
Setting prohibited
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
1/f
X
(200 ns)
2
(400 ns)
2
2
×
×
1/f
1/f
X
X
(800 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
2
(12.8
2
7 ×
1/f
X
(25.6
µ s)
2
4
6
8
×
(3.2
×
×
1/f
1/f
(51.2
µ
µ
µ s)
1/f
X
2
5 ×
1/f
X
(6.4
µ s)
X s)
X s)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
(3.2
1/f
µ s)
X
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
(12.8
µ
X s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
(51.2
µ
X s)
2
9 ×
1/f
X
(102.4
µ s)
2
9 ×
1/f
X
2
10 ×
1/f
X
(102.4
µ s) (204.8
µ s)
2
10 ×
1/f
X
2
11 ×
1/f
X
(204.8
µ s) (409.6
µ s)
2
11 ×
1/f
X
2
12 ×
1/f
X
(409.6
µ s) (819.2
µ s)
2
2
(3.28 ms)
2
(6.55 ms)
2
(13.1 ms)
2
12
14
15
16
17
×
×
×
×
×
1/f
(819.2
µ
1/f
1/f
1/f
1/f
X s)
2
13 ×
1/f
X
(1.64 ms)
X
X
X
X
(26.2 ms)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
2
2
16
17
18
×
×
×
1/f
1/f
1/f
X
(13.1 ms)
X
(26.2 ms)
X
(52.4 ms)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
2
(12.8
2
7 ×
1/f
X
(25.6
µ s)
2
4
6
8
×
(3.2
×
×
1/f
1/f
(51.2
µ
µ
µ s)
1/f
X
2
5 ×
1/f
X
(6.4
µ s)
X s)
X s)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
(3.2
1/f
µ s)
X
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
(12.8
1/f
µ
X s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
(51.2
1/f
µ
X s)
2
9 ×
1/f
X
(102.4
µ s)
2
9 ×
1/f
X
2
10 ×
1/f
X
(102.4
µ s) (204.8
µ s)
2
11 ×
1/f
X
2
12 ×
1/f
X
2
19 ×
1/f
X
2
20 ×
1/f
X
2
11 ×
1/f
X
2
12 ×
1/f
X
(409.6
µ s) (819.2
µ s) (104.9 ms) (209.7 ms) (409.6
µ s) (819.2
µ s)
Setting prohibited
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. Values in parentheses when operated at f
X
= 5.0 MHz.
4. n = 5, 6
92
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.4.2 External event counter operation
The external event counter counts the number of external clock pulses to be input to the TI5/PI00/TO5 and TI6/
P101/TO6 pins with 8-bit timer registers 5 and 6 (TM5 and TM6).
TM5 and TM6 are incremented each time the valid edge specified with the timer clock select register 5 and 6 (TCL5 and TCL6) is input. Either the rising or falling edge can be selected.
When the TM5 and TM6 counted values match the values of 8-bit compare registers 50 and 60 (CR50 and CR60),
TM5 and TM6 are cleared to 0 and the interrupt request signals (INTTM5 and INTTM6) are generated.
Figure 6-10. 8-Bit Timer Mode Control Register Setting for External Event Counter Operation
TMCn
TCEn TMCn6
1 0 0 0
LVSn LVRn TMCn1 TOEn
× × ×
0
TOn output disable
Clear and start mode on match of TMn and CRn0
TMn operation enable
Remarks 1. n = 5, 6
2.
×
: don’t care
Figure 6-11. External Event Counter Operation Timings (with Rising Edge Specification)
Count Clock
N-1 N 00 01 02 03 TMn Count Value 00 01 02 03 04 05
N CRn0
TCEn
INTTMn
Remarks 1. N = 00H to FFH
2. n = 5, 6
93
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.4.3 Square-wave output
This makes the value set in advance in the 8-bit conveyor register 50, 60 (CR50, CR60) to be the interval. It operates as a square wave output at the desired frequency.
The TO5/P100/TI5 or TO6/P101/TI6 pin output status is reversed at intervals of the count value preset to CR50 or CR60 by setting bit 1 (TMC51) and bit 0 (TOE5) of 8-bit timer output control register 5 (TMC5), or bit 1 (TMC61) and bit 0 (TOE6) of 8-bit timer mode control register 6 (TMC6) to 1.
This enables a square wave of any selected frequency to be output.
Figure 6-12. 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation
TMCn
TCEn TMCn6
1 0 0 0
LVSn LVRn TMCn1 TOEn
0/1 0/1 1 1
TOn output enable
Inversion of output on match of TMn and CRn0
Specifies timer output F/F1 initial value
Clear and start mode on match of TMn and CRn0
TMn operation enable
Caution When TI5/P100/TO5 or TI6/P101/TO6 pin is used as the timer output, set 0 to port mode register
(PM100 or PM101) and output latch (P100 or P101).
Remark n = 5, 6
94
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Minimum Pulse Width
MCS = 1 MCS = 0
— 1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Table 6-6. 8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Maximum Pulse Width
MCS = 1
—
MCS = 0
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
11 ×
1/f
X
(409.6
µ s)
2
12 ×
1/f
X
(819.2
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
11 ×
1/f
X
(409.6
µ s)
Resolution
MCS = 1 MCS = 0
— 1/f
X
(200 ns)
2
×
1/f
X
(400 ns)
2
2 ×
1/f
X
(800 ns)
2
3 ×
1/f
X
(1.6
µ s)
2
4 ×
1/f
X
(3.2
µ s)
2
5 ×
1/f
X
(6.4
µ s)
2
6 ×
1/f
X
(12.8
µ s)
2
7 ×
1/f
X
(25.6
µ s)
2
8 ×
1/f
X
(51.2
µ s)
2
9 ×
1/f
X
(102.4
µ s)
2
10 ×
1/f
X
(204.8
µ s)
2
12 ×
1/f
X
(819.2
µ s)
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
3. Values in parentheses when operated at f
X
= 5.0 MHz.
95
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.4.4 PWM output operations
Setting the 8-bit timer mode control registers 5 and 6 (TMC5 and TMC6) as shown in Figure 6-13 allows operation as PWM output. Pulses with the duty ratio determined by the values preset in the 8-bit compare registers 50 and
60 (CR50 and CR60) output from the TO5/P100/TI5 or TO6/P101/TI6 pin.
Select the active level of PWM pulse with bit 1 (TMC51) of 8-bit timer mode control register 5 (TMC5) or bit 1
(TMC61) of 8-bit timer mode control register 6 (TMC6).
This PWM pulse has an 8-bit resolution. The pulse can be converted into an analog voltage by integrating it with an external low-pass filter (LPF). Count clock of 8-bit timer register 5 (TM5) can be selected with timer clock select register 5 (TCL5) and count clock of 8-bit timer register 6 (TM6) can be selected with timer clock select register 6
(TCL6).
PWM output enable/disable can be selected with bit 0 (TOE5) of TMC5 or bit 0 (TOE6) of TMC6.
Figure 6-13. 8-Bit Timer Mode Control Register Settings for PWM Output Operation
TMCn
TCEn TMCn6
1 1 0 0
LVSn LVRn TMCn1 TOEn
× ×
0/1 1
TOn output enable
Sets active level
PWM mode
TMn operation enable
Remarks 1. n = 5, 6
2.
×
: don’t care
96
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Figure 6-14. PWM Output Operation Timing (Active high setting)
CRn0 Changing
(M
→
N)
Count Clock
TMn Count Value
CRn0
TCEn
INTTMn
OVFn
00
M
01 02 FF 00 01 02
N
N N+1 N+2 N+3 00
N
TOn
Inactive Level
Inactive Level Active Level Inactive Level
Remark n = 5, 6
Figure 6-15. PWM Output Operation Timings (CRn0 = 00H, active high setting)
CRn0 Changing
(M
→
00)
Count Clock
00 01 02 FF 00 01 02 FF 00 01 02 00 TMn Count Value
CRn0 M 00 00
TCEn
INTTMn
OVFn
TOn
Inactive Level Inactive Level
Remark n = 5, 6
97
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
Count Clock
TMn Count Value
CRn0
TCEn
INTTMn
OVFn
TOn
Figure 6-16. PWM Output Operation Timings (CRn0 = FFH, active high setting)
00
FF
01 02 FF 00 01 02
FF
FF 00 01 02 00
FF
Inactive Level Active Level
Inactive Level
Inactive Level
Active Level
Remark n = 5, 6
98
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
99
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
6.5 Cautions on 8-Bit Timer/Event Counters 5 and 6
(1) Timer start errors
An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This is because 8-bit timer registers 5 and 6 (TM5 and TM6) are started asynchronously with the count pulse.
Figure 6-18. 8-Bit Timer Registers 5 and 6 Start Timing
Count Pulse
TM5, TM6 Count Value 00H 01H 02H 03H 04H
Timer Start
(2) 8-bit compare register 50 and 60 setting
The 8-bit compare registers 50 and 60 (CR50 and CR60) can be set to 00H.
Thus, when these 8-bit compare registers are used as event counters, one-pulse count operation can be carried out.
Figure 6-19. External Event Counter Operation Timing
TI5, TI6, Input
CR50, CR60
TM5, TM6 Count Value
TO5, TO6
Interrupt Request Flag
00H
00H
00H 00H 00H
100
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
(3) Operation after compare register change during timer count operation
If the values after the 8-bit compare registers 50 and 60 (CR50 and CR60) are changed are smaller than those of 8-bit timer registers 5 and 6 (TM5 and TM6), TM5 and TM6 continue counting, overflow and then restart counting from 0. Thus, if the value (M) after CR50 and CR60 change is smaller than value (N) before the change, it is necessary to restart the timer after changing CR50 and CR60.
Figure 6-20. Timing after Compare Register Change during Timer Count Operation
Count Pulse
CR50, CR60
TM5, TM6 Count Value X-1
N
Remark N > X > M
X
M
FFH 00H 01H 02H
101
[MEMO]
CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6
102
CHAPTER 7 WATCHDOG TIMER
CHAPTER 7 WATCHDOG TIMER
7.1 Watchdog Timer Functions
The watchdog timer has the following functions.
• Watchdog timer
• Interval timer
Caution Select the watchdog timer mode or the interval timer mode with the watchdog timer mode register
(WDTM) (The watchdog timer and interval timer cannot be used at the same time).
(1) Watchdog timer mode
An inadvertent program loop is detected. Upon detection of the inadvertent program loop, a non-maskable interrupt request or RESET can be generated.
Table 7-1. Watchdog Timer Overrun Detection Times
Runaway Detection Time
2
11 ×
1/f
XX
2
12 ×
1/f
XX
2
13 ×
1/f
XX
2
14 ×
1/f
XX
2
15 ×
1/f
XX
2
16 ×
1/f
XX
2
17 ×
1/f
XX
2
19 ×
1/f
XX
MCS = 1
2
11 ×
1/f
X
(410
µ s)
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz.
MCS = 0
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
103
CHAPTER 7 WATCHDOG TIMER
(2) Interval timer mode
Interrupt requests are generated at the preset time intervals.
Table 7-2. Interval Times
Interval Time
2
11 ×
1/f
XX
2
12 ×
1/f
XX
2
13 ×
1/f
XX
2
14 ×
1/f
XX
2
15 ×
1/f
XX
2
16 ×
1/f
XX
2
17 ×
1/f
XX
2
19 ×
1/f
XX
MCS = 1
2
11 ×
1/f
X
(410
µ s)
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz.
CS = 0
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
104
CHAPTER 7 WATCHDOG TIMER
7.2 Watchdog Timer Configuration
The watchdog timer consists of the following hardware.
Item
Table 7-3. Watchdog Timer Configuration
Control register
Configuration
Timer clock select register 2 (TCL2)
Watchdog timer mode register (WDTM)
Figure 7-1. Watchdog Timer Block Diagram
Internal Bus f
XX
/2
3 f
XX
2
4 f
XX
2
5 f
XX
2
6
Prescaler f
XX
2
7 f
2
XX
8 f
2
XX
9 f
2
XX
11
3
TCL22 TCL21 TCL20
Timer Clock Select Register 2
RUN
8-Bit Counter
TMMK4
Control
Circuit
TMIF4
WDTM4 WDTM3
Watchdog Timer Mode Register
INTWDT
Maskable
Interrupt
Request
RESET
INTWDT
Non-Maskable
Interrupt
Request
Internal Bus
105
CHAPTER 7 WATCHDOG TIMER
7.3 Watchdog Timer Control Registers
The following two types of registers are used to control the watchdog timer.
• Timer clock select register 2 (TCL2)
• Watchdog timer mode register (WDTM)
(1) Timer clock select register 2 (TCL2)
This register sets the watchdog timer count clock.
TCL2 is set with 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Remark Besides setting the watchdog timer count clock, TCL2 sets the buzzer output frequency.
106
CHAPTER 7 WATCHDOG TIMER
Figure 7-2. Timer Clock Select Register 2 Format
Symbol 7 6 5 4
TCL2 TCL27 TCL26 TCL25 0
3
0
2 1 0
TCL22 TCL21 TCL20
Address
FF42H
After
Reset
00H
R/W
R/W
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
MCS=1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1 f f f
XX f
XX
/2
4
XX f
XX
/2
6
XX
/2
/2
/2 f
XX
/2
8
3
5
7 f f
X
/2
3
(625 kHz)
X
/2 f
X
/2
5
(156 kHz) f
X
/2
4
6
(313 kHz)
(78.1 kHz) f
X
/2
7
(39.1 kHz)
1
1
1
1
0
1 f
XX
/2 f
XX
/2
9
11 f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
11
(2.4 kHz)
MCS=0 f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
10
(4.9 kHz) f
X
/2
12
(1.2 kHz)
TCL27 TCL26 TCL25
Buzzer Output Frequency Selection
MCS=1
0
1
×
0
×
0
Buzzer output disable f
XX
/2
9 f
X
/2
9
(9.8 kHz)
1
1
0
1
1
0 f
XX
/2
10 f
XX
/2
11 f
X
/2
10
(4.9 kHz) f
X
/2
11
(2.4 kHz)
1 1 1 Setting prohibited
MCS=0 f
X
/2
10
(4.9 kHz) f
X
/2
11
(2.4 kHz) f
X
/2
12
(1.2 kHz)
Caution 1. When rewriting TCL2 to other data, stop the timer operation beforehand.
2. Set 0 to the bits 3 and 4.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
3.
×
: Main system clock oscillation frequency
: Don’t care
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X
= 5.0 MHz.
107
CHAPTER 7 WATCHDOG TIMER
(2) Watchdog timer mode register (WDTM)
This register sets the watchdog timer operating mode and enables/disables counting.
WDTM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets WDTM to 00H.
Symbol 7
WDTM RUM
6
0
Figure 7-3. Watchdog Timer Mode Register Format
5 4 3
0 WDTM4 WDTM3
2
0
1
0
0
0
Address
FFF9H
After
Reset
00H
R/W
R/W
WDTM4 WDTM3
Watchdog Timer Operation Mode
Selection Note 1
0
1
1
×
0
1
Interval timer mode Note 2
(Maskable interrupt occurs upon generation of an overflow.)
Watchdog timer mode 1
(Non-maskable interrupt occurs upon generation of an overflow.)
Watchdog timer mode 2
(Reset operation is activated upon generation of an overflow.)
RUN
0
1
Watchdog Timer Operation Mode Selection Note 3
Count stop
Counter is cleared and counting starts.
Notes 1. Once set to 1, WDTM3 and WDTM4 cannot be cleared to 0 by software.
2. The watchdog timer starts operating as an interval timer as soon as RUN has been set to 1.
3. Once set to 1, RUN cannot be cleared to 0 by software.
Thus, once counting starts, it can only be stopped by RESET input.
Cautions 1. When 1 is set in RUN so that the watchdog timer is cleared, the actual overflow time is up to 0.5 % shorter than the time set by timer clock select register 2.
2. To use watchdog timer modes 1 and 2, make sure that the interrupt request flag (TMIF4) is 0, and then set WDTM4 to 1.
If WDTM4 is set to 1 when TMIF4 is 1, the non-maskable interrupt request occurs, regardless of the contents of WDTM3.
Remark
×
: Don’t care
108
CHAPTER 7 WATCHDOG TIMER
7.4 Watchdog Timer Operations
7.4.1 Watchdog timer operation
When bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1, the watchdog timer is operated to detect any inadvertent program loop.
The watchdog timer count clock (inadvertent program loop detection time interval) can be selected with bits 0 to
2 (TCL20 to TCL22) of the timer clock select register 2 (TCL2).
Watchdog timer starts by setting bit 7 (RUN) of WDTM to 1. After the watchdog timer is started, set RUN to 1 within the set overrun detection time interval. The watchdog timer can be cleared and counting is started by setting
RUN to 1. If RUN is not set to 1 and the inadvertent program loop detection time is past, system reset or a non-maskable interrupt request is generated according to the WDTM bit 3 (WDTM3) value.
By setting RUN to 1, the watchdog timer can be cleared.
The watchdog timer continues operating in the HALT mode but it stops in the STOP mode. Thus, set RUN to 1 before the STOP mode is set, clear the watchdog timer and then execute the STOP instruction.
Caution The actual overrun detection time may be shorter than the set time by a maximum of
0.5 %.
Table 7-4. Watchdog Timer Overrun Detection Time
TCL22 TCL21 TCL20 Runaway Detection Time
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
11 ×
1/f
XX
2
12 ×
1/f
XX
2
13 ×
1/f
XX
2
14 ×
1/f
XX
2
15 ×
1/f
XX
2
16 ×
1/f
XX
2
17 ×
1/f
XX
2
19 ×
1/f
XX
MCS = 1
2
11 ×
1/f
X
(410
µ s)
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz.
MCS = 0
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
109
CHAPTER 7 WATCHDOG TIMER
7.4.2 Interval timer operation
The watchdog timer operates as an interval timer which generates interrupt requests repeatedly at an interval of the preset count value when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 0.
A count clock (interval time) can be selected by the bits 0 to 2 (TCL20 to TCL22) of the timer clock select register
2 (TCL2). By setting the bit 7 (RUN) of WDTM to 1, the watchdog timer starts operating as an interval timer.
When the watchdog timer operated as interval timer, the interrupt mask flag (TMMK4) and priority specify flag
(TMPR4) are validated and the maskable interrupt request (INTWDT) can be generated. Among maskable interrupt requests, the INTWDT default has the highest priority.
The interval timer continues operating in the HALT mode but it stops in STOP mode. Thus, set bit 7 (RUN) of
WDTM to 1 before the STOP mode is set, clear the interval timer and then execute the STOP instruction.
Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (with the watchdog timer mode selected), the interval timer mode is not set unless RESET input is applied.
2. The interval time just after setting with WDTM may be shorter than the set time by a maximum of 0.5 %.
TCL22 TCL21 TCL20
0 0 0
1
1
0
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Table 7-5. Interval Timer Interval Time
Interval Time
2
11 ×
1/f
XX
2
12 ×
1/f
XX
2
13 ×
1/f
XX
2
14 ×
1/f
XX
2
15 ×
1/f
XX
2
16 ×
1/f
XX
2
17 ×
1/f
XX
2
19 ×
1/f
XX
MCS = 1
2
11 ×
1/f
X
(410
µ s)
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
19 ×
1/f
X
(104.9 ms)
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz.
MCS = 0
2
12 ×
1/f
X
(819
µ s)
2
13 ×
1/f
X
(1.64 ms)
2
14 ×
1/f
X
(3.28 ms)
2
15 ×
1/f
X
(6.55 ms)
2
16 ×
1/f
X
(13.1 ms)
2
17 ×
1/f
X
(26.2 ms)
2
18 ×
1/f
X
(52.4 ms)
2
20 ×
1/f
X
(209.7 ms)
110
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
8.1 Clock Output Control Circuit Functions
The clock output control circuit is intended for carrier output during remote controlled transmission and clock output for supply to peripheral LSI. Clocks selected with the timer clock select register 0 (TCL0) are output from the PCL/
P35 pin.
Follow the procedure below to output clock pulses.
(1) Select the clock pulse output frequency (with clock pulse output disabled) with bits 0 to 3 (TCL00 to TCL03) of TCL0.
(2) Set the P35 output latch to 0.
(3) Set bit 5 (PM35) of port mode register 3 to 0 (set to output mode).
(4) Set bit 7 (CLOE) of timer clock select register 0 to 1.
Caution Clock output cannot be used when setting P35 output latch to 1.
Remark When clock output enable/disable is switched, the clock output control circuit does not output pulses with small widths (See the portions marked with * in Figure 8-1).
Figure 8-1. Remote Controlled Output Application Example
CLOE
PCL/P35 Pin Output
* *
111
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
8.2 Clock Output Control Circuit Configuration
The clock output control circuit consists of the following hardware.
Table 8-1. Clock Output Control Circuit Configuration
Item
Control register
Configuration
Timer clock select register 0 (TCL0)
Port mode register 3 (PM3)
Figure 8-2. Clock Output Control Circuit Block Diagram f
XX f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7
Synchronizing
Circuit
4
CLOE TCL03 TCL02 TCL01 TCL00
P35
Output Latch
Timer Clock Select Register 0
Internal Bus
PCL /P35
PM35
Port Mode Register 3
112
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
8.3 Clock Output Function Control Registers
The following two types of registers are used to control the clock output function.
• Timer clock select register 0 (TCL0)
• Port mode register 3 (PM3)
(1) Timer clock select register 0 (TCL0)
This register sets PCL output clock.
TCL0 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets TCL0 to 00H.
Symbol 7
TCL0 CLOE
6
0
5
0
Figure 8-3. Timer Clock Select Register 0 Format
4
0
3 2 1 0
TCL03 TCL02 TCL01 TCL00
Address
FF40H
After
Reset
00H
R/W
R/W
TCL03 TCL02 TCL01 TCL00
PCL Output Clock Selection
MCS=1
0 1 1 f
X
(5.0 MHz)
0
0
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
Other than above
0
1
0
1
0
1
0 f
XX f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7
Setting prohibited f
X
/2 (2.5 MHz) f
X
/2
2 f
X
/2
3 f
X
/2
4 f
X
/2
5 f
X
/2
6 f
X
/2
7
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
MCS=0 f
X
/2 (2.5 MHz) f
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz) f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz)
CLOE PCL Output Control
0 Output disable
1 Output enable
Cautions 1. When enabling PCL output, set TCL00 to TCL03, then set 1 in CLOE with a 1-bit memory manipulation instruction.
2. When rewriting TCL0 to other data, stop the clock operation beforehand.
3. Set 0 to bits 4 to 6.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz.
113
CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT
(2) Port mode register 3 (PM3)
This register set port 3 input/output in 1-bit units.
When using the P35/PCL pin for clock output function, set PM35 and output latch of P35 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 8-4. Port Mode Register 3 Format
Symbol
PM3
7 6 5 4 3 2 1 0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
Address
FF23H
After
Reset
FFH
R/W
R/W
PM3n P3n Pin Input/Output Mode Selection (n=0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
114
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
9.1 Buzzer Output Control Circuit Functions
The buzzer output control circuit outputs 1.2 kHz, 2.4 kHz, 4.9 kHz, or 9.8 kHz frequency square waves. The buzzer frequency selected with timer clock select register 2 (TCL2) is output from the BUZ/P36 pin.
Follow the procedure below to output the buzzer frequency.
(1) Select the buzzer output frequency with bits 5 to 7 (TCL25 to TCL27) of TCL2.
(2) Set the P36 output latch to 0.
(3) Set bit 6 (PM36) of port mode register 3 to 0 (Set to output mode).
Caution Buzzer output cannot be used when setting P36 output latch to 1.
9.2 Buzzer Output Control Circuit Configuration
The buzzer output control circuit consists of the following hardware.
Table 9-1. Buzzer Output Control Circuit Configuration
Item
Control register
Configuration
Timer clock select register 2 (TCL2)
Port mode register 3 (PM3)
Figure 9-1. Buzzer Output Control Circuit Block Diagram f
XX
/2
9 f
XX
/2
10 f
XX
/2
11
BUZ/P36
3
TCL27 TCL26 TCL25
Timer Clock Select Register 2
P36
Output Latch
Internal Bus
PM36
Port Mode Register 3
115
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
9.3 Buzzer Output Function Control Registers
The following two types of registers are used to control the buzzer output function.
• Timer clock select register 2 (TCL2)
• Port mode register 3 (PM3)
(1) Timer clock select register 2 (TCL2)
This register sets the buzzer output frequency.
TCL2 is set with an 8-bit memory manipulation instruction.
RESET input sets TCL2 to 00H.
Remark Besides setting the buzzer output frequency, TCL2 sets the watchdog timer count clock.
116
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
Figure 9-2. Timer Clock Select Register 2 Format
Symbol 7 6 5 4
TCL2 TCL27 TCL26 TCL25 0
3
0
2 1 0
TCL22 TCL21 TCL20
Address
FF42H
After
Reset
00H
R/W
R/W
TCL22 TCL21 TCL20
Watchdog Timer Count Clock Selection
MCS=1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1 f f f
XX f
XX
/2
4
XX f
XX
/2
6
XX
/2
/2
/2 f
XX
/2
8
3
5
7 f
X
/2
3
(625 kHz) f
X
/2 f
X
/2
5
(156 kHz) f
X
/2
4
6
(313 kHz)
(78.1 kHz) f
X
/2
7
(39.1 kHz)
1
1
1
1
0
1 f
XX
/2 f
XX
/2
9
11 f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
11
(2.4 kHz)
MCS=0 f
X
/2
4
(313 kHz) f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
10
(4.9 kHz) f
X
/2
12
(1.2 kHz)
TCL27 TCL26 TCL25
Buzzer Output Frequency Selection
MCS=1
0
1
×
0
×
0
Buzzer output disable f
XX
/2
9 f
X
/2
9
(9.8 kHz)
1
1
0
1
1
0 f
XX
/2
10 f
XX
/2
11 f
X
/2
10
(4.9 kHz) f
X
/2
11
(2.4 kHz)
1 1 1 Setting prohibited
MCS=0 f
X
/2
10
(4.9 kHz) f
X
/2
11
(2.4 kHz) f
X
/2
12
(1.2 kHz)
Cautions 1. When rewriting TCL2 to other data, stop the timer operation beforehand.
2. Set 0 to bits 3 and 4.
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
3.
×
: Main system clock oscillation frequency
: don’t care
4. MCS : Oscillation mode selection register (OSMS) bit 0
5. Values in parentheses when operated at f
X
= 5.0 MHz
117
CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT
(2) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P36/BUZ pin for buzzer output function, set PM36 and output latch of P36 to 0.
PM3 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PM3 to FFH.
Figure 9-3. Port Mode Register 3 Format
Symbol
PM3
7 6 5 4 3 2 1 0
PM37 PM36 PM35 PM34 PM33 PM32 PM31 PM30
Address
FF23H
After
Reset
FFH
R/W
R/W
PM3n P3n Pin Input/Output Mode Selection (n=0 to 7)
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
118
CHAPTER 10 A/D CONVERTER
CHAPTER 10 A/D CONVERTER
10.1 A/D Converter Functions
The A/D converter converts an analog input into a digital value. It consists of 8 channels (ANI0 to ANI7) with an
8-bit resolution.
The conversion method is based on successive approximation and the conversion result is held in the 8-bit A/D conversion result register (ADCR).
The following two ways are available to start A/D conversion.
(1) Hardware start
Conversion is started by trigger input (INTP3).
(2) Software start
Conversion is started by setting the A/D converter mode register.
Select 1 channel of analog input from ANI0 to ANI7 and perform A/D conversion. As for A/D conversion operations, when the hardware is started up, the A/D conversion operation stops when A/D conversion is completed, and an interrupt request (INTAD) is generated. In the case of software start, the A/D conversion operation is repeated. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.
10.2 A/D Converter Configuration
The A/D converter consists of the following hardware.
Register
Table 10-1. A/D Converter Configuration
Item
Analog input
Control register
Configuration
8 Channels (ANI0 to ANI7)
A/D converter mode register (ADM)
A/D converter input select register (ADIS)
External interrupt mode register 1 (INTM1)
Successive approximation register (SAR)
A/D conversion result register (ADCR)
119
CHAPTER 10 A/D CONVERTER
Figure 10-1. A/D Converter Block Diagram
Internal Bus
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
A / D Converter Input Select Register
ADIS3 ADIS2 ADIS1 ADIS0
4
Note 1 Note 2
Sample & Hold Circuit
3
Successive
Approximation
Register (SAR)
Voltage
Series Resistor String
AV
DD
AV
REF
Comparator
AV
SS
INTP3/P03
Edge
Detector
Control
Circuit
ES40, ES41
Note 3
Trigger Enable
CS TRG FR1 FR0 ADM3 ADM2 ADM1 HSC
A /D Converter Mode Register
A / D Conversion
Result Register
(ADCR)
Internal Bus
Notes 1. Selector to select the number of channels to be used for analog input.
2. Selector to select the channel for A/D conversion.
3. External interrupt mode register 1 (INTM1) bits 0 and 1.
INTAD
INTP3
120
CHAPTER 10 A/D CONVERTER
(1) Successive approximation register (SAR)
This register compares the analog input voltage value to the voltage tap (compare voltage) value applied from the series resistor string and holds the result from the most significant bit (MSB).
When held to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR are transferred to the A/D conversion results register.
(2) A/D conversion result register (ADCR)
This register holds the A/D conversion result. Each time A/D conversion terminates, the conversion result is loaded from the successive approximation register.
ADCR is read with an 8-bit memory manipulation instruction.
RESET input makes ADCR undefined.
(3) Sample & hold circuit
The sample & hold circuit samples each analog input signal sequentially applied from the input circuit and sends it to the voltage comparator. This circuit holds the sampled analog input voltage value during A/D conversion.
(4) Voltage comparator
The voltage comparator compares the analog input to the series resistor string output voltage.
(5) Series resistor string
The series resistor string is connected within AV
REF
to AV
SS
and generates a voltage for comparison with the analog input.
(6) ANI0 to ANI7 pins
These are 8-channel analog input pins to input analog signals to undergo A/D conversion to the A/D converter.
Pins other than those selected as analog input by the A/D converter input select register (ADIS) can be used as input/output ports.
Caution Use ANI0 to ANI7 input voltages within the specified range. If a voltage higher than AV
REF or lower than AV
SS
is applied (even if within the absolute maximum ratings), the converted value of the corresponding channel becomes indeterminate and may adversely affect the converted values of other channels.
(7) AV
REF
pin
This pin inputs the A/D converter reference voltage.
It converts signals input to ANI0 to ANI7 into digital signals according to the voltage applied between AV
REF and AV
SS
.
The current flowing in the series resistor string can be reduced by setting the voltage to be input to the AV
REF pin to AV
SS
level in standby mode.
(8) AV
SS
pin
This is a GND potential pin of the A/D converter. Keep it at the same potential as the V
SS
pin when not using the A/D converter.
(9) AV
DD
pin
This is an A/D converter analog power supply pin. Keep it at the same potential as the V
SS
pin when not using the A/D converter.
121
CHAPTER 10 A/D CONVERTER
10.3 A/D Converter Control Registers
The following three types of registers are used to control the A/D converter.
• A/D converter mode register (ADM)
• A/D converter input select register (ADIS)
• External interrupt mode register 1 (INTM1)
(1) A/D converter mode register (ADM)
This register sets the analog input channel for A/D conversion, conversion time, conversion start/stop and external trigger.
ADM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ADM to 01H.
122
CHAPTER 10 A/D CONVERTER
Figure 10-2. A/D Converter Mode Register Format
Symbol
ADM
7
CS
6
TRG
5 4 3 2 1 0
FR1 FR0 ADM3 ADM2 ADM1 HSC
Address
FF80H
After
Reset
01H
R/W
R/W
ADM3 ADM2 ADM1
0 0 0
Analog Input Channel Selection
ANI0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
FR1
0
0
1
1
FR0
0
1
0
0
A/D Conversion Time Selection
Note 1
HSC f
X
=5.0 MHz Operation
1
1
0
1
Other than above
MCS=1 MCS=0
80/f
X
( Setting prohibited
Note 2
) 160/f
X
(32.0 s)
40/f
X
( Setting prohibited
Note 2
) 80/f
X
( Setting prohibited
Note 2
)
50/f
X
( Setting prohibited
Note 2
) 100/f
X
(20.0 s)
100/f
X
(20.0 s) 200/f
X
(40.0 s)
MCS=1
80/f
40/f
X
X
(19.1 s)
( Setting prohibited
Note 2
50/f
X
( Setting prohibited
Note 2
)
100/f
X
(23.8 s)
)
MCS=0
160/f
X
(38.1 s)
80/f
X
(19.1 s)
100/f
X
(23.8 s)
200/f
X
(47.7 s)
Setting prohibited f
X
=4.19 MHz Operation
TRG
0
1
External Trigger Selection
No external trigger (software starts)
Conversion started by external trigger (hardware starts)
CS
0
1
A/D Conversion Operation Control
Operation stop
Operation start
Notes 1. Set so that the A/D conversion time is 19.1
µ s or more.
2. Setting prohibited because A/D conversion time is less than 19.1
µ s.
Cautions 1. The following sequence is recommended for power consumption reduction of A/D converter when the standby function is used: Clear bit 7 (CS) to 0 first to stop the
A/D conversion operation, and then execute the HALT or STOP instruction.
2. When restarting the stopped A/D conversion operation, start the A/D conversion operation after clearing the interrupt request flag (ADIF) to 0.
Remarks 1. f
X
: Main system clock oscillation frequency
2. MCS : Oscillation mode selection register (OSMS) bit 0
123
CHAPTER 10 A/D CONVERTER
(2) A/D converter input select register (ADIS)
This register determines whether the ANI0/P10 to ANI7/P17 pins should be used for analog input channels or ports. Pins other than those selected as analog input can be used as input/output ports.
ADIS is set with an 8-bit memory manipulation instruction.
RESET input sets ADIS to 00H.
Cautions 1. Set the analog input channel in the following order.
(1) Set the number of analog input channels with ADIS.
(2) Using A/D converter mode register (ADM), select one channel to undergo A/D conversion from among the channels set for analog input with ADIS.
2. No internal pull-up resistor can be used to the channels set for analog input with ADIS, irrespective of the value of bit 1 (PUO1) of the pull-up resistor option register L (PUOL).
Symbol
ADIS
7
0
Figure 10-3. A/D Converter Input Select Register Format
6
0
5
0
4
0
3 2 1 0
ADIS3 ADIS2 ADIS1 ADIS0
Address
FF84H
After
Reset
00H
R/W
R/W
ADIS3 ADIS2 ADIS1 ADIS0 Number of Analog Input Channel Selection
0 0
0
0
0
0
0 1
No analog input channel (P10-P17)
1 channel (ANI0, P11-P17)
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
1
0
1
1 0
1
1
0 0
Other than above
1
0
1
0
2 channel (ANI0, ANI1, P12-P17)
3 channel (ANI0-ANI2, P13-P17)
4 channel (ANI0-ANI3, P14-P17)
5 channel (ANI0-ANI4, P15-P17)
6 channel (ANI0-ANI5, P16, P17)
7 channel (ANI0-ANI6, P17)
8 channel (ANI0-ANI7)
Setting prohibited
124
CHAPTER 10 A/D CONVERTER
(3) External interrupt mode register 1 (INTM1)
This register sets the valid edge for INTP3.
INTM1 is set with an 8-bit memory manipulation instruction.
RESET input sets INTM1 to 00H.
Symbol
INTM1
7
0
6
0
5
0
Figure 10-4. External Interrupt Mode Register 1 Format
4
0
3
0
2 1 0
0 ES41 ES40
Address
FFEDH
After
Reset
00H
R/W
R/W
ES41 ES40 INTP3 Valid Edge Selection
0 0 Falling edge
0
1
1
1
0
1
Rising edge
Setting prohibited
Both falling and rising edges
Caution Set 0 to the bits 2 to 7.
125
CHAPTER 10 A/D CONVERTER
10.4 A/D Converter Operations
10.4.1 Basic operations of A/D converter
(1) Set the number of analog input channels with A/D converter input select register (ADIS).
(2) From among the analog input channels set with ADIS, select one channel for A/D conversion with A/D converter mode register (ADM).
(3) Sample the voltage input to the selected analog input channel with the sample & hold circuit.
(4) Sampling for the specified period of time sets the sample & hold circuit to the hold state so that the circuit holds the input analog voltage until termination of A/D conversion.
(5) Bit 7 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set at
(1/2) AV
REF
by the tap selector.
(6) The voltage difference between the series resistor string voltage tap and the analog input is compared by the voltage comparater. If the analog input is larger than (1/2) AV
REF
, the MSB of the SAR remains set. If it is smaller than (1/2) AV
REF
, the MSB is reset.
(7) Next, bit 6 of SAR is automatically set and the operation proceeds to the next comparison. In this case, the series resistor string voltage tap is selected according to the preset value of bit 7 as described below.
• Bit 7 = 1 : (3/4) AV
REF
• Bit 7 = 0 : (1/4) AV
REF
The voltage tap and analog input voltage are compared and bit 6 of SAR is manipulated with the result as follows.
• Analog input voltage
≥
Voltage tap : Bit 6 = 1
• Analog input voltage
≤
Voltage tap : Bit 6 = 0
(8) Comparison of this sort continues up to bit 0 of SAR.
(9) Upon completion of the comparison of 8 bits, any effective digital resultant value remains in SAR and the resultant value is transferred to and latched in the A/D conversion result register (ADCR).
At the same time, the A/D conversion termination interrupt request (INTAD) can also be generated.
126
CHAPTER 10 A/D CONVERTER
Sampling Time
Figure 10-5. A/D Converter Basic Operation
Conversion
Time
A/D Converter
Operation
Sampling
SAR
Undefined 80H
C0H or
40H
ADCR
A /D Conversion
INTAD
Conversion
Result
Conversion
Result
A/D conversion operations are performed continuously until bit 7 (CS) of A/D converter mode register (ADM) is reset (0) by software.
If a write to the ADM is performed during an A/D conversion operation, the conversion operation is initialized, and if the CS bit is set (1), conversion starts again from the beginning.
After RESET input, the value of ADCR is undefined.
127
CHAPTER 10 A/D CONVERTER
10.4.2 Input voltage and conversion results
The relation between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (the value stored in A/D conversion result register (ADCR)) is shown by the following expression.
V
IN
ADCR = INT (
AV
REF
×
256 + 0.5) or
(ADCR – 0.5)
×
AV
REF
256
≤
V
IN
< (ADCR + 0.5)
× AV
REF
256
Where, INT( ) : Function which returns integer parts of value in parentheses.
V
IN
: Analog input voltage
AV
REF
: AV
REF
pin voltage
ADCR : Value of A/D conversion result register (ADCR)
Figure 10-6 shows the relation between the analog input voltage and the A/D conversion result.
Figure 10-6. Relations between Analog Input Voltage and A/D Conversion Result
255
254
A/D Conversion
Results
(ADCR)
253
3
2
1
0
1
512
1
256
3
512
2
256
5
512
3
256
507
512
254
256
509
512
255
256
511
512
Input Voltage/AV
REF
1
128
CHAPTER 10 A/D CONVERTER
10.4.3 A/D converter operating mode
Using the A/D converter input select register (ADIS) and the A/D converter mode register (ADM), select one channel for the analog input from ANI0 to ANI7 and start A/D conversion.
The following two ways are available to start A/D conversion.
• Hardware start: Conversion is started by trigger input (INTP3).
• Software start: Conversion is started by setting ADM.
The A/D conversion result is stored in the A/D conversion result register (ADCR) and the interrupt request signal
(INTAD) is simultaneously generated.
(1) A/D conversion by hardware start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 1, the A/D conversion standby state is set. When the external trigger signal (INTP3) is input, the A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, another operation is not started until a new external trigger signal is input.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and waits for a new external trigger signal to be input. When the external trigger input signal is reinput, A/D conversion is carried out from the beginning.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately.
Figure 10-7. A/D Conversion by Hardware Start
INTP3
ADM Rewrite
CS=1, TRG=1
A /D Conversion
Standby
State
ANIn ANIn
Standby
State
ANIn
ADM Rewrite
CS=1, TRG=1
Standby
State
ANIm ANIm ANIm
ANIn ANIm ANIm ADCR
INTAD
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
ANIn ANIn
129
CHAPTER 10 A/D CONVERTER
(2) A/D conversion operation in software start
When bit 6 (TRG) and bit 7 (CS) of A/D converter mode register (ADM) are set to 0 and 1, respectively, the
A/D conversion starts on the voltage applied to the analog input pins specified with bits 1 to 3 (ADM1 to
ADM3) of ADM.
Upon termination of the A/D conversion, the conversion result is stored in the A/D conversion result register
(ADCR) and the interrupt request signal (INTAD) is generated. After one A/D conversion operation is started and terminated, the next A/D conversion operation starts immediately. The A/D conversion operation continues repeatedly until new data is written to ADM.
If data with CS set to 1 is written to ADM again during A/D conversion, the converter suspends its A/D conversion operation and starts A/D conversion on the newly written data.
If data with CS set to 0 is written to ADM during A/D conversion, the A/D conversion operation stops immediately.
Figure 10-8. A/D Conversion by Software Start
Conversion Start
CS=1, TRG=0
ADM Rewrite
CS=1, TRG=0
ADM Rewrite
CS=0, TRG=0
A /D Conversion ANIn ANIn ANIn ANIm
Conversion suspended
Conversion results are not stored
ANIm
Stop
ADCR ANIn ANIn ANIm
INTAD
Remarks 1. n = 0, 1, ... , 7
2. m = 0, 1, ... , 7
130
CHAPTER 10 A/D CONVERTER
10.5 A/D Converter Cautions
(1) Power consumption in standby mode
The A/D converter operates on the main system clock. Therefore, its operation stops in STOP mode. As a current still flows in the AV
REF
pin at this time, this current must be cut in order to minimize the overall system power dissipation. In Figure 10-9, the power dissipation can be reduced by outputting a low-level signal to the output port in standby mode. However, there is no precision to the actual AV
REF
voltage, and therefore the conversion values themselves lack precision and can only be used for relative comparison.
Figure 10-9. Example of Method of Reducing Current Dissipation in Standby Mode
V
DD
Output Port
µ
PD78082
AV
REF
AV
REF
.
DD
AV
SS
Series Resistor String
(2) Input range of ANI0 to ANI7
The input voltages of ANI0 to ANI7 should be within the specification range. In particular, if a voltage above
AV
REF
or below AV
SS
is input (even if within the absolute maximum rating range), the conversion value for that channel will be indeterminate. The conversion values of the other channels may also be affected.
131
CHAPTER 10 A/D CONVERTER
(3) Noise countermeasures
In order to maintain 8-bit resolution, attention must be paid to noise on pins AV
REF
and ANI0 to ANI7. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 10-10 in order to reduce noise.
Reference
Voltage Input
Figure 10-10. Analog Input Pin Disposition
If there is possibility that noise whose level is AV
REF
or higher or AV
SS
or lower may enter, clamp with a diode with a small V
F
(0.3 V or less).
AV
REF
C=100-1000 pF
V
DD
ANI0-ANI7
V
DD
AV
DD
AV
SS
V
SS
(4) Pins ANI0/P10 to ANI7/P17
The analog input pins ANI0 to ANI7 also function as input/output port (PORT1) pins. When A/D conversion is performed with any of pins ANI0 to ANI7 selected, be sure not to execute a PORT1 input instruction while conversion is in progress, as this may reduce the conversion resolution.
Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected
A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion.
(5) AV
REF
pin input impedance
A series resistor string of approximately 10 k
Ω
is connected between the AV
REF
pin and the AV
SS
pin.
Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AV
REF
pin and the AV
SS
pin, and there will be a large reference voltage error.
132
CHAPTER 10 A/D CONVERTER
(6) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the A/D converter mode register (ADM) is changed.
Caution is therefore required since, if a change of analog input pin is performed during A/D conversion, the
A/D conversion result and ADIF for the pre-change analog input may be set just before the ADM rewrite, and when ADIF is read immediately after the ADM rewrite, ADIF may be set despite the fact that the A/D conversion for the post-change analog input has not ended.
When the A/D conversion is stopped and then resumed, clear the ADIF before it is resumed.
Figure 10-11. A/D Conversion End Interrupt Request Generation Timing
ADM Rewrite
(Start of ANIm Conversion)
ADIF is set but ANIm conversion has not ended
ADM Rewrite
(Start of ANIn Conversion)
A /D Conversion ANIn ANIn ANIm ANIm
ADCR ANIn ANIn ANIm ANIm
INTAD
(7) AV
DD
pin
The AV
DD
pin is the analog circuit power supply pin, and supplies power to the input circuits of ANI0/P10 to
ANI7/P17.
Therefore, be sure to apply the same voltage as V
DD
to this pin shown in the following figure even when the application circuit is designed so as to switch to a backup battery.
Figure 10-12. Handling of AV
DD
Pin
Main power supply
Capacitor for back-up
AV
REF
V
DD
AV
DD
AV
SS
V
SS
133
[MEMO]
CHAPTER 10 A/D CONVERTER
134
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.1 Serial Interface Channel 2 Functions
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
(1) Operation stop mode
This mode is used when serial transfer is not carried out to reduce power consumption.
(2) Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates. In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
(3) 3-wire serial I/O mode (MSB-first/LSB-first switchable)
In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK2), and serial data lines
(SI2, SO2).
In the 3-wire serial I/O mode, simultaneous transmission and reception is possible, increasing the data transfer processing speed.
Either the MSB or LSB can be specified as the start bit for an 8-bit data serial transfer, allowing connection to devices using either as the start bit.
The 3-wire serial I/O mode is useful for connection to peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc.
135
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.2 Serial Interface Channel 2 Configuration
Serial interface channel 2 consists of the following hardware.
Table 11-1. Serial Interface Channel 2 Configuration
Item
Register
Control register
Configuration
Transmit shift register (TXS)
Receive shift register (RXS)
Receive buffer register (RXB)
Serial operating mode register 2 (CSIM2)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
136
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
★ Figure 11-1. Serial Interface Channel 2 Block Diagram
Internal Bus
Receive Buffer
Register
(RXB/SIO2)
Asynchronous
Serial Interface
Status Register
PE FE OVE
Direction
Control Circuit
Asynchronous
Serial Interface
Mode Register
TXE RXE PS1 PS0 CL SL ISRM SCK
Direction
Control Circuit
Transmit Shift
Register
(TXS/SIO2)
Receive Shift
Register (RXS)
RxD/SI2/
P70
TxD/SO2/
P71
PM71
Reception
Control
Circuit INTSR/INTCSI2
ISRM
INTSER Transmission
Control
Circuit
SCK Output
Control Circuit
INTST
ASCK/
SCK2/P72
PM72
CSIE2
CSIM
22
CSCK
Serial Operating
Mode Register 2
Baud Rate Generator Note
CSIE2
TXE
RXE
4 4 f xx
-f xx
/2 10
SCK
CSCK
Internal Bus
MDL3 MDL2 MDL1 MDL0 TPS3 TPS2 TPS1 TPS0
Baud Rate Generator
Control Register
Note See Figure 11-2 for the baud rate generator configuration.
137
Transmit
Clock
Receive
Clock
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
Figure 11-2. Baud Rate Generator Block Diagram
CSIE2
TXE
Start Bit
Sampling Clock
5-Bit
Counter
1/2
MDL0-MDL3
Match
ASCK/SCK2/P72
Selector
4 f xx
-f xx
TPS0-TPS3
SCK
CSCK
/2 10
Decoder
4
Match
1/2
RXE
Start Bit Detection
5-Bit
Counter
4
TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
Baud Rate Generator
Control Register
Internal Bus
138
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(1) Transmit shift register (TXS)
This register is used to set the transmit data. The data written in TXS is transmitted as serial data.
If the data length is specified as 7 bits, bits 0 to 6 of the data written in TXS are transferred as transmit data.
Writing data to TXS starts the transmit operation.
TXS is written to with an 8-bit memory manipulation instruction. It cannot be read.
TXS value is FFH after RESET input.
Caution TXS must not be written to during a transmit operation. TXS and the receive buffer register
(RXB) are allocated to the same address, and when a read is performed, the value of RXB is read.
(2) Receive shift register (RXS)
This register is used to convert serial data input to the RxD pin to parallel data. When one byte of data is received, the receive data is transferred to the receive buffer register (RXB).
RXS cannot be directly manipulated by a program.
(3) Receive buffer register (RXB)
This register holds receive data. Each time one byte of data is received, new receive data is transferred from the receive shift register (RXS).
If the data length is specified as 7 bits, the receive data is transferred to bits 0 to 6 of RXB, and the MSB of
RXB is always set to 0.
RXB is read with an 8-bit memory manipulation instruction. It cannot be written to.
RXB value is FFH after RESET input.
Caution RXB and the transmit shift register (TXS) are allocated to the same address, and when a write is performed, the value is written to TXS.
(4) Transmission control circuit
This circuit performs transmit operation control such as the addition of a start bit, parity bit and stop bit to data written in the transmit shift register (TXS) in accordance with the contents set in the asynchronous serial interface mode register (ASIM).
(5) Reception control circuit
This circuit controls receive operations in accordance with the contents set in the asynchronous serial interface mode register (ASIM). It performs error checks for parity errors, etc., during a receive operation, and if an error is detected, sets a value in the asynchronous serial interface status register (ASIS) in accordance with the error contents.
139
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.3 Serial Interface Channel 2 Control Registers
Serial interface channel 2 is controlled by the following four registers.
• Serial Operating Mode Register 2 (CSIM2)
• Asynchronous Serial Interface Mode Register (ASIM)
• Asynchronous Serial Interface Status Register (ASIS)
• Baud Rate Generator Control Register (BRGC)
(1) Serial operating mode register 2 (CSIM2)
This register is set when serial interface channel 2 is used in the 3-wire serial I/O mode.
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM2 to 00H.
Figure 11-3. Serial Operating Mode Register 2 Format
Symbol
7 6
CSIM2 CSIE2 0
5
0
4
0
3
0
2 1 0
CSIM
22
CSCK 0
Address After Reset R/W
FF72H 00H R/W
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22 First Bit Specification
0
1
MSB
LSB
CSIE2 Operation Control in 3-wire Serial I/O Mode
0
1
Operation stopped
Operation enabled
Cautions 1. Set 0 to the bits 0 and 3 to 6.
2. When UART mode is selected, CSIM2 should be set to 00H.
140
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(2) Asynchronous serial interface mode register (ASIM)
This register is set when serial interface channel 2 is used in the asynchronous serial interface mode.
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM to 00H.
Figure 11-4. Asynchronous Serial Interface Mode Register Format
Symbol
7 6 5 4 3
ASIM TXE RXE PS1 PS0 CL
2 1 0
SL ISRM SCK
Address After Reset R/W
FF70H 00H R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface
Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output Note
ISRM
0
1
Control of Reception Completion Interrupt in Case of Error Generation
Reception completion interrupt generated in case of error generation
Reception completion interrupt not generated in case of error generation
SL Transmit Data Stop Bit Length Specification
0
1
1 bit
2 bits
CL
0
1
Character Length Specification
7 bits
8 bits
PS1
0
0
1
1
PS0
0
1
0
1
Parity Bit Specification
No Parity
0 parity always added in transmission
No parity test in reception (parity error not generated)
Odd parity
Even parity
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
Cautions 1. When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
2. The serial transmit/receive operation must be stopped before changing the operating mode.
141
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
Table 11-2. Serial Interface Channel 2 Operating Mode Settings
(1) Operation Stop Mode
ASIM CSIM2
TXE RXE SCK CSIE2 CSIM22 CSCK
PM70 P70 PM71 P71 PM72 P72 Start
Bit
Shift
Clock
P70/SI2
/RxD Pin
Functions
P71/SO2
/TxD Pin
Functions
P72/SCK2
/ASCK Pin
Functions
0 0 x 0 x x x
Note1 x
Note1 x
Note1 x
Note1 x
Note1 x
Note1
— — P70 P71 P72
Other than above Setting prohibited
(2) 3-wire Serial I/O Mode
ASIM CSIM2
TXE RXE SCK CSIE2 CSIM22 CSCK
0 0 0 1 0 0
PM70 P70 PM71 P71 PM72 P72
1
Note2 x
Note2
0 1 1 x
Start
Bit
MSB
Shift
Clock
External clock
P70/SI2
/RxD Pin
Functions
SI2
Note2
P71/SO2
/TxD Pin
Functions
P72/SCK2
/ASCK Pin
Functions
SO2
(CMOS output)
SCK2 input
1 0 1 Internal clock
SCK2 output
1 1 0 1 x LSB External clock
SCK2 input
1 0 1 Internal clock
SCK2 output
Other than above Setting prohibited
(3) Asynchronous Serial Interface Mode
ASIM CSIM2
TXE RXE SCK CSIE2 CSIM22 CSCK
PM70 P70 PM71 P71 PM72 P72 Start
Bit
Shift
Clock
P70/SI2
/RxD Pin
Functions
P71/SO2
/TxD Pin
Functions
P72/SCK2
/ASCK Pin
Functions
1 0 0
1
0 0 0 x
Note1 x
Note1
0 1 x
1
Note1 x x
Note1
LSB External clock
Internal clock
P70 TxD
(CMOS output)
ASCK input
P72
0 1 0 0 0 0 1 x x
Note1 x
Note1
1 x External clock
RxD P71 ASCK input
1 x
Note1 x
Note1
Internal clock
P72
1 1 0
1
0 0 0 1 x 0 1 x
1
Note1 x x
Note1
External clock
Internal clock
TxD
(CMOS output)
ASCK input
P72
Other than above Setting prohibited
Notes 1. Can be used freely as port function.
2. Can be used as P70 (CMOS input/output) when only transmitter is used.
Remark
×
: Don’t care
PM
××
: Port mode register
P
××
: Port output latch
142
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(3) Asynchronous serial interface status register (ASIS)
This is a register which displays the type of error when a reception error is generated in the asynchronous serial interface mode.
ASIS is read with a 1-bit or 8-bit memory manipulation instruction.
In 3-wire serial I/O mode, the contents of the ASIS are undefined.
RESET input sets ASIS to 00H.
Figure 11-5. Asynchronous Serial Interface Status Register Format
Symbol
ASIS
7
0
6
0
5
0
4
0
3
0
2
PE
1 0
FE OVE
Address After Reset R/W
FF71H 00H R
OVE
0
1
Overrun Error Flag
Overrun error not generated
Overrun error generated Note 1
(When next receive operation is completed before data from receive buffer register is read)
FE
0
1
Framing Error Flag
Framing error not generated
Framing error generated Note 2
(When stop bit is not detected)
PE
0
1
Parity Error Flag
Parity error not generated
Parity error generated (When transmit data parity does not match)
Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only single stop bit detection is performed during reception.
143
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(4) Baud rate generator control register (BRGC)
This register sets the serial clock for serial interface channel 2.
BRGC is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC to 00H.
Figure 11-6. Baud Rate Generator Control Register Format (1/2)
Symbol
7 6 5 4 3 2 1 0 Address After Reset R/W
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection
0 0 0 0 f
SCK
/16
0
0
0
0
0
0
0
1
1
1
0
1 f f f
SCK
/17
SCK
SCK
/18
/19
0
0
1
1
0
0
0
1 f
SCK
/20 f
SCK
/21
0
0
1
1
1
1
0
1 f
SCK
/22 f
SCK
/23
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0 f f
SCK
/24 f
SCK
/25 f
SCK
/26 f
SCK
/27
SCK
/28 f
SCK
/29 1
1
0
1
1
0 1
1 1 1 1 f
SCK
/30 f
SCKNote
Note Can only be used in 3-wire serial I/O mode.
Remarks 1. f
SCK
: 5-bit counter source clock
2. k : Value set in MDL0 to MDL3 (0
≤
k
≤
14)
10
11
12
13
14
—
8
9
6
7
2
3
4
5
0
1 k
144
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
Figure 11-6. Baud Rate Generator Control Register Format (2/2)
5-Bit Counter Source Clock Selection
TPS3 TPS2 TPS1 TPS0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
Other than above
0
1
0
1
0
1
0
1
0
1
0 f
XX
/2
10 f
XX
MCS=1 f
XX
/2
10 f
X f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7 f
XX
/2
8 f
XX
/2
9
Setting prohibited f
X
/2 f
X
/2
2 f
X
/2
3 f
X
/2
4 f
X
/2
5 f
X
/2
6 f
X
/2
7 f
X
/2
8 f
X
/2
9
(4.9 kHz)
MCS=0 f
X
/2
11
(5.0 MHz)
(2.5 MHz) f f
X
/2
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
(313 kHz) f
X
/2
4 f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
10
(2.4 kHz)
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz) n
6
7
4
5
11
1
2
3
8
9
10
Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally. Therefore, BRGC must not be written to during a communication operation.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XX
: Main system clock frequency (f
X
or f
X
/2)
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. n : Value set in TPS0 to TPS3 (1
≤
n
≤
11)
5. Values in parentheses when operated at f
X
=5.0 MHz
145
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
(a) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clocks generated by scaling the main system clock. The baud rate generated from the main system clock is found from the following expression.
f
XX
[Baud rate] = [Hz]
2 n ×
(k+16) where, f
X
: Main system clock oscillation frequency f
XX
: Main system clock frequency (fx or fx/2) n k
: Value set in TPS0 to TPS3 (1
≤
n
≤
11)
: Value set in MDL0 to MDL3 (0
≤
k
≤
14)
★
Table 11-3. Relation between Main System Clock and Baud Rate
Baud
Rate
(bps)
75
110
150
300
600
1200
2400
4800
9600
19200
31250
38400 fx=5.0 MHz fx=4.19 MHz
MCS=1 MCS=0 MCS=1 MCS=0
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)
– 00H
E6H
1.73
0.88
0BH
03H
1.14
–2.01
EBH
E3H
1.14
–2.01
06H
00H
0.88
1.73
E0H
D0H
1.73
1.73
EBH
DBH
1.14
1.14
DBH
CBH
1.14
1.14
E0H
D0H
1.73
1.73
C0H
B0H
1.73
1.73
CBH
BBH
1.14
1.14
BBH
ABH
1.14
1.14
C0H
B0H
1.73
1.73
A0H
90H
1.73
1.73
ABH
9BH
1.14
1.14
9BH
8BH
1.14
1.14
A0H
90H
1.73
1.73
80H
70H
1.73
1.73
8BH
7BH
1.14
1.14
7BH
6BH
1.14
1.14
80H
74H
70H
1.73
0
1.73
64H
60H
0
1.73
71H
6BH
–1.31
1.14
1.14
61H
5BH
—
–1.31
1.14
— 76800 60H 1.73
50H 1.73
5BH
Remark MCS: Oscillation mode selection register (OSMS) bit 0
146
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(b) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
f
ASCK
[Baud rate] = [Hz]
2
×
(k+16) where, f k
ASCK
: Frequency of clock input to ASCK pin
: Value set in MDL0 to MDL3 (0
≤
k
≤
14)
Table 11-4. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
Baud Rate (bps)
75
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
ASCK Pin Input Frequency
2.4 kHz
3.52 kHz
4.8 kHz
9.6 kHz
19.2 kHz
38.4 kHz
76.8 kHz
153.6 kHz
307.2 kHz
614.4 kHz
1000.0 kHz
1228.8 kHz
147
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.4 Serial Interface Channel 2 Operation
Serial interface channel 2 has the following three modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
• 3-wire serial I/O mode
11.4.1 Operation stop mode
In the operation stop mode, serial transfer is not performed, and therefore power consumption can be reduced.
In the operation stop mode, the P70/SI2/RxD, P71/SO2/TxD and P72/SCK2/ASCK pins can be used as normal input/output ports.
(1) Register setting
Operation stop mode settings are performed using serial operating mode register 2 (CSIM2) and the asynchronous serial interface mode register (ASIM).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM2 to 00H.
Symbol
7 6
CSIM2 CSIE2 0
5
0
4
0
3
0
2 1 0
CSIM
22
CSCK 0
Address After Reset R/W
FF72H 00H R/W
CSIE2 Operation Control in 3-wire Serial I/O Mode
0
1
Operation stopped
Operation enabled
Caution Set 0 to the bits 0 and 3 to 6.
148
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM to 00H.
Symbol
7 6 5 4 3
ASIM TXE RXE PS1 PS0 CL
2
SL
1 0
ISRM SCK
Address After Reset R/W
FF70H 00H R/W
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
149
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.4.2 Asynchronous serial interface (UART) mode
In this mode, one byte of data is transmitted/received following the start bit, and full-duplex operation is possible.
A dedicated UART baud rate generator is incorporated, allowing communication over a wide range of baud rates.
In addition, the baud rate can be defined by scaling the input clock to the ASCK pin.
The MIDI standard baud rate (31.25 kbps) can be used by employing the dedicated UART baud rate generator.
(1) Register setting
UART mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), the asynchronous serial interface status register (ASIS), and the baud rate generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM2 to 00H.
When the UART mode is selected, 00H should be set in CSIM2.
Symbol
7 6
CSIM2 CSIE2 0
5
0
4
0
3
0
2 1
CSIM
22
CSCK
0
0
Address After Reset R/W
FF72H 00H R/W
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22 First Bit Specification
0
1
MSB
LSB
CSIE2 Operation Control in 3-wire Serial I/O Mode
0
1
Operation stopped
Operation enabled
Caution Set 0 to the bits 0 and 3 to 6.
150
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM to 00H.
Symbol
7 6 5 4 3
ASIM TXE RXE PS1 PS0 CL
2 1 0
SL ISRM SCK
Address After Reset R/W
FF70H 00H R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface
Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output Note
ISRM
0
1
Control of Reception Completion Interrupt in Case of Error Generation
Reception completion interrupt request generated in case of error generation
Reception completion interrupt request not generated in case of error generation
SL Transmit Data Stop Bit Length Specification
0 1 bit
1 2 bits
CL
0
1
Character Length Specification
7 bits
8 bits
PS1
0
0
1
1
PS0
0
1
0
1
Parity Bit Specification
No Parity
0 parity always added in transmission
No parity test in reception (parity error not generated)
Odd parity
Even parity
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
Note When SCK is set to 1 and the baud rate generator output is selected, the ASCK pin can be used as an input/output port.
Caution The serial transmit/receive operation must be stopped before changing the operating mode.
151
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(c) Asynchronous serial interface status register (ASIS)
ASIS is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIS to 00H.
Symbol
ASIS
7
0
6
0
5
0
4
0
3
0
2
PE
1 0
FE OVE
Address After Reset R/W
FF71H 00H R
OVE
0
1
Overrun Error Flag
Overrun error not generated
Overrun error generated Note 1
(When next receive operation is completed before data from receive buffer register is read)
FE
0
1
Framing Error Flag
Framing error not generated
Framing error generated Note 2
(When stop bit is not detected)
PE
0
1
Parity Error Flag
Parity error not generated
Parity error generated (When transmit data parity does not match)
Notes 1. The receive buffer register (RXB) must be read when an overrun error is generated. Overrun errors will continue to be generated until RXB is read.
2. Even if the stop bit length has been set as 2 bits by bit 2 (SL) of the asynchronous serial interface mode register (ASIM), only single stop bit detection is performed during reception.
152
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(d) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC to 00H.
Symbol
7 6 5 4 3 2 1 0 Address After Reset R/W
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection
0 0 0 0 f
SCK
/16
0
0
0
0
0
0
0
1
1
1
0
1 f f f
SCK
/17
SCK
SCK
/18
/19
0
0
1
1
0
0
0
1 f
SCK
/20 f
SCK
/21
0
0
1
1
1
1
0
1 f
SCK
/22 f
SCK
/23
1
1
1
1
0
0
0
0
0
0
1
0
1
0 f
SCK
/24 f
SCK
/25 f
SCK
/26 f
SCK
/27 1
0
1
0 1
1
1
1
1
1
0
1
1
0 f
SCK
/28 f
SCK
/29 f
SCK
/30
Remark f
SCK
: 5-bit counter source clock k : Value set in MDL0 to MDL3 (0
≤
k
≤
14)
8
9
6
7
2
3
4
5
0
1
10
11
12
13
14 k
(continued)
153
154
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
5-Bit Counter Source Clock Selection
TPS3 TPS2 TPS1 TPS0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
Other than above
0
1
0
1
0
1
0
1
0
1
0 f
XX
/2
10 f
XX
MCS=1 f
X
/2
10 f
X f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7 f
XX
/2
8 f
XX
/2
9
Setting prohibited f
X
/2 f
X
/2
2 f
X
/2
3 f
X
/2
4 f
X
/2
5 f
X
/2
6 f
X
/2
7 f
X
/2
8 f
X
/2
9
(4.9 kHz)
MCS=0 f
X
/2
11
(5.0 MHz)
(2.5 MHz) f f
X
/2
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
(313 kHz) f
X
/2
4 f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
10
(2.4 kHz)
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz) n
6
7
4
5
11
1
2
3
8
9
10
Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XX
: Main system clock frequency (f
X
or f
X
/2)
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. n : Value set in TPS0 to TPS3 (1
≤
n
≤
11)
5. Values in parentheses when operated at f
X
= 5.0 MHz.
★
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
The baud rate transmit/receive clock generated is either a signal scaled from the main system clock, or a signal scaled from the clock input from the ASCK pin.
(i) Generation of baud rate transmit/receive clock by means of main system clock
The transmit/receive clock is generated by scaling the main system clock. The baud rate generated from the main system clock is obtained with the following expression.
f
XX
[Baud rate] = [Hz]
2 n ×
(k+16) where, f
X
: Main system clock oscillation frequency f
XX
: Main system clock frequency (fx or fx/2) n k
: Value set in TPS0 to TPS3 (1
≤
n
≤
11)
: Value set in MDL0 to MDL3 (0
≤
k
≤
14)
Table 11-5. Relation between Main System Clock and Baud Rate
Baud
Rate
(bps)
600
1200
2400
4800
75
110
150
300
9600
19200
31250
38400
76800 fx=5.0 MHz fx=4.19 MHz
MCS=1 MCS=0 MCS=1 MCS=0
BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%) BRGC Set Value Error (%)
– 00H
E6H
1.73
0.88
0BH
03H
1.14
–2.01
EBH
E3H
1.14
–2.01
06H
00H
0.88
1.73
E0H
D0H
1.73
1.73
EBH
DBH
1.14
1.14
DBH
CBH
1.14
1.14
E0H
D0H
1.73
1.73
C0H
B0H
1.73
1.73
CBH
BBH
1.14
1.14
BBH
ABH
1.14
1.14
C0H
B0H
1.73
1.73
A0H
90H
1.73
1.73
ABH
9BH
1.14
1.14
9BH
8BH
1.14
1.14
A0H
90H
1.73
1.73
80H 1.73
8BH 1.14
7BH 1.14
80H
74H
70H
60H
1.73
0
1.73
1.73
70H
64H
60H
50H
1.73
0
1.73
1.73
7BH
71H
6BH
5BH
1.14
–1.31
1.14
1.14
6BH
61H
5BH
—
1.14
–1.31
1.14
—
Remark MCS: Oscillation mode selection register (OSMS) bit 0
155
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(ii) Generation of baud rate transmit/receive clock by means of external clock from ASCK pin
The transmit/receive clock is generated by scaling the clock input from the ASCK pin. The baud rate generated from the clock input from the ASCK pin is obtained with the following expression.
f
ASCK
[Baud rate] = [Hz]
2
×
(k+16) where, f k
ASCK
: Frequency of clock input to ASCK pin
: Value set in MDL0 to MDL3 (0
≤
k
≤
14)
Table 11-6. Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)
Baud Rate (bps)
75
110
150
300
600
1200
2400
4800
9600
19200
31250
38400
ASCK Pin Input Frequency
2.4 kHz
3.52 kHz
4.8 kHz
9.6 kHz
19.2 kHz
38.4 kHz
76.8 kHz
153.6 kHz
307.2 kHz
614.4 kHz
1000.0 kHz
1228.8 kHz
156
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(2) Communication operation
(a) Data format
The transmit/receive data format is as shown in Figure 11-7.
Figure 11-7. Asynchronous Serial Interface Transmit/Receive Data Format
One Data Frame
Start
Bit
D0 D1 D2 D3 D4 D5 D6 D7
Parity
Bit
Stop Bit
Character Bit
1 Data frame is configured from the following bits.
• Start bits ..................
1 bit
• Character bits .........
7 bits/8 bits
• Parity bits ................
Even parity/odd parity/0 parity/no parity
• Stop bit(s) ...............
1 bit/2 bits
The specification of character bit length, parity selection, and specification of stop bit length for each data frame is carried out with asynchronous serial interface mode register (ASIM).
When 7 bits are selected as the number of character bits, only the lower 7 bits (bits 0 to 6) are valid; in transmission the most significant bit (bit 7) is ignored, and in reception the most significant bit (bit 7) is always “0”.
The serial transfer rate is selected by means of the ASIM and the baud rate generator control register
(BRGC).
If a serial data receive error is generated, the receive error contents can be determined by reading the status of the asynchronous serial interface status register (ASIS).
157
158
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(b) Parity types and operation
The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmitting side and the receiving side. With even parity and odd parity, a one-bit (odd number) error can be detected. With 0 parity and no parity, an error cannot be detected.
(i) Even parity
• Transmission
The number of bits with a value of “1”, including the parity bit, in the transmit data is controlled to be even.
The value of the parity bit is as follows:
Number of bits with a value of “1” in transmit data is odd: 1
Number of bits with a value of “1” in transmit data is even: 0
• Reception
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If it is odd, a parity error occurs.
(ii) Odd parity
• Transmission
Conversely to the situation with even parity, the number of bits with a value of “1”, including the parity bit, in the transmit data is controlled to be odd. The value of the parity bit is as follows:
Number of bits with a value of “1” in transmit data is odd: 0
Number of bits with a value of “1” in transmit data is even: 1
• Reception
The number of bits with a value of “1”, including the parity bit, in the receive data is counted. If it is even, a parity error occurs.
(iii) 0 Parity
When transmitting, the parity bit is set to "0" irrespective of the transmit data.
At reception, a parity bit check is not performed. Therefore, a parity error is not generated, irrespective of whether the parity bit is set to "0" or "1".
(iv) No parity
A parity bit is not added to the transmit data. At reception, data is received assuming that there is no parity bit. Since there is no parity bit, a parity error is not generated.
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(c) Transmission
A transmit operation is started by writing transmit data to the transmit shift register (TXS). The start bit, parity bit and stop bit(s) are added automatically.
When the transmit operation starts, the data in the transmit shift register (TXS) is shifted out, and when the transmit shift register (TXS) is empty, a transmission completion interrupt request (INTST) is generated.
Figure 11-8. Asynchronous Serial Interface Transmission Completion Interrupt Request Timing
(a) Stop bit length: 1
TxD (Output) D0 D1 D2 D6 D7 Parity
STOP
START
INTST
TxD (Output)
INTST
(b) Stop bit length: 2
START
D0 D1 D2 D6 D7 Parity
STOP
Caution Rewriting of the asynchronous serial interface mode register (ASIM) should not be performed during a transmit operation. If rewriting of the ASIM register is performed during transmission, subsequent transmit operations may not be possible (the normal state is restored by RESET input).
It is possible to determine whether transmission is in progress by software by using a transmission completion interrupt request (INTST) or the interrupt request flag (STIF) set by the INTST.
159
160
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(d) Reception
When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), a receive operation is enabled and sampling of the RxD pin input is performed.
RxD pin input sampling is performed using the serial clock specified by ASIM.
When the RxD pin input becomes low, the 5-bit counter of the baud rate generator (see Figure 11-2) starts counting, and at the time when the half time determined by specified baud rate has passed, the data sampling start timing signal is output. If the RxD pin input sampled again as a result of this start timing signal is low, it is identified as a start bit, the 5-bit counter is initialized and starts counting, and data sampling is performed. When character data, a parity bit and one stop bit are detected after the start bit, reception of one frame of data ends.
When one frame of data has been received, the receive data in the shift register is transferred to the receive buffer register (RXB), and a reception completion interrupt request (INTSR) is generated.
If an error is generated, the receive data in which the error was generated is still transferred to RXB, and
INTSR is generated.
If the RXE bit is reset (0) during the receive operation, the receive operation is stopped immediately. In this case, the contents of RXB and ASIS are not changed, and INTSR and INTSER are not generated.
Figure 11-9. Asynchronous Serial Interface Reception Completion Interrupt Request Timing
RxD (Input) D6 D7 Parity
STOP
START
D0 D1 D2
INTSR
Caution The receive buffer register (RXB) must be read even if a receive error is generated. If
RXB is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
★
★
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(e) Receive errors
Three kinds of errors can occur during a receive operation: a parity error, framing error, or overrun error.
When a data reception results error flag is set in the asynchronous serial interface register (ASIS), a reception error interrupt request (INTSER) is generated.
The reception error interrupt request is generated first before the reception completed interrupt request
(INTSR). Receive error causes are shown in Table 11-7.
It is possible to determine what kind of error was generated during reception by reading the contents of the asynchronous serial interface status register (ASIS) in the reception error interrupt servicing (INTSER)
(see Figures 11-9 and 11-10).
The contents of ASIS are reset (0) by reading the receive buffer register (RXB) or receiving the next data
(if there is an error in the next data, the corresponding error flag is set).
Table 11-7. Receive Error Causes
Receive Errors
Parity error
Framing error
Overrun error
Cause
Transmission-time parity specification and reception data parity do not match
Stop bit not detected
Reception of next data is completed before data is read from receive register buffer
RxD (Input)
Figure 11-10. Receive Error Timing
D0 D1 D2 D6 D7 Parity
STOP
START
INTSR
INTSER
Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are reset (0) by reading the receive buffer register (RXB) or receiving the next data. To ascertain the error contents, ASIS must be read before reading RXB.
2. The receive buffer register (RXB) must be read even if a receive error is generated.
If RXB is not read, an overrun error will be generated when the next data is received, and the receive error state will continue indefinitely.
161
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(3) UART mode cautions
(a) In cases where bit 7 (TXE) of the asynchronous serial interface mode register (ASIM) has been cleared and a transmit operation has been terminated during transmission, be sure to set 1 in TXE after setting
FFH in the transmit shift register (TXS) before executing the next transmission.
(b) In cases where bit 6 (RXE) of the asynchronous serial interface mode register (ASIM) has been cleared
(0) and a receive operation terminated during reception, enable/disable will differ depending on the timing, the condition of the receive buffer register (RXB), and generation of the reception completed interrupt request (INTSR) . The timing is displayed in Figure 11-11.
Figure 11-11 State of the Receive Buffer Register (RXB) when Reception is Interrupted, and Generation/
Non Generation of an Interrupt Request (INTSR)
RxD Pin
RXB
Parity
INTSR
<1> <3>
<2>
When RXE is set to 0 at a time indicated by <1>, RXB holds the previous data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <2>, RXB renews the data and does not generate INTSR.
When RXE is set to 0 at a time indicated by <3>, RXB renews the data and generates INTSR.
162
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
11.4.3 3-wire serial I/O mode
The 3-wire serial I/O mode is useful for connection of peripheral I/Os and display controllers, etc., which incorporate a conventional synchronous clocked serial interface, such as the 75X/XL series, 78K series, 17K series, etc.
Communication is performed using three lines: the serial clock (SCK2), serial output (SO2), and serial input (SI2).
(1) Register setting
3-wire serial I/O mode settings are performed using serial operating mode register 2 (CSIM2), the asynchronous serial interface mode register (ASIM), and the baud rate generator control register (BRGC).
(a) Serial operating mode register 2 (CSIM2)
CSIM2 is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets CSIM2 to 00H.
Symbol
7 6
CSIM2 CSIE2 0
5
0
4
0
3
0
2 1
CSIM
22
CSCK
0
0
Address After Reset R/W
FF72H 00H R/W
CSCK
0
1
Clock Selection in 3-wire Serial I/O Mode
Input clock from off-chip to SCK2 pin
Dedicated baud rate generator output
CSIM22 First Bit Specification
0
1
MSB
LSB
CSIE2 Operation Control in 3-wire Serial I/O Mode
0
1
Operation stopped
Operation enabled
Caution Set 0 to the bits 0 and 3 to 6.
163
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(b) Asynchronous serial interface mode register (ASIM)
ASIM is set with a 1-bit or 8-bit memory manipulation instruction.
RESET input sets ASIM to 00H.
When the 3-wire serial I/O mode is selected, 00H should be set in ASIM.
Symbol
7 6 5 4 3
ASIM TXE RXE PS1 PS0 CL
2 1 0
SL ISRM SCK
Address After Reset R/W
FF70H 00H R/W
SCK
0
1
Clock Selection in Asynchronous Serial Interface
Mode
Input clock from off-chip to ASCK pin
Dedicated baud rate generator output
ISRM
0
1
Control of Reception Completion Interrupt in Case of Error Generation
Reception completion interrupt request generated in case of error generation
Reception completion interrupt request not generated in case of error generation
SL Transmit Data Stop Bit Length Specification
0
1
1 bit
2 bits
CL
0
1
Character Length Specification
7 bits
8 bits
PS1
0
0
1
1
PS0
0
1
0
1
Parity Bit Specification
No Parity
0 parity always added in transmission
No parity test in reception (parity error not generated)
Odd parity
Even parity
RXE
0
1
Receive Operation Control
Receive operation stopped
Receive operation enabled
TXE
0
1
Transmit Operation Control
Transmit operation stopped
Transmit operation enabled
164
★
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(c) Baud rate generator control register (BRGC)
BRGC is set with an 8-bit memory manipulation instruction.
RESET input sets BRGC to 00H.
Symbol
7 6 5 4 3 2 1 0 Address After Reset R/W
BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 FF73H 00H R/W
MDL3 MDL2 MDL1 MDL0 Baud Rate Generator Input Clock Selection
0 0 0 0 f
SCK
/16
0
0
0
0
0
0
0
1
1
1
0
1 f f f
SCK
/17
SCK
SCK
/18
/19
0
0
1
1
0
0
0
1 f
SCK
/20 f
SCK
/21
0
0
1
1
1
1
0
1 f
SCK
/22 f
SCK
/23
1
1
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0 f f
SCK
/24 f
SCK
/25 f
SCK
/26 f
SCK
/27
SCK
/28 f
SCK
/29 1
1
0
1
1
0 1
1 1 1 1 f
SCK
/30 f
SCK
10
11
12
13
14
—
8
9
6
7
2
3
4
5
0
1 k
(continued)
Remark f
SCK
: 5-bit counter source clock k : Value set in MDL0 to MDL3 (0
≤
k
≤
14)
165
166
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
5-Bit Counter Source Clock Selection
TPS3 TPS2 TPS1 TPS0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
Other than above
0
1
0
1
0
1
0
1
0
1
0 f
XX
/2
10 f
XX
MCS=1 f
X
/2
10 f
X f
XX
/2 f
XX
/2
2 f
XX
/2
3 f
XX
/2
4 f
XX
/2
5 f
XX
/2
6 f
XX
/2
7 f
XX
/2
8 f
XX
/2
9
Setting prohibited f
X
/2 f
X
/2
2 f
X
/2
3 f
X
/2
4 f
X
/2
5 f
X
/2
6 f
X
/2
7 f
X
/2
8 f
X
/2
9
(4.9 kHz)
MCS=0 f
X
/2
11
(5.0 MHz)
(2.5 MHz) f f
X
/2
X
/2
2
(1.25 MHz) f
X
/2
3
(625 kHz)
(313 kHz) f
X
/2
4 f
X
/2
5
(156 kHz) f
X
/2
6
(78.1 kHz) f
X
/2
7
(39.1 kHz) f
X
/2
8
(19.5 kHz) f
X
/2
9
(9.8 kHz) f
X
/2
10
(2.4 kHz)
(2.5 MHz)
(1.25 MHz)
(625 kHz)
(313 kHz)
(156 kHz)
(78.1 kHz)
(39.1 kHz)
(19.5 kHz)
(9.8 kHz)
(4.9 kHz) n
6
7
4
5
11
1
2
3
8
9
10
Caution When a write is performed to BRGC during a communication operation, baud rate generator output is disrupted and communication cannot be performed normally.
Therefore, BRGC must not be written to during a communication operation.
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XX
: Main system clock frequency (f
X
or f
X
/2)
3. MCS : Oscillation mode selection register (OSMS) bit 0
4. n : Value set in TPS0 to TPS3 (1
≤
n
≤
11)
5. Values in parentheses when operated at f
X
= 5.0 MHz.
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
When the internal clock is used as the serial clock in the 3-wire serial I/O mode, set BRGC as described below.
BRGC Setting is not required if an external serial clock is used.
(i) When the baud rate generator is not used:
Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
The serial clock frequency becomes the same as the source clock frequency for the 5-bit counter.
(ii) When the baud rate generator is used:
Select a serial clock frequency with TPS0-TPS3. Be sure then to set MDL0 to MDL3 to 1,1,1,1.
The serial clock frequency is calculated by the following formula: f
XX
Serial clock frequency= [H z
]
2 n
x (k + 16)
Remarks 1. f
X
: Main system clock oscillation frequency
2. f
XX
: Main system clock frequency (f
X
or f
X
/2)
3. n
4. k
: Value set in TPS0 to TPS3 (1
≤
n
≤
11)
: Value set in MDL0 to MDL3 (0
≤
k
≤
14)
167
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
(2) Communication operation
In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/ received bit by bit in synchronization with the serial clock.
Transmit shift register (TXS/SIO2) and receive shift register (RXS) shift operations are performed in synchronization with the fall of the serial clock SCK2. Then transmit data is held in the SO2 latch and output from the SO2 pin. Also, receive data input to the SI2 pin is latched in the receive buffer register (RXB/SIO2) on the rise of SCK2.
At the end of an 8-bit transfer, the operation of the TXS/SIO2 or RXS stops automatically, and the interrupt request flag (SRIF) is set.
Figure 11-12. 3-Wire Serial I/O Mode Timing
SCK2 1 2 3 4 5 6 7 8
SI2 DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0
SO2 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0
★
SRIF
End of Transfer
Transfer Start at the Falling Edge of SCK2
(3) MSB/LSB switching as the start bit
The 3-wire serial I/O mode enables to select transfer to start from MSB or LSB.
Figure 11-13 shows the configuration of the transmission shift register (TXS/SIO2) and internal bus. As shown in the figure, MSB/LSB can be read/written in reverse form.
MSB/LSB switching as the start bit can be specified with bit 2 (CSIM22) of the serial operating mode register
2 (CSIM2).
168
★
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
Figure 11-13. Circuit of Switching in Transfer Bit Order
Internal Bus
7
6
1
0
LSB-first
MSB-first Read/Write Gate Read/Write Gate
SI2 Transmission Shift Register (TXS/SIO02) D Q
SO0 Latch
SO2
SCK2
Start bit switching is realized by switching the bit order for data write to SIO2. The SIO2 shift order remains unchanged.
Thus, switching between MSB-first and LSB-first must be performed before writing data to the shift register.
(4) Transfer start
Serial transfer is started by setting transfer data to the transmission shift register (TXS/SIO2) when the following two conditions are satisfied.
•
Serial interface channel 2 operation control bit (CSIE2) =1
•
Internal serial clock is stopped or SCK2 is a high level after 8-bit serial transfer.
Caution If CSIE2 is set to "1" after data write to TXS/SIO2, transfer does not start.
Upon termination of 8-bit transfer, serial transfer automatically stops and the interrupt request flag (SRIF) is set.
169
[MEMO]
CHAPTER 11 SERIAL INTERFACE CHANNEL 2
170
CHAPTER 12 INTERRUPT FUNCTION
CHAPTER 12 INTERRUPT FUNCTION
12.1 Interrupt Function Types
The following three types of interrupt functions are used.
(1) Non-maskable interrupt
This interrupt is acknowledged unconditionally even in the interrupt disabled status. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.
It generates a standby release signal.
One of the non-maskable interrupts is the interrupt request from the Watchdog Timer.
(2) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specify flag register (PR0L, PR0H, PR1L).
Multiple high priority interrupts can be applied to low priority interrupts. If two or more interrupts with the same priority are simultaneously generated, each interrupts has a predetermined priority (see Table 12-1).
A standby release signal is generated.
Maskable interrupts include three external interrupt requests and eight internal interrupt requests.
(3) Software interrupt
This is a vectored interrupt that occurs when the BRK instruction is executed. It is acknowledged even in a disabled state. The software interrupt does not undergo interrupt priority control.
171
CHAPTER 12 INTERRUPT FUNCTION
12.2 Interrupt Sources and Configuration
There are a total of 13 interrupts, combining non-maskable interrupts, maskable interrupts and software interrupts
(see Table 12-1).
Interrupt
Type
Nonmaskable
Maskable
Software
Table 12-1. Interrupt Source List
Note 1
Default
Priority
—
0
3
4
1
2
5
6
7
8
9
—
Name
INTWDT
INTWDT
Interrupt Source
Trigger
Watchdog timer overflow (with watchdog timer mode 1 selected)
Watchdog timer overflow (with interval timer mode selected)
Pin input edge detection
Internal/
External
Internal
INTP1
INTP2
INTP3
INTSER
External
INTSR
INTCSI2
INTST
INTAD
INTTM5
INTTM6
BRK
Serial interface channel 2 UART reception Internal error generation
End of serial interface channel 2
UART reception
End of serial interface channel 2
3-wire transfer
End of serial interface channel 2
UART transfer
End of A/D converter conversion
Generation of 8-bit timer/event counter 5 match signal
Generation of 8 bit timer/event counter 6 match signal
BRK instruction execution —
Vector
Table
Address
0004H
Note 2
Basic
Configuration
Type
(A)
0008H
000AH
000CH
0018H
001AH
001CH
0028H
002AH
002CH
003EH
(B)
(C)
(B)
(D)
Notes 1. Default priorities are intended for two or more simultaneously generated maskable interrupts. 0 is the highest priority and 9 is the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) of Figure 12-1.
172
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-1. Basic Configuration of Interrupt Function (1/2)
(A) Internal non-maskable interrupt
Internal Bus
Interrupt
Request
Priority Control
Circuit
Vector Table
Address
Generator
Standby
Release Signal
(B) Internal maskable interrupt
Interrupt
Request
IF
MK
Internal Bus
IE PR ISP
Priority Control
Circuit
Vector Table
Address
Generator
Standby
Release Signal
173
174
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-1. Basic Configuration of Interrupt Function (2/2)
(C) External maskable interrupt
Internal Bus
External Interrupt
Mode Register
(INTM0, INTM1)
MK IE PR ISP
Interrupt
Request
Edge
Detector
IF
Priority Control
Circuit
Vector Table
Address
Generator
Standby
Release Signal
(D) Software interrupt
Internal Bus
Interrupt
Request
Remark
Priority Control
Circuit
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : Inservice priority flag
MK : Interrupt mask flag
PR : Priority specify flag
Vector Table
Address
Generator
CHAPTER 12 INTERRUPT FUNCTION
12.3 Interrupt Function Control Registers
The following five types of registers are used to control the interrupt functions.
• Interrupt request flag register (IF0L, IF0H, IF1L)
• Interrupt mask flag register (MK0L, MK0H, MK1L)
• Priority specify flag register (PR0L, PR0H, PR1L)
• External interrupt mode register (INTM0, INTM1)
• Program status word (PSW)
Table 12-2 gives a listing of interrupt request flags, interrupt mask flags, and priority specify flags corresponding to interrupt request sources.
Table 12-2. Various Flags Corresponding to Interrupt Request Sources
Interrupt Source
INTWDT
INTP1
INTP2
INTP3
INTSER
INTSR/INTCSI2
INTST
INTAD
INTTM5
INTTM6
SRIF
STIF
ADIF
TMIF5
TMIF6
TMIF4
PIF1
Interrupt Request Flag
Register
IF0L
PIF2
PIF3
SERIF IF0H
IF1L
TMMK4
PMK1
Interrupt Mask Flag
Register
MK0L
PMK2
PMK3
SERMK MK0H
SRMK
STMK
ADMK
TMMK5
TMMK6
MK1L
TMPR4
PPR1
Priority Specify Flag
Register
PR0L
PPR2
PPR3
SERPR PR0H
SRPR
STPR
ADPR
TMPR5
TMPR6
PR1L
175
CHAPTER 12 INTERRUPT FUNCTION
(1) Interrupt request flag registers (IF0L, IF0H, IF1L)
The interrupt request flag is set to 1 when the corresponding interrupt request is generated or an instruction is executed. It is cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
IF0L, IF0H, and IF1L are set with a 1-bit or 8-bit memory manipulation instruction. If IF0L and IF0H are used as a 16-bit register IF0 use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to 00H.
Symbol
IF0L
IF0H
IF1L
7
0
7
0
7
0
6
0
6
0
6
0
Figure 12-2. Interrupt Request Flag Register Format
5
0
5
0
5
0
4
PIF3
3
PIF2
2
PIF1
4 3 2
STIF SRIF SERIF
4 3 2
TMIF6 TMIF5 ADIF
1
0
1
0
1
0
0
TMIF4
0
0
0
0
Address
FFE0H
FFE1H
FFE2H
After
Reset
00H
00H
00H
R/W
R/W
R/W
R/W
× ×
IF
×
0
Interrupt Request Flag
No interrupt request signal
1 Interrupt request signal is generated;
Interrupt request state
Cautions 1. TMIF4 flag is R/W enabled only when a watchdog timer is used as an interval timer. If a watchdog timer is used in watchdog timer mode 1, set TMIF4 flag to 0.
2. Set 0 to the bits 1, 5 to 7 of IF0L and bits 0, 1, 5 to 7 of IF0H and IF1L.
176
CHAPTER 12 INTERRUPT FUNCTION
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable.
MK0L, MK0H, and MK1L are set with a 1-bit or 8-bit memory manipulation instruction. If MK0L and MK0H are used as a 16-bit register MK0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Symbol
MK0L
MK0H
MK1L
7
1
7
1
7
1
6
1
6
1
6
1
Figure 12-3. Interrupt Mask Flag Register Format
5
1
5
1
5
1
4 3 2
PMK3 PMK2 PMK
4 3 2
STMK SRMK SERMK
4 3 2
TMMK6 TMMK5 ADMK
1
1
1
1
1
1
0
TMMK4
0
1
0
1
Address
FFE4H
FFE5H
FFE6H
After
Reset
FFH
FFH
FFH
R/W
R/W
R/W
R/W
× ×
MK
×
0
Interrupt Servicing Control
Interrupt servicing enabled
1 Interrupt servicing disabled
Cautions 1. If TMMK4 flag is read when a watchdog timer is used in watchdog timer mode 1, MK0 value becomes undefined.
2. Because port 0 has a dual function as the external interrupt request input, when the output level is changed by specifying the output mode of the port function, an interrupt request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the output mode.
3. Set 1 to the bits 1, 5 to 7 of MK0L and bits 0, 1, 5 to 7 of MK0H and MK1L.
177
CHAPTER 12 INTERRUPT FUNCTION
(3) Priority specify flag registers (PR0L, PR0H, and PR1L)
The priority specify flag is used to set the corresponding maskable interrupt priority orders.
PR0L, PR0H, and PR1L are set with a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are used as a 16-bit register PR0, use a 16-bit memory manipulation instruction for the setting.
RESET input sets these registers to FFH.
Symbol
PR0L
PR0H
PR1L
7
1
7
1
7
1
6
1
6
1
6
1
Figure 12-4. Priority Specify Flag Register Format
5
1
5
1
5
1
4 3 2
PPR3 PPR2 PPR1
4 3 2
STPR SRPR SERPR
4 3 2
TMPR6 TMPR5 ADPR
1
1
1
1
1
1
0
TMPR4
0
1
0
1
Address
FFE8H
FFE9H
FFEAH
After
Reset
FFH
FFH
FFH
R/W
R/W
R/W
R/W
× ×
PR
×
0
Priority Level Selection
High priority level
1 Low priority level
Cautions 1. If a watchdog timer is used in watchdog timer mode 1, set TMPR4 flag to 1.
2. Set 1 to the bits 1, 5 to 7 of PR0L and bits 0, 1, 5 to 7 of PR0H and PR1L.
178
CHAPTER 12 INTERRUPT FUNCTION
(4) External interrupt mode register (INTM0, INTM1)
These registers set the valid edge for INTP1 to INTP3.
INTM0 and INTM1 are set by 8-bit memory manipulation instructions.
RESET input sets these registers to 00H.
Figure 12-5. External Interrupt Mode Register 0 Format
Symbol 7 6 5 4
INTM0 ES31 ES30 ES21 ES20
3
0
2
0
1
0
0
0
Address
FFECH
After
Reset
00H
R/W
R/W
0
1
1
ES21 ES20
0 0
1
0
1
INTP1 Valid Edge Selection
Falling edge
Rising edge
Setting prohibited
Both falling and rising edges
ES31 ES30
0 0
INTP2 Valid Edge Selection
Falling edge
0
1
1
1
0
1
Rising edge
Setting prohibited
Both falling and rising edges
Caution Set 0 to the bits 0 to 3.
Symbol
INTM1
7
0
6
0
5
0
Figure 12-6. External Interrupt Mode Register 1 Format
4
0
3
0
2
0
1 0
ES41 ES40
Address
FFEDH
After
Reset
00H
R/W
R/W
ES41 ES40
0
0
0
1
INTP3 Valid Edge Selection
Falling edge
Rising edge
1
1
0
1
Setting prohibited
Both falling and rising edges
Caution Set 0 to the bits 2 to 7.
179
CHAPTER 12 INTERRUPT FUNCTION
(5) Program status word (PSW)
The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged or when the BRK instruction is executed, the contents of PSW is automatically saved to the stack and the IE flag is reset to 0.
If a maskable interrupt request is acknowledged the contents of the priority specify flag of the acknowledged interrupt are transferred to the ISP flag. The contents of PSW are also saved to the stack by the PUSH PSW instruction. It is reset from the stack with the RETI, RETB, and POP PSW instructions.
RESET input sets PSW to 02H.
PSW
7
IE
Figure 12-7. Program Status Word Configuration
6
Z
5
RBS1
4 3
AC RBS0
2
0
1
ISP
0
CY
State after
Reset
02H
Used when normal instruction is executed
ISP Priority of Interrupt Currently Being Received
0 High-priority interrupt servicing
(low-priority interrupt disable)
1
Interrupt not acknowledged or low-priority interrupt request servicing
(all-maskable interrupts enable)
IE
0
1
Interrupt Request Acknowledge Enable/Disable
Disable
Enable
180
CHAPTER 12 INTERRUPT FUNCTION
12.4 Interrupt Servicing Operations
12.4.1 Non-maskable interrupt request acknowledge operation
A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt request acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts.
If a non-maskable interrupt request is acknowledged, the contents of program status word (PSW) and program counter (PC), in that order, are saved to the stack, the IE flag and ISP flag are reset (0), and the contents of the vector table are loaded in the PC and branched.
A new non-maskable interrupt request generated during execution of a non-maskable interrupt servicing program is acknowledged after the current execution of the non-maskable interrupt servicing program is terminated (following
RETI instruction execution) and one main routine instruction is executed. If a new non-maskable interrupt request is generated twice or more during non-maskable interrupt service program execution, only one non-maskable interrupt request is acknowledged after termination of the non-maskable interrupt service program execution.
The flowchart showing the flow from non-maskable interrupt request generation to acknowledgment is shown in
Figure 12-8, the non-maskable interrupt request acknowledge timing is shown in Figure 12-9, and acknowledge operation in the case where multiple non-maskable interrupt requests are generated, is shown in Figure 12-10.
181
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-8. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment
Start
WDTM4=1
(with watchdog timer mode selected)?
Yes
No
Overflow in WDT?
No
Yes
WDTM3=0
(with non-maskable interrupt selected)?
Yes
Interrupt request generation
No
Interval timer
Reset processing
WDT interrupt servicing?
No
Yes
Interrupt control register unaccessed?
No
Yes
Interrupt service start
Interrupt request held pending
WDTM : Watchdog timer mode register
WDT : Watchdog timer
CPU Instruction
TMIF4
Figure 12-9. Non-Maskable Interrupt Request Acknowledge Timing
Instruction Instruction
PSW and PC Save, Jump to Interrupt Servicing
Interrupt Sevicing
Program
Interrupt requests which generate within this space are acknowledged with
↑
timing.
TMIF4 : Watchdog timer interrupt request flag
182
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation
(a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution
Main Routine
NMI Request ➀
1 Instruction
Execution
NMI Request ➁
NMI Request ➀ Execute
NMI Request ➁ Reserve
Reserved NMI Request Processing
(b) If two non-maskable interrupt requests are generated during non-maskable interrupt servicing program execution
Main Routine
NMI Request ➀
1 Instruction
Execution
NMI
Request ➁
NMI
Request ➂
NMI Request ➀ Execute
NMI Request ➁ Reserve
NMI Request ➂ Reserve
Reserved NMI Request ➁
Processing
Cannot acknowledge NMI Request ➂
(Although multiple NMI requests may be generated twice or more, they can only be acknowledged once.)
183
CHAPTER 12 INTERRUPT FUNCTION
12.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with
ISP flag reset to 0).
The waiting time from the point when a maskable interrupt request is generated until interrupt processing is executed is as shown in Table 12-3.
Please refer to Figures 12-12 and 12-13 concerning interrupt request acknowledgement timing.
Table 12-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time Maximum Time
Note
When
××
PR=0
When
××
PR=1
7 clocks
8 clocks
32 clocks
33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock : (f
CPU
: CPU clock) f
CPU
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority with the priority specify flag is acknowledged first. Also, when the same priority is specified with the priority specify flag, the interrupt request with the higher default priority is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 12-11 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the contents are saved to the stack in the order of first, program status word (PSW), then, program counter (PC), then the IE flag is reset (0) and the contents of the acknowledged interrupt request priority specification flag are transferred to the ISP flag.
Further, the data in the vector table which has been determined with each interrupt request, are loaded into the
PC and branched.
Return from the interrupt is possible with the RETI instruction.
184
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-11. Interrupt Request Acknowledge Processing Algorithm
Start
Interrupt request reserve
Interrupt request reserve
Interrupt request reserve
Yes
Do any of the simultaneously generated
××
PR=0 interrupt requests have a high priority?
No
No
IE=1?
Yes
Vectored interrupt servicing
Yes (High priority)
No
No
× ×
IF=1?
Yes (Interrupt Request
Generation)
× ×
MK=0?
Yes
× ×
PR=0?
No (Low Priority)
Any
Simultaneously generated
××
PR=0 interrupt requests?
No
Yes
Interrupt request reserve
Any
Simultaneously generated high-priority interrupt requests?
Yes
No
Interrupt request reserve
No
IE=1?
Yes
Interrupt request reserve
No
ISP=1?
Yes
Vectored interrupt servicing
Interrupt request reserve
××
IF : Interrupt request flag
××
MK : Interrupt mask flag
××
PR : Priority specify flag
IE : Flag which controls maskable interrupt request acknowledgment (1 = enable, 0 = disable)
ISP : Flag which indicates the priority of the interrupt currently being processed. (0 = high priority interrupt being processed, 1= interrupt request not acknowledged, or low priority interrupt being processed.)
185
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time)
6 Clocks
CPU Processing Instruction Instruction
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
× ×
IF
(
× ×
PR=1)
8 Clocks
× ×
IF
(
× ×
PR=0)
7 Clocks
Remark
1 f
CPU
CPU
: CPU clock)
Figure 12-13. Interrupt Request Acknowledge Timing (Maximum Time)
25 Clocks
CPU Processing Instruction Divide Instruction
6 Clocks
PSW and PC Save,
Jump to Interrupt
Servicing
Interrupt
Servicing
Program
× ×
IF
(
× ×
PR=1)
33 Clocks
× ×
IF
(
× ×
PR=0)
1
Remark 1 clock : (f
CPU
: CPU clock) f
CPU
32 Clocks
186
CHAPTER 12 INTERRUPT FUNCTION
12.4.3 Software interrupt request acknowledge operation
A software interrupt request is acknowledged by BRK instruction execution. Software interrupt cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved to the stack in the order of first, program status word (PSW), then the program counter (PC), then the IE flag is reset (0) and the contents of the vector tables
(003EH, 003FH) are loaded into the PC and branched.
Return from the software interrupt is possible with the RETB instruction.
Caution Do not use the RETI instruction for returning from the software interrupt.
12.4.4 Multiple interrupt servicing
When another interrupt is acknowledged while an interrupt is being processed, this is called multiple interrupt.
Multiple interrupts are not generated unless interrupt request acknowledge is enabled (IE = 1) (non-maskable interrupts excepted). Also, at the point when an interrupt request is acknowledged, acknowledgment of other interrupt requests is disabled (IE = 0).Therefore, in order to enable multiple interrupts, it is necessary during interrupt processing to set the IE flag (1) using the IE instruction, and enable interrupts.
There are cases where multiple requests are not enabled even though interrupts are enabled. However, this is controlled by the priority of the interrupt. There are two interrupt priorities, the default priority and the programmable priority. Multiple interrupt control is handled by programmable priority control.
In interrupt enabled condition, when an interrupt request is generated which is the same level, or which has a higher priority than the interrupt currently being processed, it is acknowledged as a multiple interrupt. When an interrupt request is generated which has a lower priority than the interrupt currently being processed, it is not acknowledged as a multiple interrupt.
Interrupt requests which have not been permitted as multiple interrupts because of low priority or because of the interrupt being disabled, are reserved, and after the current interrupt processing has been completed, they are acknowledged after executing one of the main processing instructions.
Multiple interrupts are not permitted during non-maskable interrupt processing.
Multiple interrupt enabled interrupt requests are shown in Table 12-4, and an example of multiple interrupts is given in Figure 12-14 .
187
188
CHAPTER 12 INTERRUPT FUNCTION
Table 12-4. Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
Multiple Interrupt
Request
Non-maskable
Interrupt
Interrupt during processing
Request
Non-maskable interrupt D
Maskable interrupt ISP=0
ISP=1
E
E
Software interrupt E
E
E
E
IE=1
D
Maskable Interrupt Request
PR=0 PR=1
IE=0
D
IE=1
D
IE=0
D
D
D
D
D
E
E
D
D
D
Remarks 1.
E : Multiple interrupt enable
2.
D : Multiple interrupt disable
3.
ISP and IE are the flags contained in PSW
ISP=0 : An interrupt with higher priority is being serviced
ISP=1 : An interrupt request is not accepted or an interrupt with lower priority is being serviced
IE=0 : Interrupt request acknowledge is disabled
IE=1 : Interrupt request acknowledge is enabled
4.
PR is a flag contained in PR0L, PR0H, and PR1L
PR=0 : Higher priority level
PR=1 : Lower priority level
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-14. Multiple Interrupt Example (1/2)
Example 1.
Example of when a multiple interrupt is generated twice.
Main Processing INTxx
Servicing
INTyy
Servicing
IE=0 IE=0
EI
EI EI
IE=0
INTzz
Servicing
INTxx
(PR=1)
INTyy
(PR=0)
INTzz
(PR=0)
RETI
RETI RETI
Two interrupt requests, INTyy and INTzz, are acknowledged during processing of interrupt INTxx, and a multiple interrupt is generated. Before each interrupt request is acknowledged, the EI instruction is always executed and interrupt request acknowledgment enabled.
Example 2.
Example of when a multiple interrupt is not generated because of priority control.
Main Processing INTxx
Servicing
INTyy
Servicing
INTxx
(PR=0)
EI IE=0
EI
INTyy
(PR=1)
RETI
1 Instruction
Execution
IE=0
RETI
Interrupt request INTyy, which has been generated during processing of interrupt INTxx, and which has an interrupt priority that is lower than that of INTxx, is not acknowledged, and a multiple interrupt is not generated. Interrupt request INTyy is reserved and is acknowledged after execution of one main processing instructions.
PR = 0 : High priority level
PR = 1 : Low priority level
IE = 0 : Interrupt request acknowledge disabled
189
CHAPTER 12 INTERRUPT FUNCTION
Figure 12-14 Multiple Interrupt Example (2/2)
Example 3. Example of when a multiple interrupt is not generated because interrupts are not enabled.
Main Processing
INTxx
(PR=0)
EI
INTxx
Servicing
IE=0
INTyy
(PR=0)
RETI
INTyy
Servicing
IE=0
1 Instruction
Execution
RETI
Because interrupts are not enabled (the EI instruction is not executed) during processing of interrupt
INTxx , interrupt request INTyy is not acknowledged and a multiple interrupt is not generated. Interrupt request INTyy is reserved and acknowledged after one main processing instruction is implemented.
PR = 0 : High priority level
IE = 0 : Interrupt request acknowledge disabled.
190
CHAPTER 12 INTERRUPT FUNCTION
12.4.5 Interrupt request reserve
There are some instructions which, though an interrupt request may be generated while they are being executed, will reserve the acknowledgment of the request until after execution of the next instruction. These instructions (interrupt request reserve instructions) are shown below.
• MOV PSW, #byte
• MOV A, PSW
• MOV PSW, A
• MOV1 PSW.bit, CY
• MOV1 CY, PSW.bit
• AND1 CY, PSW.bit
• OR1 CY, PSW.bit
• XOR1 CY, PSW.bit
• SET1 PSW.bit
• CLR1 PSW.bit
• RETB
• RETI
• PUSH PSW
• POP PSW
• BT
• BF
PSW.bit, $addr16
PSW.bit, $addr16
• BTCLR PSW.bit, $addr16
• EI
• DI
• Manipulate instructions for IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, PR1L, INTM0, INTM1 registers
Caution The BRK instruction is not one of the above interrupt request reserve instructions. However in the case of software interrupts, which are activated by execution of the BRK instruction, the IE flag is cleared to 0. Therefore, even if a maskable interrupt request is generated during BRK instruction execution, the interrupt request will not be acknowledged. However, non-maskable interrupt requests will be acknowledged.
191
CHAPTER 12 INTERRUPT FUNCTION
The interrupt request reserve timing is shown in Figure 12-15.
Figure 12-15. Interrupt Request Hold
CPU processing Instruction N Instruction M
Save PSW and PC,
Jump to interrupt service
× ×
IF
Interrupt service program
Remarks 1. Instruction N: Instruction that holds interrupts requests
2. Instruction M: Instructions other than instruction N
3. The operation of
××
IF (interrupt request) is not affected by
××
PR (priority level) values.
192
CHAPTER 13 STANDBY FUNCTION
CHAPTER 13 STANDBY FUNCTION
13.1 Standby Function and Configuration
13.1.1 Standby function
The standby function is designed to decrease power consumption of the system. The following two modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock.
System clock oscillator continues oscillation. In this mode, current consumption cannot be decreased as in the STOP mode. The HALT mode is valid to restart immediately upon interrupt request and to carry out intermittent operations.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the main system clock oscillator stops and the whole system stops. CPU current consumption can be considerably decreased.
Data memory low-voltage hold (down to V
DD
= 1.8 V) is possible. Thus, the STOP mode is effective to hold data memory contents with ultra-low current consumption. Because this mode can be cleared upon interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is necessary to secure an oscillation stabilization time after the STOP mode is cleared, select the HALT mode if it is necessary to start processing immediately upon interrupt request.
In any mode, all the contents of the register, flag and data memory just before standby mode setting are held. The input/output port output latch and output buffer statuses are also held.
Cautions 1. When proceeding to the STOP mode, be sure to stop the peripheral hardware operation and execute the STOP instruction.
2. The following sequence is recommended for power consumption reduction of the A/D converter when the standby function is used: first clear bit 7 (CS) of A/D converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP instruction.
193
CHAPTER 13 STANDBY FUNCTION
13.1.2 Standby function control register
A wait time after the STOP mode is cleared upon interrupt request till the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS).
OSTS is set with an 8-bit memory manipulation instruction.
RESET input sets OSTS to 04H. However, it takes 2
17
/f
X
, not 2
18
/f
X
, until the STOP mode is cleared by RESET input.
Symbol
OSTS
7
0
6
0
Figure 13-1. Oscillation Stabilization Time Select Register Format
5
0
4
0
3
0
2 1 0
OSTS2 OSTS1 OSTS0
Address
FFFAH
After
Reset
04H
R/W
R/W
OSTS2 OSTS1 OSTS0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
Selection of Oscillation Stabilization
Time when STOP Mode is Released
MCS = 1 MCS = 0
2
12
/f xx
2
2
14
16
/f
/f xx
2
15
/f xx xx
2
17
/f xx
2
12
/f x
(819 s)
2
14
/f x
(3.28 ms)
2
15
/f x
(6.55 ms)
2
16
/f x
(13.1 ms)
2
17
/f x
(26.2 ms)
2
2
2
2
2
13
15
16
17
18
/f
/f
/f
/f
/f x x x x x
(1.64 ms)
(6.55 ms)
(13.1 ms)
(26.2 ms)
(52.4 ms)
Other than above Setting prohibited
Caution The wait time after STOP mode clear does not include the time (see "a" in the illustration below) from STOP mode clear to clock oscillation start, regardless of clearance by RESET input or by interrupt generation.
X1 Pin
Voltage
Waveform
V
SS
STOP Mode Clear a
Remarks 1. f
XX
: Main system clock frequency (f
X
or f
X
/2)
2. f
X
: Main system clock oscillation frequency
3. MCS : Oscillation mode select register (OSMS) bit 0
4. Values in parentheses when operated at f
X
= 5.0 MHz
194
CHAPTER 13 STANDBY FUNCTION
13.2 Standby Function Operations
13.2.1 HALT mode
(1) HALT mode set and operating status
The HALT mode is set by executing the HALT instruction.
The operating status in the HALT mode is described below.
Table 13-1. HALT Mode Operating Status
Clock generator
Item
CPU
Port
8-bit timer/event counter 5, 6
Watchdog timer
A/D converter
Serial interface
External interrupt request
HALT Mode Operating Status
Can be oscillated. Supply to the CPU clock is stopped.
Operation stops.
Status before HALT mode setting is held.
Operable.
195
CHAPTER 13 STANDBY FUNCTION
(2) HALT mode clear
The HALT mode can be cleared with the following three types of sources.
(a) Clear upon unmasked interrupt request
An unmasked interrupt request is used to clear the HALT mode. If interrupt acknowledge is enabled, vectored interrupt service is carried out. If disabled, the next address instruction is executed.
Figure 13-2. HALT Mode Clear upon Interrupt Generation
Standby
Release Signal
Operating
Mode
HALT
Instruction
HALT Mode
Wait
Wait Operating Mode
Oscillation
Clock
Remarks 1. The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged.
2. Wait time will be as follows:
• When vectored interrupt service is carried out: 8 to 9 clocks
• When vectored interrupt service is not carried out: 2 to 3 clocks
(b) Clear upon non-maskable interrupt request
The HALT mode is cleared and vectored interrupt service is carried out whether interrupt acknowledge is enabled or disabled.
196
CHAPTER 13 STANDBY FUNCTION
(c) Clear upon RESET input
As is the case with normal reset operation, a program is executed after branch to the reset vector address.
Figure 13-3. HALT Mode Release by RESET Input
Wait
(2
17
/f x
: 26.2 ms)
RESET
Signal
Operating
Mode
HALT
Instruction
HALT Mode
Oscillation
Clock
Reset
Period
Oscillation stop
Oscillation
Stabilization
Wait Status
Oscillation
Operating
Mode
Remarks 1. f
X
: main system clock oscillation frequency
2. Values in parentheses when operated at f x
= 5.0 MHz
Release Source
Maskable interrupt request
Non-maskable interrupt request
RESET input
Remark
×
: Don’t care
1
–
0
0
MK
××
0
0
0
–
Table 13-2. Operation after HALT Mode Release
PR
××
0
0
1
1
1
×
–
1
1
×
×
0
×
IE
0
0
1
×
×
ISP
×
×
1
Operation
Next address instruction execution
Interrupt service execution
Next address instruction execution
Interrupt service execution
HALT mode hold
Interrupt service execution
–
× ×
Reset processing
197
CHAPTER 13 STANDBY FUNCTION
13.2.2 STOP mode
(1) STOP mode set and operating status
The STOP mode is set by executing the STOP instruction.
Cautions 1. When the STOP mode is set, the X2 pin is internally connected to V
DD
via a pull-up resistor to minimize the leakage current at the crystal oscillator. Thus, do not use the STOP mode in a system where an external clock is used for the main system clock.
2. Because the interrupt request signal is used to clear the standby mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after execution of the STOP instruction. After the wait set using the oscillation stabilization time select register (OSTS), the operating mode is set.
The operating status in the STOP mode is described below.
Table 13-3. STOP Mode Operating Status
Clock generator
Item
CPU
Port
8-bit timer/event counter 5, 6
Watchdog timer
A/D converter
Serial interface
External interrupt request
STOP Mode Operating Status
Oscillation stops.
Operation stops.
Status before STOP mode setting is held.
Operable when TI5 and TI6 are selected for the count clock.
Operation stops.
Three-wire serial I/O is operable when the externally input clock is selected as the serial clock. UART operation stops.
Operable.
198
CHAPTER 13 STANDBY FUNCTION
(2) STOP mode release
The STOP mode can be cleared with the following two types of sources.
(a) Release by unmasked interrupt request
An unmasked interrupt request is used to release the STOP mode. If interrupt acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out. If interrupt acknowledge is disabled, the next address instruction is executed.
Figure 13-4. STOP Mode Release by Interrupt Generation
Wait
(Time set by OSTS) STOP
Instruction
Standby
Release Signal
Operationg
Mode
Clock
Oscillation
STOP Mode
Oscillation Stop
Oscillation Stabilization
Wait Status
Oscillation
Operating
Mode
Remark The broken line indicates the case when the interrupt request which has cleared the standby status is acknowledged.
199
200
CHAPTER 13 STANDBY FUNCTION
(b) Release by RESET input
The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out.
Figure 13-5. Release by STOP Mode RESET Input
STOP
Instruction
RESET
Signal
Operating
Mode
Clock
Oscillation
STOP Mode
Oscillation Stop
Reset
Period
Wait
(2
17
/f x
: 26.2 ms)
Oscillation
Stabilization
Wait Status
Oscillation
Operating
Mode
Remarks 1. f
X
: main system clock oscillation frequency
2. Values in parentheses when operated at f
X
= 5.0 MHz
Release Source
Maskable interrupt request
RESET input
Remark
×
: Don’t care
Table 13-4. Operation after STOP Mode Release
1
–
0
0
MK
××
0
0
0
PR
××
0
0
1
1
1
×
–
1
0
×
1
×
×
IE
0
0
1
×
×
ISP
×
×
1
Operation
Next address instruction execution
Interrupt service execution
Next address instruction execution
Interrupt service execution
STOP mode hold
Reset processing
CHAPTER 14 RESET FUNCTION
CHAPTER 14 RESET FUNCTION
14.1 Reset Function
The following two operations are available to generate the reset signal.
(1) External reset input with RESET pin
(2) Internal reset by watchdog timer overrun time detection
External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
When a low level is input to the RESET pin or the watchdog timer overflows, a reset is applied and each hardware is set to the status as shown in Table 14-1. Each pin has high impedance during reset input or during oscillation stabilization time just after reset clear.
When a high level is input to the RESET input, the reset is cleared and program execution starts after the lapse of oscillation stabilization time (2
17
/f
X
). The reset applied by watchdog timer overflow is automatically cleared after a reset and program execution starts after the lapse of oscillation stabilization time (2
17
/f
X
) (see Figure 14-2 to 14-
4).
Cautions 1. For an external reset, input a low level for 10
µ s or more to the RESET pin.
2. Main system clock oscillation stops during reset input.
3. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input.
However, the port pin becomes high-impedance.
Figure 14-1. Block Diagram of Reset Function
RESET Reset Control Circuit
Reset
Signal
Count Clock Watchdog Timer
Stop
Overflow Interrupt
Function
201
CHAPTER 14 RESET FUNCTION
Figure 14-2. Timing of Reset Input by RESET Input
X1
Normal Operation
Reset Period
(Oscillation
Stop)
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
RESET
Internal
Reset Signal
Delay
Delay
Hi-Z
Port Pin
Figure 14-3. Timing of Reset due to Watchdog Timer Overflow
X1
Watchdog
Timer
Overflow
Internal
Reset Signal
Normal Operation Reset Period
(Oscillation
Stop)
Oscillation
Stabilization
Time Wait
Normal Operation
(Reset Processing)
Hi-Z
Port Pin
Figure 14-4. Timing of Reset Input in STOP Mode by RESET Input
X1
RESET
Internal
Reset Signal
STOP Instruction Execution
Normal Operation
Stop Status
(Oscillation
Stop)
Delay
Port Pin
Reset Period
(Oscillation
Stop)
Delay
Oscillation
Stabilization
Time Wait
Hi-Z
Normal Operation
(Reset Processing)
202
CHAPTER 14 RESET FUNCTION
Program counter (PC)
Port (Output latch)
Note1
Stack pointer (SP)
Program status word (PSW)
RAM
Table 14-1. Hardware Status after Reset (1/2)
Hardware
Data memory
General register
Port 0, Port 1, Port 3, Port 5, Port 7,
Port 10 (P0, P1, P3, P5, P7, P10)
Port mode register (PM0, PM1, PM3, PM5, PM7, PM10)
Pull-up resistor option register (PUOH, PUOL)
Processor clock control register (PCC)
Oscillation mode selection register (OSMS)
Memory size switching register (IMS)
Oscillation stabilization time select register (OSTS)
Timer clock selection register 0 (TCL0)
8-bit timer/event counter
5 and 6
Timer register (TM5, TM6)
Compare registers (CR50, CR60)
Clock select register (TCL5, TCL6)
Watchdog timer
Serial Interface
A/D converter
Mode control registers (TMC5, TMC6)
Clock select register (TCL2)
Mode register (WDTM)
Mode register (CSIM2)
Asynchronous serial interface mode register (ASIM)
Asynchronous serial interface status register (ASIS)
Baud rate generator control register (BRGC)
Transmit shift register (TXS)
Receive buffer register (RXB)
Mode register (ADM)
Conversion result register (ADCR)
Input select register (ADIS)
Status after Reset
The contents of reset vector tables (0000H and 0001H) are set.
Undefined
02H
Undefined
Note2
Undefined
Note2
00H
01H
Undefined
00H
04H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
04H
00H
Note3
203
CHAPTER 14 RESET FUNCTION
Table 14-1. Hardware Status after Reset (2/2)
Interrupt
Hardware
Request flag register (IF0L, IF0H, IF1L)
Mask flag register (MK0L, MK0H, MK1L)
Priority specify flag register (PR0L, PR0H, PR1L)
External interrupt mode register (INTM0, INTM1)
Status after Reset
00H
FFH
FFH
00H
Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remains unchanged after reset.
2. The post-reset status is held in the standby mode.
3. The values after reset depend on the product.
µ
PD78081 : 82H,
µ
PD78082 : 64H,
µ
PD78P083 : 46H
204
CHAPTER 15
µ
PD78P083
CHAPTER 15
µ
PD78P083
The
µ
PD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has program write, erasure and rewrite capability.
Differences between the
µ
PD78P083 and mask ROM versions are shown in Table 15-1.
Table 15-1. Differences between the
µ
PD78P083 and Mask ROM Versions
Parameter
Internal ROM type
Internal ROM capacity
Internal high-speed RAM capacity
µ
PD78P083
One-time PROM/EPROM
24 Kbytes
512 bytes
Mask ROM Versions
Mask ROM
µ
PD78081 : 8 Kbytes
µ
PD78082 : 16 Kbytes
µ
PD78081 : 256 bytes
µ
PD78082 : 384 bytes
Disable Internal ROM and internal high-speed
RAM capacity change by internal memory size switching register (IMS)
IC pin
V
PP
pin
Electrical specifications
Enable Note
Not available
Available
Refer to a data sheet of each product
Available
Not available
Note The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512 bytes by the RESET input.
Caution Noise resistance and noise radiation differs between PROM versions and Mask ROM versions.
If studying the replacement of PROM versions with mask ROM versions in the process of prototype to volume production, do a thorough evaluation with mask ROM versions with CS versions (not ES versions).
205
CHAPTER 15
µ
PD78P083
15.1 Memory Size Switching Register
It is possible to specify the internal memory of the
µ
PD78P083 by means of the memory size switching register
(IMS). By setting the IMS, memory mapping can be made to match the memory mapping of the
µ
PD78081 and 78082, which have different internal memory.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to 46H.
Figure 15-1. Memory Size Switching Register Format
Symbol 7 6 5
IMS RAM2 RAM1 RAM0
4
0
3 2 1 0
ROM3 ROM2 ROM1 ROM0
Address
FFF0H
After
Reset
46H
R/W
R/W
ROM3 ROM2 ROM1 ROM0 Internal ROM Capacity Selection
0 0 1 0 8 Kbytes
0 1 0 0 16 Kbytes
0 1 1
Other than above
0 24 Kbytes
Setting prohibited
RAM2 RAM1 RAM0 Internal High-Speed RAM Capacity Selection
0 1 0 512 bytes
0
1
1
0
1
0
Other than above
384 bytes
256 bytes
Setting prohibited
Caution If using mask ROM versions, do not specify any values in the IMS other than when resetting.
The IMS settings to give the same memory map as mask ROM versions are shown in Table 15-2.
Table 15-2. Examples of Memory Size Switching Register Settings
Relevant Mask ROM Version
µ
PD78081
µ
PD78082
IMS Setting
82H
64H
206
CHAPTER 15
µ
PD78P083
15.2 PROM Programming
The
µ
PD78P083 incorporate a 24-Kbyte PROM as program memory, respectively. To write a program into the
µ
PD78P083 PROM, make the device enter the PROM programming mode by setting the levels of the V
PP and RESET pins as specified. For the connection of unused pins, see paragraph (2) “PROM programming
mode” in section 1.5 Pin Configuration (Top View).
Caution Perform program writing only in the 0000H to 5FFFH address range (specify the last address as 5FFFH.)
The program cannot be correctly written by a PROM programmer which does not have a write address specification function.
15.2.1 Operating modes
When +5 V or +12.5 V is applied to the V
PP
pin and a low-level signal is applied to the RESET pin, the
µ
PD78P083 are set to the PROM programming mode. This is one of the operating modes shown in Table 15-3 below according to the setting of the CE, OE, and PGM pins.
The PROM contents can be read by setting the read mode.
Table 15-3. PROM Programming Operating Modes
Pin RESET V
PP
V
DD
CE OE PGM
Operating mode
Page data latch
Page write
Byte write
Program verify
Program inhibit
Read
Output disabled
Standby
Remark
×
: L or H
L +12.5 V +6.5 V
+5 V
(1) Read mode
Read mode is set by setting CE to L and OE to L.
+5V
L
L
×
×
L
H
H
L
H
L
H
×
H
L
H
L
L
H
D0-D7
H Data input
L High impedance
L Data input
H Data output
H High impedance
L
H Data output
×
High impedance
×
High impedance
(2) Output disable mode
If OE is set to H, data output becomes high impedance and the output disable mode is set.
Therefore, if multiple
µ
PD78P083s are connected to the data bus, data can be read from any one device by controlling the OE pin.
207
CHAPTER 15
µ
PD78P083
(3) Standby mode
Setting CE to H sets the standby mode.
In this mode, data output becomes high impedance irrespective of the status of OE.
(4) Page data latch mode
Setting CE to H, PGM to H, and OE to L at the start of the page write mode sets the page data latch mode.
In this mode, 1-page 4-byte data is latched in the internal address/data latch circuit.
(5) Page write mode
After a 1-page 4-byte address and data are latched by the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=H and OE=H. After this, program verification can be performed by setting CE to L and OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X
≤
10).
(6) Byte write mode
A byte write is executed by applying a 0.1-ms program pulse (active-low) to the PGM pin while CE=L and OE=H.
After this, program verification can be performed by setting OE to L.
If programming is not performed by one program pulse, repeated write and verify operations are executed
X times (X
≤
10).
(7) Program verify mode
Setting CE to L, PGM to H, and OE to L sets the program verify mode.
After writing is performed, this mode should be used to check whether the data was written correctly.
(8) Program inhibit mode
The program inhibit mode is used when the OE pins, V
PP
pins and pins D0 to D7 of multiple
µ
PD78P083s are connected in parallel and any one of these devices must be written to.
The page write mode or byte write mode described above is used to perform a write. At this time, the write is not performed on the device which has the PGM pin driven high.
208
CHAPTER 15
µ
PD78P083
15.2.2 PROM write procedure
Address = Address + 1
Figure 15-2. Page Program Mode Flowchart
Start
Address = G
V
DD
= 6.5 V, V
PP
= 12.5 V
X = 0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
X = X + 1
0.1-ms program pulse
No
Verify 4 Bytes
Pass
Address = N?
Yes
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
Fail
Fail
Pass
All bytes verified?
All Pass
Remark:
G = Start address
N = Last address of program
No
X = 10?
Yes
End of write Defective product
209
CHAPTER 15
µ
PD78P083
Figure 15-3. Page Program Mode Timing
Page Data Latch
Page
Program Program Verify
A2-A14
A0, A1
D0-D7
V
PP
V
PP
V
DD
V
DD
V
DD
+1.5
V
DD
V
IH
CE
V
IL
V
IH
PGM
V
IL
V
IH
OE
V
IL
Data Input Data Output
210
CHAPTER 15
µ
PD78P083
Address = Address + 1
Figure 15-4. Byte Program Mode Flowchart
Start
Address = G
V
DD
= 6.5 V, V
PP
= 12.5 V
X = 0
X = X + 1
0.1-ms program pulse
No
Verify
Pass
Address = N?
Yes
V
DD
= 4.5 to 5.5 V, V
PP
= V
DD
Fail
Pass
All bytes verified?
All Pass
Fail
Remark:
G = Start address
N = Last address of program
No
X = 10?
Yes
End of write Defective product
211
CHAPTER 15
µ
PD78P083
Figure 15-5. Byte Program Mode Timing
Program Program Verify
A0-A14
D0-D7 Data Input Data Output
V
PP
V
PP
V
DD
V
DD
V
DD
+1.5
V
DD
CE
PGM
OE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
Cautions 1. Be sure to apply V
DD
before applying V
PP
, and remove it after removing V
PP
.
2. V
PP
must not exceed +13.5 V including overshoot voltage.
3. Disconnecting/inserting the device from/to the on-board socket while +12.5 V is being applied to the V
PP
pin may have an adverse affect on device reliability.
212
CHAPTER 15
µ
PD78P083
15.2.3 PROM reading procedure
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.
(1) Fix the RESET pin low, and supply +5 V to the V
PP
pin. Unused pins are handled as shown in paragraph,
(2) “PROM programming mode” in section 1.5 Pin Configuration (Top View).
(2) Supply +5 V to the V
DD
and V
PP
pins.
(3) Input the address of data to be read to pins A0 through A14.
(4) Read mode is entered.
(5) Data is output to pins D0 through D7.
The timing for steps (2) through (5) above is shown in Figure 15-6.
Figure 15-6. PROM Read Timing
A0-A14 Address Input
CE (Input)
OE (Input)
D0-D7
Hi-Z
Data Output
Hi-Z
213
CHAPTER 15
µ
PD78P083
15.3 Erasure Procedure (
µ
PD78P083DU Only)
With the
µ
PD78P083DU, it is possible to erase ( or set all contents to FFH) the data contents written in the program memory, and rewrite the memory.
The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or shorter.
Typically, data is erased by 254-nm ultraviolet light rays. The minimum lighting level to completely erase the written data is shown below.
• UV intensity
×
exposure time: 30 W
.
s/cm
2
or more
• Exposure time: 40 minutes or more (using a 12 mW/cm
2
ultraviolet lamp. A longer exposure time may be required in case of deterioration of the ultraviolet lamp or dirt on the package window).
When erasing written data, remove any filter on the window and place the device within 2.5 cm of the lamp tube.
15.4 Opaque Film Masking the Window (
µ
PD78P083DU Only)
To prevent unintentional erasure of the EPROM contents by light and to prevent internal circuits from mulfunction due to light coming in through the erasure window, mask the window with opaque film after writing the EPROM.
15.5 Screening of One-Time PROM Versions
One-time PROM versions (
µ
PD78P083CU, 78P083GB-3B4, 78P083GB-3-MTX) cannot be fully tested by NEC before shipment due to the structure of one-time PROM. Therefore, after users have written data into the PROM, screening should be implemented by user: that is, store devices at high temperature for one day as specified below, and verify their contents after the devices have returned to room temperature.
Storage Temperature
125
°
C
Storage Time
24 hours
For users who do not wish to implement screening by themselves, NEC provides such users with a charged service in which NEC performs a series of processes from writing one-time PROMs and screening them to verifying their contents for users by request. The PROM version devices which provide this service are called QTOP
TM microcontrollers. As regards the
µ
PD78P083, preparations are underway. For details, please consult an NEC sales representative.
214
CHAPTER 16 INSTRUCTION SET
CHAPTER 16 INSTRUCTION SET
This chapter describes each instruction set of the
µ
PD78083 subseries as list table. For details of its operation and operation code, refer to the separate document “78K/0 series USER’S MANUAL—Instruction (IEU-1372).”
215
CHAPTER 16 INSTRUCTION SET
16.1 Legends Used in Operation List
16.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are key words and must be described as they are. Each symbol has the following meaning.
• # : Immediate data specification
• !
: Absolute address specification
• $ : Relative address specification
• [ ] : Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description.
Identifier r rp sfr sfrp saddr saddrp addr16 addr11 addr5 word byte bit
RBn
Table 16-1. Operand Identifiers and Description Methods
Description Method
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7),
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol
Note
Special-function register symbol (16-bit manipulatable register even addresses only)
Note
FE20H-FF1FH Immediate data or labels
FE20H-FF1FH Immediate data or labels (even address only)
0000H-FFFFH Immediate data or labels
(Only even addresses for 16-bit data transfer instructions)
0800H-0FFFH Immediate data or labels
0040H-007FH Immediate data or labels (even address only)
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RB0 to RB3
Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.
Remark For special-function register symbols, refer to Table 3-2 Special-Function Register List.
216
CHAPTER 16 INSTRUCTION SET
16.1.2 Description of “operation” column
A : A register; 8-bit accumulator
X
B
: X register
: B register
C
D
E
H
: C register
: D register
: E register
: H register
L
AX
BC
DE
: L register
: AX register pair; 16-bit accumulator
: BC register pair
: DE register pair
HL
PC
: HL register pair
: Program counter
SP : Stack pointer
PSW : Program status word
CY
AC
: Carry flag
: Auxiliary carry flag
Z : Zero flag
RBS : Register bank select flag
IE : Interrupt request enable flag
NMIS : Non-maskable interrupt servicing flag
( ) : Memory contents indicated by address or register contents in parentheses
×
H
,
×
L
: Higher 8 bits and lower 8 bits of 16-bit register
: Logical product (AND)
: Logical sum (OR)
: Exclusive logical sum (exclusive OR)
—— : Inverted data addr16 : 16-bit immediate data or label jdisp8 : Signed 8-bit data (displacement value)
16.1.3 Description of “flag operation” column
(Blank) : Nt affected
0
1
×
R
: Cleared to 0
: Set to 1
: Set/cleared according to the result
: Previously saved value is restored
217
CHAPTER 16 INSTRUCTION SET
16.2 Operation List
Instruction
Group
Mnemonic
8-bit data transfer
MOV
XCH
[DE], A
A, [HL]
[HL], A
A, [HL + byte]
[HL + byte], A
A, [HL + B]
[HL + B], A
A, [HL + C]
[HL + C], A
A, r
A, saddr
A, sfr
A, !addr16
A, [DE]
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C] r, #byte saddr, #byte sfr, #byte
A, r r, A
A, saddr saddr, A
A, sfr sfr, A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
Operands
Note 3
Note 3
Note 3
Byte
Clock
Note 1 Note 2
1
2
3
1
2
2
2
2
1
1
1
1
2
1
1
2
1
1
2
1
3
2
3
3
2
2
2
2
1
1
2
3
3
4
8
8
4
8
8
4
–
6
2
6
6
8
6
4
8
4
4
–
4
–
–
8
8
–
–
4
4
2
2
4
6
–
10
10
6
6
10
7
7
9
7
5
9
5
5
6
6
7
–
10
5
5
7
5
9
9
5
5
5
5
–
–
–
7
7
Operation
A
←
(HL)
(HL)
←
A
A
←
(HL + byte)
(HL + byte)
←
A
A
←
(HL + B)
(HL + B)
←
A
A
←
(HL + C)
(HL + C)
←
A
A
↔
r
A
↔
(saddr)
A
↔
sfr
A
↔
(addr16)
A
↔
(DE)
A
↔
(HL)
A
↔
(HL + byte)
A
↔
(HL + B)
A
↔
(HL + C) r
←
byte
(saddr)
←
byte sfr
←
byte
A
←
r r
←
A
A
←
(saddr)
(saddr)
←
A
A
←
sfr sfr
←
A
A
←
(addr16)
(addr16)
←
A
PSW
←
byte
A
←
PSW
PSW
←
A
A
←
(DE)
(DE)
←
A
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed.
3. Except “r = A”
Flag
Z AC CY
× × ×
× × ×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
218
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
16-bit data transfer
8-bit operation
MOVW
XCHW
ADD
ADDC
Operands
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C] rp, #word saddrp, #word sfrp, #word
AX, saddrp saddrp, AX
AX, sfrp sfrp, AX
AX, rp rp, AX
AX, !addr16
!addr16, AX
AX, rp
A, #byte saddr, #byte
A, r r, A
Note 3
Note 3
Note 3
Note 4
Note 4
Byte
Clock
Note 1 Note 2
2
2
1
2
2
3
2
2
2
3
2
2
1
2
2
3
2
2
2
3
3
1
1
3
2
1
2
2
4
2
3
4
8
8
4
8
4
8
4
4
4
6
8
8
4
8
4
8
4
4
4
6
4
10
10
4
–
4
6
–
–
6
6
8
9
9
5
9
5
9
–
–
–
8
9
9
5
9
5
9
–
–
–
8
–
12
12
–
8
–
8
8
–
10
10
8
Operation rp
←
word
(saddrp)
←
word sfrp
←
word
AX
←
(saddrp)
(saddrp)
←
AX
AX
←
sfrp sfrp
←
AX
AX
←
rp rp
←
AX
AX
←
(addr16)
(addr16)
←
AX
AX
↔
rp
A, CY
←
A + byte
(saddr), CY
←
(saddr) + byte
A, CY
←
A + r r, CY
←
r + A
A, CY
←
A + (saddr)
A, CY
←
A + (addr16)
A, CY
←
A + (HL)
A, CY
←
A + (HL + byte)
A, CY
←
A + (HL + B)
A, CY
←
A + (HL + C)
A, CY
←
A + byte + CY
(saddr), CY
←
(saddr) + byte + CY
A, CY
←
A + r + CY r, CY
←
r + A + CY
A, CY
←
A + (saddr) + CY
A, CY
←
A + (addr16) + CY
A, CY
←
A + (HL) + CY
A, CY
←
A + (HL + byte) + CY
A, CY
←
A + (HL + B) + CY
A, CY
←
A + (HL + C) + CY
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Only when rp = BC, DE or HL
4. Except “r = A”
Flag
Z AC CY
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
219
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
8-bit operation
SUB
SUBC
AND
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
Operands
Note 3
Note 3
Note 3
Byte
Clock
Note 1 Note 2
1
2
2
3
2
2
2
2
2
3
2
2
1
2
2
3
2
2
2
3
2
2
1
2
2
3
2
2
2
3
4
8
4
8
8
8
4
4
4
6
8
8
4
8
4
8
4
4
4
6
8
8
4
8
4
8
4
4
4
6
5
9
5
9
9
9
–
–
–
8
9
9
5
9
5
9
–
–
–
8
9
9
5
9
5
9
–
–
–
8
Operation
A, CY
←
A – byte
(saddr), CY
←
(saddr) – byte
A, CY
←
A – r r, CY
←
r – A
A, CY
←
A – (saddr)
A, CY
←
A – (addr16)
A, CY
←
A – (HL)
A, CY
←
A – (HL + byte)
A, CY
←
A – (HL + B)
A, CY
←
A – (HL + C)
A, CY
←
A – byte – CY
(saddr), CY
←
(saddr) – byte – CY
A, CY
←
A – r – CY r, CY
←
r – A – CY
A, CY
←
A – (saddr) – CY
A, CY
←
A – (addr16) – CY
A, CY
←
A – (HL) – CY
A, CY
←
A – (HL + byte) – CY
A, CY
←
A – (HL + B) – CY
A, CY
←
A – (HL + C) – CY
A
←
A byte
(saddr)
←
(saddr) byte
A
←
A r r
←
r A
A
←
A (saddr)
A
←
A (addr16)
A
←
A (HL)
A
←
A (HL + byte)
A
←
A (HL + B)
A
←
A (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Flag
Z AC CY
×
×
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
×
×
× × ×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
220
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
8-bit operation
OR
XOR
CMP
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte saddr, #byte
A, r r, A
A, saddr
A, !addr16
Operands
Note 3
Note 3
Note 3
Byte
Clock
Note 1 Note 2
1
2
2
3
2
2
2
2
2
3
2
2
1
2
2
3
2
2
2
3
2
2
1
2
2
3
2
2
2
3
4
8
4
8
8
8
4
4
4
6
8
8
4
8
4
8
4
4
4
6
8
8
4
8
4
8
4
4
4
6
5
9
5
9
9
9
–
–
–
8
9
9
5
9
5
9
–
–
–
8
9
9
5
9
5
9
–
–
–
8
Operation
A
←
A byte
(saddr)
←
(saddr) byte
A
←
A r r
←
r A
A
←
A (saddr)
A
←
A (addr16)
A
←
A (HL)
A
←
A (HL + byte)
A
←
A (HL + B)
A
←
A (HL + C)
A
←
A byte
(saddr)
←
(saddr) byte
A
←
A r r
←
r A
A
←
A (saddr)
A
←
A (addr16)
A
←
A (HL)
A
←
A (HL + byte)
A
←
A (HL + B)
A
←
A (HL + C)
A – byte
(saddr) – byte
A – r r – A
A – (saddr)
A – (addr16)
A – (HL)
A – (HL + byte)
A – (HL + B)
A – (HL + C)
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
3. Except “r = A”
Flag
Z AC CY
×
×
×
×
×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
× × ×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
221
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
16-bit operation
Multiply/ divide
ADDW
SUBW
CMPW
MULU
DIVUW
Increment/ decrement
Rotate
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
Operands saddr rp rp
A, 1
A, 1
A, 1
A, 1
AX, #word
AX, #word
AX, #word
X r
C r saddr
ROR4 [HL]
BCD adjust
Bit manipulate
ROL4
ADJBA
ADJBS
MOV1
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Byte
Clock
Note 1 Note 2
1
1
1
1
1
2
1
2
1
2
1
3
2
3
3
2
2
2
2
2
2
2
4
2
4
4
25
2
4
2
6
6
6
16
3
3
3
2
3
3
2
2
3
2
10
10
4
4
–
–
–
–
–
6
–
6
–
–
–
–
–
–
–
6
–
–
6
6
–
4
4
–
6
12
12
–
–
7
7
–
7
7
8
8
–
8
8
Operation
AX, CY
←
AX + word
AX, CY
←
AX – word
AX – word
AX
←
A
×
X
AX (Quotient), C (Remainder)
←
AX
÷
C r
←
r + 1
(saddr)
←
(saddr) + 1 r
←
r – 1
(saddr)
←
(saddr) – 1 rp
←
rp + 1 rp
←
rp – 1
(CY, A
7
←
A
0
, A m – 1
←
A m
)
×
1 time
(CY, A
0
←
A
7
, A m + 1
←
A m
)
×
1 time
(CY
←
A
0
, A
7
←
CY, A m – 1
←
A m
)
×
1 time
(CY
←
A
7
, A
0
←
CY, A m + 1
←
A m
)
×
1 time
A
3 – 0
←
(HL)
3 – 0
, (HL)
7 – 4
←
A
3 – 0
,
(HL)
3 – 0
←
(HL)
7 – 4
A
3 – 0
←
(HL)
7 – 4
, (HL)
3 – 0
←
A
3 – 0
,
(HL)
7 – 4
←
(HL)
3 – 0
Decimal Adjust Accumulator after
Addition
Flag
Z AC CY
× × ×
× × ×
× × ×
× ×
× ×
× ×
× ×
× × ×
×
×
×
×
Decimal Adjust Accumulator after
Subtract
CY
←
(saddr.bit)
CY
←
sfr.bit
CY
←
A.bit
CY
←
PSW.bit
CY
←
(HL).bit
(saddr.bit)
←
CY sfr.bit
←
CY
A.bit
←
CY
PSW.bit
←
CY
(HL).bit
←
CY
× × ×
× ×
×
×
×
×
×
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
222
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
Bit manipulate
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
Operands sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
CY
CY
Byte
Clock
Note 1 Note 2
2
2
2
3
2
2
3
2
1
1
2
1
2
2
2
3
3
3
3
2
3
2
2
3
2
3
3
3
4
–
4
–
–
6
–
4
2
2
6
2
6
4
4
–
6
–
–
6
–
4
6
6
4
–
6
–
–
6
6
8
6
8
8
–
–
–
8
–
7
6
–
7
7
7
7
7
7
–
7
7
–
7
7
7
Operation
(saddr.bit)
←
1 sfr.bit
←
1
A.bit
←
1
PSW.bit
←
1
(HL).bit
←
1
(saddr.bit)
←
0 sfr.bit
←
0
A.bit
←
0
PSW.bit
←
0
(HL).bit
←
0
CY
←
1
←
0
←
CY
CY
←
CY (saddr.bit)
CY
←
CY sfr.bit
CY
←
CY A.bit
CY
←
CY PSW.bit
CY
←
CY (HL).bit
CY
←
CY (saddr.bit)
CY
←
CY sfr.bit
CY
←
CY A.bit
CY
←
CY PSW.bit
CY
←
CY (HL).bit
CY
←
CY (saddr.bit)
CY
←
CY sfr.bit
CY
←
CY A.bit
CY
←
CY PSW.bit
CY
←
CY (HL).bit
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Flag
Z AC CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
× × ×
× × ×
1
0
×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
223
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
Call/return
Stack manipulate
CALL
CALLF
CALLT
BRK
RET
RETI
RETB
PUSH
POP
MOVW
Unconditional branch
BR
BC
Conditional BNC branch
BZ
BNZ
!addr16
!addr11
[addr5]
Operands
PSW rp
PSW rp
SP, #word
SP, AX
AX, SP
!addr16
$addr16
AX
$addr16
$addr16
$addr16
$addr16
Byte
Clock
Note 1 Note 2
3
2
1
1
1
1
1
1
1
1
1
2
2
3
2
4
2
2
2
2
2
7
5
6
6
6
6
6
2
4
2
4
8
6
6
6
–
–
–
6
6
6
–
–
–
–
–
–
–
–
–
–
–
10
8
8
–
–
–
–
–
–
–
Flag
Operation
Z AC CY
(SP – 1)
←
(PC + 3)
H
, (SP – 2)
←
(PC + 3)
PC
←
addr16, SP
←
SP – 2
L
,
(SP – 1)
←
(PC + 2)
H
, (SP – 2)
←
(PC + 2)
PC
15 – 11
←
00001, PC
10 – 0
←
addr11,
SP
←
SP – 2
L
,
(SP – 1)
←
(PC + 1)
H
, (SP – 2)
←
(PC + 1)
L
,
PC
H
←
(00000000, addr5 + 1),
PC
L
←
(00000000, addr5),
SP
←
SP – 2
(SP – 1)
←
PSW, (SP – 2)
←
(PC + 1)
H
,
(SP – 3)
←
(PC + 1)
L
, PC
H
←
(003FH),
PC
L
←
(003EH), SP
←
SP – 3, IE
←
0
PC
H
←
(SP + 1), PC
L
←
(SP),
SP
←
SP + 2
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3,
NMIS
←
0
R R R
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3
(SP – 1)
←
PSW, SP
←
SP – 1
(SP – 1)
←
rp
H
SP
←
SP – 2
, (SP – 2)
←
rp
L
,
PSW
←
(SP), SP
←
SP + 1 rp
H
←
(SP + 1), rp
L
←
(SP),
SP
←
SP + 2
SP
←
word
SP
←
AX
AX
←
SP
PC
←
addr16
PC
←
PC + 2 + jdisp8
PC
H
←
A, PC
L
←
X
PC
←
PC + 2 + jdisp8 if CY = 1
PC
←
PC + 2 + jdisp8 if CY = 0
PC
←
PC + 2 + jdisp8 if Z = 1
PC
←
PC + 2 + jdisp8 if Z = 0
R
R
R
R
R
R
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
224
CHAPTER 16 INSTRUCTION SET
Instruction
Group
Mnemonic
Conditional branch
CPU control
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
Operands saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16 saddr. $addr16
RBn
10
10
–
8
8
–
8
–
–
10
Byte
Clock
Note 1 Note 2
4
3
3
4
4
3
3
3
3
4
11
11
11
–
9
11
–
9
11
11
4
4
3
4
3
2
2
3
2
2
2
2
1
2
10
–
8
–
10
6
6
8
4
2
–
–
6
6
12
12
–
12
12
–
–
10
–
–
6
6
–
–
Operation
PC
←
PC + 3 + jdisp8 if(saddr.bit) = 1
PC
←
PC + 4 + jdisp8 if sfr.bit = 1
PC
←
PC + 3 + jdisp8 if A.bit = 1
PC
←
PC + 3 + jdisp8 if PSW.bit = 1
PC
←
PC + 3 + jdisp8 if (HL).bit = 1
PC
←
PC + 4 + jdisp8 if(saddr.bit) = 0
PC
←
PC + 4 + jdisp8 if sfr.bit = 0
PC
←
PC + 3 + jdisp8 if A.bit = 0
PC
←
PC + 4 + jdisp8 if PSW. bit = 0
PC
←
PC + 3 + jdisp8 if (HL).bit = 0
PC
←
PC + 4 + jdisp8 if(saddr.bit) = 1 then reset(saddr.bit)
PC
←
PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit
PC
←
PC + 3 + jdisp8 if A.bit = 1 then reset A.bit
PC
←
PC + 4 + jdisp8 if PSW.bit = 1 then reset PSW.bit
PC
←
PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit
B
←
B – 1, then
PC
←
PC + 2 + jdisp8 if B
≠
0
C
←
C –1, then
PC
←
PC + 2 + jdisp8 if C
≠
0
(saddr)
←
(saddr) – 1, then
PC
←
PC + 3 + jdisp8 if(saddr)
≠
0
RBS1, 0
←
n
No Operation
IE
←
1(Enable Interrupt)
IE
←
0(Disable Interrupt)
Set HALT Mode
Set STOP Mode
Notes 1. When the internal high-speed RAM area is accessed or instruction with no data access
2. When an area except the internal high-speed RAM area is accessed
Flag
Z AC CY
× × ×
Remark One instruction clock cycle is one cycle of the CPU clock (f
CPU
) selected by the PCC register.
225
CHAPTER 16 INSTRUCTION SET
16.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
226
CHAPTER 16 INSTRUCTION SET r
First Operand
A
Second Operand
#byte A
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP r Note
[HL + byte] sfr saddr !addr16 PSW [DE] [HL] [HL + B] $addr16 1 None
[HL + C]
MOV MOV MOV MOV MOV MOV MOV MOV
XCH XCH XCH XCH XCH XCH XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ADD
ADDC ADDC
SUB
ADD
SUBC SUBC
AND
OR
XOR
CMP
SUB
AND
OR
XOR
CMP
ADD
ADDC ADDC
SUB
OR
XOR
CMP
ADD
SUB
SUBC SUBC
AND AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
INC
DEC
B, C DBNZ sfr saddr
!addr16
PSW
MOV MOV
MOV MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
MOV MOV
DBNZ INC
DEC
PUSH
POP
[DE]
[HL]
MOV
MOV ROR4
ROL4
[HL + byte]
[HL + B]
[HL + C]
X
C
MOV
MULU
DIVUW
Note Except r = A
227
CHAPTER 16 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
First Operand
AX rp
#word
ADDW
SUBW
CMPW
MOVW
AX
MOVW
Note rp
Note
MOVW
XCHW sfrp
MOVW saddrp
MOVW
!addr16
MOVW
SP
MOVW
None
INCW
DECW
PUSH
POP sfrp saddrp
!addr16
SP
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW MOVW
Note Only when rp = BC, DE, HL
(3) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
First Operand
A.bit
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
MOV1 sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
AND1
OR1
XOR1
MOV1
MOV1
MOV1
MOV1
$addr16 None
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
BT
BF
BTCLR
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
228
CHAPTER 16 INSTRUCTION SET
(4) Call/instructions/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
First Operand
Basic instruction BR
AX !addr16
CALL
BR
!addr11
CALLF
[addr5]
CALLT
Compound instruction
$addr16
BR
BC
BNC
BZ
BNZ
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
229
[MEMO]
CHAPTER 16 INSTRUCTION SET
230
APPENDIX A DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for the development of systems which employ the
µ
PD78083 subseries.
Figure A-1 shows the configuration of the development tools.
231
232
APPENDIX A DEVELOPMENT TOOLS
Figure A-1. Development Tool Configuration
Embedded software
• Real-time OS, OS
• Fuzzy inference development
support system
PROM programmer control software
• PG-1500 controller
Language processing software
• Assembler package
• C compiler package
• C library source file
• System simulator
• Screen debugger or
integrated debugger
• Device file
Host machine (PC or EWS)
Interface adapter (only when integrated debugger is used)
PROM writing environments
PROM programmer
Programmer adapter
PROM containing version
In-circuit emulator
Interface adapter (only when integrated debugger is used)
Emulation board
Emulation probe
Conversion socket
Target system
APPENDIX A DEVELOPMENT TOOLS
A.1 Language Processing Software
RA78K/0
Assembler Package
CC78K/0
C Compiler Package
DF78083
Note
Device File
CC78K/0-L
C Library Source File
This assembler converts a program written in mnemonics into an object code executable with a microprocontroller.
Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization.
Used in combination with optional device file (DF78083).
Part Number:
µ
S
××××
RA78K/0
This compiler converts a program written in C Language into an object code executable with an microcontroller.
Used in combination with optional assembler package (RA78K/0) and device file (DF78083).
Part Number:
µ
S
××××
CC78K/0
This is a file containing information inherent to the device.
Used in combination with optional RA78K/0, CC78K/0, SM78K0, ID78K0, or SD78K/0.
Part Number:
µ
S
××××
DF78083
This is a function source program configurating object library included in CC78K/0 C compiler.
Necessary for changing object library included in CC78K/0 in according to customer’s specifications.
Part Number:
µ
S
××××
CC78K0-L
Note The DF78083 can be used commonly with all the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0.
Remark
××××
of the part number differs depending on the host machine and OS used. Refer to the table below.
µ
S
××××
RA78K0
µ
S
××××
CC78K0
µ
S
××××
DF78083
µ
S
××××
CC78K0-L
××××
Host Machine
5A13 PC-9800 Series
5A10
7B13 IBM PC/AT and their
7B10 compatible machines
3H15 HP9000 series 300™
3P16 HP9000 series 700™
3K15 SPARCstation™
3M15 EWS-4800 series (RISC)
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
Refer to A.4
HP-UX™ (rel. 7.05B)
HP-UX (rel. 9.01)
SunOS™ (rel. 4.1.1)
EWS-UX/V (rel. 4.0)
Medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
Cartridge tape (QIC-24)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
233
APPENDIX A DEVELOPMENT TOOLS
A.2 PROM Programming Tools
A.2.1 Hardware
PG-1500
PROM programmer
PA-78P083CU
PA-78P083GB
PROM programmer adapter
This is a PROM programmer capable of programming the single-chip microcontroller with on-chip
PROM by manipulating from the stand-alone or host machine through connection of the separately available programmer adapter and the attached board. It can also program separate
PROM ICs with a capacity from 256 Kbits to 4 Mbits.
This is a PROM programmer adapter for the
µ
PD78P083, and is used connected to the PG-1500.
PA-78P083CU: 42-pin plastic shrink DIP (600 mil)
42-pin ceramic shrink DIP (with window) (600 mil)
PA-78P083GB: 44-pin plastic QFP (10
×
10 mm)
A.2.2 Software
PG-1500 controller This program controls the PG-1500 from the host machine through serial and/or parallel interface cable(s).
Part Number:
µ
S
××××
PG1500
Remark
××××
of the part number differs depending on the host machine and OS used. Refer to the table below.
µ
S
××××
PG1500
××××
Host Machine
5A13 PC-9800 Series
5A10
7B13 IBM PC/AT and their
7B10 compatible machines
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
Refer to A.4
3.5-inch 2HD
Medium
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
234
APPENDIX A DEVELOPMENT TOOLS
A.3 Debugging Tools
A.3.1 Hardware
IE-78000-R-A
In-circuit emulator
(supporting integrated
debugger)
This in-circuit emulator helps users in debugging hardware and software of an application system that includes a 78K/0 series device. This in-circuit emulator supports integrated debugger
(ID78K0). It is used with emulation probe and interface adapter that connects host machine.
IE-70000-98-IF-B
Interface adapter
IE-70000-98N-IF
Interface adapter
This is an adapter necessary when using the PC-9800 series (except notebook type) as a host machine for the IE-78000-R-A.
This is an adapter and cable necessary when using notebook type PC-9800 series as a host machine for the IE-78000-R-A.
This is an adapter necessary when using IBM PC/AT as a host machine for the IE-78000-R-A.
IE-70000-PC-IF-B
Interface adapter
IE-78000-R-SV3
Interface adapter
IE-78000-R
In-circuit emulator
(supporting screen debugger)
IE-78078-R-EM
Emulation board
IEP-78083CU-R
Emulation probe
EP-78083GB-R
Emulation probe
This is an adapter and cable necessary when using EWS as a host machine for the IE-78000-R-
A.
As Ethernet™, 10Base-5 is supported. With other mode, commercially available conversion adapter is necessary.
This is in-circuit emulator that debugs hardware and software when application system using
78K/0 series is developed. It supports screen debugger (SD78K/0), and is used with emulation probe. This emulator is connected to host machine or PROM programmer for efficient debugging.
This board is used to emulate device-specific peripheral hardware (3.0 to 5.5 V), and is used with in-circuit emulator.
This is a probe to connect an in-circuit emulator to target sytem.
This probe is designed for 42-pin plastic shrink DIP (CU type) and 42-pin ceramic shrink DIP
(DU type).
This is a probe to connect an in-circuit emulator to target system.
This probe is designed for 44-pin plastic QFP (GB-3B4, GB-3BS-MTX types).
This probe set includes a 44-pin conversion socket EV-9200G-44 for easier development of target systems
EV-9200G-44 This adapter connects the EP-78083GB-R to the target system board designed for 44-pin plastic
Conversion socket QFP (GB-3B4, GB-3BS-MTX types).
Remark EV-9200G-44s are sold in sets of five units.
235
APPENDIX A DEVELOPMENT TOOLS
A.3.2 Software (1/3)
SM78K0
System simulator
This simulator can debug target system at C source level or assembler level while simulating operation of target system on host machine.
SM78K0 runs on Windows.
By using SM78K0, logic and performance of application can be verified without in-circuit emulator independently of hardware development, so that development efficiency and software quality can be improved.
This simulator is used with optional device file (DF78083).
Part Number:
µ
S
××××
SM78K0
Remark
××××
of the part number differs depending on the host machine and OS used. Refer to the table below.
µ
S
××××
SM78K0
××××
Host Machine
AA13 PC-9800 Series
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
+
Windows (Ver. 3.0 to 3.1)
Refer to A.4
Medium
3.5-inch 2HD
3.5-inch 2HC AB13 IBM PC/AT and their compatible machines
(Windows in Japanese)
BB13 IBM PC/AT and their compatible machines
(Windows in English)
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
236
APPENDIX A DEVELOPMENT TOOLS
A.3.2 Software (2/3)
ID78K0
Integrated debugger
This is control program that debugs 78K/0 series.
This program employs Windows on personal computer and OSF/Motif™ on EWS as graphical user interface, and provides appearance and operability conforming to interface. In addition debugging functions supporting C language are reinforced. Trace result can be displayed at C level by using window integration function that associates source program, disassemble display, and memory display with trace result. Moreover, debugging efficiency of program using real-time
OS can be enhanced by using function expansion modules such as task debugger and system performance analyzer.
This program is used in combination with optional device file (DF78083).
Part Number:
µ
S
××××
ID78K0
Remark
××××
of the part number differs depending on the host machine and OS used. Refer to the table below.
µ
S
××××
ID78K0
××××
Host Machine
AA13 PC-9800 Series
Medium
3.5-inch 2HD
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
+
Windows (Ver. 3.1)
Refer to A.4 3.5-inch 2HC AB13 IBM PC/AT and their compatible machines
(Windows in Japanese)
BB13 IBM PC/AT and their compatible machines
(Windows in English)
3P16 HP9000 series 700
3K15 SPARCstation
3K13
3R16 NEWS™ (RISC)
3R13
3M15 EWS4800 series (RISC)
HP-UX (rel. 9.01)
SunOS (rel. 4.1.1)
NEWS-OS™ (6.1x)
EWS-UX/V (rel. 4.0)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
3.5-inch 2HC
1/4-inch CGMT
3.5-inch 2HC
Cartridge tape (QIC-24)
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
237
APPENDIX A DEVELOPMENT TOOLS
A.3.2 Software (3/3)
SD78K/0
Screen debugger
DF78083
Note
Device file
This program controls IE-78000-R on host machine with IE-78000-R and host machine connected with serial interface (RS-232-C).
It is used with optional device file (DF78083).
Part Number:
µ
S
××××
SD78K0
File containing device-specific information.
It is used with optional RA78K/0, CC78K/0, SM78K0, ID78K0, or SD78K/0.
Part Number:
µ
S
××××
DF78083
Note This device file can be used for any of the RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0 devices.
Remark
××××
of the part number differs depending on the host machine and OS used. Refer to the table below.
µ
S
××××
SD78K0
µ
S
××××
DF78083
××××
Host Machine
5A13 PC-9800 Series
5A10
7B13 IBM PC/AT and their
7B10 compatible machines
(Windows in Japanese)
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
Refer to A.4
Medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
238
APPENDIX A DEVELOPMENT TOOLS
A.4 OS for IBM PC
As the OS for IBM PC, the following is supported.
To run SM78K0, ID78K0, or FE9200 (refer to B.2 Fuzzy Inference Development Support System), Windows
(Ver. 3.0 to Ver. 3.1) is necessary.
OS
PC DOS
IBM DOS™
MS-DOS
Version
Ver. 5.02 to 6.3
J6.1/V
Note
to J6.3/V
Note
J5.02/V
Note
Ver. 5.0 to 6.22
5.0/V
Note
to 6.2/V
Note
Note Only English mode is supported.
Caution The task swap function is not available with this software through the function is provided in
MS-DOS version 5.0 or later.
239
APPENDIX A DEVELOPMENT TOOLS
A.5 System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series In-Circuit Emulator
If you already have an in-circuit emulator for the 78K series or the 75X/XL series, you can use that in-circuit emulator as the equivalent of the 78K/0 series in-circuit emulator IE-78000-R or IE-78000-R-A by replacing the internal break board with the IE-78000-R-BK.
Table A-1. System-Up Method from Other In-Circuit Emulator to IE-78000-R
Series Name
75X/XL series
78K/I series
78K/II series
78K/III seires
In-Circuit Emulator Owned
IE-75000-R
Note
, IE-75001-R
IE-78130-R, IE-78140-R
IE-78230-R
Note
, IE-78230-R-A,
IE-78240-R
Note
, IE-78240-R-A
IE-78320-R
Note
, IE-78327-R,
IE-78330-R, IE-78350-R
Board to be Purchased
IE-78000-R-BK
Note Maintenance product
Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A
Series Name
75X/XL series
78K/I series
78K/II series
78K/III seires
In-Circuit Emulator Owned
IE-75000-R
Note 1
, IE-75001-R
IE-78130-R, IE-78140-R
IE-78230-R
Note 1
, IE-78230-R-A,
IE-78240-R
Note 1
, IE-78240-R-A
IE-78320-R
Note 1
, IE-78327-R,
IE-78330-R, IE-78350-R
IE-78000-R
Board to be Purchased
IE-78000-R-BK
Note 2
—
Note 2
78K/0 series
Notes 1. Maintenance product
2. Partial remodeling of the frame of the in-circuit emulator and replacement of the control/ trace board with a supervisor board must be done by NEC.
240
APPENDIX A DEVELOPMENT TOOLS
Drawing and Footprint for Conversion Socket (EV-9200G-44)
Figure A-2. EV-9200G-44 Drawing (For Reference Only)
Based on EV-9200G-44
(1) Package drawing (in mm)
E
A
B
EV-9200G-44
F
M
N O
No.1 pin index
1
G
H
I
O
P
Q
R
M
N
I
J
K
L
G
H
ITEM
A
B
C
D
E
F
MILLIMETERS
15.0
10.3
10.3
15.0
4-C 3.0
0.8
5.0
12.0
14.7
5.0
12.0
14.7
8.0
7.8
2.0
1.35
0.35±0.1
EV-9200G-44-G0E
INCHES
0.591
0.406
0.406
0.591
4-C 0.118
0.031
0.197
0.472
0.579
0.197
0.472
0.579
0.315
0.307
0.079
0.053
0.014
+0.004
–0.005
241
APPENDIX A DEVELOPMENT TOOLS
Figure A-3. EV-9200G-44 Footprint (For Reference Only)
Based on EV-9200G-44
(2) Pad drawing (in mm)
G
J
K
L
C
B
A
F
G
H
K
L
I
J
ITEM
A
B
C
D
E
MILLIMETERS
15.7
EV-9200G-44-P1E
INCHES
0.618
11.0
0.8±0.02
×
10=8.0±0.05
0.8±0.02
×
10=8.0±0.05
0.031
×
0.394=0.315
+0.002
–0.002
0.031
×
0.394=0.315
+0.002
–0.002
11.0
0.433
0.433
15.7
5.00±0.08
5.00±0.08
0.5±0.02
0.618
0.197
+0.003
–0.004
0.197
+0.003
–0.004
0.02
+0.001
–0.002
0.062
+0.001
–0.002
+0.004
–0.005
+0.001
–0.002
Caution Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).
242
APPENDIX B EMBEDDED SOFTWARE
APPENDIX B EMBEDDED SOFTWARE
This section describes the embedded software which are provided for the
µ
PD78083 subseries to allow users to develop and maintain the application program for these subseries.
243
APPENDIX B EMBEDDED SOFTWARE
B.1 Real-time OS
MX78K0
OS
µ
ITRON-specification subset OS. Nucleus of MX78K0 is supplied.
This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next.
Part Number:
µ
S
××××
MX78K0-
∆∆∆
Remark
×××× and
∆∆∆
of the part number differs depending on the host machine and operating system used.
Refer to the table below.
µ
S
××××
MX78K0-
∆∆∆
∆∆∆
001
××
S01
Product outline
Evaluation object
Mass-production object
Source program
Note
Use for experimental production.
Use for mass production.
Can be purchased only when object for mass production has been purchased.
××××
5A13
Host Machine
PC-9800 Series
5A10
7B13
7B10
3H15
3P16
3K15
IBM PC/AT and their compatible machines
HP9000 series 300
HP9000 series 700
SPARCstation
3M15 EWS4800 series (RISC)
OS
MS-DOS
(Ver. 3.30 to 6.2
Note
)
Refer to A.4
HP-UX (rel. 7.05B)
HP-UX (rel. 9.01)
SunOS (rel. 4.1.1)
EWS-UX/V (rel. 4.0)
Medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
Cartridge tape (QIC-24)
Digital audio tape (DAT)
Cartridge tape (QIC-24)
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
244
APPENDIX B EMBEDDED SOFTWARE
B.2 Fuzzy Inference Development Support System
FE9000/FE9200 This program supports input of fuzzy knowledge data (fuzzy rule and membership function),
Fuzzy Knowledge Data editing (edit), and evaluation (simulation)
Creation Tool FE9200 operations on Windows.
Part Number:
µ
S
××××
FE9000 (PC-9800 series)
µ
S
××××
FE9200 (IBM PC/AT and their compatible machines)
FT9080/FT9085
Translator
This program converts fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to RA78K/0 assembler source program.
Part Number:
µ
S
××××
FT9080 (PC-9800 series)
µ
S
××××
FT9085 (IBM PC/AT and their compatible machines)
FI78K0 This program executes fuzzy inference by linking fuzzy knowledge data converted by translator.
Fuzzy Inference Module Part Number:
µ
S
××××
FI78K0 (PC-9800 series, IBM PC/AT and their compatible machines)
FD78K0
Fuzzy Inference
Debugger
This software supports evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator.
Part Number:
µ
S
××××
FD78K0 (PC-9800 series, IBM PC/AT and their compatible machines)
Remark
×××× of the part number differs depending on the host machine and operating system used. Refer to the table below.
µ
S
××××
FE9000
µ
S
××××
FT9080
µ
S
××××
FI78K0
µ
S
××××
FD78K0
××××
5A13
5A10
Host Machine
PC-9800 Series
OS
MS-DOS
(Ver. 3.30 to 6.2
Note2
)
Medium
3.5-inch 2HD
5-inch 2HD
Note The task swap function is not available with this software through the function is provided in MS-DOS version 5.0 or later.
µ
S
××××
FE9200
µ
S
××××
FT9085
µ
S
××××
FI78K0
µ
S
××××
FD78K0
××××
7B13
7B10
Host Machine
IBM PC/AT and their compatible machines
Refer to A.4
OS Medium
3.5-inch 2HC
5-inch 2HC
245
[MEMO]
APPENDIX B EMBEDDED SOFTWARE
246
APPENDIX C REGISTER INDEX
APPENDIX C REGISTER INDEX
C.1 Register Index
8-bit timer mode control register (TMC5) ............................................................................................................ 87
8-bit timer register 5 (TM5) ........................................................................................................................... 79, 84
8-bit timer register 6 (TM6) ........................................................................................................................... 79, 84
[A]
ADCR:
ADIS:
ADM:
ASIM:
ASIS:
A/D conversion result register ........................................................................................................ 121
A/D converter input select register ................................................................................................. 124
A/D converter mode register .......................................................................................................... 122
Asynchronous serial interface mode register ............................................................... 141, 149, 151
Asynchronous serial interface status register .............................................................. 143, 152, 164
[B]
BRGC: Baud rate generator control register ............................................................................. 144, 153, 165
[C]
CR50:
CR60:
CSIM2:
Compare registers 50 ....................................................................................................................... 84
Compare registers 60 ....................................................................................................................... 84
Serial operating mode register 2 ........................................................................... 140, 148, 150, 163
[E]
External interrupt mode register (INTM0) ......................................................................................................... 179
External interrupt mode register (INTM1) ................................................................................................ 125, 179
[I]
IF0H:
IF0L:
IF1L:
IMS:
INTM0:
INTM1:
Interrupt request flag register 0H .......................................................................................... 175, 176
Interrupt request flag register 0L ........................................................................................... 175, 176
Interrupt request flag register 1L ........................................................................................... 175, 176
Memory size switching register ...................................................................................................... 206
External interrupt mode register 0 ........................................................................................ 175, 179
External interrupt mode register 1 ................................................................................ 125, 175, 179
Interrupt mask flag register 0H (MK0H) ................................................................................................... 175, 177
Interrupt mask flag register 0L (MK0L) .................................................................................................... 175, 177
Interrupt mask flag register 1L (MK1L) .................................................................................................... 175, 177
[M]
MK0H:
MK0L:
MK1L:
Interrupt mask flag register 0H .............................................................................................. 175, 177
Interrupt mask flag register 0L .............................................................................................. 175, 177
Interrupt mask flag register 1L .............................................................................................. 175, 177
Memory size switching register (IMS) ............................................................................................................... 206
[O]
OSMS:
OSTS:
Oscillation mode selection register ..................................................................................... 71, 72, 76
Oscillation stabilization time select register ................................................................................... 194
247
APPENDIX C REGISTER INDEX
PM0:
PM1:
PM3:
PM5:
PM7:
PM10:
PR0H:
PR0L:
[P]
P0:
P1:
P3:
P5:
P7:
P10:
PCC:
PR1L:
PSW:
PUOH:
PUOL:
Port0 ........................................................................................................................................... 17, 55
Port1 ........................................................................................................................................... 17, 57
Port3 ........................................................................................................................................... 18, 58
Port5 ........................................................................................................................................... 18, 59
Port7 ........................................................................................................................................... 19, 60
Port10 ......................................................................................................................................... 19, 62
Processor clock control register .......................................................................................... 71, 76, 77
Port mode register 0 ......................................................................................................................... 63
Port mode register 1 ......................................................................................................................... 63
Port mode register 3 ........................................................................................................ 63, 114, 118
Port mode register 5 ......................................................................................................................... 63
Port mode register 7 ......................................................................................................................... 63
Port mode register 10 ................................................................................................................ 63, 89
Priority specify flag register 0H ............................................................................................. 175, 178
Priority specify flag register 0L .............................................................................................. 175, 178
Priority specify flag register 1L .............................................................................................. 175, 178
Program status word ........................................................................................................ 33, 175, 180
Pull-up resistor option register H ..................................................................................................... 66
Pull-up resistor option register L ...................................................................................................... 66
[R]
RXB: Receive buffer register ................................................................................................................... 139
[S]
SAR:
SFR:
Successive approximation register ................................................................................................ 121
Special-function register ...................................................................................................... 29, 37, 49
Serial operating mode register 2 (CSIM2) ............................................................................... 140, 148, 150, 163
[T]
TCL0:
TCL2:
TCL5:
TCL6:
TM5:
TM6:
TMC5:
TMC6:
TXS:
Timer clock select register 0 .......................................................................................................... 113
Timer clock select register 2 ................................................................................................. 106, 116
Timer clock select register 5 ............................................................................................................ 84
Timer clock select register 6 ............................................................................................................ 86
8-bit timer register 5 ................................................................................................................... 79, 84
8-bit timer register 6 ................................................................................................................... 79, 84
8-bit timer mode control register 5 ................................................................................................... 87
8-bit timer mode control register 6 ................................................................................................... 88
Transmit shift register ..................................................................................................................... 139
[W]
WDTM: Watchdog timer mode register ........................................................................................ 79, 103, 108
248
APPENDIX D REVISION HISTORY
APPENDIX D REVISION HISTORY
Major revisions by edition and revised chapters are shown below.
Edition
2nd
Major revisions from previous version
The following products have been already developed
µ
PD78081CU-
×××
, 78081GB-
×××
-3B4, 78082CU-
×××
,
78082GB-
×××
-3B4, 78P083CU, 78P083DU, 78P083GB-3B4
The following products have been added
µ
PD78081GB-
×××
-3BS-MTX, 78082GB-
×××
-3B4-MTX,
780P083GB-3BS-MTX, 78081GB(A)-
×××
-3B4,78082GB(A)-
×××
-3B4,
78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX,
78081GB(A2)-
×××
-3B4
Power voltage changed to V
DD
= 1.8 to 5.5V.
Throughout
1.6 78K/0 Series Development has been changed.
1.9 Differences between the
µ
PD78081, 78082, and 78P083, the
µ
PD78081(A), 78082(A), and 78P083(A), and the
µ
PD78081(A2) has been added.
Cautions regarding the use of functions in common with 2.2.5
(2) (d) ASCK has been added.
CHAPTER 1 OUTLINE
CHAPTER 2
Revised Chapter
PIN FUNCTION
Cautions concerning the Write to OSMS Command has been added to 5.3 (2) Oscillation mode select register (OSMS).
Cautions concerning external clock input in 5.4.1 Main system
clock oscillation has been changed.
CHAPTER 5 CLOCK GENERATOR
Figure 7-3. Watchdog Timer Mode Register Format, notes and CHAPTER 7 WATCHDOG TIMER cautions have been added.
Description of 7.4.2 Interval timer operation has been changed.
CHAPTER 8 CLOCK OUTPUT CONTROL
CIRCUIT
CHAPTER 10 A/D CONVERTER
Cautions with regard to rewriting TCL0 to other than same data has been added to 8.3 (1) Timer clock select register 0 (TCL0).
The HSC bit has been added to the A/D Converter Mode
Register in Figure10-1. A/D Converter Block Diagram.
10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby
function, and Cautions have been added.
Figure 11-1. Serial Interface Channel 2 Block Diagram has been corrected.
11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/
receive clock by means of main system clock have been added.
76800 bps has been added to baud rate generated from the main system clock.
CHAPTER 11 SERIAL INTERFACE
CHANNEL 2
Figure 11-10. Receive Error Timing has been corrected.
11.4.3 (c) Baud rate generator control register (BRGC) has been added.
15.1 Memory Size Switching Register has been changed from
W to R/W.
Items and cautions have been added to Table 15-1. Differences between the
µ
PD78P083 and Mask ROM Versions.
A description of the QTOP icon has been added to 15.5 Screening of One-Time PROM Versions.
CHAPTER 15
µ
PD78P083
249
APPENDIX D REVISION HISTORY
Edition
2nd
Major revisions from previous version Revised Chapter
Figure A-1. Development Tool Configuration has been changed.
APPENDIX A DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS
The following Development Tools have been added:
IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98-N-IF,
IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0
A.4 OS for IBM PC has been added.
Table A-2. System-Up Method from Other In-Circuit Emulator
to IE-78000-R-A has been added.
B.1 Real-time OS has been added.
APPENDIX B EMBEDDED SOFTWARE
250
Facsimile Message
From:
Name
Company
Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation.
Please complete this form whenever you'd like to report errors or suggest improvements to us.
Tel.
FAX
Address
Thank you for your kind support.
North America
NEC Electronics Inc.
Corporate Communications Dept.
Fax: 1-800-729-9288
1-408-588-6130
Europe
NEC Electronics (Europe) GmbH
Technical Documentation Dept.
Fax: +49-211-6503-274
South America
NEC do Brasil S.A.
Fax: +55-11-889-1689
Hong Kong, Philippines, Oceania
NEC Electronics Hong Kong Ltd.
Fax: +852-2886-9022/9044
Korea
NEC Electronics Hong Kong Ltd.
Seoul Branch
Fax: 02-528-4411
Taiwan
NEC Electronics Taiwan Ltd.
Fax: 02-719-5951
Asian Nations except Philippines
NEC Electronics Singapore Pte. Ltd.
Fax: +65-250-3583
Japan
NEC Corporation
Semiconductor Solution Engineering Division
Technical Information Support Dept.
Fax: 044-548-7900
I would like to report the following error/make the following suggestion:
Document title:
Document number: Page number:
If possible, please fax the referenced page or drawing.
Excellent Good Document Rating
Clarity
Technical Accuracy
Organization
Acceptable Poor
CS 96.8
Prenesi
Javna povezava posodobljena
Javna povezava do vašega klepeta je bila posodobljena. You may view and manage your chat links after registration here.
Javna povezava do dokumenta
Oglas