Marvell Integrated Controller 88F6281 Hardware Specifications

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88F6281

Integrated Controller

Hardware Specifications

Marvell.

Moving Forward Faster

Doc. No. MV-S104859-U0, Rev. E

December 2, 2008, Preliminary

Document Classification: Proprietary Information

88F6281

Hardware Specifications

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to hardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: Preliminary Technical Publication: 0.xx

For more information, visit our website at: www.marvell.com

Disclaimer

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.

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December 2, 2008, Preliminary

88F6281

Integrated Controller

Hardware Specifications

PRODUCT OVERVIEW

The Marvell

88F6281 is a high-performance, highly integrated controller. The 88F6281 is based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva

™

CPU core. The CPU core integrates a 256 KB L2 cache.

JTAG Interface

Processor

Sheeva™ CPU Core

16 KB-I, 16 KB-D

Up to 1.5 GHz

Cache

256 KB

External DDR

800 MHz

Memory

DDR

SDRAM

Controller

High Speed I/0

PCI Express

SATA

USB 2.0

FXS / FXO

SPI, NAND, SDIO

Security Engine

AES/DES/

3DES

SHA-1/MD5

XOR Engine

4 XOR/DMA channels

Misc

TDM

UART x2

GPIO, TWSI

Flash, SDIO

Media Interfaces

MPEG TS

Audio

Gigabit Ethernet

IEEE 1588AVB support

88F6281 Functional Block Diagram

PCI Express x1

Dual SATA ports

USB 2.0 port

MPEG2-TS

S / S/PDIF

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88F6281

Hardware Specifications

FEATURES

The 88F6281 includes:

• High-performance CPU core, running at up to

1.5 GHz, with integrated, four-way, set-associative

L1 16-KB I-cache/16-KB D-cache and unified,

256-KB, four-way, set-associative L2 cache

• High-bandwidth dual-port DDR2 memory interface

(16-bit DDR2 SDRAM @ up to 800 MHz data rate)

• PCI Express (x1) port with integrated PHY

• Two Gigabit Ethernet (10/100/1000 Mbps) MACs

• USB 2.0 port with integrated PHY

• Two SATA 2.0 ports with integrated 3 Gbps SATA II

PHY

• Security Cryptographic engine

• S/PDIF (Sony/Philips Digital Interconnect Format) /

S (Integrated Interchip Sound) Audio in/out interface

• SD/SDIO/MMC interface

• TDM SLIC/SLAC Codec interface

• Two XOR engines, each containing two XOR/DMA channels (a total of four XOR/DMA channels)

• MPEG Transport Stream (TS) interface

• SPI port with SPI flash boot support

• 8-bit NAND flash interface with boot support

• Two 16550 compatible UART interfaces

• TWSI port

• 50 multi-purpose pins

• Internal Real Time Clock (RTC)

• Interrupt controller

• Timers

• 128-bit eFuse (one-time programmable memory)

Sheeva

™

CPU core

• Up to 1.5 GHz

• 32-bit and 16-bit RISC architecture

• Compliant with v5TE architecture, as published in the ARM Architect Reference Manual, Second

Edition

• Includes MMU to support virtual memory features

• 256-KB, four-way, set-associative L2 unified cache

• 16-KB, four-way, set-associative I-cache

• 16-KB, four-way, set-associative D-cache

• 64-bit internal data bus

• Branch Prediction Unit

• Supports JTAG/ARM ICE

• Supports both Big and Little Endian modes

DDR2 SDRAM controller

• 16-bit interface

• Up to 400 MHz clock frequency (800 MHz data rate)

• DDR SDRAM with a clock ratio of 1:N and 2:N between the DDR SDRAM and the CPU core, respectively

• SSTL 1.8V I/Os

• Auto calibration of I/Os output impedance

• Supports four DRAM chip selects

• Supports all DDR devices densities up to 2 Gb

• Supports up to 32 open pages (page per bank)

• Up to 2 GB total address space

• Supports on-board DDR designs (no DIMM support)

• Supports 2T mode, to enable high-frequency operation under heavy load configuration

• Supports DRAM bank interleaving

• Supports up to a 128-byte burst per single memory access

PCI Express interface (x1)

• PCI Express Base 1.1 compatible

• Integrated low-power SERDES PHY, based on proven Marvell

SERDES technology

• Serves as a Root Complex or an Endpoint port

• x1 link width

• 2.5 Gbps data rate

• Lane polarity reversal support

• Maximum payload size of 128 bytes

• Single Virtual Channel (VC-0)

• Replay buffer support

• Extended PCI Express configuration space

• Advanced Error Reporting (AER) support

• Power management: L0s and software L1 support

• Interrupt emulation message support

• Error message support

PCI Express master specific features

• Single outstanding read transaction

• Maximum read request of up to 128 bytes

• Maximum write request of up to 128 bytes

• Up to four outstanding read transactions in

Endpoint mode

PCI Express target specific features

• Supports up to eight read request transactions

• Maximum read request size of 4 KB

• Maximum write request of 128 bytes

• Supports PCI Express access to all of the controller’s internal registers

Two Integrated GbE (10/100/1000) MAC ports

• Supports 10/100/1000 Mbps

• Dedicated DMA for data movement between memory and port

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Features

• Priority queuing on receive based on Destination

Address (DA), VLAN Tag, and IP TOS

• Layer 2/3/4 frame encapsulation detection

• TCP/IP checksum on receive and transmit

• Supports proprietary 200 Mbps Marvell MII (MMII) interface

• Supports four modes:

Port 0 RGMII, Port 1 RGMII

Port 0 RGMII, Port 1 MII/MMII

Port 0 MII/MMII, port 1 RGMII

Port 0 GMII, Port 1 N/A

• DA filtering

Precise Timing Protocol (PTP)

• Supports precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE

802.1AS draft standards

• Supports Flexible Time Application interface to distribute PTP clock and time to other devices in the system

• Optionally accepts an external clock input for time stamping

Audio Video Bridging networks

• Supports IEEE 802.1Qav draft Audio Video

Bridging networks

• Supports time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects—suitable for audio/video applications

• Supports Egress Jitter Pacer for AVB-Class A and

AVB-Class B traffic and strict priority for legacy traffic queues

USB 2.0 port

• Serves as a peripheral or host

• USB 2.0 compliant

• Integrated USB 2.0 PHY

• Enhanced Host Controller Interface (EHCI) compatible as a host

• As a host, supports direct connection to all peripheral types (LS, FS, HS)

• As a peripheral, connects to all host types (HS, FS) and hubs

• Up to four independent endpoints, supporting control, interrupt, bulk, and isochronous data transfers

• Dedicated DMA for data movement between memory and port

Two Integrated Marvell 3 Gbps (Gen2i) SATA PHYs

• Compliant with SATA II Phase 1 specifications

Supports SATA II Native Command Queuing

(NCQ), up to 128 outstanding commands per port

Fully supports first party DMA (FPDMA)

Backwards compatible with SATA I devices

• Supports SATA II Phase 2 advanced features

3 Gbps (Gen2i) SATA II speed

Port Multiplier (PM)—Performs FIS-based switching, as defined in SATA working group PM definition

Port Selector (PS)—Issues the protocol-based

Out-Of-Band (OOB) sequence for selecting the active host port

• Supports device 48-bit addressing

• Supports ATA Tag Command Queuing

SATA II Host Controller

• Enhanced-DMA (EDMA) for the SATA ports

• Automatic command execution, without host intervention

• Command queuing support, for up to 32 outstanding commands

• Separate SATA request/response queues

• 64-bit addressing support for descriptors and data buffers in system memory

• Read ahead

• Advanced interrupt coalescing

• Target mode operation—supports attaching two

88F6281 controllers through their Serial-ATA ports, enabling data communication between the

88F6281 controllers

• Advanced drive diagnostics via the ATA SMART command

Cryptographic engine

• Hardware implementation on encryption and authentication engines, to boost packet processing speed

• Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the

DDR memory

• Implements AES, DES, and 3DES encryption algorithms

• Implements SHA1 and MD5 authentication algorithms

S/PDIF / I

S Audio In/Out interface

• Either S/PDIF or I

S inputs can be active at one time

• Both S/PDIF and I

S outputs can be simultaneously active, transferring the same PCM data

S/PDIF-specific features

• Compliant with 60958-1, 60958-3, and IEC61937 specifications

• Sample rates of 44.1/48/96 kHz

• 16/20/24-bit depths

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88F6281

Hardware Specifications

S-specific features

• Sample rates of 44.1/48/96 kHz

• I

S input and I

S output operate at the same sample rate

• 16/24-bit depths

• I

S in and I

S out support independent bit depths

(16 bit/24 bit)

• Supports plain I

S, right-justified and left-justified formats

SD/SDIO/MMC host interface

• 1-bit/4-bit SDmem, SDIO, and MMC cards

• Up to 50 MHz

• Hardware generate/check CRC, on all command and data transactions on the card bus

TDM SLIC/SLAC Codec interface

• Generic interface to standard SLIC/SLAC codec devices

• Compatible with standard PCM highway formats

• TDM protocol support for two channels, up to

128 time slots

• Dedicated SPI interface for codec management

• Integrated DMA to transfer voice data to/from memory buffer

Two XOR engines and DMA

• Two XOR/DMA channels per XOR engine (for a total of four XOR/DMA channels)

• Chaining via linked-lists of descriptors

• Moves data from source interface to destination interface

• Supports increment or hold on both Source and

Destination Addresses

• Supports XOR operation, on up to eight source blocks—useful for RAID applications

• Supports iSCSI CRC-32 calculation

NAND flash controller

• 8-bit NAND flash interface

• Glueless interface to CE Care and CE Don’t Care

NAND flash devices

• Boot support

Serial Peripheral Interface (SPI) controller

• Up to 50 MHz clock

• Supports direct boot from external SPI serial flash memory

MPEG Transport Stream (TS) interface

• ISO/IEC 13818-1 standard compliant

• Supports any one of the following modes:

Parallel (8 bit) input

Parallel output

Two independent serial interfaces

• Data rate up to 80 Mbps

Two UART Interfaces

• 16550 UART compatible

• Two pins for transmit and receive operations

• Two pins for modem control functions

Two-Wire Serial Interface (TWSI)

• General purpose TWSI master/slave port

• Can also be used for serial ROM initialization

50 dedicated Multi-Purpose Pins (MPPs) for peripheral functions and general purpose I/O

• Each pin can be configured independently.

• GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts.

• Only two of the following multiplexed interfaces may be configured simultaneously:

Audio

TDM

GbE Port 0 in GMII mode or GbE Port 1

Interrupt Controller

Maskable interrupts to CPU core

(and PCI Express for a PCI Express endpoint)

Two general purpose 32-bit timers/counters

Internal architecture

• Mbus-L bus for high-performance, low-latency CPU core to DDR SDRAM connectivity

• Advanced Mbus architecture

• Dual port DDR SDRAM controller connectivity to both CPU and Mbus

Bootable from

• SPI flash

• SATA device

• NAND flash

• PCI Express

• UART (for debug purpose)

288-pin HSBGA package, 19 x 19 mm, 1 mm ball pitch

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SATA Port

Multiplier

HDD

PCI Express

Mini Card Wi-Fi

SD Card

USB Host x16

On Board DDR2

SPI Flash (op.)

88F6281

TDM x8

Audio

A/D – D/A

GbE PHY FXS

Usage Model Example: VoIP Gateway

FXO

NAND Flash

Features

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88F6281

Hardware Specifications

Product Overview ....................................................................................................................................... 3

5.1

6.1

6.2

6.3

6.4

6.5

6.6

6.7

7.1

7.2

7.3

7.4

7.5

1.1

1.2

1.3

4.1

4.2

4.3

Features....................................................................................................................................................... 4

Preface....................................................................................................................................................... 15

About this Document .......................................................................................................................................15

Related Documentation...................................................................................................................................15

Document Conventions ...................................................................................................................................16

Pin and Signal Descriptions ....................................................................................................... 17

Pin Logic .........................................................................................................................................................18

Pin Descriptions ..............................................................................................................................................19

Internal Pull-up and Pull-down Pins ................................................................................................................48

Unused Interface Strapping........................................................................................................ 49

88F6281 Pin Map and Pin List .................................................................................................... 50

Pin Multiplexing ........................................................................................................................... 51

Multi-Purpose Pins Functional Summary ........................................................................................................51

Gigabit Ethernet (GbE) Pins Multiplexing on MPP ..........................................................................................57

TSMP (TS Multiplexing Pins) on MPP.............................................................................................................59

Clocking ....................................................................................................................................... 60

Spread Spectrum Clock Generator (SSCG)....................................................................................................62

System Power Up/Down and Reset Settings ............................................................................ 63

Power-Up/Down Sequence Requirements......................................................................................................63

Hardware Reset ..............................................................................................................................................64

PCI Express Reset ..........................................................................................................................................66

Sheeva

™

CPU TAP Controller Reset..............................................................................................................66

Pins Sample Configuration..............................................................................................................................66

Serial ROM Initialization ..................................................................................................................................70

Boot Sequence................................................................................................................................................71

JTAG Interface ............................................................................................................................. 73

TAP Controller.................................................................................................................................................73

Instruction Register .........................................................................................................................................73

Bypass Register ..............................................................................................................................................74

JTAG Scan Chain ...........................................................................................................................................74

ID Register ......................................................................................................................................................74

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Table of Contents

11.1

11.2

8.1

8.2

8.3

8.4

8.5

8.6

8.7

Electrical Specifications (Preliminary) ...................................................................................... 75

Absolute Maximum Ratings ............................................................................................................................75

Recommended Operating Conditions .............................................................................................................77

Thermal Power Dissipation .............................................................................................................................79

Current Consumption ......................................................................................................................................80

DC Electrical Specifications ............................................................................................................................81

AC Electrical Specifications ............................................................................................................................86

Differential Interface Electrical Characteristics..............................................................................................118

Thermal Data (Preliminary) ....................................................................................................... 129

Package ...................................................................................................................................... 130

Part Order Numbering/Package Marking ................................................................................ 132

Part Order Numbering ...................................................................................................................................132

Package Marking ..........................................................................................................................................133

Revision History ........................................................................................................................ 134

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88F6281

Hardware Specifications

List of Tables

1 Pin and Signal Descriptions ............................................................................................................ 17

Table 1: Pin Functions and Assignments Table Key ......................................................................................19

Table 2:

Table 3:

Table 4:

Table 5:

Table 6:

Table 7:

Table 8:

Table 9:

Interface Pin Prefix Codes ................................................................................................................19

Power Pin Assignments ....................................................................................................................21

Miscellaneous Pin Assignments .......................................................................................................23

DDR SDRAM Interface Pin Assignments .........................................................................................24

PCI Express Interface Pin Assignments ...........................................................................................26

SATA Port Interface Pin Assignment ................................................................................................27

Gigabit Ethernet Port0/1 Interface Pin Assignments .......................................................................28

Serial Management Interface (SMI) Pin Assignments ......................................................................32

Table 10: USB 2.0 Interface Pin Assignments..................................................................................................33

Table 11: JTAG Pin Assignment.......................................................................................................................34

Table 12: RTC Interface Pin Assignments........................................................................................................35

Table 13: NAND Flash Interface Pin Assignment .............................................................................................36

Table 14: MPP Interface Pin Assignment .........................................................................................................37

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment ............................................................38

Table 16: UART Port 0/1 Interface Pin Assignment .........................................................................................39

Table 17: Audio (S/PDIF / I

S) Interface Signal Assignment ............................................................................40

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................41

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................42

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................43

Table 21: Transport Stream (TS) Interface Signal Assignment ........................................................................45

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................47

Table 23: Internal Pull-up and Pull-down Pins ..................................................................................................48

2 Unused Interface Strapping ............................................................................................................. 49

Table 24: Unused Interface Strapping ..............................................................................................................49

3 88F6281 Pin Map and Pin List ......................................................................................................... 50

4 Pin Multiplexing ................................................................................................................................ 51

Table 25: MPP Functionality .............................................................................................................................52

Table 26: MPP Function Summary ...................................................................................................................53

Table 27: Ethernet Ports Pins Multiplexing .......................................................................................................57

Table 28: TS Port Pin Multiplexing .................................................................................................................59

5 Clocking............................................................................................................................................. 60

Table 29: 88F6281Clocks .................................................................................................................................60

Table 30: Supported Clock Combinations ........................................................................................................61

6 System Power Up/Down and Reset Settings ................................................................................. 63

Table 31: I/O and Core Voltages ......................................................................................................................63

Table 32: Reset Configuration ..........................................................................................................................67

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List of Tables

7 JTAG Interface .................................................................................................................................. 73

Table 33: Supported JTAG Instructions............................................................................................................73

Table 34: IDCODE Register Map .....................................................................................................................74

8 Electrical Specifications (Preliminary) ........................................................................................... 75

Table 35: Absolute Maximum Ratings ..............................................................................................................75

Table 36: Recommended Operating Conditions...............................................................................................77

Table 37: Thermal Power Dissipation ...............................................................................................................79

Table 38: Current Consumption........................................................................................................................80

Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................81

Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications .............................................................82

Table 41: SDRAM DDR2 Interface DC Electrical Specifications ......................................................................83

Table 42: TWSI Interface 3.3V DC Electrical Specifications.............................................................................84

Table 43: SPI Interface 3.3V DC Electrical Specifications................................................................................84

Table 44: TDM Interface 3.3V DC Electrical Specifications..............................................................................85

Table 45: Reference Clock AC Timing Specifications ......................................................................................86

Table 46: SDRAM DDR2 Interface AC Timing Table .......................................................................................88

Table 47: SDRAM DDR2 Interface Address Timing Table ...............................................................................89

Table 48: SDRAM DDR2 Clock Specifications .................................................................................................90

Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V ..................................................................................93

Table 50: RGMII 10/100 AC Timing Table at 3.3V ...........................................................................................93

Table 51: GMII AC Timing Table ......................................................................................................................95

Table 52: MII/MMII MAC Mode AC Timing Table .............................................................................................97

Table 53: SMI Master Mode AC Timing Table..................................................................................................99

Table 54: JTAG Interface AC Timing Table ....................................................................................................101

Table 55: TWSI Master AC Timing Table .......................................................................................................103

Table 56: TWSI Slave AC Timing Table .........................................................................................................103

Table 57: S/PDIF AC Timing Table ................................................................................................................105

Table 58: Inter-IC Sound (I2S) AC Timing Table ............................................................................................107

Table 59: TDM Interface AC Timing Table .....................................................................................................109

Table 60: SPI (Master Mode) AC Timing Table ..............................................................................................111

Table 61: SDIO Host in High Speed Mode AC Timing Table .........................................................................113

Table 62: Transport Stream Output Interface AC Timing Table ....................................................................115

Table 63: Transport Stream Input Interface AC Timing Table ........................................................................115

Table 64: PCI Express Interface Differential Reference Clock Characteristics ..............................................118

Table 65: PCI Express Interface Spread Spectrum Requirements.................................................................119

Table 66: PCI Express Interface Driver and Receiver Characteristics ...........................................................120

Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics ...............................................123

Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................124

Table 69: USB Low Speed Driver and Receiver Characteristics ....................................................................125

Table 70: USB Full Speed Driver and Receiver Characteristics.....................................................................126

Table 71: USB High Speed Driver and Receiver Characteristics ...................................................................127

9 Thermal Data (Preliminary) ............................................................................................................ 129

Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary) .............................129

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Hardware Specifications

10 Package ........................................................................................................................................... 130

Table 73: HSBGA 288-pin Package Dimensions ...........................................................................................131

11 Part Order Numbering/Package Marking...................................................................................... 132

Table 74: 88F6281 Part Order Options ..........................................................................................................132

A Revision History ............................................................................................................................. 134

Table 75: Revision History ..............................................................................................................................134

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List of Figures

List of Figures

1 Pin and Signal Descriptions ........................................................................................................... 17

Figure 1: 88F6281 Pin Logic Diagram ............................................................................................................18

2 Unused Interface Strapping ............................................................................................................ 49

3 88F6281 Pin Map and Pin List ........................................................................................................ 50

4 Pin Multiplexing ............................................................................................................................... 51

5 Clocking............................................................................................................................................ 60

6 System Power Up/Down and Reset Settings ................................................................................ 63

Figure 2: Power-Up Sequence Example..........................................................................................................64

Figure 3: Serial ROM Data Structure ...............................................................................................................70

Figure 4: Serial ROM Read Example...............................................................................................................71

7 JTAG Interface ................................................................................................................................. 73

8 Electrical Specifications (Preliminary) .......................................................................................... 75

Figure 5: SDRAM DDR2 Interface Test Circuit ................................................................................................91

Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram .........................................................................91

Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram .................................................92

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram .........................................................................92

Figure 9: RGMII Test Circuit ............................................................................................................................94

Figure 10: RGMII AC Timing Diagram ...............................................................................................................94

Figure 11: GMII Test Circuit ...............................................................................................................................95

Figure 12: GMII Output AC Timing Diagram ......................................................................................................96

Figure 13: GMII Input AC Timing Diagram.........................................................................................................96

Figure 14: MII/MMII MAC Mode Test Circuit......................................................................................................97

Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram...................................................................97

Figure 16: MII/MMII MAC Mode Input AC Timing Diagram................................................................................98

Figure 17: MDIO Master Mode Test Circuit .......................................................................................................99

Figure 18: MDC Master Mode Test Circuit ......................................................................................................100

Figure 19: SMI Master Mode Output AC Timing Diagram ...............................................................................100

Figure 20: SMI Master Mode Input AC Timing Diagram ..................................................................................100

Figure 21: JTAG Interface Test Circuit ............................................................................................................101

Figure 22: JTAG Interface Output Delay AC Timing Diagram .........................................................................102

Figure 23: JTAG Interface Input AC Timing Diagram ......................................................................................102

Figure 24: TWSI Test Circuit............................................................................................................................104

Figure 25: TWSI Output Delay AC Timing Diagram.........................................................................................104

Figure 26: TWSI Input AC Timing Diagram .....................................................................................................104

Figure 27: S/PDIF Test Circuit .........................................................................................................................106

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Hardware Specifications

Figure 28: Inter-IC Sound (I2S) Test Circuit ....................................................................................................107

Figure 29: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................108

Figure 30: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................108

Figure 31: TDM Interface Test Circuit ..............................................................................................................109

Figure 32: TDM Interface Output Delay AC Timing Diagram...........................................................................110

Figure 33: TDM Interface Input Delay AC Timing Diagram..............................................................................110

Figure 34: SPI (Master Mode) Test Circuit ......................................................................................................111

Figure 35: SPI (Master Mode) Output AC Timing Diagram .............................................................................112

Figure 36: SPI (Master Mode) Input AC Timing Diagram ................................................................................112

Figure 37: Secure Digital Input/Output (SDIO) Test Circuit .............................................................................113

Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram .........................................................114

Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram............................................................114

Figure 40: Transport Stream Interface Test Circuit..........................................................................................116

Figure 41: Transport Stream Output Interface AC Timing Diagram ................................................................116

Figure 42: Transport Stream Input Interface AC Timing Diagram ...................................................................117

Figure 43: PCI Express Interface Test Circuit..................................................................................................121

Figure 44: Low/Full Speed Data Signal Rise and Fall Time ............................................................................127

Figure 45: High Speed TX Eye Diagram Pattern Template .............................................................................128

Figure 46: High Speed RX Eye Diagram Pattern Template.............................................................................128

9 Thermal Data (Preliminary) ........................................................................................................... 129

10 Package .......................................................................................................................................... 130

Figure 47: HSBGA 288-pin Package and Dimensions ...................................................................................130

11 Part Order Numbering/Package Marking..................................................................................... 132

Figure 48: Sample Part Number ......................................................................................................................132

Figure 49: Commercial Package Marking and Pin 1 Location .........................................................................133

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Preface

About this Document

Preface

About this Document

This datasheet provides the hardware specifications for the 88F6281 integrated controller. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications.

This datasheet is intended to be the basic source of information for designers of new systems.

In this document, the “88F6281” is often referred to as the “device”.

Document Conventions

The following conventions are used in this document:

Signal Range

Active Low Signals #

A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb).

Example: DB_Addr[12:0]

An n letter at the end of a signal name indicates that the signal’s active state occurs when voltage is low.

Example: INTn

State Names

Conventions

State names are indicated in italic font.

Example: linkfail

Example: <RegInit>

Example: Field [1:0]

Example: 0x0

Reserved: The contents of the register are reserved for internal use only or for future use.

A lowercase <n> in angle brackets in a register indicates that there are multiple registers with this name.

Example: Multicast Configuration Register<n>

Reset Values

Abbreviations

Reset values have the following meanings:

0 = Bit clear

1 = Bit set

Kb: kilobit

KB: kilobyte

Mb: megabit

MB: megabyte

Gb: gigabit

GB: gigabyte

Numbering Conventions Unless otherwise indicated, all numbers in this document are decimal (base 10).

An 0x prefix indicates a hexadecimal number.

An 0b prefix indicates a binary number.

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Pin and Signal Descriptions

Pin and Signal Descriptions

This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality.

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MPP[49:0]

NF_IO[7:0]

NF_CLE

NF_ALE

NF_CEn

NF_REn

NF_WEn

JT_CLK

JT_TDI

JT_TDO

JT_TMS_CPU

JT_TMS_CORE

JT_RSTn

SATA0_T_P

SATA0_T_N

SATA0_R_P

SATA0_R_N

SATA1_T_P

SATA1_T_N

SATA1_R_P

SATA1_R_N

RTC_XIN

RTC_XOUT

VDD

VDD_CPU

VDDO

VDD_GE_A

VDD_GE_B

VDD_M

VSS

CPU_PLL_AVDD

CPU_PLL_AVSS

CORE_PLL_AVDD

CORE_PLL_AVSS

XTAL_AVDD

XTAL_AVSS

PEX_AVDD

SATA0_AVDD

SATA1_AVDD

USB_AVDD

RTC_AVDD

RTC_AVSS

SSCG_AVDD

SSCG_AVSS

VHV

88F6281

Hardware Specifications

1.1 Pin Logic

Figure 1: 88F6281 Pin Logic Diagram

Power

MPP

NAND

Flash

JTAG

SATA0/1

RTC

Misc.

PCI Express

USB

Gigabit Ethernet

SDRAM

REF_CLK_XIN

XOUT

SYSRSTn

ISET

RESERVED

MRn

PEX_CLK_P

PEX_CLK_N

PEX_TX_P

PEX_TX_N

PEX_RX_P

PEX_RX_N

PEX_ISET

USB_DP

USB_DM

GE_TXCLKOUT

GE_TXD[3:0]

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

GE_MDC

GE_MDIO

M_CLKOUT

M_CLKOUTn

M_CKE

M_RASn

M_CASn

M_WEn

M_A[14:0]

M_BA[2:0]

M_CSn[3:0]

M_DQ[15:0]

M_DQS[1:0]

M_DQSn[1:0]

M_DM[1:0]

M_ODT[1:0]

M_STARTBURST

M_STARTBURST_IN

M_PCAL

M_NCAL

NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock.

For details about MPP configuration options see Section 4.1, Multi-Purpose Pins Functional

Summary, on page 51 .

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1.2

Pin and Signal Descriptions

Pin Descriptions

Pin Descriptions

This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes.

Table 1<Default ¬¹ Font> defines the abbreviations and acronyms used in the pin description tables.

Table 1: Pin Functions and Assignments Table Key

DDR

GND

HCSL

I/O

O o/d

Te r m

[n]

<n>

Analog

Calib

CML

CMOS

Power

SSTL t/s

XXXn

D e f i n i t i o n n - Represents the SERDES pair number

Represents port number when there are more than one ports

Analog Driver/Receiver or Power Supply

Calibration pad type

Common Mode Logic

Complementary Metal-Oxide-Semiconductor

Double Data Rate

Ground Supply

High-speed Current Steering Logic

Input

Input/Output

Output

Open Drain pin

The pin allows multiple drivers simultaneously (wire-OR connection).

A pull-up is required to sustain the inactive value.

VDD Power Supply

Stub Series Terminated Logic for 1.8V

Tri-State pin n - Suffix represents an Active Low Signal

Table 2: Interface Pin Prefix Codes

I n t e r f a c e

Misc

DDR SDRAM

PCI Express

SATA

Gigabit Ethernet

USB 2.0

JTAG

P r e f i x

N/A

PEX_

SATA0_

SATA1_

GE_

USB_

JT_

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Hardware Specifications

Table 2: Interface Pin Prefix Codes (Continued)

I n t e r f a c e

RTC RTC_

NAND Flash NF_

MPP

TWSI

N/A

TW_

UART

P r e f i x

UA0_

UA1_

Audio

SPI

AU_

SPI_

SDIO SD_

TDM TDM_

PTP PTP_

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Pin and Signal Descriptions

Pin Descriptions

1.2.1 Power Supply Pins

Table 3 provides the voltage levels for the various interface pins. These do not include the analog power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables.

Table 3: Power Pin Assignments

P i n N a m e

VDD

VDD_CPU

VDDO

VDD_GE_A I

I / O P i n

Ty p e

Power

VDD_GE_B

VDD_M

VSS

CPU_PLL_AVDD

CPU_PLL_AVSS

CORE_PLL_AVDD

CORE_PLL_AVSS

SSCG_AVDD

SSCG_AVSS

XTAL_AVDD

XTAL_AVSS

VHV

I Power

Power

GND

Power

GND

Power

GND

Power

GND

Power

GND

Power

D e s c r i p t i o n

1.0V Digital core voltage

1.1V Digital CPU voltage

3.3V I/O power for MPP[49:36],MPP[19:0] and JTAG pins

1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces

3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces

I/O power for MPP[35:20]

1.8V or 3.3V I/O supply voltage for RGMII interfaces

3.3V I/O supply voltage for GMII and MII/MMII interfaces

1.8V I/O supply voltage for the DDR2 SDRAM interface

VSS

1.8V analog quiet power to CPU PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

CPU PLL ground

1.8V analog quiet power to Core PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

Core PLL ground

1.8V quiet power supply to the internal Spread Spectrum Clock

Generator

Ground for the internal Spread Spectrum Clock Generator

1.8V analog quiet power to on-chip clock inverter for supporting external crystal, and on-chip current reference for SATA and USB PHYs

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

Ground for supporting external crystal, and on-chip current reference for

SATA and USB PHYs

I/O supply voltage for eFuse:

• 2.5V for eFuse burning only

• 1.0V for eFuse reading only

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Table 3: Power Pin Assignments (Continued)

P i n N a m e D e s c r i p t i o n

PEX_AVDD I

I / O P i n

Ty p e

Power

SATA0_AVDD

SATA1_AVDD

USB_AVDD

RTC_AVDD

RTC_AVSS I

I Power

Power

GND

PCI Express PHY quiet power supply 1.8V

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

SATA II port0/1 quiet 3.3V power supply

NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation.

USB 2.0 PHY quiet 3.3V power supply

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendation.

1.5V (via battery) or 1.8V (via the board) RTC interface voltage

RTC ground

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Pin and Signal Descriptions

Pin Descriptions

1.2.2 Miscellaneous Pin Assignment

The Miscellaneous signal list contains clock and reset, test, and related signals.

Table 4: Miscellaneous Pin Assignments

P i n N a m e

REF_CLK_XIN

XOUT

SYSRSTn

SYSRST_OUTn

PEX_RST_OUTn

ISET

MRn

RESERVED

I / O P i n

Ty p e

Analog

CMOS

Analog

CMOS

P o w e r

R a i l

D e s c r i p t i o n

XTAL_AVDD Reference clock input from external oscillator or input from external crystal. Used as input to core, CPU, SATA, and USB

PLLs.

XTAL_AVDD XTAL_OUT

Feedback signal to external crystal.

When not used, leave this pin floating.

VDDO System reset

Main reset signal of the device clock. Used to reset all units to their initial state.

When in the reset state, most output pins are in Tri-State.

VDDO Reset request from the device to the board reset logic.

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51 ).

VDDO

VDD_GE_A

Optional PCI Express Endpoint card reset output

This pin is multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51 ).

Analog Test Point for SATA, USB, and PCI Express interfaces

For internal use. Leave this pin unconnected.

Current reference for both the USB and SATA PHYs.

Terminate this pin with a 6.04 k

resistor, pulled down.

Active-Low, Manual Reset Input

SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low, and for additional 20 ms after MRn

(manual reset) de-assertion

This pin is internally pulled up.

Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

Reserved for Marvell

¬Æ

future usage.

Leave unconnected externally.

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Hardware Specifications

1.2.3 DDR SDRAM Interface Pin Assignments

Table 5: DDR SDRAM Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

O SSTL

P o w e r

R a i l

VDD_M

D e s c r i p t i o n

SDRAM Differential Clock Pair M_CLKOUT

M_CLKOUTn

M_CKE O SSTL VDD_M

M_RASn

M_CASn

M_WEn

M_A[14:0]

M_BA[2:0]

M_CSn[3:0]

M_DQ[15:0]

M_DQS[1:0],

M_DQSn[1:0]

M_DM[1:0]

M_ODT[1:0]

O t/s

I/O t/s

I/O

SSTL

VDD_M

Driven high to enable SDRAM clock.

Driven low when setting the SDRAM to Self-refresh mode.

SDRAM Row Address Select

Asserted to indicate an active ROW address driven on the

SDRAM address lines.

SDRAM Column Address Select

Asserted to indicate an active column address driven on the

SDRAM address lines.

SDRAM Write Enable

Asserted to indicate a write command to the SDRAM.

SDRAM Address

Driven with M_BA[2:0] during RASn and CASn cycles to generate the SDRAM address.

Driven during M_RASn and M_CASn cycles to select one of the eight SDRAM virtual banks.

NOTE: If an SDRAM device does not support the BA[2] pin, leave the M_BA[2] unconnected.

SDRAM Chip Selects

Asserted to select a specific SDRAM Physical bank.

SDRAM Data Bus

Driven during write.

Driven by SDRAM during reads.

SDRAM Data Strobe

Driven by the 88F6281 during write.

Driven by SDRAM during reads.

SDRAM Data Mask

Asserted by the 88F6281 to select the specific byte out of the

16-bit data to be written to the SDRAM.

SDRAM On Die Termination control

Driven high to connect the SDRAM on die termination.

Driven low to disconnect the SDRAM’s termination.

NOTE: For the recommended setting, refer to the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

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Pin Descriptions

Table 5: DDR SDRAM Interface Pin Assignments (Continued)

P i n N a m e D e s c r i p t i o n

M_STARTBURST

I / O P i n

Ty p e

O SSTL

P o w e r

R a i l

VDD_M

I SSTL VDD_M

Start Burst

88F6281 indication of starting a burst read transaction.

Asserted with the first M_CASn cycle of SDRAM access.

NOTE: Must be routed on board to the SDRAM, and back to the 88F6281 as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 88F6180, 88F6190,

88F6192, and 88F6281 Design Guide.

Start Burst Input M_START

BURST_IN

M_PCAL I Calib

M_NCAL I Calib

SDRAM interface P channel output driver calibration. Connect to VSS through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the calibration resistors.

SDRAM interface N channel output driver calibration. Connect to M_VDD through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the calibration resistors.

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Hardware Specifications

1.2.4 PCI Express Interface Pin Assignments

Table 6: PCI Express Interface Pin Assignments

P i n N a m e

PEX_CLK_P/N

PEX_TX_P/N

PEX_RX_P/N

PEX_ISET I

I / O P i n

Ty p e

I/O HCSL

O CML

CML

Analog

P o w e r

R a i l

D e s c r i p t i o n

PEX_AVDD PCI Express Reference Clock

100 MHz, differential

This clock can be configured as input or output according to the reset strap (see Table 32, Reset Configuration, on page 67 ).

NOTE: For Output mode, 50-ohm, pull-down resistors are required.

PEX_AVDD Transmit Lane

Differential pair of PCI Express transmit data

PEX_AVDD Receive Lane

Differential pair of PCI Express receive data

Current reference. Pull down to VSS through a 5 k

resistor.

See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for the recommended resistor value.

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Pin and Signal Descriptions

Pin Descriptions

1.2.5 SATA Interface Pin Assignments

Table 7: SATA Port Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

O CML

P o w e r R a i l D e s c r i p t i o n

SATA0_T_P/N

SATA1_T_P/N

SATA0_R_P/N

SATA1_R_P/N

SATA0_PRESENTn

SATA1_PRESENTn

CML

SATA0/1_AVDD Transmit Data: Differential analog output of SATA II port0/1

SATA0/1_AVDD Receive Data: Differential analog input of SATA II port0/1

CMOS VDDO/

VDD_GE_B

SATA0_ACTn

SATA1_ACTn

O CMOS VDDO/

VDD_GE_B

When this signal is asserted there is an active link between the SATA II port and the external device (disk).

NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51 ).

When this signal is asserted, there is an active and used link between the SATA II port and the external device

(disk).

NOTE: These signals are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51 ).

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Hardware Specifications

1.2.6 Gigabit Ethernet Port Interface Pin Assignments

For additional information about the Gigabit Ethernet port pin functions refer to Section 4.2, Gigabit

Ethernet (GbE) Pins Multiplexing on MPP, on page 57 .

Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

Port0—Dedicated GbE Pins

GE_TXCLKOUT t/s

CMOS

P o w e r

R a i l

D e s c r i p t i o n

GE_TXD[3:0]

I t/s

O t/s

CMOS

VDD_GE_A RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and

GE_TXCTL.

Provides 125 MHz, 25 MHz or 2.5 MHz clock.

Not used in MII/MMII mode.

MII/MMII Transmit Clock

MII/MMII transmit reference clock from PHY.

Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

VDD_GE_A RGMII Transmit Data

Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge.

MII/MMII Transmit Data

Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data

Contains the transmit data nibble outputs.

VDD_GE_A RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge.

GE_TXEN is driven on the rising edge of GE_TXCLKOUT.

A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock.

GMII Transmit Enable

Indicates that the packet is being transmitted to the PHY.

It Is synchronous to GE_TXCLKOUT.

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Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK I

I / O P i n

Ty p e

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input rising/falling edge.

MII/MMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input.

GMII Receive Data

Contains the receive data nibble inputs.

VDD_GE_A RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK.

A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid

GMII Receive Data Valid.

VDD_GE_A RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock

Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Receive Clock

Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at

125 MHz

Port1—Multiplexed GbE Pins

MPP[23:20]/

GE1[3:0] t/s

CMOS VDD_GE_B RGMII Transmit Data

Contains the transmit data nibble outputs that run at double data rate with bits [3:0] presented on the rising edge of

GE_TXCLKOUT and bits [7:4] presented on the falling edge.

MII/MMII Transmit Data

Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data

Contains the transmit data nibble outputs.

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Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

MPP[27:24]/

GE1[7:4]

MPP[28]/GE1[8]

MPP[29]/GE1[9]

MPP[30]/GE1[10] I

MPP[31]/GE1[11] I

I / O P i n

Ty p e

CMOS t/s

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_B RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input rising/falling edge.

MII/MMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input.

GMII Receive Data

Contains the receive data nibble inputs.

VDD_GE_B MII/MMII Collision Detect

Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock.

GMII Collision Detect

VDD_GE_B MII/MMII Transmit Clock

MII/MMII transmit reference clock from PHY.

Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

VDD_GE_B RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK.

A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid

GMII Receive Error

VDD_GE_B RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock

Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

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Table 8: Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e I / O P i n

Ty p e

MPP[32]/GE1[12] I/O CMOS

MPP[33]/GE1[13] t/s

CMOS

MPP[34]/GE1[14] O

MPP[35]/GE1[15] I

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_B RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and

GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock.

Not used in MII/MMII mode.

MII/MMII Carrier Sense

Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock.

GMII Carrier Sense

VDD_GE_B RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge.

GE_TXEN is presented on the rising edge of GE_TXCLKOUT.

A logical derivative of transmit enable transmit error is presented on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Error

It is synchronous to transmit clock.

NOTE: Multiplexed on MPP.

GMII Transmit Error

It Is synchronous to GE_TXCLKOUT.

NOTE: Multiplexed on MPP.

VDD_GE_B MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock.

VDD_GE_B MII/MMII Receive Error

Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to

GE_RXCLK input.

NOTE: Multiplexed on MPP.

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1.2.7 Serial Management Interface (SMI) Interface Pin

Assignments

Table 9: Serial Management Interface (SMI) Pin Assignments

P i n N a m e

GE_MDC

GE_MDIO

I / O P i n

Ty p e t/s

CMOS/ t/s

I/O

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A Management Data Clock

MDC is derived from TCLK divided by 128.

Provides the timing reference for the transfer of the MDIO signal.

VDD_GE_A Management Data In/Out

Used to transfer control and status information between PHY devices and the GbE controller.

NOTE: An external pullup is required.

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Pin Descriptions

1.2.8 USB 2.0 Interface Pin Assignments

Table 10: USB 2.0 Interface Pin Assignments

P i n N a m e

USB_DP

USB_DM

I / O

I/O

P i n

Ty p e

CML

P o w e r

R a i l

D e s c r i p t i o n

USB_AVDD USB 2.0 Data Differential Pair

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Hardware Specifications

1.2.9 JTAG Interface Pin Assignment

Table 11: JTAG Pin Assignment

P i n N a m e

I / O P i n

Ty p e

CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

JT_CLK

JT_RSTn

JT_TMS_CPU

JT_TMS_CORE

JT_TDO

JT_TDI I

CMOS

VDDO

JTAG Clock

Clock input for the JTAG controller.

NOTE: This pin is internally pulled down to 0.

JTAG Reset

When asserted, resets the JTAG controller.

NOTE: This pin is internally pulled down to 0.

CPU JTAG Mode Select

Controls CPU JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE: This pin is internally pulled up to 1.

Core JTAG Mode Select

Controls the Core JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE: This pin is internally pulled up to 1.

JTAG Data Out

Driven on the falling edge of JT_CLK.

JTAG Data In

JTAG serial data input. Sampled with the JT_CLK rising edge.

NOTE: This pin is internally pulled up to 1.

1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the

JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.

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Pin and Signal Descriptions

Pin Descriptions

1.2.10 Real Time Clock (RTC) Interface Pin Assignments

Table 12: RTC Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

RTC_XIN I Analog

D e s c r i p t i o n

RTC_AVDD RTC Crystal Clock Input

RTC_XOUT O Analog RTC_AVDD RTC Crystal Clock Feedback

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Hardware Specifications

1.2.11 NAND Flash Interface Pin Assignment

Table 13: NAND Flash Interface Pin Assignment

P i n N a m e

NF_IO[7:0]

I / O P i n

Ty p e

I/O CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

NF_CLE

NF_ALE

NF_CEn

NF_REn

NF_WEn

CMOS

VDDO

Data Input/Output

Used to output command, address and data, and to input data during read operations.

NOTE: All of the NF_IO pins are multiplexed on the MPP pins

(see Section 4, Pin Multiplexing, on page 51 )

Command Latch Enable

Controls the activating path for commands sent to the command register.

Address Latch Enable

Controls the activating path for the address to the internal address registers.

Chip Enable

Controls the device selection.

Read Enable

Controls the serial data-in.

Write Enable

Controls writes to the NF_IO[7:0] ports.

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Pin and Signal Descriptions

Pin Descriptions

1.2.12 MPP Interface Pin Assignment

Table 14: MPP Interface Pin Assignment

P i n N a m e

MPP[19:0]

MPP[35:20]

MPP[49:36] t/s

I/O t/s

I/O

I / O P i n

Ty p e t/s

I/O

CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

Multi Purpose Pin

Various functionalities

VDD_GE_B Multi Purpose Pin

Various functionalities

VDDO Multi Purpose Pin

Various functionalities

The various functionalities of the MPP pins are detailed in Section 4, Pin Multiplexing, on page 51 .

Note

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1.2.13

88F6281

Hardware Specifications

Two-Wire Serial Interface (TWSI) Interface

Note

All of the TWSI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).

Table 15: Two-Wire Serial Interface (TWSI) Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

TW_SDA o/d

I/O

CMOS VDDO TWSI Port Serial Data

Address or write data driven by the TWSI master or read response data driven by the TWSI slave.

NOTE: Requires a pull-up resistor to VDDO.

TW_SCK o/d

I/O

CMOS VDDO TWSI Port Serial Clock

Serves as output when acting as an TWSI master.

Serves as input when acting as an TWSI slave.

NOTE: Requires a pull-up resistor to VDDO.

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Pin and Signal Descriptions

Pin Descriptions

1.2.14 UART Interface

Note

All of the UART signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).

Table 16: UART Port 0/1 Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

UA0/1_RXD

UA0/1_TXD

CMOS

VDDO

UART Port 0/1 RX Data

UART Port 0/1 TX Data

UA0/1_CTS

UA0/1_RTS

CMOS

VDDO

Clear to Send

Request to Send

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Hardware Specifications

1.2.15 Audio (S/PDIF / I

2 S) Interface

Note

All of the Audio signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51 ).

If the Audio interface is not used, leave all of the signals unconnected.

The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option.

Table 17: Audio (S/PDIF / I

S) Interface Signal Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

AU_SPDIFI I S/PDIF In

AU_SPDIFO

AU_

SPDFRMCLK

AU_I2SBCLK

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

S/PDIF Out

S/PDIF Recovered Master Clock (256 x F s

)

For the frequency of this clock, see the Audio External

Reference Clock section of Table 45, Reference Clock AC

Timing Specifications, on page 86 .

S Bit Clock (64 x F s

)

AU_I2SDO

AU_I2SLRCLK

AU_I2SMCLK

AU_I2SDI

AU_EXTCLK I

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

CMOS VDDO/

VDD_GE_B

Transmitter Data Out

S Left/Right Clock (1 x F s

)

S Master Clock (256 x F s

)

S Receiver Data In

External Audio Clock

For the frequency of this clock, see the Audio External

Reference Clock section of Table 45, Reference Clock AC

Timing Specifications, on page 86 .

1. F s

is the audio sample rate.

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1.2.16

Pin and Signal Descriptions

Pin Descriptions

Serial Peripheral Interface (SPI) Interface

Note

All of the SPI signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).

Table 18: Serial Peripheral Interface (SPI) Interface Signal Assignment

I/O Description

Pin Name

SPI_MOSI

Pin Type

CMOS

Power Rail

VDDO SPI Data Output

Data is output from the master and input to the slave.

SPI_MISO

I CMOS VDDO SPI Data Input

Data is input to the master and output from the slave.

SPI_SCK O CMOS VDDO SPI Clock

SPI_CSn O CMOS VDDO SPI Chip Select

NOTE: This pin requires an external pull up.

1. MOSI = Master Out Slave In.

2. MISO = Master In Slave Out.

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Hardware Specifications

Secure Digital Input/Output (SDIO) Interface

Note

All of the SDIO signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).

Table 19: Secure Digital Input/Output (SDIO) Interface Signal Assignment

I/O Description

Pin Name

SD_CLK O

Pin Type

CMOS

Power Rail

VDDO SDIO Clock

SD_CMD I/O CMOS VDDO SDIO Command

Used to transfer a command serially from the SDIO host to the

SDIO device. Used to transfer a command response serially from the SDIO device to the SDIO host.

NOTE: This pin requires a pull up on board.

SD_D[3:0] I/O CMOS VDDO SDIO Data Input/Output

Used to transfer data from the SDIO host to the SDIO device or vice versa.

NOTE: These pins require a pull up on board.

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Pin and Signal Descriptions

Pin Descriptions

1.2.18 Time Division Multiplexing (TDM) Interface

Note

All of the TDM signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51 ).

The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option (see Section 4, Pin Multiplexing, on page 51 ).

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment

I/O Description

Pin Name

TDM_CH0_TX_

TDM_CH2_TX_

TDM_CH0_RX_

TDM_CH2_RX_

TDM_CODEC_

INTn

TDM_CODEC_

RSTn

TDM_PCLK

TDM_FS

TDM_DRX

TDM_DTX

I/O

TDM_SPI_CS[1:0] O

Pin Type

CMOS

Power Rail

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

TDM Channel0 Transmit Qualifier

TDM Channel2 Transmit Qualifier

TDM Channel0 Receive Qualifier

TDM Channel2 Receive Qualifier

Interrupt Signal FROM the SLIC/codec

SLIC/codec Reset Signal

PCM Audio Bit Clock

TDM Frame Sync Signal

PCM Audio Input Data (for recording)

PCM Audio Output Data (for playback)

TDM_SPI_SCK O CMOS VDDO/

VDD_GE_B

Active low SPI chip selects driven by the host to the codec for register access. Always asserted for eight SCLK cycles at a time.

Only Byte-by-Byte mode codec register read/write is supported.

Serial SPI clock from the host to the codec for register access.

This is an RTO (return to one) clock. It toggles for eight cycles at a time (for 1 byte transfer) during codec register access, then it returns to high.

The host drives write data on TDM_SPI_MOSI on the negative edge of TDM_SPI_SCK, and captures read data from the codec on the positive edge of TDM_SPI_SCK.

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Hardware Specifications

Table 20: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued)

I/O Description

Pin Name

TDM_SPI_MOSI

TDM_SPI_MISO I

Pin Type

CMOS

Power Rail

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

Serial SPI data from the host to the codec for register access.

When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time.

In a byte, the data can be driven MSB or LSB first.

Serial SPI read data from the CODEC to the host for register access.

When TDM_SPI_CS is asserted low, this data is driven from

CODEC on negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. The CODEC drives data on this line only for a read operation, when it gets command and address in previous bytes from the host on TDM_SPI_MOSI

In a byte, the data can be driven MSB or LSB first.

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Pin and Signal Descriptions

Pin Descriptions

1.2.19 Transport Stream (TS) Interface

Note

All of the TS signals are multiplexed on the MPP pins (see Section 4, Pin

Multiplexing, on page 51 ).

The TS signals are powered on VDDO or on VDD_GE_B based on the pin multiplexing option (see Section 4, Pin Multiplexing ).

Table 21: Transport Stream (TS) Interface Signal Assignment

I/O Description

Pin Name

TSMP[0]

TSMP[1]

TSMP[2]

TSMP[3]

TSMP[4]

TSMP[5]

TSMP[6]

I/O

Pin Type

CMOS

Power Rail

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

EXT_CLK

External clock that can be used to drive the TS0_CLK and

TS1_CLK

TS0_CLK

Port0 TS clock.

• If TS0_VAL is used, the clock may be continuous.

• If TS0_VAL is not used, the clock may toggle only when valid data is available on TS0_DATA.

TS0_SYNC

Port0 Sync/Frame Start Indicator or Packet Clock.

The TS0_SYNC in parallel mode is a pulse that is active during the first (Sync) byte of the TS packet. In serial mode, the

TS0_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low.

TS0_VAL

Port0 Valid Data Indicator

When this signal is used and is valid, it indicates that valid data is present on TS0_DATA. TS0_VAL is active during the TS frame packet data and inactive when there is no TS synchronization.

In output mode, the polarity of TS0_VAL is programmable to be either active high or active low.

TS0_ERR

Port0 Uncorrectable Packet Error

When this signal is used, an error indicates that the packet contains an uncorrectable error, and therefore should not be used.

In output mode, the TS0_ERR is active during the entire TS frame.

TS0_DATA[0]

Port0 TS Data bit 0 in both parallel and serial modes.

In Serial mode TS0_DATA[0] is used as data input or output.

• Parallel Mode:

TS0_DATA[1]: Port0 TS Data bit 1

• Serial Mode:

TS1_CLK: Port1 TS clock.

- If TS1_VAL is used, the clock may be continuous.

- If TS1_VAL is not used, the clock may toggle only when valid data is available on TS1_DATA

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Hardware Specifications

Table 21: Transport Stream (TS) Interface Signal Assignment (Continued)

I/O

Pin Name

TSMP[7]

TSMP[8]

TSMP[9]

TSMP[10]

TSMP[11]

TSMP[12]

I/O

Pin Type

CMOS

Power Rail

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

VDDO/

VDD_GE_B

Description

• Parallel Mode:

TS0_DATA[2]: Port0 TS Data bit 2

• Serial Mode:

TS1_SYNC: Port1 Sync/Frame Start Indicator or Packet

Clock.

The TS1_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low

• Parallel Mode:

TS0_DATA[3]: Port0 TS Data bit 3

• Serial Mode:

TS1_VAL: Port1Valid Data Indicator

When this signal is used and is valid, it indicates that valid data is present on TS1_DATA[0].

TS1_VAL is active during the TS frame packet data and inactive when there is no TS synchronization.

In output mode, the polarity of TS1_VAL is programmable to be either active high or active low.

• Parallel Mode:

TS0_DATA[4]: Port0 TS Data bit 4

• Serial Mode:

TS1_ERR: Port1 Uncorrectable Packet Error

When this signal is used, an error indicates that the packet contains an uncorrectable error, and, therefore, should not be used.

In output mode the TS1_ERR is active during the entire TS frame.

• Parallel Mode:

TS0_DATA[5]: Port0 TS Data bit 5

• Serial Mode:

TS1_DATA[0]: Port1 TS Data bit 0, used as data input or output.

TS0_DATA[6]

Port0 TS Data bit 6

This pin is only valid in Parallel mode.

TS0_DATA[7]

Port0 TS Data bit 7

This pin is only valid in Parallel mode.

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1.2.20 Precise Timing Protocol (PTP) Interface

Pin and Signal Descriptions

Pin Descriptions

Note

All of the PTP signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing, on page 51 ).

Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment

I/O Description

Pin Name

PTP_CLK I

Pin Type

CMOS

Power Rail

VDDO PTP Clock

PTP_EVENT_REQ I CMOS VDDO Trigger generation to the PTP core.

PTP_TRIG_GEN O CMOS VDDO Trigger generated by the PTP core.

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1.3

88F6281

Hardware Specifications

Internal Pull-up and Pull-down Pins

Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins.

The internal pull-up and pull-down resistor value is 50 k

. An external resistor with a lower value can override this internal resistor.

MPP[5]

MPP[7]

MPP[10]

MPP[11]

MPP[12]

MPP[14]

MPP[18]

MPP[19]

MPP[33]

NF_CLE

NF_CEn

NF_WEn

MRn

MPP[1]

MPP[2]

MPP[3]

MPP[4]

P i n N a m e

GE_TXD[0]

GE_TXD[1]

GE_TXD[2]

GE_TXD[3]

GE_TXCTL

GE_MDC

JT_TMS_CORE

JT_RSTn

JT_TDI

JT_TMS_CPU

NF_ALE

NF_REn

Table 23: Internal Pull-up and Pull-down Pins

U12

V13

V10

U10

T10

R06

R07

T07

N03

V08

V07

V09

T09

R11

V11

V12

F04

R14

V15

R10

U11

J04

L03

T14

T15

P i n N u m b e r

H02

H01

H03

H04

Pull down

Pull up

Pull down

Pull up

Pull down

Pull up

Pull down

Pull up

Pull down

P u l l u p / P u l l d o w n

Pull down

Pull up

Pull down

Pull up

Pull down

Pull up

Pull down

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Unused Interface Strapping

Unused Interface Strapping

Table 24 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not connected).

Table 24: Unused Interface Strapping

U n u s e d I n t e r f a c e

Ethernet SMI

MPP

USB

PCI Express

SATA

RTC

SSCG eFuse

St r a p p i n g

Pull up GE_MDIO.

Configure any unused MPP pin to GPIO output.

Leave the power supply connected.

• If the related power supply is VDDO, leave it connected to 3.3V.

• If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V.

Discard the power filter.

Leave USB_AVDD connected to 3.3V.

All other signals can be left unconnected.

Discard the analog power filters.

Leave PEX_AVDD connected to 1.8V.

Pull down the PEX_CLK_N signal through a 50 k

resistor to GND.

Pull up the PEX_CLK_P signal through a 16 k

resistor to 1.8V.

All other signals can be left unconnected.

Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in Table 32,

Reset Configuration, on page 67 .

Discard the analog power filters.

SATA0_AVDD/SATA1_AVDD can be left unconnected.

Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND.

Discard the power filter.

Leave SSCG_AVDD connected to 1.8V.

Connect VHV to VDD

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88F6281

Hardware Specifications

88F6281 Pin Map and Pin List

The 88F6281 pin list is provided as an Excel file attachment.

To open the attached Excel pin list file, double-click the pin icons below:

88F6281 Pin Map and Pin List.xls

Note

File attachments are only supported by Adobe Reader 6.0 and above.

To download the latest version of free Adobe Reader go to http://www.adobe.com

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Pin Multiplexing

Multi-Purpose Pins Functional Summary

Pin Multiplexing

4.1 Multi-Purpose Pins Functional Summary

The 88F6281 device contains 50 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register.

General Purpose pins: MPP[5:0] and MPP[49:7]:

• GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and

MPP[49:34]

• GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], MPP[19:18], and MPP[33]

SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output.

SYSRST_OUTn is the default setting for MPP[6].

PEX_RST_OUTn: Optional PCI Express Endpoint card reset output.

MII/MMII/GMII/RGMII interface signals

SATA0/1_ACTn/SATA0/1_PRESENTn (port 0 and port 1): SATA active and SATA present indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

NF_IO[7:0] (NAND Flash data [7:0])

SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn

UART interface (port 0 and port 1): Transmit and receive functions: UA0_TXD, UA0_RXD,

UA1_TXD, UA1_RXD, and Modem control functions: UA0_RTSn, UA0_CTSn, UA1_RTSn,

UA1_CTSn

SDIO interface: SD_CLK, SD_CMD, SD_D[3:0]

Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK, AU_I2SBCLK,

AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK

TS (Transport Stream) interface signals: TSMP[12:0]

TDM/SPI interface signals: TDM_CH0/2_TX_QL, TDM_CH0/2_RX_QL, TDM_SPI_CS0/1,

TDM_SPI_SCK, TDM_SPI_MOSI, TDM_SPI_MISO, TDM_CODEC_INTn,

TDM_CODEC_RSTn, TDM_PCLK, TDM_FS, TDM_DRX, TDM_DTX

PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK

TWSI signals: TW_SDA, TW_SCK

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Hardware Specifications

MPP pins can be assigned to different functionalities through the MPP Control register, as shown in

Table 25 .

Table 25: MPP Functionality

M P P [ 1 9 : 0 ] :

GPIO

SATA LEDs

NAND flash

TWSI

UART

SPI

PTP

SDIO

M P P [ 3 5 : 2 0 ] :

GPIO

SATA LEDs

GbE

Audio

TDM

PTP

M P P [ 4 9 : 3 6 ] :

GPIO

Audio

TDM

Table 26 lists the functionality of the MPP pins, as determined by the MPP Multiplex register, see the

Pins Multiplexing Interface Registers section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

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Pin Multiplexing

Multi-Purpose Pins Functional Summary

Table 26: MPP Function Summary

Pin name 0x0 0x1 0x2 0x3 0x4 0x5 0xC 0xD

MPP[0]

GPIO[0]

(in/out)

NF_IO[2]

(in/out)

SPI_SCn

(out)

MPP[1]

GPO[1] (out only)

NF_IO[3]

(in/out)

SPI_MOSI

(out)

MPP[2]

GPO[2] (out only)

NF_IO[4]

(in/out)

SPI_SCK

(out)

MPP[3]

GPO[3] (out only)

NF_IO[5]

(in/out)

SPI_MISO

(in)

MPP[4]

GPIO[4]

(in/out)

NF_IO[6]

(in/out)

UA0_RXD

(in)

MPP[5]

GPO[5] (out only)

NF_IO[7]

(in/out)

UA0_TXD

(out)

MPP[6] -

SYSRST_O

UTn (out)

SPI_MOSI

(out)

PTP_TRIG_

GEN (out)

SATA1_AC

Tn (out)

PTP_TRIG_

GEN (out)

SATA0_AC

Tn (out)

MPP[7]

MPP[8]

MPP[9]

MPP[10]

GPO[7] (out only)

PEX_RST_

OUTn (out)

GPIO[8]

(in/out)

GPIO[9]

(in/out)

GPO [10]

(out only)

TW_SDA

(in/out)

TW_SCK

(in/out)

SPI_SCn

(out)

PTP_TRIG_

GEN (out)

SPI_SCK

(out)

UA0_TXD

(out)

UA0_RTS

(out)

UA0_CTS

(in)

UA1_RTS

(out)

MII0_RXER

R (in)

UA1_CTS

(in)

SATA1_PR

ESE NTn

(out)

SATA0_PR

ESE NTn

(out)

PTP_CLK

(in)

PTP_EVEN

T_REQ (in)

MII0_COL

(in)

MII0_CRS

(in)

SATA1_AC

Tn (out)

PTP_TRIG_

GEN (out)

MPP[11]

GPIO[11]

(in/out)

SPI_MISO

(in)

UA0_RXD

(in)

PTP_EVEN

T_REQ (in)

SATA0_AC

Tn (out)

PTP_TRIG_

GEN (out)

PTP_clk

(in)

MPP[12]

GPO[12]

(out only)

SD_CLK

(out)

MPP[13]

MPP[14]

MPP[15]

GPIO[13]

(in/out)

GPIO[14]

(in/out)

GPIO[15]

(in/out)

SD_CMD

(in/out)

SD_D[0]

(in/out)

SD_D[1]

(in/out)

UA1_TXD

(out)

UA1_RXD

(in)

SATA1_PR

ESE NTn

(out)

UA0_RTS

(out)

UA1_TXD

(out)

SATA0_AC

Tn (out)

MPP[16]

MPP[17]

GPIO[16]

(in/out)

SD_D[2]

(in/out)

GPIO[17]

(in/out)

SD_D[3]

(in/out)

UA0_CTS

(in)

UA1_RXD

(in)

SATA1_AC

Tn (out)

SATA0_PR

ESE NTn

(out)

PTP_CLK

(in)

MII0_COL

(in)

MII0_CRS

(in)

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88F6281

Hardware Specifications

Table 26: MPP Function Summary (Continued)

Pin name 0x0 0x1 0x2 0x3 0x4 0x5 0xC

MPP[18]

GPO[18]

(out only)

NF_IO[0]

(in/out)

MPP[19]

GPO[19]

(out only)

NF_IO[1]

(in/out)

MPP[20]

GPIO[20]

(in/out)

TSMP[0]

(in/out)

TDM_CH0_

TX_QL (out)

GE1[0]

AU_SPDIFI

(in)

SATA1_AC

Tn (out)

MPP[21]

MPP[22]

MPP[23]

MPP[24]

GPIO[21]

(in/out)

TSMP[1]

(in/out)

TDM_CH0_

RX_QL (out)

GPIO[22]

(in/out)

GPIO[23]

(in/out)

GPIO[24]

(in/out)

TSMP[2]

(in/out)

TSMP[3]

(in/out)

TSMP[4]

(in/out)

TDM_CH2_

TX_QL (out)

TDM_CH2_

RX_QL (out)

TDM_SPI_

CS0 (out)

GE1[1]

GE1[2]

GE1[3]

GE1[4]

AU_SPDIF

O (out)

SATA0_AC

Tn (out)

AU_SPDIF

RMCLK(out

)

AU_I2SBCL

K (out)

SATA1_PR

ESENTn

(out)

SATA0_PR

ESENTn

(out)

AU_I2SDO

(out)

MPP[25]

GPIO[25]

(in/out)

TSMP[5]

(in/out)

TDM_SPI_

SCK (out)

GE1[5]

AU_I2SLRC

LK (out)

MPP[26]

MPP[27]

MPP[28]

MPP[29]

MPP[30]

GPIO[26]

(in/out)

TSMP[6]

(in/out)

TDM_SPI_

MISO (in)

GE1[6]

AU_I2SMC

LK (out)

GPIO[27]

(in/out)

GPIO[28]

(in/out)

GPIO[29]

(in/out)

TSMP[7]

(in/out)

TSMP[8]

(in/out)

TSMP[9]

(in/out)

TDM_SPI_

MOSI (out)

TDM_COD

EC_INTn

(in)

TDM_COD

EC_RSTn

(out)

GE1[7]

GE1[8]

GE1[9]

GPIO[30]

(in/out)

TSMP[10]

(in/out)

TDM_PCLK

(in/out)

GE1[10]

AU_I2SDI

(in)

AU_EXTCL

K (in)

MPP[31]

GPIO[31]

(in/out)

TSMP[11]

(in/out)

TDM_FS

(in/out)

GE1[11]

MPP[32]

MPP[33]

GPIO[32]

(in/out)

TSMP[12]

(in/out)

TDM_DRX

(in)

GE1[12]

GPO[33]

(out only)

TDM_DTX

(out)

GE1[13]

MPP[34]

MPP[35]

GPIO[34]

(in/out)

GPIO[35]

(in/out)

TDM_SPI_

CS1 (out)

GE1[14]

TDM_CH0_

TX_QL (out)

GE1[15]

SATA1_AC

Tn (out)

SATA0_AC

Tn (out)

MII0_RXER

R (in)

0xD

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Pin Multiplexing

Multi-Purpose Pins Functional Summary

Table 26: MPP Function Summary (Continued)

Pin name

MPP[36]

0x0 0x1 0x2

GPIO[36]

(in/out)

TSMP[0]

(in/out)

TDM_SPI_

CS1 (out)

MPP[37]

GPIO[37]

(in/out)

TSMP[1]

(in/out)

TDM_CH2_

TX_QL (out)

MPP[38]

GPIO[38]

(in/out)

TSMP[2]

(in/out)

TDM_CH2_

RX_QL (out)

MPP[39]

GPIO[39]

(in/out)

TSMP[3]

(in/out)

TDM_SPI_

CS0 (out)

MPP[40]

GPIO[40]

(in/out)

TSMP[4]

(in/out)

TDM_SPI_

SCK (out)

MPP[41]

GPIO[41]

(in/out)

TSMP[5]

(in/out)

TDM_SPI_

MISO (in)

MPP[42]

MPP[43]

MPP[44]

MPP[45]

GPIO[42]

(in/out)

GPIO[43]

(in/out)

GPIO[44]

(in/out)

GPIO[45]

(in/out)

TSMP[6]

(in/out)

TDM_SPI_

MOSI (out)

TSMP[7]

(in/out)

TSMP[8]

(in/out)

TDM_COD

EC_INTn

(in)

TDM_COD

EC_RSTn

(out)

TSMP[9]

(in/out)

TDM_PCLK

(in/out)

MPP[46]

GPIO[46]

(in/out)

TSMP[10]

(in/out)

TDM_FS

(in/out)

MPP[47]

GPIO[47]

(in/out)

TSMP[11]

(in/out)

TDM_DRX

(in)

MPP[48]

GPIO[48]

(in/out)

TSMP[12]

(in/out)

TDM_DTX

(out)

MPP[49]

GPIO[49]

(in/out)

TDM_CH0_

RX_QL (out)

0x3

0x4

AU_SPDIFI

(in)

AU_SPDIF

O (out)

AU_SPDIF

RMCLK

(out)

AU_I2SBCL

K (out)

AU_I2SDO

(out)

AU_I2SLRC

LK (out)

AU_I2SMC

LK (out)

AU_I2SDI

(in)

AU_EXTCL

K (in)

0x5

PTP_CLK

(in)

0xC

0xD

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88F6281

Hardware Specifications

Note

For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset depends on Boot mode (see the Boot Device field in Table 32, Reset

Configuration, on page 67 ):

• When Boot mode is NAND Flash, MPP[5:0] and MPP[19:18] wake up after reset in NAND Flash mode.

• When Boot mode is SPI Flash, either MPP[3:0] or {MPP[3:1] and MPP[7]} wake up after reset in SPI mode, (according to boot mode configured by reset strap pins).

Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn)

Pin MPP[7] wakes up after reset:

• As SPI_CSn, if the boot device—selected according to boot device reset strapping—is 0x2 (boot from SPI flash, SPI_CSn on MPP[7]).

• As PEX_RST_OUTn, if the boot device—selected according to boot device reset strapping—is any option other than 0x2.

When TWSI serial ROM initialization is enabled (see TWSI Serial ROM

Initialization in Table 32, Reset Configuration, on page 67 ), MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively.

All other MPP interface pins wake up after reset in 0x0 mode (GPIO/GPO) and are default set to Data Output disabled (Tri-State). Therefore, those MPPs that are

GPIO are in fact inputs, and those that are GPO are Tri-State.

The SPI interface can be configured using one of the following sets of MPP pins:

• MPP[3:0]

• MPP[11], MPP[10], MPP[7], and MPP[6]

• MPP[3:1] and MPP[7]

Do not configure both MPP[3] and MPP[11] as SPI_MISO.

UART0 and UART1 signals are duplicated on a few MPPs. The UART0 or UART1 signals must not be configured to more than one MPP.

When selecting the MII/MMII interface (MPP[35:20]) and the TDM interface

(MPP[49:35]), the TDM signal TDM_CH0_TX_QL and the MII/MMII signal

MII1_RXERR are both multiplexed on MPP[35]. However, MPP[35] can only be configured to one of these functions at a time.

Some of the MPP pins are sampled during SYSRSTn de-assertion to set the device configuration. These pins must be set to the correct value during reset (see

Section 6.5, Pins Sample Configuration, on page 66 ).

Pins that are left as GPIO and are not connected should be set to output after

SYSRSTn de-assertion.

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Pin Multiplexing

Gigabit Ethernet (GbE) Pins Multiplexing on MPP

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

MPP[8] or

MPP[35]

MPP[8] or

MPP[14]

MPP[9] or

MPP[16]

MPP [23:20] /

GE1[3:0]

MPP_[27:24] /

GE1[7:4]

MPP_28 /

GE1[8]

MPP_29 /

GE1[9]

MPP_30 /

GE1[10]

MPP_31 /

GE1[11]

MPP_32 /

GE1[12]

MPP_33 /

GE1[13]

4.2 Gigabit Ethernet (GbE) Pins Multiplexing on MPP

The 88F6281 has 14 dedicated pins for its GbE port. (12 RGMII pins, an MDC pin, and an MDIO pin).

For the 88F6281, additional GbE interface pins are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch.

Two RGMII ports

One RGMII port and one MMII/MII port

(either port 0 as RGMII and port 1 as MMII/MII or port 0 as MMII/MII and port 1 as RGMII)

One GMII port (port 0)

Table 27 summarizes the GbE port pins multiplexing.

Table 27: Ethernet Ports Pins Multiplexing

P i n N a m e 1 x G M I I

GE_TXCLKOUT GMII0_TXCLKOUT

(out)

GE_TXD[3:0] GMII0_TXD[3:0] (out)

GMII0_TXEN (out)

GMII0_RXD[3:0] (in)

GMII0_RXDV (in)

GMII0_RXCLK (in)

R G M I I 0 + M I I 1 /

M M I I 1

2 x R G M I I

RGMII0_TXCLKOUT

(out)

RGMII0_TXD[3:0]

(out)

RGMII0_TXCLKOUT

(out)

RGMII0_TXD[3:0]

(out)

RGMII0_TXCTL (out) RGMII0_TXCTL (out)

RGMII0_RXD[3:0] (in) RGMII0_RXD[3:0] (in)

RGMII0_RXCTL (in) RGMII0_RXCTL (in)

RGMII0_RXCLK (in)

M I I 0 / M M I I 0 +

R G M I I 1

MII0_TXCLK (in)

MII0_TXD[3:0] (out)

MII0_TXEN (out)

MII0_RXD[3:0] (in)

MII0_RXDV (in)

MII0_RXCLK (in)

MII0_RXERR (in)

GMII0_TXD[7:4] (out)

GMII0_RXD[7:4] (in)

GMII0_COL (in)

GMII0_TXCLK (in)

GMII0_RXERR (in)

GMII0_CRS (in)

GMII0_TXERR (out)

MII1_TXD[3:0] (out)

MII1_RXD[3:0] (in)

MII1_COL (in)

MII1_TXCLK (in)

MII1_RXDV (in)

MII1_RXCLK (in)

MII1_CRS (in)

MII1_TXERR (out)

MII0_COL (in)

MII0_CRS (in)

RGMII1_TXD[3:0]

(out)

RGMII1_TXD[3:0]

(out)

RGMII1_RXD[3:0] (in) RGMII1_RXD[3:0] (in)

RGMII1_RXCTL (in)

RGMII1_RXCLK (in)

RGMII1_TXCLKOUT

(out)

RGMII1_TXCTL (out)

RGMII1_RXCTL (in)

RGMII1_RXCLK (in)

RGMII1_TXCLKOUT

(out)

RGMII1_TXCTL (out)

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88F6281

Hardware Specifications

Table 27: Ethernet Ports Pins Multiplexing (Continued)

P i n N a m e 1 x G M I I

R G M I I 0 + M I I 1 /

M M I I 1

MII1_TXEN (out) MPP_34 /

GE1[14]

MPP_35 /

GE1[15]

NA MII1_RXERR (in)

2 x R G M I I

Note

M I I 0 / M M I I 0 +

R G M I I 1

When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals

(except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) must still be configured accordingly and must have a pull-down resistor.

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4.3

Pin Multiplexing

TSMP (TS Multiplexing Pins) on MPP

P i n

N a m e

TSMP[0]

TSMP[1]

TSMP[2]

TSMP[3]

TSMP[4]

TSMP[5]

TSMP[6]

TSMP[7]

TSMP[8]

TSMP[9]

TSMP[10]

TSMP[11]

TSMP[12]

TSMP (TS Multiplexing Pins) on MPP

The TS interface can be configured to one of five modes:

One or two serial in interfaces

One or two serial out interfaces

Serial in and serial out interface

Parallel in interface

Parallel out interface

In parallel in or serial in mode, all TS signals are inputs.

In parallel out or serial out mode, all TS signals are outputs.

Table 28 summarizes the TS port pins multiplexing.

Table 28: TS Port Pin Multiplexing

F u n c t i o n a l i t y i n T S s e r i a l m o d e s

2 x i n / 2 x o u t / i n + o u t

EXT_CLK (in)

TS0_CLK (in/out))

TS0_SYNC(in/out))

TS0_VAL (in/out))

TS0_ERR (in/out))

TS0_DATA[0] (in/out)

TS1_CLK (in/out))

TS1_SYNC(in/out))

TS1_VAL (in/out))

TS1_ERR (in/out))

TS1_DATA[0] (in/out)

F u n c t i o n a l i t y i n T S pa r a l l e l i n / o u t m o d e

EXT_CLK (in)

TS0_CLK (in/out))

TS0_SYNC(in/out))

TS0_VAL (in/out))

TS0_ERR (in/out))

TS0_DATA[0] (in/out)

TS0_DATA[1] (in/out))

TS0_DATA[2] (in/out))

TS0_DATA[3] (in/out))

TS0_DATA[4] (in/out))

TS0_DATA[5] (in/out))

TS0_DATA[6] (in/out))

TS0_DATA[7] (in/out))

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88F6281

Hardware Specifications

Clocking

Table 29 lists the clocks in the 88F6281.

Table 29: 88F6281Clocks

C l o c k Ty p e

CPU PLL

D e s c r i p t i o n

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clocks:

- CPU clock

- L2 cache clock

- DDR Clock (the Mbus-L uses the DDR clock.)

NOTE: See Table 32, Reset Configuration, on page 67 for CPU, L2 cache and

DDR frequency configuration.

Core PLL

PEX PHY

USB PHY PLL

L2 cache clock frequency must be equal or higher then DDR clock frequency.

If the SSCG enable bit in the Sampled at Reset register is set, then the

SSCG circuit is applied for the CPU PLL reference clock (refer to the

Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and

88F6281 Functional Specifications).

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clocks:

- TCLK (core clock, 200 MHz)

- SDIO Clock (100 MHz)

- Gigabit Ethernet Clock (125 MHz)

- TS unit Clock(100/91/83/77MHz)

- SPI clock (TCLK/30–TCLK/4 MHz)

- SMI clock (TCLK/128 MHz)

- TWSI clock (up to TCLK/1600)

NOTE: See Table 32, Reset Configuration, on page 67 for TCLK frequency configuration.

NOTE: See the TS Interface Configuration register in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications for TS clock frequency configuration.

There are two options for the reference clock configuration, depending on the PCI

Express clock 100 MHz differential clock:

• The device uses an external source for PCI Express clock. The PEX_CLK_P pin is an input.

• The device uses an internal generated clock for PCI Express clock. The

PEX_CLK_P pin is an output, driving out the PCI Express differential clock.

• Reference clock:

REF_CLK_XIN (25 MHz)

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Clocking

Table 29: 88F6281Clocks (Continued)

C l o c k Ty p e

SATA PHY PLL

RTC

PTP

D e s c r i p t i o n

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clock:

SATA Clock (150 MHz)

• Reference clock:

RTC_XIN (32.768 kHz)

Used for real time clock functionality, see the Real Time Clock section in the

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

• Reference clock:

PTP_CLK (125 MHz)

The PTP_CLK can be used for the following functions:

• PTP time stamp clock

Two options for reference clock:

- PTP_CLK

- Gigabit Ethernet Clock (125 MHz)

• TS unit clock

Two options for reference clock:

- PTP_CLK/2

- Core PLL

• Audio unit clock

Two options for reference clock:

- PTP_CLK

- REF_CLK_XIN (25 MHz)

For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and

88F6281 Functional Specifications.

The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see Section 6.5, Pins Sample

Configuration, on page 66 ).

Table 30: Supported Clock Combinations

D D R C l o c k

( M H z )

333

250

200

400

300

267

200

375

C P U t o D D R

C l o c k R a t i o

3:1

4:1

5:1

3:1

4:1

4.5:1

6:1

4:1

C P U C l o c k

( M H z )

1000

1200

1500

C P U t o L 2

C l o c k R a t i o

3:1

L 2 C l o c k

( M H z )

333

400

500

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5.1

88F6281

Hardware Specifications

Spread Spectrum Clock Generator (SSCG)

The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock for the PLL input. See SSCG Disable in Table 32, Reset Configuration, on page 67 , for SSCG enable/bypass configuration settings.

The SSCG block can be configured to perform up spread, down spread and center spread.

The modulation frequency is configurable. Typical frequency is 30 kHz.

The spread percentage can also be configured up to 1%.

For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications

.

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System Power Up/Down and Reset Settings

Power-Up/Down Sequence Requirements

System Power Up/Down and Reset

Settings

This section provides information about the device power-up/down sequence and configuration at reset.

6.1

6.1.1

Power-Up/Down Sequence Requirements

Power-Up Sequence Requirements

These guidelines must be applied to meet the 88F6281 device power-up requirements:

The non-core voltages (I/O and Analog) as listed in Table 31 must reach 70% of their voltage level before the core voltages reach 70% of their voltage level.

The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level

(shown in Figure 2 ).

The order of the power-up sequence between the core voltages (VDD and VDD_CPU) is unimportant.

The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level

(shown in Figure 2 ).

The reference clock(s) inputs must toggle with their respective voltage levels before the core voltages reach 70% of their voltage level (shown in Figure 2 ).

If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

Table 31: I/O and Core Voltages

I / O Vo l ta g e s

VDD_GE_A

VDD_GE_B

VDD_M

VDDO

N o n - C o r e Vo l ta g e s

A n a l o g P o w e r S u p p l i e s

CPU_PLL_AVDD

CORE_PLL_AVDD

PEX_AVDD

RTC_AVDD

SATA0_AVDD

SATA1_AVDD

SSCG_AVDD

XTAL_AVDD

USB_AVDD

C o r e Vo l ta g e s

VDD

VDD_CPU

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88F6281

Hardware Specifications

Figure 2: Power-Up Sequence Example

Voltage

Non-Core Voltage

Core Voltage

70% of

Non-Core

Voltage

70% of Core

Voltage

6.1.2

6.2

Reset(s)

Clock(s)

Note

It is the designer's responsibility to verify that the power sequencing requirements of other components are also met.

Although the non-core voltages can be powered up any time before the core voltages, allow a reasonable time limitation (for example, 100 ms) between the

first non-core voltage power-up and the last core voltage power-up.

Power-Down Sequence Requirements

There are no special requirements for the core supply to go down before non-core power, or for reset assertion when powering down (except for VHV, as described below). However, allow a reasonable time limitation (no more than 100 ms) between the first and last voltage power-down.

When using the eFuse in Burning mode, VHV must be powered down before VDD.

Hardware Reset

The device has one reset input pin—SYSRSTn. When asserted, the entire chip is placed in its initial state. Most outputs are placed in high-z, except for the following output pins, that are still active during SYSRSTn assertion:

M_CLKOUT, M_CLKOUTn

M_CKE

M_ODT[1:0]

M_STARTBURST

SYSRST_OUTn

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6.2.1

6.2.2

6.2.3

System Power Up/Down and Reset Settings

Hardware Reset

Note

Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward.

Reset Out Signal

The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic. SYSRST_OUTn is the default option for that MPP pin.

This signal is asserted low for 20 ms, when one of the following maskable events occurs:

Received hot reset indication from the PCI Express link (only relevant when used as a PCI

Express endpoint), and bit <PexRstOutEn> is set to 1 in the RSTOUTn Mask Register (see the

Reset register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications).

PCI Express link failure (only relevant when used as a PCI Express endpoint), and bit

<PexRstOutEn> is set to 1 in the RSTOUTn Mask Register.

Watchdog timer expiration and bit <WDRstOutEn> is set to 1 in the RSTOUTn Mask Register.

Bit <SystemSoftRst> is set to 1 in System Soft Reset Register and bit <SoftRstOutEn> is set to 1 in RSTOUTn Mask Register.

This signal is asserted low for 20 ms, when one of the following non-maskable events occurs:

Power on reset (The device includes a power-on-reset (POR) circuit for VDD power.)

SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low and for an additional 20 ms after MRn de-assertion. (This is useful for implementations that include a manual reset button.)

Power On Reset (POR)

The SYSRST_OUTn output signal is asserted low for 20 ms, when the power-on-reset (POR) circuit is triggered.

POR is triggered when VDD power up (digital core voltage) reaches a VDD threshold (threshold maximum value 0.8V).

Hysteresis: Another trigger will only occur after the power first drops to 50 mV, and then a power up occurs.

SYSRSTn Duration Counter

When SYSRSTn is asserted low, a SYSRSTn duration counter is running.

The counter clock is the 25 MHz reference clock.

It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds).

The host software can read the counter value and reset the counter.

When the counter reach its maximum value, it remains at this value until counter reset is triggered by software.

Note

The SYSRSTn duration counter is useful for implementing manufacturer/factory reset.

Upon a long reset assertion, greater than a pre-configured threshold, the host software may reset all settings to the factory default values.

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6.3

6.3.1

6.3.2

6.4

6.5

88F6281

Hardware Specifications

PCI Express Reset

PCI Express Root Complex Reset

As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a

Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180,

88F6190, 88F6192, and 88F6281 Functional Specifications.

PCI Express Endpoint Reset

When a Hot Reset packet is received:

A maskable interrupt is asserted.

If the <conf_dis_hot_rst_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

The device triggers an internal reset, if not masked by the <conf_msk_hot_reset> field in the

PCI Express Debug Control register.

Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected:

A maskable interrupt is asserted.

If the <conf_dis_link_fail_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

The device triggers an internal reset, if the <conf_msk_link_fail> field is not masked by PCI

Express Debug Control register.

Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express interface). All the chip logic is reset to the default values, except for sticky registers and the sample on reset logic. In addition, these events can trigger reset to the board, using one of the following:

PEX_RST_OUTn signal (multiplexed on MPP).

SYSRST_OUTn output (multiplexed on MPP)—if not masked by the <PexRstOutEn> bit.

The external reset logic (on the board) may assert the SYSRSTn input pin and reset the entire chip.

Sheeva

™

CPU TAP Controller Reset

The Sheeva

™

CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and

JT_TMS_CPU is active.

Pins Sample Configuration

The following pins are sampled during SYSRSTn de-assertion:

Internal pull up/down resistors set the default mode (see Section 1.3, Internal Pull-up and

Pull-down Pins, on page 48 ).

Higher value, external pull up/down resistors are required to change the default mode of operation.

These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion).

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System Power Up/Down and Reset Settings

Pins Sample Configuration

Note

If external logic is used instead of pull-up and pull-down resistors, the logic must drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion.

All reset sampled values are registered in the Sample at Reset register (see the

MPP Registers in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications). This is useful for board debug purposes and identification of board and system settings for the host software.

If a signal is pulled up on the board, it must be pulled to the proper voltage level.

Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B.

Those pins have multiple voltage options (see Table 36, Recommended Operating

Conditions, on page 77 ).

In each row of Table 32 , the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK

Frequency Select, MPP[2] is the MSB and MPP[10] is the LSB).

Table 32: Reset Configuration

P i n

MPP[1]

C o n f i g u r a t i o n F u n c t i o n

TWSI Serial ROM Initialization

0 = Disabled

1 = Enabled

NOTE: Internally pulled down to 0x0.

When this pin is set to 0x1, MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively (see Section 4.1, Multi-Purpose Pins Functional Summary, on page 51 ).

CPU_CLK Frequency Select MPP[2],MPP[5],

MPP[19],

MPP[10]

0x0–0x6 = Reserved

0x7 = 1000 MHz

0x8 = Reserved

0x9 = 1200 MHz

0xA–0xB = Reserved

0xC = 1500 MHz

0xD–0xF = Reserved

NOTE: Internally pulled to 0x6.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61 .

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88F6281

Hardware Specifications

Table 32: Reset Configuration (Continued)

P i n

MPP[33],

NF_ALE,

NF_REn,

NF_CLE

C o n f i g u r a t i o n F u n c t i o n

CPU_CLK to DDR CLK Ratio

0x0–0x3 = Reserved

0x4 = 3:1

0x5 = Reserved

0x6 = 4:1

0x7 = 4.5:1

0x8 = 5:1

0x9 = 6:1

0xA–0xF = Reserved

MPP[3], MPP[12],

NF_WEn

NOTE: Internally pulled to 0x4.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61 .

CPU_CLK to CPU L2 Clock Ratio

0x0 = Reserved

0x1 = 2:1

0x2 = Reserved

0x3 = 3:1

0x4–0x7 = Reserved

NOTE: Internally pulled to 0x1.

The supported combination for CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and CPU_CLK to CPU L2 clock ratio are listed in Table 30, Supported Clock Combinations, on page 61 .

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System Power Up/Down and Reset Settings

Pins Sample Configuration

Table 32: Reset Configuration (Continued)

P i n

GE_TXD[2:0]

C o n f i g u r a t i o n F u n c t i o n

Boot Device

0x0 = Reserved

0x1 = Reserved

0x2 = Boot from SPI flash (SPI_CSn on MPP[7])

0x3 = Reserved

0x4 = Boot from SPI flash (SPI_CSn on MPP[0])

0x5 = Boot from NAND flash

0x6 = Boot from SATA

0x7 = Boot from the PCI Express port

GE_TXD[3]

GE_MDC

GE_TXCTL

MPP[7]

NOTE:

• Internally pulled to 0x4.

• Only SPI signals configured on pins MPP[3:0] or on pins MPP[7] and MPP[3:1] can be used for booting from SPI.

SPI signals that are multiplexed on other MPPs can only be used after booting (see Section 4.1,

Multi-Purpose Pins Functional Summary, on page 51 ).

• When GE_TXD[2:0] is set to 0x4, MPP[3:0] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x2, MPP[7] and MPP[3:1] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x5, MPP[5:0] and MPP[19:18] wake up as NAND Flash signals.

• For a more detailed description of the bootROM, see the BootROM section in the 88F6180,

88F6190, 88F6192, and 88F6281 Functional Specifications.

• For a more detailed description of the boot from SPI flash or NAND flash, see the SPI Interface and NAND Flash Interface sections in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications.

• There is an option to boot from UART when GE_TXD[2:0] = 0x2–0x7. For a more detailed description of the boot from UART, see the BootROM section in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications.

SSCG Disable

0 = Enable

1 = Disable

NOTE: Internally pulled to 0x1.

PCI Express Clock (100 MHz Differential Clock) Configuration

0x0 = The device use external source for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N are inputs.

0x1 = The device uses internal generated clock for PCI Express clock. Pins

PEX_CLK_P/PEX_CLK_N pins are outputs, driving out the PCI Express differential clock.

NOTE: Internally pulled to 0x1.

Used for internal testing

Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to

0x0 during reset.

Reserved

Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

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88F6281

Hardware Specifications

Table 32: Reset Configuration (Continued)

P i n

MPP[18]

C o n f i g u r a t i o n F u n c t i o n

Reserved

NOTE: MUST be externally pulled down to 0x0 during reset.

6.6

6.6.1

Serial ROM Initialization

The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface. If serial ROM initialization is enabled, the device TWSI master starts reading initialization data from serial ROM and writes it to the appropriate registers, upon de-assertion of

SYSRSTn.

When using Serial ROM Initialization, the MPP[9:8] pins must be configured to as TW_SCK

(MPP[9]) and TW_SDA (MPP[8]).

Serial ROM Data Structure

Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown in Figure 3 .

Figure 3: Serial ROM Data Structure

Start

MSB LSB address0[31:24] address0[23:16] address0[15:8] address0[7:0] data0[31:24] data0[23:16] data0[15:8] data0[7:0] address1[31:24] address1[23:16] address1[15:8] address1[7:0] data1[31:24] data1[23:16] data1[15:8] data1[7:0]

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System Power Up/Down and Reset Settings

Boot Sequence

6.6.2

The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the

32-bit address being read, and based on address decoding result, writes the next four bytes to the required target.

The Serial Initialization Last Data Register contains the expected value of last serial data item

(default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence.

Serial ROM Initialization Operation

On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in Figure 4 .

Figure 4: Serial ROM Read Example

6.7

s r t t a w t e i r s 1 0 1 0 0 0 0 0

ROM

Address a c k

Upper Byte Offset

0 0 0 0 0 0 0 0 a c k

Lower Byte Offset

0 0 0 0 0 0 0 0 a c k a r s t t r e a d s 1 0 1 0 0 0 0 1 a c k

ROM

Address

Data from

ROM

A A A A A A A A a c k

A A A A

Last Data from ROM

1 1 1 1 1 1 1 1 a c k

1 1 1 1 1 1 1 1 a c k x x x x x x x x c k n a s t o p p

For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

Initialization data must be programmed in the serial ROM starting at offset 0x0.

The device assumes 7-bit serial ROM address of ‘b1010000.

After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an additional byte of dummy data. It responds with no-ack and then asserts the stop bit.

The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte

ROM.).

Boot Sequence

The device requires that SYSRSTn stay asserted for at least 300

μ s after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion:

While SYSRSTn is asserted, the CPU PLL and the core PLL are locked.

Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles.

If Serial ROM initialization is enabled, an initialization sequence is started.

If configured to boot from NAND flash (and BootROM is disabled), the device also performs a

NAND Flash boot sequence to prepare page 0 in the NAND flash device for read.

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88F6281

Hardware Specifications

Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see Table 32, Reset Configuration, on page 67 .

For bootROM details, see the BootROM section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

As part of the CPU boot code, the CPU typically performs the following:

Configures the PCI Express address map.

Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization

(sets <InitEn> bit [0] to 1 in the SDRAM Initialization Control register).

Sets the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.

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JTAG Interface

TAP Controller

JTAG Interface

To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface.

The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions.

7.1

7.2 TAP Controller

The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine

(FSM), as defined by IEEE JTAG standard 1149.1.

To place the device in a functional mode, reset the JTAG state machine to disable the JTAG interface.

According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the 88F6281

SYSRSTn is asserted. The JTAG state machine can only be reset by one of the following methods:

Asserting JT_RSTn.

Setting JT_TMS_CORE for at least five JT_CLK cycles.

To place the device in one of the boundary scan test mode, the JTAG state machine must be moved to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift instructions into the Instruction register while in SHIFT-IR state and shift data into and from the various data registers when in SHIFT-DR state.

Instruction Register

The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel.

Table 33 lists the instructions supported by the device.

Table 33: Supported JTAG Instructions

I n s t r u c t i o n

HIGHZ

IDCODE

EXTEST

SAMPLE/PRE

LOAD

BYPASS

C o d e

0011

0010

0000

0001

1111

D e s c r i p t i o n

Select the single bit Bypass register between TDI and TDO.

Sets the device output pins to high-impedance state.

Selects the Identification register between TDI and TDO. This 32-bit register is used to identify the device.

Selects the Boundary Scan register between TDI and TDO. Outputs the boundary scan register cells to drive the output pins of the device. Inputs the boundary scan register cell to sample the input pin of the device.

Selects the Boundary Scan register between TDI and TDO. Samples input pins of the device to input boundary scan register cells.

Preloads the output boundary scan register cells with the Boundary Scan register value.

Selects the single bit Bypass register between TDI and TDO. This allows for rapid data movement through an untested device.

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7.3

7.4

7.5

88F6281

Hardware Specifications

Bypass Register

The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0 when the TAP FSM is in the Capture-DR state.

JTAG Scan Chain

The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to sequentially access all of the data pins both for driving and strobing data. For further details, refer to the BSDL Description file for the device.

ID Register

The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID register is shown in Table 34 , which describes the various ID Code fields.

Table 34: IDCODE Register Map

B i ts Va l u e

31:28 0x0

27:12 0x6281

D e s c r i p t i o n

Version (4'b0010 for version A0, 4'b0011 for A1, etc.)

11:1 0x1AB

0 1 Mandatory

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Electrical Specifications (Preliminary)

Absolute Maximum Ratings

Electrical Specifications (Preliminary)

The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE.

Note

8.1 Absolute Maximum Ratings

Table 35: Absolute Maximum Ratings

P a r a m e t e r

VDD

VDD_CPU

CPU_PLL_AVDD

CORE_PLL_AVDD

SSCG_AVDD

M i n

-0.5

M a x

1.2

1.32

2.2

U n i ts

C o m m e n ts

Core voltage

CPU interface

Analog supply for the internal PLL

VDD_GE_A

VDD_GE_B

VDD_M

VDDO

VHV

PEX_AVDD

USB_AVDD

SATA0_AVDD

SATA1_AVDD

XTAL_AVDD

-0.5

4.0

2.2

4.0

3.0

2.2

4.0

2.2

Analog supply for:

Internal Spread Spectrum Clock Generator

I/O voltage for:

RGMII/GMII/MII/MMII/SMI interface

I/O voltage for:

SDRAM interface

I/O voltage for:

MPP, TWSI, JTAG, SDIO, I

S, SPI, TS, and

TDM interfaces

I/O voltage for eFuse burning

Analog supply for:

PCI Express interface

Analog supply for:

USB interface

Analog supply for:

SATA interface

Analog supply for internal clock inverter for crystal support and current source for SATA and

USB PHYs

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88F6281

Hardware Specifications

Table 35: Absolute Maximum Ratings (Continued)

P a r a m e t e r

RTC_AVDD

M i n

-0.5

M a x

2.2

U n i ts

STG

-40

125

° C

C o m m e n ts

Analog supply for:

RTC interface

Case temperature

Storage temperature

Caution

Exposure to conditions at or beyond the maximum rating may damage the device.

Operation beyond the recommended operating conditions ( Table 36 ) is neither recommended nor guaranteed.

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Electrical Specifications (Preliminary)

Recommended Operating Conditions

8.2 Recommended Operating Conditions

Table 36: Recommended Operating Conditions

P a r a m e t e r

VDD

VDD_CPU

CPU_PLL_AVDD

CORE_PLL_AVDD

SSCG_AVDD

M i n

0.95

1.05

1.7

Ty p

1.0

1.1

1.8

M a x

1.05

1.15

1.9

Units C o m m e n ts

Core voltage

CPU interface

Analog supply for the internal PLL

VDD_GE_A

VDD_GE_B

VDD_M

VDDO

3.15

1.7

3.15

3.3

1.8

3.3

3.45

1.9

3.45

Analog supply for:

Internal Spread Spectrum Clock

Generator

I/O voltage for:

RGMII(10/100 RGMII only)/

GMII/MII/MMII/SMI interfaces

I/O voltage for:

RGMII/SMI interfaces

I/O voltage for:

SDRAM interface

I/O voltage for:

MPP, TWSI, JTAG, SDIO, I

S, SPI,

TS, and TDM interfaces

VHV (during eFuse

Burning mode)

VHV (during eFuse

Reading mode)

PEX_AVDD

USB_AVDD

SATA0_AVDD

SATA1_AVDD

2.375

0.95

1.7

3.15

2.5

1.0

1.8

3.3

2.625

1.05

1.9

3.45

I/O voltage for eFuse burning

NOTE: If the VHV voltage is higher than VDD voltage (burning mode), VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

I/O voltage for eFuse reading

NOTE: It is recommended that if only a read operation is required, VHV would be connected to the device

VDD power.

Analog supply for:

PCI Express interface

Analog supply for:

USB interface

Analog supply for:

SATA interface

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88F6281

Hardware Specifications

Table 36: Recommended Operating Conditions (Continued)

P a r a m e t e r

XTAL_AVDD

RTC_AVDD

M i n

1.7

1.3

Ty p

1.8

1.5

M a x

1.9

1.7

105

Units C o m m e n ts

° C

Analog supply for:

Internal clock inverter for crystal support and current source for

SATA and USB PHYs

Analog supply for RTC in Regular mode

Analog supply for RTC in Battery

Back-up mode

Junction Temperature

Caution

Operation beyond the recommended operating conditions is neither recommended nor guaranteed.

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Electrical Specifications (Preliminary)

Thermal Power Dissipation

8.3 Thermal Power Dissipation

Note

Before designing a system, Marvell recommends reading application note AN-63:

Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.

The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.

Table 37: Thermal Power Dissipation

I n t e r f a c e

Core (VDD 1.0V)

Embedded CPU (VDD_CPU 1.1V)

S y m b o l

VDD

VDD_CPU

Te s t C o n d i t i o n s

TCLK @ 200 MHz

CPU @ 1000 MHz,

L2 @ 333 MHz

CPU @ 1200 MHz,

L2 @ 400 MHz

CPU @ 1500 MHz,

L2 @ 500 MHz

Ty p

280

790

870

1050

U n i ts mW mW mW mW

RGMII 1.8V interface P

RGMII

RGMII (10/100 RGMII only) 3.3V interface P

RGMII

GMII 3.3V interface P

GMII

MII/MMII 3.3V interface P

MII

Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio,

SDIO, TDM, TS, and SPI)

MISC

DDR2

DDR2 SDRAM interface (On-board,

16-bit, 400 MHz) eFuse during Burning mode

NOTE: Since the eFuse burn is performed only once, there is no thermal effect after the burn has finished.

FUSE

Four on board devices, 75 ohm

ODT termination

250

50 mW mW mW mW mW mW mW eFuse during Reading mode

PCI Express interface

USB interface

FUSE

PEX

USB

100

120 mW mW mW

SATA interface P

SATA

Both SATA ports 410 mW

Notes:

The values are for nominal voltage.

Power in mW is calculated using the typical recommended VDDIO specification for each power rail.

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Hardware Specifications

8.4 Current Consumption

The purpose of the Current Consumption table is to support board power design and power module selection.

Table 38: Current Consumption

I n t e r f a c e

Core (VDD 1.0V)

Embedded CPU (VDD_CPU 1.1V)

S y m b o l

VDD

VDD_CPU

Te s t C o n d i t i o n s

TCLK @ 200 MHz

CPU @ 1000 MHz,

L2 @ 333 MHz

CPU @ 1200 MHz,

L2 @ 400 MHz

CPU @ 1500 MHz,

L2 @ 500 MHz

M a x

600

1920

2010

2100

U n i ts mA mA mA mA

RGMII 1.8V or 3.3V interface

GMII 3.3V interface

MII/MMII 3.3V interface

RGMII

GMII

MII_MMII

MISC

Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio,

SDIO, TDM, TS, and SPI)

DDR2 SDRAM interface (16-bit 400 MHz) I

DDR2

Four on board devices, 75 ohm

ODT termination

550 mA mA mA mA mA eFuse during Burning mode eFuse during Reading mode

PCI Express interface

USB interface

SATA interface

FUSE

PEX

USB

SATA

Both SATA ports

130 mA mA mA mA mA

Notes:

Current in mA is calculated using maximum recommended VDDIO specification for each power rail.

All output clocks toggling at their specified rate.

Maximum drawn current from the power supply.

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DC Electrical Specifications

8.5 DC Electrical Specifications

Note

See Section 1.3, Internal Pull-up and Pull-down Pins, on page 48 for internal pullup/pulldown information.

8.5.1 General 3.3V (CMOS) DC Electrical Specifications

The DC electrical specifications in Table 39 are applicable for the following interfaces and signals:

JTAG

RGMII (10/100 Mbps)/GMII/MII/MMII

Secure Digital Input/Output (SDIO)

S/PDIF / I

S (Audio)

Transport Stream (TS)

NAND flash

UART

MPP

PTP

SYSRSTn

In the following table, for the JTAG, SDIO, S/PDIF / I

S, TS, NAND flash, UART, PTP, and MPP interfaces, VDDIO means the VDDO power rail. For the RGMII/GMII/MII/MMII interface, VDDIO means the VDD_GE_A and VDD_GE_B power rails.

Table 39: General 3.3V Interface (CMOS) DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL IOL = 2 mA

VOH IOH = -2 mA

IIL 0 < VIN < VDDIO

Cpin

Min

-0.3

2.0

2.4

-10

Typ

Max

0.8

VDDIO+0.3

0.4

Units Notes

V -

V uA pF

1, 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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8.5.2 RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical

Specifications

In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail.

In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail.

Table 40: RGMII 1.8V Interface (CMOS) DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

VOH

IIL

Cpin

IOL = 2 mA

IOH = -2 mA

0 < VIN < VDDIO

Min

-0.3

0.65*VDDIO

VDDIO-0.45

-10

Typ

Max

0.35*VDDIO

VDDIO+0.3

0.45

Units Notes

V -

V uA pF

1, 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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DC Electrical Specifications

8.5.3 SDRAM DDR2 Interface DC Electrical Specifications

In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail.

Table 41: SDRAM DDR2 Interface DC Electrical Specifications

Input low level

Parameter

Input high level

Output low level

Output high level

Rtt effective impedance value

Symbol Test Condition

VIL -

VIH -

VOL IOL = 13.4 mA

VOH IOH = -13.4 mA

RTT See note 2

Deviation of VM w ith respect to VDDQ/2 dVm See note 3

Input leakage current

Pin capacitance

IIL

Cpin -

0 < VIN < VDDIO

Min

-0.3

VREF + 0.125

Typ Max Units Notes

VREF - 0.125

V -

1.42

120

-6

-10

150

VDDIO + 0.3

0.28

180

10 ohm 1 , 2

% uA pF

4, 5

V ohm 1 , 2 ohm 1 , 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. See SDRAM functional description section for ODT configuration.

2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,

then measure current I (VREF + 0.25) and I (VREF - 0.25) respectively.

RTT

=

( VREF

0 .

25 )

0 .

−

( VREF

−

0 .

25 )

3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.

dVM

=

×

Vm

VDDIO

−

×

100 %

4. While I/O is in High-Z.

5. This current does not include the current flow ing through the pullup/pulldow n resistor.

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Hardware Specifications

8.5.4 Two-Wire Serial Interface (TWSI) 3.3V DC Electrical

Specifications

In the following table, VDDIO means the VDDO power rail.

Table 42: TWSI Interface 3.3V DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

IIL

Cpin

IOL = 3 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

-10

Typ

Max

0.3*VDDIO

VDDIO+0.5

0.4

Units Notes

V -

V uA pF

1, 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

8.5.5 Serial Peripheral Interface (SPI) 3.3V DC Electrical

Specifications

In the following table VDDIO means the VDDO power rail.

Table 43: SPI Interface 3.3V DC Electrical Specifications

Typ Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

VOH

IIL

Cpin

IOL = 4 mA

IOH = -4 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

VDDIO-0.6

-10

Max

0.3*VDDIO

VDDIO+0.5

0.4

Units Notes

V -

V uA pF

1, 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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DC Electrical Specifications

8.5.6 Time Division Multiplexing (TDM) 3.3V DC Electrical

Specifications

In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface.

Table 44: TDM Interface 3.3V DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

VOH

IIL

Cpin

IOL = 4 mA

IOH = -4 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

VDDIO-0.6

-10

Typ

Max

0.3*VDDIO

VDDIO+0.5

0.4

Units Notes

V -

V uA pF

1, 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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Hardware Specifications

8.6 AC Electrical Specifications

See Section 8.7, Differential Interface Electrical Characteristics, on page 118 for differential interface specifications.

8.6.1 Reference Clock AC Timing Specifications

Table 45: Reference Clock AC Timing Specifications

D e s c r i p t i o n

C P U a n d C o r e R e f e r e n c e C l o c k

S y m b o l

Frequency F

REF_CLK_XIN

M i n M a x

50 ppm

0.7

50 ppm

60 Clock duty cycle

Slew rate

Pk-Pk jitter

E t h e r n e t R e f e r e n c e C l o c k

Frequency in MII/MMII-MAC mode

REF_CLK_XIN

MII/MMII-MAC mode clock duty cycle

Slew rate

GE_TXCLK_OUT

GE_RXCLK

GE_TXCLK_OUT

GE_RXCLK

GE_TXCLK_OUT

GE_RXCLK

A u d i o E x t e r n a l R e f e r e n c e C l o c k

Audio external reference clock

S / P D I F R e c o v e r e d M a s t e r C l o c k

S/PDIF recovered master clock

S R e f e r e n c e C l o c k

S clock

S P I O u t p u t C l o c k

AU_EXTCLK

AU_SPDFRMCLK

I2S_BCLK

SPI output clock

R T C R e f e r e n c e C l o c k

SPI_SCK

RTC_XIN crystal frequency F

RTC_XIN

Tr a n s p o r t St r e a m ( T S ) O u t pu t M o d e R e f e r e n c e C l o c k

TS output clock in parallel mode F

TS0_CLK,

TS1_CLK

TS output clock in serial mode F

TS0_CLK,

TS1_CLK

Tr a n s p o r t St r e a m I n p u t M o d e R e f e r e n c e C l o c k

TS input clock in parallel mode F

TS0_CLK,

TS1_CLK

TS input clock in serial mode F

TS0_CLK,

TS1_CLK

Tr a n s p o r t St r e a m E x t e r n a l R e f e r e n c e C l o c k

TS external clock in parallel mode

TS external clock in serial mode

EXT_CLK

2.5 -

100 ppm

50 +

100 ppm

MHz

0.7

200

256 X F s

64 X F s

Units N o t e s

MHz

V/ns ps

V/ns

1, 7 kHz 3 kHz 3 kHz 3

TCLK/30 TCLK/4 MHz

9.61

12.5

13.5

12.5

MHz

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AC Electrical Specifications

Table 45: Reference Clock AC Timing Specifications (Continued)

D e s c r i p t i o n

T D M _ S P I O u t p u t C l o c k

TDM_SPI output clock

S M I M a s t e r M o d e R e f e r e n c e C l o c k

SMI output MDC clock

T W S I M a s t e r M o d e R e f e r e n c e C l o c k

SCK output clock

S y m b o l

TDM_SPI_SCK

8.192

GE_MDC

M i n M a x

TCLK/128

Units N o t e s

MHz

TW_SCK

TCLK/

1600 kHz 6

P T P R e f e r e n c e C l o c k

Frequency

Clock duty cycle

Slew rate

Pk-Pk jitter

PTP_CLK

125 -

100 ppm

0.7

125 +

100 ppm

MHz

100

V/ns ps

Notes:

Slew rate is defined from 20% to 80% of the reference clock signal.

For additional information regarding configuring this clock, see the Serial Memory Interface

Control Register in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

F s

is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the

Audio (I

S / S/PDIF) Interface section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications).

The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components are provided internally. Connect the crystal and the passive network as recommended by the crystal manufacturer.

The frequency can be set using the TS Interface Configuration register (see the 88F6180,

88F6190, 88F6192, and 88F6281 Functional Specifications).

For the minimum value refer to the Baud Rate Register section of the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications.

The Ethernet Reference Clock parameters refer both to the reference clock for an Ethernet port configured using the dedicated port pins and for an Ethernet port configured using the multiplexed port pins.

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8.6.2 SDRAM DDR2 Interface AC Timing

8.6.2.1 SDRAM DDR2 Interface AC Timing Table

Table 46: SDRAM DDR2 Interface AC Timing Table

Description

Clock frequency

DQ and DM valid output time before DQS transition

DQ and DM valid output time after DQS transition

DQ and DM output pulse w idth

DQS output high pulse w idth

DQS output low pulse w idth

DQS falling edge to CLK-CLKn rising edge

DQS falling edge from CLK-CLKn rising edge

DQS latching rising transitions to associated clock edges

DQS w rite preamble

DQS w rite postamble

Average CLK-CLKn high-level w idth

Average CLK-CLKn low -level w idth

DQ input setup time relative to DQS in transition

DQ input hold time relative to DQS in transition

Address and control output pulse w idth

Sym bol fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH(avg) tCL(avg) tDSI tDHI tIPW

400 MHz @ 1.8V

Min

0.40

0.35

0.34

-0.11

0.35

400.0

Max Units

MHz ns

ns tCK(avg) tCK(avg) tCK(avg) tCK(avg) tCK(avg)

0.11

tCK(avg)

Notes

0.40

0.48

-0.42

0.70

0.60

0.52

tCK(avg) tCK(avg) tCK(avg) ns ns tCK(avg)

1, 2, 3

1, 2, 4

Notes:

General comment: All timing values are defined from Vref to Vref, unless otherw ise specified.

General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate defined from Vref +/-125 mV).

General comment: tCK(avg) is calculated as the average clock period across any consecutive 200 cycle w indow .

General comment: All timing parameters w ith DQS signal are defined on DQS-DQSn crossing point.

General comment: For Address and Control output timing parameters, refer to the Address Timing table.

General comment: For all signals, the load is CL = 14 pF.

1. This timing value is defined on CLK / CLKn crossing point.

2. Refer to SDRAM DDR2 clock specifications table for more information.

3. tCH(avg) is defined as the average HIGH pulse w idth, as calculated across any consecutive 200 HIGH pulses.

4. tCL(avg) is defined as the average LOW pulse w idth, as calculated across any consecutive 200 LOW pulses.

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Table 47: SDRAM DDR2 Interface Address Timing Table

Description

Address and Control valid output time before CLK-CLkn rising edge

Address and Control valid output time after CLK-CLKn rising edge

Address and Control valid output time before CLK-CLkn rising edge

Address and Control valid output time after CLK-CLKn rising edge

Sym bol tAOVB tAOVA tAOVB tAOVA

400 MHz @ 1.8V

Min

0.65

Max

0.65

2.95

0.65

Units ns ns ns ns

Notes

1, 2

1, 3

Notes:

General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.

General comment: For all signals, the load is CL = 14 pF.

1. This timing value is defined on CLK / CLKn crossing point.

2. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge.

For more information, see register settings.

3. This timing value is defined w hen Address and Control signals are output on CLK-CLKn falling edge.

and 2T mode is enabled. For more information, see register settings.

Except for ODT, CKE and CS signals.

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8.6.2.2 SDRAM DDR2 Clock Specifications

Table 48: SDRAM DDR2 Clock Specifications

Description

Clock period jitter

Clock perior jitter during DLL locking period

Cycle to cycle clock period jitter

Cycle to cycle clock period jitter during DLL locking period

Cumulative error across 2 cycles

Cumulative error across 3 cycles

Cumulative error across 4 cycles

Cumulative error across 5 cycles

Cumulative error across n cycles, n=6...10, inclusive

Cumulative error across n cycles, n=11…50, inclusive

Duty cycle jitter

Absolute clock period

Absolute clock high pulse w idth

Absolute clock low pulse w idth

Sym bol tJIT(per) tJIT(per,lck) tJIT(cc) tJIT(cc,lck) tERR(2per) tERR(3per) tERR(4per) tERR(5per) tERR(6-10per) tERR(11-50per) tJIT(duty) tCK(abs) tCH(abs) tCL(abs)

Min

-100

-80

-200

-160

-150

-175

-200

-300

-450

-100

See note 7

See note 8

See note 9

200

300

450

100

Max

100

200

160

150

175 ps ps ps ps ps ps ps ps

Units Notes ps 1 ps 2 ps ps ps ps

Notes:

General comment: All timing values are defined on CLK / CLKn crossing point, unless otherw ise specified.

1. tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg).

tJIT(per) = Min/max of {tCKi- tCK(avg) w here i=1 to 200}.

tJIT(per) defines the single period jitter w hen the DLL is already locked.

2. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only.

3. tJIT(cc) is defined as the difference in clock period betw een tw o consecutive clock cycles: tJIT(cc) = Max of |tCKi+1 – tCKi|.

tJIT(cc) defines the cycle to cycle jitter w hen the DLL is already locked.

4. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only.

5. tERR is defined as the cumulative error across multiple consecutive cycles from tCK(avg).

Please refer to JEDEC Standard No. 79-2C (DDR2 SDRAM Specification), Chapter 5 (page 100) for more information.

6. tJIT(duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of

any single tCH from tCH(avg). tCL jitter is the largest deviation of any single tCL from tCL(avg).

tJIT(duty) = Min/max of {tJIT(CH), tJIT(CL)} w here,

tJIT(CH) = {tCHi- tCH(avg) w here i=1 to 200}; tJIT(CL) = {tCLi- tCL(avg) w here i=1 to 200}.

7. tCK(abs),min = tCK(avg),min + tJIT(per),min; tCK(abs),max = tCK(avg),max + tJIT(per),max.

8. tCH(abs),min = tCH(avg),min x tCK(avg),min + tJIT(duty),min; tCH(abs),max = tCH(avg),max x tCK(avg),max + tJIT(duty),max.

9. tCL(abs),min = tCL(avg),min x tCK(avg),min + tJIT(duty),min; tCL(abs),max = tCL(avg),max x tCK(avg),max + tJIT(duty),max.

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8.6.2.3 SDRAM DDR2 Interface Test Circuit

Figure 5: SDRAM DDR2 Interface Test Circuit

Test Point

VTT

50 ohm

8.6.2.4 SDRAM DDR2 Interface AC Timing Diagrams

Figure 6: SDRAM DDR2 Interface Write AC Timing Diagram tDSH tDSS

CLK

CLKn

DQS tCH

DQSn tCL tWPRE tDQSH tDQSL tWPST tDIPW

DQ tDOVB tDOVA

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Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram

CLK

CLKn tCH tCL

ADDRESS/

CONTROL tIPW tAOVB tAOVA

Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram

DQS

DQSn

DQ tDSI tDHI

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8.6.3

8.6.3.1

Electrical Specifications

AC Electrical Specifications

Reduced Gigabit Media Independent Interface (RGMII)

AC Timing

RGMII AC Timing Table

Table 49: RGMII 10/100/1000 AC Timing Table at 1.8V

Description

Clock frequency

Data to Clock output skew

Data to Clock input skew

Clock cycle duration

Duty cycle for Gigabit

Duty cycle for 10/100 Megabit

Sym bol Min fCK 125.0

Max Units Notes

MHz -

Tskew T -0.50

0.50

ns 2

Tskew R 1.00

Tcyc 7.20

Duty_G 0.45

Duty_T 0.40

2.60

8.80

0.55

0.60

ns ns tCK tCK

1 , 2

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

General comment: If the PHY does not support internal-delay mode, the PC board design requires

routing clocks so that an additional trace delay of greater than 1.5 ns and less

than 2.0 ns is added to the associated clock signal.

For 10/100 Mbps RGMII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is CL = 5 pF.

Table 50: RGMII 10/100 AC Timing Table at 3.3V

Description

Clock frequency

Data to Clock output skew

Data to Clock input skew

Clock cycle duration

Duty cycle for Gigabit

Duty cycle for 10/100 Megabit

Sym bol Min fCK 25.0

Max Units Notes

MHz -

Tskew T -0.50

Tskew R 1.00

0.50

2.60

ns ns

Tcyc 7.20

Duty_G 0.45

Duty_T 0.40

8.80

0.55

0.60

ns tCK tCK

1 , 2

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

General comment: If the PHY does not support internal-delay mode, the PC board design requires

routing clocks so that an additional trace delay of greater than 1.5 ns

is added to the associated clock signal.

For 10/100 Mbps RGMII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is CL = 5 pF.

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8.6.3.2

88F6281

Hardware Specifications

RGMII Test Circuit

Figure 9: RGMII Test Circuit

Test Point

8.6.3.3 RGMII AC Timing Diagram

Figure 10: RGMII AC Timing Diagram

CLOCK

(At Transmitter)

DATA

CLOCK

(At Receiver)

DATA

TskewT

TskewR

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AC Electrical Specifications

8.6.4 Gigabit Media Independent Interface (GMII) AC Timing

8.6.4.1 GMII AC Timing Table

Table 51: GMII AC Timing Table

Description

GTX_CLK cycle time

RX_CLK cycle time

GTX_CLK and RX_CLK high level w idth

GTX_CLK and RX_CLK low level w idth

GTX_CLK and RX_CLK rise time

GTX_CLK and RX_CLK fall time

Data input setup time relative to RX_CLK rising edge

Data input hold time relative to RX_CLK rising edge

Data output valid before GTX_CLK rising edge

Data output valid after GTX_CLK rising edge

Sym bol tCK tCKrx tHIGH tLOW tR tF tSETUP tHOLD tOVB tOVA

2.0

0.0

2.5

0.5

125 MHz

Min

7.5

2.5

Max

8.5

1.0

ns ns ns ns ns ns

Units ns ns ns ns

1, 2

Notes

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is CL = 5 pF.

2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

8.6.4.2 GMII Test Circuit

Figure 11: GMII Test Circuit

Test Point

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8.6.4.3

88F6281

Hardware Specifications

GMII AC Timing Diagrams

Figure 12: GMII Output AC Timing Diagram

tLOW tHIGH

GTX_CLK

TXD, TX_EN, TX_ER

tOVB tOVA

Figure 13: GMII Input AC Timing Diagram tLOW tHIGH

RX_CLK

RXD, RX_EN, RX_ER tSETUP tHOLD

VIH(min)

VIL(max)

VIH(min)

VIL(max)

VIH(min)

VIL(max)

VIH(min)

VIL(max)

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AC Electrical Specifications

8.6.5 Media Independent Interface/Marvell Media Independent

Interface (MII/MMII) AC Timing

8.6.5.1 MII/MMII MAC Mode AC Timing Table

Table 52: MII/MMII MAC Mode AC Timing Table

Description

Data input setup relative to RX_CLK rising edge

Data input hold relative to RX_CLK rising edge

Data output delay relative to MII_TX_CLK rising edge

Sym bol tSU tHD tOV

Min

3.5

2.0

0.0

Max

10.0

Units ns ns ns

Notes

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is CL = 5 pF.

8.6.5.2 MII/MMII MAC Mode Test Circuit

Figure 14: MII/MMII MAC Mode Test Circuit

Test Point

8.6.5.3 MII/MMII MAC Mode AC Timing Diagrams

Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram

MII_TX_CLK

TXD, TX_EN, TX_ER

Vih(min)

Vil(max)

Vih(min)

Vil(max)

TOV

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Figure 16: MII/MMII MAC Mode Input AC Timing Diagram

RX_CLK

RXD, RX_EN, RX_ER

Vih(min)

Vil(max) tSU tHD

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8.6.6 Serial Management Interface (SMI) AC Timing

8.6.6.1 SMI Master Mode AC Timing Table

Table 53: SMI Master Mode AC Timing Table

Description

MDC clock frequency

MDC clock duty cycle

MDIO input setup time relative to MDC rise time

MDIO input hold time relative to MDC rise time

MDIO output valid before MDC rise time

MDIO output valid after MDC rise time

Sym bol fCK tDC tSU tHO tOVB tOVA

Min Max

See note 2

0.4

40.0

0.0

15.0

0.6

Units Notes

MHz tCK ns

ns ns ns

Notes:

General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF.

2. See "Reference Clocks" table for more details.

8.6.6.2 SMI Master Mode Test Circuit

Figure 17: MDIO Master Mode Test Circuit

Test Point

VDDIO

2 kilohm

MDIO

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Hardware Specifications

Figure 18: MDC Master Mode Test Circuit

Test Point

MDC

8.6.6.3 SMI Master Mode AC Timing Diagrams

Figure 19: SMI Master Mode Output AC Timing Diagram

VIH(min)

MDC

MDIO

tOVB tOVA

Figure 20: SMI Master Mode Input AC Timing Diagram

MDC

VIH(min)

VIL(max)

VIH(min)

MDIO

VIH(min)

VIL(max) tSU tHO

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8.6.7 JTAG Interface AC Timing

8.6.7.1 JTAG Interface AC Timing Table

Table 54: JTAG Interface AC Timing Table

Description

JTClk frequency

JTClk minimum pulse w idth

JTClk rise/fall slew rate

JTRSTn active time

TMS, TDI input setup relative to JTClk rising edge

TMS, TDI input hold relative to JTClk rising edge

JTClk falling edge to TDO output delay

Sym bol fCK

Tpw

Sr/Sf

Trst

Tsetup

Thold

Tprop

Min

30 MHz

Max

30.0

0.45

0.55

0.50

1.0

6.67

13.0

1.0

8.33

Units

MHz tCK

V/ns ms ns ns ns

Notes

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For TDO signal, the load is CL = 10 pF.

2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time.

8.6.7.2 JTAG Interface Test Circuit

Figure 21: JTAG Interface Test Circuit

Test Point

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Hardware Specifications

JTAG Interface AC Timing Diagrams

Figure 22: JTAG Interface Output Delay AC Timing Diagram

Tprop

(max)

JTCK

VIH

VIL

TDO

Tprop

(min)

Figure 23: JTAG Interface Input AC Timing Diagram

JTCK

TMS,TDI

Tsetup

Thold

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8.6.8 Two-Wire Serial Interface (TWSI) AC Timing

8.6.8.1 TWSI AC Timing Table

Table 55: TWSI Master AC Timing Table

Description

SCK clock frequency

SCK minimum low level w idth

SCK minimum high level w idth

SDA input setup time relative to SCK rising edge

SDA input hold time relative to SCK falling edge

SDA and SCK rise time

SDA and SCK fall time

SDA output delay relative to SCK falling edge

Sym bol fCK tLOW tHIGH tSU tHD tr tf tOV

Min Max

See note 1

0.47

0.40

250.0

0.0

1000.0

300.0

0.4

Units Notes kHz 1 tCK 2 tCK ns ns ns ns tCK

2, 3

Notes:

General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.

3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

Table 56: TWSI Slave AC Timing Table

Description

SCK minimum low level w idth

SCK minimum high level w idth

SDA input setup time relative to SCK rising edge

SDA input hold time relative to SCK falling edge

SDA and SCK rise time

SDA and SCK fall time

SDA output delay relative to SCK falling edge

Sym bol tLOW tHIGH tSU tHD tr tf tOV

100 kHz

Min

4.7

Max

4.0

250.0

0.0

1000.0

300.0

4.0

Units us us ns ns ns ns us

Notes

1, 2

Notes:

General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.

1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.

2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

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Hardware Specifications

TWSI Test Circuit

Figure 24: TWSI Test Circuit

Test Point

VDDIO

8.6.8.3 TWSI AC Timing Diagrams

Figure 25: TWSI Output Delay AC Timing Diagram tHIGH tLOW

SCK

SDA tOV(min) tOV(max)

Figure 26: TWSI Input AC Timing Diagram tLOW tHIGH

SCK

SDA tSU tHD

Vih(min)

Vil(max)

Vih(min)

Vil(max)

Vih(min)

Vil(max)

Vih(min)

Vil(max)

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8.6.9 Sony/Philips Digital Interconnect Format (S/PDIF) AC

Timing

8.6.9.1 S/PDIF AC Timing Table

Table 57: S/PDIF AC Timing Table

Description

Output frequency accuracy

Input frequency accuracy

Output jitter - total peak-to-peak

Jitter transfer gain

Input jitter - total peak-to-peak

Sym bol

Ftxtol

Frxtol

Txjit

Txjitgain

Rxjit

Min

-50.0

-100.0

Max

50.0

100.0

0.05

3.0

10.0

0.25

0.2

Units ppm ppm

Notes

1, 2

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications,

IEC 60958-3:2003(E), Chapter 7.3, January 2003.

1. For all signals, the load is CL = 10 pF.

2. Using inristic jitter filter.

3. Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003.

4. Defined for up to 5 Hz.

5. Defined from 200 Hz to 400 kHz.

6. Defined for above 400 kHz.

Note

For additional information about working with a coax connection, see the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

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Hardware Specifications

S/PDIF Test Circuit

Figure 27: S/PDIF Test Circuit

Test Point

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8.6.10 Inter-IC Sound Interface (I

2 S) AC Timing

8.6.10.1 Inter-IC Sound (I

S) AC Timing Table

Table 58: Inter-IC Sound (I

S) AC Timing Table

Description

I2SBCLK clock frequency

I2SBCLK clock high/low level pulse w idth

I2SDI input setup time relative to I2SBCLK rise time

I2SDI input hold time relative to I2SBCLK rise time

I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time

Sym bol fCK tCH/tCL tSU tHO tOD

Min Max

See note 2

0.37

0.10

0.00

0.10

0.70

Units Notes

MHz 2 tCK tCK ns tCK

Notes:

General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For all signals, the load is CL = 15 pF.

2. See "Reference Clocks" table for more details.

8.6.10.2 Inter-IC Sound (I

S) Test Circuit

Figure 28: Inter-IC Sound (I

S) Test Circuit

Test Point

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Hardware Specifications

Inter-IC Sound (I

S) AC Timing Diagrams

Figure 29: Inter-IC Sound (I

S) Output Delay AC Timing Diagram tCL tCH

I2SBCLK

VIH(min)

VIL(max)

VIH(min)

VIL(max)

I2SDO,

I2SLRCLK tODmin tODmax

Figure 30: Inter-IC Sound (I

S) Input AC Timing Diagram tCL tCH

I2SBCLK

I2SDI

VIH(min)

VIL(max)

VIH(min)

VIL(max) tSU tHO

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8.6.11 Time Division Multiplexing (TDM) Interface AC Timing

8.6.11.1 TDM Interface AC Timing Table

Table 59: TDM Interface AC Timing Table

Description

PCLK cycle time

PCLK duty cycle

PCLK rise/fall time

DTX and FSYNC valid after PCLK rising edge

DRX and FSYNC setup time relative to PCLK falling edge

DRX and FSYNC hold time relative to PCLK falling edge

Sym bol

1/tC tDTY tR/tF tD tSU tHD

8.192 MHz

Min

0.256

Max

8.192

0.4

0.0

10.0

0.6

3.0

20.0

Units

MHz tC ns ns ns ns

Notes

1, 3

1, 2, 8

1, 4, 6

5, 7

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

1. For all signals, the load is CL = 20 pF.

2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform.

3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192 MHz frequencies only.

4. This parameter is relevant to FSYNC signal in master-mode only.

5. This parameter is relevant to FSYNC signal in slave-mode only.

6. In negative-mode, the DTX signal is relative to PCLK falling edge.

7. In negative-mode, the DRX signal is relative to PCLK rising edge.

8. This parameter is relevant w hen the PCLK pin is output.

8.6.11.2 TDM Interface Test Circuit

Figure 31: TDM Interface Test Circuit

Test Point

CL

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Hardware Specifications

TDM Interface Timing Diagrams

Figure 32: TDM Interface Output Delay AC Timing Diagram tC

PCLK

DTX tD tD

Figure 33: TDM Interface Input Delay AC Timing Diagram tC

PCLK

DRX tSU tHD

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8.6.12 Serial Peripheral Interface (SPI) AC Timing

8.6.12.1 SPI (Master Mode) AC Timing Table

Table 60: SPI (Master Mode) AC Timing Table

Description

SCLK clock frequency

SCLK high time

SCLK low time

SCLK slew rate

Data out valid relative to SCLK falling edge

CS active before SCLK rising edge

CS not active after SCLK rising edge

Data in setup time relative to SCLK rising edge

Data in hold time relative to SCLK rising edge

Sym bol fCK tCH tCL tSR tDOV tCSB tCSA tSU tHD

SPI

Min Max

See Note 3

0.46

0.5

-2.5

8.0

0.2

5.0

2.5

Units

MHz tCK tCK

V/ns ns ns ns tCK ns

Notes

Notes:

General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For all signals, the load is CL = 10 pF.

2. Defined from vddio/2 to vddio/2.

3. See "Reference Clocks" table for more details.

8.6.12.2 SPI (Master Mode) Test Circuit

Figure 34: SPI (Master Mode) Test Circuit

Test Point

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Hardware Specifications

SPI (Master Mode) Timing Diagrams

Figure 35: SPI (Master Mode) Output AC Timing Diagram tCH tCL

SCLK

Data

Out tDOVmin tDOVmax

CS tCSB

Figure 36: SPI (Master Mode) Input AC Timing Diagram tCSA

SCLK

Data in

tSU

tHD

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8.6.13 Secure Digital Input/Output (SDIO) Interface AC Timing

8.6.13.1 Secure Digital Input/Output (SDIO) AC Timing Table

Table 61: SDIO Host in High Speed Mode AC Timing Table

Description

Clock frequency in Data Transfer Mode

Clock high/low level pulse w idth

Clock rise/fall time

CMD, DAT output valid before CLK rising edge

CMD, DAT output valid after CLK rising edge

CMD, DAT input setup relative to CLK rising edge

CMD, DAT input hold relative to CLK rising edge

Symbol fCK

Min

0 tWL/tWH 0.35

tTLH/tTHL tDOVB

6.5

tDOVA tISU tIHD

2.5

7.0

0.0

Max

3.0

Units Notes

MHz tCK ns ns

1, 3

2, 3 ns ns ns

2, 3

Notes:

General comment: tCK = 1/fCK.

1. Defined on VIL(max) and VIH(min) levels.

2. Defined on VDDIO/2 for Clock signal, and VIL(max) / VIH(min) for CMD & DAT signals.

3. For all signals, the load is CL = 10 pF.

8.6.13.2 Secure Digital Input/Output (SDIO) Test Circuit

Figure 37: Secure Digital Input/Output (SDIO) Test Circuit

Test Point

VDDIO

50 KOhm

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Hardware Specifications

Secure Digital Input/Output (SDIO) AC Timing Diagrams

Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram tWL tWH

CLK

DAT,

CMD

VIH(min)

VIL(max)

VIH(min)

VDDIO/2

VIL(max) tDOVB tDOVA

Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram tWL tWH

CLK

DAT,

CMD

VIH(min)

VIL(max)

VIH(min)

VDDIO/2

VIL(max) tISU tIHD

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8.6.14 Transport Stream (TS) Interface AC Timing

8.6.14.1 Transport Stream Interface AC Timing Table

Table 62: Transport Stream Output Interface AC Timing Table

Description

Clock frequency

Clock minimum low level w idth

Clock minimum high level w idth

Data output valid after Clock rising edge

Sym bol fCK tLOW tHIGH tOV

Min Max Units

See note 1 MHz

0.4

0.6

tCK tCK

0.4

0.6

tCK

Notes

2, 3

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. For all signals, the load is CL = 5 pF.

3. When configured to falling edge, the tOV parameter is relative to Clock falling edge.

Table 63: Transport Stream Input Interface AC Timing Table

Description

Clock frequency

Clock minimum low level w idth

Clock minimum high level w idth

Data input setup time relative to Clock rising edge

Sym bol fCK tLOW tHIGH tSU tHD

Min Max Units

See note 1

0.35

0.65

MHz tCK tCK

0.30

tCK tCK

Notes

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. When configured to falling edge, the tSU/tHD parameters are relative to Clock falling edge.

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88F6281

Hardware Specifications

Transport Stream Interface Test Circuit

Figure 40: Transport Stream Interface Test Circuit

Test Point

8.6.14.3 Transport Stream Interface Timing Diagrams

Figure 41: Transport Stream Output Interface AC Timing Diagram tHIGH tLOW

Clock

Data Out

Vih(min)

Vil(max)

Vih(min)

Vil(max) tOV(min) tOV(max)

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AC Electrical Specifications

Figure 42: Transport Stream Input Interface AC Timing Diagram tLOW tHIGH

Clock

Data In

Vih(min)

Vil(max)

Vih(min)

Vil(max) tSU tHD

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Hardware Specifications

8.7 Differential Interface Electrical Characteristics

This section provides the reference clock, AC, and DC characteristics for the following differential interfaces:

PCI Express Interface Electrical Characteristics

SATA Interface Electrical Characteristics

USB Electrical Characteristics

8.7.1 Differential Interface Reference Clock Characteristics

8.7.1.1 PCI Express Interface Differential Reference Clock Characteristics

Table 64: PCI Express Interface Differential Reference Clock Characteristics

Description

Clock frequency

Clock duty cycle

Differential rising/falling slew rate

Differential high voltage

Differential low voltage

Absolute crossing point voltage

Variation of Vcross over all rising clock edges

Sym bol fCK

DCrefclk

SRrefclk

VIHrefclk

VILrefclk

Vcross

Vcrs_dlta

Min

0.4

0.6

150.0

100.0

Max

0.6

4.0

-150.0

Average differential clock period accuracy

Absolute differential clock period

Differential clock cycle-to-cycle jitter

Tperavg

Tperabs

Tccjit

250.0

-300.0

9.8

Notes:

General Comment: The reference clock timings are based on 100 ohm test circuit.

General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1,

550.0

140.0

2800.0

10.2

150.0

March 2005, section 2.1.3 for more information.

1. Defined on a single-ended signal.

2. Including jitter and spread spectrum.

3. Defined from -150 mV to +150 mV on the differential w aveform.

Units Notes

MHz tCK

V/nS

3 mV mV mV mV

ppm nS pS

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Differential Interface Electrical Characteristics

PCI Express Interface Spread Spectrum Requirements

Table 65: PCI Express Interface Spread Spectrum Requirements

Fmod

Fspread

Sym bol Min

0.0

-0.5

Max

33.0

0.0

Units Notes kHz 1

% 1

Notes:

1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations.

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Hardware Specifications

8.7.2 PCI Express Interface Electrical Characteristics

8.7.2.1 PCI Express Interface Driver and Receiver Characteristics

Table 66: PCI Express Interface Driver and Receiver Characteristics

Description

Baud rate

Unit interval

Baud rate tolerance

Differential peak to peak output voltage

Minimum TX eye w idth

Differential return loss

Common mode return loss

DC differential TX impedance

Differential input peak to peak voltage

Minimum receiver eye w idth

Differential return loss

Common mode return loss

DC differential RX impedance

DC common input impedance

Sym bol

Bppm

Driver parameters

VTXpp

TTXeye

TRLdiff

TRLcm

ZTXdiff

Receiver parameters

VRXpp

TRXeye

RRLdiff

RRLcm

ZRXdiff

ZRXcm

Min Max

2.5

-300.0

400.0

300.0

0.175

0.4

10.0

6.0

80.0

40.0

0.8

0.75

10.0

6.0

80.0

1.2

120.0

60.0

1.2

120.0

Units

Gbps ps ppm

UI dB dB

Ohm

UI dB dB

Ohm

Notes

Notes:

General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005.

1. Defined from 50 MHz to 1.25 GHz.

2. Does not account for SSC dictated variations.

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8.7.2.2

Electrical Specifications

Differential Interface Electrical Characteristics

PCI Express Interface Test Circuit

Figure 43: PCI Express Interface Test Circuit

Test Points

D+

C_TX

D-

C_TX

50 ohm 50 ohm

When measuring Transmitter output parameters, C_TX is an optional portion of the

Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF.

C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane.

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Hardware Specifications

SATA Interface Electrical Characteristics

The driver and receiver characteristics for the SATA-I Interface Gen1i Mode and the SATA-II

Interface Gen2i Mode are provided in the following sections.

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Differential Interface Electrical Characteristics

8.7.3.1 SATA-I Interface Gen1i Mode Driver and Receiver Characteristics

Table 67: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics

Description

Baud Rate

Baud rate tolerance

Spread spectrum modulation frequency

Spread spectrum modulation Deviation

Unit Interval

Sym bol

Bppm

Fssc

Min

-350.0

30.0

1.5

Max

350.0

33.0

SSCtol -5000.0

UI 666.67

0.0

Differential impedance

Single ended impedance

Differential return loss (75 MHz-150 MHz)

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Output differential voltage

Total jitter at connector data-data, 5UI

Deterministic jitter at connector data-data, 5UI

Total jitter at connector data-data, 250UI

Deterministic jitter at connector data-data, 250UI

Driver Parameters

Zdifftx

Zsetx

RLOD

Vdifftx

TJ5

DJ5

TJ250

DJ250

85.0

40.0

14.0

8.0

6.0

3.0

1.0

400.0

115.0

600.0

0.355

0.175

0.470

0.220

Differential impedance

Single ended impedance

Differential return loss (75 MHz-150 MHz)

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Input differential voltage

Total jitter at connector data-data, 5UI

Deterministic jitter at connector data-data, 5UI

Total jitter at connector data-data, 250UI

Deterministic jitter at connector data-data, 250UI

Receiver Parameters

Zdiffrx

Zsetx

RLID

Vdiffrx

TJ5

DJ5

TJ250

DJ250

85.0

40.0

18.0

14.0

10.0

8.0

3.0

1.0

325.0

115.0

600.0

0.430

0.250

0.600

0.350

Notes:

General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Total jitter is defined as TJ = (14 * RJ σ ) + DJ w here Rj σ is random jitter.

2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description

for more details.

Ohm

Ohm dB dB mV

UI dB dB dB dB

Units

Gbps ppm kHz ppm ps

Ohm

Ohm dB dB dB dB dB mV

Notes

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8.7.3.2 SATA-II Interface Gen2i Mode Driver and Receiver Characteristics

Table 68: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Description

Spread spectrum modulation frequency

Spread spectrum modulation Deviation

Unit Interval

Output differential voltage

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Differential return loss (3.0 GHz-5.0 GHz)

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Sym bol

Bppm

Min

-350.0

3.0

Max

350.0

Fssc 30.0

SSCtol -5000.0

UI 333.33

33.0

0.0

Driver Parameters

Vdifftx

RLOD

TJ10

DJ10

TJ500

DJ500

400.0

14.0

8.0

6.0

3.0

1.0

700.0

0.30

0.17

0.37

0.19

Input differential voltage

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Differential return loss (3.0 GHz-5.0 GHz)

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Receiver Parameters

Vdiffrx

RLID

TJ10

DJ10

TJ500

DJ500

275.0

18.0

14.0

10.0

8.0

3.0

1.0

750.0

0.46

0.35

0.60

0.42

Notes:

General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. 0.45-0.55 UI is the range w here the signal meets the minimum level.

2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description

for more details.

3. Defined for BR/10.

4. Defined for BR/500.

5. 0.5 UI is the point w here the signal meets the minimum level.

mV dB dB dB dB dB dB

UI mV dB

UI dB dB dB dB

Units

Gbps ppm kHz ppm ps

1 , 2

Notes

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December 2, 2008, Preliminary

Electrical Specifications

Differential Interface Electrical Characteristics

8.7.4 USB Electrical Characteristics

8.7.4.1 USB Driver and Receiver Characteristics

Table 69: USB Low Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Ouput single ended high

Ouput single ended low

Description

Output signal crossover voltage

Data fall time

Data rise time

Rise and fall time matching

Source jitter total: to next transition

Source jitter total: for paired transitions

Low Speed

Sym bol

Min

1.5

Max

Bppm -15000.0

15000.0

Driver Parameters

VOH 2.8

3.6

VOL

VCRS

TLR

TLF

0.0

1.3

75.0

0.3

2.0

300.0

TLRFM

TUDJ1

TUDJ2

Receiver Parameters

VIH

VIL

VDI

80.0

-95.0

-150.0

2.0

0.2

125.0

95.0

150.0

0.8

Units

Mbps ppm

Input single ended high

Input single ended low

Differential input sensitivity

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.

2. Defined w ith 14.25 kilohm pull-dow n resistor to ground.

3. See "Data Signal Rise and Fall Time" w aveform.

% ns ns

V ns

4. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

5. Including frequency tolerance. Timing difference betw een the differential data signals.

Defined at crossover point of differential data signals.

Notes

3, 4

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Table 70: USB Full Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Ouput single ended high

Ouput single ended low

Description

Output signal crossover voltage

Output rise time

Output fall time

Source jitter total: to next transition

Sym bol

Bppm

Driver Parameters

VOH

VOL

VCRS

TFR

TFL

TDJ1

Source jitter total: for paired transitions TDJ2

Source jitter for differential transition to SE0 transition TFDEOP

Receiver Parameters

Input single ended high

Input single ended low

Differential input sensitivity

Receiver jitter : to next transition

Receiver jitter: for paired transitions

VIH

VIL

VDI tJR1 tJR2

Full Speed

Min

2.8

0.0

1.3

4.0

-3.5

-4.0

-2.0

2.0

0.2

-18.5

-9.0

12.0

Max

-2500.0

2500.0

3.6

0.3

2.0

20.0

3.5

4.0

5.0

0.8

18.5

9.0

Units

Mbps ppm ns ns ns ns

V ns

V ns ns

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1.. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.

2.. Defined w ith 14.25 kilohm pull-dow n resistor to ground.

3. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

4. See "Data Signal Rise and Fall Time" w aveform.

5. Including frequency tolerance. Timing difference betw een the differential data signals.

6. Defined at crossover point of differential data signals.

Notes

3, 4

5, 6

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Electrical Specifications

Differential Interface Electrical Characteristics

Table 71: USB High Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Data signaling high

Data signaling low

Data rise time

Data fall time

Data source jitter

Description Sym bol

Bppm

Driver Parameters

VHSOH

VHSOL

THSR

THSF

High Speed

Min

-500.0

480.0

Max

500.0

360.0

-10.0

500.0

440.0

10.0

See note 2

Units

Mbps ppm mV mV ps ps

Receiver Parameters

Differential input signaling levels

Data signaling common mode voltage range

Receiver jitter tolerance

VHSCM

See note 3

-50.0

500.0

See note 3 mV

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

2. Source jitter specified by the "TX eye diagram pattern template" figure.

3. Receiver jitter specified by the "RX eye diagram pattern template" figure.

Notes

8.7.4.2 USB Interface Driver Waveforms

Figure 44: Low/Full Speed Data Signal Rise and Fall Time

Rise Time

90%

Fall Time

VCRS

90%

10% 10%

Differential

Data Lines

TR TF

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Hardware Specifications

Figure 45: High Speed TX Eye Diagram Pattern Template

+525mV

+475mV

+300mV

+400mV

Differential

0 Volts

Differential

-300mV

-475mV

-525mV

7.5% 37.5% 62.5% 92.5%

100%

Figure 46: High Speed RX Eye Diagram Pattern Template

- 400mV

Differential

+525mV

+475mV

+400mV

Differential

+175mV

0 Volts

Differential

-175mV

- 400mV

Differential

-475mV

-525mV

12.5% 35 65 87.5%

100%

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Thermal Data (Preliminary)

Thermal Data (Preliminary)

Table 72 provides the package thermal data for the device. This data is derived from simulations that were run according to the JEDEC standard.

The thermal parameters are preliminary and subject to change.

Note

TET

The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Before designing a system it is recommended to refer to these documents:

Application Note, AN-63 Thermal Management for Selected Marvell® Products, Document

Number MV-S300281-00

White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Document Number

MV-S700019-00.

Table 72: Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package (Preliminary)

S y m b o l D e f i n i t i o n

θ

Thermal resistance: junction to ambient.

Thermal characterization parameter: junction to case center.

Thermal resistance: junction to case (not air-flow dependent)

Thermal characterization parameter: junction to the bottom of the package.

Thermal resistance: junction to the bottom of the package (not air-flow dependent)

A i r f l o w Va l u e ( C / W )

0 [ m / s ] 1 [ m / s ]

20.2

18.7

7.0

2 [ m / s ]

18.1

7.1

10.7

8.4

10.6

10.9

10.6

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Hardware Specifications

Package

This section provides the 88F6281 package drawing and dimensions.

Figure 47: HSBGA 288-pin Package and Dimensions

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Table 73: HSBGA 288-pin Package Dimensions

Package

Body size

Ball pitch

Total thickness

Mold thickness

Substrate thickness

Ball diameter

Standoff

Ball width

Mold area

H/S exposed size

H/S flatness

H/S shift with substrate edge

H/S shift with mold area

Chamfer

Package edge tolerance

Substrate flatness

Mold flatness

Copolarity

Ball offset (package)

Ball offset (ball)

Ball count

Edge ball center-to-center

Y fff n ddd eee

CA aaa bbb ccc

A1 b

S y m b o l C o m m o n D i m e n s i o n

( i n m i l l i m e t e r s )

HSBGA

E eD eE

19.000

1.000

1.910 ± 0.190

0.850 ref

0.560 ref

0.600

0.400 ~ 0.600

0.500 ~ 0.700

17.000

12.000 ~ 13.200

0.100

0.300

0.500

1.215 ref

0.200

0.250

0.350

0.200

0.250

0.100

288

17.000

Package

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Hardware Specifications

Part Order Numbering/Package Marking

11.1 Part Order Numbering

Figure 48 shows the part order numbering scheme for the 88F6281. Refer to Marvell Field

Application Engineers (FAEs) or representatives for further information when ordering parts.

Figure 48: Sample Part Number

88F6281 –xx–BIA2Cxxx–xxxx

Part number

88F6281

Die revision

Custom code (optional)

Speed code

100 = 1.0 GHz

120 = 1.2 GHz

150 = 1.5 GHz

Custom code

Package code

BIA = 288-pin HSBGA

Temperature code

C = Commercial

I = Industrial

Environmental code

2 = Green (RoHS 6/6 and

Halogen-free)

Table 74: 88F6281 Part Order Options

P a c k a g e Ty p e

288-pin BGA

P a r t O r d e r N u m b e r

88F6281-xx-BIA2C100 (Green, RoHS 6/6 and Halogen-free package), 1.0 GHz

88F6281-xx-BIA2C120 (Green, RoHS 6/6 and Halogen-free package), 1.2 GHz

88F6281-xx-BIA2C150 (Green, RoHS 6/6 and Halogen-free package), 1.5 GHz

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Part Order Numbering/Package Marking

Package Marking

11.2 Package Marking

Figure 49 shows a sample Commercial package marking and pin 1 location for the 88F6281.

Figure 49: Commercial Package Marking and Pin 1 Location

Country of origin code

(Contained in the mold ID or marked as the last line on the package.)

Part number and die revision code

88F6281 = Part number xx = Die revision code

Pin 1 location

88F6-BIAe

Lot Number

YYWW xx@

Country of Origin

88F6281-xx

XXXX

Marvell logo

Part number prefix, package code, environmental code

88F6 = Part number prefix

BIA = Package code e = Environmental code: 2 = Green

Date code, custom code, assembly plant code

YYWW = Date code (YY = year, WW = Work Week) xx = Custom code

@ = Assembly plant code

Temperature and speed code

C100 = Commercial, 1.0 GHz

C120 = Commercial, 1.2 GHz

C150 = Commercial, 1.5 GHz

Note: The above drawing is not drawn to scale. Location of markings is approximate.

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Revision History

Table 75: Revision History

R e v i s i o n D a t e C o m m e n ts

E December 2, 2008 Revision

1. In Figure 1, 88F6281 Pin Logic Diagram, on page 18 , changed the GE_TXCLKOUT pin to input/output and added a note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock.

2. In Table 6, PCI Express Interface Pin Assignments, on page 26 , revised the description of the PEX_CLK_P/N pins to state that they can be configured as input or output according to the reset strap.

3. In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28 , indicated that:

• When the GE_TXCLKOUT pin is used as an MII/MMII Transmit Clock, it is an input pin.

• When the MPP[29]/GE1[9] pin is used as a GMII Transmit Clock, it is a Tri-State output pin.

4. In Table 12, RTC Interface Pin Assignments, on page 35 , changed the type for RTC_XOUT to analog.

5. In the description of signal AU_SPDFRMCLK in Table 17, Audio (S/PDIF / I

S) Interface Signal Assignment, on page 40 , added a reference to the new AU_SPDFRMCLK information in the Reference Clock AC Timing

Specifications table.

6. In Table 24, Unused Interface Strapping, on page 49 , revise the description for configuring the PCI Express clock signals.

7. At the end of Section 4.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 57 , added a note stating that all relevant Gigabit Ethernet signals must be implemented.

8. In the Table 32, Reset Configuration, on page 67 , revised the configuration function for parameter CPU_CLK to DDR

CLK Ratio .

9. In Table 36, Recommended Operating Conditions, on page 77 , for parameter RTC_AVDD Analog supply for RTC in

Battery Back-up mode, revised the values for the minimum to 1.3V from 1.4V and for the maximum to 1.7V from 1.6V.

10. In Table 37, Thermal Power Dissipation, on page 79 :

• For the Embedded CPU (VDD_CPU 1.1V) parameter changed the L2 cache frequency to 333 MHz.

• for the eFuse during Burning mode parameter added a note:

The eFuse burn is done once, and there should be no thermal effect, after it has been burned.

11. In Table 38, Current Consumption, on page 80 , for the Embedded CPU (VDD_CPU 1.1V) parameter changed the L2 cache frequency to 333 MHz.

12. In Table 45, Reference Clock AC Timing Specifications, on page 86 :

• Revised the names of the Ethernet transmit symbols to F

GE_TXCLK_OUT

, DC

GE_TXCLK_OUT

, and SR

GE_TXCLK_OUT

• Added the S/PDIF Recovered Master Clock.

• Added the Transport Stream External Reference Clock.

• For the PTP Reference Clock, revised the values for the Frequency, Duty Cycle, and Pk-Pk jitter parameters.

13. In Table 46, SDRAM DDR2 Interface AC Timing Table, on page 88 , revised the minimum value for symbol tDHI to 0.70 ns from 0.72 ns.

D October 5, 2008 Revision

14. In Table 6, PCI Express Interface Pin Assignments, on page 26 , revised the note in the description of the

PEX_CLK_P/N pins.

15. In Table 24, Unused Interface Strapping, on page 49 , added the eFuse strapping.

16. In Section 6.1.1, Power-Up Sequence Requirements, on page 63 and Section 6.1.2, Power-Down Sequence

Requirements, on page 64 , added a power up/down requirements for when VHV is in eFuse Burning mode.

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Revision History

Table 75: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

17. In Table 36, Recommended Operating Conditions, on page 77 :

• For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode) and added notes in the comments column for both VHV voltages.

• For VDD_M, PEX_AVDD, and USB_AVDD, revised the comments column.

• for RTC_AVDD, revised the values for minimum to 1.4V from 1.3V and for maximum to 1.6V from 1.7V.

18. In Table 37, Thermal Power Dissipation, on page 79 , revised the row for the SDRAM and added a row for the eFuse.

19. In Table 38, Current Consumption, on page 80 , revised the row for the SDRAM and added a row for the eFuse.

20. In Table 45, Reference Clock AC Timing Specifications, on page 86 :

• For the CPU and Core Reference Clock frequency, revised the values.

• For the PTP Reference Clock, added the Slew rate and Pk-Pk jitter parameters.

C August 18, 2008 Revision

1. Added the XOR engine to the block diagram in the Product Overview on page 3 .

2. Added AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns to the list of Related

Documentation on page 15 .

3. In Figure 1, 88F6281 Pin Logic Diagram, on page 18 , added VHV, and MRn and changed PEX_CLK_P/N for input to input/output (I/O).

4. In the pin map and pin list, revised pins F04 to MRn and G04 to VHV.

5. In Table 3, Power Pin Assignments, on page 21 :

• Added VHV.

• Changed the voltage for XTAL_AVDD from 2.5V to 1.8V.

• Changed the voltage for SATA0_AVDD/SATA1_AVDD from 2.5V to 3.3V.

• Revised the description of VDD_GE_A and VDD_GE_B to add additional information about RGMII.

6. In Table 4, Miscellaneous Pin Assignments, on page 23 , added the signal MRn.

7. In Table 5, DDR SDRAM Interface Pin Assignments, on page 24 , revised the description of M_NCASL and M_PCAL to indicate the range of the resistor.

8. In Table 6, PCI Express Interface Pin Assignments, on page 26 , changed PEX_CLK_P/N for input to input/output (I/O).

9. Added present and active pins to Table 7, SATA Port Interface Pin Assignment, on page 27 .

10. In Section 1.2.6, Gigabit Ethernet Port Interface Pin Assignments, on page 28 :

• Added a note: For the TXCLK, use the GE_RXCLK pin. Also indicated which pins are for port0 and which for port1.

• In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28 , added a description for MII/MMII to the

GE_TXD[3:0], GE_TXCTL, GE_RXCTL, GE_RXCLK, GE_RXD[3:0] rows. Also for pin MPP[30]/GE1[10] added a description for MII/MMII Receive Data Valid.

11. In Table 17, Audio (S/PDIF / I

S) Interface Signal Assignment, on page 40 , revised the power rail to

VDDO/VDD_GE_B.

12. Revised Table 19, Secure Digital Input/Output (SDIO) Interface Signal Assignment, on page 42 to indicate the pins requiring pull up.

13. Added Table 21, Transport Stream (TS) Interface Signal Assignment, on page 45 .

14. Added Section 1.2.20, Precise Timing Protocol (PTP) Interface, on page 47 .

15. In Table 23, Internal Pull-up and Pull-down Pins, on page 48 , revised the pin numbers and changed pins GE_MDC,

MPP[7] and MPP[18] from pull down to pull up and removed MPP[13], MPP[15], and MPP[17] from the table, since they do not require a pull up/down.

16. In Table 2, Unused Interface Strapping, on page 49 , revised the description of the strapping for the

SATA0_AVDD/SATA1_AVDD pins.

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Hardware Specifications

Table 75: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

17. In Section 4.1, Multi-Purpose Pins Functional Summary, on page 51 :

• Changed all references to MPP[0] and MPP[11] from GPI to GPIO.

• Changed the MPP[6] row in the table to remove the 0x0 option.

• Added the following bullet at the end of the section, after the tables: When TWSI serial ROM initialization is enabled,

MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively.

• Revised the description of SYSRST_OUTn.

• Added a bullet: Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn).

18. In Table 27, Ethernet Ports Pins Multiplexing, on page 57 , added a new configuration option for the Gigabit Ethernet ports: Port 0 MII/MMII, port 1 RGMII.

19. In Section 4.3, TSMP (TS Multiplexing Pins) on MPP, on page 59 , added to the description of the TSMP pins.

20. Revised Table 29, 88F6281Clocks, on page 60 and Table 30, Supported Clock Combinations, on page 61 .

21. Revised Section 5.1, Spread Spectrum Clock Generator (SSCG), on page 62 .

22. In Section 6.2, Hardware Reset, on page 64 , added SYSRST_OUTn to the list of pins that are still active during

SYSRSTn assertion.

23. Revised Section 6.2.1, Reset Out Signal, on page 65 and Section 6.2.3, SYSRSTn Duration Counter, on page 65 and added Section 6.2.2, Power On Reset (POR), on page 65 .

24. In Section 6.3.2, PCI Express Endpoint Reset, on page 66 revised the bulleted items.

25. Revised Section 6.5, Pins Sample Configuration, on page 66 .

26. Made major revisions to Table 32, Reset Configuration, on page 67 .

27. Revised the first two paragraphs in Section 6.6, Serial ROM Initialization, on page 70 .

28. In Section 6.7, Boot Sequence, on page 71 revised the paragraph following step 4.

29. Revised Table 45, Reference Clock AC Timing Specifications, on page 86 .

30. In Table 34, IDCODE Register Map, on page 74 , revised the description of bits [31:28].

31. In Table 35, Absolute Maximum Ratings, on page 75 :

• Added VHV.

• Revised the voltage for the SATA and XTAL AVDD parameters.

32. In the Table 36, Recommended Operating Conditions, on page 77 :

• Added values for VDD_CPU.

• Added VHV and revised the voltage for the SATA and XTAL AVDD parameters.

• For the 3.3V interfaces, revised the minimum value to 3.15V and the maximum value to 3.45V (+/-5%).

• Revised the description of the VDD_GE_A/VDD_GE_B row, to show that RGMII can also operate with a voltage of

3.3V.

• Revised the values for PEX_AVDD to minimum 1.7V, typical 1.8V, and maximum 1.9V.

33. In Table 37, Thermal Power Dissipation, on page 79

• Revised values for Core, Embedded CPU, PCI Express, USB and SATA parameters.

• Changed all occurrences of VDD_CPU to VDD.

• Added the row RGMII 3.3V interface.

• Revised the notes following the table, to remove reference to the trace length or resistance.

34. In Table 38, Current Consumption, on page 80

• Revised values for Core, Embedded CPU, SATA, PCI Express and USB parameters.

• Changed all occurrences of VDD_CPU to VDD.

• Revised the interface RGMII 1.8V interface to RGMII 1.8V or 3.3V interface.

• Revised the notes following the table to remove reference to the trace length or resistance.

35. Deleted Section 8.5.2 REF_CLK_XIN 2.5V (CMOS) DC Electrical Specifications and added pin REF_CLK_XIN to

Section 8.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 82 , since the power rail for the REF_CLK_XIN pin was changed from 2.5V to 1.8V.

36. In Section 8.5.1, General 3.3V (CMOS) DC Electrical Specifications, on page 81 , added reference to PTP and RGMII.

37. Revised Table 64, PCI Express Interface Differential Reference Clock Characteristics, on page 118 and Table 65, PCI

Express Interface Spread Spectrum Requirements, on page 119 .

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December 2, 2008, Preliminary

Revision History

Table 75: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

38. Revised Figure 25, TWSI Output Delay AC Timing Diagram, on page 104 so that it shows SDA t

relative to the SCK falling edge, as shown in the two tables that proceed the figure.

39. In Table 73, HSBGA 288-pin Package Dimensions, on page 131 , changed the maximum value for the parameter H/S

exposed size to 13.200 mm.

40. Revised all of Section 11, Part Order Numbering/Package Marking, on page 132 .

B April 8, 2008 Revision

1. In the features list:

• Added the bullets Precise Timing Protocol (PTP) and Audio Video Bridging networks.

• Added the functional block diagram and the usage model diagram.

2. Throughout this specification, LVCMOS and LVTTL were changed to CMOS.

3. In Figure 1, 88F6281 Pin Logic Diagram, on page 18 revised the power pins and removed the interfaces that are multiplexed on the MPP pins.

4. Revised Table 1, Pin Functions and Assignments Table Key, on page 19 to show only terms relevant for this device.

5. In Table 3, Power Pin Assignments, on page 21 , added pins SSCG_AVDD and SSCG_AVSS and added the SMI interface at 1.8V and the MII/MMII interface at 3.3V to the description of the interfaces supported by pin VDD_GE_A.

6. In Table 8, Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 28 , removed pins GE_MDC and GE_MDIO.

7. Added Section 1.2.7, Serial Management Interface (SMI) Interface Pin Assignments, on page 32 , with a description of the GE_MDC and GE_MDIO pins.

8. In Table 12, RTC Interface Pin Assignments, on page 35 , changed the pin type for RTC_XIN to analog from CMOS.

9. In Table 15, Two-Wire Serial Interface (TWSI) Interface Pin Assignment, on page 38 , changed the note to:

Requires a pull-up resistor to VDDO.

10. Added Section 2, Unused Interface Strapping, on page 49 .

11. In Table 29, 88F6281Clocks, on page 60 , revised the description of CPU PLL to mention SSCG.

12. Added Section 5.1, Spread Spectrum Clock Generator (SSCG), on page 62 .

13. Added Section 6.1, Power-Up/Down Sequence Requirements, on page 63 and revised the title of Section 6 to reflect this change.

14. In Section 6.4, Sheeva

™

CPU TAP Controller Reset, on page 66 , revised the note referring to sample at reset and added the note: If a signal is pulled up on the board, it must be pulled to the proper voltage level. Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see

Table 36, Recommended Operating Conditions, on page 77 ).

15. In Table 35, Absolute Maximum Ratings, on page 75 and Table 36, Recommended Operating Conditions, on page 77 , added the parameter SSCG_VDD.

16. In Table 37, Thermal Power Dissipation, on page 79 added the following:

The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.

17. In Table 38, Current Consumption, on page 80 added the following:

The purpose of the Current Consumption table is to support board power design and power module selection.

18. In Table 45, Reference Clock AC Timing Specifications, on page 86 :

• Revised the symbols for the Transport Stream (TS) output and input mode reference clocks.

• Revised the symbols for the SMI master mode reference clock.

• Revised the symbols for the TWSI master mode reference clock.

• Revised the description for symbol F

RTC_XIN.

• Removed the RGMII, GMII, MII 100 Mbps, and MII 10 Mbps rows, since they are not relevant to this device.

19. In Table 67, SATA-I Interface Gen1i Mode Driver and Receiver Characteristics, on page 123 , added driver and receiver return loss parameters, according to updated standard.

A January 28, 2008 Initial release

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104859-U0 Rev. E

Page 137

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Contact I NFORMATION

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

Marvell.

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