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Express-HLE
User’s Manual
Manual Revision: 1.03
Revision Date: February 7, 2017
Part Number: 50-1J050-1030
Revision History
Revision Description
1.01
1.02
1.03
Add BIOS beep codes; correct PCIe Configuration Switch settings
Update 3.4.5 PEG Graphics pinout description
Update eDP-to-LVDS IC info
Date By
2014-04-23 JC
2014-10-22 JC
2017-01-04
2017-02-07
JC
JC
Page 2 Express-HLE
Preface
Copyright 2014, 2017 ADLINK Technology, Inc.
This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.
Disclaimer
The information in this document is subject to change without prior notice in order to improve reliability, design, and function and does not represent a commitment on the part of the manufacturer. In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.
Environmental Responsibility
ADLINK is committed to fulfill its social responsibility to global environmental preservation through compliance with the European Union's
Restriction of Hazardous Substances (RoHS) directive and Waste Electrical and Electronic Equipment (WEEE) directive. Environmental protection is a top priority for ADLINK. We have enforced measures to ensure that our products, manufacturing processes, components, and raw materials have as little impact on the environment as possible. When products are at their end of life, our customers are encouraged to dispose of them in accordance with the product disposal and/or recovery programs prescribed by their nation or company.
Trademarks
Product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.
Express-HLE Page 3
Table of Contents
Page 4 Express-HLE
5 Smart Embedded Management Agent (SEMA) ................................................ 40
Express-HLE Page 5
1
Introduction
The Express-HLE is a COM Express® COM.0 R2.1 Type 6 module supporting the 64-bit 4th Generation Intel® Core™ i7/i5/3 processor with
Intel® QM87 Chipset and 4th Generation Intel® Celeron® processor with Intel® HM86 Chipset. The Express-HLE is specifically designed for customers who need high-level processing and graphics performance in a long product life solution.
The Express-HLE supports Intel® Hyper-Threading Technology (up to 4 cores, 8 threads) and ECC type DDR3L dual-channel memory at
1333/1600 MHz to provide excellent overall performance. Intel® Flexible Display Interface and Direct Media Interface provide high speed connectivity from the CPU to the Intel® QM87/HM86 Chipset.
Integrated Intel Generation 7.5 Graphics includes features such as OpenGL 3.1, DirectX 11, Intel® Clear Video HD Technology, Advanced
Scheduler 2.0, 1.0, XPDM support, and DirectX Video Acceleration (DXVA) support for full AVC/VC1/MPEG2 hardware decode. Graphics outputs include VGA, LVDS and three DDI ports supporting HDMI / DVI / DisplayPort. The Express-HLE is specifically designed for customers with high-performance processing graphics requirements who want to outsource the custom core logic of their systems for reduced development time.
The Express-HLE has dual stacked SODIMM sockets for up to 16 GB ECC type DDR3L memory. The Intel® Mobile QM87/HM86 Chipset integrates VGA and dual-channel 18/24-bit LVDS display output. In addition to the onboard integrated graphics, a multiplexed PCI Express® x16 Graphics bus is available for discrete graphics expansion or general purpose x8 or x4 PCI Express® connectivity.
The Express-HLE features a single onboard Gigabit Ethernet port, USB 3.0 ports and USB 2.0 ports, and SATA 6 Gb/s ports. Support is provided for SMBus and I 2 C. The module is equipped with SPI AMI EFI BIOS with CMOS backup, supporting embedded features such as remote console, CMOS backup, hardware monitor, and watchdog timer.
Page 6 Express-HLE
2
Specifications
2.1
Core System
¾ CPU: 4th Generation Intel® Core™ and Celeron® Processors - 22nm, (formerly known as "Haswell Platform")
• Intel® Core™ i7-4860EQ 2.4 GHz (3.2 GHz Turbo), 47W (4C/GT3)
• Intel® Core™ i7-4700EQ 2.4/1.7 GHz (3.4 GHz Turbo), 47/37W (4C/GT2)
• Intel® Core™ i5-4400E 2.7 GHz (3.3 GHz Turbo), 37W (2C/GT2)
• Intel® Core™ i5-4402E 1.6 GHz (2.7 GHz Turbo), 25W (2C/GT2)
• Intel® Core™ i3-4100E 2.4 GHz (no Turbo) 3MB, 37W (2C/GT2)
• Intel® Core™ i5-4102E 1.6 GHz (no Turbo) 3MB, 25W (2C/GT2)
• Intel® Celeron 2000E 2.2 GHz (no Turbo) 35W (2C/GT1)
• Intel® Celeron 2002E 1.5 GHz (no Turbo) 25W (2C/GT1)
¾ L3 Cache : 6MB for i7-4650U, 3MB for i5-4400E, i5-4402E, i3-4100E and i3-4102E, 2MB for 2000E and 2002E
¾ Memory : Dual channel ECC 1600/1333 MHz DDR3L memory up to 16GB in dual SODIMM socket
¾ Chipset : Mobile Intel® QM87 Chipset (Intel® Core™ i7/i5/i3)
Mobile HM86 Chipset (Intel® Celeron)
¾ BIOS : AMI EFI with CMOS backup in 8MB SPI BIOS with Intel® AMT 9.0 support (Intel® AMT not supported by HM86)
2.2
Expansion Busses
¾ PCI Express x16 (Gen3) or PCI Express (2 x8 or 1 x8 with 2 x4)
¾ 6 PCI Express x1 (AB): Lanes 0/1/2/3/4/5
¾ 1 PCI Express x1 (CD): Lane 6
¾ LPC bus, SMBus (system) , I 2 C (user)
2.3
Video
¾ Integrated in Processor: Intel® Generation 7.5 graphics core architecture
¾ GPU Feature Support:
• 3 independent and simultaneous display combinations of DisplayPort / HDMI / LVDS monitors
• Encode/transcode HD content
• Playback of high definition content including Blu-ray Disc*
• Superior image quality with sharper, more colorful images
• Playback of Blu-ray* disc S3D content using HDMI (1.4a spec compliant with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
• Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 8, Windows* 7, OSX, Linux* OS support
• DirectX 11, DirectX
¾ Multi Display Support: 3 independent displays
¾ Display Types
• VGA Interface support with 300 MHz DAC Analog monitor support up to QXGA (2048 x 1536)
• LVDS Interface single/dual channel 18/24-bit LVDS through eDP (two lane) to LVDS Realtek RTD2136R(N)
Note: RTD2136R has been EOL'd and is replaced by RTD2136N in a running change.
• Digital Display Ports x3
DDI1 supporting DisplayPort / HDMI / DVI
DDI2 supporting DisplayPort / HDMI / DVI
DDI3 supporting DisplayPort / HDMI / DVI
Express-HLE Page 7
2.4
Audio
¾ Integrated: Intel® HD Audio integrated in PCH QM87/QM86
¾ Audio Codec: Realtek ALC886 on Express-BASE6
2.5
LAN
¾ Integrated: LAN MAC integrated in PCH QM87/HM86
¾ Intel PHY: Intel® Ethernet Controller i217LM
¾ Interface: 10/100/1000 GbE connection
2.6
Multi I/O and Storage
¾ Integrated in Intel® QM87/HM86 Chipset
¾ USB ports: 4 ports USB 3.0 (USB0,1 ,2 ,3) and 4 ports USB 2.0 (USB4, 5, 6, 7) – QM87
2 ports USB 3.0 (USB0, 1) and 6 ports USB 2.0 (USB3, 4, 5, 6, 7) – HM86
¾ SATA ports: 4 ports SATA 6Gb/s (SATA0, 1, 2, 3) – QM87
2 ports SATA 6Gb/s (SATA0, 1) and 2 ports SATA 3Gb/s (SATA2, 3) – HM86
¾ Serial: 2 UART ports COM1/2 with console redirection
¾ GPIO: 4 GPO and 4 GPI with interrupt
2.7
TPM (Trusted Platform Module)
¾ Chipset: ATMEL AT97SC3204
¾ Type: TPM 1.2
2.8
SEMA Board Controller
¾ Type: ADLINK Smart Embedded Management Agent (SEMA)
¾ Supports:
• Voltage/Current monitoring
• Power sequence debug support
• AT/ATX mode control
• Logistics and Forensic information
• Flat Panel Control
• General Purpose I2C
• Failsafe BIOS (dual BIOS )
• Watchdog Timer and Fan Control
2.9
Debug
¾ 40-pin flat cable connector to be used with DB-40 debug module
• supports: BIOS POSTCODE LED, BMC access, SPI BIOS flashing, Power Testpoints, Debug LEDs
¾ 60-pin XDP header for ICE debug of CPU/Chipset
Page 8 Express-HLE
2.10
Power Specifications
¾ Power Modes: AT and ATX mode (AT mode start controlled by SEMA)
¾ Standard Voltage Input: ATX = 12V±5% / 5Vsb ±5% or AT = 12V ±5%
¾ Wide Voltage Input: ATX = 8.5~20 V / 5Vsb ±5% or AT = 8.5 ~20V
¾ Power Management: ACPI 4.0 compliant, Smart Battery support
¾ Power States: supports C1-C6, S0, S1, S4, S3, S5, S5 ECO mode (Wake on USB S3/S4, WOL S3/S4/S5)
2.11
Operating Temperatures
¾ Standard Operating Temperature: 0°C to 60°C (wide voltage input)
¾ Extreme Rugged Operating Temperature: -40°C to 85°C (standard voltage input)
2.12
Environmental
¾ Humidity: 5-90% RH operating, non-condensing
5-95% RH storage (and operating with conformal coating).
¾ Shock and Vibration: IEC 60068-2-64 and IEC-60068-2-27
Method
¾ Halt: Thermal Stress, Vibration Stress, Thermal Shock and Combined Test
2.13
Specification Compliance
¾ PICMG COM.0: Rev 2.1 Type 6, basic size 125 x 95
2.14
Operating Systems
¾ Standard Support: Windows 7/8 32/64-bit, Linux 32/64-bit
¾ Extended Support (BSP): WEC7/8, Linux , VxWorks
Express-HLE Page 9
2.15 Function Diagram
1333/1600 MHz
1~8 GB DDR3L
1333/1600 MHz
1~8 GB DDR3L single / dual
18/24-bit LVDS RTD2136R(N) eDP
2 lane
“Haswell”
60-pin
DDI 1 (port B)
DP / HDMI / DVI / SDVO
DDI 2 (port C)
DP / HDMI / DVI
DDI 3 (port D)
DP / HDMI / DVI
PCI Express x16 (Gen3)
2 x8 or 1 x8 + 2 x4
VGA
6x PCIe x1 (Gen2)
(port 0~5) i217LM
PCIe x1
(port 7)
4x SATA3 (QM87)
2x SATA3 & 2x SATA2 (HM86)
8x USB 1.1/2.0
HD Audio
UART0
UART1
NCT5104D
ATMEL
AT97SC3204
Debug header LPC bus
4x GP0
4x GPI
PCA9535
SMBus
GP I 2 C
DDC I 2 C
SPI_CS#
SPI
Mobile Intel®
QM87/HM86
Chipset
SPI_CS0
SPI_CS1
4x USB 3.0 upgrade (QM87)
2x USB 3.0 upgrade (HM86)
1x PCIe x1 (Gen2)
(port 6)
-40+85°C
Page 10 Express-HLE
2.16
Mechanical Drawing
Express-HLE Page 11
3
Pinouts and Signal Descriptions
Row A
Name Pin
GND (FIXED)
GBE0_MDI3-
B1
B2
GBE0_MDI3+ B3
GBE0_LINK100# B4
GBE0_LINK1000# B5
GBE0_MDI2- B6
GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1-
GBE0_MDI1+
GND (FIXED)
GBE0_MDI0-
GBE0_MDI0+
GBE0_CTREF
SUS_S3#
SATA0_TX+
SATA0_TX-
SUS_S4#
SATA0_RX+
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
SATA0_RX-
GND (FIXED)
SATA2_TX+
SATA2_TX-
SUS_S5#
SATA2_RX+
SATA2_RX-
BATLOW#
(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
AC/HDA_BITCLK B32
AC/HDA_SDOUT B33
BIOS_DIS0# B34
THRMTRIP# B35
Pin
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A1
A2
A3
A4
A5
A6
A7
A29
A30
A31
A32
A33
A34
A21
A22
A23
A24
A25
A26
A27
A28
A35
3.1
AB / CD Pin Definitions
The Express-HLE is a Type 6 module supporting USB3.0 and DDI channels on the CD connector
All pins in the COM Express specification are described, including those not supported on the Express-HLE. Those not supported on the
Express-HLE module are crossed out
Row B
Name Pin
GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TX-
SUS_STAT#
SATA1_RX+
SATA1_RX-
GND (FIXED)
SATA3_TX+
SATA3_TX-
PWR_OK
SATA3_RX+
SATA3_RX-
WDT
C20
C21
C22
C23
C24
C25
C26
C27
AC/HDA_SDIN2 C28
AC/HDA_SDIN1 C29
AC/HDA_SDIN0 C30
GND (FIXED)
SPKR
I2C_CK
I2C_DAT
THRM#
C16
C17
C18
C19
C31
C32
C33
C34
C35
C8
C9
C10
C11
C12
C13
C14
C15
C1
C2
C3
C4
C5
C6
C7
Pin
D29
D30
D31
D32
D33
D34
D21
D22
D23
D24
D25
D26
D27
D28
D35
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D1
D2
D3
D4
D5
D6
D7
Row C
Name
GND FIXED)
GND
USB_SSRX0-
USB_SSRX0+
GND
USB_SSRX1-
USB_SSRX1+
GND
USB_SSRX2- *
USB_SSRX2+ *
GND (FIXED)
USB_SSRX3- *
USB_SSRX3+ *
GND
DDI1_PAIR6+
DDI1_PAIR6-
RSVD
RSVD
PCIE_RX6+
PCIE_RX6-
GND (FIXED)
PCIE_RX7+
PCIE_RX7-
DDI1_HPD
DDI1_PAIR4+
DDI1_PAIR4-
RSVD
RSVD
DDI1_PAIR5+
DDI1_PAIR5-
GND (FIXED)
DDI2_CTRLCLK_AUX+
DDI2_CTRLDATA_AUX-
DDI2_DDC_AUX_SEL
RSVD
Row D
Name
GND FIXED)
GND
USB_SSTX0-
USB_SSTX0+
GND
USB_SSTX1-
USB_SSTX1+
GND
USB_SSTX2- *
USB_SSTX2+ *
GND (FIXED)
USB_SSTX3- *
USB_SSTX3+ *
GND
DDI1_CTRLCLK_AUX+
DDI1_CTRLDATA_AUX
RSVD
RSVD
PCIE_TX6+
PCIE_TX6-
GND (FIXED)
PCIE_TX7+
PCIE_TX7-
RSVD
RSVD
DDI1_PAIR0+
DDI1_PAIR0-
RSVD
DDI1_PAIR1+
DDI1_PAIR1-
GND (FIXED)
DDI1_PAIR2+
DDI1_PAIR2-
DDI1_DDC_AUX_SEL
RSVD
Page 12 Express-HLE
Row A
Pin Name
A36 USB6-
A37 USB6+
A38 USB_6_7_OC#
A39 USB4-
A40 USB4+
A41 GND (FIXED)
A42 USB2-
A43 USB2+
A44 USB_2_3_OC#
A45 USB0-
A46 USB0+
A47 VCC_RTC
A48 EXCD0_PERST#
A49 EXCD0_CPPE#
A50 LPC_SERIRQ
A51 GND (FIXED)
A52 PCIE_TX5+
A53 PCIE_TX5-
A54 GPI0
A55 PCIE_TX4+
A56 PCIE_TX4-
A57 GND
A58 PCIE_TX3+
A59 PCIE_TX3-
A60 GND (FIXED)
A61 PCIE_TX2+
A62 PCIE_TX2-
A63 GPI1
A64 PCIE_TX1+
A65 PCIE_TX1-
A66 GND
A67 GPI2
A68 PCIE_TX0+
A69 PCIE_TX0-
A70 GND (FIXED)
A71 LVDS_A0+
A72 LVDS_A0-
A73 LVDS_A1+
A74 LVDS_A1-
A75 LVDS_A2+
A76 LVDS_A2-
A77 LVDS_VDD_EN
A78 LVDS_A3+
A79 LVDS_A3-
A80 GND (FIXED)
Pin
B65
B66
B67
B68
B69
B70
B57
B58
B59
B60
B61
B62
B63
B64
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B51
B52
B53
B54
B55
B56
B43
B44
B45
B46
B47
B48
B49
B50
B36
B37
B38
B39
B40
B41
B42
Row B
Name Pin
USB7-
USB7+
USB_4_5_OC#
USB5-
C36
C37
C38
C39
USB5+
GND (FIXED)
C40
C41
USB3-
USB3+
USB_0_1_OC#
USB1-
USB1+
C42
C43
C44
C45
C46
EXCD1_PERST# C47
EXCD1_CPPE#
SYS_RESET#
CB_RESET#
GND (FIXED)
PCIE_RX5+
PCIE_RX5-
GPO1
PCIE_RX4+
PCIE_RX4-
GPO2
PCIE_RX3+
PCIE_RX3-
GND (FIXED)
PCIE_RX2+
PCIE_RX2-
GPO3
PCIE_RX1+
PCIE_RX1-
WAKE0#
WAKE1#
PCIE_RX0+
C65
C66
C67
C68
PCIE_RX0-
GND (FIXED)
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
LVDS_BKLT_EN C79
GND (FIXED) C80
C57
C58
C59
C60
C61
C62
C63
C64
C48
C49
C50
C51
C52
C53
C54
C55
C56
Row C
Name
DDI3_CTRLCLK_AUX+
DDI3_CTRLDATA_AUX-
DDI3_DDC_AUX_SEL
DDI3_PAIR0+
DDI3_PAIR0-
GND (FIXED)
DDI3_PAIR1+
DDI3_PAIR1-
DDI3_HPD
RSVD
DDI3_PAIR2+
DDI3_PAIR2-
RSVD
DDI3_PAIR3+
DDI3_PAIR3-
GND (FIXED)
PEG_RX0+
PEG_RX0-
TYPE0#
PEG_RX1+
PEG_RX1-
TYPE1#
PEG_RX2+
PEG_RX2-
GND (FIXED)
PEG_RX3+
PEG_RX3-
RSVD
RSVD
PEG_RX4+
PEG_RX4-
RSVD
PEG_RX5+
PEG_RX5-
GND (FIXED)
PEG_RX6+
PEG_RX6-
GND
PEG_RX7+
PEG_RX7-
GND
RSVD
PEG_RX8+
PEG_RX8-
GND (FIXED)
Pin
D65
D66
D67
D68
D69
D70
D57
D58
D59
D60
D61
D62
D63
D64
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D51
D52
D53
D54
D55
D56
D43
D44
D45
D46
D47
D48
D49
D50
D36
D37
D38
D39
D40
D41
D42
Row D
Name
PEG_TX1+
PEG_TX1-
TYPE2#
PEG_TX2+
PEG_TX2-
GND (FIXED)
PEG_TX3+
PEG_TX3-
RSVD
RSVD
PEG_TX4+
PEG_TX4-
GND
PEG_TX5+
PEG_TX5-
GND (FIXED)
PEG_TX6+
PEG_TX6-
GND
PEG_TX7+
PEG_TX7-
GND
RSVD
PEG_TX8+
PEG_TX8-
GND (FIXED)
DDI1_PAIR3+
DDI1_PAIR3-
RSVD
DDI2_PAIR0+
DDI2_PAIR0-
GND (FIXED)
DDI2_PAIR1+
DDI2_PAIR1-
DDI2_HPD
RSVD
DDI2_PAIR2+
DDI2_PAIR2-
RSVD
DDI2_PAIR3+
DDI2_PAIR3-
GND (FIXED)
PEG_TX0+
PEG_TX0-
PEG_LANE_RV#
Express-HLE Page 13
Row A
Pin Name
Row B
Pin Name Pin
Row C
Name
A81 LVDS_A_CK+
A82 LVDS_A_CK-
A83 LVDS_I2C_CK
A84 LVDS_I2C_DAT
A85 GPI3
A86 RSVD
A87 RSVD
A88 PCIE0_CK_REF+
A89 PCIE0_CK_REF-
A90 GND (FIXED)
A91 SPI_POWER
A92 SPI_MISO
A93 GPO0
A94 SPI_CLK
A95 SPI_MOSI
A96 TPM_PP
A97 TYPE10#
A98 SER0_TX
A99 SER0_RX
A100 GND (FIXED)
A101 SER1_TX
A102 SER1_RX
A103 LID#
A104 VCC_12V
A105 VCC_12V
A106 VCC_12V
A107 VCC_12V
A108 VCC_12V
B81 LVDS_B_CK+
B82 LVDS_B_CK-
C81
C82
B83 LVDS_BKLT_CTRL C83
B84 VCC_5V_SBY C84
B85 VCC_5V_SBY
B86 VCC_5V_SBY
B87 VCC_5V_SBY
B88 BIOS_DIS1#
C85
C86
C87
B89
B90
B91
VGA_RED
GND (FIXED)
VGA_GRN
B92 VGA_BLU
B93 VGA_HSYNC
C88
C89
C90
C91
C92
C93
B94 VGA_VSYNC
B95 VGA_I2C_CK
B96 VGA_I2C_DAT
B97 SPI_CS#
B98 RSVD
B99 RSVD
B100 GND (FIXED)
B101 FAN_PWMOUT
B102 FAN_TACHIN
B103 SLEEP#
B104 VCC_12V
B105 VCC_12V
B106 VCC_12V
B107 VCC_12V
B108 VCC_12V
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
PEG_RX9+
PEG_RX9-
TPM_PP
GND
PEG_RX10+
PEG_RX10-
GND
PEG_RX11+
PEG_RX11-
GND (FIXED)
PEG_RX12+
PEG_RX12-
GND
PEG_RX13+
PEG_RX13-
GND
RSVD
PEG_RX14+
PEG_RX14-
GND (FIXED)
PEG_RX15+
PEG_RX15-
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
A109 VCC_12V
A110 GND (FIXED)
B109 VCC_12V
B110 GND (FIXED)
C109 VCC_12V
C110 GND (FIXED)
*Note: USB 3.0 upgrade signals for ports 2, 3 are supported by QM87 only.
Pin
Row D
Name
D81
D82
D83
D84
D85
D86
D87
PEG_TX9+
PEG_TX9-
RSVD
GND
PEG_TX10+
PEG_TX10-
GND
PEG_TX11+
D94
D95
D96
D97
D98
D99
D88
D89
D90
D91
D92
D93
PEG_TX11-
GND (FIXED)
PEG_TX12+
PEG_TX12-
GND
PEG_TX13+
PEG_TX13-
GND
RSVD
PEG_TX14+
PEG_TX14-
D100 GND (FIXED)
D101 PEG_TX15+
D102 PEG_TX15-
D103 GND
D104 VCC_12V
D105 VCC_12V
D106 VCC_12V
D107 VCC_12V
D108 VCC_12V
D109 VCC_12V
D110 GND (FIXED)
Page 14 Express-HLE
3.2
Signal Description Terminology
The following terms are used in the COM Express AB/CD Signal Descriptions below.
Input Module
I/O Bi-directional input / output signal
I 3.3V Input 3.3V tolerant
I 5V Input 5V tolerant
O 3.3V Output 3.3V signal level
O 5V Output 5V signal level
I/O 3.3V Bi-directional signal 3.3V tolerant
I/O 5V Bi-directional signal 5V tolerant
I/O 3.3Vsb Input 3.3V tolerant active in standby state
REF Reference voltage output that may be sourced from a module power plane.
PDS Pull-down strap. This is an output pin on the module that is either tied to GND or not connected.
The signal is used to indicate the PICMG module type to the Carrier Board.
PU ADLINK implemented pull-up resistor on module
PD ADLINK implemented pull-down resistor on module
Express-HLE Page 15
3.3
AB Signal Descriptions
3.3.1
Audio Signals
Signal
AC_RST# /
HDA_RST#
AC_SYNC /
HDA_SYNC
AC_BITCLK /
HDA_BITCLK
AC _SDOUT /
HDA_SDOUT
AC _SDIN[2:0]
HDA_SDIN[2:0]
Pin #
A30
A29
A32
A33
B28
B30
Description
Reset output to codec, active low.
Sample-synchronization signal to the codec(s).
Serial data clock generated by the external codec(s).
Serial TDM data output to the codec.
Serial TDM data inputs from up to 3 codecs.
I/O 3.3V
O 3.3V
I/O 3.3V
3.3.2
Analog VGA
Signal
VGA_RED
VGA_GRN
Pin # Description
B89 Red for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
B91 Green for monitor
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
I/O
O Analog
O Analog
VGA_BLU B92 Blue for monitor.
Analog DAC output, designed to drive a
37.5-Ohm equivalent load.
B93 Horizontal sync output to VGA monitor
O Analog
VGA_HSYNC O 3.3V
VGA_VSYNC
VGA_I2C_CK
B94 Vertical sync output to VGA monitor O 3.3V
B95 DDC clock line (I²C port dedicated to identify
VGA monitor capabilities)
I/O OD 3.3V
VGA_I2C_DAT B96 DDC data line. I/O OD 3.3V
I/O
O 3.3VSB
PU/PD Comment
VSB because PCH uses suspend power for RESET
O 3.3V
PU/PD
PD 150R
PD 150R
Comment
Shall also be terminated on the carrier with 150 Ω resistor to ground close to VGA connector
Shall also be terminated on the carrier with 150 Ω resistor to ground close to VGA connector
PD 150R
PU 2k2 3.3V
Shall also be terminated on the carrier with 150 Ω resistor to ground close to VGA connector
PU 2k2 3.3V
Page 16 Express-HLE
3.3.3
LVDS
Signal
LVDS_A0+
LVDS_A0-
LVDS_A1+
LVDS_A1-
LVDS_A2+
LVDS_A2-
LVDS_A3+
LVDS_A3-
LVDS_A_CK+
LVDS_A_CK-
LVDS_B0+
LVDS_B0-
LVDS_B1+
LVDS_B1-
LVDS_B2+
LVDS_B2-
LVDS_B3+
LVDS_B3-
LVDS_B_CK+
LVDS_B_CK-
LVDS_VDD_EN
LVDS_BKLT_EN
LVDS_BKLT_CTRL
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
Pin # Description
A71
A72
A73
A74
A75
A76
A78
A79
LVDS Channel A differential pairs
LVDS Channel A differential clock
LVDS Channel B differential pairs
LVDS Channel B differential clock
A77 LVDS panel power enable
B79 LVDS panel backlight enable
B83 LVDS panel backlight brightness control
I/O
O LVDS
PU/PD
O LVDS
O LVDS
O LVDS
Comment
O 3.3V
O 3.3V
O 3.3V PD 100K
LVDS_I2C_CK
LVDS_I2C_DAT
A83 DDC lines used for flat panel detection and control. O 3.3V PU 2k2 3.3V
A84 DDC lines used for flat panel detection and control. I/O 3.3V PU 2k2 3.3V
3.3.4
Gigabit Ethernet
Gigabit Ethernet Pin # Description
GBE0_MDI0+
GBE0_MDI0-
GBE0_MDI1+
GBE0_MDI1-
GBE0_MDI2+
GBE0_MDI2-
GBE0_MDI3+
GBE0_MDI3-
GBE0_ACT#
A13
A12
A10
A9
A7
A6
A3
A2
B2
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs
0, 1, 2, 3. The MDI can operate in 1000, 100, and 10Mbit/sec modes.
Some pairs are unused in some modes according to the following:
MDI[0]+/- B1_DA+/-
MDI[1]+/- B1_DB+/-
MDI[2]+/- B1_DC+/-
MDI[3]+/- B1_DD+/-
TX+/- TX+/-
RX+/- RX+/-
Gigabit Ethernet Controller 0 activity indicator, active low.
I/O
I/O Analog
O 3.3VSB
PU/PD
PU 10k
3.3VSB
GBE0_LINK# A8
GBE0_LINK100# A4
Gigabit Ethernet Controller 0 link indicator, active low.
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
O 3.3VSB
O 3.3VSB
GBE0_LINK1000# A5
GBE0_CTREF A14
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.
Reference voltage for Carrier Board Ethernet channel 1 and 2 magnetics center tap. The reference voltage is determined by the requirements of the
Module PHY and may be as low as 0V and as high as 3.3V. The reference voltage output shall be current limited on the Module. In the case in which the reference is shorted to ground, the current shall be 250 mA or less.
O 3.3VSB
GND min
3.3V max
Realtek ePD to LVDS requirement
Comment
Twisted pair signals for external transformer.
Express-HLE Page 17
3.3.5
Serial ATA
Signal
SATA0_TX+
SATA0_TX-
SATA0_RX+
SATA0_RX-
SATA1_TX+
SATA1_TX-
SATA1_RX+
SATA1_RX-
SATA2_TX+
SATA2_TX-
SATA2_RX+
SATA2_RX-
SATA3_TX+
SATA3_TX-
Pin # Description
A16
A17
A19
A20
B16
B17
B19
B20
A22
A23
A25
A26
B22
B23
Serial ATA channel 0, Transmit Output differential pair.
Serial ATA channel 0, Receive Input differential pair.
Serial ATA channel 1, Transmit Output differential pair.
Serial ATA channel 1, Receive Input differential pair.
Serial ATA channel 2, Transmit Output differential pair.
Serial ATA channel 2, Receive Input differential pair.
Serial ATA channel 3, Transmit Output differential pair.
SATA3_RX+
SATA3_RX-
B25
B26
Serial ATA channel 3, Receive Input differential pair.
(S)ATA_ACT# A28 ATA (parallel and serial) or SAS activity indicator, active low.
I/O
O SATA
PU/PD
I SATA
O SATA
I SATA
O SATA
I SATA
O SATA
I SATA
O 3.3V
Comment
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
Page 18 Express-HLE
3.3.6
PCI Express
Signal
PCIE_TX0+
PCIE_TX0-
PCIE_RX0+
PCIE_RX0-
PCIE_TX1+
PCIE_TX1-
PCIE_RX1+
PCIE_RX1-
PCIE_TX2+
PCIE_TX2-
PCIE_RX2+
PCIE_RX2-
PCIE_TX3+
PCIE_TX3-
PCIE_RX3+
PCIE_RX3-
PCIE_TX4+
PCIE_TX4-
PCIE_RX4+
PCIE_RX4-
PCIE_TX5+
PCIE_TX5-
PCIE_RX5+
PCIE_RX5-
PCIE_CLK_REF+
PCIE_CLK_REF-
3.3.7
Express Card
Pin #
A68
A69
A55
A56
B55
B56
A52
A53
B52
B53
A88
A89
A61
A62
B61
B62
A58
A59
B58
B59
B68
B69
A64
A65
B64
B65
Description I/O
PCI Express channel 0, Transmit Output differential pair.
O PCIE
PCI Express channel 0, Receive Input differential pair.
PCI Express channel 1, Transmit Output differential pair.
PCI Express channel 1, Receive Input differential pair.
I PCIE
O PCIE
I PCIE
PCI Express channel 2, Transmit Output differential pair.
O PCIE
PCI Express channel 2, Receive Input differential pair.
PCI Express channel 3, Transmit Output differential pair.
I PCIE
O PCIE
PCI Express channel 3, Receive Input differential pair.
PCI Express channel 4, Transmit Output differential pair.
I PCIE
O PCIE
PCI Express channel 4, Receive Input differential pair.
PCI Express channel 5, Transmit Output differential pair.
I PCIE
O PCIE
I PCIE PCI Express channel 5, Receive Input differential pair.
PCI Express Reference Clock output for all PCI
Express and PCI Express Graphics Lanes.
O PCIE
Signal
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
Pin # Description
A49
B48
PCI ExpressCard: PCI Express capable card request
A48
B47
PCI ExpressCard: reset
I/O
I 3.3V
O 3.3V
PU/PD Comment
AC coupled on Module
AC coupled off Module
AC coupled on Module
AC coupled off Module
AC coupled on Module
AC coupled off Module
AC coupled on Module
AC coupled off Module
AC coupled on Module
AC coupled off Module
AC coupled on Module
AC coupled off Module
PU/PD
PU 10k 3.3V
Comment
3.3.8
LPC Bus
Signal
LPC_AD[0:3]
LPC_FRAME#
LPC_DRQ0#
LPC_DRQ1#
LPC_SERIRQ
LPC_CLK
B3
B8
B9
A50
Pin # Description
B4-B7 LPC multiplexed address, command and data bus
LPC frame indicates the start of an LPC cycle
LPC serial DMA request
B10
LPC serial interrupt
LPC clock output - 33MHz nominal
I/O
I/O 3.3V
O 3.3V
I 3.3V
PU/PD
I/O OD 3.3V PU 8k2 3.3V
O 3.3V
Comment
Express-HLE Page 19
3.3.9
USB
USB3+
USB3-
USB4+
USB4-
USB5+
USB5-
USB6+
USB6-
Signal
USB0+
USB0-
USB1+
USB1-
USB2+
USB2-
B43
B42
A40
A39
B40
B39
A37
A36
Pin # Description
A46
A45
USB differential data pairs for Port 0
USB differential data pairs for Port 1 B46
B45
A43
A42
USB differential data pairs for Port 1
USB differential data pairs for Port 2
USB differential data pairs for Port 3
USB differential data pairs for Port 4
USB differential data pairs for Port 5
USB7+
USB7-
B37
B37
USB differential data pairs for Port 6
USB_0_1_OC# B44 USB over-current sense, USB ports 0 and 1. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.
USB_2_3_OC# A44 USB over-current sense, USB ports 2 and 3. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low. .
USB_4_5_OC# B38 USB over-current sense, USB ports 4 and 5. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.
USB_6_7_OC# A38 USB over-current sense, USB ports 6 and 7. A pull-up for this line shall be present on the module. An open drain driver from a USB current monitor on the carrier board may drive this line low.
I/O
I/O 3.3VSB
PU/PD
I/O 3.3VSB
I/O 3.3VSB
I/O 3.3VSB
I/O 3.3VSB
I/O 3.3VSB
I/O 3.3VSB
I/O 3.3VSB
Comment
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
USB 1.1/ 2.0 compliant
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
I 3.3VSB PU 10k 3.3VSB Do not pull high on carrier
Page 20 Express-HLE
3.3.10
USB Root Segmentation
Express-HLE Page 21
3.3.11
SPI (BIOS only)
Signal
SPI_CS#
Pin # Description
B97 Chip select for Carrier Board SPI BIOS Flash.
I/O
O 3.3VSB
PU/PD
SPI_MISO
SPI_MOSI
A92 Data in to module from carrier board SPI BIOS flash.
A95 Data out from module to carrier board SPI BIOS flash.
I 3.3VSB
O 3.3VSB
SPI_CLK A94 Clock from module to carrier board SPI BIOS flash.
SPI_POWER A91 Power supply for Carrier Board SPI – sourced from Module
– nominally 3.3V.
The Module shall provide a minimum of 100mA on
SPI_POWER.
Carriers shall use less than 100mA of SPI_POWER.
SPI_POWER shall only be used to power SPI devices on the Carrier
O 3.3VSB
O P 3.3VSB
BIOS_DIS0# A34 Selection strap to determine the BIOS boot device. I PU 10K 3.3V
BIOS_DIS1# B88 Selection strap to determine the BIOS boot device. I
Comment
PU 10K 3.3V
Carrier shall pull to GND or leave no- connect.
Carrier shall pull to GND or leave no- connect
3.3.12
Miscellaneous
Signal
SPKR
Pin # Description
B32 Output for audio enunciator, the “speaker” in PC-AT systems
I/O
O 3.3V
PU/PD
WDT
THRM#
B27 Output indicating that a watchdog time-out event has occurred.
O 3.3V
B35 Input from off-module temp sensor indicating an over-temp situation.
I 3.3V
O 3.3V THERMTRIP#
FAN_PWMOUT
A35 Active low output indicating that the CPU has entered thermal shutdown.
B101 Fan speed control. Uses the Pulse Width Modulation
(PWM) technique to control the fan’s RPM.
FAN_TACHIN11 B102 Fan tachometer input for a fan with a two pulse output.
O OD 3.3V
I OD 3.3V
PU 330 3.3V
PU 10k 3.3V
TPM_PP11 C83 Trusted Platform Module (TPM) Physical Presence pin.
Active high. TPM chip has an internal pull down. This signal is used to indicate Physical Presence to the TPM.
I 3.3V PD 10k 3.3V
3.3.13
SMBus
Signal
SMB_CK
Pin # Description I/O PU/PD
B13 System Management Bus bidirectional clock line. Power sourced through 5V standby rail and main power rails.
I/O OD 3.3VSB PU 2k2 3.3VSB
I/O OD 3.3VSB PU 2k2 3.3VSB
Comment
SMB_DAT# B14 System Management Bus bidirectional data line. Power sourced through 5V standby rail and main power rails.
SMB_ALERT# B15 System Management Bus Alert – active low input can be used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced through 5V standby rail and main power rails.
I 3.3VSB PU 10k 3.3VSB
Comment
PD is only placed when TPM is installed on module
Page 22 Express-HLE
3.3.14
I2C Bus
Signal
I2C_CK
I2C_DAT
Pin # Description
B33 General purpose I²C port clock output/input
B34 General purpose I²C port data I/O line
3.3.15
General Purpose I/O (GPIO)
Signal Pin # Description
GPO[0] A93 General purpose output pins.
GPO[1] B54 General purpose output pins.
GPO[2] B57 General purpose output pins.
GPO[3] B63 General purpose output pins.
GPI[0]
GPI[1]
GPI[2]
GPI[3]
A54 General purpose input pins.
Pulled high internally on the module.
A63 General purpose input pins.
Pulled high internally on the module.
A67 General purpose input pins.
Pulled high internally on the module.
A85 General purpose input pins.
Pulled high internally on the module.
3.3.16
Serial Interface Signals
Signal Pin # Description
SER0_TX A98 General purpose serial port transmitter (TTL level output)
SER0_RX A99 General purpose serial port receiver (TTL level input)
SER1_TX A101 General purpose serial port transmitter (TTL level output)
SER1_RX A102 General purpose serial port receiver (TTL level input)
I/O PU/PD
I/O OD 3.3VSB PU 2k2 3.3VSB
Comment
I/O OD 3.3VSB PU 2k2 3.3VSB
O 3.3V
I 3.3V
I 3.3V
I 3.3V
I 3.3V
I/O
O 3.3V
O 3.3V
O 3.3V
I/O
O CMOS
I CMOS
O CMOS
I CMOS
PU/PD
PU 10K 3.3V
PU 10K 3.3V
PU 10K 3.3V
PU 10K 3.3V
Comment
After hardware RESET output low
After hardware RESET output low
After hardware RESET output low
After hardware RESET output low
PU/PD Comment
Power rail tolerance 5V / 12V
Power rail tolerance 5V / 12V
Power rail tolerance 5V / 12V
Power rail tolerance 5V / 12V
Express-HLE Page 23
3.3.17
Power And System Management
Signal
PWRBTN#
SUS_STAT#
SUS_S3#
Pin # Description
B12
B18
Power button to bring system out of S5 (soft off), active on falling edge.
SYS_RESET# B49 Reset button input. Active low request for module to reset and reboot. May be falling edge sensitive. For situations when SYS_RESET# is not able to reestablish control of the system, PWR_OK or a power cycle may be used.
CB_RESET#
PWR_OK
B50 Reset output from module to Carrier Board. Active low. Issued by module chipset and may result from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below the minimum specification, a watchdog timeout, or may be initiated by the module software.
B24 Power OK from main power supply. A high value indicates that the power is good. This signal can be used to hold off Module startup to allow carrier based FPGAs or other configurable devices time to be programmed.
Indicates imminent suspend operation; used to notify LPC devices.
A15 Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3# on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on a typical ATX power supply.
I/O
I 3.3VSB
I 3.3VSB
O 3.3VSB
I 3.3V
O 3.3VSB
O 3.3VSB
O 3.3VSB
PU/PD
PU 10k
3.3VSB
PU 10k
3.3VSB
PU 100k
3.3VSB
SUS_S5#
WAKE0#
WAKE1#
BATLOW#
LID#
SLEEP#
A24 Indicates system is in Soft Off state.
B66 PCI Express wake up signal.
B67
A27
General purpose wake up signal. May be used to implement wake-up on
PS/2 keyboard or mouse activity.
Battery low input. This signal may be driven low by external circuitry to signal that the system battery is low, or may be used to signal some other external power-management event.
LID button. Low active signal used by the ACPI operating system for a LID switch.
Sleep button. Low active signal used by the ACPI operating system to bring the system to sleep state or to wake it up again.
O 3.3VSB
I 3.3VSB PU 10k
3.3VSB
I 3.3VSB
I 3.3VSB
PU 10k
3.3VSB
PU 10k
3.3VSB
I OD
3.3VSB
I OD
3.3VSB
PU 10k
3.3VSB
PU 10K
3.3VSB
3.3.18
Power and Ground
Comment
Should have weak pull up
Signal Pin #
VCC_12V A104-A109
B104-B109
VCC_5V_SBY B84-B87
VCC_RTC A47
Description
Primary power input: +12V nominal (8.5 ~ 20V wide input).
All available VCC_12V pins on the connector(s) shall be used.
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY pins on the connector(s) shall be used.
Only used for standby and suspend functions. May be left unconnected if these functions are not used in the system design.
Real-time clock circuit-power input. Nominally +3.0V.
GND A1, A11, A21, A31,
A41, A51, A57, A66,
A80, A90, A96,
A100, A110, B1,
B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110
Ground - DC power and signal and AC signal return path.
I/O PU/PD Comment
P 8.5~20
P 5Vsb
P
P
Page 24 Express-HLE
3.4
CD Signal Descriptions
3.4.1
USB 3.0 extension
Signal
USB_SSRX0-
USB_SSRX0+
USB_SSTX0-
USB_SSTX0+
USB_SSRX1-
USB_SSRX1+
USB_SSTX1-
USB_SSTX1+
USB_SSRX2-
USB_SSRX2+
USB_SSTX2-
USB_SSTX2+
USB_SSRX3-
USB_SSRX3+
USB_SSTX3-
USB_SSTX3+
D6
D7
C9
C10
D9
D10
C12
C13
D12
D13
D3
D4
C6
C7
Pin
C3
C4
Description
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB0
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB0
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB1
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB1
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB2
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB2
Additional Receive signal differential pairs for the
SuperSpeed USB data path on USB3
Additional Transmit signal differential pairs for the
SuperSpeed USB data path on USB3
3.4.2
PCI Express x1
Signal
PCIE_TX6+
PCIE_TX6-
PCIE_RX6+
PCIE_RX6-
PCIE_TX7+
PCIE_TX7-
PCIE_RX7+
PCIE_RX7-
Pin # Description
D19
D20
PCI Express channel 6, Transmit Output differential pair.
C19
C20
D22
D23
C22
C23
PCI Express channel 6, Receive Input differential pair.
PCI Express channel 7, Transmit Output differential pair.
PCI Express channel 7, Receive Input differential pair.
I/O
I PCIE
O PCIE
I PCIE
PU/PD
O PCIE
I PCIE
O PCIE
I PCIE
O PCIE
Comment
AC coupled on Module
AC coupled on Module
AC coupled on Module
AC coupled on Module
I/O
O PCIE
PU/PD Comment
AC coupled on Module
I PCIE
O PCIE
I PCIE
AC coupled off Module
Not available used by LAN
Not available used by LAN
Express-HLE Page 25
3.4.3
DDI Channels
DDI 1
Signal
DDI1_PAIR0+
DDI1_PAIR0-
DDI1_PAIR1+
DDI1_PAIR1-
DDI1_PAIR2+
DDI1_PAIR2-
DDI1_PAIR3+
DDI1_PAIR3-
DDI1_PAIR4+
DDI1_PAIR4-
DDI1_PAIR5+
DDI1_PAIR5-
DDI1_PAIR6+
DDI1_PAIR6-
DDI1_HPD
Pin
D37
C25
C26
C29
C30
C15
C16
D26
D27
D29
D30
D32
D33
D36
Description
Digital Display Interface1 differential pairs
C24 Digital Display Interface Hot-Plug Detect
I/O
O PCIE
PU/PD Comment
Pair 4 to Pair 6
Not supported
IF DDI1_DDC_AUX_SEL pulled high
IF DDI1_DDC_AUX_SEL pulled high
Selects and DDI1_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the
Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and
CTRLDATA signals.
I PCIE
I/O PCIe
I/O OD 3.3V
DP1_AUX+
HDMI1_CTRLCLK
I/O PCIe
I/O OD 3.3V
I/O OD 3.3V PD 1M
DP1_AUX+
HDMI1_CTRLDATA
Page 26 Express-HLE
DDI 2
Signal
DDI2_PAIR0+
DDI2_PAIR0-
DDI2_PAIR1+
DDI2_PAIR1-
DDI2_PAIR2+
DDI2_PAIR2-
DDI2_PAIR3+
DDI2_PAIR3-
Pin
D39
D40
D42
D43
D46
D47
D49
D50
Description
Digital Display Interface2 differential pairs
DDI2_HPD D44
DDI2_CTRLCLK_AUX+ C32 IF DDI2_DDC_AUX_SEL is floating
IF DDI2_DDC_AUX_SEL pulled high
DDI2_CTRLCLK_AUX- C33 IF DDI2_DDC_AUX_SEL is floating
IF DDI2_DDC_AUX_SEL pulled high
DDI2_DDC_AUX_SEL C34 Selects the function of DDI2_CTRLCLK_AUX+ and
DDI2_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the
CRTLCLK and CTRLDATA signals.
DDI 3
I/O
I/O PCIe
I/O OD 3.3V
I/O PCIe
I/O OD 3.3V
PU/PD Comment
DP2_AUX+
HDMI2_CTRLCLK
DP2_AUX+
HDMI2_CTRLDATA
Signal
DDI3_PAIR0+
DDI3_PAIR0-
DDI3_PAIR1+
DDI3_PAIR1-
DDI3_PAIR2+
DDI3_PAIR2-
DDI3_PAIR3+
DDI3_PAIR3-
Pin
C39
C40
C42
C43
C46
C47
C49
C50
Description
Digital Display Interface3 differential pairs
DDI3_HPD C44
DDI3_CTRLCLK_AUX+ C36 IF DDI3_DDC_AUX_SEL is floating
IF DDI3_DDC_AUX_SEL pulled high
DDI3_CTRLCLK_AUX- C37 IF DDI3_DDC_AUX_SEL is floating
IF DDI3_DDC_AUX_SEL pulled high
DDI3_DDC_AUX_SEL C38 Selects function of DDI3_CTRLCLK_AUX+ and DDI3_CTRLDATA_AUX-. This pin shall have a 1M pull-down to logic ground on the
Module. If this input is floating the AUX pair is used for the DP AUX+/- signals. If pulled-high the AUX pair contains the CRTLCLK and
CTRLDATA signals.
I/O
I/O PCIe
I/O OD 3.3V
I/O PCIe
I/O OD 3.3V
PU/PD Comment
DP3_AUX+
HDMI3_CTRLCLK
DP3_AUX+
HDMI3_CTRLDATA
Express-HLE Page 27
3.4.4
DDI to DP/HDMI Mapping
Pin Name DP
C39
C40
C42
C43
C46
C47
C49
C50
C44
C36
C37
C38
D47
D49
D50
D44
C32
C33
C34
D39
D40
D42
D43
D46
Pin
C15
C16
C24
D15
C25
C26
C29
C30
D16
D34
D32
D33
D36
D37
D26
D27
D29
D30
DDI1_PAIR4+
DDI1_PAIR4-
DDI1_PAIR5+
DDI1_PAIR5-
DDI1_PAIR6+
DDI1_PAIR6-
DDI1_DDC_AUX_SEL
DDI2_DDC_AUX_SEL
DDI3_DDC_AUX_SEL
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
HDMI / DVI
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Page 28 Express-HLE
3.4.5
PCI Express Graphics x16 (PEG)
Signal
PEG_RX8+
PEG_RX8-
PEG_RX9+
PEG_RX9-
PEG_RX10+
PEG_RX10-
PEG_RX11+
PEG_RX11-
PEG_RX12+
PEG_RX12-
PEG_RX13+
PEG_RX13-
PEG_RX14+
PEG_RX14-
PEG_RX15+
PEG_RX15
PEG_RX0+
PEG_RX0-
PEG_RX1+
PEG_RX1-
PEG_RX2+
PEG_RX2-
PEG_RX3+
PEG_RX3-
PEG_RX4+
PEG_RX4-
PEG_RX5+
PEG_RX5-
PEG_RX6+
PEG_RX6-
PEG_RX7+
PEG_RX7-
PEG_TX0+
PEG_TX0-
PEG_TX1+
PEG_TX1-
PEG_TX2+
PEG_TX2-
PEG_TX3+
PEG_TX3-
PEG_TX4+
PEG_TX4-
PEG_TX5+
PEG_TX5-
PEG_TX6+
PEG_TX6-
PEG_TX7+
PEG_TX7-
PEG_TX8+
PEG_TX8-
PEG_TX9+
PEG_TX9-
PEG_TX10+
PEG_TX10-
PEG_TX11+
PEG_TX11-
PEG_TX12+
PEG_TX12-
PEG_TX13+
PEG_TX13-
PEG_TX14+
PEG_TX14-
Description
PCI Express Graphics transmit differential pairs.
PCI Express Graphics receive differential pairs.
Pin
C86
C88
C89
C91
C92
C94
C95
C98
C99
C101
C102
C62
C65
C66
C68
C69
C71
C72
C74
C75
C78
C79
C81
C82
C85
C52
C53
C55
C56
C58
C59
C61
D91
D92
D94
D95
D98
D99
D78
D79
D81
D82
D85
D86
D88
D89
D65
D66
D68
D69
D71
D72
D74
D75
D52
D53
D55
D56
D58
D57
D61
D62
Express-HLE
I/O
I PCIE
PU/PD Comment
AC coupled off Module
O PCIE AC coupled on Module
Page 29
Signal
PEG_TX15+
PEG_TX15-
PEG_LANE_RV#
Pin
D101
D102
D54
Description I/O PU/PD Comment
PCI Express Graphics lane reversal input strap.
Pull low on the Carrier board to reverse lane order.
I 1.05V
3.4.6
Module Type Definition
Signal
TYPE0#
TYPE1#
TYPE2#
Pin #
C54
C57
D57
Description
The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on the module to either ground (GND) or are noconnects (NC). For Pinout Type 1, these pins are don’t care (X).
I/O Comment
X X Pinout
NC
NC
NC
NC GND GND Pinout Type 5 (no IDE, no PCI)
GND NC NC Pinout Type 6 (no IDE, no PCI)
The Carrier Board should implement combinatorial logic that monitors the module
TYPE pins and keeps power off (e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The Carrier Board logic may also implement a fault indicator such as an LED.
3.4.7
Power and Ground
Signal Pin #
VCC_12V C104-C109
D104-D109
GND
Description
Primary power input: +12V nominal (8.5 ~ 20V wide input).
All available VCC_12V pins on the connector(s) shall be used.
C1, C11, C21, C31, C41,
C51, C60, C70, C76, C80,
C84, C87, C90, C93, C96,
C100, C103, C110, D1,
D11, D21, D31, D41, D51,
D60, D67, D70, D76, D80,
D84, D87, D90, D93, D96,
D100, D103, D110
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to carrier board GND plane.
I/O PU/PD Comment
P 8.5~20
P
Page 30 Express-HLE
4
Connector Pinouts on Module
This chapter describes connectors and pinouts, LEDs and switches that are used on the module but are not included in the PICMG standard specification
¾ Connector and LED Locations
XDP 60-pin to CPU
BIOS
Defaults
RESET
Button
FAN
4-pin
FAN
40-pin
Debug connector
CD
AB
Express-HLE Page 31
4.1
40-pin Debug Connector
¾ FPC Connector type: FCI 59GF Flex 10042867
¾ Pin orientation
¾ Express-HLE and the Debug Module
Page 32 Express-HLE
¾ 40-pin Pin Description on the COM Express Module
Pin Interface Signal
1 SPI
Program interface
VCC_SPI_IN
Remark
SPI Power Input from flash tool to module. HW need add MOS
FET to switch SPI power for SPI
ROM
2 GND
3 SPI_BIOS_CS0#
4 SPI_BIOS_CS1#
5 SPI_BIOS_MISO
6 SPI_BIOS_MOSI
7 SPI_BIOS_CLK
8 LPC Bus 3V3_LPC System power 3.3V provide from
COM module
9 GND
10 BIOS_DIS0
11 RST#
12 CLK33_LPC
13 LPC_FRAME#
14 LPC_AD3
Pin Interface
BMC Program interface
(continued)
Signal
TXD6
Remark
22 RXD6
23 FUMD0
24 RESET_IN#
25 DATA
26 CLK
27 OCD0A Include a jumper to connect
OCD0A via 1K0 pull-up to
3.3V_BMC
28 OCD0B Include a jumper to connect
OCD0A via 1K0 pull-up to
3.3V_BMC
29 PWRBTN#
30 SYS_RESET#
31 CB_RESET#
32 CB_PWROK
33 SUS_S3#
34 SUS_S4#
15 LPC_AD2
16 LPC_AD1 always power 3.3V provide from
COM module
17 LPC_AD0
35
36 BMC Debug signals
37
18
19
BMC
Program interface
3.3V_BMC always power 3.3V provide from
COM module
38
3.3V_BMC always power 3.3V provide from
COM module
39
20 GND
Note: The pin description on the debug module is the inverse of that on the COM Express module.
SUS_S5#
POSTWDT_DIS# Connect to Jumper for
Debug
SEL_BIOS Connect to Jumper for
Debug
BIOS_MODE Connect to Jumper for
Debug
BMC_STATUS
Express-HLE Page 33
4.2
Status LEDs
To facilitate easier maintenance, status LED’s are mounted on the board.
¾ LED Descriptions
Name
LED1
LED2
Color
Blue
Green
LED3 Red
Connection
BMC output
Power Source 3Vcc
Function
Power Sequence Status Code (BMC)
Power Changes, RESET
(see 5.1.4 Exception Codes below)
S0 LED ON
LED
ECO mode LED OFF
BMC and same signal as WDT
(B27) on BtB connector
Module power up WD LED = LED OFF
Watchdog counting WD LED = LED OFF
Watchdog timed out WD LED = LED ON
Watchdog RESET WD LED = LED ON
Rebooted after WD RESET WD LED = LED ON
Rebooted after PWRBTN WD LED = LED ON
Rebooted after RESET BTN WD LED = LED OFF
Note: only a RESET not initiated by the BMC can clear the WD LED (user action)
Page 34 Express-HLE
4.3
XDP Debug header
The debug port is a connection into a target-system environment that provides access to JTAG, run control, system control, and observation resources. The XDP target system connector is a Samtec™ 60-pin BSH-030-01 series connector.
Pin XDP Signal Target Signal
1 GND GND
3 OBSFN_A0 PREQ#
I/O Device Pin XDP Signal Target Signal I/O Device
NA 2 GND GND NA
I/O processor 4 OBSFN_C0 CFG[17] 2 I
5 OBSFN_A1 PRDY#
7 GND GND
I/O processor 6 OBSFN_C1 CFG[16] 2 I
NA 8 GND GND NA
9 OBSDATA_A0 2 I/O 10 CFG[8] 2 I/O
11 OBSDATA_A1 CFG[1] 2 I/O CFG[9] 2 I/O
13 GND GND NA 14 GND GND NA
15 OBSDATA_A2 CFG[2] 2 I/O CFG[10] 2 I/O
17 OBSDATA_A3 CFG[3] 2 I/O CFG[11] 2 I/O
19 GND GND NA 20 GND GND NA
21 OBSFN_B0 BPM#[0] 1 I/O
23 OBSFN_B1 BPM#[1] 1 I/O
OBSFN_D0 2 processor
OBSFN_D1 2 processor
25 GND GND NA 26 GND GND NA
27 OBSDATA_B0 CFG[4] 2 I/O CFG[12] 2 I
29 OBSDATA_B1 CFG[5] 2 I/O CFG[13] 2 I
31 GND GND NA 32 GND GND NA
33 OBSDATA_B2 CFG[6] 2 I/O CFG[14] 2 I/O
35 OBSDATA_B3 CFG[7] 2 I/O CFG[15] 2 I/O
37 GND
39 HOOK0
GND
PWRGOOD
NA 38 GND
I system
GND
40 ITPCLK/HOOK4 Open
41 HOOK11 BP_PWRGD_RST# O system 42 ITPCLK#/HOOK5 Open
43 VCC_OBS_AB VCCIO_OUT I system 44 VCC_OBS_CD VCCIO_OUT
NA
NA
NA
I system
45 HOOK2
47 HOOK3
49 GND
51 SDA1
53 SCL1
55 TCK1
PWR_DEBUG O processor 46 HOOK6/RESET# PLTRSTIN#
PCH_SYS_PWROK O system 48 HOOK7/DBR# DBR#
GND
SDA
SCL
Open
NA
I/O system
I/O system 54 TRSTn
NA
50 GND
52 TDO
56 TDI
GND
TDO
TRST#
TDI
I system
O system
NA
I processor
O processor
O processor
57 TCK0 TCK O processor 58 TMS TMS O processor
59 GND GND NA 60 GND G ND (or XDP_
PRESENT# if required)
NA
Notes:
1.
These signals are optional, can be left as OPEN/No-Connect if debug by Intel will not be needed.
2.
These CFG signals can be left as Open/No Connect if not used as a strapping signal and top side probe will be used to debug processor.
Refer to the "Shark Bay and Denlow Platforms Debug Port Design Guide (DPDG)", Document Number: 479493, Revision: 1.2
Express-HLE Page 35
4.4
Fan Connector
¾ Connector Type: JVE 24W1125A-04M00
¾ Pin Assignment
Name Signal Description
3 GND
4 P5V_S
Ground
5V
4.5
BIOS Setup Defaults RESET Button
To perform a hardware reset of BIOS default settings, perform the following steps:
1.
Shut down the system.
2.
Press the BIOS Setup Defaults RESET Button continuously and boot up the system. You can release the button when the BIOS prompt screen appears
3.
The BIOS prompt screen will display a confirmation that BIOS defaults have been reset and request that you reboot the system.
Page 36 Express-HLE
4.6
Express-HLE Switch Settings
4.6.1
Switch Locations
SW4
SW1
SW3
Express-HLE Page 37
4.6.2
SW1: PCI Express Configuration Switch
Switch SW1 allows you to configure the PCI Express x16 lanes from the CPU as 1 PCIe x16, 2 PCIe x8, or 1 PCIe x8 + 2 PCIe x4.
Mode
1x PCIe x16 (default)
2x PCIe x8
1x PCIe x8 + 2x PCIe x4
Pin 1 Pin 2
Off Off
On
On
Off
On
4.6.3
SW4: LVDS Panel Configuration Switch
Switch SW4 allows you to set the LVDS panel mode to 18-bit or 24-bit.
Mode
18 bit LVDS panel mode (default)
24 bit LVDS panel mode
Pin 2
Off
On
4.6.4
SW3: BIOS Select and Mode Configuration Switch
Module has two BIOS chips and BIOS operation can be configured to "PICMG" and "Failsafe" modes using SW3, Pin 2.
Setting the module to PICMG mode will configure the BIOS chips on the module as SPI0 and SPI1. In PICMG mode, a BIOS chip CANNOT be placed in SPI0 on the carrier.
In dual-BIOS Failsafe mode, both BIOS chips on the module are configured as SPI1. Only one of the two is connected to the SPI bus at any given time. In case of BIOS failure of the primary SPI1 BIOS, the system will reboot and switch to the secondary SPI1 BIOS on the module.
In Failsafe mode, it is allowed to also have an SPI0 BIOS on the carrier.
In both modes, strapping can select whether to boot from SPI0 or SPI1 (SW3 Pin 1).
Mode
Boot from SPI0 (Default)
Boot from SPI1
Set BIOS to PICMG mode
Pin 1 Pin 2
On —
Off
—
—
On
Set BIOS to Failsafe BIOS mode (Default) — Off
Page 38 Express-HLE
4.7
PCIe x16-to-two-x8 Adapter Card
The Express-HLE can be used with the PCIe x16-to-two-x8 Adapter Card on the Express-BASE6 Reference Carrier to support bifurbication of the CPU's PEG interface (PCIe x16). The card reroutes the PCIe x16 to two x8 and allows testing of two independent PCIe add-on cards with x8/x4/x2/x1 width. To use the card, set SW1 to "2 x8 PCI Express" as above.
PCIex16-to-two-x8 Adapter Card
(Model: P16TO28, Part No.: 91-79301-0010)
Express-HLE Page 39
5
Smart Embedded Management Agent (SEMA)
The onboard microcontroller (BMC) implements power sequencing and Smart Embedded Management Agent (SEMA) functionality. The microcontroller communicates via the System Management Bus with the CPU/chipset. The following functions are implemented:
• Total operating hours counter. Counts the number of hours the module has been run in minutes.
• On-time minutes counter. Counts the seconds since last system start.
• Temperature monitoring of CPU and board temperature. Minimum and maximum temperature values of CPU and board are stored in flash.
• Power cycles counter
• Boot counter. Counts the number of boot attempts.
• Watchdog Timer (Type-II). Set / Reset / Disable Watchdog Timer. Features auto-reload at power-up.
• System Restart Cause. Power loss / BIOS Fail / Watchdog / Internal Reset / External Reset
• Fail-safe BIOS support. In case of a boot failure, hardware signals tells external logic to boot from fail-safe BIOS.
• Flash area. 1kB Flash area for customer data
• 128 Bytes Protected Flash area. Keys, IDs, etc. can be stored in a write- and clear-protectable region.
• Board Identify. Vendor / Board / Serial number / Production Date
• Main-current & voltage. Monitors drawn current and main voltages
For a detailed description of SEMA features and functionality, please refer to SEMA Technical Manual and SEMA Software Manual , downloadable at: http://www.adlinktech.com/sema/ .
Page 40 Express-HLE
5.1
Board Specific SEMA Functions
5.1.1
Voltages
The BMC of the Express-HLE implements a voltage monitor and samples several onboard voltages. The voltages can be read by calling the
SEMA function “Get Voltages”. The function returns a 16-bit value divided into high-byte (MSB) and low-byte (LSB).
5
6
3
4
7
1
2
ADC Channel Voltage Name
0 ---
+V3.3S
+V1.05S
+V3.3A
+VDDQ (V1.35 ~ V1.5)
+V5A_DUAL
+VIN
(MAIN CURRENT)
Voltage Formula [V]
---
(MSB<<8 + LSB) x 1.100 x 3.3 / 1024
(MSB<<8 + LSB) x 3.3 / 1024
(MSB<<8 + LSB) x 1.100 x 3.3 / 1024
(MSB<<8 + LSB) x 3.3 / 1024
(MSB<<8 + LSB) x 1.833 x 3.3 / 1024
(MSB<<8 + LSB) x 6.000 x 3.3 / 1024
Use Main Current Function
5.1.2
Main Current
The BMC of the Express-HLE implements a current monitor. The current can be read by calling the SEMA function “Get Main Current”. The function returns four 16-bit values divided in high-byte (MSB) and low-byte (LSB). These 4 values represent the last 4 currents drawn by the board. The values are sampled every 250ms. The order of the 4 values is NOT in chronological order. Access by the BMC may increase the drawn current of the whole system. In this case, there are still 3 samples not influenced by the read access.
Main Current = (MSB_n<<8 + LSB_n) x 8.06mA
5.1.3
BMC Status
This register shows the status of BMC controlled signals on the Express-HL.
Status Bit Signal
0 WDT_OUT
1 LVDS_VDDEN
2 LVDS_BKLTEN
3 BIOS_MODE
4 POSTWDT_DISn
5 SEL_BIOS
6 BIOS_DIS0n
7 BIOS_DIS1n
Express-HLE Page 41
5.1.4
Exception Codes
In case of an error, the BMC drives a blinking code on the blue Status LED (LED1). The same error code is also reported by the BMC Flags register. The Exception Code is not stored in the Flash Storage and is cleared when the power is removed. Therefore, a “Clear Exception
Code” command is not needed or supported.
Exception Code Error Message
0 NOERROR
2 NO_SUSCLK
3 NO_SLP_S5
4 NO_SLP_S4
5 NO_SLP_S3
6 BIOS_FAIL
7 RESET_FAIL
8 POWER_FAIL
9 LOW_VIN
11 +P3V3_S
12 +P1V05_S
13 +P3V3_A
14 +VDDQ
15 +P5V_A
16 +P12V
18 CRITICAL_TEMP
19 NO_CB_PWROK
20 NO_SYS_GD
21 NO_VCORE_GD
22 NO_XDP_PIN47
5.1.5
BMC Flags
The BMC Flags register returns the last detected Exception Code since power-up and shows the BIOS in use and the power mode.
Bit
[ 0 ~ 4 ]
[ 6 ]
[ 7 ]
Description
Exception Code
0 = AT mode
1 = ATX mode
0 = Standard BIOS
1 = Fail-safe BIOS.
Page 42 Express-HLE
4
6
System Resources
6.1
System Memory Map
Address Range (decimal)
(4GB-2MB)
(4GB-18MB) – (4GB-17MB-1)
(4GB-20MB) – (4GB-19MB-1)
15MB – 16MB
1MB -15MB
0K –1MB
Address Range (hex)
FFE00000 – FFFFFFFF
FEE00000 – FEEFFFFF
FEC00000 – FECFFFFF
F00000 – FFFFFF
100000 - EFFFFF
00000 – FFFFFF
Size
2 MB
1 MB
1 MB
1 MB
14MB
1MB
6.2
Direct Memory Access Channels
Channel Number Data Width System Resource
Description
High BIOS Area
MSI Interrupts
APIC Configuration Space
ISA Hole
Main Memory
DOS Compatibility Memory
Reserved - cascade channel
Express-HLE Page 43
6.3
I/O Map
Hex Range
000-01F
020-02D and 030-03F
02E-02F
040-05F
060, 062, 064, 066, 068-06F
061, 063, 065, 067
Device
DMA controller 1, 8237A-5 equivalent
Interrupt controller 1, 8259 equivalent
LPC SIO () configuration index/data registers
Timer, 8254-2 equivalent
8742 equivalent (keyboard)
NMI control and status
070-07F
080-091
092
93-9F
Real Time Clock Controller( bit 7 -NMI mask)
DMA page register
Reset (Bit 0)/ Fast Gate A20 (Bit 1)
DMA page registers continued
0A0-0B1 and 0B4-0BF
0B2 and 0B3
Interrupt controller 2, 8259 equivalent
APM control and status port respectively
0C0-0DF DMA controller 2, 8237A-5 equivalent
0E0-0EF Available
0F0 Co-processor error register
0F1 N/A
0F2-0F3 N/A
0F4 IDE ID port
0F5-0F7 N/A
0F8 IDE Index port
0F9-0FB N/A
0FD-0FF N/A
100-179 Available
180-181 Default AIM4 SRAM control register (May be remapped)
182-1EF Available
1F0-1F7 Primary IDE Controller (AT Drive)
1FB-22F Available
230 -23F Available
240 -25F Serial Port 3/4
260-2F7 Available
2F8-2FF Serial Port 2
300-36F Available
370-377 Alt. Floppy Disk Controller
378-37F Available
380-3AF Available
3B0-3BB and 3BF Mono/VGA mode video
Page 44 Express-HLE
I/O Map (cont'd)
Hex Range
3BC-3BE
Device
Reserved for parallel port
3E0-3EF Available
3F0-3F7 Available
3F8-3FF Serial port 1
4D0
4D1
CF8-CFB
CF9
Master PIC Edge/Level Trigger register
Slave PIC Edge/Level Trigger register
PCI configuration address register (32 bit I/O only)
Reset Control register (8 bit I/O)
CFC-CFF
580
1C00
1800
1860
0A00~0AFF
PCI configuration data register
Smbus base address for SB.
GPIO Base Address for SB
PM (ACPI) Base Address for SB
Alias for ICH TCO base address.
Reserved for SIO functions base address (ex: PME /GPIO etc)
Express-HLE Page 45
IRQ#
13
14
15
9
10
11
12
6.4
Interrupt Request (IRQ) Lines
PIC Mode
IRQ#
4
5
2
3
6
7
Cascade interrupt from slave PIC
Serial Port 2 (COM2) / PCI
Serial Port 1 (COM1) / PCI
Parallel Port 2 (LPT2)
Generic
Generic
9 Generic
10 Serial Port 3 (COM3)
11
12
Serial Port 4 (COM4)
PS/2 Mouse
14
15
Typical Intterupt Resource
Primary IDE controller
Secondary IDE controller
Connected to Pin
N/A
N/A
N/A
IRQ3 via SERIRQ / PIRQ
IRQ4 via SERIRQ / PIRQ
IRQ5 via SERIRQ / PIRQ
IRQ6 via SERIRQ / PIRQ
IRQ7 via SERIRQ / PIRQ
N/A
N/A
IRQ10 via SERIRQ / PIRQ
IRQ11 via SERIRQ / PIRQ
IRQ12 via SERIRQ / PIRQ
N/A
IRQ14 via SERIRQ / PIRQ
IRQ15 via SERIRQ / PIRQ
Note (1): These IRQs can be used for PCI devices when onboard device is disabled.
APIC Mode
Typical Intterupt Resource
2
3
4
Cascade interrupt from slave PIC
Serial Port 2 (COM2)
Serial Port 1 (COM1
5 N/A
6 N/A
7 N/A
PCI
Serial Port 3 (COM3)
Serial Port 4 (COM4)
PS/2 Mouse
Math Processor
Primary IDE controller
Secondary IDE controller
Connected to Pin
N/A
N/A
N/A
IRQ3 via SERIRQ / PIRQ
IRQ4 via SERIRQ / PIRQ
N/A
N/A
N/A
N/A
IRQ9 via SERIRQ / PIRQ
IRQ10 via SERIRQ / PIRQ
IRQ11 via SERIRQ / PIRQ
IRQ12 via SERIRQ / PIRQ
N/A
IRQ14 via SERIRQ / PIRQ
IRQ15 via SERIRQ / PIRQ
Page 46
Available
No
No
No
Note (1)
Note (1)
Note (1)
No
Note (1)
No
Note (1)
Note (1)
Note (1)
No
Note (1)
Note (1)
Available
No
No
No
Note (1)
Note (1)
No
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Note (1)
Express-HLE
APIC Mode (cont'd)
IRQ#
16
17
18
Typical Intterupt Resource
N/A
N/A
N/A
19
20
N/A
N/A
21 N/A
22 N/A
23 N/A
Connected to Pin
Intel HDA, PCIE Port 0/1/2/3/4/5/6, EHCI Conterller
#2 ,P.E.G Root Port, I.G.D ,XHCI Controller
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,
Available
Note (1)
Note (1)
Note (1) PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port, SMBus
Controller, EHCI Controller #2
PCIE Port 0/1/2/3/4/5/6, P.E.G Root Port,
Gbe Controller
Note (1)
Note (1)
Intel HDA
EHCI Controller #1
Note (1)
Note (1)
Note (1): These IRQs can be used for PCI devices when onboard device is disabled.
Express-HLE Page 47
6.5
PCI Configuration Space Map
Routing Bus
Number
00h
Device
Number
00h
Function
Number
00h N/A
Description
Intel host Bridge
00h 03h 00h Internal HD Audio Device
00h
00h
00h
00h
00h
00h
00h
00h
00h 16h 00h Internal Intel Management Engine Interfaxe #1
00h 16h 01h Internal Intel Management Engine Interfaxe #2
00h 16h 02h Internal IDE-R
00h 16h 03h Internal KT
00h 19h 00h Internal Gigabit Etherent Controller
00h
00h
1Bh
1Ch
00h
00h
Internal
Internal
High Definition Audio controller
Intel ICH Express Root port 1
00h
00h
00h
1Ch
1Ch
1Ch
1Ch
1Ch
1Ch
1Ch
1Dh
1Ah
1Fh
1Fh
01h
02h
03h
04h
05h
06h
07h
00h
00h
00h
02h
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
N/A
Internal
Intel ICH Express Root port 2
Intel ICH Express Root port 3
Intel ICH Express Root port 4
Intel ICH Express Root port 5
Intel ICH Express Root port 6
Intel ICH Express Root port 7
Intel ICH Express Root port 8
Intel USB EHCI Controller #1
Intel USB EHCI Controller #2
Intel LPC Interface Bridge
SATA Host Controller #1
00h 1Fh 05h Internal SATA Host Controller #2
Page 48 Express-HLE
6.6
PCI Interrupt Routing Map
INT
Line
P.E.G
Root Port
Audio
Controller xHCI
Controller
ME
Controller #1
ME
Controller #2
IDE-R KT
Int0 INTA:16 INTA:16 INTA:21 INTA:16
Int1
Int2
Int3
INTD:19
INTC:18
INTB:17
GbEt
Controller
HDA
Controller
INT
Line
PCIE port1 PCIE port 2 PCIE port 3 PCIE port 4 PCIE Port 5 PCIE Port 6 PCIE Port 7 PCIE port 8
Int0 INTA:16 INTB:17 INTD:19 INTA:16 INTA:16 INTB:17 INTD:19 INTA:16
Int1 INTB:17 INTC:18 INTA:16 INTB:17 INTB:17 INTC:18 INTA:16 INTB:17
Int2 INTC:18 INTD:19 INTB:17 INTC:18 INTC:18 INTD:19 INTB:17 INTC:18
Int3 INTD:19 INTA:16 INTC:18 INTD:19 INTD:19 INTA:16 INTC:18 INTD:19
INT
Line
EHIC #1 EHIC #2 LPC
Controller
SATA
Controller #1
Int0 INTH:23 INTA:16 INTF:21
Int1 INTD:19 INTD:19
Int2
Int3
INTC:18
INTA:16
SMBus
Controller
SATA
Controller #2
Thermal
Subsystem
INTH:23
INTD:19
INTC:18
6.7
SMBus Slave Addresses
Device
DIMM A
Address
A0h
DIMM B A4h
BMC 50h
Extend GPIO 40h
Express-HLE Page 49
7
BIOS Setup
7.1
Menu Structure
This section presents the six primary menus of the BIOS Setup Utility. Use the following table as a quick reference for the contents of the
BIOS Setup Utility. The subsections in this section describe the submenus and setting options for each menu item. The default setting options are presented in bold, and the function of each setting is described in the right hand column of the respective table.
Main Advanced Boot Security Save & Exit
System Information
Processor Information
PCH Information
System ►
Management
System Date
System Time
CPU ►
Memory ►
Graphics ►
SATA ►
USB ►
Network ►
PCI and PCIe ►
Super IO ►
ACPI and ►
Power
Management
Sound ►
Serial Port ►
Console
Clock ►
Thermal ►
Miscellaneous ►
Boot Configuration ►
CSM Parameters ►
Password Description ►
Secure Boot Menu ►
Reset Options ►
Save Options ►
Page 50 Express-HLE
7.2
Main
The Main Menu provides read-only information about your system and also allows you to set the System Date and Time. Refer to the tables below the screen shot of this menu for details of the submenus and settings.
7.2.1
System Information
Feature
BIOS Version
Board Revision
Build Date and Time
Options
Info only
Info only
Info only
Description
ADLINK BIOS version.
Hardware revision.
ADLINK date the BIOS was build.
7.2.2
Processor Information
Feature
CPU Brand String
Frequency
Processor ID
Stepping
Number of Processors
GT Info
IGFX VBIOS Version
Total Memory
Options
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
7.2.3
PCH Information
Feature
PCH NAME
PCH SKU
Stepping
ME FW Version
ME Firmware SKU
System Management
Options
Info only
Info only
Info only
Info only
Info only
Submenu
Description
Display CPU Brand Name.
Display CPU Frequency.
Display CPU ID.
Display CPU Stepping.
Display number of Processors.
Display GT info of Intel Graphics.
Display VBIOS Version.
Display installed memory size.
Description
Display PCH name.
Display PCH SKU.
Display PCH stepping.
Display version of ME.
Display ME Firmware Kit SKU number.
Express-HLE Page 51
7.2.3.1
PCH Information System Management
Feature
System Management
Version
Options
Info only
Description
7.2.4
System Management
7.2.4.1
System Management > Board Information
Board Information
SMC Firmware
Build Date
SMC Boot loader
Build Date
Hardware Version
Serial Number
Manufacturing Date
Last Repair Date
MAC ID
Info only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Read only
7.2.4.2
System Management > Temperatures and Fan Speed
Feature
Temperatures and Fan
Options
Info only
Description
Display SMC Firmware.
Display SMC firmware build date.
Display SMC boot loader.
Display SMC boot loader build date.
Display SMC hardware Version.
Display SMC serial Number.
Display SMC manufacturing date.
Display SMC last repair date.
Display SMC MAC ID
Current
Startup
Min
Max
Board Temperatures
Current
Startup
Min
Max
CPU Fan Speed
System Fan Speed
Read
Read
Read only
Info only
Read
Read
Read only
Read only
Read only
Display CPU current temperature.
Display CPU startup temperature.
Display CPU min temperature.
Display board current temperature.
Display board startup temperature.
Display board min temperature.
Display CPU fan speed.
Display system fan speed.
Page 52 Express-HLE
7.2.4.3
System Management > Power Consumption
Feature
Power Consumption
Current Input Current
Current Input Power
AIN0
V3.30
V1.05
Vtt
V1.35
V5.00
V3.30
AIN7
Options
Info only
Read only
Read only
Read only
Read only
Read only
Read only
Read
Read
Read only
Read only
7.2.4.4
System Management > Runtime Statistics
Feature
Runtime Statistics
Total Runtime
Options
Info only
Read only
Boot Cycles
Boot Reason
Read
Read
Read only
Read only
Description
Display input current.
Display input power.
Display actual voltage of the AIN0.
Display actual voltage of the V3.30.
Display actual voltage of the V1.05.
Display actual voltage of the VTT.
Display actual voltage of the V1.35.
Display actual voltage of the V5.00.
Display actual voltage of the V3.30.
Display actual voltage of the AIN7.
Description
The returned value specifies the total time in minutes the system is running in S0 state.
The returned value specifies the time in seconds the system is running in S0 state.
This counter is cleared when the system is removed from the external power supply.
The returned value specifies the number of times the external power supply has been shut down
The Bootcounter is increased after a HW- or SW-Reset or after a successful power-up.
The boot reason is the event which causes the reboot of the system.
7.2.4.5
System Management > Flags
Feature Options Description
BIOS Select
ATX/AT-Mode
Read
Read only Display the selection of current BIOS ROM.
Express-HLE Page 53
7.2.4.6
System Management > Power Up
Feature
Power Up
Power Up watchdog
Attention: F12 disables the Power Up
Watchdog.
Attention: The Power-Up Mode only has effect, if the module is in ATX-Mode.
Options
Info only
Enabled
Disabled
Disabled
Enable
Turn on
Remain off
Last State
Description
The Power-Up Watchdog resets the system after a certain amount of time after power-up.
Reduces the power consumption of the system.
Turn On: The machine starts automatically when the power supply is turned on.
Remain Off :To start the machine the power button has to be pressed.
Last State: when powered on during a power failure the system will automatically power on when power is restored
7.2.4.7
System Management > LVDS Backlight
Feature
LVDS Backlight
LVDS Backlight Bright
Options
Info only
255
7.2.4.8
System Management > Smart Fan
Feature
Smart Fan
CPU Smart FanTemperature Source
CPU Fan Mode
CPU Trigger Point 1
Trigger Temperature
Options
Info only
CPU Sensor
System Sensor
AUTO (Smart Fan)
Fan Off
Fan On
Read only
15
PWM Level
CPU Trigger Point 2
Trigger Temperature
PWM Level
CPU Trigger Point 3
Trigger Temperature
PWM Level
CPU Trigger Point 4
Trigger Temperature
PWM Level
30
Read only
60
40
Read only
70
63
Read only
80
100
Page 54
Description
The value range starts by 0 and ends by 255.
Description
Select CPU smart fan source.
Select CPU Fan Mode.
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
Select PWM level.
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
Select PWM level.
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
Select PWM level.
Specifies the temperature threshold at which the BMC turns on
CPU fan with specific PWM level.
Select PWM level.
Express-HLE
7.2.5
System Date and Time
Feature
System Date
Options
Weekday, MM/DD/YYYY
System Time HH/MM/SS
Description
Requires the alpha-numeric entry of the day of the week, day of the month, calendar month, and all 4 digits of the year, indicating the century and year (Fri XX/XX/20XX)
Presented as a 24-hour clock setting in hours, minutes, and seconds
Express-HLE Page 55
7.3
Advanced
This menu contains the settings for most of the user interfaces in the system
7.3.1
CPU
Feature
CPU
CPU Signature
Processor Family
Microcode Patch
Max CPU speed
Min CPU speed
CPU Speed
Processor Cores
Options
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Description
Manufacturer, model, speed
Display CPU Signature.
Display Processor Family.
Display Microcode Patch.
Display Max CPU speed.
Display Min CPU speed.
Display CPU Speed.
Display Processor Cores.
Intel HT Technology
Intel VT-x Technology
VT-d Capability
Intel SMX Technology
64-bit
L1 Data Cache
L1 Code Cache
L2 Cache
L3 Cache
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Inf o only
Display Intel HT Technology support or not.
Display Intel VT-x Technology support or not.
Display VT-d Capability support or not.
Display Intel SMX Technology support or not.
Display 64-bit support or not.
Display cache info.
Display cache info.
Display cache info.
Display cache info.
Limit CPUID Maximum
Execute Disable Bit
Disabled
Enabled
Disabled
Enabled
When Enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher
CPUID input value. When Disabled, the processor will return the actual maximum CPUID input value
Enable/Disable the Execute Disable Bit (XD) of the processor.
With the XD bit set to enabled certain classes of malicious buffer overflow attacks can be prevented when combined with a supporting
OS.
Intel Virtualization Technology Disabled
Enabled
Enable/Disable support for the Intel virtualization technology.
VT-d Disabled
Enabled
Check to enable VT-d function on MCH.
SB CRID Enable/Disable SB Compatible Revision ID.
CPU Processor Power Managemnt (PPM)
Disabled
Enabled
Info only
EIST Disabled
Enabled
Disabled: No SpeedStep, stick to CPU ratio
Enabled: CPU speed is controlled by the operating system.
Turbo Mode Disabled
Enabled
Enable/Disable turbo mode.
Page 56 Express-HLE
Feature
CPU C3 Report
CPU C6 Report
CPU C7 Report
ACPI T State
CPU DTS
7.3.2
Memory
Feature
Memory RC Version
Memory Frequency
Total Memory
Memory Voltage
CAS Latency (tCL)
Minimum delay time
CAS to RAS (tRCDmin)
Row Precharge (tRPmin)
Active to Precharge (tRASmin)
XMP Profile 1
XMP Profile 2
SPD Write Protect
Memory Frequency Limiter
Max TOLUD
MRC Fast Boot
Memory Remap
Channel A DIMM Control
Channel B DIMM Control
Memory Thermal Management
Options
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Info only
Enabled
Disabled
Auto
Dynamic
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Options
Disabled
Enabled
Disabled
Enabled
Disabled
CPU C7
CPU C7S
Disabled
Enabled
Disabled
Enabled
Express-HLE
Description
Enable/Disable CPU C3 report to OS.
Enable/Disable CPU C6 report to OS.
Enable/Disable CPU C7 report to OS.
Enable/Disable ACPI T state support.
Enable/Disable CPU DTS.
Description
Display Memory Reference Code Version.
Display Memory Frequency.
Display Memory Voltage.
Display CAS Latency (tCL).
Display Minimum delay time.
Display CAS to RAS (tRCDmin).
Display Row Precharge (tRPmin).
Display Active to Precharge (tRASmin).
Display XMP Profile 1 support or not.
Display XMP Profile 2 support or not.
Enable:Writes to SMBus slave addresses A0h - AEh are disabled.
Maximum Memory Frequency Selections in Mhz.
Maximum Value of TOLUD. Dynamic assignment would adjust
TOLUD automatically based on largest MMIO length of installed graphic controller.
Enable/Disable MRC fast boot.
Enable/Disable e memory remap above 4G.
Enable/Disable DIMMs on channel A.
Enable/Disable DIMMs on channel B.
Enable/Disable Memory Thermal Management.
Page 57
7.3.3
Graphics
Feature
Graphics Configuration
IGFX VBIOS Version
IGfx Frequency
Graphics Turbo IMON Current
Primary Display
Primary PEG
Primary PCIE
Internal Graphics
Aperture Size
DVMT Pre-Allocated
DVMT Total Gfx Mem
Gfx Low Power Mode
LVDS Backlight Mode
GTT LVDS Backlight Control
DDI function choose
Primary IGFX Boot Display
Secondary IGFX Boot Display
Page 58
XXXM
Enabled
Disabled
BMC Mode
GTT Mode
0%
20%
40%
60%
80%
100%
Display Port
HDMI
CRT
Disabled
Options
Info only
Info only
Info only
Number entry field
Auto
IGFX
PEG
PCIE
Auto
PEG1
PEG2
Auto
PCIE1
PCIE2
PCIE3
PCIE4
PCIE5
PCIE6
PCIE7
Auto
Disabled
Enable
128MB
256MB
512MB
XXM
Description
Display VBIOS Version.
Display IGfx Frequency.
Graphics turbo IMON current values supported (14-31).
Select which of IGFX/PEG/PCI Graphics device should be Primary
Display Or select SG for Switchable Gfx.
Select PEG0/PEG1/PEG2/PEG3 Graphics device should be Primary
PEG.
Select PCIE0/PCIE1/PCIE2/PCIE3/PCIE4/PCIE5/PCIE6/PCIE7
Graphics device should be Primary PCIE.
Keep IGD enabled based on the setup options.
Select the Aperture Size.
Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device.
Select DVMT5.0 Total Graphic Memory size used by the Internal
Graphics Device.
This option is applicable for SFF only.
Select LVDS Backlight control function.
Actual backlight value in percent of the maximum setting.
Select DDI function choose to display port or HDMI.
Select the Video Device which will be activated during POS.
Select Secondary Display Device.
Express-HLE
Feature
LCD Panel Type
Active LFP
Panel Color Depth
Panel Scaling
GT – Power Management Control
GT Info
RC6 (Render Standby)
GT OverClocking Support
7.3.4
SATA
Feature
SATA Controller(s)
SATA Mode Selection
SATA Test Mode
Aggressive LPM Support
SATA Controller Speed
Intel ® Rapid Start Technology
SATA Port Configuration
Express-HLE
Options
Enabled
Disabled
IDE
AHCI
RAID
Enabled
Disabled
Enabled
Disabled
Default
Gen1
Gen2
Gen3
Submenu
Submenu
Options
VBIOS Default
640X480
800X600
1024X768
1280X1024
1400X1050
1600X1200
1366X768
1680X1050
1920X1200
1440X900
1600X900
1024X768 LVDS2
1280X800
1920X1080
2048X1536
No LVDS
Edp Port-A
18 Bit
24 Bit
Auto
Off
Force Scaling
Info only
Info only
Enabled
Disabled
Enabled
Disabled
Description
Select LCD panel used by Internal Graphics Device by selecting the appropriate setup item.
Select the Active LFP Configuration.
Select the LFP Panel Color Depth
Select the LCD panel scaling option used by the Internal Graphics
Device.
Display GT info of Intel Graphics.
Check to enable render standby support.
Enable/Disable GT OverClocking Support.
Description
Enable/Disable SATA Device.
Determines how SATA controller(s) operate.
Enable/Disable Test Mode.
Enable PCH to aggressively enter link power state.
Indicates the maximum speed the SATA controller can support.
Page 59
Feature
Software Feature Mask Configuration
RAID0
RAID1
RAID10
RAID5
Intel Rapid Recovery Technology
OROM UI and BANNER
Options
Info only
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
HDD Unlock
LED Locate
IRRT Only on ESATA
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Smart Response Technology
OROM UI Delay
Enabled
Disabled
Enabled
Disabled
7.3.4.1
SATA > Intel® Rapid Start Technology
Feature
Intel (R) Rapid Start
Entry on S3 RTC Wake
Entry After
Active Page Threshold
Hybrid Hard Disk Support
RapidStart Display Save/Restore
Options
Disabled
Enabled
Disabled
Enabled
10
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
7.3.4.2
SATA > SATA Port Configuration
Feature
SATA Port Configuration
Port X
Options
Info only
Disabled
Enabled
Page 60
Description
Enable/Disable RAID0 feature.
Enable/Disable RAID1 feature.
Enable/Disable RAID10 feature.
Enable/Disable RAID5 feature.
Enable/Disable Intel Rapid Recovery Technology.
If enabled, then the OROM UI is shown. Otherwise, no OROM banner or information will be displayed if all disks and RAID volumes are Normal.
If enabled, indicates that the HDD password unlock in the OS is enabled.
If enabled, indicates that the LED/SGPIO hardware is attached and ping to locate feature is enabled on the OS.
If enabled, then only IRRT volumes can span internal and eSATA drives. If disabled, then any RAID volume can span internal and eSATA drives.
Enable/Disable Smart Response Technology.
If enabled, indicates the delay of the OROM UI Splash Screen in a normal status.
Description
Enable/Disable Intel (R) Rapid Start.
RapidStart invocation upon S3 RTC wake.
Enable RTC wake timer at S3 entry. Value range from
0(Immediately) to 120 minutes.
Support RST with small partition.
Hybrid Hard Disk Support.
RapidStart Display Save/Restore.
Description
Enable/Disable SATA Port.
Express-HLE
Feature
Hot Plug
Mechanical Presence
External SATA
SATA Device Type
Spin up Device
7.3.5
USB
Feature
USB Devices
Legacy USB Support
USB3.0 Support
XHCI Hand-off
EHCI Hand-off
USB Mass Storage Driver Support
PCH USB Configuration
USB hardware delays and time-outs:
USB transfer time-out
Device reset time-out
Device power-up delay
Mass Storage Devices
Options
Info only
Enabled
Disabled
Auto
Info only
1 sec
5 sec
10 sec
20 sec
10 sec
20 sec
30 sec
40 sec
Auto
Manual
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Submenu
Info only
Options
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Hard Disk Drive
Sold State Drive
Disabled
Enabled
Description
Designates this port as Hot Pluggable.
Controls reporting if this port has an Mechanical Presence
Switch.\n\nNote: Requires hardware support.
External SATA Support.
Identify the SATA port is connected to Solid State Drive or Hard
Disk Drive.
On an edge detect from 0 to 1, the PCH starts a COMRESET initialization sequence to the device.
Description
X Drive, X Keyboards, X Mouse, X Hubs
Enables legacy USB support.
Auto option disables legacy support if no USB devices are connected.
Disable option will keep USB devices available only for EFI applications and setup.
Enable/Disable USB3.0 (XHCI) Controller Support.
This is a workaround for OSes without XHCI hand-off support. The
XHCI ownership change should be claimed by the XHCI OS driver.
This is a workaround for OSes without EHCI hand-off support. The
EHCI ownership change should be claimed by the EHCI OS driver.
Enable/Disable USB Mass Storage Driver Support.
The time-out value for Control, Bulk, and Interrupt transfers
USB mass storage device Start Unit command time-out.
Maximum time the device will take before it properly reports itself to the Host Controller. 'Auto' uses default value: for a Root port it is 100 ms, for a Hub port the delay is taken from Hub descriptor.
List current USB max stroge device.
Express-HLE Page 61
7.3.5.1
USB > PCH USB Configuration
Feature
USB Precondition
XHCI Mode
Options
Disabled
Enabled
Disabled
Enabled
USB Precondition
USB Port #0~13
USB30 Port #0~5
Enable
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
7.3.6
Network
Feature
Network Stack
Network Stack
PCH LAN Controller
Wake on LAN
AMT Configuration
Intel AMT
BIOS Hotkey Pressed
MEBx Selection Screen
Hide Un-Configure ME Confirmation
MEBx Debug Message Output
Un-Configure ME
Amt Wait Timer
Disable ME
ASF
Activate Remote Assistance Process
USB Configure
Options
Info only
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Info only
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
0
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Page 62
Description
Precondition work on USB host controller and root ports for faster enumeration.
Mode of operation of xHCI controller.
Precondition work on USB host controller and root ports for faster enumeration.
Control each of the USB ports (0~13) disabling.
Enable or Disable USB 3.0 Port.
Description
Enable/Disable UEFI network stack.
Enable/Disable onboard NIC.
Enable/Disable integrated LAN to wake the system. (The Wake On
LAN cannot be disabled if ME is on at Sx state.
Enable/Disable Intel (R) Active Management Technology BIOS
Extension.
Enable/Disable BIOS hotkey press.
Enable/Disable MEBx selection screen.
Hide Un-Configure ME without password Confirmation Prompt.
Enable MEBx debug message output.
Un-Configure ME without password.
Set timer to wait before sending ASF_GET_BOOT_OPTIONS.
Set ME to Soft Temporary Disabled.
Enable/Disable Alert Specification Format.
Trigger CIRA boot.
Enable/Disable USB Configure function.
Express-HLE
Feature
PET Progress
AMT CIRA Timeout
Options
Enabled
Disabled
0
OS Timer
BIOS Timer
Disabled
7.3.7
PCI and PCIe
Feature
PCI Common Settings
Options
Info only
PCI Latency Timer
VGA Palette Snoop
PCI Express Settings
Maximum Read Request
Warning: Enabling ASPM may cause some PCI-
E devices to fail
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Auto
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Auto
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Disabled
Auto
Force L0S
32 PCI Bus Clocks
64 PCI Bus Clocks
96 PCI Bus Clocks
128 PCI Bus Clocks
160 PCI Bus Clocks
192 PCI Bus Clocks
224 PCI Bus Clocks
248 PCI Bus Clocks
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Express-HLE
Description
User can Enable/Disable PET Events progress to recieve PET events or not.
OEM defined timeout for MPS connection to be established. 0 - use the default timeout value of 60 seconds. 255 - MEBX waits until the connection succeeds.
Set OS watchdog timer.
Set BIOS watchdog timer.
Description
Select the PCI latency defined in PCI Bus clock cycles
Allow PCI cards that do not contain their own VGA color palette to access the video core’s palette
Enables or Disables PCI Device to Generate PERR#.
Enables/Disables PCI Device to Generate SERR#.
Enables/Disables PCI Express Device Relaxed Ordering.
If ENABLED allows Device to use 8-bit Tag field as a requester.
Enables/Disables PCI Express Snoop option
Select Maximum Payload size or let BIOS decide (Auto)
Set Maximum Read Request Size of PCI Express Device or allow
System BIOS to select the value.
Set the ASPM Level. Disabled - Disables ASPM.
Auto - BIOS auto configure
Force L0S - Force all links to L0s State
Page 63
Feature
Link Training Retry
Options
Enabled
Disabled
3
5
Disabled
2
100
Description
If enabled the generation of PCI Express synchronization patterns is allowed
Defines number of Retry Attempts software will take to retrain the link if previous training attempt was unsuccessful.
Link Training Timeout (uS)
Restore PCIE Registers
Keep Link ON
Disable
Enabled
Disabled
Defines number of microseconds software will wait before polling
'Link Training' bit in Link Status register. Value range from 10 to
10000 uS.
In order to save power, software will disable unpopulated PCI
Express links, if this option set to 'Disable Link'.
On non-PCI Express aware OS's (Pre Windows Vista) some devices may not be correctly reinitialized after S3. Enabling this restors PCI
Express device configurations on S3 resume. Warning: Enabling this may cause issues with other hardware after S3 resume.
PEG Configuration (System Agent)
PCH-PCIe Configuration
Submenu
Submenu
7.3.7.1
PCI and PCIe > PEG Configuration (System Agent)
Feature
PEG Configuration (System Agen)
PEG0
PEG0 – Gen X
PEG0 ASPM
Detect Non-compliance Device
PEG Sampler Calibrate
PEG Gen3 Equalization
Gen3 Eq Phase 2
Gen3 Eq Preset Search
Options
Info only
Not Present
Half
Full
Enabled
Disable
Auto
Enabled
Disable
Enabled
Auto
Gen1
Gen2
Gen3
Disabled
Auto
ASPM L0S
ASPM L1
ASPM L0SL1
Disabled
Enabled
Auto
Disabled
Enable
Auto
Enabled
Disable
Description
Display PEG0 present or not.
Configure PEG0 B0:D1:F0 Gen1-Gen3
Control ASPM support for the PEG Device. This has no effect if
PEG is not the currently active device.
Enable/Disable the PEG.
Detect Non-Compliance PCI Express Device in PEG.
Enable/Disable PEG Sampler Calibrate\nAuto means Disabled for SNB MB/DT, Enabled for IVB A0 B0.
Perform PEG Swing Control, on IVB C0 and Later.
Perform PEG Gen3 Equalization steps.
Perform PEG Gen3 Equalization Phase 2.
Perform PEG Gen3 Preset Search algorithm, on IVB C0 and
Later.
Page 64 Express-HLE
Feature
PEG RxCEM LoopBack Mode
Options
Disable
Disabled
Enable
8
Description
Enabled/Disabled PEG RxCEM Loopback Mode.
PCIe Gen3 RxCTLEp Setting 0~7 The range of the setting is (0~15) This setting has to be specified basing on platform design and following the guideline.
7.3.7.2
PCI and PCIe > PCH-PCIe Configuration
Feature
PCH-PCIe Configuration
Options
Info only
Description
PCI Express Clock Gating
DMI Link ASPM Control
DMI Link Extended Synch Control
PCIE Root Port Function Swapping
Subtractive Decode
PCIE Ports 1-4 Configuration
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
4x1 Port
1X2 2X1 Port
2X2 Port
1X4 Port
Enable/Disable PCI Express Clock Gating for each root port.
The control of Active State Power Management on both NB side and SB side of the DMI Link.
The control of Extended Synch on SB side of the DMI Link.
PCIe-USB Glitch W/A for bad USB device(s) connected behind
PCIE/PEG Port.
Enable/Disable PCI Express PCI Express Root Port Function
Swapping.
Enable/Disable PCI Express Subtractive Decode.
To configure PCI-E Port 1-4 of PCH.
[4X1]: Port 1-4 (x1) and Port 8 (x1)
[1x2 2x1]: Port 1 (x2), Port 2 (disabled), Ports 3 and Port 4 (x1)
[2x2]: Port 1-2 (x2) and Port 3-4 (x2)/[1x4]:Port 1 (x4), Ports 2-4
(disable)
PCIE Ports 5-8 Configuration 4x1 Port
1X2 2X1 Port
To configure PCI-E Port 5-7 of PCH.
[4X1] : Port 5-8 (x1) and Port 8 (x1)
[1x2 2x1]: Port 5 (x2), Port 6 (disabled), Ports 7 and Port 8 (x1)
PCI Express Root Port 1~7 Submenu Configure PCI Express Root Port 1~7 setting.
PCI and PCIe > PCH-PCIe Configuration > PCI Express Root Port
Feature
PCI Express Root Port
ASPM Support
L1 Substates
Options
Disabled
Enable
Disabled
Enable
Description
Control the PCI Express Root Port.
Set the ASPM Level: Force L0s - Force all links to L0s
State: AUTO - BIOS auto configure: DISABLE - Disables
ASPM
PCI Express L1 Substates settings.
URR
FER
NFER
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Enable/Disable PCI Express Unsupported Request
Reporting.
Enable/Disable PCI Express Device Fatal Error Reporting.
Enable/Disable PCI Express Device Non-Fatal Error
Reporting.
Express-HLE Page 65
Feature
CER
CTO
SEFE
SENFE
SECE
PCIe Speed
Detect Non-Compiance
Extra Bus Reserved
Reseved Memory
Prefetchable Memory
Reserved I/O
PCIE LTR
PCIE LTR Lock
Snoop Latency Ocerrid
Non Snoop Latency Ocerrid
7.3.8
Super IO
Feature
Super IO Chip
W83627DHG Super IO Configuration
Serial Port 1 Configuration
Page 66
Options
Info only
Info only
Enabled
Disabled
IO=3F8h; IRQ=4
10
10
4
Disabled
Enable
Disabled
Enable
Disabled
Manual
Auto
Disabled
Manual
Auto
Options
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Disabled
Enable
Auto
Gen1
Gen2
Disabled
Enable
0
Description
Enable/Disable PCI Express Device Correctable Error
Reporting.
Enable/Disable PCI Express Completion Timer TO.
Enable/Disable Root PCI Express System Error on Fatal
Error.
Enable/Disable Root PCI Express System Error on Non-
Fatal Error.
Enable/Disable Root PCI Express System Error on
Correctable Error.
Enable/Disable PCI Express PME SCI.
Enable/Disable PCI Express Hot Plug.
Select PCI Express port speed.
Detect Non-Compliance PCI Express Device. If enabled, it will take more time at POST time.
Extra Bus Reserved (0-7) for bridges behind this Root
Bridge.
Reserved Memory Range for this Root Bridge.
Prefetchable Memory Range for this Root Bridge.
Reserved I/O (4K/8K/12K/16K/.../48K) Range for this Root
Bridge.
PCIE Latency Reporting Enable/Disable.
PCIE LTR Configuration Lock.
Snoop Latency Ocerride for PCH PCIE.
Non Snoop Latency Ocerride for PCH PCIE.
Description
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Express-HLE
Feature
Serial Port 2 Configuration
N5104D Super IO Configuration
Serial Port 1 Configuration
Serial Port 2 Configuration
Enabled
Disabled
IO=240h; IRQ=10
Auto
IO=240h; IRQ=10
IO=240h; IRQ=10,11,12
IO=248h; IRQ=10,11,12
IO=250h; IRQ=10,11,12
IO=258h; IRQ=10,11,12
Enabled
Disabled
IO=248h; IRQ=11
Auto
IO=248h; IRQ=11
IO=240h; IRQ=10,11,12
IO=248h; IRQ=10,11,12
IO=250h; IRQ=10,11,12
IO=258h; IRQ=10,11,12
Options
Auto
IO=3F8h; IRQ=4
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Enabled
Disabled
IO=2F8h; IRQ=4
Auto
IO=2F8h; IRQ=3
IO=3F8h; IRQ=3,4,5,6,7,10,11,12
IO=2F8h; IRQ=3,4,5,6,7,10,11,12
IO=3E8h; IRQ=3,4,5,6,7,10,11,12
IO=2E8h; IRQ=3,4,5,6,7,10,11,12
Info only
Description
Select an optimal setting for Super IO device.
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Enable/Disable Serial Port (COM).
Fixed configuration of serial port.
Select an optimal setting for Super IO device.
Express-HLE Page 67
7.3.9
ACPI and Power Management
Feature
ACPI and Power Management
Enable ACPI Auto Configuration
Enable Hibernation
ACPI Sleep State
Options
Info only
Enabled
Disabled
Enabled
Disabled
S3 only
Emulation AT/ATX Emulation AT
ATX
7.3.10
Sound
Feature Options
Enabled
Auto
Azalia Docking Support Enabled
Disabled
Enabled
Disabled
7.3.11
Serial Port Console
Feature
Serial Port Console
Options
Info only
Console Redirection Settings
Console Redirection Settings
Enabled
Disabled
Submenu
Enabled
Disabled
Submenu
Console Redirection Settings
Enabled
Disabled
Submenu
Enabled
Disabled
Submenu Console Redirection Settings
Page 68
Description
Enables or Disables BIOS ACPI Auto Configuration.
Enables or Disables System ability to Hibernate (OS/S4 Sleep
State). This option may be not effective with some OS.
Select ACPI sleep state the system will enter when the SUSPEND button is pressed.
Select Emulation AT or ATX function. If this option set to [Emulation
AT], BIOS will report no suspend functions to ACPI OS. In windows
XP, it will make OS show shutdown message during system shutdown.
Description
Disabled = Azalia will be unconditionally disabled.
Enabled = Azalia will be unconditionally enabled.
Auto = Azalia will be enabled if present, disabled other.
Enable/Disable Azalia Docking Support of Audio Controller.
Enable/Disable Power Management capability of Audio Controller.
Description
Console Redirection Enable or Disable.
Console Redirection Enable or Disable.
Console Redirection Enable or Disable.
Console Redirection Enable or Disable.
Express-HLE
7.3.11.1
Serial Port Console > Console Redirection Settings
Description Feature
Console Redirection Settings
Terminal Type
Bits per second
Data Bits
Parity
Stop Bits
Flow Control
VT-UTF8 Combo Key Support
Recorder Mode
Resolution 100x31
Legacy OS Redirection
Putty KeyPad
Redirection After BIOS Post
Options
Info only
7
8
VT100
VT100+
VT-UTF8
ANSI
9600
19200
38400
57600
115200
Disabled
Enable
Disabled
Enable
Disabled
Enable
80x24
80x25
None
Even
Odd
Mark
Space
1
2
None
Hardware RTS/CTS
VT100
LINUX
XTERMR6
SCO
ESCN
VT400
Always Enabled
BootLoader
Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto
1 or more bytes.
Selects serial port transmission speed.
Select Data Bits.
Select Parity.
Select number of stop bits.
Select flow control.
Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.
With this mode enabled only text will be sent. This is to capture
Terminal data.
Enables or disables extended terminal resolution
On Legacy OS, the Number of Rows and Columns supported redirection
Select FunctionKey and KeyPad on Putty.
The Settings specify if BootLoader is selected than Legacy console redirection is disabled before booting to Legacy OS.
Default value is Always Enable which means Legaacy console
Redirection is enabled for Legacy OS.
7.3.12
Clock
Feature Options Description
Use Watchdog Timer for ICC Enabled
Disabled
Enable Watchdog Timer operation for ICC. If enabled, Watchdog
Timer will be started after ICC-related changes. This timer detects platform instability caused by wrong clock settings.
Express-HLE Page 69
Feature
Turn off unused PCI/PCIe clocks
ICC Locks After EOP
Clock Manipulation
ICC Overclocking Lib
CLKRUN# Logic
7.3.13
Thermal
Feature
Options
Disabled
Enable
Default
All Locked
All UnLocked
Info only
Info only
Enabled
Disabled
Description
Disabled: all clocks turned on.
Enabled: clocks for empty PCI/PCIe slots will be turned off to save power. Platform must be powered off for changes to take effect.
Lock ICC register after EOP.
Enable the CLKRUN# logic to stop the PCI clock.
Options Description
Automatic Thermal Reporting
Critical Trip Point
Enabled
Disabled
Disabled
85 C
95 C
Configure _CRT, _PSV and _AC0 automatically based on values recommended in BWG’s Thermal Reporting for Thermal
Management settings. Set to Disabled for manual conmfiguration.
This value controls the temperature of the ACPI Critical Trip Point - the point in which the OS will shut the system off.
NOTE: 100C is the Plan Of Record (POR) for all Intel mobile processors.
This value controls the temperature of the ACPI Active Trip Point - the point in which the OS will turn the processor fan on Active Trip
Point Fan Speed.
Active Trip Point
Passive Trip Point
Disabled
40 C
50 C
60 C
70 C
BMC Default
Disabled
80 C
90 C
1
This value controls the temperature of the ACPI Passive Trip Point - the point in which the OS will begin throttling the processor.
Passive TC1 Value
Passive TC2 Value
Passive TSP Value
5
10
This value sets the TC1 value for the ACPI Passive Cooling
Formula. Range 1 – 16.
This value value sets the TC2 value for the ACPI Passive Cooling
Formula. Range 1 - 16
This item sets the TSP value for the ACPI Passive Cooling Formula.
It represents in tenths of a second how often the OS will read the temperature when passive cooling is enabled. Range 2 – 32.
Enable/Disable Watchdog ACPI Even Shutdown. Watchdog ACPI Even Shutdown Disabled
Enable
7.3.14
Miscellaneous
Feature
High Precision Timer
Options
Enabled
Disabled
Description
Enable/Disable the High Precision Event Timer.
Security
BIOS Security Configuration Submenu
Page 70 Express-HLE
Feature
Intel TXT(LT) Configuration
Options
Submenu
Enabled
Disabled
Description
Enables or Disables the High Precision Event Timer.
7.3.14.1
Miscellaneous > BIOS Security Configuration
Feature
SMI Lock
BIOS Lock
GPIO Lock
BIOS Interface Lock
RTC RAM Lock
Options
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Description
Enable or Disable the SMI Lock
Enable or Disable the BIOS lock enable (BLE) bit
Enable or Disable the GPIO lockdown
Enable or Disable the BIOS interface lockdown
Enable or Disable bytes 38h-2Fh in the upper and lower 128byte bank of the RTC RAM lockdown
7.3.14.2
Miscellaneous > Trusted Computing
Feature
Security Device Support
Options
Enabled
Disabled
Description
Enables or Disables BIOS support for security device.
When disabled OS wil not show Security Device. TCG EFI protocol and INT1A interface will not be available
Express-HLE Page 71
7.4
Boot
7.4.1
Boot Configuration
Feature
Boot Configuration
Setup Prompt Timeout
Bootup NumLock State
Quiet Boot
Options
Info only
1
On
Disabled
Enabled
Fast Boot
Boot Option Priorities
CSM16 Module Version
Option ROM Messages
INT19 Trap Response
Disabled
Enabled
Info only
Submenu
Info only
Upon Request
Always
Force BIOS
Keep Current
Immediate
Postponed
Submenu
7.4.2
CSM parameters
Feature
Launch CSM
Boot Option filter
Launch PXE OpROM policy
Launch Storage OpROM policy
Launch Video OpROM policy
Other PCI device ROM priority
Options
Enabled
Disable
UEFI and Legacy
Legacy only
UEFI only
Do not launch
Legacy only
UEFI only
Do not launch
UEFI only
Legacy only
Do not launch
UEFI only
Legacy only
UEFI OpROM
Legacy OpROM
Page 72
Description
Enable/Disable the onboard SATA controllers.
Select SATA controller mode.
Enable/Disable the PATA port. In fact this enables or disables the
SATA channel on which the onboard SATA to PATA converter is attached. When set to enabled the system boot will be delayed for the time specified in PATA Port Detection Timeout if no PATA device is connected.
Auto: Scan for PATA device and enable per default.
Define the maximum time to wait for drive detection on PATA port.
UPON REQUEST - GA20 can be disabled using BIOS services.
ALWAYS - do not allow disabling GA20; this option is useful when any RT code is executed above 1MB.
Set display mode for Option ROM.
BIOS reaction on INT19 trapping by Option ROM: IMMEDIATE - execute the trap right away; POSTPONED - execute the trap during legacy boot.
Description
This option controls if CSM will be launched.
This option controls what devices system can to boot.
Controls the execution of UEFI and Legacy PXE OpROM.
Controls the execution of UEFI and Legacy Storage OpROM.
Controls the execution of UEFI and Legacy Video OpROM.
For PCI devices other than Network, Mass storage or Video defines which OpROM to launch.
Express-HLE
7.5
Security
7.5.1
Password Description
Feature Options Description
User Password
Secure Boot menu
7.5.2
Secure Boot Menu
Feature
System Mode
Secure Boot
Secure Boot Support
Secure Boot Mode
Enter password
Submenu
Options
Setup
Info only
Disabled
Enabled
Standard
Custom
7.6
Save & Exit
7.6.1
Reset Options
Feature
Save Changes and Reset
Discard Changes and Reset
Description
Secure Boot can be enabled if 1.System running in User mode with enrolled Platform Key(PK) 2.CSM function is disabled.
Secure Boot mode selector. 'Custom' Mode enables users to change
Image Execution policy and manage Secure Boot Keys.
Options
Save changes and reset the system.
Reset the system without saving any changes.
Description
Save Changes and Reset
Discard Changes and Reset
7.6.2
Save Options
Feature
Save Changes
Discard Changes
Restore Defaults
Save as User Defaults
Restore User Defaults
Options Description
Save Changes done so far to any of the setup options.
Discard Changes done so far to any of the setup options.
Restore/Load Default values for all the setup options.
Save the changes done so far as User Defaults.
Restore the User Defaults to all the setup options.
Express-HLE Page 73
8
BIOS Checkpoints, Beep Codes
This section of this document lists checkpoints and beep codes generated by AMI Aptio BIOS. The checkpoints defined in this document are inherent to the AMIBIOS generic core, and do not include any chipset or board specific checkpoint definitions.
Checkpoints and Beep Codes Definition
A checkpoint is either a byte or word value output to I/O port 80h. The BIOS outputs checkpoints throughout bootblock and Power-On Self
Test (POST) to indicate the task the system is currently executing. Checkpoints are very useful for debugging problems that occur during the preboot process.
Beep codes are used by the BIOS to indicate a serious or fatal error. They are used when an error occurs before the system video has been initialized, and generated by the system board speaker.
Aptio Boot Flow
While performing the functions of the traditional BIOS, Aptio 5.x core follows the firmware model described by the Intel Platform Innovation
Framework for EFI (“the Framework”). The Framework refers the following “boot phases”, which may apply to various status code & checkpoint descriptions:
• Security (SEC) – initial low-level initialization
• Pre-EFI Initialization (PEI) – memory initialization 1
• Driver Execution Environment (DXE) – main hardware initialization 2
• Boot Device Selection (BDS) – system setup, pre-OS user interface & selecting a bootable device (CD/DVD, HDD, USB, Network,
Shell, …)
Viewing BIOS Checkpoints
Viewing all checkpoints generated by the BIOS requires a checkpoint card, also referred to as a OST Card or POST Diagnostic Card. These are PCI add-in cards that show the value of I/O port 80h on a LED display.
Some computers display checkpoints in the bottom right corner of the screen during POST. This display method is limited, since it only displays checkpoints that occur after the video card has been activated.
Keep in mind that not all computers using AMI Aptio BIOS enable this feature. In most cases, a checkpoint card is the best tool for viewing
AMI Aptio BIOS checkpoints.
1 Analogous to “bootblock” functionality of legacy BIOS
2 Analogous to “POST” functionality in legacy BIOS
Page 74 Express-HLE
8.1
Status Code Ranges
Status Code
Range
Description
0x01 – 0x0F SEC Status Codes & Errors
0x10 – 0x2F PEI execution up to and including memory detection
0x30 – 0x4F PEI execution after memory detection
0x50 – 0x5F PEI errors
0x60 – 0xCF DXE execution up to BDS
0xD0 – 0xDF DXE errors
0xE0 – 0xE8 S3 Resume (PEI)
0xE9 – 0xEF S3 Resume errors (PEI)
0xF0 – 0xF8 Recovery (PEI)
0xF9 – 0xFF Recovery errors (PEI)
8.2
Standard Status Codes
8.2.1
SEC Status Codes
Status Code Description
0x0 Not used
Progress Codes
0x1
0x2
0x3
Power on. Reset type detection (soft/hard).
AP initialization before microcode loading
North Bridge initialization before microcode loading
0x4
0x5
South Bridge initialization before microcode loading
OEM initialization before microcode loading
0x6
0x7
0x8
0x9
Microcode loading
AP initialization after microcode loading
North Bridge initialization after microcode loading
South Bridge initialization after microcode loading
0xA
0xB
OEM initialization after microcode loading
Cache initialization
SEC Error Codes
0xC – 0xD Reserved for future AMI SEC error codes
0xE
0xF
Microcode not found
Microcode not loaded
Express-HLE Page 75
8.2.2
SEC Beep Codes
None
8.2.3
PEI Status Codes
Status Code Description
Progress Codes
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x10
0x11
0x12
0x13
0x14
0x15
0x16
PEI Core is started
Pre-memory CPU initialization is started
Pre-memory CPU initialization (CPU module specific)
Pre-memory CPU initialization (CPU module specific)
Pre-memory CPU initialization (CPU module specific)
Pre-memory North Bridge initialization is started
Pre-Memory North Bridge initialization (North Bridge module specific)
0x17
0x18
0x19
Pre-Memory North Bridge initialization (North Bridge module specific)
Pre-Memory North Bridge initialization (North Bridge module specific)
Pre-memory South Bridge initialization is started
0x1A
0x1B
Pre-memory South Bridge initialization (South Bridge module specific)
Pre-memory South Bridge initialization (South Bridge module specific)
0x1C Pre-memory South Bridge initialization (South Bridge module specific)
0x1D – 0x2A OEM pre-memory initialization codes
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F-0x4E
Memory initialization. Serial Presence Detect (SPD) data reading
Memory initialization. Memory presence detection
Memory initialization. Programming memory timing information
Memory initialization. Configuring memory
Memory initialization (other).
Reserved for ASL (see ASL Status Codes section below)
Memory Installed
CPU post-memory initialization is started
CPU post-memory initialization. Cache initialization
CPU post-memory initialization. Application Processor(s) (AP) initialization
CPU post-memory initialization. Boot Strap Processor (BSP) selection
CPU post-memory initialization. System Management Mode (SMM) initialization
Post-Memory North Bridge initialization is started
Post-Memory North Bridge initialization (North Bridge module specific)
Post-Memory North Bridge initialization (North Bridge module specific)
Post-Memory North Bridge initialization (North Bridge module specific)
Post-Memory South Bridge initialization is started
Post-Memory South Bridge initialization (South Bridge module specific)
Post-Memory South Bridge initialization (South Bridge module specific)
Post-Memory South Bridge initialization (South Bridge module specific)
OEM post memory initialization codes
Page 76 Express-HLE
Status Code Description
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x4F DXE IPL is started
PEI Error Codes
0x50 Memory initialization error. Invalid memory type or incompatible memory speed
0x51
0x52
Memory initialization error. SPD reading has failed
Memory initialization error. Invalid memory size or memory modules do not match.
Memory initialization error. No usable memory detected
Unspecified memory initialization error.
Memory not installed
Invalid CPU type or Speed
CPU mismatch
CPU self test failed or possible CPU cache error
CPU micro-code is not found or micro-code update is failed
0x5A
0x5B
Internal CPU error reset PPI is not available
0x5C-0x5F Reserved for future AMI error codes
S3 Resume Progress Codes
0xE0
0xE1
0xE2
0xE3
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
S3 Boot Script execution
Video repost
OS S3 wake vector call
0xE4-0xE7
0xE0
Reserved for future AMI progress codes
S3 Resume is stared (S3 Resume PPI is called by the DXE IPL)
S3 Resume Error Codes
0xE8
0xE9
S3 Resume Failed in PEI
S3 Resume PPI not Found
0xEA
0xEB
S3 Resume Boot Script Error
S3 OS Wake Error
0xEC-0xEF Reserved for future AMI error codes
Recovery Progress Codes
0xF0
0xF1
0xF2
0xF3
Recovery condition triggered by firmware (Auto recovery)
Recovery condition triggered by user (Forced recovery)
Recovery process started
Recovery firmware image is found
0xF4
0xF5-0xF7
Recovery firmware image is loaded
Reserved for future AMI progress codes
Recovery Error Codes
0xF8
0xF9
Recovery PPI is not available
Recovery capsule is not found
0xFA Invalid recovery capsule
0xFB – 0xFF Reserved for future AMI error codes
Express-HLE Page 77
8.2.4
PEI Beep Codes
# of Beeps Description
4
4
3
7
2
3
1
1
Memory not Installed
Memory was installed twice (InstallPeiMemory routine in PEI Core called twice)
Recovery started
DXEIPL was not found
DXE Core Firmware Volume was not found
Reset PPI is not available
Recovery failed
S3 Resume failed
8.2.5
DXE Status Codes
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
Status Code Description
0x60 DXE Core is started
0x61
0x62
NVRAM initialization
Installation of the South Bridge Runtime Services
0x63
0x64
CPU DXE initialization is started
CPU DXE initialization (CPU module specific)
CPU DXE initialization (CPU module specific)
CPU DXE initialization (CPU module specific)
CPU DXE initialization (CPU module specific)
PCI host bridge initialization
North Bridge DXE initialization is started
North Bridge DXE SMM initialization is started
North Bridge DXE initialization (North Bridge module specific)
North Bridge DXE initialization (North Bridge module specific)
North Bridge DXE initialization (North Bridge module specific)
North Bridge DXE initialization (North Bridge module specific)
North Bridge DXE initialization (North Bridge module specific)
South Bridge DXE initialization is started
South Bridge DXE SMM initialization is started
South Bridge devices initialization
South Bridge DXE Initialization (South Bridge module specific)
South Bridge DXE Initialization (South Bridge module specific)
South Bridge DXE Initialization (South Bridge module specific)
South Bridge DXE Initialization (South Bridge module specific)
Page 78 Express-HLE
Status Code Description
0x77
0x78
South Bridge DXE Initialization (South Bridge module specific)
ACPI module initialization
0x79 CSM initialization
0x7A – 0x7F Reserved for future AMI DXE codes
0x80 – 0x8F OEM DXE initialization codes
0x90 Boot Device Selection (BDS) phase is started
0x91
0x92
Driver connecting is started
PCI Bus initialization is started
0x93
0x94
0x95
PCI Bus Hot Plug Controller Initialization
PCI Bus Enumeration
PCI Bus Request Resources
0xAA
0xAB
0xAC
0xAD
0xAE
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
PCI Bus Assign Resources
Console Output devices connect
Console input devices connect
Super IO Initialization
USB initialization is started
USB Reset
USB Detect
USB Enable
0x9E – 0x9F Reserved for future AMI codes
0xA0 IDE initialization is started
0xA1
0xA2
IDE Reset
IDE Detect
0xA3
0xA4
0xA5
0xA6
IDE Enable
SCSI initialization is started
SCSI Reset
SCSI Detect
0xA7
0xA8
0xA9
SCSI Enable
Setup Verifying Password
Start of Setup
Reserved for ASL (see ASL Status Codes section below)
Setup Input Wait
Reserved for ASL (see ASL Status Codes section below)
Ready To Boot event
Legacy Boot event
Express-HLE Page 79
Status Code Description
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
Exit Boot Services event
Runtime Set Virtual Address MAP Begin
Runtime Set Virtual Address MAP End
Legacy Option ROM Initialization
System Reset
USB hot plug
PCI bus hot plug
Clean-up of NVRAM
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xB7 Configuration Reset (reset of NVRAM settings)
0xB8 – 0xBF Reserved for future AMI codes
0xC0 – 0xCF OEM BDS initialization codes
DXE Error Codes
0xD0
0xD1
0xD2
0xD3
CPU initialization error
North Bridge initialization error
South Bridge initialization error
Some of the Architectural Protocols are not available
PCI resource allocation error. Out of Resources
No Space for Legacy Option ROM
No Console Output Devices are found
No Console Input Devices are found
Invalid password
Error loading Boot Option (LoadImage returned error)
Boot Option is failed (StartImage returned error)
Flash update is failed
Reset protocol is not available
8.2.6
DXE Beep Codes
7
8
1
6
5
5
# of Beeps Description
4 Some of the Architectural Protocols are not available
No Console Output Devices are found
No Console Input Devices are found
Invalid password
Flash update is failed
Reset protocol is not available
Platform PCI resource requirements cannot be met
Page 80 Express-HLE
8.2.7
ACPI/ASL Checkpoint
Status Code Description
0x01
0x02
0x03
0x04
0x05
0x10
0x20
0x30
0x40
0xAC
0xAA
System is entering S1 sleep state
System is entering S2 sleep state
System is entering S3 sleep state
System is entering S4 sleep state
System is entering S5 sleep state
System is waking up from the S1 sleep state
System is waking up from the S2 sleep state
System is waking up from the S3 sleep state
System is waking up from the S4 sleep state
System has transitioned into ACPI mode. Interrupt controller is in PIC mode.
System has transitioned into ACPI mode. Interrupt controller is in APIC mode.
8.3
OEM-Reserved Checkpoint Ranges
Status Code Description
0x05 OEM SEC initialization before microcode loading
0x0A OEM SEC initialization after microcode loading
0x1D – 0x2A OEM pre-memory initialization codes
0x3F – 0x4E OEM PEI post memory initialization codes
0x80 – 0x8F OEM DXE initialization codes
0xC0 – 0xCF OEM BDS initialization codes
Express-HLE Page 81
9
Mechanical Information
9.1
Board-to-Board Connectors
To allow for different stacking heights, the receptacles for COM Express carrier boards are available in two heights: 5 mm and 8 mm. When
5 mm receptacles are chosen, the carrier board should be free of components.
Tyco 3-1827253-6
Foxconn QT002206-2131-3H
• 220-pin board-to-board connector with 0.5mm for a stacking height of 5 mm.
• This connector can be used with 5 mm through-hole standoffs (SMT type).
Tyco 3-6318491-6
Foxconn QT002206-4141-3H
• 220-pin board-to-board connector with 0.5mm for a stacking height of 8 mm.
• This connector can be used with 8 mm through-hole standoffs (SMT type).
Common Specifications
• Current capacity: 0.5A per pin
• Rated voltage: 50 VAC
• Insulation resistance: 100M or greater @ 500 VDC
• Temperature rating: -40°C ~ 85°C
• UL certification (ECBT2.E28476)
• Copper alloy (contacts)
• Housing: thermo-plastic molded compound (L.C.P.)
Page 82 Express-HLE
9.2
Thermal Solution
9.2.1
Heat Spreaders
The function of the heat spreader is to ensure an identical mechanical profile for all COM Express modules. By using a heat spreader, the thermal solution that is built on top of the module is compatible with all COM Express modules.
9.2.2
Heat Sinks
A heat sink can be used as a thermal solution for a specific COM Express module and can have a fan or be fanless, depending on the thermal requirements.
9.2.3
Installation
Install a heat spreader or heat sink using the following instructions.
Step 1: Before mounting the heatsink, install the required memory modules onto the SODIMM socket(s) on the COM Express module.
Step 2: Remove the protective membranes from the thermal pads.
Step 3: Assemble the heatsink onto the COM Express module.
Express-HLE Page 83
Step 4: Use the four M2.5, L=6mm screws provided to fasten the heatsink to the module.
Step 5: Place the COM Express module and heatsink assembly onto the connectors on the carrier board as shown.
Then press down on the module until it is firmly seated on the carrier board.
Step 6: Use the five M2.5, L=16mm screws provided to secure the COM Express module to the carrier board from the solder side.
Step 7: If you are installing a heatsink with a fan, plug the fan connector into the carrier board as shown.
Page 84 Express-HLE
9.3
Mounting Methods
There are several standard ways to mount the COM Express module with a thermal solution onto a carrier board. In addition to the choice of
5 mm or 8mm board-to-board connectors, there is the choice of Top and Bottom mounting. In Top mounting, the threaded standoffs are on the carrier board and the thermal solution is equipped with through-hole standoffs. In Bottom mounting, the threaded standoffs are on the thermal solution and the carrier board has through-hole standoffs.
Express-HLE Page 85
9.4
Standoff Types
The standoffs available for Top and Bottom mounting methods are shown below. Note that threaded standoffs are DIP type and throughhole standoffs are SMT type. Other types not listed are available upon request.
5mm through-hole standoff (SMT type)
P/N: 33-72000-0050
5mm threaded standoff (DIP type)
P/N: 33-72016-0050
8mm through-hole standoff (SMT type)
P/N: 33-72000-0080
8mm threaded standoff (DIP type)
P/N: 33-72015-0050
Page 86 Express-HLE
Safety Instructions
Read and follow all instructions marked on the product and in the documentation before you operate your system. Retain all safety and operating instructions for future use.
• Please read these safety instructions carefully.
• Please keep this User‘s Manual for later reference.
• Read the specifications section of this manual for detailed information on the operating environment of this equipment.
• When installing/mounting or uninstalling/removing equipment, turn off the power and unplug any power cords/cables.
• To avoid electrical shock and/or damage to equipment:
Keep equipment away from water or liquid sources.
Keep equipment away from high heat or high humidity.
Keep equipment properly ventilated (do not block or cover ventilation openings).
Make sure to use recommended voltage and power source settings.
Always install and operate equipment near an easily accessible electrical socket-outlet.
Secure the power cord (do not place any object on/over the power cord).
Only install/attach and operate equipment on stable surfaces and/or recommended mountings.
If the equipment will not be used for long periods of time, turn off and unplug the equipment from its power source.
• Never attempt to fix the equipment. Equipment should only be serviced by qualified personnel.
Express-HLE Page 87
Getting Service
Ask an Expert: http://askanexpert.adlinktech.com
ADLINK Technology, Inc.
Address: 9F, No.166 Jian Yi Road, Zhonghe District
New Taipei City 235, Taiwan
Tel: +886-2-8226-5877
Fax:
Email:
+886-2-8226-5717 [email protected]
Ampro ADLINK Technology, Inc.
Address: 5215 Hellyer Avenue, #110, San Jose, CA 95138, USA
Tel: +1-408-360-0200
Toll Free: +1-800-966-5200 (USA only)
Fax: +1-408-360-0222
Email: [email protected]
ADLINK Technology (China) Co., Ltd.
Address: 300 Fang Chun Rd., Zhangjiang Hi-Tech Park, Pudong New Area
Shanghai, 201203 China
Tel:
Fax:
+86-21-5132-8988
+86-21-5132-3588
Email: [email protected]
LiPPERT ADLINK Technology GmbH
Address: Hans-Thoma-Strasse 11, D-68163, Mannheim, Germany
Tel:
Fax:
+49-621-43214-0
+49-621 43214-30
Email: [email protected]
Please visit the Contact page at www.adlinktech.com
for information on how to contact the ADLINK regional office nearest you.
Page 88 Express-HLE
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