These submodules can be combined in a configurable manner to form a complex timer module that serves different application domains and different classes within one application domain. Because of this scalability and configurability the timer is called generic.

The scalability and configurability is reached with an architecture philosophy where dedicated hardware submodules are located around a central routing unit (called Advanced

Routing Unit (ARU)). The ARU can connect the submodules in a flexible manner. The connectivity is software programmable and can be configured during runtime.

Nevertheless, the GTM-IP is designed to unload the CPU or a peripheral core from a high interrupt load. Most of the tasks inside the GTM-IP can run -once setup by an external CPU- independent and in parallel to the software. There may be special situations, where the CPU has to take action but the goal of the GTM design was to reduce these situations to a minimum.

The hardware submodules have dedicated functionalities, e.g. there are timer input modules where incoming signals can be captured and characterized together with a notion of time. By combination of several submodules through the ARU complex functions can be established. E.g. the signals characterized at an input module can be routed to a signal processing unit where an intermediate value about the incoming signal frequency can be calculated.

The modules that help to implement such complex functions are called infrastructural components further on. These components are present in all GTM variants. However, the number of these components may vary from device to device.

Other submodules have a more general architecture and can fulfill typical timer functions, e.g. there are PWM generation units. The third class of submodules are those fulfilling a dedicated functionality for a certain application domain, e.g. the DPLL serves engine management applications. A fourth group of submodules is responsible for supporting the implementation of safety functions to fulfill a defined safety level. The fifth group is composed by the Interrupt Concentrator Module (ICM) in charge of interrupt services.

Each GTM-IP is build up therefore with submodules coming from those four groups. The application class is defined by the amount of components of those submodules integrated into the implemented GTM-IP.

The structure of this document is motivated out of the aforementioned submodule classes.

Chapter 2: GTM architecture describes the dedicated GTM-IP implementation this

specification is written for. It gives an overview about the implemented submodules.

The following Chapter 3: Advanced Routing Unit (ARU) up to

Chapter 9: Time Base Unit

(TBU) deal with the so called infrastructural components for routing, clock management and

common time base functions. Chapter 10: Timer Input Module (TIM) to

Chapter 12: ARUconnected Timer Output Module (ATOM) describe the signal input and output modules while

the following Chapter 13: Multi Channel Sequencer (MCS) explains the signal processing

and generation submodule.

Chapter 14: Memory Configuration (MCFG)

outlines a memory

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Preface RM0361 configuration module for the described signal processing and generation submodule. The next chapters provide a detailed description of application specific and safety related modules like the MAP, DPLL, SPE, CMP and MON submodules.

Chapter 18: Interrupt

Concentrator Module (ICM) describes a module that bundles several interrupts coming from

the other submodules and connect them to the outside world.

These submodule groups are shown in the following table.

Chapter

Table 1. Submodule groups

Submodule

Advanced Routing Unit (ARU)

Broadcast Module (BRC)

First In First Out Module (FIFO)

AEI-to-FIFO Data Interface (AFD)

FIFO-to-ARU Interface (F2A)

Clock Management Unit (CMU)

Time Base Unit (TBU)

Timer Input Module (TIM)

Timer Output Module (TOM)

ARU-connected Timer Output Module (ATOM)

Multi Channel Sequencer (MCS)

Memory Configuration Module (MCFG)

TIM0 Input Mapping Module (MAP)

Digital PLL (DPLL)

Sensor Pattern Evaluation Module (SPE)

Interrupt Concentrator Module (ICM)

Output Compare Unit (CMP)

Monitoring Unit (MON)

Group

Infrastructural components

IO Modules

Signal generation and processing

Infrastructural component for MCS

Dedicated

BLDC support

Interrupt services

Safety features

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2.1 Overview

As already mentioned in Chapter 1: Preface the GTM-IP forms a generic timer platform that

serves different application domains and different classes within these application domains.

Depending on these multiple requirements of application domains multiple device configurations with different count of submodules (i.e. ATOM, BRC, MCS, PSM, SPE, TIM,

TOM) and different count of channel per submodule (if applicable) are possible.

The configuration (i.e. the count of submodules and the register map) of a specific GTM-IP configuration is detailed in the document called Appendix B (see

Section 22.3: References ).

In this section as an example of possible device configurations the GTM-IP_103

implementation is outlined. The architecture of the GTM-IP_103 is depicted in Figure 1

Please note, that the size of the submodules in the figure does not reflect the physical size of the modules in the implementation.

The device dependent configuration (i.e. the count of submodules and channels per submodule) is listed in the device specific Appendix B of this document (

Section 22.3:

References ).

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The central component of the GTM-IP is the Advanced Routing Unit (ARU) where most of the submodules are located around and connected to. This ARU forms together with the

Broadcast (BRC) and the Parameter Storage Module (PSM) the infrastructural part of the

GTM. The ARU is able to route data from a connected source submodule to a connected destination submodule. The routing is done in a deterministic manner with a round-robin scheduling scheme of connected channels which receive data from ARU and with a worst case round-trip time.

The routed data word size of the ARU is 53 bits. The data word can logically be split into three parts. These parts are shown in

Figure 2 . Bits 0 to 23 and bits 24 to 47 typically hold

data for the operation registers of the GTM-IP. This can be for example the duty cycle and period duration of a measured PWM input signal or the output characteristic of an output

PWM to be generated. Another possible content of Data0 and Data1 can be two 24-bit values of the GTM-IP time bases TBU_TS0, TBU_TS1 and TBU_TS2. Bits 48 to 52 can contain control bits to send control information from one submodule to another. These ARU

Control Bits (ACB) can have a different meaning for different submodules.

It is also possible to route data from a source to a destination and the destination can act later on as source for another destination. These routes through the GTM-IP are further on

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RM0361 GTM architecture called data streams . For a detailed description of the ARU submodule please refer to

Chapter 3: Advanced Routing Unit (ARU)

Figure 2. ARU data word description

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The BRC is able to distribute data from one source module to more than one destination modules connected to the ARU. The PSM submodule consists of three subunits, the AEI-to-

FIFO Data Interface (AFD), FIFO-to-ARU Interface (F2A) and the FIFO itself. The PSM can serve as a data storage for incoming data characteristics or as parameter storage for outgoing data. This data is stored in a RAM that is logically located inside the FIFO subunit, but physically the RAM is implemented and integrated by the silicon vendor with his RAM implementation technology. Therefore, the GTM-IP provides the interface to the RAM at its module boundary. The AFD subunit is the interface between the FIFO and the GTM SoC system bus interface AEI (please see

Section 2.2.1: GTM-IP generic bus interface (AEI)

for detailed discussion). The F2A subunit is the interface between the FIFO subunit and the

ARU.

Signals are transferred into the GTM-IP at the Timer Input Modules (TIM). These modules are able to filter the input signals and annotate additional information. Each channel is for example able to measure pulse high or low times and the period of a PWM signal in parallel and route the values to ARU for further processing. The internal operation registers of the

TIM submodule are 24 bits wide.

The Clock Management Unit (CMU) serves up to 13 different clocks for the GTM and up to three external clock pins GTM_ECLK0...2

. It acts as a clock divider for the system clock.

The counters implemented inside other submodules are typically driven from this submodule. Please note, that the CMU clocks are implemented as enable signals for the counters while the whole system runs with the GTM global clock SYS_CLK . This global clock typically corresponds to the microcontroller bus clock the GTM-IP is connected to and should not exceed 100 MHz because of the power dissipation of the used transistors where the GTM is implemented with.

The Time Base Unit (TBU) provides up to three independent common time bases for the

GTM-IP. In general, the number of time bases depends on the implemented device. If three time bases are implemented, two of these time bases can also be clocked with the digital

PLL (DPLL) sub_inc1 c and sub_inc2c outputs. The DPLL generates the higher frequent clock signals sub_inc1 , sub_inc2 , sub_inc1c and sub_inc2c on behalf of the frequencies of up to two input signals. These two input signals can be selected out of six incoming signals from the TIM0 submodule. In this submodule the incoming signals are filtered and transferred to the MAP submodule where two of these six signals are selected for further processing inside the DPLL.

Signal outputs are generated with the Timer Output Modules (TOM) and the ARUconnected TOMs (ATOM). Each TOM channel is able to generate a PWM signal at its output. Because of the integrated shadow register even the generation of complex PWM outputs is possible with the TOM channels by serving the parameters with the CPU. It is possible to trigger TOM channels for a successor TOM submodule through a trigger line between TOM(x)_CH(15) and TOM(x+1)_CH(0). But to avoid long trigger paths the GTM-IP integrator can configure after which TOM submodule instance a register is placed into the

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GTM architecture RM0361 trigger signal chain. Each register results in one SYS_CLK cycle delay of the trigger signal.

Please refer to device specification of silicon vendor for unregistered trigger chain length.

In addition, each TOM submodule can integrate functions to drive one BLDC engine. This

BLDC support is established together with the TIM and Sensor Pattern Evaluation (SPE) submodule.

The ATOMs offer the additional functionality to generate complex output signals without

CPU interaction by serving these complex waveform characteristics by other submodules that are connected to the ARU like the PSM or Multi Channel Sequencer (MCS). While the internal operation and shadow registers of the TOM channels are 16-bit wide, the operation and shadow registers of the ATOM channels are 24-bit wide to have a higher resolution and to have the opportunity to compare against time base values coming from the TBU.

It is possible to trigger ATOM channels for a successor ATOM submodule through a trigger line between ATOM(x)_CH(7) and ATOM(x+1)_CH(0). But to avoid long trigger paths the

GTM-IP integrator can configure after which ATOM submodule instance a register is placed into the trigger signal chain. Each register results in one SYS_CLK cycle delay of the trigger signal. Please refer to device specification of silicon vendor for unregistered trigger chain length.

Together with the MCS the ATOM is able to generate an arbitrary predefined output sequence at the GTM-IP output pins. The output sequence is defined by instructions located in RAM connected to the MCS submodule. The instructions define the points were an output signal should change or to react on other signal inputs. The output points can be one or two time stamps (or even angle stamp in case of an engine management system) provided by the TBU. Since the MCS is able to read data from the ARU it is also able to operate on incoming data routed from the TIM. Additionally, the MCS can process data that is located in its connected RAMs. The MCS RAM is located logically inside the MCS while the silicon vendor has to implement its own RAM technology there.

The two modules Compare Module (CMP) and Monitor Module (MON) implement safety related features. The CMP compares two output channels of an ATOM or TOM and sends the result to the MON submodule were the error is signaled to the CPU. The MON module is also able to monitor the ARU and CMU activities.

In the described implementation the submodules of the GTM-IP have a huge amount of different interrupt sources. These interrupt sources are grouped and concentrated by the

Interrupt Concentrator Module (ICM) to form a much easier manageable bunch of interrupts that are visible outside of the GTM-IP.

On the GTM-IP top level there are some configurable signal connections from the signal output of the TOM, ATOM modules to the input signals of the TIM modules.

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Figure 3. GTM-IP_103 signal multiplex

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The next diagram gives an overview of the connectivity. The source selection is defined with the bit SRXx in the register GTM_TIM[y]_AUX_IN_SRC .

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2.2.1

In general the GTM-IP can be divided into four interface groups. Two interface groups represent the ports of the GTM-IP where incoming signals are assembled and outgoing signals are created. These interfaces are therefore connected to the GTM-IP input submodule TIM and to the GTM-IP output submodules TOM and ATOM.

Another interface is the bus interface where the GTM-IP can be connected to the SoC

system bus. This generic bus interface is described in more detail in Section 2.2.1: GTM-IP generic bus interface (AEI)

. The last interface is the interrupt controller interface. The GTM-

IP provides several interrupt lines coming from the various submodules. These interrupt lines are concentrated inside the ICM and have to be adapted to the dedicated microcontroller environment where each interrupt handling can look different. The interrupt concept is described in more detail in

Section 2.5: GTM-IP interrupt concept

GTM-IP generic bus interface (AEI)

The GTM-IP is equipped with a generic bus interface that can be widely adapted to different

SoC bus systems. This generic bus interface is called AE-Interface (AEI). The adaptation of the AEI to SoC buses is typically done with a bridge module translating the AEI signals to

36/558 DocID025070 Rev 1

RM0361 GTM architecture the SoC bus signals of the silicon vendor. The AEI bus signals are depicted in the following table.

Signal name

AEI_SEL

AEI_ADDR

AEI_PIPE

AEI_W1R0

AEI_WDATA

AEI_RDATA

AEI_READY

AEI_STATUS

I/O

Table 2. AEI bus signals

Description

I GTM-IP select line

GTM-IP address

AEI address phase signal

Read/write access

Write data bus

Read data bus

Data ready signal

AEI access status

Bit width

The AEI status signal may drive one of the following values:

AEI_STATUS

Table 3. AEI status signal

Description

No error

Illegal byte addressing

Illegal address access

Unsupported address

The signal value "00" is driven if no error occurred during AEI access.

The signal value "01" is driven if the bus address is not an integer multiple of 4 (byte addressing).

The signal value "11" is driven if the address is not handled in the GTM.

The signal value "10" is driven if an illegal write access to one of the following register is performed:

 Register is protected (for example protected by bit RF_PROT)

In case of an illegal write access signaled by the status "10", the register content will not be modified.

Reading registers will never return the status "10".

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Write access to following addresses returns status "10" under special conditions:



ARU_IRQ_FORCINT



ATOM[i]_CH[x]_CM0



ATOM[i]_CH[x]_CM1



ATOM[i]_CH[x]_SR0



ATOM[i]_CH[x]_SR1



ATOM[i]_CH[x]_RDADDR



ATOM[i]_CH[x]_IRQ_FORCINT



BRC_IRQ_FORCINT



BRC_SRC_[x]_ADDR (x=0...11)



CMP_IRQ_FORCINT



CMU_GCLK_NUM



CMU_GCLK_DEN



CMU_CLK[x]_CTRL (x=0...7)



CMU_ECLK_NUM



CMU_ECLK_DEN



CMU_FXCLK_CTRL



DPLL_ACT_STA



DPLL_OSW



DPLL_IRQ_FORCINT



DPLL_ID_PMTR_[x] (x=0...23

(a)

)



DPLL_INC_CNT1



DPLL_INC_CNT2



DPLL_TSAC[x] (x=0...23

(a)

)



DPLL_PSAC[x] (x=0...23

(a)

)



DPLL_ACB_[x] (x=0...5

(b)

)



F2A[i]_CH[x]_ARU_RD_FIFO



F2A[i]_CH[x]_STR_CFG



FIFO[i]_CH[x]_IRQ_FORCINT



GTM_IRQ_FORCINT



GTM_RST



SPE[i]_IRQ_FORCINT



TIM[i]_CH[x]_CNTS



TIM[i]_CH[x]_GPR1



TIM[i]_CH[x]_IRQ_FORCINT



TOM[i]_CH[x]_IRQ_FORCINT



MCS[i]_CH[x]_CTRL



MCS[i]_CH[x]_PC

RM0361 a. 31 for device 4.

b. 7 for device 4.

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GTM architecture



TOM[i]_CH[x]_IRQ_FORCINT



MCS[i]_CTRL



TBU_CH[x]_BASE



TBU_CH[x]_CTRL



MCS RAM during initialization



DPLL RAM during initialization

GTM-IP multi-master and multi-tasking support

To support multi-master and multi-task access to the registers of the GTM-IP a dedicated write-access scheme is used for critical control bits inside the IP that need such a mechanism. This can be for example a shared register where more than one channel can be controlled globally by one register write access. Such register bits are implemented inside the GTM-IP with a double bit mechanism, where the writing of '00' and '11' has no effect on the register bit and where '01' sets the bit and '10' resets the bit. If the CPU wants to read the status of the bit it always gets a '00' if the bit is reset and it gets a '11' if the bit is set.

2.3 ARU routing concept

One central concept of the GTM-IP is the routing mechanism of the ARU submodule for data streams. Each data word transferred between the ARU and its connected submodule is

53-bit wide. It is important to understand this concept in order to use the resources of the

GTM-IP effectively. Each module that is connected to the ARU may provide an arbitrary number of ARU write channels and an arbitrary number of ARU read channels. In the following, the ARU write channels are named data sources and the ARU read channels are named data destinations.

The concept of the ARU intends to provide a flexible and resource efficient way for connecting any data source to an arbitrary data destination. In order to save resource costs, the ARU does not implement a switch matrix, but it implements a data router with serialized connectivity providing the same interconnection flexibility.

Figure 5 shows the ARU data

routing principle. Data sources are marked with a green rectangle and the data destinations are marked with yellow rectangles. The dashed lines in the ARU depict the configurable connections between data sources and data destinations. A connection between a data source and a data destination is also called a data stream.

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2.3.1 Principle of data routing using ARU

Figure 5. ARU data routing

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The configuration of the data streams is realized according to the following manner: each data source has its fixed and unique source address. The fixed address of each data source is pointed out by the numbers in the green boxes of

Figure 5 . The address definitions of all

available data sources in the GTM-IP can be obtained from table specified in

Section 21.3:

ARU write address overview

. The connection from a specific data source to a specific data destination is defined by configuring the corresponding address of a data source in the

DocID025070 Rev 1

RM0361 GTM architecture desired data destination. The configured address of each data destination is pointed out by the numbers in the yellow boxes of

Figure 5 .

Normally, the destination is idle and waits for data from the source. If the source offers new data, the destination does a destructive read, processes the data and goes idle again. The same data is never read twice.

There is one submodule for which this destructive read access does not hold. This is the

BRC submodule configured in Maximum Throughput Mode. For a detailed description of this module please refer to

Chapter 4: Broadcast module (BRC) .

The functionality of the ARU is as follows: The ARU sequentially polls the data destinations of the connected modules in a round-robin order. If a data destination requests new data from its configured data source and the data source has data available, the ARU delivers the data to the destination and it informs both, the data source and destination that the data is transferred. The data source marks the delivered ARU data as invalid which means that the destination consumed the data.

It should be noted that each data source should only be connected to a single data destination. This is because the destinations consume the data. If two destinations would reference the same source one destination would consume the data before the other destination could consume it. Since the data transfers are blocking, the second destination would block until it receives new data from the source. If a data source should be connected to more than one data destination the submodule Broadcast (BRC) has to be used. On the other hand, the transfer from a data source to the ARU is also blocking, which means that the source channel can only provide new data to the ARU when an old data word is consumed by a destination. In order to speed up the process of data transfers, the ARU handles two different data destinations in parallel.

Following table gives an overview about the number of channels for the GTM-IP_103 variant used as a reference within this chapter.

Table 4. ARU data sources and destination for GTM-IP_103

Submodule Number of data sources Number of data destinations

ARU

DPLL

TIM 0-3

MCS 0-3

BRC

TOM

ATOM 0-4

PSM 0

ICM

CMP

MON

Total

223

116

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2.3.2

RM0361

ARU round trip time

The ARU uses a round-robin arbitration scheme with a fixed round trip time for all connected data destinations. This means that the time between two adjacent read requests resulting from a data destination channel always takes the round trip time, independently if the read request succeeds or fails.

Another important concept of the ARU is its blocking mechanism that is implemented for transferring data from a data source to a data destination. This mechanism is used by ARU

connected submodules to synchronize the submodules to the routed data streams. Figure 6

explains the blocking mechanism.

Figure 6. ARU blocking mechanism

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If a data destination requests data from a data source over the ARU but the data source does not have any data yet, it has to wait until the data source provides new data. In this case the submodule that owns the data destination may perform other tasks. When a data source produces new data faster than a data destination can consume the data the source raises an error interrupt and signals that the data could not be delivered in time. The new data is marked as valid for further transfers and the old data is overwritten.

In any case the round trip time for the ARU is always fixed for a specific device configuration.

Please refer to device specific Appendix B of this specification for detailed information (see

Section 22.3: References

One exception is the BRC submodule when configured in Maximum Throughput Mode.

Please refer to

Chapter 4: Broadcast module (BRC)

for a detailed description.

GTM-IP Clock and Time Base Management (CTBM)

Inside the GTM-IP several subunits are involved in the clock and time base management of the whole GTM.

Figure 7 shows the connections and sub blocks involved in these tasks.

The sub blocks involved are called Clock and Time Base Management (CTBM) modules further on.

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Figure 7. CTBM architecture diagram

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One important module of the CTBM is the Clock Management Unit (CMU) which generates up to13 clocks for the submodules of the GTM and up to three GTM external clocks

CMU_ECLK[z] (z: 0...2). For a detailed description of the CMU functionality and clocks please refer to

Chapter 8: Clock Management Unit (CMU)

The five (5) CMU_FXCLK[y] (y: 0...4) clocks are used by the TOM submodule for PWM generation. Up to eight (8) CMU_CLK[x] (x: 0...7) clocks can be used by other submodules of the GTM for signal generation.

Each of the Time Base Unit (TBU) channel can use one of the

CMU_CLK[x]

clocks as reference to generate a common time base for the GTM . Besides the CMU_CLK[x] signals, the TBU can use the compensated SUB_INC[i]c (i: 1,2) signals coming from the DPLL submodule for time base generation. This time base then typically represents an angle clock

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GTM architecture RM0361 for an engine management system. For the meaning of compensated ( SUB_INC[i]c ) and uncompensated ( SUB_INC[i] ) DPLL signals please refer to the DPLL

Chapter 16: Digital

PLL module (DPLL) . The

SUB_INC[i]c signals in combination with the two direction signal lines DIR[i] the TBU time base can be controlled to run forwards or backwards. The TBU

functionality is described in Chapter 9: Time Base Unit (TBU) .

In this device the TBU submodule generates the three time base signals TBU_TS0 ,

TBU_TS1 and TBU_TS2 which are widely used inside the GTM as common time bases for signal characterization and generation.

As stated before, the DPLL submodule provides the four clock signals SUB_INC[i] and

SUB_INC[i]c which can be seen as a clock multiplier generated out of the two input signal vectors TRIGGER and STATE coming from the MAP submodule. For a detailed description of the DPLL functionality please refer to

Chapter 16: Digital PLL module (DPLL)

The MAP submodule is used to select the TRIGGER and STATE signals for the DPLL out of six input signals coming from TIM0 submodule. Besides this, the MAP submodule is able to generate a TDIR (TRIGGER Direction) and SDIR (STATE Direction) signal for the DPLL and

TBU coming from the SPE0 and SPE1 signal lines. The direction signals are generated out of a defined input pattern. For a detailed description of the MAP submodule please refer to

Chapter 15: TIM0 input mapping module (MAP) .

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The submodules of the GTM-IP can generate thousands of interrupts on behalf of internal events. These interrupts are combined inside the Interrupt Concentrator Module (ICM) into interrupt groups. In these interrupt groups the GTM-IP submodule interrupt signals are bundled to a smaller set of interrupts. Out of these interrupt sets a smaller amount of interrupt signals is created and signaled outside of the GTM-IP as a signal

GTM_<MOD>_IRQ, whereas <MOD> identifies the name of the corresponding GTM-IP submodule.

Moreover, each output signal GTM_<MOD>_IRQ has a corresponding input signal

GTM_<MOD>_IRQ_CLR that can be used for clearing the interrupts. These input signals can be used by the surrounding microcontroller system as:

 Acknowledge signal from a DMA controller

 Validation signal from ADC

 Clear signal from an GTM-external interrupt controller to do an atomic clear while entering an ISR routine

The controlling of the individual interrupts is done inside the submodules. If a submodule consists of several submodule channels that are most likely to work independently from each other (like TIM, PSM, MCS, TOM, and ATOM), each submodule channel has its own interrupt control and status register set, named as interrupt set in the following. Other submodules (SPE, ARU, DPLL, BRC, CMP and global GTM functionality) have a common interrupt set for the whole submodule.

The interrupt set consists of four registers: The IRQ_EN register, the IRQ_NOTIFY register, the IRQ_FORCINT register, and the IRQ_MODE register. While the registers IRQ_EN ,

IRQ_NOTIFY, and IRQ_FORCINT signalize the status and allow controlling of each individual interrupt source within an interrupt set, the register IRQ_MODE configures the interrupt mode that is applied to all interrupts that belong to the same interrupt set.

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RM0361 GTM architecture

In order to support a wide variety of microcontroller architectures and interrupt systems with different interrupt signal output characteristics and internal interrupt handling the following four modes can be configured:

 Level mode

 Pulse mode

 Pulse-Notify mode

 Single-Pulse mode

Refer to the device reference manual (chapter GTM Integration, section Interrupt and DMA support) to know the interrupt mode used.

These interrupt modes are described in more details in the following subsections.

The register IRQ_EN allows the enabling and disabling of an individual interrupt within an interrupt set. Independent of the configured mode, only enabled interrupts can signalize an interrupts on its signal GTM_<MOD>_IRQ .

The register IRQ_NOTIFY collects the occurrence of interrupt events. The behavior for setting a bit in this register depends on the configured mode and thus it is described later on in the mode descriptions.

Independent of the configured mode any write access with value '1' to a bit in the register

IRQ_NOTIFY always clears the corresponding IRQ_NOTIFY bit.

Moreover, the enabling of a disabled interrupt sources with a write access to the register

IRQ_EN also clears the corresponding bit in the IRQ_NOTIFY register but only if the error interrupt source EIRQ_EN is disabled. However, if the enabling of a disabled interrupt is simultaneous to an incoming interrupt event, the interrupt event is dominant and the register

IRQ_NOTIFY is not cleared.

Additionally, each write access to the register IRQ_MODE , clears all bits in the

IRQ_NOTIFY register. It should be notified that the clearing of IRQ_NOTIFY is applied independently of the written data (e.g. no mode change).

Thus, a secure way for reconfiguring the interrupt mode of an interrupt set, is to disable all interrupts of the interrupt set with the register IRQ_EN , define the new interrupt mode by writing register IRQ_MODE , followed by enabling the desired interrupts with the register

IRQ_EN .

Thus, a secure way for reconfiguring the interrupt mode of an error interrupt set, is to disable all error interrupts of the error interrupt set with the register EIRQ_EN , define the new interrupt mode by writing register IRQ_MODE , followed by enabling the desired error interrupts with the register EIRQ_EN .

The register IRQ_FORCINT is used by software for triggering individual interrupts with a write access with value '1'. Since a write access to IRQ_FORCINT only generates a single pulse, IRQ_FORCINT is not implemented as a true register and thus any read access to

IRQ_FORCINT always results with a value of '0'.

It should be noted, that the mechanism for triggering interrupts with IRQ_FORCINT is globally disabled after reset. It has to be explicitly enabled by clearing the bit RF_PROT in the register GTM_CTRL

(see Section 2.9.3: Register GTM_CTRL )

For the modules AEI-bridge, BRC, FIFO, TIM, MCS, DPLL, SPE and CMP each interrupt may configured to raise instead of the normal interrupt an error interrupt if enabled by the corresponding error interrupt enable bit in register EIRQ_EN .

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Note:

RM0361

It is possible for one source to enable the normal interrupt and the error interrupt in parallel.

Because of both interrupt clear signals could reset the notify bit this is expected to cause problems in a system and therefore it is strongly recommended to not enable both interrupt types at the same point in time.

Similar to enabling an interrupt, the enabling of a disabled error interrupt source with a write access to the register EIRQ_EN also clears the corresponding bit in the IRQ_NOTIFY register only if the interrupt source IRQ_EN is disabled. However, if the enabling of a disabled error interrupt is simultaneous to an incoming interrupt event, the interrupt event is dominant and the register IRQ_NOTIFY is not cleared.

All enabled error interrupts are or-combined inside the ICM and assigned to the dedicated

GTM port gtm_err_irq . A corresponding input gtm_err_irq_clr allows the reset of this error interrupt from outside the GTM (hardware clear).

To be able to detect the module source of the error interrupt the ICM provides the register

ICM_IRQG_MEI . The error interrupt causing channel can be determined for the modules

FIFO, TIM and MCS by evaluating the ICM register ICM_IRQG_CEI0 to ICM_IRQG_CEI4 .

46/558

The default interrupt mode is the Level Interrupt Mode. In this mode each occurred interrupt event is collected in the register IRQ_NOTIFY , independent of the corresponding enable bit of register IRQ_EN and EIRQ_EN .

An interrupt event, which is defined as a pulse on the signal Int_out of

Figure 8 , may be

triggered by the interrupt source of the submodule or by software performing a write access to the corresponding register IRQ_FORCINT , with a disabled bit RF_PROT in register

GTM_CTRL .

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Figure 8. Level interrupt mode scheme

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A collected interrupt bit in register IRQ_NOTIFY may be cleared by a clear event, which is defined as a pulse on signal Clear of

Figure 8 . A clear event can be performed with a write

access with value '1' to the corresponding bit in the register IRQ_NOTIFY leading to a pulse on signals SW_clear. A clear event may also result from an externally connected signal

GTM_<MOD>_IRQ_CLR , which is routed to the signal HW_clear of

Figure 8

. However, the hardware clear mechanism is only possible, if the corresponding interrupt is enabled by register IRQ_EN .

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RM0361 GTM architecture

As the

Table 5

shows, interrupt events are dominant in the case of a simultaneous interrupt event and clear event.

Int_in

Table 5. Priority of interrupt events and clear events

Clear_in Int_out Clear_out

As it can be seen from the Figure 8

an occurred interrupt event is signaled as a constant signal level with value 1 to the signal IRQ_bit , if the corresponding interrupt is enabled in register IRQ_EN .

With exception of the submodules ARU and DPLL, the signal IRQ_bit is OR-combined with the neighboring IRQ_bit signals of the same interrupt set and they are routed as a signal

IRQ_line to the interrupt concentrator module (ICM). The interrupt signals IRQ_bit of the submodules DPLL and ARU are routed directly as a signal IRQ_line to the submodule ICM.

In some cases (submodules TOM and ATOM) the ICM may further OR-combine several

IRQ_line signals to an outgoing interrupt signal GTM_<MOD>_IRQ . In the other cases the

IRQ_line signals are directly connected to the outgoing signals GTM_<MOD>_IRQ, within the submodule ICM.

The signal IRQ_occurred is connected in a similar way as the signal IRQ_line , however this signal is used for monitoring the interrupt state of the register IRQ_NOTIFY in the registers of the ICM.

The additional error interrupt enable mechanism for level interrupt is shown below.

,54B)25&,17

Figure 9. Level interrupt scheme for modules AEI-bridge, BRC, FIFO, TIM, MCS,

DPLL, SPE, CMP

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2.5.2

RM0361

A collected interrupt bit in register IRQ_NOTIFY may be cleared by a clear event, which is defined as a pulse on signal Clear_out of

Figure 9 . A clear event can be performed with a

write access with value '1' to the corresponding bit in the register IRQ_NOTIFY leading to a pulse on signals SW_clear. A clear event may also result from externally connected signal

gtm_<MOD>_irq_clr

gtm_err_irq_clr

, which is routed as a

HW_clear

Clear_in

Figure 9 . However, the hardware clear mechanism is only possible, if the corresponding

interrupt or error interrupt is enabled by register IRQ_EN or EIRQ_EN .

As it can be seen from the figure an occurred interrupt event is signaled as a constant signal

level with value 1 to the signal IRQ_bit , if the corresponding interrupt is enabled in register

IRQ_EN .

Pulse interrupt mode

The Pulse interrupt mode behavior can be observed from Figure 10 .

,54B)25&,17

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Figure 10. Pulse interrupt mode scheme

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In Pulse Interrupt Mode each Interrupt Event will generate a pulse on the IRQ_bit signal if

IRQ_EN is enabled.

As it can be seen from the figure, the interrupt bit in IRQ_NOTIFY register is always cleared if IRQ_EN is enabled.

However, if an interrupt is disabled in the register IRQ_EN , an occurred interrupt event is captured in the register IRQ_NOTIFY , in order to allow polling for disabled interrupts by software.

Disabled interrupts may be cleared by an interrupt clear event.

In Pulse interrupt mode, the signal IRQ_occurred is always 0.

The additional error interrupt enable mechanism for pulse interrupt is shown below.

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,54B)25&,17

Figure 11. Pulse interrupt scheme for modules AEI-bridge, BRC, FIFO, TIM, MCS,

DPLL, SPE, CMP

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In pulse interrupt mode each interrupt event will generate a pulse on the EIRQ_bit signal if

EIRQ_EN is enabled.

As it can be seen from the figure, the interrupt bit in IRQ_NOTIFY register is always cleared if EIRQ_EN or IRQ_EN are enabled.

However, if an error interrupt is disabled in the register EIRQ_EN , an occurred error interrupt event is captured in the register IRQ_NOTIFY , in order to allow polling for disabled error interrupts by software.

Disabled error interrupts may be cleared by an error interrupt clear event.

In Pulse interrupt mode, the signal EIRQ_occurred is always 0.

In pulse-notify interrupt mode, all interrupt events are captured in the register IRQ_NOTIFY .

If an interrupt is enabled by the register IRQ_EN , each interrupt event will also generate a pulse on the IRQ_bit signal. The signal IRQ_occurred will be high if interrupt is enabled in register IRQ_EN and the corresponding bit of register IRQ_NOTIFY is set. The Pulse-notify

interrupt mode is shown in Figure 12

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,54B)25&,17

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Figure 12. Pulse-notify interrupt mode scheme

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The additional error interrupt enable mechanism for pulse-notify interrupt is shown below.

,54B)25&,17

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Figure 13. Pulse-notify interrupt scheme for modules AEI-bridge, BRC, FIFO, TIM,

MCS, DPLL, SPE, CMP

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In pulse-notify interrupt mode, all error interrupt events are captured in the register

IRQ_NOTIFY . If an error interrupt is enabled by the register EIRQ_EN , each error interrupt event will also generate a pulse on the EIRQ_bit signal. The signal EIRQ_occurred will be high if error interrupt is enabled in register EIRQ_EN and the corresponding bit of register

IRQ_NOTIFY is set. The Pulse-notify interrupt mode for error interrupts is shown in

Figure 13

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In single-pulse interrupt mode, an interrupt event is always captured in the register

IRQ_NOTIFY , independent of the state of IRQ_EN . However, only the first interrupt event of an enabled interrupt within a common interrupt set is forwarded to signal IRQ_line.

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RM0361 GTM architecture

Additional interrupt events of the same interrupt set cannot generate pulses on the signal

IRQ_line , until the corresponding bits in register IRQ_NOTIFY of enabled interrupts are cleared by a clear event. The IRQ_occurred signal line will be high, if the IRQ_EN and the

IRQ_NOTIFY register bits are set. The Single-pulse interrupt mode is shown in

Figure 14 .

The only exceptions are the modules ARU and DPLL. In these modules the IRQ_occurred bit of each interrupt is directly connected (without OR-conjunction of neighboring

IRQ_occurred bits) to the inverter for suppressing further interrupt pulses.

Figure 14. Single-pulse interrupt mode scheme

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To avoid unexpected IRQ behavior in the single pulse mode, all desired interrupt sources should be enabled by a single write access to IRQ_EN and the notification bits should be cleared by a single write access to the register IRQ_NOTIFY .

The additional error interrupt enable mechanism for single-pulse interrupt is shown below.

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GTM architecture RM0361

Figure 15. Single-pulse interrupt scheme for modules AEI-bridge, BRC, FIFO, TIM,

MCS, DPLL, SPE, CMP

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In single-pulse interrupt mode, an error interrupt event is always captured in the register

IRQ_NOTIFY , independent of the state of EIRQ_EN . However, only the first error interrupt event of an enabled error interrupt within a common error interrupt set is forwarded to signal

EIRQ_line.

Additional error interrupt events of the same error interrupt set cannot generate pulses on the signal EIRQ_line , until the corresponding bits in register IRQ_NOTIFY of enabled error interrupts are cleared by a clear event. The EIRQ_occurred signal line will be high, if the EIRQ_EN and the IRQ_NOTIFY register bits are set. The Single-pulse interrupt mode for error interrupts is shown in

Figure 15

To avoid unexpected EIRQ behavior in the single pulse mode, all desired error interrupt sources should be enabled by a single write access to EIRQ_EN and the notification bits should be cleared by a single write access to the register IRQ_NOTIFY .

The only exceptions are the modules ARU and DPLL. In these modules the EIRQ_occurred bit of each error interrupt is directly connected (without OR-conjunction of neighboring

EIRQ_occurred bits) to the inverter for suppressing further error interrupt pulses.

GTM-IP interrupt concentration method

As the interrupts are grouped inside the ICM, user software must access the ICM a first time in order to determine the interrupt set that triggered the interrupt. A second access to the responsible register IRQ_NOTIFY is then necessary to identify the interrupt source, serve it and to reset the interrupt flag in register IRQ_NOTIFY afterwards. Therefore, the interrupt flags are never reset by an access to the ICM. For a detailed description of the ICM

submodule please refer to Chapter 18: Interrupt Concentrator Module (ICM) .

2.6 GTM-IP software debugger support

For software debugger support the GTM-IP comes with several features. E.g. status register bits must not be altered by a read access from a software debugger. To avoid this behavior

52/558 DocID025070 Rev 1

RM0361 GTM architecture to reset a status register bit by software, the CPU has to write a '1' explicitly to the register bit to reset its content.

The

Table 6 describes the behavior of some GTM-IP registers with special functionality on

behalf of read accesses from the AEI bus interface.

AFD

TIM

Module

ATOM

Table 6. Register behavior in case of software debugger accesses

Register Description

AFD[i]_CH[x]_BUFFACC

TIM[i]_CH[x]_GPR0/1

ATOM[i]_CH[x]_SR0/1

The FIFO read access pointers are not altered on behalf of a debugger read access to this register.

The overflow bit is not altered in case of a debugger read access to this registers.

In SOMC mode a read access to this register by the debugger does not release the channel for a new compare/match event.

The GTM provides an external signal gtm_halt , which disables clock signal SYS_CLK for debugging purposes. If SYS_CLK is disabled, a connected debugger can read any GTM related register and the GTM internal RAMs using AEI. Moreover, the debugger can also perform write accesses to the internal RAMs and to all GTM related registers in order to enable advanced debugging features (e.g. modifications of register contents in single step mode).

2.7 GTM-IP programming conventions

To serve different application domains the GTM-IP is a highly configurable module with many configuration modes. In principle the submodules of the GTM-IP are intended to be configured at system start-up to fulfill certain functionality for the application domain the microcontroller runs in.

For example, a TIM input channel can be used to monitor an application specific external signal, and this signal has to be filtered. Therefore, the configuration of the TIM channel filter mode will be specific to the external signal characteristic. While it can be necessary to adapt the filter thresholds during runtime an adaptation of the filter mode during runtime is not reasonable. Thus, the change of the filter mode during runtime can lead to an unexpected behavior.

In general, the programmer has to be careful when reprogramming configuration registers of the GTM-IP submodules during runtime. It is recommended to disable the channels before reconfiguration takes place to avoid unexpected behavior of the GTM-IP.

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2.8 GTM-IP TOP-level configuration registers overview

GTM-IP TOP-level contains following configuration registers:

Register name

Table 7. GTM-IP TOP-level configuration registers

Description Details in section

GTM_REV

GTM_RST

GTM_CTRL

GTM_AEI_ADDR_XPT

GTM_IRQ_NOTIFY

GTM_IRQ_EN

GTM_EIRQ_EN

GTM_IRQ_FORCINT

GTM_IRQ_MODE

GTM_TIM[i]_AUX_IN_SRC (i= 0... n)

GTM-IP Version control register

GTM-IP Global reset register

GTM-IP Global control register

Section 2.9.1

Section 2.9.2

Section 2.9.3

GTM-IP AEI Timeout exception address register

Section 2.9.4

GTM-IP Interrupt notification register

Section 2.9.5

GTM-IP Interrupt enable register

GTM-IP Error interrupt enable register

Section 2.9.6

Section 2.9.12

GTM-IP Software interrupt generation register

Section 2.9.7

GTM-IP top level interrupts mode selection.

Please note that this mode selection is only valid for the three interrupts described in

Section 2.9.5: Register GTM_IRQ_NOTIFY

Section 2.9.8

GTM-IP TIM[i] module AUX_IN source selection register

Section 2.9.13

2.9 GTM-IP TOP-level configuration registers description

Address offset: see Appendix B Initial value: 0xXXXX_XXXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

DEV_CODE2 DEV_CODE1 DEV_CODE0 MAJOR MINOR NO STEP Bit

Mode

Initial value

0xX

0xXX

Bit

[24:31]

[20:23]

[16:19]

[12:15]

Table 8. GTM_REV field description

Description

STEP : Release step.

GTM Release step

NO : Delivery number.

Define delivery number of GTM-IP specification.

MINOR : Minor version number.

Define minor version of GTM-IP specification.

MAJOR : Major version number.

Define major version of GTM-IP specification

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Note:

Bit

[8:11]

[4:7]

[0:3]

Table 8. GTM_REV field description (continued)

Description

DEV_CODE0 : Device encoding digit 0.

Device encoding digit 0.

DEV_CODE1 : Device encoding digit 1.

Device encoding digit 1.

DEV_CODE2 : Device encoding digit 2.

Device encoding digit 2.

Note: The numbers are encoded in BCD. Values "A" - "F" are characters

See

Section 22.3: References

for reset value.

GTM architecture

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

0x000000 0

Bit

[0:30]

Table 9. GTM_RST field description

Description

RST

: GTM-IP reset.

0 = No reset action

1 = Initiate reset action for all submodules

Note: This bit is automatically cleared by hardware after it was written. Therefore, the register is always read as zero (0) by the software.

Note:

This bit is write protected by bit RF_PROT of Section 2.9.3

Reserved .

Note: Read as zero, should be written as zero.

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Address offset:

Bit

Mode

Initial value

Bit

[28:29]

[23:27]

[0:22] see Appendix B Initial value: 0x0000_0001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TO_VAL

0x000000

00000

0 1

Table 10. GTM_CTRL field description

Description

RF_PROT : RST and FORCINT protection.

0 = SW RST (global), SW interrupt FORCINT, and SW RAM reset functionality is enabled

1 = SW RST (global), SW interrupt FORCINT, and SW RAM reset functionality is disabled

TO_MODE

: AEI timeout mode.

0 = Observe: If timeout_counter=0 the address and rw signal in addition with timeout flag will be stored to the

GTM_AEI_ADDR_XPT

register. Following timeout_counter=0 accesses will not overwrite the first entry in the aei_addr_timeout register. Clearing the timeout flag/aei_status error_code will re enable the storing of a next faulty access.

1 = Abort: In addition to observe mode the pending access will be aborted by signaling an illegal module access on aei_status and sending ready. In case of a read deliver as data 0 by serving of next AEI accesses.

Reserved

Note:

Read as zero, should be written as zero.

TO_VAL

: AEI Timeout value.

Note:

These bits define the number of cycles after which a timeout event occurs. When

TO_VAL equals zero (0) the AEI timeout functionality is disabled.

Reserved .

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

29 30 31

Bit Reserved TO_ADDR

Mode

Initial value

0x000

0x00000

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Bit

[12:31]

[0:10]

GTM architecture

Table 11. GTM_AEI_ADDR_XPT field description

Description

TO_ADDR : AEI timeout address.

Note:

This bit field defines the AEI address for which the AEI timeout event occurred.

TO_W1R0 : AEI timeout read/write flag.

Note:

This bit defines the AEI Read/Write flag for which the AEI timeout event occurred.

Reserved .

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

29 30 31

Bit Reserved

Mode

Initial value

Bit

0x0000000 0 0 0 0

Table 12. GTM_IRQ_NOTIFY field description

Description

AEI_TO_XPT

: AEI timeout exception occurred.

0 = No interrupt occurred

1 =

AEI_TO_XPT

interrupt was raised by the AEI timeout detection unit

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

AEI_USP_ADDR

: AEI unsupported address interrupt.

0 = No interrupt occurred

1 = AEI_USP_ADDR interrupt was raised by the AEI interface

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

AEI_IM_ADDR:

AEI illegal module address interrupt.

0 = No interrupt occurred

1 = AEI_IM_ADDR interrupt was raised by the AEI interface

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Bit

[0:27]

RM0361

Table 12. GTM_IRQ_NOTIFY field description

Description

AEI_USP_BE: AEI Unsupported byte enable interrupt.

0 = No interrupt occurred

1 = AEI_USP_BE interrupt was raised by the AEI interface

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Reserved.

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:27]

0x0000000

Table 13. GTM_IRQ_EN field description

Description

AEI_TO_XPT_IRQ_EN: AEI_TO_XPT_IRQ

interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

AEI_USP_ADDR_IRQ_EN: AEI_USP_ADDR_IRQ

interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

AEI_IM_ADDR_IRQ_EN: AEI_IM_ADDR_IRQ interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

AEI_USP_BE_IRQ_EN: AEI_USP_BE_IRQ interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

Reserved.

Note:

Read as zero, should be written as zero.

0 0 0 0

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

29 30 31

Bit

Reserved

Mode

Initial value

Bit

[0:27]

0x0000000

Table 14. GTM_IRQ_FORCINT field description

Description

TRG_AEI_TO_XPT: Trigger AEI_TO_XPT_IRQ interrupt by software.

0 = No interrupt triggering

1 = Assert

AEI_TO_XPT_IRQ

interrupt for one clock cycle

Note:

This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of Section 2.9.3

TRG_AEI_USP_ADDR

: Trigger AEI_USP_ADDR_IRQ interrupt by software.

0 = No interrupt triggering

1 = Assert AEI_USP_ADDR_IRQ interrupt for one clock cycle

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of

Section 2.9.3

TRG_AEI_IM_ADDR : Trigger AEI_IM_ADDR_IRQ interrupt by software.

0 = No interrupt triggering

1 = Assert AEI_IM_ADDR_IRQ interrupt for one clock cycle

Note:

This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of

Section 2.9.3

TRG_AEI_USP_BE

: Trigger AEI_USP_BE_IRQ interrupt by software.

0 = No interrupt triggering

1 = Assert AEI_USP_BE_IRQ interrupt for one clock cycle

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of

Section 2.9.3

Reserved.

Note:

Read as zero, should be written as zero.

0 0 0 0

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Bit

Mode

Initial value

Reserved

Bit

[30:31]

[0:29]

0x0000000000

Table 15. GTM_IRQ_MODE field description

Description

IRQ_MODE : Interrupt strategy mode selection for the AEI timeout and address monitoring interrupts.

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5

Reserved.

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0xXX00_X00X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Bit

Mode

Initial value

Bit

0xXX

0x00 0 0x0 X 0x0 0 0 0x00

Table 16. GTM_BRIDGE_MODE field description

Description

BRG_MODE

: Defines the operation mode for the AEI bridge.

0 = AEI bridge operates in sync_bridge mode

1 = AEI bridge operates in async_bridge mode

Note: Reset value depends on the hardware configuration chosen by silicon vendor.

MSK_WR_RSP : Mask write response.

0 = Do not mask the write response

1 = Mask write response

0 X

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Bit

[24:29]

[20:21]

[16:18]

[8:14]

[0:7]

GTM architecture

Table 16. GTM_BRIDGE_MODE field description (continued)

Description

Reserved

Note:

Read as zero, should be written as zero.

MODE_UP_PGR : Mode update in progress.

0 = No update in progress.

1 = Update in progress.

BUFF_OVL

: Buffer overflow register.

0 = No buffer overflow occurred.

1 = Buffer overflow occurred.

Note: : A buffer overflow can occur while multiple aborts are issued by the external bus or a pipelined instruction is started while FBC = 0 (see GTM_BRIDGE_PTR1 register).

Reserved

Note:

Read as zero, should be written as zero.

SYNC_INPUT_REG : additional pipelined stage in synchronous bridge mode

0 = No additional pipelined stage implemented.

1 = additional pipelined stage implemented. All accesses in synchronous mode will be increased by one clock cycle.

Note:

Reset value depends on the hardware configuration chosen by silicon vendor.

Reserved

Note:

Read as zero, should be written as zero.

BRG_RST

: Bridge software reset.

0 = No bridge reset request.

1 = Bridge reset request.

Note:

This bit is cleared automatically after write.

Reserved

Note: Read as zero, should be written as zero.

BUFF_DPT

: Buffer depth of AEI bridge.

Signals the buffer depth of the GTM AEI bridge implementation.

Note: Reset value depends on the hardware configuration chosen by silicon vendor.

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

RSP_TRAN_RDY

0x00

FBC

0xXX

ABT_TRAN_PGR TRAN_IN_PGR FIRST_RSP_PTR NEW_TRAN_PTR

R R R R

0x0 0x0 0x0 0x0

Bit

[27:31]

[22:26]

[17:21]

[12:16]

[6:11]

[0:5]

Table 17. GTM_BRIDGE_PTR1 field description

Description

NEW_TRAN_PTR

: New transaction pointer.

Signals the actual value of the new transaction pointer.

FIRST_RSP_PTR

: First response pointer.

Signals the actual value of first response pointer.

TRAN_IN_PGR

: Transaction in progress pointer (acquire)

Transaction in progress pointer.

ABT_TRAN_PGR

: Aborted transaction in progress pointer.

Aborted transaction in progress pointer.

FBC

: Free buffer count.

Number of free buffer entries.

Note:

Initial value depends on the hardware configuration chosen by silicon vendor. (see

BUFF_DPT in GTM_BRIDGE_MODE register).

RSP_TRAN_RDY

: Response transactions ready.

Amount of ready response transactions.

Note: This register operates on the AEI_CLK domain.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TRAN_IN_PGR2 Bit

Mode

Initial value

0x0000000

0x0

Bit

[27:31]

[0:26]

Table 18. GTM_BRIDGE_PTR2 field description

Description

TRAN_IN_PGR2 : transaction in progress pointer (aquire2)

Transaction in progress pointer 2.

Reserved

Note:

Read as zero, should be written as zero.

Note:

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:27]

0x0000000

Table 19. GTM_EIRQ_EN field description

Description

AEI_TO_XPT_EIRQ_EN : AEI_TO_XPT_EIRQ error interrupt enable.

0 = Disable error interrupt, interrupt is not visible outside GTM-IP

1 = Enable error interrupt, interrupt is visible outside GTM-IP

AEI_USP_ADDR_EIRQ_EN : AEI_USP_ADDR_EIRQ error interrupt enable.

0 = Disable error interrupt, interrupt is not visible outside GTM-IP

1 = Enable error interrupt, interrupt is visible outside GTM-IP.

AEI_IM_ADDR_EIRQ_EN : AEI_IM_ADDR_EIRQ error interrupt enable.

0 = Disable error interrupt, interrupt is not visible outside GTM-IP

1 = Enable error interrupt, interrupt is visible outside GTM-IP

AEI_USP_BE_EIRQ_EN

: AEI_USP_BE_EIRQ error interrupt enable.

0 = Disable error interrupt, interrupt is not visible outside GTM-IP

1 = Enable error interrupt, interrupt is visible outside GTM-IP

Reserved

Note:

Read as zero, should be written as zero.

0 0 0 0

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[0:23]

0x000000

0 0 0 0 0 0 0 0

Table 20. GTM_TIM[i]_AUX_IN_SRC (i= 0... n) field description

Description

SRC_CH0

: Defines AUX_IN source of TIM[i] channel 0 x=0

0 = TOM Output selected TOM[a] channel [b] with a = (i* 8 +x) div 16; b = (i* 8 +x) mod 16;

1 = ATOM Output selected ATOM[i] channel[x]

SRC_CH1 : Defines AUX_IN source of TIM[i] channel 1 x=1, see bit 31

SRC_CH2

: Defines AUX_IN source of TIM[i] channel 2 x=2, see bit 31

SRC_CH3

: Defines AUX_IN source of TIM[i] channel 3 x=3, see bit 31

SRC_CH4

: Defines AUX_IN source of TIM[i] channel 4 x=4, see bit 31

SRC_CH5 : Defines AUX_IN source of TIM[i] channel 5 x=5, see bit 31

SRC_CH6 : Defines AUX_IN source of TIM[i] channel 6 x=6, see bit 31

SRC_CH7 : Defines AUX_IN source of TIM[i] channel 7 x=7, see bit 31

Reserved

Note: Read as zero, should be written as zero.

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Advanced Routing Unit (ARU)

3.1 Overview

The Advanced Routing Unit (ARU) is a flexible infrastructure component for transferring 

53- bit wide data (five control bits and two 24-bit values) between several submodules of the

GTM core in a configurable manner.

Since the concept of the ARU has already been described in

Section 2.3: ARU routing concept , this section only describes additional ARU features that can be used by the

software for configuring and debugging ARU related data streams.

Also the definition of 'streams' and 'channels' in the ARU context is done in

Section 2.3:

ARU routing concept

3.2 Special sources

Besides the addresses of the submodule related data sources as described in

Section 21.3:

ARU write address overview

, the ARU provides two special data sources that can be used for the configuration of data streams. These data sources are defined as follows:

Address 0x1FF: Data source that provides always a 53-bit data word with zeros. A read access to this memory location will never block a requesting data destination.

Address 0x1FE: Data source that never provides a data word. A read access to this memory location will always block a requesting data destination. This is the reset value of the read registers inside the data destinations.

Address 0x000: This address is reserved and can be used to bring data through the ARU registers ARU_DATA_H and ARU_DATA_L into the system by writing the write address

0x000 into the ARU_ACCESS register. This means that software test data can be brought into the GTM-IP by the CPU.

3.3 ARU access via AEI

Besides the data transfer between the connected submodules, there are two possibilities to access ARU data via the AEI.

The default ARU access incorporates the registers ARU_ACCESS , which is used for initiation of a read or write request and the registers ARU_DATA_H and ARU_DATA_L that provide the ARU data word to be transferred.

The status of a read or write transfer can be determined by polling specific bits in register

ARU_ACCESS . Furthermore the acc_ack bit in the interrupt notify register is set after the read or write access is performed to avoid data loss e.g. on access cancellation.

A pending read or write request may also be canceled by clearing the associated bit.

In the case of a read request, the AEI access behaves as a read request initiated by a data destination of a module. The read request is served by the ARU immediately when no other destination has a pending read request. This means, that an AEI read access does not take

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On the other hand, the AEI access has the lowest priority behind the ARU scheduler that serves the destination channels. Thus, in worst case, the read request is served after one round trip of the ARU, when all destination channels would request data at the same point in time.

In the case of the write request, the ARU provides the write data at the address defined by the ADDR bit field inside the ARU_ACCESS register.

To avoid data loss, the reserved ARU address 0x0 has to be used to bring data into the system. Otherwise, in case the address specified inside the ADDR bit field is defined for another submodule that acts as a source at the ARU data loss may occur and no deterministic behavior is guaranteed.

This is because the regular source submodule is not aware that its address is used by the

ARU itself to provide data to a destination.

It is guaranteed that the ARU write data is send to the destination in case both modules want to provide data at the same time.

3.4

The debug access mode enables to inspect routed data of configured data streams during runtime.

The ARU provides two independent debug channels, whereas each is configured by a dedicated ARU read address in register ARU_DBG_ACCESS0 and ARU_DBG_ACCESS1 respectively.

The registers ARU_DBG_DATA0_H and ARU_DBG_DATA0_L ( ARU_DBG_DATA1_H and ARU_DBG_DATA1_L ) provide read access to the latest data word that the corresponding data source sent through the ARU.

Any time when data is transferred through the ARU from a data source to the destination requesting the data the interrupt signal ARU_NEW_DATA0 _IRQ ( ARU_NEW_DATA1 _IRQ) is raised.

For advanced debugging purposes, the interrupt signal can also be triggered by software using the register ARU_IRQ_FORCINT .

Please note, that the debug mechanism should not be used by the application, when a HW-

Debugger is used to trace the ARU communication. In that case, the debug registers are used by the HW-Debugger to specify the ARU streams that should be traced.

ARU interrupt signals

The following table describes ARU interrupt signals.

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Signal

ARU_NEW_DATA0

_IRQ

ARU_NEW_DATA1

_IRQ

ACC_ACK_IRQ

Advanced Routing Unit (ARU)

Table 21. ARU interrupt signals

Description

Indicates that data is transferred through the ARU using debug channel

ARU_DBG_ACCESS0

Indicates that data is transferred through the ARU using debug channel

ARU_DBG_ACCESS1

ARU access acknowledge IRQ.

3.5

Register name

ARU_ACCESS

ARU_DATA_H

ARU_DATA_L

ARU_DBG_ACCESS0

ARU_DBG_DATA0_H

ARU_DBG_DATA0_L

ARU_DBG_ACCESS1

ARU_DBG_DATA1_H

ARU_DBG_DATA1_L

ARU_IRQ_NOTIFY

ARU_IRQ_EN

ARU_IRQ_FORCINT

ARU_IRQ_MODE

ARU configuration registers overview

The following table lists the ARU configuration registers. Refer to the GTM-IP specific version Appendix B for the address offsets (see

Section 22.3: References ).

Table 22. ARU configuration registers map

Description Details in section

ARU access register

ARU access register upper data word

ARU access register lower data word

Debug access channel 0

Debug access 0 transfer register upper data word

Debug access 0 transfer register lower data word

Debug access channel 0

Section 3.6.5

Section 3.6.6

Section 3.6.7

Debug access 1 transfer register upper data word

Debug access 1 transfer register lower data word

ARU Interrupt notification register

Section 3.6.8

Section 3.6.9

IRQ mode configuration register

Section 3.6.10

ARU Interrupt enable register

Section 3.6.11

ARU_NEW_DATA

_IRQ interrupt

Section 3.6.12

Section 3.6.13

3.6 ARU configuration registers description

Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved ADDR

Mode

Initial value

0x00000

0 0

000

RPw

0x1FE

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Bit

[23:31]

[20:22]

[0:17]

Table 23. ARU_ACCESS field description

Description

ADDR : ARU address

Define the ARU address used for transferring data

Note: For an ARU write request, the preferred address 0x0 has to be used.

Note:

A write request to the address 0x1FF (always full address) or 0x1FE (always empty address) is ignored and doesn't have any effect.

Note:

ARU address bits ADDR are only writable if RREQ and WREQ bits are zero

Reserved

Note:

Read as zero, should be written as zero.

RREQ : Initiate read request

0 = No read request is pending

1 = Set read request to source channel addressed by ADDR

Note:

This bit is cleared automatically after transaction. Moreover, it can be cleared by software to cancel a read request.

Note:

RREQ bit is only writable if WREQ bit is zero, so to switch from RREQ to WREQ a cancel request has to be performed before.

Note:

Configuring both RREQ and WREQ bits results in a read request, so RREQ bit will be set if the WREQ bit of the register isn't already set.

Note:

The ARU read request on address ADDR is served immediately when no other destination has actually a read request when the RREQ bit is set by CPU. In a worst case scenario, the read request is served after one round trip of the ARU, but this is only the case when every destination channel issues a read request at consecutive points in time.

WREQ

: Initiate write request

0 = No write request is pending

1 = Mark data in registers ARU_DATA_H and ARU_DATA_L as valid

Note:

This bit is cleared automatically after transaction. Moreover, it can be cleared by software to cancel a write request.

Note:

WREQ bit is only writable if RREQ bit is zero, so to switch from WREQ to RREQ a cancel request has to be performed before.

Note:

Configuring both RREQ and WREQ bits results in a read request, so WREQ bit will not be set

Note:

The data is provided at address ADDR. This address has to be programmed as the source address in the destination submodule channel. In worst case, the data is provided after one full ARU round trip.

Reserved

Note: Read as zero, should be written as zero.

Note: The register ARU_ACCESS can be used either for reading or for writing at the same point in time.

Configuring both read and write request bits results in a read request, if the write request bit inside the register isn't already set. The read request bit will be set but not the write request bit. The following table describes the important cases of the bit 12 (RREQ) and bit 13

(WREQ) of the ARU_ACCESS register.

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0 0

0 1

1 0

1 1

Advanced Routing Unit (ARU)

Table 24. ARU_ACCESS(13:12) truth table

Actual value of

ARU_ACCESS(13:12)

Next value of

ARU_ACCESS(13:12)

0 1

1 0

0 1

0 0

1 0

0 1

0 0 0 1

1 0 1 0

Comment

Cancel read request

Cancel write request

Unchanged register

Both read and write request results in a read request

As before but WREQ bit is already set -> unchanged register

3.6.2 ARU Data High register (ARU_DATA_H)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0000

0x0000000

Bit

[3:31]

[0:2]

Table 25. ARU_DATA_H field description

Description

DATA : Upper ARU data word

Note: Transfer upper ARU data word addressed by ADDR. The data bits 24 to 52 of an ARU word are mapped to the data bits 0 to 28 of this register

Reserved

Note: Read as zero, should be written as zero.

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3.6.3 ARU Data low register (ARU_DATA_L)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

DATA

0x0000000

Bit

[3:31]

[0:2]

Table 26. ARU_DATA_L field description

Description

DATA

: Lower ARU data word

Note: Transfer lower ARU data word addressed by ADDR. The data bits 0 to 23 of an ARU word are mapped to the data bits 0 to 23 of this register and the data bits 48 to 52 of an

ARU word are mapped to the data bits 24 to 28 of this register when data is read by the

CPU.

Note: For writing data into the ARU by the CPU the bits 24 to 28 are not transferred to bit 48 to 52 of the ARU word. Only bits 0 to 23 are written to bits 0 to 23 of the ARU word

Reserved

Note: Read as zero, should be written as zero.

3.6.4 ARU Debug Access 0 register (ARU_DBG_ACCESS0)

Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

0x1FE

Bit

[23:31]

[0:22]

Table 27. ARU_DBG_ACCESS0 field description

Description

ADDR

: ARU debugging address

Note:

Define address of ARU debugging channel 0.

Reserved

Note:

Read as zero, should be written as zero.

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3.6.5 ARU Debug Data0 High register (ARU_DBG_DATA0_H)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0

DATA

0x0000000

Bit

[3:31]

[0:2]

Table 28. ARU_DBG_DATA0_H field description

Description

DATA

: Upper debug data word

Note: Transfer upper ARU data word addressed by register DBG_ACCESS0 . The data bits 24 to 52 of an ARU word are mapped to the data bits 0 to 28 of this register.

Note: The interrupt ARU_NEW_DATA0_IRQ is raised if a new data word is available.

Reserved

Note:

Read as zero, should be written as zero.

3.6.6 ARU Debug Data0 Low register (ARU_DBG_DATA0_L)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0x0

0x0000000

Bit

[3:31]

[0:2]

Table 29. ARU_DBG_DATA0_L field description

Description

DATA : Lower debug data word

Note: Transfer lower ARU data word addressed by register DBG_ACCESS0 .The data bits 0 to 23 of an ARU word are mapped to the data bits 0 to 23 of this register and the data bits 48 to 52 of an ARU word is mapped to the data bits 24 to 28 of this register.

Note: The interrupt ARU_NEW_DATA0_IRQ is raised if a new data word is available.

Reserved

Note: Read as zero, should be written as zero.

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3.6.7 ARU Debug Access 1 register (ARU_DBG_ACCESS1)

Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

0x1FE

Bit

[23:31]

[0:22]

Table 30. ARU_DBG_ACCESS1 field description

Description

ADDR

: ARU debugging address

Note: Define address of ARU debugging channel 1.

Reserved

Note: Read as zero, should be written as zero.

3.6.8 ARU Debug Data1 High register (ARU_DBG_DATA1_H)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0x0

0x0000000

Bit

[3:31]

[0:2]

Table 31. ARU_DBG_DATA1_H field description

Description

DATA : Upper debug data word

Note: Transfer upper ARU data word addressed by register DBG_ACCESS1 . The data bits 24 to 52 of an ARU word are mapped to the data bits 0 to 28 of this register

Note: The interrupt ARU_NEW_DATA1_IRQ is raised if a new data word is available.

Reserved

Note: Read as zero, should be written as zero.

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3.6.9 ARU Debug Data1 Low register (ARU_DBG_DATA1_L)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0x0

0x0000000

Bit

[3:31]

[0:2]

Table 32. ARU_DBG_DATA1_L field description

Description

DATA : Lower debug data word

Note:

Transfer lower ARU data word addressed by register

DBG_ACCESS1

.The data bits 0 to 23 of an ARU word are mapped to the data bits 0 to 23 of this register and the data bits 48 to 52 of an ARU word is mapped to the data bits 24 to 28 of this register.

Note: The interrupt ARU_NEW_DATA1_IRQ is raised if a new data word is available.

Reserved

Note: Read as zero, should be written as zero.

3.6.10 ARU IRQ Notification register (ARU_IRQ_NOTIFY)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:28]

0x00000000 0 0 0

Table 33. ARU_IRQ_NOTIFY field description

Description

NEW_DATA0 : Data was transferred for addr ARU_DBG_ACCESS0

0 = No interrupt occurred

1 = ARU_NEW_DATA0_IRQ interrupt was raised by the ARU

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

NEW_DATA1

: Data was transferred for addr ARU_DBG_ACCESS1

0 = No interrupt occurred

1 = ARU_NEW_DATA1_IRQ interrupt was raised by the ARU

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACC_ACK

: AEI to ARU access finished, on read access data are valid

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Reserved

Note:

Read as zero, should be written as zero.

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3.6.11 ARU IRQ Enable register (ARU_IRQ_EN)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:28]

0x00000000

Table 34. ARU_IRQ_EN field description

Description

NEW_DATA0_IRQ_EN : ARU_NEW_DATA0_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

NEW_DATA1_IRQ_EN

: ARU_NEW_DATA1_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

ACC_ACK_IRQ_EN

: ACC_ACK_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

Reserved

Note: Read as zero, should be written as zero.

0 0 0

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3.6.12 ARU Force IRQ register (ARU_IRQ_FORCINT)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[0:28]

0x00000000

Table 35. ARU_IRQ_FORCINT field description

Description

TRG_NEW_DATA0

: Trigger new data 0 interrupt

0 = corresponding bit in status register will not be forced

1 = Assert corresponding field in ARU_IRQ_NOTIFY register

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_NEW_DATA1 : Trigger new data 1 interrupt

0 = corresponding bit in status register will not be forced

1 = Assert corresponding field in ARU_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_ACC_ACK

: Trigger ACC_ACK interrupt

0 = corresponding bit in status register will not be forced

1 = Assert corresponding field in ARU_IRQ_NOTIFY register

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

Reserved

Note:

Read as zero, should be written as zero.

0 0 0

3.6.13 ARU IRQ Mode register (ARU_IRQ_MODE)

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000000 XX

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Bit

[30:31]

[0:29]

Table 36. ARU_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note:

Read as zero, should be written as zero.

RM0361

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4 Broadcast module (BRC)

Broadcast module (BRC)

4.1 Overview

Since each write address for the submodule channels of the GTM-IP that are able to write to the ARU can only be read by a single module, it is impossible to provide a data stream to different modules in parallel (This statement holds not for sources, which do not invalidate their data after the data were read by any consumer, e.g. DPLL).

To overcome this issue for regular modules, the submodule Broadcast (BRC) enables to duplicate data streams multiple times.

The BRC submodule provides 12 input channels as well as 22 output channels.

In order to clone an incoming data stream, the corresponding input channel can be mapped to zero or more output channels.

When mapped to zero no channel is read.

To destroy an incoming data stream, the EN_TRASHBIN bit inside the

BRC_SRC_[x]_DEST register has to be set.

The total number of output channels that are assigned to a single input channel is variable.

However, the total number of assigned output channels must be less than or equal to 22.

As it is the case with all other submodules connected to the ARU, the input channels can read arbitrary ARU address locations and the output channels provide the broadcast data to fixed ARU write address locations.

The associated write addresses for the BRC submodule are fixed and can be obtained from

Chapter 21: Appendix A

The read address for each input channel is defined by the corresponding register

BRC_SRC_[x]_ADDR (x: 0...11).

The mapping of an input channel to several output channels is defined by setting the appropriate bits in the register BRC_SRC_[x]_DEST (x: 0...11). Each output channel is represented by a single bit in the register BRC_SRC_[x]_DEST . The address of the output channel is defined in

Chapter 21: Appendix A

If no output channel bit is set within a register BRC_SRC_[x]_DEST , no data is provided to the corresponding ARU write address location from the defined read input specified by

BRC_SRC_[x]_ADDR . This means that the channel does not broadcast any data and is disabled (reset state).

Besides the possibility of mapping an input channel to several output channels, the bit

EN_TRASHBIN of register BRC_SRC_[x]_DEST may be set, which results in dropping an incoming data stream. In this case the data of an input channel defined by

BRC_SRC_[x]_ADDR is consumed by the BRC module and not routed to any succeeding submodule. In consequence, the output channels defined in the register

BRC_SRC_[x]_DEST are ignored. Therefore, the bits 0 to 21 are set to zero (0) when trash bin functionality is enabled.

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In general, the BRC submodule can work in two independent operation modes. In the first operation mode the data consistency is guaranteed since a BRC channel requests only new data from a source when all destination channels for the BRC have consumed the old data value. This mode is called Data Consistency Mode (DCM).

In a second operation mode the BRC channel always requests data from a source and distributes this data to the destination regardless whether all destinations have already consumed the old data. This mode is called Maximum Throughput Mode (MTM).

MTM ensures that always the newest available data is routed through the system, while it is not guaranteed data consistency since some of the destination channels can be provided with the old data while some other destination channels are provided with the new data. If this is the case, the data inconsistency detected interrupt BRC_DID_IRQ[x] is raised but the channel continues to work.

Furthermore in MTM mode it is guaranteed that it is not possible to read a data twice by a read channel. This is blocked.

The channel mode can be configured inside the BRC_SRC_[x]_ADDR register.

To avoid invalid configurations of the registers BRC_SRC_[x]_DEST , the BRC also implements a plausibility check for these configurations. If the software assigns an already used output channel to a second input channel, BRC performs an auto correction of the lastly configured register BRC_SRC_[x]_DEST and it triggers the interrupt

BRC_DEST_ERR .

Consider the following example for clarification of the auto correction mechanism. Assume that the following configuration of the 22 lower significant bits for the registers

BRC_SRC_[x]_DEST :

BRC_SRC_0_DEST : 00 0000 0000 1000 1000 0000 (binary)

BRC_SRC_1_DEST: 00 0000 0000 0100 0000 0100 (binary)

BRC_SRC_2_DEST: 00 0000 0000 0001 0100 0010 (binary)

BRC_SRC_3_DEST: 00 0000 0000 0010 0001 1001 (binary)

If the software overwrites the value for register BRC_SRC_2_DEST with

BRC_SRC_2_DEST : 00 0000 0000 1001 0010 0010 (binary)

(changed bits are underlined), then the BRC releases a BRC_DEST_ERR interrupt since bit

11 (counting from right ) is already assigned in register BRC_SRC_0_DEST . The auto correction forces bit 11 to be cleared. The modifications of the bits 5 and 6 are accepted, since there is no violation with previous configurations. So the result of the write access mentioned above results in the following modified register configuration:

BRC_SRC_2_DEST : 00 0000 0000 0001 0010 0010 (binary)

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For debug purposes, the interrupt BRC_DEST_ERR can also be released by writing to register BRC_IRQ_FORCINT . Nevertheless, the interrupt has to be enabled to be visible outside of the GTM-IP.

4.3 BRC interrupt signals

Interrupt signals are defined in following table.

Signal

BRC_DEST_ERR_IRQ

BRC_DID_IRQ [x]

Table 37. BRC interrupt signals

Description

Indicating configuration errors for BRC module

Data inconsistency occurred in MTM mode (x: 0...11)

4.4

Register name

BRC_SRC_[x]_ADDR

BRC_SRC_[x]_DEST

BRC_IRQ_NOTIFY

BRC_IRQ_EN

BRC_EIRQ_EN

BRC_IRQ_FORCINT

BRC_RST

BRC_IRQ_MODE

BRC configuration registers overview

Following table shows the list of BRC configuration registers. Refer to the Appendix B of the

GTM-IP used for the address offsets.

Table 38. BRC configuration registers

Description Details in section

Read address for input channel x (x: 0...11)

Section 4.5.1

Destination channels for input channel x (x: 0...11)

Section 4.5.2

BRC interrupt notification register

BRC interrupt enable register

Section 4.5.3

Section 4.5.4

BRC error interrupt enable register

Section 4.5.7

Section 4.5.5

Software reset

IRQ mode configuration register

Section 4.5.8

Section 4.5.6

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4.5 BRC configuration registers description

4.5.1 BRC Source x Address register, x:0...11 (BRC_SRC_[x]_ADDR)

Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved ADDR

Bit

[23:31]

[20:22]

[0:18]

0x00000 0

000

RPw

0x1FE

Table 39. BRC_SRC_[x]_ADDR field description

Description

ADDR : Source ARU address. Define an ARU read address used as data source for input channel x (x: 0...11).

Note: this bit field is only writable if channel is disabled.

Reserved

Note: Read as zero, should be written as zero.

BRC_MODE

: BRC Operation mode select.

0 = Consistency Mode (DCM) selected

1 = Maximum Throughput Mode (MTM) selected

Note: this bit field is only writable if channel is disabled.

Reserved

Note: Read as zero, should be written as zero.

4.5.2 BRC Source x to Destination register, x:0...11 (BRC_SRC_[x]_DEST)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

0x00

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Note:

Bit

[0:8]

Table 40. BRC_SRC_[x]_DEST field description

Description

EN_DEST0 : Enable BRC destination address 0

0 = Destination address 0 not mapped to source BRC_SRC_[x]_ADDR

1 = Destination address 0 mapped to source BRC_SRC_[x]_ADDR

Note:

The destination address 0 for BRC channel is defined in section 21.3

EN_DEST1 : Enable BRC destination address 1, see bit 31.

EN_DEST2

: Enable BRC destination address 2, see bit 31.

EN_DEST3 : Enable BRC destination address 3, see bit 31.

EN_DEST4

: Enable BRC destination address 4, see bit 31.

EN_DEST5 : Enable BRC destination address 5, see bit 31.

EN_DEST6

: Enable BRC destination address 6, see bit 31.

EN_DEST7 : Enable BRC destination address 7, see bit 31.

EN_DEST8 : Enable BRC destination address 8, see bit 31.

EN_DEST9 : Enable BRC destination address 9, see bit 31.

EN_DEST10

: Enable BRC destination address 10, see bit 31.

EN_DEST11

: Enable BRC destination address 11, see bit 31.

EN_DEST12

: Enable BRC destination address 12, see bit 31.

EN_DEST13 : Enable BRC destination address 13, see bit 31.

EN_DEST14 : Enable BRC destination address 14, see bit 31.

EN_DEST15 : Enable BRC destination address 15, see bit 31.

EN_DEST16

: Enable BRC destination address 16, see bit 31.

EN_DEST17

: Enable BRC destination address 17, see bit 31.

EN_DEST18

: Enable BRC destination address 18, see bit 31.

EN_DEST19 : Enable BRC destination address 19, see bit 31.

EN_DEST22 : Enable BRC destination address 20, see bit 31.

EN_DEST21

: Enable BRC destination address 21, see bit 31.

EN_TRASHBIN

: Control trash bin functionality.

0 = Trash bin functionality disabled

1 = Trash bin functionality enabled

Note: When bit EN_TRASHBIN is enabled bits 0 to 21 are ignored for this input channel.

Therefore, the bits 0 to 21 are set to zero (0) when trash bin functionality is enabled.

Reserved

Note: Read as zero, should be written as zero.

The bits 0 to 21 are cleared by auto correction mechanism if a destination channel is assigned to multiple source channels.

When a BRC input channel is disabled (all EN_DESTx (x: 0...21) bits are reset to zero) the internal states are reset to their reset value.

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4.5.3 BRC IRQ Notification register (BRC_IRQ_NOTIFY)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[19:30]

[0:18]

0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 41. BRC_IRQ_NOTIFY field description

Description

DEST_ERR

: Configuration error interrupt for BRC submodule

0 = No BRC configuration error occurred

1 = BRC configuration error occurred

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

DIDx : Data inconsistency occurred in MTM mode, (x:0...11)

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Reserved

Note: Read as zero, should be written as zero.

4.5.4 BRC IRQ Enable register (BRC_IRQ_EN)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[19:30]

[0:18]

0x00000

0 0 0 0 0 0 0 0 0 0 0 0 0

Table 42. BRC_IRQ_EN field description

Description

DEST_ERR_IRQ_EN

: BRC_DEST_ERR_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

DID_ENx : DID interrupt enable, see bit 31 for description. (x: 0...11)

Reserved

Note: Read as zero, should be written as zero.

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4.5.5 BRC Force IRQ register (BRC_IRQ_FORCINT)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[19:30]

[0:18]

0x00000000

RA w

0 0 0 0 0 0 0 0 0 0 0 0 0

Table 43. BRC_IRQ_FORCINT field description

Description

TRG_DEST_ERR : Trigger destination error interrupt.

0 = corresponding bit in status register will not be forced

1 = Assert corresponding field in BRC_IRQ_NOTIFY register

Note: This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_DIDx : Trigger data inconsistency error interrupt, see bit 31 for description. (x: 0...11)

Reserved

Note: Read as zero, should be written as zero.

4.5.6 BRC IRQ Mode register (BRC_IRQ_MODE)

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

Bit

[30:31]

[0:29]

0x00000000

Table 44. BRC_IRQ_MODE field description

Description

IRQ_MODE

: IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note:

Read as zero, should be written as zero.

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4.5.7 BRC Error IRQ Enable register (BRC_EIRQ_EN)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[19:30]

[0:18]

0x0000_0000

0 0 0 0 0 0 0 0 0 0 0 0 0

Table 45. BRC_EIRQ_EN field description

Description

DEST_ERR_EN : BRC_DEST_ERR_EIRQ error interrupt enable

0 = Disable error interrupt, error interrupt is not visible outside GTM-IP

1 = Enable error interrupt, error interrupt is visible outside GTM-IP

DID_EIRQ_ENx

: BRC_DID_EIRQ error interrupt enable, see bit 31. (x: 0...11)

Reserved

Note:

Read as zero, should be written as zero.

4.5.8 BRC Software Reset register (BRC_RST)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

0x00000000

RA w

Bit

[0:30]

Table 46. BRC_RST field description

Description

TRST : Software reset

0 = No action

1 = Reset BRC

Note:

This bit is cleared automatically after write by CPU. The channel registers are set to their reset values and channel operation is stopped immediately.

Reserved

Note: Read as zero, should be written as zero.

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5 First In First Out module (FIFO)

First In First Out module (FIFO)

5.1 Overview

The FIFO unit is the storage part of the FIFO submodule. The F2A described in

Chapter 7:

FIFO to ARU unit (F2A) and the AFD described in

Chapter 6: AEI to FIFO data interface

(AFD) implement the interface part of the FIFO submodule to the ARU and the AEI bus.

Each FIFO unit embeds eight logical FIFOs also called FIFO channels. These logical FIFOs are configurable in the following manner:

 FIFO size (defines start and end address)

 FIFO operation modes (normal mode or ring buffer operation mode)

 Fill level control / memory region read protection

Each logical FIFO represents a data stream between the submodules of the GTM and the

microcontroller connected to AFD submodule (see Chapter 6: AEI to FIFO data interface

(AFD) ). The FIFO RAM counts 1 K words, where the word size is 29-bit. This gives the

freedom to program or receive 24-bit of data together with the five control bits inside an ARU data word.

The FIFO unit provides three ports for accessing its content. One port is connected to the

F2A interface, one port is connected to the AFD interface and one port has its own AEI bus interface (called direct AEI interface) .

The AFD interface has always the highest priority. Accesses to the FIFO from AFD interface and direct AEI interface in parallel - which means at the same time - is not possible, because both interfaces are driven from the same AEI bus interface of the GTM.

The priority between F2A and direct AEI interface can be defined by software. This can be done by using the register FIFO[i]_CH[x]_CTRL for all FIFO channels of the submodule.

The FIFO is organized as a single RAM that is also accessible through the FIFO direct AEI interface connected to one of the FIFO ports. To provide the direct RAM access, the RAM is mapped into the address space of the microcontroller. The addresses for accessing the

RAM via AEI can be found in

Section 22.3: References

After reset, the FIFO RAM isn't initialized by hardware.

The FIFO channels can be flushed individually. Each of the eight FIFO channels can be used whether in normal FIFO operation mode or in ring buffer operation mode.

Beside the possibility of flushing each FIFO channel directly, a write access to

FIFO[i]_CH[x]_END_ADDR or to FIFO[i]_CH[x]_START_ADDR will also flush the corresponding channel which means that the read and write pointer and also the fill level of the channel will be reset. In consequence of this existing data in the concerned FIFO channel are not longer valid- thereafter the channel is empty.

In normal FIFO operation mode the content of the FIFO is written and read in first-in first-out order, where the data is destroyed after it is delivered to the system bus or the F2A submodule (see

Chapter 7: FIFO to ARU unit (F2A) ).

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5.2.2

RM0361

The upper and lower watermark registers (registers FIFO[i]_CH[x]_UPPER_WM and

FIFO[i]_CH[x]_LOWER_WM ) are used for controlling the FIFO’s fill level. If the fill level declines the lower watermark or it exceeds the upper watermark, an interrupt signal is triggered by the FIFO submodule if enabled inside the FIFO[i]_IRQ_EN .

The interrupt signals are sending to the Interrupt Concentrator Module (ICM) (see

Chapter 18: Interrupt Concentrator Module (ICM)

. The ICM can also initiate specific DMA transfers.

Ring buffer operation mode

The ring buffer mode is a powerful tool to provide a continuous data or configuration stream to the other GTM submodules without CPU interaction. In ring buffer mode the FIFO provides a continuous data stream to the F2A submodule. The first word of the FIFO is delivered first and after the last word is provided by the FIFO to the ARU, the first word can be obtained again.

If in ring buffer mode the read pointer reaches the write pointer it will be set again to the configured start address. So the read pointer always rotates cyclic between the configured start address of the selected FIFO channel (first written data) and the write pointer which points to the last written data of the channel.

It is possible to add data via the AEI to FIFO interface (AFD) to the FIFO channel while running in ring buffer mode. The new written data will be added in the next ring buffer cycle.

It is recommended to fill the FIFO channel first before enabling the data stream in the FIFO to ARU interface (F2A).

There could be the requirement that the user must be able to change some data inside the continuous data stream to the GTM submodules or system bus. This is possible through direct memory access provided by the FIFO AEI interface.

Interrupt signals are defined in following table.

Table 47. FIFO interrupt signals

Signal

FIFO [i] _CH[x]_EMPTY

(1)

FIFO [i]

FIFO [i]

FIFO

[i]

_CH[x]_UPPER_WM

(1)

Description

Indicating FIFO channel x (x: 0...7) is empty.

Indicating FIFO channel x (x: 0...7) is full.

Indicating FIFO channel x (x: 0...7) reached lower watermark.

Indicating FIFO channel x (x: 0...7) reached upper watermark.

1. Where i: 0...number of FIFO elements in the selected GTM-IP implementation.

5.4 FIFO configuration registers overview

The following table lists the FIFO configurations registers. Refer to the Appendix B of the targeted GTM-IP implementation for the address offsets (see

Section 22.3: References ).

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Register name

FIFO[i]_CH[x]_CTRL

FIFO[i]_CH[x]_END_ADDR

FIFO[i]_CH[x]_START_ADDR

FIFO[i]_CH[x]_UPPER_WM

FIFO[i]_CH[x]_LOWER_WM

FIFO[i]_CH[x]_STATUS

FIFO[i]_CH[x]_FILL_LEVEL

FIFO[i]_CH[x]_WR_PTR

FIFO[i]_CH[x]_RD_PTR

FIFO[i]_CH[x]_IRQ_NOTIFY

FIFO[i]_CH[x]_IRQ_EN

FIFO[i]_CH[x]_EIRQ_EN

FIFO[i]_CH[x]_IRQ_FORCINT

FIFO[i]_CH[x]_IRQ_MODE

Table 48. FIFO configuration registers

Description Details in section

FIFO Channel x control register (x: 0...7)

FIFO Channel x end address register (x: 0...7)

FIFO Channel x start address register (x: 0...7)

FIFO Channel x upper watermark register (x: 0...7)

FIFO Channel x lower watermark register (x: 0...7)

FIFO Channel x status register (x: 0...7)

FIFO Channel x fill level register (x: 0...7)

FIFO Channel x write pointer register (x: 0...7)

Section 5.5.5

Section 5.5.6

Section 5.5.7

FIFO Channel x interrupt enable register (x: 0...7)

Section 5.5.8

FIFO Channel x read pointer register (x: 0...7)

Section 5.5.9

FIFO Channel x interrupt notification register (x: 0...7)

Section 5.5.10

Section 5.5.11

FIFO Channel x Error interrupt enable register (x: 0...7)

Section 5.5.14

FIFO Channel x register to force interrupt by software

(x: 0...7)

Section 5.5.12

FIFO Channel x IRQ mode control register (x: 0...7)

Section 5.5.13

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

0x00000000

RA w

0 0 0 0

Bit

Table 49. FIFO[i]_CH[x]_CTRL field description

Description

RBM

: Ring buffer mode enable

0 = Normal FIFO operation mode

1 = Ring buffer mode.

RAP

: RAM access priority

0 = FIFO ports have higher access priority than AEI-IF

1 = AEI-IF has higher access priority than FIFO ports

Note: RAP bit is only functional in register FIFO_0_CTRL. The priority is defined for all FIFO channels there

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Bit

[0:27]

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Table 49. FIFO[i]_CH[x]_CTRL field description (continued)

Description

FLUSH : FIFO Flush control

0 = Normal operation

1 = Execute FIFO flush (bit is automatically cleared after flush).

Note:

A FIFO Flush operation resets the FIFO[i]_CH[x]_FILL_LEVEL,

FIFO[i]_CH[x]_WR_PTR and FIFO[i]_CH[x]_RD_PTR registers to their initial values.

WULOCK

: RAM write unlock. Enable/disable direct RAM write access to the memory mapped

FIFO region.

0 = Direct RAM write access disabled

1 = Direct RAM write access enabled

Note:

Only the bit WULOCK of register FIFO[i]_CH0_CTRL enables/disables the direct RAM write access for all FIFO channel (whole FIFO RAM). The WULOCK bits of the other channels are writable but have no effect.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0XXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

0xXXX

Bit

[22:31]

[0:21]

Table 50. FIFO[i]_CH[x]_END_ADDR field description

Description

ADDR : End address for FIFO channel x, (x: 0...7)

Note: value for ADDR is calculated as ADDR = 128*(x+1) - 1

Note:

A write access will flush the regarding channel

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0XXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

0xXXX

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Bit

[22:31]

[0:21]

First In First Out module (FIFO)

Table 51. FIFO[i]_CH[x]_START_ADDR field description

Description

ADDR : Start address for FIFO channel x, (x: 0...7)

Note:

Initial value for ADDR is calculated as ADDR = 128*x

Note: A write access will flush the regarding channel

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0060

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ADDR Bit

Mode

Initial value

0x000000

0x60

Bit

[22:31]

[0:21]

Table 52. FIFO[i]_CH[x]_UPPER_WM field description

Description

ADDR

: Upper watermark address.

Note:

The upper watermark is configured as a relative fill level of the FIFO. ADDR must be in range: 

0 <= ADDR <= FIFO[i]_CH[x]_END_ADDR - FIFO[i]_CH[x]_START_ADDR. 

Initial value for ADDR is defined as ADDR = 0x60.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0020

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x000000

ADDR

0x20

Bit

[22:31]

[0:21]

Table 53. FIFO[i]_CH[x]_LOWER_WM field description

Description

ADDR

: Lower watermark address.

Note: The lower watermark is configured as a relative fill level of the FIFO. ADDR must be in range: 

0 <= ADDR <= FIFO[i]_CH[x]_END_ADDR - FIFO[i]_CH[x]_START_ADDR. 

Initial value for ADDR is defined as ADDR = 0x20.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0005

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

R R R R

0 1 0 1

Bit

0x0000000

Table 54. FIFO[i]_CH[x]_STATUS field description

Description

EMPTY

: FIFO is empty.

0 = Fill level > 0

1 = Fill level = 0

Note: Bit only applicable in normal mode.

FULL : FIFO is full.

0 = Fill level < FIFO[i]_CH[x]_END_ADDR - FIFO[i]_CH[x]_START_ADDR + 1

1 = Fill level = FIFO[i]_CH[x]_END_ADDR - FIFO[i]_CH[x]_START_ADDR + 1

Note:

Bit only applicable in normal mode

LOW_WM

: Lower watermark reached

0 = Fill level > lower watermark

1 = Fill level <= lower watermark

Note: Bit only applicable in normal mode

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Bit

[0:27]

First In First Out module (FIFO)

Table 54. FIFO[i]_CH[x]_STATUS field description (continued)

Description

UP_WM : Upper watermark reached

0 = Fill level < upper watermark

1 = Fill level >= upper watermark

Note:

Bit only applicable in normal mode

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

LEVEL

0x00

Bit

[21:31]

[0:20]

Table 55. FIFO[i]_CH[x]_FILL_LEVEL field description

Description

LEVEL

: Fill level of the current FIFO

Note:

LEVEL is in range: 

0 <= LEVEL <= FIFO[i]_CH[x]_END_ADDR - FIFO[i]_CH[x]_START_ADDR + 1. 

Register content is compared to the upper and lower watermark values for this channel to detect watermark over- and underflow.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0XXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

0xXXX

Bit

[22:31]

[0:21]

Table 56. FIFO[i]_CH[x]_WR_PTR field description

Description

ADDR

: Position of the write pointer

Note:

ADDR must be in range 0 <= ADDR <=1023. Initial value for ADDR is defined as 

ADDR = FIFO[i]_CH[x]_START_ADDR

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0XXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

ADDR

0xXXX

Bit

[22:31]

[0:21]

Table 57. FIFO[i]_CH[x]_RD_PTR field description

Description

ADDR

: Position of the read pointer

Note: ADDR must be in range 0 <= ADDR <=1023. Initial value for ADDR is defined as 

ADDR = FIFO[i]_CH[x]_START_ADDR

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0005

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:27]

0x0000000 0 1 0 1

Table 58. FIFO[i]_CH[x]_IRQ_NOTIFY field description

Description

FIFO_EMPTY

: FIFO is empty

0 = No interrupt occurred.

1 = FIFO is empty interrupt occurred.

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

FIFO_FULL

: FIFO is full. see bit 31.

FIFO_LWM

: FIFO Lower watermark was under-run. see bit 31.

FIFO_UWM : FIFO Upper watermark was over-run. see bit 31.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[0:27]

0x0000000

Table 59. FIFO[i]_CH[x]_IRQ_EN field description

Description

FIFO_EMPTY_IRQ_EN : interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP.

1 = Enable interrupt, interrupt is visible outside GTM-IP.

FIFO_FULL_IRQ_EN

: interrupt enable. see bit 31.

FIFO_LWM_IRQ_EN

: interrupt enable. see bit 31.

FIFO_UWM_IRQ_EN

: interrupt enable. see bit 31.

Reserved

Note:

Read as zero, should be written as zero.

0 0 0 0

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000000 0 0 0 0

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Bit

[0:27]

Table 60. FIFO[i]_CH[x]_IRQ_FORCINT field description

Description

TRG_FIFO_EMPTY : Force interrupt of FIFO empty status.

0 = corresponding bit in status register will not be forced

1 = Assert corresponding field in FIFO[i]_CH[i]_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note: This bit is cleared automatically after write.

TRG_FIFO_FULL

: Force interrupt of FIFO full status. see bit 31.

TRG_FIFO_LWM : Force interrupt of lower watermark. see bit 31.

TRG_FIFO_UWM

: Force interrupt of upper watermark. see bit 31.

Reserved

Note:

Read as zero, should be written as zero.

RM0361

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[30:31]

0x0000000

Table 61. FIFO[i]_CH[x]_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

DMA_HYSTERESIS

: Enable DMA hysteresis mode.

0 = Disable FIFO hysteresis for DMA access.

1 = Enable FIFO hysteresis for DMA access.

0 0 XX

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[0:27]

First In First Out module (FIFO)

Table 61. FIFO[i]_CH[x]_IRQ_MODE field description (continued)

Description

DMA_HYST_DIR : DMA direction in hysteresis mode

0 = DMA direction read in hysteresis mode.

1 = DMA direction write in hysteresis mode.

Note:

In the case of DMA writing data to a FIFO the DMA requests must be generated by the lower watermark. If the DMA hysteresis is enabled, the FIFO does not generate a new

DMA request until the upper watermark is reached.

Note: In the case of DMA reading data from FIFO the DMA requests must be generated by the upper watermark. If the DMA hysteresis is enabled, the FIFO does not generate a new

DMA request until the lower watermark is reached.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[0:27]

0x0000000 0 0 0 0

Table 62. FIFO[i]_CH[x]_EIRQ_EN (x:0...7) field description

Description

FIFO_EMPTY_EIRQ_EN : error interrupt enable

0 = Disable error interrupt, error interrupt is not visible outside GTM-IP.

1 = Enable error interrupt, error interrupt is visible outside GTM-IP.

FIFO_FULL_EIRQ_EN : interrupt enable. see bit 31.

FIFO_LWM_EIRQ_EN : interrupt enable. see bit 31.

FIFO_UWM_EIRQ_EN

: interrupt enable. see bit 31.

Note: In the case of DMA reading data from FIFO the DMA requests must be generated by the upper watermark. If the DMA hysteresis is enabled, the FIFO does not generate a new

DMA request until the lower watermark is reached.

Reserved

Note:

Read as zero, should be written as zero.

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6 AEI to FIFO data interface (AFD)

RM0361

6.1 Overview

The AFD submodule implements a data interface between the AEI bus and the FIFO submodule, which consists of eight logical FIFO channels.

The AFD submodule provides one buffer registers that are dedicated to the logical channels of the FIFO. Access to the corresponding FIFO channel is given by reading or writing this buffer registers AFD[i]_CH[x]_BUF_ACC .

An AEI write access to the buffer register where the corresponding fifo channel is full will be ignored. The data will be lost.

An AEI read access to the buffer register where the corresponding fifo channel is empty will be served with zero data.

6.2 AFD register overview

Following table lists the AFD configuration registers.

Register name

AFD[i]_CH[x]_BUF_ACC

Table 63. AFD register

Description

AFD FIFO x buffer access register (x: 0...7)

Details in section

Section 6.3.1

6.3 AFD register description

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0x0

0x0000000

Bit

[3:31]

[0:2]

Table 64. AFD[i]_CH[x]_BUF_ACC field description

Description

DATA : Read/write data from/to FIFO

Reserved

Note: Read as zero, should be written as zero.

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7 FIFO to ARU unit (F2A)

FIFO to ARU unit (F2A)

7.1 Overview

The F2A is the interface between the ARU and the FIFO submodule. Since the data width of the ARU (ARU word) is 53-bit (two 24-bit values and five control bits) and the data width of the FIFO is only 29-bit, the F2A has to distribute the data from and to the FIFO channels in a configurable manner.

The data transfer between FIFO and ARU is organized with eight different streams that are connected to the eight different channels of the corresponding FIFO module. A stream represents a data flow from/to ARU to/from the FIFO via the F2A.

The general definition of 'channels' and 'streams' in the ARU context is done in

Section 2.3:

ARU routing concept

Each FIFO channel can act as a write stream (data flow from FIFO to ARU) or as a read stream (data flow from ARU to FIFO).

Within these streams the F2A can transmit/receive the lower, the upper or both 24 bit values of the ARU together with the ARU control bits according to the configured transfer modes as described in

Section 7.2: Transfer modes

The F2A unit provides several transfer modes to map 29-bit data of the FIFO from/to 53-bit data of the ARU. E.g. it is configurable that the 24-bit FIFO data is written to the lower ARU data entry (means bits 0 to 23) or to the higher 24-bit ARU data entry (means bits 24 to 47).

Bits 24 to 28 of the FIFO data entry (the five control bits) are written/read in both cases to/from bits 48 to 52 of the ARU entry.

When both values of the ARU have to be stored in the FIFO the values are stored behind each other inside the FIFO if the FIFO is not full.

If there is only space for one 24-bit data word plus the five control bits, the F2A transfers one part of the 53 bits first and than waits for transferring the second part before new data is requested from the ARU.

When two values from the FIFO have to be written to one ARU location the words have to be located behind each other inside the FIFO.

The transfer to ARU is only established when both parts could be read out of the FIFO otherwise if only one 29-bit word was provided by the FIFO the F2A waits until the second part is available before the data is made available at the ARU.

Figure 16

shows the data ordering of the FIFO when both ARU values must be transferred between ARU and FIFO.

When reading from the ARU the F2A first writes the lower word to the FIFO.

In case of writing to the ARU the F2A reads the lower word first from the FIFO, thus the lower word must be written first to the FIFO through the AFD interface.

Please note, that the five control bits (bits 48 to 52 of the ARU data word) are duplicated as bits 24 to 28 of both FIFO words in case of reading from ARU.

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In the case of writing to the ARU, bits 24 to 28 of the last written FIFO word (the higher ARU word) are copied to bits 48 to 52 of the corresponding ARU location.

The transfer modes can be configured with the TMODE bits of registers

F2A[i]_CH[x]_STR_CFG (x: 0...7).

Figure 16. Data transfer of both ARU words between ARU and FIFO

GAPGMS00208

The following table lists the F2A configuration registers.

Register name

F2A[i]_ENABLE

F2A[i]_CH[x]_ARU_RD_FIFO

F2A[i]_CH[x]_STR_CFG

Table 65. F2A configuration registers

Description

F2A stream activation register

F2A read channel address register (x: 0...7)

F2A stream x configuration register (x: 0...7)

Details in section

Section 7.4.1

Section 7.4.2

Section 7.4.3

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

Bit

[30:31]

[28:29]

[26:27]

[24:25]

[22:23]

[20:21]

[18:19]

[16:17]

[0:15]

0x0000

Table 66. F2A[i]_ENABLE field description

Description

STR0_EN : Enable/disable stream 0

Write of following double bit values is possible:

00 = Don't care, bits 30:31 will not be changed

01 =Stream 0 is disabled and internal states are reset

10 = Stream 0 is enabled

11 = Don't care, bits 30:31 will not be changed

Read of following double values means:

00 = Stream disabled

11 = Stream enabled

STR1_EN : Enable/disable stream 1

See bits [30:31]

STR2_EN : Enable/disable stream 2

See bits [30:31]

STR3_EN : Enable/disable stream 3

See bits [30:31]

STR4_EN : Enable/disable stream 4

See bits [30:31]

STR5_EN : Enable/disable stream 5

See bits [30:31]

STR6_EN : Enable/disable stream 6

See bits [30:31]

STR7_EN : Enable/disable stream 7

See bits [30:31]

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00000

ADDR

RPw

0x1FE

Bit

[23:31]

[0:22]

Table 67. F2A[i]_CH[x]_ARU_RD_FIFO field description

Description

ADDR

: ARU Read address

Note: this bit field is only writable if channel is disabled.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000 0 00

Reserved

0x0000

Bit

[16:31]

[14:15]

[0:12]

Table 68. F2A[i]_CH[x]_STR_CFG field description

Description

Reserved

Note:

Read as zero, should be written as zero.

TMODE

: Transfer mode for 53 bit ARU data from/to FIFO

00 = Transfer low word (ARU bits 23:0) from/to FIFO

01 = Transfer high word (ARU bits 47:24) from/to FIFO

10 = Transfer both words from/to FIFO

11 = Reserved

DIR : Data transfer direction

0 = Transport from ARU to FIFO

1 = Transport from FIFO to ARU

Reserved

Note: Read as zero, should be written as zero.

Note: The write protected bits of register F2A_STR_[x]_CFG are only writable if the corresponding enable bit STRx_EN of register F2A_ENABLE is cleared.

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8 Clock Management Unit (CMU)

Clock Management Unit (CMU)

8.1 Overview

The Clock Management Unit (CMU) is responsible for clock generation of the counters and of the GTM-IP. The CMU consists of three subunits that generate different clock sources for

the whole GTM-IP. Figure 17

shows a block diagram of the CMU.

The Configurable Clock Generation (CFGU) subunit provides eight dedicated clock sources for the following GTM submodules: TIM, ATOM, TBU, and MON. Each instance of such a submodule can choose an arbitrary clock source, in order to specify wide-ranging time bases.

The Fixed Clock Generation (FXU) subunit generates predefined non-configurable clocks

CMU_FXCLK[y] (y: 0...4) for the TOM submodules and the MON submodule. The

CMU_FXCLK[y] signals are derived from the CMU_GCLK_EN signal generated by the global clock divider. The dividing factors are defined as 2

, 2

, and 2

The External Clock Generation (EGU) subunit is able to generate up to three chip external clock signals visible at CMU_ECLK[z] (z: 0...2) with a duty cycle of about 50 %.

The clock source signals CMU_CLK[x] (x: 0...7) and CMU_FXCLK[y] are implemented in form of enable signals for the corresponding registers, which means that the actual clock signal of all registers always use the SYS_CLK signal.

The four configurable clock signals CMU_CLK0 , CMU_CLK1, CMU_CLK6 and CMU_CLK7 are connected to the TIM filter counters.

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8.3

The sub block Global Clock Divider can be used to divide the GTM-IP global input clock signal SYS_CLK into a common subdivided clock signal.

The divided clock signal of the sub block Global Clock Divider is implemented as an enable signal that enables dedicated clocks from the SYS_CLK signal to generate the user specified divided clock frequency.

The resulting fractional divider ( Z/N) specified through equation:

CMU_GCLK_EN

   T

SYS_CLK is implemented according to the following algorithm:

Z: CMU_GCLK_NUM(23:0);

N: CMU_GCLK_DEN(23:0) ; 



Z,N >0

Set remainder ( R ), operand1 ( OP1 ) and operand2 ( OP2 ) register during init-phase

(with implicit conversion to signed): 

R=Z, OP1=N, OP2=N-Z;

2. After leaving init-phase (at least one CMU_CLK[x] has been enabled) the sign of remainder R for each SYS_CLK cycle will be checked:

3. If keep updating remainder and keep CMU_GCLK_EN=’0’ : 

R=R-OP1;

4. If update remainder and set CMU_GCLK_EN=’1’ : 

R=R-OP2 ;

After at most ( Z/N +1) subtractions (3) there will be a negative R and an active phase of the generated clock enable (for one cycle) will be triggered (4). The remainder R is a measure for the distance to a real Z/N clock and will be regarded for the next generated clock enable cycle phase. The new R value will be R=R+(Z-N) . In the worst case the remainder R will sum up to an additional cycle in the generated clock enable period after Z -cycles. In the other cases equally distributed additional cycles will be inserted for the generated clock enable. If Z is an integer multiple of N no additional cycles will be included for the generated clock enable at all.

Note that for a better resource sharing all arithmetic has been reduced to subtractions and the initialization of the remainder R uses the complement of ( Z-N ).

Configurable clock generation subunit (CFGU)

The CMU subunit CFGU provides up to eight configurable clock divider blocks that divide the common C MU_GCLK_EN signal into dedicated enable signals for the GTM-IP sub blocks.

The configuration of the eight different clock signals CMU_CLK[x] (x: 0…7) always depends on the configuration of the global clock enable signal CMU_GCLK_EN . Additionally, each clock source has its own configuration data, provided by the control register

CMU_CLK_[x]_CTRL (x: 0…7).

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According to the configuration of the global clock divider, the configuration of the Clock

Source x Divider is done by setting an appropriate value in the bit field CLK_CNT[x] of the register CMU_CLK_[x]_CTRL .

The frequency f x

=1/T x

of the corresponding clock enable signal CMU_CLK[x] can be determined by the unsigned representation of CLK_CNT[x] of the register

CMU_CLK_[x]_CTRL in the following way:

CMU_CLK[x]

 CLK_CNT[x] 1   T

CMU_GCLK_EN

The corresponding wave form is shown in

Figure 18 Wave form of generated clock signal

CMU_CLK[x]

Each clock signal CMU_CLK[x] can be enabled individually by setting the appropriate bit field EN_CLK[x] in the register CMU_CLK_EN . Except for CMU_CLK6 and CMU_CLK7 individual enabling and disabling is active only if CLK6_SEL and CLK7_SEL is unset.

Alternatively, clock source six and seven ( CMU_CLK6 and CMU_CLK7 ) may provide the signal SUB_INC1 and SUB_INC2 coming from submodule DPLL as clock enable signal depending on the bit field CLK6_SEL of the register CMU_CLK_6_CTRL and on the bit field CLK7_SEL of the register CMU_CLK_7_CTRL .

To avoid unexpected behavior of the hardware, the configuration of a register

CMU_CLK_[x]_CTRL can only be changed, when the corresponding clock signal

CMU_CLK[x] is disabled.

Further, any changes to the registers CMU_GCLK_NUM and CMU_GCLK_DEN can only be performed, when all clock enable signals CMU_CLK[x] and the EN_FXCLK bit inside the

CMU_CLK_EN register are disabled.

The hardware guarantees that all clock signals CMU_CLK[x], which were enabled simultaneous, are synchronized to each other. Simultaneous enabling does mean that the bits EN_CLK[x] in the register CMU_CLK_EN are set by the same write access.

8.4 Wave form of generated clock signal CMU_CLK[x]

Figure 18. Wave form of generated clock signal CMU_CLK[x]

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8.5

Clock Management Unit (CMU)

Fixed clock generation (FXU)

The FXU subunit generates fixed clock enables out of the CMU_GCLK_EN or one of the eight CMU_CLK[x] enable signal depending on the FXCLK_SEL bit field of the

CMU_FXCLK_CTRL register. These clock enables are used for the PWM generation inside the TOM submodules.

All clock enables CMU_FXCLK[y] can be enabled or disabled simultaneous by setting the appropriate bit field EN_FXCLK in the register CMU_CLK_EN .

The dividing factors are defined as 2

, 2

, and 2

. The signals CMU_FXCLK[y] are

implemented in form of enable signals for the corresponding registers (see also Section 8.4:

Wave form of generated clock signal CMU_CLK[x] .

8.6 External Generation Unit (EGU)

The EGU subunit generate up to three separate clock output signals CMU_ECLK[z] (z:

0...2).

Each of these clock signals is derived from the corresponding External Clock Divider z sub block, which generates a clock signal derived from the GTM-IP input clock SYS_CLK .

In contrast to the signals CMU_CLK[x] and CMU_FXCLK[y] , which are treated as simple enable signals for the registers, the signals CMU_ECLK[z] have a duty cycle of about 50 % that is used as a true clock signal for external peripheral components.

Each of the external clocks are enabled and disabled by setting the appropriate bit field

EN_ECLK[z] in the register CMU_CLK_EN .

The clock frequencies f

CMU_ECLK[z]

=1/T

CMU_ECLK[z]

of the external clocks are controlled with the registers CMU_ECLK_[z]_NUM and CMU_ECLK_[z]_DEN as follows:

CMU_ECLK[z]

2   ECLK[z]_NUM/ECLK[z]_DEN   T

SYS_CLK and is implemented according the following algorithm

( Z: CMU_ECLK_[z]_NUM(23:0); N: CMU_ECLK_[z]_DEN(23:0) ; Z,N >0 ; Z>=N;

CMU_ECLK[z] ='0'):

Set remainder ( R ), operand1 ( OP1 ) and operand2 ( OP2 ) register during init-phase

(with implicit conversion to signed): 

R=Z, OP1=N, OP2=N-Z;

2. After leaving init-phase ( CMU_ECLK[z] has been enabled) the sign of remainder R for each SYS_CLK cycle will be checked:

3. If keep updating remainder and keep CMU_ECLK[z] : 

R=R-OP1;

4. If update remainder and toggle CMU_ECLK[z] : 

R=R-OP2 ;

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Clock Management Unit (CMU) RM0361 equally distributed additional cycles will be inserted for the generated clock toggle. If Z is an integer multiple of N no additional cycles will be included for the generated clock toggle at all. Note that for a better resource sharing all arithmetic has been reduced to subtractions and the initialization of the remainder R uses the complement of ( Z-N ).

The default value of the CMU_ECLK[z] output is low.

8.7

Register name

CMU_CLK_EN

CMU_GCLK_NUM

CMU_GCLK_DEN

CMU_CLK_0_CTRL

CMU_CLK_1_CTRL

CMU_CLK_2_CTRL

CMU_CLK_3_CTRL

CMU_CLK_4_CTRL

CMU_CLK_5_CTRL

CMU_CLK_6_CTRL

CMU_CLK_7_CTRL

CMU_ECLK_0_NUM

CMU_ECLK_0_DEN

CMU_ECLK_1_NUM

CMU_ECLK_1_DEN

CMU_ECLK_2_NUM

CMU_ECLK_2_DEN

CMU_FXCLK_CTRL

CMU configuration registers overview

Table 69. CMU configuration registers

Description

Clock enable

Global clock control numerator

Global clock control denominator

Control for clock source 0

Control for clock source 1

Control for clock source 2

Control for clock source 3

Control for clock source 4

Control for clock source 5

Control for clock source 6

Control for clock source 7

External clock 0 control numerator

External clock 0 control denominator

External clock 1 control numerator

External clock 1 control denominator

External clock 2 control numerator

External clock 2 control denominator

Control FXCLK subunit input clock

Details in section

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RM0361 Clock Management Unit (CMU)

[28:29]

[26:27]

[24:25]

[22:23]

[20:21]

[18:19]

[16:17]

[14:15]

[12:13]

[10:11]

[8:9]

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

Bit

[30:31]

[0:7]

0x000

Table 70. CMU_CLK_EN field description

Description

EN_CLK0

: Enable clock source 0

00 = clock source is disabled (ignore write access)

01 = disable clock signal and reset internal states

10 = enable clock signal

11 = clock signal enabled (ignore write access)

Note: Any read access to an EN_CLK[x], EN_ECLK[z] or EN_FXCLK bit field will always result in a value 00 or 11 indicating current state. A modification of the state is only performed with the values 01 and 10. Writing the values 00 and 11 is always ignored.

Note: Any disabling to EN_CLK[x] will be reset internal counters for configurable clocks.

EN_CLK1

: Enable clock source 1, see bits [30:31]

EN_CLK2

: Enable clock source 2, see bits [30:31]

EN_CLK3

: Enable clock source 3, see bits [30:31]

EN_CLK4

: Enable clock source 4, see bits [30:31]

EN_CLK5 : Enable clock source 5, see bits [30:31]

EN_CLK6 : Enable clock source 6, see bits [30:31]

EN_CLK7

: Enable clock source 7, see bits [30:31]

EN_ECLK0

: Enable ECLK 0 generation subunit, see bits [30:31]

EN_ECLK1

: Enable ECLK 1 generation subunit, see bits [30:31]

EN_ECLK2

: Enable ECLK 2 generation subunit, see bits [30:31]

EN_FXCLK : Enable all CMU_FXCLK, see bits [30:31]

Note:

An enable to EN_FXCLK from disable state will reset the internal fixed clock counters.

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

GCLK_NUM

RPw

0x00001

Bit

[8:31]

[0:7]

Table 71. CMU_GCLK_NUM field description

Description

Numerator for global clock divider. Defines numerator of the fractional divider.

Note: Value can only be modified when all clock enables EN_CLK[x] and the EN_FXCLK are disabled.

Note: The CMU hardware alters the content of CMU_GCLK_NUM and CMU_GCLK_DEN automatically to 0x1, if CMU_GCLK_NUM is specified less than CMU_GCLK_DEN or one of the values is specified with a value zero. Thus, a secure way for altering the values is writing twice to the register CMU_GCLK_NUM followed by a single write to register CMU_GCLK_DEN.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved GCLK_DEN Bit

Mode

Initial value

0x00

RPw

0x000001

Bit

[8:31]

[0:7]

Table 72. CMU_GCLK_DEN field description

Description

Denominator for global clock divider. Defines denominator of the fractional divider

Note:

Value can only be modified when all clock enables EN_CLK[x] and the EN_FXCLK are disabled.

Note:

The CMU hardware alters the content of CMU_GCLK_NUM and CMU_GCLK_DEN automatically to 0x1, if CMU_GCLK_NUM is specified less than CMU_GCLK_DEN or one of the values is specified with a value zero. Thus, a secure way for altering the values is writing twice to the register CMU_GCLK_NUM followed by a single write to register CMU_GCLK_DEN.

Reserved

Note:

Read as zero, should be written as zero.

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8.8.4 Register CMU_CLK_[x]_CTRL (x:0...5)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

CLK_CNT

RPw

0x000000

Bit

[8:31]

[0:7]

Table 73. CMU_CLK_[x]_CTRL field description

Description

CLK_CNT

: Clock count. Defines count value for the clock divider of clock source

CMU_CLK[x] (x: 0...5).

Note:

Value can only be modified when clock enable EN_CLK[x] (x: 0...5) is disabled.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved CLK_CNT

Mode

Initial value

Bit

[8:31]

[0:6]

0x00 0

RPw

0x000000

Table 74. CMU_CLK_6_CTRL field description

Description

CLK_CNT

: Clock count. Define count value for the clock divider of clock source CMU_CLK6.

Note: Value can only be modified when clock enable EN_CLK6 is disabled

CLK6_SEL

: Clock source selection for CMU_CLK6.

0 = use Clock Source 6 Divider

1 = use signal SUB_INC2 of submodule DPLL

Note: Value can only be modified when clock enable EN_CLK6 is disabled.

Reserved : reserved bits

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved CLK_CNT

Bit

[8:31]

[0:6]

0x00 0

RPw

0x000000

Table 75. CMU_CLK_7_CTRL field description

Description

CLK_CNT

: Clock count. Define count value for the clock divider of clock source CMU_CLK7.

Note: Value can only be modified when clock enable EN_CLK7 is disabled

CLK7_SEL

: Clock source selection for CMU_CLK7.

0 = use Clock Source 7 Divider

1 = use signal SUB_INC1 of submodule DPLL

Note: Value can only be modified when clock enable EN_CLK7 is disabled.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ECLK_NUM Bit

Mode

Initial value

0x00

RPw

0x00001

Bit

[8:31]

[0:7]

Table 76. CMU_ECLK_[z]_NUM (z:0...2) field description

Description

Numerator for external clock divider. Defines numerator of the fractional divider.

Note:

Value can only be modified when clock enable EN_ECLK[z] is disabled.

Reserved

Note:

Read as zero, should be written as zero.

Note: The CMU hardware alters the content of CMU_ECLK_[z]_NUM and CMU_ECLK_[z]_DEN automatically to 0x1, if CMU_ECLK_[z]_NUM is specified less than CMU_ECLK_[z]_DEN or one of the values is specified with a value zero. Thus, a secure way for altering the values is writing twice to the register CMU_ECLK_[z]_NUM followed by a single write to register

CMU_ECLK_[z]_DEN.

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Address offset: see Appendix B Initial value: 0x0000_0001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

ECLK_DEN

RPw

0x000001

Bit

[8:31]

[0:7]

Table 77. CMU_ECLK_[z]_DEN field description

Description

Denominator for external clock divider. Defines denominator of the fractional divider.

Note: Value can only be modified when clock enable EN_ECLK[z] is disabled.

Reserved

Note: Read as zero, should be written as zero.

CMU_ECLK_[z]_DEN.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved FXCLK_SEL Bit

Mode

Initial value

0x0000000

RPw

0x0

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Bit

[28:31]

[0:27]

RM0361

Table 78. CMU_FXCLK_CTRL field description

Description

FXCLK_SEL : Input clock selection for EN_FXCLK line.

0000 = CMU_GCLK_EN selected.

0001 = CMU_CLK0 selected.

0010 = CMU_CLK1 selected.

0011 = CMU_CLK2 selected.

0100 = CMU_CLK3 selected.

0101 = CMU_CLK4 selected.

0110 = CMU_CLK5 selected.

0111 = CMU_CLK6 selected.

1000 = CMU_CLK7 selected.

Note: This value can only be written, when the CMU_FXCLK generation is disabled. See bits

[8:9] in register CMU_CLK_EN.

Note: Other values for FXCLK_SEL are reserved and should not be used, but they behave like

FXCLK_SEL = 0.

Reserved

Note: Read as zero, should be written as zero.

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9 Time Base Unit (TBU)

Time Base Unit (TBU)

9.1 Overview

The Time Base Unit TBU provides common time bases for the GTM-IP. The TBU submodule is organized in channels, where the number of channels is device dependent.

There are at most three channels implemented inside the TBU. The TBU channel 0 time base register TBU_CH0_BASE is 27 bits and it is configurable whether the lower 24-bit or the upper 24-bit are provided to the GTM as signal TBU_TS0 . The two TBU channels 1 and

2 have a time base register TBU_CH[y]_BASE (y: 1, 2) of 24-bit length. The time base register value TBU_TS[y] are provided to subsequent submodules of the GTM.

The TBU_UP[z] (z: 1...2) signals are set to high for a single SYS_CLK period, whenever the corresponding signal TBU_TS[z] (z:1...2) is getting updated. The signal TBU_UP0_L is set to high for a single SYS_CLK period if the signal TBU_TS0 and TBU_TS0x is getting updated and TBU_UP0_H is set to high for a single SYS_CLK period, whenever if the upper

24-bit of TBU_TS0 are updated.

The time base channels can run independently of each other and can be enabled and disabled synchronously by control bits in a global TBU channel enable register TBU_CHEN .

Section 9.1.1: TBU block diagram

shows a block diagram of the Time Base Unit.

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Figure 19. TBU block diagram

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Depending on the device a third TBU channel exists which offers the same functionality as the time base channel 1.

DocID025070 Rev 1

RM0361 Time Base Unit (TBU)

The configuration of the independent time base channels TBU_BASE_[z] is done via the

AEI interface. Each TBU channel may select one of the eight CMU_CLK[x] (x: 0...7) signals coming from the CMU submodule.

For TBU channels 1 and 2 an additional clock signal SUB_INC[y]c (y: 1, 2) coming from the

DPLL can be selected as input clock for the TBU_BASE_[y]. This clock in combination with the DIR[y] signals determines the counter direction of the TBU_BASE_[y].

The selected time stamp clock signal for the TBU_BASE_0 subunit is served via the

TS_CLK signal line to the DPLL submodule. The TS_CLK signal equals the signal

TBU_UP0 .

9.2 TBU time base channels

The time base values are generated within the TBU time base channels in two independent operation modes.

9.2.1 TBU channel modes

TBU channel 0 provides a 27-bit counter in a free running counter mode. Depending on the bit field LOW_RES of register TBU_CH0_CTRL, the lower 24 bits (bit 0 to 23) or the upper

24 bits (bits 3 to 26) are provided to the GTM submodules.

TBU channel 1 and channel 2 can run in two modes; the free running counter mode and forward/backward counter mode, where the time base can run backwards depending on the

DIR[y] input signal values.

In both modes, the time base register TBU_CH[z]_BASE can be initialized with a start value just before enabling the corresponding TBU channel.

Moreover, the time base register TBU_CH[z]_BASE can always be read in order to determine the actual value of the counter.

9.2.1.1 Free running counter mode

In TBU Free running counter mode, the time base register TBU_CH[y]_BASE is updated on every specified incoming clock event by the selected signal CMU_CLK[x] (depending on

TBU_CH[z]_CTRL register). In general the time base register TBU_CH[y]_BASE is incremented on every CMU_CLK[x] clock tick.

9.2.1.2 Forward/backward counter mode

As mentioned above TBU channels 1 and 2 can also be configured to run in forward/backward counter mode. In this mode the DIR[y] signal provided by the DPLL is taken into account.

The value of the time base register TBU_CH[y]_BASE is incremented in case when the

DIR[y] signal equals ‘0’ and decremented in case when the DIR[y] signal is ‘1’.

9.3 TBU configuration registers overview

Following table lists the configuration registers of the TBU .

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Register name

TBU_CHEN

TBU_CH0_CTRL

TBU_CH0_BASE

TBU_CH1_CTRL

TBU_CH1_BASE

TBU_CH2_CTRL

TBU_CH2_BASE

Note:

RM0361

Table 79. TBU configuration registers

Description

TBU global channel enable

TBU channel 0 control

TBU channel 0 base

TBU channel 1 control

TBU channel 1 base

TBU channel 2 control

TBU channel 2 base

Details in section

The standard configuration of the TBU implements only channels 0 and 1. Refer to the

Appendix B of the target GTM-IP implementation to know if channel 2 is available (see

Section 22.3: References

9.4 TBU registers description

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

Bit

[30:31]

[28:29]

0x000000

Table 80. TBU_CHEN field description

Description

ENDIS_CH0

: TBU channel 0 enable/disable control.

Write of following double bit values is possible:

00 = don't care, bits 1:0 will not be changed

01 = channel disabled: is read as 00 (see below)

10 = channel enabled: is read as 11 (see below)

11 = don't care, bits 1:0 will not be changed

Note:

Read of following double values means:

00 = channel disabled

11 = channel enabled

ENDIS_CH1:

TBU channel 1 enable/disable control. See bits [30:31]

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Bit

[26:27]

[0:25]

Time Base Unit (TBU)

Table 80. TBU_CHEN field description

Description

ENDIS_CH2: TBU channel 2 enable/disable control. See bits [30:31]

Note:

These bits are only applicable if channel is implemented for this device, otherwise read and write as zero

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

Bit

[28:30]

[0:27]

00x0000000

RPw

000

RP w

Table 81. TBU_CH0_CTRL field description

Description

LOW_RES

: TBU_CH0_BASE register resolution.

0 = TBU channel uses lower counter bits (bit 0 to 23)

1 = TBU channel uses upper counter bits (bit 3 to 26)

Note: The two resolutions for the TBU channel 0 can be used in the TIM channel 0 and the

DPLL submodules.

Note: This value can only be modified if channel 0 is disabled.

CH_CLK_SRC : Clock source for channel x (x:0...2) time base counter

000 = CMU_CLK0 selected

001 = CMU_CLK1 selected

010 = CMU_CLK2 selected

011 = CMU_CLK3 selected

100 = CMU_CLK4 selected

101 = CMU_CLK5 selected

110 = CMU_CLK6 selected

111 = CMU_CLK7 selected

Note:

This value can only be modified if channel 0 is disabled.

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

BASE

RPw

0x000000

Bit

[5:31]

[0:4]

Table 82. TBU_CH0_BASE field description

Description

BASE

: Time base value for channel 0.

Note: The value of BASE can only be written if the TBU channel 0 is disabled

Note:

If channel 0 is enabled, a read access to this register provides the current value of the underlying 27-bit counter.

Reserved

Note:

Read as zero, should be written as zero.

9.4.4 Register TBU_CH[y]_CTRL (y:1, 2)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

0x0000000

RPw

000

RP w

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Bit

[28:30]

[0:27]

Time Base Unit (TBU)

Table 83. TBU_CH[y]_CTRL field description

Description

CH_MODE : Channel mode

0 = Free running counter mode

1 = Forward/backward counter mode

Note:

This value can only be modified if channel y (y:1,2) is disabled. In Free running counter mode the CMU clock source specified by CH_CLK_SRC is used for the counter. In

Forward/Backward counter mode the SUB_INC[y]c clock signal in combination with the

DIR[y] input signal is used to determine the counter direction and clock frequency.

CH_CLK_SRC

: Clock source for channel y (y: 1...2) time base counter

000 = CMU_CLK0 selected

001 = CMU_CLK1 selected

010 = CMU_CLK2 selected

011 = CMU_CLK3 selected

100 = CMU_CLK4 selected

101 = CMU_CLK5 selected

110 = CMU_CLK6 selected

111 = CMU_CLK7 selected

Note: This value can only be modified if channel y was disabled

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved BASE Bit

Mode

Initial value

0x00

RPw

0x000000

Bit

[8:31]

[0:7]

Table 84. TBU_CH[y]_BASE field description

Description

BASE

: Time base value for channel y (y: 1, 2)

Note:

The value of BASE can only be written if the corresponding TBU channel y is disabled

Note: If the corresponding channel y is enabled, a read access to this register provides the current value of the underlying counter.

Reserved

Note:

Read as zero, should be written as zero.

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Timer Input Module (TIM)

10 Timer Input Module (TIM)

RM0361

10.1 Overview

The Timer Input Module (TIM) is responsible for filtering and capturing input signals of the

GTM. Several characteristics of the input signals can be measured inside the TIM channels.

For advanced data processing the detected input characteristics of the TIM module can be routed through the ARU to subsequent processing units of the GTM.

Input characteristics mean either time stamp values of detected input rising or falling edges together with the new signal level or the number of edges received since channel enable together with the actual time stamp or PWM signal durations for a whole PWM period.

The architecture of TIM is shown in Figure 20 .

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Figure 20. TIM block diagram

Timer Input Module (TIM)

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The number of channels m inside a TIM submodule depends on the device.

Each of the m dedicated input signals are filtered inside the FLTx subunit of the TIM Module.

It should be noted that the incoming input signals are synchronized to the clock SYS_CLK, resulting in a delay of two SYS_CLK periods for the incoming signals.

The submodule TIM provides different filter mechanisms described in more detail in

Section 10.2: TIM filter functionality (FLT)

. After filtering, the signal is routed to the corresponding TIM channel.

The measurement values can be read by the CPU directly via the AEI-Bus or they can be routed through the ARU to other submodules of the GTM.

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For timeout detection of an incoming signal (no subsequent edge detected during a specified duration) each individual channel has a Timeout Detection Unit (TDU).

For the GTM-IP TIM0 submodule only, the dashed signal outputs TIM[i]_CH[x](23:0) ,

TIM[i]_CH[x](47:24) and TIM[i]_CH[x](48) come from the TIM0 submodule channels zero (0) to five (5) and are connected to MAP submodule. There, they are used for further processing and for routing to the DPLL.

The two (three) time bases coming from the TBU are connected to the TIM channels to annotate time stamps to incoming signals. For TIM0 the extended 27-bit width time base

TBU_TS0 is connected to the TIM channels, and the user has to select if the lower 24 bits

( TBU_TS0(23...0) ) or the higher 24 bits ( TBU_TS0(26...3) ) are stored inside the GPR0 and

GPR1 registers.

10.1.2 Input source selection INPUTSRCx

The fields CICTRL (in TIM[i]_CH[x]_CTRL register), MODE_x and VAL_x (in

TIM[i]_IN_SRC register) allow to select the source of the input signal to be processed by the filter, timeout detection and TIM channel stages.

10.1.2.1 INPUTSRC block diagram

Figure 21. INPUTSRC block diagram

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In a certain MODE_x , VAL_x combination the input signal F_IN(x) can be driven by

VAL_x(1) with 0 or 1 directly.

The m channels of a TIM[i] submodule are bundled in the register TIM[i]_IN_SRC allowing a synchronous control of all the input channels.

Two adjacent channels can be combined by setting the CICTRL bit field in the corresponding TIM[i]_CH[x]_CTRL register. This allows for a combination of complex measurements on one input signal with two TIM channels.

The additional input signal AUX_IN[x ] can be selected as an input signal. The source of this

signal is defined in the Figure 3: GTM-IP_103 signal multiplex

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Each channel can operate on an external capture signal EXT_CAPTURE . The source to use for this signal can be configured by the bit field EXT_CAP_SRCx in the register

TIM[i]_CH[x]_ECTRL.

Figure 22. EXTCAPSRC block diagram

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The external capture functionality for the TIM[i] channel x can be enabled with the bit

EXT_CAP_EN in the register TIM[i]_CH[x]_CTRL ; it will trigger on each rising edge. A pulse generation for each rising edge of the selected input signal TIM_IN[x] and AUX_IN[x] is applied.

The six channel interrupt sources for TIM[i] can be triggered by the TIM[i] channel mode.

Alternatively they can be issued by a software trigger setting the corresponding bit in the

TIM[i]_CH[x+1]_IRQ_FORCINT register.

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10.2 TIM filter functionality (FLT)

10.2.1 Overview

The TIM submodule provides a configurable filter mechanism for each input signal. These filter mechanism is provided inside the FLT subunit.

FLT architecture is shown in Figure 23 .

The filter includes a clock synchronization unit (CSU), an edge detection unit (EDU), and a filter counter associated to the filter unit (FLTU).

The CSU is synchronizing the incoming signal F_IN to the selected filter clock frequency, which is controlled with the bit field FLT_CNT_FRQ of register TIM[i]_CH[x]_CTRL .

The synchronized input signal F_IN_SYNC is used for further processing within the filter.

It should be noted that glitches with a duration less than the selected CMU clock period are lost.

The filter modes can be applied individually to the falling and rising edges of an input signal.

The following filter modes are available:

 Immediate edge propagation mode

 Individual de-glitch time mode (up/down counter)

 Individual de-glitch time mode (hold counter)

Figure 23. FLT architecture

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The filter parameters (deglitch and acceptance time) for the rising and falling edge can be configured inside the two filter parameter registers FLT_RE (rising edge) and FLT_FE

(falling edge). The exact meaning of the parameter depends on the filter mode.

However the delay time T of both filter parameters FLT_xE can always be determined by:

 FLT_xE+1   T

FLT_CLK whereas T

FLT_CLK is the clock period of the selected CMU clock signal in bit field

FLT_CNT_FRQ of register TIM[i]_CH[x]_CTRL .

When a glitch is detected on an input signal a status flag GLITCHDET is set inside the

TIM[i]_CH[x]_IRQ_NOTIFY register.

Table 85 gives an overview about the meanings for the registers

FLT_RE and FLT_FE . In the individual deglitch time modes, the actual filter threshold for a detected regular edge is provided on the TIM[i]_CH[x](47:24) output line. In the case of immediate edge propagation mode, a value of zero is provided on the TIM[i]_CH[x](47:24) output line.

The TIM[i]_CH[x](47:24) output line is used by the MAP submodule for further processing

(please see

Chapter 15: TIM0 input mapping module (MAP) ).

10.2.1.2 Filter parameter summary for the different filter modes

Table 85. Filter parameter summary for the different filter modes

Filter mode Meaning of FLT_RE Meaning of FLT_FE

Immediate edge propagation Acceptance time for rising edge

Individual de-glitch time

(up/down counter)

De-glitch time for rising edge

Individual de-glitch time (hold counter)

De-glitch time for rising edge

Acceptance time for falling edge

De-glitch time for falling edge

A counter FLT_CNT is used to measure the glitch and acceptance times.

The frequency of the FLT_CNT counter is configurable in bit field FLT_CNT_FRQ of register

TIM[i]_CH[x]_CTRL .

The counter FLT_CNT can either be clock with the CMU_CLK0, CMU_CLK1, CMU_CLK6 or the CMU_CLK7 signal. These signals are coming from the CMU submodule.

The FLT_CNT , FLT_FE and FLT_RE registers are 24-bit width. For example, when the resolution of the CMU_CLK0 signal is 50 ns this allows maximal de-glitch and acceptance times of about 838 ms for the filter.

10.2.2.1 Immediate edge propagation mode

In immediate edge propagation mode after detection of an edge the new signal level on

F_IN_SYNC is propagated to F_OUT with a delay of one T

FLT_CLK period and the new signal level remains unchanged until the configured acceptance time expires.

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For each edge type the acceptance time can be specified separately in the FLT_RE and

FLT_FE registers.

Each signal change on the input F_IN_SYNC during the duration of the acceptance time has no effect on the output signal level F_OUT of the filter but it sets the glitch GLITCHDET bit in the TIM[i]_CH[x]_IRQ_NOTIFY register.

After it expires an acceptance time the input signal F_IN_SYNC is observed and on signal level change the filter raises a new detected edge and the new signal level is propagated to

F_OUT .

Independent of a signal level change the value of F_OUT is always set to F_IN_SYNC, when the acceptance time expires (see also

Figure 25 ).

Figure 24

shows an example for the immediate edge propagation mode, in the case of rising edge detection. Both, the signal before filtering ( F_IN ) and after filtering ( F_OUT ) are shown. The acceptance time at1 is specified in the register FLT_RE .

Figure 24. Immediate edge propagation mode in the case of a rising edge

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In immediate edge propagation mode the glitch measurement mechanism is not applied to the edge detection. Detected edges on F_IN_SYNC are transferred directly to F_OUT .

The counter FLT_CNT is incremented until acceptance time threshold is reached.

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Figure 25

shows a more complex example of the TIM filter, in which both, rising and falling edges are configured in immediate edge propagation mode.

Figure 25. Immediate edge propagation mode in the case of a rising and falling edge

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If the FLT_CNT has reached the acceptance time for a specific signal edge and the signal

F_IN_SYNC has already changed to the opposite level of F_OUT , the opposite signal level is set to F_OUT

and the acceptance time measurement is started immediately. Figure 25

shows this scenario at the detection of the first rising edge and the second falling edge.

10.2.2.2 Individual de-glitch time mode (up/down counter)

In individual de-glitch time mode (up/down counter) each edge of an input signal can be filtered with an individual de-glitch threshold filter value mentioned in the registers FLT_RE and FLT_FE, respectively.

The filter counter register FLT_CNT is incremented when the signal level on F_IN_SYNC is unequal to the signal level on F_OUT and decremented if F_IN_SYNC equals F_OUT .

After FLT_CNT has reached a value of zero during decrementation the counter is stopped immediately.

If a glitch is detected a glitch detection bit GLITCHDET is set in the

TIM[i]_CH[x]_IRQ_NOTIFY register.

The detected edge signal together with the new signal level is propagated to F_OUT after the individual de-glitch threshold is reached.

Figure 26

shows the behavior of the filter in individual de-glitch time (up/down counter) mode in the case of the rising edge detection.

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Figure 26. Individual de-glitch time mode (up/down counter) in the case of a rising edge

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10.2.2.3 Individual de-glitch time mode (hold counter)

In individual de-glitch time mode (hold counter) each edge of an input signal can be filtered with an individual de-glitch threshold filter value mentioned in the registers FLT_RE and

FLT_FE, respectively.

The filter counter register FLT_CNT is incremented when the signal level on F_IN_SYNC is unequal to the signal level on F_OUT and the counter value of FLT_CNT is hold if F_IN equals F_OUT .

If a glitch is detected the glitch detection bit GLITCHDET is set in the

TIM[i]_CH[x]_IRQ_NOTIFY register.

The detected edge signal together with the new signal level is propagated to F_OUT after the individual de-glitch threshold is reached.

Figure 27

shows the behavior of the filter in individual de-glitch time (hold counter) mode in the case of the rising edge detection.

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Figure 27. Individual de-glitch time mode (hold counter) in the case of a rising edge

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10.2.2.4 Immediate edge propagation and individual de-glitch mode

As already mentioned, the three different filter modes can be applied individually to each edge of the measured signal.

However, if one edge is configured with immediate edge propagation and the other edge with an individual deglitch mode (whether up/down counter or hold counter) a special consideration has to be applied.

Assume that the rising edge is configured for immediate edge propagation and the falling edge with individual deglitch mode (up/down counter) as shown in

Figure 28

If the falling edge of the incoming signal already occurs during the measuring of the acceptance time of the rising edge, the measurement of the deglitch time on the falling edge is started delayed, but immediately after the acceptance time measurement phase of the rising edge has finished.

Consequently, the deglitch counter can not measure the time T

ERROR

Figure 28

, as shown in

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Figure 28. Mixed mode measurement

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If FLT_EN =1 a change of FLT_RE or FLT_FE will take place immediately.

If FLT_EN =1 a change of FLT_MODE_RE or FLT_MODE_FE will be used with the next occurring corresponding edge. If the mode is changed while the filter unit is processing a certain mode, it will end this edge filtering in the mode as started.

If FLT_EN =1 a change of FLT_CTR_RE or FLT_CTR_FE will take place immediately.

10.3 Timeout Detection Unit (TDU)

The Timeout Detection Unit (TDU) is responsible for timeout detection of the TIM input signals.

Each channel of the TIM submodule has its own Timeout Detection Unit (TDU) where a timeout event can be set up on the filtered input signal of the corresponding channel.

The TDU architecture is shown in

Figure 29: TDU block diagram .

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Figure 29. TDU block diagram

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It is possible to detect timeouts with the resolution of the CMU_CLKx input signal selected with the bit field TCS of the register TIM[i]_CH[x]_TDUV . The individual timeout values have to be specified in number of ticks of the selected input clock signal and have to be specified in the field TOV of timeout value register TIM[i]_CH[x]_TDUV of the TIM channel x.

The exact time out value T

TDU

can be calculated with:

TDU

 TOV+1   T

CMU_CLKx whereas T

CMU_CLKx is the clock period of the selected CMU clock signal.

Timeout detection can be enabled or disabled individually inside the TIM[i]_CH[x]_CTRL register by setting/resetting the TOCTRL bit.

Timeout detection can be enabled to be sensitive to falling, rising or both edges of the input signal by writing the corresponding values to the bit field TOCTRL .

The counter TO_CNT is reset by each detected valid input edge coming either from the filtered input signal or when the timeout value TOV is reached by the counter TO_CNT .

After such a reset or by enabling the channel inside the TIM[i]_CH[x]_CTRL register the counter TO_CNT starts counting again from value 0 with the specified clock input signal.

Otherwise, timeout measurements start immediately after the TOCTRL bit inside the

TIM[i]_CH[x]_CTRL register is written (enabled).

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The TDU generates an interrupt signal TIM_TODETx_IRQ whenever a timeout is detected for an individual input signal, and the TODET bit is set inside the

TIM[i]_CH[x]_IRQ_NOTIFY register.

In addition, when the ARU access is enabled with the ARU_EN bit inside the

TIM[i]_CH[x]_CTRL register, the actual values stored inside the TIM[i]_CH[x]_GPR0 and

TIM[i]_CH[x]_GPR1 registers are sent together with the last stored signal level to the ARU if a timeout event occurs.

To signal that a timeout occurred, the ARU_OUT(50) bit (ACB(2)) is set. The bit ACB(0) will be updated with the timeout event to the signal level on which the timeout was detected.

Thus, a destination could determine if a timeout occurred at the TIM input by evaluating

ACB bit 2.

Since the TIM channel still monitors its input pin although the timeout happened, a valid edge could occur at the input pin while the timeout information is still valid at the ARU. In that case, the new edge associated data is stored inside the registers TIM[i]_CH[x]_GPR0 and TIM[i]_CH[x]_GPR1 , the GPR overflow detected bit is set together in the ACB field

(ACB(1)) with the timeout bit (ACB(2)) and the values are marked as valid to the ARU.

The ACB bit 2 is cleared, when a successful ARU write access by the TIM channel took place.

The ACB bit 1 is cleared after a successful ARU write access by the TIM channel took place.

When a valid edge initiates an ARU write access which has not ended while a new timeout occurs, the GPR overflow detected bit (ACB(1)) is set. The bit ACB(0) will be updated to the level on which the timeout occurred.

When a timeout occurred and initiates an ARU write access which has not ended while a new timeout occurs the GPR overflow detected bit (ACB(1)) is not set.

The following table clarifies the meaning of the ACB bits for valid data provided by a TIM channel.

Table 86. ARU Control Bits (ACB) definition for valid data provided by a TIM channel

ACB4/3 ACB2 ACB1 ACB0 Description dc dc dc dc

Valid edge detected

Input edge overwritten by subsequent edge

Timeout detected without valid edge

Timeout detected with subsequent valid edge detected

10.4.1 Overview

Each TIM channel consists of an input edge counter ECNT , a Signal Measurement Unit

(SMU) with a counter CNT , a counter shadow register CNTS for SMU counter and two general purpose registers GPR0 and GPR1 for value storage.

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The value TOV of the timeout register TIM[i]_CH[x]_TDU is provided to TDU subunit of each individual channel for timeout measurement. The architecture of the TIM channel is depicted in

Figure 30 .

Figure 30. TIM channel architecture

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Each TIM channel receives both input trigger signals REDGE_DETx and FEDGE_DETx, generated by the corresponding filter module in order to signalize a detected echo of the input signal F_INx . The signal F_OUTx shows the filtered signal of the channel's input signal

F_INx .

The edge counter ECNT counts every incoming filtered edge (rising and falling). The counter value is uneven in case of detected rising, and even in case of detected falling edge. Thus, the input signal level is part of the counter and can be obtained by bit 0 of

ECNT . (However, the actual counter implementation counts only falling edges on ECNT[n:1] bits. It generates ECNT by composing the ECNT[n:1] bits with F_OUTx as bit 0).

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Thus, the whole ECNT counter value is always odd, when a positive edge was received and always even, when a negative edge was received.

The current ECNT[7:0] register content is made visible on the bits 31 down to 24 of the registers GPR0 , GPR1 and CNTS . This allows the software to detect inconsistent read accesses to registers GPR0 , GPR1 , and CNTS . However, the update strategy of these registers depends on the selected TIM modes, and thus the consistency check has to be adapted carefully.

It can be chosen with the bit field FR_ECNT_OFL when an ECNT overflow is signaled on

ECNTOFL . An ECNT overflow can be signaled on 8 bit or full range resolution.

While reading the register TIM[i]_CH[x]_ECNT the bit ECNT[0] shows the input signal value F_OUTx independent of the state (enabled / disabled) of the channel. If a channel gets disabled (OSM mode or resetting TIM_EN) the content of TIM[i]_CH[x]_ECNT will be frozen until a read of the register takes place. This read will reset the ECNT counter.

Continuing reads will show the input signal value in bit ECNT[0] again.

When new data is written into GPR0 and GPR1 the NEWVAL bit is set in

TIM[i]_CH[x]_IRQ_NOTIFY register and depending on the corresponding enable bit value the NEWVALx_IRQ interrupt is raised.

Each TIM input channel has an ARU connection for providing data via the ARU to the other

GTM submodules. The data provided to the ARU depends on the TIM channel mode and its corresponding adjustments (e.g. multiplexer configuration).

The bit ARU_EN of register TIM[i]_CH[x]_CTRL decides, whether the measurement results of registers GPR0 and GPR1 are consumed by another submodule via ARU ( ARU_EN = 1) or the CPU via AEI ( ARU_EN = 0).

To guarantee a consistent delivery of data from the GPR0 and GPR1 registers to the ARU or the CPU each TIM channel has to ensure that the data is consumed before it is overwritten with new values.

If new data was produced by the TIM channel (bit NEWVAL is set inside

TIM[i]_CH[x]_IRQ_NOTIFY register) while the old data is not consumed by the ARU

( ARU_EN = 1) or CPU ( ARU_EN = 0), the TIM channel sets the GPROFL bit inside the status register TIM[i]_CH[x]_IRQ_NOTIFY and it overwrites the data inside the GPR0 and

GPR1 registers. In addition, when ARU_EN = 1 , the bit ACB(1) bit is set to 1 to indicate the overflow in the ARU data.

If the CPU is selected as consumer for the GPR0 and GPR1 registers ( ARU_EN = 0), the acknowledge for reading out data is performed by a read access to the register GPR0 .

Thus, register GPR1 should be read always before GPR0 .

If the ARU is selected as consumer for the GPR0 and GPR1 registers ( ARU_EN = 1), the acknowledge for reading out data is performed by the ARU itself. However, the GPR0 and

GPR1 registers could be read by CPU without giving an acknowledge.

10.4.2 TIM channel modes

The TIM provides six different measurement modes that can be configured with the bit field

TIM_MODE of register TIM[i]_CH[x]_CTRL . The measurement modes are described in the following subsections. Besides these different basic measurement modes, there exist

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

DSL : control the signal level for the measurement modes (e.g. if a measurement is started with rising edge or falling edge, or if high level pulses or low level pulses are measured.



EGPR0_SEL, GPR0_SEL and EGPR1_SEL, GPR1_SEL : control the actual content of the registers GPR0 and GPR1 after a measurement has finished.



CNTS_SEL : control the content of the registers CNTS. The actual time for updating the

CNTS register is mode dependent.



OSM : activate measurement in one-shot mode or continuous mode. In one-shot mode only one measurement cycle is performed and after that the channel is disabled.



NEWVAL : the NEWVAL IRQ interrupt is triggered at the end of a measurement cycle, signaling that the registers GPR0 and GPR1 are updated.



ARU_EN : enables sending of the registers GPR0 and GPR1 together with the actual signal level (in bit 48) and the overflow signal GPROFL (in bit 49), and the timeout status information (bit 50) to the ARU.



EXT_CAP_EN : forces an update of the registers GPR0 and GPR1 and CNTS (TIM channel mode dependant) only on each rising edge of the EXT_CAPTURE signal and triggers a NEWVAL IRQ interrupt. If this mode is disabled the NEWVAL IRQ interrupt is triggered at the end of each measurement cycle.



For each channel the source of the EXT_CAPTURE signal can be configured with the bit fields EXT_CAP_SRC in the register TIM[i]_CH[x]_ECTRL.

10.4.2.1 TIM PWM Measurement Mode (TPWM)

In TIM PWM Measurement Mode the TIM channel measures duty cycle and period of an incoming PWM signal. The DSL bit defines the polarity of the PWM signal to be measured.

When measurement of pulse high time and period is requested (PWM with a high level duty cycle, DSL =1), the channel starts measuring after the first rising edge is detected by the filter.

Measurement is done with the CNT register counting with the configured clock coming from

CMU_CLKx until a falling edge is detected.

Then the counter value is stored inside the shadow register CNTS (if CNTS_SEL = 0) and the counter CNT counts continuously until the next rising edge is reached.

On this following rising edge the content of the CNTS register is transferred to GPR0 and the content of CNT register is transferred to GPR1 , assuming settings for the selectors

GPR0_SEL =11 and GPR1_SEL =11. By this, GPR0 contains the duty cycle length and

GPR1 contains the period. It should be noted, that the bits 1 to 7 of the ECNT may be used to check data consistency of the registers GPR0 and GPR1 .

In addition the CNT register is cleared NEWVAL status bit inside of

TIM[i]_CH[x]_IRQ_NOTIFY status register and depending on corresponding interrupt enable condition TIM_NEWVALx_IRQ interrupt is raised.

The CNTS register update is not performed until the measurement is started (first edge defined by DSL is detected). Afterwards each edge leaving the level defined by DSL is performing a CNTS register update.

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If a PWM with a low level duty cycle should be measured ( DSL = 0), the channel waits for a falling edge until measurement is started. On this edge the low level duty cycle time is stored first in CNTS and then finally in GPR0 and the period is stored in GPR1 .

When a PWM period was successfully measured, the data in the GPR0 and GPR1 registers is marked as valid for reading by the ARU when the ARU_EN bit is set inside

TIM[i]_CH[x]_CTRL register, the NEWVAL bit is set inside the TIM[i]_CH[x]_IRQ_NOTIFY register, and a new measurement is started.

If the preceding PWM values were not consumed by a reader attached to the ARU

( ARU_EN bit enabled) or by the CPU the TIM channel set GPROFL status bit in

TIM[i]_CH[x]_IRQ_NOTIFY and depending on the corresponding interrupt enable bit value raises a GPROFL_IRQ and overwrites the old values in GPR0 and GPR1 . A new measurement is started afterwards.

If the register CNT produces an overflow during the measurement, the bit CNTOFL is set inside the register TIM[i]_CH[x]_IRQ_NOTIFY and interrupt TIM_CNTOFL[x]_IRQ is raised depending on the corresponding interrupt enable condition.

If the register ECNT produces an overflow during the measurement, the bit ECNTOFL is set inside the register TIM[i]_CH[x]_IRQ_NOTIFY and interrupt TIM_ECNTOFL[x]_IRQ i s raised depending on the corresponding interrupt enable condition.

Input signal

F_OUTx

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

10.4.2.1.1 External capture TIM PWM Measurement Mode (TPWM)

If external capture is enabled, the PWM measurement is done continuously. The actual measurement values are captured to GPRx if an external capture events occurs.

Operation is done depending on CMU clock, ISL, DSL bit and the input signal value defined in next table.

Table 87. External capture TPWM operation

Selected CMU clock

External capture ISL

DSL

Action description

CNT++

Capture CNT value in CNTS

CNT=0

Capture CNT value in CNTS;

CNT=0

CNT++

Capture CNT value in CNTS

CNT=0

Capture CNT value in CNTS;

CNT=0

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Input signal

F_OUTx

Table 87. External capture TPWM operation (continued)

Selected CMU clock

External capture ISL DSL Action description

Rising edge

0 -

Do GPRx capture; issue

NEWVAL_IRQ

The CNTS register update is not performed until the measurement is started (first edge defined by DSL is detected). Afterwards, the update of CNTS register is defined by ISL and

DSL combinations as described in

Table 87 .

10.4.2.2 TIM Pulse Integration Mode (TPIM)

In TIM Pulse Integration Mode each TIM channel is able to measure a sum of pulse high or low times on an input signal, depending on the selected signal level bit DSL of register

TIM[i]_CH[x]_CTRL register.

The pulse times are measured by incrementing the TIM channel counter CNT whenever the pulse has the specified signal level DSL . The counter is stopped whenever the input signal has the opposite signal level.

The counter CNT counts with the CMU_CLKx clock specified by the CLK_SEL bit field of the TIM[i]_CH[x]_CTRL register.

The CNT register is reset at the time the channel is activated (enabling via AEI write access) and it accumulates pulses while the channel is staying enabled.

Whenever the counter is stopped, the registers CNTS , GPR0 and GPR1 are updated according to settings of its corresponding input multiplexers, using the bits EGPR0_SE L,

EGPR1_SE L, GPR0_SE L, GPR1_SE L, and CNTS_SEL . It should be noted, that the bits 1 to 7 of the ECNT may be used to check data consistency of the registers GPR0 and GPR1 .

When the ARU_EN bit is set inside the TIM[i]_CH[x]_CTRL register the measurement results of the registers GPR0 and GPR1 can be send to subsequent submodules attached to the ARU.

10.4.2.2.1 External capture TIM Pulse Integration Mode (TPIM)

If external capture is enabled, the pulse integration is done until next external capture event occurs.

Operation is done depending on cmu clock, DSL bit and the input signal value defined in next table.

Input signal

F_OUTx

Table 88. External capture TPIM operation

Selected CMU clock

External capture

ISL DSL Action description

CNT++

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Input signal

F_OUTx

Table 88. External capture TPIM operation (continued)

Selected CMU clock

External capture

ISL DSL Action description

Rising edge

0 -

Do capture; issue

NEWVAL_IRQ; CNT=0

10.4.2.3 TIM Input Event Mode (TIEM)

In TIM input event mode the TIM channel is able to count edges.

It is configurable if rising, falling or both edges should be counted. This can be done with the bit fields DSL and ISL in TIM[i]_CH[x]_CTRL register.

In addition, a TIM[i]_NEWVAL[x]_IRQ interrupt is raised when the configured edge was received and this interrupt was enabled.

The counter register CNT is used to count the number of edges, and the bit fields

EGPR0_SE L, EGPR1_SE L, GPR0_SEL , GPR1_SEL , and CNTS_SEL can be used to configure the desired update values for the registers GPR0 , GPR1 and CNTS . These register are updated whenever the edge counter CNT is incremented due to the arrival of a desired edge.

If the preceding data was not consumed by a reader attached to the ARU or by the CPU the

TIM channel sets GPROFL status bit and raises a GPROFL[x]_IRQ if it was enabled in

TIM[i]_CH[x]_IRQ_EN register and overwrites the old values in GPR0 and GPR1 with the new ones.

If the register CNT produces an overflow during the measurement, the bit CNTOFL is set inside the register TIM[i]_CH[x]_IRQ_NOTIFY and interrupt TIM_CNTOFL[x]_IRQ i s raised depending on corresponding interrupt enable condition.

The TIM Input Event Mode does not depend on the bit field CLK_SEL of register

TIM[i]_CH[x]_CTRL .

10.4.2.3.1 External capture TIM Input Event Mode (TIEM)

If external capture is enabled, capturing is done depending on the DSL , ISL bit and the input signal value defined in next table.

Table 89. External capture TIEM operation

Input signal

F_OUTx

External capture

Rising edge

ISL

DSL

Action description

Do capture; issue NEWVAL_IRQ; CNT++

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Table 89. External capture TIEM operation (continued)

Input signal

F_OUTx

External capture

Rising edge

ISL

DSL

Action description

Do capture; issue NEWVAL_IRQ; CNT++

10.4.2.4 TIM Input Prescaler Mode (TIPM)

In the TIM input prescaler mode the number of edges which should be detected before a

T IM[i]_NEWVAL[x]_IRQ is raised is programmable. In this mode it must be specified in the

CNTS register after how many edges the interrupt has to be raised.

A value of 0 in CNTS means that after one edge an interrupt is raised and a value of 1 means that after two edges an interrupt is raised, and so on.

The edges to be counted can be selected by the bit fields DSL and ISL of register

TIM[i]_CH[x]_CTRL .

With each triggered interrupt, the registers GPR0 and GPR1 are updated according to bits

EGPR0_SE L, EGPR1_SE L, GPR0_SEL and GPR1_SEL .

The TIM Input Prescaler Mode does not depend on the bit field CLK_SEL of register

TIM[i]_CH[x]_CTRL .

10.4.2.4.1 External capture TIM Input Prescaler Mode (TIPM)

If external capture is enabled, the external capture events are counted instead of the input signal edges.

Operation is done depending on the external capture signal, DSL , ISL bit and the input signal value defined in next table.

Table 90. External capture TIPM operation

Input signal

F_OUTx

External capture ISL DSL Action description

0 -

Rising edge

1 if CNT == CNTS then do capture; issue NEWVAL_IRQ; CNT=0 else

CNT++ endif

No if CNT == CNTS then do capture; issue NEWVAL_IRQ; CNT=0 else

CNT++ endif

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Input signal

F_OUTx

Table 90. External capture TIPM operation (continued)

External capture ISL DSL Action description

Rising edge 0

0 if CNT == CNTS then do capture; issue NEWVAL_IRQ; CNT=0 else

CNT++ endif

10.4.2.5 TIM Bit Compression Mode (TBCM)

The TIM bit compression mode can be used to combine all filtered input signals of a TIM submodule to a parallel m bit data word, which can be routed to the ARU, where m is the number of channels available in the TIM submodule.

Since this mode uses all available input signals with its input filters, it is only available within

TIM channel 0 of each TIM submodule. Figure 31

gives an overview of the TIM bit compression mode.

Figure 31. TIM bit compression mode

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The register CNTS of TIM channel 0 is used to configure the event that releases the

NEWVAL_IRQ and samples the input signals F_IN(0) to F_IN( m -1) in ascending order as a parallel data word in GPR1 .

The bits 0 to m-1 of the CNTS register are used to select the REDGE_DET signals of the

TIM filters 0 to m-1 as a sampling event, and the bits 8 to (7+ m ) are used to select the

FEDGE_DET signals of the TIM filters 0 to m-1 , respectively. If multiple events are selected, the events are OR-combined (see also

Figure 31 ).

EGPR0_SE L, GPR0_SEL selects the time stamp value, which is routed through the ARU.

GPR1_SEL is not applicable in TBCM mode.

If the bit ARU_EN of register TIM[i]_CH0_CTRL is set, the sampled data of register GPR1 is routed together with a time stamp of register GPR0 to the ARU, whenever the

NEWVAL_IRQ is released.

In TIM Bit compression mode, the register ECNT increments with each NEWVAL_IRQ , which means that the value of ECNT may depend on all m input signals. Consequently, the

LSB of ECNT does not reflect the actual level of the input signal TIM_IN0.

The TIM Bit Compression Mode does not depend on the bit field CLK_SEL of register

TIM[i]_CH[x]_CTRL .

10.4.2.5.1 External capture Bit Compression Mode (TBCM)

If external capture is enabled, capturing is done depending on the DSL , ISL bit and the input signal value defined in next table.

Table 91. External capture TBCM operation

Input signal

F_OUTx

External capture ISL DSL Action description

Rising edge

Do capture; issue NEWVAL_IRQ;

CNT++

Do capture; issue NEWVAL_IRQ;

CNT++

Do capture; issue NEWVAL_IRQ;

CNT++

10.4.2.6 TIM Gated Periodic Sampling mode (TGPS)

In the TIM Gated Periodic Sampling Mode the number of CMU clock cycles which should elapse before capturing and raising TIM[i]_NEWVAL[x]_IRQ is programmable. In this mode it must be specified in the CNTS register after how many CMU clock cycles the interrupt has to be raised.

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A value of 0 in TIM[i]_CH[x]_CNTS means that after one CLK_SEL edge a trigger/interrupt is raised, and a value of 1 means that after two edges a trigger/interrupt is raised, and so on.

In the TIM[i]_CH[x]_CNT register the elapsed cycles were incremented and compared against TIM[i]_CH[x]_CNTS . If TIM[i]_CH[x]_CNT is greater or equal to

TIM[i]_CH[x]_CNTS a trigger will be raised. This allows by writing a value to

TIM[i]_CH[x]_CNTS that the actual period time can be changed on the fly.

Operation is done depending on CMU clock, DSL , ISL bit and the input signal value defined in next table:

Input signal

F_OUTx

Selected CMU clock

Table 92. TGPS operation

External capture

ISL DSL Action description

if CNT == CNTS then do capture; issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

No if CNT == CNTS then do capture;issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

No if CNT == CNTS then do capture;issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

In this mode the TIM[i]_CH[x]_GPR1 operates as a shadow register for

TIM[i]_CH[x]_CNTS . This would allow that the period for the next sampling period could be specified. The update of TIM[i]_CH[x]_CNTS will only take place once on a trigger if the

TIM[i]_CH[x]_GPR1 was written by the CPU. This means that the captured value from the previous trigger can be read by the CPU from TIM[i]_CH[x]_GPR1 and afterwards the new sampling period for the next sampling period (the one after the actual sampling period) could be written.

With each triggered interrupt, the registers GPR0 and GPR1 are updated according to bits

GPR0_SEL , GPR1_SEL, EGPR0_SEL and EGPR1_SEL .

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When selecting ECNT as a source for the capture registers, GPRx will show the edge count and the input signal value at point of capture. Selecting GPR0_SEL = '11' and

EGPR0_SEL = '0' for TIM channel 0 all 8 TIM input signals will be captured to GPR0[7:0] .

In the TGPS Mode the bit field CLK_SEL of register TIM[i]_CH[x]_CTRL will define the selected CMU clock which will be used.

The behavior of the ECNT counter is configurable by ECNT_RESET . If set to 1 on each interrupt (period expired) the ECNT will be reset. Otherwise it operates in wrap around mode.

10.4.2.6.1 External capture TIM Gated Periodic Sampling Mode (TGPS)

If external capture is enabled, the external capture events will capture the GPRx, reset the counter CNT and issue a NEWVAL_IRQ .

Operation is done depending on the CMU clock, external capture signal, DSL , ISL bit and the input signal value defined in next table.

Input signal

F_OUTx

Table 93. External capture TGPS operation

Selected CMU clock

External capture

ISL DSL Action description

Rising edge

0 if CNT == CNTS then do capture; issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

No if CNT == CNTS then do capture; issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

No if CNT == CNTS then do capture; issue

NEWVAL_IRQ; CNT=0 else

CNT++ endif

No do capture; issue

NEWVAL_IRQ; CNT =0

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10.5 MAP submodule interface

The GTM-IP provides one dedicated TIM submodule TIM0 where channels zero (0) to five

(5) are connected to the MAP submodule described in Chapter 15: TIM0 input mapping module (MAP) . There, the TIM0 submodule channels provide the input signal level together

with the actual filter value and the annotated time stamp for the edge together in a 49-bit wide signal to the MAP submodule. This 49-bit wide data signal is marked as valid with a separate valid signal tim0_map_dval[x] (x: 0...5).

tim0_map_data[x](48) tim0_map_data[x](47:24)

Table 94. TIM0 49-bit output data to MAP

Signal level bit from tim0_ch[x]

Actual filter value

TIM0_CH[x]_FLT_RE

TIM0_CH[x]_FLT_FE if corresponding channel x bit field

FLT_MODE_RE

FLT_MODE_FE

is 1 else 0 is assigned.

tim0_map_data[x](23:0) tim0_map_dval[x]

Time stamp value selected by TBU0_SEL, GRP0_SEL,

EGPR0_SEL, CNTS_SEL

of channel x if bit field

TIM_EN

= 1

Mark tim0_map_data[x] valid for one clock cycle

Note:

With TIM_EN=1 the MAP interface starts operation, it is not depending on the setting of the bit fields TIM_MODE, ISL, DSL.

While the MAP interface is in use the following guidelines have to be fulfilled, otherwise inconsistent filter values can be transferred.

Change TIM0_CH[x]_FLT_RE only between occurrence of rising and falling edge.

Change TIM0_CH[x]_FLT_FE only between occurrence of falling and rising edge.

10.6 TIM interrupt signals

TIM provides 6 interrupt lines per channel. These interrupts are shown below.

Signal

TIM[i]_NEWVAL[x]_IRQ

TIM[i]_ECNTOFL[x]_IRQ

TIM[i]_CNTOFL[x]_IRQ

TIM[i]_GPROF[x]_IRQ

TIM[i]_TODET[x]_IRQ

TIM[i]_GLITCHDET_IRQ

Table 95. TIM interrupt signals

Description

New measurement value detected by SMU of channel x (x: 0...m-1)

ECNT counter overflow of channel x (x: 0...m-1)

SMU CNT counter overflow of channel x (x: 0...m-1)

GPR0 and GPR1 data overflow, old data was not read out before new data has arrived at input pin of channel x (x: 0...m-1)

Time out reached for input signal of channel x (x: 0...m-1)

A glitch was detected by the TIM filter of channel x (x: 0...m-1)

10.7 TIM configuration registers overview

TIM contains following configuration registers.

TIM_6

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Register name

TIM[i]_CH[x]_CTRL, i>0

TIM0_CH[x]_CTRL

TIM[i]_CH[x]_ECTRL

TIM[i]_CH[x]_FLT_RE

TIM[i]_CH[x]_FLT_FE

TIM[i]_CH[x]_TDUV

TIM[i]_CH[x]_TDUC

TIM[i]_CH[x]_GPR0

TIM[i]_CH[x]_GPR1

TIM[i]_CH[x]_CNT

TIM[i]_CH[x]_ECNT

TIM[i]_CH[x]_CNTS

TIM[i]_CH[x]_IRQ_NOTIFY

TIM[i]_CH[x]_IRQ_EN

TIM[i]_CH[x]_EIRQ_EN

TIM[i]_CH[x]_IRQ_FORCINT

TIM[i]_CH[x]_IRQ_MODE

TIM[i]_RST

TIM[i]_IN_SRC

Timer Input Module (TIM)

Table 96. TIM configuration registers

Description channel x (x:0...m-1) control channel x (x:1...m-1) control channel x (x:0...m-1) extended control channel x (x:0...m-1) filter parameter 0 channel x (x:0...m-1) filter parameter 1 channel x (x:0...m-1) TDU control. channel x (x:0...m-1) TDU counter. channel x (x:0...m-1) general purpose 0 channel x (x:0...m-1) general purpose 1 channel x (x:0...m-1) SMU counter channel x (x:0...m-1) SMU edge counter channel x (x:0...m-1) SMU shadow counter channel x (x:0...m-1) interrupt notification channel x (x:0...m-1) interrupt enable channel x (x:0...m-1) error interrupt enable channel x (x:0...m-1) software interrupt force

IRQ mode configuration register (x=0...m-1)

TIM global software reset

TIM AUX IN source selection

Detail in section

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

00 0 0 0 000 0 0 0 0 0 00 0 0 0 0 0 00 00 0 0 0 0 000 0

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Table 97. TIM[i]_CH[x]_CTRL field description

Description

TIM_EN : TIM channel x (x:0...7) enable

0 = Channel disabled

1 = Channel enabled

Note:

Enabling of the channel resets the registers ECNT, TIM[i]_CH[x]_CNT,

TIM[i]_CH[x]_GPR0, and TIM[i]_CH[x]_GPR1 to their reset values.

Note:

After finishing the action in one-shot mode the TIM_EN bit is cleared automatically.

Otherwise, the bit must be cleared manually.

TIM_MODE

: TIM channel x (x:0...7) mode

000 = PWM Measurement Mode (TPWM)

001 = Pulse Integration Mode (TPIM)

010 = Input Event Mode (TIEM)

011 = Input Prescaler Mode (TIPM)

100 = Bit Compression Mode (TBCM)

101 = Gated Periodic Sampling Mode (TGPS)

Note: The Bit Compression Mode is only available in TIM channel 0. If this mode is selected in any other channels, the TIM_MODE = 000 (TPWM mode) is used instead. However, the register TIM_MODE is read with value 100.

Note: If an undefined value is written to the TIM_MODE register, the hardware switches automatically to TIM_MODE = 000 (TPWM mode).

Note: The TIM_MODE register should not be changed while the TIM channel is enabled.

Note: If the TIM channel is enabled and operating in TPWM or TPIM mode after the first valid edge defined by DSL has occurred, a reconfiguration of DSL,ISL,TIM_MODE will not change the channel behavior. Reading these bit fields after reconfiguration will show the newly configured settings but the initial channel behavior will not change. Only a disabling of the TIM channel by setting TIM_EN= 0 and re enabling with TIM_EN= 1 will change the channel operation mode.

OSM : One-shot mode

0 = Continuous operation mode

1 = One-shot mode

Note:

After finishing the action in one-shot mode the TIM_EN bit is cleared automatically.

CICTRL

: Channel Input Control.

0 = use signal TIM_IN(x) as input for channel x

1 = use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is 0)

CICTRL

: Channel Input Control.

0 = use signal TIM_IN(x) as input for channel x

1 = use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is 0)

Reserved

Note: Read as zero, should be written as zero.

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Table 97. TIM[i]_CH[x]_CTRL field description (continued)

Description

GPR0_SEL : Selection for GPR0 register

If EGPR0_SEL =0:

00 = use TBU_TS0 as input

01 = use TBU_TS1 as input

10 = use TBU_TS2 as input

11 = use CNTS as input; if TGPS mode in channel = 0 is selected use TIM Filter F_OUT as input

If EGPR0_SEL =1:

00 = use ECNT as input

01 = reserved

10 = reserved

11 = reserved

Note: If a reserved value is written to the EGPR0_SEL, GPR0_SEL bit fields, the hardware will use TBU_TS0 input.

GPR1_SEL : Selection for GPR1 register

If EGPR1_SEL =0:

00 = use TBU_TS0 as input

01 = use TBU_TS1 as input

10 = use TBU_TS2 as input

11 = use CNT as input

If EGPR1_SEL =1:

00 = use ECNT as input

01 = reserved

10 = reserved

11 = reserved

Note:

In TBCM mode EGPR1_SEL, GPR1_SEL are ignored TIM Filter F_OUT is used as input

Note:

If a reserved value is written to the EGPR1_SEL, GPR1_SEL bit fields, the hardware will use TBU_TS0 input.

CNTS_SEL

: Selection for CNTS register

0 = use CNT register as input

1 = use TBU_TS0 as input

Note: The functionality of the CNTS_SEL is disabled in the modes TIPM and TBCM.

DSL

: Signal level control

0 = Measurement starts with falling edge (low level measurement)

1 = Measurement starts with rising edge (high level measurement)

ISL : Ignore signal level

0 = use DSL bit for selecting active signal level

1 = ignore DSL and treat both edges as active edge

Note:

This bit is only applicable in Input Event mode (TIEM)

ECNT_RESET

: Enables resetting the ECNT counter in periodic sampling mode

0 = ECNT counter operating in wrap around mode

1 = ECNT counter is reset with periodic sampling

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Table 97. TIM[i]_CH[x]_CTRL field description (continued)

Description

FLT_EN : Filter enable for channel x (x:0...7)

0 = Filter disabled and internal states are reset

1 = Filter enabled

Note:

If the filter is disabled all filter related units (including CSU) are bypassed, which means that the signal F_IN is directly routed to signal F_OUT.

FLT_CNT_FRQ

: Filter counter frequency select

00 = FLT_CNT counts with CMU_CLK0

01 = FLT_CNT counts with CMU_CLK1

10 = FLT_CNT counts with CMU_CLK6

11 = FLT_CNT counts with CMU_CLK7

EXT_CAP_EN : Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored.

0 = External capture disabled

1 = External capture enabled

FLT_MODE_RE : Filter mode for rising edge.

0 = Immediate edge propagation mode

1 = individual de-glitch mode

FLT_CTR_RE

: Filter counter mode for rising edge.

0 = Up/down counter

1 = Hold counter

Note: This bit is only applicable in Individual Deglitch Time Mode

FLT_MODE_FE

: Filter mode for falling edge.

0 = Immediate edge propagation mode

1 = Individual de-glitch mode

FLT_CTR_FE : Filter counter mode for falling edge.

0 = Up/down counter

1 = Hold counter

CLK_SEL : CMU clock source select for channel.

000 = CMU_CLK0 selected

001 = CMU_CLK1 selected

010 = CMU_CLK2 selected

011 = CMU_CLK3 selected

100 = CMU_CLK4 selected

101 = CMU_CLK5 selected

110 = CMU_CLK6 selected

111 = CMU_CLK7 selected

FR_ECNT_OFL : Extended Edge counter overflow behavior

0 = Overflow will be signaled on ECNT bit width = 8

1 = Overflow will be signaled on EECNT bit width (full range)

EGPR0_SEL

: Extension of GPR0_SEL bit field.

Details described in GPR0_SEL bit field.

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Table 97. TIM[i]_CH[x]_CTRL field description (continued)

Description

EGPR1_SEL : Extension of GPR1_SEL bit field.

Details described in GPR1_SEL bit field.

TOCTRL : Timeout control

00 = Timeout feature disabled

11 = Timeout feature enabled for both edges

01 = Timeout feature enabled for rising edge only

10 = Timeout feature enabled for falling edge only

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 00 0 0 0 000 0 0 0 0 0 00 0 0 0 0 0 00 00 0 0 0 0 000 0

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Table 98. TIM0_CH[x]_CTRL field description

Description

TIM_EN : TIM channel x (x:0...m-1) enable

0 = Channel disabled

1 = Channel enabled

Note:

Enabling of the channel resets the registers ECNT, TIM[i]_CH[x]_CNT,

TIM[i]_CH[x]_GPR0, and TIM[i]_CH[x]_GPR1 to their reset values.

Note:

After finishing the action in one-shot mode the TIM_EN bit is cleared automatically.

Otherwise, the bit must be cleared manually.

TIM_MODE

: TIM channel x (x:0...m-1) mode

000 = PWM Measurement Mode (TPWM)

001 = Pulse Integration Mode (TPIM)

010 = Input Event Mode (TIEM)

011 = Input Prescaler Mode (TIPM)

100 = Bit Compression Mode (TBCM)

101 = Gated Periodic Sampling Mode (TGPS)

Note: If an undefined value is written to the TIM_MODE register, the hardware switches automatically to TIM_MODE = 000 (TPWM mode).

Note: The TIM_MODE register should not be changed while the TIM channel is enabled.

OSM

: One-shot mode

0 = Continuous operation mode

1 = One-shot mode

Note:

After finishing the action in one-shot mode the TIM_EN bit is cleared automatically.

ARU_EN

: GPR0 and GPR1 register values routed to ARU

0 = Registers content not routed

1 = Registers content routed

CICTRL

: Channel Input Control.

0 = Use signal TIM_IN(x) as input for channel x

1 = Use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is 0)

TBU0_SEL : TBU_TS0 bits input select for TIM0_CH[x]_GPRz (z: 0, 1)

0 = Use TBU_TS0(23.0) to store in TIM0_CH[x]_GPR0/TIM0_CH[x]_GPR1

1 = Use TBU_TS0(26.3) to store in TIM0_CH[x]_GPR0/TIM0_CH[x]_GPR1.

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Table 98. TIM0_CH[x]_CTRL field description (continued)

Description

GPR0_SEL : Selection for GPR0 register

If EGPR0_SEL =0:

00 = use TBU_TS0 as input

01 = use TBU_TS1 as input

10 = use TBU_TS2 as input

11 = use CNTS as input; if TGPS mode in channel = 0 is selected use TIM Filter F_OUT as input

If EGPR0_SEL =1:

00 = use ECNT as input

01 = reserved

10 = reserved

11 = reserved

Note: If a reserved value is written to the EGPR0_SEL, GPR0_SEL bit fields, the hardware will use TBU_TS0 input.

GPR1_SEL : Selection for GPR1 register

If EGPR1_SEL =0:

00 = use TBU_TS0 as input

01 = use TBU_TS1 as input

10 = use TBU_TS2 as input

11 = use CNT as input

If EGPR1_SEL =1:

00 = use ECNT as input

01 = reserved

10 = reserved

11 = reserved

Note:

In TBCM mode EGPR1_SEL, GPR1_SEL are ignored TIM Filter F_OUT is used as input

Note:

If a reserved value is written to the EGPR1_SEL, GPR1_SEL bit fields, the hardware will use TBU_TS0 input.

CNTS_SEL

: Selection for CNTS register

0 = use CNT register as input

1 = use TBU_TS0 as input

Note: The functionality of the CNTS_SEL is disabled in the modes TIPM and TBCM.

DSL

: Signal level control

0 = Measurement starts with falling edge (low level measurement)

1 = Measurement starts with rising edge (high level measurement)

ISL : Ignore signal level

0 = use DSL bit for selecting active signal level

1 = ignore DSL and treat both edges as active edge

Note:

This bit is only applicable in Input Event mode (TIEM)

ECNT_RESET

: Enables resetting the ECNT counter in periodic sampling mode

0 = ECNT counter operating in wrap around mode

1 = ECNT counter is reset with periodic sampling

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Table 98. TIM0_CH[x]_CTRL field description (continued)

Description

FLT_EN : Filter enable for channel x (x:0...m-1)

0 = Filter disabled and internal states are reset

1 = Filter enabled

Note:

If the filter is disabled all filter related units (including CSU) are bypassed, which means that the signal F_IN is directly routed to signal F_OUT.

FLT_CNT_FRQ

: Filter counter frequency select

00 = FLT_CNT counts with CMU_CLK0

01 = FLT_CNT counts with CMU_CLK1

10 = FLT_CNT counts with CMU_CLK6

11 = FLT_CNT counts with CMU_CLK7

EXT_CAP_EN : Enables external capture mode. The selected TIM mode is only sensitive to external capture pulses the input event changes are ignored.

0 = External capture disabled

1 = External capture enabled

FLT_MODE_RE : Filter mode for rising edge.

0 = Immediate edge propagation mode

1 = individual de-glitch mode

FLT_CTR_RE

: Filter counter mode for rising edge.

0 = Up/down counter

1 = Hold counter

Note: This bit is only applicable in Individual deglitch time mode

FLT_MODE_FE

: Filter mode for falling edge.

0 = Immediate edge propagation mode

1 = Individual de-glitch mode

FLT_CTR_FE : Filter counter mode for falling edge.

0 = Up/down counter

1 = Hold counter

Note:

This bit is only applicable in Individual deglitch time mode

CLK_SEL : CMU clock source select for channel.

000 = CMU_CLK0 selected

001 = CMU_CLK1 selected

010 = CMU_CLK2 selected

011 = CMU_CLK3 selected

100 = CMU_CLK4 selected

101 = CMU_CLK5 selected

110 = CMU_CLK6 selected

111 = CMU_CLK7 selected

FR_ECNT_OFL

: Extended Edge counter overflow behavior

0 = Overflow will be signaled on ECNT bit width = 8

1 = Overflow will be signaled on EECNT bit width (full range)

EGPR0_SEL

: Extension of GPR0_SEL bit field.

Details described in GPR0_SEL bit field.

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Table 98. TIM0_CH[x]_CTRL field description (continued)

Description

EGPR1_SEL : Extension of GPR1_SEL bit field.

Details described in GPR1_SEL bit field.

TOCTRL : Timeout control

00 = Timeout feature disabled

11 = Timeout feature enabled for both edges

01 = Timeout feature enabled for rising edge only

10 = Timeout feature enabled for falling edge only

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved FLT_RE Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 99. TIM[i]_CH[x]_FLT_RE field description

Description

FLT_RE

: Filter parameter for rising edge.

Note:

This register has different meanings in the various filter modes.

Immediate edge propagation mode = acceptance time for rising edge

Individual deglitch time mode = deglitch time for rising edge.

Reserved : reserved

Note: Read as zero, should be written as zero

10.8.4 Register TIM[i]_CH[x]_FLT_FE (x:0...m-1)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

FLT_FE

0x000000

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Table 100. TIM[i]_CH[x]_FLT_FE field description

Description

FLT_FE : Filter parameter for falling edge.

Note:

This register has different meanings in the various filter modes.

Immediate edge propagation mode = acceptance time for falling edge

Individual deglitch time mode = deglitch time for falling edge.

Reserved : reserved

Note:

Read as zero, should be written as zero

RM0361

Functionality is replaced by register TIM[i]_CH[x]_TDUV, TIM[i]_CH[x]_TDUC and bit field

TOCTRL in Register TIM[i]_CH[x]_CTRL

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ECNT GPR0 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 101. TIM[i]_CH[x]_GPR0 field description

Description

GPR0

: Input signal characteristic parameter 0.

Note:

The content of this register has different meaning for the TIM channels modes. The content directly depends on the bit fields EGPR0_SEL, GPR0_SEL of register

TIM[i]_CH[x]_CTRL.

ECNT : Edge counter.

Note:

The ECNT counts every incoming filtered edge (rising and falling). The counter value is uneven in case of detected rising, and even in case of detected falling edge. Thus, the input signal level is part of the counter and can be obtained by bit 0 of ECNT.

Note: The ECNT register is reset to its initial value when the channel is enabled. Please note, that bit 0 depends on the input level coming from the filter unit and defines the reset value immediately.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ECNT GPR1 Bit

Mode

Initial value

0x00

RPw

0x000000

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[8:31]

[0:7]

Timer Input Module (TIM)

Table 102. TIM[i]_CH[x]_GPR1 field description

Description

GPR1 : Input signal characteristic parameter 1.

Note:

The content of this register has different meaning for the TIM channels modes. The content directly depends on the bit fields EGPR1_SEL, GPR1_SEL of register

TIM[i]_CH[x]_CTRL.

Note: In TBCM mode EGPR1_SEL, GPR1_SEL are ignored; TIM Filter F_OUT is used as input, Bits GPR1(23:8) = 0.

Note: The content of this register can only be written in TIM channel mode TGPS.

ECNT

: Edge counter.

Note: The ECNT counts every incoming filtered edge (rising and falling). The counter value is uneven in case of detected rising, and even in case of detected falling edge. Thus, the input signal level is part of the counter and can be obtained by bit 0 of ECNT.

Note:

The ECNT register is reset to its initial value when the channel is enabled. Please note, that bit 0 depends on the input level coming from the filter unit and defines the reset value immediately.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

CNT

0x000000

Bit

[8:31]

[0:7]

Table 103. TIM[i]_CH[x]_CNT field description

Description

CNT

: Actual SMU counter value

Note: The meaning of this value depends on the configured mode:

TPWM = actual duration of PWM signal.

TPIM = actual duration of all pulses (sum of pulses).

TIEM = actual number of received edges.

TIPM = actual number of received edges.

Reserved

: reserved

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

ECNT CNTS Bit

Mode

Initial value

0x00

RPw

0x000000

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[8:31]

[0:7]

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Table 104. TIM[i]_CH[x]_CNTS field description

Description

CNTS : Counter shadow register.

Note:

The content of this register has different meaning for the TIM channels modes. The content depends directly on the bit field CNTS_SEL of register TIM[i]_CH[x]_CTRL.

Note:

The register TIM[i]_CH[x]_CNTS is only writable in TIPM,TBCM and TGPS mode.

ECNT: edge counter.

Note:

The ECNT register is reset to its initial value when the channel is enabled. Please note, that bit 0 depends on the input level coming from the filter unit and defines the reset value immediately.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:25]

0x0000000

Table 105. TIM[i]_CH[x]_IRQ_NOTIFY field description

Description

NEWVAL

: New measurement value detected by in channel x (x:0...m-1)

0 = No event was occurred

1 = NEWVAL was occurred on the TIM channel

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ECNTOFL: ECNT counter overflow of channel x, (x:0...m-1). see bit 31.

CNTOFL:

SMU

CNT

counter overflow of channel x, (x:0...m-1). see bit 31.

GPROFL: GPR0 and

GPR1 data overflow, old data not read out before new data has arrived at input pin, (x:0...m-1). see bit 31.

TODET: Timeout reached for input signal of channel x, (x:0...m-1). see bit 31.

GLITCHDET: Glitch detected on channel x, (x:0...m-1).

0 = no glitch detected for last edge

1 = glitch detected for last edge

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Reserved: reserved

Note:

Read as zero, should be written as zero

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:25]

0x0000000

Table 106. TIM[i]_CH[x]_IRQ_EN field description

Description

NEWVAL_IRQ_EN : TIM_NEWVALx_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

ECNTOFL_IRQ_EN: TIM_ECNTOFLx_IRQ interrupt enable, see bit 31.

CNTOFL_IRQ_EN: TIM_CNTOFLx_IRQ interrupt enable, see bit 31.

GPROFL_IRQ_EN: TIM_GPROFL_IRQ

interrupt enable, see bit 31.

TODET_IRQ_EN: TIM_TODETx_IRQ

interrupt enable, see bit 31.

GLITCHDET_IRQ_EN: TIM_GLITCHDETx_IRQ

interrupt enable, see bit 31.

Reserved.

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000000

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Bit

[0:25]

Table 107. TIM[i]_CH[x]_IRQ_FORCINT field description

Description

TRG_NEWVAL : Trigger NEWVAL bit in TIM_CHx_IRQ_NOTIFY register by software

0 = No interrupt triggering

1 = Assert corresponding field in TIM[i]_CH[x]_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_ECNTOFL:

Trigger

ECNTOFL bit in

TIM_CHx_IRQ_NOTIFY

TRG_CNTOFL: Trigger CNTOFL bit in TIM_CHx_IRQ_NOTIFY register by software, see bit 31.

TRG_GPROFL:

Trigger

GPROFL

bit in

TIM_CH[x]_IRQ_NOTIFY

TRG_TODET: Trigger TODET bit in TIM_CHx_IRQ_NOTIFY register by software, see bit 31.

TRG_GLITCHDET:

Trigger

GLITCHDET

bit in

TIM_CHx_IRQ_NOTIFY

31.

Reserved: reserved

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[30:31]

[0:29]

0x00000000

Table 108. TIM[i]_CH[x]_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note: The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved: reserved

Note: Read as zero, should be written as zero

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x000000 0 0 0 0 0 0 0 0

Bit

[0:23]

Table 109. TIM[i]_RST field description

Description

RST_CH0 : Software reset of channel 0

0 = No action

1 = Reset channel 0

Note:

This bit is cleared automatically after write by CPU. The channel registers are set to their reset values and channel operation is stopped immediately.

RST_CH1: Software reset of channel 1, see bit 31.

RST_CH2: Software reset of channel 2, see bit 31.

RST_CH3:

Software reset of channel 3, see bit 31.

RST_CH4:

Software reset of channel 4, see bit 31.

RST_CH5:

Software reset of channel 5, see bit 31.

RST_CH6: Software reset of channel 6, see bit 31.

RST_CH7: Software reset of channel 7, see bit 31.

Note: Please note, that the RST field width of this register depends on the number of implemented channels m within this submodule. This register description represents a register layout for m = 8.

Reserved.

Note: Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Bit

[30:31]

[28:29]

[8:9]

[6:7]

[4:5]

[2:3]

[0:1]

[26:27]

[24:25]

[22:23]

[20:21]

[16:17]

[14:15]

[12:13]

[10:11]

Table 110. TIM[i]_IN_SRC field description

Description

VAL_0 : Value to be fed to Channel 0 multicore encoding is used ( VALx(1) defines the state of the signal)

00 = State is 0 (ignore write access)

01 = Change of state to 0

10 = Change of state to 1

11 = State is 1 (ignore write access). The function depends on the combination of

VAL_x(1)

and

MODE_x(1) , see MODE_0 description

Note:

Any read access to a

VAL_x

, bit field will always result in a value 00 or 11 indicating current state. A modification of the state is only performed with the values 01 and 10. Writing the values 00 and 11 is always ignored.

MODE_0

: Input source to Channel 0

Multicore encoding is used (

MODE_x(1) defines the state of the signal).

00 = State is 0 (ignore write access)

01 = Change state to 0

10 = Change state to 1

11 = State is 1 (ignore write access)

Function table:

Mode_x(1)=0 , VAL_x(1)=0 : the input signal defined by the CICTRL bit field of the TIM channel is used as input source

Mode_x(1)=0 , VAL_x(1)=1 : the TIM_AUX_IN signal of the TIM channel is used as input source

Mode_x(1)=1 , VAL_x(1)=x : the state of VAL_x(1) defines the input level of the TIM channel

Note:

Any read access to a

MODE_x

, bit field will always result in a value 00 or 11 indicating current state. A modification of the state is only performed with the values 01 and 10.

Writing the values 00 and 11 is always ignored.

VAL_1:

Value to be fed to Channel 1, see bits [30:31].

MODE_1:

Input source to Channel 1, see bits [28:29].

VAL_2:

Value to be fed to Channel 2, see bits [30:31].

MODE_2:

Input source to Channel 2, see bits [28:29]

MODE_3: Input source to Channel 3, see bits [30:31].

VAL_4: Value to be fed to Channel 4, see bits [28:29].

MODE_4:

Input source to Channel 4, see bits [30:31].

VAL_5:

Value to be fed to Channel 5, see bits [28:29].

MODE_5:

Input source to Channel 5, see bits [30:31].

VAL_6:

Value to be fed to Channel 6, see bits [28:29].

MODE_6: Input source to Channel 6, see bits [30:31].

VAL_7: Value to be fed to Channel 7, see bits [28:29].

MODE_7: Input source to Channel 7, see bits [30:31].

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

[0:25]

0x0000000

Table 111. TIM[i]_CH[x]_EIRQ_EN field description

Description

NEWVAL_EIRQ_EN

: TIM_NEWVALx_EIRQ error interrupt enable

0 = Disable error interrupt, error interrupt is not visible outside GTM-IP

1 = Enable error interrupt, error interrupt is visible outside GTM-IP

ECNTOFL_EIRQ_EN : TIM_ECNTOFLx_IRQ interrupt enable, see bit 31.

CNTOFL_EIRQ_EN

: TIM_CNTOFLx_IRQ interrupt enable, see bit 31.

GPROFL_EIRQ_EN: TIM_GPROFL_IRQ

interrupt enable, see bit 31.

TODET_EIRQ_EN: TIM_TODETx_IRQ

interrupt enable, see bit 31.

GLITCHDET_EIRQ_EN: TIM_GLITCHDETx_IRQ interrupt enable, see bit 31.

Reserved.

Note: Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

TCS

000

Reserved

0x0000

TOV

0x00

Bit

[24:31]

[4:23]

Table 112. TIM[i]_CH[x]_TDUV field description

Description

TOV

: Time out duration for channel x (x:0...m-1).

Reserved.

Note:

Read as zero, should be written as zero

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Bit

[1:3]

Table 112. TIM[i]_CH[x]_TDUV field description (continued)

Description

TCS : Timeout Clock selection

000 = CMU_CLK0 selected

001 = CMU_CLK1 selected

010 = CMU_CLK2 selected

011 = CMU_CLK3 selected

100 = CMU_CLK4 selected

101 = CMU_CLK5 selected

110 = CMU_CLK6 selected

111 = CMU_CLK7 selected

Reserved.

Note:

Read as zero, should be written as zero

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TO_CNT Bit

Mode

Initial value

0x000000

0x00

Bit

[24:31]

[0:23]

Table 113. TIM[i]_CH[x]_TDUC field description

Description

TO_CNT : Current timeout value for channel x (x:0...m-1).

Reserved.

Note: Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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Bit

[16:31]

[0:15]

Table 114. TIM[i]_CH[x]_ECNT field description

Description

ECNT : Edge counter

Note:

If TIM channel is disabled the content of ECNT gets frozen. A read will auto clear the bits

[15:1]. Further read accesses to ECNT will show on Bit 0 the actual input signal value of the channel.

Reserved.

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[29:31]

[0:28]

0x00000000

Table 115. TIM[i]_CH[x]_ECTRL field description

Description

EXT_CAP_SRC

: Defines selected source for triggering the EXT_CAPTURE functionality.

000 = NEW_VAL_IRQ of following channel selected

001 = AUX_IN selected

010 = CNTOFL_IRQ of following channel selected

011 and CICTRL = 1: use signal TIM_IN(x) as input for channel x

011 and CICTRL = 0: use signal TIM_IN(x-1) as input for channel x (or TIM_IN(m-1) if x is 0)

100 = ECNTOFL_IRQ of following channel selected

101 =TODET_IRQ of following channel selected

110 = GLITCHDET_IRQ of following channel selected

111 = GPROFL_IRQ of following channel selected

Reserved.

Note: Read as zero, should be written as zero

000

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11 Timer Output Module (TOM)

RM0361

11.1 Overview

The Timer Output Module (TOM) offers up to 16 independent channels (index x) to generate simple PWM signals at each output pin TOM[i]_CH[x]_OUT .

Additionally, at TOM output TOM[i]_CH15_OUT a pulse count modulated signal can be generated.

The architecture of the TOM submodule is depicted in Figure 32 .

Indices and their range as used inside this chapter are: y=0,1 z=0...7

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RM0361

Figure 32. TOM block diagram

Timer Output Module (TOM)

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Timer Output Module (TOM) RM0361

The two submodules TGC0 and TGC1 are global channel control units that control the enabling/disabling of the channels and their outputs as well as the update of their period and duty cycle register.

The module TOM receives two (three) timestamps values TBU_TS0 , TBU_TS1 (and

TBU_TS2 ) in order to realize synchronized output behavior on behalf of a common time base.

The 5 dedicated clock line inputs CMU_FXCLK are providing divided clocks that can be selected to clock the output pins.

11.2 TOM global channel control (TGC0, TGC1)

11.2.1 Overview

There exist two global channel control units (TGC0 and TGC1) to drive a number of individual TOM channels synchronously by external or internal events.

Each TGC[y] can drive up to eight TOM channels where TGC0 controls TOM channels 0 to

7 and TGC1 controls TOM channels 8 to 15.

The TOM submodule supports four different kinds of signaling mechanisms:

 Global enable/disable mechanism for each TOM channel with control register

TOM[i]_TGC[y]_ENDIS_CTRL and status register TOM[i]_TGC[y]_ENDIS_STAT

 Global output enable mechanism for each TOM channel with control register

TOM[i]_TGC[y]_OUTEN_CTRL and status register TOM[i]_TGC[y]_OUTEN_STAT

 Global force update mechanism for each TOM channel with control register

TOM[i]_TGC[y]_FUPD_CTRL

 Update enable of the register CM0 , CM1 and CLK_SRC for each TOM channel with the control bit field UPEN_CTRL[z] of TOM[i]_TGC[y]_GLB_CTRL

Note:

Each of the first three individual mechanisms (enable/disable of the channel, output enable and force update) can be driven by three different trigger sources.

The three trigger sources are:

 The host CPU (bit HOST_TRIG of register TOM[i]_TGC[y]_GLB_CTRL )

 The TBU time stamp (signal TBU_TS0, TBU_TS1, TBU_TS2 if available)

 The internal trigger signal TRIG (bunch of trigger signals TRIG_[x] )

The trigger signal is only active for one configured CMU clock period.

As a consequence, if the configured CMU clock period of the channel generating the trigger

TRIG_[X] is smaller than the CMU clock period of triggered channel, the triggered channel may not recognize the trigger signal TRIG_[X].



Thus, it is recommended to configure all channels connected via the triggerTRIG_[x] to the same CMU clock period.

The first way is to trigger the control mechanism by a direct register write access via host

CPU (bit HOST_TRIG of register TOM[i]_TGC[y]_GLB_CTRL ).

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The second way is provided by a compare match trigger on behalf of a specified time base coming from the module TBU (selected by bits TBU_SEL ) and the time stamp compare value defined in the bit field ACT_TB of register TOM[i]_TGC[y]_ACT_TB .

Note, a signed compare of ACT_TB and selected TBU_TS [ x ] with x=0,1,2 is performed.

The third possibility is the input TRIG (set of trigger signals TRIG_[x] ) coming from the TOM channels 0 to 7/8 to 15.

The corresponding trigger signal TRIG_[x] coming from channel [x] can be masked by the register TOM[i]_TGC[y]_INT_TRIG .

To enable or disable each individual TOM channel, the registers

TOM[i]_TGC[y]_ENDIS_CTRL and/or TOM[i]_TGC[y]_ENDIS_STAT have to be used.

The register TOM[i]_TGC[y]_ENDIS_STAT controls directly the signal ENDIS . A write access to this register is possible.

The register TOM[i]_TGC[y]_ENDIS_CTRL is a shadow register that overwrites the value of register TOM[i]_TGC[y]_ENDIS_STAT if one of the three trigger conditions matches.

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Timer Output Module (TOM)

Figure 33. TOM global channel control mechanism

RM0361

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The output of the individual TOM channels can be controlled using the register

TOM[i]_TGC[y]_OUTEN_CTRL and TOM[i]_TGC[y]_OUTEN_STAT .

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DocID025070 Rev 1

RM0361 Timer Output Module (TOM)

The register TOM[i]_TGC[y]_OUTEN_STAT controls directly the signal OUTEN . A write access to this register is possible.

The register TOM[i]_TGC[y]_OUTEN_CTRL is a shadow register that overwrites the value of register TOM[i]_TGC[y]_OUTEN_STAT if one of the three trigger conditions matches.

If a TOM channel is disabled by the register TOM[i]_TGC[y]_OUTEN_STAT , the actual value of the channel output at TOM_CH[x]_OUT is defined by the signal level bit ( SL ) defined in the channel control register TOM[i]_CH[x]_CTRL .

If the output is enabled, the output at TOM_CH[x]_OUT depends on value of FlipFlop

SOUR .

The register TOM[i]_TGC[y]_FUPD_CTRL defines which of the TOM channels receive a

FORCE_UPDATE event if the trigger signal CTRL_TRIG is raised.

The register bits UPEN_CTRL[z] defines for which TOM channel the update of the working register CM0 , CM1 and CLK_SRC by the corresponding shadow register SR0 , SR1 and

CLK_SRC_SR is enabled. If update is enabled, the register CM0 , CM1 and CLK_SRC will be updated on reset of counter register CN0 (see

Figure 34

and

Figure 35 ).

11.3 TOM channel (TOM_CH[x])

Each individual TOM channel comprises a Counter Compare Unit 0 (CCU0), a Counter

Compare Unit 1 (CCU1) and the Signal Output Generation Unit (SOU). The architecture is depicted in

Figure 34 for channels 0 to 7 and in

Figure 35

for channels 8 to 15.

All the channels have a common architecture with the following particularities:

 Channels 0 to 7 are connected to the Sensor Pattern Evaluation (SPE), see

Chapter 17: Sensor Pattern Evaluation (SPE)

 Channel 15 has the Pulse Count Modulation (PCM) functionality

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Timer Output Module (TOM)

Figure 34. TOM channel 0...7 architecture

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Figure 35. TOM channel 8...14 architecture

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Timer Output Module (TOM)

Figure 36. TOM channel 15 architecture for PCM generation

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The CCU0 contains a counter CN0 which is clocked with one of the selected input frequencies ( CMU_FXCLK ) provided from outside of the submodule.

DocID025070 Rev 1

RM0361 Timer Output Module (TOM)

Depending on configuration bits RST_CCU0 of register TOM[i]_CH[x]_CTRL the counter can be reset either when the counter value is equal to the compare value CM0 or when signaled by the TOM[i] trigger signal TRIG_[x-1] of the preceding channel [x-1] (which can also be the last channel of preceding instance TOM[i-1]).

When the counter register CN0 is greater than or equal to the register CM0, the subunit

CCU0 triggers the SOU subunit and the succeeding TOM submodule channel (signal

TRIG_CCU0 ).

In the subunit CCU1 the counter register CN0 is compared with the value of register CM1 . If

CN0 is greater than or equal to CM1 the subunit CCU1 triggers the SOU subunit (signal

TRIG_CCU1 ).

If counter register CN0 of channel x is reset by its own CCU0 unit (i.e. the compare match of

CN0 >= CM0 configured by RST_CCU0 = 0), following statements are valid:

 The configuration of CM1 = 0 represents 0 % duty cycle at the output

 The configuration of CM1 >= CM0 represents 100 % duty cycle

 If both registers are configured to 0 ( CM0 = CM1 = 0), the output is 0 % duty cycle

 If CM0 = 0, 0 % duty cycle is generated independent of CM1

If the counter register CN0 of channel x is reset by the trigger signal coming from another channel or the assigned TIM module (configured by RST_CCU0 = 1), following statements are valid:



CM0 defines the edge to SL value, CM1 defines the edge to !SL value

 If CM0 = CM1 , the output is 100 % SL ( CM0 has higher priority)

 If CM0 = 0, the output stays at its last value ( CN0 stops counting)

The hardware ensures that for both 0 % and 100 % duty cycle no glitch occurs at the output of the TOM channel.

The SOU subunit is responsible for output signal generation. On a trigger TRIG_CCU0 from subunit CCU0 or TRIG_CCU1 from subunit CCU1 a SR-FlipFlop of subunit SOU is either set or reset. If it is set or reset depends on the configuration bit SL of the control register

TOM[i]_CH[x]_CTRL . The initial signal output level for the channel is the reverse value of the bit SL .

Figure 39

clarifies the PWM output behavior with respect to the SL bit definition.

The output level on the TOM channel output pin TOM[i]_CH[x]_OUT is captured in bit OL of register TOM[i]_CH[x]_STAT .

11.3.1 Duty cycle, period and selected counter clock frequency update mechanisms

The two action registers CM0 and CM1 can be reloaded with the content of the shadow registers SR0 and SR1 . The register CLK_SRC that determines the clock frequency of the counter register CN0 can be reloaded with its shadow register CLK_SRC_SR (bit field in register TOM[i]_CH[x]_CTRL )

The update of the register CM0 , CM1 and CLK_SRC with the content of its shadow register is done when the reset of the counter register CN0 is requested (via signal RESET ). This reset of CN0 is done if the comparison of CN0 greater than or equal to CM0 is true or when the reset is triggered by another TOM channel [x-1] via the signal TRIG_[x-1] .

For TOM0 channel 0 TRIG_[-1] is '0' hard coded.

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With the update of the register CLK_SRC at the end of a period a new counter CN0 clock frequency can easily be adjusted.

An update of duty cycle, period and counter CN0 clock frequency becoming effective synchronously with start of a new period can easily be reached by performing following steps:

Disable the update of the action register with the content of the corresponding shadow register by setting the channel specific configuration bit UPEN_CTRL[z] of register

TOM[i]_TGC[y]_GLB_CTRL to '0'.

2. Write new desired values to SR0 , SR1 , CLK_SRC_SR

3. Enable update of the action register by setting the channel specific configuration bit

UPEN_CTRL[z] of register TOM[i]_TGC[y]_GLB_CTRL to '1'.

11.3.1.1 Synchronous update of duty cycle only

A synchronous update of only the duty cycle can be done by simply writing the desired new value to register SR1 without preceding disable of the update mechanism (as described in the chapter above). The new duty cycle is then applied in the period following the period where the update of register SR1 was done.

Figure 37. Synchronous update of duty cycle

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11.3.1.1.1 Asynchronous update of duty cycle only

To update the duty cycle independently from the start of a new period (asynchronous update), the desired new value can be written directly to the CM1 register. In this case it is recommended to additionally either disable the synchronous update mechanism as a whole

(i.e. clearing bits UPEN_CTRL[z] of corresponding channel [x] in register

TOM[i]_TGX[y]_GLB_CTRL ) or updating SR1 with the same value as CM1 before writing to CM1 .

Depending on the point of time of the update of CM1 in relation to the actual value of CN0 and CM1 , the new duty cycle is applied in the current period or the following period (see

Figure 38

). In any case the creation of glitches is avoided. The new duty cycle may jitter from update to update by a maximum of one period (given by CM0 ). However, the period remains unchanged.

Figure 38. Asynchronous update of duty cycle

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11.3.2 TOM continuous mode

In continuous mode the TOM channel starts incrementing the counter register CN0 once it is enabled by setting the corresponding bits in register TOM[i]_TGC[y]_ENDIS_STAT (refer to

Section 11.2.2: TGC subunit

for details of enabling a TOM channel).

The signal level of the generated output signal can be configured with the configuration bit

SL of the channel configuration register TOM[i]_CH[x]_CTRL .

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If the counter CN0 is reset from CM0 back to zero, the first edge of a period is generated at

TOM[i]_CH[x]_OUT .

The second edge of the period is generated if CN0 has reached CM1 .

Every time the counter CN0 has reached the value of CM0 it is reset back to zero and proceeds with incrementing.

Figure 39. PWM output with respect to configuration bit SL in continuous mode

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11.3.3 TOM one shot mode

In One-shot mode, the TOM channel generates one pulse with a signal level specified by the configuration bit SL in the channel [x] configuration register TOM[i]_CH[x]_CTRL .

First the channel has to be enabled by setting the corresponding

TOM[i]_TGC[y]_ENDIS_STAT value and the one-shot mode has to be enabled by setting bit OSM in register TOM[i]_CH[x]_CTRL .

In one-shot mode the counter CN0 will not be incremented once the channel is enabled.

A write access to the register CN0 triggers the start of pulse generation (i.e. the increment of the counter register CN0 ).

If SPE mode of TOM[i] channel 2 is enabled (set bit SPEM of register TOM[i]_CH2_CTRL ), also the trigger signal SPE[i]_NIPD can trigger the reset of register CN0 to zero and a start of the pulse generation.

The new value of CN0 determines the start delay of the first edge. The delay time of the first edge is given by ( CM0-CN0 ) multiplied with period defined by current value of CLK_SRC .

If the counter CN0 is reset from CM0 back to zero, the first edge at TOM[i]_CH[x]_OUT is generated.

To avoid an update of CMx register with content of SRx register at this point in time, the automatic update should be disabled by setting UPEN_CTRL[x] = 00 (in register

TOM[i]_CH[x]_CTRL )

The second edge is generated if CN0 is greater than or equal to CM1 (i.e. CN0 was incremented until it has reached CM1 or CN0 is greater than CM1 after an update of CM1 ).

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If the counter CN0 has reached the value of CM0 a second time, the counter stops.

Figure 40. PWM output with respect to configuration bit SL in one-shot mode: trigger by writing to CN0

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Further output of single periods can be started by a write access to register CN0.

If CN0 is already incrementing (i.e. started by writing to CN0 a value CN0start < CM0), the effect of a second write to CN0 depends on the phase of CN0:

 phase 1: CN0 never reached the CM0 value

 phase 2: CN0 reached CM0 a first time but is lower than CM1

 phase 3: CN0 reached CM0 a first time and is greater than or equal to CM1

In phase 1: writing the CN0 counter with a {CN0new < CM1} while {CN0old < CM1} leads to a lengthening of the pulse. The CN0 counter stops when it reaches CM0.

In phase 2: writing to incrementing counter CN0 a value CN0new < CM1 while CN0old is below CM1 leads to a lengthening of the pulse. The counter CN0 stops if is reaches CM0.

In phase 3: writing to incrementing counter CN0 a value CN0new while CN0old is already greater than or equal to CM1 leads to an immediate restart of a single pulse generation inclusive the initial delay defined by CM0 - CN0new.

At the output TOM[i]_CH15_OUT a pulse count modulated signal can be generated instead of the simple PWM output signal.

Figure 36

outlines the circuit for pulse count modulation.

The PCM mode is enabled by setting bit BITREV to 1.

With the configuration bit BITREV = 1 a bit-reversing of the counter output CN0 is configured. In this case the bits LSB and MSB are swapped, the bits LSB+1 and MSB-1 are swapped, the bits LSB+2 and MSB-2 are swapped and so on.

The effect of bit-reversing of the CN0

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Figure 41. Bit reversing of counter CN0 output

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RM0361

Note:

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In the PCM mode the counter register CN0 is incremented by every clock tick depending on the configured CMU clock ( CMU_FXCLK ).

The output of counter register CN0 is first bit-reversed and than compared with the configured register value CM1 .

If the bit-reversed value of register CN0 is greater than CM1 , the SR-FlipFlop of submodule

SOU is set (depending on configuration register SL ) otherwise the SR-FlipFlop is reset. This generates at the output TOM[i]_CH15_OUT a pulse count modulated signal.

In PCM mode the CM0 register always - in which the period is defined - normally has to be set to its maximum value 0xFFFF.

In this mode the interrupt CCU1TC (see register ATOM[i]_CH[x]_IRQ_NOTIFY) is set every time if bit reverse value of CN0 is greater than or equal to CM1 which may be multiple times during one period. Therefore, from an application point of view it is not useful to enable this interrupt.

11.4 TOM BLDC support

The TOM submodule offers in combination with the SPE submodule a BLDC support. To drive a BLDC engine TOM channels 0 to 7 can be used.

The BLDC support can be configured by setting the SPEM bit inside the

TOM[i]_CH[z]_CTRL register. When this bit is set the TOM channel output is controlled through the SPE_OUT(z) signal coming from the SPE submodule (see

Figure 34 ). Please

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Chapter 17: Sensor Pattern Evaluation (SPE)

for a detailed description of the SPE submodule.

The TOM[i]_CH2 can be used together with the SPE module to trigger a delayed update of the SPE_OUT_CTRL register after new input pattern detected by SPE (signaled by

SPE[i]_NIPD ). This feature is configured on TOM[i]_CH2 by setting SPEM = 1 and

OSM = 1. For details please refer to chapter of SPE submodule description.

11.5 TOM gated counter mode

Each TOM-SPE module combination provides also the feature of a gated counter mode.

This is reached by using the FSOI input of a TIM module to gate the clock of a CCU0 submodule.

To configure this mode, registers of module SPE should be set as follows:

 The SPE should be enabled (bit SPE_EN = 1)

 All three TIM inputs should be disabled ( SIE0 = SIE1 = SIE2 = 0)



SPE[i]_OUT_CTRL should be set to 00005555h (set SPE_OUT() to '0')

 Mode FSOM should be enabled ( FSOM = 1)

 Set in bit field FSOL bit c if channel c of module TOM is chosen for gated counter mode

Additionally in module TOM

 The SPE mode should be disabled ( SPEM = 0)

 The gated counter mode should be enabled ( GCM = 1)

As a result of this configuration, the counter CN0 in submodule CCU0 of TOM channel c counts as long as input FSOI is '0'.

11.6 TOM interrupt signals

The following table describes TOM interrupt signals.

Signal

TOM_CCU0TCx_IRQ

TOM_CCU1TCx_IRQ

Table 116. TOM interrupt signals

Description

CCU0 trigger condition interrupt for channel x

CCU1 trigger condition interrupt for channel x

11.7 TOM configuration registers overview

Table 117. TOM configuration registers overview

Register name

TOM[i]_TGC0_GLB_CTRL

TOM[i]_TGC0_ENDIS_CTRL

TOM[i]_TGC0_ENDIS_STAT

TOM[i]_TGC0_ACT_TB

Description

TGC0 global control reg

TGC0 enable/disable control reg

TGC0 enable/disable status reg

TGC0 action time base register

Details in section

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Table 117. TOM configuration registers overview (continued)

Register name Description Details in section

TOM[i]_TGC0_OUTEN_CTRL TGC0 output enable control reg

TOM[i]_TGC0_OUTEN_STAT TGC0 output enable status reg

TOM[i]_TGC0_FUPD_CTRL

TOM[i]_TGC0_INT_TRIG

TGC0 force update control reg

TGC0 internal trigger control

TOM[i]_TGC1_GLB_CTRL

TOM[i]_TGC1_ENDIS_CTRL

TOM[i]_TGC1_ENDIS_STAT

TOM[i]_TGC1_ACT_TB

TGC1 global control register

TGC1 enable/disable control reg

TGC1 enable/disable status reg

TGC1 action time base register

TOM[i]_TGC1_OUTEN_CTRL TGC1 output enable control reg

TOM[i]_TGC1_OUTEN_STAT TGC1 output enable status reg

TOM[i]_TGC1_FUPD_CTRL

TOM[i]_TGC1_INT_TRIG

TGC1 force update control reg

TGC1 internal trigger control

TOM[i]_CH[x]_CTRL

TOM[i]_CH15_CTRL

TOM[i]_CH[x]_CN0

TOM[i]_CH[x]_CM0

TOM Channel x control register (x = 0…14)

TOM Channel 15 control reg

TOM Channel x CCU0 counter register (x = 0…15)

TOM[i]_CH[x]_SR0

TOM[i]_CH[x]_CM1

TOM[i]_CH[x]_SR1

TOM Channel x CCU0 compare register (x = 0…15)

TOM Channel x CCU0 compare shadow register (x =

0…15)

TOM Channel x CCU1 compare register (x = 0…15)

TOM Channel x CCU1 compare shadow register (x =

0…15)

TOM[i]_CH[x]_STAT

TOM[i]_CH[x]_IRQ_NOTIFY

TOM[i]_CH[x]_IRQ_EN

TOM channel status (x = 0…15)

Section 11.8.24

TOM channel x interrupt notification register (x = 0…15)

Section 11.8.25

TOM channel x interrupt enable register (x = 0…15)

Section 11.8.26

TOM[i]_CH[x]_IRQ_FORCINT TOM channel x software interrupt generation (x = 0…15)

Section 11.8.27

TOM[i]_CH[x]_IRQ_MODE IRQ mode configuration register (x = 0...15)

Section 11.8.28

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11.8 TOM configuration registers description

Timer Output Module (TOM)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:30]

A w

0 0 0 0 0 0 0 0

A w

Table 118. TOM[i]_TGC0_GLB_CTRL field description

Description

HOST_TRIG : trigger request signal (see TGC0, TGC1) to update the register ENDIS_STAT and OUTEN_STAT

0 = no trigger request

1 = set trigger request

Note: this flag is reset automatically after triggering the update

Reserved

Note:

Read as zero, should be written as zero.

RST_CH0

: Software reset of channel 0

0 = No action

1 = Reset channel

Note: This bit is cleared automatically after write by CPU. The channel registers are set to their reset values and channel operation is stopped immediately. The S-R FlipFlop SOUR is set to '1'.

RST_CH1

: Software reset of channel 1

See bit 23

RST_CH2

: Software reset of channel 2

See bit 23

RST_CH3

: Software reset of channel 3

See bit 23

RST_CH4

: Software reset of channel 4

See bit 23

RST_CH5

: Software reset of channel 5

See bit 23

RST_CH6

: Software reset of channel 6

See bit 23

RST_CH7

: Software reset of channel 7

See bit 23

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[8:9]

[6:7]

[4:5]

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[0:1]

Table 118. TOM[i]_TGC0_GLB_CTRL field description (continued)

Description

UPEN_CTRL0 : TOM channel 0 enable update of register CM0, CM1 and CLK_SRC from

SR0, SR1 and CLK_SRC_SR.

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = update disabled: is read as 00 (see below)

10 = update enabled: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = channel disabled

11 = channel enabled

UPEN_CTRL2 : TOM channel 2 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL3 : TOM channel 3 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL4

: TOM channel 4 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL5

: TOM channel 5 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL6

: TOM channel 6 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL7

: TOM channel 7 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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[26:27]

[24:25]

[22:23]

Timer Output Module (TOM)

Table 119. TOM[i]_TGC0_ENDIS_CTRL field description

Description

ENDIS_CTRL0 : TOM channel 0 enable/disable update value.

If a TOM channel is disabled, the counter CN0 is stopped and the FlipFlop SOUR is set to the inverse value of control bit SL. On an enable event, the counter CN0 starts counting from its current value.

Write of following double bit values is possible:

00 = don’t care, bits 1:0 of register ENDIS_STAT will not be changed on an update trigger

01 = disable channel on an update trigger

10 = enable channel on an update trigger

11 = don’t change bits 1:0 of this register

Note:

If the channel is disabled (ENDIS[0]=0) or the output is disabled (OUTEN[0]=0), the TOM channel 0 output TOM_OUT[0] is the inverted value of bit SL.

ENDIS_CTRL1

: TOM channel 1 enable/disable update value.

See bits [30:31]

ENDIS_CTRL2

: TOM channel 2 enable/disable update value.

See bits [30:31]

ENDIS_CTRL3

: TOM channel 3 enable/disable update value.

See bits [30:31]

ENDIS_CTRL4

: TOM channel 4 enable/disable update value.

See bits [30:31]

ENDIS_CTRL5

: TOM channel 5 enable/disable update value.

See bits [30:31]

ENDIS_CTRL6

: TOM channel 6 enable/disable update value.

See bits [30:31]

ENDIS_CTRL7

: TOM channel 7 enable/disable update value.

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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Table 120. TOM[i]_TGC0_ENDIS_STAT field description

Description

ENDIS_STAT0 : TOM channel 0 enable/disable

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = channel disabled: is read as 00 (see below)

10 = channel enabled: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = channel disable

11 = channel enable

ENDIS_STAT1 : TOM channel 1 enable/disable

See bits [30:31]

ENDIS_STAT2 : TOM channel 2 enable/disable

See bits [30:31]

ENDIS_STAT3 : TOM channel 3 enable/disable

See bits [30:31]

ENDIS_STAT4 : TOM channel 4 enable/disable

See bits [30:31]

ENDIS_STAT5

: TOM channel 5 enable/disable

See bits [30:31]

ENDIS_STAT6

: TOM channel 6 enable/disable

See bits [30:31]

ENDIS_STAT7

: TOM channel 7 enable/disable

See bits [30:31]

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

00000

A w

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[5:6]

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Timer Output Module (TOM)

Table 121. TOM[i]_TGC0_ACT_TB field description

Description

ACT_TB : specifies the signed compare value with selected signal TBU_TS[x], x=0...2. If selected TBU_TS[x] value is in the interval [ACT_TB-007FFFFFh,ACT_TB] the event is in the past and the trigger is generated immediately. Otherwise the event is in the future and the trigger is generated if selected TBU_TS[x] is equal to ACT_TB.

TB_TRIG : Set trigger request

0 = no trigger request

1 = set trigger request

Note:

This flag is reset automatically if the selected time base unit (TBU_TS0 or TBU_TS1 or

TBU_TS2 if present) has reached the value ACT_TB and the update of the register were triggered.

TBU_SEL : Selection of time base used for comparison

00 = TBU_TS0 selected

01 = TBU_TS1 selected

10 = TBU_TS2 selected

11 = same as 00

Note: The bit combination “10” is only applicable if the TBU of the device contains three time base channels. Otherwise, this bit combination is also reserved. Please refer to GTM

Architecture block diagram on page 3 to determine the number of channels for TBU of this device.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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Bit

[30:31]

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Table 122. TOM[i]_TGC0_OUTEN_CTRL field description

Description

OUTEN_CTRL0 : Output TOM_OUT(0) enable/disable update value

Write of following double bit values is possible:

00 = don’t care, bits 1:0 of register OUTEN_STAT will not be changed on an update trigger

01 = disable channel output on an update trigger

10 = enable channel output on an update trigger

11 = don’t change bits 1:0 of this register

Note: If the channel is disabled (ENDIS[0]=0) or the output is disabled (OUTEN[0]=0), the TOM channel 0 output TOM_OUT[0] is the inverted value of bit SL.

OUTEN_CTRL1 : Output TOM_OUT(1)enable/disable update value

See bits [30:31]

OUTEN_CTRL2 : Output TOM_OUT(2)enable/disable update value

See bits [30:31]

OUTEN_CTRL3 : Output TOM_OUT(3)enable/disable update value

See bits [30:31]

OUTEN_CTRL4

: Output TOM_OUT(4)enable/disable update value

See bits [30:31]

OUTEN_CTRL5

: Output TOM_OUT(5)enable/disable update value

See bits [30:31]

OUTEN_CTRL6

: Output TOM_OUT(6)enable/disable update value

See bits [30:31]

OUTEN_CTRL7

: Output TOM_OUT(7)enable/disable update value

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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[18:19]

[16:17]

[0:15]

[28:29]

[26:27]

[24:25]

[22:23]

Timer Output Module (TOM)

Table 123. TOM[i]_TGC0_OUTEN_STAT field description

Description

OUTEN_STAT0 : Control/status of output TOM_OUT(0)

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = channel disabled: is read as 00 (see below)

10 = channel enabled: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = channel disable

11 = channel enable

OUTEN_STAT1

: Control/status of output TOM_OUT(1)

See bits [30:31]

OUTEN_STAT2

: Control/status of output TOM_OUT(2)

See bits [30:31]

OUTEN_STAT3 : Control/status of output TOM_OUT(3)

See bits 1:0

OUTEN_STAT4 : Control/status of output TOM_OUT(4)

See bits [30:31]

OUTEN_STAT5 : Control/status of output TOM_OUT(5)

See bits [30:31]

OUTEN_STAT6 : Control/status of output TOM_OUT(6)

See bits [30:31]

OUTEN_STAT7 : Control/status of output TOM_OUT(7)

See bits [30:31]

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Bit

[30:31]

[14:15]

[12:13]

[10:11]

[8:9]

[6:7]

Table 124. TOM[i]_TGC0_FUPD_CTRL field description

Description

FUPD_CTRL0 : Force update of TOM channel 0 operation registers

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = force update disabled: is read as 00 (see below)

10 = force update enabled: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = force update disabled

11 = force channel enabled

FUPD_CTRL1

: Force update of TOM channel 1 operation registers

See bits [30:31]

FUPD_CTRL2

: Force update of TOM channel 2 operation registers

See bits [30:31]

FUPD_CTRL3 : Force update of TOM channel 3 operation registers

See bits [30:31]

FUPD_CTRL4 : Force update of TOM channel 4 operation registers

See bits [30:31]

FUPD_CTRL5 : Force update of TOM channel 5 operation registers

See bits [30:31]

FUPD_CTRL6 : Force update of TOM channel 6 operation registers

See bits [30:31]

FUPD_CTRL7 : Force update of TOM channel 7 operation registers

See bits [30:31]

RSTCN0_CH0 : Reset CN0 of channel 0 on force update event

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = CN0 is not reset on forced update: is read as 00 (see below)

10 = CN0 is reset on forced update: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = CN0 is not reset on forced update

11 = CN0 is reset on forced update

RSTCN0_CH1 : Reset CN0 of channel 1 on force update event

See bits [14:15]

RSTCN0_CH2 : Reset CN0 of channel 2 on force update event

See bits [14:15]

RSTCN0_CH3 : Reset CN0 of channel 3 on force update event

See bits [14:15]

RSTCN0_CH4 : Reset CN0 of channel 4 on force update event

See bits [14:15]

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RM0361 Timer Output Module (TOM)

Bit

[4:5]

[2:3]

[0:1]

Table 124. TOM[i]_TGC0_FUPD_CTRL field description (continued)

Description

RSTCN0_CH5 : Reset CN0 of channel 5 on force update event

See bits [14:15]

RSTCN0_CH6 : Reset CN0 of channel 6 on force update event

See bits [14:15]

RSTCN0_CH7 : Reset CN0 of channel 7 on force update event

See bits [14:15]

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[28:29]

[26:27]

[24:25]

[22:23]

[20:21]

[18:19]

0x0000

Table 125. TOM[i]_TGC0_INT_TRIG field description

Description

INT_TRIG0 : Select input signal TRIG_0 as a trigger source

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be changed

01 = internal trigger from channel 0 (TRIG_0) not used: is read as 00 (see below)

10 = internal trigger from channel 0 (TRIG_0) used: is read as 11 (see below)

11 =Read of following double values means:

00 = internal trigger from channel 0 (TRIG_0) not used

11 = internal trigger from channel 0 (TRIG_0) used don’t care, bits 1:0 will not be changed

INT_TRIG1 : Select input signal TRIG_1 as a trigger source

See bits [30:31]

INT_TRIG2 : Select input signal TRIG_2 as a trigger source

See bits [30:31]

INT_TRIG3 : Select input signal TRIG_3 as a trigger source

See bits [30:31]

INT_TRIG4 : Select input signal TRIG_4 as a trigger source

See bits [30:31]

INT_TRIG5 : Select input signal TRIG_5 as a trigger source

See bits [30:31]

INT_TRIG6 : Select input signal TRIG_6 as a trigger source

See bits [30:31]

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[16:17]

[0:15]

Table 125. TOM[i]_TGC0_INT_TRIG field description (continued)

Description

INT_TRIG7 : Select input signal TRIG_7 as a trigger source

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

RM0361

Controls channel 8 to 15

For description see

Section 11.8.1: Register TOM[i]_TGC0_GLB_CTRL

Controls channel 8 to 15

For description see

Section 11.8.2: Register TOM[i]_TGC0_ENDIS_CTRL

Controls channel 8 to 15

For description see

Section 11.8.3: Register TOM[i]_TGC0_ENDIS_STAT

Controls channel 8 to 15

For description see

Section 11.8.4: Register TOM[i]_TGC0_ACT_TB

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Controls channel 8 to 15

For description see

Section 11.8.5: Register TOM[i]_TGC0_OUTEN_CTRL

Controls channel 8 to 15

For description see

Section 11.8.6: Register TOM[i]_TGC0_OUTEN_STAT

Controls channel 8 to 15

For description see

Section 11.8.7: Register TOM[i]_TGC0_FUPD_CTRL

Controls channel 8 to 15

For description see

Section 11.8.8: Register TOM[i]_TGC0_INT_TRIG

DocID025070 Rev 1

RM0361 Timer Output Module (TOM)

Address offset: see Appendix B Initial value: 0x0000_0X00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[21:31]

[17:19]

[12:16]

[8:10]

0x0 0 0 0 0 0 0 000 0 00000 000 X 0x000

Table 126. TOM[i]_CH[x]_CTRL field description

Description

Reserved

Note: Read as zero, should be written as zero.

: Signal level for duty cycle

0 = Low signal level

1 = High signal level

If the output is disabled, the output TOM_OUT[x] is set to inverse value of SL.

Note: : Reset value depends on the hardware configuration chosen by silicon vendor.

CLK_SRC_SR : Clock source select for channel

The register CLK_SRC is updated with the value of CLK_SRC_SR together with the update of register CM0 and CM1.

The input of the FX clock divider depends on the value of FXCLK_SEL (see CMU).

000 = CMU_FXCLK(0) selected: clock selected by FXCLK_SEL

001 = CMU_FXCLK(1) selected: clock selected by FXCLK_SEL/ 2^4

010 = CMU_FXCLK(2) selected: clock selected by FXCLK_SEL/ 2^8

011 = CMU_FXCLK(3) selected: clock selected by FXCLK_SEL/ 2^12

100 = CMU_FXCLK(4) selected: clock selected by FXCLK_SEL/ 2^16

101 = no CMU_FXCLK selected, clock of channel stopped

110 = no CMU_FXCLK selected, clock of channel stopped

111 = no CMU_FXCLK selected, clock of channel stopped

Note:

If clock of channel is stopped (i.e. CLK_SRC = 101/110/111), the channel can only be restarted by resetting CLK_SRC_SR to a value of 000 to 100 and forcing an update via the force update mechanism.

Reserved

Note: Read as zero, should be written as zero.

RST_CCU0 : Reset source of CCU0

0 = Reset counter register CN0 to 0 on matching comparison CM0

1 = Reset counter register CN0 to 0 on trigger TRIG_[x-1]

Note:

On TOM channel 2 SPEM=1 has special meaning.

If SPEM = 1, the signal SPE_NIPD triggers the reset of CN0 independent of RST_CN0.

Reserved

Note:

Read as zero, should be written as zero.

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RM0361

Table 126. TOM[i]_CH[x]_CTRL field description (continued)

Description

TRIGOUT : Trigger output selection (output signal TRIG_[x]) of module TOM_CH[x]

0 = TRIG_[x] is TRIG_[x-1]

1 = TRIG_[x] is TRIG_CCU0

Reserved

Note: Read as zero, should be written as zero.

OSM

: One-shot mode. In this mode the counter CN0 counts for only one period. The length of period is defined by CM0. A write access to the register CN0 triggers the start of counting.

0 = One-shot mode disabled

1 = One-shot mode enabled

Reserved

Note:

Read as zero, should be written as zero.

SPEM

: SPE mode enable for channel.

0 = SPE mode disabled

1 = SPE mode enabled

Note: The SPE mode is only implemented for TOM instances connected to a SPE module and only for channels 0 to 7.

Note: On TOM channel 2 SPEM=1 has special meaning.

If SPEM = 1, the signal SPE_NIPD triggers the reset of CN0.

If SPEM = 1 and OSM=1,the signal SPE_NIPD triggers the start of single pulse generation

GCM

: Gated Counter Mode enable

0 = Gated Counter mode disabled

1 = Gated Counter mode enabled

Note:

The Gated Counter mode is only available for TOM instances connected to a SPE module and only for channels 0 to 7.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0X00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0

0 0 0 0

000

00000

000

0x000

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Bit

[21:31]

[17:19]

[12:16]

[8:10]

[0:3]

Timer Output Module (TOM)

Table 127. TOM[i]_CH15_CTRL field description

Description

Reserved

Note:

Read as zero, should be written as zero.

SL : Signal level for duty cycle

0 = Low signal level

1 = High signal level

If the output is disabled, the output ATOM_OUT[x] is set to inverse value of SL.

Note: Reset value depends on the hardware configuration chosen by silicon vendor.

CLK_SRC_SR

: Clock source select for channel

The register CLK_SRC is updated with the value of CLK_SRC_SR together with the update of register CM0 and CM1.

The input of the FX clock divider depends on the value of FXCLK_SEL (see CMU).

000 = CMU_FXCLK(0) selected: clock selected by FXCLK_SEL

001 = CMU_FXCLK(1) selected: clock selected by FXCLK_SEL/ 2^4

010 = CMU_FXCLK(2) selected: clock selected by FXCLK_SEL/ 2^8

011 = CMU_FXCLK(3) selected: clock selected by FXCLK_SEL/ 2^12

100 = CMU_FXCLK(4) selected: clock selected by FXCLK_SEL/ 2^16

101 = no CMU_FXCLK selected, clock of channel stopped

110 = no CMU_FXCLK selected, clock of channel stopped

111 = no CMU_FXCLK selected, clock of channel stopped

Note: If clock of channel is stopped (i.e. CLK_SRC = 101/110/111), the channel can only be restarted by resetting CLK_SRC_SR to a value of 000 to 100 and forcing an update via the force update mechanism.

Reserved

Note:

Read as zero, should be written as zero.

RST_CCU0

: Reset source of CCU0

0 = Reset counter register CN0 to 0 on matching comparison CM0

1 = Reset counter register CN0 to 0 on trigger TRIG_14

Reserved

Note: Read as zero, should be written as zero.

TRIGOUT

: Trigger output selection (output signal TRIG_15) of module TOM_CH15

0 = TRIG_15 is TRIG_14

1 = TRIG_15 is TRIG_CCU0

Reserved

Note: Read as zero, should be written as zero.

OSM

: One-shot mode. In this mode the counter CN0 counts for only one period. The length of period is defined by CM0. A write access to the register CN0 triggers the start of counting.

0 = One-shot mode disabled

1 = One-shot mode enabled

BITREV

: Bit-reversing of output of counter register CN0. This bit enables the PCM mode of channel 15

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000

CN0

0x0000

Bit

[16:31]

[0:15]

Table 128. TOM[i]_CH[x]_CN0 field description

Description

CN0

: TOM CCU0 counter register

This counter is stopped if the TOM channel is disabled and not reset on an enable event of

TOM channel.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000

CM0

0x0000

Bit

[16:31]

[0:15]

Table 129. TOM[i]_CH[x]_CM0 field description

Description

CN0

: TOM CCU0 counter register

Setting CM0 < CM1 configures a duty cycle of 100 %.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved SR0 Bit

Mode

Initial value

0x0000

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[16:31]

[0:15]

Timer Output Module (TOM)

Table 130. TOM[i]_CH[x]_SR0 field description

Description

SR0 : TOM channel x shadow register SR0 for update of compare register CM0.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved CM1 Bit

Mode

Initial value

0x0000

Bit

[16:31]

[0:15]

Table 131. TOM[i]_CH[x]_CM1 field description

Description

CM1 : TOM CCU1 compare register

Setting CM1 = 0 configures a duty cycle of 0% independent of the configured value of CM0.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[16:31]

[0:15]

Table 132. TOM[i]_CH[x]_SR1 field description

Description

SR1 : TOM channel x shadow register SR1 for update of compare register CM1

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B

Bit

Mode

Initial value

Initial value:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x0000000

0x0000_0000 x

Bit

[0:30]

Table 133. TOM[i]_CH[x]_STAT field description

Description

: Output level of output TOM_OUT(x)

Note: Reset value is the inverted value of SL bit which depends on the hardware configuration chosen by silicon vendor.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

0x0000000

C w

0 0

C w

Bit

[0:29]

Table 134. TOM[i]_CH[x]_IRQ_NOTIFY field description

Description

CCU0TC : CCU0 Trigger condition interrupt for channel x

0 = No interrupt occurred

1 = The condition CN0 >= CM0 was detected.

The notification of the interrupt is only triggered one time after reaching the condition CN0 >=

CM0. To re-trigger the notification first the condition CN0 < CM0 has to be occurred.

CCU1TC : CCU1 Trigger condition interrupt for channel x

0 = No interrupt occurred

1 = The condition CN0 >= CM1 was detected.

The notification of the interrupt is only triggered one time after reaching the condition CN0 >=

CM1. To re-trigger the notification first the condition CN0 < CM1 has to be occurred

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

0 0

Mode

Initial value

Bit

[0:29]

0x0000000

Table 135. TOM[i]_CH[x]_IRQ_EN field description

Description

CCU0TC_IRQ_EN

: TOM_CCU0TC_IRQ interrupt enable

0 = Disable interrupt, interrupt is not visible outside GTM-IP

1 = Enable interrupt, interrupt is visible outside GTM-IP

CCU1TC_IRQ_EN

: TOM_CCU1TC_IRQ interrupt enable see bit 31

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Reserved

Mode

Initial value

0x0000000

A w

0 0

A w

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Bit

[0:29]

Table 136. TOM[i]_CH[x]_IRQ_FORCINT field description

Description

TRG_CCU0TC0 : Trigger TOM_CCU0TC0_IRQ interrupt by software

0 = No interrupt triggering

1 = Assert CCU0TC0_IRQ interrupt for one clock cycle

Note:

This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_CCU1TC0

: Trigger TOM_CCU1TC0_IRQ interrupt by software

0 = No interrupt triggering

1 = Assert CCU1TC0_IRQ interrupt for one clock cycle

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

Reserved

Note:

Read as zero, should be written as zero.

RM0361

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value:

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

IRQ_

MOD

0x00000000

0x0000_000X

Bit

[30:31]

[0:29]

Table 137. TOM[i]_CH[x]_IRQ_MODE field description

Description

IRQ_MODE

: IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note:

Read as zero, should be written as zero.

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12

ARU-connected Timer Output Module (ATOM)

ARU-connected Timer Output Module (ATOM)

12.1 Overview

The ARU-connected Timer Output Module (ATOM) is able to generate complex output signals without CPU interaction thanks to its connectivity to the ARU. Typically, output signal characteristics are provided over the ARU connection through submodules connected to

ARU like e.g. the MCS, DPLL or PSM. Each ATOM submodule contains eight output channels which can operate independently from each other in several configurable operation modes. A block diagram of the ATOM submodule is depicted in

Figure 42 .

Figure 42. ATOM block diagram

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The architecture of the ATOM submodule is similar to the TOM submodule, but there are some differences. First, the ATOM integrates only eight output channels. Hence, there exists one ATOM Global Control subunit (AGC) for the ATOM channels. The ATOM is connected to the ARU and can set up individual read requests from the ARU and write requests to the ARU. Furthermore, the ATOM channels are able to generate signals on behalf of time stamps and the ATOM channels are able to generate a serial output signal on behalf of an internal shift register.

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ARU-connected Timer Output Module (ATOM) RM0361

Each ATOM channel provides four modes of operation:

 ATOM Signal Output Mode Immediate (SOMI)

 ATOM Signal Output Mode Compare (SOMC)

 ATOM Signal Output Mode PWM (SOMP)

 ATOM Signal Output Mode Serial (SOMS)

These modes are described in more detail in

Section 12.3: ATOM channel modes

The ATOM channels’ operation registers (e.g. counter, compare registers) are 24-bit wide.

Moreover, the input clocks for the ATOM channels come from the configurable CMU_CLKx signals of the CMU submodule. This gives the freedom to select a programmable input clock for the ATOM channel counters. The ATOM channel is able to generate a serial bit stream, which is shifted out at the ATOM[i]_CH[x]_OUT output. When configured in this serial shift mode (SOMS) the selected CMU clock defines the shift frequency.

Each ATOM channel provides the so called operation and shadow register sets. With this architecture it is possible to work with the operation register set, while the shadow register set can be reloaded with new parameters over CPU and/or ARU.

When update via ARU is selected, it is possible to configure if both shadow registers are updated via ARU or only one of the shadow registers is updated for SOMP mode.

On the other hand, the shadow registers can be used to provide data to the ARU when one or both of the compare units inside an ATOM channel match. This feature is only applicable in SOMC mode.

As in TOM channels it is possible to reload the content of the ATOM channels operation registers with the content of the corresponding shadow registers and change the clock input signal for the counter register simultaneously.

In addition to the feature that the CPU can select another CMU_CLKx during operation (i.e. updating the shadow register bit field CLK_SRC_SR of the ATOM[i]_CH[x]_CTRL register), the selection can also be changed via the ARU. Then, for the clock source update, the ACBI register bits of the ATOM[i]_CH[x]_STAT register are used as a shadow register for the new clock source.

In general, the behavior of the compare units CCU0 and CCU1 and the output signal behavior are controlled with the ACB bit field inside the ATOM[i]_CH[x]_CTRL register when the ARU connection is disabled and the behavior is controlled via ARU through the

ACBI bit field of the ATOM[i]_CH[x]_STAT register, when the ARU is enabled.

Since the ATOM is connected to the ARU, the shadow registers of an ATOM channel can be reloaded via the ARU connection or via CPU over its AEI interface. When loaded via the

ARU interface, the shadow registers act as a buffer between the ARU and the channel operation registers. Thus, a new parameter set for a PWM can be reloaded via ARU into the shadow registers, while the operation registers work on the actual parameter set.

12.1.1 ATOM Global Control (AGC)

Synchronous start and stop of more than one output channel is possible with the AGC subunit. This subunit has the same functionality as the TGC subunit of the TOM submodule.

For a description of the AGC subunit functionality, please refer therefore to Section 11.2:

TOM global channel control (TGC0, TGC1)

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12.1.2 ATOM channel mode overview

Each ATOM channel offers the following different operation modes:

In ATOM Signal Output Mode Immediate (SOMI), the ATOM channels generate an output signal immediately after receiving an ARU word according to the two signal level output bits of the ARU word received through the ACBI bit field. Due to the fact, that the

ARU destination channels are served in a round robin order, the output signal can jitter in this mode with a jitter of the ARU round trip time.

2. In ATOM Signal Output Mode Compare (SOMC), the ATOM channel generates an output signal on behalf of time stamps that are located in the ATOM operation registers.

These time stamps are compared with the time stamps, the TBU generates. The ATOM is able to receive new time stamps either by CPU or via the ARU. The new time stamps are directly loaded into the channels operation register. The shadow registers are used as capture registers for two time base values, when a compare match of the channels operation registers occurs.

3. In ATOM Signal Output Mode PWM (SOMP), the ATOM channel is able to generate simple and complex PWM output signals like the TOM submodule by comparing its operation registers with a submodule internal counter. In difference to the TOM, the

ATOM shadow registers can be reloaded by the CPU and by the ARU in the background, while the channel operates on the operation registers.

4. In ATOM Signal Output Mode Serial (SOMS), the ATOM channel generates a serial output bit stream on behalf of a shift register. The number of bits shifted and the shift direction is configurable. The shift frequency is determined by one of the CMU_CLKx

clock signals. Please refer to Section 12.3.4: ATOM Signal Output Mode Serial (SOMS)

for further details.

12.2 ATOM channel architecture

Each ATOM channel is able to generate output signals according to four operation modes.

The architecture of the ATOM channels is similar to the architecture of the TOM channels.

The general architecture of an ATOM channel is depicted in

Figure 43 .

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ARU-connected Timer Output Module (ATOM)

12.2.1 ATOM channel architecture

Figure 43. ATOM channel architecture

RM0361

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RM0361 ARU-connected Timer Output Module (ATOM)

For all ATOM channels the operation registers (CN0, CMO and CM1) and the shadow registers (SR0 and SR1) are 24-bit wide . The comparators inside CCU0 and CCU1 provide a selectable signed greater/equal or less/equal comparison to compare against the GTM time bases TBU_TS0 and TBU_TS1 . If there is a third time base TBU_TS2 implemented inside the GTM, this time base can also be selected inside the ATOM channel with the

TB12_SEL bit inside the ATOM[i]_CH[x]_CTRL register for comparison. Please refer

Chapter 9: Time Base Unit (TBU) for further details. For an overview of the implemented

TBU submodule version please refer to

Figure 1: GTM-IP_103 architecture block diagram

The CCU0 and CCU1 units have different tasks for the different ATOM channel modes.

The signed compare is used to detect time base overflows and to guarantee, that a compare match event can be set up for the future even when the time base will first overflow and then reach the compare value. Please note, that for a correct behavior of this signed compare, the new compare value must not be specified larger/smaller than half of the range of the total time base value (0x7FFFFF).

In SOMC mode, the two compare units CCUx can be used in combination to each other.

When used in combination, the trigger lines TRIG_CCU0 and TRIG_CCU1 can be used to enable/disable the other compare unit on a match event. Please refer to

Section 12.3.2:

ATOM Signal Output Mode Compare (SOMC)

for further details.

The Signal Output Unit (SOU) generates the output signal for each ATOM channel. This output signal level depends on the ATOM channel mode and on the SL bit of the

ATOM[i]_CH[x]_CTRL register in combination with the two control bits. These two control bits ACB(1) and ACB(0) can either be received via CPU in the ACB register field of the

ATOM[i]_CH[x]_CTRL register or via ARU in the ACBI bit field of the

ATOM[i]_CH[x]_STAT register.

The SL bit in the ATOM[i]_CH[x]_CTRL register defines in all modes the operational behaviour of the ATOM channel.

When the channel and its output are disabled, the output signal level of the channel is the inverse of the SL bit.

In SOMI and SOMC modes the output signal level depends on the SL, ACB0 and ACB1 bits. In SOMP mode the output signal level depends on the two trigger signals TRIG_CCU0 and TRIG_CCU1 since theses two triggers define the PWM timing characteristics and the

SL bit defines the level of the duty cycle. In SOMS mode the output signal level is defined by the bit pattern that has to be shifted out by the ATOM channel. The bit pattern is located inside the CM1 register.

The ARU Communication Interface (ACI) subunit is responsible for requesting data routed through ARU to the ATOM channel in SOMI, SOMP and SOMS modes, and additionally for providing data to the ARU in SOMC mode.

In SOMC mode the ACI shadow registers have a different behaviour and are used as output buffer registers for data send to ARU.

The ATOM channels have an ARU Communication Interface (ACI) subunit. This subunit is responsible for data exchange from and to the ARU. This is done with the two implemented registers SR0 , SR1 , and the ACBI and ACBO bit fields that are part of the

ATOM[i]_CH[x]_STAT

register. The ACI architecture is shown in Figure 44

If the ARU_EN bit is set inside the ATOM[i]_CH[x]_CTRL register, the ATOM channel is enabled by setting the enable bits inside the ATOM[i]_AGC_ENDIS_STAT register and the

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CPU hasn't written data not equal to zero into the CM0 , CM1, SR0, SR1 register, the ATOM channel will first request data from the ARU before the signal generation starts in SOMP,

SOMS and SOMC mode.

If in SOMP mode there is data inside the CM0 or SR0 register not equal to '0' the channel counter CN0 will start counting immediately, regardless whether the channel has received

ARU data yet.

If in SOMS mode there is data inside the CM0 or SR0 register not equal to '0' the channel will start shifting immediately, regardless whether the channel has received ARU data yet.

Figure 44. ACI architecture overview

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Incoming ARU data (53-bit width signal ARU_CHx_IN ) is split into three parts by the ACI and communicated to the ATOM channel registers. In SOMI, SOMP and SOMS modes incoming ARU data ARU_CHx_IN is split in a way that the lower 24 bits of the ARU data (23 downto 0) are stored in the SR0 register, the upper bits (47 down to 24) are stored in the

SR1 register and the bits 52 down to 48 ( CTRL_BITS ) are stored in the ACBI bit field of the register ATOM[i]_CH[x]_STAT .

The ATOM channel has to ensure, that in a case when the channel operation registers CM0 and CM1 are updated with the SR0 and SR1 register content and an ARU transfer to these

DocID025070 Rev 1

RM0361 ARU-connected Timer Output Module (ATOM) shadow registers happens in parallel that either the old data in both shadow registers is transferred into the operation registers or both new values from the ARU are transferred.

In SOMC mode incoming ARU data ARU_CHx_IN is written directly to the ATOM channel operation register in the way that the lower 24 bits (23 down to 0) are written to CM0 , and the bits 47 down to 24 are written to register CM1 . The bits 52 down to 48 are stored in the

ACBI bit field of the ATOM[i]_CH[x]_STAT register and control the behavior of the compare units and the output signal of the ATOM channel.

In SOMC mode the SR0 and SR1 registers serve as capture registers for the time stamps coming from TBU whenever a compare match event is signaled by the CCU0 and/or CCU1 subunits via the CAP signal line. These two time stamps are then provided together with actual ATOM channel status information located in the ACBO bit field to the ARU at the dedicated ARU write address of the ATOM channel when the ARU is enabled.

The encoding of the ARU control bits in the different ATOM operation modes is described in more detail in the following chapters.

12.3 ATOM channel modes

As described above, each ATOM channel can operate independently from each other in one of four dedicated output modes:

 ATOM Signal Output Mode Immediate (SOMI)

 ATOM Signal Output Mode Compare (SOMC)

 ATOM Signal Output Mode PWM (SOMP)

 ATOM Signal Output Mode Serial (SOMS)

The Signal Output Mode PWM (SOMP) is principally the same as the output mode for the

TOM submodule except the bit reverse mode which is not included in the ATOM. In addition, it is possible to reload the shadow registers over the ARU without the need of a CPU interaction. The three other modes provide additional functionality for signal output control.

All operation modes are described in more detail in the following sections.

Note that in any output mode, if a channel is enabled, one-shot mode is disabled ( OSM = 0; only used in modes SOMP and SOMS) and CM0 >= CN0 , the counter CN0 is incrementing until it reaches CM0 .

To avoid unintended counting of CN0 after enabling a channel, it is recommended to reset a channel (or at least CN0 and CM0 ) before any change on the mode bits MODE, ARU_EN and OSM.

In ATOM Signal Output Mode Immediate (SOMI), the ATOM channel generates output signals on the ATOM[i]_CH[x]_OUT output port immediate after update of the bit ACBI(0) of register ATOM[i]_CH[x]_STAT or ACB(0) bit of register ATOM[i]_CH[x]_CTRL .

If ARU access is enabled by setting bit ARU_EN in register ATOM[i]_CH[x]_CTRL , the update of the output ATOM[i]_CH[x]_OUT depends on the bit ACBI(0) of register

ATOM[i]_CH[x]_STAT received at the ACI subunit and the bit SL bit of register

ATOM[i]_CH[x]_CTRL . The remaining 48 ARU bits (47 downto 0) have no meaning in this mode.

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If ARU access is disabled, the update of the output ATOM[i]_CH[x]_OUT depends on the bit

ACB(0) and the bit SL of register ATOM[i]_CH[x]_CTRL .

The initial ATOM channel port pin ATOM[i]_CH[x]_OUT signal level has to be specified by the SL bit field of the ATOM[i]_CH[x]_CTRL register when OUTEN_CTRL register bit field

OUTEN_CTRLx is disabled (see

Section 11.8.5: Register TOM[i]_TGC0_OUTEN_CTRL

) for details.

In SOMI mode the output behavior depends on the SL bit of register ATOM[i]_CH[x]_CTRL and the bit ACBI(0) of the ATOM[i]_CH[x]_STAT register or the bit ACB0 of register

ATOM[i]_CH[x]_CTRL .

Table 138. ATOM output level behavior in SOMI mode

ACBI(0)/

ACB(0)

Output behavior

Set output to inverse of SL (1)

Set output to SL (0)

Set output to inverse of SL (0)

Set output to SL (1)

12.3.1.1 Register ATOM[i]_CH[x]_CTRL in SOMI mode (x: 0...7)

Address offset: see Appendix B Initial value: 0x0000_0x00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

The signal level bit ACBI(0) is transferred to the SOU subunit of the ATOM and made visible at the output port according to the table above immediately after the data was received by the ACI. This can introduce a jitter on the output signal since the ARU channels are served in a time multiplexed fashion.

Mode

Initial value

Bit

[30:31]

0 0 0

0 0

W x

Table 139. ATOM[i]_CH[x]_CTRL in SOMI mode field description

Description

MODE

: ATOM channel mode select.

00: ATOM Signal Output Mode Immediate (SOMI)

Not used

: Not used in this mode

Note:

Not used in this mode.

ARU_EN

: ARU Input stream enable

0 = ARU Input stream disabled

1 = ARU Input stream enabled

0 0 0

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Bit

Table 139. ATOM[i]_CH[x]_CTRL in SOMI mode field description (continued)

Description

[23:26]

[21:22]

[17:19]

[12:14]

[8:10]

[0:4]

ACB(0) : ACB bit 0

0 = Set output to inverse of SL bit

1 = Set output to SL bit

Not used

: Not used in this mode

Note: Not used in this mode.

Reserved

Note: Read as zero, should be written as zero.

: Initial signal level after channel is enabled

0 = Low signal level

1 = High signal level

Note: Reset value depends on the hardware configuration chosen by silicon vendor.

Note:

After reset and if channel is disabled, the register SOUR is set to the inverse reset value of bit SL (i.e. '1'). If the channel is disabled or the output is disabled, the output

ATOM_OUT[x] is set to inverse value of SL.

Not used

: Not used in this mode

Reserved

Note:

Read as zero, should be written as zero.

Not used

: Not used in this mode

Reserved

Note:

Read as zero, should be written as zero.

Not used

: Not used in this mode

Not used

: Not used in this mode

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

12.3.2.1 Overview

In ATOM Signal Output Mode Compare (SOMC) the output action is performed in dependence of the comparison between input values located in CM0 and/or CM1 registers and the two (three) time base values TBU_TS0 or TBU_TS1 (or TBU_TS2 ) provided by the

TBU. For a description of the time base generation please refer to the TBU specification in

Chapter 9: Time Base Unit (TBU) . User can select, which of the two (three) time bases is to

be compared with one or both values in CM0 and CM1 .

The behavior of the two compare units CCU0 and CCU1 is controlled either with the bits 4 down to 2 of ACB bit field inside the ATOM[i]_CH[x]_CTRL register, when the ARU connection is disabled or with the ACBI bit field of the ATOM[i]_CH[x]_STAT register, when

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The CCUx trigger signals TRIG_CCU0 and TRIG_CCU1 always create edges, depending on the predefined signal level in SL bit in combination with two control bits that can be specified by either ARU or CPU within the aforementioned ATOM[i]_CH[x]_CTRL or

ATOM[i]_CH[x]_STAT registers.

In SOMC mode the channel is always disabled after the specified compare match event occurred. The shadow registers are used to store two time stamp values at the match time.

The channel can be enabled again by first reading the shadow registers, either by CPU or

ARU and by providing new data for CMx registers through CPU or ARU. For a detailed description please refer to the

Section 12.3.2.2: SOMC Mode under CPU control

and

Section 12.3.2.3: SOMC mode under ARU control .

If three time bases exist for the GTM-IP there must be a preselection between TBU_TS1 and TBU_TS2 for the ATOM channel. This can be done with TB12_SEL bit in the

ATOM[i]_CH[x]_CTRL register.

The comparison in CCU0/1 with time base TBU_TS1 or TBU_TS2 can be done on a greater/equal or less/equal comparison according to the CMP_CTRL bit. This control bit has no effect to a compare unit CCU0 or CCU1 that compares against TBU_TS0. In this case always a greater/equal compare is done. The bit CMP_CTRL is part of the

ATOM[i]_CH[x]_CTRL register.

When configured in SOMC mode, the channel port pin has to be initialized to an initial signal level. This initial level after enabling the ATOM channel is determined by the SL bit in the

ATOM[i]_CH[x]_CTRL register. If the output is disabled, the signal level is set to the inverse level of the SL bit.

If the channel is disabled, the register SOUR is set to the SL bit in the

ATOM[i]_CH[x]_CTRL register.

On a compare match event the shadow registers SR0 and SR1 are used to capture the TBU time stamp values. SR0 always holds TBU_TS0 and SR1 either holds TBU_TS1 or

TBU_TS2 depending on the TB12_SEL bit in the ATOM[i]_CH[x]_CTRL register.

Please note, that when the channel is disabled and the compare registers are written, the compare registers CMx are loaded with the written value and the channel starts with the comparison on behalf of this values, when the channel is enabled.

12.3.2.2 SOMC Mode under CPU control

As already mentioned above the ATOM channel can be controlled either by CPU or by ARU.

When the channel should be controlled by CPU, the ARU_EN bit inside the

ATOM[i]_CH[x]_CTRL register has to be reset.

The output of the ATOM channel is set on a compare match event depending on the ACB10 bit field in combination with the SL bit both located in the ATOM[i]_CH[x]_CTRL register.

The output behavior according to the ACB10 bit field in the control register is shown in the following table.

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Table 140. ATOM output level behavior in SOMC mode

ACB10(5) ACB10(4) Output behavior

No signal level change at output (exception in

Table 143

mode ACB42 =

001)

Set output signal level to 1

Set output signal level to 0

Toggle output signal level (exception in Table 143 mode ACB42 = 001)

No signal level change at output (exception in

Table 143

mode ACB42 =

001)

Set output signal level to 0

Set output signal level to 1

Toggle output signal level (exception in

Table 143

mode ACB42 = 001)

The capture/compare strategy of the two CCUx units can be controlled with the ACB42 bit field inside the ATOM[i]_CH[x]_CTRL register. The meaning of these bits is shown in the following table.

ACB42(8) ACB42(7)

Table 141. ATOM CCUx operation in SOMC mode

ACB42(6) CCUx control

Serve First: Compare in CCU0 using TBU_TS0 and in parallel in

CCU1 using

TBU_TS1 or

TBU_TS2

. Disable other CCUx on compare match. Output signal level on the compare match of the matching CCUx unit is defined by combination of SL, ACB10(5) and

ACB10(4).

Details see

Table 143

Serve First: Compare in CCU0 using TBU_TS0 and in parallel in

CCU1 using TBU_TS1 or TBU_TS2 . Disable other CCUx on compare match. Output signal level on the compare match of the matching CCUx unit is defined by combination of SL, ACB10(5) and

ACB10(4).

Details see

Table 143

Compare in CCU0 only, use time base

TBU_TS0

. Output signal level is defined by combination of SL, ACB10(5) and ACB10(4) bits.

Compare in CCU1 only, use time base TBU_TS1 or TBU_TS2 .

Output signal level is defined by combination of SL, ACB10(5) and

ACB10(4) bits.

Serve Last: Compare in CCU0 and then in CCU1 using

TBU_TS0

Output signal level when CCU0 matches is defined by combination of SL, ACB10(5) and ACB10(4). On the CCU1 match the output level is toggled.

Serve Last: Compare in CCU0 and then in CCU1 using TBU_TS1 or TBU_TS2 . Output signal level when CCU0 matches is defined by combination of SL, ACB10(5) and ACB10(4). On the CCU1 match the output level is toggled.

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ACB42(8)

Table 141. ATOM CCUx operation in SOMC mode (continued)

ACB42(7) ACB42(6) CCUx control

Serve Last: Compare in CCU0 using TBU_TS0 and then in CCU1 using

TBU_TS1

TBU_TS2

. Output signal level when CCU1 matches is defined by combination of SL, ACB10(5) and ACB10(4).

Not used when ARU disabled.

ACB4

The behavior of the ACBI/ACB42 bit combinations '000' and '001' is described in more details in

Table 142

and

Table 143

Table 142. ATOM channel operation in SOMC serve first when ACB42 = '000'

ACB3 ACB2 ACB1 ACB0 SL

CCU0 match

CCU1 match

Pin level new

0 toggle toggle toggle hold hold hold hold hold

0 hold

1 toggle toggle toggle

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ACB4

Table 143. ATOM channel operation in SOMC serve first when ACB42 = '001'

ACB3 ACB2 ACB1 ACB0 SL

CCU0 match

CCU1 match

Pin level new

1 toggle hold toggle hold toggle hold

0 hold toggle hold

0 toggle hold toggle

If the ATOM channel is enabled, the CM0 and/or CM1 registers and the ACB42 bit field of the ATOM[i]_CH[x]_CTRL register can be updated by the CPU until the first match event occurs in case of a serve last compare strategy or until the overall match event in case of the other compare strategies.

After a compare match event that causes an update of the shadow registers SR0 / SR1 and before reading the SR0 and/or SR1 register via ARU, the update of the registers CM0 and/or CM1 is possible but has no effect.

To set up a new compare action, first the SR0 and/or SR1 register containing captured values have to be read and then new compare values have to be written into the register

CM0 and/or CM1 .

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Which CMx register has to be updated depends on the compare strategy defined in the

ACB42 bit field of the channel control register. Since the channel immediately starts with the comparison after the CMx register was/were written, the compare strategy has to be updated before the CMx registers are written.

For the serve last compare strategies , if the CM0 and CM1 registers are updated, it can happen that one or both compare values are already located in the past. In any way the

ATOM channel will first wait until both compare values are written, before it starts the time base comparisons to avoid a deadlock.

The CPU can check at any time if at least one of the ATOM channels' capture compare register contains valid data and waits for a compare event to happen. This is signaled by the

DV bit inside the ATOM[i]_CH[x]_STAT register.

For serve last compare strategies, if the DV bit is currently not set, a write to CM0 or CM1 immediately sets the DV bit although the compare is only started if both values are written

In SOMC mode and CCUx control mode 'serve last' an exception exists to update the register CM0 / CM1 . If in this mode the CCU0 compare match event occurred, the update of register CM0 / CM1 via CPU is blocked until the CCU1 compare match event.

In the serve last mode (ACB42 = "100" or ACB42 = "101") it is possible to generate very small spikes on the output pin by loading CM0 and CM1 with two time stamp values for

TBU_TS0 , TBU_TS1 or TBU_TS2 close together. The output pin will then be set or reset depending on the SL bit and the specified ACB10(5) and ACB10(4) bits in the ACB10 bit field of the ATOM[i]_CH[x]_CTRL register on the first match event and the output will toggle on the second compare event in the CCU1 compare unit.

It is important to note, that the bigger (smaller) time stamp has to be loaded into the CM1 register, since the CCU0 will enable the CCU1 once it has reached its comparison time stamp. The order of the comparison time stamps depends on the defined greater/equal or less/equal comparison of the CCUx units.

In addition to storing the captured time stamps in the shadow registers, the ATOM channel provides the result of the compare match event in the ACBO(4) and ACBO(3) bits of the

ATOM[i]_CH[x]_STAT register. The meaning of the bits is shown in the following table.

ACBO(4)

Table 144. ACBO(4)/(3) compare match status

ACBO(3) Indication

CCU0 compare match occurred

CCU1 compare match occurred

Please note, that in case of the 'serve last' compare strategy, when the SLA-bit in the

ATOM[i]_CH[x]_CTRL register is not set, the ACBO(4) bit is always set and the ACBO(3) bit is always reset after the compare match event occurred.

The ACBO bit field is reset, when the DV bit is set.

Depending on the capture compare unit where the time base matched the interrupt

CCU0TCx_IRQ or CCU1TCx_IRQ is raised.

The behavior of an ATOM channel in SOMC mode under CPU control is visualized in

Figure 45

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Figure 45. SOMC state diagram for channel under CPU control

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12.3.2.3 SOMC mode under ARU control

When the channel should be controlled by ARU, the ARU_EN bit inside the

ATOM[i]_CH[x]_CTRL register has to be set.

In case, the ATOM channel is under ARU control the content for the compare registers CM0 and CM1 as well as the update of the compare strategy can be loaded via the 53 bits ARU word.

The ARU word bits 23 to 0 are loaded into the CM0 register while the ARU word bits 47 to

24 are loaded into the CM1 register. The five ARU control bits 52 to 48 are loaded into the

ACBI bit field of the ATOM[i]_CH[x]_STAT register and control the channel compare strategy as well as the output behavior in case of compare match events.

For the five ARU control bits 52 to 48 the bits 49 and 48 are loaded into the ACBI bits 1 and

0. The output behavior also depends on the setting of the SL bit inside of the

ATOM[i]_CH[x]_CTRL register and is shown in the following table.

Table 145. SL, ACBI(1) and ACBI(2) effect on ATOM channel output behavior

SL ACBI(1) ACBI(0) Output behavior

No signal level change at output (exception in

Set output signal level to 1

Set output signal level to 0

Toggle output signal level (exception in

Table 142 and

Table 143

mode ACB42 = 001)

No signal level change at output (exception in

Set output signal level to 0

Set output signal level to 1

Toggle output signal level (exception in

Table 142

and

Table 143 mode ACB42 = 001)

For the five ARU control bits 52 to 48 the bits 52 to 50 are loaded into the ACBI bits 4 to 2.

With these three bits the capture/compare units CCUx can be controlled as shown in the following table:

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ACBI(4)

Table 146. ACBI(4:2) effect on CCUx operation

ACBI(3) ACBI(2) CCUx control

Serve First: Compare in CCU0 using TBU_TS0 and in parallel in CCU1 using

TBU_TS1 or

TBU_TS2

. Disable other CCUx on compare match. Output signal level on the compare match of the matching CCUx unit is defined by combination of SL, ACBI(1) and ACBI(0).

Details see

Table 143

Serve First: Compare in CCU0 using TBU_TS0 and in parallel in CCU1 using

TBU_TS1 or

TBU_TS2

. Disable other CCUx on compare match. Output signal level on the compare match of the matching CCUx unit is defined by combination of SL, ACBI(1) and ACBI(0).

Details see

Table 142

Compare in CCU0 only, use time base TBU_TS0 . Output signal level is defined by combination of SL, ACBI(1) and

ACBI(0) bits.

Compare in CCU1 only, use time base TBU_TS1 or

TBU_TS2 . Output signal level is defined by combination of

SL, ACBI(1) and ACBI(0) bits.

Serve Last: Compare in CCU0 and then in CCU1 using

TBU_TS0

. Output signal level when CCU0 matches is defined by combination of SL, ACBI(1) and ACBI(0). On the

CCU1 match the output level is toggled.

Serve Last: Compare in CCU0 and then in CCU1 using

TBU_TS1

TBU_TS2

. Output signal level when CCU0 matches is defined by combination of SL, ACBI(1) and

ACBI(0). On the CCU1 match the output level is toggled.

Serve Last: Compare in CCU0 using TBU_TS0 and then in

CCU1 using TBU_TS1 or TBU_TS2 . Output signal level when CCU1 matches is defined by combination of SL,

ACBI(1) and ACBI(0).

Change ARU read address to ATOM_RDADDR1

DV flag is not set. Neither ACBI(1) nor ACBI(0) is evaluated.

It is important to note that the bit combination "111" for the ACBI(4), ACBI(3) and ACBI(2) bits forces the channel to request new compare values from another destination read address defined in the ATOM_RDADDR1 bit field of the ATOM[i]_CH[x]_RDADDR register.

After data was successfully received and the compare event occurred the ATOM channel switches back to ATOM_RDADDR0 to receive the next data from there.

After the specified compare match event, the captured time stamps are stored in SR0 and

SR1 and the compare result is stored in the ACBO bit field of the ATOM[i]_CH[x]_STAT register. The meaning of the ACBO(4) and ACBO(3) bits of the ATOM[i]_CH[x]_STAT is shown in the following table.

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ACBO(4)

Table 147. ACBO(4:3) compare status

ACBO(3) Return value to ARU

CCU0 compare match occurred

CCU1 compare match occurred

Please note, that in case of the 'serve last' compare strategy, when the SLA-bit in the

ATOM[i]_CH[x]_CTRL register is not set, the ACBO(4) bit is always set and the ACBO(3) bit is always reset after the compare match event occurred.

The ACBO bit field is reset, when the DV bit is set.

Depending on the capture compare unit where the time base matched the interrupt

CCU0TCx_IRQ or CCU1TCx_IRQ is raised.

When CCU0 and CCU1 is used for comparison it is possible to generate very small spikes on the output pin by loading CM0 and CM1 with two time stamp values for TBU_TS0 ,

TBU_TS1 or TBU_TS2 close together. The output pin will then be set or reset depending on the SL bit and the specified ACBI(0) and ACBI(1) bits in the ACBI bit field of the

ATOM[i]_CH[x]_STAT register on the first match event and the output will toggle on the second match event.

For compare strategy 'serve last' the CCU0 and CCU1 compare match may occur sequentially. During different phases of compare match the CPU access rights to register

CM0 and CM1 as well as to WR_REQ bit is different. These access rights by CPU to register CM0 and CM1 and the WR_REQ are depicted in the following figure.

12.3.2.3.1 CPU access rights in case of compare strategy 'serve last'

Figure 46. CPU access rights in case of compare strategy 'serve last'

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RM0361 ARU-connected Timer Output Module (ATOM)

12.3.2.3.2 ARU non-blocking mode

When the compare registers are updated via ARU the update behaviour of the channel is configurable with the ABM bit inside the ATOM[i]_CH[x]_CTRL register. When the ABM bit is reset, the ATOM channel is in ARU non-blocking mode.

In this ARU non-blocking mode, data received via ARU is continuously transferred to the registers CM0 and CM1 and the bit field ACBI of register ATOM[i]_CH[x]_STAT as long as no specified compare match event occurs.

After a compare match event that causes an update of the shadow register SR0 / SR1 and before reading the SR0 / SR1 register via CPU or ARU, the update of the registers CM0 /

CM1 via CPU or ARU is possible but has no effect.

To set up a new compare action, first the SR0 / SR1 registers containing captured values have to be read and then new compare values have to be written into the register

CM0 / CM1 . This can be done either by ARU or by CPU.

When the CPU does the register accesses, only one of the shadow registers has to be read.

Depending on the compare strategy, the CPU has to write one or both of the compare registers.

The CPU can check at any time if the ATOM channel has received valid data from the ARU and waits for a compare event to happen. This is signaled by the DV bit inside the

ATOM[i]_CH[x]_STAT register.

The behavior of an ATOM channel in SOMC mode, when ARU is enabled and ARU blocking mode (ABM) is disabled is shown in

Figure 47 .

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Figure 47. SOMC state diagram for SOMC mode, ARU enabled, ABM disabled

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RM0361 ARU-connected Timer Output Module (ATOM)

12.3.2.3.3 ARU blocking mode

When the compare registers are updated by ARU, the ATOM channel can be configured to receive ARU data in a blocking manner. This can be configured by setting the ABM bit in the

ATOM[i]_CH[x]_CTRL register.

If the ABM and ARU_EN bits are set, the (one) two compare values for CM0 and/or CM1 can be provided by ARU or CPU. If the compare registers CM0 and/or CM1 are/is updated, the ATOM channel waits for the compare match event to happen. No further data is requested from the ARU.

When the specified compare match event happens, the shadow registers SR0 and SR1 are updated together with the ACBO bits in the ATOM[i]_CH[x]_STAT register. The data in the shadow registers is marked as valid for the ARU and the DV bit is reset inside the

ATOM[i]_CH[x]_CTRL register.

If the register SR0 and SR1 holding the captured TBU time stamp values are read by either the ARU or the CPU, the next write access to or update of the register CM0 or CM1 via ARU or the CPU enables the new compare match check again.

At least one of the registers SR0 or SR1 has to be read, before new data is requested from

ARU.

The CPU can check at any time if the ATOM channel has received valid data from the ARU and waits for a compare event to happen. This is signaled by a set DV bit inside the

ATOM[i]_CH[x]_STAT register.

The behavior of an ATOM channel in SOMC mode, when ARU is enabled and ARU blocking

mode is enabled is shown in Figure 48 .

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Figure 48. SOMC state diagram for SOMC mode, ARU enabled and ABM enabled

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RM0361 ARU-connected Timer Output Module (ATOM)

12.3.2.3.4 ATOM SOMC late update mechanism

Although the ATOM channel may be controlled by data received via the ARU, the CPU is able to request at any time a late update of the compare register. This can be initiated by setting the WR_REQ bit inside the ATOM[i]_CH[x]_CTRL register. By doing this, the ATOM will request no further data from ARU (if ARU access was enabled). The channel will in any case continue to compare against the values stored inside the compare registers (if bit DV was set). The CPU can now update the new compare values until the compare event happens by writing to the shadow registers, and force the ATOM channel to update the compare registers by writing to the force update register bits in the AGC register.

If the WR_REQ bit is set and a compare match event happens, any further access to the shadow registers SR0 , SR1 is blocked and the force update of this channel is blocked. In addition, the WRF bit is set in the ATOM[i]_CH[x]_STAT register. Thus, the CPU can determine that the late update failed by reading the WRF bit.

If a compare match event already happened, the WR_REQ bit could not be set until the channel is unlocked for a new compare match event by reading the shadow registers. In addition, the WRF bit is set if the CPU tries to write the WR_REQ bit in that case.

If between a correct WR_REQ bit set, a correct shadow register write, and before the force update is requested by the AGC a match event occurs on the old compare values, the WRF bit will be set.

The WRF bit will be set in any case if the CPU tries to write to a blocked shadow register.

The WR_REQ bit and the DV bit will be reset on a compare match event.

A blocked force update mechanism will be enabled again after a read access to the register

SR0 or SR1 by either the ARU or the CPU.

The ATOM SOMC late update mechanism from CPU is shown in

Figure 49

Figure 49. SOMC state diagram for late update requests by CPU

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12.3.2.4 Register ATOM[i]_CH[x]_CTRL in SOMC mode (x: 0...7)

Address offset: see Appendix B Initial value: 0x0000_0x00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 00 0 0 00

Bit

[30:31]

[26:27]

[23:25]

Table 148. ATOM[i]_CH[x]_CTRL in SOMC mode field description

Description

MODE : ATOM channel mode select.

01: ATOM Signal Output Mode Compare (SOMC)

TB12_SEL : Select time base value TBU_TS1 or TBU_TS2.

0 = TBU_TS1 selected for comparison

1 = TBU_TS2 selected for comparison

Note:

This bit is only applicable if three time bases are present in the GTM-IP. Otherwise, this bit is reserved.

ARU_EN : ARU Input stream enable.

0 = ARU Input stream disabled

1 = ARU Input stream enabled

ACB10 : Signal level control bits.

00: No signal level change at output (exception in

Table 142

and

Table 143

mode

ACB42=001).

01: Set output signal level to 1 when SL bit = 0 else output signal level to 0.

10: Set output signal level to 0 when SL bit = 0 else output signal level to 1.

11: Toggle output signal level (exception in

Table 142

and

Table 143

mode ACB42=001).

Note: These bits are only applicable if ARU_EN = '0'.

ACB42

: ATOM control bits ACB(4), ACB(3), ACB(2)

000: Compare in CCU0 and CCU1 in parallel, disable the CCUx on a compare match on either of compare units. Use TBU_TS0 in CCU0 and TBU_TS1 or TBU_TS2 in CCU1.

001: Compare in CCU0 and CCU1 in parallel, disable the CCUx on a compare match on either compare units. Use TBU_TS0 in CCU0 and TBU_TS1 or TBU_TS2 in CCU1.

010: Compare in CCU0 only against TBU_TS0.

011: Compare in CCU1 only against TBU_TS1 or TBU_TS2.

100: Compare first in CCU0 and then in CCU1. Use TBU_TS0.

101: Compare first in CCU0 and then in CCU1. Use TBU_TS1 or TBU_TS2.

110: Compare first in CCU0 and then in CCU1. Use TBU_TS0 in CCU0 and TBU_TS1 or

TBU_TS2 in CCU1.

111: Reserved.

Note:

These bits are only applicable if ARU_EN = '0'.

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Bit

Table 148. ATOM[i]_CH[x]_CTRL in SOMC mode field description (continued)

Description

[17:19]

[12:14]

[8:10]

CMP_CTRL : CCUx compare strategy select.

0 = Greater/equal compare against TBU time base values (TBU_TS1/2 >= CM0/1)

1 = Less/equal compare against TBU time base values (TBU_TS1/2 <= CM0/1)

Note:

The compare unit CCU0 or CCU1 that compares against TBU_TS0 (depending on

CCUx control mode defined by ACBI(4:2) or ACB42) always performs a greater/equal comparison, independent of CMP_CTRL bit.

Reserved

Note:

Read as zero, should be written as zero.

SL : Initial signal level after channel enable.

0 = Low signal level

1 = High signal level

Note:

Reset value depends on the hardware configuration chosen by silicon vendor.

Note: If the output is disabled, the output ATOM_OUT[x] is set to inverse value of SL.

Note:

If the channel and output are disabled, in MODE=01 (SOMC mode) the output register of SOU unit is set to value of SL. If the output is enabled afterwards, the output

ATOM_OUT[x] is equal to the value of SL.

Not used

: Not used in this mode

Reserved

Note:

Read as zero, should be written as zero.

WR_REQ

: CPU write request bit

0 = No late update requested by CPU

1 = Late update requested by CPU

Note: The CPU can disable subsequent ARU read requests by the channel and can update the shadow registers with new compare values, while the compare units operate on old compare values received by former ARU accesses, if occurred.

Note: On a compare match event, the WR_REQ bit will be reset by hardware.

Note: At the point of the force update only the shadow registers SR0 and SR1 are transferred into the CM0, CM1 registers. The output action is still defined by the ACBI bit field described by the ARU together with the old compare values for CM0/CM1.

Reserved

Note:

Read as zero, should be written as zero.

Not used

: Not used in this mode

Not used

: Not used in this mode

TRIGOUT

: Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx.

0 = TRIG_[x] is TRIG_[x-1]

1 = TRIG_[x] is TRIG_CCU0

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Bit

Table 148. ATOM[i]_CH[x]_CTRL in SOMC mode field description (continued)

Description

[0:3]

SLA : Serve last ARU communication strategy.

0 = Capture SRx time stamps after CCU0 match event not provided to ARU

1 = Capture SRx time stamps after CCU0 match event provided to ARU

Please note, that setting of this bit has only effect, when ACBI(4:2) is configured for serve last compare strategy ("100", "101", or "110").

Note:

When this bit is not set, the captured time stamps in the shadow registers SRx are only provided after the CCU1 match occurred. The ACBO(4:3) bits always return "10" in that case.

Note: By setting this bit, the ATOM channel also provides the captured time stamps after the

CCU0 match event to the ARU. The ACBO(4:3) bits are set to “01” in that case. After the

CCU1 match event, the time stamps are captured again in the SRx registers and provided to the ARU. The ACBO(4:3) bits are set to “10”. When the data in the shadow registers after the CCU0 match was not consumed by an ARU destination and the CCU1 match occurs, the data in the shadow registers is overwritten by the new captured time stamps. The ATOM channel does not request new data from the ARU when the CCU0 match values are read from an ARU destination.ture SRx time stamps after CCU0 match event provided to ARU. The ACBO(4:3) bits are set to “10”. When the data in the shadow registers after the CCU0 match was not consumed by an ARU destination and the CCU1 match occurs, the data in the shadow registers is overwritten by the new captured time stamps. The ATOM channel does not request new data from the ARU when the CCU0 match values are read from an ARU destination.

Not used

: Not used in this mode

ABM

: ARU blocking mode

0 = ARU blocking mode disabled: ATOM reads continuously from ARU and updates CM0,

CM1 independent of pending compare match event

1 = ARU blocking mode enabled: after updating CM0,CM1 via ARU, no new data is read from

ARU until compare match event occurred and SR0 and/or SR1 are read.

Reserved

Note:

Read as zero, should be written as zero.

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In ATOM Signal Output Mode PWM (SOMP) the ATOM submodule channel is able to generate complex PWM signals with different duty cycles and periods. Duty cycles and periods can be changed synchronously and asynchronously. Synchronous change of the duty cycle and/or period means that the duty cycle or period duration changes after the end of the preceding period. An asynchronous change of period and/or duty cycle means that the duration changes during the actual running PWM period.

The signal level of the pulse generated inside the period can be configured inside the channel control register (SL bit of ATOM[i]_CH[x]_CTRL register). The initial signal output

level for the channel is the reverse pulse level defined by the SL bit. Figure 50 clarifies this

behavior.

In SOMP mode, depending on the configuration bits RST_CCU0 of register

ATOM[i]_CH[x]_CTRL the counter register CN0 can be reset either when the counter value is equal to the compare value CM0 or when signaled by the ATOM[i] trigger signal TRIG_[x-

1] of the preceding channel.

DocID025070 Rev 1

RM0361 ARU-connected Timer Output Module (ATOM)

In this case, if UPEN_CTRL[x] = 1, also the working register CM0, CM1 and CLK_SRC are updated.

Figure 50. PWM output behavior with respect to the SL bit in the

ATOM[i]_CH[x]_CTRL register

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On an asynchronous update, it is guaranteed, that no spike occurs at the output port of the channel due to a too late update of the operation registers. The behavior of the output signal due to the different possibilities of an asynchronous update during a PWM period is shown in

Figure 51

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Figure 51. PWM output behavior in case of an asynchronous update of the duty cycle

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The duration of the pulse high or low time and period is measured with the counter in subunit CCU0. The trigger of the counter is one of the eight CMU clock signals configurable in the channel control register ATOM[i]_CH[x]_CTRL . The register CM0 holds the duration of the period and the register CM1 holds the duration of the duty cycle in clock ticks of the selected CMU clock.

If counter register CN0 of channel x is reset by its own CCU0 unit (i.e. the compare match of

CN0 >= CM0 configured by RST_CCU0 = 0), the following statements are valid:

 The configuration of CM1 = 0 represents 0 % duty cycle at the output

 The configuration of CM1 >= CM0 represents 100 % duty cycle

 If both registers are configured to 0 ( CM0 = CM1 = 0), the output is 0 % duty cycle

 If CM0 = 0, 0 % duty cycle is generated independent of CM1

If the counter register CN0 of channel x is reset by the trigger signal coming from another channel or the assigned TIM module (configured by RST_CCU0 = 1), following statements are valid:



CM0 defines the edge to SL value, CM1 defines the edge to !SL value

 If CM0 = CM1 , the output is 100 % SL ( CM0 has higher priority)

 If CM0 = 0, the output stays at its last value ( CN0 stops counting)

In case the counter value CN0 reaches the compare value in register CM0 or the channel receives an external update trigger via the FUPD(x) signal, a synchronous update is performed. A synchronous update means that the registers CM0 and CM1 are updated with the content of the shadow registers SR0 and SR1 and the CLK_SRC register is updated with the value of the CLK_SRC_SR register.

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RM0361 ARU-connected Timer Output Module (ATOM)

The clock source for the counter can be changed synchronously at the end of a period. If

ARU access is disabled, this is done by using the bit field CLK_SRC_SR of register

ATOM[i]_CH[x]_CTRL as shadow registers for the next CMU clock source.

If ARU access is enabled, the bits ACBI(4), ACBI(3) and ACBI(2) received via ARU and stored in register ATOM_[i]_CH[x]_STAT are used as shadow register for the update of the

CMU clock source register CLK_SRC .

For the synchronous update mechanism the generation of a complex PWM output waveform is possible without CPU interaction by reloading the shadow registers SR0 , SR1 and the ACBI bit field over the ACI subunit from the ARU, while the ATOM channel operates on the CM0 and CM1 registers.

This internal update mechanism is established, when the old PWM period ends. The shadow registers are loaded into the operation registers, the counter register is reset, the new clock source according to the CLK_SRC_SR or ACBI(4), ACBI(3) and ACBI(2) bits is selected and the new PWM generation starts.

In parallel, the ATOM channel issues a read request to the ARU to reload the shadow registers with new values while the ATOM channel operates on the operation registers. To guarantee the reloading, the PWM period must not be smaller than the worst case ARU round trip time and source for the PWM characteristic must provide the new data within this time. Otherwise, the old PWM values are used from the shadow registers.

When updated over the ARU the user has to ensure that the new period duration is located in the lower (bits 23 to 0) and the duty cycle duration is located in the upper (bits 47 to 24)

ARU data word and the new clock source is specified in the ARU control bits 52 to 50.

This pipelined data stream character is shown in

Figure 52

Figure 52. ARU data input stream pipeline structure for SOMP mode

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When an ARU transfer is in progress which means the ARU_RREQ is served by the ARU, the ACI locks the update mechanism of CM0 , CM1 and CLK_SRC until the read request

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ARU-connected Timer Output Module (ATOM) RM0361 has finished. The CCU0 and CCU1 operate on the old values when the update mechanism is locked.

The shadow registers SR0 and SR1 can also be updated over the AEI bus interface. When updated via the AEI bus the CM0 and CM1 update mechanism has to be locked via the

AGC_GLB_CTRL register with the UPENx signal in the AGC subunit. To select the new clock source in this case, the CPU has to write to the CLK_SRC_SR bit field of the

ATOM[i]_CH[x]_CTRL register.

For an asynchronous update of the duty cycle and/or period the new values must be written directly into the compare registers CM0 and/or CM1 while the counter CN0 continues counting. This update can be done only via the AEI bus interface immediately by the CPU or by the FUPD(x) trigger signal triggered from the AGC global trigger logic. Values received through the ARU interface are never loaded asynchronously into the operation registers

CM0 and CM1 . Therefore, the ATOM channel can generate a PWM signal on the output port pin ATOM[i]_CH[x]_OUT on behalf of the content of the CM0 and CM1 registers, while it receives new PWM values via the ARU interface ACI in its shadow registers.

On a compare match of CN0 and CM0 or CM1 the output signal level of

ATOM[i]_CH[x]_OUT is toggled according to the signal level output bit SL in the

ATOM[i]_CH[x]_CTRL register.

Thus, the duty cycle output level can be changed during runtime by writing the new duty cycle level into the SL bit of the channel configuration register. The new signal level becomes active for the next trigger CCU_TRIGx (since bit SL is written).

Since the ATOM[i]_CH[x]_OUT signal level is defined as the reverse duty cycle output level when the ATOM channel is enabled, a PWM period can be shifted earlier by writing an initial offset value to CN0 register. By doing this, the ATOM channel first counts until CN0 reaches

CM0 and then it toggles the output signal at ATOM[i]_CH[x]_OUT .

12.3.3.1 SOMP one-shot mode

The ATOM channel can operate in One-shot mode when the OSM bit is set in the channel control register. One-shot mode means that a single pulse with the pulse level defined in bit

SL is generated on the output line.

First the channel has to be enabled by setting the corresponding ENDIS_STAT value.

In One-shot mode the counter CN0 will not be incremented once the channel is enabled.

A write access to the register CN0 triggers the start of pulse generation (i.e. the increment of the counter register CN0 ).

If the counter CN0 is reset from CM0 back to zero, the first edge at ATOM[i]_CH[x]_OUT is generated.

To avoid an update of CMx register with content of SRx register at this point in time, the automatic update should be disabled by setting UPEN_CTRL[x] = 00 (in register

ATOM[i]_CH[x]_CTRL )

The second edge is generated if CN0 is greater than or equal to CM1 (i.e. CN0 was incremented until it has reached CM1 or CN0 is greater than CM1 after an update of CM1 ).

If the counter CN0 has reached the value of CM0 a second time, the counter stops.

The new value of CN0 determines the start delay of the first edge. The delay time of the first edge is given by ( CM0-CN0 ) multiplied with period defined by current value of CLK_SRC .

Figure 53

clarifies the pulse generation in SOMP one-shot mode.

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Figure 53. PWM output with respect to configuration bit SL in one-shot mode: trigger by writing to CN0

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Further output of single pulses can be started by a write access to register CN0 .

If CN0 is already incrementing (i.e. started by writing to CN0 a value CN0start < CM0), the affect of a second write access to CN0 depends on the phase of CN0:

 phase 1: update of CN0 before CN0 reaches first time CM0

 phase 2: update of CN0 after CN0 has reached first time CM0 but is less than CM1

 phase 3: update of CN0 after CN0 has reached first time CM0 and CN0 is greater than or equal CM1

In phase 1: writing to counter CN0 a value CN0new < CM0 leads to a shift of first edge

(generated if CN0 reaches CM0 first time) by the time CM0-CN0new.

In phase 2: writing to incrementing counter CN0 a value CN0new < CM1 while CN0old is below CM1 leads to a lengthening of the pulse. The counter CN0 stops if it reaches CM0.

12.3.3.2 Register ATOM[i]_CH[x]_CTRL in SOMP mode (x: 0...7)

Address offset: see Appendix B Initial value: 0x0000_0x00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 0

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[23:25]

[21:22]

[17:19]

[12:14]

Table 149. ATOM[i]_CH[x]_CTRL in SOMP mode field description

Description

MODE : ATOM channel mode select.

10: ATOM Signal Output Mode PWM (SOMP)

Not used : Not used in this mode

ARU_EN

: ARU Input stream enable

0 = ARU Input stream disabled

1 = ARU Input stream enabled

ADL : ARU data select for SOMP.

00: Load both ARU words into shadow registers

01: Load ARU low word (Bits 23...0) into shadow register SR0

10: Load ARU high word (Bits 47...24) into shadow register SR1

11: Reserved

Note:

This bit field is only used in SOMP mode to select the ARU data source.

Not used

: Not used in this mode

Reserved

Note:

Read as zero, should be written as zero.

: Signal level for pulse of PWM.

0 = Low signal level

1 = High signal level

Note: Reset value depends on the hardware configuration chosen by silicon vendor.

If the output is disabled, the output ATOM_OUT[x] is set to inverse value of SL.

CLK_SRC_SR : Shadow register for CMU clock source register CLK_SRC

000: CMU_CLK0 selected

001: CMU_CLK1 selected

010: CMU_CLK2 selected

011: CMU_CLK3 selected

100: CMU_CLK4 selected

101: CMU_CLK5 selected

110: CMU_CLK6 selected

111: CMU_CLK7 selected

Note:

This register is a shadow register for the CMU_CLKx select. Thus, if the CMU_CLK source for PWM generation should be changed during operation, the old CMU_CLK has to operate until the update of the ATOM channels internal CLK_SRC register by the

CLK_SRC_SR content is done either by an end of a period or a FORCE_UPDATE.

Note: After (channel) reset the selected CLK_SRC value is the SYS_CLK (input of Global

Clock Divider). To use one of the CMU_CLKx, it is required to perform a forced update of CLK_SRC with the value of CLK_SRC_SR value before/with enabling the channel.

Note:

These bits are only applicable if ARU_EN = '0'.

Reserved

Note:

Read as zero, should be written as zero.

Not used

: Not used in this mode

Reserved

Note:

Read as zero, should be written as zero.

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Bit

Table 149. ATOM[i]_CH[x]_CTRL in SOMP mode field description (continued)

Description

[8:10]

[0:3]

RST_CCU0 : Reset source of CCU0

0 = Reset counter register CN0 to 0 on matching comparison with CM0

1 = Reset counter register CN0 to 0 on trigger TRIG_[x-1]

Note:

If RST_CCU0=1 and UPEN_CTRLx=1 are set, TRIG_[x-1] triggers also the update of work register (CM0, CM1 and CLK_SRC).

Not used

: Not used in this mode.

TRIGOUT : Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx.

0 = TRIG_[x] is TRIG_[x-1]

1 = TRIG_[x] is TRIG_CCU0

Reserved

Note: Read as zero, should be written as zero.

OSM

: One-shot mode

0 = Continuous PWM generation after channel enable

1 = A single pulse is generated

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

In ATOM Signal Output Mode Serial (SOMS) the ATOM channel acts as a serial output shift register where the content of the CM1 register in the CCU1 unit is shifted out whenever the unit is triggered by the selected CMU_CLK input clock signal. The shift direction is configurable with the ACB(0) bit inside the ATOM[i]_CH[x]_CTRL register when ARU is disabled and the ACBI(0) bit inside the ATOM[i]_CH[x]_STAT register when ARU is enabled.

The data inside the CM1 register has to be aligned according to the selected shift direction in the ACB(0)/ACBI(0) bit. This means that when a right shift is selected, that the data word has to be aligned to bit 0 of the CM1 register and when a left shift is selected, that the data has to be aligned to bit 23 of the CM1 register.

Figure 54. SOMS mode output generation

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Figure 54

shows the output generation in case of SOMS mode is selected.

In SOMS mode CCU0 runs in counter/compare mode and counts the number of bits shifted out so far. The total number of bits that should be shifted is defined as CM0 . The total number of bits that are visible at ATOM_OUT is CM0+1 .

When the output is disabled the ATOM_OUT is set to the inverse SL bit definition.

When the content of the CM1 register is shifted out, the inverse signal level is shifted into the CM1 register.

When the output is enabled while UPEN_CTRL[x] is disabled, the ATOM_OUT signal level is defined by CM1 bit 0 or 23, depending on the shift direction defined by ACB(0) or ACBI(0) register setting.

Figure 55

should clarify the ATOM channel start-up behavior in this case for right shift. For left shift the CM1

bit 0 in Figure 55 has to be replaced by

CM1 bit 23.

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Figure 55. SOMS output signal level at start-up, UPEN_CTRL[x] disabled

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If UPEN_CTRL[x] is set and the channel is enabled, the output level is defined by bit 0 or 23 of CM1

case.

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Figure 56. SOMS output signal level at start-up, UPEN_CTRL[x] enabled

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When the serial data to be shifted is provided via ARU the number of bits that should be shifted has to be defined in the lower 24 bits of the ARU word (23 to 0) and the data that is to be shifted has to be defined in the ARU bits 47 to 24 aligned according to the shift direction. This shift direction has to be defined in the ARU word bit 48 (SL0 bit).

If bit UPEN_CTRL[x] of a channel x is set, after update of CM0 / CM1 register with the content of the SR0 / SR1 register, a new ARU read request is set up.

If bit UPEN_CTRL[x] of a channel x is not set, no (further) ARU read request is set up

(because the SR0 / SR1 register is never used for update) and the ATOM may stop shifting after CN0 has reached CM0 . Note, that in this case also no automatic restart of shifting is possible.

If a channel is enabled with the settings SOMS mode and ARU_EN = 1, the first received values from ARU are stored in register SR0 and SR1.

If CN0 and CM0 are 0 (i.e. CN0 is not counting) and the update of channel x is enabled ( UPEN_CTRL[x] = 1), an immediate update of the register CM0 and CM1 is also done. This update of CM0 and CM1 triggers the start of shifting.

It is recommended to configure the ATOM channel in One-shot mode when the ARU_EN bit is not set, since the ATOM channel would reload new values from the shadow registers when CN0 reaches CM0 .

12.3.4.1 SOMS mode with ARU_EN = 1 and OSM = 0, UPEN_CTRL[x] = 1

In case of bit ARU_EN is set and bit OSM is not set, the channel is running in the SOMS continuous mode. Then, if the content of the CM0 register equals the counter CN0 , the CM0 and CM1 registers are reloaded with the SR0 and SR1 content and new values are requested from the ARU. If the update of the shadow registers does not happen before CN0 reaches CM0 the old values of SR0 and SR1 are used to reload the operation registers.

In contrast to controlling the channel via AEI, the shift direction defined by ARU word bit 48 has only effect after the update of CMx operation registers from the SRx registers.

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12.3.4.2 SOMS mode with ARU_EN = 1 and OSM = 1, UPEN_CTRL[x] = 1

In case of bit ARU_EN is set and bit OSM is set, the channel is running in the SOMS oneshot mode. Then, if the content of the CM0 register equals the counter CN0 and if new values are available in SR0 and SR1 (bit DV set), the CM0 and CM1 registers are reloaded with the SR0 and SR1 content and new values are requested from the ARU. If no new values are available in SR0 and SR1 , the register CM0 and CM1 will not be updated, the counter CN0 stops and the ATOM channel continues to request new data from ARU. A later reception of new ARU data in SR0 and SR1 will immediately force the update of the register

CM0 and CM1 and restart the counter CN0 .

12.3.4.3 SOMS mode with ARU_EN = 0 and OSM = 0, UPEN_CTRL[x] = 1

In case of bit ARU_EN is not set and bit OSM is not set, the ATOM channel updates its

CM0/CM1 register with the content of the SR0/SR1 register and restarts shifting immediately. The first bit of new CM1 register value will be applied at the output without any gap to the last bit of the previous CM1 register value.

12.3.4.4 SOMS mode with ARU_EN = 0 and OSM = 1, UPEN_CTRL[x] = 1:

In case of bit ARU_EN is not set and bit OSM is set, the ATOM channel stops shifting when

CN0 reaches CM0 and no update of CM0 and CM1 is performed.

Then, the shifting of the channel can be restarted again by writing a zero (0) to the CN0 register again. Please note, that the CN0 register should be written with a zero since the

CN0 register counts the number of bits shifted out by the ATOM channel.

The writing of a zero to CN0 causes also an immediate update of CM0 / CM1 register with the content of SR0 / SR1 register.

12.3.4.5 Interrupts in SOMS mode

In ATOM Signal Output Mode Serial only the interrupt CCU0TC

( ATOM[i]_CH[x]_IRQ_NOTIFY ) in case of CN0 >= CM0 is generated. The interrupt

CCU1TC has no meaning and is not generated.

12.3.4.6 Register ATOM[i]_CH[x]_CTRL in SOMS mode (x: 0...7)

Address offset: see Appendix B Initial value: 0x0000_0x00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0

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Table 150.

ATOM[i]_CH[x]_CTRL in SOMS mode

Description

MODE : ATOM channel mode select.

11: ATOM Signal Output Mode Serial (SOMS)

Not used : Not used in this mode

ARU_EN

: ARU Input stream enable

0 = ARU Input stream disabled

1 = ARU Input stream enabled

ACB0 : Shift direction for CM1 register

0 = Right shift of data is started from bit 0 of CM1

1 = Left shift of data is started from bit 23 of CM1

Note:

The data that has to be shifted out has to be aligned inside the CM1 register according to the defined shift direction.

Note:

This bit is only applicable if ARU_EN = '0'.

Note: If the direction (ACB0) is changed the output ATOM_OUT[x] switches immediately to the other 'first' bit of CM1 (bit 0 if ACB0 = 0, bit 23 if ACB0 = 1).

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

SL : Defines signal level when channel and output is disable

0 = High signal level

1 = Low signal level

Note:

Reset value depends on the hardware configuration chosen by silicon vendor.

Note:

If the output is disabled, the output ATOM_OUT[x] is set to inverse value of SL.

Note:

If the output is enabled, the output ATOM_OUT[x] is set to bit 0 or 23 of CM1 register.

Note: The inverse value of SL is shifted into the CM1 register.

Note: An enable or disable of the channel x has no effect on ATOM_OUT[x].

CLK_SRC : Shift frequency select for channel

000: CMU_CLK0 selected

001: CMU_CLK1 selected

010: CMU_CLK2 selected

011: CMU_CLK3 selected

100: CMU_CLK4 selected

101: CMU_CLK5 selected

110: CMU_CLK6 selected.

111: CMU_CLK7 selected

Note:

This register is a shadow register for the CMU_CLKx select. Thus, if the channel should operate on another CMU_CLK then CMU_CKL0 at the beginning, the different

CMU_CLK has to be specified inside this register and the CMU_CLK has to be configured with a FORCE_UPDATE in that case before the channel operation would start.

Reserved

Note:

Read as zero, should be written as zero.

Not used

: Not used in this mode

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Table 150.

ATOM[i]_CH[x]_CTRL in SOMS mode

(continued)

Description

Reserved

Note:

Read as zero, should be written as zero.

Not used : Not used in this mode

Not used

: Not used in this mode

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

OSM

: One-shot mode

0 = Continuous shifting is enabled

1 = Channel stops, after number of bits defined in CM0 is shifted out

Not used : Not used in this mode

Reserved

Note: Read as zero, should be written as zero.

12.4 ATOM interrupt signals

The following table describes ATOM interrupt signals.

Signal

CCU0TCx_IRQ

CCU1TCx_IRQ

Table 151. ATOM interrupt signals

Description

CCU0 trigger condition interrupt for channel x

CCU1 trigger condition interrupt for channel x

RM0361

12.5 ATOM register overview

Table 152. ATOM register Address offset and initial values

Register name

ATOM[i]_AGC_GLB_CTRL

ATOM[i]_AGC_ENDIS_CTRL

ATOM[i]_AGC_ENDIS_STAT

ATOM[i]_AGC_ACT_TB

ATOM[i]_AGC_OUTEN_CTRL

ATOM[i]_AGC_OUTEN_STAT

ATOM[i]_AGC_FUPD_CTRL

ATOM[i]_AGC_INT_TRIG

Description

AGC Global control register

AGC0 Enable/disable control register

AGC Enable/disable status register (represents status of

ATOM channels)

AGC Action time base register

AGC Output enable control register

AGC Output enable status register

AGC Force update control register

AGC Internal trigger control register

Details in section

12.6.1

12.6.2

12.6.3

12.6.4

12.6.5

12.6.6

12.6.7

12.6.8

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Table 152. ATOM register Address offset and initial values (continued)

Register name

ATOM[i]_CH[x]_CTRL

ATOM[i]_CH[x]_STAT

ATOM[i]_CH[x]_RDADDR

ATOM[i]_CH[x]_CN0

ATOM[i]_CH[x]_CM0

ATOM[i]_CH[x]_SR0

ATOM[i]_CH[x]_CM1

ATOM[i]_CH[x]_SR1

ATOM[i]_CH[x]_IRQ_NOTIFY

ATOM[i]_CH[x]_IRQ_EN

ATOM[i]_CH[x]_IRQ_FORCINT

ATOM[i]_CH[x]_IRQ_MODE

Description

Details in section

ATOM Channel x control register (x = 0…7)

ATOM Channel x status register (x = 0…7)

ATOM Channel x ARU read address register (x = 0...7)

ATOM Channel x CCU0 counter register (x = 0…7)

ATOM Channel x CCU0 compare register (x = 0…7)

ATOM Channel x CCU0 compare shadow register (x =

0…7)

12.6.9

12.6.10

12.6.11

12.6.12

12.6.13

12.6.14

ATOM Channel x CCU1 compare register (x = 0…7)

ATOM Channel x CCU1 compare shadow register (x =

0…7)

ATOM channel x interrupt notification register (x = 0…7)

12.6.15

12.6.16

IRQ mode configuration register (x = 0...7)

12.6.17

ATOM channel x interrupt enable register (x = 0…7)

12.6.18

ATOM channel x software interrupt generation (x = 0…7)

12.6.19

12.6.20

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12.6 ATOM register description

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:30]

A w

0 0 0 0 0 0 0 0

A w

Table 153. ATOM[i]_AGC_GLB_CTRL field description

Description

HOST_TRIG : trigger request signal (see AGC) to update the register ENDIS_STAT and

OUTEN_STAT

0 = no trigger request

1 = set trigger request

Note: this flag is reset automatically after triggering the update

Reserved

Note:

Read as zero, should be written as zero.

RST_CH0

: Software reset of channel 0

0 = No action

1 = Reset channel

Note: : This bit is cleared automatically after write by CPU. The channel registers are set to their reset values and channel operation is stopped immediately. The S-R Flip-Flop

SOUR is reset to '1'.

RST_CH1

: Software reset of channel 1

See bit 23.

RST_CH2

: Software reset of channel 2

See bit 8.

RST_CH3

: Software reset of channel 3

See bit 23.

RST_CH4

: Software reset of channel 4

See bit 23.

RST_CH5

: Software reset of channel 5

See bit 23.

RST_CH6

: Software reset of channel 6

See bit 23.

RST_CH7

: Software reset of channel 7

See bit 23.

A w

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[10:11]

[8:9]

[6:7]

[4:5]

[2:3]

[0:1]

Table 153. ATOM[i]_AGC_GLB_CTRL field description (continued)

Description

UPEN_CTRL0 : ATOM channel 0 enable update of register CM0, CM1 and CLK_SRC from

SR0, SR1 and CLK_SRC_SR.

Write of following double bit values is possible:

00 = don’t care, bits 1:0 will not be change

01 = update disabled: is read as 00 (see below)

10 = update enabled: is read as 11 (see below)

11 = don’t care, bits 1:0 will not be changed

Read of following double values means:

00 = channel disabled

11 = channel enabled

UPEN_CTRL1 : ATOM channel 1 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL2 : ATOM channel 2 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL3

: ATOM channel 3 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15].

UPEN_CTRL4

: ATOM channel 4 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL5

: ATOM channel 5 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL6

: ATOM channel 6 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

UPEN_CTRL7

: ATOM channel 7 enable update of register CM0, CM1 and CLK_SRC

See bits [14:15]

12.6.2 ATOM[i]_AGC_ENDIS_CTRL

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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Table 154. ATOM[i]_AGC_ENDIS_CTRL field description

Description

ENDIS_CTRL0 : ATOM channel 0 enable/disable update value.

If an ATOM channel is disabled, the counter

CN0

is stopped and the Flip-Flop

SOUR

is set to the inverse value of control bit SL. On an enable event, the counter CN0 starts counting from its current value.

Write of following double bit values is possible:

00 = don’t care, bits 1:0 of register ENDIS_STAT will not be changed on an update trigger

01 = disable channel on an update trigger

10 = enable channel on an update trigger

11 = don’t change bits 1:0 of this register

Note:

If the channel is disabled (ENDIS[0]=0) or the output is disabled (OUTEN[0]=0), the

ATOM channel 0 output ATOM_OUT[0] is the inverted value of bit SL.

ENDIS_CTRL1

: ATOM channel 1 enable/disable update value.

See bits [30:31]

ENDIS_CTRL2

: ATOM channel 2 enable/disable update value.

See bits [30:31]

ENDIS_CTRL3

: ATOM channel 3 enable/disable update value.

See bits [30:31]

ENDIS_CTRL4

: ATOM channel 4 enable/disable update value.

See bits [30:31]

ENDIS_CTRL5

: ATOM channel 5 enable/disable update value.

See bits [30:31]

ENDIS_CTRL6

: ATOM channel 6 enable/disable update value.

See bits [30:31]

ENDIS_CTRL7

: ATOM channel 7 enable/disable update value.

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

12.6.3 ATOM[i]_AGC_ENDIS_STAT

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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[24:25]

[22:23]

Table 155. ATOM[i]_AGC_ENDIS_STAT field description

Description

If an ATOM channel is disabled, the counter CN0 is stopped and the Flip-Flop SOUR is set to the inverse value of control bit SL. On an enable event, the counter

CN0

starts counting from its current value.

Write of following double bit values is possible:

00 = don't care, bits [30:31] will not be changed

01 = channel disabled: is read as 00 (see below)

10 = channel enabled: is read as 11 (see below)

11 = don't care, bits [30:31] will not be changed

Read of following double values means:

00 = channel disable

11 = channel enable

ENDIS_STAT1

: ATOM channel 1 enable/disable update value.

See bits [30:31]

ENDIS_STAT2

: ATOM channel 2 enable/disable update value.

See bits [30:31]

ENDIS_STAT3

: ATOM channel 3 enable/disable update value.

See bits 1:0

ENDIS_STAT4

: ATOM channel 4 enable/disable update value.

See bits [30:31]

ENDIS_STAT5

: ATOM channel 5 enable/disable update value.

See bits [30:31]

ENDIS_STAT6

: ATOM channel 6 enable/disable update value.

See bits [30:31]

ENDIS_STAT7

: ATOM channel 7 enable/disable update value.

See bits [30:31]

Reserved

Note: Read as zero, should be written as zero.

12.6.4 ATOM[i]_AGC_ACT_TB

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit ACT_TB

Mode

Initial value

00000

A w

0x00_0000

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Table 156. ATOM[i]_AGC_ACT_TB field description

Description

ACT_TB : specifies the signed compare value with selected signal TBU_TS[x], x=0...2. If selected TBU_TS[x] value is in the interval [

ACT_TB

-007FFFFFh,

ACT_TB

] the event is in the past and the trigger is generated immediately. Otherwise the event is in the future and the trigger is generated if selected TBU_TS[x] is equal to

ACT_TB

TB_TRIG : Set trigger request

0 = no trigger request

1 = set trigger request

Note:

This flag is reset automatically if the selected time base unit (TBU_TS0 or TBU_TS1 or

TBU_TS2 if present) has reached the value ACT_TB and the update of the register were triggered.

TBU_SEL : Selection of time base used for comparison

00 = TBU_TS0 selected

01 = TBU_TS1 selected

10 = TBU_TS2 selected

11 = same as 00

Note: The bit combination "10" is only applicable if the TBU of the device contains three time base channels. Otherwise, this bit combination is also reserved. Please refer to GTM

Architecture block diagram on page 3 to determine the number of channels for TBU of this device.

Reserved

Note:

Read as zero, should be written as zero.

12.6.5 ATOM[i]_AGC_OUTEN_CTRL

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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Bit

[30:31]

ARU-connected Timer Output Module (ATOM)

Table 157. ATOM[i]_AGC_OUTEN_CTRL field description

Description

OUTEN_CTRL0 : Output ATOM_OUT(0) enable/disable update value

Write of following double bit values is possible:

00 = don't care, bits [30:31] of register OUTEN_STAT will not be changed on an update trigger

01 = disable channel output on an update trigger

10 = enable channel output on an update trigger

11 = don't change bits [30:31] of this register

Note: If the channel is disabled (ENDIS[0]=0) or the output is disabled (OUTEN[0]=0), the TOM channel 0 output ATOM_OUT[0] is the inverted value of bit SL.

OUTEN_CTRL1 : Output ATOM_OUT(1) enable/disable update value.

See bits [30:31]

OUTEN_CTRL2 : Output ATOM_OUT(2) enable/disable update value.

See bits [30:31]

OUTEN_CTRL3 : Output ATOM_OUT(3) enable/disable update value.

See bits [30:31]

OUTEN_CTRL4

: Output ATOM_OUT(4) enable/disable update value.

See bits [30:31]

OUTEN_CTRL5

: Output ATOM_OUT(5) enable/disable update value.

See bits [30:31]

OUTEN_CTRL6

: Output ATOM_OUT(6) enable/disable update value.

See bits [30:31]

OUTEN_CTRL7

: Output ATOM_OUT(7) enable/disable update value.

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

12.6.6 ATOM[i]_AGC_OUTEN_STAT

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

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ARU-connected Timer Output Module (ATOM)

Bit

[30:31]

Table 158. ATOM[i]_AGC_OUTEN_STAT field description

Description

OUTEN_STAT0 : Control/status of output ATOM_OUT(0)

Write of following double bit values is possible:

00 = don't care, bits 1:0 will not be changed

01 = channel disabled: is read as 00 (see below)

10 = channel enabled: is read as 11 (see below)

11 = don't care, bits 1:0 will not be changed

Read of following double values means:

00 = channel disable

11 = channel enable

OUTEN_STAT1

: Control/status of output ATOM_OUT(1)

See bits [30:31]

OUTEN_STAT2

: Control/status of output ATOM_OUT(2)

See bits [30:31]

OUTEN_STAT3 : Control/status of output ATOM_OUT(3)

See bits [30:31]

OUTEN_STAT4 : Control/status of output ATOM_OUT(4)

See bits [30:31]

OUTEN_STAT5 : Control/status of output ATOM_OUT(5)

See bits [30:31]

OUTEN_STAT6 : Control/status of output ATOM_OUT(6)

See bits [30:31]

OUTEN_STAT7 : Control/status of output ATOM_OUT(7)

See bits [30:31]

Reserved

Note: Read as zero, should be written as zero.

RM0361

12.6.7 ATOM[i]_AGC_FUPD_CTRL

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Bit

[30:31]

[20:21]

[18:19]

[16:17]

[28:29]

[26:27]

[24:25]

[22:23]

[14:15]

[12:13]

[10:11]

ARU-connected Timer Output Module (ATOM)

Table 159. ATOM[i]_AGC_FUPD_CTRL field description

Description

FUPD_CTRL0 : Force update of ATOM channel 0 operation registers

Write of following double bit values is possible:

00 = don’t care, bits [30:31] will not be changed

01 = force update disabled: is read as 00 (see below)

10 = force update enabled: is read as 11 (see below)

11 = don’t care, bits [30:31] will not be changed

Read of following double values means:

00 = force update disabled

11 = force channel enabled

FUPD_CTRL1

: Force update of ATOM channel 1 operation registers

See bits [30:31]

FUPD_CTRL2

: Force update of ATOM channel 2 operation registers

See bits [30:31]

FUPD_CTRL3 : Force update of ATOM channel 3 operation registers

See bits [30:31]

FUPD_CTRL4 : Force update of ATOM channel 4 operation registers

See bits [30:31]

FUPD_CTRL5 : Force update of ATOM channel 5 operation registers

See bits [30:31]

FUPD_CTRL6 : Force update of ATOM channel 6 operation registers

See bits [30:31]

FUPD_CTRL7 : Force update of ATOM channel 7 operation registers

See bits [30:31]

RST_CH6 : Software reset of channel 6

See bit 23.

RST_CH7 : Software reset of channel 7

See bit 23.

RSTCN0_CH0 : Reset CN0 of channel 0 on force update event

Write of following double bit values is possible:

00 = don't care, bits [30:31] will not be changed

01 = CN0 is not reset on forced update: is read as 00 (see below)

10 = CN0 is reset on forced update: is read as 11 (see below)

11 = don't care, bits [30:31] will not be changed

Read of following double values means:

00 = CN0 is not reset on forced update

11 = CN0 is reset on forced update

RSTCN0_CH1 : Reset CN0 of channel 1 on force update event

See bits [14:15]

RSTCN0_CH2 : Reset CN0 of channel 2 on force update event

See bits [14:15]

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Bit

[8:9]

[6:7]

[4:5]

[2:3]

[0:1]

Table 159. ATOM[i]_AGC_FUPD_CTRL field description (continued)

Description

RSTCN0_CH3 : Reset CN0 of channel 3 on force update event

See bits [14:15]

RSTCN0_CH4 : Reset CN0 of channel 4 on force update event

See bits [14:15]

RSTCN0_CH5 : Reset CN0 of channel 5 on force update event

See bits [14:15]

RSTCN0_CH6 : Reset CN0 of channel 6 on force update event

See bits [14:15]

RSTCN0_CH7 : Reset CN0 of channel 7 on force update event

See bits [14:15]

RM0361

12.6.8 ATOM[i]_AGC_INT_TRIG

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[28:29]

[26:27]

[24:25]

[22:23]

0x0000

Table 160. ATOM[i]_AGC_INT_TRIG field description

Description

INT_TRIG0 : Select input signal TRIG_0 as a trigger source

Write of following double bit values is possible:

00 = don't care, bits [30:31] will not be changed

01 = internal trigger from channel 0 (TRIG_0) not used: is read as 00 (see below)

10 = internal trigger from channel 0 (TRIG_0) used: is read as 11 (see below)

11 = don't care, bits 1:0 will not be changed

Read of following double values means:

00 = internal trigger from channel 0 (TRIG_0) not used

11 = internal trigger from channel 0 (TRIG_0) used

INT_TRIG1

: Select input signal TRIG_1 as a trigger source

See bits [30:31]

INT_TRIG2

: Select input signal TRIG_2 as a trigger source

See bits [30:31]

INT_TRIG3

: Select input signal TRIG_3 as a trigger source

See bits [30:31]

INT_TRIG4

: Select input signal TRIG_4 as a trigger source

See bits [30:31]

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[18:19]

[16:17]

[0:15]

ARU-connected Timer Output Module (ATOM)

Table 160. ATOM[i]_AGC_INT_TRIG field description (continued)

Description

INT_TRIG5 : Select input signal TRIG_5 as a trigger source

See bits [30:31]

INT_TRIG6 : Select input signal TRIG_6 as a trigger source

See bits [30:31]

INT_TRIG7 : Select input signal TRIG_7 as a trigger source

See bits [30:31]

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0X00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[23:27]

0x0

0 0 0 0

0 0

W x 0 0

0 0

Table 161. ATOM[i]_CH[x]_CTRL field description

Description

MODE : ATOM channel mode select.

00: ATOM Signal Output Mode Immediate (SOMI)

01: ATOM Signal Output Mode Compare (SOMC)

10: ATOM Signal Output Mode PWM (SOMP)

11: ATOM Signal Output Mode Serial (SOMS)

TB12_SEL

: Select time base value TBU_TS1 or TBU_TS2.

0 = TBU_TS1 selected for comparison

1 = TBU_TS2 selected for comparison

Note: This bit is only applicable in SOMC mode.

ARU_EN

: ARU Input stream enable.

0 = ARU Input stream disabled

1 = ARU Input stream enabled

ACB : ATOM Mode control bits.

Note: These bits have different meaning in the different ATOM channel modes. Please refer to the mode description sections.

Note: These bits are only applicable when ARU_EN = '0'.

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[17:19]

[12:14]

RM0361

Table 161. ATOM[i]_CH[x]_CTRL field description (continued)

Description

CMP_CTRL : CCUx compare strategy select.

0 = Greater/equal compare against TBU time base values (TBU_TSx >= CMx)

1 = Less/equal compare against TBU time base values (TBU_TSx <= CMx)

Note:

This bit is only applicable in SOMC mode

Reserved

Note:

Read as zero, should be written as zero.

SL : Initial signal level.

0 = Low signal level

1 = High signal level

Note:

Reset value depends on the hardware configuration chosen by silicon vendor.

Note: If the output is disabled, the output ATOM_OUT[x] is set to inverse SL independent of the ATOM channel mode.

Note: In SOMP, SOMI, SOMS mode, if the channel is disabled, the internal register SOUR inside ATOM sub unit SOU is set to inverse value of SL. By enabling the channel the register SOUR is not changed. Thus, if the output is enabled afterwards, the output

ATOM_OUT[x] is the inverse value of SL.

Note: In SOMC mode, if the channel is disabled, the internal register SOUR inside ATOM sub unit SOU is set to value of SL. By enabling the channel the register SOUR is not changed. Thus, if the output is enabled and the channel is disabled, the output

ATOM_OUT[x] is the value of SL.

Note:

In SOMS mode, this bit is only applicable when the channel and its output are disabled.

CLK_SRC

CLK_SRC_SR

: actual CMU clock source (SOMS)/ shadow register for CMU clock source (SOMP).

000: CMU_CLK0 selected

001: CMU_CLK1 selected

010: CMU_CLK2 selected

011: CMU_CLK3 selected

100: CMU_CLK4 selected

101: CMU_CLK5 selected

110: CMU_CLK6 selected

111: CMU_CLK7 selected

Note: This register is a shadow register for the CMU_CLKx select. Thus, if the CMU_CLK source for PWM generation should be changed during operation, the old CMU_CLK has to operate until the update of the ATOM channels internal CLK_SRC register by the

CLK_SRC_SR content is done either by an end of a period or a FORCE_UPDATE.

Note:

After (channel) reset the selected CLK_SRC value is the SYS_CLK (input of Global

Clock Divider). To use in SOMP mode one of the CMU_CLKx, it is required to perform a forced update of CLK_SRC with the value of CLK_SRC_SR value before/with enabling the channel.

Reserved

Note: Read as zero, should be written as zero.

WR_REQ : CPU Write request bit for late compare register update.

Note: This bit is only applicable in SOMC mode.

Reserved

Note: Read as zero, should be written as zero.

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[0:3]

ARU-connected Timer Output Module (ATOM)

Table 161. ATOM[i]_CH[x]_CTRL field description (continued)

Description

RST_CCU0 : Reset source of CCU0

0 = Reset counter register CN0 to 0 on matching comparison with CM0

1 = Reset counter register CN0 to 0 on trigger TRIG_[x-1]

Note:

If RST_CCU0=1 and UPEN_CTRLx=1 are set, TRIG_[x-1] triggers also the update of work register ( CM0 , CM1 and CLK_SRC ).

Note:

This bit is only applicable in SOMP mode.

Reserved

Note:

Read as zero, should be written as zero.

TRIGOUT : Trigger output selection (output signal TRIG_CHx) of module ATOM_CHx.

0 = TRIG_[x[ is TRIG_[x-1]

1 = TRIG_[x] is TRIG_CCU0

SLA

: Serve last ARU communication strategy

0 = Capture SRx time stamps after CCU0 match event not provided to ARU

1 = Capture SRx time stamps after CCU0 match event provided to ARU

Note:

This bit is only applicable in SOMC mode.

Note:

Please note, that setting of this bit has only effect, when ACBI(4:2) is configured for serve last compare strategy (“100”, “101”, or “110”).

Note:

When this bit is not set, the captured time stamps in the shadow registers SRx are only provided after the CCU1 match occurred. The ACBO(4:3) bits always return "10" in that case.

Note:

By setting this bit, the ATOM channel also provides the captured time stamps after the

CCU0 match event to the ARU. The ACBO(4:3) bits are set to “01” in that case. After the

OSM : One-shot mode

0 = Continuous PWM generation after channel enable

1 = A single pulse is generated

Note: this bit is only applicable in SOMP and SOMS modes.

ABM

: ARU blocking mode

0 = ARU blocking mode disabled: ATOM reads continuously from ARU and updates CM0,

CM1 independent of pending compare match event

1 = ARU blocking mode enabled: after updating CM0,CM1 via ARU, no new data is read from

ARU until compare match event is occurred.

Note:

This bit is only applicable in SOMC mode.

Reserved

: Read as zero, should be written as zero

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

C w

0 0 0

0x00

Bit

[16:30]

[11:15]

[3:7]

[0:2]

Table 162. ATOM[i]_CH[x]_STAT field description

Description

OL : Actual output signal level of ATOM_CHx_OUT.

0 = Actual output signal level is low

1 = Actual output signal level is high

Note:

Reset value is the inverted value of bit SL which depends on the hardware configuration chosen by silicon vendor.

Reserved

Note: Read as zero, should be written as zero.

ACBI : ATOM Mode control bits received through ARU.

Note: This register serves as a mirror for the five ARU control bits received through the ARU interface. The bits are valid, when the DV bit is set..

DV : Valid ARU Data stored in compare registers.

0 = No valid data was received by ARU

1 = Valid data received by ARU and stored in CM0 and/or CM1

Note:

This bit is only applicable in SOMC mode. The CPU can determine the status of the ARU transfers with this bit. After the compare event occurred, the bit is reset by hardware.

WRF : Write request of CPU failed for late update.

0 = Late update was successful, CCUx units wait for comparison.

1 = Late update failed.

The bit WRF can be reset by writing a 1 to it.

Note:

This bit is only applicable in SOMC mode.

Reserved

Note:

Read as zero, should be written as zero.

ACBO

: ATOM Internal status bits.

ACBO[3] = 1: CCU0 Compare match occurred

ACBO[4] = 1: CCU1 Compare match occurred

Note: These bits are only set in SOMC mode.

Note: ACBO is reset to 0b00000 on an update of register CM0 or CM1 (via ARU or CPU)

Note:

In SOMC mode these bits are sent as ARU control bits 52...48

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x01FE_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[23:31]

[16:22]

[7:15]

[0:6]

0x00

RPw

0x1FE

0x00

RPw

0x1FE

Table 163. ATOM[i]_CH[x]_RDADDR field description

Description

RDADDR0 : ARU Read address 0.

Note:

This read address is used by the ATOM channel to receive data from ARU immediately after the channel and ARU access is enabled (see ATOM[i]_CH[x]_CTRL register for details).

Note: This bit field is only writable if channel is disabled.

Reserved

Note: Read as zero, should be written as zero.

RDADDR1 : ARU Read address 1.

Note: The ATOM channel switches to this read address, when requested in the ARU control bits 52 to 48 with the pattern "111--". The channel switches back to the RDADDR0 after one ARU data package was received on RDADDR1.

Note: This read address is only applicable in SOMC mode.

Note: This bit field is only writable if channel is disabled.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved CN0 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 164. ATOM[i]_CH[x]_CN0 field description

Description

CN0

: ATOM CCU0 counter register.

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

CM0

0x000000

Bit

[8:31]

[0:7]

Table 165. ATOM[i]_CH[x]_CM0 field description

Description

CM0

: ATOM CCU0 compare register.

Reserved

Note:

Read as zero, should be written as zero.

Note: This register is write protected in SOMC mode and returns AEI_STATUS='10' on write access, when in serve last compare strategy the first match of CCU0 occurred

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

SR0

0x000000

Bit

[8:31]

[0:7]

Table 166. ATOM[i]_CH[x]_SR0 field description

Description

SR0

: ATOM channel x shadow register SR0.

Note: The SR0 register is used as shadow register for CM0 in SOMP and SOMS modes and is used as capture register for time base TBU_TS0 in SOMC mode.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

CM1

0x000000

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[8:31]

[0:7]

ARU-connected Timer Output Module (ATOM)

Table 167. ATOM[i]_CH[x]_CM1 field description

Description

CM1 : ATOM CCU1 compare register.

Reserved

Note: Read as zero, should be written as zero.

Note:

This register is write protected in SOMC mode and returns AEI_STATUS='10' on write access, when in serve last compare strategy the first match of CCU0 occurred.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved SR1 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 168. ATOM[i]_CH[x]_SR1 field description

Description

SR1 : ATOM channel x shadow register SR0.

Note:

The SR1 register is used as shadow register for

CM1

in SOMP and SOMS modes and is used as capture register for time base TBU_TS1 or TBU_TS2 (when selected in

ATOM[i]_CH[x]_CTRL register) in SOMC mode.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000000

C w

0 0

C w

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Table 169. ATOM[i]_CH[x]_IRQ_NOTIFY field description

Description

CCU0TC : CCU0 Trigger condition interrupt for channel x.

0 = No interrupt occurred.

1 = CCU0 Trigger condition interrupt was raised by ATOM channel x.

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

CCU1TC

: CCU1 Trigger condition interrupt for channel x.

See bit 31.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

0 0

Mode

Initial value

Bit

[0:29]

0x0000000

Table 170. ATOM[i]_CH[x]_IRQ_EN field description

Description

CCU0TC_IRQ_EN

: ATOM_CCU0TC_IRQ interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP.

1 = Enable interrupt, interrupt is visible outside GTM-IP.

CCU1TC_IRQ_EN

: ATOM_CCU1TC_IRQ interrupt enable.

See bit 31.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:29]

0x0000000

Table 171. ATOM[i]_CH[x]_IRQ_FORCINT field description

Description

TRG_CCU0TC

: Trigger ATOM_CCU0TC_IRQ interrupt by software.

0 = No interrupt triggering.

1 = Assert CCU0TC_IRQ interrupt for one clock cycle.

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_CCU1TC : Trigger ATOM_CCU1TC_IRQ interrupt by software

0 = No interrupt triggering.

1 = Assert CCU1TC_IRQ interrupt for one clock cycle.

Note:

This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

Reserved

Note:

Read as zero, should be written as zero.

A w

0 0

A w

Address offset: see Appendix B Initial value: 0x0000_000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x00000000

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[30:31]

[0:29]

Table 172. ATOM[i]_CH[x]_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note:

Read as zero, should be written as zero.

RM0361

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13 Multi Channel Sequencer (MCS)

Multi Channel Sequencer (MCS)

13.1 Overview

The Multi Channel Sequencer (MCS) submodule is a generic data processing module that is connected to the ARU. One of its major applications is to calculate complex output sequences that may depend on the time base values of the TBU and are processed in combination with the ATOM sub module. Other applications can use the MCS sub module to perform extended data processing of input data resulting from the TIM sub module.

Moreover, some applications may process data provided by the CPU within the MCS sub module, and the calculated results are sent to the outputs using the ATOM sub modules.

13.1.1 Architecture

Figure 57

gives an overview of the MCS architecture.

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Multi Channel Sequencer (MCS)

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The MCS sub module mainly embeds a single data path with five pipeline stages, consisting of a simple 24-bit Arithmetic Logic Unit (ALU), several decoders, and a connection to two

RAM pages located outside of the MCS sub module.

The data path of the MCS is shared by eight so called MCS-channels, whereas each MCSchannel executes a dedicated micro-program that is stored inside the RAM pages connected to the MCS sub module. The execution of the different MCS-channels is controlled by a central task scheduler.

Both RAM pages may contain arbitrary sized code and data sections that are accessible by all MCS-channels and the CPU via AEI. The addresses for accessing the RAM pages via

AEI can be found in

Section 22.3: References

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The MCS sub module supports a memory layout of up to 2 12 memory locations each 32 bit wide leading to a maximum byte wise address range from 0 to 2 14 -1.

This address space of the MCS is divided into two seamless memory pages.

Memory page 0 begins from address 0 and ranges to address MP0-4 and memory page 1 ranges from MP0 to MP1-4.

The parameters MP0 and MP1 are defined externally by the memory configuration sub

module MCFG of Chapter 14: Memory Configuration (MCFG) .

Depending on the silicon vendor configuration, the connected RAM pages are initialized with zeros in the case of an MCS module reset.

If an ECC Error occurs while an MCS-channel reads data from a memory module, the corresponding MCS-channel is disabled and the ERR bit in register STA is raised.

An MCS-channel can also be considered as an individual task of a processor that is scheduled at a specific point in time.

A more detailed description of the scheduling can be found in

Section 13.1.2: Scheduling

Moreover, each MCS-channel has a dedicated ARU interface for communication with other

ARU connected modules, an Instruction Register (IR), a Program Counter Register (PC), a

Status Register (STA), an ARU Control Bit Register (ACB), a Memory High Byte Register

(MHB) and a Register Bank with eight 24-bit general purpose registers (R0, R1,...R7).

All the registers, mentioned above, are only visible within its dedicated MCS-channel and thus the MCS-channels cannot exchange data using registers.

An exception is the common 16-bit wide trigger register that can be accessed by all MCS channels in order to trigger other MCS-channels located in the same sub module. STRG is used to set bits and CTRG is used to clear bits in the trigger register.

To enable triggering of MCS-channels by CPU, it can set bits in the common trigger register by writing to MCS[i]_STRG and clear bits by writing to MCS[i]_CTRG .

Whenever data has to be exchanged between different MCS-channels, the connected RAM pages, which are accessible by all MCS-channels, must be used.

However, since the data registers are writable by the Host CPU, an MCS channel may also exchange data with the CPU using its data registers.

The main actions of the different pipeline stages are as follows.

Pipeline stage 0 performs a setup of address, input data, and control signals for the next

RAM access of a specific MCS-channel.

The actual RAM access of a specific MCS-channel is executed in pipeline stage 1 and 2, assuming an external connection of a synchronous RAM with a latency of one clock cycle.

The RAM priority decoder arbitrates RAM accesses that are requested by the CPU via AEI and by the active MCS-channel. If both, CPU and an MCS-channel request a memory access to the same memory module the MCS-channel is prioritized.

Pipeline stage 3 performs pre-decoding of instruction and data resulting from the RAM.

Finally, in pipeline stage 4 the current instruction is executed.

Since the internal registers of the MCS can be updated by different sources (MCS write access, AEI write access, ARU read access) a write conflict occurs if more than one source

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However, the software should setup its application in a way that such conflicts do not occur.

One exception is the common trigger register which may be written by multiple sources

(different MCS channels and AEI) in order to enable fast triggering of different MCS channels. Typically, the software should setup its application in a manner that different sources should not write the same bits in the trigger register.

13.1.2 Scheduling

The MCS sub module provides two different scheduling schemes: round-robin schedule and accelerated schedule .

The scheduling scheme can be selected by the SCHED bit field in the global MCS[i]_CTRL register.

The round-robin order scheduling assigns all MCS-channels an equal amount of time slices.

In addition, the scheduler also assigns one time slice to the CPU, in order to guarantee at least one memory access by the CPU within each round-trip cycle.

Figure 58

shows the round-robin scheduling with 8 MCS-channels (C

0 scheduled together with a single CPU access.

to C

) that are

13.1.2.1 Scheduling

Figure 58. Scheduling

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& W & W & W &38W & W & W & W

& W & W

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& W &38W & W & W

& W & W

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The figure also shows which MCS-channel is activated in specific pipeline stage at a specific point in time.

The execution time of an MCS-channel in a specific pipeline stage is always one clock cycle.

The index t marks all instruction parts of the corresponding MCS-channels belonging to the same round-trip cycle.

Consequently, a single cycle instruction of an MCS-channel requires an effective execution time of 9 clock cycles, ignoring the five clock cycles of pipeline latency.

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To improve memory bandwidth between CPU and MCS memory, the time slices of any suspended MCS-channel is also granted to the CPU.

An MCS-channel can be suspended due to the following reasons:

 An MCS-channel is executing a blocking read or write request to an ARU connected sub module (instruction ARD, AWR, ARDI, AWRI)

 An MCS-channel waits on a register match event (instruction WURM), in order to wait on a desired register value (e.g. trigger event from another MCS channel)

 An MCS-channel is disabled

The round-robin scheduling leads to a deterministic round trip time for the whole sub module, however it may waste clock cycles by scheduling MCS-channels that are not able to run at a specific point in time assuming that there is no high CPU bandwidth required.

The second scheduling mode, the accelerated scheduling mode , improves the computational performance of the MCS by skipping suspended MCS-channels (and channels that are currently in stage 0, 1, 2, or 3) during scheduling.

Whenever the scheduler detects an MCS-channel that is suspended or not in the last pipeline stage, it is selecting another non-suspended MCS-channel.

Considering the timing of Figure 58 in conjunction with the accelerated scheduling scheme,

a single cycle instruction of an MCS-channel requires an effective execution time between 5 and 9 clock cycles, depending on the number of suspended MCS-channels.

In summary, the round-robin scheduling mode grants time slices of suspended MCSchannels to the CPU and the accelerated scheduling mode grants time slices of suspended

MCS-channels to non-suspended MCS-channels.

This section describes the entire instruction set of the MCS sub module.

After the introduction of the different instruction formats in Section 13.2.1: Instruction format

the individual instructions are described in Section 13.2.2.1: MOVL instruction

Section 13.2.7: Other instructions .

In general, each instruction is 32 bit wide but the duration of each instruction varies between several instruction cycles . An instruction cycle is defined as the time in system clock cycles that rest between two consecutive instructions of a channel.

As already described in

Section 13.2.1: Instruction format , the number of required clock

cycles for a single instruction cycle can vary in the range of 5 to 9 clock cycles, depending on the number suspended MCS-channels, when the accelerated scheduling scheme is selected inside the MCS[i]_CTRL register. In the round robin scheduling scheme, each single cycle instruction takes exactly 9 clock cycles.

Before the instruction formats and the actual instructions are described, some commonly used terms, abbreviations and expressions are introduced:

OREG : The operation register set OREG = {R0, R1, R2,..., R7, STA, ACB, CTRG, STRG,

TBU_TS0, TBU_TS1, TBU_TS2, MHB} includes all MCS accessible internal registers, as well as the global time bases TBU_TS0, TBU_TS1, and TBU_TS2 that are provided by the sub module TBU.

AREG : The ARU register set AREG = {R0, R1, R2,..., R7, ZERO} includes the all registers that can be written by incoming ARU transfers (ARD, ARDI, NARD, and NARDI

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LIT4 : The set LIT4 = {0,1,...,15} is an unsigned 4-bit literal.

LIT16 : The set LIT16 = {0,1,...,2 16 -1} is an unsigned 16-bit literal.

LIT24 : The set LIT24 = {0,1,..., 2 24 -1} is an unsigned 24-bit literal.

BIT SELECTION : The expression VAR[i] represents the i-th bit of a variable VAR.

BIT RANGE SELECTION : The expression VAR[m:n] represents the bit slice of variable

VAR that is ranging from bit n to bit m.

MEMORY ADRESSING : The expression MEM(X) represents the 32-bit value at address X of the memory.

Address X ranges between 0 and 2 14 -4, whereas X must be an integral multiple of 4.

The expression MEM(X)[m:n] represents the bit slice ranging from bit n to m of the 32-bit word at memory location X.

ARU ADRESSING : In the case of ARU reading, the expression ARU(X) represents the 

53-bit ARU word of ARU channel at address X.

The read address X ranges between 0 and 2 9 -1.

In the case of ARU writing, the expression ARU(X) represents a 53-bit ARU word that is written to an ARU channel indexed by the index X.

The index X selects a single ARU write channel from the pool of the MCS sub module's allocated ARU write channels.

An MCS sub module has 24 ARU write channels, indexed by values 0 to 23.

The expression ARU(X)[m:n] represents the bit slice ranging from bit n to m of the 53-bit

ARU word.

The first instruction format, called literal instruction format, embeds a primary 4-bit opcode

OPC0, a 24-bit literal value C  LIT24, and a 4-bit value A, which may be an element of set

OREG or AREG, depending on the actual instruction.

Figure 59

shows the bit alignment of the literal instruction format.

13.2.1.1 Literal instruction format

Figure 59. Literal instruction format

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The literal instruction format is primarily used for instructions that are accessing a 24 bit literal and a single 24 bit register as operands.

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In the following subsections the binary codes of a 24-bit literal instruction is defined as

"xxxxaaaacccccccccccccccccccccccc", whereas the digits 'x' encode the field OPC0, the digits 'a' encode the operand field A, and the digits 'c' encode the 24-bit literal field C.

If an instruction ignores several bits of field, the bits are defined as '-' in its code.

The second instruction format, called double operand instruction format, embeds a 4 bit primary opcode OPC0, a 4-bit secondary opcode OPC1, a 16-bit literal C  LIT16 and two

4-bit values A and B, which may be an element of set OREG, AREG, or LIT4 depending on the actual instruction.

Figure 60

shows the bit alignment of the double operand instruction format.

13.2.1.2 Double operand instruction format

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Figure 60. Double operand instruction format

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The double operand instruction format is primarily used for instructions that are accessing two operands stored in the 24-bit registers.

In the following subsections the binary codes of a 16-bit literal instruction is defined as

"xxxxaaaabbbbyyyycccccccccccccccc", whereas the digits 'x' encode the bit field OPC0, 'y' the digits of field OPC2, the digits 'a' encode the operand field A, the digits 'b' the operand field B, and the digits 'c' encode the 16-bit literal field C.

If an instruction ignores several bits of field, the bits are defined as '-' in its code.

If the instruction decoder detects an invalid combination of the fields opcode OPC0 and

OPC1, the corresponding MCS-channel is disabled and the ERR bit in the register STA is set.

13.2.2 Data transfer instructions

Syntax : MOVL A, C

Operation : A  C

Status : Z

Duration : 1 instruction cycle

Code : 0001aaaacccccccccccccccccccccccc

Description : Transfer literal value C (C  LIT24) to register A (A  OREG).

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

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Syntax : MOV A, B

Operation : A  B

Status : Z

Duration : 1 instruction cycle

Code : 1010aaaabbbb0000----------------

Description : Transfer value B (B  OREG) to register A (A  OREG).

The zero bit Z of status register STA is set, if the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : MRD A, C

Operation : A  MEM(C[13:0])[23:0];

MHB  MEM(C[13:0])[31:24]

Status : Z

Duration : 2 instruction cycles

Code : 1010aaaa----0001--cccccccccccccc

Description : Transfer the lower 24 bits of memory content at address C (C  LIT16) to register A (A  OREG).

The upper 8 bits of the memory content at address C are transferred to MHB register.

The zero bit Z of status register STA is set, if the lower 24 bits of the transferred value are zero, otherwise the zero bit is cleared.

If the MHB register is selected as destination register A (A  OREG), the bits 0 to 7 of the referred memory location are transferred to MHB.

The program counter PC is incremented by the value 4.

Syntax : MWR A, C

Operation : MEM(C[13:0])[23:0]  A;

MEM(C[13:0])[31:24]  MHB

Status : -

Duration : 2 instruction cycles

Code : 1010aaaa----0010--cccccccccccccc

Description : Transfer 24 bit value of register A (A  OREG) together with the MHB register to the memory location at address C (C  LIT16).

The 24 bit value of register A is stored in the lower significant bits (bit 0 to 23) of the memory location.

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The MHB register is stored in bits 24 to 31 of the referred memory location.

The program counter PC is incremented by the value 4.

Syntax : MWR24 A, C

Operation : MEM(C[13:0])[23:0]  A

Status : -

Duration : 3 instruction cycles

Code : 1010aaaa----0111--cccccccccccccc

Description : Transfer 24 bit value of register A (A  OREG) to memory at address C (C 

LIT16).

The 24 bit value of register A is stored in the lower significant bits (bit 0 to 23) of the memory location and the bits 24 to 31 are left unchanged.

The program counter PC is incremented by the value 4.

It should be noted that this operation is not an atomic instruction.

Syntax : MRDI A, B

Operation : A  MEM(B[13:0])[23:0]

MHB  MEM(B[13:0])[31:24]

Status : Z

Duration : 2 instruction cycles

Code : 1010aaaabbbb0011----------------

Description : Transfer the lower 24 bits of a memory location to register A (A  OREG) using indirect addressing.

The upper 8 bits of the memory location are transferred to MHB register.

The memory location where to read from is defined by the bits 0 to 13 of register B (B 

OREG).

The 24 bit value is received from the lower significant bits (bit 0 to 23) of the memory location.

The zero bit Z of status register STA is set, if the lower 24 bit of the transferred value is zero, otherwise the zero bit is cleared.

If the MHB register is selected as destination register A (A  OREG), the bits 0 to 7 of the referred memory location are transferred to MHB.

The program counter PC is incremented by the value 4.

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Syntax : MWRI A, B

Operation : MEM(B[13:0])[23:0]  A;

MEM(B[13:0])[31:24]  MHB

Status : -

Duration : 2 instruction cycles

Code : 1010aaaabbbb0100----------------

Description : Transfer 24 bit value of register A (A  OREG) to the 24 least significant bits of to the memory using indirect addressing.

The memory location where to write to is defined by the bits 0 to 13 of register B (B 

OREG).

The 24 bit value is stored in the lower significant bits (bit 0 to 23) of the memory location and the MHB register is stored in bits 24 to 31.

The program counter PC is incremented by the value 4.

Syntax : MWRI24 A, B

Operation : MEM(B[13:0])[23:0]  A;

Status : -

Duration : 3 instruction cycles

Code : 1010aaaabbbb1000----------------

Description : Transfer 24 bit value of A (A  OREG) to memory using indirect addressing.

The memory location where to write to is defined by the bits 0 to 15 of register B (B 

OREG).

The 24 bit value is stored in the lower significant bits (bit 0 to 23) of the memory location and the bits 24 to 31 are left unchanged.

The program counter PC is incremented by the value 4.

It should be noted that this operation is not an atomic instruction.

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Syntax : POP A

Operation : A  MEM(R7[13:0])[23:0];

R7  R7 - 4;

SP_CNT  SP_CNT - 1

MHB  MEM(R7[13:0])[31:24];

Status : Z, EN

Duration : 2 instruction cycles

Code : 1010aaaa----0101----------------

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Description : Transfer the lower significant bits (bit 0 to 23) from the top of stack to register

A (A  OREG), followed by decrementing the stack pointer register R7 with the value 4.

The upper 8 bits (bit 24 to 31) from the top of the stack are transferred to register MHB.

If the MHB register is selected as destination register A (A  OREG), the bits 0 to 7 from the top of the stack are transferred to MHB.

The memory location for the top of the stack is identified by the bits 0 to 13 of the stack pointer register R7.

The zero bit Z of status register STA is set, if the lower 24 bit of the transferred value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is decremented.

If an underflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an underflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the current MCS-channel is disabled by clearing the EN bit of STA .

Syntax : PUSH A

Operation : R7  R7 + 4;

SP_CNT  SP_CNT + 1;

MEM(R7[13:0])[23:0]  A;

MEM(R7[13:0])[31:24]  MHB

Status : EN

Duration : 2 instruction cycles

Code : 1010aaaa----0110----------------

Description : Increment the stack pointer register R7 with the value 4, followed by transferring a 24 bit value of operand A (A  OREG) together with a MHB register to the new top of the stack. The 24 bit value of A is stored in the bits 0 to 23 of the memory location.

The content of the MHB register is stored in the bit 24 to 31 of the memory location.

The memory location for the top of the stack is addressed by the bits 0 to 13 of the stack pointer register.

The program counter PC is incremented by the value 4.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is incremented.

If an overflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the current MCS-channel is disabled by clearing the EN bit of STA .

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the memory write operation for the A and MHB is discarded.

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Syntax : ARD A, B, C

Operation : A  ARU(C[8:0])[23:0];

B  ARU(C[8:0])[47:24];

ACB[4:0]  ARU(C[8:0])[52:48]

Status : CAT

Duration : suspends current MCS-channel

Code : 1011aaaabbbb0000-------ccccccccc

Description : Perform a blocking read access to the ARU and transfer both 24 bit values received at the ARU port to the registers A and B (A  AREG, B  AREG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

If A and B refer to the same register, only the upper 24 bit ARU word is stored and the lower

24 bit ARU word is discard.

If any transferred 24 bit value from the ARU should not stored in a register, the dummy register ZERO  AREG can be selected in A or B to discard the corresponding ARU data.

Actually, all address values of A and B that exceed the range 0 to 7 discard the corresponding ARU data.

The received ARU control bits are stored in the register ACB.

The lower significant bits of the literal C (C  LIT16) define the ARU address where to read from.

At the beginning of the instruction execution the CAT bit in the register STA is always cleared. After the execution of the instruction the CAT bit is updated in order to show if the instruction finished successfully (CAT = 0) or it was canceled by the CPU (CAT = 1).

The program counter PC is incremented by the value 4.

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Syntax : ARDI A, B

Operation : A  ARU(R6[8:0])[23:0];

B  ARU(R6[8:0])[47:24];

ACB[4:0]  ARU(R6[8:0])[52:48]

Status : CAT

Duration : suspends current MCS-channel

Code : 1011aaaabbbb0100----------------

If A and B refer to the same register, only the upper 24 bit ARU word is stored and the lower

24 bit ARU word is discarded.

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If any transferred 24 bit value from the ARU should not stored in a register, the dummy register ZERO  AREG can be selected in A or B to discard the corresponding ARU data.

Actually, all address values of A and B that exceed the range 0 to 7 discard the corresponding ARU data.

The received ARU control bits are stored in the register ACB.

The read address is obtained from the bits 0 to 8 of the channels register R6.

The program counter PC is incremented by the value 4.

Syntax : AWR A, B, C

Operation : ARU(C[4:0])[23:0]  A;

ARU(C[4:0])[47:24]  B;

ARU(C[4:0])[52:48]  ACB[4:0];

Status : CAT

Duration : suspends current MCS-channel

Code : 1011aaaabbbb0001-----------ccccc

Description : Perform a blocking write access to the ARU and transfer two 24 bit values to the ARU port using the registers A and B (A  OREG, B  OREG), whereas A holds the lower 24 bit ARU word and B holds the upper 24 bit ARU word.

The ARU control bits to be sent are taken from the register ACB.

The lower significant bits (bit 0 to bit 4) of the literal C (C  LIT16) define an index into the pool of ARU write address that is used for writing data.

Each MCS sub module has a pool of several write addresses that can be shared between all MCS-channels arbitrarily.

The program counter PC is incremented by the value 4.

Syntax : AWRI A, B

Operation : ARU(R6[4:0])[23:0]  A;

ARU(R6[4:0])[47:24]  B;

ARU(R6[4:0])[52:48]  ACB[4:0];

Status : CAT

Duration : suspends current MCS-channel

Code : 1011aaaabbbb0101----------------

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The ARU control bits to be sent are taken from the register ACB.

The bits 0 to 4 of the register R6 define an index into the pool of ARU write address that is used for writing data.

Each MCS sub module has a pool of several write addresses that can be shared between all MCS-channels arbitrarily.

The program counter PC is incremented by the value 4.

Syntax : NARD A, B, C

Operation : A  ARU(C[8:0])[23:0];

B  ARU(C[8:0])[47:24];

ACB[4:0]  ARU(C[8:0])[52:48]

Status : SAT

Duration : suspends current MCS-channel for a maximum of one ARU round trip cycle

Code : 1011aaaabbbb0010-------ccccccccc

Description : Perform a non-blocking read access to the ARU trying to transfer both 24 bit values received at the ARU port to the registers A and B (A  AREG, B  AREG), whereas

A holds the lower 24 bit ARU word, B holds the upper 24 bit ARU word, and the ACB register holds the received ARU control bits.

The lower significant bits of the literal C (C  LIT16) define the ARU address where to read from.

If the transfer finishes successfully, the bit SAT of the register STA is set and the transferred values are stored in the registers A, B, and ACB.

If the transfer fails due to missing data at requested source, the bit SAT of the register STA is cleared and registers A, B, and ACB are not changed.

If A and B refer to the same register, only the upper 24 bit ARU word is stored and the lower

24 bit ARU word is discard.

If any transferred 24 bit value from the ARU should not stored in a register, the dummy register ZERO  AREG can be selected in A or B to discard the corresponding ARU data.

Actually, all address values of A and B that exceed the range 0 to 7 discard the corresponding ARU data.

The program counter PC is incremented by the value 4.

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Syntax : NARDI A, B

Operation : A  ARU(R6[8:0])[23:0];

B  ARU(R6[8:0])[47:24];

ACB[4:0]  ARU(R6[8:0])[52:48]

Status : SAT

Duration : suspends current MCS-channel for a maximum of one ARU round trip cycle

Code : 1011aaaabbbb0011----------------

Description : Perform a non-blocking read access to the ARU trying to transfer both 24 bit values received at the ARU port to the registers A and B (A  AREG, B  AREG), whereas

A holds the lower 24 bit ARU word, B holds the upper 24 bit ARU word, and the ACB register holds the received ARU control bits.

The read address is obtained from the bits 0 to 8 of the channels register R6.

If the transfer finishes successfully, the bit SAT of the register STA is set and the transferred values are stored in the registers A, B, and ACB.

If the transfer fails due to missing data at requested source, the bit SAT of the register STA is cleared and registers A, B, and ACB are not changed.

If A and B refer to the same register, only the upper 24 bit ARU word is stored and the lower

24 bit ARU word is discard.

If any transferred 24 bit value from the ARU should not stored in a register, the dummy register ZERO  AREG can be selected in A or B to discard the corresponding ARU data.

Actually, all address values of A and B that exceed the range 0 to 7 discard the corresponding ARU data.

The program counter PC is incremented by the value 4.

13.2.4 Arithmetic logic instructions

Syntax : ADDL A, C

Operation : A  A + C

Status : Z, CY, N, V

Duration : 1 instruction cycle

Code : 0010aaaacccccccccccccccccccccccc

Description : Perform addition operation of a register A (A  OREG) with a 24 bit literal value C (C  LIT24) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow/underflow occurred during addition, otherwise the bit is cleared. An unsigned overflow has occurred, when the result of the operation cannot be represented in the interval [0; 2

-1], assuming that both operands A and C are unsigned values within the interval [0; 2

-1].

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The overflow bit V of status register STA is set, if a signed overflow/underflow occurred during addition, otherwise the bit is cleared. A signed overflow/underflow has occurred, when the result of the operation cannot be represented in the interval [-2 23 ; 2 23 assuming that both operands A and C are signed values within the interval [-2

-1],

23 ; 2 23 -1].

The negative bit N of status register STA equals the most significant bit of the operation result, in order to determine if a calculated signed result is negative (N=1) or positive (N=0), assuming that no overflow/underflow occurred.

The program counter PC is incremented by the value 4.

Syntax : ADD A, B

Operation : A  A + B

Status : Z, CY, N, V

Duration : 1 instruction cycle

Code : 1100aaaabbbb0000----------------

Description : Perform addition operation of a register A (A  OREG) with an operand B (B 

OREG) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned overflow occurred during addition, otherwise the bit is cleared. An unsigned overflow has occurred, when the result of the operation cannot be represented in the interval [0; 2 24 -1], assuming that both operands

A and B are unsigned values within the interval [0; 2 24 -1].

-1],

23 ; 2 23 -1].

The program counter PC is incremented by the value 4.

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Syntax : SUBL A, C

Operation : A  A - C

Status : Z, CY, N, V

Duration : 1 instruction cycle

Code : 0011aaaacccccccccccccccccccccccc

Description : Perform subtraction operation of a register A (A  OREG) with a 24 bit literal value C (C  LIT24) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

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The carry bit CY of status register STA is set, if an unsigned underflow occurred during subtraction, otherwise the bit is cleared. An unsigned underflow has occurred, when the result of the operation cannot be represented in the interval [0; 2 24 -1], assuming that both operands A and C are unsigned values within the interval [0; 2 24 -1].

The overflow bit V of status register STA is set, if a signed overflow/underflow occurred during subtraction, otherwise the bit is cleared. A signed overflow/underflow has occurred, when the result of the operation cannot be represented in the interval [-2 23 ; 2 23 assuming that both operands A and C are signed values within the interval [-2

-1],

23 ; 2 23 -1].

The program counter PC is incremented by the value 4.

Syntax : SUB A, B

Operation : A  A - B

Status : Z, CY, N, V

Duration : 1 instruction cycle

Code : 1100aaaabbbb0001----------------

Description : Perform subtraction operation of a register A (A  OREG) with an operand B

(B  OREG) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is set, if an unsigned underflow occurred during subtraction, otherwise the bit is cleared. An unsigned underflow has occurred, when the result of the operation cannot be represented in the interval [0; 2 24 -1], assuming that both operands A and B are unsigned values within the interval [0; 2 24 -1].

-1],

23 ; 2 23 -1].

The program counter PC is incremented by the value 4.

Syntax : NEG A, B

Operation : A  - B

Status : Z, N, V

Duration : 1 instruction cycle

Code : 1100aaaabbbb0010----------------

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Description : Perform negation operation (2's Complement) with an operand B (B  OREG) and store the result in a register A (A  OREG).

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

-1],

23 ; 2 23 -1].

The program counter PC is incremented by the value 4.

Syntax : ANDL A, C

Operation : A  A AND C

Status : Z

Duration : 1 instruction cycle

Code : 0100aaaacccccccccccccccccccccccc

Description : Perform bitwise AND conjunction of a register A (A  OREG) with a 24 bit literal value C (C  LIT24) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : AND A, B

Operation : A  A AND B

Status : Z

Duration : 1 instruction cycle

Code : 1100aaaabbbb0011----------------

Description : Perform bitwise AND conjunction of a register A (A  OREG) with an operand

B (B  OREG) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : ORL A, C

Operation : A  A OR C

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Status : Z

Duration : 1 instruction cycle

Code : 0101aaaacccccccccccccccccccccccc

Description : Perform bitwise OR conjunction of a register A (A  OREG) with a 24 bit literal value C (C  LIT24) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : OR A, B

Operation : A  A OR B

Status : Z

Duration : 1 instruction cycle

Code : 1100aaaabbbb0100----------------

Description : Perform bitwise OR conjunction of a register A (A  OREG) with an operand B

(B  OREG) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : XORL A, C

Operation : A  A XOR C

Status : Z

Duration : 1 instruction cycle

Code : 0110aaaacccccccccccccccccccccccc

Description : Perform bitwise XOR conjunction of a register A (A  OREG) with a 24 bit literal value C (C  LIT24) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : XOR A, B

Operation : A  A XOR B

Status : Z

Duration : 1 instruction cycle

Code : 1100aaaabbbb0101----------------

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Description : Perform bitwise XOR conjunction of a register A (A  OREG) with an operand

B (B  OREG) and store the result in register A.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : SHR A, C

Operation : A  A >> C

Status : Z, CY

Duration : 1 instruction cycle

Code : 1100aaaa----0110-----------ccccc

Description : Perform right shift operation C (C  LIT16) times of register A (A  OREG), whereas C must be in the range [0; 24]. The most significant bits that are shifted into A are cleared.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is updated to the last LSB that is shifted out of the register.

The program counter PC is incremented by the value 4.

Syntax : SHL A, C

Operation : A  A << C

Status : Z, CY

Duration : 1 instruction cycle

Code : 1100aaaa----0111-----------ccccc

Description : Perform left shift operation C (C  LIT16) times of register A (A  OREG), whereas C must be in the range [0; 24]. The lower significant bits that are shifted into A are cleared.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The carry bit CY of status register STA is updated to the last MSB that is shifted out of the register.

The program counter PC is incremented by the value 4.

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Syntax : ATUL A, C

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Operation : A - C

Status : Z, CY

Duration : 1 instruction cycle

Code : 0111aaaacccccccccccccccccccccccc

Description : Arithmetic Test with an unsigned operand A (A  OREG) and an unsigned 24 bit literal value C (C  LIT24).

The carry bit CY of status register STA is set if unsigned operand A is less than unsigned literal C.

Otherwise, the carry bit CY of status register STA is cleared if unsigned operand A is greater than or equal to unsigned literal C.

The zero bit Z of status register STA is set, if A equals to C.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to C.

The program counter PC is incremented by the value 4.

Syntax : ATU A, B

Operation : A - B

Status : Z, CY

Duration : 1 instruction cycle

Code : 1101aaaabbbb0000----------------

Description : Arithmetic Test with an unsigned operand A (A  OREG) and an unsigned operand B (B  OREG).

The carry bit CY of status register STA is set if unsigned operand A is less than unsigned operand B.

Otherwise, the carry bit CY of status register STA is cleared if unsigned operand A is greater than or equal to unsigned operand B.

The zero bit Z of status register STA is set, if A equals to B.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to B.

The program counter PC is incremented by the value 4.

Syntax : ATSL A, C

Operation : A - C

Status : Z, CY

Duration : 1 instruction cycle

Code : 1000aaaacccccccccccccccccccccccc

Description : Arithmetic Test with a signed operand A (A  OREG) and a signed 24 bit literal value C (C  LIT24).

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The carry bit CY of status register STA is set if signed operand A is less than signed literal

Otherwise, the carry bit CY of status register STA is cleared if signed operand A is greater than or equal to signed literal C.

The zero bit Z of status register STA is set, if A equals to C.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to C.

The program counter PC is incremented by the value 4.

Syntax : ATS A, B

Operation : A - B

Status : Z, CY

Duration : 1 instruction cycle

Code : 1101aaaabbbb0001----------------

Description : Arithmetic Test with a signed operand A (A  OREG) and a signed operand B

(B  OREG).

The carry bit CY of status register STA is set if signed operand A is less than signed operand B.

Otherwise, the carry bit CY of status register STA is cleared if signed operand A is greater than or equal to signed operand B.

The zero bit Z of status register STA is set, if A equals to B.

Otherwise, the zero bit Z of status register STA is cleared, if A is unequal to B.

The program counter PC is incremented by the value 4.

Syntax : BTL A, C

Operation : A AND C

Status : Z

Duration : 1 instruction cycle

Code : 1001aaaacccccccccccccccccccccccc

Description : Bit test of an operand A (A  OREG) with a 24 bit literal bit mask C (C 

LIT24).

The bit test is performed by applying a bitwise logical AND operation with operand A and the bit mask C without storing the result.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

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Syntax : BT A, B

Operation : A AND B

Status : Z

Duration : 1 instruction cycle

Code : 1101aaaabbbb0010----------------

Description : Bit test of an operand A (A  OREG) with an operand B (B  OREG), whereas usually one of the operands is a register holding a bit mask.

The bit test is performed by applying a bitwise logical AND operation with register A and register B without storing the result.

The zero bit Z of status register STA is set, if the calculated value is zero, otherwise the zero bit is cleared.

The program counter PC is incremented by the value 4.

Syntax : JMP C

Operation : PC  C[13:0]

Status : -

Duration : 1 instruction cycle

Code : 1110--------0000--cccccccccccccc

Description : Execute unconditional jump to the memory location C (C  LIT16).

The program counter PC is loaded with literal C.

Syntax : JBS A, B, C

Operation : PC  C[13:0] if A[B] is set

Status : -

Duration : 1 instruction cycle

Code : 1110aaaabbbb0001--cccccccccccccc

Description : Execute conditional jump to the memory location C (C  LIT16).

The program counter PC is loaded with literal C, if the bit at position B (B  LIT4) of operand

A (A  OREG) is set.

Otherwise, if the bit is cleared, the program counter PC is incremented by the value 4.

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Syntax : JBC A, B, C

Operation : PC  C[13:0] if A[B] is cleared

Status : -

Duration : 1 instruction cycle

Code : 1110aaaabbbb0010--cccccccccccccc

Description : Execute conditional jump to the memory location C (C  LIT16).

The program counter PC is loaded with literal C, if the bit at position B (B  LIT4) of operand

A (A  OREG) is cleared.

Otherwise, if the bit is set, the program counter PC is incremented by the value 4.

Syntax : CALL C

Operation : R7  R7 + 4;

MEM(R7[15:0])[15:0]  PC + 4;

PC  C[13:0];

SP_CNT  SP_CNT + 1

Status : EN

Duration : 2 instruction cycles

Code : 1110--------0011--cccccccccccccc

Description : Call subprogram at memory location C (C  LIT16).

The stack pointer register R7 is incremented by the value 4.

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

After the stack pointer is incremented, the incremented value of the PC is transferred to the top of the stack.

The program counter PC is loaded with literal C.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is incremented.

If an overflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the channel current MCS-channel is disabled by clearing the EN bit of

STA .

If an overflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the memory write operation of the incremented PC is discarded.

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Syntax : RET

Operation : PC  MEM(R7[15:0])[15:0];

R7  R7 - 4;

SP_CNT  SP_CNT - 1

Status : EN

Duration : 2 instruction cycles

Code : 1110--------0100----------------

Description : Return from subprogram.

The program counter PC is loaded with current value on the top of the stack.

Finally, the stack pointer register R7 is decremented by the value 4.

The memory location for the top of the stack is identified by the bits 0 to 15 of the stack pointer register.

The SP_CNT bit field inside the MCS[i]_CH[x]_CTRL register is decremented.

If an underflow on the SP_CNT bit field occurs, the STK_ERR[i]_IRQ is raised.

If an underflow on the SP_CNT bit field occurs and the bit HLT_SP_OFL of register

MCS[i]_CTRL is set, the channel current MCS-channel is disabled by clearing the EN bit of

STA .

Syntax : WURM A B C

Operation : Wait until register match

Status : CWT

Duration : suspends current MCS-channel

Code : 1111aaaabbbb0000cccccccccccccccc

Description : Suspend current MCS-channel until the following register match condition occurs:

A = (B AND MASK) whereas A  OREG, B  OREG, AND is a bitwise AND operation with bitmask MASK. The bits 16 to 23 of MASK are set to true and the bits 0 to 15 are copied from the instructions literal C  LIT16.

If the match condition is true at the beginning of the instruction execution, the instruction does not suspend the channel and the program counter PC is incremented by the value 4.

This instruction can be used to wait for one or more trigger events generated by other MCSchannels or the CPU. In this case register B is the trigger register STRG, A is a general purpose register holding the bits with the trigger condition to wait for and C is the bitmask that enables trigger bits of interest.

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The trigger bits can be set by other MCS channels with a write access (e.g. using a MOVL instruction) to the STRG register or the CPU with a write access to the MCS[i]_STRG register.

The trigger bits are not cleared automatically by hardware after resuming an MCS-channel, but they have to be cleared explicitly with a write access to the register CTRG by the MCSchannel or with a write access to the register MCS[i]_CTRG by the CPU.

Please note that more than one channel can wait for the same trigger bit to continue.

The instruction can also be used to wait on a specific time/angle event provided by the TBU.

In this case register B is the interesting TBU register TBU_TS0, TBU_TS1, or TBU_TS2, register A is a general purpose register holding the value to wait for and bit mask C should be set to 0xFFFF.

At the beginning of the instruction execution the CWT bit in the register STA is always cleared. After the execution of the instruction the CWT bit is updated in order to show if the instruction finished successfully (CWT = 0) or it was canceled by the CPU (CWT = 1).

If the CWT bit is set simultaneously with the occurrence of the register match condition, the register match condition has the higher priority resulting in a cleared CWT bit.

The program counter PC is incremented by the value 4, when the trigger bit is set and the channel continues its operation.

Syntax : NOP

Operation : -

Status : -

Duration : 1 instruction cycle

Code : 0000----------------------------

Description : No operation is performed.

The program counter PC is incremented by the value 4.

13.3 MCS internal registers

This section describes MCS internal registers which are partly only accessible by the

corresponding MCS-channel itself and partly global to all channels. Please see Table 173

for clarification.

These registers can be directly accessed with the entire MCS instruction set, e.g. using the

ORL instruction to set a specific bit.

13.3.1 MCS internal registers overview

The table describes the MCS internal registers. Only parts of this register set can be accessed by the CPU.

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R[x]

Register name

STA

ACB

CTRG

STRG

TBU_TS0

TBU_TS1

TBU_TS2

MHB

Table 173. MCS internal registers

Description

General purpose register x (x: 0...7),

MCS Task internal register.

Status register

MCS Task internal register.

ARU Control Bit register

MCS Task internal register.

Clear Trigger Bits register

MCS Global register from task view.

Set Trigger Bits register

MCS Global register from task view.

TBU Timestamp TS0 register

MCS Global register from task view.

TBU Timestamp TS1 register

MCS Global register from task view.

TBU Timestamp TS2 register

MCS Global register from task view.

Memory High Byte register

MCS Task internal register.

Multi Channel Sequencer (MCS)

13.3.5

13.3.6

13.3.7

13.3.8

Details in section

13.3.2

13.3.3

13.3.4

13.3.9

13.3.10

13.3.2 General purpose register R[x] (x:0...7)

Address offset: 0x0 + x Initial value: 0x000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value n/a DATA

0x0000_00

Bit

[8:31]

[0:7]

Table 174. R[x] (x:0...7) field description

Description

DATA

: data field of general purpose register.

n/a

Note:

MCS micro program.

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Address offset: 0x8 Initial value: 0x000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

000

0x00

R R R R R R R

A w

0 0 0 0 0 0 0 0 0 0 0

Bit

Table 175. STA field description

Description

EN : Enable current MCS-channel.

0: Disable current MCS-channel.

1: Enable current MCS-channel.

IRQ : Trigger IRQ.

0: No triggered IRQ signal.

1: Trigger IRQ signal.

Note:

An MCS-channel triggers an IRQ by writing value 1 to bit IRQ. Writing a value 0 to this bit does not cancel the IRQ, and thus has no effect.

Note:

An MCS-channel can read the IRQ bit in order to determine the current state of the IRQ handling. The MCS-channel reads a value 1 if an IRQ was released but not cleared by

CPU. If an MCS-channel reads a value 0 no IRQ was released or it has been cleared by

CPU.

Note: The IRQ bit can only be cleared by CPU, by writing a 1 to the corresponding

MCS[i]_CH[x]_NOTIFY register (see

Section 13.4.4: Register MCS[i]_CH[x]_R[y]

(x:0...7, y:0...5, 7) ).

ERR

: Set Error Signal.

0: No Error occurred.

1: Error occurred.

Note: The ERR signal of an MCS-channel reflects Error status that may be caused by one of the following conditions: 

MCS-channel program sets the ERR signal by writing to this bit 

ECC RAM Error occurred while accessing the connected RAM pages (also disables

MCS channel by clearing bit EN) 

Decoding an instruction with an invalid opcode (also disables MCS-channel by clearing bit EN)

Note:

If the GTM includes a MON sub module, the ERR signal is always captured by this module.

Note:

An MCS-channel releases an error signal by writing value 1 to bit ERR. Writing a value

0 to this bit does not cancel the error signal, and thus has no effect.

Note:

An MCS-channel can read the ERR bit in order to determine the current state of the error signal. The MCS-channel reads a value 1 if an ERR occurred previously, but not cleared by CPU. If an MCS-channel reads a value 0 no error was set or it has been cleared by

CPU.

Note: The ERR bit can only be cleared by CPU, by writing a 1 to the MCS[i]_ERR register (see

Section 13.4.16: Register MCS[i]_ERR

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Bit

[16:20]

[8:12]

[0:7]

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Table 175. STA field description (continued)

Description

MCA : MON Activity signaling for MCS channel.

0: No activity signaled to sub module MON.

1: Activity signaled to sub module MON.

Note:

When this bit is set the corresponding channel in the MON sub module register

MON_ACTIVITY is set (see Section 20.8.2: Register MON_ACTIVITY_0 .

This bit is automatically cleared after writing it by the MCS channel program.

CY : Carry bit.

The carry bit is updated by several arithmetic and logic instructions. In arithmetic operations, the carry bit indicates an unsigned under/overflow.

: Zero bit.

The zero bit is updated by several arithmetic, logic and data transfer instructions to indicate a result of zero.

V : Overflow bit

The overflow bit is updated by arithmetic instructions in order to indicate a signed under/overflow.

N : Negative bit.

The negative bit is updated by arithmetic instructions in order to indicate a negative result.

CAT : Cancel ARU transfer bit.

0: Last ARU transfer was not canceled.

1: CPU canceled last ARU transfer.

Note:

This bit is updated after each ARU transfer and it should be evaluated immediately after the ARU instruction. Otherwise, the CPU could set the bit leading to a bad status information in the MCS program.

CWT : Cancel WURM instruction bit.

0: Last WURM instruction was not canceled.

1: CPU canceled last WURM instruction of channel.

Note:

This bit is updated after each WURM instruction and it should be evaluated immediately after the WURM instruction. Otherwise, the CPU could set the bit leading to a bad status information in the MCS program.

SAT : Successful ARU transfer bit.

0: Non-blocking ARU transfer failed due to missing data.

1: Non-blocking ARU transfer finished successfully.

Reserved : Read as zero, should be written as zero.

n/a

Note: If both, the CPU and the MCS-channel are writing to the same register at the clock cycle, the value of the CPU is written to the register and the value of the MCS-channel is discarding.

Writing to bits of the register STA with instructions that do implicitly a read-modify-write operation (e.g. "ANDL STA, 0xFFFFFE" or "OR STA, R0") is dangerous, since writing back the possibly modified content of the read access (which reflects status information) may cause undesirable results. A secure way for writing to bits of the register STA is to use instructions that do not read the content of STA (e.g. "MOVL STA, 0x0 or MOV STA, R1").

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Address offset: 0x9 Initial value: 0x01FE00

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[8:26]

[8:12]

[0:7]

Table 176. ACB field description

Description

ACB0

: ARU Control bit 0.

Note: This bit is updated by each ARU read access and its value is sent to ARU by each ARU write access on bit 48 of the ARU word.

ACB1

: ARU Control bit 1.

Note:

This bit is updated by each ARU read access and its value is sent to ARU by each ARU write access on bit 49 of the ARU word

ACB2

: ARU Control bit 2.

Note:

This bit is updated by each ARU read access and its value is sent to ARU by each ARU write access on bit 50 of the ARU word

ACB3 : ARU Control bit 3.

Note:

This bit is updated by each ARU read access and its value is sent to ARU by each ARU write access on bit 51 of the ARU word

ACB4 : ARU Control bit 4.

Note: This bit is updated by each ARU read access and its value is sent to ARU by each ARU write access on bit 52 of the ARU word

Reserved

: Read as zero, should be written as zero.

Reserved

: Read as zero, should be written as zero.

n/a

Address offset: 0xA Initial value: 0x000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Bit

Table 177. CTRG field description

Description

TRG0 : trigger bit 0.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG1

: trigger bit 1.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG2 : trigger bit 2.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG3

: trigger bit 3.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG4

: trigger bit 4.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG5

: trigger bit 5.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG6 : trigger bit 6.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG7 : trigger bit 7.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG8 : trigger bit 8.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG9

: trigger bit 9.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG10

: trigger bit 10.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG11

: trigger bit 11.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG12 : trigger bit 12.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

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[0:7]

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Table 177. CTRG field description (continued)

Description

TRG13 : trigger bit 13.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG14

: trigger bit 14.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG15 : trigger bit 15.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

Note:

The trigger bits TRGx (x = 0...15) are accessible by all MCS channels as well as the

CPU. Setting a trigger bit can be performed with the STRG register, in the case of an

MCS-channel or the MCS[i]_STRG register in the case of the CPU. Clearing a trigger bit can be performed with the CTRG register, in the case of an MCS-channel or the

MCS[i]_CTRG register in the case of the CPU.

Trigger bits can be used for signalizing specific events to MCS-channels or the CPU. An

MCS-channel suspended with a WURM instruction can be resumed by setting the appropriate trigger bit.

Reserved

: Read as zero, should be written as zero.

n/a

Address offset: 0xB Initial value: 0x000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 178. STRG field description

Description

TRG0 : trigger bit 0.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG1

: trigger bit 1.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG2

: trigger bit 2.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

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Table 178. STRG field description (continued)

Description

TRG3 : trigger bit 3.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG4

: trigger bit 4.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG5 : trigger bit 5.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG6

: trigger bit 6.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG7 : trigger bit 7.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG8

: trigger bit 8.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG9

: trigger bit 9.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG10

: trigger bit 10.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG11 : trigger bit 11.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG12 : trigger bit 12.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG13 : trigger bit 13.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG14

: trigger bit 14.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

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Table 178. STRG field description (continued)

Description

TRG15 : trigger bit 15.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

Note:

The trigger bits TRGx (x = 0...15) are accessible by all MCS channels as well as the

CPU. Setting a trigger bit can be performed with the STRG register, in the case of an

MCS-channel or the MCS[i]_STRG register in the case of the CPU. Clearing a trigger bit can be performed with the CTRG register, in the case of an MCS-channel or the

MCS[i]_CTRG register in the case of the CPU.

Trigger bits can be used for signalizing specific events to MCS-channels or the CPU. An

MCS-channel suspended with a WURM instruction can be resumed by setting the appropriate trigger bit.

Reserved

: Read as zero, should be written as zero.

n/a

Address offset: 0xC Initial value: 0xXXXXXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 n/a TS Bit

Mode

Initial value

0xXXXXXX

Bit

[8:31]

[0:7]

Table 179. TBU_TS0 field description

Description

TS : Current TBU time stamp 0.

n/a

Note: Any write access to a time base register discards the written data. A write access to a time base register may be used to destroy an unused 24-bit data word of an ARU read transfer.

Address offset: 0xD Initial value: 0xXXXXXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 n/a TS Bit

Mode

Initial value

0xXXXXXX

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Table 180. TBU_TS1 field description

Description

TS : Current TBU time stamp 1.

n/a

Note: Any write access to a time base register discards the written data. A write access to a time base register may be used to destroy an unused 24-bit data word of an ARU read transfer.

Address offset: 0xD Initial value: 0xXXXXXX

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 n/a TS Bit

Mode

Initial value

0xXXXXXX

Bit

[8:31]

[0:7]

Table 181. TBU_TS2 field description

Description

TS : Current TBU time stamp 2.

n/a

Note: Any write access to a time base register discards the written data. A write access to a time base register may be used to destroy an unused 24-bit data word of an ARU read transfer.

Address offset: 0xF Initial value: 0x000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 n/a Reserved DATA Bit

Mode

Initial value

0x000000

Bit

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[0:7]

Table 182. MHB field description

Description

DATA : High Byte of a memory transfer.

Reserved

: Read as zero, should be written as zero.

n/a

13.4 MCS configuration registers

This section describes the configuration registers of the MCS sub module.

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These registers can only be accessed by the CPU using AEI, but not within the MCSchannel using MCS instructions.

The table describes the MCS registers that are visible and accessible by the CPU.

Register name

MCS[i]_CH[x]_CTRL

MCS[i]_CH[x]_ACB

MCS[i]_CH[x]_PC

MCS[i]_CH[x]_R[y]

MCS[i]_CH[x]_IRQ_NOTIFY

MCS[i]_CH[x]_IRQ_EN

MCS[i]_CH[x]_IRQ_FORCINT

MCS[i]_CH[x]_IRQ_MODE

MCS[i]_CH[x]_EIRQ_EN

MCS[i]_CTRL

MCS[i]_CTRG

MCS[i]_STRG

MCS[i]_RST

MCS[i]_ERR

Table 183. MCS registers

Description Details in section

MCS Channel control register (x: 0...7)

MCS Channel ACB register (x: 0...7)

MCS Channel Program counter register (x: 0...7)

13.4.2

13.4.6

13.4.3

MCS Channel GPRx registers (x: 0...7; y: 0...7)

MCS Channel x interrupt notification register (x: 0...7)

13.4.4

13.4.7

MCS Channel x interrupt enable register (x: 0...7)

MCS Channel x software interrupt generation register (x:

0...7)

13.4.8

13.4.9

IRQ mode configuration register (x=0...7)

13.4.10

MCS Channel x error interrupt enable register (x: 0...7)

13.4.11

MCS Control register

13.4.12

MCS Clear trigger control register

MCS Set trigger control register

13.4.13

13.4.14

MCS Channel reset register

MCS Error register

13.4.15

13.4.16

Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 184. MCS[i]_CH[x]_CTRL (x:0...7) field description

Description

EN : Enable MCS-channel

0: Disable current MCS-channel.

1: Enable current MCS-channel.

Note:

Enabling or disabling of an MCS-channel is synchronized to the ending of an instruction and thus it may take several clock cycles, e.g. active memory transfers or pending

WURM transfers have to be finished before disabling the MCS-channel. The internal state of a channel can be obtained by reading the bit EN.

Note:

In order to disable an MCS channel reliably the EN bit should be cleared followed by setting the CAT and CWT bit in order to cancel any pending WURM or ARU instructions.

Note:

The EN bit is write protected during RAM reset phase.

IRQ : Interrupt state.

0: No interrupt pending in MCS-channel x.

1: Interrupt is pending in MCS-channel x.

Note:

This bit is read only and it mirrors the internal IRQ state

ERR : Error state.

0: No error signal pending in MCS-channel x.

1: Error signal is pending in MCS-channel x.

Note:

This bit is read only and it mirrors the internal error state.

Reserved : Read as zero, should be written as zero.

CY : Carry bit state.

Note: : This bit is read only and it mirrors the internal carry flag CY.

Z : Zero bit state.

Note: This bit is read only and it mirrors the internal zero flag Z.

V : Overflow bit state.

Note: This bit is read only and it mirrors the internal carry flag V.

N : Negative bit state.

Note: This bit is read only and it mirrors the internal zero flag N..

CAT : Cancel ARU transfer state.

Note: This bit is read only and it mirrors the internal cancel ARU transfer status flag CAT.

CWT : Cancel WURM instruction state.

Note: This bit is read only and it mirrors the internal cancel WURM instruction status flag CWT.

SAT : Successful ARU transfer bit.

0: Non-blocking ARU transfer failed due to missing data.

1: Non-blocking ARU transfer finished successfully

Reserved : Read as zero, should be written as zero.

SP_CNT : Stack pointer counter value.

Actual stack depth of channel. The bit field is incremented on behalf of a CALL or PUSH instruction and decremented on behalf of a RET or POP instruction. The MCS channel

STK_ERR_IRQ is raised, when an overflow or underflow is detected on this bit field

Reserved

: Read as zero, should be written as zero.

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13.4.3 Register MCS[i]_CH[x]_PC (x:0...7)

Address offset: see Appendix B Initial value: 0x00000000 + 4*x

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x000

RPw

0x000000+4*x

Bit

[18:31]

[0:17]

Table 185. MCS[i]_CH[x]_PC (x:0...7) field description

Description

: Current Program Counter.

Note: The program counter is only writable if the corresponding MCS-channel is disabled. The bits 0 and 1 are always written as zeros.

Reserved : Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DATA Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 186. MCS[i]_CH[x]_R[y] (x:0...7, y:0...5, 7) field description

Description

DATA

: Data of MCS general purpose register R[y].

Reserved

: Read as zero, should be written as zero.

Note:

This register is the same as described in

Section 13.3.2: General purpose register R[x]

(x:0...7)

Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

DATA

RPw

0x000000

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Table 187. MCS[i]_CH[x]_R6 field description

Description

DATA : Data of MCS general purpose register R[y].

Reserved

: Read as zero, should be written as zero.

Note: This register is write protected during an active ARDI or NARDI instruction.

Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:26]

Table 188. MCS[i]_CH[x]_ACB (x:0...7) field description

Description

ACB0

: ARU Control bit 0.

Note:

This bit is read only and it mirrors the internal state.

ACB1

: ARU Control bit 1.

Note:

This bit is read only and it mirrors the internal state.

ACB2

: ARU Control bit 2.

Note:

This bit is read only and it mirrors the internal state.

ACB3

: ARU Control bit 3.

Note:

This bit is read only and it mirrors the internal state.

ACB4

: ARU Control bit 4.

Note:

This bit is read only and it mirrors the internal state.

Reserved

: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:28]

Table 189. MCS[i]_CH[x]_IRQ_NOTIFY (x:0...7) field description

Description

MCS_IRQ

: Interrupt request by MCS-channel x.

0 = No IRQ released

1 = IRQ released by MCS-channel

Note: This bit will be cleared on a CPU write access with a value '1'. A read access leaves the bit unchanged.

Note: By writing a '1' to this register, the IRQ flag in the MCS channel status register STA is cleared.

STK_ERR_IRQ : Stack counter overflow/underflow of channel x.

0 = No IRQ released

1 = A stack counter overflow or underflow occurred

Note:

This bit will be cleared on a CPU write access with a value '1'. A read access leaves the bit unchanged.

MEM_ERR_IRQ : Memory access out of range in channel x.

0 = No IRQ released

1 = MCS-channel request a memory location out of range.

Note:

This bit will be cleared on a CPU write access with a value '1'. A read access leaves the bit unchanged.

Note:

In the case of a memory overflow, any read or write access to the RAM is always blocked. The read data is unpredictable.

Note:

It should be noted that in the case of a memory overflow, the MCS channel will continue.

Thus it is recommended that the CPU immediately stops the MCS channel.

Reserved : Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:28]

Table 190. MCS[i]_CH[x]_IRQ_EN (x:0...7) field description

Description

MCS_IRQ_EN

: MCS channel x MCS_IRQ interrupt enable

0 = Disable interrupt

1 = Enable interrupt

STK_ERR_IRQ_EN

: MCS channel x STK_ERR_IRQ interrupt enable

0 = Disable interrupt

1 = Enable interrupt

MEM_ERR_IRQ_EN : MCS channel x MEM_ERR_IRQ interrupt enable

0 = Disable interrupt

1 = Enable interrupt

Reserved : Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 191. MCS[i]_CH[x]_IRQ_FORCINT (x:0...7) field description

Description

TRG_MCS_IRQ : Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software

0 = No interrupt triggering

1 = Assert corresponding field in MCS[i]_CH[x]_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_STK_ERR_IRQ

: Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software

0 = No interrupt triggering

1 = Assert corresponding field in MCS[i]_CH[x]_IRQ_NOTIFY register

Note: This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_MEM_ERR_IRQ : Trigger IRQ bit in MCS_CH_[x]_IRQ_NOTIFY register by software

0 = No interrupt triggering

1 = Assert corresponding field in MCS[i]_CH[x]_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note:

This bit is write protected by bit RF_PROT of register GTM_CTRL

Reserved

: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[0:29]

Table 192. MCS[i]_CH[x]_IRQ_MODE (x:0...7) field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note: The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note: Read as zero, should be written as zero.

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0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:28]

Table 193. MCS[i]_CH[x]_EIRQ_EN (x:0...7) field description

Description

MCS_EIRQ_EN

: MCS channel x MCS_EIRQ error interrupt enable

0 = Disable error interrupt

1 = Enable error interrupt

STK_ERR_EIRQ_EN

: MCS channel x STK_ERR_IRQ error interrupt enable

0 = Disable error interrupt

1 = Enable error interrupt

MEM_ERR_EIRQ_EN

: MCS channel x MEM_ERR_EIRQ error interrupt enable

0 = Disable error interrupt

1 = Enable error interrupt

Reserved : Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x000X_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 194. MCS[i]_CTRL field description

Description

SCHED : MCS submodule scheduling scheme

0 = Accelerated scheduling scheme.

1 = Round-Robin scheduling scheme.

HLT_SP_OFL

: Halt on stack pointer overflow.

0 = No halt on MCS-channel stack pointer counter over/underflow.

1 = MCS-channel is disabled if a stack pointer counter over/underflow occurs

Reserved : Read as zero, should be written as zero.

RAM_RST

: RAM reset bit.

0 = READ: no RAM reset is active / WRITE : do nothing.

1 = READ: MCS currently resets RAM content / WRITE : trigger RAM reset.

Note: The RAM reset initializes the memory content with zeros. RAM access and enabling of

MCS channels is disabled during active RAM reset.

Note: This bit is only writable if the bit RF_PROT in register GTM_CTRL is cleared and all

MCS-channels are disabled.

Note:

The actual reset values of this bit depends on the silicon vendor configuration. The reset value is 1, if the RAM reset is performed together with the sub module reset, otherwise the reset value is 0. If the reset value is 1, the reset value is changed to 0 by hardware, when the RAM reset finished.

Reserved : Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 195. MCS[i]_CTRG field description

Description

TRG0 : trigger bit 0.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG1 : trigger bit 1.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG2 : trigger bit 2.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

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Table 195. MCS[i]_CTRG field description (continued)

Description

TRG3 : trigger bit 3.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG4

: trigger bit 4.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG5 : trigger bit 5.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG6

: trigger bit 6.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG7 : trigger bit 7.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG8

: trigger bit 8.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG9

: trigger bit 9.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG10

: trigger bit 10.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG11 : trigger bit 11.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG12 : trigger bit 12.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG13 : trigger bit 13.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

TRG14

: trigger bit 14.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

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Table 195. MCS[i]_CTRG field description (continued)

Description

TRG15 : trigger bit 15.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: clear trigger bit

Note:

The trigger bits TRGx (x = 0...15) are accessible by all MCS channels as well as the

CPU. Setting a trigger bit can be performed with the STRG register, in the case of an

MCS-channel or the MCS[i]_STRG register in the case of the CPU. Clearing a trigger bit can be performed with the CTRG register, in the case of an MCS-channel or the

MCS[i]_CTRG register in the case of the CPU.

Note: Trigger bits can be used for signalizing specific events to MCS-channels or the CPU. An

MCS-channel suspended with a WURM instruction can be resumed by setting the appropriate trigger bit.

Note:

A write access to MCS[i]_CTRG may take up to 13 clock cycles, since the write access is scheduled to the next CPU time slot determined by the MCS scheduler.

Reserved

: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 196. MCS[i]_STRG field description

Description

TRG0 : trigger bit 0.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG1 : trigger bit 1.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG2

: trigger bit 2.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG3

: trigger bit 3.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG4

: trigger bit 4.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

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Table 196. MCS[i]_STRG field description (continued)

Description

TRG5 : trigger bit 5.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG6

: trigger bit 6.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG7 : trigger bit 7.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG8

: trigger bit 8.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG9 : trigger bit 9.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG10

: trigger bit 10.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG11

: trigger bit 11.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG12

: trigger bit 12.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG13 : trigger bit 13.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

TRG14 : trigger bit 14.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

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Table 196. MCS[i]_STRG field description (continued)

Description

TRG15 : trigger bit 15.

0: READ: trigger bit is cleared / WRITE: do nothing

1: READ: trigger bit is set / WRITE: set trigger bit

Note:

The trigger bits TRGx (x = 0...15) are accessible by all MCS channels as well as the

CPU. Setting a trigger bit can be performed with the STRG register, in the case of an

MCS-channel or the MCS[i]_STRG register in the case of the CPU. Clearing a trigger bit can be performed with the CTRG register, in the case of an MCS-channel or the

MCS[i]_CTRG register in the case of the CPU.

Note: Trigger bits can be used for signalizing specific events to MCS-channels or the CPU. An

MCS-channel suspended with a WURM instruction can be resumed by setting the appropriate trigger bit.

Note:

A write access to MCS[i]_STRG may take up to 13 clock cycles, since the write access is scheduled to the next CPU time slot determined by the MCS scheduler.

[0:15]

Reserved

: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 197. MCS[i]_RST field description

Description

RST0

: Software reset of channel 0

0 = No action

1 = Reset channel

RST1

: Software reset of channel 1

0 = No action

1 = Reset channel

RST2 : Software reset of channel 2

0 = No action

1 = Reset channel

RST3 : Software reset of channel 3

0 = No action

1 = Reset channel

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Multi Channel Sequencer (MCS)

Table 197. MCS[i]_RST field description (continued)

Description

RST4 : Software reset of channel 4

0 = No action

1 = Reset channel

RST5

: Software reset of channel 5

0 = No action

1 = Reset channel

RST6 : Software reset of channel 6

0 = No action

1 = Reset channel

RST7

: Software reset of channel 7

0 = No action

1 = Reset channel

Note: The RSTx (x = 0...7) bits is cleared automatically after write access of CPU. All channel related registers are set to their reset values and channel operation is stopped immediately. The reset action RSTx has a higher priority than setting the bits CWTx or

CATx (x = 0...7).

Note: Channel related registers are all registers MCS[i]_CH[x]_*, all MCS internal registers accessible by the corresponding channel, with exception of the common trigger register

(accessed by CTRG/STRG).

CAT0

: Cancel ARU transfer for channel 0.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT1 : Cancel ARU transfer for channel 1.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT2 : Cancel ARU transfer for channel 2.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT3 : Cancel ARU transfer for channel 3.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT4

: Cancel ARU transfer for channel 4.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT5

: Cancel ARU transfer for channel 5.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

CAT6

: Cancel ARU transfer for channel 6.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer

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Bit

[0:7]

RM0361

Table 197. MCS[i]_RST field description (continued)

Description

CAT7 : Cancel ARU transfer for channel 7.

0 = Do nothing.

1 = Cancel any pending ARU read or write transfer.

Note:

The CATx (x = 0...7) bit inside the STA register of the corresponding MCS-channel is set and any pending ARU read or write request is canceled. The MCS-channel resumes with the instruction after the ARU transfer instruction.

Note: The CATx (x = 0...7) bit is cleared by the corresponding MCS channel, when the channel reaches an ARU read or write instruction.

CWT0 : Cancel WURM instruction for channel 0.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT1

: Cancel WURM instruction for channel 1.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT2 : Cancel WURM instruction for channel 2.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT3 : Cancel WURM instruction for channel 3.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT4 : Cancel WURM instruction for channel 4.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT5

: Cancel WURM instruction for channel 5.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT6

: Cancel WURM instruction for channel 6.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

CWT7

: Cancel WURM instruction for channel 7.

0 = Do nothing.

1 = Cancel any pending WURM instruction.

Note: The CWTx (x = 0...7) bit inside the STA register of the corresponding MCS-channel is set and any pending WURM instruction is cancelled. The MCS-channel resumes with the instruction after the WURM instruction.

Note: The CWTx (x = 0...7) bit is cleared by the corresponding MCS channel, when the channel reaches a WURM instruction.

Reserved

: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:23]

Table 198. MCS[i]_ERR field description

Description

ERR0

: Error State of MCS-channel 0.

0: No error signal.

1: Error signal is pending.

ERR1

: Error State of MCS-channel 1.

0: No error signal.

1: Error signal is pending.

ERR2

: Error State of MCS-channel 2.

0: No error signal.

1: Error signal is pending.

ERR3 : Error State of MCS-channel 3.

0: No error signal.

1: Error signal is pending.

ERR4 : Error State of MCS-channel 4.

0: No error signal.

1: Error signal is pending.

ERR5 : Error State of MCS-channel 5.

0: No error signal.

1: Error signal is pending.

ERR6

: Error State of MCS-channel 6.

0: No error signal.

1: Error signal is pending.

ERR7

: Error State of MCS-channel 7.

0: No error signal.

1: Error signal is pending.

Note: The CPU can read the ERRx (x = 0...7) bits in order to determine the current error state of the corresponding MCS-channel x. The error state is also evaluated by the sub module MON, if this module is available.

Note: Writing a value 1 to this bit resets the corresponding error state and resets the channel internal ERR bit in the STA and channel CTRL registers.

Reserved

: Read as zero, should be written as zero.

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14 Memory Configuration (MCFG)

RM0361

14.1 Overview

The Memory Configuration submodule (MCFG) is an infrastructure module that organizes physical memory blocks and maps them to the instances of Multi Channel Sequencer

(MCS) submodules.

The default configuration maps a memory of size 1 K*32 bit = 4 KB to MCS memory page 0 and a memory of size 0.5 K*32 bit = 2 KB to MCS memory page 1.

In order to support different memory sizes for different MCS instances, the MCFG module provides two additional layout configurations for reorganization of memory pages between

neighbouring MCS modules. Figure 61 shows all layout configurations.

The layout configuration SWAP is swapping the 2 KB memory page of the current MCS instance with the 4KB memory page of the successive MCS instance. Thus, the memory of the current MCS module is increased by 2KB but the memory of the successor is decreased by 2 KB.

The layout configuration BORROW is borrowing the 4 KB memory page of the successive

MCS instance for the current instance. Thus, the memory of the current MCS module is increased by 4 KB but the memory of the successor is decreased by 4 KB.

It should be noted that the successor of the last MCS instance is the first MCS instance

MCS0.

The actual size of the memory pages for an MCS instance depends on the layout configuration for the current instance MCS[i] and the layout configuration of the preceding memory instance MCS[i-1].

Table 199

summarizes the layout parameters MP0 and MP1 for MCS instance MCS[i].

The addressing of memory page 0 ranges from 0 to MP0-4 and the addressing of memory page 1 ranges from MP0 to MP1-4.

Besides these software related Layout configurations, the MCFG submodule has an additional input port MCS_RAM1_EN_ADDR_MSB which is routed to the top level of the

GTM-IP.

The above mentioned behaviour of the MCFG submodule is applied if this port is connected to a constant logic level of zero (0).

If a constant logic level of one (1) is applied to this port, the MCFG submodule assumes that a memory of size 1 K*32 bit = 4 KB is also mapped to MCS memory page 1.

In this case the memory layout configurations of the MCFG submodule change as shown in

Figure 62 and the memory layout parameters are modified according to Table 200 .

This document assumes that the GTM implementation embeds 7 MCS instances. However,

the actual number of implemented MCS instances can be obtained from Section 22.3:

References .

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Figure 61. Memory layout configurations (MCS_RAM1_EN_ADDR_MSB = 0)

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Table 199. Memory layout parameters (MCS_RAM1_EN_ADDR_MSB = 0)

Memory layout configuration of preceding MCS instance MCS[i-1]

DEFAULT

SWAP

MP0

MP1

MP0

MP1

MP0

DEFAULT

0x1000

0x1800

0x1000

0x2000

0x1000

SWAP

0x800

0x1000

0x800

0x1800

0x800

BORROW

0x0

0x800

0x0

0x1000

0x0

BORROW

MP1 0x2800 0x2000 0x1800

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Figure 62. Memory layout configurations (MCS_RAM1_EN_ADDR_MSB = 1)

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Table 200. Memory layout parameters (MCS_RAM1_EN_ADDR_MSB = 1)

Memory layout configuration of preceding MCS instance MCS[i-1]

DEFAULT

SWAP

MP0

MP1

MP0

MP1

MP0

DEFAULT

0x1000

0x2000

0x1000

0x2000

0x1000

SWAP

0x1000

0x2000

0x1000

0x2000

0x1000

BORROW

0x0

0x1000

0x0

0x1000

0x0

BORROW

MP1 0x3000 0x3000 0x2000

This section describes the configuration registers of the MCFG submodule.

Register name

MCFG_CTRL

Table 201. MCFG configuration registers

Description

Memory layout configuration.

14.3

Details in section

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Address offset: see Appendix B Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[28:29]

[26:27]

[24:25]

[22:23]

[20:21]

Table 202. MCFG_CTRL field description

Description

MEM0

: Configure Memory pages for MCS-instance MCS0.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

MEM1 : Configure Memory pages for MCS-instance MCS1.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

MEM2

: Configure Memory pages for MCS-instance MCS2.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

MEM3 : Configure Memory pages for MCS-instance MCS3.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

MEM4

: Configure Memory pages for MCS-instance MCS4.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

MEM5 : Configure Memory pages for MCS-instance MCS5.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

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Bit

[18:19]

[0:17]

Table 202. MCFG_CTRL field description (continued)

Description

MEM6 : Configure Memory pages for MCS-instance MCS6.

00: DEFAULT configuration

01: SWAP configuration

10: BORROW configuration

11: DEFAULT configuration

Reserved

: Read as zero, should be written as zero.

Note:

RM0361

It should be noted that the actual GTM-IP implementation may embed less than 7 MCS instances (see

Section 22.3: References ). In this case this register only implements the

register bits for available MCS instances.

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15

TIM0 input mapping module (MAP)

TIM0 input mapping module (MAP)

15.1 Overview

The MAP submodule generates the two input signals TRIGGER and STATE for the submodule DPLL by evaluating the output signals of the channel 0 up to channel 5 of submodule TIM0. By using the TIM as input submodule, the filtering of the input signals can be done inside the TIM channels themselves. The MAP submodule architecture is depicted in

Figure 63

Figure 63. MAP submodule architecture

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Generally, the MAP submodule can route the channel signals coming from TIM0 in three ways. First, it is possible to route the whole 49 bits of data coming from channel 0 of module

TIM0 (TIM0_CH0) to the TRIGGER signal which is then provided to the DPLL together with the T_VALID signal.

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Second, the MAP module can route one of the five signals coming from the module TIM0

(i.e. the signals coming from channel 1 up to channel 5) to the output signal STATE which is then provided to the module DPLL together with the S_VALID signal.

Third, the TRIGGER , T_VALID , STATE and S_VALID signals can be generated out of the

TIM Signal Preprocessing (TSPP) subunits. This is done in combination with the Sensor

Pattern Evaluation (SPE) submodule described in Chapter 17: Sensor Pattern Evaluation

(SPE) .

There, the signal TRIGGER is generated in subunit TSPP0 out of the TIM0 signals coming from channel 0 up to 2.

The signal STATE is generated in subunit TSPP1 out of the TIM signals coming from channel 3 up to channel 5.

This is only be done, when the TSSPx subunits are enabled and when the SPEx_NIPD signal is raised by the SPE submodule. The SPEx_NIPD_NUM signal encodes, which of the

3 TIMx_CHy input signals has been changed. The SPEx_DIR signal is routed through the

TSPPx subunit and implements the T_DIR or S_DIR signal.

A third method to provide a direction signal to DPLL is to use TIM0 channel 6 input

( TIM0_IN6 ) and to route it instead of the DIR signal coming from TSSOP0 to the MAP output T_DIR (set TSEL=0)

15.2 TIM signal preprocessing (TSPP)

The TSPP combines the three 49 bit input streams coming from the TIM0 submodule and generates one combined 49 bit output stream TSPPO . The input stream combination is done in the unit Bit Stream Combination (BSC). The architecture of the TSPP is shown in

Figure 64

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15.2.1 TIM signal preprocessing (TSPP) subunit architecture

Figure 64. TIM signal preprocessing (TSPP) subunit architecture

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15.2.2 Bit stream combination

The BSC subunit is used to xor-combine the three most significant bits TIM0_CHx(48) ,

TIM0_CHy(48) and TIM0_CHz(48) of the TIM0 inputs. The xor-combined signal is merged with the remaining 48 bits of one of the three input signals TIM0_CHx(47…0) ,

TIM0_CHy(47…0) or TIM0_CHz(47…0) the TSPPO signal. The selection is done with the

SPEx_NIPD_NUM input signal coming from the SPE submodule. The action, when the 49 bits are transferred to the TSPPO and the T_VALID or S_VALID signal is raised is determined by the SPEx_NIPD signal coming from the SPE submodule. The TSPPO output

signal generation is shown in the example in Figure 65 .

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Figure 65. TSPP signal generation for signal TSPPO

TIM0_CHx(48)

TIM0_CHy(48)

TIM0_CHz(48)

TIM0_CHx(47:0)

TIM0_CHy(47:0)

TIM0_CHz(47:0)

SPEx_NIPD

SPEx_NIPD_NUM(1:0)

TSPPO(48)

TSPPO(47:0)

X11,X12

Y11,Y12

Z11,Z12

00 01

X21,X22

Y21,Y22

Z21,Z22

10 t

X11,X12 t

Y11,Y12 t

Z11,Z12 t

X21,X22 t

Y21,Y22 t

Z21,Z22

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The SPEx_NIPD_NUM input signal determines, which data is routed to the TSPPO signal.

At the first edge of TIM0_CHx(48) the new data X11 and X12 are routed to TSPPO(47:0) .

The values X11 and X12 are the two 24 bit values coming from the TIM input channel

TIM0_CHx. The next edge is at time t

on signal TIM0_CHy(48) . Therefore, at time t

the

TSPPO(48) signal level changes and the TSPPO(47:0) is set to Y11 and Y12 and so forth.

15.3 MAP register overview

The following table gives an overview about the MAP registers.

Table 203. MAP registers

Register name Description

MAP_CTRL MAP control register

Details in section

15.4.1

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

000

Mode

Initial value

Bit

[28:30]

[16:26]

[12:13]

0 0 0 0

0 0 0 0 0 0

0 0

Table 204. MAP_CTRL field description

Description

TSEL

: TRIGGER signal output select.

0 = TIM0_CH0 selected as TRIGGER output signal.

TIM0_IN6 (TIM0 channel 6 input) is used as direction signal T_DIR.

1 = TSPP0_TSPPO selected as TRIGGER output signal.

SSL

: STATE signal output select.

000: TIM0_CH1 selected as STATE output signal.

001: TIM0_CH2 selected as STATE output signal.

010: TIM0_CH3 selected as STATE output signal.

011: TIM0_CH4 selected as STATE output signal.

100: TIM0_CH5 selected as STATE output signal.

101: TSPP1_TSPPO selected as STATE output signal.

110: same as '000'

111: same as '000'

LSEL : TIM0_IN6 input level selection

0 = TIM0_IN6 input level '0' encodes TRIGGER in forward direction.

1 = TIM0_IN6 input level '1' encodes TRIGGER in forward direction.

Reserved

Note: Read as zero, should be written as zero.

TSPP0_EN : Enable of TSPP0 subunit.

0 = TSPP0 disabled.

1 = TSPP0 enabled.

TSPP0_DLD : DIR level definition bit.

0 = SPEx_DIR signal is routed through as it is.

1 = SPEx_DIR signal is inverted.

Reserved

Note:

Read as zero, should be written as zero.

TSPP0_I0V

: Disable of TSPP0 TIM0_CHx(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP0 is set to zero (0).

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Bit

[4:5]

Table 204. MAP_CTRL field description (continued)

Description

TSPP0_I1V : Disable of TSPP0 TIM0_CHy(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP0 is set to zero (0).

TSPP0_I2V

: Disable of TSPP0 TIM0_CHz(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP0 is set to zero (0).

Reserved

Note:

Read as zero, should be written as zero.

TSPP1_EN : Enable of TSPP1 subunit.

0 = TSPP1 disabled.

1 = TSPP1 enabled.

TSPP1_DLD

: DIR level definition bit.

0 = SPEx_DIR signal is routed through as it is.

1 = SPEx_DIR signal is inverted.

Reserved

Note:

Read as zero, should be written as zero.

TSPP1_I0V : Disable of TSPP1 TIM0_CHx(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP1 is set to zero (0).

TSPP1_I1V

: Disable of TSPP1 TIM0_CHy(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP1 is set to zero (0).

TSPP1_I2V

: Disable of TSPP1 TIM0_CHz(48) input line.

0 = Input line enabled.

1 = Input line disabled; input for TSPP1 is set to zero (0).

Reserved

Note: Read as zero, should be written as zero.

RM0361

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16 Digital PLL module (DPLL)

Digital PLL module (DPLL)

16.1 Overview

The digital PLL (DPLL) submodule is used for frequency multiplication. The purpose of this module is to get a higher precision of position or value information also in the case of applications with rapidly changing input frequencies. There are two input signals TRIGGER and STATE for which periodic events are processed. The time period between two valid events is called an increment. Each increment is divided into a given number of sub increments pulses called SUB_INC. The resolution of the generated pulses is restricted by the period of the CMU_CLK0 clock or the TS_CLK respectively (see

Chapter 8: Clock

Management Unit (CMU) and

Chapter 9: Time Base Unit (TBU) ). The input signals

TRIGGER and STATE can have the meaning of position information of linear or angle motions, mass flow values, temperature, pressure or level of liquids.

The DPLL can reduce the load of a CPU by handling repeated or periodic standard tasks.

The DPLL is able to perform the following tasks:

 Prediction of the duration of the current increment in

Section 16.6: Prediction of the current increment duration

 Generation of SUB_INC1,2 pulses for up to 2 position counters in normal or emergency mode (see

Section 16.8.3: Sub pulse generation for SMC=0 )



Synchronization of the actual position under CPU control (see Section 16.8.6.2:

Synchronization description

)

 Possibility of seamless switch to emergency mode and back under CPU control, see

configuration register DPLL_CTRL_0 at Section 16.11

 Prediction of position and time related events in

Section 16.7

16.2 Requirements and demarcation

The two input signals TRIGGER and STATE can be sensor signals from the same device or from two independent devices. When they come from the same device the TRIGGER input is typically a more frequent signal and STATE is a less frequent signal. In such a case the

STATE signal can support an emergency mode, when no TRIGGER signal is available.

There are also applications supported when STATE and TRIGGER are independent signals from different devices. Both input signals are combined with a validation signal T_VALID or

S_VALID respectively, which shows the appearance of new data and must result in a data fetch and a start of the correspondent state machine to perform the calculations (see explanation below).

When STATE is a redundant signal of the same device only the TRIGGER input is used to generate the SUB_INC1 pulses in normal mode. There is a configuration possible, called emergency mode, for which the SUB_INC1 pulses are generated using the STATE input signal.

The decision to switch in the emergency mode and back is made outside the DPLL. The

CPU must switch the configuration bit RMO (reference mode) in the DPLL_CTRL_0 register

(see Section 16.11

). Because a switch in emergency mode can appear suddenly, the

information of the last increment durations of the STATE input up to FULL_SCALE should be stored always as a precaution.

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The filtering as well as the combination or choice of the input signals is made in the TIM submodule (see

Chapter 10: Timer Input Module (TIM)

) by use of a configurable filter algorithm for each slope and signal as well as in the MAP module (see

Chapter 15: TIM0 input mapping module (MAP)

) the right TRIGGER or STATE signal is selected by a multiplexer or in the SPE module (see

Chapter 18: Interrupt Concentrator Module (ICM) )

different signals are combined to a TRIGGER or STATE signal by using an anti-valence operation.

The filter delay value of the signal is transmitted from the TIM module in the FT part of the corresponding signal, because the delay conditions of the signals can change during application.

The filter delays depend also on the filter algorithms used. Only the effective filter delay can be considered in the DPLL.

In order to provide the timing conditions to the DPLL the input trigger signals should have a time stamp (and optional in addition a filter value and a signal level value, as stated above) with an appropriate resolution. The resolution of the time stamps can be either the same resolution as the input time base TBU_TS0 (see

Figure 67: DPLL block diagram ) or 8 times

higher, selected by configuration bits in the DPLL_CTRL_1 register (see

Section 16.11.2

The time base TBU_TS0 is used to predict events in the future, called actions.

At the SUB_INCx outputs a predefined number of pulses between each active slope of the

TRIGGER/STATE signal is generated, when the correspondent pulse generator is enabled by the enable bits SGEx=1 in the DPLL_CTRL_1 register (see

Section 16.11.2

Different strategies can be used to correct a wrong pulse number.

The FULL_SCALE range is divided into a fix number of nominal increments. Nominal increments do have the same size. The number of nominal increments in HALF_SCALE is

specified in the DPLL_CTRL_0 register (see Section 16.11

For synchronization purposes some TRIGGER / STATE input signals can be suppressed depending on the current position. Therefore an increment as duration between two valid input events can be either a nominal increment or it can consist of more than one nominal increment.

While a true nominal increment starts with a valid event a virtual increment (of always nominal size) is an increment which starts with a missing event. Each increment which represents a gap (e.g. for synchronization purposes) consists of exactly one true nominal increment and at least one virtual increment, each of them having the same nominal duration (see

Figure 66 ).

Typical input signal courses are shown in the figure below.

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Figure 66. Trigger inputs with valid high-low space

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16.4 Block and interface description

The block description of the DPLL is shown in the following figure.

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/2:B5(6

Figure 67. DPLL block diagram

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Name

TRIGGER

T_VALID

STATE

S_VALID

Table 205

summarizes the interface signals of the DPLL shown by the block diagram above.

Width I/O

Table 205. Interface description of DPLL

Description

49 I

Normal signal for triggering DPLL by positions/values

Bit(48)= TRIGGER_S

Bits(47:24)= TRIGGER_FT

Bits(23:0)= TRIGGER_TS

Comment

One bit signal value (SV), 24 bits filter delay value info and 24 bits time stamp, filtered in different modes.

1 I The values of

TRIGGER

are valid

Announces the arrival of a new

TRIGGER value

49 I

Assistance signal for synchronization

STATE(48)= STATE_S

STATE(47:24)= STATE_FT

STATE(23:0)= STATE_TS

Replacement of signal TRIGGER for emergency situations, or signal from an independent device; bits like above, corresponding

1 I The values of STATE are valid

Announces the arrival of a new

STATE value

322/558 DocID025070 Rev 1

RM0361

Name

PMTR_D

PMTR_V

ARU_CA

PMTR_RA

PMTR_RR

ACT_D

ACT_V

ACT_RA

ACT_RR

Digital PLL module (DPLL)

Table 205. Interface description of DPLL (continued)

Width I/O Description Comment

Position minus time request data, delivered by ARU on request for up to

24 requests PMTR_RR;

SV_i=PMTR_D(52:48): ACB bits, directly written to the correspondent

DPLL_ACB_j registers

PSA[i]=PMTR_D(47:24): position value for action

DLA[i]=PMTR_D(23:0) time delay value for action

Data values for calculation of actual

ACTIONs; the values are requested by AENi=1

(1)

and CAIP=0

(2)

; a served request is shown by PMTR_V which signals that valid PMTR data arrived and they are written immediately after that to the corresponding RAM regions and registers;

The DLA[i] values must have the same resolution as the TBU_TS0 input.

Signals a valid PMTR_D value, that means data is delivered on request

When valid: PMTR_D overwrites data in the PSA[i] and DLA[i] registers, also when the corresponding

ACT_N[i]

(3)

bit =1;

Channel address; for valid PMTR addresses: demand data by setting

PMTR_RR=1 when enabled by

Counter value of ARU selects PMTR_RA and PMTR_RR when a valid address

Read address of PMTR access

Read request of PMTR access; suppressed for CAIPi=1 (see

DPLL_STATUS register)

Reflects ID_PMTR_i according to the selected channel address

Reflects the value of the

corresponding AENi

(1)

bit while the correspondent bit CAIPi=0

(2)

Output of a time stamp, a position and a control signal for a calculated action;

SV_i=ACT_D(52:48): ACB bits, directly written from the correspondent

PMTR_D signals; ACT_D(47:24) is the calculated position value PSAC[i] for the action in relation to TBU_TS1 or 2

(4)

and ACT_D(23:0) is the time stamp value TSAC[i] for the action in relation

to TBU_TS0

(4)

Future time stamp with the resolution as TBU_TS0 input, additional position information and additional control bits;

ACT_D value is available and valid; blocking read access

For a valid action address: ACT_V reflects the shadow value of

ACT_N[i]

(3)

(ACT_N[i] is 1 when new PMTR values are available and the shadow register is updated, when a calculation of the actual PMTR values was done); reset after reading of the ACT_D values

I ACTION read address;

Read request of selected action

Address bits for selection of all 24 action channels

The action data is demanded from an other module

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Digital PLL module (DPLL) RM0361

Name

IRQ

SUB_INC1

SUB_INC2

SUB_INC1c

SUB_INC2c

TS_CLK

CMU_CLK0

SYS_CLK

RESET_N

LOW_RES

TBU_TS0

TBU_TS1

TBU_TS2

TDIR

Table 205. Interface description of DPLL (continued)

Width I/O Description Comment

Interrupt request output

Pulse output for TRIGGER input filter

Interrupts of DPLL;

Sub-position increment provided continuously

Pulse output for

STATE

input filter

(when TRIGGER and STATE are used for 2 independent devices)

Sub-position increment provided continuously

Pulse output for time base unit 1 in compensation mode (can stop in automatic end mode)

Sub-position increment related to

TRIGGER input

Pulse output for time base unit 2 in compensation mode (can stop in automatic end mode)

Time stamp clock

CMU clock 0

System clock

Asynchronous reset signal

Sub-position increment related to

STATE input (when TRIGGER and

STATE

are used for 2 independent devices)

Used for generation of the time stamps; this clock is used to generate the SUB_INC1,2 pulses

Used for rapid pulse correction of

SUB_INC1,2

High frequency clock

Low active;

After Reset he DPLL is available only after performing the RAM reset procedures by the DPLL hardware.

Low resolution of TBU_TS0 selected; shows witch of the 27 bits of TBU_TS0 are connected to the DPLL

LOW_RES=0: TBU_TS0(DPLL)= lower 24 Bits of TBU_TS0(TBU);

LOW_RES=1: TBU_TS0(DPLL)= higher 24 Bits of TBU_TS0(TBU);

In the case LOW_RES=1 the

TS0_HRT and/or TS0_HRS bits can be set

(5)

Actual time stamp from TBU; is needed to decide, if a calculated action is already in the past

24 bit time input, with a resolution of the time stamp clock

Actual position/value stamp 1; for calculation of position stamps

(

TRIGGER

STATE

)

24 bit pos./val. input, with a resolution of the SUB_INC1 pulses

Actual position/value stamp 2; to be implemented for an additional independent position

Ditto for SUB_INC2 for calculation of position stamps

(

STATE

) for SMC

(5)

=RMO

(6)

Direction of

TRIGGER

input values

(TDIR=0 does mean a forward direction and TDIR=1 a backward direction)

Direction information from multiple sensors valid only for SMC

IDDS

(5)

=1 or

324/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL)

Name

Table 205. Interface description of DPLL (continued)

Width I/O Description Comment

SDIR 1 I

Direction of STATE input values

(SDIR=0 does mean a forward direction and SDIR=1 a backward direction)

Direction information from multiple sensors valid only for SMC

(5)

DIR1

DIR2

Direction information of SUB_INC1

(count forwards for DIR1=0 and backwards for DIR1=1)

Direction information of SUB_INC2

(count forwards for DIR2=0 and backwards for DIR2=1)

Count direction of TBU_CH1_BASE;

DIR1 changes always after the evaluation of the corresponding valid

TRIGGER

slope and after incrementing/decrementing of the address pointer

Count direction of TBU_CH2_BASE;

DIR2 changes always after the evaluation of the corresponding valid

STATE

slope and after incrementing/decrementing of the address pointer

1. See DPLL_CTRL_x register, x=2,3,4; see

2. See DPLL_STATUS register; see

Section 16.11.30

3. See DPLL_ACT_STA register; see

Section 16.11.7

4. See DPLL input signal description; see Section 16.11.1

5. See DPLL_CTRL_1 register; see

Section 16.11.2

6. See DPLL_CTRL_0 register; see

Section 16.1

16.5.1 Purpose of the module

The DPLL generates a predefined number of incremental signal pulses within the period between two events of an input TRIGGER or STATE signal, when the corresponding pulse generator is enabled. The resolution of the pulses is restricted by the frequency of the time stamp clock (TS_CLK). Changes in the period length of the predicted time period of the current increment will result in a change of the pulse frequency in order to get the same number of pulses. This adoption can be performed by DPLL hardware, software or with support of DPLL hardware in different modes.

The major scope of a DPLL is to do a prediction of the current period between two

TRIGGER and/or STATE signal edges. Disturbances and systematic failures must be considered as well as changes of increment durations caused by acceleration and deceleration of the supervised process. Therefore, a good estimation can be done using some measuring values from the past. When a process takes a steady and differentiable course not only the current increment but also some more increments for the future can be predicted.

As already shown in Section 16.1

the DPLL has to perform different tasks. The basic

function for all these tasks is the prediction of the current increment which is based on a relation between increments in the past. Because the relation between two succeeding

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Digital PLL module (DPLL) RM0361 intervals at a fixed position remains also valid in the case of acceleration or deceleration the prediction of the duration of the current time interval is done by a similarity transformation.

Having a good estimation of the current time interval, all the other tasks can be done easily by calculations explained in

Section 16.6

All registers are read using the system clock SYS_CLK . The SUB_INC1,2 pulses generated have in the normal case the highest frequency not higher than CMU_CLK0 or the half of

TS_CLK respectively. For individual pulses the frequency can be doubled. All operations can be performed using the system clock.

The clock is generated outside the DPLL.

For the system clock a reasonable clock frequency should be applied to give the DPLL module sufficient computational power to calculate all needed values (prediction of next increment, actions) in time. The typical system clock frequency is in the range from 40 MHz up to 150 MHz.

The time stamps for the input signals TRIGGER and STATE have 24 bits each. These bits represent the value of the 24-bit free running counter running with a clock frequency selected by the configuration of the TBU. Using a typical frequency of 20 MHz the time stamp represents a relative value of time with a resolution of 50 ns.

The input signals have to be filtered. The filter is not part of the DPLL. The time stamps can have a delay caused by the filter algorithm used. There are delayed and undelayed filter algorithms available and the delay value can depend on a time or a position value.

Systematic deviations of TRIGGER inputs can be corrected by a profile, which also considers systematic missing TRIGGER s. The increments containing missing TRIGGER S are divided into the corresponding number of nominal increments whereas the duration of a nominal increment is the greatest divider of all increment durations.

For each increment this number of enclosed nominal increments is stored in a profile as NT value for TRIGGER . When the increment is a nominal increment the NT value is 1.

For the TRIGGER input the value NT is stored in the ADT_T field in RAM region 2c.

In the case of AMT

(c) = 1 the ADT_T[i] values in the RAM region 2c must also contain the adapting information for the TRIGGER signal, which considers for each increment a systematic physical deviation PD from the perfect increment value with a resolution according to the chosen value of MLT+1, which describes the number of SUB_INC1 pulses for a nominal increment.

The value PD for the TRIGGER describes the amount of missing or surplus pulses with a

13-bit signed integer value, to be added to MLT+1 directly. The correction value is in this

326/558 c. Adapt Mode for Trigger, see DPLL_CTRL_0 register; see

Section 16.11.1

DocID025070 Rev 1

RM0361 Digital PLL module (DPLL) way also applicable in the case of missing TRIGGER inputs for the synchronization gaps. In this case the amount of provided SUB_INC1 pulses for a nominal increment (MLT+1) is multiplied by NT first before the PD value is added.

The NT value of the current increment is stored in the variable SYN_T (see NUTC register in

Section 16.11.14

In the case of RMO

(d) = 1 for SMC

(e) =0 (emergency mode) the time stamp of STATE is used to generate the output signal SUB_INC1.

More inaccuracy should be accepted in emergency mode because usually there are only fewer events available for FULL_SCALE according to the value SNU

(d)

For the STATE signal the systematic deviations of the increments can be corrected in the same way as for TRIGGER by profile and adaptation information as described below.

Systematic deviations of STATE inputs can be corrected by a profile, which also considers systematic missing STATE events. The increments containing missing STATEs are divided into the corresponding number of nominal increments whereas the duration of a nominal increment is the greatest divider of all increment durations.

For each increment this number of enclosed nominal increments is stored in a profile as NS value for STATE . When the increment is a nominal increment the NS value is 1.

For the STATE input the value NS is stored in the ADT_S field in RAM region 1c3.

In the case of

AMS

(d)

= 1 the ADT_S[i] values in the RAM region 1c3 must contain the adapting information for the STATE signal, which considers for each increment a systematic physical deviation PD_S from the perfect increment value with a resolution according to the chosen value of MLS1, which describes the number of SUB_INC1 pulses for a nominal increment (see below).

The number of pulses SUB_INC1 for a nominal STATE increment in emergency mode (for

SMC=0) is given by the value of MLS1= (MLT + 1)* (TNU + 1) /(SNU + 1) in order to get the same number of pulses in FULL_SCALE for normal and emergency mode. This value has to be configured by the CPU.

The value PD_S for the STATE describes the amount of missing or surplus pulses with a 16bit signed integer value, to be added to MLS1 directly. The correction value is in this way also applicable in the case of missing STATE inputs for the synchronization gaps. In this case the amount of provided SUB_INC1 pulses for a nominal increment MLS1 is multiplied by NS first before the PD_S value is added.

The current NS value is stored in the variable SYN_S (see NUSC register in

Section 16.11.15

As shown in Figure 67 the DPLL can process different input signals. The signal

TRIGGER is the normal input signal which gives the detailed information of the supervised process. It can be for instance the information of water or other liquid level representing the volume of the liquid, where each millimeter increasing results in a TRIGGER signal generation. In order to get a predefined filling level, without overflow also the inertia of the system must be d. See DPLL_CTRL_0 register; see

Section 16.11.1

e. See DPLL_CTRL_1 register; see

Section 16.11.2

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Digital PLL module (DPLL) RM0361 taken into account. Hence, some delay for closing the inlet valve and also the remaining water amount in the pipe must be considered in order to start the closing action earlier as the filling level will be reached.

A second input signal STATE sends an additional (redundant) information for instance at some centimeters and because of intervals with different distances it also gives information about the system state with the direction of the water flow (in or out), while the TRIGGER signal must not contain information concerning the flow direction. In some applications the inactive slope of TRIGGER can be utilized to transmit the information on the current direction. In the case of faults in the TRIGGER signal the STATE signal is to be processed in order to reach the desired value nevertheless, maybe with some loss of accuracy.

The measuring scale can have some systematic failures, because not all millimeter or centimeter distances measured mean the same value. This could be due to changes in the thickness of the measuring cylinder or the inaccurate position of the marks. These systematic failures are well known by the system and for improvement of the prediction the signals ADT_T and ADT_S for the correction of the systematic failures of TRIGGER and

STATE respectively are stored in the internal RAM.

The input signals TRIGGER and STATE are represented as a time stamp signal each, which is stored in the 24 bit TS-part of the corresponding signal.

Information concerning the delay of this signal by filtering of disturbances is stored in the 24 bit FT-part of the signal.

In order to establish the relation of time stamps to the actual time the TBU_TS0 (f) value is also provided showing the actual time value used for prediction of actions in the future.

After reaching the desired water level the water is filled in a bottle by draining. After that the water filling is repeated. The water level at draining is observed by the same sensor signals

(the same number of TRIGGER pulses), but the duration of the draining could be different from the filling time. Both times together form the FULL_SCALE region, while one of them is a HALF_SCALE region, which can differ in time but not in the number of pulses, especially for TRIGGER .

For synchronization purposes some TRIGGER marks can be omitted in order to set the system to a proper synchronization value (maybe before the upper filling value is reached).

In emergency situations, when the TRIGGER signals are missed the STATE signal is used instead.

The PMTR_i (f)

signals announce the request for a position minus time calculation for up to

32 events.

All events can be activated enabling the 32 AENi (g) bits. Each of these bits are managed by the routing engine for a read access. The corresponding read request is generated by the

AENi bit while CAIPx is zero. CAIP1 and CAIP2 are two bits of the DPLL_STATUS register for 12 actions each with the meaning “calculation of actions in progress”, scheduled by the state machine (see

Section 16.2: Requirements and demarcation

When such a request is serviced by the ARU (in the case CAIPx=0) the values for position and time are written in the corresponding RAM 1a region (0x0200… 0x025C for the position value and 0x0260… 0x02BC for the delay value), the control bits for the corresponding

328/558 f.

See DPLL input signal description; see

Section 16.1

g. See DPLL_CTRL_x register, x=2,3,4; see

DocID025070 Rev 1

RM0361 Digital PLL module (DPLL) action are set accordingly. When a new PMTR value arrives, an old value is overwritten without notice and the shadow bit of ACT_N[i] is cleared while the ACT_N[i] (new action) bit in the DPLL_ACT_STA register is set.The ACT_N[i] is cleared, when the currently calculated action value is in the past. Overwriting of old information is possible without data inconsistency because the read request to ARU is suppressed during action calculations by the CAIP1,2 bits. In this way always the last possible PMTR value is used consistently.

The DPLL block diagram (see

Figure 67

) will now be explained in detail in combination with some example configurations of the control registers. There are different configuration bits available which can adopt the DPLL to the use case (see

Section 16.11

Let for example in HALF_SCALE the TRIGGER number TNU

(h)

be 0x3B (which is for

TNU+1 = 60 decimal that does mean 120 events in FULL_SCALE) and the number of

SUB_INC1 pulses between two TRIGGER

s MLT

(h)

be 0x257 (this means 600 pulses per

TRIGGER event). Than the FULL_SCALE region can be divided into 72000 parts each of them associated with its own SUB_INC1 pulse. For a run through FULL_SCALE all 72000 pulses should appear but maybe with a different pulse frequency between two TRIGGER events. For this example after each 600 pulses at the SUB_INC1 output the next TRIGGER event is to be expected with the corresponding new time stamp.

Missing SUB_INC1 pulses due to acceleration have to be taken into account within the next increment. Not one pulse has to be missed or added because of calculation inaccuracy in average for a sufficient number of FULL_SCALE periods. This means that not one pulse is sent in addition and all missing pulses are to be caught up on afterwards.

For the systematic arrangement of TRIGGER inputs the profile , as already mentioned in

Section 16.5.6

, is stored in the RAM region 2c (see

Section 16.12.3

). In this field the relative position of gaps can be stored in the NT value and also physical deviations in the PD value.

For the consideration of systematic missing TRIGGER s the actual NT value of the profile is

stored in the SYN_T bits of the NUTC register (see Section 16.11.14

In normal mode the physical deviation values PD in the ADT_T field could be used to balance the local systematic inaccuracy of the TRIGGER signal. The value of PD (see

Section 16.12.3

) is the pulse difference in the corresponding increment and does mean the number of sub pulses to be added to the nominal number of pulses. PD is a signed integer value using 13 bits: up to +/-4096 pulses can be added for each increment.

The NT value of the profile ADT_T has the value 1, when a nominal increment is assumed.

An integer number greater than 1 shows the number of nominal increments to be considered for a gap. For the actual increment after synchronization the corresponding NT value is stored in SYN_T of the NUTC register.

Using the STATE input there are similar configuration bits available (see

Section 16.11

Let for example in HALF_SCALE the STATE number SNU

(i)

be 0xB (which is for SNU+1

=12 decimal and while SYSF

(i)

=0 that does mean 24 events in FULL_SCALE). In order to

get the same number of SUB_INC1 pulses for FULL_SCALE as above for TRIGGER s the value (MLT+1)=600 is divided by 2*(SNU+1)=24 and multiplied with 2*(TNU+1)=120. The h. See DPLL_CTRL_0 register; see

Section 16.11.1

see DPLL_CTRL_0 register; see

Section 16.11.1

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Digital PLL module (DPLL) RM0361

result 3000 must be stored in MLS1 by the CPU (see Memory DPLL_MLS1: Calculated number of sub-pulses between two STATE events for SMC=0).

For the systematic arrangement of STATE inputs the profile (as already mentioned in

Section 16.5.6

is stored in the RAM region 1c3 (see

Section 16.11.94

). In this field the relative position of gaps can be stored in the NS value and also physical deviations in the

PD_S value.

For the consideration of systematic missing TRIGGER s the actual NS value of the profile is

stored in the SYN_S bits of the NUSC register (see Section 16.11.15

In emergency mode the physical deviation values PD_S in the ADT_S field could be used to balance the local systematic inaccuracy of the STATE signal. The value of PD_S (see

Section 16.11.94

) is the pulse difference in the corresponding increment and does mean the number of sub pulses to be added to the nominal number of pulses. PD_S is a signed integer value using 16 bits: up to +/-32768 pulses can be added for each increment.

The NS value of the profile ADT_S has the value 1, when a nominal increment is assumed.

An integer number greater than 1 shows the number of nominal increments to be considered for a gap. For the actual increment after synchronization the corresponding NS value is stored in SYN_S of the NUSC register.

16.5.9 Block diagrams of time stamp processing.

Figure 68. Time stamp processing for TRIGGER

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As shown in the block diagram above the time stamp difference of two succeeding input events is calculated. For the prediction of the current increment duration such values from the past are used. For this purpose the measured and calculated values of the last

330/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL)

FULL_SCALE period are stored in the RAM. For the TRIGGER input there are 4 different

RAM parts in the RAM region 2:

 2a: stores the reciprocals of each nominal increment duration RDT_T

 2b: stores the time stamps of each valid input event TSF_T

 2c: is used for the profile ADT_T and

 2d: for the nominal increment durations DT_T

Because the prediction is based on the relations of increments in the past this relation can be calculated easily by the multiplication of increment duration values with the reciprocal value of an other increment. In order not to be forced to distinguish between gaps and

"normal" increment durations also for gaps only the nominal duration and the correspondent reciprocal values are stored in the RAM field. This is possible by consideration of the NT value in the profile: the measured increment duration is divided by NT.

Figure 69. Time stamp processing for STATE

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For the STATE input there are also 4 different RAM parts in the RAM region 1c:

 1c1: stores the reciprocals of each nominal increment duration RDT_S

 1c2: stores the time stamps of each valid input event TSF_S

 1c3: is used for the profile ADT_S and

 1c4: for the nominal increment durations DT_S.

The calculations are performed similar as for the TRIGGER input. The NS value in the profile shows the appearance of a gap.

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Digital PLL module (DPLL) RM0361

The address map of the DPLL is divided into register and memory regions as defined in

Table 206

. The addresses from 0x0000 to 0x00FC are reserved for registers, from 0x0100 to 0x01FC are reserved for action registers to serve the ARU at immediately read request.

The RAM is divided into 3 independently accessible parts 1a, 1b+c and 2.

The part 1a from 0x0200 to 0x037C is used for PMTR values got from ARU and intermediate calculation values; there is no write access from the CPU possible, while the

DPLL is enabled.

The RAM 1b part from 0x0400 to 0x05FC is reserved for RAM variables and the RAM part

1c from 0x0600 to 0x09FC is used for the STATE signal values.

The RAM region 2 from 0x4000 to 0x7FFC is reserved for the TRIGGER signal values.

RAM region 1a has a size of 288 bytes, Ram 1b+c uses 1,125 Kbytes while RAM region 2 is configurable from 1,5 to 12 Kbytes, depending on the number of TRIGGER events in

FULL_SCALE. The AOSV_2 register, see

Section 16.11.9

, is used to determine the

beginning of each part.

The

Table 206

gives the DPLL address map overview.

16.5.10.1 Register and RAM address map

Registers are used to control the DPLL and to show its status. Also parameters are stored in registers when useful. The table below shows the addresses for status and control registers as well as values stored in additional registers. The register meaning explained in the

register overview ( Section 16.10

) while the bit positions of the status and control registers

are described in detail in Section 16.11

Time stamps for TRIGGER and STATE can have either the same resolution as the

TBU_TS0 input or 8 times higher. This is configured in the DPLL_CTRL_1 register (see

Section 16.11.2

). While the TBU_TS0 is used for action predictions the higher resolution of

TRIGGER and STATE inputs can be used for a more accurate pulse generation.

The time stamp fields of TRIGGER and STATE are stored in the corresponding RAM regions in such a way, that for a gap also entries for the virtual increments are provided. This is due to the necessity to calculate time differences between a given number of (real and virtual) input events independent of a gap. Therefore the gap is extended in the RAM fields

2b and 1c2.

For all other RAM regions in RAM 2 and RAM 1c the gap is considered as one increment.

For the access to the RAM fields there must be address pointers. When the device starts all address pointers have a zero value and the first measured and calculated values are stored in the beginning of the corresponding RAM field.

Because the position of the device is usually unknown at the beginning no profile information can be used. The profile regions must have their own address pointers which are set by the CPU as soon as the position is known. By setting the appropriate value to the address pointer APT_2c of the TRIGGER profile or APS_1c3 of the STATE profile respectively the synchronization bits in the DPLL_STATUS register SYT or SYS are set respectively. From now on the gap information can be used.

Because the time stamp fields are extended at the gaps there must be additional address pointers for these regions: APT_2b for TRIGGER time stamps and APS_1c2 for STATE time

332/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL) stamps. These address pointers must be incremented by NT or NS respectively when a gap appears.

Address range start

0x0000

0x100

Address range end

0x0FC

0x1FC

0x0200

0x0400

0x0600

0x09FC

0x0600

0x0700

0x0800

0x0900

0x4000

0x4200 to

5000

0x4400 to

6000

0x4600 to

7000

0x03FC

0x05FC

0x06FC

0x07FC

0x08FC

0x09FC

0x47FC to

0x7FFC

0x41FC to

4FFC

0x43FC to

5FFC

0x45FC to

6FFC

0x47FC to

7FFC

128 to

1024

128 to

1024

128 to

1024

128 to

1024

Table 206. Register and RAM address map

Value number

Byte # Content Indication

128

256

192 ACTION registers

384

PMTR values

RAM 1a used/reserved

Direct read from

ARU

CPU R/Pw access, when DPLL disabled;

ARU has highest priority

Region RAM size

1a with own ports

No RAM

RAM part

1a: 384 bytes

128 384 Variables RAM 1b

R and monitored W access by the CPU

RAM part

1b+c:

1,125

Kbytes

256

768

192

STATE

data

RDT_S[i]

TSF_S[i]

ADT_S[i]

DT_S[i]

R and monitored W access by the CPU

STATE reciprocal values

STATE

TS values adapt values of

STATE nom. STATE inc

1c1

1c2

1c3

1c4

512 to

4096

1536 to

12288

TRIGGER data

R and monitored W access of CPU

RAM part

2: 1,5 to

12 Kbytes

384 to

3072

384 to

3072

384 to

3072

384 to

3072

RDT_T[i]

TSF_T[i]

ADT_T[i]

DT_T[i]

TRIGGER

reciprocal values

TRIGGER TS values

Adapt values of

TRIGGER

Nom.

TRIGGER increments

16.5.10.2 RAM Region 1

RAM region 1 has a size of 1,5 Kbytes and is used to store variables and parameters as well as the measured and calculated values for increments of STATE . The RAM 1 region is divided into two independent accessible RAM parts (a and b+c) with own ports. The address information is shown in the table above and the detailed description is performed in the following chapters. The RAM 1a is used to store the PMTR values got from ARU and in addition some intermediate calculation results of actions. RAM region 1b is used for variables needed for the prediction of increments, while RAM 1c is used to store time

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Note:

RM0361 stamps, profile and durations for all the STATE inputs of the last FULL_SCALE region. All variables and values of RAM 1b+c part use a data width of up to 24 bits.

The RAM is to be initialized by the DPLL after HW-reset. All RAM cells must have a zero value after performing the initialize procedure. This is performed when setting The Init_RAM bit in the DPLL_RAM_INI register. The DPLL is only available after finishing this procedure.

The initialization progress is shown in the status bits of the same register.



RAM region 1a: used for storage of PMTR values got from ARU; read and write access by the CPU is only possible, when the DPLL is disabled. The CPU Address range: 0x0200 – 0x03FC



RAM region 1b: usable for intermediate calculations and auxiliary values, data width of

3 bytes used for 24 bit values;

– A write access to this region results in an interrupt to the CPU, when enabled.

– Address range: 0x0400 – 0x05FC



RAM region 1c : Values of all STATE increments in FULL_SCALE, data width of 3 bytes used for 24 bit values;

– A write access to this region results in an interrupt to the CPU, when enabled.

– Address range: 0x0600 – 0x09FC

In RAM region 1c there is a difference in the amount of data. While for the RAM regions 1c1,

1c3 and 1c4 there are 2*(SNU+1-SYN_NS) entries for SYSF=0 or 2*(SNU+1) -SYN_NS entries for SYSF=1, for the RAM region 1c2 there are 2*(SNU+1) entries (see

DPLL_CTRL_0 and DPLL_CTRL_1 registers). For the latter also the virtual events are considered, that means the gap is divided into equidistant parts each having the same position share as increments without a gap. For that reason the CPU must extend the stored

TSF_S[i] values in the RAM region 1c2 before the APS_1c3 is written. The write access to

APS_1c3 sets the SYS bit in the DPLL_Status register in order to show the end of the synchronization process. Only when the SYS bit is set the PMTR values can consider more then the last increment duration for the action prediction by setting NUSE (Number of Used

State Events, see

Section 16.11.15

) to a corresponding value.

RAM regions 1b and 1c have a common port.

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Figure 70. Address pointers for RAM regions 1c

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The address pointers for RAM region 1c are shown in the diagram above. While the address pointer APS points to the RAM regions 1c1 and 1c4, the address pointer APS_1c2 points to the time stamp field in the region 1c2. This is necessary, because in the time stamp field the gaps are extended to the number of nominal increments (see explanation above and also to the synchronization procedure explained in

Section 16.8.6.2: Synchronization description

The address pointer APS_1c3 is set by the CPU when the position is known and therefore the relation to the other address pointers is calculated. This setting of the profile address pointer synchronizes the RAM fields to one another. The synchronization is shown in the

DPLL_STATUS register (see Section 16.11.30

) by the SYS bit.

16.5.10.3 RAM Region 2

The RAM region 2 has a configurable size of 1,5 to 12 Kbytes and is used to store measured and calculated values for increments of TRIGGER . The address information is

explained in Section 16.10

while the meaning is explained in this chapter.

As there can be up to 512 TRIGGER events in half scale, the fields 2a, b c and d must have up to 1024 storage places each. For 3 Bytes word size this does mean up to 12 k Byte of

RAM region 2.

In order to save RAM size for configurations with less TRIGGER events the RAM is configurable by the offset switch Register OSW (0x001C) and the Address offset value register of RAM region 2 AOSV_2 (0x0020). The RAM is to be initialized by the DPLL after

HW-reset. All RAM cells must have a zero value after performing the initialize procedure.

The DPLL is only available after finishing this procedure.

In RAM region 2 there is a difference in the amount of data. While for the RAM regions 2a,

2c and 2d there are 2*(TNU+1-SYN_NT) entries, for the RAM region 2b there are

2*(TNU+1) entries (see DPLL_CTRL_0 and _1 registers). For the latter also the virtual

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Digital PLL module (DPLL) RM0361 events are considered, that means the gap is divided into equidistant parts each having the same position share as increments without a gap. For that reason the CPU must extend the stored TSF_T[i] values in the RAM region 2b before the APT_2c is written.

The write access to APT_2c sets the SYT bit in the DPLL_Status register in order to show the end of the synchronization process. Only when the SYT bit is set the PMTR values can consider more than the last increment duration for the action prediction by setting NUTE to a value greater than one.

Figure 71. Address pointers for RAM region 2

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The address pointers for RAM region 2 are shown in the diagram above. While the address pointer APT points to the RAM regions 2a and 2d, the address pointer APT_2b points to the time stamp field in the region 2b. This is necessary, because in the time stamp field the gaps are extended to the number of nominal increments (see explanation above and also to the synchronization procedure explained in

Section 16.8.6.2: Synchronization description

The address pointer APT_2c is set by the CPU when the position is known and therefore the relation to the other address pointers is calculated. This setting of the TRIGGER profile address pointer synchronizes the RAM fields to one another. The synchronization is shown

in the DPLL_STATUS register (see Section 16.11.30

) by the SYT bit.

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16.6 Prediction of the current increment duration

16.6.1 The use of increments in the past

16.6.1.1 Past values to be considered for the prediction of TRIGGER

In order to take into account values of increments for TRIGGER s in the past, the NUTE

value (Number of Used Trigger Events, see Section 16.11.14

) is configured to determine the

number of past values. In addition the VTN has a value according to the number of virtual increments in the NUTE region. Because gaps come in to the NUTE region or leave it the

VTN value must be updated by the CPU until NUTE is set to HALF_SCALE or

FULL_SCALE. For the RAM regions 2a and 2d the value NUTE-VTN is to be considered while for the RAM region 2b only the NUTE value is to be considered. This is due to the fact that the time stamp entries in a gap are extended to the number of nominal increments, but not to the duration entries.

16.6.1.2 Past values to be considered for the prediction of STATE

In order to take into account values of increments for STATE in the past, the NUSE (Number of Used State Events, see

Section 16.11.15

) value is configured to determine the number of past values. In addition the VSN has a value according to the number of virtual increments in the NUSE region. Because gaps come in to the NUSE region or leave it the VSN value must be updated by the CPU until NUSE is set to HALF_SCALE or FULL_SCALE. For the

RAM regions 1c1 and 1c4 in the past the value NUSE-VSN is to be considered while for the

RAM region 1c2 only the NUSE value is to be considered. This is due to the fact that time stamp entries in a gap are extended to the number of nominal increments, but not to the duration entries.

16.6.2 Increment prediction in normal mode forwards (DIR1=0)

For the prediction of increments and actions in normal mode the values are calculated as described in the following equations.

Please note, that the ascending order of calculation must be hold in order not to lose results still needed. It is important for TRIGGER values to calculate and store in the RAM region 2 all values according to equations up to

Equation 43

before

Equation 48

, Equation 49

Equation 50 , Equation 51

Equation 52 and

Equation 53

, while the last one overwrites

DT_T[i] when NUTE (see

Section 16.11.14

) is set to the FULL_SCALE range. Because the

old value of DT_T[i] is also needed for

Equations 21 and 22 to calculate the current increment (nominal value)

and equations

this value is stored temporarily at

DT_T_ACT as shown by equations

1 to 4

Equation 5

respectively until all prediction calculations are done and after that equation

Equation 48 ,

Equation 49 , Equation 50 ,

Equation 51 , Equation 52

and

Equation 53 updates DT_T[i]: update DT_T[i] after

calculations of

Equation 43

. For p = APT calculates in normal mode.

When using filter information of TRIGGER_FT, selected by IDT=1, it must be distinguished by IFP, if this filter information is time or position related.

In order to enable the automatic resolution corrections of Equation 2

(case a) the filter unit in

TIM module must operate using the time stamp clock.

16.6.2.1 Equations

to calculate TRIGGER time stamps

For calculation of time stamps use the filter delay information

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Digital PLL module (DPLL) RM0361

Equation 1

TS_T = TRIGGER_TS (unchanged for IDT = 0)

Equation 2

TS_T = TS_T - FTV_Tx (for IDT=1 and IFP=0) with

FTV_Tx = FTV_T/8 (for LOW_RES = 1 and TS0_HRT = 0)

( Equation 2:

case a)

FTV_Tx = FTV_T (for LOW_RES = 0 or TS0_HRT = 1) (

Equation 2: case b)

and

Equation 3

TS_T = TS_T - FTV_T *(CDT_TX/NMB_T)_old

(j)

for (IDT = 1 and IFP = 1)

Note:

This can be also calculated using the value of ADD_IN_CALN:

Equation 4

TS_T = TS_T - FTV_T *(1/ADD_IN_CALN_old

(j)

) for (IDT = 1 and IFP = 1)

CDT_TX is the predicted duration of the last TRIGGER increment and NMB_T the calculated number of SUB_INC1 events in the last increment, because the new calculations

are done by equations Equation 10 and

Equation 72 for the current increment after that.

Therefore in

Equation 4 the value ADD_IN of the last increment is used (see

Equation 75

SYN_T_old is the number of TRIGGER events including missing TRIGGERs as specified in the NUTC register for the last increment, with the initial value of 1.

For storage of time stamps in the RAM see also Equation 48

and following after calculation

of actions, in Equation 48 to update the time stamp values for TRIGGER .

Equation 5

DT_T_ACT = (TS_T - TS_T_OLD)/SYN_T_old

For the case SYT = 0 (still no synchronization to the profile) the values SYN_T and

SYN_T_old are still assumed as having the value 1.

Equation 6

RDT_T_ACT = 1/ DT_T_ACT

338/558 j.

Consider values, calculated for the last increment; position related filter values are only considered up to at least 1 ms time between two TRIGGER events.The reciprocal value is stored using a 32 bit fractional part, while only the 24 lower bits are used - for explanation see note 3) at DPLL_CTRL_0 register (see

Section 16.11.1: Register DPLL_CTRL_0 Control register 0 ). The value of 1/ADD_IN_CALN_old or

(CDT_TX/NMB_T)_old is set to 0xFFFFFF in the case of an overflow.

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RM0361 Digital PLL module (DPLL)

Note:

Relation of the recent last two increment values for APT = p in forward direction (DIR1 = 0)

Equation 7

QDT_T_ACT = DT_T_ACT * RDT_T[p-1]

QDT_T_ACT as well as QDT_T[i] have a 24-bit value using a 6-bit integer part and a 18-bit fractional part.

QDT_T_ACT uses a 6-bit integer part and a 18-bit fractional part.

Note:

When q = NUTE-VTN considers for the error calculation only the last valid prediction values for DIR1 = 0:

Calculate the error of the last prediction when using only RDT_T_FS1, DT_T[p-q] and

DT_T[p-1] for the prediction of DT_T[p]:

Equation 8

EDT_T = DT_T_ACT-(DT_T[p-1] * QDT_T[p-q]) with

QDT_T[p-q] = DT_T[p-q] * RDT_T[p-q-1] for FST = 0

QDT_T[p-q] = DT_T[p-q] * RDT_T_FS1 for FST = 1

( Equation 8

case a)

( Equation 8

case b) and FST has the meaning: NUTE=FULL_SCALE (see NUTC register) while

QDT_T_ACT as well as QDT_T[i] have a 24-bit value using a 6-bit integer part and a 18-bit fractional part.

QDT_T[p-q] uses a 6-bit integer part and a 18-bit fractional part.

For SYT = 1 calculate:

Equation 9

MEDT_T:= (EDT_T + MEDT_T)/2

16.6.2.7 Equations

and equation

to calculate the current increment value

Nominal increment value:

Equation 10

CDT_TX_nom = (DT_T_ACT + MEDT_T) * QDT_T[p-q+1] with:

QDT_T[p-q+1] = DT_T[p-q+1] * RDT_T[p-q] (for q > 1)

and for q = 1 use Equation 7

while

(

Equation 10 case a)

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Note:

QDT_T_ACT as well as QDT_T[i] have a 24-bit value using a 6-bit integer part and a 18-bit fractional part.

And the expected duration to the next TRIGGER event:

Equation 11

CDT_TX = CDT_TX _nom * SYN_T

QDT_T[p-q+1] uses a 6-bit integer part and a 18-bit fractional part.

In the case of an overflow in Equation 10

or Equation 11 set the value to 0xFFFFFF and the

corresponding CTO bit in the DPLL_STATUS register. In the case of negative values set

CDT_TX to 0x0 without any effect to the CTO bit.

16.6.3 Increment prediction in emergency mode forwards (DIR2=0)

Please note, that the ascending order of calculations for STATE and storage of the values in the RAM region 1c must be hold in order not to lose results still needed. The same

considerations as done for DT_T_ACT are valid for DT_S_ACT ( Equation 55

Equation 56 ,

Equation 57 ,

Equation 58

, and

Equation 59 ): update TD_S[i] only after calculations of

equation

Equation 44 .

When using filter information of STATE_FT, selected by IDS=1, it must be distinguished by

IFP, if this filter information is time or position related.

In order to enable the automatic resolution corrections of Equation 13

(case a) the filter unit in TIM must operate using the time stamp clock.

16.6.3.1 Equations to

to calculate STATE time stamps

For calculation of time stamps use the filter delay information and use p = APS while

DIR2 = 0:

Equation 12

TS_S = STATE_TS (for IDS = 0, received unchanged value)

Equation 13

TS_S = TS_S - FTV_Sx (for IDS = 1 and IFP = 0) with

FTV_Sx = FTV_S/8 (for LOW_RES = 1 and TS0_HRS = 0) (

Equation 13 case a)

FTV_Sx = FTV_S (for LOW_RES = 0 or TS0_HRS = 1)

( Equation 13

case b) and

Equation 14

TS_S = TS_S - FTV_S *(CDT_SX/NMB_S)_old

(k)

(for IDS = 1 and IFP = 1) 

340/558 k. Consider values, calculated for the last increment; position related filter values are only considered up to at least 1 ms time between two STATE events. The reciprocal value is stored using a 32 bit fractional part, while

only the 24 lower bits are used - for explanation see note 3) at DPLL_CTRL_0 register Section 16.11.1

. The

value of 1/ADD_IN_CALE_old or (CDT_SX/NMB_S)_old is set to 0xFFFFFF in the case of an overflow.

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RM0361 Digital PLL module (DPLL)

Note:

This can be also calculated using the value of ADD_IN_CALE:

Equation 15

TS_S = TS_S - FTV_S *(1/ADD_IN_CALE)_old

(k)

(for IDS = 1 and IFP = 1) with see also the

Equation 43 (case a and case b)

Section 16.6.2

for TRIGGER .

CDT_SX is the predicted duration of the last STATE increment and NMB_S the calculated number of SUB_INC1 events in the last increment, because the new calculations are done by

Equation 29

and Equation 73

respectively for the current increment after that. Therefore in

Equation 15

the value ADD_IN of the last increment is used (see Equation 77

SYN_S_old is the number of increments including missing STATEs as specified in the

NUSC register for the last increment with the initial value of 1. The update to the RAM region 1c4 is done after all related calculations (see

Equation 59 -after

Equation 43 - for this

reason).

16.6.3.2 Equation

to calculate DT_S_ACT (nominal value)

Equation 16

DT_S_ACT= (TS_S - TS_S_OLD)/SYN_S_old

For the case SYS=0 (still no synchronization to the profile) the values SYN_S and

SYN_S_old are still assumed as having the value 1.

16.6.3.3 Equation

to calculate RDT_S_ACT (nominal value)

Equation 17

RDT_S_ACT = 1/ DT_S_ACT 

16.6.3.4 Equation

to calculate QDT_S_ACT

For APS = p in forward direction (DIR2 = 0)

Note:

Equation 18

QDT_S_ACT = DT_S_ACT * RDT_S[p-1]

QDT_S_ACT as well as QDT_S[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.

QDT_S_ACT uses a 6 bit integer part and a 18 bit fractional part.



16.6.3.5 Equation

to calculate the error of last prediction

With q = NUSE-VSN when using QDT_S[p-q] and DT_S[p-1] for the prediction of DT_S[p]

Equation 19

EDT_S = DT_S_ACT - (DT_S[p-1] * QDT_S[p-q]) and with

QDT_S[p-q] = DT_S[p-q] * RDT_S[p-q-1] for FSS=0

QDT_S[p-q] = DT_S[p-q] * RDT_S_FS1 for FSS=1

( Equation 19

case a)

( Equation 19

case b)

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Digital PLL module (DPLL) RM0361

Note: and FSS has the meaning: NUSE=FULL_SCALE (see NUSC register)

QDT_S_ACT as well as QDT_S[i] have a 24-bit value using a 6-bit integer part and a 18-bit fractional part.

QDT_S[p-q] uses a 6-bit integer part and a 18-bit fractional part.

16.6.3.6 Equation

to calculate the weighted average error

For SYS = 1 calculate:

Equation 20

MEDT_S:= (EDT_S + MEDT_S)/2

16.6.3.7 Equations and

to calculate the current increment (nominal value)

Equation 21

CDT_SX_nom = (DT_S_ACT + MEDT_S) * QDT_S[p-q+1] with

QDT_S[p-q+1] = DT_S[p-q+1] * RDT_S[p-q] (for q>1)

see Equation 18

for q = 1

( Equation 21

case a) while

QDT_S_ACT as well as QDT_S[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.



Note:

And the expected duration to the next STATE event:

Equation 22

CDT_SX = CDT_SX_nom * SYN_S

QDT_S[p-q+1] uses a 6 bit integer part and a 18 bit fractional part.

In the case of an overflow in equations

Equation 21 or Equation 22 set the value to

0xFFFFFF and the corresponding CSO bit in the DPLL_STATUS register. In the case of negative values set CDT_SX to 0x0 without any effect to the CSO bit.

All 5 steps above (

Equation 12

Equation 21

) are only needed in emergency mode. For the normal mode the calculations of

Equation 12 ,

Equation 18 and Equation 19

(case a and case b) are done solely in order to get the values needed for a sudden switch to emergency mode.

16.6.4 Increment prediction in normal mode backwards (DIR1=1)

16.6.4.1 Equations to calculate QDT_T_ACT backwards

Equation 23

QDT_T_ACT = DT_T_ACT * RDT_T[p+1]

QDT_T_ACT as well as QDT_T[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.



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RM0361 Digital PLL module (DPLL)

16.6.4.2 Equation

to calculate of the error of last prediction

When q = NUTE-VTN and DIR1=1 using only QT_T[p+q] and DT_T[p+1] for the prediction of DT_T[p]

Equation 24

EDT_T = DT_T_ACT-(DT_T[p+1]*QDT_T[p+q] with

QDT_T[p+q] = DT_T[p+q] * RDT_T[p+q+1] for FST=0

QDT_T[p+q] = DT_T[p+q] * RDT_T_FS1 for FST=1

( Equation 24

case a)

( Equation 24

case b) and FST has the meaning: NUTE=FULL_SCALE (see NUTC register)

QDT_T_ACT as well as QDT_T[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.



For SYT = 1 calculate:

MEDT_T:= (EDT_T + MEDT_T)/2 (see

Equation 9 )

16.6.4.4 Equation

to calculate the current increment value

Note:

Equation 25

CDT_TX _nom = (DT_T_ACT + MEDT_T)* QDT_T[p+q-1] with

QDT_T[p+q-1] = DT_T[p+q-1] * RDT_T[p+q] (for q>1)

for q=1 use Equation 7

( Equation 25

case a)

( Equation 25

case b) while



QDT_T_ACT as well as QDT_T[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part  and the expected duration to the next TRIGGER event

Equation 26

CDT_TX = CDT_TX _nom * SYN_T

In the case of an overflow in equations

Equation 25 or

Equation 11 set the value to

0xFFFFFF and the corresponding CTO bit in the DPLL_STATUS register. In the case of negative values set CDT_TX(_nom) to 0x0.

16.6.5 Increment prediction in emergency mode backwards (DIR2=1)

16.6.5.1 Equation

to calculate QDT_S_ACT backwards

Equation 27

QDT_S_ACT = DT_S_ACT * RDT_S[p+1]

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Digital PLL module (DPLL) RM0361

QDT_S_ACT as well as QDT_S[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.

16.6.5.2 Equation

to calculate the error of the last prediction

While q = NUSE-VSN, use only QDT_S[p+q] and DT_S[p+1] for the prediction of DT_S[p]

Equation 28

EDT_S = DT_S_ACT - (DT_S[p+1] * QDT_S[p+q]) with

QDT_S[p-q] = DT_S[p+q] * RDT_S[p+q+1] for FSS=0

QDT_S[p-q] = DT_T[p+q] * RDT_S_FS1 for FSS=1

( Equation 28

case a)

( Equation 28

case b) and FSS has the meaning: NUSE=FULL_SCALE (see NUSC register)

QDT_S_ACT as well as QDT_S[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.

16.6.5.3 Equation to calculate the weighted average error

See

Equation 20 in Section 16.6.3.6: Equation 20 to calculate the weighted average error

16.6.5.4 Equations to calculate the current increment value

Note:

Equation 29

CDT_SX _nom= (DT_S_ACT + MEDT_S)* QDT_S[p+q-1] with

QDT_S[p+q-1] = DT_S[p+q-1] * RDT_S[p+q] (for q>1)

( Equation 29

case a)

for q=1 use Equation 18

. ( Equation 29

case b) while

QDT_S_ACT as well as QDT_S[i] have a 24 bit value using a 6 bit integer part and a 18 bit fractional part.

And calculate the expected duration to the next STATE event

CDT_SX = CDT_SX _nom * SYN_S

(see Equation 22

)

In the case of an overflow in equations

Equation 29 or

Equation 22 set the value to

0xFFFFFF and the corresponding CSO bit in the DPLL_STATUS register. In the case of negative values set CDT_SX(_nom) to 0x0.

All 5 steps above (

Equation 12

Equation 29

) are only needed in emergency mode. For the normal mode the calculations of equations

Equation 12 ,

Equation 18

and

Equation 19

(case a and case b) are done solely in order to get the values needed for a sudden switch to emergency mode.

16.7 Calculations for actions

As already shown for the calculation of the current interval by equations Equation 1 to

Equation 29 for the prediction of actions a similar calculation is to be done, as shown by the

equations Equation 30

to Equation 44 . The calculation of actions is also needed when the

DPLL is used for synchronous motor control applications (SMC=1, see DPLL_CTRL_1

344/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL) register). For action prediction purposes the measured time periods of the past (one

FULL_SCALE back, when the corresponding NUTE or NUSE values are set properly by the

CPU) are used. The calculation can be explained by the following assumptions, which are considerably simple.

Take the corresponding increments for prediction in the past and put the sum of it in relation to the increment (DT_T[k], DT_S[k], with k >= 0, which is represented by the time stamp difference) which is exactly one FULL_SCALE period in the past (equations in

and

respectively). Make a prediction for the coming sum of increments using the current measured increment

(DT_T_ACT or DT_S_ACT respectively, that means

Equation 5

or Equation 16 respectively)

and add a weighted average error (

Equation 8 and Equation 9 or

Equation 19 and

Equation

20 respectively, calculated for one increment prediction) before multiplication with the

relation of equations in

respectively in order to get the result as described by Equation 34 or

Equation 44 respectively.

In order to avoid division operations instead of the increment (DT_T[k], DT_S[k], with k > 0) in the past its reciprocal value (RDT_T[k], RDT_S[k], with k > 0) is used, which is stored also in RAM. For the calculation of actions perform always a new refined calculation as long as the resulting time stamp is not in the past. In the other case the tsac/psac values

(time/position stamp of action calculated) is set to the time/position stamp of the last input event (TRIGGER/STATE), the ACT_N[i] bit in the DPLL_ACT_STA register is reset, while the corresponding ACT_N[i] bit in the DPLL_ACT_STA_shadow register is set. Each new

PMTR_i value will set this ACT_N[i] bit again and reset the correspondent shadow bit until a new calculation is performed.

Action updates at highest speed

Up to 32 action values can be calculated. For the shortest increment durations (23,4 µs) not all of them can be updated with each valid input event. Please notice the following conditions and parameters for an estimation of possible results.

All time estimation values are given for a system clock frequency of 100 MHz and the assumption, that the calculation of the DPLL is not impeded by a remote read or write access to the DPLL RAMs. Each RAM access is to be considered by an additional delay of about 40 ns (t remote_RAM_acces

, to be precised later). When using a different system clock frequency the calculation duration is extended accordingly.

Typical time needed for basic operations (RAM update, pointer calculation and

SUB_INC generation for normal, emergency mode or one PMSM:  t basic_0

= 9.9 µs.

2. Typical time needed basic operations (RAM update, pointer calculation and SUB_INC generation for two PMSMs:  t basic_1

= 11.0 µs.

3. Typical time needed to calculate one action  t action_i

= 3.7 µs.

Please notice that the above mentioned values are observed worst case values, when the two state machines of TRIGGER and STATE are both in operation.

These values allow the calculation of at least 3 action values for each input event for all specified increment durations. The complete time needed for the basic operation, n action calculations and k remote RAM access operations can be calculated as follows

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= t basic_0/1

+ n*t action_i

+ k*t remote_RAM_access

RM0361

Typical applications

Normal and emergency mode

For a typical application with the shortest increment duration of 100 µs in normal or emergency mode the calculation of up to 24 action values can be performed for each valid input event.

One PMSM

For one PMSM and a typical shortest increment time of 39 µs there is the calculation of up to 7 action values possible for each input event.

Two PMSMs with restricted action calculations

When only one PMSM uses the action calculation service an the shortest increment duration is 39 µs, there can up to 7 actions served for each valid input event.

Two PMSMs with unrestricted action calculations

When 2 PMSMs are used and both use the action calculation service at a minimal increment duration of 39 µs there are up to 7 action calculations possible for each of the two engines - that means up to 14 action calculations per increment in average.

Valid for RMO = 0 or for SMC = 1 with

 p = APT_2b

 t = APT

 m = NA[i] (part w)

 mb = NA[i](part b)/1024

 NUTE-VTN = q

 NUTE = n

16.7.1.1

Equation 30

to calculate the time prediction for an action

For DIR1=0 and q>m calculate:

Equation 30

PDT_T[i] = (TSF_T[p+m-n] - TSF_T[p-n] + mb * DT_Tx[t-q+1]) * RDT_T[t-q] with

DT_Tx[t-q+1] = DT_T[t-q+1] for TS0_HRT=0 (

Equation 30 case a)

DT_Tx[t-q+1] = DT_T[t-q+1]/8 for TS0_HRT=1 (

Equation 30 case b)

and while the multiplication with mb does mean the fractional part of NA[i].

For SMC=0 and RMO=0 calculate for DIR1=0 all 32 actions in forward direction, if requested; in the case SMC=1 calculate up to 16 actions 0 to 15 depending on the

TRIGGER input.

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16.7.1.2

Equation 31

to calculate the time prediction for an action

For SYT = 1, NUTE = 2*(TNU+1), q>m and DIR1=0 Equation 31

is equal to

Equation 31

PDT_T[i] = (TSF_T[p+m] - TSF_T[p]+ mb* DT_Tx[t-q+1]) * RDT_T[t] with

DT_Tx[t-q+1] = DT_T[t-q+1] for TS0_HRT=0 (see

Equation 30

case a) or

DT_Tx[t-q+1] = DT_T[t-q+1]/8 for TS0_HRT=1 (see

Equation 30

case b)

16.7.1.3

Equation 32

to calculate the time prediction for an action

For DIR1 = 0, NUTE-VTN = q, q (< or =) m, n>1 and t=APT:

Note:

Equation 32

PDT_T[i] = (m+mb)*DT_Tx[t-q+1] * RDT_T[t-q] with

DT_Tx[t-q+1] = DT_T[t-q+1] for TS0_HRT=0 or

DT_Tx[t-q+1] = DT_T[t-q+1]/8 for TS0_HRT=1

(see

Equation 30

case a)

(see

Equation 30

case b)

Make the calculations above before updating the TSF_T[i] values according to equations 48

51 .

16.7.1.4

Equation 33

to calculate the time prediction for an action

For n = 1 (this is always valid for SYT = 0)

Note:

Equation 33

PDT_T[i] = (m+mb)* DT_T_ax* RDT_T[t-1] with

DT_T_ax = DT_T_ACT for TS0_HRT=0 or

DT_T_ax = DT_T_ACT/8 for TS0_HRT=1

(

Equation 33 case a)

(

Equation 33 case b)

For the relevant last increment add the fractional part of DT_T_ACT as described in NA[i].

16.7.1.5

Equation 34

to calculate the duration value until action

Note:

Equation 34

DTA[i] = (DT_T_ACT + MEDT_T)* PDT_T[i]

All 5 steps in equations

Equation 30

Equation 34 are only calculated in normal mode.

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Valid for RMO = 0 or for SMC = 1 with

 p = APT_2b

 t = APT

 m = NA[i] (part w)

 mb = NA[i](part b)/1024

 q = NUTE-VTN and

 n = NUTE

For SMC=0 and RMO=0 calculate for DIR1=1 all 32 actions in backward direction for special purposes; in the case SMC=1 calculate up to 16 actions 0 to 15 depending on the

TRIGGER input.

16.7.2.1

Equation 35

to calculate the time prediction for an action

For DIR1 = 1 and q > m calculate:

Equation 35

PDT_T[i] = (TSF_T[p-m+n] - TSF_T[p+n] + mb * DT_Tx[t+q-1]) * RDT_T[t+q] with

DT_Tx[t+q-1] = DT_T[t+q-1] for TS0_HRT=0 (

Equation 35 case a)

DT_Tx[t+q-1] = DT_T[t+q-1]/8 for TS0_HRT=1 (

Equation 35 case b)

16.7.2.2

Equation 36

to calculate the time prediction for an action

For SYT = 1 and NUTE = 2*(TNU+1), q>m, VTN = 2*SYN_NT and hence 

NUTE-VTN = 2 *(TNU + 1 - SYN_NT) for DIR1 = 1 this is equal to

Note:

Equation 36

PDT_T[i] = (TSF_T[p-m] - TSF_T[p]+ mb* DT_Tx[t+q-1]) * RDT_T[t] with

DT_Tx[t+q-1] = DT_T[t+q-1] for TS0_HRT=0 or

(see

Equation 35

case a)

DT_Tx[t+q-1] = DT_T[t+q-1]/8 for TS0_HRT=1 (see

Equation 35

case b)

Make the calculations above before updating the TSF_T[i] values according to equations 48

51 .

16.7.2.3

Equation 37

to calculate the time prediction for an action

For NUTE-VTN = q, q  m the following equation is valid for n > 1 and t = APT:

Equation 37

PDT_T[i] = (m+mb)*DT_Tx[t+q-1] * RDT_T[t+q] with

DT_Tx[t+q-1] = DT_T[t+q-1] for TS0_HRT=0 (see

Equation 35

case a)

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DT_Tx[t+q-1] = DT_T[t+q-1]/8 for TS0_HRT=1 (see

Equation 35

case b)

16.7.2.4

Equation 38

to calculate the time prediction for an action

For n = 1 (this is always valid for SYT = 0)

Note:

Equation 38

PDT_T[i] = (m+mb)* DT_T_ax * RDT_T[t+1] with

DT_T_ax = DT_T_ACT for TS0_HRT=0 or

DT_T_ax = DT_T_ACT/8 for TS0_HRT=1

(see

Equation 33

case a)

(see

Equation 33

case b)

For the relevant last increment add the fractional part of DT_T_ACT as described in NA[i].

16.7.2.5

Equation 34

to calculate the duration value for an action

DTA[i] = (DT_T_ACT + MEDT_T)* PDT_T[i]

Use the results of equations

and

for the above calculation.

Note: All 5 steps in equations

30 to

are only calculated in normal mode or when SMC=1.

16.7.3 Action calculations for STATE forwards

Valid for RMO=1 with

 p = APS_1c2

 t = APS

 m = NA[i](part w)

 mb = NA[i](part b)/1024

 NUSE-VSN = q and NUSE = n > m

For SMC = 0 and RMO = 1 calculate for DIR2=0 all 32 actions in forward direction, if requested; in the case SMC = 1 and RMO = 1 calculate up to 16 actions 16 to 31 depending on the STATE input.

16.7.3.1

Equation 39

to calculate the time prediction for an action

For DIR2 = 0 and q > m calculate:

Equation 39

PDT_S[i] = (TSF_S[p+m-n] - TSF_S[p-n] + mb* DT_Sx[t-q+1] * RDT_S[t-q] with

DT_Sx[t-q+1]= DT_S[t-q+1] for TS0_HRS=0 or

(

Equation 39 case a)

DT_Sx[t-q+1] = DT_S[t-q+1]/8 for TS0_HRS=1 (

Equation 39 case b)

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16.7.3.2

Equation 40

to calculate the time prediction for an action

For SYS = 1 and NUSE = 2*(SNU+1), q > m, SYSF = 0, VSN = 2*SYN_NS and hence

NUSE-VSN = 2*(SNU+1-SYN_NS)

Equation 39 is equal to

Equation 40

PDT_S[i] = (TSF_S[p+m] - TSF_S[p]+ mb*DT_Sx[t-q+1]) * RDT_S[t] with

DT_Sx[t-q+1] = DT_S[t-q+1] for TS0_HRS = 0 (see

Equation 39

case a) or

DT_Sx[t-q+1] = DT_S[t-q+1]/8 for TS0_HRS = 1 (see

Equation 39

case b)

16.7.3.3

Equation 41

to calculate the time prediction for an action

For NUSE -VTN = q, q  m and n > 1:

Equation 41

PDT_S[i] = (m+mb)*DT_Sx[t-q+1] * RDT_S[t-q] with

DT_Sx[t-q+1] = DT_S[t-q+1] for TS0_HRS = 0 or

DT_Sx[t-q+1] = DT_S[t-q+1]/8 for TS0_HRS = 1

(see

Equation 39

case a)

(see

Equation 39

case b)

16.7.3.4

Equation 42

to calculate the time prediction for an action

For n = 1

Equation 42

PDT_S[i] = (m+mb)* DT_S_ax * RDT_S[t-1] with

DT_S_ax = DT_S_ACT for TS0_HRS=0 or

DT_S_ax = DT_S_ACT/8 for TS0_HRS=1

(

Equation 42 case a)

(

Equation 42 case b)

16.7.3.5

Equation 43

to calculate the duration value for an action

Note:

Equation 43

DTA[i] = (DT_S_ACT + MEDT_S)* PDT_S[i]

Use the results of

Equation 18 , Equation 19

and Equation 20

for the above calculation.

All 5 steps of equations

Equation 39 to

Equation 43

are only calculated in emergency mode or for SMC=1 in combination with RMO=1.

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RM0361 Digital PLL module (DPLL)

16.7.4 Action calculations for STATE backwards

Valid for RMO=1 with

 p = APS_1c2

 t = APS

 m = NA[i](part w)

 mb = NA[i](part b)/1024

 NUSE-VSN = q and NUSE = n

For SMC = 0 and RMO = 1 calculate for DIR1 = 1 all 32 actions in backwards mode for special purposes; in the case SMC = 1 and RMO = 1 calculate up to 16 actions 16 to 31 depending on the STATE input.

16.7.4.1

Equation 44

to calculate the time prediction for an action

For (DIR2 = 1 (SMC = 1) or DIR1 = 1 (SMC = 0)) and q > m calculate

Equation 44

PDT_S[i] = (TSF_S[p-m+n] - TSF_S[p+n] + mb* DT_Sx[p+q-1]) * RDT_S[t+q] with

DT_Sx[p+q-1] = DT_S[p+q-1] for TS0_HRS = 0 or

(

Equation 44 case a)

DT_Sx[p+q-1] = DT_S[p+q-1]/8 for TS0_HRS = 1 (

Equation 44 case b)



16.7.4.2

Equation 45

to calculate the time prediction for an action

For SYS = 1, NUSE = 2*(SNU+1), q > m, SYSF = 0, VSN = 2*SYN_NS and hence 

NUSE-VSN = 2*(SNU+1-SYN_NS)

Equation 44 is equal to

Equation 45

PDT_S[i] = (TSF_S[p-m] - TSF_S[p]+ mb* DT_Sx[p+q-1]) * RDT_S[t] with

DT_Sx[p+q-1]= DT_S[p+q-1] for TS0_HRS=0

(see Equation 44

case a) or

DT_Sx[p+q-1] = DT_S[p+q-1]/8 for TS0_HRS=1

(see Equation 44

case b) 

16.7.4.3

Equation 46

to calculate the time prediction for an action

For NUSE-VSN = q, q  m, NUSE = n and n > 1:

Equation 46

PDT_S[i] = m*DT_Sx[t+q-1] * RDT_S[t+q] with

DT_Sx[p+q-1] = DT_S[t+q-1] for TS0_HRS = 0 (see

Equation 44

case a)

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DT_Sx[p+q-1] = DT_S[t+q-1]/8 for TS0_HRS = 1

(see Equation 44

case b) 

RM0361

16.7.4.4

Equation 47

to calculate the time prediction for an action

For n = 1

Equation 47

PDT_S[i] = (m+mb)* DT_S_ax * RDT_S[t+1] with

DT_S_ax = DT_S_ACT for TS0_HRS=0 or

DT_S_ax = DT_S_ACT/8 for TS0_HRS=1

(see

Equation 42

case a)

(see

Equation 42

case b)

16.7.4.5

Equation 43

to calculate the duration value until action

Note:

DTA[i] = (DT_S_ACT + MEDT_S)* PDT_S[i] (see

Equation 43 )

Use the results of

Equation 18 , Equation 19

and Equation 20

for the above calculation

All 5 steps of equations

Equation 39 to

Equation 43

are only calculated in emergency mode or for SMC = 1 in combination with RMO = 1.

16.7.5 Update of RAM in normal and emergency mode

After considering the calculations for up to all 24 actions according to equations in sections

16.7.1

16.7.2

, only when going back to state 1 or

21 (because of a new TRIGGER or STATE event, that means when no further PMTR values are to be considered) set time stamp values and durations of increments in the RAM.

16.7.5.1

Equation 48

to update the time stamp values for TRIGGER

Equation 48

TSF_T[s] = TS_Tx

Using the following equations for the determination of TS_Tx

For TS0_HRT = 0:

TS_Tx=TS_T

DT_T_ax = DT_T_ACT

(

Equation 48 case a)

(see

Equation 33

case a) 

For TS0_HRT = 1:

TS_Tx(20:0) = TS_T/8

( Equation 48

case b)

TS_Tx(23:21)=TBU_TS0_T(23:21) (

Equation 48 case c),

for TBU_TS0_T(20:0)  TS_Tx(20:0)

TS_Tx(23:21)=TBU_TS0_T(23:21) -1 (

Equation 48 case d),

for TBU_TS0_T(20:0) < TS_Tx(20:0)

DT_T_ax = DT_T_ACT/8 (see

Equation 33 case b)

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RM0361 Digital PLL module (DPLL)

Note: The combination of values LOW_RES=0 and TS0_HRT=1 is not possible.

Store the time stamp values in the time stamp field according to the address pointer

APT_2b = s, but make this update only after the calculation of actions (see

Section 16.7

)

because the old TSF_T[i] values are still needed for these calculations. Please note that the address pointer after a gap is still incremented by SYN_T_old in that case (see state machine step 1 in

Section 16.8.6

16.7.5.2

Equation 49

-

Equation 51

to extend the time stamp values for TRIGGER in forward direction

When SYT = 1 and SYN_T_old = r>1 and DIR1 = 0

Equation 49

TSF_T[s-1] = TSF_T[s] -DT_T_ax

Equation 50

TSF_T[s-2] = TSF_T[s-1] -DT_T_ax until

Equation 51

TSF_T[s- r+1] = TSF_T[s- r+2] -DT_T_ax after the incrementation of the pointer APT_2b by SYN_T_old 

16.7.5.3

Equation 49

-

Equation 51

for backward direction

When SYT = 1 and SYN_T_old = r>1 and DIR1 = 1

TSF_T[s+1] = TSF_T[s] -DT_T_ax until

TSF_T[s+2] = TSF_T[s+1] -DT_T_ax

TSF_T[s+r-1] = TSF_T[s+r-2] -DT_T_ax after the decrementation of the pointer APT_2b by SYN_T_old

16.7.5.7

Equation 52

and

Equation 53

to update the RAM after calculation

Equation 52

DT_T[p] = DT_T_ACT save old reciprocal value from RAM before overwriting:

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Digital PLL module (DPLL) RM0361

Equation 53

RDT_T_FS1= RDT_T[p] after that store new value in RAM

Equation 54

RDT_T[p] = RDT_T_ACT

Store increment duration and reciprocal value in RAM region 2 in normal mode after calculation of actions only when a new valid TRIGGER slope is detected and in emergency mode directly after calculation of DT_T_ACT or RDT_T_ACT respectively.



16.7.5.8

Equation 55

to update the time stamp values for STATE

Equation 55

TSF_S[s] = TS_Sx

Using the following equations for the determination of TS_Sx

For TS0_HRS = 0:

TS_Sx = TS_S

DT_S_ax = DT_S_ACT

(Equation

)

(see

Equation 42

case a) 

Note:

For TS0_HRS = 1:

TS_Sx(20:0) = TS_S/8

TS_Sx(23:21) = TBU_TS0_S(23:21) for TBU_TS0_S(20:0) > or = TS_Sx(20:0)

TS_Sx(23:21) = TBU_TS0_S(23:21) -1 for TBU_TS0_S(20:0) < TS_Sx(20:0)

DT_S_ax = DT_S_ACT/8

(

case b),

case c),

(see

Equation 42

case b)

The combination of values LOW_RES=0 and TS0_HRS=1 is not possible.

Store the time stamp value in the time stamp field according to the address pointer

APS_1c2=s, but make this update only after the calculation of actions ( Equation 40

Equation 45 , if applicable) because the old TSF_S[i] values are still needed for these

calculations. Please note, that the address pointer after a gap is still incremented by

SYN_S_old in that case (see state machine step 21 in Section 16.8.6: Scheduling of the calculation ).

16.7.5.9

Equation 56

-

Equation 58

to extend the time stamp values for STATE

When SYS = 1 and SYN_S_old = r > 1 and DIR2 = 0 or DIR1 = 0 respectively calculate

Equation 56

TSF_S[s-1] = TSF_S[s] - DT_S_ax

Equation 57

TSF_S[s-2] = TSF_S[s-1] - DT_S_ax until

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Equation 58

TSF_S[s- r+1] = TSF_S[s- r+2] - DT_S_ax after incrementation of the pointer APS_2b by SYN_S_old

16.7.5.10

Equation 56

-

Equation 58

for backward direction

When SYS = 1 and SYN_S_old = r>1 and DIR2 = 1 or DIR1 = 1 respectively calculate

TSF_S[s+1] = TSF_S[s] - DT_S_ax until

TSF_S[s+2] = TSF_S[s+1] - DT_S_ax

TSF_S[s+r-1] = TSF_S[s+r-2] - DT_S_ax after the incrementation of the pointer APS_1c2 by SYN_S_old

16.7.5.14

Equation 59

to

Equation 61

to update the RAM after calculation

Equation 59

DT_S[p] = DT_S_ACT save old reciprocal value from RAM before overwriting:

Equation 60

RDT_S_FS1= RDT_S[p] after that store new value in RAM

Equation 61

RDT_S[p] = RDT_S_ACT when a new valid STATE slope is detected in emergency mode or in normal mode

(SMC=RMO=0) directly after calculation of the values above.

Store increment duration and reciprocal value in RAM region 1c in emergency mode after calculation of actions only when a new valid STATE slope is detected and in normal mode directly after calculation of DT_S_ACT or RDT_S_ACT respectively.

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16.7.6 Time and position stamps for actions in normal mode

16.7.6.1 Equations (cases a, case b and case c) to calculate the action time stamp

Note:

Equation 62

TSAC[i] = DTA[i] - DLA[i] + TS_Tx

(for DTA[i] > DLA[i] and DTA[i] - DLA[i] < 0x800000)

TSAC[i]= TS_Tx

(for DTA[i] < DLA[i])

TSAC[i] = 0x7FFFFF + TS_Tx

(for DTA[i] > DLA[i] and DTA[i] - DLA[i] > 0x7FFFFF)

(Equation

case a),

case b)

case c),

For TS_Tx see Equation 48 to update the time stamp values for TRIGGER and following.

The calculation is done after the calculation of the current expected duration value according to

Equation 34

Equation 34 to calculate the duration value for an action . The

time stamp of the action can be calculated as shown above in Equation 62

using the delay value of the action and the current time stamp.

16.7.6.2

Equation 63

and

to calculate the position stamp forwards

For DIR1 = 0 and TS0_HRT = 0 :

Equation 63

PSAC[i] = PSA[i] - (DLA[i]*RCDT_TX_NOM)*(MLT+1) with

RCDT_TX_NOM= RCDT_TX * SYN_T and

RCDT_TX= 1/CDT_TX

( Equation 63

case a)

( Equation 63

case b)

For DIR1 = 0 and TS0_HRT = 1 :

Equation 64

PSAC[i] = PSA[i] - (8*DLA[i]*RCDT_TX_NOM)*(MLT+1) with

RCDT_TX_NOM= RCDT_TX * SYN_T and

(see

Equation 63

case a)

RCDT_TX= 1/CDT_TX (see

Equation 63

case b)

Replace (MLT+1) in Equation 63 and Equation 64

by MLS1 for SMC=1.

Use the calculated value of Equation 63

(case b) also for the generation of SUB_INCi and serve the action by transmission of TSAC[i] and PSAC[i] to ACT_D_i.

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RM0361 Digital PLL module (DPLL) the corresponding shadow bit in the DPLL_ACT_STA register. Because of the blocking read operation the ACT_D values can be read only once.

16.7.6.3

Equations

65 and 66

to calculate the position stamp backwards

For DIR1=1 and TS0_HRT=0:

Equation 65

PSAC[i] = PSA[i] + (DLA[i]*RCDT_TX_NOM)*(MLT+1) with

RCDT_TX_NOM= RCDT_TX * SYN_T and

(see

Equation 63

case a)

RCDT_TX= 1/CDT_TX (see

Equation 63

case b)

For DIR1=1 and TS0_HRT=1:

Equation 66

PSAC[i] = PSA[i] + (8*DLA[i]*RCDT_TX_NOM)*(MLT+1) with

RCDT_TX_NOM= RCDT_TX * SYN_T and

(see

Equation 63

case a)

RCDT_TX= 1/CDT_TX (see

Equation 63

case b)

Replace (MLT+1) in Equation 65 and Equation 66

by MLS1 for SMC=1

Use the calculated value of Equation 63

(case b) also for the generation of SUB_INCi and serve the action by transmission of TSAC[i] and PSAC[i] to ACT_D_i

The action is to be updated for each new TRIGGER event until the calculated time stamp is in the past.In this case use the time stamp of the last input event instead of the calculated value and the calculated position stamp of the actual increment as target position value. Set the corresponding shadow bit in the DPLL_ACT_STA register. Because of the blocking read operation the ACT_D values can be read only once.

16.7.7 The use of the RAM

The RAM is used to store the data of the last FULL_SCALE period. The use of single port

RAMs is recommended. The data width of the RAM is usual 3 bytes, but could be extended to 4 bytes in future applications. There are 3 different RAMs, each with separate access ports. the RAM 1a is used to store the position minus time requests, got from the ARU. No

CPU access is possible to this RAM during operation (when the DPLL is enabled).

Ram 1b is used for configuration parameters and variables needed for calculations. Within

RAM 1c the values of the STATE events are stored. RAM 1b and RAM 1c do have a common access port and are also marked as RAM 1bc in order to clarify this fact.

RAM 2 is used for values of the TRIGGER events.

Because of the access of the DPLL internal state machine at the one side and the CPU at the other side the access priority has to be controlled for both RAMs 1bc and 2. The access

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Digital PLL module (DPLL) RM0361 priority is defined as stated below. The CPU access procedure via AE-interface goes in a wait state (waiting for data valid) while it needs a colliding RAM access during serving a corresponding state machine RAM access. In order not to provoke unexpected behavior of the algorithms the writing of the CPU to the RAM regions 1b, 1c or 2 will be monitored and results in interrupt requests when enabled.

CPU access is specified at follows:

CPU has the highest priority for a single read/write access. The DPLL algorithm is stalled during external bus RAM accesses.

2. After serving the CPU access to the RAM the DPLL gets the highest RAM access priority for 8 clock cycles. Afterwards continue with 1.

The RAM address space has to be implemented in the address space of the CPU.

16.7.8 Time and position stamps for actions in Emergency Mode

16.7.8.1 Equations (case a, case b and case c) to calculate the action time stamp

Note:

Equation 67

TSAC[i] = DTA[i] - DLA[i] + TS_Sx for DTA[i] > DLA[i] and DTA[i] - DLA[i] < 0x800000

TSAC[i] = TS_Sx for DTA[i] < DLA[i]

TSAC[i] = 0x7FFFFF + TS_Sx for DTA[i] > DLA[i] and DTA[i] - DLA[i] > 0x7FFFFF

(

( Equation 67

Equation 67

case a),

case b),

case c),

For TS_Sx see Equation 42

and following in

Equation 55 to update the time stamp values for STATE .

The calculation is done after the calculation of the current expected duration value according to

Equation 43 at Section 16.7.3.5: Equation 43 to calculate the duration value for an action

. The time stamp of the action can be calculated as shown in Equation 67

using the delay value of the action and the current time stamp.

16.7.8.2

Equation 68

and

Equation 69

to calculate the position stamp forwards

For DIR2=0 or DIR1=0 respectively and TS0_HRS=0:

Equation 68

PSAC[i] = PSA[i] - (DLA[i]*RCDT_SX_NOM)*MLS1 with

RCDT_SX_NOM= RCDT_SX * SYN_S and

RCDT_SX= 1/CDT_SX

( Equation 68

case a)

( Equation 68

case b)

For DIR2=0 or DIR1=0 respectively and TS0_HRS=1:

Equation 69

PSAC[i] = PSA[i] - (8*DLA[i]*RCDT_SX_NOM)*MLS1

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RM0361 Digital PLL module (DPLL) with

RCDT_SX_NOM= RCDT_SX * SYN_S and

RCDT_SX= 1/CDT_SX

(see

Equation 68

case a) case b)

Replace MLS1 in Equation 68

and

Equation 69 by MLS2 for (SMC=1 and RMO=1)

Use the calculated value of Equation 68

( case b) also for the generation of SUB_INCi. and serve the action by transmission of TSAC[i] and PSAC[i] to ACT_D.

The action is to be updated for each new STATE event until the event is in the past. In this case use the time stamp of the last input event instead of the calculated value and the calculated position stamp of the actual increment as target position value. Set the corresponding shadow bit in the DPLL_ACT_STA register. Because of the blocking read operation the ACT_D values can be read only once.



16.7.8.3

Equation 70

and

Equation 71

to calculate the position stamp backwards

For DIR2=1 or DIR1=1 respectively and TS0_HRS=0:

Equation 70

PSAC[i] = PSA[i] + (DLA[i]*RCDT_SX_NOM)*MLS1 with

RCDT_SX_NOM= RCDT_SX * SYN_S and

(see

Equation 68

case a)

RCDT_SX= 1/CDT_SX (see

Equation 68

case b)

For DIR2=1 or DIR1=1 respectively and TS0_HRS=1:

Equation 71

PSAC[i] = PSA[i] + (8*DLA[i]*RCDT_SX_NOM)*MLS1 with

RCDT_SX_NOM= RCDT_SX * SYN_S (see

Equation 68

case a) and

RCDT_SX= 1/CDT_SX (see

Equation 68

case b)

Replace MLS1 in Equation 70

and

Equation 71 by MLS2 for (SMC = 1 and RMO = 1).

Use the calculated value of Equation 68

( case b ) also for the generation of SUB_INCi. and serve the action by transmission of TSAC[i] and PSAC[i] to ACT_D.

The action is to be updated for each new STATE event until the event is in the past.In this case use the time stamp of the last input event instead of the calculated value and the calculated position stamp of the actual increment as target position value. Set the corresponding shadow bit in the DPLL_ACT_STA register. Because of the blocking read operation the ACT_D values can be read only once.

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Signal processing does mean the computation of the time stamps in order to calculate at which time the outputs have to appear. For such purposes the time stamp values have to be stored in the RAM and by calculating the difference between old and new values the duration of the last time interval is determined simply. This difference should be also stored in the RAM in order to see the changes between the intervals by changing the conditions and the speed of the observed process.

16.8.2 Count and compare unit

The count and compare unit processes all input signals taking into account the configuration values. It uses a state machine and provides the output signals as described above.

16.8.3 Sub pulse generation for SMC=0

16.8.3.1

Equation 72

to calculate the number of pulses to be sent in normal mode using the automatic end mode condition

For RMO = 0, SMC = 0 and DMO = 0

Equation 72

NMB_T = (MLT+1)*SYN_T + MP + PD_store + MPVAL1 with:

 PD_store = ADT_T[12:0], prefetched during last increment

 SYN_T = ADT_T[18:16], prefetched during last increment

 MPVAL1 = pulse correction value for PCM1_SHADOW_TRIGGER=1 while:

 the value for PD_store is zero for AMT=0 and

 the value of MP is zero for COA=0

In order to get a higher resolution for higher speed a generator for the sub-pulses is chosen using an adder. All missing pulses MP are considered using

Equation 72 and are

determined by counting the number of pulses of the last increment. The value SYN_T is stored from the last increment using NT of the ADT_T[i] value at RAM region 2c.

16.8.3.2

Equation 73

-

Equation 74

to calculate the number of pulses to be sent in emergency mode using the automatic end mode condition for SMC=0

For RMO=1, SMC=0 and DMO=0; the value for PD_S_store is zero for AMS=0

Equation 73

NMB_S = MLS1 *SYN_S+ MP + PD_S_store with

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Equation 74

MLS1= (MLT+1) * (TNU+1) / (SNU+1)

 PD_S_store = ADT_S[15:0], prefetched during the last increment

 SYN_S = ADT_S[21:16], prefetched during the last increment

 MPVAL1 = pulse correction value for PCM1_SHADOW_STATE=1 while the value for PD_S_store is zero for AMS=0 and the value of MP is zero for COA=0

Please note, that these calculations above in

Equation 72 and Equation 73 are only valid for

an automatic end mode (DMO = 0).

For calculation of the number of generated pulses a value of 0.5 is added as shown in

Equation 75

Equation 77

respectively in order to compensate rounding down errors at the succeeding arithmetic operations. Because in automatic end mode the number of pulses is limited by INC_CNT1, it is guaranteed, that the right number of pulses is generated and in the same way missing pulses are caught up for the next increment.



16.8.3.3

Equation 75

to calculate ADD_IN in normal mode for SMC=0

In normal mode (for RMO=0) calculate, in the case LOW_RES=TS0_HRT

Equation 75

ADD_IN_CALN= (NMB_T+0.5) *RCDT_TX with

RCDT_TX is the 2

32 time value of the quotient in

Equation 63 (case b) (see

Section 16.7.6.3: Equations 65 and 66 to calculate the position stamp backwards ).



In normal mode (for RMO=0) calculate, in the case LOW_RES=1 and TS0_HRT=0

ADD_IN_CALN= (NMB_T+0.5) *(RCDT_TX /8) (

Equation 75 case a)

with

RCDT_TX is the 2 32 time value of the quotient in

Equation 63 (case b) (see

Section 16.7.6.3: Equations 65 and 66 to calculate the position stamp backwards ).



For RMO=0 and SMC=0:

Equation 76

ADD_IN_CAL1 = ADD_IN_CALN 

LOW_RES=0 and TS0_HRT=1 is not possible. For such a configuration the RCT bit in the

DPLL_STATUS register is set together with the ERR bit.

In the automatic end mode (DMO=0) missing pulses should be sent to the input RPCUx

(rapid pulse catch up on) in

Figure 72

to be caught up on with CMU_CLK0 (for COA=0).

When normal and rapid pulses are generated simultaneously, the SUB_INCx frequency is doubled at this moment in order to count two pulses at the TBU_CHx_BASE register. In order to make the frequency doubling possible, the CMU_CLK0 should be having a

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For the normal mode replace ADD_IN of the ADDER (see Figure 72 ) by ADD_IN_CAL1

(when calculated, DLM=0) or ADD_IN_LD1 (when provided by the CPU, DLM=1).

The sub-pulse generation in this case is done by the following calculations using a 24 bit adder with a carry out c out

and the following inputs:

 ADD_IN

 The second input is the output of the adder, stored one time stamp clock before

In order not to complicate the calculation procedure use a multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

16.8.3.4 Enabling of the compensated output for pulses

The c out

of the adder influences directly the SUB_INC1

output of the DPLL (see Figure 72 ).

The compensated output SUB_INCxc is in automatic end mode only enabled by EN_Cxc when INC_CNTx >0.

16.8.3.5 Equations to calculate ADD_IN in emergency mode for SMC=0

In emergency mode (RMO=1) calculate, in the case LOW_RES=TS0_HRS

Equation 77

ADD_IN_CALE= (NMB_S+0.5)* RCDT_SX while

RCDT_SX is the 2

32 time value of the quotient in

Equation 68

(case b) (see

Section 16.7.8.2: Equation 68 and Equation 69 to calculate the position stamp forwards



In emergency mode (RMO=1) calculate, in the case LOW_RES=1 and TS0_HRS=0

ADD_IN_CALE= (NMB_S+0.5)* RCDT_SX /8

( Equation 77

case a) while

RCDT_SX is the 2 32 time value of the quotient in

Equation 68 (see Section 16.7.8.2:

Equation 68 and Equation 69 to calculate the position stamp forwards ).

For RMO=1 and SMC=0:

ADD_IN_CAL1 = ADD_IN_CALE

( Equation 77

case b)

LOW_RES=0 and TS0_HRS=1 is not possible. For such a configuration the RCS bit in the

DPLL_STATUS register is set together with the ERR bit.

In the automatic end mode (DMO=0) missing pulses should be sent to the input RPCUx

(rapid pulse catch up on) in

Figure 72

, to be caught up on with CMU_CLK0 (for COA=0).

ADD_IN value should never exceed the value 0x800000 when the TS_CLK frequency

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RM0361 Digital PLL module (DPLL) exceeds half the frequency of the system clock. This limitation is only necessary for DMO=0 and COA=0 (see DPLL_CTRL_1 register).

For the emergency mode replace ADD_IN of the ADDER (see Figure 72

) by ADD_IN_CAL1

(when calculated, DLM=0) or ADD_IN_LD1 (when provided by the CPU, DLM=1).

The sub-pulse generation in this case is done by the following calculations using a 24-bit adder with a carry out c out

and the following inputs:

 ADD_IN

 The second input is the output of the adder, stored one time stamp clock before.

In order not to complicate the calculation procedure use a multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

Figure 72. Adder for generation of SUB_INCx by the carry cout

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The SUB_INC generation by the circuit above has the advantage, that the resolution for higher speed values is better as for a simple down counter.

After RESET and after EN_Cxg=0 the flip-flops (FFs) should have a zero value. EN_Cxg has to be zero until reliable ADD_IN values are available and the pulse generation starts.

This is controlled by the configuration bits SGE1,2 in the DPLL_CONTROL_1 register. The calculated values for the increment prediction using

Equation 10 case a,

Equation 25 case a 16.6.4.4

Equation 21 case a or

Equation 29 case a respectively are valid only when

at least NUTE>1 TRIGGER values or at least NUSE>1 STATE values are available. For

NUTE =1 or NUSE=1 respectively the equations Equation 75

(see

Section 16.8.3.3:

Equation 75 to calculate ADD_IN in normal mode for SMC=0

) and Equation 77

use the actual increment value subtracted by the weighted average error.

The generation of SUB_INC1 pulses depends on the configuration of the DPLL.

In automatic end mode the counter INC_CNT1 resets the enable signal EN_C1 when the number of pulses desired is reached. In this case only the uncompensated output

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SUB_INC1 remains active in order to provide pulses for the input filter unit. In the case of acceleration missing pulses can be determined at the next TRIGGER/STATE event in normal/emergency mode easily. For the correction strategy COA = 0 those missing pulses are sent out with CMU_CLK0 frequency as soon they are determined. During this time period the EN_Cxg remains cleared. After calculation or providing of a new ADD_IN value the FFs are enabled by EN_Cxg. In this way no pulse is lost. The new pulses are sent out afterwards, when INC_CNT1 is set to the desired value, maybe by adding MLT+1 or MLS1 respectively for the new TRIGGER/STATE event.

Because the used DIV procedure of the algorithms results only in integer values, a systematic failure could appear. The pulse generation at SUB_INC1 will stop in automatic end mode when the INC_CNT1 register reaches zero or all remaining pulses at a new increment will be considered in the next calculation. In this way the lost of pulses can be avoided.

When a new TRIGGER/STATE appears the value of SYN_T*(MLT+1) or SYN_S*MLS1 respectively is added to INC_CNT1 , when SGE1=1.

Therefore for FULL_SCALE

2*(TNU+1)*(MLT+1) pulses SUB_INC1 generated, when INC_CNT1 reaches the zero value. The generation of SUB_INC1 pulses has to be done as fast as possible. The calculations for the ADD_IN value must be done first. Therefore all values needed for calculation are to be fetched in a forecast.

16.8.4 Sub pulse generation for SMC=1

16.8.4.1 Necessity of two pulse generators

The Adder of

Figure 72

must be implemented twice in the case of SMC=1: one for

SUB_INC1 controlled by the TRIGGER input and (while RMO=1) one for SUB_INC2, controlled by the STATE input. In the case described in the chapter above for SMC=0 only one Adder is used to generate SUB_INC1 controlled by the TRIGGER in normal mode or by

STATE in emergency mode.

16.8.4.2

Equation 78

to calculate the number of pulses to be sent for the first device using the automatic end mode condition

For SMC=1 and DMO=0

Equation 78

NMB_T = MLS1*SYN_T + MP + PD_store + MPVAL1 with

 PD_store = ADT_T[12:0], prefetched during last increment

 SYN_T = ADT_T[18:16], prefetched during last increment

 MPVAL1 = pulse correction value for PCM1_SHADOW_TRIGGER=1 while the value for PD_store is zero for AMT=0 and for COA=0 use zero instead of the value of MP

16.8.4.3

Equation 79

to calculate the number of pulses to be sent for the second device using the automatic end mode condition

for RMO=1, SMC=1 and DMO=0

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RM0361 Digital PLL module (DPLL)

Equation 79

NMB_S = MLS2 *SYN_S+ MP + PD_S_store + MPVAL2 with

 PD_S_store = ADT_S[15:0], prefetched during last increment

 SYN_S = ADT_S[21:16], prefetched during last increment

 MPVAL2 = pulse correction value for PCM2_SHADOW_STATE=1 while the value for PD_S_store is zero for AMS=0 and for COA=0 use zero instead of the value of MP

Please note, that these calculations above in equations

Equation 78

and Equation 79

are only valid for an automatic end mode (DMO = 0). In addition the number of generated pulses is added by 0.5 as shown in

Equation 80

or Equation 81

respectively in order to compensate rounding down errors at the succeeding division operation. Because in automatic end mode the number of pulses is limited by INC_CNTx it is guaranteed, that the right number of pulses is generated and in the same way missing pulses are made up for the next increment.

16.8.4.4

Equation 80

to calculate ADD_IN for the first device for SMC=1

The sub-pulse generation in this case is done by the following calculations using a 24 bit adder with a carry out c out

and the following inputs:

 ADD_IN

 The second input is the (delayed) output of the adder, stored with each time stamp clock.

Replace ADD_IN by ADD_IN_CAL1 (when calculated, DLM1=0) or ADD_IN_LD1 (when provided by the CPU, DLM1=1) respectively while:

For SMC=1 and LOW_RES=TS0_HRT

Equation 80

ADD_IN_CAL1= (NMB_T+0.5) * RCDT_TX

When RCDT_TX is the 2

32 time value of the quotient in

Equation 63

(case b) of

Section 16.7.6.2: Equation 63 and 64 to calculate the position stamp forwards

For SMC=1,LOW_RES= 1 and TS0_HRT=0

ADD_IN_CAL1= (NMB_T+0.5) * (RCDT_TX /8) (

Equation 80 case a)

When RCDT_TX is the 2 32 time value of the quotient in

Equation 63

(case b) of

Section 16.7.6.3: Equations 65 and 66 to calculate the position stamp backwards .

In order not to complicate the calculation procedure use a multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

ADD_IN_CAL1 is a 24-bit integer value. The CDT_TX is the expected duration of current

TRIGGER increment.

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The c out

of the adder influences directly the SUB_INC1

output of the DPLL (see Figure 72 ).

The SUB_INC1 output is in automatic end mode only enabled by EN_C1 when 

INC_CNT1 >0.

16.8.4.5

Equation 81

to calculate ADD_IN for the second device for SMC=1

Replace ADD_IN by ADD_IN_CAL2 (when calculated, DLM2=0) or ADD_IN_LD2 (when provided by the CPU, DLM2=1) respectively while: for SMC=1, RMO=1 and LOW_RES=TS0_HRS:

Equation 81

ADD_IN_CAL2= (NMB_S+0.5)* RCDT_SX

When RCDT_SX is the 2

time value of the quotient in Equation 68 (case b) of

Section 16.7.8.2: Equation 68 and Equation 69 to calculate the position stamp forwards

Note:

366/558 for SMC=1, RMO=1, LOW_RES=1 and TS0_HRS=0:

ADD_IN_CAL2= (NMB_S+0.5)* (RCDT_SX /8)

( Equation 81

case a)

When RCDT_SX is the 2 32

time value of the quotient in Equation 68 (case b).

In order not to complicate the calculation procedure use a multiplier with a sufficient bit width at the output and use the corresponding shifted output bits.

The c out

of the adder2 influences directly the SUB_INC2 output of the DPLL (see

Figure 72:

Adder for generation of SUB_INCx by the carry cout ).

The SUB_INC2 output is in automatic end mode only enabled by EN_C2 when 

INC_CNT2 >0.

After RESET and after EN_Cxc=0 (after stopping in automatic end mode) the flip-flops (FFs) have a zero value and also EN_Cxg has to be zero until reliable ADD_IN values are available and the pulse generation starts. The calculated values for the increment prediction using

Equation 10

(case a) (see

Equations 10 and equation 11 to calculate the current increment value on page 339

), Equation 25 (case a) (see Equation 25 to calculate the current increment value on page 343 ),

Equation 21 (case a) (see Equations 21 and 22 to calculate the current increment (nominal value) on page 342 ) or

Equation 29 (case a) (see

Equations 29 to calculate the current increment value

) respectively are valid only when

NUTE>1 or NUSE>1 respectively. For NUTE=1 or NUSE=1 respectively the Equation 80

(see Equation 80 to calculate ADD_IN for the first device for SMC=1 Please note, that these calculations above in equations Equation 78 and Equation 79 are only valid for an automatic end mode (DMO = 0). In addition the number of generated pulses is added by 0.5 as shown in Equation 80 or Equation 81 respectively in order to compensate rounding down errors at the succeeding division operation. Because in automatic end mode the number of pulses is limited by INC_CNTx it is guaranteed, that the right number of pulses is generated and in

the same way missing pulses are made up for the next increment. ) and Equation 81

(see

Section 16.8.4.5: Equation 81 to calculate ADD_IN for the second device for SMC=1 ) use

the actual increment value subtracted by the weighted average error.

The generation of SUB_INCx pulses depends on the configuration of the DPLL.

In automatic end mode the counter INC_CNTx resets the enable signal EN_Cxcu when the number of pulses desired is reached. In this case only the uncompensated outputs

SUB_INCx remain active in order to provide pulses for the input filter units. A new

TRIGGER or STATE input respectively can reset the FFs and also ADD_IN, especially when

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RM0361 Digital PLL module (DPLL)

EN_Cxc was zero before. In the case of acceleration missing pulses can be determined at the next TRIGGER/STATE event easily. For the correction strategy COA = 0 those missing pulses are sent out with CMU_CLK0 frequency as soon they are determined. After that the pulse counter INC_CNTx should be always zero and the new pulses are sent out afterwards, when INC_CNTx is set to the desired value by adding MLS1 or MLS2 for the new TRIGGER or STATE event respectively.

Because the used DIV procedure of the algorithms results only in integer values, a systematic failure could appear. The pulse generation will stop when the INC_CNTx register reaches zero or all remaining pulses at a new increment will be considered in the next calculation. In this way the lost of pulses can be avoided.

When a new TRIGGER appears the value of SYN_T*MLS1 is added to INC_CNT1 .

Therefore for FULL_SCALE 2*(TNU+1)*MLS1 pulses SUB_INC1 generated, when

INC_CNT1 reaches the zero value. The generation of SUB_INC1 pulses has to be done as fast as possible.

When a new STATE appears the value of SYN_S*MLS2 is added to INC_CNT2 . Therefore for FULL_SCALE 2*(SNU+1)*MLS2 pulses SUB_INC2 generated, when INC_CNT2 reaches the zero value. The generation of SUB_INC2 pulses has to be done as fast as possible.

16.8.5 Calculation of the accurate position values

All appearing TRIGGER and STATE signals do have a time stamp and a position stamp assigned after the input filter procedure. For the calculation of the exact time stamp the filter values are considered in the calculations of Equations

1 to 4

(see

Section 16.6.2.1:

Equations 1 to 4 to calculate TRIGGER time stamps

) or

Equation 12

16 (see

Section 16.6.3.1: Equations 12 to 15 to calculate STATE time stamps ) respectively. A

corresponding calculation is to be performed for the calculation of position values.

The PSTC and PSSC values can be corrected by the CPU, when needed.

After reset, while FTD=0 and no active TRIGGER slope is detected:

Equation 82

PSTC = 0

Calculate the new Position value for each valid TRIGGER event:

PSTC= PSTC_old + NMB_T_TAR_OLD when FTD=1 and SGE1=1 with

 PSTC_old is the last PSTC value and

 NMB_T_old is the number of pulses which are calculated and provided for sending out in the last increment.

After reset, while FSD=0 and no active STATE slope is detected:

(

Equation 82 case a)

( Equation 82

case b)

Equation 83

PSSC= 0

Calculate the new Position value for each STATE event:

PSSC= PSSC_old + NMB_S_TAR_OLD

( Equation 83

case a)

( Equation 83

case b)

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Digital PLL module (DPLL) RM0361 when FSD=1 and SGE1=1 (SMC=0) or SGE2=1 (SMC=1) respectively with

 PSSC_old is the last PSSC value and

 NMB_S_old is the number of pulses which are calculated and provided for sending out in the last increment.

16.8.6 Scheduling of the calculation

After enabling the DPLL with each valid TRIGGER or STATE event respectively a cycle of operations is performed to calculate all the results shown in detail in the table below. A state machine controls this procedure and consists of two parts, the first is triggered by a valid slope of the signal TRIGGER , begins at step 1 and ends at step 20 (in normal mode and for

SMC=1). The second state machine is controlled by a valid slope of the signal STATE , begins at step 21 and ends at step 40 (in emergency mode and also for SMC=RMO=1).

Depending on the mode used all 20 steps are executed or already after 2 steps the jump into the initial state is performed, as shown in the state machine descriptions below. For each new extended cycle (without this jump) all prediction values for actions in the case

SMC=0 are calculated once more (with maybe improved accuracy because of better parameters) and all pending decisions are made using these new values when transmitted to the decision device.

In Table 207 the steps of the state machine are described. Please note, that the elaboration

of the steps depends on the configuration bits described in the comments. The steps 4 to 17 are only calculated in normal mode (in the state machine explanation below marked yellow in

Section 16.2: Requirements and demarcation

), but steps 24 to 37 are only calculated in emergency mode (in the state machine explanation below marked cyan in

Section 16.2:

Requirements and demarcation ) when SMC=0.

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16.8.6.1 State machine partitioning for normal and emergency mode

Figure 73. State machine partitioning for normal and emergency mode

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TRIGGER:

The APT (address pointer for duration and reciprocal duration values of TRIGGER increments) is initially set to zero and incremented with each valid TRIGGER event.

Therefore data are stored in the RAM beginning from the first available value. The actual duration of the last increment is stored at DT_T_ACT. For the prediction of the next increment it is assumed, that the same value is valid as long as NUTE is one.

A missing TRIGGER is assumed, when at least after TOV* DT_T_ACT no valid TRIGGER event appears.

The data of equations

Equation 52

and Equation 54

are written in the corresponding RAM regions and APT is incremented accordingly up to 2*TNU-2*SYN_NT+1.

The APT_2b (address pointer for the time stamp field of TRIGGER ) is initially set to zero and incremented with each valid TRIGGER event. When no gap is detected because of the incomplete synchronization process at the beginning, for all TRIGGER events the time stamp values are written in the RAM up to 2*(TNU+1) entries, although only 2*(TNU+1-

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Digital PLL module (DPLL) RM0361

SYN_NT) events in FULL_SCALE appear. When the current position is detected, the synchronization procedure can be performed as described below:

Before the CPU sets the APT_2c address pointer in order to synchronize to the profile, it writes the corresponding increment value for the necessary extension of the RAM region 2b value APT_2b_ext into the register APT_2b_sync and sets the status bit APT_2c_status.

This value can be e.g. 2*SYN_NT, when all gaps in FULL_SCALE already passed the input data stream of TRIGGER , or less then this value, when up to now e.g. only a single gap is to be considered in the data stream stored already in the RAM region 2b. The number of virtual increments to be considered depends on the number of inputs already got. After writing

APT_2c by the CPU, with the next TRIGGER event the APT_2b address pointer is incremented (as usual) and then the additional offset value APT_2b_ext is added to it once

(while APT_2b_status=1 and for forward direction). For that reason the APT_2b_status bit is reset after it. The old APT_2b value before adding the offset is stored in the APT_2b_old register as information for the CPU where to start the extension procedure. In the following the CPU fills in the time stamp field around the APT_2b_old position taking into account the corresponding number of virtual entries stored in the APT_2b_ext value and the corresponding NT values in the profile. The extension procedure ends when all gaps considered in the APT_2b_ext value are treated once. In the consequence all storage locations of RAM region 2b up to now do have the corresponding entries. Future gaps are treated by the DPLL.

For a backward direction the APT_2c_ext value is subtracted accordingly.

When the CPU writes the APT_2c address pointer the SYT bit is set simultaneously. For

SYT=1 in normal mode (SMC=0) the LOCK1 bit is set with the system clock, when the right number of increments between two synchronization gaps is detected by the DPLL. An unexpected missing TRIGGER or an additional TRIGGER between two synchronization gaps does reset the LOCK1 bit in normal mode. In that case the CPU must correct the

SUB_INC pulse number and maybe correct the APT_2c pointer. For this purpose the LL1I interrupt can be used.

When SYT is set the calculations of

Equation 1 to

16.6.2.7Equations 10 and equation 11 to calculate the current increment value

are performed accordingly and the values are stored in (and distributed to) the right RAM positions.

This includes the multiple time stamp storage by the DPLL for a gap according to equations

49 51 forwards ( Section 16.7.5.2: Equation 49-Equation 51 to extend the time stamp values for TRIGGER in forward direction ) or backwards ( Section 16.7.5.3: Equation 49-Equation 51 for backward direction

). The APT_2b pointer is for that reason incremented or decremented before this operation considering the virtual increments in addition.

Please note, that for the APT and APT_2c pointers the gap is considered as a single increment.

STATE:

The APS (address pointer for duration and reciprocal duration values of STATE ) is initially set to zero and incremented with each valid STATE event. Therefore data are stored in the

RAM field beginning at the first location. The actual duration of the last increment is stored at DT_S_ACT. For the prediction of the next increment it is assumed, that the same value is valid as long as NUSE is one.

A missing STATE is assumed, when at least after TOV_S* DT_S_ACT no valid STATE event appears.

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The data of equations

Equation 59 to Equation 61 is written in the corresponding RAM

regions and APS is incremented accordingly up to 2*SNU-2*SYN_NS+1 (for SYSF=0).

The APS_1c2 (address pointer for the time stamp field of STATE ) is initially set to zero and incremented with each valid STATE event. When no gap is detected because of the incomplete synchronization process at the beginning, for all STATE events the time stamp values are written in the RAM up to 2*(SNU+1) entries, although (e.g. for SYSF=0) only

2*(SNU+1-SYN_NS) events in FULL_SCALE appear. When the current position is detected, the synchronization procedure can be performed as described below:

Before the CPU sets the APS_1c3 address pointer in order to synchronize to the profile, it writes the corresponding increment value APS_1c2_ext for the necessary extension of the

RAM region 1c2 into the register DPLL_APS_SYNC and sets the APS_1c2_status bit there.

This value can be e.g. 2*SYN_NS (for SYSF=0) or SYN_NS (for SYSF=1), when all gaps in

FULL_SCALE already passed the input data stream of STATE . Also less then this value can be considered, when up to now only a single gap is to be considered in the data stream stored already in the RAM region 1c2. The number of increments to be considered depends on the number of inputs already got. After writing APS_1c3 by the CPU, with the next valid

STATE slope the APS_1c2 address pointer is incremented (as usual) and then the additional offset value APS_1c2_ext is added to it once (while APS_1c2_status=1 and forward direction). For that reason the APS_1c2_status bit is reset after it. The old APS_1c2 value is stored in the APS_1c2_old register as information for the CPU where to start the extension procedure. In the following the CPU extends the time stamp field beginning from the APS_1c2_old position taking into account the corresponding number of virtual entries according to the APS_1c2_ext value and also the correspondent NS values in the profile.

The extension procedure ends when all gaps considered in the APS_1c2_ext value are treated once. In the consequence all storage locations of RAM region 1c2 up to now do have the corresponding entries. Future gaps are treated by the DPLL.

For a backward direction the APS_1c2_ext value is subtracted accordingly.

When the CPU writes the APS_1c3 address pointer the SYS bit is set simultaneously. For

SYS=1 in emergency mode (SMC=0 and DMO=1) the LOCK1 bit is set with the system clock, when the right number of increments between two synchronization gaps is detected by the DPLL. An unexpected missing STATE or an additional STATE between two synchronization gaps does reset the LOCK1 bit in emergency mode. In that case the CPU must correct the SUB_INC1 pulse number and maybe correct the APS_1c3 pointer. For this purpose the LL1I interrupt can be used.

When SYS is set the calculations of equations

10 to

are performed accordingly and the values are stored in (and distributed to) the right RAM positions.

This includes the multiple time stamp storage by the DPLL for a gap according to

Equation

-

Equation 58

(forwards) or Equation 62

-

Equation 64

(backwards). The APS_1c2 pointer is for that reason incremented or decremented before this operation considering the virtual increments in addition.

Please note, that for the APS and APS_2c pointers the gap is considered as a single increment.

SMC=1:

For SMC=1 it is assumed, that the starting position is known by measuring the characteristic of the device. In this way the APT and APT_2c as well the APS and APS_1c3 values are set properly, maybe with an unknown repetition rate. When no gap is to be considered for

TRIGGER or STATE signals the APT_2b and APS_1c2 address pointers are set equal to

APT or APS respectively. It is assumed, that all missing TRIGGER s and missing STATE s

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Digital PLL module (DPLL) RM0361 can be also considered from the beginning, when a valid profile with the corresponding adapt values is written in the RAM regions 1c3 and 2c respectively. In that case the TSF_T[i] and TSF_S[i] must be extended by the DPLL according to the profile. . Thus the SYT and

SYS bits could be set from the beginning and the LOCK1 and LOCK2 bits are set after recognition of the corresponding gaps accordingly. When no gap exists (SYN_NT=0 or

SYN_NS=0), the LOCK bits are set immediately. The CPU can correct the APT_2c and

APS_1c3 pointer according to the recognized repetition rate later once more without the loss of Lock1,2.

16.8.6.3 Operation for direction change in normal and emergency mode (SMC=0)

When for SMC=0 in normal mode a backwards condition is detected for the TRIGGER input signal (e.g. when THMI is not violated), the LOCK1 bit in the DPLL_STATUS register is reset, the NUTE value in NUTC register is set to 1 (the same for NUSE in NUSC). The address pointers APT_2c as described below (and after that decremented for each following valid slope of TRIGGER as long as the DIR1 bit shows the backward direction).

Please notice, that in the case of the change of the direction the ITN and ISN bit in the

DPLL_STATUS register are reset.

For this transition to the backward direction no change of address pointer APT and APT_2b is necessary.

Note:

Profile update for TRIGGER when changing direction

The profile address pointer APT_2c is changed step by step in order to update the profile information in SYN_T, SYN_T old and PD_store:

 Decrement APT_2c, load SYN_T

 Decrement APT_2c, load SYN_T, PD_store, update SYN_T_old

 Decrement APT_2c, make calculations , load SYN_T and PD_store, update

SYN_T_old and PD_store_old and wait for a new TRIGGER event.

The update of SYN_T_old and the loading of PD_store can be performed in all steps above.

The value of APT_2b needs not to be corrected. For a direction change from backwards to forwards make the same corrections by incrementing APT_2c.

Make calculations does mean: the operation of the state machine starts with the calculations of NMB_T and INC_CNT1 using the actual APT_2c address pointer value, see

Section 16.2: Requirements and demarcation .

The TBU_TB1 value is to be corrected by the number of pulses sent out in the wrong direction mode during the last and current increment. This correction is done by sending out

SUB_INC1 pulses for decrementing TBU_TB1 (while DIR1=1).

Save inc_cnt1 value at direction change to inc_cnt1_save.

Calculate the new inc_cnt1 value as follows:

Stop sending pulses and save inc_cnt1 at the moment of direction change as inc_cnt1_save.

2. Set inc_cnt1 to the target value of the last increment  nmb_t_tar_old

3. Add the target number of trigger which were calculated for the current increment when this value was already added to inc_cnt1 before the direction change is detected 

+ nmb_t_tar

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4. Subtract the value of still not sent pulses (remaining value at inc_cnt1_save) 

- inc_cnt1_save

5. Calculate the new target pulses to be sent considering the new values of SYN_T and

PD_store and add them:

+ nmb_t_tar_new

This does mean the following equation: inc_cnt1 = nmb_t_tar_old + nmb_t_tar

- inc_cnt1_save + nmb_t_tar_new

All pulses summarized at inc_cnt1 are sent out by the maximum possible frequency, because no speed information is available for the first increment after changing the direction. Please notice that no pulse correction using PCM1 of DPLL_CTRL1 is possible during direction change.

When PSTC was incremented/decremented at the active slope and after that the direction change was detected at the same input event, correct PSTC once by

- nmb_t_tar_old when changed to backwards

+ nmb_t_tar_old when changed to forwards in order to compensate the former operation. When the direction information is known before an intended change of PSTC, do not change them.

Store the new calculated value nmb_t_tar_new at nmb_t_tar for the correct calculation of

PSTC at the next input event.

Consequences for STATE

With the next valid STATE event the direction information is already given. The profile pointer APS_1c3 is to be corrected by a two times decrement in order to point to the profile of the next following increment. From now on it is decremented with each STATE event while DIR1=1. The SYN_S and PD_S_store values must be updated accordingly, including

SYN_S_old and PD_S_store_old.

Because the right direction is already known when an input event appears, make the following corrections:

 Decrement APS_1c3, load SYN_S and PD_S_store, update SYN_S_old and

PD_S_store_old

 Decrement APS_1c3, make calculations , load SYN_S and PD_S_store, update

SYN_S_old and PD_S_store_old and wait for a new STATE event.

The update of SYN_S_old and the loading of PD_S_store can be performed in all steps above. The value of APS_1c2 needs not to be corrected.

When a new STATE event occurs, all address pointers are decremented accordingly as long as DIR1=1.

In emergency mode the pulses are corrected as follows:

Save inc_cnt1 value at direction change to inc_cnt1_save.

Calculate the new inc_cnt1 value as follows:

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Stop sending pulses and save inc_cnt1 at the moment of direction change as inc_cnt1_save.

2. Set inc_cnt1 to the target value of the current increment  nmb_s_tar

Please notice, that differently from the normal mode, nmb_s_tar is to be used instead of nmb_s_tar_old, because direction information in emergency mode is only given from the

TRIGGER input and occurs independent of a STATE event.

That means: the calculations at the last STATE event were done for the correct former direction. In addition still no pulse calculations are performed for the current increment, because the direction change is known at the moment of the recent STATE event. Later direction changes are considered at the next STATE event.

3. Do not add the calculated number of state pulses because no new STATE event occurred.

4. Subtract the value of still not sent target pulses (remaining value at inc_cnt1_save) 

- inc_cnt1_save

5. Add the new calculated target pulses for the current increment 

+ nmb_s_tar_new when for the calculation all new conditions of PD_S_store and SYN_S are considered.

inc_cnt1 = nmb_s_tar_old - inc_cnt1_save + nmb_s_tar_new

Do not change PSSC and suppress incrementing/decrementing of PSSC at the event directly following to the direction change information.

Store the new calculated value nmb_s_tar_new at nmb_s_tar for the correct calculation of

PSTC at the next input event.

Repeated change to forward direction for TRIGGER

The DIR1 bit remains set as long as the THMI value remains none violated for the following

TRIGGER events and is reset when for an invalid TRIGGER slope the THMI is violated.

Resetting the DIR1 to 0 results (after repeated reset of LOCK1, ITN, ISN) the opposite correction of the profile address pointer considered.

This does mean two increment operations of the address pointer APS_1c3 including the update of SYN_S and PD_S_store with the automatic update of SYN_S_old and

PD_S_store_old for STATE and four increment operations of the address pointer APT_2c including the update of SYN_T and PD_store with the automatic update of SYN_T_old and PD_store_old for TRIGGER.

The correction of TBU_CH1 is done by sending out the correction pulses with the highest possible frequency at SUB_INC1 while DIR1=0. The number of pulses is calculated as shown above.

Consequences for STATE see corrections above. After that the address pointers are incremented again with each following valid STATE event as long as DIR1=0.

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16.8.6.4 Operation for direction change for TRIGGER (SMC=1)

When for SMC=1 a backwards condition is detected for the TRIGGER input signal (TDIR=1, resulting in DIR1=1), the LOCK1 bit in the DPLL_STATUS register is reset, the NUTE value in NUTC register is set to 1. The address pointers APT and APT_2c as well as APT_2b are decremented for each valid slope of TRIGGER as long as the DIR1 bit shows the backward direction.

Please notice, that in the case of the change of the direction the ITN bit in the

DPLL_STATUS register is reset.

Profile update for TRIGGER

Make the same update steps for the profile address pointer as shown in

Section 16.8.6.3:

Operation for direction change in normal and emergency mode (SMC=0) Operation for direction change in normal and emergency mode (SMC=0): decrement APT_2c for 2 times

with the update of the SYN_T and PD_store values at each step with an automatic update of

SYN_T_old and PD_store_old:

 Decrement APT_2c, load SYN_T, PD_store, update SYN_T_old

 Decrement APT_2c, make calculations , load SYN_T and PD_store, update

SYN_T_old and PD_store_old and wait for a new TRIGGER event.

In the normal case no correction of wrong pulses sent is necessary, because the direction change is detected by the pattern immediately.

Nevertheless a correction is necessary as shown below. In the other case: see treatment of

pulses TBU_CH1_BASE in normal mode at Section 16.8.6.3: Operation for direction change in normal and emergency mode (SMC=0) Operation for direction change in normal and emergency mode (SMC=0).

Save inc_cntx value at direction change to inc_cnt1_save.

Calculate the new inc_cnt1 value as follows:

Clear inc_cnt1

2. Set inc_cnt1 to the target value of the last increment  nmb_t_tar

Please notice, that differently from the normal mode, nmb_t_tar is to be used instead of nmb_t_tar_old, because the direction information is known before the calculation takes place.

3. Do not add the calculated number of trigger pulses because it is not calculated yet before the direction change information is known.

4. Subtract the value of still not sent pulses (remaining value at inc_cnt1_save) 

- inc_cnt1_save

5. Add the new calculated target pulses for the current increment 

+ nmb_t_tar_new when for the calculation all new conditions of PD_S_store and SYN_S are considered.

inc_cnt1 = nmb_t_tar_old - inc_cnt1_save + nmb_t_tar_new

Suppress changing of PSTC for the TRIGGER event when a direction change is detected.

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Store the new calculated value nmb_t_tar_new at nmb_t_tar for the correct calculation of

PSTC at the next input event.

Repeated change to forward direction for TRIGGER

The DIR1 bit remains set as long as the TDIR bit is set for the following TRIGGER events and is reset when for a valid TRIGGER slope the TDIR is zero.

Resetting the DIR1 to 0 results (after repeated reset of LOCK1 and ITN) the opposite correction of the address pointer use.

This does mean two increment operations of the address pointer including the update of

SYN_T and PD_store.

A complex correction of TBU_CH1_BASE and INC_CNT1 is in the normal case not necessary, when all increments are equal (SYN_NT=0) and no adapt information is used. In this case only the MLS1 value is added to INC_CNT1 in order to back count the value for the last increment. In the other case: see treatment of pulses TBU_CH1_BASE and

ICN_CNT1 in normal mode at

Section 16.8.6.3: Operation for direction change in normal and emergency mode (SMC=0)

16.8.6.5 Operation for direction change for STATE (SMC=1)

When for SMC=1 a backwards condition is detected for the STATE input signal (SDIR=1, resulting in DIR2=1), the LOCK2 bit in the DPLL_STATUS register is reset, the NUSE value in NUSC register is set to 1 and the address pointers APS and APS_1c3_f and APS_1c2 are decremented for each valid slope of STATE as long as the DIR2 bit shows the backward direction.

Please notice, that in case the direction changes, the ISN bit in the DPLL_STATUS register is reset.

For this transition to the backward direction no change of address pointer APS and

APS_1c2 is necessary.

Profile update for STATE

Make the same update steps for the profile address pointer as shown in

Section 16.8.6.3:

Operation for direction change in normal and emergency mode (SMC=0) Operation for direction change in normal and emergency mode (SMC=0): decrement APS_1c3 for 2 times

with the update of the SYN_S, SYN_S_old, PD_S_store and PD_S_store_old values at each step:

 Decrement APT_1c3, load SYN_S, PD_S_store, update SYN_S_old

 Decrement APT_1c3, make calculations , load SYN_S and PD_S_store, update

SYN_S_old and PD_S_store_old and wait for a new STATE event.

A complex correction of TBU_CH2_BASE and INC_CNT2 is in the normal case not necessary, when all increments are equal (SYN_NS = 0) and no adapt information is used.

In this case only the MLS2 value is added to INC_CNT2 in order to back count the value for the last increment. In the other case: see treatment of pulses TBU_CH1_BASE and

ICN_CNT1 in normal mode at

Section 16.8.6.3: Operation for direction change in normal and emergency mode (SMC=0)

For the second PMSM the pulses are corrected as follows:

Save inc_cnt2 value at direction change to inc_cnt2_save.

Calculate the new inc_cnt2 value as follows:

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Clear inc_cnt2

2. Set inc_cnt2 to the target value of the last increment  nmb_s_tar

Please notice, that differently from the normal mode, nmb_s_tar is to be used instead of nmb_s_tar_old, because no new calculation is performed so far.

3. Do not add the calculated number of state pulses because it is not calculated yet before the direction change information is known.

4. Subtract the value of still not sent pulses (remaining value at inc_cnt2_save) 

- inc_cnt2_save

5. Add the new calculated target pulses for the current increment 

+ nmb_s_tar_new when for the calculation all new conditions of PD_S_store and SYN_S are considered.

inc_cnt2 = nmb_s_tar_old - inc_cnt2_save + nmb_s_tar_new

All pulses summarized at inc_cnt2 are sent out by the maximum possible frequency, because no speed information is available for the first increment after changing the direction. Please notice that no pulse correction using PCM2 of DPLL_CTRL1 is possible during direction change.

Do not change PSSC for a STATE event when a direction change is detected.

Store the new calculated value nmb_s_tar_new at nmb_s_tar for the correct calculation of

PSTC at the next input event.

Repeated change to forward direction for STATE

The DIR2 bit remains set as long as the SDIR bit is set for the following STATE events and is reset when for a valid STATE slope SDIR is zero.

Resetting the DIR2 to 0 results (after repeated reset of LOCK2 and FSD) in the opposite correction of the address pointer use.

After a last decrementing of all address pointers the APS_1c3 is incremented 2 times with a repeated update of SYN_S, SYN_S_old and PD_S_store after each increment.

16.8.6.6 DPLL reaction in the case of non plausible input signals

When the DPLL is synchronized concerning the TRIGGER signal by setting the FTD, SYT and LOCK1 bits in the DPLL_STATUS register, the number of valid TRIGGER events between the gaps is to be checked continuously.

When additional events appear while a gap is expected, the LOCK1 bit is reset and the ITN bit in the DPLL_STATUS register is set.

When an unexpected gap appears (missing TRIGGER S), the NUTE value in the NUTC register is set to 1, the LOCK1 bit is reset and the ITN bit in the DPLL_STATUS register is set. The address pointers are incremented with the next valid TRIGGER slope accordingly.

When the TRIGGER locking range TLR is violated (l) , the state machine 1 will remain in state

1 and the address pointer APT, APT_2b and APT_2c will remain unchanged until the CPU l.

The TOR Bit in the DPLL_STATUS register is set, when the time to the next active TRIGGER slope exceeds the value of the last nominal TRIGGER duration multiplied with the value of the TLR register (see

16.11.76

). In

this case also the TORI interrupt is generated, when enabled.

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Digital PLL module (DPLL) RM0361 sets the APT_2c accordingly. In this case also the NUTE value in the NUTC register is set to

1. The DPLL stops the generation of the SUB_INC1 pulses and will perform no other actions

- remaining in step1 of the first state machine (see Section 16.2

When in the following the direction DIR1 changes as described in the chapters above the

ITN bit in the DPLL_STATUS register is reset, the use of the address pointers APT_2c is switched and the pulse correction takes place as described above.

In all other cases the CPU can interact to leave the instable state. This can be done by setting the APT_2c address pointer which results in a reset of the ITN bit. In the following

NUTE can also be set to higher values.

When the DPLL is synchronized concerning the STATE signal by setting the FSD, SYS and

LOCK1 (for SMC=0) or LOCK2 (for SMC=1) bits in the DPLL_STATUS register, the number of valid STATE events between the gaps is to be checked continuously.

When additional events appear while a gap is expected or while an unexpected missing

STATE event appears, the LOCK1,2 bit is reset and the ISN bit in the DPLL_STATUS register is set.

When an unexpected gap appears for RMO=SMC=1 (missing STATE s for synchronous motor control), the NUSE value in the NUSC register is set to 1, the LOCK2 bit is reset and the ISN bit in the DPLL_STATUS register is set. The address pointers are incremented with the next valid STATE slope accordingly.

When the STATE locking range SLR is violated (m) , the state machine 2 will remain in state

21 and the address pointer APS, APS_1c2 and APS_1c3 will remain unchanged until the

CPU sets the APS_1c3 accordingly. In this case also the NUSE value in the NUSC register is set to 1. The DPLL stops the generation of the SUB_INC1,2 pulses respectively and will perform no other actions - remaining in step21 of the second state machine (see

Section 16.2

In this case also the SORI interrupt is generated, when enabled.

When in the following the direction DIR2 changes as described in the chapters above the

ISN bit in the DPLL_STATUS register is reset, the use of the address pointers APS_1c3 is switched and the pulse correction takes place as described above. In all other cases the

CPU must interact to leave the instable state. This can be done by setting the APS_1c3 address pointers which results in a reset of the ISN bit. In the following NUSE can also be set to higher values.

378/558 m. The SOR Bit in the DPLL_STATUS register is set, when the time to the next active STATE slope exceeds the

value of the last nominal STATE duration multiplied with the value of the SLR register (see 16.11.77

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Step

Table 207. State description of the state machine

Description Comments

Always for

DEN=1

For each inactive TRIGGER slope: generate the TISI interrupt; calculate the time stamp difference ∆ T to the last valid event, store this value at

THVAL; when THMI >0 is violated ( ∆ T < THMI): generate TINI interrupt, set DIR1 = 0 (forwards) set BWD1 = 0 (see DPLL_STATUS register) else (only for THMI >0): set DIR1 = 1 (backwards); set BWD1 = 1 (see DPLL_STATUS register) after changing the direction correct the pulses WP sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency:

WP=NMB_T-DPLL_INC_CNT1; correct INC_CNT1 by addition of 2*WP before sending the correction pulses; check THMA, when THMA is violated, generate the TAXI interrupt; go to step 1

For each inactive STATE slope: set DIR2 = DIR1

For SMC=0; set DIR1 always after inc./ decr. the address pointers APT, APT_x; go to step 1; stop output of SUB_INC1 and correct pulses after changing DIR1 after incr./ decr. of APS_x set DIR2 always after incr./decr. the address pointers APS, APS_x; go to step 1 always for

DEN=1 set DIR1 = BWD1 = TDIR, set DIR2 = BWD2 = SDIR; for each change of TDIR go to step 1 after performing the following calculations: correct INC_CNT1 correct the pulses (WP, see above) sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency.

For each change of SDIR go to step 21 after performing the following calculations: update of SYN_S, PD_S_store according to

Section 16.8.6.3: Operation for direction change in normal and emergency mode (SMC=0)

Operation for direction change in normal and emergency mode (SMC=0)

correct INC_CNT1,2 correct the pulses sent with wrong direction information and send the pulses for the actual increment in addition with highest possible frequency.

for SMC=1 ; set the direction bits always after incr./decr. the corresponding address pointers;

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Table 207. State description of the state machine (continued)

Description Comments

When DEN = 0 or TEN=0: stay in step 1 until DEN=1, TEN=1 and at least one valid

TRIGGER has been detected (FTD=1); the following steps are performed always (not necessarily in step 1, but also in steps 18 to 20 (when waiting for new

PMTR values to be calculated): compare TRIGGER_S with

TSL (valid slope);

When no valid TRIGGER appears and when TS_T_CHECK time is reached:

– send missing

TRIGGER

INT, also when a Gap is expected according to the profile; set MT=1 (missing TRIGGER bit) in the DPLL_STATUS register; do not leave the active step, until a valid TRIGGER appears.

When a valid TRIGGER appears check PVT

– When the PVT value is violated: generate the PWI interrupt, ignore the

TRIGGER

input and wait for the next valid TRIGGER slope (ignore each invalid slope); do not store any value

–

- When the PVT value is fulfilled: store the actual position stamp at PSTM (value at the

TRIGGER event) update the RAM region 2 by

and

Section 16.7.5: Update of RAM in normal and emergency mode

) store the actual INC_CNT1 value at MP1 as missing

pulses (instead of calculation in step 5) store all relevant configuration bits

of the

DPLL_CTRL(0,1) Registers in shadow

registers and consider them for all corresponding calculations of steps 2 to

20 accordingly; the relevant bits are explained in the registers itself generate the TASI interrupt; for FTD=0:

– set PSTC=PSTM

– set FTD (first

TRIGGER

detected)

– do not change PSTC,APT, APT_2b

– for (RMO=0 or SMC=1) and SGE1=1

: increment

INC_CNT1 by (MLT+1)

(1)

+MPVAL1

(2)

– send SUB_INC1 pulses with highest possible frequency when SGE1=1

Depending on TSL, TEN, DEN the leaving of step one is done with the next

TRIGGER input;

Note: Step 1 is also left in emergency mode when a valid

TRIGGER event appears in order to make a switch back to normal mode possible; 

_old - values are values valid at the last but one valid TRIGGER event;  for the whole table: use always

MLS1 instead of (MLT+1) for the case SMC=1;  dir_crement does mean:  increment for DIR1=0  decrement for DIR1=1 for SYT=0 and FTD =1: dir_crement APT and APT_2b by one; dir_crement

for

SGE1_delay

(3)

NMB_T_TAR

(4)

= 1 and TOR=0

PSTC by for (RMO=0 or SMC=1) and SGE1 = 1, TOR = 0

: increment

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RM0361 Digital PLL module (DPLL)

Step

Table 207. State description of the state machine (continued)

Description Comments

(continued)

2 for SYT=1 and TOR=0:

– dir_crement

APT, APT_2c

, dir_crement

APT_2b by

SYN_T_old

– dir_crement

for

SGE1_delay

(3)

= 1

PSTC by

NMB_T_TAR

(4)

– for (RMO = 0 or SMC = 1) and SGE1 = 1

: increment

INC_CNT1 by SYN_T*(MLT+1)

(1)

+ PD_store

(5)

MPVAL1 (2)

PD_store is 0 for AMT=0 within the DPLL_STATUS register:

– set LOCK1 bit accordingly;

Calculate TS_T according to equations

and

; calculate DT_T_ACT = TS_T - TS_T_OLD calculate RDT_T_ACT

calculate QDT_TX according to Equation 7

Send CDTI interrupt when NTI_CNT is zero or decrement

NTI_CNT when not zero; calculate EDT_T and MEDT_T according to equations

Equation 8 and Equation 9

for (RMO = 1 and SMC = 0): update SYN_T, PD_store and go back to step 1

Calculate CDT_TX according to

Equation 10

and

Equation

;

Note: There are different behaviors of

RM and HW-IP: For the HW-IP the values of SYN_T and

PD_store are not updated until a new valid TRIGGER slope occurs.

for RMO=0 or SMC=1; calculate missing pulses:

MP1 = INC_CNT1 (at the moment of a valid TRIGGER slope) calculate target pulses:

NMB_T_TAR = (MLT+1)

(1)

*SYN_T + PD_store + MPVAL1

(instead of PD_store use zero in the case AMT=0) for RMO=0 or SMC=1; add MPVAL1 only for PCM=1 and reset

PCM1 after that; sent MP with highest possible frequency and set

NMB_T = NMB_T_TAR for RMO=0 or SMC=1, DMO=0 and

COA=0 calculate the number of pulses to be sent

NMB_T = NMB_T_TAR + MP (see Equation 72

Equation

respectively)

for RMO=0 or SMC=1,

DMO=0 and COA=1

NMB_T = SYN_T*CNT_NUM_1 update SYN_T and PD_store; for RMO=0 or SMC=1,

DMO=1

Note:

There are different behaviors of

RM and HW-IP: For the HW-IP the values of SYN_T and

PD_store are not updated until a new valid TRIGGER slope occurs.

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Digital PLL module (DPLL) RM0361

Step

Table 207. State description of the state machine (continued)

Description Comments calculate ADD_IN_CAL1 according to

Equation 75

and

Equation 76

Equation 81

and store this value in RAM use ADD_IN_CAL1 as ADD_IN value for the case DLM = 0 use ADD_IN_LD1 as ADD_IN for the case DLM = 1, but do this update immediately (without waiting for this step 10); for DMO = DLM=0 and EN_C1u = 0: reset the FlipFlops in the SUB_INC1 generator; start sending SUB_INC1; calculate

TS_T_CHECK = TS_T + DT_T_ACT *(TOV) ; automatic setting of actions masking bits in the

DPLL_STATUS register: for SMC = 0: set CAIP1 = CAIP2 = 1 for SMC = 1: set only CAIP1 = 1 for RMO=0 or SMC=1 for DLM=0 for DLM=1 for RMO=0 or SMC=1; steps 12 to 16 are not valid for the combination: (SMC=0 and RMO=1) for all correspondent actions with ACT_N[i]=1 calculate:

NA[i] = (PSA[i] - PSTC)/(MLT+1)

(1)

for forward direction with w= integer part and b = remainder of the division (fractional part); for backward direction use

NA[i] = (PSTC - PSA[i])/(MLT+1)

(1)

and consider in both cases the time base overflow in order to get a positive difference actions 0…11 for SMC=1 actions 0…23 for SMC=0 depending on ACT_N[i] in

DPLL_ACT_STA register; calculate PDT_T[i] and DTA[i] for up to 24 action values

according to equations

Equation 34

calculate TSAC[i] according to according to

Equation 63

;

Equation 62

and PSAC[i] actions 0…11 for SMC=1 actions 0…23 for SMC=0 actions 0…11 for SMC=1 actions 0…23 for SMC=0 automatic resetting of actions masking bits in the

DPLL_STATUS register: for SMC=0: set CAIP1=CAIP2=0 for SMC=1: set only CAIP1=0; set the corresponding ACT_N[i] bits in the DPLL_ACT_STA register

Set ACT_N[i] for all enabled actions concerned:

0…11 for SMC=1

0…23 for SMC=0 check the relation of the last increment to its predecessor according to the profile and taking into account TOV: set the

ITN status bit and reset the corresponding LOCK bit, when not plausible; go to step 18, when no valid TRIGGER appears for all following steps 18 to 20: go immediately back to step 1, when a valid TRIGGER event occurs, interrupt all calculations there and reset all CAIP in that case; when going back to step 1: store TS_T in RAM 2b according to APT_2b; update RAM 2a and RAM 2d for all conditions

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Step

Table 207. State description of the state machine (continued)

Description Comments wait for a new PMTR value; set the corresponding CAIPx values and go to step 19 in that case go immediately to step 1 and update the RAM according to step 17 when a valid

TRIGGER

event occurs make the requested action calculation according to new

PMTR values go immediately to step 1 and update the RAM according to step 17 when a valid

TRIGGER

event occurs reset CAIPx and go back to step 18 go immediately to step 1 and update the RAM according to step 17 when a valid TRIGGER event occurs

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Step

Table 207. State description of the state machine (continued)

Description Comments

When DEN = 0 or SEN=0: stay in step 1 until DEN=1, SEN=1 and at least one valid

STATE has been detected (FSD=1); the following steps are performed always (not necessarily in step 21, but also in steps 38 to 40 (when waiting for new

PMTR values to be calculated): compare STATE_S with SSL (valid slope); for each invalid slope: generate a SISI interrupt;

– send missing STATE INT when TS_S_CHECK time is reached and set MS=1 (missing

STATE

bits) in that case; do not leave step 21 while no valid STATE appears.

When a valid STATE appears: store the actual position stamp at PSSM (value at the

STATE event) update RAM by

Equation 12 to

Equation 17

(see

Section 16.7.5: Update of RAM in normal and emergency mode );

store the actual INC_CNT1/2 at MP1/MP2 respectively as

missing pulses (instead of calculations in step 25) store all relevant configuration bits

of the

DPLL_CTRL(0,1) Registers in shadow registers and consider them for all corresponding calculations of steps 22 to 37 accordingly; the relevant bits are explained in the registers itself for FSD=0: set PSSC=PSSM set FSD (first STATE detected) do not increment PSSC for (RMO=1 and SMC=0) and SGE1=1

: increment

INC_CNT1 by MLS1+MPVAL1 (6) for (RMO=1 and SMC=1) and SGE2=1

: increment

INC_CNT2 by MLS2+MPVAL2 (6)

Depending on SSL, SEN, DEN the leaving of step 21 one is done with the next

STATE

input; for the steps 22-37: for SMC=1 replace:

MLS1 by MLS2,

LOCK1 by LOCK2;

SUB_INC1 by SUB_INC2;

CNT_NUM_1 by CNT_NUM_2;

MPVAL1 by MPVAL2;

EN_C1u by EN_C2u; dir_crement

does mean: increment for DIR2=0 decrement for DIR2=1 or DIR1 respectively for SYS=0, FSD =1 and SOR=0: dir_crement PSSC by NMB_S_TAR

SGE1_delay

(8)

(7)

for (SMC=0 and

= 1

) or (SMC=1 and

SGE2_delay

(9)

= 1

) increment INC_CNT1 by MLS1+MPVAL1

(6)

(for SMC=0,

SGE1=1

and RMO=1); increment INC_CNT2 by MLS2+MPVAL2

(6)

(for SMC=1,

SGE2=1

and RMO=1); dir_crement APS and APS_1c3

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Step

Table 207. State description of the state machine (continued)

Description Comments

(continued)

22 for SYS=1 and SOR=0: dir_crement

APS and APS_1c3 dir_crement APS_1c2 by SYN_S_old for RMO=1 and SMC=0: for

SGE1_delay

(8)

= 1 dir_crement

PSSC by NMB_S_TAR

(7)

; for SGE1=1 increment INC_CNT1 by SYN_S*MLS1 + PD_S_store +

MPVAL1

(6)

for RMO=1 and SMC=1: for

SGE2_delay

(9)

= 1 dir_crement

PSSC by NMB_S_TAR

(7)

; for SGE2=1 increment INC_CNT2 by SYN_S*MLS2 + PD_S_store (10)

+MPVAL2

(6)

within the DPLL_STATUS register: set LOCK1 or 2 bit accordingly; calculate TS_S according to equations

and

;

calculate DT_S_ACT = TS_S - TS_S_OLD calculate RDT_S_ACT calculate QDT_SX

24 send CDSI interrupt;

calculate EDT_S and MEDT_S according to Equation 19

and

Equation 20

for RMO=0: go back to step 21 for RMO=0 and update SYN_S and

PD_S_store using the current ADT_S[i] values in that case; calculate CDT_SX according to equation

Equation 21

and

Equation 22

;

Note:

There are different behaviors of

RM and HW-IP: For the HW-IP the values of SYN_S and

PD_S_store are not updated until a new valid STATE slope occurs.

only for RMO=1 only for RMO=1 calculate missing pulses

- for TBU_CH1: MP1 = INC_CNT1(valid STATE slope)

- for TBU_CH2: MP2 = INC_CNT2(valid STATE slope) calculate target number of pulses:

NMB_S_TAR = MLS1*SYN_S + PD_S_store +MPVAL1 (for

SMC=0)

NMB_S_TAR = MLS2*SYN_S + PD_S_store + MPVAL2 (for

SMC=1)

(instead of PD_S_store use zero in the case AMS=0) for SMC=0 instead of MPVAL1 use zero for

PCM1=0 for SMC=1 instead of MPVAL2 use zero for

PCM2=0; add MPVAL1/2 once to INC_CNT1/2 and reset PCM1/2 after that sent MPx with highest possible frequency and set

NMB_S = NMB_S_TAR only for RMO=1,

DMO=0 and COA=0 calculate number of pulses to be sent according to

Equation

NMB_S = NMB_S_TAR + MPx only for RMO=1,

DMO=0 and COA=1

NMB_S = SYN_S*CNT_NUM_1 (SMC=0)

NMB_S = SYN_S*CNT_NUM_2 (SMC=1) only for RMO=1,

DMO=1

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Step

Table 207. State description of the state machine (continued)

Description Comments update SYN_S and PD_S_store;

Note: There are different behaviors of

RM and HW-IP: For the HW-IP the values of SYN_S and

PD_S_store are not updated until a new valid STATE slope occurs.

calculate ADD_IN_CAL2 according to

Equation 77

(case a)

and Equation 77

(case b) or Equation 81

respectively and store this value in RAM use ADD_IN_CAL2 as ADD_IN value for the case DLM=0 use ADD_IN_LD2 as ADD_IN for the case DLM=1, but do this update immediately (without waiting for this step 30); for RMO=1, DMO=DLM=0 and EN_C1u=0 (EN_C1u=0): reset the FlipFlops in the SUB_INC1 or SUB_INC2 generator respectively; start sending SUB_INC1 / SUB_INC2; calculate

TS_S_CHECK = TS_S +

DT_S _ACT * (TOV_S); automatic setting of actions masking bits in the

DPLL_STATUS register:

CAIP1 and CAIP2 for SMC=0 only CAIP2 for SMC=1 for all actions with ACT_N[i]=0 calculate:

NA[i] = (PSA[i] - PSSC)/MLS1 for forward direction with w = integer part and b = remainder of the division (fractional part) for backward direction use

NA[i] = (PSSC - PSA[i])/(MLS1) and consider in both cases the time base overflow in order to get a positive difference only for RMO=1 for DLM=0 for DLM=1 only for RMO=1; for RMO=1 for SMC=0: 24 actions, for SMC=1: 12 actions; depending on ACT_N[i] in

DPLL_ACT_STA register use MLS2 as divider in the case of SMC=1 calculate PDT_S[i] and DTA[i] for up to 24 action values

according to equations

and

Equation 43

; only for RMO=1; for SMC=0 actions 0…23 for SMC=1 actions 12...23

calculate TSAC[i] according to

Equation 67 and PSAC[i] according to Equation 68

automatic reset of the actions masking bit CAIP in the

DPLL_STATUS register:

CAIP1=CAIP2=0 for SMC=0 and only CAIP2=0 for SMC=1 set the corresponding ACT_N[i] bits in the DPLL_ACT_STA register for the relevant actions (see above) and

RMO=1 for the relevant actions (see above) and

RMO=1

Set ACT_N[i] and reset ACT_WRi for all enabled actions

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Step

Table 207. State description of the state machine (continued)

Description Comments

40 check the duration of the last increment to its predecessor according to the profile and taking into account TOV_S: set the ISN status bit and reset the corresponding LOCK bit, when not plausible; go to step 38, when no valid STATE appears for all following steps 38 to 40: go immediately back to step 21, when a valid STATE event occurs, interrupt all calculations there and reset all CAIPx in that case; when going back to step 21: store TS_S in RAM 1c2 according to APS_1c2; update RAM 1c1 and RAM 1c4 for all conditions wait for a new PMTR value; set the corresponding CAIPx values and go to step 39 in that case go immediately to step 21 and update the RAM according to step 37 when a valid

STATE

event occurs make the requested action calculation according to new

PMTR values reset CAIP and go back to step 38 go immediately to step 21 and update the RAM according to step 37 when a valid STATE event occurs go immediately to step 21 and update the RAM according to step 37 when a valid

STATE

event occurs

1. Replace (MLT+1) by MLS1 for SMC=1.

Add MPVAL1 once to INC_CNT1, that means only when PCM1=1.

SGE1_delay is the value of SGE1 delayed by one valid TRIGGER event.

4. NMB_T_TAR is the target value of NMB_T of the last increment (see step 5 ff.).

5. PD_store = 0 for AMT=0 (see DPLL_CTRL_0 register).

6. Add MPVAL1 or MPVAL2 only once, that means as long as PCM1 or PCM2 is set respectively.

7. Target number of pulses of the last increment (see step 25 ff.)

SGE1_delay

is the value of SGE1 delayed by one valid STATE event.

SGE2_delay is the value of SGE2 delayed by one valid STATE event.

10. PD_S_store = 0 for AMS=0 (see DPLL_CTRL_0 register).

16.9 DPLL interrupt signals

The DPLL provides 27 interrupt lines. These interrupts are shown below.

Signal

DPLL_SORI_IRQ

DPLL_TORI_IRQ

DPLL_CDSI_IRQ

DPLL_CDTI_IRQ

DPLL_TE4_IRQ

Table 208. DPLL interrupt signals

Description

STATE

is out of range

TRIGGER

is out of range

STATE

duration calculated for last increment

TRIGGER duration calculated for last increment

TRIGGER

event interrupt 4 request

(1)

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Table 208. DPLL interrupt signals (continued)

Signal

DPLL_TE3_IRQ

DPLL_TE2_IRQ

DPLL_TE1_IRQ

DPLL_TE0_IRQ

DPLL_LL2_IRQ

DPLL_GL2_IRQ

DPLL_E_IRQ

DPLL_LL1_IRQ

DPLL_GL1_IRQ

DPLL_W1_IRQ

DPLL_W2_IRQ

DPLL_PW_IRQ

DPLL_TAS_IRQ

DPLL_SAS_IRQ

DPLL_MT_IRQ

Error interrupt request

TRIGGER

STATE

Missing TRIGGER

Description

TRIGGER

event interrupt 3 request

(1)

TRIGGER

event interrupt 2 request (1)

TRIGGER

event interrupt 1 request

(1)

TRIGGER

event interrupt 0 request

(1)

Lost of lock interrupt for SUB_INC2 request

Get of lock interrupt for SUB_INC2 request

Lost of lock interrupt for SUB_INC1 request

Get of lock interrupt for SUB_INC1 request

Write access to RAM region 1b or 1c interrupt request

Write access to RAM region 2 interrupt request

Plausibility window violation interrupt of

TRIGGER

request

active slope while NTI_CNT is zero interrupt request

active slope interrupt request

interrupt request

DPLL_MS_IRQ

DPLL_TIS_IRQ

DPLL_SIS_IRQ

DPLL_TAX_IRQ

DPLL_TIN_IRQ

Missing STATE interrupt request

TRIGGER inactive slope interrupt request

STATE

inactive slope interrupt request

TRIGGER

maximum hold time violation interrupt request

TRIGGER

minimum hold time violation interrupt request

DPLL_PE_IRQ

DPLL_PD_IRQ

DPLL enable interrupt request

DPLL disable interrupt request

1. See TINT value in the corresponding ADT_T[i] section of RAM region 2; see

Section 16.12.3: Memory DPLL_ADT_T[i]:

Adapt and Profile Values of the TRIGGER Increments in FULL_SCALE

Note: TEi_IRQ depends on the TINT value in ADT_T[i]

(n)

and is only active when SYT

(o)

=1.

n. see RAM region 2 explanations; see Section 16.12: DPLL RAM region 2 value description

o. see DPLL STATUS register; see

Section 16.11.30: DPLL_STATUS

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16.10 DPLL register overview

The registers available and the size of RAM region 2 depends on the GTM-IP implementation, refer to the Appendix B of your version (s ee

Section 22.3: References

)

Table 209. DPLL register overview

Details in section

16.11.1

16.11.2

16.11.3

16.11.4

16.11.5

16.11.6

Name

DPLL_CTRL_0

DPLL_CTRL_1

DPLL_CTRL_2

DPLL_CTRL_3

DPLL_CTRL_4

DPLL_CTRL_5 (1)

16.11.7

DPLL_ACT_STA

16.11.8

16.11.9

DPLL_OSW

DPLL_AOSV_2

DPLL_APT

DPLL_APS

DPLL_APT_2C

DPLL_APS_1C3

DPLL_NUTC

DPLL_NUSC

DPLL_NTI_CNT

DPLL_IRQ_NOTIFY

DPLL_IRQ_EN

DPLL_IRQ_FORCINT

DPLL_IRQ_MODE

DPLL_EIRQ_EN

INC_CNT1

INC_CNT2

DPLL_APT_SYNC

DPLL_APS_SYNC

TBU_TS0_T

Description Init value

Control Register 0

Control Register 1

Control Register 2 (actions 0-7 enable)

Control Register 3 (actions 8-15 enable)

0x003B_BA57

0xB000_0000

0x0000_0000

Control Register 4 (actions 16-23 enable)

Control Register 5 (actions 24-31 enable)

0x0000_0000

ACTION Status Register with connected shadow register

0x0000_0000

Offset and switch old/new address register 0x0000_0200

Address offset register for APT in RAM region 2 0x1810_0800

Actual RAM pointer to RAM regions 2a, b and d 0x0000_0000

Actual RAM pointer to regions 1c1, 1c2 and 1c4 0x0000_0000

Actual RAM pointer to RAM region 2c 0x0000_0000

0x0000_0000 Actual RAM pointer to RAM region 1c3

Number of recent TRIGGER events used for calculations (mod 2*(TNU +1-SYN_NT))

0x0001_2001

Number of recent

STATE

events used for calculations (e.g. mod 2*(SNU +1-SYN_NS) for

SYSF=0)

0x0000_2081

Number of active TRIGGER events to interrupt 0x0000_0000

Interrupt notification register 0x0000_0000

Interrupt enable register 0x0000_0000

Interrupt force register

Interrupt mode register

Error interrupt enable register

Counter for pulses for TBU_CH1_BASE to be sent in automatic end mode

Counter for pulses for TBU_CH2_BASE to be sent in automatic end mode when

SMC=RMO=1

0x0000_0000

0x0000_0000 old RAM pointer and offset value for TRIGGER 0x0000_0000 old RAM pointer and offset value for STATE 0x0000_0000

TBU_CH0_BASE value at last

TRIGGER

event 0x0000_0000

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Table 209. DPLL register overview (continued)

Details in section

Name Description

16.11.27

TBU_TS0_S

16.11.28

ADD_IN_LD1

16.11.29

ADD_IN_LD2

TBU_CH0_BASE value at last

STATE

event direct load input value for SUB_INC1 direct load input value for SUB_INC2

16.11.30

16.11.31

16.11.32

DPLL_STATUS

DPLL_ID_PMTR_0-31

(2)

Status Register

9 bit ID information for input signals PMT_0-31

(8:0)

DPLL_CTRL_0_SHADOW_TR

IGGER shadow register of DPLL_CTRL_0

16.11.33

16.11.34

16.11.35

DPLL_CTRL_0_SHADOW_ST

ATE

DPLL_CTRL_1_SHADOW_TR

IGGER shadow register of DPLL_CTRL_0 shadow register of DPLL_CTRL_1

DPLL_CTRL_1_SHADOW_ST

ATE shadow register of DPLL_CTRL_1

16.11.36

DPLL_RAM_INI initialization control and status for RAMs

1. This register is only available for device 4.

2. The registers DPLL_ID_PMTR 24-31 are only available for device 4.

Init value

0x0000_0000

0x0000_01FE

0x0000_0257

0x0000_0000

Name

PSA0 - PSA31 (1)

DTA0 - DTA31

Table 210. RAM region 1 map description

Description

Address offset in relation to

DPLL start address

RAM region 1a

384 bytes for 128 words of 24 Bits; this RAM is only accessible for DEN=0

0x0200 - 0x03FC

ACTION_i Position/Value action request Register (i =

0...31)

(2)

ACTION_i time to react before PSAi (i = 0...31)

# of

TRIGGER

STATE

increments to ACTION_i (i = 0...31) calculated relative time to ACTION_i (i = 0...31)

0x0200 - 0x027C (device 4)

0x0200 - 0x025C (device 1-3)

See

16.11.37

0x0280 - 0x02FC (device 4)

0x0260 - 0x02BC (device 1-3)

See

16.11.38

0x0300 - 0x037C (device 4)

0x02C0 - 0x031C (device 1-3)

See Memory DPLL_NA[i]:

Calculated Number of

TRIGGER/STATE Increments to Action i, (RAM1a, i=0...31) 16.11.39

0x0380 - 0x03FC (device 4)

0x0320 - 0x037C (device 1-3)

See

16.11.40

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RM0361

TS_T

TS_T_OLD

FTV_T

TS_S

TS_S_OLD

FTV_S

THMI

THMA

THVAL

Name

Digital PLL module (DPLL)

Table 210. RAM region 1 map description (continued)

Description

Address offset in relation to

DPLL start address

RAM Region 1b

0x0400-

0x05FC

Note:

The following registers for variables are located in RAM

Region 1b, read access by AEI via bus interface possible, writing results in an interrupt; data width of 3 Bytes used for 24 bit values

288 bytes for 96 words of 24

Bits

TRIGGER signal information stored

Actual signal

TRIGGER

Previous signal

time stamp register TRIGGER_TS

TRIGGER

TRIGGER_TS_old

time stamp register

0x0400/

0x0404

See 16.11.41

and

16.11.42

0x0404/

0x0400

Note: The switch of the LSB address bits is performed using the SWON register at 0x0020

0x0400…

0x0404

Actual signal do not use

TRIGGER

filter value

0x0408

See

16.11.43

0x040C

STATE signal information stored

Actual signal

STATE

time stamp register STATE_TS

filter value

0x0410/

0x0414

Previous signal

STATE

time stamp register STATE_TS_old

0x0414/

0x0410

Note:

The switch of the LSB address bits is performed using the SWON register at 0x0020.

0x0410…

0x0414

0x0418

do not use

TRIGGER

hold time min value

hold time max value measured last pulse time from valid to invalid slope do not use

TRIGGER

0x041C

0x0420

0x0424

0x0428

See

16.11.49

0x042C

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Name

Table 210. RAM region 1 map description (continued)

Description

Address offset in relation to

DPLL start address

TOV

TOV_S

ADD_IN_CAL1

ADD_IN_CAL2

MPVAL1

MPVAL2

NMB_T_TAR

NMB_S_TAR

Time out value of

TRIGGER

STATE , according to the last nominal increment a missing STATE

, according to the last nominal increment for a missing TRIGGER calculated ADD_IN value for SUB_INC1 generation calculated ADD_IN value for SUB_INC2 generation

0x0430

0x0434

0x0438

0x043C

missing pulses to be added/subtracted directly to SUB_INC1 and INC_CNT1 once

0x0440

See 16.11.54

missing pulses to be added/subtracted directly to SUB_INC2 and INC_CNT2 once

0x0444

See

16.11.55

target number of TRIGGER pulses

NMB_T_TAR_OLD target number of TRIGGER pulses target number of STATE pulses

NMB_S_TAR_OLD target number of STATE pulses do not use

0x0448

0x044C

0x0450

0x0454

0x0458... 0x045C

RCDT_TX

RCDT_SX reciprocal value of expected increment duration (T) reciprocal value of expected increment duration (S)

0x0460

0x0464

RCDT_TX_NOM

RCDT_SX_NOM

RDT_T_ACT

RDT_S_ACT

DT_T_ACT

DT_S_ACT reciprocal value of the expected nominal increment duration

(T) reciprocal value of the expected nominal increment duration

(S) actual reciprocal value of actual reciprocal value of

Duration of last

TRIGGER

STATE

TRIGGER

STATE

increment

0x0468

0x046C

0x0470

0x0474

0x0478

0x047C

Calculated immediate values (equations

to 22

)

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RM0361

Name

EDT_T

MEDT_T

EDT_S

MEDT_S

CDT_TX

CDT_SX

CDT_TX_NOM

CDT_SX_NOM

TLR

SLR

PDT_[i]

(3)

MLS1

MLS2

CNT_NUM_1

CNT_NUM_2

PVT

Digital PLL module (DPLL)

Table 210. RAM region 1 map description (continued)

Description

Address offset in relation to

DPLL start address

Absolute error of prediction for last

(without consideration of missing events)

TRIGGER

locking range value; the TOR bit in the

DPLL_STATUS register is set when violated

STATE

TRIGGER

increment

Average absolute error of prediction up to the last TRIGGER increment absolute error of prediction for last

STATE

increment

Average absolute error of prediction up to the last increment

Expected duration of current

TRIGGER

STATE

increment

Expected nominal duration of current

TRIGGER

STATE

(without consideration of missing events)

STATE

increment

locking range value; the SOR bit is set when violated

0x0480

0x0484

0x0488

0x048C

0x0490

0x0494

0x0498

0x049C

0x04A0

0x04A4

Relations of the sum of prediction increments to the reference increment in the past (see equations in sections

16.7.1

16.7.2

16.7.3

16.7.4

for calculation)

predicted time to ACTION_[i]

(3)

0x0500...

0x057C

See 16.11.78

do not use

Calculated number of sub-pulses between two STATE events

(to be set by CPU)

0x0580 - 0x05BC

0x05C0

See 16.11.79

Calculated number of sub-pulses between two STATE events

(to be set by CPU) for the use when SMC=RMO=1

0x05C4

See 16.11.80

number of sub-pulses of SUB_INC1 in continuous mode, updated by the host only number of sub-pulses of SUB_INC2 in continuous mode, updated by the host only

Plausibility value of next active do not use

TRIGGER slope

0x05C8

See 16.11.81

0x05CC

See 16.11.82

0x05D0

See 16.11.83

0x05D4...

0x05DC

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Digital PLL module (DPLL) RM0361

Name

Table 210. RAM region 1 map description (continued)

Description

Address offset in relation to

DPLL start address

PSTC

PSTM

PSTM_OLD

PSSM

PSSM_OLD

Accurate calculated position stamp of last

PSSC Accurate

Measured position stamp at last valid

TRIGGER

STATE

TRIGGER

input;

input

0x05E0

See 16.11.84

0x05E4

See 16.11.85

0x05E8/

0x05EC

Measured position stamp at last but one valid

TRIGGER

input

0x05EC/

0x05E8

See 16.11.86

and

16.11.87

Measured position stamp at last valid STATE input

Measured position stamp at last but one valid STATE input

0x05F0/

0x05F4

See 16.11.88

and

16.11.89

0x05F4/

0x05F0

See 16.11.88

and

16.11.89

NMB_T

NMB_S

Number of pulses of current increment in normal mode for

SUB_INC1(see

Equation 72

or for SMC=1 equation Equation

respectively)

0x05F8

See 16.11.90

Number of pulses of current increment in emergency mod for

SUB_INC1 (see equation

Equation 73

) or in the case SMC=1

for SUB_INC2 (see Equation 79

)

0x05FC

See

16.11.91

RAM Region 1c

0x0600 –

0x09FC

See

16.11.92

1c1

RDT_S0

RDT_S1

…

RDT_S63

Note: The following registers for the signal STATE are located in RAM Region 1c, read access by AEI via bus interface possible, writing results in an interrupt; data width of 3 Bytes used for 24 bit values

0,75 Kbytes for 256 words of

24 Bits

Reciprocal values of the corresponding successive increments RDT_S[i] (see

Equation 13

and

Equation 16

); the values are calculated using the recent NUSE increments (see

NUSC register at address 0x0038)

RDT_S0

RDT_S1 up to 2*(SNU+1)-SYN_NS valid entries

RDT_S63

0x0600

0x0604

…

0x06FC

See 16.11.92

1c2 Time stamp field for STATE events

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RM0361 Digital PLL module (DPLL)

Name

Table 210. RAM region 1 map description (continued)

Description

Address offset in relation to

DPLL start address

TSF_S0

TSF_S1

…

TSF_S63

TSF_S0

TSF_S1 up to

2*(SNU+1) valid entries

TSF_S63

0x0700

See 16.11.93

0x0704

See 16.11.93

…

0x07FC

See

16.11.93

1c3

Adapt values for the current STATE increment; time stamp values bits 24-27 in addition to the corresponding

24 bit value of TSF_Sx above, stored in bits 23:20 of

ADT_S[i];

ADT_S0

ADT_S1

…

ADT_S63

ADT_S0

ADT_S1 up to

2*(SNU+1)-SYN_NS valid entries

ADT_S63

0x0800

0x0808

…

0x08FC

See

16.11.94

1c4

Uncorrected last increment value of STATE (DT_S) for

FULL_SCALE; measuring data of increments without corrections used for the CPU to generate ADT_S values

DT_S0

DT_S1

…

DT_S63

DT_S0

DT_S1 up to

2*(SNU+1)-SYN_NS valid entries

DT_S63

0x0900

See 16.11.95

0x0904

See 16.11.95

…

0x09FC

See 16.11.95

1. The values PSA24-31, DLA24-31, NA24-31 and DTA24-31 in RAM 1a are only available for device 4.

2. The registers DPLL_TSAC24-31, DPLL_PSAC24-31 and DPLL_ACB_6-7 are only available for device 4.

3. The values PDT_24 to PDT_31 in RAM1b are only available for device 4.

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Digital PLL module (DPLL) RM0361

Table 211. Register region EXT map description

Address offset in relation to

DPLL start address

Name Description Init value

0x0E00 -

0x0F1C

Register Region EXT extension of register region in order to allow up to 32 action calculations

(device 4)

0x0E00 -

0x0E7C

See 16.11.96

0x0E80 -

0x0EFC

0x0F00

0x0F04

0x0F08

0x0F0C

0x0F10

0x0F14

0x0F18

0x0F1C

DPLL_TSAC0-TSAC31

DPLL_ACB_0

DPLL_ACB_1

DPLL_ACB_2

DPLL_ACB_3

DPLL_ACB_4

DPLL_ACB_5

DPLL_ACB_6

DPLL_ACB_7

(1)

calculated action time stamps for actions 0...31

calculated action position stamps for actions 0...31

control bits for actions 0...3

control bits for actions 4...7

control bits for actions 8...11

control bits for actions 12...15

control bits for actions 16...19

control bits for actions 20...23

control bits for actions 24...27

control bits for actions 28...31

0x007F_FFFF

0x0000_0000

1. The registers DPLL_TSAC24-31, DPLL_PSAC24-31 and DPLL_ACB_6-7 are only available for device 4.

396/558 DocID025070 Rev 1

Region 2a

RDT_T0

See

16.12.1

RDT_T1

See

16.12.1

…

RDT_T1023

See

16.12.1

Region 2b

TSF_T0

See

16.12.2

TSF_T1

See

16.12.2

…

RM0361

Name

Digital PLL module (DPLL)

Table 212. RAM region 2 map description

Description

Address offset in relation to

DPLL start address

RAM Region 2

0x4000 –

0x4800...

0x7FFC depending on device chosen

See

16.12

Note:

The following registers for the signal

TRIGGER are located in RAM region 2, read access by AEI via bus interface possible, write access results in an interrupt, when enabled; data width of 3 bytes used for 24 bit values.



The RAM field part contains up to 1024 values and all are configurable for 128, 256, 512 or 1024 values in order to select the RAM size needed.



The maximum available RAM size depends on the device as shown below:  device 1: 512 words á 24 bits  device 2: 1024 words á 24 bits  device 3: 2048 words á 24 bits  device 4: 4096 words á 24 bits size from 1,5 Kbytes to 12

Kbytes configurable for word sizes of 24 Bits

Reciprocal values of the corresponding successive increments RDT_T[i] (see equations

(case a and case b));

Address offsets are given by the AOSV_2a

AOSV_2a values are addresses after shift left by 8

RDT_T0 AOSV_2a

RDT_T1

… 2*(TNU+1-SYN_NT) valid entries

RDT_T1023

Time stamp field for all TRIGGER events in

FULL_SCALE; 24 bit time stamp values

TSF_T0

TSF_T1

… 2*(TNU+1) valid entries

…

+4092

AOSV_2b

…

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Digital PLL module (DPLL)

Name

TSF_T1023

See

16.12.2

Region 2c

ADT_T0

See

16.12.3

ADT_T1

See

16.12.3

…

ADT_T1023

See

16.12.3

Region 2d

DT_T0

See

16.12.4

DT_T1

See

16.12.4

…

DT_T1023

See

16.12.4

RM0361

Table 212. RAM region 2 map description

Description

Address offset in relation to

DPLL start address

TSF_T1023

ADT_T values to correct the measured

TRIGGER signal values; time stamp values bits 24-27 in addition to the 24 bit value of TSF_Tx, stored in the bits 23:20 of

ADT_T[i]

+4092

ADT_T0 AOSV_2c

ADT_T1

… 2*(TNU+1-SYN_NT) valid entries

ADT_T1023

Uncorrected last increment values of TRIGGER

(DT_T); measuring raw data of increments

DT_T0

DT_T1

… 2*(TNU+1-SYN_NT) valid entries

DT_T1023

…

+4092

AOSV_2d

…

+4092

16.11 DPLL register and Memory description

Description of Registers beginning from Register DPLL_CTRL_0.

Description of RAM Regions beginning from RAM 1a (see below): bits 31 down to 24 in each RAM region are not implemented and therefore always read as zero (reserved). Other bits which are declared as reserved are not protected against writing.

Reserved address regions are not protected against writing.

Description of memory region RAM 1a beginning from Memory PSA[i]: the RAM Region 1a is writable only for DEN=0 (see DPLL_CTRL_1 register).

Description of memory region RAM1b beginning from Memory TS_T.

Description of memory region RAM1c beginning from Memory RDT_S.

Description of register region EXT beginning from Register DPLL_TSAC[i]:

398/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL) this is an extension of the normal register region above in order to allow up to 32 action calculations (device 4).

Description of memory region RAM 2 beginning from Memory RDT_T.

Address offset: see Appendix B Initial value: 0x003B_BA57

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[22:31]

[16:20]

[7:15]

Table 213. DPLL_CTRL_0 field description

Description

MLT

(1)

: multiplier for TRIGGER ; MLT+1 is number of SUB_INC1 pulses between two

TRIGGER events in normal mode (1…1024);

For emergency mode the number of SUB_INC1 pulses between two STATE events is calculated by the CPU using the formula MLS1=(MLT+1)* (TNU+1) / (SNU+1) in order to get the same number of SUB_INC1 pulses for FULL_SCALE. This value is stored in RAM at

0x05C0. Change of MLT by the CPU must result in the corresponding change of MLS1 by the

CPU for SMC=0.

Note:

The number of MLT events is the binary value plus 1. The value MLT+1 is replaced by

MLS1 in the case of SMC=1 (see DPLL_CTRL_1 register) for all relevant calculations.

IFP

(1)

(2)(3)

: Input filter position ; value contains position or time related information.

0 = TRIGGER_FT and STATE_FT mean time related values, that means the number of time stamp clocks

1 = TRIGGER_FT and STATE_FT mean position related values, that means the number of

SUB_INC1 (or SUB_INC2 in the case SMC=1) pulses respectively

SNU

(4)

STATE number

; SNU+1 is number of nominal STATE events in HALF_SCALE

(1…32).

Note:

The number of nominal STATE events is the binary value plus 1. This value can only be written when the DPLL is disabled.

TNU

(4)

TRIGGER number ; TNU+1 is number of nominal TRIGGER events in HALF_SCALE

(1…512).

Note: The number of nominal TRIGGER events is the binary value plus 1. This value can only be written when the DPLL is disabled.

AMS

(2)

: Adapt mode STATE ; Use of adaptation information of STATE.

0 =No adaptation information is used for STATE

1 =Immediate adapting mode; the values ADT_S[i] are considered to calculate SUB_INC1 pulses in emergency mode (SMC=0) or SUB_INC2 pulses for SMC=1

AMT

(1)

: Adapt mode TRIGGER ; Use of adaptation information of TRIGGER.

0 =No adaptation information for TRIGGER is used

1 =Immediate adapting mode; the values ADT_T[i] are considered to calculate the SUB_INC1 pulses in normal mode and for SMC=1

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Digital PLL module (DPLL) RM0361

Table 213. DPLL_CTRL_0 field description

Bit

Description

IDS

(2)

: Input delay STATE ; Use of input delay information transmitted in FT part of the

STATE signal.

0 =Delay information is not used

1 =Up to 24 bits of the FT part contain the delay value of the input signal, concerning the corresponding edge

IDT

(1)

Input delay TRIGGER

; use of input delay information transmitted in FT part of the

TRIGGER signal.

0 =Delay information is not used

1 =Up to 24 bits of the FT part contain the delay value of the input signal, concerning the corresponding edge

SEN : STATE enable .

0 =STATE signal is not enabled (no signal considered)

1 =STATE signal is enabled

TEN

TRIGGER enable

0 =TRIGGER signal is not enabled (no signal considered)

1 =TRIGGER signal is enabled

RMO

(1) (2)

Reference mode ; selection of the relevant the input signal for generation of

SUB_INC1.

0 =Normal mode; the signal TRIGGER is used to generate the SUB_INC1 signals

1 =Emergency mode for SMC=0; signal STATE is used to generate the SUB_INC1 signals;

Double synchronous mode for SMC=1: signal TRIGGER is used to generate the

SUB_INC1 signals and STATE is used to generate the SUB_INC2 signals

Note: for SMC=0: TRIGGER and STATE are prepared to calculate SUB_INC1. The RMO bit gives a decision only, which of them is used.



For changing from normal mode to emergency mode at the following TRIGGER slope

(according to the RMO value in the shadow register)

(1)

the PSSC value is calculated by

PSSC = PSSM + correction_value (forward direction) or PSSC = PSSM - correction value (backward direction) with the correction_value = inc_cnt1 - nmb_t.



For changing from emergency mode to normal mode at the following STATE slope

(according to the RMO value in the shadow register)

(2)

the PSTC value is calculated by

PSTC = PSTM + correction_value (forward direction) or PSTC = PSTM - correction value (backward direction) with the correction_value = inc_cnt1 - nmb_s. 

In the case of no further TRIGGER or STATE events appearing the CPU has to perform the corrections above accordingly.

1. Stored in an independent shadow register for a valid TRIGGER event and for DEN = 1.

2. Stored in an independent shadow register for a valid STATE event and for DEN = 1.

3. For IFP=1 the time between two valid TRIGGER or STATE events must be always greater than 2,34 ms and the value x of

MLT, MLS1 or MLS2 must be chosen so that the number of time stamp pulses between two SUB_INC events must be less than 65536. This is fulfilled when x is greater than 256.

4. The time between two valid STATE or TRIGGER events must be always greater than 23,4 µs; in addition the TS_CLK and the resolution must be chosen so that for each nominal increment the time stamps at the beginning and the end of the increment differ at least in the value of 257.

400/558 DocID025070 Rev 1

RM0361 Digital PLL module (DPLL)

16.11.2 Register DPLL_CTRL_1 Control Register 1

Address offset: see Appendix B Initial value: 0xB000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 214. DPLL_CTRL_1 field description

Description

DMO

(1) (2) :

DPLL mode select

0 =Automatic end mode; if the number of pulses for a increment is reached, no further pulse is generated until the next valid TRIGGER/STATE is received; in the case of getting a new valid

TRIGGER/STATE before the defined number of pulses is reached, the pulse frequency is changed according to the conditions described below (COA)

1 =Continuous mode; in this mode a difference between the predefined number of pulses and the actual number of generated pulses can influence the pulse frequency by writing a corresponding pulse number into CNT_NUM_1 or CNT_NUM_2 respectively in RAM region

1b.

DEN

DPLL enable

0 =The DPLL is not enabled; Disabling the DPLL will result in a reset state of the

DPLL_STATUS register which remains in this state until DEN=1. No DPLL related interrupt will be generated in that case.

1 =The DPLL is enabled;

Note:

The bits 31 down to 0 of the DPLL_STATUS register are cleared, when the DPLL is disabled. Some bits of the control registers can be set only when DEN=0. The protected bits in the DPLL_CTRL_1 register can not be written when simultaneously DEN is set to

IDDS : Input direction detection strategy in the case of SMC=0

0 =The input direction is detected comparing the THMI value with the duration between valid and invalid slope of TRIGGER.

1 =The input direction is detected using TDIR input signal also in the case SMC=0.

Note:

This bit can only be written when the DPLL is disabled and be fixed to zero, when not needed for an implementation. Independent of the value of IDDS is the direction information for TRIGGER in the case SMC=0 always considered at the moment when the invalid slope appears.

COA

(1) (2)

Correction strategy in automatic end mode

(DMO=0).

0 =The pulse frequency of the CMU_CLK0 will be used to make up for missing pulses from last increment; the output of the calculated new pulses will start after resetting the FFs in the pulse generation unit. The frequency of CMU_CLK0 should not exceed half the frequency of

the system clock (see

Figure 72

1 =missing pulses of the last increment are distributed evenly to the next increment, calculations are done when the next valid input event appears. The number of missing subpulses will be determined by the pulse counter difference between the last two valid

TRIGGER/STATE events respectively; the FFs in the pulse generation unit are not reset before sending new pulses.

Note: For SMC=RMO=1: COA is used for SUB_INC1 and SUB_INC2.

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Bit

[16:20]

RM0361

Table 214. DPLL_CTRL_1 field description (continued)

Description

PIT

(1)

: Plausibility value PVT to next valid TRIGGER is time related

0 =the plausibility value is position related (PVT contains the number of SUB_INC1 pulses)

1 =the plausibility value is time related (the PVT value is to be multiplied with the duration of the last increment DT_T_ACT and divided by 1024)

SGE1

(1) (2)

: SUB_INC1 generator enable.

0 =The SUB_INC1 generator is not enabled

1 =The SUB_INC1 generator is enabled

DLM1

(1) (2)

: Direct Load Mode for SUB_INC1 generation

0 =the DPLL uses the calculated ADD_IN_CAL value for the SUB_INC1 generation

1 =the ADD_IN_LD value is used for the SUB_INC1 generation and is provided by the CPU; the value remains valid until the CPU writes a new one; the calculated ADD_IN values are stored as ADD_IN_CAL in the RAM at different locations for normal and emergency mode

PCM1

(1) (2)

(3)

: Pulse Correction Mode for SUB_INC1 generation.

0 =the DPLL does not use the correction value stored in MPVAL1

1 =the DPLL uses the correction value stored in MPVAL1 in normal and emergency mode

SGE2

(2)

: SUB_INC2 generator enable.

0 =The SUB_INC2 generator is not enabled

1 =The SUB_INC2 generator is enabled

DLM2

(2)

: Direct Load Mode for SUB_INC2 generation

0 =the DPLL uses the calculated ADD_IN_CAL value for the SUB_INC2 generation

1 =the ADD_IN_LD value is used for the SUB_INC2 generation and is provided by the CPU; the value remains valid until the CPU writes a new one; the calculated ADD_IN values are stored as ADD_IN_CAL in the RAM at different locations for normal and emergency mode

PCM2

(2)(3)

: Pulse Correction Mode for SUB_INC2 generation.

0 =the DPLL does not use the correction value stored in MPVAL2

1 =the DPLL uses the correction value stored in MPVAL2

SYN_NS : Synchronization number of STATE; summarized number of virtual increments in

HALF_SCALE sum of all systematic missing STATE events in HALF_SCALE (for SYSF=0) or

FULL SCALE (for SYSF=1) ; the SYN_NS missing STATES can be divided up to an arbitrary number of blocks. The pattern of events and missing events in FULL_SCALE is shown in

RAM region 1c3 as value NS in addition to the adapt values. The number of stored increments in FULL_SCALE must be equal to 2*(SNU+1-SYN_NS) for SYSF=0 or

2*(SNU+1)-SYN_NS for SYSF=1. This pattern is written by the CPU beginning from a fixed reference point (maybe beginning of the FULL_SCALE region). The relation to the actual increment is established by setting of the profile RAM pointer APS_1c3 in an appropriate relation to the RAM pointer APS of the actual increment by the CPU.

Note:

This value can only be written when the DPLL is disabled.

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RM0361

Bit

[10:15]

Digital PLL module (DPLL)

Table 214. DPLL_CTRL_1 field description (continued)

Description

SYN_NT : Synchronization number of TRIGGER; summarized number of virtual increments in

HALF_SCALE sum of all systematic missing TRIGGER events in HALF_SCALE; the

SYN_NT missing TRIGGER can be divided up to an arbitrary number of blocks. The pattern of events and missing events in FULL_SCALE is shown in RAM region 2c as value NT in addition to the adapt values. The number of stored increments in FULL_SCALE must be equal to 2*(TNU-SYN_NT). This pattern is written by the CPU beginning from a fixed reference point (maybe beginning of the FULL_SCALE region). The relation to the actual increment is established by setting of the profile RAM pointer APT_2c in an appropriate relation to the RAM pointer APT of the actual increment by the CPU.

Note:

This value can only be written when the DPLL is disabled.

LCD : Locking condition definition

0 =locking condition definition is one times missing TRIGGERs as expected by the profile in

HALF_SCALE (one gap)

1 =locking condition definition is n-1 times missing TRIGGERs as expected by the profile in

HALF_SCALE (one additional tooth)

Note:

This bit can only be written when the DPLL is disabled and be fixed to zero, when not needed for an implementation.

SWR : Software reset resets all register and internal states of the DPLL

0 =no software reset enabled

1 =software reset enabled

Setting the SWR bit results only in a software reset when the DPLL is not enabled (DEN=0).

SYSF

: SYN_NS for FULL_SCALE the value SYN_NS does mean the sum of all systematic missing STATE events in

HALF_SCALE (for SYSF=0) or FULL SCALE (for SYSF=1)

0 =the SYN_NS value is valid for HALF_SCALE

1 =the SYN_NS value is valid for FULL_SCALE

Note: This value can only be written when the DPLL is disabled.

TS0_HRS

: Time stamp high resolution STATE

0 =the resolution of the used DPLL input TBU_TS0 bits is equal to the STATE input time stamp resolution

1 =the STATE input time stamps have a 8 times higher resolution as the TBU_TS0 DPLL input

Note: This bit can only be written when the DPLL is disabled.

TS0_HRT : Time stamp high resolution TRIGGER

0 =the resolution of the used DPLL input TBU_TS0 bits is equal to the TRIGGER input time stamp resolution

1 =the TRIGGER input time stamps have a 8 times higher resolution as the TBU_TS0 input

Note:

This bit can only be written when the DPLL is disabled.

SMC : Synchronous Motor Control

0 =TRIGGER and STATE inputs are used for a control different to SMC

1 =the TRIGGER input reflects a combined sensor signal for SMC and in the case of RMO=1 also STATE reflects a different combined sensor signal

Note:

: This bit can only be written when the DPLL is disabled.

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Bit

Table 214. DPLL_CTRL_1 field description (continued)

Description

[2:3]

[0:1]

SSL : STATE slope select; Definition of active slope for signal STATE each active slope is an event defined by SNU. Set by DEN=0 only.

00:No slope of STATE will be used; this value makes only sense in normal mode

01:Low high slope will be used as active slope, only inputs with a signal value of “1” will be considered

10:High low slope will be used as active slope, only inputs with a signal value of “0” will be considered

11:Both slopes will be used as active slopes

Note: This bit can only be written when the DPLL is disabled.

TSL

: TRIGGER slope select; Definition of active slope for signal TRIGGER each active slope is an event defined by TNU. Set by DEN=0 only.

00:No slope of TRIGGER will be used; this value makes only sense in emergency mode

01:Low high slope will be used as active slope, only inputs with a signal value of “1” will be considered

10:High low slope will be used as active slope, only inputs with a signal value of “0” will be considered

11:Both slopes will be used as active slopes

Note: This bit can only be written when the DPLL is disabled.

1. Stored in an independent shadow register for a valid TRIGGER event and for DEN = 1.

2. Stored in an independent shadow register for a valid STATE event and for DEN = 1.

3. Bit is cleared, when transmitted to shadow register.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:31]

Table 215. DPLL_CTRL_2 field description

Description

Reserved

Note:

Read as zero, should be written as zero.

AEN0

(1) : ACTION_0 enable.

0= the corresponding action is not enable

1= the corresponding action is enabled

AEN1

(1)

: ACTION_1 enable.

See bit 23

AEN2

(1)

: ACTION_2 enable.

See bit 23

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Bit

Table 215. DPLL_CTRL_2 field description

Description

[0:7]

AEN3 : ACTION_3 enable.

See bit 23

AEN4

(1)

: ACTION_4 enable.

See bit 23

AEN5

(1)

: ACTION_5 enable.

See bit 23

AEN6

(1)

: ACTION_6 enable.

See bit 23

AEN7

(1)

: ACTION_7 enable.

See bit 23

WAD0

: Write control bit of Action_0.

0= the corresponding AENi bit is not writeable

1= the corresponding AENi bit is writeable

WAD2

: Write control bit of Action_2.

See bit 15

WAD3 : Write control bit of Action_3.

See bit 15

WAD4 : Write control bit of Action_4.

See bit 15

WAD5 : Write control bit of Action_5.

See bit 15

WAD6

: Write control bit of Action_6.

See bit 15

WAD7

: Write control bit of Action_7.

See bit 15

WAD8

: Write control bit of Action_8.

See bit 15

Note:

For writing WADi =1 only the corresponding the AENx bits are written. The AENi bits remain unchanged when the corresponding WADi=0.

Reserved

Note:

Read as zero, should be written as zero.

1. This bit can only be written when the correspondent WADi Bit is set. It can be set for debug purposes by CPU also, when

DPLL is disabled. The enable bit becomes active only when the DPLL is in operation (DEN=1).

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16.11.4 Register DPLL_CTRL_3 Action Enable Register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:31]

Table 216. DPLL_CTRL_3 field description

Description

Reserved

Note: Read as zero, should be written as zero.

AEN8

(1)

: ACTION_8 enable.

0= the corresponding action is not enabled

1= the corresponding action is enabled

AEN9

(1)

: ACTION_9 enable.

See bit 23

AEN10

(1)

: ACTION_10 enable.

See bit 23

AEN11 : ACTION_11 enable.

See bit 23

AEN12

(1)

: ACTION_12 enable.

See bit 23

AEN13

(1)

: ACTION_13 enable.

See bit 23

AEN14

(1)

: ACTION_14 enable.

See bit 23

AEN15

(1)

: ACTION_15 enable.

See bit 23

WAD8 : Write control bit of Action_8.

0= the corresponding AENi bit is not writable

1= the corresponding AENi bit is writable

WAD9

: Write control bit of Action_9.

See bit 15

WAD10

: Write control bit of Action_10.

See bit 15

WAD11

: Write control bit of Action_11.

See bit 15

WAD12

: Write control bit of Action_12.

See bit 15

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Bit

Table 216. DPLL_CTRL_3 field description (continued)

Description

WAD13 : Write control bit of Action_13.

See bit 15

WAD14 : Write control bit of Action_14.

See bit 15

WAD15 : Write control bit of Action_15.

See bit 15

Note: For writing WADi =1 only the corresponding the AENx bits are written. The AENi bits remain unchanged when the corresponding WADi=0.

[0:7]

Reserved

Note:

Read as zero, should be written as zero.

1. This bit can only be written when the correspondent WADi Bit is set. It can be set for debug purposes by CPU also, when

DPLL is disabled. The enable bit becomes active only when the DPLL is in operation (DEN=1).

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:31]

Table 217. DPLL_CTRL_4 field description

Description

Reserved

Note:

Read as zero, should be written as zero.

AEN16

(1)

: ACTION_16 enable.

0= the corresponding action is not enabled

1= the corresponding action is enabled

AEN17

(1) : ACTION_17 enable.

see bit 23

AEN18

(1) : ACTION_18 enable.

see bit23

AEN19

: ACTION_19 enable.

see bit 23

AEN20

(1) : ACTION_20 enable.

see bit 23

AEN21

(1) : ACTION_21 enable.

see bit 23

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Table 217. DPLL_CTRL_4 field description (continued)

Bit

Description

AEN22

(1)

: ACTION_22 enable.

see bit 23

AEN23

(1)

: ACTION_23 enable.

see bit 23

WAD16 : Write control bit of Action_16.

0= the corresponding AENi bit is not writable

1= the corresponding AENi bit is writable

WAD17

: Write control bit of Action_17.

see bit 15

WAD18

: Write control bit of Action_18.

see bit 15

WAD19

: Write control bit of Action_19.

see bit 15

WAD20

: Write control bit of Action_20.

see bit 15

WAD21

: Write control bit of Action_21.

see bit 15

WAD22

: Write control bit of Action_22.

see bit 15

WAD23

: Write control bit of Action_23.

see bit 15

[0:7]

Reserved

Note: Read as zero, should be written as zero.

1. This bit can only be written when the correspondent WADi Bit is set. It can be set for debug purposes by CPU also, when

DPLL is disabled. The enable bit becomes active only when the DPLL is in operation (DEN=1).

Note: For writing WADx =1 only the corresponding the AENx bits are written. The AENx bits remain unchanged when the corresponding WADx=0.

DPLL_CTRL_5

(p)

Action Enable Register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value p. This register is only available for device 4.

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Table 218. DPLL_CTRL_5 field description

Description

Reserved

Note:

Read as zero, should be written as zero.

AEN24

(1)

: ACTION_24 enable.

0= the corresponding action is not enabled

1= the corresponding action is enabled

AEN25

(1)

: ACTION_25 enable.

see bit 23

AEN26

(1)

: ACTION_26 enable.

see bit 23

AEN27

(1)

: ACTION_27 enable.

see bit 23

AEN28

(1)

: ACTION_28 enable.

see bit 8

AEN29

(1)

: ACTION_29 enable.

see bit 23

AEN30

(1)

: ACTION_30 enable.

see bit 23

AEN31 : ACTION_31 enable.

see bit 23

WAD24 : Write control bit of Action_24.

0= the corresponding AENi bit is not writable

1= the corresponding AENi bit is writable

WAD25 : Write control bit of Action_25.

see bit 15

WAD26 : Write control bit of Action_26.

see bit 15

WAD27

: Write control bit of Action_27.

see bit 15

WAD28

: Write control bit of Action_28.

see bit 15

WAD29

: Write control bit of Action_29.

see bit 15

WAD30

: Write control bit of Action_30.

see bit 15

Digital PLL module (DPLL)

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Bit

Table 218. DPLL_CTRL_5 field description (continued)

Description

WAD31 : Write control bit of Action_31.

see bit 15

Note: For writing WADx =1 only the corresponding the AENx bits are written. The AENi bits remain unchanged when the corresponding WADx=0.

[0:7]

Reserved

Note:

Read as zero, should be written as zero.

1. This bit can only be written when the correspondent WADi Bit is set. It can be set for debug purposes by CPU also, when

DPLL is disabled. The enable bit becomes active only when the DPLL is in operation (DEN=1).

Note: For writing WADx =1 only the corresponding the AENx bits are written. The AENx bits remain unchanged when the corresponding WADx=0.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 219. DPLL_ACT_STA field description

Description

[8:31]

[0:7]

ACT_N[i],(i=0...23) : New output data values concerning to action i provided

0 =no new output data available after a recent PMT request or actual event value is in the past or invalid

1 =new PMTR data received or calculation is to be precised by taking into account new

TRIGGER or STATE values

Note:

ACT_N[i] is set (for AENi=1 and a new valid PMTR), that means when new action data are to be calculated for the correspondent action. After each calculation of the new actions values the ACT_N[i] bit updates the corresponding bit in the connected shadow register. The status of the ACT_N[i] bits in the shadow register is reflected by the corresponding DPLL output signal ACT_V (valid bit).



Reset together with the corresponding shadow register bit for AENi=0;  reset without the corresponding shadow register bit when the calculated event is in the past (the shadow register bit is set, when it was not set before in that case) the corresponding shadow register bit is reset, when new PMTR data are written or when the provided action data are read (blocking read) writeable for debugging purposes together with the corresponding shadow register when DEN=0

Note:

These bits can only be written for test purposes when the DPLL is disabled.

Reserved

(1)

or ACT_N[i]

(2)

,(i=24...31):

New output data values concerning to action i provided

Note:

Read as zero, should be written as zero.

1. Valid for devices 1-3: Read as zero, should be written as zero.

2. Valid for device 4: These bits can only be written for test purposes when the DPLL is disabled.

16.11.8 DPLL_OSW (offset and switch old/new address register)

Address offset: see Appendix B Initial value: 0x0000_0200

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 220. DPLL_OSW field description

Description

SWON_S : Switch of new STATE; Switch bit for LSB address of STATE.

This bit is changed for each write access to TS_S/TS_S_OLD. Using this unchanged address bit SWON_S for any access to TS_S results always in an access to TS_S_OLD. For writing to this address the former old (TS_S_OLD_old) value is overwritten by the new one while the

SWON_S bit changes. Thus the former new one is now the old one and the next access is after changing SWON_S directed to this place. Therefore write to TS_S first and after that immediately to FTV_S and PSSM, always before a new TS_S value is to be written.

Note:

After writing TS_S, FTV_S and PSSM in this order the address pointer AP with

LSB(AP)=SWON_S shows for the corresponding address to TS_S_OLD, FTV_S and

PSSM while LSB(AP)=/SWON_S results in an access to TS_S, FTV_S_old and

PSSM_OLD respectively. The value can be read only. This bit is reset when disabling the DPLL (DEN=0).

SWON_T : Switch of new TRIGGER; Switch bit for LSB address of TRIGGER.

This bit is changed for each write access to TS_T/TS_T_OLD. Using this unchanged address bit SWON_T for any access to TS_T results always in an access to TS_T_OLD. For writing to this address the former old (TS_T_OLD_old) value is overwritten by the new one while the

SWON_T bit changes. Thus the former new one is now the old one and the next access is after changing SWON_T directed to this place. Therefore write to TS_T first and after that immediately to FTV_T and PSTM, always before a new TS_T value is to be written.

Note:

After writing TS_T, FTV_T and PSTM in this order the address pointer AP with

LSB(AP)=SWON_T shows for the corresponding address to TS_T_OLD, FTV_T and

PSTM while LSB(AP)=/SWON_T results in an access to TS_T, FTV_T_old and

PSTM_OLD respectively. The value can be read only. This bit is reset when disabling the DPLL (DEN=0).

Reserved

Note: Read as zero, should be written as zero.

OSS

: Offset size of RAM region 2

0x0: Offset size 128 of RAM region 2.

0x1: Offset size 256 of RAM region 2.

0x2: Offset size 512of RAM region 2.

0x3: Offset size 1024 of RAM region 2.

Note:

At least 128 and at most 1024 values can be stored in each of the RAM 2 regions a to d accordingly. The value can be set only for DEN=0. The change of the OSS value results in an automatic change of the offset values in the DPLL_AOSV_2 register.

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

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16.11.9 DPLL_AOSV_2 (Address offset register of RAM 2 regions)

Address offset: see Appendix B Initial value: 0x1810_0800

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:31]

[16:23]

[8:15]

[0:7]

Table 221. DPLL_AOSV_2 field description

Description

AOSV_2a

: Address offset value of the RAM 2a region.

The value in this field is to be multiplied by 256 (shift left 8 Bits) and added with the start address of the RAM in order to get the start address of RAM region 2a. When the APT value is added to this start address, the current RAM cell RDT_Tx is addressed.

AOSV_2b

: Address offset value of the RAM 2b region.

The value in this field is to be multiplied by 256 (shift left 8 Bits) and added with the start address of the RAM in order to get the start address of RAM region 2b. When the APT value is added to this start address, the current RAM cell TSF_Tx is addressed.

AOSV_2c : Address offset value of the RAM 2c region.

The value in this field is to be multiplied by 256 (shift left 8 Bits) and added with the start address of the RAM in order to get the start address of RAM region 2c. When the APT value is added to this start address, the current RAM cell ADT_Tx is addressed.

AOSV_2d

: Address offset value of the RAM 2d region.

The value in this field is to be multiplied by 256 (shift left 8 Bits) and added with the start address of the RAM in order to get the start address of RAM region 2d. When the APT value is added to this start address, the current RAM cell DT_Tx is addressed.

Note:

The offset values are needed to support a scalable RAM size of region 2 from 1,5 Kbytes to 12 Kbytes. The values above must be in correlation with the offset size defined in the

OSW register. All offset values are set automatically in accordance to the OSS value in the DPLL_OSW register. This value can be set only for DEN=0.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 222. DPLL_APT field description

Description

Reserved

Note:

Read as zero, should be written as zero.

WAPT : Write bit for address pointer APT, read as zero.

0= the APT is not writable

1= the APT is writable

APT

: Address pointer TRIGGER; Actual RAM pointer address value offset for DT_T[i] and

RDT_T[i] in FULL_SCALE for 2*(TNU+1-SYN_NT) TRIGGER events.

this pointer is used for the RAM region 2 subsections 2a and 2d. The pointer APT is incremented for each valid TRIGGER event (simultaneously with APT_2b, APT_2c) for

DIR1=0. For DIR1=1 the APT is decremented.

The APT offset value is added in the above shown bit position with the subsection Address offset of the corresponding RAM region

Note: The APT pointer value is directed to the RAM position, in which the data values are to be written, which corresponds to the last increment. The APT value is not to be changed, when the direction (shown by DIR1) changes, because it points always to a storage place after the considered increment. Changing of DIR1 takes place always after a valid

TRIGGER event and the resulting increment/decrement.

Note: This value can only be written when the WAPT bit is set.

Reserved

Note: Read as zero, should be written as zero.

WAPT_2b : Write bit for address pointer APT_2b, read as zero.

0= The APT_2b is not writable

1= The APT_2b is writable

APT_2b : Address pointer TRIGGER for RAM region 2b; Actual RAM pointer address value for TSF_T[i]

Actual RAM pointer address of TRIGGER events in FULL_SCALE for 2*(TNU+1) TRIGGER periods; this pointer is used for the RAM region 2b. The RAM pointer is initially set to zero.

For SYT=1: The pointer APT_2b is incremented by SYN_T_old for each valid TRIGGER event (simultaneously with APT and APT_2c) for DIR1=0 when a valid TRIGGER input appears. For DIR1=1 (backwards) the APT is decremented by SYN_T_old.

For SYT=0: APT_2b is incremented or decremented by 1.

In addition when the APT_2c value is written by the CPU - in order to synchronize the DPLL- with the next valid TRIGGER event the APT_2b_ext value is added/subtracted (while

APT_2b_status is one; see DPLL_APT_SYNC register at

Section 16.11.24

Note:

This value can only be written when the WAPT_2b bit is set

Reserved

Note:

Read as zero, should be written as zero.

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16.11.11 DPLL_APS (actual RAM pointer address for STATE)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[24:29]

[19:23]

Table 223. DPLL_APS field description

Description

Reserved

Note: Read as zero, should be written as zero.

WAPS

: Write bit for address pointer APS, read as zero.

0= the APS is not writable

1= the APS is writable

APS : Address pointer STATE; Actual RAM pointer address value for DT_S[i] and RDT_S[i]

Actual RAM pointer and synchronization position/value of STATE events in FULL_SCALE for up to 64 STATE events but limited to 2*(SNU+1-SYN_NS) in normal and emergency mode for

SYSF=0 or to 2*(SNU+1)-SYN_NS for SYSF=1 respectively; this pointer is used for the RAM region 1c1 and 1c4.

APS is incremented (decremented) by one for each valid STATE event and DIR2=0 DIR2=1).

The APS offset value is added in the above shown bit position with the subsection offset of the

RAM region.

Note:

The APS pointer value is directed to the RAM position, in which the data values are to be written, which correspond to the last increment. The APS value is not to be changed, when the direction (shown by DIR2) changes, because it points always to a storage place after the considered increment. Changing of DIR2 takes place always after a valid

STATE event and the resulting increment/decrement.

Note: This value can only be written when the WAPS bit is set.AM region.

Reserved

Note: Read as zero, should be written as zero.

WAPS_1c2 : Write bit for address pointer APS_1c2, read as zero.

0= the APS_1c2 is not writable

1= the APS_1c2 is writable

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Table 223. DPLL_APS field description (continued)

Description

APS_1c2 : Address pointer STATE for RAM region 1c2; Actual RAM pointer address value for

TSF_S[i].

Initial value: zero (0x00). Actual RAM pointer and synchronization position/value of STATE events in FULL_SCALE for up to 64 STATE events but limited to 2*(SNU+1) in normal and emergency mode; this pointer is used for the RAM region 1c2.

For SYS=1: APS_1c2 is incremented (decremented) by SYN_S_old for each valid STATE event and DIR2=0 (DIR2=1).

For SYS=0: APT_1c2 is incremented or decremented by 1 respectively.

The APS_1c2 offset value is added in the above shown bit position with the subsection offset of the RAM region.

In addition when the APS_1c3 value is written by the CPU - in order to synchronize the DPLL- with the next valid STATE event the APS_1c2_ext value is added/subtracted (while

APS_1c2_status is one; see DPLL_APT_SYNC register at Section 16.11.17

Note:

This value can only be written when the WAPS_1c2 bit is set

Reserved

Note:

Read as zero, should be written as zero.

16.11.12 DPLL_APT_2C (actual RAM pointer address for region 2c)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Digital PLL module (DPLL)

Table 224. DPLL_APT_2C field description

Description

Reserved

Note:

Read as zero, should be written as zero.

APT_2c : Address pointer TRIGGER for RAM region 2c; Actual RAM pointer address value for

ADT_T[i].

Actual RAM pointer address value of TRIGGER adapt events in FULL_SCALE for 2*(TNU+1-

SYN_NT) TRIGGER periods depending on the size of the used RAM 2; this pointer is used for the RAM region 2 for the subsection 2c only. The RAM pointer is initially set to zero. The

APT_2c value is set by the CPU when the synchronization condition was detected. Within the

RAM region 2c initially the conditions for synchronization gaps and adapt values are stored by the CPU.

Reserved

Note:

Read as zero, should be written as zero.

Note: The APT_2c pointer values are directed to the RAM position of the profile element in

RAM region 2c, which correspond to the current increment. For DIR1=0 (DIR1=1) the pointers APT_2c_x are incremented (decremented) by one simultaneously with APT.

For SMC=0 the change of DIR1 takes place always after a valid TRIGGER event (by evaluation of the invalid slope) and the resulting increment/decrement. In the case

SMC=1 the direction change is known before the input event is processed.



The correction of the APT_2c pointer differs: for SMC=0 correct 4 times and for SMC=1 correct only 2 times.



The APT_2c_x offset value is added in the above shown bit position with the subsection

Address offset of the corresponding RAM region.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[24:29]

Table 225. DPLL_APS_1C3 field description

Description

Reserved

Note:

Read as zero, should be written as zero.

APS_1c3

: Address pointer STATE for RAM region 1c3; Actual RAM pointer address value for

ADT_S[i]

Initial value: zero (0x00). Actual RAM pointer and synchronization position/value of STATE events in FULL_SCALE for up to 64 STATE events but limited to 2*(SNU+1-SYN_NS) in normal and emergency mode for SYSF=0 or to 2*(SNU+1)-SYN_NS for SYSF=1 respectively; this pointer is used for the RAM region 1c3. The RAM pointer is set by the CPU accordingly, when the synchronization condition was detected.

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Table 225. DPLL_APS_1C3 field description (continued)

Description

Reserved

Note:

Read as zero, should be written as zero.

Note: The APS_1c3 pointer value is directed to the RAM position of the profile element in RAM region 1c2, which corresponds to the current increment. When changing the direction

DIR1 or DIR2 respectively, this is always known before a valid STATE event is processed. This is because of the pattern recognition in SPE (for PMSM) or because of the direction change recognition by TRIGGER. This direction change results in an automatic increment (forwards) or decrement (backwards) when the input event occurs in addition with a 2 times correction.



The APS_1c3_x offset value is added in the above shown bit position with the subsection Address offset of the corresponding RAM region.

16.11.14 DPLL_NUTC (number of recent TRIGGER events used for calculations)

Address offset: see Appendix B Initial value: 0x0001_2001

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[22:31]

[19:20]

[16:18]

Table 226. DPLL_NUTC field description

Description

NUTE : Number of recent TRIGGER events used for SUB_INC1 and action calculations modulo 2*(TNUmax+1).

NUTE: number of last nominal increments to be considered for the calculations.

No gap is considered in that case for this value, but in the VTN value (see below):

This register is set by the CPU, but reset automatically to “1” by a change of direction or lost of

LOCK. Each other value can be set by the CPU, maybe Full_SCALE, HALF_SCALE or parts of them. The relation values QDT_Tx are calculated using NUTE values in the past with its maximum value of 2*(TNU +1). The value zero does mean 211 values in the past.

Note: This value can only be written when the WNUT bit is set.

FST : FULL_SCALE of TRIGGER; this value is to be set, when NUTE is set to FULL_SCALE

0= the NUTE value is less then FULL_SCALE

1= the NUTE value is equal to FULL_SCALE

Note:

This value can only be written when the WNUT bit is set.

Reserved

Note:

Read as zero, should be written as zero.

SYN_T : number of real and virtual events to be considered for the current increment.

This value reflects the NT value of the last valid increment, stored in ADT_T[i]; to be updated

after all calculations in step 17 of Table 207.

Note:

This value can only be written when the WSYN bit in this register is set.

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Table 226. DPLL_NUTC field description (continued)

Description

SYN_T_old : number of real and virtual events to be considered for the last increment.

This value reflects the NT value of the last but one valid increment, stored in ADT_T[i]; is updated automatically when writing SYN_T

Note:

This value is updated by the SYN_T value when the WSYN bit in this register is set.

VTN : Virtual TRIGGER number; number of virtual increments in the current NUTE region

This value reflects the number of virtual increments in the current NUTE region; for NUTE=1 this value is zero, when the CPU sets NUTE to a value > 1, it must also set VTN to the correspondent value; for NUTE is set to FULL_SCALE including NUTE = zero (211 modulo

211) the VTN is to be set to 2* SYN_NT.

The VTN value is subtracted from the NUTE value in order to get the corresponding APT value for the past; the VTN value is not used for the APT_2b pointer.

VTN is to be updated by the CPU when a new gap is to be considered for NUTE or a gap is leaving the NUTE region; for this purpose the TINT values in the profile can be used to generate an interrupt for the CPU at the corresponding positions; no further update of VTN is necessary when NUTE is set to FULL_SCALE

Note: This value can only be written when the WVTN bit is set.

Reserved

Note: Read as zero, should be written as zero.

WNUT : write control bit for NUTE; read as zero.

0= the NUTE value is not writable

1= the NUTE value is writable

WSYN : write control bit for SYN_T and SYN_T_old; read as zero.

0= the SYN_T value is not writable

1= the SYN_T value is writable

WVTN : write control bit for VTN; read as zero.

0= the VTN value is not writable

1= the VTN value is writable

Address offset: see Appendix B Initial value: 0x0000_2081

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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RM0361

Table 227. DPLL_NUSC field description

Description

NUSE : Number of recent STATE events used for SUB_INCx calculations modulo

2*(SNUmax+1).

No gap is considered in that case for this value, but in the VSN value (see below):

This register is set by the CPU but reset automatically to “1” by a change of direction or lost of

LOCK. Each other value can be set by the CPU, maybe Full_SCALE, HALF_SCALE or parts of them. The relation values QDT_Sx are calculated using NUSE values in the past with its maximum value of 2*SNU+1.

Note:

This value can only be written when the WNUS bit is set.

FSS : FULL_SCALE of STATE; this value is to be set, when NUSE is set to FULL_SCALE

0= the NUSE value is less then FULL_SCALE

1= the NUSE value is equal to FULL_SCALE

Note:

This value can only be written when the WNUS bit is set.

SYN_S : number of real and virtual events to be considered for the current increment.

This value reflects the NS value of the last valid increment, stored in ADT_S[i]; to be updated

after all calculations in step 37 of Table 207.

Note: This value can only be written when the WSYN bit in this register is set.

SYN_S_old : number of real and virtual events to be considered for the last increment.

This value reflects the NS value of the last but one valid increment, stored in ADT_S[i]; is updated automatically when writing SYN_S

Note: This value is updated by the SYN_S value when the WSYN bit in this register is set.

VSN : virtual STATE number; number of virtual state increments in the current NUSE region.

This value reflects the number of virtual increments in the current NUSE region; for NUSE=1 this value is zero, when the CPU sets NUSE to a value > 1 or zero(27 modulo 27), it must also set VSN to the correspondent value; the VSN value is subtracted from the NUSE value in order to get the corresponding APS value for the past; the VSN value is not used for the APS_1c2 pointer.

VSN is to be updated by the CPU when a new gap is to be considered for NUSE or a gap is leaving the NUSE region; for this purpose the SASI interrupt can be used; no further update of

VSN is necessary when NUSE is set to FULL_SCALE

Note:

This value can only be written when the WVSN bit is set.

Reserved

Note:

Read as zero, should be written as zero.

WNUS

: write control bit for NUSE; read as zero.

0= the NUSE value is not writable

1= the NUSE value is writable

WSYN

: write control bit for SYN_S and SYN_S_old; read as zero.

0= the SYN_S value is not writable

1= the SYN_S value is writable

WVSN

: write control bit for VSN; read as zero.

0= the VSN value is not writable

1= the VSN value is writable

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16.11.16 DPLL_NTI_CNT (number of active TRIGGER events to interrupt)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[22:31]

[0:21]

Table 228. DPLL_NTI_CNT field description

Description

NTI_CNT : Number of TRIGGERs to interrupt; Number of active TRIGGER events to the next

DPLL_CDTI interrupt.

This value shows the remaining TRIGGER events until an active TRIGGER slope results in a

DPLL_CDTI interrupt; the value is to be count down for each valid TRIGGER event.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 229. DPLL_IRQ_NOTIFY field description

Description

PDI : DPLL disable interrupt; announces the switch off of the DEN bit.

0 =The DPLL disable interrupt is not requested

1 =The DPLL disable interrupt is requested

Note:

This event is combined with the PEI interrupt to the common PDI + PEI interrupt line number 1.

PEI

: DPLL enable interrupt; announces the switch on of the DEN bit.

0 =The DPLL disable interrupt is not requested

1 =The DPLL disable interrupt is requested

Note: This event is combined with the PDI interrupt to the common PDI + PEI interrupt line number 1.

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Table 229. DPLL_IRQ_NOTIFY field description (continued)

Description

TINI : TRIGGER minimum hold time violation interrupt (dt <= THMI > 0).

0 =No violation of minimum hold time of TRIGGER is detected

1 =A violation of minimum hold time of TRIGGER is detected

TAXI

: TRIGGER maximum hold time violation interrupt (dt > THMA > 0).

0 =No violation of maximum hold time of TRIGGER is detected

1 =A violation of maximum hold time of TRIGGER is detected

SISI : STATE inactive slope interrupt.

0 =No inactive slope of STATE is detected

1 =An inactive slope of STATE is detected

TISI

: TRIGGER inactive slope interrupt.

0 =No inactive slope of TRIGGER is detected

1 =An inactive slope of TRIGGER is detected

MSI : Missing STATE interrupt.

0 =The missing STATE interrupt is not requested

1 =The missing STATE interrupt is requested

MTI

: Missing TRIGGER interrupt.

0 =The missing TRIGGER interrupt is not requested

1 =The missing TRIGGER interrupt is requested

SASI

: STATE active slope interrupt.

0 =No active slope of STATE is detected

1 =An active slope of STATE is detected

TASI

: TRIGGER active slope interrupt.

0 =No active slope of TRIGGER is detected

1 =An active slope of TRIGGER is detected

PWI : Plausibility window (PVT) violation interrupt of TRIGGER.

0 =The plausibility window is not violated

1 =The plausibility window is violated

W2I : RAM write access to RAM region 2 interrupt.

0 =The RAM write access interrupt is not requested

1 =The RAM write access interrupt is requested

W1I : Write access to RAM region 1b or 1c interrupt.

0 =The RAM write access interrupt is not requested

1 =The RAM write access interrupt is requested

GL1I

: Get of lock interrupt, for SUB_INC1.

0 =The lock getting interrupt is not requested

1 =The lock getting interrupt is requested

LL1I

: Lost of lock interrupt for SUB_INC1.

0 =The lock lose interrupt is not requested

1 =The lock lose interrupt is requested

RM0361

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Table 229. DPLL_IRQ_NOTIFY field description (continued)

Description

EI : Error interrupt (see status register bit 0).

0 =The error interrupt is not requested

1 =The error interrupt is requested

GL2I

: Get of lock interrupt, for SUB_INC2.

0 =The lock getting interrupt is not requested

1 =The lock getting interrupt is requested

LL2I : Lost of lock interrupt for SUB_INC2.

0 =The lock lose interrupt is not requested

1 =The lock lose interrupt is requested

TE0I

: TRIGGER event interrupt 0.

0 =No Interrupt on TRIGGER event 0 requested

1 =Interrupt on TRIGGER event 0 requested

TE1I : TRIGGER event interrupt 1.

0 =No Interrupt on TRIGGER event 1 requested

1 =Interrupt on TRIGGER event 1 requested

TE2I

: TRIGGER event interrupt 2.

0 =No Interrupt on TRIGGER event 2 requested

1 =Interrupt on TRIGGER event 2 requested

TE3I

: TRIGGER event interrupt 3.

0 =No Interrupt on TRIGGER event 3 requested

1 =Interrupt on TRIGGER event 3 requested

TE4I

: TRIGGER event interrupt 4.

0 =No Interrupt on TRIGGER event 4 requested

1 =Interrupt on TRIGGER event 4 requested

CDTI : Calculation of TRIGGER duration done, only while NTI_CNT is zero.

0 =No Interrupt on calculated TRIGGER duration requested or NTI_CNT is not zero

1 =Interrupt on calculated TRIGGER duration requested while NTI_CNT is zero

CDSI : Calculation of STATE duration done

0 =No Interrupt on calculated STATE duration requested

1 =Interrupt on calculated STATE duration requested

TORI : TRIGGER out of range interrupt

0 =TRIGGER is not out of range

1 =TRIGGER is out of range, the TOR bit in the DPLL_STATUS register is set to 1

SORI

: STATE out of range

0 =STATE is not out of range

1 =STATE is out of range, the SOR bit in the DPLL_STATUS register is set to 1

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Table 229. DPLL_IRQ_NOTIFY field description (continued)

Description

DCGI : Direction change interrupt

0 =No direction change of TRIGGER is detected

1 =Direction change of TRIGGER is detected

Note:

The interrupt occurs at line number 0.

Reserved

Note:

Read as zero, should be written as zero.

RM0361

16.11.18 DPLL_IRQ_EN (DPLL Interrupt enable register DPLL_IRQ_EN)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 230. DPLL_IRQ_EN field description

Description

PDI_IRQ_EN

: DPLL disable interrupt enable, when switch off of the DEN bit.

0 =The DPLL disable interrupt is not enabled

1 =The DPLL disable interrupt is enabled

PEI_IRQ_EN : DPLL enable interrupt enable, when switch on of the DEN bit.

0 =The DPLL enable interrupt is not enabled

1 =The DPLL enable interrupt is enabled

TINI_IRQ_EN : TRIGGER minimum hold time violation interrupt enable bit.

0 =Minimum hold time violation of TRIGGER interrupt is not enabled

1 =The minimum hold time violation of TRIGGER interrupt is enabled

TAXI_IRQ_EN : TRIGGER maximum hold time violation interrupt enable bit.

0 =Maximum hold time violation of TRIGGER interrupt is not enabled

1 =The maximum hold time violation of TRIGGER interrupt is enabled

SISI_IRQ_EN

: STATE inactive slope interrupt enable bit.

0 =The interrupt at the inactive slope of STATE is not enabled

1 =The interrupt at the inactive slope of STATE is enabled

TISI_IRQ_EN

: TRIGGER inactive slope interrupt enable bit.

0 =The interrupt at the inactive slope of TRIGGER is not enabled

1 =The interrupt at the inactive slope of TRIGGER is enabled

MSI_IRQ_EN : Missing STATE interrupt enable.

0 =The missing STATE interrupt is not enabled

1 =The missing STATE interrupt is enabled

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Table 230. DPLL_IRQ_EN field description (continued)

Description

MTI_IRQ_EN : Missing TRIGGER interrupt enable.

0 =The missing TRIGGER interrupt is not enabled

1 =The missing TRIGGER interrupt is enabled

SASI_IRQ_EN

: STATE active slope interrupt enable.

0 =The active slope STATE interrupt is not enabled.

1 =The active slope STATE interrupt is enabled

TASI_IRQ_EN : TRIGGER active slope interrupt enable.

0 =The active slope TRIGGER interrupt is not enabled

1 =The active slope TRIGGER interrupt is enabled

PWI_IRQ_EN

: Plausibility window (PVT) violation interrupt of TRIGGER enable.

0 =The plausibility violation interrupt is not enabled

1 =The plausibility violation interrupt is enabled

W2I_IRQ_EN : RAM write access to RAM region 2 interrupt enable.

0 =The RAM write access interrupt is not enabled

1 =The RAM write access interrupt is enabled

W1I_IRQ_EN

: Write access to RAM region 1b or 1c interrupt.

0 =The RAM write access interrupt is not enabled

1 =The RAM write access interrupt is enabled.

GL1I_IRQ_EN

: Get of lock interrupt enable, when lock arises.

0 =The lock getting interrupt is not enabled

1 =The lock getting interrupt is enabled

LL1I_IRQ_EN

: Lost of lock interrupt enable.

0 =The lock lose interrupt is not enabled

1 =The lock lose interrupt is enabled

EI_IRQ_EN : Error interrupt enable (see status register).

0 =The error interrupt is not enabled

1 =The error interrupt is enabled

GL2I_IRQ_EN : Get of lock interrupt enable for SUB_INC2.

0 =The lock getting interrupt is not requested

1 =The lock getting interrupt is requested

LL2I_IRQ_EN : Lost of lock interrupt enable for SUB_INC2.

0 =The lock lose interrupt is not requested

1 =The lock lose interrupt is requested

TE0I_IRQ_EN

: TRIGGER event interrupt 0 enable.

0 =No Interrupt on TRIGGER event 0 enabled

1 =Interrupt on TRIGGER event 0 enabled

TE1I_IRQ_EN

: TRIGGER event interrupt 1 enable.

0 =No Interrupt on TRIGGER event 1 enabled

1 =Interrupt on TRIGGER event 1 enabled

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Table 230. DPLL_IRQ_EN field description (continued)

Description

TE2I_IRQ_EN : TRIGGER event interrupt 2 enable.

0 =No Interrupt on TRIGGER event 2 enabled

1 =Interrupt on TRIGGER event 2 enabled

TE3I_IRQ_EN

: TRIGGER event interrupt 3 enable.

0 =No Interrupt on TRIGGER event 3 enabled

1 =Interrupt on TRIGGER event 3 enabled

TE4I_IRQ_EN : TRIGGER event interrupt 4 enable.

0 =No Interrupt on TRIGGER event 4 enabled

1 =Interrupt on TRIGGER event 4 enabled

CDTI_IRQ_EN

: Enable interrupt when calculation of TRIGGER duration done

0 =No Interrupt on calculated TRIGGER duration enabled

1 =Interrupt on calculated TRIGGER duration enabled

CDSI_IRQ_EN : Enable interrupt when calculation of TRIGGER duration done

0 =No Interrupt on calculated STATE duration enabled

1 =Interrupt on calculated STATE duration enabled

TORI

: TRIGGER out of range interrupt

0 =No Interrupt when TRIGGER is out of range enabled

1 =Interrupt when TRIGGER is out of range enabled

SORI

: STATE out of range

0 =No Interrupt when STATE is out of range enabled

1 =Interrupt when STATE is out of range enabled

DCGI

: Direction change interrupt

0 =No Interrupt when a direction change of TRIGGER is detected

1 =Interrupt when a direction change of TRIGGER is detected

Reserved

Note: Read as zero, should be written as zero.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 231. DPLL_IRQ_FORCINT field description

Description

TRG_PDI : Force Interrupt PDI

0= the corresponding interrupt is not forced

1= the corresponding interrupt is forced for one clock

Note:

This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_PEI

: Force Interrupt PEI see bit 31

TRG_TINI

: Force Interrupt TINI see bit 31

TRG_TAXI

: Force Interrupt TAXI see bit 31

TRG_SISI

: Force Interrupt SISI see bit 31

TRG_TISI

: Force Interrupt TISI see bit 31

TRG_MSI

: Force Interrupt MSI see bit 31

TRG_MTI

: Force Interrupt MTI see bit 31

TRG_SASI

: Force Interrupt SASI see bit 31

TRG_TASI

: Force Interrupt TASI see bit 31

TRG_PWI

: Force Interrupt PWI see bit 31

TRG_W2I

: Force Interrupt W2IF see bit 31

TRG_W1I

: Force Interrupt W1I see bit 31

TRG_GL1I

: Force Interrupt GL1I see bit 31

TRG_LL1I

: Force Interrupt LL1I see bit 31

TRG_EI

: Force Interrupt EI see bit 31

TRG_GL2I

: Force Interrupt GL2I see bit 31

TRG_LL2I

: Force Interrupt LL2I see bit 31

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Table 231. DPLL_IRQ_FORCINT field description (continued)

Description

TRG_TE0I : Force Interrupt TE0I see bit 31

TRG_TE1I : Force Interrupt TE1I see bit 31

TRG_TE2I : Force Interrupt TE2I see bit 31

TRG_TE3I : Force Interrupt TE3I see bit 31

TRG_TE4I : Force Interrupt TE4I see bit 31

TRG_CDTI : Force Interrupt CDTI see bit 31

TRG_CDSI

: Force Interrupt CDSI see bit 31

TRG_TORI

: Force Interrupt TORI see bit 31

TRG_SORI

: Force Interrupt SORI see bit 31

TRG_DCGI

: Force interrupt DCGI see bit 31

Reserved

Note:

Read as zero, should be written as zero.

RM0361

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16.11.20 DPLL_IRQ_MODE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[0:29]

Table 232. DPLL_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5

Reserved

Note:

Read as zero, should be written as zero.

16.11.21 DPLL_EIRQ_EN (DPLL Error interrupt enable register)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 233. DPLL_EIRQ_EN field description

Description

PDI_EIRQ_EN : DPLL disable interrupt enable, when switch off of the DEN bit.

0 =The DPLL disable interrupt is not enabled

1 =The DPLL disable interrupt is enabled

PEI_EIRQ_EN : DPLL enable interrupt enable, when switch on of the DEN bit.

0 =The DPLL enable interrupt is not enabled

1 =The DPLL enable interrupt is enabled

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Table 233. DPLL_EIRQ_EN field description (continued)

Description

TINI_EIRQ_EN : TRIGGER minimum hold time violation interrupt enable bit.

0 =Minimum hold time violation of TRIGGER interrupt is not enabled

1 =The minimum hold time violation of TRIGGER interrupt is enabled

TAXI_EIRQ_EN

: TRIGGER maximum hold time violation interrupt enable bit.

0 =Maximum hold time violation of TRIGGER interrupt is not enabled

1 =The maximum hold time violation of TRIGGER interrupt is enabled

SISI_EIRQ_EN : STATE inactive slope interrupt enable bit.

0 =The interrupt at the inactive slope of STATE is not enabled

1 =The interrupt at the inactive slope of STATE is enabled

TISI_EIRQ_EN

: TRIGGER inactive slope interrupt enable bit.

0 =The interrupt at the inactive slope of TRIGGER is not enabled

1 =The interrupt at the inactive slope of TRIGGER is enabled

MSI_EIRQ_EN : Missing STATE interrupt enable.

0 =The missing STATE interrupt is not enabled

1 =The missing STATE interrupt is enabled

MTI_EIRQ_EN

: Missing TRIGGER interrupt enable.

0 =The missing TRIGGER interrupt is not enabled

1 =The missing TRIGGER interrupt is enabled

SASI_EIRQ_EN

: STATE active slope interrupt enable.

0 =The active slope STATE interrupt is not enabled.

1 =The active slope STATE interrupt is enabled

TASI_EIRQ_EN

: TRIGGER active slope interrupt enable.

0 =The active slope TRIGGER interrupt is not enabled

1 =The active slope TRIGGER interrupt is enabled

PWI_EIRQ_EN : Plausibility window (PVT) violation interrupt of TRIGGER enable.

0 =The plausibility violation interrupt is not enabled

1 =The plausibility violation interrupt is enabled

W2I_EIRQ_EN : RAM write access to RAM region 2 interrupt enable.

0 =The RAM write access interrupt is not enabled

1 =The RAM write access interrupt is enabled

W1I_EIRQ_EN : Write access to RAM region 1b or 1c interrupt.

0 =The RAM write access interrupt is not enabled

1 =The RAM write access interrupt is enabled.

GL1I_EIRQ_EN

: Get of lock interrupt enable, when lock arises.

0 =The lock getting interrupt is not enabled

1 =The lock getting interrupt is enabled

LL1I_EIRQ_EN

: Lost of lock interrupt enable.

0 =The lock lose interrupt is not enabled

1 =The lock lose interrupt is enabled

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Table 233. DPLL_EIRQ_EN field description (continued)

Description

EI_EIRQ_EN : Error interrupt enable (see status register).

0 =The error interrupt is not enabled

1 =The error interrupt is enabled

GL2I_EIRQ_EN

: Get of lock interrupt enable for SUB_INC2.

0 =The lock getting interrupt is not requested

1 =The lock getting interrupt is requested

LL2I_EIRQ_EN : Lost of lock interrupt enable for SUB_INC2.

0 =The lock lose interrupt is not requested

1 =The lock lose interrupt is requested

TE0I_EIRQ_EN

: TRIGGER event interrupt 0 enable.

0 =No Interrupt on TRIGGER event 0 enabled

1 =Interrupt on TRIGGER event 0 enabled

TE1I_EIRQ_EN : TRIGGER event interrupt 1 enable.

0 =No Interrupt on TRIGGER event 1 enabled

1 =Interrupt on TRIGGER event 1 enabled

TE2I_EIRQ_EN

: TRIGGER event interrupt 2 enable.

0 =No Interrupt on TRIGGER event 2 enabled

1 =Interrupt on TRIGGER event 2 enabled

TE3I_EIRQ_EN

: TRIGGER event interrupt 3 enable.

0 =No Interrupt on TRIGGER event 3 enabled

1 =Interrupt on TRIGGER event 3 enabled

TE4I_EIRQ_EN

: TRIGGER event interrupt 4 enable.

0 =No Interrupt on TRIGGER event 4 enabled

1 =Interrupt on TRIGGER event 4 enabled

CDTI_EIRQ_EN : Enable interrupt when calculation of TRIGGER duration done

0 =No Interrupt on calculated TRIGGER duration enabled

1 =Interrupt on calculated TRIGGER duration enabled

CDSI_EIRQ_EN : Enable interrupt when calculation of TRIGGER duration done

0 =No Interrupt on calculated STATE duration enabled

1 =Interrupt on calculated STATE duration enabled

TORI : TRIGGER out of range interrupt

0 =No Interrupt when TRIGGER is out of range enabled

1 =Interrupt when TRIGGER is out of range enabled

SORI

: STATE out of range

0 =No Interrupt when STATE is out of range enabled

1 =Interrupt when STATE is out of range enabled

DCGI

: Direction change interrupt

0 =No Interrupt when a direction change of TRIGGER is detected

1 =Interrupt when a direction change of TRIGGER is detected

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[8:31]

[0:7]

Table 234. DPLL_INC_CNT1 field description

Description

INC_CNT1 : Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode;

Automatic addition of the number of demanded pulses

MLT/MLS1 when getting a valid TRIGGER/STATE input in normal or emergency mode respectively when SGE1=1; writable only for test purposes when DEN=0

In the case of a change of the direction the wrong number of pulses are corrected twice:

Add the difference between NMB_T and INC_CNT1 twice to INC_CNT1 before sending out the correction pulses.

Note: This value can only be written when the DPLL is disabled.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[8:31]

[0:7]

Table 235. DPLL_INC_CNT2 field description

Description

INC_CNT2 : Actual number of pulses to be still sent out at the current increment until the next valid input signal in automatic end mode;

Automatic addition of the number of demanded pulses MLS2 when getting a valid

TRIGGER/STATE input in normal or emergency mode respectively when SGE2=1; writable only for test purposes when DEN=0

In the case of a change of the direction the wrong number of pulses are corrected twice:

Add the difference between NMB_S and INC_CNT2 twice to INC_CNT2 before sending out the correction pulses.

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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[8:17]

[0:7]

RM0361

Table 236. DPLL_APT_SYNC field description

Description

APT_2b_ext : Address pointer 2b extension; this offset value determines, by which value the

APT_2b is changed at the synchronization time; set by CPU before the synchronization is performed.

This offset value is the number of virtual increments to be inserted in the TSF for an imminent intended synchronization; the CPU sets its value depending on the gaps until the synchronization time taking into account the considered NUTE value to be set and including the next future increment (when SYN_T_old is still 1). When the synchronization takes place, this value is to be added to the APT_2b address pointer (for forward direction, DIR1=0) and the APT_2b_status bit is cleared after it. For backward direction subtract APT_2b_ext accordingly. This correction is done after updating the RAM TSF with the last TS_T value.

Note: When the synchronization is intended and the NUTE value is to be set to FULL_SCALE after it, the APT_2b_ext value must be set to 2*SYN_NT in order to be able to fill all gaps in the extended TSF_T with the corresponding values by the CPU.When still not all values for FULL_SCALE are available, the APT_2b_ext value considers only a share according to the corresponding NUTE value to be set after the synchronization.

APT_2b_status : Address pointer 2b status; set by CPU before the synchronization is performed. The value is cleared when the APT_2b_old value is written.

0 = APT_2b_ext is not to be considered.

1 = APT_2b_ext has to be considered for time stamp field extension.

Reserved

Note: Read as zero, should be written as zero.

APT_2b_old : Address pointer TRIGGER for RAM region 2b at synchronization time; this value is set by the current APT_2b value when the synchronization takes place for the first valid TRIGGER event after writing APT_2c but before adding the offset value APT_2b_ext

(that means: when APT_2b_status=1).

Address pointer APT_2b value at the moment of synchronization, before the offset value is added, that means the pointer with this value points to the last value before the additional inserted gap

Reserved

Note:

Read as zero, should be written as zero.

16.11.25 DPLL_APS_SYNC (TSF offset at synchronization time)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Bit

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[18:24]

[12:17]

[0:11]

Table 237. DPLL_APS_SYNC field description

Description

APS_1c2_ext : Address pointer 1c2 extension; this offset value determines, by which value the APS_1c2 is changed at the synchronization time; set by CPU before the synchronization is performed.

This offset value is the number of virtual increments to be inserted in the TSF for an imminent intended synchronization; the CPU sets its value depending on the gaps until the synchronization time taking into account the considered NUSE value to be set and including the next future increment (when SYN_S_old is still 1). When the synchronization takes place, this value is to be added to the APS_1c2 address pointer (for forward direction, DIR2=0) and the APT_1c2_status bit is cleared after it. For backward direction subtract APS_1c2_ext accordingly.

Note: When the synchronization is intended and the NUSE value is to be set to FULL_SCALE after it, the APS_1c2_ext value must be set to SYN_NS (for SYSF=1) or 2*SYN_NS (for

SYSF=0) in order to be able to fill all gaps in the extended TSF_S with the corresponding values by the CPU.



When still not all values for FULL_SCALE are available, the APS_1c2_ext value considers only a share according to the NUSE value to be set after the synchronization.

APS_1c2_status : Address pointer 1c2 status; set by CPU before the synchronization is performed. The value is cleared automatically when the APS_1c2_old value is written.

0 = APS_1c2_ext is not to be considered.

1 = APS_1c2_ext has to be considered for time stamp field extension.

Reserved

Note: Read as zero, should be written as zero.

APS_1c2_old

: Address pointer STATE for RAM region 1c2 at synchronization time; this value is set by the current APS_1c2 value when the synchronization takes place for the first valid

STATE event after writing APS_1c3 but before adding the offset value APS_1c2_ext (that means: when APS_1c2_status=1).

Address pointer APS_1c2 value at the moment of synchronization, before the offset value is added, that means the pointer with this value points to the last value before the additional inserted gap

Reserved

Note: Read as zero, should be written as zero.

16.11.26 TBU_TS0_T

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

TBU_TS0_T

RPw

0x000000

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[0:7]

Table 238. TBU_TSO_T field description

Description

TBU_TS0_T : value of TBU_TS0 at the last TRIGGER event; for each T_VALID the value of TBU_TS0 is stored in this register; the register is writable only for test purposes when DEN=0.

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

RM0361

16.11.27 TBU_TS0_S

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TBU_TS0_S Bit

Mode

Initial value

0x00

RPw

0x000000

Bit

[8:31]

[0:7]

Table 239. TBU_TSO_S field description

Description

TBU_TS0_S

: value of TBU_TS0 at the last STATE event; for each S_VALID the value of TBU_TS0 is stored in this register; the register is writable only for test purposes when DEN=0.

Note: This value can only be written when the DPLL is disabled.

Reserved

Note: Read as zero, should be written as zero.

16.11.28 ADD_IN_LD1

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ADD_IN_LD1 Bit

Mode

Initial value

0x00

0x000000

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Table 240. ADD_IN_LD1 field description

Description

ADD_IN_LD_1 : Input value for SUB_INC1 generation, given by CPU. This value can be used in normal and emergency mode (SMC=0) as well as for SMC=1.

Note: The value is loaded by the CPU but used by the DPLL only for DLM1=1 (see

DPLL_CTRL_1 register). When switching DLM1 to 1, the value in the register is used for the SUB_INC1 generation beginning from the next valid TRIGGER or STATE event respectively independently if new values are written by the CPU or not.

Note: When a new value is written the output frequency changes according to the given value beginning immediately from the moment of writing. Do not wait for performing step 10 in the state machine for ADD_IN calculations.

Note:

If the ADD_IN_LD1 value is zero all pulses are sent with the highest possible frequency.

Reserved

Note:

Read as zero, should be written as zero.

16.11.29 ADD_IN_LD2

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ADD_IN_LD2 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 241. ADD_IN_LD2 field description

Description

ADD_IN_LD_2

: Input value for SUB_INC2 generation, given by CPU. This value can be used for SMC=1 while RMO=1.

Note:

The value is loaded by the CPU but used by the DPLL only for DLM2=1 (see

DPLL_CTRL_1 register). When switching DLM2 to 1, the value in the register is used for the SUB_INC2 generation beginning from the next valid STATE event independently if new values are written by the CPU or not.

Note: When a new value is written the output frequency changes according to the given value beginning immediately from the moment of writing. Do not wait for performing step 30 in the state machine for ADD_IN calculations.

Note: If the ADD_IN_LD2 value is zero all pulses are sent with the highest possible frequency.

Reserved

Note: Read as zero, should be written as zero.

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16.11.30 DPLL_STATUS

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 242. DPLL_STATUS field description

Description

Reserved

Note:

Read as zero, should be written as zero.

CSO

: Calculated STATE duration overflow; Bit is set when

an overflow

Reserved

Note:

Read as zero, should be written as zero.

CTO

: Calculated TRIGGER duration overflow; Bit is set when

Equation 10

Equation 11

lead to an overflow

0 =No overflow at equation

Equation 10

Equation 11

1 =overflow at equation

Equation 10

Equation 11

Note: When one of the above bits is set the corresponding register contains the maximum value 0xFFFFFF.

CRO

: Calculated Reciprocal value overflow; Bit is set when the calculation of RDT_T_actual or RDT_S_actual leads to an overflow

0 =No overflow at any reciprocal calculation

1 =overflow for at least one reciprocal calculation

Note: An overflow in calculation of reciprocal values can occur, when the condition of Note 4

to the DPLL_CTRL_0 register is violated (see

16.11.1

). Such an overflow can occur

according to the calculations in

Equation 6

Equation 17



The overflow is detected when after the calculation and shifting left 32 bits at least one of the bits 31 to 24 is not zero. In that case the corresponding register is set to 0xFFFFFF.

RCS : Resolution conflict STATE.

0 =No resolution conflict detected

1 =the TS0_HRT value is set to 1 while LOW_RES=0

RCT : Resolution conflict TRIGGER.

0 =No resolution conflict detected

1 =the TS0_HRS value is set to 1 while LOW_RES=0

PSE

: Prediction space configuration error

0 =No prediction space error detected

1 =Configured offset value of RAM2 is too small in order to store all TNU+1 values twice in

FULL_SCALE

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Table 242. DPLL_STATUS field description (continued)

Description

SOR

(1) : STATE out of range

0 =all STATE signal events appear within SLR interval or a direction change was detected

1 =at least one STATE signal event is out of SLR

: Missing STATE detected.

0 =No missing STATE detected or a new valid STATE slope occurred

1 =At least one missing STATE detected after the last valid slope

TOR

(2) : TRIGGER out of range

0 =all TRIGGER signal events appear within TLR interval or a direction change was detected

1 =at least one TRIGGER signal event is out of TLR

: Missing TRIGGER detected.

0 =No missing TRIGGER detected or a new valid TRIGGER slope occurred

1 =At least one missing TRIGGER detected after the last valid slope

RAM2_ERR : DPLL internal access to not configured RAM2 memory space

0 = No access to not configured RAM2 memory space

1 = access to not configured RAM2 memory space

Reserved

Note:

Read as zero, should be written as zero.

LOW_RES

: low resolution of TBU_TS0 is used for DPLL input; this value reflects the input signal LOW_RES

0 =the lower 24 Bits of TBU_TS0 are used as input for the DPLL

1 =the higher 24 Bits of TBU_TS0 are used as input for the DPLL

CSVS

: Current signal value STATE

0 =the last STATE_S value was 0

1 =the last STATE_S value was 1

CSVT

: Current signal value TRIGGER

0 =the last TRIGGER_S value was 0

1 =the last TRIGGER_S value was 1

CAIP2

: Calculation of actions 12 to 23 in progress (2nd part)

0 =currently no action calculation, new data requests possible

1 =action calculation in progress, no new data requests possibl e

CAIP1 : Calculation of actions 0 to 11 in progress (1st part)

0 =currently no action calculation, new data requests possible

1 =action calculation in progress, no new data requests possible

ISN : Increment number of STATE is not plausible; Bit is set when the number of STATES is different to profile

0 =the number of STATE events between synchronization gaps is plausible, a direction change is detected or the APS_1c3 pointer is written

1 =after setting LOCK1 in emergency mode (SMC=0 and RMO=1) or LOCK2 for SMC=RMO=1 missing or additional STATE signals detected; bit is cleared when a direction change is detected or the APS_1c3 is written

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Table 242. DPLL_STATUS field description (continued)

Description

ITN : Increment number of TRIGGER is not plausible; Bit is set when the number of

TRIGGERS is different to profile

0 =the number of TRIGGER events between synchronization gaps is plausible, a direction change is detected or the address pointer APT_2c is written

1 =after setting LOCK1 in normal mode (for SMC=0 or SMC=1) or in emergency mode (only for SMC=0) for missing or additional TRIGGER signals detected; bit is cleared when a direction change is detected or the APT_2c is written

BWD2

: Backwards drive of SUB_INC2

0 =forward direction

1 =backward direction

BWD1 : Backwards drive of SUB_INC1

Note: see bit 9

Reserved

Note:

Read as zero, should be written as zero.

LOCK2 : DPLL Lock status concerning SUB_INC2

0 =The DPLL is not locked concerning STATE for SMC=1

1 =The DPLL is locked concerning STATE for SMC=1

Note:

Locking of SUB_INC2 appears  for RMO=SMC=1: Bit is set, when SYS is set and the number of events between two missing STATEs is as expected by the SYN_S values.

Note: LOCK2 is set  for SMC=RMO=1:  for a valid STATE event when SYS is set and SYN_NS=0  or when SYS is set and the profile stored in the ADS_Ti field matches once between two gaps.

LOCK2 is reset: for SMC=RMO=1

– when the number of corresponding events between two STATE gaps is unexpected,

– when an unexpected missing STATE event occurs

– when the corresponding input signal STATE is out of locking range SLR

SYS : Synchronization condition of STATE fixed.

This bit is set when the CPU writes to the APS_1c3 address pointer.

SYT : Synchronization condition of TRIGGER fixed.

This bit is set when the CPU writes to the APT_2c address pointer.

FSD : First STATE detected.

0 =Still no valid STATE event was detected after enabling DPLL

1 =At least one valid STATE event was detected after enabling DPLL

Note:

No change of FSD for switching from normal to emergency mode or vice versa.

FTD

: First TRIGGER detected.

0 =No valid TRIGGER event was detected after enabling DPLL

1 =At least one valid TRIGGER event was detected after enabling DPLL

Note: No change of FTD for switching from normal to emergency mode or vice versa.

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Bit

Table 242. DPLL_STATUS field description (continued)

Description

LOCK1 : DPLL Lock status concerning SUB_INC1

0 =The DPLL is not locked for TRIGGER

(while SMC=RMO=0 or SMC=1) or for STATE (while SMC=0 and RMO=1)

1 =The DPLL is locked for TRIGGER

(while SMC=RMO=0 or SMC=1) or for STATE (while SMC=0 and RMO=1)

Note:

LOCK1 is set:

- in normal mode (for RMO=SMC=0): Bit is set for a valid TRIGGER event when SYT is set and the number of events between two gaps is as expected by the profile (NT values in the

ADT_T[i] field) or when SYN_NT=0 and SYT=1.

- in emergency mode (for RMO=1 and SMC=0): Bit is set for a valid STATE event, when SYS is set and the received event are in correspondence to the profile (NS values in the ADT_S[i] field) for at least two expected missing STATE events or when SYN_NS=0.

- for SMC=1: Bit is set for a valid TRIGGER even when SYT is set and SYN_NT=0 or when

SYT is set and the profile stored in the ADT_T[i] field matches once between two gaps.

LOCK1 is reset: for RMO=0 (RMO=1) while SMC=0

or for SMC=1

- when the number of corresponding events between two TRIGGER(STATE) gaps is unexpected,

- when an unexpected corresponding missing TRIGGER(STATE) event occurs,

- when the corresponding input signal TRIGGER (STATE) is out of locking range TLR (SLR),

- when a corresponding direction change is detected

ERR : Error during configuration or operation resulting in unexpected values.

0 =when all bits in position 8 to 0 and 10 and 12 are zero

1 =when at least one bit in position 8 to 0 or 10 or 12 is one

1. The SOR bit is set, when the time to the next active STATE slope exceeds the value of the last nominal STATE duration multiplied with the value of the SLR register (see chapter ) and is reset, when at the current or last valid input event a direction change was detected. The SYS bit is not influenced by setting the SOR bit.

2. The TOR bit is set, when the time to the next active TRIGGER slope exceeds the value of the last nominal TRIGGER duration multiplied with the value of the TLR register (see chapter ) and is reset, when at the current or last valid input event a direction change was detected. The SYT bit is not influenced by setting the TOR bit 

The DPLL_STATUS register is reset, when the DPLL is disabled (switching DEN from 1 to 0).

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(x=0…31))

(q)

Address offset: see Appendix B Initial value: 0x0000_01FE

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ID_PMTR_x Bit

Mode

Initial value

0x000000

RPw

0x01FE

Bit

[23:31]

[0:22]

Table 243. DPLL_ID_PMTR_x field description

Description

ID_PMTR_x : ID information to the input signal PMTR_x from the ARU.

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

16.11.32 DPLL_CTRL_0_SHADOW_TRIGGER: Shadow Register of

DPLL_CTRL_0 controlled by a valid TRIGGER Slope

Address offset: see Appendix B Initial value: 0x0000_0257

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[22:31]

[6:20]

Table 244. DPLL_CTRL_0_SHADOW_TRIGGER field description

Description

MLT

(1)

: multiplier for TRIGGER; MLT+1 is number of SUB_INC1 pulses between two

TRIGGER events in normal mode (1…1024);

IFP

(1)

: Input filter position; value contains position or time related information.

Reserved

Note: Read as zero, should be written as zero.

AMT

(1)

: Adapt mode TRIGGER; Use of adaptation information of TRIGGER.

Reserved

Note:

Read as zero, should be written as zero.

IDT

(1)

: Input delay TRIGGER; use of input delay information transmitted in FT part of the

TRIGGER signal.

q. The registers DPLL_ID_PMTR_24-31 are only available for device 4.

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Table 244. DPLL_CTRL_0_SHADOW_TRIGGER field description (continued)

Description

[1:2]

Reserved

Note:

Read as zero, should be written as zero.

RMO

(1)

: Reference mode; selection of the relevant the input signal for generation of

SUB_INC1.

1. The registers DPLL_ID_PMTR_24-31 are only available for device 4.

Note: Only the values characterized by Note 1 are stored for a valid TRIGGER slope. All other values remain 0. When DEN=0 the relevant bit values of the original register DPLL_CTRL_0 are transferred without any input event at the next system clock. This results in the above reset value.

16.11.33 DPLL_CTRL_0_SHADOW_STATE: Shadow Register of DPLL_CTRL_0 controlled by a valid STATE Slope

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 245. DPLL_CTRL_0_SHADOW_STATE field description

Description

[22:31]

Reserved

Note: Read as zero, should be written as zero.

IFP

(1) : Input filter position; value contains position or time related information.

Reserved

Note:

Read as zero, should be written as zero.

AMS

(1)

: Adapt mode STATE; Use of adaptation information of STATE.

Reserved

Note: Read as zero, should be written as zero.

IDS

(1)

: Input delay STATE; Use of input delay information transmitted in FT part of the STATE signal.

[1:3]

Reserved

Note:

Read as zero, should be written as zero.

RMO

(1)

: Reference mode; selection of the relevant the input signal for generation of

SUB_INC1.

1. This value is stored for a valid STATE slope. All other values remain 0. When DEN=0 the relevant bit values of the original register DPLL_CTRL_0 are transferred without any input event at the next system clock

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16.11.34 DPLL_CTRL_1_SHADOW_TRIGGER: Shadow Register of

DPLL_CTRL_1 controlled by a valid TRIGGER Slope

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Table 246. DPLL_CTRL_1_SHADOW_TRIGGER field description

Bit Description

31 DMO

(1)

: DPLL mode select.

[29:30]

Reserved

Note: Read as zero, should be written as zero.

COA

(1)

: Correction strategy in automatic end mode (DMO=0).

PIT

(1)

: Plausibility value PVT to next valid TRIGGER is time related

SGE1

(1)

: SUB_INC1 generator enable.

DLM1

(1)

: Direct Load Mode for SUB_INC1 generation

PCM1

(1)

: Pulse Correction Mode for SUB_INC1 generation.

[0:3]

Reserved

Note: Read as zero, should be written as zero.

1. This value is stored for a valid TRIGGER slope. All other values remain 0. When DEN=0 the relevant bit values of the original register DPLL_CTRL_1 are transferred without any input event at the next system clock.

16.11.35 DPLL_CTRL_1_SHADOW_STATE: DPLL Shadow Register of

DPLL_CTRL_1 controlled by a valid STATE Slope

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

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Table 247. DPLL_CTRL_1_SHADOW_STATE field description

Bit

[29:30]

Description

DMO

(1)

: DPLL mode select.

Reserved

Note: Read as zero, should be written as zero.

COA

(1)

: Correction strategy in automatic end mode (DMO=0).

[0:20]

Reserved

Note:

Read as zero, should be written as zero.

SGE1

(1)

: SUB_INC1 generator enable.

DLM1

(1) : Direct Load Mode for SUB_INC1 generation

PCM1

(1)

: Pulse Correction Mode for SUB_INC1 generation.

SGE2

(1)

: SUB_INC2 generator enable.

DLM2

(1)

: Direct Load Mode for SUB_INC2 generation

PCM2

(1)

: Pulse Correction Mode for SUB_INC2 generation.

SYN_NS

: Synchronization number of STATE; summarized number of virtual increments in

HALF_SCALE

1. This value is stored for a valid STATE slope. All other values remain 0. When DEN=0 the relevant bit values of the original register DPLL_CTRL_1 are transferred without any input event at the next system clock.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 248. DPLL_RAM_INI field description

Description

INIT_1A

: RAM region 1a initialization in progress

0 =No initialization of considered RAM region in progress

1 =Initialization of considered RAM region in progress

INIT_1B

: RAM region 1b initialization in progress see bit 31

INIT_2

: RAM region 2 initialization in progress see bit 31

Reserved

Note:

Read as zero, should be written as zero.

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Table 248. DPLL_RAM_INI field description (continued)

Description

INIT_RAM : RAM regions 1a, 1b and 2 are to be initialized.

0 =Do not start initialization of all RAM regions

1 =Start initialization of all RAM regions

Note:

Setting the INIT_RAM bit results only in a RAM reset when the DPLL is not enabled

(DEN=0).

Note:

Depending on the vendor configuration the connected RAM regions are initialized to zero in the case of a module HW reset or for setting the RST bit in the GTM_RST register.

Note: In the case of no RAM initialization it must be ensured that all relevant parameters are configured correctly. Otherwise there is no guarantee to get a predictable behavior.

Reserved

Note:

Read as zero, should be written as zero.

16.11.37 DPLL_PSA[i]: Position request for Action i, (RAM1a, i=0...31)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

PSA

RPw

0x000000

Table 249. DPLL_PSA[i] field description

Bit

[8:31]

Description

PSA:

Position information of a desired action (i=0…31)

(1)

Note: This value can only be written when the DPLL is disabled.

[0:7]

Reserved

Note: Read as zero, should be written as zero.

1. The PSA values for actions 24...31 are only available for device 4.

16.11.38 Memory DPLL_DLA[i]: Time to React for Action i, (RAM1a, i=0...31)

Address offset: see Appendix B Initial value: 0x0000_0000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit

Mode

Initial value

Reserved

0x00

DLA

RPw

0x000000

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Bit

Table 250. Memory DPLL_DLA[i] field description

Description

[8:31]

DLA : Time to react before the corresponding position value of a desired action is reached

(x=0…31)

(1)

. In the case of LOW_RES=1 (see

Table 205

) this delay value must be also given

as low resolution value.

Note:

This value can only be written when the DPLL is disabled.

[0:7]

Reserved

Note:

Read as zero, should be written as zero.

1. The DLA values for actions 24...31 are only available for device 4.

Increments to Action i, (RAM1a, i=0...31)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

Reserved DW

RPw

0x0

RPw

0x000

RPw

0x000

Table 251. Memory DPLL_NA[i] field description

Bit

[22:31]

[12:21]

[8:11]

Description

: number of events to Action_i (fractional part, i=0...31

(1)

Note: This value can only be written when the DPLL is disabled.

: number of events to Action_i (integer part, i=0...31

(1)

Note: Use the maximum value for DW=0x3FF in the case of a calculated value which exceeds the represent able value.

Note: This value can only be written when the DPLL is disabled.

Reserved

Note: Read as zero, should be written as zero.

[0:7]

Reserved

Note: Read as zero, should be written as zero.

1. The NA values for actions 24...31 are only available for device 4.

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16.11.40 Memory DPLL_DTA[i]: Calculated Relative Time to Action i, (RAM1a, i=0...31)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DTA Bit

Mode

Initial value

0x00

RPw

0x000000

Table 252. Memory DPLL_DTA[i] field description

Bit

[8:31]

Description

DTA : calculated relative time to ACTION_i (i=0...31)

(1)

Note:

This value can only be written when the DPLL is disabled. The DTA value is a positive integer value. When calculations using

Equation 34

Equation 43

result in a negative value, it is replaced by zero.

[0:7]

Reserved

Note:

Read as zero, should be written as zero.

1. The DTA values for actions 24...31 are only available for device 4.

16.11.41 Memory DPLL_TS_T: Actual TRIGGER time stamp value register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TRIGGER_TS Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 253. memory DPLL_TS_T field description

Description

TRIGGER_TS : Time stamp value of the last valid TRIGGER input.

measured TRIGGER time stamp

Note: The LSB address is determined using the SWON_T value in the OSW register (see

Section 16.11.8

Reserved

Note:

Read as zero, should be written as zero.

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16.11.42 Memory DPLL_TS_T_OLD: previous TRIGGER time stamp value register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TRIGGER_TS_OLD Bit

Mode

Initial value

0x00

0x0000

Bit

[8:31]

[0:7]

Table 254. Memory DPLL_TS_T_OLD field description

Description

TRIGGER_TS_OLD : Time stamp value of the last but one valid TRIGGER input.

previous measured TRIGGER time stamp

Note: The LSB address is determined using the SWON_T value in the OSW register (see

Section 16.11.8

Reserved

Note:

Read as zero, should be written as zero.

16.11.43 Memory DPLL_FTV_T: Actual TRIGGER filter value register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

TRIGGER_FT

0x0000

Bit

[8:31]

[0:7]

Table 255. Memory DPLL_FTV_T field description

Description

TRIGGER_FT : Filter value of the last valid TRIGGER input.

transmitted filter value

Note:

The LSB address is determined using the SWON_T value in the OSW register (see

Section 16.11.8

Reserved

Note: Read as zero, should be written as zero.

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16.11.44 Memory DPLL_TS_S: Actual STATE time stamp register

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved STATE_TS Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 256. Memory DPLL_TS_S field description

Description

STATE_TS : Time stamp value of the last valid STATE input.

Note:

The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

Reserved

Note: Read as zero, should be written as zero.

16.11.45 Memory DPLL_TS_S_OLD: previous STATE time stamp register

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

STATE_TS_OLD

0x000000

Bit

[8:31]

[0:7]

Table 257. Memory DPLL_TS_S_OLD field description

Description

STATE_TS_OLD

: Time stamp value of the last valid STATE input.

Note: The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

Reserved

Note:

Read as zero, should be written as zero.

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16.11.46 Memory DPLL_FTV_S: Actual STATE filter value

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved STATE_FT Bit

Mode

Initial value

0x00

0x0000

Bit

[8:31]

[0:7]

Table 258. Memory DPLL_FTV_S field description

Description

STATE_FT : Filter value of the last valid STATE input.

transmitted filter value

Note:

The LSB address is determined using the SWON register (see Section 16.11.8

Reserved

Note: Read as zero, should be written as zero.

16.11.47 Memory DPLL_THMI: TRIGGER hold time min value

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved THMI Bit

Mode

Initial value

0x00

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 259. Memory DPLL_THMI field description

Description

THMI : minimal time between active and inactive TRIGGER slope (uint16); the time value corresponds to the time stamp clock counts: this does mean the clock selected for the

TBU_CH0_BASE (see TBU_CH0_CTRL register) set min value; generate the TINI interrupt in the case of a violation for THMI>0.

Note: Typical retention time values after a valid slope can be e.g. between 45 µs (forwards) and 90 µs (backwards). When THMI is zero, consider always a THMI violation

(forwards).

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved THMA Bit

Mode

Initial value

0x00

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 260. Memory DPLL_THMA field description

Description

THMA : maximal time between active and inactive TRIGGER slope (uint16); the time value corresponds to the time stamp clock counts: this does mean the clock selected for the

TBU_CH0_BASE (see TBU_CH0_CTRL register) max value to be set; generate the TAX interrupt in the case of a violation for THMA>0.

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved THVAL Bit

Mode

Initial value

0x00

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 261. Memory DPLL_THVAL field description

Description

THVAL : measured time from the last valid slope to the next inactive TRIGGER slope in time stamp clock counts: this does mean the clock selected for the TBU_CH0_BASE (uint16); measured value

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

Note: In the case of LOW_RES=1 and TBU_HRT=0 the difference between the time stamps of valid and invalid slope is multiplied by 8. The register contains this value.

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16.11.50 Memory DPLL_TOV: Time Out Value of Active TRIGGER Slope (for missing TRIGGER generation)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved DW DB

0x00

RW RW

0x000

Bit

[22:31]

[16:21]

[8:15]

[0:7]

Table 262. Memory DPLL_TOV field description

Description

DB : Decision value (fractional part) for missing TRIGGER interrupt.

: Decision value (integer part) for missing TRIGGER interrupt.

TOV(15:0) is to be multiplied with the duration of the last increment and divided by 1024 in order to get the timeout time value for a missing TRIGGER event.

Note: For the case of LOW_RES=1 (see DPLL_STATUS register) consider for the calculation of the time out value the following cases: 

LOW_RES=1 and DPLL_CTRL_1/TS0_HRT=1:  multiply the TBU_TS0 value by 8 

LOW_RES=1 and DPLL_CTRL_1/TS0_HRT=0:  multiply the TBU_TS0 value by  multiply the estimated time point value (using TS_T, dt_t_ACT and TOV) by 8 

LOW_RES=0 and DPLL_CTRL_1/TS0_HRT=0:  use TBU_TS0 and the estimated time point value unchanged.

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

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16.11.51 Memory DPLL_TOV_S: Time Out Value of Active STATE Slope (for missing STATE generation)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved DW DB Bit

Mode

Initial value

0x00

0x000

Bit

[22:31]

[16:21]

[8:15]

[0:7]

Table 263. Memory DPLL_TOV_S field description

Description

DB : Decision value (fractional part) for missing STATE interrupt.

: Decision value (integer part) for missing STATE interrupt.

TOV_S ([16:31]) is to be multiplied with the duration of the last increment and divided by 1024 in order to get the timeout time value for a missing STATE event.

Note:

For the case of LOW_RES=1 (see DPLL_STATUS register) consider for the calculation of the time out value the following cases: 

LOW_RES=1 and DPLL_CTRL_1/TS0_HRS=1:  multiply the TBU_TS0 value by 8 

LOW_RES=1 and DPLL_CTRL_1/TS0_HRS=0:  multiply the TBU_TS0 value by 8  multiply the estimated time point value (using TS_T, dt_s_ACT and TOV_S) by 8 

LOW_RES=0 and DPLL_CTRL_1/TS0_HRS=0  use TBU_TS0 and the estimated time point value unchanged.

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

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16.11.52 Memory DPLL_ADD_IN_CAL1: Calculated ADD_IN Value for SUB_INC1

Generation

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ADD_IN_CAL1 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 264. Memory DPLL_ADD_IN_CAL1 field description

Description

ADD_IN_CAL_1 : Calculated input value for SUB_INC1 generation, calculated by the DPLL.

calculated value

The update of the ADD_IN value by the new calculated value ADD_IN_CAL1 is suppressed for one increment when an unexpected missing TRIGGER (SMC=1 or RMO=0) or an unexpected STATE (RMO=1 and SMC=0) is detected.

Reserved

Note:

Read as zero, should be written as zero.

generation

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved ADD_IN_CAL2 Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 265. Memory DPLL_ADD_IN_CAL2 field description

Description

ADD_IN_CAL_2 : Input value for SUB_INC2 generation, calculated by the DPLL for

SMC=RMO=1.

calculated value

The update of the ADD_IN value by the calculated value ADD_IN_CAL2 is suppressed for one increment when an unexpected missing STATE (RMO=SMC=1) is detected.

Reserved

Note: Read as zero, should be written as zero.

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16.11.54 Memory DPLL_MPVAL1: Missing pulses to be added or subtracted directly

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

SIX1

0x00

MPVAL1

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 266. Memory DPLL_MPVAL1 field description

Description

MPVAL1

: missing pulses for direct correction of SUB_INC1 pulses by the CPU (sint16); used only for RMO=0 or SMC=1 for the case PCM1=1. Add MPVAL1 once to INC_CNT1 and reset PCM1 after applying once

SIX1 : sign extension for MPVAL1

0x00 =MPVAL1 is a positive number

0xFF =MPVAL1 is a negative number

Note: All bits must be written to either all zeros or all ones.

Reserved

Note: Read as zero, should be written as zero.

Note: Do not provide negative values which exceed the amount of NT*(MLT+1) or MLS1 respectively; when considered negative PD values the sum of both should not exceed the amount of NT*(MLT+1) or MLS1 respectively.

16.11.55 Memory DPLL_MPVAL2: Missing pulses to be added or subtracted directly

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved SIX2 MPVAL2

0x00

0x0000

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Bit

[16:31]

[8:15]

[0:7]

Table 267. Memory DPLL_MPVAL2 field description

Description

MPVAL2 : missing pulses for direct correction of SUB_INC2 pulses by the CPU (sint16); used only for SMC=RMO=1 for the case PCM2=1. Add MPVAL2 once to INC_CNT2 and reset PCM2 after applying once

Note:

Do not provide negative values which exceed the amount of MLS2; when considered negative PD_S values the sum of both should not exceed the amount of MLS2.

SIX2

: sign extension for MPVAL2

0x00 =MPVAL2 is a positive number

0xFF =MPVAL2 is a negative number

Note: All bits must be written to either all zeros or all ones.

Reserved

Note: Read as zero, should be written as zero.

16.11.56 Memory DPLL_NMB_T_TAR: target number of pulses to be sent in normal mode

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved NMB_T_TAR

0x00

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 268. Memory DPLL_NMB_T_TAR field description

Description

NMB_T_TAR : Target Number of pulses for TRIGGER; Calculated number of pulses in normal mode for the current TRIGGER increment without missing pulses.

calculated target pulse number

Note:

The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

Pulses to be Sent in Normal Mode

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

Reserved

0x00

NMB_T_TAR_OLD

0x0000

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Bit

[16:31]

[8:15]

[0:7]

RM0361

Table 269. Memory DPLL_NMB_T_TAR_OLD field description

Description

NMB_T_TAR_OLD : Target Number of pulses for TRIGGER; Calculated number of pulses in normal mode for the current TRIGGER increment without missing pulses.

calculated target pulse number

Note:

The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

16.11.58 Memory DPLL_NMB_S_TAR: Target Number of Pulses to be Sent in

Emergency Mode

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved NMB_S_TAR Bit

Mode

Initial value

0x00

0x0

0x00000

Bit

[12:31]

[8:11]

[0:7]

Table 270. Memory DPLL_NMB_S_TAR field description

Description

NMB_S_TAR

: Target Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment without missing pulses.

calculated target pulse number

Note:

The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note:

Read as zero, should be written as zero.

16.11.59 Memory DPLL_NMB_S_TAR_OLD: Target number of pulses to be sent in emergency mode

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved NMB_S_TAR_OLD Bit

Mode

Initial value

0x00

0x0

0x00000

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Bit

[12:31]

[8:11]

[0:7]

Table 271. Memory DPLL_NMB_S_TAR_OLD field description

Description

NMB_S_TAR_OLD : Target Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment without missing pulses.

calculated target pulse number

Note:

The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8: DPLL_OSW (offset and switch old/new address register)

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

16.11.60 Memory DPLL_RCDT_TX: Reciprocal value of the expected increment duration of TRIGGER

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RCDT_TX Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 272. Memory DPLL_RCDT_TX field description

Description

RCDT_TX

: Reciprocal value of expected increment duration *2 are used.

while only the lower 24 bits

Calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF.

Reserved

Note:

Read as zero, should be written as zero.

16.11.61 Memory DPLL_RCDT_SX: Reciprocal value of the expected increment duration of STATE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RCDT_SX Bit

Mode

Initial value

0x00

0x000000

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Bit

[8:31]

[0:7]

Table 273. Memory DPLL_RCDT_SX field description

RM0361

Description

RCDT_SX : Reciprocal value of expected increment duration *2

while only the lower 24 bits are used.

Calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF.

Reserved

Note: Read as zero, should be written as zero.

Nominal Increment Duration of TRIGGER

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RCDT_TX_NOM Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 274. Memory DPLL_RCDT_TX_NOM field description

Description

RCDT_TX_NOM

: Reciprocal value of nominal increment duration *2 bits are used.

while only the lower 24

Calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF.

Reserved

Note:

Read as zero, should be written as zero.

Nominal Increment Duration of STATE

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RCDT_SX_NOM

0x00

0x000000

Bit

[8:31]

[0:7]

Table 275. Memory DPLL_RCDT_SX_NOM field description

Description

RCDT_SX_NOM : Reciprocal value of nominal increment duration *2

while only the lower 24 bits are used.

calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF.

Reserved

Note: Read as zero, should be written as zero.

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Note: RCDT_TX_NOM and RCDT_SX_NOM are calculated by the values RCDT_TX and

RCDT_SX to be multiplied with SYN_T or SYN_S respectively.

16.11.64 Memory DPLL_RDT_T_ACT: Reciprocal Value of the Last Increment of

TRIGGER

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RDT_T_ACT Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 276. Memory DPLL_RDT_T_ACT field description

Description

RDT_T_actual : Reciprocal value of last TRIGGER increment *2

, only the lower 24 bits are used; the LSB is rounded up when the next truncated bit is 1.

calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF and the

CRO bit in the DPLL_STATUS register is set (see

Section 16.11.30

Reserved

Note:

Read as zero, should be written as zero.

16.11.65 Memory DPLL_RDT_S_ACT: Reciprocal Value of the Last Increment of

STATE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RDT_S_ACT Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 277. Memory DPLL_RDT_S_ACT field description

Description

RDT_S_ACT : Reciprocal value of last STATE increment *2

, only the lower 24 bits are used; the LSB is rounded up when the next truncated bit is 1. calculated value; when an overflow occurs in calculation the value is set to 0xFFFFFF and the

CRO bit in the DPLL_STATUS register is set (see

Section 16.11.30

Reserved

Note: Read as zero, should be written as zero.

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16.11.66 DT_T_ACT (duration of the last TRIGGER increment (DT_T_ACT))

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

DT_T_ACT

0x000000

Bit

[8:31]

[0:7]

Table 278. Memory DPLL_DT_T_ACT field description

Description

DT_T_ACT

: Calculated duration of the last TRIGGER increment.

calculated duration of the last increment;

Value will be written into the corresponding RAM field, when all calculations for the considered increment are done and APT is valid.

Reserved

Note:

Read as zero, should be written as zero.

16.11.67 Memory DPLL_DT_S_ACT: Duration of the last STATE increment

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DT_S_ACT Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 279. Memory DPLL_DT_S_ACT field description

Description

DT_S_ACT : Calculated duration of the last STATE increment.

Calculated increment duration

Value will be written into the corresponding RAM field, when all calculations for the considered increment are done and APS is valid.

Reserved

Note: Read as zero, should be written as zero.

16.11.68 Memory DPLL_EDT_T: Difference of Prediction to Actual Value of the

Last TRIGGER Increment

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved EDT_T

0x00

0x000000

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Bit

[8:31]

[0:7]

Digital PLL module (DPLL)

Table 280. Memory DPLL_EDT_T field description

Description

EDT_T : Signed difference between actual value and a simple prediction of the last TRIGGER increment: sint24 calculated error value

Reserved

Note: Read as zero, should be written as zero.

TRIGGER)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

MEDT_T

0x000000

Bit

[8:31]

[0:7]

Table 281. Memory DPLL_MEDT_T field description

Description

MEDT_T

: Signed middle weighted difference between actual value and prediction of the last

TRIGGER increments: sint24; only calculated for SYT=1 calculated medium error value, see

Section 16.6.2.6: Equation 9 to calculate the weighted average error

The value is calculated only after synchronization (SYT=1) and the update is suppressed for one increment when an unexpected missing TRIGGER is detected.

Reserved

Note: Read as zero, should be written as zero.

last STATE increment)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved EDT_S

0x00

0x000000

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Bit

[8:31]

[0:7]

RM0361

Table 282. Memory DPLL_EDT_S field description

Description

EDT_S : Signed difference between actual value and prediction of the last STATE increment: sint24 calculated error value, see

Section 16.6.2.5: Equation 8 to calculate the error of last prediction

Reserved

Note:

Read as zero, should be written as zero.

16.11.71 Memory DPLL_MEDT_S: Weighted difference of prediction errors of

STATE)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved MEDT_S

0x00

0x000000

Bit

[8:31]

[0:7]

Table 283. Memory DPLL_MEDT_S field description

Description

MEDT_S : Signed middle weighted difference between actual value and prediction of the last

STATE increments: sint24; only calculated for SYS=1 calculated medium error value, see

Section 16.6.2.6: Equation 9 to calculate the weighted average error

The value is calculated only after synchronization (SYS=1) and the update is suppressed for one increment when an unexpected missing STATE is detected.

Reserved

Note:

Read as zero, should be written as zero.

duration)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved CDT_TX

0x00

0x000000

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Bit

[8:31]

[0:7]

Digital PLL module (DPLL)

Table 284. Memory DPLL_CDT_TX field description

Description

CDT_TX : Calculated duration of the current TRIGGER increment.

calculated value

Reserved

Note:

Read as zero, should be written as zero.

16.11.73 Memory DPLL_CDT_SX: Prediction of the actual STATE increment duration

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved CDT_SX

0x00

0x000000

Bit

[8:31]

[0:7]

Table 285. Memory DPLL_CDT_SX field description

Description

CDT_SX : Calculated duration of the current STATE increment.

calculated value

Reserved

Note:

Read as zero, should be written as zero.

increment duration

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

CDT_TX_NOM

0x000000

Bit

[8:31]

[0:7]

Table 286. Memory DPLL_CDT_TX_NOM field description

Description

CDT_TX_NOM : Calculated duration of the current nominal TRIGGER event.

calculated value

Reserved

Note:

Read as zero, should be written as zero.

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increment duration

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

CDT_SX_NOM

0x000000

Bit

[8:31]

[0:7]

Table 287. Memory DPLL_CDT_SX_NOM field description

Description

CDT_SX_NOM

: Calculated duration of the current t nominal STATE event.

calculated value

Reserved

Note: Read as zero, should be written as zero.

16.11.76 Memory DPLL_TLR: TRIGGER locking range

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved TLR

0x00

0x0000

0x00

Bit

[24:31]

[8:23]

[0:7]

Table 288. Memory DPLL_TLR field description

Description

TLR : Value is to be multiplied with the last nominal TRIGGER duration in order to get the range for the next TRIGGER event without setting TOR in the DPLL_STATUS register multiply value with the last nominal increment duration and check violation; when TLR=0 don't perform the check

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note:

Read as zero, should be written as zero.

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16.11.77 Memory DPLL_SLR: STATE locking range

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x00000000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

Reserved

0x0000

SLR

0x00

Bit

[24:31]

[8:23]

[0:7]

Table 289. Memory DPLL_SLR field description

Description

SLR

: Value is to be multiplied with the last nominal STATE duration in order to get the range for the next STATE event without setting SOR bit in the DPLL_STATUS register multiply value with the last nominal increment duration and check violation; when SLR=0 don't perform the check.

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

16.11.78 Memory DPLL_PDT_[i]: Projected increment sum relations for

Action_[i]

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved DW DB

0x00

0x000

0x0000

Bit

Table 290. Memory DPLL_PDT_[i] field description

Description

[18:31]

[8:17]

: Fractional part of relation between TRIGGER or STATE increments.

DW : Integer part of relation between TRIGGER or STATE increments.

Definition of relation values between TRIGGER or STATE increments PDT_[i] according to

equations 30

or equations

(i = 0...31)

(1)

Note:

The PDT_i values for actions 24...31 are only available for device 4.

[0:7]

Reserved

Note:

Read as zero, should be written as zero.

1. The PDT_i values for actions 24...31 are only available for device 4.

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STATE events for SMC=0

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved MLS1

0x00

0x0000_0

Bit

[14:31]

[8:13]

[0:7]

Table 291. Memory DPLL_MLS1 field description

Description

MLS1 : number of pulses between two STATE events (to be set and updated by the CPU).

For SMC=0 the value of MLS1 is calculated once by the CPU for fixed values in the

DPLL_CTRL_0 register by the formula MLS1 = ((MLT+1)*(TNU+1)/(SNU+1)) and set accordingly

FOR SMC=1 the value of MLS1 represents the number of pulses between two TRIGGER events (to be set and updated by the CPU)

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note:

Read as zero, should be written as zero.

STATE events for SMC=1 and RMO=1

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

Reserved

0x00

MLS2

0x0000_0

Bit

[14:31]

[8:13]

[0:7]

Table 292. Memory DPLL_MLS2 field description

Description

MLS2 : number of pulses between two STATE events (to be set and updated by the CPU).

Using adapt information and the missing STATE event information SYN_S, this value can be corrected for each increment automatically.

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved CNT_NUM_1

0x00

0x000000

Bit

[8:31]

[0:7]

Table 293. Memory DPLL_CNT_NUM_1 field description

Description

CNT_NUM_1 : Counter for number of SUB_INC1 pulses; Number of pulses in continuous mode for a nominal increment in normal and emergency mode for SUB_INC1, given and updated by CPU only.

Count value for continuous mode

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

CNT_NUM_2

0x000000

Bit

[8:31]

[0:7]

Table 294. Memory DPLL_CNT_NUM_2 field description

Description

CNT_NUM_2 : Counter for number of SUB_INC2 pulses; Number of pulses in continuous mode for a nominal increment in normal and emergency mode for SUB_INC2, given and updated by CPU only.

Count value for continuous mode

Reserved

Note:

Read as zero, should be written as zero.

16.11.83 Memory DPLL_PVT: Plausibility value of next TRIGGER slope

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

0x00

PVT

0x000000

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Bit

[8:31]

[0:7]

RM0361

Table 295. Memory DPLL_PVT field description

Description

PVT : Plausibility value of next valid TRIGGER slope.

The meaning of the value depends on the value of the PIT value in the DPLL_CTRL_1 register.

For PIT=0: the number of SUB_INC1 pulses to be waited for until a next valid TRIGGER event is accepted.

For PIT=1: PVT is to be multiplied with the last nominal increment time DT_T_ACT and divided by 1024 and reduced to a 24 bit value in order to get the time to be waited for until the next valid TRIGGER event is accepted. The wait time must be exceeded for a valid slope.

Note: When a valid TRIGGER slope is detected while the wait condition is not fulfilled the interrupt PWI is generated. Please note, that the SGE1 must be set, when PIT=0 in order to provide the necessary SUB_INC1 pulses for checking. After an unexpected missing

TRIGGER the plausibility check is suppressed for the following increment.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

PSTC

0x000000

Bit

[8:31]

[0:7]

Table 296. Memory DPLL_PSTC field description

Description

PSTC

: calculated position stamp of last TRIGGER input; value is set by the DPLL and can be updated by the CPU when filter values are to be considered for the exact position

(see DPLL_STATUS and DPLL_CTRL registers for explanation of the status and control bits used). For each valid slope of TRIGGER in normal mode when FTD=0: PSTC is set from actual position value, for the first valid TRIGGER event (no filter delay considered) the CPU must update the value once, taking into account the filter value when FTD=1: PSTC is incremented at each TRIGGER event by

SMC=0: (MLT+1)*(SYN_T) +PD; while PD=0 for AMT=0

SMC=1: (MLS1)*(SYN_T) +PD; while PD=0 for AMT=0

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved PSSC

0x00

0x000000

Bit

[8:31]

[0:7]

Table 297. Memory DPLL_PSSC field description

Description

PSSC : calculated position stamp for the last STATE input; first value is set by the DPLL and can be updated by the CPU when the filter delay is to be considered. For each valid slope of STATE in emergency mode when FSD=0: PSSC is set from actual position value (no filter delay considered), the CPU must update the value once, taking into account the filter value when FSD=1: at each valid slope of STATE (PD_S_store=0 for AMS=0):

SMC=0: add MLS1*(SYN_S) + PD_S_store;

SMC=1: add MLS2*(SYN_S) + PD_S_store;

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

PSTM

0x000000

Bit

[8:31]

[0:7]

Table 298. Memory DPLL_PSTM field description

Description

PSTM

: Position stamp of TRIGGER, measured; Measured position stamp of last valid

TRIGGER input.

Store the value TBU_TS1 when a valid TRIGGER event occurs. The value of PSTM is invalid for (RMO=1 and SMC=0).

Reserved

Note: Read as zero, should be written as zero.

Note: The LSB address is determined using the SWON_T value in the OSW register (see

Section 16.11.8

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TRIGGER input

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved PSTM_OLD

0x00

0x000000

Note:

Bit

[8:31]

[0:7]

The LSB address is determined using the SWON_T value in the OSW register (see

Section 16.11.8

Table 299. Memory DPLL_PSTM_OLD field description

Description

PSTM_OLD : Last but one position stamp of TRIGGER, measured; Measured position stamp of last but one valid TRIGGER input.

last PSTM value: see explanation of PSTM

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved PSSM Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 300. Memory DPLL_SSM field description

Description

PSSM : Position stamp of STATE, measured; Measured position stamp of last valid STATE input.

Store the value TBU_TS1 or TBU_TS2 respectively at the moment when a valid STATE event occurs. The value of PSSM is invalid for (RMO=0 and SMC=0).

Reserved

Note:

Read as zero, should be written as zero.

Note: The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

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16.11.89 Memory DPLL_PSSM_OLD: Measured position stamp at last but one

STATE input

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved PSSM_OLD

0x00

0x000000

Bit

[8:31]

[0:7]

Table 301. Memory DPLL_PSSM_OLD field description

Description

PSSM_OLD : Last but one position stamp of STATE, measured; Measured position stamp of last but one valid STATE input.

last PSSM value: see explanation of PSSM

Reserved

Note: Read as zero, should be written as zero.

Note: The LSB address is determined using the SWON_S value in the OSW register (see

Section 16.11.8

16.11.90 Memory NMB_T: Number of pulses to be sent in normal mode

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved Reserved NMB_T Bit

Mode

Initial value

0x00

0x0000

Bit

[16:31]

[8:15]

[0:7]

Table 302. Memory DPLL_NMB_T field description

Description

NMB_T : Number of pulses for TRIGGER; Calculated number of pulses in normal mode for the current TRIGGER increment.

calculated pulse number

Reserved

Note: Read as zero, should be written as zero.

Reserved

Note: Read as zero, should be written as zero.

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16.11.91 Memory DPLL_NMB_S: Number of pulses to be sent in emergency mode

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

Reserved

0x0

NMB_S

0x00000

Bit

[12:31]

[8:11]

[0:7]

Table 303. Memory DPLL_NMB_S field description

Description

NMB_S

: Number of pulses for STATE; Calculated number of pulses in emergency mode for the current STATE increment.

calculated pulse number

Reserved

Note:

Read as zero, should be written as zero.

Reserved

Note:

Read as zero, should be written as zero.

16.11.92 Memory DPLL_RDT_S[i]: Reciprocal Values of the Nominal STATE

Increment Durations in FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

RDT_S

0x000000

Bit

[8:31]

[0:7]

Table 304. Memory DPLL_RDT_S[i] field description

Description

RDT_S

: Reciprocal difference time of TRIGGER; nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment *2

while only the lower 24 bits are used; no gap considered. The LSB is rounded up when the next truncated bit is 1.

Note:

There are 2*(SNU+1-SYN_NS) entries for SYSF=0 or 2*(SNU+1)-SYN_NS entries for

SYSF=1 respectively.

Reserved

Note: Read as zero, should be written as zero.

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16.11.93 Memory DPLL_TSF_S[i]: Time Stamp Values of the Nominal STATE

Events in FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

TSF_S

0x000000

Bit

[8:31]

[0:7]

Table 305. Memory DPLL_TSF_S[i] field description

Description

TSF_S

: Time stamp field of STATE; Time stamp value of each valid STATE event.

Note: There are 2* (SNU+1) entries.

Reserved

Note: Read as zero, should be written as zero.

16.11.94 Memory DPLL_ADT_S[i]: Adapt and Profile Values of the STATE

Increments in FULL_SCALE)

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

Reser ved

PD_S

0x00 0x0 000 0x0000

Bit

[16:31]

[10:15]

[8:9]

[0:7]

Table 306. Memory DPLL_ADT_S[i] field description

Description

PD_S

: Physical deviation of STATE; Adapt values for each STATE increment in FULL_SCALE

(sint16);

This value represents the number of pulses to be added to the correspondent increment.

: Number of STATEs; number of nominal STATE parts in the corresponding increment.

Note:

There are 2*(SNU+1-SYN_NS) entries for SYSF=0 or 2*(SNU+1)-SYN_NS entries for

SYSF=1 respectively.

Reserved

Note:

Must be written to zero.

Reserved

Note:

Read as zero, should be written as zero.

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16.11.95 Memory DPLL_DT_S[i]: Nominal STATE Increment Durations in

FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

DT_S

0x000000

Bit

[8:31]

[0:7]

Table 307. Memory DPLL_DT_S[i] field description

Description

DT_S

: Difference time of STATE; nominal increment duration values for each STATE increment in FULL_SCALE (considering no gap).

Note:

There are 2*(SNU+1-SYN_NS) entries for SYSF=0 or 2*(SNU+1)-SYN_NS entries for

SYSF=1 respectively.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x007F_FFFF

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved TSAC Bit

Mode

Initial value

0x00

RPw

0x7FFFFF

Table 308. DPLL_TSAC[i] field description

Bit

[8:31]

Description

TSAC calculated time stamp for ACTION_i (i = 0...31)

(1)

Note: This value can only be written when the DPLL is disabled.

[0:7]

Reserved

Note: Read as zero, should be written as zero.

1. The DPLL_TSAC24...31 are only available for device 4.

Address offset: see Appendix B Initial value: 0x007F_FFFF

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved PSAC Bit

Mode

Initial value

0x00

RPw

0x7FFFFF

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Bit

Table 309. DPLL_PSAC[i] field description

Description

[8:31]

PSAC : Calculated position value for the start of ACTION_i in normal or emergency mode

according to equations

respectively (i = 0...31)

(1)

Note: This value can only be written when the DPLL is disabled.

[0:7]

Reserved

Note: Read as zero, should be written as zero.

1. The DPLL_PSAC24...31 are only available for device 4.

control registers, j: 0...7)

(r)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[27:31]

[24:26]

[19:23]

[16:18]

[11:15]

[8:10]

[3:7]

[0:2]

0x0

RPw

00000

RPw

00000

RPw

00000

Table 310. DPLL_ACB_i field description

Description

ACB_0 : Action Control Bits of ACTION_i, reflects ACT_D[i](52:48), i=4*j

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

ACB_1 : Action Control Bits of ACTION_(i + 1), reflects ACT_D[i+1](52:48), i=4*j

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

ACB_2 : Action Control Bits of ACTION_(i + 2), reflects ACT_D[i+2](52:48), i=4*j

Note:

: This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

ACB_3 : Action Control Bits of ACTION_(i + 3), reflects ACT_D[i+3](52:48), i=4*j

Note:

This value can only be written when the DPLL is disabled.

Reserved

Note:

Read as zero, should be written as zero.

RPw

00000

Note: The DPLL_ACB_6 and DPLL_ACB_7 register are only available for device 4.

The DPLL_ACB_6 and DPLL_ACB_7 register are only available for device 4.

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Note: Bits 0 to 7 of RAM region 2 are not implemented and therefore always read as zero

(reserved). Other bits which are declared as reserved are not protected against writing.

Unused address regions are not protected against writing when implemented.

16.12.1 Memory DPLL_RDT_T[i]: Reciprocal Values of the Nominal TRIGGER

Increment Durations in FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved RDT_T Bit

Mode

Initial value

0x00

0x000000

Bit

[8:31]

[0:7]

Table 311. Memory DPLL_RDT_T[i] field description

Description

RDT_T : Reciprocal difference time of TRIGGER; 2* (TNU+1- SYN_NT) stored values nominal reciprocal value of the number of time stamp clocks measured in the corresponding increment

(which is divided by the number of nominal increments); multiplied by *232 while only the lower 24 bits are used; the LSB is rounded up, when the next truncated bit is 1.

Note:

There are 2* (TNU+1- SYN_NT) entries. The maximum number of entries is restricted to a value corresponding to the OSS value in the DPLL_OSW register.

Reserved

Note:

Read as zero, should be written as zero.

16.12.2 Memory DPLL_TSF_T[i]: Time Stamp Values of the Nominal TRIGGER

Increments in FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

TSF_T

0x000000

Bit

[8:31]

[0:7]

Table 312. Memory DPLL_TSF_T[i] field description

Description

TSF_T : Time stamp field of valid TRIGGER slopes

Note: There are 2* (TNU+1) entries. The maximum number of entries is restricted to a value corresponding to the OSS value in the DPLL_OSW register.

Reserved

Note: Read as zero, should be written as zero.

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16.12.3 Memory DPLL_ADT_T[i]: Adapt and Profile Values of the TRIGGER

Increments in FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

Reserved

0x00

000

TINT

000

0x0000

Bit

[19:31]

[16:18]

[13:15]

[8:12]

Table 313. Memory DPLL_ADT_T[i] field description

Description

: Physical deviation; Adapt values for each TRIGGER increment in FULL_SCALE (sint13); the PD value does mean the number of SUB_INC1 pulses to be added to NT*(MLT+1); the absolute value of a negative PD must not exceed NT*(MLT+1) or MLS1 respectively; systematic missing TRIGGER events must not be considered for the value of PD.

TINT

: TRIGGER Interrupt information; depending on the value up to 7 different interrupts can be generated. In the current version the 5 interrupts TE0_IRQ … TE4_IRQ are supported by TINT=”001”, “010”, "011”, “100”, “101” respectively. For the values "000", "110" and "111" no interrupt is generated and no other reaction is performed.

The corresponding interrupt is activated, when the TINT value is read by the DPLL together with the other values (PD, NT) according to the profile.

NT : Number of TRIGGERs; number of nominal TRIGGER parts in the corresponding increment.

Note: There are 2* (TNU+1- SYN_NT) entries. The maximum number of entries is restricted to a value corresponding to the OSS value in the DPLL_OSW register.

Reserved

Note: Read as zero, should be written as zero.

FULL_SCALE

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x00

DT_T

0x000000

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Table 314. Memory DPLL_DT_T[i] field description

Description

DT_T : Difference time of TRIGGER; increment duration values for each TRIGGER increment in FULL_SCALE divided by the number of nominal increments (nominal value).

Note: There are 2* (TNU+1- SYN_NT) entries. The maximum number of entries is restricted to a value corresponding to the OSS value in the DPLL_OSW register.

Reserved

Note:

Read as zero, should be written as zero.

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17 Sensor Pattern Evaluation (SPE)

Sensor Pattern Evaluation (SPE)

17.1 Overview

The Sensor Pattern Evaluation (SPE) submodule can be used to evaluate three hall sensor inputs and together with the TOM submodule to support the drive of BLDC engines. Thus, the input signals are filtered already in the connected TIM channels. In addition, the SPE submodule can be used as an input stage to the MAP submodule if the DPLL should be used to calculate the rotation speed of one or two electric engine(s). The integration of the

SPE submodule into the overall GTM-IP architecture concept is shown in Figure 74 .

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Figure 74. SPE submodule integration concept into GTM-IP

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As mentioned above, the SPE submodule can determine a rotation direction out of the combined TIM[i]_CHx(48) , TIM[i]_CHy(48) and TIM[i]_CHz(48) signals. On this input signals a pattern matching algorithm is applied to generate the SPEx_DIR signal on behalf of the temporal relation between these input patterns. A possible sample pattern of the three

DocID025070 Rev 1

RM0361 Sensor Pattern Evaluation (SPE) input signals is shown in

Figure 75

. In general, the input pattern is programmable within the

SPE submodule.

Figure 75. SPE Sample input pattern for TIM[i]_CH[x,y,z](48)

100

110 101

010 001

011

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Figure 75 the input signals define the pattern from the input sensors which have a 50 % high and 50 % low phase. The pattern according to Figure 75 is as follows:

100 – 110 – 010 – 011 – 001 – 101 – 100 where the first bit (smallest circle) represents TIM[i]_CH[x](48) , the second bit represents

TIM[i]_CH[y](48) , and the third bit (greatest circle) represents TIM[i]_CH[z](48) .

Note that the SPE module expects that with every new pattern only one of the three input signals changes its value.

17.2 SPE submodule description

The SPE submodule can handle sensor pattern inputs. Every time that one of the input signals TIM[i]_CH[x](48) , TIM[i]_CH[y](48) or TIM[i]_CH[z](48) changes its value, a sample of all three input signals is made. From this sample, the encoded rotation direction and the validity of the input pattern sequence can be detected and signaled. When a valid input pattern is detected, the SPE submodule can control the outputs of a dedicated connected

TOM submodule. This connection is shown in Figure 76 .

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Figure 76. SPE to TOM connections

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The TOM[i]_CH[x]_TRIG_CCU[y] and TOM[i]_CH[x]_SOUR signal lines are used to evaluate the current state of the TOM outputs, whereas the SPE[i]_OUT output vector is used to control the TOM output depending on the new input pattern. The SPE[i]_OUT output vector is defined inside the SPE submodule in a pattern definition table

SPE[i]_OUT_PAT[x] . The internal SPE submodule architecture is shown in

Figure 77 .

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Figure 77. SPE submodule architecture

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The SPE[i]_PAT register holds the valid input pattern for the three input signals

TIM[i]_CH[x](48) , TIM[i]_CH[y](48) and TIM[i]_CH[z](48) . The input pattern is programmable. The valid bit shows if the programmed pattern is a valid one.

Figure 77

shows the programming of the SPE[i]_PAT register for the input pattern defined in

Figure 75

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The rotation direction is determined by the order of the valid input pattern. This rotation direction defines if the SPE_PAT_PTR is incremented (DIR = 0) or decremented (DIR = 1).

Whenever a valid input pattern is detected, the NIPD signal is raised, the SPE_PAT_PTR is incremented/decremented and a new output control signal SPE[i]_OUT(x) is sent to the corresponding TOM submodule.

The TOM[i]_CH2 with i=0..3 can be used together with the SPE module to trigger a delayed update of the SPE_OUT_CTRL register after new input pattern detected by SPE (signaled by SPE[i]_NIPD ).

To do this, the TOM[i]_CH2 has to be configured to work in one-shot mode (set bit OSM in register TOM[i]_CH2_CTRL ). The SPE mode of this channel has to be enabled, too (set bit

SPEM in register TOM[i]_CH2_CTRL ). The SPE module has to be configured to update

SPE_OUT_CTRL on TOM[i]_CH2_TRIG_CCU1 (set in SPE[i]_CTRL_STAT bits

TRIG_SEL to '11'). Then, on new input detected by SPE, the signal SPE[i]_NIPD triggers the start of the TOM channel 2 to generates one PWM period by resetting CN0 to 0. On second PWM edge triggered by CCU1 of TOM channel 2, the signal

TOM[i]_CH2_TRIG_CCU1 triggers the update of SPE_OUT_CTRL .

According to Figure 77 the two input patterns “000” and “111” are not allowed combinations

and will generate a SPE[i]_PERR interrupt. These two patterns can be used to determine a sensor input error. A SPE[i]_PERR interrupt will also be raised, if the input patterns occur in a wrong order, e.g. if the pattern "010" does not follow the pattern "110" or "011".

The register SPE[i]_IN_PAT bit field inside the SPE[i]_CTRL_STAT register is implemented, where the input pattern history is stored by the SPE submodule. When a SPE[i]_PERR interrupt occurs, the CPU can detect if a sensor is broken by analyzing the bit pattern NIP inside the SPE[i]_CTRL_STAT register. The input pattern in the SPE[i]_CTRL_STAT register is updated whenever a valid edge is detected on one of the input lines

TIM[i]_CH[x](48) , TIM[i]_CH[y](48) or TIM[i]_CH[z](48) . The pattern bit fields are then shifted. The input pattern history generation inside the SPE[i]_CTRL_STAT register is

shown in Figure 78 .

Additionally to the sensor pattern evaluation the SPE module also provides the feature of fast shut-off for all TOM channels controlled by the SPE module. The feature is enabled by setting bit FSOM in register SPE[i]_CTRL_STAT . The fast shut-off level itself is defined in the bit field FSOL of register SPE[i]_CTRL_STAT . The TIM input used to trigger the fast shut-off is either TIM channel 6 or TIM channel 7 depending on the TIM instance connected to the SPE module. For details of connections please refer to

Figure 74

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Figure 78. SPE[i]_IN_PAT register representation

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The CPU can disable one of the three input signals, e.g. when a broken input sensor was detected, by disabling the input with the three input enable bits SIE inside the

SPE[i]_CTRL_STAT register.

Whenever at least one of the input signal TIM[i]_CH[x](48) , TIM[i]_CH[y](48) or

TIM[i]_CH[z](48) changes the SPE submodule stores the new bit pattern in an internal register NIP (New Input Pattern). If the current input pattern in NIP is the same as in the

Previous Input Pattern (PIP) the direction of the engine changed, the SPE[i]_DCHG interrupt is raised, the direction change is stored internally and the pattern in the PIP bit field is filled with the AIP bit field (Actual Input Pattern) and the AIP bit field is filled with the NIP bit field. The SPE[i]_DIR bit inside the SPE[i]_CTRL_STAT register is toggled and the

SPE[i]_DIR signal is changed.

If the SPE encounters that with the next input pattern detected new input pattern NIP the direction change again, the input signal is categorized as bouncing and the bouncing input signal interrupt SPE[i]_BIS is raised.

Immediately after update of register NIP, when the new detected input pattern doesn’t match the PIP pattern (i.e. no direction change was detected), the SPE shifts the value of register

AIP to register PIP and the value of register NIP to register AIP. The SPE[i]_NIPD interrupt is raised.

The number of the channel that has been changed and thus leads to the new input pattern is encoded in the signal SPE[i]_NIPD_NUM .

If a sensor error was detected, the CPU has to define upon the pattern in the

SPE[i]_CTRL_STAT register, which input line comes from the broken sensor. The faulty signal line has to be masked by the CPU and the SPE submodule determines the rotation direction on behalf of the two remaining TIM[i]_CH[x ] input lines.

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The pattern history can be determined by the CPU by reading the two bit fields AIP and PIP of the SPE[i]_CTRL_STAT register. The AIP register field holds the actual detected input pattern at TIM[i]_CH[x](48) , TIM[i]_CH[y](48) and TIM[i]_CH[z](48) and the PIP holds the previous detected pattern.

After reset the register NIP, AIP and PIP as well as the register SPE[i]_PAT_PTR and

SPE[i]_OUT_CTRL will not contain valid startup values which would allow correct behaviour after enabling SPE and detecting the first input patterns.

Thus, it is necessary to initialize these registers to correct values.

To do this, before enabling the SPE, the bit field NIP of register SPE[i]_CTRL_STAT can be read and depending on this value the initialization values for the register AIP, PIP,

SPT_PAT_PTR and SPE[i]_OUT_CTRL can be determined.

17.2.1 SPE revolution detection

The SPE submodule is able to detect and count the number of valid input patterns detected at the specified input ports. This is done with a 24 bit revolution counter SPE_REV_CNT .

The counter is incremented by a value of one (1) when a new valid input pattern indicating forward direction is detected. The counter is decremented by a value of one (1) when a new valid input pattern indicating backward direction is detected.

In addition there exists a 24 bit SPE_REV_CMP register. The user can initialize this register with a compare value, where an interrupt SPE[i]_RCMP is raised, when the revolution counter equals the compare value either in forward or backward direction.

Both registers may be written by software at any time.

17.3 SPE interrupt signals

The following table describes SPE interrupt signals.

Signal

SPE[i]_NIPD

SPE[i]_DCHG

SPE[i]_PERR

SPE[i]_BIS

SPE[i]_RCMP

Table 315. SPE interrupt signals

Description

SPE new valid input pattern detected.

SPE rotation direction change detected on behalf of input pattern.

SPE invalid input pattern detected.

SPE bouncing input signal detected at input.

SPE revolution counter compare value reached.

17.4 SPE register overview

The following table shows an overview about the SPE register set.

Register name

SPE[i]_CTRL_STAT

SPE[i]_PAT

Table 316. SPE register overview

Description

SPE control status register

SPE input pattern definition register

Details in section

17.5.1

17.5.2

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Register name

SPE[i]_OUT_PAT[x]

SPE[i]_OUT_CTRL

SPE[i]_REV_CNT

SPE[i]_REV_CMP

SPE[i]_IRQ_NOTIFY

SPE[i]_IRQ_EN

SPE[i]_EIRQ_EN

SPE[i]_IRQ_FORCINT

SPE[i]_IRQ_MODE

Table 316. SPE register overview (continued)

Description

SPE output definition registers (x: 0...7)

SPE output control register

SPE input revolution counter

SPE revolution counter compare value

SPE interrupt notification register

SPE interrupt enable register

SPE error interrupt enable register

SPE interrupt generation by software

IRQ mode configuration register

Details in section

17.5.3

17.5.4

17.5.5

17.5.6

17.5.7

17.5.8

17.5.11

17.5.9

17.5.10

17.5 SPE register description

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 317. SPE[i]_CTRL_STAT field description

Description

SPE_EN : SPE Submodule enable.

0 = SPE disabled.

1 = SPE enabled.

SIE0

: SPE Input enable for TIM_CHx(48).

0 = SPE Input is disabled.

1 = SPE Input is enabled.

Note: When the input is disabled, a '0' signal is sampled for this input.

However, the bit field NIP of this register shows the true value of the input signal.

SIE1 : SPE Input enable for TIM_CHy(48).

See bit 30.

SIE2 : SPE Input enable for TIM_CHz(48).

See bit 30.

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Table 317. SPE[i]_CTRL_STAT field description (continued)

Description

TRIG_SEL : Select trigger input signal.

00 = SPE[i]_NIPD selected.

01 = TOM_CH0_TRIG_CCU0 selected.

10 = TOM_CH0_TRIG_CCU1 selected.

11 = TOM_CH2_TRIG_CCU1 selected.

TIM_SEL

: select TIM input signal

SPE0:

0 = TIM0_CH0...2

1 = TIM1_CH0...2

SPE1:

0 = TIM0_CH3...5

1 = TIM1_CH3...5

SPE2:

0 = TIM2_CH0...2

1 = unused

SPE3:

0 = TIM2_CH3...5

1 = unused

FSOM

: Fast Shut-Off Mode

0 = Fast Shut-Off mode disabled

1 = Fast Shut-Off mode enabled

SPE_PAT_PTR : Pattern selector for TOM output signals.

Actual index into the SPE[i]_OUT_PAT[x] register table.

Each register SPE[i]_OUT_PAT[x] is fixed assigned to one bit field IPx_PAT of register

SPE[i]_PAT. Thus, the pointer SPE[i]_PAT_PTR represents an index to the selected

SPE[i]_OUT_PAT[x] register as well as the actual detected input pattern IPx_PAT.

000: SPE[i]_OUT_PAT0 selected

Reserved

Note: Read as zero, should be written as zero.

AIP : Actual input pattern that was detected by a regular input pattern change.

ADIR : Actual rotation direction.

0 = Rotation direction is 0 according to SPE[i]_PAT register.

1 = Rotation direction is 1 according to SPE[i]_PAT register.

PIP : Previous input pattern that was detected by a regular input pattern change.

PDIR : Previous rotation direction.

0 = Rotation direction is 0 according to SPE[i]_PAT register.

1 = Rotation direction is 1 according to SPE[i]_PAT register.

NIP : New input pattern that was detected.

Note: This bit field mirrors the new input pattern. SPE internal functionality is triggered on each change of this bit field.

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Table 317. SPE[i]_CTRL_STAT field description (continued)

Description

Reserved

Note:

Read as zero, should be written as zero.

FSOL : Fast Shut-Off Level for TOM[i] channel 0 to 7

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 000 0 000 0 000 0 000 0 000 0 000 0 000 0 000 0

Bit

[28:30]

[24:26]

[20:22]

[16:18]

[12:14]

Table 318. SPE[i]_PAT field description

Description

IP0_VAL : Input pattern 0 is a valid pattern.

0 = Pattern invalid.

1 = Pattern valid..

IP0_PAT : Input pattern 0.

Bit field defines the first input pattern of the SPE input signals.

Bit 1 defines the TIM[i]_CHx(48) input signal.

Bit 2 defines the TIM[i]_CHy(48) input signal.

Bit 3 defines the TIM[i]_CHz(48) input signal.

IP1_VAL

: Input pattern 1 is a valid pattern.

See bit 31.

IP1_PAT

: Input pattern 1.

See bits [28:30].

IP2_VAL

: Input pattern 2 is a valid pattern.

See bit 31.

IP2_PAT

: Input pattern 2.

See bits [28:30].

IP3_VAL

: Input pattern 3 is a valid pattern.

See bit 31.

IP3_PAT

: Input pattern 3.

See bits [28:30].

IP4_VAL

: Input pattern 4 is a valid pattern

See bit 31.

IP4_PAT

: Input pattern 4.

See bits [28:30].

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Table 318. SPE[i]_PAT field description (continued)

Description

IP5_VAL : Input pattern 5 is a valid pattern

See bit 31.

IP5_PAT : Input pattern 5.

See bits [28:30].

IP6_VAL : Input pattern 6 is a valid pattern

See bit 31.

IP6_PAT : Input pattern 6.

See bits [28:30].

IP7_VAL : Input pattern 7 is a valid pattern

See bit 31.

IP7_PAT : Input pattern 7.

See bits [28:30].

Note:

RM0361

Only the first block of valid input patterns defines the commutator. All input patterns following the first marked invalid input pattern are ignored.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000

SPE_OUT_PAT

0x0000

Bit

[16:31]

[0:15]

Table 319. SPE[i]_OUT_PAT[x] (x: 0...7) field description

Description

SPE_OUT_PAT

: SPE output control value for TOM_CH0 to TOM_CH7

SPE_OUT_PAT[n+1:n] defines output select signal of TOM[i]_CH[n]

00 = set SPE_OUT(n) to TOM_CH0_SOUR

01 = set SPE_OUT(n) to TOM_CH1_SOUR

10 = set SPE_OUT(n) to '0'

11 = set SPE_OUT(n) to '1' with n = 0...7

Reserved

Note:

Read as zero, should be written as zero.

Note: Register SPE_OUT_PAT[x] defines the output selection for TOM[i]_CH0 to TOM[i]_CH7 depending on actual input pattern IP[x]_PAT with x:0...7.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000

SPE_OUT_CTRL

0x0000

Bit

[16:31]

[0:15]

Table 320. SPE[i]_OUT_CTRL field description

Description

SPE_OUT_CTRL

: SPE output control value for TOM_CH0 to TOM_CH7

SPE_OUT_CTRL[n+1:n] defines output select signal of TOM_CHn

00 = set SPE_OUT(n) to TOM_CH0_SOUR

01 = set SPE_OUT(n) to TOM_CH1_SOUR

10 = set SPE_OUT(n) to '0'

11 = set SPE_OUT(n) to '1' with n = 0...7

Note:

Current output control selection for SPE[i]_OUT(0...7).

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved REV_CNT Bit

Mode

Initial value

0x0000

0x000000

Bit

[8:31]

[0:7]

Table 321. SPE[i]_REV_CNT field description

Description

REV_CNT : Input signal revolution counter

The counter is running if SPE module is enabled (bit SPE_EN).

REV_CNT is incrementing if SPE_PAT_PTR is incrementing

REV_CNT is decrementing if SPE_PAT_PTR is decrementing

Reserved

Note:

Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Reserved

0x0000

REV_CMP

0x000000

Bit

[8:31]

[0:7]

Table 322. SPE[i]_REV_CMP field description

Description

REV_CMP

: Input signal revolution counter compare value

The interrupt SPE[i]_RCMP is raised when the SPE[i]_REV_CNT value equals the

SPE[i]_REV_CMP register. It should be noted that SPE[i]_RCMP is only raised if an incrementation or decremention of SPE[i]_REV_CNT is applied, due to a input signal change.

Any update of SPE[i]_REV_CNT or SPE[i]_REV_CMP via AEI does not raise an

SPE[i]_RCMP interrupt.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x0000000

C w

0 0 0 0 0

C w

Table 323. SPE[i]_IRQ_NOTIFY field description

Description

SPE_NIPD : New input pattern interrupt occurred.

0 = No interrupt occurred.

1 = New input pattern detected interrupt occurred.

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

SPE_DCHG

: SPE_DIR bit changed on behalf of new input pattern.

see bit 31.

SPE_PERR

: Wrong or invalid pattern detected at input.

see bit 31.

SPE_BIS

: Bouncing input signal detected.

see bit 31.

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Table 323. SPE[i]_IRQ_NOTIFY field description (continued)

Description

SPE_RCMP : SPE revolution counter match event.

see bit 31.

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

0 0 0 0 0

Mode

Initial value

Bit

[0:26]

0x0000000

Table 324. SPE[i]_IRQ_EN field description

Description

SPE_NIPD_IRQ_EN

: SPE_NIPD_IRQ interrupt enable.

0 = Disable interrupt, interrupt is not visible outside GTM-IP.

1 = Enable interrupt, interrupt is visible outside GTM-IP.

SPE_DCHG_IRQ_EN : SPE_DCHG_IRQ interrupt enable.

see bit 31.

SPE_PERR_IRQ_EN : SPE_PERR_IRQ interrupt enable.

see bit 31.

SPE_BIS_IRQ_EN : SPE_BIS_IRQ interrupt enable.

see bit 31.

SPE_RCMP_IRQ_EN : SPE_RCMP_IRQ interrupt enable.

see bit 31.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

A w

0 0 0 0 0

A w

Mode

Initial value

Bit

[0:26]

0x0000000

Table 325. SPE[i]_IRQ_FORCINT field description

Description

TRG_SPE_NIPD : Force interrupt of SPE_NIPD.

0 = Corresponding bit in status register will not be forced.

1 = Assert corresponding field in SPE_IRQ_NOTIFY register.

Note: This bit is cleared automatically after interrupt is released

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_SPE_DCHG : Force interrupt of SPE_DCHG.

see bit 31.

TRG_SPE_PERR : Force interrupt of SPE_PERR.

see bit 31.

TRG_SPE_BIS : Force interrupt of SPE_BIS.

see bit 31.

TRG_SPE_RCMP : Force interrupt of SPE_RCMP.

see bit 31.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B

Bit

Mode

Initial value

Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Reserved

IRQ_

MOD

0x00000000 00

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[0:29]

Sensor Pattern Evaluation (SPE)

Table 326. SPE[i]_IRQ_MODE field description

Description

IRQ_MODE : IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note:

The interrupt modes are described in

Section 2.5: GTM-IP interrupt concept

Reserved

Note:

Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[0:26]

Table 327. SPE[i]_EIRQ_EN field description

Description

SPE_NIPD_EIRQ_EN

: SPE_NIPD_EIRQ interrupt enable.

0 = Disable error interrupt, error interrupt is not visible outside GTM-IP.

1 = Enable error interrupt, error interrupt is visible outside GTM-IP.

SPE_DCHG_EIRQ_EN : SPE_DCHG_EIRQ error interrupt enable.

see bit 31.

SPE_PERR_EIRQ_EN : SPE_PERR_EIRQ error interrupt enable.

see bit 31.

SPE_BIS_EIRQ_EN : SPE_BIS_EIRQ error interrupt enable.

see bit 31.

SPE_RCMP_EIRQ_EN : SPE_RCMP_EIRQ error interrupt enable.

see bit 31.

Reserved

Note: Read as zero, should be written as zero.

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18 Interrupt Concentrator Module (ICM)

RM0361

18.1 Overview

The Interrupt Concentrator Module (ICM) is used to bundle the GTM-IP interrupt lines of the individual submodules in a reasonable manner into interrupt groups. By this bundling a smaller amount of interrupt lines is visible at the outside of the GTM-IP.

The individual interrupts of the GTM-IP submodules and channels have to be enabled or disabled inside the submodules and channels.

The feed through architecture of bundled interrupt lines is used for the submodules AEI,

ARU, BRC, CMP, SPE, PSM, TIM, DPLL, TOM, ATOM and MCS.

To determine the detailed interrupt source the microcontroller has to read the submodule/channel interrupt notification register NOTIFY and serve the channel individual interrupt.

Please note, that the interrupts are only visible inside the ICM and in consequence outside of the GTM-IP, when the interrupt is enabled inside the submodules themselves.

18.2 Bundling

The GTM-IP submodule individual interrupt sources are connected to the ICM. There, the individual interrupt lines are either feed through and signalled to the outside world or bundled a second time into groups and are then signalled to the outside world.

The ICM interrupt bundling is described in the following sections.

18.2.1 GTM infrastructure interrupt bundling

The first interrupt group contains interrupts of the infrastructure and safety components of the GTM. This interrupt group includes therefore interrupt lines coming from the AEI, ARU,

BRC, PSM, SPE and CMP submodules. In this interrupt group each individual channel of the submodules has its own interrupt line to the outside world.

Thus, the active interrupt line can be used by the CPU to determine the GTM-IP submodule channel that raised the interrupt. The interrupts are also represented in the ICM_IRQG_0 register. This register is typically not read by the CPU, but it is readable.

The DPLL Interrupt group handles the interrupts coming from the DPLL submodule of the

GTM-IP. Each of the individual DPLL interrupt lines has its own dedicated interrupt line to the outside world. The interrupts are additionally identified in the ICM_IRQG_1 interrupt group register. This register is typically not read out by the CPU, but it is readable.

18.2.3 TIM interrupt bundling

Inside this group submodules which handle GTM-IP input signals are treated. This is the case for the TIM[i] submodules. Each TIM submodule channel is able to generate six (6) individual interrupts if enabled inside the TIM channel. This six interrupts are bundled into one interrupt per TIM channel connected to the ICM.

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The ICM does no further bundling. Thus, for the GTM-IP 32 interrupt lines TIM[i]_IRQ [y] are provided for the external microcontroller. The channel responsible for the interrupt can be determined by the raised interrupt line.

In addition, the ICM_IRQG_2 and ICM_IRQG_3 registers are mirrors for the TIM submodule channel interrupts and typically not read out by the CPU, but it is readable.

18.2.4 MCS interrupt bundling

For complex signal output generation, the MCS submodules are used inside the GTM-IP.

Each of these MCS submodules has eight channels with one interrupt line. This interrupt line is connected to the ICM submodule and is fed through directly to the outside world.

In addition the interrupt line status are shown in the ICM_IRQG_4 and ICM_IRQG_5 register. Typically, the interrupt source is determined by the corresponding interrupt line and the ICM_IRQG_4(/_5) register is typically not read out by the CPU, but it is readable.

18.2.5 TOM and ATOM interrupt bundling

For the TOM and ATOM submodules, the interrupts are bundled within the ICM submodule a second time to reduce external interrupt lines. The interrupts are OR-ed in a manner that one GTM-IP external interrupt line represents two adjacent TOM or ATOM channel interrupts. For TOM[i] and ATOM[i] the bundling is shown in

Section 18.2.5.1: TOM and

ATOM interrupt bundling within ICM

18.2.5.1 TOM and ATOM interrupt bundling within ICM

TOM[i]-input IRQs i=0...number of

TOM’s-1

TOM[i]_CH0_IRQ

TOM[i]_CH1_IRQ

TOM[i]_CH2_IRQ

TOM[i]_CH3_IRQ

TOM[i]_CH4_IRQ

TOM[i]_CH5_IRQ

TOM[i]_CH6_IRQ

TOM[i]_CH7_IRQ

TOM[i]_CH8_IRQ

TOM[i]_CH9_IRQ

TOM[i]_CH10_IRQ

TOM[i]_CH11_IRQ

Table 328. TOM and ATOM interrupt bundling

TOM-output IRQs

(OR-ed)

GTM_TOM[i]_IRQ[0]

GTM_TOM[i]_IRQ[1]

GTM_TOM[i]_IRQ[2]

GTM_TOM[i]_IRQ[3]

GTM_TOM[i]_IRQ[4]

GTM_TOM[i]_IRQ[5]

ATOM[i]-input IRQs

[i]=0...number of ATOM’s-1

ATOM[i]_CH0_IRQ

ATOM[i]_CH1_IRQ

ATOM[i]_CH2_IRQ

ATOM[i]_CH3_IRQ

ATOM[i]_CH4_IRQ

ATOM[i]_CH5_IRQ

ATOM[i]_CH6_IRQ

ATOM[i]_CH7_IRQ

ATOM-output IRQs

(OR-ed)

GTM_ATOM[i]_IRQ[0]

GTM_ATOM[i]_IRQ[1]

GTM_ATOM[i]_IRQ[2]

GTM_ATOM[i]_IRQ[3]

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TOM[i]-input IRQs i=0...number of

TOM’s-1

TOM[i]_CH12_IRQ

TOM[i]_CH13_IRQ

TOM[i]_CH14_IRQ

TOM[i]_CH15_IRQ

Table 328. TOM and ATOM interrupt bundling (continued)

TOM-output IRQs

(OR-ed)

ATOM[i]-input IRQs

[i]=0...number of ATOM’s-1

ATOM-output IRQs

(OR-ed)

GTM_TOM[i]_IRQ[6]

GTM_TOM[i]_IRQ[7]

The interrupts coming from the TOM[i] submodules are registered in the ICM_IRQG_6 /

ICM_IRQG_7 / ICM_IRQG_8 register. Always two TOM's are bundled in one ICM register,

TOM0 and TOM1 are bundled in ICM_IRQG_6 . To identify the TOM submodule channel where the interrupt occurred, the CPU has to read out the ICM_IRQG_6(/_7/_8) register first before it goes to the TOM submodule channel itself.

The ICM_IRQG_6(/_7/_8) register bits are cleared automatically, when their corresponding interrupt in the submodule channels is cleared.

The interrupts coming from the ATOM[i] submodules are registered in the ICM_IRQG_9 /

ICM_IRQG_10 /ICM_IRQG_11 register. Always four ATOM's are bundled in one ICM register, ATOM0,ATOM1,ATOM2 and ATOM3 are bundled in ICM_IRQG_9. To identify the

ATOM submodule channel where the interrupt occurred, the CPU has to read out the

ICM_IRQG_9(/_10/_11) register first before it goes to the ATOM submodule channel itself.

The interrupts coming from the ATOM[i] submodules are registered in the ICM_IRQG_9 register. ATOM0,ATOM1 and ATOM2 are bundled in ICM_IRQG_9. To identify the ATOM submodule channel where the interrupt occurred, the CPU has to read out the ICM_IRQG_9 register first before it goes to the ATOM submodule channel itself.

The ICM_IRQG_9(/_10/_11) register bits are cleared automatically, when their corresponding interrupt in the submodule channels is cleared.

18.2.6 Module error interrupt bundling

The Module Error Interrupt group handles the error interrupts coming from the BRC, FIFO,

TIM, MCS, SPE, CMP, DPLL submodule of the GTM-IP. The Module Error interrupts are additionally identified in the ICM_IRQG_MEI error interrupt group register. This register is typically not read out by the CPU, but it is readable.

The ICM_IRQG_MEI register bits are cleared automatically, when their corresponding error interrupt in the submodule is cleared.

18.2.7 FIFO channel error interrupt bundling

The FIFO Channel Error Interrupt group handles the error interrupts coming from the FIFO channel of the GTM-IP. The FIFO Channel Error interrupts are additionally identified in the

ICM_IRQG_CEI0 error interrupt group register. This register is typically not read out by the

CPU, but it is readable.

The ICM_IRQG_CEI0 register bits are cleared automatically, when their corresponding error interrupt in the submodule channel is cleared.

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18.2.8 TIM channel error interrupt bundling

The TIM Channel Error Interrupt group handles the error interrupts coming from the TIM channel of the GTM-IP. The TIM Channel Error interrupts are additionally identified for the submodules TIM0, TIM1, TIM2 and TIM3 in the ICM_IRQG_CEI1 error interrupt group register and for the submodules TIM4, TIM5 and TIM6 in the ICM_IRQG_CEI2 error interrupt group register. These registers are typically not read out by the CPU, but they are readable.

The ICM_IRQG_CEI1 and ICM_IRQG_CEI2 register bits are cleared automatically, when their corresponding error interrupt in the submodule channel is cleared.

18.2.9 MCS channel error interrupt bundling

The MCS Channel Error Interrupt group handles the error interrupts coming from the MCS channel of the GTM-IP. The MCS Channel Error interrupts are additionally identified for the submodules MCS0, MCS1, MCS2 and MCS3 in the ICM_IRQG_CEI3 error interrupt group register and for the submodules MCS4, MCS5 and MCS6 in the ICM_IRQG_CEI4 error interrupt group register. These registers are typically not read out by the CPU, but they are readable.

The ICM_IRQG_CEI3 and ICM_IRQG_CEI4 register bits are cleared automatically, when their corresponding error interrupt in the submodule channel is cleared.

18.3 ICM interrupt signals

Following table shows the GTM-IP interrupt lines that are visible at the outside of the IP.

Signal

GTM_AEI_IRQ

GTM_ARU_IRQ

[2:0]

GTM_BRC_IRQ

GTM_CMP_IRQ

GTM_SPE[i]_IRQ

GTM_PSM[i]_IRQ [x]

GTM_DPLL_IRQ [0]

GTM_DPLL_IRQ [1]

GTM_DPLL_IRQ

[2]

GTM_DPLL_IRQ

[3]

GTM_DPLL_IRQ

[4]

GTM_DPLL_IRQ [5]

GTM_DPLL_IRQ [6]

GTM_DPLL_IRQ [7]

Table 329. ICM interrupt signals

Description

AEI shared interrupt

[0]: ARU_NEW_DATA0 interrupt

[1]: ARU_NEW_DATA1 interrupt

[2]: ARU_ACC_ACK interrupt

BRC shared interrupt

CMP shared interrupt

SPE shared interrupt (i: 0..number of SPE's-1)

PSM shared interrupts (x: 0…7) (i: 0...number of PSM's-1)

DPLL_DCGI: DPLL direction change interrupt

DPLL_EDI; DPLL enable or disable interrupt

DPLL_TINI:

DPLL

TRIG

. min. hold time (THMI) viol. detected

DPLL_TAXI:

DPLL

TRIG.

max. hold time (THMA) viol. detected

DPLL_SISI:

DPLL

STATE

inactive slope detected

DPLL_TISI: DPLL TRIGGER inactive slope detected

DPLL_MSI: DPLL Missing STATE interrupt

DPLL_MTI: DPLL Missing TRIGGER interrupt

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GTM_DPLL_IRQ [8]

GTM_DPLL_IRQ

[9]

GTM_DPLL_IRQ [10]

GTM_DPLL_IRQ

[11]

GTM_DPLL_IRQ [12]

GTM_DPLL_IRQ

[13]

GTM_DPLL_IRQ [14]

GTM_DPLL_IRQ

[15]

GTM_DPLL_IRQ [16]

GTM_DPLL_IRQ

[17]

GTM_DPLL_IRQ [18]

GTM_DPLL_IRQ

[19]

GTM_DPLL_IRQ

[20]

GTM_DPLL_IRQ

[21]

GTM_DPLL_IRQ [22]

GTM_DPLL_IRQ [23]

GTM_DPLL_IRQ [24]

GTM_DPLL_IRQ

[25]

GTM_DPLL_IRQ

[26]

GTM_TIM[i]_IRQ

[x]

GTM_MCS[i]_IRQ [x]

GTM_TOM[i]_IRQ

[x]

GTM_ATOM[i]_IRQ

[x]

GTM_ERR_IRQ

Interrupt Concentrator Module (ICM)

Table 329. ICM interrupt signals (continued)

Description

DPLL_SASI: DPLL STATE active slope detected

DPLL_TASI:

DPLL

TRIG.

active slope detected while NTI_CNT is 0

DPLL_PWI: DPLL plausibility window (PVT) viol. int. of TRIG .

DPLL_W2I:

DPLL write access to RAM region 2 interrupt

DPLL_W1I: DPLL write access to RAM region 1b or 1c int.

DPLL_GL1I:

DPLL get of lock interrupt for

SUB_INC1

DPLL_LL1I: DPLL lost of lock interrupt for SUB_INC1

DPLL_EI:

DPLL error interrupt

DPLL_GL2I: DPLL get of lock interrupt for SUB_INC2

DPLL_LL2I:

DPLL lost of lock interrupt for

SUB_INC2

DPLL_TE0I: DPLL TRIGGER event interrupt 0

DPLL_TE1I:

DPLL

TRIGGER

event interrupt 1

DPLL_TE2I:

DPLL

TRIGGER

event interrupt 2

DPLL_TE3I:

DPLL

TRIGGER

event interrupt 3

DPLL_TE4I; DPLL TRIGGER event interrupt 4

DPLL_CDTI; DPLL calculated duration interrupt for TRIGGER

DPLL_CDSI; DPLL calculated duration interrupt for STATE

DPLL_TORI; TRIGGER

out of range interrupt

DPLL_SORI; STATE

out of range interrupt

TIM Shared interrupts (i: 0...number of TIM's-1) (x: 0...7)

MCS Interrupt for channel x (x: 0…7) (i: 0...number of MCS's-1)

TOM shared interrupts for x:0...7 = {ch0||ch1,...,ch14||ch15}

(i: 0...number of TOM's-1)

ATOM shared interrupts for x:0...3 = {ch0||ch1,...,ch6||ch7}

(i: 0...number of ATOM's-1)

GTM error interrupt

RM0361

ICM_IRQG_0

ICM_IRQG_1

ICM contains the following configuration registers:

Register name

Table 330. ICM configuration registers

Description

ICM interrupt group register covering infrastructural and safety components (ARU, BRC, AEI, PSM0,

PSM1, MAP, CMP,SPE)

ICM interrupt group register covering DPLL

Details in section

18.5.1

18.5.2

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Register name

ICM_IRQG_2

ICM_IRQG_3

ICM_IRQG_4

ICM_IRQG_5

ICM_IRQG_6

ICM_IRQG_7

ICM_IRQG_8

ICM_IRQG_9

ICM_IRQG_10

ICM_IRQG_11

ICM_IRQG_MEI

ICM_IRQG_CEI0

ICM_IRQG_CEI1

ICM_IRQG_CEI2

ICM_IRQG_CEI3

ICM_IRQG_CEI4

Table 330. ICM configuration registers (continued)

Description

ICM Interrupt group register covering TIM0, TIM1,

TIM2, TIM3

ICM Interrupt group register covering TIM4, TIM5,

TIM6, TIM7

ICM Interrupt group register covering MCS0 to MCS3 submodules

ICM Interrupt group register covering MCS4 to MCS6 submodules

ICM Interrupt group register covering GTM-IP output submodules TOM0 to TOM1

ICM Interrupt group register covering GTM-IP output submodules TOM2 to TOM3

ICM Interrupt group register covering GTM-IP output submodules TOM4 to TOM5

ICM Interrupt group register covering GTM-IP output submodules ATOM0, ATOM1, ATOM2 and ATOM3

ICM Interrupt group register covering GTM-IP output submodules ATOM4 to ATOM7

ICM Interrupt group register covering GTM-IP output submodules ATOM8 to ATOM11

ICM Interrupt group register for module error interrupt information

ICM Interrupt group register 0 for channel error interrupt information

ICM Interrupt group register 1 for channel error interrupt information

ICM Interrupt group register 2 for channel error interrupt information

ICM Interrupt group register 3 for channel error interrupt information

ICM Interrupt group register 4 for channel error interrupt information

Details in section

18.5.3

18.5.4

18.5.5

18.5.6

18.5.7

18.5.8

18.5.9

18.5.10

18.5.11

18.5.12

18.5.13

18.5.14

18.5.15

18.5.16

18.5.17

18.5.18

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18.5.1 Register ICM_IRQG_0 (GTM infrastructure interrupt group)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[16:21]

R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0x00

R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0

Table 331. ICM_IRQG_0 field description

Description

ARU_NEW_DATA0_IRQ

: ARU_NEW_DATA0 interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

ARU_NEW_DATA1_IRQ

: ARU_NEW_DATA1 interrupt. see bit 31.

ARU_ACC_ACK_IRQ

: ARU_ACC_ACK interrupt. see bit 31.

BRC_IRQ : BRC shared submodule interrupt. see bit 31.

AEI_IRQ : AEI_IRQ interrupt. see bit 31.

CMP_IRQ : CMP shared submodule interrupt. see bit 31.

SPE0_IRQ

: SPE0 shared submodule interrupt. see bit 31

SPE1_IRQ

: SPE1 shared submodule interrupt. see bit 31

SPE2_IRQ

: SPE2 shared submodule interrupt. see bit 31.

SPE3_IRQ : SPE3 shared submodule interrupt. see bit 31.

Reserved

Note: Read as zero, should be written as zero.

PSM0_CH0_IRQ : PSM0 shared submodule channel 0 interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

Note:

When set this bit represents one of the four interrupt sources FIFO_[x]_EMPTY,

FIFO_[x]_FULL, FIFO_[x]_LOWER_WM or FIFO_[x]_UPPER_WM

PSM0_CH1_IRQ : PSM0 shared submodule channel 1 interrupt.See bit 15.

PSM0_CH2_IRQ : PSM0 shared submodule channel 2 interrupt. See bit 15.

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Table 331. ICM_IRQG_0 field description (continued)

Description

PSM0_CH3_IRQ : PSM0 shared submodule channel 3 interrupt. See bit 15.

PSM0_CH4_IRQ

: PSM0 shared submodule channel 4 interrupt. See bit 15.

PSM0_CH5_IRQ : PSM0 shared submodule channel 5 interrupt. See bit 15.

PSM0_CH6_IRQ

: PSM0 shared submodule channel 6 interrupt. See bit 15.

PSM0_CH7_IRQ : PSM0 shared submodule channel 7 interrupt. See bit 15.

PSM1_CH0_IRQ

: PSM1 shared submodule channel 0 interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

Note: When set this bit represents one of the four interrupt sources FIFO_[x]_EMPTY,

FIFO_[x]_FULL, FIFO_[x]_LOWER_WM or FIFO_[x]_UPPER_WM

PSM1_CH1_IRQ : PSM1 shared submodule channel 1 interrupt. See bit 15.

PSM1_CH2_IRQ

: PSM1 shared submodule channel 2 interrupt. See bit 15.

PSM1_CH3_IRQ

: PSM1 shared submodule channel 3 interrupt. See bit 15.

PSM1_CH4_IRQ

: PSM1 shared submodule channel 4 interrupt. See bit 15.

PSM1_CH5_IRQ : PSM1 shared submodule channel 5 interrupt. See bit 15.

PSM1_CH6_IRQ : PSM1 shared submodule channel 6 interrupt. See bit 15.

PSM1_CH7_IRQ : PSM1 shared submodule channel 7 interrupt. See bit 15.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00

R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 332. ICM_IRQG_1 field description

Description

DPLL_DCGI_IRQ

: TRIGGER direction change detected.

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

DPLL_EDI_IRQ : DPLL enable/disable interrupt. see bit 31.

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Table 332. ICM_IRQG_1 field description (continued)

Description

DPLL_TINI_IRQ : TRIGGER minimum hold time (THMI) violation detected interrupt. see bit

31.

DPLL_TAXI_IRQ : TRIGGER maximum hold time (THMA) violation detected interrupt. see bit

31.

DPLL_SISI_IRQ : STATE inactive slope detected interrupt. see bit 31.

DPLL_TISI_IRQ

: TRIGGER inactive slope detected interrupt. see bit 31.

DPLL_MSI_IRQ : Missing STATE interrupt. see bit 31.

DPLL_MTI_IRQ

: Missing TRIGGER interrupt. see bit 31.

DPLL_SASI_IRQ : STATE active slope detected. see bit 31.

DPLL_TASI_IRQ

: TRIGGER active slope detected while NTI_CNT is zero. see bit 31.

DPLL_PWI_IRQ : Plausibility window (PVT) violation interrupt of TRIGGER. see bit 31.

DPLL_W2I_IRQ

: Write access to RAM region 2 interrupt. see bit 31.

DPLL_W1I_IRQ

: Write access to RAM region 1b or 1c interrupt. see bit 31.

DPLL_GL1I_IRQ

: Get of lock interrupt for SUB_INC1. see bit 31.

DPLL_LL1I_IRQ : Lost of lock interrupt for SUB_INC1. see bit 31.

DPLL_EI_IRQ : Error interrupt. see bit 31.

DPLL_GL2I_IRQ : Get of lock interrupt for SUB_INC2. see bit 31.

DPLL_LL2I_IRQ

: Lost of lock interrupt for SUB_INC2. see bit 31.

DPLL_TE0I_IRQ

: TRIGGER event interrupt 0. see bit 31.

DPLL_TE1I_IRQ

: TRIGGER event interrupt 1. see bit 31.

DPLL_TE2I_IRQ : TRIGGER event interrupt 2. see bit 31.

DPLL_TE3I_IRQ : TRIGGER event interrupt 3. see bit 31.

DPLL_TE4I_IRQ

: TRIGGER event interrupt 4. see bit 31.

DPLL_CDTI_IRQ

: DPLL calculated duration interrupt for trigger. see bit 31.

DPLL_CDSI_IRQ

: DPLL calculated duration interrupt for state. see bit 31.

DPLL_TORI_IRQ

: DPLL calculated duration interrupt for state. see bit 31.

DPLL_SORI_IRQ : DPLL calculated duration interrupt for state. see bit 31.

Reserved

Note: Read as zero, should be written as zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 333. ICM_IRQG_2 field description

Description

TIM0_CH0_IRQ

: TIM0 shared interrupt channel 0.

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

Note:

When set this bit represents one of the six interrupt sources NEWVALx_IRQ,

ECNTOFLx_IRQ, CNTOFLx_IRQ, GPRXOFLx_IRQ, GLITCHDETx_IRQ or TOx_IRQ.

TIM0_CH1_IRQ : TIM0 shared interrupt channel 1. see bit 31.

TIM0_CH2_IRQ : TIM0 shared interrupt channel 2. see bit 31.

TIM0_CH3_IRQ : TIM0 shared interrupt channel 3. see bit 31.

TIM0_CH4_IRQ

: TIM0 shared interrupt channel 4. see bit 31.

TIM0_CH5_IRQ

: TIM0 shared interrupt channel 5. see bit 31.

TIM0_CH6_IRQ

: TIM0 shared interrupt channel 6. see bit 31.

TIM0_CH7_IRQ : TIM0 shared interrupt channel 7. see bit 31.

TIM1_CH0_IRQ : TIM1 shared interrupt channel 0. see bit 31.

TIM1_CH1_IRQ

: TIM1 shared interrupt channel 1. see bit 31.

TIM1_CH2_IRQ

: TIM1 shared interrupt channel 2. see bit 31.

TIM1_CH3_IRQ

: TIM1 shared interrupt channel 3. see bit 31.

TIM1_CH4_IRQ

: TIM1 shared interrupt channel 4. see bit 31.

TIM1_CH5_IRQ : TIM1 shared interrupt channel 5. see bit 31.

TIM1_CH6_IRQ : TIM1 shared interrupt channel 6. see bit 31.

TIM1_CH7_IRQ

: TIM1 shared interrupt channel 7. see bit 31.

TIM2_CH0_IRQ

: TIM2 shared interrupt channel 0. see bit 31.

TIM2_CH1_IRQ

: TIM2 shared interrupt channel 1. see bit 31.

TIM2_CH2_IRQ

: TIM2 shared interrupt channel 2. see bit 31.

TIM2_CH3_IRQ : TIM2 shared interrupt channel 3. see bit 31.

TIM2_CH4_IRQ : TIM2 shared interrupt channel 4. see bit 31.

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Table 333. ICM_IRQG_2 field description (continued)

Description

TIM2_CH5_IRQ : TIM2 shared interrupt channel 5. see bit 31.

TIM2_CH6_IRQ

: TIM2 shared interrupt channel 6. see bit 31.

TIM2_CH7_IRQ : TIM2 shared interrupt channel 7. see bit 31.

TIM3_CH0_IRQ

: TIM3 shared interrupt channel 0. see bit 31.

TIM3_CH1_IRQ : TIM3 shared interrupt channel 1. see bit 31.

TIM3_CH2_IRQ

: TIM3 shared interrupt channel 2. see bit 31.

TIM3_CH3_IRQ : TIM3 shared interrupt channel 3. see bit 31.

TIM3_CH4_IRQ

: TIM3 shared interrupt channel 4. see bit 31.

TIM3_CH5_IRQ : TIM3 shared interrupt channel 5. see bit 31.

TIM3_CH6_IRQ

: TIM3 shared interrupt channel 6. see bit 31.

TIM3_CH7_IRQ : TIM3 shared interrupt channel 7. see bit 31.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00

R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 334. ICM_IRQG_3 field description

Description

TIM4_CH0_IRQ : TIM4 shared interrupt channel 0.

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

Note:

When set this bit represents one of the six interrupt sources NEWVALx_IRQ,

ECNTOFLx_IRQ, CNTOFLx_IRQ, GPRXOFLx_IRQ, GLITCHDETx_IRQ or TOx_IRQ.

TIM4_CH1_IRQ : TIM4 shared interrupt channel 1. see bit 31.

TIM4_CH2_IRQ : TIM4 shared interrupt channel 2. see bit 31.

TIM4_CH3_IRQ

: TIM4 shared interrupt channel 3. see bit 31.

TIM4_CH4_IRQ

: TIM4 shared interrupt channel 4. see bit 31.

TIM4_CH5_IRQ

: TIM4 shared interrupt channel 5. see bit 31.

TIM4_CH6_IRQ : TIM4 shared interrupt channel 6. see bit 31.

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Table 334. ICM_IRQG_3 field description (continued)

Description

TIM4_CH7_IRQ : TIM4 shared interrupt channel 7. see bit 31.

TIM5_CH0_IRQ

: TIM5 shared interrupt channel 0. see bit 31.

TIM5_CH1_IRQ : TIM5 shared interrupt channel 1. see bit 31.

TIM5_CH2_IRQ

: TIM5 shared interrupt channel 2. see bit 31.

TIM5_CH3_IRQ : TIM5 shared interrupt channel 3. see bit 31.

TIM5_CH4_IRQ

: TIM5 shared interrupt channel 4. see bit 31.

TIM5_CH5_IRQ : TIM5 shared interrupt channel 5. see bit 31.

TIM5_CH6_IRQ

: TIM5 shared interrupt channel 6. see bit 31.

TIM5_CH7_IRQ : TIM5 shared interrupt channel 7. see bit 31.

TIM6_CH0_IRQ

: TIM6 shared interrupt channel 0. see bit 31.

TIM6_CH1_IRQ : TIM6 shared interrupt channel 1. see bit 31.

TIM6_CH2_IRQ

: TIM6 shared interrupt channel 2. see bit 31.

TIM6_CH3_IRQ

: TIM6 shared interrupt channel 3. see bit 31.

TIM6_CH4_IRQ

: TIM6 shared interrupt channel 4. see bit 31.

TIM6_CH5_IRQ : TIM6 shared interrupt channel 5. see bit 31.

TIM6_CH6_IRQ : TIM6 shared interrupt channel 6. see bit 31.

TIM6_CH7_IRQ : TIM6 shared interrupt channel 7. see bit 31.

Reserved

Note: Read as zero, should be written as zero.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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RM0361

Table 335. ICM_IRQG_4 field description

Description

MCS0_CH0_IRQ : MCS0 channel 0 interrupt

0 = No interrupt occurred

1 = Interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

MCS0_CH1_IRQ

: MCS0 channel 1 interrupt. see bit 31.

MCS0_CH2_IRQ : MCS0 channel 2 interrupt. see bit 31.

MCS0_CH3_IRQ

: MCS0 channel 3 interrupt. see bit 31.

MCS0_CH4_IRQ : MCS0 channel 4 interrupt. see bit 31.

MCS0_CH5_IRQ

: MCS0 channel 5 interrupt. see bit 31.

MCS0_CH6_IRQ : MCS0 channel 6 interrupt. see bit 31.

MCS0_CH7_IRQ

: MCS0 channel 7 interrupt. see bit 31.

MCS1_CH0_IRQ : MCS1 channel 0 interrupt. see bit 31.

MCS1_CH1_IRQ

: MCS1 channel 1 interrupt. see bit 31.

MCS1_CH2_IRQ

: MCS1 channel 2 interrupt. see bit 31.

MCS1_CH3_IRQ

: MCS1 channel 3 interrupt. see bit 31.

MCS1_CH4_IRQ : MCS1 channel 4 interrupt. see bit 31.

MCS1_CH5_IRQ : MCS1 channel 5 interrupt. see bit 31.

MCS1_CH6_IRQ

: MCS1 channel 6 interrupt. see bit 31.

MCS1_CH7_IRQ

: MCS1 channel 7 interrupt. see bit 31.

MCS2_CH0_IRQ

: MCS2 channel 0 interrupt. see bit 31.

MCS2_CH1_IRQ

: MCS2 channel 1 interrupt. see bit 31.

MCS2_CH2_IRQ : MCS2 channel 2 interrupt. see bit 31.

MCS2_CH3_IRQ : MCS2 channel 3 interrupt. see bit 31.

MCS2_CH4_IRQ

: MCS2 channel 4 interrupt. see bit 31.

MCS2_CH5_IRQ

: MCS2 channel 5 interrupt. see bit 31.

MCS2_CH6_IRQ

: MCS2 channel 6 interrupt. see bit 31.

MCS2_CH7_IRQ

: MCS2 channel 7 interrupt. see bit 31.

MCS3_CH0_IRQ : MCS3 channel 0 interrupt. see bit 31.

MCS3_CH1_IRQ : MCS3 channel 1 interrupt. see bit 31.

MCS3_CH2_IRQ

: MCS3 channel 2 interrupt. see bit 31.

MCS3_CH3_IRQ

: MCS3 channel 3 interrupt. see bit 31.

MCS3_CH4_IRQ

: MCS3 channel 4 interrupt. see bit 31.

MCS3_CH5_IRQ

: MCS3 channel 5 interrupt. see bit 31.

MCS3_CH6_IRQ : MCS3 channel 6 interrupt. see bit 31.

MCS3_CH7_IRQ : MCS3 channel 7 interrupt. see bit 31.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit Reserved

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 336. ICM_IRQG_5 field description

Description

MCS4_CH0_IRQ

: MCS4 channel 0 interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

MCS4_CH1_IRQ

: MCS4 channel 1 interrupt. see bit 31.

MCS4_CH2_IRQ

: MCS4 channel 2 interrupt. see bit 31.

MCS4_CH3_IRQ : MCS4 channel 3 interrupt. see bit 31.

MCS4_CH4_IRQ : MCS4 channel 4 interrupt. see bit 31.

MCS4_CH5_IRQ : MCS4 channel 5 interrupt. see bit 31.

MCS4_CH6_IRQ

: MCS4 channel 6 interrupt. see bit 31.

MCS4_CH7_IRQ

: MCS4 channel 7 interrupt. see bit 31.

MCS5_CH0_IRQ

: MCS5 channel 0 interrupt. see bit 31.

MCS5_CH1_IRQ : MCS5 channel 1 interrupt. see bit 31.

MCS5_CH2_IRQ : MCS5 channel 2 interrupt. see bit 31.

MCS5_CH3_IRQ : MCS5 channel 3 interrupt. see bit 31.

MCS5_CH4_IRQ

: MCS5 channel 4 interrupt. see bit 31.

MCS5_CH5_IRQ

: MCS5 channel 5 interrupt. see bit 31.

MCS5_CH6_IRQ

: MCS5 channel 6 interrupt. see bit 31.

MCS5_CH7_IRQ : MCS5 channel 7 interrupt. see bit 31.

MCS6_CH0_IRQ : MCS6 channel 0 interrupt. see bit 31.

MCS6_CH1_IRQ : MCS6 channel 1 interrupt. see bit 31.

MCS6_CH2_IRQ

: MCS6 channel 2 interrupt. see bit 31.

MCS6_CH3_IRQ

: MCS6 channel 3 interrupt. see bit 31.

MCS6_CH4_IRQ

: MCS6 channel 4 interrupt. see bit 31.

MCS6_CH5_IRQ : MCS6 channel 5 interrupt. see bit 31.

MCS6_CH6_IRQ : MCS6 channel 6 interrupt. see bit 31.

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Table 336. ICM_IRQG_5 field description (continued)

Description

MCS6_CH7_IRQ : MCS6 channel 7 interrupt. see bit 31.

Reserved

Note: Read as zero, should be written as zero.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 337. ICM_IRQG_6 field description

Description

TOM0_CH0_IRQ

: TOM0 channel 0 shared interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

TOM0_CH1_IRQ : TOM0 channel 1 shared interrupt. see bit 31.

TOM0_CH2_IRQ

: TOM0 channel 2 shared interrupt. see bit 31.

TOM0_CH3_IRQ

: TOM0 channel 3 shared interrupt. see bit 31.

TOM0_CH4_IRQ

: TOM0 channel 4 shared interrupt. see bit 31.

TOM0_CH5_IRQ : TOM0 channel 5 shared interrupt. see bit 31.

TOM0_CH6_IRQ : TOM0 channel 6 shared interrupt. see bit 31.

TOM0_CH7_IRQ : TOM0 channel 7 shared interrupt. see bit 31.

TOM0_CH8_IRQ

: TOM0 channel 8 shared interrupt. see bit 31.

TOM0_CH9_IRQ

: TOM0 channel 9 shared interrupt. see bit 31.

TOM0_CH10_IRQ

: TOM0 channel 10 shared interrupt. see bit 31.

TOM0_CH11_IRQ : TOM0 channel 11 shared interrupt. see bit 31.

TOM0_CH12_IRQ : TOM0 channel 12 shared interrupt. see bit 31.

TOM0_CH13_IRQ

: TOM0 channel 13 shared interrupt. see bit 31.

TOM0_CH14_IRQ

: TOM0 channel 14 shared interrupt. see bit 31.

TOM0_CH15_IRQ

: TOM0 channel 15 shared interrupt. see bit 31.

TOM1_CH0_IRQ

: TOM1 channel 0 shared interrupt. see bit 31.

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Table 337. ICM_IRQG_6 field description (continued)

Description

TOM1_CH1_IRQ : TOM1 channel 1 shared interrupt. see bit 31.

TOM1_CH2_IRQ

: TOM1 channel 2 shared interrupt. see bit 31.

TOM1_CH3_IRQ : TOM1 channel 3 shared interrupt. see bit 31.

TOM1_CH4_IRQ

: TOM1 channel 4 shared interrupt. see bit 31.

TOM1_CH5_IRQ : TOM1 channel 5 shared interrupt. see bit 31.

TOM1_CH6_IRQ

: TOM1 channel 6 shared interrupt. see bit 31.

TOM1_CH7_IRQ : TOM1 channel 7 shared interrupt. see bit 31.

TOM1_CH8_IRQ

: TOM1 channel 8 shared interrupt. see bit 31.

TOM1_CH9_IRQ : TOM1 channel 9 shared interrupt. see bit 31.

TOM1_CH10_IRQ

: TOM1 channel 10 shared interrupt. see bit 31.

TOM1_CH11_IRQ : TOM1 channel 11 shared interrupt. see bit 31.

TOM1_CH12_IRQ

: TOM1 channel 12 shared interrupt. see bit 31.

TOM1_CH13_IRQ

: TOM1 channel 13 shared interrupt. see bit 31.

TOM1_CH14_IRQ

: TOM1 channel 14 shared interrupt. see bit 31.

TOM1_CH15_IRQ : TOM1 channel 15 shared interrupt. see bit 31.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 338. ICM_IRQG_7 field description

Description

TOM2_CH0_IRQ

: TOM2 channel 0 shared interrupt

0 = No interrupt occurred

1 = Interrupt was raised by the corresponding submodule

Note: This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

TOM2_CH1_IRQ

: TOM2 channel 1 shared interrupt. see bit 31.

TOM2_CH2_IRQ

: TOM2 channel 2 shared interrupt. see bit 31.

TOM2_CH3_IRQ : TOM2 channel 3 shared interrupt. see bit 31.

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Table 338. ICM_IRQG_7 field description (continued)

Description

TOM2_CH4_IRQ : TOM2 channel 4 shared interrupt. see bit 31.

TOM2_CH5_IRQ

: TOM2 channel 5 shared interrupt. see bit 31.

TOM2_CH6_IRQ : TOM2 channel 6 shared interrupt. see bit 31.

TOM2_CH7_IRQ

: TOM2 channel 7 shared interrupt. see bit 31.

TOM2_CH8_IRQ : TOM2 channel 8 shared interrupt. see bit 31.

TOM2_CH9_IRQ

: TOM2 channel 9 shared interrupt. see bit 31.

TOM2_CH10_IRQ : TOM2 channel 10 shared interrupt. see bit 31.

TOM2_CH11_IRQ

: TOM2 channel 11 shared interrupt. see bit 31.

TOM2_CH12_IRQ : TOM2 channel 12 shared interrupt. see bit 31.

TOM2_CH13_IRQ

: TOM2 channel 13 shared interrupt. see bit 31.

TOM2_CH14_IRQ : TOM2 channel 14 shared interrupt. see bit 31.

TOM2_CH15_IRQ

: TOM2 channel 15 shared interrupt. see bit 31.

TOM3_CH0_IRQ

: TOM3 channel 0 shared interrupt. see bit 31.

TOM3_CH1_IRQ

: TOM3 channel 1 shared interrupt. see bit 31.

TOM3_CH2_IRQ : TOM3 channel 2 shared interrupt. see bit 31.

TOM3_CH3_IRQ : TOM3 channel 3 shared interrupt. see bit 31.

TOM3_CH4_IRQ : TOM3 channel 4 shared interrupt. see bit 31.

TOM3_CH5_IRQ

: TOM3 channel 5 shared interrupt. see bit 31.

TOM3_CH6_IRQ

: TOM3 channel 6 shared interrupt. see bit 31.

TOM3_CH7_IRQ

: TOM3 channel 7 shared interrupt. see bit 31.

TOM3_CH8_IRQ : TOM3 channel 8 shared interrupt. see bit 31.

TOM3_CH9_IRQ : TOM3 channel 9 shared interrupt. see bit 31.

TOM3_CH10_IRQ : TOM3 channel 10 shared interrupt. see bit 31.

TOM3_CH11_IRQ

: TOM3 channel 11 shared interrupt. see bit 31.

TOM3_CH12_IRQ

: TOM3 channel 12 shared interrupt. see bit 31.

TOM3_CH13_IRQ

: TOM3 channel 13 shared interrupt. see bit 31.

TOM1_CH14_IRQ : TOM3 channel 14 shared interrupt. see bit 31.

TOM3_CH15_IRQ : TOM3 channel 15 shared interrupt. see bit 31.

RM0361

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RM0361 Interrupt Concentrator Module (ICM)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 339. ICM_IRQG_8 field description

Description

TOM4_CH0_IRQ : TOM4 channel 0 shared interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

TOM4_CH1_IRQ

: TOM4 channel 1 shared interrupt. see bit 31.

TOM4_CH2_IRQ : TOM4 channel 2 shared interrupt. see bit 31.

TOM4_CH3_IRQ : TOM4 channel 3 shared interrupt. see bit 31.

TOM4_CH4_IRQ : TOM4 channel 4 shared interrupt. see bit 31.

TOM4_CH5_IRQ

: TOM4 channel 5 shared interrupt. see bit 31.

TOM4_CH6_IRQ

: TOM4 channel 6 shared interrupt. see bit 31.

TOM4_CH7_IRQ

: TOM4 channel 7 shared interrupt. see bit 31.

TOM4_CH8_IRQ : TOM4 channel 8 shared interrupt. see bit 31.

TOM4_CH9_IRQ : TOM4 channel 9 shared interrupt. see bit 31.

TOM4_CH10_IRQ : TOM4 channel 10 shared interrupt. see bit 31.

TOM4_CH11_IRQ

: TOM4 channel 11 shared interrupt. see bit 31.

TOM4_CH12_IRQ

: TOM4 channel 12 shared interrupt. see bit 31.

TOM4_CH13_IRQ

: TOM4 channel 13 shared interrupt. see bit 31.

TOM4_CH14_IRQ : TOM4 channel 14 shared interrupt. see bit 31.

TOM4_CH15_IRQ : TOM4 channel 15 shared interrupt. see bit 31.

TOM5_CH0_IRQ

: TOM5 channel 0 shared interrupt. see bit 31.

TOM5_CH1_IRQ

: TOM5 channel 1 shared interrupt. see bit 31.

TOM5_CH2_IRQ

: TOM5 channel 2 shared interrupt. see bit 31.

TOM5_CH3_IRQ

: TOM5 channel 3 shared interrupt. see bit 31.

TOM5_CH4_IRQ : TOM5 channel 4 shared interrupt. see bit 31.

TOM5_CH5_IRQ : TOM5 channel 5 shared interrupt. see bit 31.

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Table 339. ICM_IRQG_8 field description (continued)

Description

TOM5_CH6_IRQ : TOM5 channel 6 shared interrupt. see bit 31.

TOM5_CH7_IRQ

: TOM5 channel 7 shared interrupt. see bit 31.

TOM5_CH8_IRQ : TOM5 channel 8 shared interrupt. see bit 31.

TOM5_CH9_IRQ

: TOM5 channel 9 shared interrupt. see bit 31.

TOM5_CH10_IRQ : TOM5 channel 10 shared interrupt. see bit 31.

TOM5_CH11_IRQ

: TOM3 channel 11 shared interrupt. see bit 31.

TOM5_CH12_IRQ : TOM5 channel 12 shared interrupt. see bit 31.

TOM5_CH13_IRQ

: TOM5 channel 13 shared interrupt. see bit 31.

TOM5_CH14_IRQ : TOM5 channel 14 shared interrupt. see bit 31.

TOM5_CH15_IRQ

: TOM5 channel 15 shared interrupt. see bit 31.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 340. ICM_IRQG_9 field description

Description

ATOM0_CH0_IRQ : ATOM0 channel 0 shared interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

ATOM0_CH1_IRQ

: ATOM0 channel 1 shared interrupt. see bit 31.

ATOM0_CH2_IRQ : ATOM0 channel 2 shared interrupt. see bit 31.

ATOM0_CH3_IRQ : ATOM0 channel 3 shared interrupt. see bit 31.

ATOM0_CH4_IRQ : ATOM0 channel 4 shared interrupt. see bit 31.

ATOM0_CH5_IRQ

: ATOM0 channel 5 shared interrupt. see bit 31.

ATOM0_CH6_IRQ

: ATOM0 channel 6 shared interrupt. see bit 31.

ATOM0_CH7_IRQ

: ATOM0 channel 7 shared interrupt. see bit 31.

ATOM1_CH0_IRQ : ATOM1 channel 0 shared interrupt. see bit 31.

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Table 340. ICM_IRQG_9 field description (continued)

Description

ATOM1_CH1_IRQ : ATOM1 channel 1 shared interrupt. see bit 31.

ATOM1_CH2_IRQ

: ATOM1 channel 2 shared interrupt. see bit 31.

ATOM1_CH3_IRQ : ATOM1 channel 3 shared interrupt. see bit 31.

ATOM1_CH4_IRQ

: ATOM1 channel 4 shared interrupt. see bit 31.

ATOM1_CH5_IRQ : ATOM1 channel 5 shared interrupt. see bit 31.

ATOM1_CH6_IRQ

: ATOM1 channel 6 shared interrupt. see bit 31.

ATOM1_CH7_IRQ : ATOM1 channel 7 shared interrupt. see bit 31.

ATOM2_CH0_IRQ

: ATOM2 channel 0 shared interrupt. see bit 31.

ATOM2_CH1_IRQ : ATOM2 channel 1 shared interrupt. see bit 31.

ATOM2_CH2_IRQ

: ATOM2 channel 2 shared interrupt. see bit 31.

ATOM2_CH3_IRQ : ATOM2 channel 3 shared interrupt. see bit 31.

ATOM2_CH4_IRQ

: ATOM2 channel 4 shared interrupt. see bit 31.

ATOM2_CH5_IRQ

: ATOM2 channel 5 shared interrupt. see bit 31.

ATOM2_CH6_IRQ

: ATOM2 channel 6 shared interrupt. see bit 31.

ATOM2_CH7_IRQ : ATOM2 channel 7 shared interrupt. see bit 31.

ATOM3_CH0_IRQ : ATOM3 channel 0 shared interrupt. see bit 31.

ATOM3_CH1_IRQ : ATOM3 channel 1 shared interrupt. see bit 31.

ATOM3_CH2_IRQ

: ATOM3 channel 2 shared interrupt. see bit 31.

ATOM3_CH3_IRQ

: ATOM3 channel 3 shared interrupt. see bit 31.

ATOM3_CH4_IRQ

: ATOM3 channel 4 shared interrupt. see bit 31.

ATOM3_CH5_IRQ : ATOM3 channel 5 shared interrupt. see bit 31.

ATOM3_CH6_IRQ : ATOM3 channel 6 shared interrupt. see bit 31.

ATOM3_CH7_IRQ : ATOM3 channel 7 shared interrupt. see bit 31.

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 341. ICM_IRQG_10 field description

Description

ATOM4_CH0_IRQ : ATOM4 channel 0 shared interrupt

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

ATOM4_CH1_IRQ

: ATOM4 channel 1 shared interrupt. see bit 31.

ATOM4_CH2_IRQ : ATOM4 channel 2 shared interrupt. see bit 31.

ATOM4_CH3_IRQ

: ATOM4 channel 3 shared interrupt. see bit 31.

ATOM4_CH4_IRQ : ATOM4 channel 4 shared interrupt. see bit 31.

ATOM4_CH5_IRQ

: ATOM4 channel 5 shared interrupt. see bit 31.

ATOM4_CH6_IRQ : ATOM4 channel 6 shared interrupt. see bit 31.

ATOM4_CH7_IRQ

: ATOM4 channel 7 shared interrupt. see bit 31.

ATOM5_CH0_IRQ : ATOM5 channel 0 shared interrupt. see bit 31.

ATOM5_CH1_IRQ

: ATOM5 channel 1 shared interrupt. see bit 31.

ATOM5_CH2_IRQ

: ATOM5 channel 2 shared interrupt. see bit 31.

ATOM5_CH3_IRQ

: ATOM5 channel 3 shared interrupt. see bit 31.

ATOM5_CH4_IRQ : ATOM5 channel 4 shared interrupt. see bit 31.

ATOM5_CH5_IRQ : ATOM5 channel 5 shared interrupt. see bit 31.

ATOM5_CH6_IRQ

: ATOM5 channel 6 shared interrupt. see bit 31.

ATOM5_CH7_IRQ

: ATOM5 channel 7 shared interrupt. see bit 31.

ATOM6_CH0_IRQ

: ATOM6 channel 0 shared interrupt. see bit 31.

ATOM6_CH1_IRQ

: ATOM6 channel 1 shared interrupt. see bit 31.

ATOM6_CH2_IRQ : ATOM6 channel 2 shared interrupt. see bit 31.

ATOM6_CH3_IRQ : ATOM6 channel 3 shared interrupt. see bit 31.

ATOM6_CH4_IRQ

: ATOM6 channel 4 shared interrupt. see bit 31.

ATOM6_CH5_IRQ

: ATOM6 channel 5 shared interrupt. see bit 31.

ATOM6_CH6_IRQ

: ATOM6 channel 6 shared interrupt. see bit 31.

ATOM6_CH7_IRQ

: ATOM6 channel 7 shared interrupt. see bit 31.

ATOM7_CH0_IRQ : ATOM7 channel 0 shared interrupt. see bit 31.

ATOM7_CH1_IRQ : ATOM7 channel 1 shared interrupt. see bit 31.

ATOM7_CH2_IRQ

: ATOM7 channel 2 shared interrupt. see bit 31.

ATOM7_CH3_IRQ

: ATOM7 channel 3 shared interrupt. see bit 31.

ATOM7_CH4_IRQ

: ATOM7 channel 4 shared interrupt. see bit 31.

ATOM7_CH5_IRQ

: ATOM7 channel 5 shared interrupt. see bit 31.

ATOM7_CH6_IRQ : ATOM7 channel 6 shared interrupt. see bit 31.

ATOM7_CH7_IRQ : ATOM7 channel 7 shared interrupt. see bit 31.

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RM0361 Interrupt Concentrator Module (ICM)

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 342. ICM_IRQG_11 field description

Description

ATOM8_CH0_IRQ : ATOM8 channel 0 shared interrupt

0 = No interrupt occurred

1 = Interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the interrupt is enabled in the interrupt enable register of the corresponding submodule.

ATOM8_CH1_IRQ : ATOM8 channel 1 shared interrupt. see bit 31.

ATOM8_CH2_IRQ : ATOM8 channel 2 shared interrupt. see bit 31.

ATOM8_CH3_IRQ

: ATOM8 channel 3 shared interrupt. see bit 31.

ATOM8_CH4_IRQ

: ATOM8 channel 4 shared interrupt. see bit 31.

ATOM8_CH5_IRQ

: ATOM8 channel 5 shared interrupt. see bit 31.

ATOM8_CH6_IRQ : ATOM8 channel 6 shared interrupt. see bit 31.

ATOM8_CH7_IRQ : ATOM8 channel 7 shared interrupt. see bit 31.

ATOM9_CH0_IRQ : ATOM9 channel 0 shared interrupt. see bit 31.

ATOM9_CH1_IRQ

: ATOM9 channel 1 shared interrupt. see bit 31.

ATOM9_CH2_IRQ

: ATOM9 channel 2 shared interrupt. see bit 31.

ATOM9_CH3_IRQ

: ATOM9 channel 3 shared interrupt. see bit 31.

ATOM9_CH4_IRQ : ATOM9 channel 4 shared interrupt. see bit 31.

ATOM9_CH5_IRQ : ATOM9 channel 5 shared interrupt. see bit 31.

ATOM9_CH6_IRQ : ATOM9 channel 6 shared interrupt. see bit 31.

ATOM9_CH7_IRQ

: ATOM9 channel 7 shared interrupt. see bit 31.

ATOM10_CH0_IRQ

: ATOM10 channel 0 shared interrupt. see bit 31.

ATOM10_CH1_IRQ

: ATOM10 channel 1 shared interrupt. see bit 31.

ATOM10_CH2_IRQ : ATOM10 channel 2 shared interrupt. see bit 31.

ATOM10_CH3_IRQ : ATOM10 channel 3 shared interrupt. see bit 31.

ATOM010_CH4_IRQ : ATOM10 channel 4 shared interrupt. see bit 31.

ATOM10_CH5_IRQ

: ATOM10 channel 5 shared interrupt. see bit 31.

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Table 342. ICM_IRQG_11 field description (continued)

Description

ATOM10_CH6_IRQ : ATOM10 channel 6 shared interrupt. see bit 31.

ATOM10_CH7_IRQ

: ATOM10 channel 7 shared interrupt. see bit 31.

ATOM11_CH0_IRQ : ATOM11 channel 0 shared interrupt. see bit 31.

ATOM11_CH1_IRQ

: ATOM11 channel 1 shared interrupt. see bit 31.

ATOM11_CH2_IRQ : ATOM11 channel 2 shared interrupt. see bit 31.

ATOM11_CH3_IRQ

: ATOM11 channel 3 shared interrupt. see bit 31.

ATOM11_CH4_IRQ : ATOM11 channel 4 shared interrupt. see bit 31.

ATOM11_CH5_IRQ

: ATOM11 channel 5 shared interrupt. see bit 31.

ATOM11_CH6_IRQ : ATOM11 channel 6 shared interrupt. see bit 31.

ATOM11_CH7_IRQ

: ATOM11 channel 7 shared interrupt. see bit 31.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00

R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 343. ICM_IRQG_MEI field description

Description

GTM_EIRQ

: GTM Error interrupt request

0 = no interrupt occurred

1 = interrupt was raised by the corresponding submodule

Note: This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

BRC_EIRQ

: BRC error interrupt. see bit 31.

FIFO0_EIRQ

: FIFO0 error interrupt. see bit 31.

FIFO1_EIRQ : FIFO1 error interrupt. see bit 31.

TIM0_EIRQ : TIM0 error interrupt. see bit 31.

TIM1_EIRQ : TIM1error interrupt. see bit 31.

TIM2_EIRQ

: TIM2 error interrupt. see bit 31.

TIM3_EIRQ

: TIM3 error interrupt. see bit 31.

TIM4_EIRQ

: TIM4 error interrupt. see bit 31.

TIM5_EIRQ : TIM5 error interrupt. see bit 31.

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Bit

Interrupt Concentrator Module (ICM)

Table 343. ICM_IRQG_MEI field description (continued)

Description

TIM6_EIRQ : TIM6 error interrupt. see bit 31.

Reserved

: Read as zero, should be written as zero.

Note: Read as zero, should be written as zero

MCS0_EIRQ

: MCS0 error interrupt. see bit 31.

MCS1_EIRQ : MCS1 error interrupt. see bit 31.

MCS2_EIRQ

: MCS2 error interrupt. see bit 31.

MCS3_EIRQ : MCS3 error interrupt. see bit 31.

MCS4_EIRQ

: MCS4 error interrupt. see bit 31.

MCS5_EIRQ : MCS5 error interrupt. see bit 31.

MCS6_EIRQ

: MCS6 error interrupt. see bit 31.

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

SPE0_EIRQ : SPE0 error interrupt. see bit 31.

SPE1_EIRQ : SPE1 error interrupt. see bit 31.

SPE2_EIRQ : SPE2 error interrupt. see bit 31.

SPE3_EIRQ

: SPE3 error interrupt. see bit 31.

CMP_EIRQ

: CMP error interrupt. see bit 31.

DPLL_EIRQ

: DPLL error interrupt. see bit 31.

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

0x0000

R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Bit

RM0361

Table 344. ICM_IRQG_CEI0 field description

Description

FIFO0_CH0_EIRQ : FIFO0 channel 0 error interrupt

0 = no interrupt occurred

1 = error interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

FIFO0_CH1_EIRQ

: FIFO0 channel 1 shared interrupt. see bit 31.

FIFO0_CH2_EIRQ : FIFO0 channel 2 shared interrupt. see bit 31.

FIFO0_CH3_EIRQ

: FIFO0 channel 3 shared interrupt. see bit 31.

FIFO0_CH4_EIRQ : FIFO0 channel 4 shared interrupt. see bit 31.

FIFO0_CH5_EIRQ

: FIFO0 channel 5 shared interrupt. see bit 31.

FIFO0_CH6_EIRQ : FIFO0 channel 6 shared interrupt. see bit 31.

FIFO0_CH7_EIRQ

: FIFO0 channel 7 shared interrupt. see bit 31.

FIFO1_CH0_EIRQ

: FIFO1 channel 0 shared interrupt. see bit 31.

FIFO1_CH1_EIRQ

: FIFO1 channel 1 shared interrupt. see bit 31.

FIFO1_CH2_EIRQ : FIFO1 channel 2 shared interrupt. see bit 31.

FIFO1_CH3_EIRQ : FIFO1 channel 3 shared interrupt. see bit 31.

FIFO1_CH4_EIRQ

: FIFO1 channel 4 shared interrupt. see bit 31.

FIFO1_CH5_EIRQ

: FIFO1 channel 5 shared interrupt. see bit 31.

FIFO1_CH6_EIRQ

: FIFO1 channel 6 shared interrupt. see bit 31.

FIFO1_CH7_EIRQ

: FIFO1 channel 7 shared interrupt. see bit 31.

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 345. ICM_IRQG_CEI1 field description

Description

TIM0_CH0_EIRQ

: TIM0 channel 0 error interrupt

0 = no error interrupt occurred

1 = error interrupt was raised by the corresponding submodule

Note: This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

TIM0_CH1_EIRQ : TIM0 channel 1 error interrupt. see bit 31.

TIM0_CH2_EIRQ

: TIM0 channel 2 error interrupt. see bit 31.

TIM0_CH3_EIRQ

: TIM0 channel 3 error interrupt. see bit 31.

TIM0_CH4_EIRQ

: TIM0 channel 4 error interrupt. see bit 31.

TIM0_CH5_EIRQ : TIM0 channel 5 error interrupt. see bit 31.

TIM0_CH6_EIRQ : TIM0 channel 6 error interrupt. see bit 31.

TIM0_CH7_EIRQ : TIM0 channel 7 error interrupt. see bit 31.

TIM1_CH0_EIRQ

: TIM1 channel 0 error interrupt. see bit 31.

TIM1_CH1_EIRQ

: TIM1 channel 1 error interrupt. see bit 31.

TIM1_CH2_EIRQ

: TIM1 channel 2 error interrupt. see bit 31.

TIM1_CH3_EIRQ : TIM1 channel 3 error interrupt. see bit 31.

TIM1_CH4_EIRQ : TIM1 channel 4 error interrupt. see bit 31.

TIM1_CH5_EIRQ : TIM1 channel 5 error interrupt. see bit 31.

TIM1_CH6_EIRQ

: TIM1 channel 6 error interrupt. see bit 31.

TIM1_CH7_EIRQ

: TIM1 channel 7 error interrupt. see bit 31.

TIM2_CH0_EIRQ

: TIM2 channel 0 error interrupt. see bit 31.

TIM2_CH1_EIRQ : TIM2 channel 1 error interrupt. see bit 31.

TIM2_CH2_EIRQ : TIM2 channel 2 error interrupt. see bit 31.

TIM2_CH3_EIRQ

: TIM2 channel 3 error interrupt. see bit 31.

TIM2_CH4_EIRQ

: TIM2 channel 4 error interrupt. see bit 31.

TIM2_CH5_EIRQ

: TIM2 channel 5 error interrupt. see bit 31.

TIM2_CH6_EIRQ

: TIM2 channel 6 error interrupt. see bit 31.

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Table 345. ICM_IRQG_CEI1 field description (continued)

Description

TIM2_CH7_EIRQ : TIM2 channel 7 error interrupt. see bit 31.

TIM3_CH0_EIRQ

: TIM3 channel 0 error interrupt. see bit 31.

TIM3_CH1_EIRQ : TIM3 channel 1 error interrupt. see bit 31.

TIM3_CH2_EIRQ

: TIM3 channel 2 error interrupt. see bit 31.

TIM3_CH3_EIRQ : TIM3 channel 3 error interrupt. see bit 31.

TIM3_CH4_EIRQ

: TIM3 channel 4 error interrupt. see bit 31.

TIM3_CH5_EIRQ : TIM3 channel 5 error interrupt. see bit 31.

TIM3_CH6_EIRQ

: TIM3 channel 6 error interrupt. see bit 31.

TIM3_CH7_EIRQ : TIM3 channel 7 error interrupt. see bit 31.

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00

R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 346. ICM_IRQG_CEI2 field description

Description

TIM4_CH0_EIRQ : TIM4 channel 0 error interrupt

0 = no error interrupt occurred

1 = error interrupt was raised by the corresponding submodule

Note:

This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

TIM4_CH1_EIRQ : TIM4 channel 1 error interrupt. see bit 31.

TIM4_CH2_EIRQ : TIM4 channel 2 error interrupt. see bit 31.

TIM4_CH3_EIRQ

: TIM4 channel 3 error interrupt. see bit 31.

TIM4_CH4_EIRQ

: TIM4 channel 4 error interrupt. see bit 31.

TIM4_CH5_EIRQ

: TIM4 channel 5 error interrupt. see bit 31.

TIM4_CH6_EIRQ : TIM4 channel 6 error interrupt. see bit 31.

TIM4_CH7_EIRQ : TIM4 channel 7 error interrupt. see bit 31.

TIM5_CH0_EIRQ : TIM5 channel 0 error interrupt. see bit 31.

TIM5_CH1_EIRQ

: TIM5 channel 1 error interrupt. see bit 31.

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Table 346. ICM_IRQG_CEI2 field description (continued)

Description

TIM5_CH2_EIRQ : TIM5 channel 2 error interrupt. see bit 31.

TIM5_CH3_EIRQ

: TIM5 channel 3 error interrupt. see bit 31.

TIM5_CH4_EIRQ : TIM5 channel 4 error interrupt. see bit 31.

TIM5_CH5_EIRQ

: TIM5 channel 5 error interrupt. see bit 31.

TIM5_CH6_EIRQ : TIM5 channel 6 error interrupt. see bit 31.

TIM5_CH7_EIRQ

: TIM5 channel 7 error interrupt. see bit 31.

TIM6_CH0_EIRQ : TIM6 channel 0 error interrupt. see bit 31.

TIM6_CH1_EIRQ

: TIM6 channel 1 error interrupt. see bit 31.

TIM6_CH2_EIRQ : TIM6 channel 2 error interrupt. see bit 31.

TIM6_CH3_EIRQ

: TIM6 channel 3 error interrupt. see bit 31.

TIM6_CH4_EIRQ : TIM6 channel 4 error interrupt. see bit 31.

TIM6_CH5_EIRQ

: TIM6 channel 5 error interrupt. see bit 31.

TIM6_CH6_EIRQ

: TIM6 channel 6 error interrupt. see bit 31.

TIM6_CH7_EIRQ

: TIM6 channel 7 error interrupt. see bit 31.

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 347. ICM_IRQG_CEI3 field description

Description

MCS0_CH0_EIRQ

: MCS0 channel 0 error interrupt

0 = no error interrupt occurred

1 = error interrupt was raised by the corresponding submodule

Note: This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

MCS0_CH1_EIRQ : MCS0 channel 1 error interrupt. see bit 31.

MCS0_CH2_EIRQ

: MCS0 channel 2 error interrupt. see bit 31.

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Table 347. ICM_IRQG_CEI3 field description (continued)

Description

MCS0_CH3_EIRQ : MCS0 channel 3 error interrupt. see bit 31.

MCS0_CH4_EIRQ

: MCS0 channel 4 error interrupt. see bit 31.

MCS0_CH5_EIRQ : MCS0 channel 5 error interrupt. see bit 31.

MCS0_CH6_EIRQ

: MCS0 channel 6 error interrupt. see bit 31.

MCS0_CH7_EIRQ : MCS0 channel 7 error interrupt. see bit 31.

MCS1_CH0_EIRQ

: MCS1 channel 0 error interrupt. see bit 31.

MCS1_CH1_EIRQ : MCS1 channel 1 error interrupt. see bit 31.

MCS1_CH2_EIRQ

: MCS1 channel 2 error interrupt. see bit 31.

MCS1_CH3_EIRQ : MCS1 channel 3 error interrupt. see bit 31.

MCS1_CH4_EIRQ

: MCS1 channel 4 error interrupt. see bit 31.

MCS1_CH5_EIRQ : MCS1 channel 5 error interrupt. see bit 31.

MCS1_CH6_EIRQ

: MCS1 channel 6 error interrupt. see bit 31.

MCS1_CH7_EIRQ

: MCS1 channel 7 error interrupt. see bit 31.

MCS2_CH0_EIRQ

: MCS2 channel 0 error interrupt. see bit 31.

MCS2_CH1_EIRQ : MCS2 channel 1 error interrupt. see bit 31.

MCS2_CH2_EIRQ : MCS2 channel 2 error interrupt. see bit 31.

MCS2_CH3_EIRQ : MCS2 channel 3 error interrupt. see bit 31.

MCS2_CH4_EIRQ

: MCS2 channel 4 error interrupt. see bit 31.

MCS2_CH5_EIRQ

: MCS2 channel 5 error interrupt. see bit 31.

MCS2_CH6_EIRQ

: MCS2 channel 6 error interrupt. see bit 31.

MCS2_CH7_EIRQ : MCS2 channel 7 error interrupt. see bit 31.

MCS3_CH0_EIRQ : MCS3 channel 0 error interrupt. see bit 31.

MCS3_CH1_EIRQ : MCS3 channel 1 error interrupt. see bit 31.

MCS3_CH2_EIRQ

: MCS3 channel 2 error interrupt. see bit 31.

MCS3_CH3_EIRQ

: MCS3 channel 3 error interrupt. see bit 31.

MCS3_CH4_EIRQ

: MCS3 channel 4 error interrupt. see bit 31.

MCS3_CH5_EIRQ : MCS3 channel 5 error interrupt. see bit 31.

MCS3_CH6_EIRQ : MCS3 channel 6 error interrupt. see bit 31.

MCS3_CH7_EIRQ

: MCS3 channel 7 error interrupt. see bit 31.

RM0361

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00

R R R R R R R R R R R R R R R R R R R R R R R R

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 348. ICM_IRQG_CEI4 field description

Description

MCS4_CH0_EIRQ

: MCS0 channel 0 error interrupt

0 = No error interrupt occurred

1 = Error interrupt was raised by the corresponding submodule

Note: This bit is only set, when the error interrupt is enabled in the error interrupt enable register of the corresponding submodule.

MCS4_CH1_EIRQ

: MCS4 channel 1 error interrupt. see bit 31.

MCS4_CH2_EIRQ

: MCS4 channel 2 error interrupt. see bit 31.

MCS4_CH3_EIRQ : MCS4channel 3 error interrupt. see bit 31.

MCS4_CH4_EIRQ : MCS4 channel 4 error interrupt. see bit 31.

MCS4_CH5_EIRQ : MCS4 channel 5 error interrupt. see bit 31.

MCS4_CH6_EIRQ

: MCS4 channel 6 error interrupt. see bit 31.

MCS4_CH7_EIRQ

: MCS4 channel 7 error interrupt. see bit 31.

MCS5_CH0_EIRQ

: MCS5 channel 0 error interrupt. see bit 31.

MCS5_CH1_EIRQ : MCS5 channel 1 error interrupt. see bit 31.

MCS5_CH2_EIRQ : MCS5 channel 2 error interrupt. see bit 31.

MCS5_CH3_EIRQ : MCS5 channel 3 error interrupt. see bit 31.

MCS5_CH4_EIRQ

: MCS5 channel 4 error interrupt. see bit 31.

MCS5_CH5_EIRQ

: MCS5 channel 5 error interrupt. see bit 31.

MCS5_CH6_EIRQ

: MCS5 channel 6 error interrupt. see bit 31.

MCS5_CH7_EIRQ : MCS5 channel 7 error interrupt. see bit 31.

MCS6_CH0_EIRQ : MCS6 channel 0 error interrupt. see bit 31.

MCS6_CH1_EIRQ : MCS6 channel 1 error interrupt. see bit 31.

MCS6_CH2_EIRQ

: MCS6 channel 2 error interrupt. see bit 31.

MCS6_CH3_EIRQ

: MCS6 channel 3 error interrupt. see bit 31.

MCS6_CH4_EIRQ

: MCS6 channel 4 error interrupt. see bit 31.

MCS6_CH5_EIRQ : MCS6 channel 5 error interrupt. see bit 31.

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Bit

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Table 348. ICM_IRQG_CEI4 field description (continued)

Description

MCS6_CH6_EIRQ : MCS6 channel 6 error interrupt. see bit 31.

MCS6_CH7_EIRQ

: MCS6 channel 7 error interrupt. see bit 31.

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

RM0361

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19 Output compare unit (CMP)

Output compare unit (CMP)

19.1 Overview

The Output Compare Unit (CMP) is designed for the use in safety relevant applications. The main idea is to have the possibility to duplicate outputs in order to be compared in this unit.

Because of the simple EXOR function used it is necessary to ensure the total cycle accurate output behavior of the output modules to be compared. This is given when two ATOM units produce output signals at the same time stamp or when two TOMs have the same configuration and start their output generation at the same time. This is possible by means of the trigger mechanisms TRIG_x

provided by the TOMs as shown in the Figure 32: TOM block diagram

. It is not necessary to compare each output channel with each other.

The CMP enables the comparison of 2x24 channels of the TOM and ATOM units respectively and is restricted to neighbor channels. Thus, channel 0 is compared with channel 1, channel 2 with 3 and so on until the comparison of channel 22 with channel 23.

$720

Figure 79. Architecture of the compare unit

&03B,54

&03

&03B(,54

&03B,54B(1 &03B(,54B(1

%:&

&03B(55

$720

720 &03B(1

("1(.4

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19.2 Bitwise compare unit (BWC)

The bitwise compare unit compares in pairs the combinations shown in following table.

TBWC/ABWC comparator number

Table 349. Bitwise compare unit

Compare TOM/ATOM bit number one

Compare TOM/ATOM bit number two

Output number

Because of the restrictions described in the section above the compare unit consists of 24 anti-valence (EXOR) elements, a select register CMP_EN which selects the corresponding comparisons and a status register CMP_IRQ_NOTIFY which shows and stores each mismatching result, when selected.

For each with CMP_IRQ_EN enabled mismatching error an interrupt signal on CMP_IRQ is generated.

For each with CMP_EIRQ_EN enabled mismatching error an interrupt signal on CMP_EIRQ is generated.

The error generator generates an error signal to be transmitted directly to the MON unit and independently from the CMP_IRQ and CMP_EIRQ . The error is set when in the

CMP_IRQ_NOTIFY register at least one bit is set. The CMP_IRQ_NOTIFY bits are not mask able for this purpose.

The CMP_ERR output reflects its status in the status register of the monitor unit, which is to be polled by the CPU.

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RM0361 Output compare unit (CMP)

The CMP submodule has two interrupt signals, one normal interrupt and one error interrupt.

The source of both interrupt can be determined by reading the CMP_IRQ_NOTIFY register under consideration of CMP_IRQ_EN register and CMP_EIRQ_EN register. Each source can be forced separately for debug purposes using the interrupt force CMP_IRQ_FORCINT register. CMP_IRQ_MODE configures interrupt output characteristic. All interrupt modes are described in detail in

Section 2.5: GTM-IP interrupt concept

Signal

CMP_EIRQ

CMP_IRQ

Table 350. CMP interrupt signals

Description

Mismatching interrupt of outputs to be compared, when enabled

19.6 CMP configuration registers overview

CMP contains following configuration registers.

Register name

CMP_EN

CMP_IRQ_NOTIFY

CMP_IRQ_EN

CMP_IRQ_FORCINT

CMP_IRQ_MODE

CMP_EIRQ_EN

Table 351. CMP configuration registers

Description Details in section

Comparator enable register

Event notification register

Interrupt enable register

19.7.1

19.7.2

19.7.3

Interrupt force register

19.7.4

IRQ mode configuration register

19.7.5

Error interrupt enable register

19.7.6

19.7 CMP configuration registers description

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 0x00

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 352. CMP_EN field description

Description

ABWC0_EN

: Enable comparator 0 in ABWC (see Section 19.2: Bitwise compare unit (BWC) )

0 = ABWC Comparator 0 is disabled

1 = ABWC Comparator 0 is enabled

ABWC1_EN

: Enable comparator 1 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC2_EN

: Enable comparator 2 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC3_EN

: Enable comparator 3 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC4_EN

: Enable comparator 4 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC5_EN

: Enable comparator 5 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC6_EN

: Enable comparator 6 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC7_EN

: Enable comparator 7 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC8_EN

: Enable comparator 8 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC9_EN

: Enable comparator 9 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC10_EN

: Enable comparator 10 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

)

see bit 31

ABWC11_EN

: Enable comparator 11 in ABWC (see

Section 19.2: Bitwise compare unit (BWC)

) see bit 31

TBWC0_EN

: Enable comparator 0 in TBWC (see

Section 19.2: Bitwise compare unit (BWC)

)

0 = TBWC comparator 0 is disabled

1 = TBWC comparator 0 is enabled

TBWC1_EN : Enable comparator 1 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

See bit 19

TBWC2_EN : Enable comparator 2 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

See bit 19

TBWC3_EN : Enable comparator 3 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

See bit 19

TBWC4_EN : Enable comparator 4 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

TBWC5_EN : Enable comparator 5 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

TBWC6_EN : Enable comparator 6 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

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Output compare unit (CMP)

Table 352. CMP_EN field description (continued)

Description

TBWC7_EN : Enable comparator 17in TBWC (see

Section 19.2: Bitwise compare unit (BWC)

) see bit 19

TBWC8_EN : Enable comparator 8 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

TBWC9_EN : Enable comparator 9 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

TBWC10_EN : Enable comparator 10 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

TBWC11_EN : Enable comparator 11 in TBWC (see

Section 19.2: Bitwise compare unit (BWC) )

see bit 19

Reserved : Read as zero, should be written as zero.

Note:

Read as zero, should be written as zero

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 353. CMP_IRQ_NOTIFY field description

Description

ABWC0 : error indication for ABWC0

0 = no error recognized on ATOM sub modules bits 0 and 1 (see Section 19.2: Bitwise compare unit (BWC) )

1 = an error was recognized on corresponding ATOM sub modules bits

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ABWC1 : error indication for ABWC1. see bit 31.

see bit 31

ABWC2 : error indication for ABWC2. see bit 31.

see bit 31

ABWC3 : error indication for ABWC3. see bit 31.

see bit 31

ABWC4 : error indication for ABWC4. see bit 31.

see bit 31

ABWC5 : error indication for ABWC5. see bit 31.

see bit 31

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Table 353. CMP_IRQ_NOTIFY field description (continued)

Description

ABWC6 : error indication for ABWC6. see bit 31.

see bit 31

ABWC7 : error indication for ABWC7. see bit 31.

see bit 31

ABWC8 : error indication for ABWC8. see bit 31.

see bit 31

ABWC9 : error indication for ABWC9. see bit 31.

see bit 31

ABWC10 : error indication for ABWC10. see bit 31.

see bit 31

ABWC11 : error indication for ABWC11. see bit 31.

see bit 31

TBWC0

: TOM sub modules outputs bitwise comparator 0 error indication

0 = no error recognized on TOM sub modules bits 0 and 1 (see chapter )

1 = an error was recognized on corresponding TOM sub modules bits

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

TBWC1

: TOM sub modules outputs bitwise comparator 1 error indication. See bit 19.

TBWC2

: TOM sub modules outputs bitwise comparator 2 error indication. See bit 19.

TBWC3

: TOM sub modules outputs bitwise comparator 3 error indication. See bit 19.

TBWC4 : TOM sub modules outputs bitwise comparator 4 error indication. See bit 19.

TBWC5 : TOM sub modules outputs bitwise comparator 5 error indication. See bit 19.

TBWC6 : TOM sub modules outputs bitwise comparator 6 error indication. See bit 19.

TBWC7

: TOM sub modules outputs bitwise comparator 7 error indication. See bit 19.

TBWC8

: TOM sub modules outputs bitwise comparator 8 error indication. See bit 19.

TBWC9

: TOM sub modules outputs bitwise comparator 9 error indication. See bit 19.

TBWC10 : TOM sub modules outputs bitwise comparator 10 error indication. See bit 19.

TBWC11 : TOM sub modules outputs bitwise comparator 11 error indication. See bit 19.

Reserved : Read as zero, should be written as zero.

Note: Read as zero, should be written as zero

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 354. CMP_IRQ_EN field description

Description

ABWC0_EN_IRQ : enable ABWC0 interrupt source for CMP_IRQ line

0 = interrupt source ABWC0 is disabled

1 = interrupt source ABWC0 is enabled

ABWC1_EN_IRQ

: enable ABWC1 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC2_EN_IRQ

: enable ABWC2 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC3_EN_IRQ

: enable ABWC3 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC4_EN_IRQ

: enable ABWC4 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC5_EN_IRQ

: enable ABWC5interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC6_EN_IRQ

: enable ABWC6 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC7_EN_IRQ

: enable ABWC7 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC8_EN_IRQ

: enable ABWC8 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC9_EN_IRQ

: enable ABWC9 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC10_EN_IRQ

: enable ABWC10 interrupt source for CMP_IRQ line. see bit 31.

see bit 31

ABWC11_EN_IRQ

: enable ABWC11 interrupt source for CMP_IRQ line. see bit 31.

See bit31

TBWC0_EN_IRQ

: enable TBWC0 interrupt source for CMP_IRQ line

0 = interrupt source TBWC0 is disabled

1 = interrupt source TBWC0 is enabled

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Table 354. CMP_IRQ_EN field description (continued)

Description

TBWC1_EN_IRQ : enable TBWC1 interrupt source for CMP_IRQ line.

See bit 19

TBWC2_EN_IRQ : enable TBWC2 interrupt source for CMP_IRQ line.

See bit 19

TBWC3_EN_IRQ : enable TBWC3 interrupt source for CMP_IRQ line.

See bit 19

TBWC4_EN_IRQ : enable TBWC4 interrupt source for CMP_IRQ line.

See bit 19

TBWC5_EN_IRQ : enable TBWC5 interrupt source for CMP_IRQ line.

See bit 19

TBWC6_EN_IRQ : enable TBWC6 interrupt source for CMP_IRQ line.

See bit 19

TBWC7_EN_IRQ

: enable TBWC7 interrupt source for CMP_IRQ line.

See bit 19

TBWC8_EN_IRQ

: enable TBWC8 interrupt source for CMP_IRQ line.

See bit 19

TBWC9_EN_IRQ

: enable TBWC9 interrupt source for CMP_IRQ line.

See bit 19

TBWC10_EN_IRQ

: enable TBWC10 interrupt source for CMP_IRQ line.

See bit 19

TBWC11_EN_IRQ

: enable TBWC11 interrupt source for CMP_IRQ line.

See bit 19

Reserved

: reserved

Note:

Read as zero, should be written as zero

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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Table 355. CMP_IRQ_FORCINT field description

Description

TRG_ABWC0 : Trigger ABWC0 bit in CMP_IRQ_NOTIFY register by software

0 = No event triggering

1 = Assert corresponding field in CMP_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

Note: This bit is write protected by bit RF_PROT of register GTM_CTRL

TRG_ABWC1

: Trigger ABWC1 bit in CMP_IRQ_NOTIFY register by software.

See bit 31

TRG_ABWC2

: Trigger ABWC2 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC3

: Trigger ABWC3 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC4

: Trigger ABWC4 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC5

: Trigger ABWC5 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC6

: Trigger ABWC6 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC7

: Trigger ABWC7 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC8

: Trigger ABWC8 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC9

: Trigger ABWC9 bit in CMP_IRQ_NOTIFY register by software.

see bit 31

TRG_ABWC10

: Trigger ABWC10 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_ABWC11

: Trigger ABWC11 bit in CMP_IRQ_NOTIFY register by software. see bit 31

TRG_TBWC0

: Trigger TBWC0 bit in CMP_IRQ_NOTIFY register by software

0 = No event triggering

1 = Assert corresponding field in CMP_IRQ_NOTIFY register

Note:

This bit is cleared automatically after write.

TRG_TBWC1

: Trigger TBWC1 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC2

: Trigger TBWC2 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC3

: Trigger TBWC3 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC4

: Trigger TBWC4 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

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Table 355. CMP_IRQ_FORCINT field description (continued)

Description

TRG_TBWC5 : Trigger TBWC5 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC6 : Trigger TBWC6 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC7 : Trigger TBWC7 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC8 : Trigger TBWC8 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC9 : Trigger TBWC9 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC10 : Trigger TBWC10 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

TRG_TBWC11

: Trigger TBWC11 bit in CMP_IRQ_NOTIFY register by software.

See bit 19

Reserved

: reserved

Note:

Read as zero, should be written as zero

RM0361

Address offset: see Appendix B Initial value: 0x0000_000X

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

[30:31]

[0:29]

0x00000000

Table 356. CMP_IRQ_MODE field description

Description

IRQ_MODE

: IRQ mode selection

00 = Level mode

01 = Pulse mode

10 = Pulse-Notify mode

11 = Single-Pulse mode

Note: The interrupt modes are described in section .

Reserved

: reserved

Note: Read as zero, should be written as zero

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

Table 357. CMP_EIRQ_EN field description

Description

ABWC0_EN_EIRQ : enable ABWC0 interrupt source for CMP_EIRQ line

0 = interrupt source ABWC0 is disabled

1 = interrupt source ABWC0 is enabled

ABWC1_EN_EIRQ

: enable ABWC1 interrupt source for CMP_EIRQ line. see bit 31

ABWC2_EN_EIRQ

: enable ABWC2 interrupt source for CMP_EIRQ line. see bit 31

ABWC3_EN_EIRQ

: enable ABWC3 interrupt source for CMP_EIRQ line. see bit 31

ABWC4_EN_EIRQ

: enable ABWC4 interrupt source for CMP_EIRQ line. see bit 31

ABWC5_EN_EIRQ

: enable ABWC5 interrupt source for CMP_EIRQ line. see bit 31

ABWC6_EN_EIRQ

: enable ABWC6 interrupt source for CMP_EIRQ line. see bit 31

ABWC7_EN_EIRQ

: enable ABWC7 interrupt source for CMP_EIRQ line.

see bit 31

ABWC8_EN_EIRQ

: enable ABWC8 interrupt source for CMP_EIRQ line.

see bit 31

ABWC9_EN_EIRQ

: enable ABWC9 interrupt source for CMP_EIRQ line. see bit 31

ABWC10_EN_EIRQ

: enable ABWC10 interrupt source for CMP_EIRQ line. see bit 31

ABWC11_EN_EIRQ

: enable ABWC11 interrupt source for CMP_EIRQ line. see bit 31

TBWC0_EN_EIRQ

: enable TBWC0 interrupt source for CMP_EIRQ line

0 = interrupt source TBWC0 is disabled

1 = interrupt source TBWC0 is enabled

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Table 357. CMP_EIRQ_EN field description (continued)

Description

TBWC1_EN_EIRQ : enable TBWC1 interrupt source for CMP_EIRQ line.

See bit 19

TBWC2_EN_EIRQ : enable TBWC2 interrupt source for CMP_EIRQ line.

See bit 19

TBWC3_EN_EIRQ : enable TBWC3 interrupt source for CMP_EIRQ line.

See bit 19

TBWC4_EN_EIRQ : enable TBWC4 interrupt source for CMP_EIRQ line.

See bit 19

TBWC5_EN_EIRQ : enable TBWC5 interrupt source for CMP_EIRQ line.

See bit 19

TBWC6_EN_EIRQ : enable TBWC6 interrupt source for CMP_EIRQ line.

See bit 19

TBWC7_EN_EIRQ

: enable TBWC7 interrupt source for CMP_EIRQ line.

See bit 19

TBWC8_EN_EIRQ

: enable TBWC8 interrupt source for CMP_EIRQ line.

See bit 19

TBWC9_EN_EIRQ

: enable TBWC9 interrupt source for CMP_EIRQ line.

See bit 19

TBWC10_EN_EIRQ

: enable TBWC10 interrupt source for CMP_EIRQ line.

See bit 19

TBWC11_EN_EIRQ

: enable TBWC11 interrupt source for CMP_EIRQ line.

See bit 19

Reserved

: reserved

Note:

Read as zero, should be written as zero

RM0361

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20 Monitor unit (MON)

Monitor unit (MON)

20.1 Overview

The Monitor Unit (MON) is designed for the use in safety relevant applications. The main idea is to have a possibility to supervise common used circuitry and resources. In this way the activity of the clocks is supervised. In addition the characteristics of output signals can be checked in a MCS channel by a re-read-in via TIM and routing to the MCS. When the comparison fails an error signal is generated in MCS and sent to the monitor unit. One error signal per MCS summarizes the errors of all channels. By generating of an activity signal per channel for each such performed comparison, the activity of TIM, ARU and the used clocks are checked implicitly.

In addition the ARU cycle time could be also compared in a MCS channel to given values.

Figure 80. MON block diagram

021

&08

&08B);&/.

&08B&/.

&03B(55

&03

0&6B(55

0&6

0&6B&+B0&$

[

("1(.4

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20.1.1 Realization without activity checker of the clock signals

An activity checker of the clock signals used is not needed because these enable signals are only enabled to be used in combination with the system clock. Therefore the clock enables are to be checked to have a high value.

The monitor unit has a connection to each of the 8 clocks CMU_CLK[x] (x=0...7), provided by the CMU. Some of these clocks can be used for special tasks (see

Chapter 8: Clock

Management Unit (CMU) ).

In addition the 5 clock inputs of the TOMs CMU_FXCLK[y] (y=0...4) are also connected to the MON unit.

The supervising of the clocks is done by scanning for activity of each clock.

A high value is defined as the state to be monitored.

When a high value of the clock enable is detected, the corresponding bit in the status register MON_STATUS is set.

The status register bits are reset by writing a one.

When the register is polled by the CPU and the time between two read accesses is higher than the period of the slowest clock, all bits of the corresponding clocks must have been set.

When polling in shorter time distances, not for all clocks an activity can be shown, although they are still working.

Because of the realization without a select register for the clock signals only the bits of the status register are to be considered for which the clock signal is enabled in the CMU.

20.3 CMP error monitoring

The signal CMP_ERR is to be received directly from module CMP and is set if an error occurred.

20.4 Checking the characteristics of signals by MCS

By use of the MCS some given properties of signals can be checked. Such signals can be generated output signals of TOM or ATOM channels, which are re-read in into a TIM and the time stamp information is routed via ARU to the MCS module.

The corresponding MCS signal performs the check according to given properties. In this way signal high or low time as well as signal periods can be checked, also taking into account tolerances. When the check fails a MCS internal error signal is generated and

ORed with the error signals of the other channels of the MCS module to a summarized error signal MCS[z]_ERR (z=0...3).

For each MCS a summarized error signal is transmitted to MON and monitored in the

MON_STATUS register.

In order to check the execution of the comparison for each MCS channel an activity signal is generated. In the MCA_i_x (x=0...7) vector always for each MCS 8 bits for each channels are combined. The activity signals are stored in the MON_ACTIVITY_0 register for MCS0 to

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MCS3 and in the MON_ACTIVITY_1 register for MCS4 to MCS6. The bits are set by a one signal and reset by writing a one to it (preferably after polling the status of the register).

Because the activity signal shows the execution of a comparison, the involved units for providing the signals and execution of comparison (like TIM, ARU and MCS itself) are checked implicitly to work accordingly. Also the involved clocks and time bases are checked in this way.

20.5 Checking ARU cycle time

The cycle time of the ARU can be checked, when this is essential for safety purposes. This check can be performed by an MCS channel. It should be noted that the MCS program for measuring the ARU round trip time must add a tolerance value.

The resulting error is reported to the MON unit using the summarized error signal

MCS[z]_ERR for each MCS module in addition to an interrupt, generated in MCS. The same signals and status bits are used as in the case of checking the signal characteristics.

The corresponding MCS is programmed to get a fixed data value at address 0x1FF. The data value is always zero and is not blocked. When getting the access the time stamp value

TBU_TS0 is stored in a register. The next time getting the access the new TBU_TS0 value is stored and the difference between both values is compared with a given value. When the comparison fails, an error flag is set in the MCS internal status register, an interrupt is generated and the error signal MCS[z]_ERR is provided.

When the check is performed, an activity signal MCA_x (x=0...31) is provided for each channel x of every MCS[i] (i=0...6) instance together with a summarized interrupt

MCS[i]_ERR for each MCS.

The activity signal sets a bit in the MON_ACTIVITY register.

The bits in the MON_ACTIVITY registers are reset by writing a one.

When the check fails, an interrupt is generated and the error signal MCS[z]_ERR is provided for the MON unit.

Figure 80

shows the block diagram of the monitor unit.

20.6 MON interrupt signals

The MON submodule has no interrupt signals.

20.7 MON registers overview

Following configuration registers are considered in MON sub module.

Register name

MON_STATUS

MON_ACTIVITY_0

MON_ACTIVITY_1

Table 358. MON registers overview

Description

Monitor status register

Monitor activity register 0

Monitor activity register 1

Details in section

20.8.1

20.8.2

20.8.3

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20.8 MON configuration registers description

RM0361

Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00 0 0 0 0 0 0 0 0x00 0 0x0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 359. MON_STATUS field description

Description

ACT_CMU0

: CMU_CLK0 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU1 : CMU_CLK1 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU2

: CMU_CLK2 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU3 : CMU_CLK3 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU4

: CMU_CLK4 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU5 : CMU_CLK5 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU6

: CMU_CLK6 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMU7 : CMU_CLK7 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Monitor unit (MON)

Table 359. MON_STATUS field description (continued)

Description

ACT_CMUFX0 : CMU_CLKFX0 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMUFX1

: CMU_CLKFX1 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMUFX2 : CMU_CLKFX2 activity

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMUFX3

: CMU_CLKFX3 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

ACT_CMUFX4

: CMU_CLKFX4 activity

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Note: Bits 31 to 19 are set, when a high low slope is detected at the considered clock

Reserved

: reserved

Note: Read as zero, should be written as zero

CMP_ERR

: Error detected at CMP

Note: This bit will be readable only.

Reserved

: reserved

Note: Read as zero, should be written as zero

MCS0_ERR

: Error detected at MCS0

Note: This bit will be readable only.

MCS1_ERR

: Error detected at MCS1

Note: This bit will be readable only.

MCS2_ERR

: Error detected at MCS2

Note: This bit will be readable only.

MCS3_ERR

: Error detected at MCS3

Note: This bit will be readable only.

MCS4_ERR

: Error detected at MCS4

Note: This bit will be readable only.

MCS5_ERR

: Error detected at MCS5

Note: This bit will be readable only.

MCS6_ERR

: Error detected at MCS6

Note: This bit will be readable only.

Reserved

: reserved

Note: Read as zero, should be written as zero

Note: Bits16 and 11 to 5 are set, when the corresponding unit reports an error

Note:

The MCS can be programmed to generate an error, when the comparison of signal values (duty time, cycle time) fails or also when the cycle time of the ARU (checking of the TBU_TS0 between two periodic accesses) is out of the expected range.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit

Table 360. MON_ACTIVITY_0 field description

Description

MCA_0_0

: activity of check performed in module MCS0 at channel 0

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_1 : activity of check performed in module MCS0 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_2

: activity of check performed in module MCS0 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_3 : activity of check performed in module MCS0 at channel 3

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_4

: activity of check performed in module MCS0 at channel 4

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_5 : activity of check performed in module MCS0 at channel 5

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_6

: activity of check performed in module MCS0 at channel 6

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_0_7 : activity of check performed in module MCS0 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_0

: activity of check performed in module MCS1 at channel 0

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Table 360. MON_ACTIVITY_0 field description (continued)

Description

MCA_1_1 : activity of check performed in module MCS1 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_2

: activity of check performed in module MCS1 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_3 : activity of check performed in module MCS1 at channel 3

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_4

: activity of check performed in module MCS1 at channel 4

Note: : This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_5

: activity of check performed in module MCS1 at channel 5

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_6

: activity of check performed in module MCS1 at channel 6

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_1_7

: activity of check performed in module MCS1 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_0

: activity of check performed in module MCS2 at channel 0

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_1 : activity of check performed in module MCS2 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_2 : activity of check performed in module MCS2 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_3

: activity of check performed in module MCS2 at channel 3

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_4

: activity of check performed in module MCS2 at channel 4

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_5

: activity of check performed in module MCS2 at channel 5

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_2_6

: activity of check performed in module MCS2 at channel 6

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Monitor unit (MON)

Bit

RM0361

Table 360. MON_ACTIVITY_0 field description (continued)

Description

MCA_2_7 : activity of check performed in module MCS2 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_0

: activity of check performed in module MCS3 at channel 0

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_1 : activity of check performed in module MCS3 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_2

: activity of check performed in module MCS3 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_3

: activity of check performed in module MCS3 at channel 3

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_4

: activity of check performed in module MCS3 at channel 4

Note:

: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_5

: activity of check performed in module MCS3 at channel 5

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_6

: activity of check performed in module MCS3 at channel 6

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_3_7 : activity of check performed in module MCS3 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Note: When not all MCS modules are implemented or the channels are not used for check purposes with supervising, the corresponding activity bits remain zero.

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Address offset: see Appendix B Initial value: 0x0000_0000

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Bit

Mode

Initial value

Bit

0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 361. MON_ACTIVITY_1 field description

Description

MCA_4_0

: activity of check performed in module MCS4 at channel 0

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_1 : activity of check performed in module MCS4 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_2

: activity of check performed in module MCS4 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_3 : activity of check performed in module MCS4 at channel 3

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_4

: activity of check performed in module MCS4 at channel 4

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_5 : activity of check performed in module MCS4 at channel 5

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_6

: activity of check performed in module MCS4 at channel 6

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_4_7 : activity of check performed in module MCS4 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_0

: activity of check performed in module MCS5 at channel 0

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Monitor unit (MON)

Bit

RM0361

Table 361. MON_ACTIVITY_1 field description (continued)

Description

MCA_5_1 : activity of check performed in module MCS5 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_2

: activity of check performed in module MCS5 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_3 : activity of check performed in module MCS5 at channel 3

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_4

: activity of check performed in module MCS5 at channel 4

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_5

: activity of check performed in module MCS5 at channel 5

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_6

: activity of check performed in module MCS5 at channel 6

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_5_7

: activity of check performed in module MCS5 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_0

: activity of check performed in module MCS6 at channel 0

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_1 : activity of check performed in module MCS6 at channel 1

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_2 : activity of check performed in module MCS6 at channel 2

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_3

: activity of check performed in module MCS6 at channel 3

Note: This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_4

: activity of check performed in module MCS6 at channel 4

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_5

: activity of check performed in module MCS6 at channel 5

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

MCA_6_6

: activity of check performed in module MCS6 at channel 6

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

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Note:

Bit

[0:7]

Monitor unit (MON)

Table 361. MON_ACTIVITY_1 field description (continued)

Description

MCA_6_7 : activity of check performed in module MCS6 at channel 7

Note:

This bit will be cleared on a CPU write access of value '1'. A read access leaves the bit unchanged.

Reserved

: Reserved bits

Note: Read as zero should be written as zero

When not all MCS modules are implemented or the channels are not used for check purposes with supervising, the corresponding activity bits remain zero.

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Appendix A RM0361

21.1 Register bit attributes

Below the bit name in a register table, the attributes "Access mode" and "Reset value" of each bit are described with the following syntax:

Mode

Table 362. Register bit attributes

Description

Read access

Write access

Clear on read access

Set on read access

Clear by write 1 (sets only those bits with value 1)

Set by write 1 (clears only those bits with value 1)

Auto clear after write (e.g. trigger something)

Protected write (separate write enable bit, e.g. init)

Note: When using Cw or Sw for a bit field e.g. representing a number, a clear/set has to be applied to all bits of the data field, to avoid construction of unintended values different to "00...00" and "11...11".

21.2 Register reset value

Reset value

Table 363. Register reset value

Description

Logic value is 0 after reset

Logic value is 1 after reset

21.3 ARU write address overview

The ARU write address map is specified in Appendix B of your version (see Section 22.3:

References ).

21.4 GTM configuration registers address map

The addresses of the implemented submodules are specified in Appendix B of your version

(see Section 22.3: References ).

The start and end addresses of the configured rams are specified in Appendix B of your version (see

Section 22.3: References

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The full address map of all implemented registers, the start and end addresses of configured rams are recorded in Appendix B of your version (see

Section 22.3: References ).

21.5 GTM application constraints

The constraints put on applications by GTM implementation are specified in Appendix B of your version (see

Section 22.3: References

21.6 GTM internal functional dependencies

The

Figure 81

shows the functional dependencies of GTM.

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Appendix A

Figure 81. Functional dependencies of GTM

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22.1 Revision Number Notice

The specification revision number of this document consists of four decimal integers separated by a dot.

The first decimal integer represents the major release number, the second represents the minor release number and the third represents the delivery number of specification.

A GTM-IP release always refers to the first three decimal integer of the specification revision number and is extended by a design step identifier. This GTM-IP release number can be read out of register GTM_REV.

The fourth decimal integer of specification revision number is related to updated versions of the specification which are independent of a GTM-IP release.

During silicon validation and qualification process it may turn out that the current specification revision related to the silicon is incomplete, inconsistent or ambiguous. It may also be the case that the silicon behaviour diverges for a specific functional feature from specification but the behaviour of silicon is also acceptable for intended GTM applications.

In these cases Bosch AE will update the specification and indicate this update by an increase of the fourth decimal integer of specification revision number.

An increased fourth decimal integer means that either the new specification is more precise or that a functional feature was limited or removed. It never means that there was added a new feature.

22.2 Conventions

The following conventions are used within this document.

ARIAL BOLD CAPITALS

Arial italic

Courier

Names of register and register bits

Names of signals

Extracts of files

22.3 References

GTM-IP_101 Appendix B (UM1663, DocID 025134)

2. GTM-IP_122 Appendix B (UM1666, DocID 025138)

22.4 Terms and abbreviations

This document uses the following terms and abbreviations.

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Term

GTM

DPLL

FULL_SCALE

HALF_SCALE

[i]

[x] div mod

Further information RM0361

Table 364. Terms and abbreviations

Meaning

Generic Timer Module

Digital Phase Locked Loop

Range in which all positions/values depend on the information of TRIGGER and

STATE signals

Range in which all positions/values depend on the information of TRIGGER signal only; two consecutive HALF_SCALE periods form a FULL_SCALE period

Time stamp representation

Position (or value) stamp representation; common description

Numbering of Instances of a module (e.g. ATOM[i] references to instance i of module ATOM)

Numbering of channels of a module (e.g. ATOM[i] references to channel x of instance i of module ATOM)

Calculates the quotient of integer division

Calculates the remainder of integer division

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Date

29-Sep-2015

Table 365. Document revision history

Revision Changes

1 Initial release.

Revision history

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