ST SPC563M64CAL144 calibration adapter board Reference Manual

RM0345

Reference manual

SPC563M64CAL144 calibration adapter board for SPC563M64xx devices

Introduction

The SPC563M64CAL144 (rev.B) system is designed to enable the use of new enhanced automotive calibration and debug tools on the SPC563M64xx family of automotive microcontrollers.

The SPC563M64CAL144 (rev.B) can be fitted onto the application printed circuit board

(PCB) in place of the standard SPC563M64xx family microcontroller in LQFP144 package.

SPC563M64CAL144 (rev.B) hardware is designed to support two standardized tool connectors, allowing a variety of calibration and debug hardware to be connected and reused

Figure 1.

SPC563M64CAL144 (rev.B)

Table 1.

Board summary

Order code

SPC563M64CAL144

On board device

SPC563M64xx

*$3*5,

Target footprint

QFP144

September 2013 Doc ID 024080 Rev 3 1/38 www.st.com

Contents

Contents

RM0345

1 Calibration system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2

3

4

7

8

5

6

9

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Calibration bus interface and External Memory . . . . . . . . . . . . . . . . . . 12

4.1

External memory specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2

SRAM supply and data retention function . . . . . . . . . . . . . . . . . . . . . . . . 12

4.3

Calibration bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Tool IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CAN interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Calibration software compatibility and configuration . . . . . . . . . . . . . 22

9.1

Calibration bus sw configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9.1.1

9.1.2

9.1.3

Cal Bus PCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Cal Bus ECCR Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Cal Bus EBI Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9.2

Example Configuration CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Appendix A Calibration base footprints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Appendix B Mechanical constrains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Appendix C Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Appendix D Options placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/38 Doc ID 024080 Rev 3

RM0345 Contents

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Doc ID 024080 Rev 3 3/38

List of tables

List of tables

RM0345

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Board summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

J15, J2 and J14 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset and configuration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

J11 configuration of SRAM supply for retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

J3, J5 and J10 option cut traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Nexus signals on AMP 38 Mictor connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

J12, J13 FlexCAN interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 9.

J6, J17 and J7 FlexCAN interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10.

CAN transceiver operating voltage selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 11.

Calibration bus signals configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 12.

EBDF field definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 13.

EBI_MCR register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14.

EBI_CAL_BRx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 15.

EBI_CAL_BOx register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 16.

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4/38 Doc ID 024080 Rev 3

RM0345

List of figures

List of figures

Figure 1.

SPC563M64CAL144 (rev.B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 2.

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3.

Supply signals from the QFP144 footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4.

Test points on J4 connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5.

Supply signals on SPC563M64xx CSP496 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6.

SRAM supply circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 7.

SRAM schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 8.

JP1 development connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 9.

AMP 38 Mictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 10.

J9 Calibration connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11.

Calibration triggers TOOL_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 12.

CAN schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 13.

TQPACK144SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 14.

Top and side view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 15.

Side and bottom view drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 16.

Complete system side view drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 17.

SPC563M64xx in CSP package schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 18.

Polypod-TQ144 connector schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 19.

Memory, CAN and connectors schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 20.

Options placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 024080 Rev 3 5/38

Calibration system overview

1 Calibration system overview

RM0345

The Calibration Adapter board features 2 Mbytes of SRAM in order to substitute to the

SPC563M64xx internal Flash during calibration.

A voltage regulator is also integrated upon the board to generate, from selectable 5 V source, the 3.3 V voltage for the RAM and the calibration bus interface.

Development connector (Mictor AMP38) is providing the interface for the debug and trace tools.

A calibration connector (ERNI 154819) is providing an interface optimized for calibration usage.

A high speed CAN transceiver is connected to the FlexCAN of the mcu device.

The components chosen in the design of this board are automotive qualified to allow system evaluation over the full automotive evaluation range (-40 °C to 125 °C).

calibration systems include these distinctive features:

●

●

Use 100% production silicon, ensuring full hardware and software compatibility between production and calibration systems;

Support LQFP144 MCU production package allowing calibration systems to be built without requiring modifications to the standard production system housing;

●

●

●

●

2MByte static RAM organized as 1024K words by 16 bits;

On-board latch providing a 16-bit de-multiplexed bus interface from the SPC563M64xx

16-bit multiplexed calibration interface;

Support for Nexus-based debug tools even if application PCB does not include Nexus connector;

Nexus functionality with 12 Message Data Out (MDO) signals;

●

●

●

●

●

●

Support for full-feature calibration tools, via availability of comprehensive set of device signals available on the connectors;

ERNI 154819 connector optimized for calibration;

High speed CAN transceiver with signals protection;

Allows system calibration without impacting standard MCU I/O resources;

Allows system calibration regardless of availability of standard MCU external bus;

Uses tried and tested technology.

6/38 Doc ID 024080 Rev 3

RM0345 Power supply

The Calibration boards requires a +5 V to supply the on board CAN transceiver and a

+3.3 V to supply the SPC563M64xx calibration bus interface and for the external RAM.

The 3.3 V supply is generated on the SPC563M64CAL144 (rev.B) via the very low drop voltage regulator by using the +5V. A LED (D1) will light when the board is powered.

Figure 2.

Power supply

5

9

&

X)

&

Q

8

,1

/)&'775<

287

*1'

9

&

X)

&

Q

*$3*5,

By default the 5V is taken from the target application through the VDDREG supply level

(supply input for the internal voltage regulators of the SPC563M64xx). Gauge J14 enables

the powering from the application board. Table 2 shows its option configuration.

In case that no additional power loading could be applied to the application system during calibration, the +5V can be supplied externally via J4 connector (+5V test point, see

Figure 4 ) and the gauge J14 (see Figure 3 ) must be open.

Doc ID 024080 Rev 3 7/38

Power supply

Figure 3.

Supply signals from the QFP144 footprint

RM0345

VDDEH1B

VDDEH6A

VDDEH6B

VDDEH7

VDDEH7

VDDPLL

VDDREG

VRC33

VRCCTL

VSSPLL

VSSA0

VSTBY

VDDA0

VSUP

10

13

11

77

7

12

6

79

24

34

46

61

78

93

102

113

74

VDDREG

VRCCTL

VSTBY

VDDEH1A

VDDEH1B

VDDEH6A

VDDEH6B

VDDEH7

VDDSYN

VDDA0

+5V

J14

Default = CLOSE

VSSA

VSSSYN

GND

J15

Default = CL

C46

1uF

GND

GAPGRI00341

Figure 4.

Test points on J4 connector

-

9

9

9' '

&21

*1'

*$3*5,

All power signals and voltage references of the SPC563M64xx QFP144 footprint from the application board are directly connected to the respective calibration device signals.

The VDDE12 supply used to power the dedicated SPC563M64xx calibration bus interface is connected to the upon board +3.3 V voltage regulator.

8/38 Doc ID 024080 Rev 3

RM0345

Figure 5.

Supply signals on SPC563M64xx CSP496

Power supply

9''(+

&YUFSOBM#VT*OUFSGBDF &#*

8

63&0

9''(+

9''(+

$

%

9''(+

9''(+$ %

9''(+% $

-

*

$'

9

.

95&

95&

95&

95&

95&

%

'

:

$(

$)

8

8

8

9

9

9

9

5

5

7

7

7

7

8

$$

$$

$%

$%

$(

$*

$*

.

1

5

5

5

5

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(

9''(+$

9''(+%

9''(+%

9''(+$

95&

9

&ORVH[&87

2SHQ[&87

-

9''(+%

-

9

*$3*5,

The VRC33 signal of the CSP496 is connected to its respective signal of the QFP144 target application via the J15 cut trace option.

The VRC33 can be also connected to the on board +3.3V by closing the J2 gauge. In this case the gauge J15 must be open (

Table 2

).

Doc ID 024080 Rev 3 9/38

Power supply RM0345

Table 2.

Option name

J15, J2 and J14 option cut traces

Function Value

(1)

Note

J15

J2

VRC33

VRC33 open close

(default) open

(default) close

VRC33 signal is disconnected from the target application board

VRC33 signal is connected to the target application board

VRC33 signal is disconnected from the on board

+3.3V signal

VRC33 signal is connected to the on board

+3.3V signal

+5V is powered from J4 connector

J14 +5V supply open close

(default)

+5V is powered from target application via

VDDREG pin of the QFP144 target footprint

1.

Refer to Chapter Appendix D: Options placement for layout Jumper placement

10/38 Doc ID 024080 Rev 3

RM0345

3 Reset and configuration signals

Reset and configuration signals

Calibration and debug tools may use the reset signals included in the connectors to have visibility of when the SPC563M64xx device has been reset. Debug tools may also require the ability to force device reset.

All signals of the SPC563M64xx QFP144 footprint from the application board are directly connected to the respective calibration device signals. This includes the following signals on the

Table 3

.

Table 3.

Reset and configuration signals

Signal name Function

/RESET

/RSTOUT

BOOTCFG[1]

PLLREF

WKPCFG

Notes

Reset / Configuration (5)

External reset input

External reset output

Boot configuration input

FMPLL Mode Selection

Weak Pull Configuration

The /RESET pin is an active low input. The

RESET pin is asserted by an external device during a power-on or external reset. The internal reset signal asserts only if the RESET pin asserts for 10 clock cycles. Assertion of the RESET pin while the device is in reset causes the reset cycle to start over.

The RSTOUT pin is an active low output that uses a push/pull configuration. The RSTOUT pin is driven to the low state by the MCU for all internal and external reset sources. There is a delay between initiation of the reset and the assertion of the RSTOUT pin.

The BOOTCFG field holds the value of the

BOOTCFG[1] pin that was latched on the last negation of the RSTOUT pin. The BOOTCFG field is used by the BAM program to determine the location of the Reset

Configuration Word.

PLLREF is used to select whether the oscillator operates in xtal mode or external reference mode from reset.

If RSTCFG is 0, External reference clock selected.

If RSTCFG is 1, Xtal oscillator mode is selected

The signal on the WKPCFG pin determines whether weak pull up or pull down devices are enabled after reset on the eTPU and eMIOS pins.

0: Weak pulldown applied to eTPU and eMIOS pins at reset

1: Weak pullup applied to eTPU and eMIOS pins at reset.

Doc ID 024080 Rev 3 11/38

Calibration bus interface and External Memory

4 Calibration bus interface and External Memory

RM0345

The SPC563M64xx features a 16-bit de-multiplexed calibration bus interface that is connected to an external 2Mbyte SRAM thanks to an on board latch.

4.1

4.2

External memory specification

The calibration board provides a SRAM with the following characteristics:

– 2Mbyte static RAMs organized as 1024K words by 16 bits;

– 16-bit data width;

– Fully static operation: no clock or refresh required;

– 3.3V input supply;

– /CE power-down;

– High-speed access time (10ns);

– Full automotive temperature range;

– Lead-free.

When /CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.

SRAM supply and data retention function

The circuitry in Figure 6

has been implemented on the calibration board to protect the memory and to guarantee that the Working Page is valid after a power fail of the target application by putting the SRAM in standby powered.

The 3.3 V supply of the SRAM (Vmem) is gated by the RESET and RSTOUT signals of the

SPC563M64xx.

The memory enable is driven via the SPC563M64xx chip select C_CS0 “and” the RESETs signals combination.

12/38 Doc ID 024080 Rev 3

RM0345 Calibration bus interface and External Memory

Figure 6.

SRAM supply circuitry

D1

LED

R1

330

+5V

C34

4.7uF

/RSOUT

/RESET

/CS0

1

C35

100n

U2

IN

LF33CDT-TRY

OUT

3

C36

2.2uF

+3.3V

STT5PF20V

C37

100n

Q1

Vmem

GND

C31

1uF

GND

2

1

Vmem

U7

4

74V1G00CTR

GND

2

1

Vmem

U8

4

74V1G32CTR

/CE_RAM

GND

ECU_Vstby

+3.3V

D2

20CJQ060

J11 2

VSTBY

GAPGRI00344

The jumper J11 (see Figure 6

) allows to select the standby operation of the SRAM.

The standby voltage can be selected between:

●

●

●

SPC563M64xx Vstby pin: same standby voltage as the internal RAM; the 3.3V generated on the calibration board;

ECU_Stby supplied by the calibration connector J9 (see

Figure 10

).

Table 4.

J11

J11 configuration of SRAM supply for retention mode

SRAM standby supply source all open

1-2 closed

2-3 closed

ECU_Stby: standby voltage on J9 calibration connector

Upon the board +3.3V generated

VSTBY input pin of the SPC563M64xx from the target application

Doc ID 024080 Rev 3 13/38

Calibration bus interface and External Memory RM0345

4.3 Calibration interface

The calibration bus is made up of address bus, data bus, and bus control signals, and is used on the calibration board to access the upon board memory.

The calibration board supports a 16-bit de-mulitplexed calibration bus. This is derived from the multiplexed bus on the SPC563M64xx, where the majority of address lines are derived from the data lines (CAL_DATA on SPC563M64 device), by using an onboard external latch controlled by the C_TS signal. The ALE functionality of this signal indicates to the external latch when to capture the address signals

Figure 7.

SRAM schematic diagram

&

Q

9PHP

*1'

&

X)

&(B5$0

&B76

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

&(B5$0

&B76

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

9PHP

8$

2(

/(

9&&

'

'

'

'

'

'

'

'

*1'

4

4

4

4

4

4

4

4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

61/9&'**5

*1'

9PHP

2(

/(

9&&

'

'

'

'

'

'

'

'

*1'

4

4

4

4

4

4

4

4

8%

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

61/9&'**5

*1'

9PHP

&

Q

9PHP

*1'

&

X)

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

/DWFKB4

$''5

$''5

$''5

$''5

&6

8

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

$

(

'

+

*

+

+

*

*

)

)

&

&

'

+

+

$

$

$

%

%

$

+

(

1&

1&

1&

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

,2

&(

:(

/%

8%

2(

)

)

*

%

&

%

&

&

'

(

&

'

(

)

)

*

%

*

$

%

$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

'$7$

&(B5$0

&B5'B:5

&B:(

&B:(

&B2(

,6:9%//

*1'

*$3*5,

The

Section 9: Calibration software compatibility and configuration

shows the necessary software configuration of the SPC563M64xx calibration interface.

14/38 Doc ID 024080 Rev 3

RM0345 Development connector

The JTAG signals and Nexus functionality with 12 Message Data Out (MDO) signals are available on the JP1 development connector (Nexus connector).

A hardware control bit in the SPC563M64xx Nexus port controller, is used to control whether the added signals for full width trace port are routed to the MDO[4:11] signals, or the

CAL_MDO[4:11] signals. This control bit is set by the cut trace J1 (default close) on the

NEXUSCFG pin of the SPC563M64xx device, as on the calibration board the

CAL_MDO[4:11] signals are routed to the JP1 development connector.

Figure 8.

JP1 development connector

9

*1'

&

X)

'()$8/7 &/26(

%227&)*

-

$''5

5(6(7

7'2

$''5

7&.

706

7',

-&203

$''5

5 .

*1'

967%<

*3,2B9

9''(+$

-

*3,2B9

'()$8/7 &/26(

-3 1(;86

569'

569'

9(1B,2

9(1B,2

567,1

7'2

9(1B,2

7&.

706

7',

-&203

9(1B,2

567287

722/B,2

722/B,2

8%$77

8%$77

722/B,2

9$/75()

569'

569'

&/.287

9(1B,2

(97,

975()

5'<

0'2

0'2

0'2

0'2

0'2

0'2

0'2

0'2

(972

0&.2

06(2

06(2

'()$8/7 &/26(

-

&/.287

$''5

$''5

9

$''5

$''5

$''5

$''5

$''5

$''5

$''5

$''5

&B(972

&B0&.2

$''5

$''5

*1'

*$3*5,

The option cut trace J3, J5 and J10 are listed on Figure 5

.

Table 5.

option name

J3, J5 and J10 option cut traces

Function Value

J3

J5

J10

CLKOUT

VSTBY

BOOTCFG1 open close

(default) open close

(default) open close

(default)

Note

CLKOUT signal is disconnected to the Nexus JP1 connector

CLKOUT signal is connected to the Nexus JP1 connector

VSTBY signal is disconnected to the Nexus JP1 connector

VSTBY signal is connected to the Nexus JP1 connector

BOOTCFG1 signal is disconnected to the Nexus

JP1 connector

BOOTCFG1 signal is connected to the Nexus

JP1 connector

Doc ID 024080 Rev 3 15/38

Development connector RM0345

Figure 6 shows the mapping of the development connector that provides Debug, Nexus

trace and calibration signals. The port connector is an AMP 38 pin Mictor style.

Figure 9.

AMP 38 Mictor

SLQQ

16/38

*$3*5,

Table 6.

Pin

Nexus signals on AMP 38 Mictor connector

Description

1 nc

3 nc

5 C_MDO9

7 BOOTCFG1*

9 /RESET

11 TDO

13 C_MDO10

15 TCK

17 TMS

19 TDI

21 JCOMP

23 C_MDO11

25 nc

27 10K pull down resistor

29 TOOL_IO1

31 VDDEH1A

33 VDDEH1A

35 TOOL_IO0

37 VSTBY*

Pin Descriptio

2 nc

4 nc

6 CLKOUT*

8 C_MDO8

10 C_EVTI

12 +3.3V

14 RDY

22 C_MDO4

24 C_MDO3

28 C_MDO1

30 C_MDO0

32 C_EVTO

34 C_MCKO

36 C_MSEO1

*) signal is connected via cut trace option

Doc ID 024080 Rev 3

RM0345 Calibration connector

The board is equipped with an ERNI connector to give a more robust solution in terms of physical connectivity for Calibration purpose.

Figure 10.

J9 Calibration connector

56287

*1'

*1'

*1'

*1'

*1'

*1'

5(6(7

*3,2B9

*3,2B9

(&8B9VWE\

-

%

%

%

%

%

%

%

%

%

%

$

$

%

%

$

$

% $

$

$

$

$

$

$

$

$

(51,B

-&203

&$/:DNHXS

$''5

7'2

706

7&.

7',

9PHP

569'[

0'2

73

73

9''(+$

3,17(67

3,17(67

*$3*5,

The

Table 7

shows the mapping of the calibration connector that provides Debug and calibration signals. The port connector is an ERNI 154819 style.

Table 7.

Pin

Nexus signals on AMP 38 Mictor connector

SPC563M64xx routing standard function

Pin

SPC563M64xx routing

B1 nc

B2 nc nc nc

A1 nc

A2 JCOMP

B3 /RSOUT

B4 GND

B5

B6

GND

GND

B7

B8

GND

GND

/RSOUT

GND

GND

GND

GND

GND

A3 CAL

A4

A5

A6

A7

A8

C_EVTI

TDO

TMS

TCK

TDI

B9

B10

B11

GND

/RESET

GPIO[207]

(@3.3V)

GND

/RESET

GPIO Pins for startup handshake and triggering

A9

A10

A11

Vmem nc

RSVDx standard function nc

12V output for Wakeup functionality

JTAG interface

JTAG interface

JTAG interface

JTAG interface

JTAG interface

VDDSBRAM (Backup

Voltage of ECU

Standby RAM) nc reserved Input, connect pin to a solder pad

Doc ID 024080 Rev 3 17/38

Calibration connector RM0345

Table 7.

Pin

Nexus signals on AMP 38 Mictor connector (continued)

SPC563M64xx routing standard function

Pin

SPC563M64xx routing standard function

B12

GPIO[207]

(@3.3V)

GPIO Pins for startup handshake and triggering

A12 MDO 0

Detect that the PLL is locked

B13 ECU_Vsby

VDDSBRAM Supply

(Backup Voltage of

ECU Standby RAM)

A13 +5V

VDDP Comparator

Input (Supply of microcontroller

Interface Pins)

18/38 Doc ID 024080 Rev 3

RM0345 Tool IO

The SPC563M64xx in CSP496 package provides 2 signals, GPIO[206] & GPIO[207], that are not available in the QFP144 standard production package. They can be used by the calibration tools to implement triggers and handshakes. On the calibration board, these signals are available on the JP1 development connector and J9 calibration connector.

By default GPIO[206] & GPIO[207] are powered by VDDEH at 5V. A level shifter (see

Figure 11

) does the translation between the 5v and the 3.3V. This is because the calibration tools operates at 3.3V that is the voltage level of the JTAG and Nexus interfaces.

Figure 11.

Calibration triggers TOOL_IO

*3,2

*3,2

9''(+

5

.

5

.

9

$

$

%

%

8

5

2( 2(

&%7

5

*3,2B9

*3,2B9

*1'

*$3*5,

Doc ID 024080 Rev 3 19/38

CAN interface RM0345

The calibration board is equipped with one ST L9616 High-Speed Transceiver. It provides the Controller Area Network (CAN) communication interface through the SPC563M64xx

CAN interface for calibration via CAN. This serial communication can reach speeds up to

1Mbps.

Figure 12.

CAN schematic diagram

'()$8/7 23(1

-

9

&

X)

9

'()$8/7 &/26(

&17;

&

&15;

Q

*1'

&17;B&

-

-803(5

& 1 7 ;

'()$8/7 23(1

9

'()$8/7 23(1

9

8

7; $6&

*1'

9V

&B+

&B/

5; 5;

/

-

-

&15;B&

-

-803(5

& 1 5 ;

'()$8/7 &/26(

*1'

&

Q

*1'

5

5

*1'

-

&21

&$1B+,*+

&$1B/2:

'

183

&17;B$ &15;B$

*$3*5,

Two jumpers (J12 and J13), allow to select between the two FlexCAN interfaces of the

SPC563M64xx mcu.

Table 8.

J12, J13 FlexCAN interface selection

FlexCAN interface

J12 pin configuration

TX select

J13 pin configuration

RX select

FlexCAN A

FlexCAN C

2 - 3

2 - 1

2 - 3

2 - 1

The CAN channel is terminated with a 120 ohms resistor. Moreover, a protection circuitry has been designed to protect the CAN transceiver in high-speed and fault tolerant networks

from ESD and other harmful transient voltage events (see Figure 12

).

The L9616 CAN transceiver has an Adjustable Slope Control (ASC) feature that sets the slope speed using its ASC pin. This feature select the modes of operation:

●

● low speed (CAN baud rate up to 250kBaud) high speed (CAN baud rate from 250kBaud to 1000kBaud)

This pin can be put to high or to low by the cut trace options J6, J17 & J7 as described in

Table 9

.

20/38 Doc ID 024080 Rev 3

RM0345

Note:

CAN interface

Table 9.

J6, J17 and J7 FlexCAN interface selection

J6 (or J17 if 3.3V) J7 FlexCAN interface closed open open closed low speed operation (default)

(CAN baud rate up to 250kBaud) high speed operation

(CAN baud rate from 250kBaud to 1000kBaud)

The cut trace options J6, J17, J18 and J19 has been put in the design of this board to select the supply of the CAN transceiver between 5 V and 3.3 V. By this option is possible to replace the ST L9616 High-Speed Transceiver mounted on board by default, with a different transceiver that operates at 3.3 V.

Table 10.

CAN transceiver operating voltage selection

CAN Transceiver J6 J17

5V - ST L9616 High-Speed

Transceiver

Adjustable

Slope Control open

3.3V - CAN transceiver open

Adjustable

Slope Control

J18 open close

J19 close open

Refer to Section Appendix D: Options placement

for layout options placement.

Doc ID 024080 Rev 3 21/38

Calibration software compatibility and configuration

9

RM0345

Calibration software compatibility and configuration

The calibration board uses standard production silicon packaged in the CSP (Chip Scale

Package). Therefore, all production silicon features exist and are identical on the calibration board.

The required initialization code may be as simple as the configuration of the EBI and its related pins in the SIU, and it could be integrated into standard application software.

The calibration bus and the SIU can also be configured by an external tool connected to the debug port, removing the need of specific configuration functions in the application software.

9.1

9.1.1

Calibration bus sw configuration

A 16-bit calibration bus is implemented on the board. In multiplexed mode the CAL_DATA signals will output the address signals during the address phase by using an onboard external latch controlled by the CAL_TS signal. The CAL_ALE may be used to drive an external latch when an asynchronous memory is in use.

There are few steps to configure the SPC563M64xx Calibration Bus

– SIU PCR (Pad Configuration Register)

– SIU ECCR (External Clock Control Register)

– External Bus Interface (EBI)

Cal Bus PCR Settings

The SIU PCR registers used to configure the calibration bus are shown in the Table 11

The table also shows the recommended PA field setting.

Table 11.

Calibration bus signals configuration

signal name

SPC563M64xx mcu signal name

Function

C_DATA[0:15]

C_ADDR[12:15]

C_ADDR[16:31]

Address/Data Bus (44)

CAL_DATA[0:15]

CAL_ADDR[12:15]

Calibration data bus

Calibration address bus

-

-

CAL_ADDR[16:31]

C_CS[0] CAL_CS[0]

Calibration address bus

Calibration chip select

-

-

P

A

G

(1)

PCR

PA field

(2)

PCR

(3)

-

-

-

341

340

345

336

Notes

C_CS[2]

CAL_CS[2]

CAL_ADDR[10]

Calibration chip select

Calibration address bus

P

A

1

0

338

22/38 Doc ID 024080 Rev 3

RM0345 Calibration software compatibility and configuration

Table 11.

Calibration bus signals configuration (continued)

signal name

SPC563M64xx mcu signal name

Function

P

A

G

(1)

PCR

PA field

(2)

PCR

(3)

C_CS[3]

CAL_CS[3]

CAL_ADDR[11]

Calibration chip select

Calibration address bus

Calibration

C_OE CAL_OE

Output enable

P

A

-

Calibration

C_RD_WR CAL_RD_WR

Read/write

Calibration

-

-

CAL_TS enable

Calibration transfer start

P

C_TS

CAL_ALE

Address Latch enable

A

Clock Synthesizer (1)

C_CLKOUT CLKOUT

System clock output

P

1

0

-

-

-

1

0

01

339

342

342

342

343

229

Notes

Clock output signal from MCU

Note: 1 The P/A/G column indicates the position a signal occupies in the muxing order for a pin:

Primary, Alternate 1, Alternate 2, Alternate 3, or GPIO. Signals are selected by setting the

PA field value in the appropriate PCR register in the SIU module. The PA field values are as follows: P - 0b0001, A1 - 0b0010, A2 -0b0100, A3 - 0b1000, or G - 0b0000. Depending on the register, the PA field size can vary in length. For PA fields having fewer than four bits, remove the appropriate number of leading zeroes from these values.

2 The Pad Configuration Register (PCR) PA field is used by software to select pin function.

3 Values in the PCR No. column refer to registers in the System Integration Unit (SIU). The actual register name is “SIU_PCR” suffixed by the PCR number.

9.1.2 Cal Bus ECCR Settings

The SIU ECCR registers used to control the timing relationship between the system clock and the external clock CLKOUT.

The external bus clock (CLKOUT) divider can be programmed to divide the system clock by one, two or four based on the settings of the EBDF bit field.

Table 12.

EBDF field definition

Register EBDF field

SIU_ECCR

00

01

10

11

External Bus Division Factor

1

2 reserved

4

Doc ID 024080 Rev 3 23/38

Calibration software compatibility and configuration

9.1.3

RM0345

Cal Bus EBI Settings

For using the calibration bus with an external memory the user must configure the bus for multiplexed operation. These settings are located in two registers:

– EBI Module Configuration Register (EBI_MCR)

– EBI Calibration Base Register (EBI_CAL_BRx)

– EBI Calibration Option Register (EBI_CAL_ORx)

The EBI Module Configuration Register contains bits which configure various attributes associated with EBI operation. In the EBI_MCR register, the D16_31, AD_MUX and DBM fields need to be configured.

Table 13.

EBI_MCR register setting bit field

Name

29

30

31

Description

D16_31

Data Bus 16_31 Select

The D16_31 bit controls whether the EBI uses the

DATA[0:15] or DATA[16:31] signals, when in 16-bit Data

Bus Mode (DBM=1) or for chip-select accesses to a 16bit port (PS=1).

1 = DATA[16:31] signals are used for 16-bit port accesses

0 = DATA[0:15] signals are used for 16-bit port accesses

AD_MUX

Address on Data Bus

Multiplexing Mode

The AD_MUX bit controls whether non-chip-select accesses have the address driven on (or sampled from for external master transfers) the data bus in the address phase of a cycle.

1 = Address on Data Multiplexing Mode is used for non-

CS accesses.

0 = Only Data on data pins for non-CS accesses.

DBM

Data Bus Mode

The DBM bit controls whether the EBI is in 32-bit or 16-bit

Data Bus Mode.

1 = 16-bit Data Bus Mode is used

0 = 32-bit Data Bus Mode is used value

0b0

0b1

0b1

In the EBI_CAL_BRx register there are few fields that need to be configured, these are

detailed in the Table 14

.

24/38 Doc ID 024080 Rev 3

RM0345 Calibration software compatibility and configuration

Table 14.

EBI_CAL_BRx register setting bit field

Name

0-16

20

24

26

30

Description

BA

Base address

PS

Port Size

These bits are compared to the corresponding unmasked address signals among ADDR[0:16] of the internal address bus to determine if a memory bank controlled by the memory controller is being accessed by an internal bus master

Note: An MCU may have some of the upper bits of the

BA field tied to a fixed value internally in order to restrict the address range of the EBI for that MCU. Refer to the device-specific documentation to see which bits are tied off, if any, for a particular MCU. Tied-off bits can be read but not written. These bits are ignored by the EBI during the chip-select address comparison. However, the internal bridge of the MCU most likely requires that the chipselect banks be located in memory regions corresponding to the fixed values chosen

The PS bit determines the data bus width of transactions to this chip-select bank.

Note: In the case where the DBM bit in EBI_MCR is set for 16-bit Data Bus Mode, the PS bit value is ignored and is always treated as a ’1’ (16-bit port).

1 = 16-bit port

0 = 32-bit port

AD_MUX

Address on Data Bus

Multiplexing

The AD_MUX bit controls whether accesses for this chip select have the address driven on the data bus in the address phase of a cycle

1 = Address on Data Multiplexing Mode is enabled for this chip select.

0 = Address on Data Multiplexing Mode is disabled for this chip select.

WEBS

Write Enable / Byte

Select

This bit controls the functionality of the WE[0:3]/BE[0:3] signals.

1 = The WE[0:3]/BE[0:3] signals function as BE[0:3]

0 = The WE[0:3]/BE[0:3] signals function as WE[0:3]

BI

Burst Inhibit

This bit determines whether or not burst read accesses are allowed for this chipselect bank. The BI bit is ignored

(treated as 1) for chip-select accesses with external TA

(SETA=1).

1 = Disable burst accesses for this bank. This is the default value out of reset (or when SETA=1).

0 = Enable burst accesses for this bank] value

-

0b1

0b1

0b1

0b1

Doc ID 024080 Rev 3 25/38

Calibration software compatibility and configuration RM0345

Table 14.

EBI_CAL_BRx register setting bit field

Name

31

V

Valid bit

Description

The user writes this bit to indicate that the contents of this Base Register and Option Register pair are valid.

The appropriate CS signal does not assert unless the corresponding V-bit is set.

1: This bank is valid

0: This bank is not valid value

0b1

The EBI Option Registers are used to define the address mask and other attributes for the corresponding chip select.The SCY field of the EBI_CAL_BOx register is detailed in the

Table 15 .

Table 15.

EBI_CAL_BOx register setting bit field

Name

0-16

24-27

29-30

Description

AM

Address Mask

SCY

Cycle length in clocks

BSCY

Burst beats length in clocks

This field allows masking of any corresponding bits in the associated Base Register.

Masking the address independently allows external devices of different size address ranges to be used. Any clear bit masks the corresponding address bit. Any set bit causes the corresponding address bit to be used in comparison with the address pins.

Address mask bits can be set or cleared in any order in the field, allowing a resource to reside in more than one area of the address map. This field can be read or written at any time.

This field represents the number of wait states (external cycles) inserted after the address phase in the single transfer case, or in the first beat of a burst, when the memory controller handles the external memory access.

Values range from 0 to 15 and its depends on the RAM connected on top board.

This is the main parameter for determining the length of the cycle. These bits are ignored when SETA=1.

The total cycle length for the first beat (including the TS cycle) = (2+SCY) external clock cycles.

This field determines the number of wait states (external cycles) inserted in all burst beats except the first, when the memory controller starts handling the external memory access and thus is using SCY[0:3] to determine the length of the first beat.

These bits are ignored when SETA=1.

The total memory access length for each beat is (1 +

BSCY) external clock cycles.

The total cycle length (including the TS cycle) = (2+SCY)

+ (#beats(h)-1) * (BSCY+1).

value

-

-

-

26/38 Doc ID 024080 Rev 3

RM0345

9.2

Calibration software compatibility and configuration

Example Configuration CODE

The following code is used to configure the calibration bus for 16bit de-multiplexed mode.

//---------------------------------------------------

// SIU PCR (Pad Configuration Register) setup

// (Cal BUS bommon drive strength = 20pF, DSC = 0b01)

//---------------------------------------------------

SIU.PCR[336].R = 0x0040;//CAL_CS[0]DSC=20pF (0b01)

SIU.PCR[338].R = 0x0440;//CAL_CS[2] (PA=0b1),DSC=20pF (0b01)

SIU.PCR[339].R = 0x0040;//CAL_ADDR[11] (PA=0b0), DSC=20pF (0b01)

SIU.PCR[340].R = 0x0040;//CAL_ADDR[12..15], DSC=20pF (0b01)

SIU.PCR[345].R = 0x0040;//CAL_ADDR[16..30], DSC=20pF (0b01)

SIU.PCR[341].R = 0x0040;//CAL_DATA[0..15], DSC=20pF (0b01)

SIU.PCR[342].R = 0x0040;//CAL_RD/WR, CAL_WE[0-1], CAL_OE, DSC=20pF

(0b01)

SIU.PCR[343].R = 0x0040;//CAL_ALE, DSC=20pF (0b01)

//--------------------------------------------------

// SIU ECCR (External Clock Control Register) setup

//--------------------------------------------------

SIU.ECCR.R = 0x1000//External Bus Division Factor = 1 (EBDF=0b00)

//--------------------------------------------------

// EBI Registers setup

//--------------------------------------------------

//-----------------------------------------------------------------

// EBI MCR setup for 16-bit bus configuration:

//

// EARP = 01 (Equal priority);

// D16_31 = 0 (DATA[0:15] signals are used for 16-bit port accesses);

// AD_MUX = 1 (Addr on Data Multiplexing Mode is used for non-CS acc.);

// DBM = 0 (32-bit Data Bus Mode is used);

EBI.MCR.R = 0x802;

//------------------------------------------------------

// EBI Base Register setup for 16-bit bus configuration:

//

// Base Address = 0x20000000;

// PS = 1 (16-bits port size)

// AD_MUX = 1 (Address on Data Multiplexing Mode is enabled for this chip select);

// WEBS = 1 (Use BE function);

// BI = 1 (Disable burst accesses for this bank);

// V = 1 (Valid CS Bank)

EBI.CAL_CS[0].BR.R = 0x200008A3;

Doc ID 024080 Rev 3 27/38

Calibration software compatibility and configuration

//-----------------------------------------

// EBI Option Register setup:

//

// Address mask = 0xefe00000;

// Wait state = 0 (set 0 wait states);

EBI.CAL_CS[0].OR.R = 0xffe00000;

RM0345

28/38 Doc ID 024080 Rev 3

RM0345

Appendix A Calibration base footprints

Calibration base footprints

SPC563M64CAL144 (rev.B) calibration board had footprint compatible with QFP144 production package version of SPC563M64xx devices, ensuring that they can be fitted to an application PCB that has been designed to accept standard QFP144 packaged

SPC563M64xx devices.

Bases can be supplied with solder footprints, to allow direct and permanent soldered connection to an application PCB, or with pin adapter connectors fitted, allowing connection and removal from an application PCB that is fitted with a compatible receiver socket.

Figure 13.

TQPACK144SD

DOOGLPHQVLRQDUHLQPP all dimension are in mm

*$3*5,

Doc ID 024080 Rev 3 29/38

Mechanical constrains

Appendix B Mechanical constrains

Figure 14.

Top and side view drawing

RM0345

30/38 Doc ID 024080 Rev 3

6OJUTNN

*$3*5,

RM0345

Figure 15.

Side and bottom view drawing

Mechanical constrains

3LQ

Doc ID 024080 Rev 3

;

8QLWVPP

*$3*5,

31/38

Mechanical constrains

Figure 16.

Complete system side view drawing

RM0345

8QLWVPP

*$3*5,

32/38 Doc ID 024080 Rev 3

RM0345

Appendix C Schematic

Figure 17.

SPC563M64xx in CSP package schematic

Schematic

AD16

AA7

AA11

Y8

W8

H18

G19

P18

C27

N18

M18

F24

H22

L15

J21

L17

L16

L18

D26

AB20

AA20

AB19

AA19

AB17

AA18

AB16

AA17

U22

U21

T22

T21

W22

V21

Y22

W21

M7

M8

N7

U7

P8

P7

W7

U8

L7

V8

T8

L8

V7

K8

AB14

AB13

AA15

R8

AA14

AB10

AA10

AB11

E14

B14

G14

C13

A13

B13

B12

E12

B11

C11

H13

H12

E8

E9

B7

C16

G15

H15

E16

B6

C4

E11

G13

B9

C10

E10

G12

B8

C9

B4

B5

C5

A14

C6

O

O

S

E

E1

E0

R

5

4

3

2

1

0

0

9

9

8

7

6

7

6

8

4

3

5

2

1

9

8

0

6

5

7

4

3

3

2

2

0

13

12

11

10

15

14

_W

C_T

C_O

CK

VT

AT

AT

AT

AT

AT

AT

C_CS

C_CS

C_CS

C_W

C_W

C_ADD2

C_ADD2

C_ADD2

C_ADD2

C_ADD2

C_ADD1

C_ADD1

C_ADD2

C_ADD1

C_ADD1

C_ADD1

C_ADD1

C_ADD1

C_ADD1

C_ADD2

C_ADD2

C_ADD2

C_ADD3

C_ADD2

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_DAT

C_D

C_D

C_D

C_D

C_D

C_D

C_M

C_E

C_RD

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

VDDEH7

SD

SD

SD

FC

AN16

AN17

AN18

AN11

AN21

O

S

AN9

K

AN7

AN6

AN5

AN4

AN22

AN3

AN2

AN1

AN23

AN0

AN24

AN25

AN27

AN28

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

AN13-

AN12-

AN14-

AN15-

R

O

O

_W

VT

CK

E1

E0

E

S

A.4

A.3

A.5

A.1

A.0

A.2

R.2

R.2

R.2

R.3

R.2

A.1

A.1

A.1

A.1

A.1

A.1

A.9

A.8

A.7

A.6

R.2

R.2

R.2

R.2

R.2

R.2

R.1

R.1

R.1

R.1

R.1

R.1

R.1

R.1

3

2

1

0

5

4

5

4

3

2

1

0

9

8

7

6

5

4

3

2

7

6

8

0

9

C_T

C_O

C_W

C_W

C_RD

C_E

C_M

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

DAT

ADD

ADD

ADD

ADD

ADD

DAT

DAT

DAT

DAT

DAT

DAT

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

/CS3

/CS2

/CS0

6

5

7

8

9

3

2

4

0

8

1

7

5

4

3

2

3

2

4

1

7

6

5

1

8

AN.3

AN.3

AN.3

AN.3

AN.3

AN.3

AN.3

AN.3

AN.3

AN.2

AN.3

AN.2

AN.2

AN.2

AN.2

AN.2

AN.1

AN.1

AN.1

AN.1

AN.9

AN.7

AN.6

AN.1

AN.1

AN.1

AN.2

AN.1

AN.5

AN.4

AN.3

AN.2

AN.1

AN.0

Reset & Configuration

A27

A28

AA21

A1

A2

AA8

AB22

AB7

AD5

AF3

AF26

AG1

AG2

AG27

AG28

AH1

AH2

AH27

AH28

E5

E24

C3

C26

B28

B27

B2

B1

G22

G7

H21

H8

L14

L13

L12

L11

M12

M13

M14

M15

U18

U17

U12

T17

R16

R15

T16

T13

P14

N17

N16

P16

P15

P17

R14

N14

N15

V18

V11

M17

M16

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

9

06

07

8

GPIO9

GPIO2

GPIO2

GPIO9

AG10

AH10

N24

N26 8

9

06

07

GPIO9

GPIO9

GPIO2

GPIO2

Doc ID 024080 Rev 3

GAPGRI00355

33/38

Schematic

Figure 18.

Polypod-TQ144 connector schematic

AN.14

AN.15

AN.16

AN.17

AN.18

AN.21

AN.22

AN.23

AN.24

AN.25

AN.27

AN.28

AN.30

AN.31

AN.0

AN.1

AN.2

AN.3

AN.4

AN.5

AN.6

AN.7

AN.9

AN.11

AN.12

AN.13

AN.32

AN.33

AN.34

AN.35

AN.38

AN.39

AN28

AN30

AN31

AN32

AN33

AN34

AN35

AN38

AN39

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

AN9

AN11

AN12-SDS

AN13-SDO

AN14-SDO

AN15-FCK

AN16

AN17

AN18

AN21

AN22

AN23

AN24

AN25

AN27

117

116

3

144

132

131

130

129

128

2

1

127

126

125

124

123

122

121

9

8

137

136

5

4

119

118

143

142

141

140

139

138

ETPUA.1

ETPUA.2

ETPUA.3

ETPUA.4

ETPUA.5

ETPUA.6

ETPUA.7

ETPUA.8

ETPUA.9

ETPUA.10

ETPUA.11

ETPUA.12

ETPUA.13

ETPUA.14

ETPUA.15

ETPUA.16

ETPUA.17

ETPUA.18

ETPUA.19

ETPUA.20

ETPUA.21

ETPUA.22

ETPUA.23

ETPUA.24

ETPUA.25

ETPUA.26

ETPUA.27

ETPUA.28

ETPUA.29

ETPUA.30

ETPUA.31

28

27

25

23

21

20

35

33

32

31

30

29

19

18

17

16

15

14

44

43

42

41

40

39

38

37

51

50

49

47

45

/RSOUT

/RESET

85

80

WKPCFG

BOOTCFG1

71

70

PLLREF 68

ETPUA0

ETPUA1

ETPUA2

ETPUA3

ETPUA4

ETPUA5

ETPUA6

ETPUA7

ETPUA8

ETPUA9

ETPUA10

ETPUA11

ETPUA12

ETPUA13

ETPUA14

ETPUA15

ETPUA16

ETPUA17

ETPUA18

ETPUA19

ETPUA20

ETPUA21

ETPUA22

ETPUA23

ETPUA24

ETPUA25

ETPUA26

ETPUA27

ETPUA28

ETPUA29

ETPUA30

ETPUA31

RSTOUT

RESET

WKPCFG

BOOTCFG1

PLLREF

U5

Polypod-TQ144

54

55

56

57

58

60

62

63

64

65

EMIOS.0

EMIOS.2

EMIOS.4

EMIOS.8

EMIOS.9

EMIOS.10

EMIOS.11

EMIOS.12

EMIOS.14

EMIOS.23

133

134

135

VRL

VRH

REFBYPC

75

76

EXTAL

XTAL

66

67

84

81

83

82

72

69

CNTX_A

CNRX_A

CNTX_C

CNRX_C

TXD_A

RXD_A

TXD_B

RXD_B

87

88

97

90

92

94

95

96

89

98

100

107

105

108

JCOMP

TDO

TDI

TCK

TMS

99

101

103

106

109

110

111

112

114

MCKO

/MSEO1

EVTI

EVTO

/MSEO0

MDO0

MDO1

MDO2

MDO3

PCS_B5

PCS_B4

PCS_B3

PCS_B2

PCS_B1

PCS_B0

SIN_B

SOUT_B

SCK_B

102

113

74

10

13

11

77

7

24

34

46

61

78

93

12

6

79

VDDREG

VRCCTL

VSTBY

VDDEH1A

VDDEH1B

VDDEH6A

VDDEH6B

VDDEH7

VDDSYN

VDDA0

EMIOS0

EMIOS2

EMIOS4

EMIOS8

EMIOS9

EMIOS10

EMIOS11

EMIOS12

EMIOS14

EMIOS23

VRL

VRH

REFBYPC

EXTAL

XTAL

CNTXA

CNRXA

CNTXC

CNRXC

TXDA

RXDA

TXDB

RXDB

JCOMP

TDO

TDI

TCK

TMS

MCKO

MSEO1

EVTI

EVTO

MSEO0

MDO0

MDO1

MDO2

MDO3

PCSB5

PCSB4

PCSB3

PCSB2

PCSB1

PCSB0

SINB

SOUTB

SCKB

VDDEH1A

VDDEH1B

VDDEH1B

VDDEH6A

VDDEH6A

VDDEH6B

VDDEH7

VDDEH7

VDDPLL

VDDREG

VRC33

VRCCTL

VSSPLL

VSSA0

VSTBY

VDDA0

VSUP

GND

+5V

J14

VSSA VSSSYN

Default = CLOSE

J15

Default = CLOSE

GND

C46

1uF

VDD

VRC33

GND

GAPGRI00356

RM0345

34/38 Doc ID 024080 Rev 3

RM0345

Figure 19.

Memory, CAN and connectors schematic

GND

2

5 3 5 3

1 3

PEN T=O UL FA DE

1 3

1 3

8

Vcc GND

4

E1

D6

VDD

VDD GND

GND

E6

D1

Schematic

GND

0

18

7 10

4

15

21

42

31

39

34

45

28

GAPGRI00357

Doc ID 024080 Rev 3 35/38

Options placement

Appendix D Options placement

Figure 20.

Options placement

TOP view

RM0345

Bottom view

36/38 Doc ID 024080 Rev 3

GAPGRI00358

RM0345

Revision history

Table 16.

Document revision history

Date Revision

18-Jan-2013

13-Feb-2013

17-Sep-2013

1

2

3

Initial release.

Modified Figure 14 .

Updated Disclaimer.

Changes

Revision history

Doc ID 024080 Rev 3 37/38

RM0345

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED

WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED

WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS

OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE

SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B)

AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS

OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT

PURCHASER’S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS

EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR “AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL” INDUSTRY

DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE

DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY.

Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.

ST and the ST logo are trademarks or registered trademarks of ST in various countries.

Information in this document supersedes and replaces all information previously supplied.

The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.

© 2013 STMicroelectronics - All rights reserved

STMicroelectronics group of companies

Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -

Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com

38/38 Doc ID 024080 Rev 3