ST Book E processors Reference Manual

RM0004
Reference manual
Programmer’s reference manual for Book E processors
Introduction
This reference manual gives an overview of Book E, a version of the PowerPC architecture
intended for embedded processors. To ensure application level compatibility with the
PowerPC architecture developed by Apple, IBM, and Freescale, Book E incorporates the
user level resources defined in the user instruction set architecture (UISA), Book I, of the
AIM architectural definition.
This reference manual is a reference document for the SPC560x and RPC560Bx devices
which are based on the PowerPC architecture.
May 2015
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1
Contents
RM0004
Contents
1
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1
1.2
2
About this book . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.1
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.1.2
Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Suggested reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.1
General information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.2
Related documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.2.3
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.3
Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.4
Terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5
Part I: Book E and Book E implementation standards . . . . . . . . . . . . . . . 31
1.6
Part II: EIS-defined extensions to the Book E architecture . . . . . . . . . . . 32
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1
Overview Book E and the Book E implementation standards (EIS) . . . . . 33
2.1.1
2.2
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.3
Register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.4
Interrupts and exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.5
2.6
2/1025
Auxiliary processing units (APUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.1
Exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.2
Interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.3
Interrupt categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.4.4
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.1
Address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.5.2
MMU assist registers (MAS1–MAS7) . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5.3
Process ID registers (PID0–PID2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.4
TLB coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.5
Atomic update memory references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.6
Memory access ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.5.7
Cache control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.5.8
Programmable page characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Performance monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
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2.7
3
2.6.1
Global control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6.2
Performance monitor counter registers . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.6.3
Local control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Legacy support of PowerPC architecture . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.7.1
Instruction set compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.7.2
Memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.7.3
Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.7.4
Memory management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.7.5
Requirements for system reset generation . . . . . . . . . . . . . . . . . . . . . . 45
2.7.6
Little-endian mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2
Register model for 32-bit Book E implementations . . . . . . . . . . . . . . . . . 47
3.2.1
3.3
3.4
3.5
3.6
Registers for integer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.3.1
General purpose registers (GPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.3.2
Integer exception register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Registers for floating-point operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4.1
Floating-point registers (FPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.4.2
Floating-point status and control register (FPSCR) . . . . . . . . . . . . . . . . 59
Registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5.1
Condition register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
3.5.2
Link register (LR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.5.3
Count register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Processor control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
3.6.1
3.7
3.8
Special-purpose registers (SPRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Machine state register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Hardware implementation-dependent registers . . . . . . . . . . . . . . . . . . . . 72
3.7.1
Hardware implementation dependent register 0 (HID0) . . . . . . . . . . . . 72
3.7.2
Hardware implementation dependent register 1 (HID1) . . . . . . . . . . . . 75
3.7.3
Processor ID register (PIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.7.4
Processor version register (PVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
3.7.5
System version register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
3.8.1
Timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.8.2
Timer status register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
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3.9
3.8.3
Time base (TBU and TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3.8.4
Decrementer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.8.5
Decrementer auto-reload register (DECAR) . . . . . . . . . . . . . . . . . . . . . 83
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.9.1
3.10
Software use sprs (SPRG0–SPRG7 and USPRG0) . . . . . . . . . . . . . . . . 92
3.11
L1 cache registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.12
3.13
3.14
4/1025
Interrupt registers defined by book E . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.11.1
L1 cache control and status register 0 (L1CSR0) . . . . . . . . . . . . . . . . . 92
3.11.2
L1 cache control and status register 1 (L1CSR1) . . . . . . . . . . . . . . . . . 94
3.11.3
L1 cache configuration register 0 (L1CFG0) . . . . . . . . . . . . . . . . . . . . . 96
3.11.4
L1 cache configuration register 1 (L1CFG1) . . . . . . . . . . . . . . . . . . . . . 97
3.11.5
L1 flush and invalidate control register 0 (L1FINV0) . . . . . . . . . . . . . . . 98
MMU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.12.1
Process ID registers (PID0–PIDn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.12.2
MMU control and status register 0 (MMUCSR0) . . . . . . . . . . . . . . . . . 100
3.12.3
MMU configuration register (MMUCFG) . . . . . . . . . . . . . . . . . . . . . . . 101
3.12.4
TLB configuration registers (TLBnCFG) . . . . . . . . . . . . . . . . . . . . . . . 102
3.12.5
MMU assist registers (MAS0–MAS7) . . . . . . . . . . . . . . . . . . . . . . . . . 103
Debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.13.1
Debug control registers (DBCR0–DBCR3) . . . . . . . . . . . . . . . . . . . . . 110
3.13.2
Debug status register (DBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.13.3
Instruction address compare registers (IAC1–IAC4) . . . . . . . . . . . . . . 118
3.13.4
Data address compare registers (DAC1–DAC2) . . . . . . . . . . . . . . . . . 119
3.13.5
Data value compare registers (DVC1 and DVC2) . . . . . . . . . . . . . . . . 119
SPE and SPFP APU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
3.14.1
Signal processing, embedded floating-point status, control register
(SPEFSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.14.2
Accumulator (ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.15
Alternate time base registers (ATBL and ATBU) . . . . . . . . . . . . . . . . . . 123
3.16
Performance monitor registers (PMRs) . . . . . . . . . . . . . . . . . . . . . . . . . 124
3.16.1
Global control register 0 (PMGC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.16.2
User global control register 0 (UPMGC0) . . . . . . . . . . . . . . . . . . . . . . 127
3.16.3
Local control A registers (PMLCa0–PMLCa3) . . . . . . . . . . . . . . . . . . . 127
3.16.4
User local control A registers (UPMLCa0–UPMLCa3) . . . . . . . . . . . . 128
3.16.5
Local control B registers (PMLCb0–PMLCb3) . . . . . . . . . . . . . . . . . . . 128
3.16.6
User local control B registers (UPMLCb0–UPMLCb3) . . . . . . . . . . . . 130
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Performance monitor counter registers (PMC0–PMC3) . . . . . . . . . . . 130
3.16.8
User performance monitor counter registers (UPMC0–UPMC3) . . . . . 130
3.17
Device control registers (DCRs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.18
Book E SPR model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.18.1
Invalid SPR references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
3.18.2
Synchronization requirements for SPRs . . . . . . . . . . . . . . . . . . . . . . . 131
3.18.3
Reserved SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
3.18.4
Allocated SPRs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.1
4.2
4.3
Operand conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
4.1.1
Data organization in memory and data transfers . . . . . . . . . . . . . . . . . 134
4.1.2
Alignment and misaligned accesses . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
4.2.1
Classes of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
4.2.2
Instruction forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.2.3
Addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Instruction set overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.3.1
Book E user-level instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
4.3.2
Supervisor level instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
4.3.3
Recommended simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . 188
4.3.4
Book E instructions with implementation-specific features . . . . . . . . . 188
4.3.5
EIS instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.3.6
Context synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.4
Instruction fetching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
4.5
Memory synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.6
EIS-specific instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
4.7
5
3.16.7
4.6.1
SPE and embedded floating-point APUs . . . . . . . . . . . . . . . . . . . . . . . 190
4.6.2
Integer select (isel) APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
4.6.3
Performance monitor APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
4.6.4
Cache locking APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
4.6.5
Machine check APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
4.6.6
VLE extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Instruction listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Interrupts and exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
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5.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
5.2
EIs interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
5.2.1
5.3
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
5.4
Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
5.5
Interrupt classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
5.5.1
6/1025
Requirements for system reset generation . . . . . . . . . . . . . . . . . . . . . 257
5.6
Interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
5.7
Interrupt definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
5.7.1
Critical input interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
5.7.2
Machine check interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
5.7.3
Data storage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
5.7.4
Instruction storage interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
5.7.5
External input interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
5.7.6
Alignment interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
5.7.7
Program interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
5.7.8
Floating-point unavailable interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
5.7.9
System call interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
5.7.10
Auxiliary processor unavailable interrupt . . . . . . . . . . . . . . . . . . . . . . . 271
5.7.11
Decrementer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
5.7.12
Fixed-interval timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
5.7.13
Watchdog timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.7.14
Data tlb error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
5.7.15
Instruction tlb error interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
5.7.16
Debug interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
5.7.17
EIS-defined interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
5.8
Performance monitor interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.9
Partially executed instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
5.10
Interrupt ordering and masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
5.11
6
Recoverability from interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
5.10.1
Guidelines for system software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
5.10.2
Interrupt order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Storage architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
6.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
6.2
Memory and cache coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
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6.3
6.4
7
Memory/Cache access attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
6.2.2
Shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Cache model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.3.1
Cache programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
6.3.2
Primary (L1) cache model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Storage model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
6.4.1
Storage programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
6.4.2
The storage architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.4.3
Virtual address (VA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
6.4.4
Address spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
6.4.5
Process ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
6.4.6
Address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
6.4.7
Address translation and the ST EIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.4.8
Permission attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.4.9
Translation lookaside buffer (TLB) arrays . . . . . . . . . . . . . . . . . . . . . . 321
6.4.10
TLB management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
6.4.11
MAS registers and exception handling . . . . . . . . . . . . . . . . . . . . . . . . 329
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
7.1
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
7.2
Instruction fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
7.3
Description of instruction operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
7.4
8
6.2.1
7.3.1
SPE APU saturation and bit-reverse models . . . . . . . . . . . . . . . . . . . . 340
7.3.2
Embedded floating-point conversion models . . . . . . . . . . . . . . . . . . . . 341
7.3.3
Integer saturation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
7.3.4
Embedded floating-point results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Auxiliary processing units (APUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
8.1
8.2
Integer select APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
8.1.1
Integer select APU programming model . . . . . . . . . . . . . . . . . . . . . . . 667
8.1.2
Using isel to Improve conditional branch performance . . . . . . . . . . . . 668
Performance monitor APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
8.2.1
8.3
Performance monitor APU programming model . . . . . . . . . . . . . . . . . 668
Signal processing engine APU (SPE APU) . . . . . . . . . . . . . . . . . . . . . . 670
8.3.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
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8.4
8.5
8.3.2
Nomenclature and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
8.3.3
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671
8.3.4
Instruction definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Embedded vector and scalar single-precision floating-point APUs (SPFP
APUs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
8.4.1
Nomenclature and conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
8.4.2
Embedded floating-point APUs programming model . . . . . . . . . . . . . . 676
8.4.3
Embedded floating-point APU operations . . . . . . . . . . . . . . . . . . . . . . 683
8.4.4
Implementation options summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686
Machine check APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
8.5.1
8.6
8.7
Debug APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
8.6.1
Debug APU programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
8.6.2
Debug APU register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
8.6.3
Debug APU instruction model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Alternate time base . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
8.7.1
9
Cache line locking APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
9.1.1
9.2
9.3
11
8/1025
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690
Storage-related APUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
9.1
10
Machine check APU programming model . . . . . . . . . . . . . . . . . . . . . . 687
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692
Direct cache flush APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
9.2.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
9.2.2
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694
Cache way partitioning APU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
9.3.1
Programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
9.3.2
Interaction with the cache locking APU . . . . . . . . . . . . . . . . . . . . . . . . 695
VLE introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
10.1
Compatibility with PowerPC Book E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697
10.2
Instruction mnemonics and operands . . . . . . . . . . . . . . . . . . . . . . . . . . 698
VLE storage addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
11.1
Data memory addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
11.2
Instruction memory addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . 699
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VLE compatibility with the EIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
12.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
12.2
VLE extension processor and storage control extensions . . . . . . . . . . . 701
EIS instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
12.2.2
Book E instruction extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
12.2.3
EIS MMU extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
12.2.4
EIS debug APU extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
VLE instruction classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
13.1
13.2
Processor control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
13.1.1
System linkage instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
13.1.2
Processor control register manipulation instructions . . . . . . . . . . . . . . 705
13.1.3
Instruction synchronization instruction . . . . . . . . . . . . . . . . . . . . . . . . . 706
Branch operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
13.2.1
Registers for branch operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
13.2.2
Branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
13.3
Condition register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
13.4
Integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .711
13.5
13.6
14
12.2.1
13.4.1
Integer load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
13.4.2
Integer store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
13.4.3
Integer arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
13.4.4
Integer logical and move instructions . . . . . . . . . . . . . . . . . . . . . . . . . 715
13.4.5
Integer compare and bit test instructions . . . . . . . . . . . . . . . . . . . . . . . 717
13.4.6
Integer select instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
13.4.7
Integer trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
13.4.8
Integer rotate and shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Storage control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
13.5.1
Storage synchronization instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 721
13.5.2
Cache management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
13.5.3
TLB management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
13.5.4
Instruction alignment and byte ordering . . . . . . . . . . . . . . . . . . . . . . . . 722
Instruction listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
VLE instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
14.1
Book E– and EIS-defined instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 736
14.2
Immediate field and displacement field encodings . . . . . . . . . . . . . . . . . 740
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VLE instruction index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
15.1
Instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
15.2
Instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . 798
15.3
Instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
15.4
Instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . 834
Appendix A
Instruction set listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850
A.1
Instructions sorted by mnemonic (decimal and hexadecimal). . . . . . . . . 850
A.2
Instructions sorted by primary opcodes (decimal and hexadecimal). . . . 884
A.3
Instructions sorted by mnemonic (binary) . . . . . . . . . . . . . . . . . . . . . . . . 903
A.4
Instructions sorted by opcode (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . 930
A.5
Instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
Appendix B Simplified mnemonics for PowerPC instructions. . . . . . . . . . . . . 963
B.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
B.2
Subtract simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
B.3
B.2.1
Subtract immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 963
B.2.2
Subtract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Rotate and shift simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . 964
B.3.1
B.4
10/1025
Operations on words. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Branch instruction simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . 965
B.4.1
Key facts about simplified branch mnemonics . . . . . . . . . . . . . . . . . . . 967
B.4.2
Eliminating the BO operand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
B.4.3
Incorporating the BO branch prediction . . . . . . . . . . . . . . . . . . . . . . . . 969
B.4.4
The BI operand—CR bit and field representations . . . . . . . . . . . . . . . . 969
B.4.5
Simplified mnemonics that incorporate the BO operand . . . . . . . . . . . 973
B.4.6
Simplified mnemonics that incorporate CR conditions (eliminates BO and
replaces BI with crS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
B.5
Compare word simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
B.6
Condition register logical simplified mnemonics . . . . . . . . . . . . . . . . . . . 981
B.7
Trap instructions simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . 982
B.8
Simplified mnemonics for accessing SPRs . . . . . . . . . . . . . . . . . . . . . . . 983
B.9
Recommended simplified mnemonics. . . . . . . . . . . . . . . . . . . . . . . . . . . 984
B.9.1
No-op (nop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
B.9.2
Load immediate (li). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 984
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B.10
B.11
B.9.3
Load address (la) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
B.9.4
Move register (mr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
B.9.5
Complement register (not) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
B.9.6
Move to condition register (mtcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
EIS-specific simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
B.10.1
Integer select (isel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
B.10.2
SPE mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Comprehensive list of simplified mnemonics . . . . . . . . . . . . . . . . . . . . . 986
Appendix C Programming examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
C.1
Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
C.1.1
Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
C.1.2
Lock acquisition and release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
C.1.3
List insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
C.1.4
Synchronization notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 999
C.2
Multiple-precision shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
C.3
Floating point conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
C.4
C.3.1
Conversion from floating-point number to signed integer word . . . . . 1002
C.3.2
Conversion from floating-point number to unsigned integer word . . . 1003
Floating point selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
C.4.1
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Appendix D Guidelines for 32-bit book E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1006
D.1
Registers on 32-bit book E implementations. . . . . . . . . . . . . . . . . . . . . 1006
D.2
Addressing on 32-bit book E implementations . . . . . . . . . . . . . . . . . . . 1006
D.3
TLB fields on 32-bit book E implementations . . . . . . . . . . . . . . . . . . . . 1006
D.4
32-bit book E software guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Appendix E
D.4.1
32-bit instruction selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
D.4.2
32-bit addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
Embedded floating-point results . . . . . . . . . . . . . . . . . . . . . . . . . 1008
E.1
Notation conventions and general rules . . . . . . . . . . . . . . . . . . . . . . . . 1008
E.2
Add, subtract, multiply, and divide results . . . . . . . . . . . . . . . . . . . . . . . 1009
E.3
Double- to single-precision conversion . . . . . . . . . . . . . . . . . . . . . . . . . 1012
E.4
Single- to double-precision conversion . . . . . . . . . . . . . . . . . . . . . . . . . 1013
E.5
Conversion to unsigned. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
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E.6
Conversion to signed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
E.7
Conversion from unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
E.8
Conversion from signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
E.9
*abs, *nabs, and *neg operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
12/1025
DocID13694 Rev 2
RM0004
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Acronyms and abbreviated terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Terminology conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Instruction field conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interrupt vector registers and exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Book E special purpose registers (by SPR abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . 50
EIS–defined SPRs (by SPR abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
XER field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
FPSCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Floating-point result flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
BI operand settings for CR fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
CR0 bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
CR setting for floating-point instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CR setting for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
CR0 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Condition register setting for compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Branch to link register instruction comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Branch to count register instruction comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Floating-point exception bits—MSR[FE0,FE1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
HID0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PVR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
TCR field descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
TSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
IVOR assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Exception syndrome register (ESR) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MCSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
L1CSR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
L1CSR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
L1CFG0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
L1CFG1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
L1FINV0 fields—L1 direct cache flush . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
MMUCSR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
MMUCFG field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TLBnCFG field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
MAS0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MAS1 field descriptions—descriptor context and configuration control . . . . . . . . . . . . . . 104
MAS2 field descriptions—EPN and page attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
MAS3 field descriptions–RPN and access control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
MAS4 field descriptions—hardware replacement assist configuration . . . . . . . . . . . . . . . 107
MAS5 field descriptions—extended search pIDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MAS 6 field descriptions—search pids and search AS. . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MAS 7 field descriptions—high order RPN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DBCR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
DBCR1 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
DBCR2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
DBSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DocID13694 Rev 2
13/1025
19
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
Table 85.
Table 86.
Table 87.
Table 88.
Table 89.
Table 90.
Table 91.
Table 92.
Table 93.
Table 94.
Table 95.
Table 96.
Table 97.
Table 98.
Table 99.
Table 100.
14/1025
RM0004
SPEFSCR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
ATBL field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
ATBU field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Performance monitor registers—supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Performance monitor registers—user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PMGC0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PMLCa0–PMLCa3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
PMLCb0 –PMLCb3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
PMC0–PMC3 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
System response to an invalid spr reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Synchronization requirements for sprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Allocated SPRs defined by the EIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Address characteristics of aligned operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Allocated instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Preserved instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Synchronization requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Integer arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Integer 32-Bit compare instructions (L = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Integer logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Integer rotate instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Integer shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Floating-point load instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Floating-point store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Floating-point move instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Floating-point elementary arithmetic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Floating-point multiply-add instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Floating-point rounding and conversion instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
CR field settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Floating-point compare and select instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Floating-point status and control register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Integer load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Integer store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Integer load and store with byte-reverse instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Integer load and store multiple instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Integer load and store string instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Floating-point load instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Floating-point store instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Store floating-point single behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Store floating-point double behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
BO bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
BO operand encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Condition register logical instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
System linkage instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Move to/from condition register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Move to/from special-purpose register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Book E special-purpose registers (by SPR abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . 173
Implementation-specific SPRs (by SPR abbreviation) . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Memory synchronization instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
User-level cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
System linkage instructions—supervisor-level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
DocID13694 Rev 2
RM0004
Table 101.
Table 102.
Table 103.
Table 104.
Table 105.
Table 106.
Table 107.
Table 108.
Table 109.
Table 110.
Table 111.
Table 112.
Table 113.
Table 114.
Table 115.
Table 116.
Table 117.
Table 118.
Table 119.
Table 120.
Table 121.
Table 122.
Table 123.
Table 124.
Table 125.
Table 126.
Table 127.
Table 128.
Table 129.
Table 130.
Table 131.
Table 132.
Table 133.
Table 134.
Table 135.
Table 136.
Table 137.
Table 138.
Table 139.
Table 140.
Table 141.
Table 142.
Table 143.
Table 144.
Table 145.
Table 146.
Table 147.
Table 148.
Table 149.
Table 150.
Table 151.
Table 152.
List of tables
Move to/from machine state register instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Supervisor-Level cache management instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
TLB management instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Implementation-specific instructions summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
EIS-defined instructions (except SPE and SPFP instructions) . . . . . . . . . . . . . . . . . . . . . 189
SPE APU vector multiply instruction mnemonic structure . . . . . . . . . . . . . . . . . . . . . . . . 192
Mnemonic extensions for multiply-accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . 192
SPE APU vector instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Vector and scalar floating-point APU instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Integer select APU instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Performance monitor APU instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Performance monitor registers—supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Performance monitor registers—user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Cache locking APU instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Machine check APU instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
System linkage instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
System register manipulation instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Instruction Synchronization Instruction Set Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
VLE extension BO32 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
VLE extension BO16 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Branch instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Condition register instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Basic integer load instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Integer load byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Integer load multiple instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Integer load and reserve instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Basic integer store instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Integer store byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Integer store multiple instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Integer store conditional instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Integer arithmetic instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Integer logical instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
CR settings for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
CR settings for integer bit test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Integer compare and bit test instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Integer select instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Integer trap conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Integer trap instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Integer rotate instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Integer rotate with mask instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Integer shift instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Storage synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Cache management instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
TLB management instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Instructions listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
List of instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
Interrupt types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Interrupt registers defined by the PowerPC architecture . . . . . . . . . . . . . . . . . . . . . . . . . 253
Asynchronous and synchronous interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Interrupt and exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
Critical input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
DocID13694 Rev 2
15/1025
19
List of tables
Table 153.
Table 154.
Table 155.
Table 156.
Table 157.
Table 158.
Table 159.
Table 160.
Table 161.
Table 162.
Table 163.
Table 164.
Table 165.
Table 166.
Table 167.
Table 168.
Table 169.
Table 170.
Table 171.
Table 172.
Table 173.
Table 174.
Table 175.
Table 176.
Table 177.
Table 178.
Table 179.
Table 180.
Table 181.
Table 182.
Table 183.
Table 184.
Table 185.
Table 186.
Table 187.
Table 188.
Table 189.
Table 190.
Table 191.
Table 192.
Table 193.
Table 194.
Table 195.
Table 196.
Table 197.
Table 198.
Table 199.
Table 200.
Table 201.
Table 202.
Table 203.
Table 204.
16/1025
RM0004
Machine check interrupt settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Data storage interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Data Storage Interrupt Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Instruction storage interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Instruction storage interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
External input interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Alignment interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
Program interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
MSR[FE0,FE1] settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Program interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Floating-point unavailable interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
System call interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
Auxiliary processor unavailable interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . 271
Decrementer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Fixed-interval timer interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
Watchdog timer interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Data tlb error interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Data tlb error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Instruction TLB error interrupt exception conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Instruction TLB error interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Debug interrupt register settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
SPE/embedded floating-point APU unavailable interrupt register settings . . . . . . . . . . . . 276
Embedded floating-point data interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . . 276
Embedded floating-point round interrupt register settings . . . . . . . . . . . . . . . . . . . . . . . . 277
Operations to avoid. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
EIS asynchronous exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
EIS synchronous exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
Load and store ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Memory barrier when coherency is required (M = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Cumulative memory barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
Storage related MSR fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Exception syndrome register (ESR) definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Page size and EPN field comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Real address generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Permission control for instruction, data read, and data write accesses . . . . . . . . . . . . . . 319
Permission control and cache instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
TLB entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Fields for EA format of tlbivax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
MAS register update summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
MAS settings for an instruction or data TLB error interrupt. . . . . . . . . . . . . . . . . . . . . . . . 330
MAS settings for permissions violation ISI or DSI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
MMU assist register field updates—EIS definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Notation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Instruction field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
RTL notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
Operator precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
Conversion models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
BI operand settings for CR fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
BI operand settings for CR fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
BI operand settings for CR fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
Data samples and sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
DocID13694 Rev 2
RM0004
Table 205.
Table 206.
Table 207.
Table 208.
Table 209.
Table 210.
Table 211.
Table 212.
Table 213.
Table 214.
Table 215.
Table 216.
Table 217.
Table 218.
Table 219.
Table 220.
Table 221.
Table 222.
Table 223.
Table 224.
Table 225.
Table 226.
Table 227.
Table 228.
Table 229.
Table 230.
Table 231.
Table 232.
Table 233.
Table 234.
Table 235.
Table 236.
Table 237.
Table 238.
Table 239.
Table 240.
Table 241.
Table 242.
Table 243.
Table 244.
Table 245.
Table 246.
Table 247.
Table 248.
Table 249.
Table 250.
Table 251.
Table 252.
Table 253.
Table 254.
Table 255.
Table 256.
List of tables
Operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
Operations with special values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593
Effect of SPRN[5] and MSR[PR]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Recoding with isel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668
Performance monitor registers—supervisor level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Performance monitor registers—user level (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . 669
Performance monitor apu instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670
Mnemonic extensions for multiply accumulate instructions . . . . . . . . . . . . . . . . . . . . . . . 674
Embedded vector floating-point instruction opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
Embedded scalar single-precision floating-point instruction opcodes . . . . . . . . . . . . . . . 678
Embedded scalar double-precision floating-point instruction opcodes . . . . . . . . . . . . . . . 678
EIS-defined DBSR field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
DBCR0 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Data storage addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Instruction storage addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
TLB Entry 0 reset value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
MAS2 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
MAS4 field descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
System linkage instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
System register manipulation instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
Instruction Synchronization Instruction Set Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
CR0 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
Condition register setting for compare instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Branch to link register instruction comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708
Branch to count register instruction comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
VLE extension BO32 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
VLE extension BO16 encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Branch instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Condition register instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710
Basic integer load instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711
Integer Load Byte-Reverse Instruction Set Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Integer load multiple instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Integer load and reserve instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
Basic integer store instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Integer store byte-reverse instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Integer store multiple instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Integer store conditional instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713
Integer arithmetic instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
Integer logical instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716
CR settings for compare instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717
CR settings for integer bit test instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Integer compare and bit test instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Integer select instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718
Integer trap conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Integer trap instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719
Integer rotate instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Integer rotate with mask instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Integer shift instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
Storage synchronization instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
Cache management instruction set index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721
TLB management instruction set index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
Instructions listed by name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723
DocID13694 Rev 2
17/1025
19
List of tables
Table 257.
Table 258.
Table 259.
Table 260.
Table 261.
Table 262.
Table 263.
Table 264.
Table 265.
Table 266.
Table 267.
Table 268.
Table 269.
Table 270.
Table 271.
Table 272.
Table 273.
Table 274.
Table 275.
Table 276.
Table 277.
Table 278.
Table 279.
Table 280.
Table 281.
Table 282.
Table 283.
Table 284.
Table 285.
Table 286.
Table 287.
Table 288.
Table 289.
Table 290.
Table 291.
Table 292.
Table 293.
Table 294.
Table 295.
Table 296.
Table 297.
Table 298.
Table 299.
Table 300.
Table 301.
Table 302.
Table 303.
Table 304.
Table 305.
Table 306.
Table 307.
Table 308.
18/1025
RM0004
Instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729
Book E– and EIS-defined instructions listed by mnemonic . . . . . . . . . . . . . . . . . . . . . . . 736
Immediate field and displacement field encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Notation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
Instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778
32-bit instruction encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782
16-Bit VLE instructions sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798
32-bit instruction encodings (by mnemonic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802
Instruction index sorted by opcode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
32-bit instruction encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
Instruction index sorted by mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834
32-bit instructions by mnemonic (ignoring the e_ prefix) . . . . . . . . . . . . . . . . . . . . . . . . . 838
Instructions sorted by mnemonic (decimal and hexadecimal) . . . . . . . . . . . . . . . . . . . . . 851
Instructions sorted by primary opcodes (decimal and hexadecimal) . . . . . . . . . . . . . . . . 885
Instructions sorted by mnemonic (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904
Instructions sorted by opcode (binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 931
PowerPC instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951
PowerPC instruction set legend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 956
Subtract immediate simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Subtract simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 964
Word rotate and shift simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
BO bit encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967
BO operand encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 968
CR0 and CR1 fields as updated by integer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 971
BI operand settings for CR fields for branch comparisons . . . . . . . . . . . . . . . . . . . . . . . . 971
CR field identification symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Branch simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
Simplified mnemonics for bc and bca without LR update . . . . . . . . . . . . . . . . . . . . . . . . 974
Simplified mnemonics for bclr and bcctr without LR update . . . . . . . . . . . . . . . . . . . . . . 975
Simplified mnemonics for bcl and bcla with LR update . . . . . . . . . . . . . . . . . . . . . . . . . . 975
Simplified mnemonics for bclrl and bcctrl with LR update . . . . . . . . . . . . . . . . . . . . . . . 976
Standard coding for branch conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 976
Branch instructions and simplified mnemonics that incorporate CR conditions . . . . . . . . 977
Simplified mnemonics with comparison conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
Simplified mnemonics for bc and bca without comparison conditions or LR Update. . . . 978
Simplified mnemonics for bclr and bcctr without comparison conditions or LR update . 979
Simplified mnemonics for bcl and bcla with comparison conditions, LR update . . . . . . . 979
Simplified mnemonics for bclrl and bcctrl with comparison conditions, LR update. . . . . 980
Word compare simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 980
Condition register logical simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981
Standard codes for trap instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
Trap simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 982
TO operand bit encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Additional simplified mnemonics for accessing SPRGs . . . . . . . . . . . . . . . . . . . . . . . . . . 984
Simplified mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
Shifts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000
Comparison to zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Minimum and maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Simple if-then-else constructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Notation conventions and general rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
DocID13694 Rev 2
RM0004
Table 309.
Table 310.
Table 311.
Table 312.
Table 313.
Table 314.
Table 315.
Table 316.
Table 317.
Table 318.
List of tables
Floating-point results summary—add, sub, mul, div . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
Floating-point results summary—single convert from double . . . . . . . . . . . . . . . . . . . . . 1012
Floating-point results summary—double convert from single . . . . . . . . . . . . . . . . . . . . . 1013
Floating-point results summary—convert to unsigned . . . . . . . . . . . . . . . . . . . . . . . . . . 1013
Floating-point results summary—convert to signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Floating-point results summary—convert from unsigned . . . . . . . . . . . . . . . . . . . . . . . . 1014
Floating-point results summary—convert from signed . . . . . . . . . . . . . . . . . . . . . . . . . . 1014
Floating-point results summary—*abs, *nabs, *neg . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1024
DocID13694 Rev 2
19/1025
19
List of figures
RM0004
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
20/1025
EIS programming model register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Effective-to-Real Address Translation Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Register model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
SPE and floating point APU GPR usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Integer exception register (XER) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Floating-point status and control register (FPSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Condition register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Link register (LR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Count register (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Machine state register (MSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Hardware implementation dependent register 0 (HID0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Hardware implementation dependent register 1 (HID1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Processor ID register (PIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Processor version register (PVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
System version register (SVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Relationship of timer facilities to the time base. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Timer control register (TCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Timer status register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Time base upper/lower registers (TBU/TBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Decrementer register (DEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Decrementer auto-reload register (DECAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Save/restore register 0 (SRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Save/restore register 1 (SRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Critical save/restore register 0 (CSRR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Critical save/restore register 1 (CSRR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Data exception address register (DEAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt vector prefix register (IVPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Interrupt vector offset registers (IVOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Exception syndrome register (ESR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Debug save/restore register 0 (DSRR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Debug save/restore register 1 (DSRR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Machine check save/restore register 0 (MCSRR0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Machine check save/restore register 1 (MCSRR1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Machine check address register (MCAR/MCARU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Machine check syndrome register 1 (MCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Software-use sprs (SPRG0–SPRG7 and USPRG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
L1 cache control and status register 0 (L1CSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
L1 cache control and status register 1 (L1CSR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
L1 cache configuration register 0 (L1CFG0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
L1 cache configuration register 1 (L1CFG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
L1 flush and invalidate control register 0 (L1FINV0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Process ID registers (PID0–PID2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
MMU control and status register 0 (MMUCSR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
MMU configuration register 1 (MMUCFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TLB configuration register n (TLB0CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
MAS register 0 (MAS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MAS register 1 (MAS1) format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MAS register 2 (MAS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
DocID13694 Rev 2
RM0004
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
Figure 76.
Figure 77.
Figure 78.
Figure 79.
Figure 80.
Figure 81.
Figure 82.
Figure 83.
Figure 84.
Figure 85.
Figure 86.
Figure 87.
Figure 88.
Figure 89.
Figure 90.
Figure 91.
Figure 92.
Figure 93.
Figure 94.
Figure 95.
Figure 96.
Figure 97.
Figure 98.
Figure 99.
Figure 100.
List of figures
MAS register 3 (MAS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
MAS register 4 (MAS4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
MAS register 5 (MAS5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MAS register 6 (MAS6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MAS register 7 (MAS7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Debug control register 0 (DBCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Debug control register 1 (DBCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Debug control register 2 (DBCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Debug control register 3 (DBCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Debug status register (DBSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Instruction address compare registers (IAC1–IAC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Data address compare registers (DAC1–DAC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Data value compare registers (DVC1–DVC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Signal processing, embedded floating-point status and control register (SPEFSCR) . . . 120
Alternate time base register lower (ATBL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Alternate time base register upper (ATBU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Global control register 0 (PMGC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Local control A registers (PMLCa0–PMLCa3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Local control B registers (PMLCb0–PMLCb3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Performance monitor counter registers (PMC0–PMC3) . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Register indirect with immediate index addressing for integer loads/stores . . . . . . . . . . . 159
Register indirect with index addressing for integer loads/stores. . . . . . . . . . . . . . . . . . . . 160
Register indirect addressing for integer loads/stores . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Branch relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Branch conditional relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Branch to absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Branch conditional to absolute addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Branch conditional to link register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Branch conditional to count register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Integer and fractional operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Virtual Address Space in Book E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Current address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
Current PID Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Virtual address and TLB-entry comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Effective-to-real address translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
Granting of Access Permission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
TLBs accessed through MAS registers and TLB instructions. . . . . . . . . . . . . . . . . . . . . . 324
Instruction description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
Vector absolute value (evabs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Vector add immediate word (evaddiw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Vector add signed, modulo, integer to accumulator word (evaddsmiaaw) . . . . . . . . . . . 418
Vector add signed, saturate, integer to accumulator word (evaddssiaaw) . . . . . . . . . . . 419
Vector add unsigned, modulo, integer to accumulator word (evaddumiaaw) . . . . . . . . . 420
Vector add unsigned, saturate, integer to accumulator word (evaddusiaaw) . . . . . . . . . 421
Vector add word (evaddw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
Vector AND (evand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
Vector AND with complement (evandc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
Vector Compare Equal (evcmpeq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
Vector compare greater than signed (evcmpgts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
Vector compare greater than unsigned (evcmpgtu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
Vector compare less than signed (evcmplts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
Vector compare less than unsigned (evcmpltu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
DocID13694 Rev 2
21/1025
24
List of figures
Figure 101.
Figure 102.
Figure 103.
Figure 104.
Figure 105.
Figure 106.
Figure 107.
Figure 108.
Figure 109.
Figure 110.
Figure 111.
Figure 112.
Figure 113.
Figure 114.
Figure 115.
Figure 116.
Figure 117.
Figure 118.
Figure 119.
Figure 120.
Figure 121.
Figure 122.
Figure 123.
Figure 124.
Figure 125.
Figure 126.
Figure 127.
Figure 128.
Figure 129.
Figure 130.
Figure 131.
Figure 132.
Figure 133.
Figure 134.
Figure 135.
Figure 136.
Figure 137.
Figure 138.
Figure 139.
Figure 140.
Figure 141.
Figure 142.
Figure 143.
Figure 144.
Figure 145.
Figure 146.
Figure 147.
Figure 148.
Figure 149.
Figure 150.
Figure 151.
22/1025
RM0004
Vector count leading signed bits word (evcntlsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
Vector count leading zeros word (evcntlzw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
Vector divide word signed (evdivws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
Vector divide word unsigned (evdivwu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Vector equivalent (eveqv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
Vector extend sign byte (evextsb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
Vector extend sign half word (evextsh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
evldd results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
evlddx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
evldh Results in Big- and Little-Endian Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
evldhx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
evldw results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
evldwx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
evlhhesplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
evlhhesplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
evlhhossplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
evlhhossplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
evlhhousplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
evlhhousplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
evlwhe results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
evlwhex results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
evlwhos results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
evlwhosx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
evlwhou results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
evlwhoux results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460
evlwhsplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
evlwhsplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
evlwwsplat results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
evlwwsplatx results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
High order element merging (evmergehi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
High order element merging (evmergehilo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
Low order element merging (evmergelo). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
Low order element merging (evmergelohi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
evmhegsmfaa (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
evmhegsmfan (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
evmhegsmiaa (even form). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
evmhegsmian (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
evmhegumiaa (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
evmhegumian (even form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472
Even multiply of two signed modulo fractional elements (to accumulator) (evmhesmf) . 473
Even form of vector half-word multiply (evmhesmfaaw) . . . . . . . . . . . . . . . . . . . . . . . . . 474
Even form of vector half-word multiply (evmhesmfanw) . . . . . . . . . . . . . . . . . . . . . . . . . 475
Even form for vector multiply (to accumulator) (evmhesmi) . . . . . . . . . . . . . . . . . . . . . . 476
Even form of vector half-word multiply (evmhesmiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . 477
Even form of vector half-word multiply (evmhesmianw) . . . . . . . . . . . . . . . . . . . . . . . . . 478
Even multiply of two signed saturate fractional elements (to accumulator) (evmhessf) . 479
Even form of vector half-word multiply (evmhessfaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 480
Even form of vector half-word multiply (evmhessfanw). . . . . . . . . . . . . . . . . . . . . . . . . . 481
Even form of vector half-word multiply (evmhessiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 482
Even form of vector half-word multiply (evmhessianw) . . . . . . . . . . . . . . . . . . . . . . . . . . 483
Vector multiply half words, even, unsigned, modulo, integer (to accumulator) (evmheumi) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
DocID13694 Rev 2
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Figure 152.
Figure 153.
Figure 154.
Figure 155.
Figure 156.
Figure 157.
Figure 158.
Figure 159.
Figure 160.
Figure 161.
Figure 162.
Figure 163.
Figure 164.
Figure 165.
Figure 166.
Figure 167.
Figure 168.
Figure 169.
Figure 170.
Figure 171.
Figure 172.
Figure 173.
Figure 174.
Figure 175.
Figure 176.
Figure 177.
Figure 178.
Figure 179.
Figure 180.
Figure 181.
Figure 182.
Figure 183.
Figure 184.
Figure 185.
Figure 186.
Figure 187.
Figure 188.
Figure 189.
Figure 190.
Figure 191.
Figure 192.
List of figures
Even form of vector half-word multiply (evmheumiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . 485
Even form of vector half-word multiply (evmheumianw) . . . . . . . . . . . . . . . . . . . . . . . . . 486
Even form of vector half-word multiply (evmheusiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 487
Even form of vector half-word multiply (evmheusianw). . . . . . . . . . . . . . . . . . . . . . . . . . 489
evmhogsmfaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
evmhogsmfan (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
evmhogsmiaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
evmhogsmian (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
evmhogumiaa (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
evmhogumian (odd form) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
Vector multiply half words, odd, signed, modulo, fractional (to accumulator) (evmhosmf) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
Odd form of vector half-word multiply (evmhosmfaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 497
Odd form of vector half-word multiply (evmhosmfanw). . . . . . . . . . . . . . . . . . . . . . . . . . 498
Vector multiply half words, odd, signed, modulo, integer (to accumulator) (evmhosmi) . 499
Odd form of vector half-word multiply (evmhosmiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 500
Odd form of vector half-word multiply (evmhosmianw) . . . . . . . . . . . . . . . . . . . . . . . . . . 501
Vector multiply half words, odd, signed, saturate, fractional (to accumulator) (evmhossf) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
Odd form of vector half-word multiply (evmhossfaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 504
odd Form of Vector Half-Word Multiply (evmhossfanw) . . . . . . . . . . . . . . . . . . . . . . . . . 505
Odd form of vector half-word multiply (evmhossiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Odd form of vector half-word multiply (evmhossianw) . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Vector multiply half words, odd, unsigned, modulo, integer (to accumulator) (evmhoumi) . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Odd form of vector half-word multiply (evmhoumiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 510
Odd form of vector half-word multiply (evmhoumianw). . . . . . . . . . . . . . . . . . . . . . . . . . 511
Odd form of vector half-word multiply (evmhousiaaw) . . . . . . . . . . . . . . . . . . . . . . . . . . 512
Odd form of vector half-word multiply (evmhousianw) . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Initialize accumulator (evmra) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
Vector multiply word high signed, modulo, fractional (to accumulator) (evmwhsmf). . . . 515
Vector multiply word high signed, modulo, integer (to accumulator) (evmwhsm) . . . . . . 516
Vector multiply word high signed, saturate, fractional (to accumulator) (evmwhssf). . . . 518
Vector multiply word high unsigned, modulo, integer (to accumulator) (evmwhumi) . . . 519
Vector multiply word low signed, modulo, integer & accumulate in words (evmwlsmiaaw) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
Vector multiply word low signed, modulo, integer and accumulate negative in words (evm
wlsmianw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
Vector multiply word low signed, saturate, integer & accumulate in words (evmwlssiaaw) .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
Vector multiply word low signed, saturate, integer & accumulate negative in words (evmwls
sianw). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
Vector multiply word low unsigned, modulo, integer (evmwlumi) . . . . . . . . . . . . . . . . . . 524
Vector multiply word low unsigned, modulo, integer & accumulate in words (evmwlumiaaw)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Vector multiply word low unsigned, modulo, integer & accumulate negative in words (evm
wlumianw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526
Vector multiply word low unsigned, saturate, integer & accumulate in words (evmwlusiaaw)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528
Vector multiply word low unsigned, saturate, integer & accumulate negative in words (evm
wlusianw). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
Vector multiply word signed, modulo, fractional (to accumulator) (evmwsmf). . . . . . . . . 530
DocID13694 Rev 2
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List of figures
Figure 193.
Figure 194.
Figure 195.
Figure 196.
Figure 197.
Figure 198.
Figure 199.
Figure 200.
Figure 201.
Figure 202.
Figure 203.
Figure 204.
Figure 205.
Figure 206.
Figure 207.
Figure 208.
Figure 209.
Figure 210.
Figure 211.
Figure 212.
Figure 213.
Figure 214.
Figure 215.
Figure 216.
Figure 217.
Figure 218.
Figure 219.
Figure 220.
Figure 221.
Figure 222.
Figure 223.
Figure 224.
Figure 225.
Figure 226.
Figure 227.
Figure 228.
Figure 229.
Figure 230.
Figure 231.
Figure 232.
Figure 233.
Figure 234.
Figure 235.
Figure 236.
Figure 237.
Figure 238.
Figure 239.
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Figure 243.
Figure 244.
24/1025
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Vector multiply word signed, modulo, fractional & accumulate (evmwsmfaa) . . . . . . . . . 531
Vector multiply word signed, modulo, fractional & accumulate negative (evmwsmfan) . 532
Vector multiply word signed, modulo, integer (to accumulator) (evmwsmi). . . . . . . . . . . 533
Vector multiply word signed, modulo, integer & accumulate (evmwsmiaa). . . . . . . . . . . 534
Vector multiply word signed, modulo, integer & accumulate negative (evmwsmian) . . . 535
Vector multiply word signed, saturate, fractional (to accumulator) (evmwssf). . . . . . . . . 536
Vector multiply word signed, saturate, fractional, & accumulate (evmwssfaa) . . . . . . . . 537
Vector multiply word signed, saturate, fractional & accumulate negative (evmwssfan) . 538
Vector multiply word unsigned, modulo, integer (to accumulator) (evmwumi) . . . . . . . . 539
Vector multiply word unsigned, modulo, integer & accumulate (evmwumiaa). . . . . . . . . 540
Vector multiply word unsigned, modulo, integer & accumulate negative (evmwumian) . 541
Vector NAND (evnand) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Vector negate (evneg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542
Vector NOR (evnor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543
Vector OR (evor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544
Vector OR with complement (evorc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
Vector rotate left word (evrlw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Vector rotate left word immediate (evrlwi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
Vector round word (evrndw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547
Vector select (evsel). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548
Vector shift left word (evslw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Vector shift left word immediate (evslwi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Vector splat fractional immediate (evsplatfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
evsplati sign extend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Vector shift right word immediate signed (evsrwis) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
Vector shift right word immediate unsigned (evsrwiu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
Vector shift right word signed (evsrws) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
Vector shift right word unsigned (evsrwu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
evstdd results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
evstddx Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
evstdh Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556
evstdhx Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557
evstdw results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
evstdwx Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
evstwhe Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559
evstwhex Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560
evstwho Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
evstwhox Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
evstwwe Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
evstwwex Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563
evstwwo Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
evstwwox Results in big- and little-endian modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564
Vector subtract signed, modulo, integer to accumulator word (evsubfsmiaaw) . . . . . . . 565
Vector subtract signed, saturate, integer to accumulator word (evsubfssiaaw) . . . . . . . 566
Vector subtract unsigned, modulo, integer to accumulator word (evsubfumiaaw) . . . . . 567
Vector subtract unsigned, saturate, integer to accumulator word (evsubfusiaaw) . . . . . 568
Vector subtract from word (evsubfw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
Vector subtract immediate from word (evsubifw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Vector XOR (evxor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
Two-element vector operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
Floating-point data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
BI field (Bits 11–14 of the instruction encoding) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 970
DocID13694 Rev 2
RM0004
Preface
1
Preface
1.1
About this book
The primary objective of this reference is to provide a view of the programming model
defined by Book E and the Book E implementation standards (EIS).
Book E is a PowerPC™ architecture definition for embedded processors that ensures binary
compatibility with the user instruction set architecture (UISA) portion of the PowerPC
architecture as it was jointly developed by Apple, IBM, and Motorola (now Freescale
Semiconductor, Inc.).
This book should be used with the user documentation for individual implementations; such
documents provide a high-level summary of the information that appears here, as well as
implementation-specific features and implementation differences that are not described
here.
This document distinguishes between the three levels of the architectural and
implementation definition, as follows:

The Book E architecture —Book E defines a set of user-level instructions and registers
that are drawn from the UISA portion of the AIM definition of the PowerPC architecture.
Book E also include numerous other supervisor-level registers and instructions as they
were defined in the AIM version of the PowerPC architecture for the virtual environment
architecture (VEA) and the operating environment architecture (OEA). 
Because Book E defines a much different model for operating system resources such
as the MMU and interrupts, it defines many new registers and instructions.

Book E implementation standards (EIS). In many cases, the Book E architecture
definition provides a very general framework, leaving many higher-level details up to
the implementation. 
To ensure consistency among its Book E implementations, working standards were
defined, providing an additional layer of architecture between Book E and actual
devices. This layer includes more specific definitions of Book E features as well as
extensions to the architecture, typically in the form of auxiliary processing units (APUs),
which define additional registers, instructions, and interrupts that provide specially
targeted capabilities. Note that some APUs are implementation-specific and are
available only on individual devices. The APUs described here are those that are
implemented on multiple processors or families of processors. 
The EIS guarantees that if an APU is implemented, it conforms to the EIS architecture
described here.
Information in this book is subject to change without notice, as described in the disclaimers
on the title page of this book. As with any technical documentation, it is the readers’
responsibility to be sure they are using the most recent version of the documentation.
1.1.1
Audience
It is assumed that the reader has the appropriate general knowledge regarding operating
systems, microprocessor system design, and the basic principles of RISC processing to use
the information in this manual.
DocID13694 Rev 2
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Preface
1.1.2
RM0004
Organization
Following is a summary and a brief description of the major sections of this manual:


Section 1.5: Part I: Book E and Book E implementation standards describes the
programming model defined by the PowerPC Book E architecture and the EIS. It
consists of the following chapters:
–
Chapter 2: Overview, provides a general discussion of the programming, interrupt,
cache, and memory management models as they are defined by Book E and the
EIS.
–
Chapter 3: Register model, is useful for software engineers who need to
understand the programming model in general and the functionality of each
register.
–
Chapter 4: Instruction model, provides an overview of the addressing modes and
a description of the instructions. Instructions are organized by function.
–
Chapter 5: Interrupts and exceptions, provides an overview of the Book E– and
EIS-defined interrupts and exception conditions that can cause them.
–
Chapter 6: Storage architecture, describes the cache and MMU portions of the
EIS.
–
Chapter 7: Instruction set, functions as a handbook for the instruction set.
Instructions are sorted by mnemonic. Each instruction description includes the
instruction formats and an individualized legend that provides such information as
the level or levels of the architecture in which the instruction may be found and the
privilege level of the instruction.
Part II: EIS-defined extensions to the Book E architecture, describes the auxiliary
procession units (APUs) defined by the EIS. It consists of the following chapters:
–
Chapter 8: Auxiliary processing units (APUs), describes extensions to the Book E
architecture defined by the EIS. These include the following:
– Section 8.1: Integer select APU
– Section 8.2: Performance monitor APU
– Section 8.3: Signal processing engine APU (SPE APU)
– Section 8.4: Embedded vector and scalar single-precision floating-point
APUs (SPFP APUs)
– Section 8.5: Machine check APU
– Section 8.6: Debug APU
–
Chapter 9: Storage-related APUs, describes the following APUs defined by the
storage architecture:
– Section 9.1: Cache line locking APU
– Section 9.2: Direct cache flush APU
– Section 9.3: Cache way partitioning APU
Subsequent chapters describe the VLE extension
– Chapter 10: VLE introduction
– Chapter 11: VLE storage addressing
– Chapter 12: VLE compatibility with the EIS
– Chapter 13: VLE instruction classes
– Chapter 14: VLE instruction set
– Chapter 15: VLE instruction index
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
The following appendixes are included:
–
Appendix A: Instruction set listings, lists all instructions except those defined by
the VLE extension instructions by both mnemonic and opcode, and includes a
quick reference table with general information, such as the architecture level,
privilege level, form, and whether the instruction is optional. VLE instruction
opcodes are listed in Section 14: VLE instruction set.
–
Appendix B: Simplified mnemonics for PowerPC instructions, describes simplified
mnemonics, which are provided for easier coding of assembly language
programs. Simplified mnemonics are defined for the most frequently used forms of
branch conditional, compare, trap, rotate and shift, and certain other instructions
defined by the PowerPC™ architecture and by implementations of and extensions
to the PowerPC architecture.
–
Appendix C: Programming examples, gives examples of how memory
synchronization instructions can be used to emulate various synchronization
primitives and to provide more complex forms of synchronization. It also describes
multiple precision shifts.
–
Appendix D: Guidelines for 32-bit book E, provides guidelines used by 32-bit
Book E implementations; a set of guidelines is also outlined for software
developers. Application software written to these guidelines can be labeled 32-bit
Book E applications and can be expected to execute properly on all
implementations of Book E, both 32-bit and 64-bit implementations.
–
Appendix E: Embedded floating-point results, provides guidelines used by 32-bit
Book E implementations; a set of guidelines is also outlined for software
developers. Application software written to these guidelines can be labeled 32-bit
Book E applications and can be expected to execute properly on all
implementations of Book E, both 32-bit and 64-bit implementations.
This book includes a glossary and an index.
1.2
Suggested reading
This section lists additional reading that provides background for the information in this
manual as well as general information about the architecture.
1.2.1
General information
The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street,
Sixth Floor, San Francisco, CA, provides useful information about the PowerPC architecture
and computer architecture in general:

1.2.2
The PowerPC Architecture: A Specification for a New Family of RISC Processors,
Second Edition, by International Business Machines, Inc.
Related documentation
ST documentation is available from the sources listed on the back cover of this manual; the
document order numbers are included in parentheses for ease in ordering:

Reference manuals—These books (formerly called user’s manuals) provide details
about individual implementations and are intended for use with the EREF.

Addenda/errata to reference manuals—Because some processors have follow-on
parts an addendum is provided that describes the additional features and functionality
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RM0004
changes. These addenda are intended for use with the corresponding reference
manuals.

Hardware specifications—Hardware specifications provide specific data regarding bus
timing, signal behavior, and AC, DC, and thermal characteristics, as well as other
design considerations.

Technical summaries—Each device has a technical summary that provides an
overview of its features. This document is roughly the equivalent to the overview
(Chapter 1) of an implementation’s reference manual.

Application notes—These short documents address specific design issues useful to
programmers and engineers working with ST processors.
Additional literature is published as new processors become available.
1.2.3
Conventions
This document uses the following notational conventions:
Table 1. Conventions
Convention
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Description
cleared/set
When a bit takes the value zero, it is said to be cleared; when it
takes a value of one, it is said to be set.
mnemonics
Instruction mnemonics are shown in lowercase bold.
italics
Italics indicate variable command parameters, for example, bcctrx.
Book titles in text are set in italics.
Internal signals are set in italics, for example, qual BG
0x
Prefix to denote hexadecimal number
0b
Prefix to denote binary number
rA, rB
Instruction syntax used to identify what is typically a source GPR
rD
Instruction syntax used to identify a destination GPR
frA, frB, frC
Instruction syntax used to identify a source FPR
frD
Instruction syntax used to identify a destination FPR
REG[FIELD]
Abbreviations for registers are shown in uppercase text. Specific
bits, fields, or ranges appear in brackets. For example, MSR[LE]
refers to the little-endian mode enable bit in the machine state
register.
x
In some contexts, such as signal encodings, an unitalicized x
indicates a don’t care.
x
An italicized x indicates an alphanumeric variable.
n
An italicized n indicates an numeric variable.
¬
NOT logical operator
&
AND logical operator
|
OR logical operator
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Table 1. Conventions (continued)
Convention
Description
Concatenation operator; for example, 010 || 111 is the same as
010111
||
—

Indicates a reserved field in a register. Although these bits can be
written to as ones
Additional conventions used with instruction encodings are described in Table 195.
1.3
Acronyms and abbreviations
Table 2 contains acronyms and abbreviations that are used in this document.
Table 2. Acronyms and abbreviated terms
Term
CR
Meaning
Condition register
CTR
Count register
DTLB
Data translation lookaside buffer
EA
Effective address
ECC
Error checking and correction
FPR
Floating-point register
FPU
Floating-point unit
GPR
General-purpose register
IEEE
Institute of Electrical and Electronics Engineers
ITLB
Instruction translation lookaside buffer
L2
LIFO
LR
Secondary cache
Last-in-first-out
Link register
LRU
Least recently used
LSB
Least-significant byte
lsb
Least-significant bit
MMU
Memory management unit
MSB
Most-significant byte
msb
Most-significant bit
MSR
Machine state register
NaN
Not a number
NIA
Next instruction address
No-op
No operation
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Table 2. Acronyms and abbreviated terms (continued)
Term
Meaning
OEA
Operating environment architecture
PTE
Page table entry
RISC
Reduced instruction set computing
RTL
Register transfer language
SIMM
Signed immediate value
SPR
Special-purpose register
TB
Time base register
TLB
Translation lookaside buffer
UIMM
Unsigned immediate value
UISA
User instruction set architecture
VA
1.4
Virtual address
VEA
Virtual environment architecture
VLE
Variable length encoding
XER
Register used primarily for indicating conditions such as carries and overflows for
integer operations
Terminology conventions
Table 3 lists certain terms used in this manual that differ from the architecture terminology
conventions.
Table 3. Terminology conventions
The architecture specification
This manual
Extended mnemonics
Simplified mnemonics
Privileged mode (or privileged state)
Supervisor level
Problem mode (or problem state)
User level
Real address
Physical address
Relocation
Translation
Out-of-order memory accesses
Speculative memory accesses
Storage (locations)
Memory
Storage (the act of)
Access
Table 4 describes instruction field notation conventions used in this manual.
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Table 4. Instruction field conventions
The architecture specification
1.5
Equivalent to:
BA, BB, BT
crbA, crbB, crbD (respectively)
BF, BFA
crfD, crfS (respectively)
D
d
DS
ds
FLM
FM
FRA, FRB, FRC, FRT, FRS
frA, frB, frC, frD, frS (respectively)

CRM
RA, RB, RT, RS
rA, rB, rD, rS (respectively)
SI
SIMM
U
IMM
UI
UIMM
/, //, ///
0...0 (shaded)
Part I: Book E and Book E implementation standards
Part I describes the registers and instructions defined by the Book E architecture and by the
Book E implementation standards (EIS). It contains the following chapters:

Chapter 2: Overview, provides a general discussion of the programming, interrupt,
cache, and memory management models as they are defined by Book E and the EIS.

Chapter 3: Register model, is useful for software engineers who need to understand
the programming model in general and the functionality of each register.

Chapter 4: Instruction model, provides an overview of the addressing modes and a
description of the instructions. Instructions are organized by function.

Chapter 5: Interrupts and exceptions, provides an overview of the Book E– and EIS–
defined interrupts and exception conditions that can cause them.

Chapter 6: Storage architecture, describes the cache and MMU portions of the EIS.
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Part II: EIS-defined extensions to the Book E architecture
This part describes the extensions defined by the Book E Implementation Standards (EIS). It
consists of the following:

Chapter 8: Auxiliary processing units (APUs), describes APUs such as the isel
instruction, performance monitor, signal processing engine (SPE), locking, and
machine check APUs.

Chapter 9: Storage-related APUs, describes the following APUs defined by the storage
architecture:

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–
Chapter 9.1: Cache line locking APU on page 692
–
Chapter 9.2: Direct cache flush APU on page 694
–
Chapter 9.3: Cache way partitioning APU on page 695
Subsequent chapters describe the VLE extension
–
Chapter 10: VLE introduction
–
Chapter 11: VLE storage addressing
–
Chapter 12: VLE compatibility with the EIS
–
Chapter 13: VLE instruction classes
–
Chapter 14: VLE instruction set
–
Chapter 15: VLE instruction index
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2
Overview
Overview
This document describes the Book E version of the PowerPC™ architecture as it is further
defined by the Book E implementation standards (EIS) and implemented on Book E cores.
This chapter includes overviews of the following:
2.1

Features of the Book E version of the PowerPC architecture and implementationdetails defined by the EIS

The Book E and EIS programming model

The Book E and EIS interrupt model

The Book E and EIS memory management model

Architectural compatibility and migration from the original version of the PowerPC
architecture as defined by Apple, IBM, and Motorola (referred to as the AIM version of
the PowerPC architecture)
Overview Book E and the Book E implementation standards
(EIS)
Book E is a version of the PowerPC architecture intended for embedded processors. To
ensure application-level compatibility with the PowerPC architecture developed by Apple,
IBM and Freescale, Book E incorporates the user-level resources defined in the user
instruction set architecture (UISA), Book I, of the AIM architectural definition.
Because operating systems for embedded processors have different needs than those for
desktop systems, Book E defines more flexible interrupt and memory management models.
Instead of the segmented memory model defined by the AIM architecture, Book E provides
a page-based memory system that supports multiple variable-sized pages managed
through translation lookaside buffers (TLBs). Interrupt offsets can be programmed through
interrupt-specific interrupt vector offset registers (IVORs). Book E defines the interrupt
vector prefix register (IVPR), which is programmed with a prefix value that is concatenated
with the IVOR values to place the interrupt vector table anywhere in memory.
As a consequence, some resources defined by the AIM version of the architecture are no
longer supported and new ones are provided. For example, segment and block address
translation (BAT) registers are gone, and new instructions, registers, and interrupts have
been defined for managing page translation and protection through TLBs.
Moreover, the Book E architecture allows greater flexibility. For example, Book E defines the
TLB Write Entry (tlbwe) and TLB Read Entry (tlbre) instructions only very generally, leaving
details of their execution and behavior up to the implementation. However, to ensure
compatibility among Book E implementations, the Book E implementation standard (EIS)
defines more specifically how these instructions work.
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Auxiliary processing units (APUs)
Book E supports the use of auxiliary processing units (APUs), which allocate opcode and
register space for extending the instruction set without affecting the instruction set defined
by Book E. This facilitates the development of special-purpose resources that are useful to
some embedded environments but impractical for others. Note that instructions from
multiple APUs may be assigned the same opcode numbers of the allocated opcode space.
The EIS defines many APUs. These APUs are not required on all devices, but devices that
implement them do so strictly following the EIS architectural definition. In addition, an
implementation may also provide an APU that is not a part of the EIS.
APUs may consist of any combination of instructions, optional behavior of Book E–defined
instructions, registers, register files, fields within Book E–defined registers, interrupts, or
exception conditions within Book E–defined interrupts.
Chapter 8: Auxiliary processing units (APUs), provides an overview of specific APUs.
2.2
Instruction set
The instruction set of a ST 32-bit Book E–compliant device includes the following:
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
The Book E instruction set for 32-bit implementations. This is composed primarily of the
user-level instructions defined by the UISA. Some implementations do not include the
Book E floating-point instructions or the Load String Word Indexed instruction (lswx).

Instructions defined by EIS APUs. These include the following:
–
Integer select APU. This APU consists of the Integer Select instruction (isel),
which incorporates an if-then-else statement that selects between two source
registers by comparison to a CR bit. This instruction eliminates conditional
branches, decreases band latency, and reduces the code footprint.
–
SPE (signal processing engine) APU instructions. SPE instructions treat 64-bit
GPRs as a vector of two 32-bit elements (some instructions also read or write 16bit elements). Section 4.6.1: SPE and embedded floating-point APUs, lists SPE
APU vector instructions.
–
The embedded vector floating-point APU provides instructions that use the upper
and lower words of the 64-bit GPRs for single-precision, vector floating-point
calculations.
–
The embedded scalar single-precision APU provides instructions that use the
lower 32 bits of the GPRs for single-precision, scalar floating-point calculations.
–
The embedded scalar double-precision APU instructions use the 64-bit GPRs for
floating-point calculations.
–
Performance monitor APU—This APU defines two instructions, mfpmr and
mtpmr, used for reading and writing the performance monitor registers (PMRs).
–
Cache block lock and unlock APU, consisting of the following instructions:
– Data Cache Block Lock Clear (dcblc)
– Data Cache Block Touch and Lock Set (dcbtls)
– Data Cache Block Touch for Store and Lock Set (dcbtstls)
– Instruction Cache Block Lock Clear (icblc)
– Instruction Cache Block Touch and Lock Set (icbtls)
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2.3
Register set
Note:
Devices that implement a particular core may not implement all registers defined by that core.
Figure 1. EIS programming model register set
User-Level Registers
Register Files
0
31 32
Instruction-Accessible Registers
63
0
31 32
(upper) GPR01 (lower)
CR
General-purpose
registers (GPRs)
GPR1
GPR31
FPR0
Floating-point
registers (FPRs)
FPR1
pmr 256–259 UPMLCbs
3
pmr 384 UPMGC03
pmr 0–3
Count register
spr 8
LR
Link register
spr 1
XER
Integer exception
register
Floating-point
status/control register
SP/embedded FP
status/control register
FPSCR
pmr 128–131 UPMLCas3
UPMCs
3
Local control
registers A0–A3
B0–B3
Global control register
Counters 0–3
32
Condition register
CTR
spr 9
FPR31
Performance Monitor Registers (PMRs)
User General SPR (Read/Write)
63
spr 512 SPEFSCR3
ACC 3
Accumulator
L1 Cache (Read-Only)
spr 515
L1CFG03
spr 516
3
L1CFG1
L1 cache configuration
registers 0–1
spr 256
63
USPRG02
User SPR
general 0
General SPRs (Read-Only)
spr 259
spr 260
SPRG3
spr 263
SPRG7
SPRG4
SPR general
registers 3–7
Time-Base Registers (Read-Only)
spr 268
TBL
TBU
spr 269
Time base
lower/upper
3
spr 526
ATBL
spr 527
ATBU 3
Alternate Time base
lower/upper
Supervisor-Level Registers
Interrupt Registers
32
spr 63
IVPR
spr 26
SRR0
spr 27
SRR1
CSRR0
spr 58
spr 59
CSRR1
spr 570 MCSRR03
spr 571 MCSRR13
spr 574 DSRR03
spr 575
DSRR13
spr 62
ESR
spr 572
MCSR3
spr 573
MCAR3
spr 61
DEAR
32
Interrupt vector
prefix register
DBCR0–2
Critical SRR 0/1
Machine check
SRR 0/1
Debug SRR 0/1
Machine check
syndrome register
Machine check
address register
Data exception
address register
Debug control 0–2
spr 561
DBCR3
Debug control 3
DBSR
Debug status register
spr 316–317
spr 318–319
IACs
DACs
DVCs
spr 400
IVOR0
spr 401
IVOR1
spr 415
IVOR15
spr 528
IVOR323
spr 529
spr 530
spr 531
IVOR333
IVOR343
32
Interrupt vector offset
registers 0–15
Instruction address
compare1–4
Data address
compare 1–2
Data value
compare 1–2
3
spr 624
MAS0
spr 625
MAS1 3
spr 630
MAS6 3
spr 944
MAS7 3
spr 48
spr 633
PID0
PID13
spr 634
PID23
MMU assist
registers 0–7
spr 688 TLB0CFG3
spr 689 TLB1CFG3
System version
register
spr 286
PIR
Processor ID register
PVR
Processor version
register
Timer/Decrementer Registers
spr 54
DEC
Decrementer
DECAR
Decrementer
auto-reload register
spr 284
TBL
spr 285
TBU
Time base
lower/upper
spr 340
TCR
Timer control register
spr 336
TSR
Timer status register
Miscellaneous Registers
spr 272–279
Process ID
registers 0–2
spr 1008
spr 1009
MMU Control and Status (Read Only)
spr 1015 MMUCFG3
Machine state register
SVR
spr 22
MMU control and status
register 0
3
spr 1023
spr 287
Interrupt vector offset
registers 32–35
IVOR353
spr 1012 MMUCSR0 3
63
MSR
MMU Control and Status (Read/Write)
Exception syndrome
register
spr 304
spr 312–315
63
Save/restore
registers 0/1
Debug Registers
spr 308–310
Configuration Registers
63
MMU configuration
TLB configuration 0/1
L1 Cache (Read/Write)
spr 1010
spr 1011
L1CSR03
L1CSR13
L1 cache control/status
registers 0/1
spr 1015
L1FINV0 3
L1 flush and invalidate
control register 0
SPRG0–7
3
HID0
HID1 3
General SPRs 0–7
Hardware
implementation
dependent 0–1
Performance Monitor Registers
pmr 400
PMGC03
Global control
pmr 16–19
PMC0–33
Counter registers 0–3
pmr 144–147 PMCa0–33
Local control a0–a3
pmr 272–275 PMCb0–33
Local control b0–b3
(1.) The 64-bit GPR registers are accessed by the SPE as separate 32-bit operands by SPE instructions. Only
SPE vector instructions can access the upper word. (2.) USPRG0 is a separate physical register from
SPRG0. (3.) EIS-defined registers; not part of the Book E architecture.
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Interrupts and exception handling
Book E and the EIS support an extended exception handling model, with nested interrupt
capability and extensive interrupt vector programmability. The following sections define the
exception model, including an overview of exception handling as implemented in a ST Book
E device, a brief description of the exception classes, and an overview of the registers
involved.
2.4.1
Exception handling
In general, interrupt processing begins with an exception that occurs due to external
conditions, errors, or program execution problems. When the exception occurs, the
processor checks to verify that interrupt processing is enabled for that particular exception.
If enabled, the interrupt causes the state of the processor to be saved in the appropriate
registers, and prepares to begin execution of the handler located at the associated vector
address for that particular exception.
Once the handler is executing, the implementation may need to check one or more bits in
the exception syndrome register (ESR) or the SPEFSCR, depending on the exception type,
to verify the specific cause of the exception and take appropriate action.
The interrupts are described in Section 2.4.4: Interrupt registers, and in Table 6.
2.4.2
Interrupt classes
All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.
2.4.3

Asynchronous interrupts are caused by events that are independent of instruction
execution. The address reported in the save/restore register is that of the instruction
that would have executed next had the asynchronous interrupt not occurred.

Synchronous interrupts are caused directly by the execution or attempted execution of
instructions. Synchronous inputs can be precise or imprecise:
–
Synchronous precise interrupts are those that precisely indicate the address of the
instruction causing the exception that generated the interrupt or, in some cases,
the address of the next instruction in program order. The interrupt type and status
bits allow determination of which of the two instructions has been addressed in the
appropriate save/restore register.
–
Synchronous imprecise interrupts may indicate the address of the instruction
causing the exception that generated the interrupt or some instruction after the
instruction causing the interrupt. If the interrupt was caused by either the context
synchronizing mechanism or the execution synchronizing mechanism, the
address in the appropriate save/restore register is the address of the interrupt
forcing instruction. If the interrupt was not caused by either of those mechanisms,
the address in the save/restore register is the last instruction to start execution and
may not have completed. No instruction following the instruction in the
save/restore register has executed.
Interrupt categories
Book E defines critical and noncritical interrupt categories, and the EIS defines the machine
check and debug interrupt categories. Each category has a separate set of save and restore
registers to which machine state and a return address are automatically written when an
interrupt is taken. Each category has a return from interrupt instruction that uses the save
and restore registers to reestablish the machine state of the interrupted process and
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provides the address within that process at which to resume execution after the interrupt
handler completes. Additional resources are provided for masking some of these interrupt
categories, as described in the following:

Debug APU interrupt (if present)—Although Book E defines debug as a critical
interrupt, the EIS defines a separate debug APU. Debug save and restore registers
(DSRR0/DSRR1) save state when a debug interrupt is taken; rdci restores state at the
end of the interrupt handler. These interrupts are masked by setting the machine check
enable bit, MSR[DE].

Machine check APU interrupt (if present)—Although Book E defines machine check as
a critical interrupt, the EIS defines a separate machine check APU. Machine check
save and restore registers (MCSRR0/MCSRR1) save state when a machine check
interrupt is taken; rfmci restores state at the end of the interrupt handler. These
interrupts are masked by setting the machine check enable bit, MSR[ME].

Noncritical interrupts—First-level interrupts that allow the processor to change program
flow to handle conditions generated by external signals, errors, or unusual conditions
arising from program execution or from programmable timer-related events. These
interrupts are largely identical to those defined by the OEA portion of the Power PC
architecture. They use save and restore registers (SRR0/SRR1) to save processor
state and the rfi instruction to restore state. Asynchronous noncritical interrupts can be
masked by the external interrupt enable bit, MSR[EE].

Critical interrupts—Can be taken during a noncritical interrupt or during regular
program flow. They use the critical save and restore registers (CSRR0/CSRR1) to save
state when they are taken; they use the rfci instruction to restore state. These
interrupts can be masked by the critical enable bit, MSR[CE]. Book E defines the
critical input and watchdog timer interrupts as critical interrupts.
One interrupt of each category can be reported at a time; when it is taken, no program state
is lost. Save/restore register pairs are serially reusable, so program state may be lost when
an unordered interrupt is taken. See Section 5.10: Interrupt ordering and masking.
2.4.4
Interrupt registers
The registers associated with interrupt and exception handling are described in Table 5.
Table 5. Interrupt registers
Register
Description
Non critical interrupt registers
SRR0
Save/restore register 0—Stores the address of the instruction causing the exception or the address of
the instruction that will execute after the rfi instruction.
SRR1
Save/restore register 1—Saves machine state on noncritical interrupts and restores machine state
after an rfi instruction is executed.
Critical interrupt registers
CSRR0
Critical save/restore register 0—On critical interrupts, CSRR0 stores either the address of the
instruction causing the exception or the address of the instruction that will execute after the rfci
instruction.
CSRR1
Critical save/restore register 1—CSRR1 saves machine state on critical interrupts and restores
machine state after an rfci instruction is executed.
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Table 5. Interrupt registers (continued)
Register
Description
Machine check interrupt registers
MCSRR0
Machine check save/restore register 0—Stores the address of the instruction that executes after rfmci
executes.
MCSRR1
Machine check save/restore register 1—MCSRR1 stores machine state on machine check interrupts
and restores machine state (if recoverable) after an rfmci instruction is executed.
MCAR
Machine check address register—MCAR holds the address of the data or instruction that caused the
machine check interrupt. MCAR contents are not meaningful if a signal triggered the machine check
interrupt.
Debug interrupt registers
DSRR0
Debug save/restore register 0—Stores the address of the instruction that executes after rfdi executes.
DSRR1
Debug save/restore register 1—Stores machine state on machine check interrupts and restores
machine state (if recoverable) after rfmci executes.
Syndrome registers
MCSR
Machine check syndrome register—MCSR saves machine state information on machine check
interrupts and restores machine state after an rfmci instruction is executed.
ESR
Exception syndrome register—ESR provides a syndrome to differentiate between the different kinds of
exceptions that generate the same interrupt type. Upon generation of a specific exception type, the
associated bit is set and all other bits are cleared.
SPE and embedded floating-point APU interrupt registers
Signal processing and embedded floating-point status and control register—Provides interrupt control
SPEFSCR and status as well as various condition bits associated with the operations performed by the SPE APU
and the embedded floating-point APUs.
Other interrupt registers
DEAR
Data exception address register—DEAR contains the address that was referenced by a load, store, or
cache management instruction that caused an alignment, data TLB miss, or data storage interrupt.
IVPR
Interrupt vector prefix register—IVPR[32–47] contains the high-order 16 bits of the address of the
exception processing routines defined in the IVOR registers.
IVORs
Interrupt vector offset registers—The IVORs contain the low-order offset of the address of the
exception processing routines defined in the IVOR registers. See Table 6.
Table 6 lists IVOR registers and associated interrupts.
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Table 6. Interrupt vector registers and exception conditions
Register
Interrupt
Book E–defined IVORs
IVOR0
Critical input
IVOR1
Machine check interrupt offset
IVOR2
Data storage interrupt offset
IVOR3
Instruction storage interrupt offset
IVOR4
External input interrupt offset
IVOR5
Alignment interrupt offset
IVOR6
Program interrupt offset
IVOR7
Floating-point unavailable interrupt offset
IVOR8
System call interrupt offset
IVOR9
Auxiliary processor unavailable interrupt offset
IVOR10
Decrementer interrupt offset
IVOR11
Fixed-interval timer interrupt offset
IVOR12
Watchdog timer interrupt offset
IVOR13
Data TLB error interrupt offset
IVOR14
Instruction TLB error interrupt offset
IVOR15
Debug interrupt offset
EIS-Defined IVORs
IVOR32
SPE APU unavailable interrupt offset
IVOR33
Embedded floating-point data exception interrupt offset
IVOR34
Embedded floating-point round exception interrupt offset
IVOR35
Performance monitor interrupt offset
Each interrupt has an associated interrupt vector address, obtained by concatenating the
IVPR and IVOR values (IVPR[32–47]||IVORn[48–59]||0b0000). The resulting address is that
of the instruction to be executed when that interrupt occurs. IVPR and IVOR values are
indeterminate on reset, and must be initialized by the system software using mtspr. For
more information, see Chapter 5: Interrupts and exceptions.
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2.5
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Memory management
The EIS supports demand-paged virtual memory as well other memory management
schemes that depend on precise control of effective-to-physical address translation and
flexible memory protection as defined by Book E. The mapping mechanism consists of
software-managed TLBs that support variable-sized pages with per-page properties and
permissions. The following properties can be configured for each TLB:
2.5.1

User mode page execute access

User mode page read access

User mode page write access

Supervisor mode page execute access

Supervisor mode page read access

Supervisor mode page write access

Write-through required (W)

Caching inhibited (I)

Memory coherence required (M)

Guarded (G)

Endianness (E)

User-definable (U0–U3), a 4-bit implementation-specific field
Address translation
Figure 2 shows a typical translation flow, although each implementation may differ in the
specific details. The MMU translates 32-bit effective addresses generated by loads, stores,
and instruction fetches into 32-bit real addresses (used for memory bus accesses) using an
interim 41-bit virtual address.
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Figure 2. Effective-to-Real Address Translation Flow
•••
IS DS •••
MSR
Instruction Access
Data Access
8 bits
AS
32-bit Effective Address (EA)
15–20 bits*
PID0
12–17 bits*
Effective Page Number
Byte Address
PID1
PID2
Three 41-bit Virtual Addresses (VAs)
L1 MMUs
L2 MMU (unified)
16-Entry Fully-Assoc. VSP Array (TLB1)
Instruction L1 MMU
2 TLBs
Data L1 MMU
2 TLBs
256-Entry 2-Way Set Assoc. Array (TLB0)
15–20 bits*
32-bit Real Address
Real Page Number
12–17 bits*
Byte Address
* Number of bits depends on page size (4 Kbytes–256 Mbytes)
As Figure 2 shows, address translation starts with an effective address that is prepended
with an address space (AS) value and a process ID to construct a virtual address (VA). The
virtual address is then translated into a real address based on the translation information
found in the on-chip TLB of the appropriate L1 MMU. The AS bit for the access is selected
from the value of MSR[IS] or MSR[DS], for instruction or data accesses, respectively.
The appropriate L1 MMU (instruction or data) is checked for a matching address translation.
The instruction L1 MMU and data L1 MMU operate independently and can be accessed in
parallel, so that hits for instruction accesses and data accesses can occur in the same clock.
If an L1 MMU misses, the request for translation is forwarded to the unified (instruction and
data) L2 MMU. If found, the contents of the TLB entry are concatenated with the byte
address to obtain the physical address of the requested access. On misses, the L1 TLB
entries are replaced from their L2 TLB counterparts using a true LRU algorithm.
2.5.2
MMU assist registers (MAS1–MAS7)
Book E defines SPR numbers for the MMU assist registers, used to hold values either read
from or to be written to the TLBs and information required to identify the TLB to be
accessed. Book E leaves MAS register bit definitions up to the implementations. To ensure
consistency among ST Book E processors, certain aspects of the implementation are
defined by the Book E standard; more specific details are left to individual implementations.
MAS3 implements the real page number (RPN), the user attribute bits (U0–U3), and
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Overview
RM0004
permission bits (UX, SX, UW, SW, UR, SR) that specify user and supervisor read, write, and
execute permissions.
Some cores may not does not implement all of the MAS registers.
MAS registers are affected by the following instructions:

MAS registers are accessed with the mtspr and mfspr instructions.

The TLB Read Entry instruction (tlbre) causes the contents of a single TLB entry from
the L2 MMU to be placed in defined locations in MAS0–MAS3. The TLB entry to be
extracted is determined by information written to MAS0 and MAS2 before the tlbre
instruction is executed.

The TLB Write Entry instruction (tlbwe) causes the information stored in certain
locations of MAS0–MAS3 to be written to the TLB specified in MAS0.

The TLB Search Indexed instruction (tlbsx) updates MAS registers conditionally,
based on success or failure of a lookup in the L2 MMU. The lookup is specified by the
instruction encoding and specific search fields in MAS6. The values placed in the MAS
registers may differ, depending on a successful or unsuccessful search.
For TLB miss and certain MMU-related DSI/ISI exceptions, MAS4 provides default values
for updating MAS0–MAS2.
2.5.3
Process ID registers (PID0–PID2)
The Book E architecture identifies a single process ID register (PID). The EIS defines
additional PIDs to hold values used to construct the virtual addresses for each access.
Among these PIDs, PID0 is the Book E–defined PID. These process IDs provide an
extended page sharing capability. Which of these three virtual addresses is used for
translation is controlled by the TID field of a matching TLB entry, and when TID = 0x00
(identifying a page as globally shared), the PID values are ignored.
A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) or a hit to
multiple entries in the L2 MMU is considered to be a programming error.
2.5.4
TLB coherency
TLB entries can be invalidated as defined in the Book E architecture. The tlbivax instruction
invalidates a matching local TLB entry.
2.5.5
Atomic update memory references
Book E supports atomic update memory references for both aligned word forms of data
using the load and reserve and store conditional instruction pair, lwarx and stwcx..
Typically, a load and reserve instruction establishes a reservation and is paired with a store
conditional instruction to achieve the atomic operation. However, the programmer is
responsible for preserving reservations across context switches and for protecting
reservations in multiprocessor implementations.
2.5.6
Memory access ordering
To optimize performance, Book E supports weakly ordered references to memory. Thus, a
processor manages the order and synchronization of instructions to ensure proper
execution when memory is shared between multiple processes or programs. The cache and
data memory control attributes, along with msync and mbar, provide the required access
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control; msync and mbar are also broadcast to provide the appropriate control in the case
of multiprocessor or shared memory systems.
2.5.7
Cache control instructions
Book E cache control instructions perform a full range of cache control functions, including
cache locking by line. The EIS defines the following cache locking instructions:

2.5.8
Data Cache Block Lock Clear (dcblc)

Data Cache Block Touch and Lock Set (dcbtls)

Data Cache Block Touch for Store and Lock Set (dcbtstls)

Instruction Cache Block Lock Clear (icblc)

Instruction Cache Block Touch and Lock Set (icbtls)
Programmable page characteristics
Cache and memory attributes are programmable on a per-page basis. In addition to the
write-through, caching-inhibited, memory coherency enforce, and guarded characteristics
defined by the WIMG bits, Book E defines an endianness bit, E, that selects big- or littleendian byte ordering on a per-page basis.
2.6
Performance monitoring
The EIS provides a performance monitoring capability that supports counting of events such
as processor clocks, instruction cache misses, data cache misses, mispredicted branches,
and others. The count of these events may be configured to trigger a performance monitor
exception. This interrupt is assigned to vector offset register IVOR35.
The register set associated with performance monitoring consists of counter registers, a
global control register, and local control registers. These registers are read/write from
supervisor mode, and each register is reflected to a corresponding read-only register for
user mode. The mtpmr and mfpmr instructions move data to and from these registers. An
overview of the performance monitoring registers is provided in the following sections. For
more information, see Section 8.2: Performance monitor APU.
2.6.1
Global control register
The performance monitor global control register 0 (PMGC0) provides global control of the
performance monitor from supervisor mode. From this register all counters may be frozen,
unfrozen, or configured to freeze on an enabled condition or event. Additionally, the
performance monitoring facility may be disabled or enabled from this register. The PMGC0
contents are reflected to UPMGC0, which may be read from user mode using mfpmr.
2.6.2
Performance monitor counter registers
There are four counter registers (PCM0–PCM3) provided in the performance monitor facility.
These 32-bit registers hold the current count for software-selectable events and can be
programmed to generate an exception on overflow. They can be accessed from supervisor
mode using mtpmr and mfpmr. Their contents are reflected to UPCM0–UPCM3, which can
be read from user mode with mfpmr.
The exception generated on overflow can be masked by clearing MSR[EE].
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2.6.3
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Local control registers
For each counter register, there are two corresponding local control registers. These two
registers specify which of the 128 available events is to be counted, the action to be taken
on overflow, and options for freezing a counter value under given modes or conditions.
2.7

PMLCa0–PMLCa3 provide fields that allow freezing of the corresponding counter in
user mode, supervisor mode, or under software control. The overflow condition may be
enabled or disabled from these registers. Register contents are reflected to UPMCLa0–
UPMLCa3, which can be read from user mode with mfpmr.

PMLCb0–PMLCb3 provide count scaling for each counter register using configurable
threshold and multiplier values. The threshold is a 6-bit value and the multiplier is a 3bit encoded value, allowing 8 multiplier values in the range of 1 to 128. Any counter
may be configured to increment only when an event occurs more than [threshold 
multiplier] times. The contents of these registers are reflected to UPMCLb0–UPMLCb3,
which can be read from user mode with mfpmr.
Legacy support of PowerPC architecture
In general, ST Book E processors support the user-level portion of the AIM architecture. The
following subsections highlight the main differences. For specific details, refer to the
relevant chapter.
2.7.1
Instruction set compatibility
The following sections generally describe compatibility between Book E and AIM PowerPC
instruction sets.
User instruction set
The user mode instruction set defined by the AIM version of the PowerPC architecture is
compatible with ST Book E processors with the following exceptions:

Floating-point functionality provided by the embedded floating-point APUs differs from
the AIM defined floating-point ISA. Also, the vector and double-precision floating-point
APUs use 64-bit GPRs rather than the FPRs defined by the UISA. Most porting of
floating-point operations can be handled by recompiling; however, there are new
instructions specific to the APUs.

String instructions are typically not implemented; therefore, trap emulation must be
provided to ensure backward compatibility.
Supervisor instruction set
The supervisor mode instruction set defined by the AIM version of the PowerPC architecture
is compatible with the EIS with the following exceptions:
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
The MMU architecture is different, so some TLB manipulation instructions have
different semantics.

Instructions that support the BATs and segment registers are not implemented.

Interrupt vectors are defined by the Book E IVORn and IVPR SPRs.

Additional instructions are defined for returning from Book E–defined critical interrupts
(rfci) and APU-specific interrupts.
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2.7.2
Overview
Memory subsystem
Both Book E and the AIM version of the PowerPC architecture provide separate instruction
and data memory resources. The EIS provides additional cache control features, including
cache locking.
2.7.3
Interrupt handling
Interrupt handling is generally the same as that defined in the AIM version of the PowerPC
architecture, with the following differences: (see Section 2.4: Interrupts and exception
handling)
2.7.4

Book E defines a new critical interrupt, providing an extra level of interrupt nesting. The
critical interrupt includes external critical and watchdog timer time-out inputs.

The machine check APU implements the machine check exception differently from the
Book E and from the AIM definition. It defines the Return from Machine Check Interrupt
instruction, rfmci, and two machine check save/restore registers, MCSRR0 and
MCSRR1.

Book E processors can use IVPR and IVORs to set exception vectors individually. To
provide compatibility, they can be set to the address offsets defined in the OEA.

Unlike the AIM version of the PowerPC architecture, Book E does not define a reset
vector; execution begins at a fixed virtual address, 0xFFFF_FFFC.

Some SPRs are different from those defined in the AIM version of the PowerPC
architecture, particularly those related to the MMU functions. Much of this information
has been moved to a new exception syndrome register (ESR).

Timer services are generally compatible, although Book E defines a new decrementer
auto reload feature and the fixed-interval timer critical interrupt.
Memory management
ST Book E processors implement a straightforward virtual address space that complies with
the Book E MMU definition, which eliminates segment registers and block address
translation resources. Book E defines resources for fixed 4-Kbyte pages and multiple,
variable page sizes that can be configured in a single implementation. TLB management is
provided with new instructions and SPRs.
2.7.5
Requirements for system reset generation
Book E does not specify a system reset interrupt as was defined in the AIM version of the
PowerPC architecture, but typically, system reset is initiated either by asserting a signal or
by software (for example, writing a 1 to DBCR0[34], if MSR[DE] = 1
At reset, instead of invoking a reset interrupt, fetching at address 0xFFFF_FFFC, as defined
by Book E. In addition to the Book E reset definition, the EIS and the implementation define
specific aspects of MMU page translation and protection mechanisms. Unlike the AIM
version of the PowerPC core, as soon as instruction fetching begins, the core is in virtual
mode with a hardware-initialized TLB entry.
2.7.6
Little-endian mode
Unlike the AIM version of the PowerPC, where the little-endian mode is controlled on a
system basis, Book E supports control of byte ordering on a memory page basis.
Additionally, true little-endian mode is supported by byte swapping.
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3
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Register model
This chapter describes the register model and indicates the architecture level at which each
register is defined.
3.1
Overview
Although this chapter organizes registers according to their functionality, they can be
differentiated according to how they are accessed, as follows:

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Register files. These user-level registers are accessed explicitly through source and
destination operands of computational, load/store, logical, and other instructions. Book
E defines two types of register files:
–
General-purpose registers (GPRs), used as source and destination operands for
most operations (except Book E–defined floating-point instructions, which use
FPRs). See Section 3.3.1: General purpose registers (GPRs).
–
Floating-point registers (FPRs), used for Book E–defined floating-point
instructions. See Section 3.4.1: Floating-point registers (FPRs).

Special-purpose registers (SPRs)—SPRs are accessed by using the Book E–defined
Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register
(mfspr) instructions. Section 3.2.1: Special-purpose registers (SPRs), lists SPRs.

System-level registers that are not SPRs. These are as follows:
–
Machine state register (MSR). MSR is accessed with the Move to Machine State
Register (mtmsr) and Move from Machine State Register (mfmsr) instructions.
See Section 3.6.1: Machine state register (MSR).
–
Condition register (CR) bits are grouped into eight 4-bit fields, CR0–CR7, which
are set as follows (see Section 3.5.1: Condition register (CR)):
– Specified CR fields can be set by a move to the CR from a GPR (mtcrf).
– A specified CR field can be set by a move to the CR from another CR field
(mcrf), from the FPSCR (mcrfs), or from the XER (mcrxr).
– CR0 can be set as the implicit result of an integer instruction.
– CR1 can be set as the implicit result of a floating-point instruction.
– A specified CR field can be set as the result of an integer or floating-point
compare instruction (including SPE and SPFP compare instructions).
–
The floating-point status and control register (FPSCR). See Section 3.4.2:
Floating-point status and control register (FPSCR).
–
The EIS-defined accumulator, which is accessed by signal processing engine
(SPE) APU instructions that update the accumulator. See Section 3.14.2:
Accumulator (ACC).

Device control registers (DCRs). Book E defines the existence of a DCR address
space and the instructions to access them, but does not define particular DCRs. The
on-chip DCRs exist architecturally outside the processor core and thus are not part of
Book E. The contents of DCR DCRN can be read into a GPR using mfdcr rD,DCRN.
GPR contents can be written into DCR DCRN using mtdcr DCRN,rS. See
Section 3.17: Device control registers (DCRs).

Performance monitor registers (PMRs). (Performance monitor APU) Similar to SPRs,
PMRs are accessed by using the EIS-defined Move to Performance Monitor Register
(mtpmr) and Move from Performance Monitor Register (mfspr) instructions. See
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Section 3.16: Performance monitor registers (PMRs).
3.2
Register model for 32-bit Book E implementations
Book E implementations include the following types of software-accessible registers:


Registers that are accessed as part of instruction execution. These include the
following:
–
The following registers are used for integer operations and are described in
Section 3.3: Registers for integer operations:
– General-purpose registers (GPRs)—Book E defines a set of 32 GPRs used
to hold source and destination operands for load, store, arithmetic, and
computational instructions, and to read and write to other registers.
– Integer exception register (XER)—XER bits are set based on the operation of
an instruction considered as a whole, not on intermediate results. (For
example, the Subtract from Carrying instruction (subfc), the result of which
is specified as the sum of three values, sets bits in the XER based on the
entire operation, not on an intermediate sum.)
–
Registers for floating-point operations. These include the following:
– Floating-point registers (FPRs)—32 registers used to hold source and
destination operands for Book E defined floating-point operations. Note that
the embedded floating-point APUs do not implement FPRs; they use GPRs
for floating-point operands.
– Floating-point status and control register (FPSCR)—Used with floating-point
operations. These registers are described in Section 3.4: Registers for
floating-point operations.
–
Condition register (CR)—Used to record conditions such as overflows and carries
that occur as a result of executing arithmetic instructions (including those
implemented by the SPE and SPFP APUs). The CR is described in Section 3.5:
Registers for branch operations.
–
Machine state register (MSR)—Used by the operating system to configure
parameters such as user/supervisor mode, address space, and enabling of
asynchronous interrupts. MSR is described in Section 3.6.1: Machine state
register (MSR).
Special-purpose registers (SPRs).
–
Book E–defined special-purpose registers (SPRs) that are accessed explicitly
using mtspr and mfspr instructions. These registers are listed in Table 7 in
Section 3.2.1: Special-purpose registers (SPRs).
–
EIS–defined SPRs that are accessed explicitly using the mtspr and mfspr
instructions. These registers are listed in Table 8 in Section 3.2.1: Special-purpose
registers (SPRs).
–
SPRs are described by function in the following sections:
– Section 3.5: Registers for branch operations
– Section 3.6: Processor control registers
– Section 3.7: Hardware implementation-dependent registers
– Section 3.8: Timer registers
– Section 3.9: Interrupt registers
– Section 3.10: Software use sprs (SPRG0–SPRG7 and USPRG0)
– Section 3.11: L1 cache registers
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–
–
–
–
Section 3.12: MMU registers
Section 3.13: Debug registers
Section 3.14: SPE and SPFP APU registers
Section 3.15: Alternate time base registers (ATBL and ATBU)

EIS-defined performance monitor registers, described in Section 3.16: Performance
monitor registers (PMRs). PMRs are like SPRs, but are accessed with EIS-defined
move to and move from PMR instructions (mtpmr and mfpmr).

EIS-defined device control registers (DCRs). Book E defines a format for implementing
device-specific device-control registers. See Section 3.17: Device control registers
(DCRs).
Book E defines 32- and 64-bit registers. However, except for the 64-bit FPRs, only bits 32–
63 of Book E’s 64-bit registers (such as LR, CTR, the GPRs, SRR0, and CSRR0) are
required to be implemented in hardware in a 32-bit Book E implementation.
Likewise, all Book E integer instructions defined to return a 64-bit result return only bits 32–
63 of the result on a 32-bit Book E implementation. SPE APU vector instructions return 64bit values; SPFP APU instructions return single-precision 32-bit values.
As with the instruction set and other aspects of the architecture, Book E defines some
features very specifically, for example, resources that ensure compatibility with
implementations of the PowerPC ISA. Other resources are either defined as optional or are
defined in a very general way, leaving specific details up to the implementation.
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Figure 3. Register model
User-Level Registers
Register Files
0
31 32
Instruction-Accessible Registers
63
0
31 32
(upper) GPR01 (lower)
CR
General-purpose
registers (GPRs)
GPR1
GPR31
FPR0
Floating-point
registers (FPRs)
FPR1
pmr 256–259 UPMLCbs3
pmr 384 UPMGC03
pmr 0–3
UPMCs 3
Local control
registers A0–A3
B0–B3
Global control register
Counters 0–3
spr 256
63
USPRG02
User SPR
general 0
CTR
spr 8
LR
Link register
XER
Integer exception
register
Floating-point
status/control register
SP/embedded FP
status/control register
Time-Base Registers (Read-Only)
Accumulator
spr 268
spr 1
Count register
FPSCR
pmr 128–131 UPMLCas3
32
Condition register
spr 9
FPR31
Performance Monitor Registers (PMRs)
User General SPR (Read/Write)
63
spr 512 SPEFSCR
ACC
3
3
L1 Cache (Read-Only)
spr 515
L1CFG03
spr 516
3
L1CFG1
L1 cache configuration
registers 0–1
General SPRs (Read-Only)
spr 259
spr 260
SPRG3
spr 263
SPRG7
SPRG4
SPR general
registers 3–7
TBL
TBU
spr 269
Time base
lower/upper
3
spr 526
ATBL
spr 527
ATBU 3
Alternate Time base
lower/upper
Supervisor-Level Registers
Interrupt Registers
32
32
Interrupt vector
prefix register
spr 63
IVPR
spr 26
SRR0
spr 27
SRR1
CSRR0
spr 58
spr 59
CSRR1
spr 570 MCSRR03
spr 571 MCSRR13
spr 574 DSRR03
spr 575
DSRR13
spr 62
ESR
MCSR
spr 573
MCAR3
DEAR
Critical SRR 0/1
Machine check
SRR 0/1
Debug SRR 0/1
DBCR0–2
Machine check
syndrome register
Machine check
address register
Data exception
address register
Debug control 0–2
spr 561
DBCR3
Debug control 3
spr 304
DBSR
Debug status register
spr 312–315
spr 316–317
spr 318–319
IACs
DACs
DVCs
spr 400
IVOR0
spr 401
IVOR1
32
Interrupt vector offset
registers 0–15
Instruction address
compare1–4
Data address
compare 1–2
Data value
compare 1–2
spr 1023
63
MSR
Machine state register
SVR 3
System version
register
spr 415
IVOR15
spr 286
PIR
Processor ID register
spr 528
IVOR323
spr 287
PVR
Processor version
register
spr 529
spr 530
spr 531
IVOR333
IVOR343
Interrupt vector offset
registers 32–35
IVOR353
MMU Control and Status (Read/Write)
Debug Registers
spr 308–310
63
Save/restore
registers 0/1
Exception syndrome
register
3
spr 572
spr 61
Configuration Registers
63
spr 1012 MMUCSR0 3
MMU control and status
register 0
3
spr 624
MAS0
spr 625
MAS1 3
spr 630
MAS6 3
spr 944
MAS7 3
spr 48
spr 633
PID0
PID13
spr 634
PID23
MMU assist
registers 0–7
spr 688 TLB0CFG3
spr 689 TLB1CFG3
spr 22
DEC
spr 54
DECAR
Decrementer
Decrementer
auto-reload register
spr 284
TBL
spr 285
TBU
Time base
lower/upper
spr 340
TCR
Timer control register
spr 336
TSR
Timer status register
Miscellaneous Registers
spr 272–279
Process ID
registers 0–2
spr 1008
spr 1009
MMU Control and Status (Read Only)
spr 1015 MMUCFG3
Timer/Decrementer Registers
MMU configuration
TLB configuration 0/1
L1 Cache (Read/Write)
spr 1010
spr 1011
L1CSR03
L1CSR13
L1 cache control/status
registers 0/1
spr 1015
L1FINV0 3
L1 flush and invalidate
control register 0
SPRG0–7
3
HID0
HID1 3
General SPRs 0–7
Hardware
implementation
dependent 0–1
Performance Monitor Registers
pmr 400
PMGC03
Global control
pmr 16–19
PMC0–33
Counter registers 0–3
pmr 144–147 PMCa0–33
Local control a0–a3
pmr 272–275 PMCb0–33
Local control b0–b3
1. The 64-bit GPR registers are accessed by the SPE as separate 32-bit operands by SPE instructions. Only
SPE vector instructions can access the upper word.
2. USPRG0 is a separate physical register from SPRG0.
3. EIS-defined registers; not part of the Book E architecture.
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3.2.1
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Special-purpose registers (SPRs)
SPRs are on-chip registers that are architecturally part of the processor core. They control
the use of the debug facilities, timers, interrupts, memory management unit, and other
architected processor resources and are accessed with the mtspr and mfspr instructions.
Unlisted encodings are reserved for future use.
Table 7 summarizes SPRs defined in Book E. The SPR numbers are used in the instruction
mnemonics. Bit 5 in an SPR number indicates whether an SPR is accessible from user or
supervisor software. An mtspr or mfspr instruction that specifies an unsupported SPR
number is considered an invalid instruction. Invalid instructions are treated as follows:

If the invalid SPR falls within the range specified as user mode (SPR[5] = 0), an illegal
exception is taken.

If supervisor software attempts to access an invalid supervisor-level SPR (SPR[5] = 1),
results are undefined.

If user software attempts to access an invalid supervisor-level SPR, a privilege
exception is taken.
Table 7. Book E special purpose registers (by SPR abbreviation)
Defined SPR number
SPR
Abbreviation
Name
CSRR0
Access
Supervisor
only
Decimal
Binary
Critical save/restore register 0
(CSRR0)
58
00001 11010
Read/Write
Yes
CSRR1
Critical save/restore register 1
(CSRR1)
59
00001 11011
Read/Write
Yes
CTR
Count register (CTR)
9
00000 01001
Read/Write
No
DAC1
Data address compare registers
(DAC1–DAC2)
316
01001 11100
Read/Write
Yes
DAC2
Data address compare registers
(DAC1–DAC2)
317
01001 11101
Read/Write
Yes
DBCR0
Debug control registers (DBCR0–
DBCR3) 1
308
01001 10100
Read/Write
Yes
DBCR1
Debug control registers (DBCR0–
DBCR3) 2
309
01001 10101
Read/Write
Yes
DBCR2
Debug control registers (DBCR0–
DBCR3) 3
310
01001 10110
Read/Write
Yes
DBSR
Debug status register (DBSR)
304
01001 10000
Read/Clear(1)
Yes
DEAR
Data exception address register
(DEAR)
61
00001 11101
Read/Write
Yes
DEC
Decrementer register
22
00000 10110
Read/Write
Yes
DECAR
Decrementer auto-reload register
(DECAR)
54
00001 10110
Write-only
Yes
DVC1
Data value compare registers
(DVC1 and DVC2) 1
318
01001 11110
Read/Write
Yes
319
01001 11111
Read/Write
Yes
DVC2
50/1025
Data value compare registers
(DVC1 and DVC2) 2
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RM0004
Register model
Table 7. Book E special purpose registers (by SPR abbreviation) (continued)
SPR
Abbreviation
Defined SPR number
Name
Decimal
Binary
Access
Supervisor
only
ESR
Exception syndrome register
(ESR)
62
00001 11110
Read/Write
Yes
IAC1
IAC2
IAC3
IAC4
Instruction address compare
registers (IAC1–IAC4)
312
313
314
315
01001 11000
01001 11001
01001 11010
01001 11011
Read/Write
Yes
IVOR0
Interrupt vector offset registers
(IVORs)
Critical input
400
01100 10000
Read/Write
Yes
IVOR1
Interrupt vector offset registers
(IVORs)
Machine check interrupt offset
401
01100 10001
Read/Write
Yes
IVOR10
Interrupt vector offset registers
(IVORs)
Decrementer interrupt offset
410
01100 11010
Read/Write
Yes
IVOR11
Interrupt vector offset registers
(IVORs)
Fixed-interval timer interrupt offset
411
01100 11011
Read/Write
Yes
IVOR12
Interrupt vector offset registers
(IVORs)
Watchdog timer interrupt offset
412
01100 11100
Read/Write
Yes
IVOR13
Interrupt vector offset registers
(IVORs)
Data TLB error interrupt offset
413
01100 11101
Read/Write
Yes
IVOR14
Interrupt vector offset registers
(IVORs)
Instruction TLB error interrupt
offset
414
01100 11110
Read/Write
Yes
IVOR15
Interrupt vector offset registers
(IVORs)
Debug interrupt offset
415
01100 11111
Read/Write
Yes
IVOR2
Interrupt vector offset registers
(IVORs)
Data storage interrupt offset
402
01100 10010
Read/Write
Yes
IVOR3
Interrupt vector offset registers
(IVORs)
Instruction storage interrupt offset
403
01100 10011
Read/Write
Yes
IVOR4
Interrupt vector offset registers
(IVORs)
External input interrupt offset
404
01100 10100
Read/Write
Yes
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Register model
RM0004
Table 7. Book E special purpose registers (by SPR abbreviation) (continued)
SPR
Abbreviation
Defined SPR number
Name
Decimal
Binary
Access
Supervisor
only
IVOR5
Interrupt vector offset registers
(IVORs)
Alignment interrupt offset
405
01100 10101
Read/Write
Yes
IVOR6
Interrupt vector offset registers
(IVORs)
Program interrupt offset
406
01100 10110
Read/Write
Yes
IVOR7
Interrupt vector offset registers
(IVORs)
Floating-point unavailable interrupt
offset
407
01100 10111
Read/Write
Yes
IVOR8
Interrupt vector offset registers
(IVORs)
System call interrupt offset
408
01100 11000
Read/Write
Yes
IVOR9
Interrupt vector offset registers
(IVORs)
APU unavailable interrupt offset
409
01100 11001
Read/Write
Yes
IVPR
Interrupt vector offset registers
(IVORs)
Interrupt vector
63
00001 11111
Read/Write
Yes
LR
Link register (LR)
8
00000 01000
Read/Write
No
PID
Process ID registers (PID0–PIDn)
48
00001 10000
Read/Write
Yes
PIR
Processor ID register (PIR)
286
01000 11110
Read-only
Yes
PVR
Processor version register (PVR)
287
01000 11111
Read-only
Yes
Software use sprs (SPRG0–
SPRG7 and USPRG0)
272
273
274
275
276
277
278
279
01000 10000
01000 10001
01000 10010
01000 10011
01000 10100
01000 10101
01000 10110
01000 10111
Read/Write
Yes
SRR0
Save/restore register 0 (SRR0)
26
00000 11010
Read/Write
Yes
SRR1
Save/restore register 1 (SRR1)
27
00000 11011
Read/Write
Yes
TBL
TBU
Time base (TBU and TBL)
284
285
01000 11100
01000 11101
Write-only
Yes
TCR
Timer control register (TCR)
340
01010 10100
Read/Write
Yes
SPRG0
SPRG1
SPRG2
SPRG3
SPRG4
SPRG5
SPRG6
SPRG7
TSR
52/1025
Timer status register (TSR)
336
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01010 10000
Read/Clear
(2)
Yes
RM0004
Register model
Table 7. Book E special purpose registers (by SPR abbreviation) (continued)
SPR
Abbreviation
Defined SPR number
Name
Access
Supervisor
only
Decimal
Binary
Software use sprs (SPRG0–
SPRG7 and USPRG0)(3)
256
259
260
261
262
263
01000 00000
01000 00011
01000 00100
01000 00101
01000 00110
01000 00111
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
No
UTBL
Time base (TBU and TBL)
268
01000 01100
Read-only
No
UTBU
Time base (TBU and TBL)
269
01000 01101
Read-only
No
1
00000 00001
Read/Write
No
USPRG0
USPRG3
USPRG4
USPRG5
USPRG6
USPRG7
XER
Integer exception register (XER)
1. The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits in the GPR can
be cleared using mtspr.
2. The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be
cleared using mtspr.
3. User-mode read access to SPRG3 is implementation-dependent
Table 8 lists EIS-defined SPRs. Compilers should recognize the mnemonic name given in
this table when parsing instructions.
Table 8. EIS–defined SPRs (by SPR abbreviation)
SPR
abbreviation
Name
SPR
number
Access
Supervisor
Section/page
only
ATBL
Alternate time base lower
526
Read-only
No
Section 3.15
on page 123
ATBU
Alternate time base upper
527
Read-only
No
Section 3.15
on page 123
DBCR3
Debug control register 3
561
Read/Write
Yes
Section 3.13.
1.4 on page
116
DSRR0
Debug save/restore register 0
574
R/W
Yes
Section 3.9.1.
10 on page
89
DSRR1
Debug save/restore register 1
575
R/W
Yes
Section 3.9.1.
11 on page 89
HID0
Hardware implementation dependent register 0
1008
Read/Write
Yes
Section 3.7.1
on page 72
HID1
Hardware implementation dependent register 1
1009
Read/Write
Yes
Section 3.7.2
on page 75
IVOR32
SPE/embedded floating-point APU unavailable
interrupt offset
528
Read/Write
Yes
Section 3.9.1.
7 on page 85
IVOR33
Embedded floating-point data exception
interrupt offset
529
Read/Write
Yes
Section 3.9.1.
7 on page 85
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Register model
RM0004
Table 8. EIS–defined SPRs (by SPR abbreviation) (continued)
SPR
abbreviation
Name
SPR
number
Access
Supervisor
Section/page
only
IVOR34
Embedded floating-point round exception
interrupt offset
530
Read/Write
Yes
Section 3.9.1.
7 on page 85
IVOR35
Performance monitor
531
Read/Write
Yes
Section 3.9.1.
7 on page 85
IVOR36
Processor doorbell interrupt. Defined by
processor signalling APU.
532
Read/Write
Yes
Section 3.9.1.
7 on page 85
IVOR37
Processor doorbell critical interrupt. Defined by
processor signalling APU.
533
Read/Write
Yes
Section 3.9.1.
7 on page 85
L1CFG0
L1 cache configuration register 0
515
Read-only
No
Section 3.11.
1 on page 92
L1CFG1
L1 cache configuration register 1
516
Read-only
No
Section 3.11.
2 on page 94
L1CSR0
L1 cache control and status register 0
1010
Read/Write
Yes
Section 3.11.
1 on page 92
L1CSR1
L1 cache control and status register 1
1011
Read/Write
Yes
Section 3.11.
2 on page 94
L1FINV0
L1 flush and invalidate control register 0
1016
Read/Write
Yes
Section 3.11.
5 on page 98
MAS0
MMU assist register 0
624
Read/Write
Yes
Section 3.12.
5 on page
103
MAS1
MMU assist register 1
625
Read/Write
Yes
Section 3.12.
5 on page
103
MAS2
MMU assist register 2
626
Read/Write
Yes
Section 3.12.
5 on page
103
MAS3
MMU assist register 3
627
Read/Write
Yes
Section 3.12.
5 on page
103
MAS4
MMU assist register 4
628
Read/Write
Yes
Section 3.12.
5 on page
103
MAS5
MMU assist register 5.
629
Read/Write
Yes
Section 3.12.
5 on page
103
MAS6
MMU assist register 6
630
Read/Write
Yes
Section 3.12.
5 on page
103
MAS7
MMU assist register 7
944
Read/Write
Yes
Section 3.12.
5 on page
103
54/1025
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RM0004
Register model
Table 8. EIS–defined SPRs (by SPR abbreviation) (continued)
SPR
abbreviation
SPR
number
Access
Machine check address register
573
Read-only
Yes
Section 3.9.1.
14 on page
90
Machine check address register upper
569
Read-only
Yes
Section 3.9.1.
14 on page
90
Machine check syndrome register
572
Read/Write
Yes
Section 3.9.1.
15 on page
90
MCSRR0
Machine-check save/restore register 0
570
Read/Write
Yes
Section 3.9.1.
12 on page
89
MCSRR1
Machine-check save/restore register 1
571
Read/Write
Yes
Section 3.9.1.
12 on page
89
MMUCFG
MMU configuration register
1015
Read-only
Yes
Section 3.12.
3 on page
101
MMUCSR0
MMU control and status register 0
1012
Read/Write
Yes
Section 3.12.
2 on page
100
MCAR
MCARU
MCSR
Name
Supervisor
Section/page
only
PID0
Process ID register 0. Book E defines only this
PID register and refers to as PID, not PID0.
48
Read/Write
Yes
Section 3.12.
1 on page 99
PID1
Process ID register 1
633
Read/Write
Yes
Section 3.12.
1 on page 99
PID2
Process ID register 2
634
Read/Write
Yes
Section 3.12.
1 on page 99
Signal processing and embedded floating-point
status and control register
512
Read/Write
No
Section 3.14.
1 on page
120
System version register
1023
Read-only
Yes
Section 3.7.5
on page 77
TLB0CFG
TLB configuration register 0
688
Read-only
Yes
Section 3.12.
4 on page
102
TLB1CFG
TLB configuration register 1
689
Read-only
Yes
Section 3.12.
4 on page
102
SPEFSCR
SVR
3.3
Registers for integer operations
The following sections describe registers defined for integer computational instructions.
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Register model
3.3.1
RM0004
General purpose registers (GPRs)
Book E implementations provide 32 GPRs (GPR0–GPR31) for integer operations. The
instruction formats provide 5-bit fields for specifying the GPRs to be used in the execution of
the instruction.
The Book E architecture defines 32-bit GPRs for 32-bit implementations; however, several
APUs make use of GPRs that are extended to 64 bits to accommodate either vector
operands or embedded double-precision floating point operands. The following APUs use
the extended 64-bit GPRs:
56/1025

The signal processing engine (SPE) APU and the embedded vector single-precision
floating-point APU treat the 64-bit operands as consisting of two, 32-bit elements, as
shown in Figure 4.

The embedded scalar double-precision floating-point APU treats the GPRs as single
64-bit operands that accommodate IEEE double-precision values.
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RM0004
Register model
Figure 4. SPE and floating point APU GPR usage
Register Model
User-Level Registers
0
SPE APU
31
32
Int/Frac
Int/Frac
Int/Frac
Int/Frac
Int/Frac
…
…
Int/Frac
General-purpose
registers (GPRs)
31
Interrupt Registers
spr 405
IVOR5
spr 528
IVOR32
SPE/floating-point
status/control
63
32
Single-prec. Single-prec.
Single-prec. Single-prec.
…
General-purpose
registers (GPRs)1
…
ACC
3
1 32
IVOR5
Alignment
spr 528
IVOR32
SPE/Embedded
Floating-point
SPE/floating-point
status/control
63
32
General-purpose
registers (GPRs) 1
…
0
31 32
spr 405
IVOR5
Alignment
spr 528
IVOR32
SPE/Embedded
Floating-point
SPE/floating-point
status/control
63
32
Double-precision
Double-precision
General-purpose
registers (GPRs) 1
…
spr 512 SPEFSCR
Machine state
Interrupt Registers
spr 62 ESR[SPE]
Exception syndrome
Interrupt Vector Offset Registers
Double-precision
ACC
63
MSR[SPE]
Double-precision
Scalar
Double-Precision
Floating-Point
APU
Exception syndrome
Interrupt Vector Offset Registers
Accumulator
spr 512 SPEFSCR
Machine state
Interrupt Registers
spr 62 ESR[SPE]
Single-prec.
ACC
63
MSR[SPE]
Single-prec.
Single-prec.
Exception syndrome
spr 405
Single-prec.
Scalar
Single-Precision
Floating-Point
APU
Machine state
Interrupt Vector Offset Registers
Accumulator
spr 512 SPEFSCR
Alignment
SPE/Embedded
Floating-point
Interrupt Registers
spr 62 ESR[SPE]
Single-prec. Single-prec.
0
Exception syndrome
63
MSR[SPE]
Single-prec. Single-prec.
Vector
Single-Precision
Floating-Point
APU
Machine state
Interrupt Vector Offset Registers
Accumulator
32
63
spr 62 ESR[SPE]
Int/Frac
spr 512 SPEFSCR
0
32
MSR[SPE]
ACC
Original SPE
APU
Supervisor-Level Registers
63
Int/Frac
Instruction Model
Accumulator
spr 405
IVOR5
Alignment
spr 528
IVOR32
SPE/Embedded
Floating-point
SPE/floating-point
status/control
Computation Load/Store
brinc
evmra
evm…
evabs
evadd…
evand…
evfsctuiz
evcntl…
evdiv…
evmerge…
evsub…
logical, rotate,
shift, extend,
round, select,
compare
evldh…
evldw…
evldd…
evl…splat…
evlwhos…
evlwh…
evstdd…
evstdh…
evstdw…
evstwh…
efvcf…
efvct…
efvabs
efvadd
efvcmp…
efvdiv
efvmul
efvneg
efvnabs
efvsub
efvtst…
From SPE:
evmergehi
evmergelo
From SPE:
evldd
evlddx
evstdd
evstddx
efscf…
efsct…
efsabs
efsadd
efscmp…
efsdiv
efsmul
efsneg
efsnabs
efssub
efstst…
Uses
PowerPC
UISA 32-bit
loads and
stores
efdcf…
efdct…
efdabs
efdadd
efdcmp…
efddiv
efdmul
efdneg
efdnabs
efdsub
efdtst…
From SPE:
evmergehi
evmergelo
From SPE:
evldd
evlddx
evstdd
evstddx
1. Gray text indicates that the APU does not use this register or register field.
Formatting of floating-point operands is as defined by IEEE 754, as described in the APU chapter of the
EREF.
As shown in Figure 4, the embedded scalar single-precision floating-point APU uses 32-bit
operands that, like 32-bit Book E instructions, do not affect the upper word of the 64-bit
GPRs. For 32-bit implementations that implement 64-bit GPRs, all instructions except SPE
APU, embedded vector single-precision APU, and embedded scalar double-precision APU
instructions use and return 32-bit values in GPR bits 32–63.
3.3.2
Integer exception register (XER)
Bits in the integer exception register (XER) are set based on the operation of an instruction
considered as a whole, not on intermediate results. (For example, the subtract from carrying
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Register model
RM0004
instruction (subfc), the result of which is specified as the sum of three values, sets bits in
the XER based on the entire operation, not on an intermediate sum.)
Figure 5. Integer exception register (XER)
Access: User read-write
SPR1
32
56 57
63
R
SO OV CA
—
Number of bytes
W
Reset
All zeros
Table 9 describes XER bit definitions.
Table 9. XER field descriptions
Bits
Name
Description
SO
Summary overflow. Set when an instruction (except mtspr) sets the overflow bit (OV). Once set,
SO remains set until it is cleared by mtspr[XER] or mcrxr. SO is not altered by compare
instructions or by other instructions (except mtspr[XER] and mcrxr) that cannot overflow.
Executing mtspr[XER], supplying the values 0 for SO and 1 for OV, causes SO to be cleared and
OV to be set.
OV
Overflow. X-form add, subtract from, and negate instructions having OE=1 set OV if the carry out
of bit 32 is not equal to the carry out of bit 33, and clear OV otherwise to indicate a signed
overflow. X-form multiply low word and divide word instructions having OE=1 set OV if the result
cannot be represented in 32 bits (mullwo, divwo, and divwuo) and clear OV otherwise. OV is not
altered by compare instructions or by other instructions (except mtspr[XER] and mcrxr) that
cannot overflow.
34
CA
Carry. Add carrying, subtract from carrying, add extended, and subtract from extended
instructions set CA if there is a carry out of bit 32 and clear it otherwise. CA can be used to
indicate unsigned overflow for add and subtract operations that set CA. Shift right algebraic word
instructions set CA if any 1 bits are shifted out of a negative operand and clear CA otherwise.
Compare instructions and instructions that cannot carry (except Shift Right Algebraic Word,
mtspr[XER], and mcrxr) do not affect CA.
35–56
—
Reserved, should be cleared.
32
33
57–63
58/1025
No. of Supports emulation of load and store string instructions. Specifies the number of bytes to be
Bytes transferred by a load string indexed or store string indexed instruction.
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RM0004
3.4
Register model
Registers for floating-point operations
This section details floating-point registers and their field descriptions.
3.4.1
Floating-point registers (FPRs)
Book E defines 32 floating-point registers (FPR0–FPR31). Floating-point instruction formats
provide 5-bit fields for specifying FPRs used in instruction execution.
Each FPR contains 64 bits that support the floating-point format. Instructions that interpret
FPR contents as floating-point values use double-precision format for this interpretation.
The computational instructions and the move and select instructions operate on data in
FPRs and, except for compare instructions, place the result into an FPR, and optionally
place status information into the CR.
Load and store double instructions are provided that transfer 64 bits of data between
memory and the FPRs with no conversion. Load single instructions are provided to transfer
and convert floating-point values in floating-point single format from memory to the same
value in floating-point double format in the FPRs. Store single instructions are provided to
transfer and convert floating-point values in floating-point double format from the FPRs to
the same value in floating-point single format in memory.
Instructions are provided that manipulate the FPSCR and the CR explicitly. Some of these
instructions copy data between an FPR and the FPSCR.
The computational instructions and the select instruction accept values from the FPRs in
double format. For single-precision arithmetic instructions, all input values must be
representable in single format; if they are not, the result placed into the target FPR, and the
setting of status bits in the FPSCR and in the CR (if Rc = 1), are undefined.
3.4.2
Floating-point status and control register (FPSCR)
The FPSCR, shown below, controls how floating-point exceptions are handled and records
status resulting from floating-point operations. FPSCR[32–55] are status bits; FPSCR[56–
63] are control bits.
Figure 6. Floating-point status and control register (FPSCR)
Access: User read/write
32
33
34
35
36
37
38
FX
FEX
VX
OX
UX
ZX
XX
39
40
41
42
43
44
45
46
47
VXSNAN VXISI VXIDI VXZDZ VXIMZ VXVC FR
FI
C
62
63
R
W
Reset
All zeros
48
51
52
53
54
55
56
57
58
59
60
61
VE
OE
UE
ZE
XE
NI
R
FPCC
— VXSOFT VXSQRT VXCVI
RN
W
Reset
All zeros
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RM0004
The exception bits, FPSCR[35–45,53–55], are sticky; once set they remain set until they are
cleared by an mcrfs, mtfsfi, mtfsf, or mtfsb0. Exception summary bits FPSCR[FX,FEX,VX]
are not considered to be exception bits, and only FX is sticky.
FEX and VX are simply the ORs of other FPSCR bits, and so are not listed among the
FPSCR bits affected by the various instructions. FPSCR fields are described in Table 10.
Table 10. FPSCR field descriptions
Bits
Name
Description
32
FX
Floating-point exception summary. Every floating-point instruction, except mtfsfi and mtfsf,
implicitly sets FX if that instruction causes any of the floating-point exception bits in the FPSCR to
change from 0 to 1. mcrfs, mtfsfi, mtfsf, mtfsb0, and mtfsb1 can alter FPSCR[FX] explicitly.
33
FEX
Floating-point enabled exception summary. FEX is the OR of all the floating-point exception bits
masked by their respective enable bits. mcrfs, mtfsfi, mtfsf, mtfsb0, and mtfsb1 cannot alter
FPSCR[FEX] explicitly.
34
VX
Floating-point invalid operation exception summary. VX is the OR of all the invalid operation
exception bits. mcrfs, mtfsfi, mtfsf, mtfsb0, and mtfsb1 cannot alter FPSCR[VX] explicitly.
35
OX
Floating-point overflow exception
36
UX
Floating-point underflow exception
37
ZX
Floating-point zero divide exception
XX
Floating-point inexact exception.
FPSCR[XX] is a sticky version of FPSCR[FI] (see below). Thus the following rules completely
describe how FPSCR[XX] is set by a given instruction:
If the instruction affects FPSCR[FI], the new FPSCR[XX] value is obtained by ORing the old
value of FPSCR[XX] with the new value of FPSCR[FI].
If the instruction does not affect FPSCR[FI], the value of FPSCR[XX] is unchanged.
38
39
VXSNAN Floating-point invalid operation exception (SNaN)
40
VXISI
Floating-point invalid operation exception ()
41
VXIDI
Floating-point invalid operation exception ()
42
VXZDZ
Floating-point invalid operation exception (0 0)
43
VXIMZ
Floating-point invalid operation exception ()
44
VXVC
Floating-point invalid operation exception (invalid compare).
45
FR
Floating-point fraction rounded. The last arithmetic or rounding and conversion instruction
incremented the fraction during rounding. This bit is not sticky.
46
FI
Floating-point fraction inexact. The last arithmetic or rounding and conversion instruction either
produced an inexact result during rounding or caused a disabled overflow exception. This bit is
not sticky. The definition of FPSCR[XX] describes the relationship between FPSCR[FI] and
FPSCR[XX].
47–
51
FPRF
Floating-point result flags. Set as described below in Table 10. For arithmetic, rounding, and
conversion instructions, FPRF is set based on the result placed into the target register, except
that if any portion of the result is undefined, the value placed into FPRF is undefined.
47
C
Floating-point result class descriptor. Arithmetic, rounding, and conversion instructions may set
this bit with the FPCC bits, to indicate the class of the result.
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Table 10. FPSCR field descriptions (continued)
Bits
Name
Description
48–
51
FPCC
Floating-point condition code. Floating-point Compare instructions set one of the FPCC bits and
clear the other three FPCC bits. Arithmetic, rounding, and conversion instructions may set the
FPCC bits with the C bit to indicate the class of the result. In this case, the three high-order FPCC
bits retain their relational significance indicating that the value is less than, greater than, or equal
to zero.
48 Floating-point less than or negative (FL or <)
49 Floating-point greater than or positive (FG or >)
50 Floating-point equal or zero (FE or =)
51 Floating-point unordered or NaN (FU or ?)
52
—
53
VXSOFT
54
Floating-point invalid operation exception (invalid square root).
Note that VXSQRT is defined even for implementations that do not support either of the two
VXSQRT optional instructions that set it, fsqrt[.] and frsqrte[.]. Defining it for all implementations gives
software a standard interface for handling square root exceptions. If an implementation does not
support fsqrt[.] or frsqrte[.], software can simulate the instruction and set VXSQRT to reflect the
exception.
Reserved, should be cleared.
Floating-point invalid operation exception (software request). Can be altered only by mcrfs,
mtfsfi, mtfsf, mtfsb0, or mtfsb1.
55
VXCVI
56
VE
Floating-point invalid operation exception enable
57
OE
Floating-point overflow exception enable
58
UE
Floating-point underflow exception enable
59
ZE
Floating-point zero divide exception enable
60
XE
Floating-point inexact exception enable
NI
Floating-point non-IEEE mode. If NI = 1, the remaining FPSCR bits may have meanings other
than those given in this document and results of floating-point operations need not conform to the
IEEE standard. If the IEEE-conforming result of a floating-point operation would be a
denormalized number, the result of that operation is 0 (with the same sign as the denormalized
number) if FPSCR[NI] = 1 and other requirements specified in the user’s manual for the
implementation are met. The other effects of setting NI may differ among implementations.
Setting NI is intended to permit results to be approximate and to cause performance to be more
predictable and less data-dependent than when NI = 0. For example, in non-IEEE mode, an
implementation returns 0 instead of a denormalized number and may return a large number
instead of an infinity. In non-IEEE mode an implementation should provide a means for ensuring
that all results are produced without software assistance (that is, without causing an enabled
exception type program interrupt or a floating-point unimplemented instruction exception type
program interrupt and without invoking an emulation assist). The means may be controlled by
one or more other FPSCR bits (recall that the other FPSCR bits have implementation-dependent
meanings if NI = 1).
RN
Floating-point rounding control (RN).
00 Round to nearest
01 Round toward zero
10 Round toward +infinity
11 Round toward –infinity
61
62–
63
Floating-point invalid operation exception (invalid integer convert)
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Table 11 describes floating-point result flags.
Table 11. Floating-point result flags
Result flags
Result value class
3.5
C
<
>
=
?
1
0
0
0
1
Quiet NaN
0
1
0
0
1
–Infinity
0
1
0
0
0
–Normalized number
1
1
0
0
0
–Denormalized number
1
0
0
1
0
–Zero
0
0
0
1
0
+Zero
1
0
1
0
0
+Denormalized number
0
0
1
0
0
+Normalized number
0
0
1
0
1
+Infinity
Registers for branch operations
This section describes registers used by Book E branch and CR operations.
3.5.1
Condition register (CR)
The 32-bit CR reflects the result of certain operations and provides a mechanism for testing
and branching.
Figure 7. Condition register (CR)
Access: User read/write
32
35 36
39 40
43 44
47 48
51 52
55 56
59 60
63
R
CR0
CR1
CR2
CR3
CR4
CR5
CR6
CR7
W
Reset
All zeros
CR bits are grouped into eight 4-bit fields, CR0–CR7, which are set as follows:

Specified CR fields can be set by a move to the CR from a GPR (mtcrf).

A specified CR field can be set by a move to the CR from another CR field (mcrf), from
the FPSCR (mcrfs), or from the XER (mcrxr).

CR0 can be set as the implicit result of an integer instruction.

CR1 can be set as the implicit result of a floating-point instruction.

A specified CR field can be set as the result of either an integer or a floating-point
compare instruction (including SPE and SPFP compare instructions).
Instructions are provided to perform logical operations on individual CR bits and to test
individual CR bits (see Section 4.6.6.4: Condition register instructions).
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Note that instructions that access CR bits (for example, Branch Conditional (bc), CR
logicals, and Move to Condition Register Field (mtcrf)) determine the bit position by adding
32 to the operand value. For example, in conditional branch instructions, the BI operand
accesses bit BI + 32, as shown in Table 12.
Table 12. BI operand settings for CR fields
CRn
Bits
CR
Bits
BI
Description
32
Negative (LT)—Set when the result is negative.
For SPE compare and test instructions:
00000
Set if the high-order element of rA is equal to the high-order element of rB; cleared
otherwise.
CR0[1]
33
Positive (GT)—Set when the result is positive (and not zero).
For SPE compare and test instructions:
00001
Set if the low-order element of rA is equal to the low-order element of rB; cleared
otherwise.
CR0[2]
34
Zero (EQ)—Set when the result is zero.
00010 For SPE compare and test instructions:
Set to the OR of the result of the compare of the high and low elements.
CR0[3]
35
Summary overflow (SO). Copy of XER[SO] at the instruction’s completion. For SPE
00011 compare and test instructions:
Set to the AND of the result of the compare of the high and low elements.
36
Copy of FPSCR[FX] at the instruction’s completion. Negative (LT)
For SPE and SPFP compare and test instructions:
00100
Set if the high-order element of rA is equal to the high-order element of rB; cleared
otherwise.
37
Copy of FPSCR[FEX] at the instruction’s completion. Positive (GT)
For SPE and SPFP compare and test instructions:
00101
Set if the low-order element of rA is equal to the low-order element of rB; cleared
otherwise.
CR1[2]
38
Copy of FPSCR[VX] at the instruction’s completion. Zero (EQ)
00110 For SPE and SPFP compare and test instructions:
Set to the OR of the result of the compare of the high and low elements.
CR1[3]
39
Copy of FPSCR[OX] at the instruction’s completion. Summary overflow (SO)
00111 For SPE and SPFP compare and test instructions:
Set to the AND of the result of the compare of the high and low elements.
CRn[0]
40
44
48
52
56
60
01000
01100
10000
10100
11000
11100
CR0[0]
CR1[0]
CR1[1]
Less than or floating-point less than (LT, FL).
For integer compare instructions:
rA < SIMM or rB (signed comparison) or rA < UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA < frB.
For SPE and SPFP compare and test instructions:
Set if the high-order element of rA is equal to the high-order element of rB; cleared
otherwise.
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Table 12. BI operand settings for CR fields (continued)
CRn
Bits
CR
Bits
BI
CRn[1]
41
45
49
53
57
61
01001
01101
10001
10101
11001
11101
Greater than or floating-point greater than (GT, FG).
For integer compare instructions:
rA > SIMM or rB (signed comparison) or rA > UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA > frB.
For SPE and SPFP compare and test instructions:
Set if the low-order element of rA is equal to the low-order element of rB; cleared
otherwise.
CRn[2]
42
46
50
54
58
62
01010
01110
10010
10110
11010
11110
Equal or floating-point equal (EQ, FE).
For integer compare instructions: rA = SIMM, UIMM, or rB.
For floating-point compare instructions: frA = frB.
For SPE and SPFP compare and test instructions:
Set to the OR of the result of the compare of the high and low elements.
CRn[3]
43
47
51
55
59
63
01011
01111
10011
10111
11011
11111
Summary overflow or floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of XER[SO] at the completion of the
instruction.
For floating-point compare instructions, one or both of frA and frB is a NaN.
For SPE and SPFP vector compare and test instructions:
Set to the AND of the result of the compare of the high and low elements.
3.5.1.1
Description
CR setting for integer instructions
For all integer word instructions in which the Rc bit is defined and set, and for addic., andi.,
and andis., CR0[32–34] are set by signed comparison of bits 32–63 of the result to zero;
CR[35] is copied from the final state of XER[SO]. The Rc bit is not defined for double-word
integer operations.
if
(target_register)32-63 < 0 then c  0b100
else if (target_register)32-63 > 0 then c  0b010
else
c  0b001
CR0  c || XERSO
The value of any undefined portion of the result is undefined, and the value placed into the
first three bits of CR0 is undefined. CR0 bits are interpreted as described in Table 13.
Table 13. CR0 bit descriptions
CR
bit
Name
32
Negative (LT)
Bit 32 of the result is equal to one.
33
Positive (GT)
Bit 32 of the result is equal to zero, and at least one of bits 33–63 of the result is
non-zero.
34
Zero (EQ)
35
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Bits 32–63 of the result are equal to zero.
Summary overflow (SO) This is a copy of the final state of XER[SO] at the completion of the instruction.
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Note that CR0 may not reflect the true (infinitely precise) result if overflow occurs.
3.5.1.2
CR setting for store conditional instructions
CR0 is also set by the integer store conditional instruction, stwcx.. See instruction
descriptions in Chapter 4: Instruction model, for detailed descriptions of how CR0 is set.
3.5.1.3
CR setting for floating-point instructions
For all floating-point instructions in which the Rc bit is defined and set, CR1 (CR[36–39]) is
copied from FPSCR[32–35]. These bits are interpreted as shown in Table 14.
Table 14. CR setting for floating-point instructions
Bit Name
3.5.1.4
Description
36
FX
Floating-point exception summary. Copy of final state of FPSCR[FX] at instruction
completion.
37
FEX
Floating-point enabled exception summary. Copy of final state of FPSCR[FEX] at
instruction completion.
38
VX
Floating-point invalid operation exception summary. Copy of final state of FPSCR[VX] at
completion.
39
OX
Floating-point overflow exception. Copy of final state of FPSCR[OX] at instruction
completion.
CR setting for compare instructions
For compare instructions, a CR field specified by the BI field in the instruction is set to reflect
the result of the comparison, as shown in Table 15.
Table 15. CR setting for compare instructions
CR Bits
CRn
bit
Bit expression
4 * cr0 + lt (or lt)
4 * cr1 + lt
4 * cr2 + lt
4 * cr3+ lt
CRn[0]
4 * cr4 + lt
4 * cr5 + lt
4 * cr6 + lt
4 * cr7 + lt
BI
AIM (BI
Operand)
Book
E
0
4
8
12
16
20
24
28
32
36
40
44
48
52
56
60
Description
0–2 3–4
000
001
010
011
100
101
110
111
00
Less than or floating-point less than (LT, FL).
For integer compare instructions: 
rA < SIMM or rB (signed comparison) or rA <
UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA <
frB.
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Table 15. CR setting for compare instructions (continued)
CR Bits
CRn
bit
Bit expression
BI
Description
AIM (BI
Operand)
Book
E
4 * cr0 + gt (or gt)
4 * cr1 + gt
4 * cr2 + gt
4 * cr3+ gt
CRn[1]
4 * cr4 + gt
4 * cr5 + gt
4 * cr6 + gt
4 * cr7 + gt
1
5
9
13
17
21
25
29
33
37
41
45
49
53
57
61
000
001
010
011
100
101
110
111
4 * cr0 + eq (or eq)
4 * cr1 + eq
4 * cr2 + eq
4 * cr3+ eq
CRn[2]
4 * cr4 + eq
4 * cr5 + eq
4 * cr6 + eq
4 * cr7 + eq
2
6
10
14
18
22
26
30
34
38
42
46
50
54
58
62
000
001
010
011
100
101
110
111
4 * cr0 + so/un (or
so/un)
4 * cr1 + so/un
4 * cr2 + so/un
CRn[3] 4 * cr3 + so/un
4 * cr4 + so/un
4 * cr5 + so/un
4 * cr6 + so/un
4 * cr7 + so/un
3
7
11
15
19
23
27
31
35
39
43
47
51
55
59
63
000
001
010
011
100
101
110
111
3.5.1.5
0–2 3–4
01
Greater than or floating-point greater than (GT,
FG).
For integer compare instructions: 
rA > SIMM or rB (signed comparison) or rA >
UIMM or rB (unsigned comparison).
For floating-point compare instructions: frA >
frB.
10
Equal or floating-point equal (EQ, FE).
For integer compare instructions: rA = SIMM,
UIMM, or rB.
For floating-point compare instructions: frA =
frB.
11
Summary overflow or floating-point unordered
(SO, FU).
For integer compare instructions, this is a copy
of XER[SO] at instruction completion.
For floating-point compare instructions, one or
both of frA and frB is a NaN.
CR bit settings in VLE mode
The VLE extension implements the entire CR, but some comparison operations and all
branch instructions are limited to using CR0–CR3. However, all Book E CR field and logical
operations are provided.
CR bits are grouped into eight 4-bit fields, CR0–CR7, which are set in one of the following
ways.

Specified CR fields can be set by a move to the CR from a GPR (mtcrf).

A specified CR field can be set by a move to the CR from another CR field (e_mcrf).

CR field 0 can be set as the implicit result of an integer instruction.

A specified CR field can be set as the result of an integer compare instruction.

CR field 0 can be set as the result of an integer bit test instruction.
Instructions are provided to perform logical operations on individual CR bits and to test
individual CR bits.
CR settings for integer instructions
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For all integer word instructions in which the Rc bit is defined and set, and for addic., the
first three bits of CR field 0 (CR[32–34]) are set by signed comparison of bits 32–63 of the
result to zero, and the fourth bit of CR field 0 (CR[35]) is copied from the final state of
XER[SO].
if
(target_register)32:63 < 0 then c  0b100
else if (target_register)32:63 > 0 then c  0b010
else
c  0b001
CR0  c || XERSO
If any portion of the result is undefined, the value placed into the first three bits of CR field 0
is undefined. The bits of CR field 0 are interpreted as shown in Table 16.
Table 16. CR0 encodings
CR bit
Description
32
Negative (LT). Bit 32 of the result is equal to 1.
33
Positive (GT). Bit 32 of the result is equal to 0 and at least one of bits 33–63 of the result is
non-zero.
34
Zero (EQ). Bits 32–63 of the result are equal to 0.
35
Summary overflow (SO). This is a copy of the final state XER[SO] at the completion of the
instruction.
CR setting for compare instructions supported by the VLE extension
For compare instructions, a CR field specified by the crD operand in the instruction for the
e_cmph, e_cmphl, e_cmpi, and e_cmpli instructions, or CR0 for the e_cmp16i,
e_cmph16i, e_cmphl16i, e_cmpl16i, se_cmp, se_cmph, se_cmphl, se_cmpi, and
se_cmpli instructions is set to reflect the result of the comparison. The CR field bits are
interpreted as shown in Table 17. A complete description of how the bits are set is given in
Chapter 7: Instruction set, and in Section 4.6.6.5: Integer instructions.
Table 17. Condition register setting for compare instructions
CR bit
Description
4CRD + 32
Less than (LT). For signed-integer compare, GPR(rA or rX) < SCI8 or SI or GPR(rB or rY).
For unsigned-integer compare, GPR(rA or rX) <u SCI8 or UI or UI5 or GPR(rB or rY).
4CRD + 33
Greater than (GT). For signed-integer compare, GPR(rA or rX) > SCI8 or SI or UI5 or GPR(rB or
rY).
For unsigned-integer compare, GPR(rA or rX) >u SCI8 or UI or UI5 or GPR(rB or rY).
4CRD + 34
Equal (EQ). For integer compare, GPR(rA or rX) = SCI8 or UI5 or SI or UI or GPR(rB or rY).
4CRD + 35
Summary overflow (SO). For integer compare, this is a copy of the final state of XER[SO] at the
completion of the instruction.
3.5.1.6
CR setting for the VLE bit test instruction
The Bit Test Immediate instruction, se_btsti, also sets CR field 0. See the instruction
description and also Section 4.6.6.5: Integer instructions.
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3.5.2
RM0004
Link register (LR)
The link register can be used to provide the branch target address for a Branch Conditional
to LR (bclrx) instruction, and it holds the return address after branch and link instructions.
Figure 8. Link register (LR)
SPR 8
Access: user read/write
32
63
R
Link address
W
Reset
All zeros
The LR contents are read into a GPR using mfspr. The contents of a GPR can be written to
the LR using mtspr. LR[62–63] are ignored by bclr instructions.
3.5.2.1
Link register usage in VLE mode
VLE instructions use the LR as defined in Book E, although the VLE extension defines a
subset of all variants of Book E conditional branches involving the LR, as shown in Table 18.
Note that because VLE instructions can reside on half-word boundaries, in VLE mode,
LR[30] is examined when the LR holds an instruction address.
Table 18. Branch to link register instruction comparison
Book E
VLE Subset
Instruction
3.5.3
Syntax
Instruction
Branch Conditional to Link Register
Branch Conditional to Link Register
& Link
Branch (Absolute) to Link
bclr BO,BI Register
bclrl BO,BI Branch (Absolute) to Link
Register & Link
Branch Conditional & Link
e_bcl
BO,BI,BD
Syntax
se_blr
se_blrl
Branch Conditional & Link
e_bcl
BO32,BI32,BD15
Branch (Absolute) & Link
e_bl BD24
se_bl BD8
Count register (CTR)
CTR can be used to hold a loop count that can be decremented and tested during execution
of branch instructions that contain an appropriately encoded BO field. If the CTR value is 0
before being decremented, it is –1 afterward. The entire CTR can be used to hold the
branch target address for a Branch Conditional to CTR (bcctrx) instruction.
Note that because VLE instructions can reside on half-word boundaries, in VLE mode,
CTR[30] is examined when the CTR holds an instruction address.
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Figure 9. Count register (CTR)
SPR 9
Access: user read/write
32
63
R
Count value
W
Reset
3.5.3.1
All zeros
Count register usage in VLE mode
VLE instructions use the CTR as defined by in Book E, although the VLE extension defines
a subset of the variants of Book E conditional branches involving the CTR, as shown in
Table 19.
Table 19. Branch to count register instruction comparison
Book E
Instruction
Branch conditional to count register
Branch conditional to count register & link
3.6
VLE
Syntax
Instruction
Branch (absolute) to count register
bcctr BO,BI
Branch (absolute) to count register &
bcctrl BO,BI
link
Syntax
se_bctr
se_bctrl
Processor control registers
This section addresses machine state, processor ID, and processor version registers.
3.6.1
Machine state register (MSR)
The MSR defines the state of the processor (that is, enabling and disabling of interrupts and
debugging exceptions, enabling and disabling of address translation for instruction and data
memory accesses, enabling and disabling some APUs, and specifying whether the
processor is in supervisor or user mode).
MSR contents are automatically saved, altered, and restored by the interrupt-handling
mechanism. If a non-critical interrupt is taken, MSR contents are automatically copied into
SRR1. If a critical interrupt is taken, MSR contents are automatically copied into CSRR1.
When an rfi or rfci is executed, MSR contents are restored from SRR1 or CSRR1.
The EIS-defined machine check APU defines additional save/restore resources. When a
machine check interrupt is taken, MCSRR0 and MCSRR1 hold the return address and MSR
information. The return from machine check interrupt instruction, rfmci, restores MCSRR1
contents to the MSR.
MSR contents are read into a GPR using mfmsr. The contents of a GPR can be written to
MSR using mtmsr. The write MSR external enable instructions (wrtee and wrteei) can be
used to set or clear MSR[EE] without affecting other MSR bits.
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Figure 10. Machine state register (MSR)
Access: supervisor-only
32
36
Book E/ R
EIS W
37
38 39
—
EIS R
APUs W
—
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
AP WE CE — EE PR FP ME FE0 — DE FE1 — IS DS
UCLE SPE
—
Reset
—
PMM —
All zeros
Table 20. MSR field descriptions
Bits
Name
32–36
—
Description
Reserved, should be cleared.(1)
UCLE
(Cache-locking APU) User-mode cache lock enable. Used to restrict user-mode cache-line
locking by the operating system.
0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and
sets either ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the
locking/unlocking of cache lines by user-mode tasks.
1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for
cache-locking. (They may still take a DSI for access violations though.)
38
SPE
(SPE, SPFP, DPFP APUs) SPE enable. Enables use of 64-bit extended GPRs used by SPE,
single-precision vector, and double-precision floating-point APUs/
0 If software attempts to execute an SPE APU instruction, the SPE APU unavailable exception
is taken.
1 Software can execute any of the SPE APU instructions.
Embedded floating-point instructions require MSR[SPE] to be set. An attempt to execute an
embedded floating-point instruction when MSR[SPE] is 0 results in an SPE APU unavailable
interrupt.
39–43
—
Reserved, should be cleared(1).
44
AP
APU available. Book E defines the operation of AP as follows:
0 The processor cannot execute APU instructions.
1 The processor can execute APU instructions.
45
WE
Wait state enable. Allows the core complex to signal a request for power management,
according to the states of HID0[DOZE], HID0[NAP], and HID0[SLEEP].
0 The processor is not in wait state and continues processing. No power management request
is signaled to external logic.
1 The processor enters wait state by ceasing to execute instructions and entering low-power
mode. Details of how wait state is entered and exited and how the processor behaves in the
wait state are implementation-dependent.
46
CE
Critical enable
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.
47
—
Preserved for Book III ILE
37
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Table 20. MSR field descriptions (continued)
Bits
Name
Description
EE
External enable
0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are
disabled.
1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are
enabled.
PR
User mode (problem state)
0 The processor is in supervisor mode, can execute any instruction, and can access any
resource (for example, GPRs, SPRs, and the MSR).
1 The processor is in user mode, cannot execute any privileged instruction, and cannot access
any privileged resource.
PR also affects memory access control.
50
FP
Floating-point available.
0 The processor cannot execute floating-point instructions, including floating-point loads, stores,
and moves.
1 The processor can execute floating-point instructions.
51
ME
Machine check enable.
0 Machine check interrupts are disabled.
1 Machine check interrupts are enabled.
52
FE0
Floating-point exception mode 0. The Book E definition of this bit is shown in Table 21.
53
—
Allocated for implementation-dependent use.
54
DE
Debug interrupt enable
0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] = 1.
See the description of the DBSR[UDE] in Section 3.13.2: Debug status register (DBSR).
55
FE1
Floating-point exception mode 1. The Book E definition of this bit is shown in Table 21.
56
—
Reserved, should be cleared(1).
57
—
Preserved for Book III IP
IS
Instruction address space
0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB
entry).
1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB
entry).
59
DS
Data address space
0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB
entry).
1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB
entry).
60
—
Reserved, should be cleared(1).
48
49
58
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Table 20. MSR field descriptions (continued)
Bits
Name
Description
61
PMM
(Performance monitor APU) Performance monitor mark bit. System software can set PMM when
a marked process is running to enable statistics gathering only during the execution of the
marked process. PMM and MSR[PR] together define a state that the processor (supervisor or
user) and the process (marked or unmarked) may be in at any time. If this state matches an
individual state specified in the PMLCax, the state for which monitoring is enabled, counting is
enabled.
62–63
—
Preserved for Book III RI and LE, respectively.
1. An MSR bit that is reserved may be altered by return from interrupt instructions.
The floating-point exception mode bits FE0 and FE1 are described in Table 21.
Table 21. Floating-point exception bits—MSR[FE0,FE1]
3.7
FE0
FE1
Mode
0
0
Ignore exceptions
0
1
Imprecise nonrecoverable
1
0
Imprecise recoverable
1
1
Precise
Hardware implementation-dependent registers
Each ST Book E processor implements hardware implementation-dependent registers,
HID0 and HID1,which contain fields defined either by the EIS or by the implementation. This
section provides architectural information about HID registers and describes only those bits
that are defined by the EIS.
Note:
Not all processors implement HID fields defined by the EIS. Consult the user
documentation.
An integrated device may not use all HID fields implemented on an embedded core or may
define those fields more specifically. Always begin by looking at the core register
descriptions in the reference manual for the integrated device.
3.7.1
Hardware implementation dependent register 0 (HID0)
HID0 is used for configuration and control. Figure below shows the HID0 bits that are
defined either generally by the EIS or as part of an EIS-defined APU. Note that not all EIScompliant device implement all HID0 fields; see the user documentation.
Writing to HID0 typically requires synchronization, as described in Section 3.18.2:
Synchronization requirements for SPRs.
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Register model
Figure 11. Hardware implementation dependent register 0 (HID0)
SPR 1008
32
R
W
33
34
35
EMC
P
Access: Supervisor-only
39 40
—
43
PWRMGMT
Reset
DPM
47
EDP
M
—
IPR
EN_MAS
7_
UPDATE
62
63
All zeros
48
49
R
EIEC
W
42
50
51
TBE SEL_TBC
N
LK
55
—
56 57
58
DAPUE SG
EIEIO_E
—
LWSYNC_EN —
N
E
N
Reset
NOPTS NOPDS
NOPTI
T
T
All zeros
HID0 fields are described in Table 22.
Table 22. HID0 field descriptions
Bits
Name
Description
32
EMCP
Enable machine check pin. Used to mask machine check exceptions delivered to the
core from the machine check input.
0 Machine check exceptions from the machine check signal are disabled.
1 Machine check exceptions from the machine check signal are enabled. If MSR[ME]
= 0, asserting the machine signal check causes a checkstop. If MSR[ME] = 1,
asserting the machine check signal causes a machine check exception.
33
—
34
SFR
35–39
—
40–42
PWRMGMT
43
44
Implementation dependent.
Sixty-four bit results. Determines how the upper 32 bits of 64-bit registers in a 64-bit
implementation are computed when the processor is executing in 32-bit mode
(MSR[CM] = 0).
0 In 32-bit mode, bits 0–31 of all 64-bit registers are not modified. Explicit 64-bit
instructions generate an unimplemented instruction exception when executed.
1 In 32-bit mode, bits 0–31 are written with the same value that is written as when the
processor is executing in 64-bit mode (except for the LR and any EAs generated that
clear bits 0–31. Explicit 64-bit instructions are allowed to execute and do not generate
an unimplemented instruction exception unless they would have when the processor
is in 64-bit mode.
Implementation dependent.
Power management control. The semantics of PWRMGMT are implementation
dependent.
DPM
Dynamic power management. Used to enable power-saving by shutting off functional
resources not in use. Setting or clearing DPM should not affect performance.
0 Dynamic power management is disabled.
1 Dynamic power management is enabled.
EDPM
Enhanced dynamic power management. Used to enable additional power-saving by
shutting off functional resources not in use. Setting EDPM may have adverse effects on
performance.
0 Enhanced dynamic power management is disabled.
1 Enhanced dynamic power management is enabled.
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Table 22. HID0 field descriptions (continued)
Bits
Name
45
—
46
ICR
Description
Implementation dependent.
Interrupt inputs clear reservation. Controls whether external input and critical input
interrupts cause an established reservation to be cleared.
0 External and critical input interrupts do not affect reservation status.
1 External and critical input interrupts, when taken, clear an established reservation.
47
Enable hot-wire update of MAS7 register. Implementations that support this bit do not
update MAS7 (upper RPN field) when hardware writes MAS registers via a tlbre, tlbsx,
or an interrupt unless this bit is set. This provides a compatibility path for processors
EN_MAS7_UPD
that originally offered only 32 bits of physical addressing but have since extended past
ATE
32 bits.
0 Hardware updates of MAS7 are disabled.
1 Hardware updates of MAS7 are enabled.
48
EIEC
Enable internal error checking. Used to control whether internal processor errors cause
a machine check exception.
0 Internal error reporting is disabled. Internally detected processor errors do not
generate a machine check interrupt.
1 Internal error reporting is enabled. Internally detected processor errors generate a
machine check interrupt.
49
TBEN
Time base enable. Used to control whether the time base increments.
0 The time base is not enabled and will not increment.
1 The time base is enabled and will increment. The rate at which the time base
increments is determined by the value of HID0[SEL_TBCLK].
50
SEL_TBCLK
51–54
—
55
DAPUEN
56
SGE
57
—
58
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EIEIO_EN
Select time base clock. Used to select the source of the time base clock.
0 The time base is updated based on a core implementation specific rate.
1 The time base is updated based on an external signal to the core
Implementation dependent.
Debug APU enable. Controls whether the debug APU or enhanced debug APU is
enabled.
0 The debug APU is disabled. Debug interrupts use CSRR0 and CSRR1 to save state
and the rfci instruction to return from the debug interrupt.
1 The debug APU is enabled; debug interrupts use DSRR0 and DSRR1 to save state
and the rfdi instruction to return from the debug interrupt.
Store gathering enable. Turns on store gathering for non-guarded cache inhibited or
write-through stores. Details and characteristics of how stores are gathered is
implementation dependent.
0 Store gathering is disabled.
1 Store gathering is enabled.
Implementation dependent.
eieio synchronization enable. Allows mbar instructions to provide the same
synchronization semantics as the eieio instruction.
0 Synchronization provided by mbar is performed in the Book E manner. Additional
forms of synchronization, if implemented, are determined by the MO value.
1 Synchronization provided by mbar is equivalent to eieio synchronization. The MO
field is ignored.
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Register model
Table 22. HID0 field descriptions (continued)
Bits
Name
Description
59
LWSYNC_EN
Lightweight synchronization enable. Allows msync instructions to provide the same
synchronization semantics as the sync instructions from the PowerPC 2.xx
architecture.
0 The synchronization provided by the msync instruction is performed in the Book E
manner.
1 The synchronization provided by the msync instruction is based on the L field defined
in PowerPC 2.xx architecture sync instruction.
60
—
61
62
63
3.7.2
Implementation dependent.
NOPTST
No-op cache touch for store instructions. Controls whether data cache touch for store
instructions perform no operation.
0 dcbtst, dstst, and dststt and other forms of cache touch for store instructions
operate as defined by the EIS and Book E unless disabled by NOPDST or NOPTI.
1 dcbtst, dstst, and dststt and other forms of cache touch for store instructions are
treated as no-ops. Cache line touch for store and lock instructions defined in the
cache line locking APU operate as defined.
NOPDST
No-op dst, dstt, dstst, and dststt instructions. Instructions that start data stream
prefetching through the dst instructions produce no-operation.
0 dst, dstt, dstst, and dststt operate as defined by the EIS unless disabled by
NOPTST or NOPTI.
1 dst, dstt, dstst, and dststt are treated as no-ops and all current dst prefetch streams
are terminated.
NOPTI
No-op cache touch instructions. Data and instruction cache touch instructions perform
no operations.
0 dcbt, dcbtst, icbt and other forms of cache touch instructions operate as defined by
the EIS and Book E unless disabled by NOPDST or NOPTST.
1 dcbt, dcbtst, icbt and other cache touch instruction forms are treated as no-ops.
Cache line touch and lock instructions defined in the cache line locking APU operate
as defined.
Hardware implementation dependent register 1 (HID1)
The EIS defines a HID1 register. HID1 contents are implementation dependent. HID1 is
used for bus configuration and control. Writing to HID1 requires synchronization, as
described in Section 3.18.2: Synchronization requirements for SPRs.
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Figure 12. Hardware implementation dependent register 1 (HID1)
SPR 1009
Access: supervisor-only
32
63
R
Implementation dependent
W
Reset
Implementation dependent
3.7.3
Processor ID register (PIR)
The processor ID register (PIR), shown below, contains a value that can be used to
distinguish the processor from other processors in the system.
Figure 13. Processor ID register (PIR)
SPR 286
Access: Supervisor read-only
32
63
R
Processor ID
W
Reset
3.7.4
Processor specific value
Processor version register (PVR)
The read-only processor version register (PVR), contains a value identifying the version and
revision level of the processor. The PVR distinguishes between processors that differ in
attributes that may affect software.
Figure 14. Processor version register (PVR)
SPR
287
32
Access: supervisor read-only
47 48
Version
R
63
Revision
W
Reset
Processor specific value
Table 23 describes PVR fields.
Table 23. PVR field descriptions
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Bits
Name
Description
32–47
Version
48–63
A 16-bit number that distinguishes between implementations of the version.
Different revision numbers indicate minor differences between processors
Revision
having the same version number, such as clock rate and engineering change
level.
A 16-bit number that identifies the version of the processor. Different version
numbers indicate major differences between processors, such as which optional
facilities and instructions are supported.
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3.7.5
Register model
System version register (SVR)
The system version register (SVR), contains a read-only SoC-dependent value; consult the
documentation for the implementation.
Figure 15. System version register (SVR)
SPR
1023
Access: supervisor read-only
32
R
63
System version
W
Reset
SoC-specific value
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3.8
RM0004
Timer registers
The time base (TB), decrementer (DEC), fixed-interval timer (FIT), and watchdog timer
provide timing functions for the system. The relationship of these timer facilities to each
other is shown in Figure 16 and is described as follows:
Figure 16. Relationship of timer facilities to the time base
Time Base (incrementer)
32
63
32
TBU
63
Timer Clock
(Time Base Clock)
core_tbclk
TBL
Watchdog timer events based on one of the TB bits selected
by the EIS–defined TCR[WPEXT] concatenated with the
Book E–defined TCR[WP] (WPEXT||WP).



Fixed-interval timer events based on one of TB bits selected
by the EIS–defined TCR[FPEXT] concatenated with the
Book E–defined TCR[FP] (FPEXT||FP).



DEC
Auto-reload
Decrementer event = 0/1 detect
32
63
DECAR

The TB is a long-period counter driven at an implementation-dependent frequency.

The decrementer, updated at the same rate as the TB, provides a way to signal an
exception after a specified period unless one of the following occurs:
–
DEC is altered by software in the interim.
–
The TB update frequency changes.

The DEC is typically used as a general-purpose software timer.

The time base for the TB and DEC is selected by the time base enable (TBEN) and
select time base clock (SEL_TBCLK) bits in HID0, as follows:
–
If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8
bus clocks.
–
If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated by an
implementation-specific clock input).

Software can select one from of four TB bits to signal a fixed-interval interrupt
whenever the bit transitions from 0 to 1. It is typically used to trigger periodic system
maintenance functions. Bits that may be selected are implementation-dependent.

The watchdog timer, also a selected TB bit, provides a way to signal a critical exception
when the selected bit transitions from 0 to 1. It is typically used for system error
recovery. If software does not respond in time to the initial interrupt by clearing the
associated status bits in the TSR before the next expiration of the watchdog timer
interval, a watchdog timer-generated processor reset may result, if so enabled.
All timer facilities must be initialized during start-up.
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3.8.1
Register model
Timer control register (TCR)
The TCR, provides control information for the on-chip timer of the core complex. The core
complex implements two fields not specified in Book E: TCR[WPEXT] and TCR[FPEXT].
The 32-bit timer control register (TCR), controls the decrementer (see Section 3.8.4:
Decrementer register).
Figure 17. Timer control register (TCR)
SPR 340
Access: Supervisor read/write
32 33 34 35 36 37 38 39 40 41 42 43
46 47
50 51
63
R
WP WRC WIEDIE FP FIEARE — WPEXT
FPEXT
—
W
Reset
Processor specific value
Table 24 describes the TCR fields.
Table 24. TCR field descriptions
Bits
Name
Description
WP
Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit
locations of the time base used to signal a watchdog timer exception on a
transition from 0 to 1.
WPEXT,WP = 0000_00 selects TBU[32] (the msb of the TB)
WPEXT,WP = 1111_11 selects TBL[63] (the lsb of the TB)
34–35
WRC
Watchdog timer reset control. When a watchdog reset event occurs, the value
programmed into WRC is reflected on core_wrs and into TSR[WRS], but the
WRC bits are reset to 00. At this point, software can reprogram WRC. Although
WRC can be set by software, it cannot be cleared by software (except by a
software-induced reset). Once written to a non-zero value, WRC may no longer
be altered by software.
00 No watchdog timer reset will occur. TCR[WRC] resets to 00; it can be set by
software, but cannot be cleared by software (except by a software-induced
reset).
xx Other values: Force processor to be reset on second time-out of watchdog
timer. The exact function of any of these settings is implementationdependent.
36
WIE
Watchdog timer interrupt enable
0 Watchdog timer interrupts disabled
1 Watchdog timer interrupts enabled
37
DIE
Decrementer interrupt enable
0 Decrementer interrupts disabled
1 Decrementer interrupts enabled
FP
Fixed interval timer period. When concatenated with FPEXT, FP specifies one of
64 bit locations of the time base used to signal a fixed-interval timer exception on
a transition from 0 to 1.
FPEXT||FP = 0000_00 selects TBU[32] (the msb of the TB)
FPEXT||FP = 1111_11 selects TBL[63] (the lsb of the TB)
32–33
38–39
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Table 24. TCR field descriptions (continued)
Bits
Description
FIE
Fixed interval interrupt enable
0 Fixed interval interrupts disabled
1 Fixed interval interrupts enabled
41
ARE
Auto-reload enable. Controls whether the value in DECAR is reloaded into the
DEC when the DEC value reaches 0000_0001.
0 Auto-reload disabled
1 Auto-reload enabled
42
—
Reserved, should be cleared.
43–46
WPEXT
(EIS) Watchdog timer period extension (see the description for WP)
47–50
FPEXT
(EIS) Fixed-interval timer period extension (see the description for FP)
51–63
—
Reserved, should be cleared.
40
3.8.2
Name
Timer status register (TSR)
As shown below, the 32-bit TSR contains status on timer events and the most recent
watchdog timer-initiated processor reset. All TSR bits function as write-1-to-clear.
Note:
Register fields designated as write-1-to-clear are cleared only by writing ones to them.
Writing zeros to them has no effect.
Figure 18. Timer status register (TSR)
SPR 336
336
32
Access: supervisor w1c
33 34 35 36 37 38
R
ENW WIS WRS DIS FIS
W
w1c w1c w1c w1cw1c
63
—
Reset
All zeros
Table 25 describes TSR fields.
Table 25. TSR field descriptions
Bits
32
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Name
Description
ENW
Enable next watchdog time. When a watchdog timer time-out occurs while WIS = 0 and the next
watchdog time-out is enabled (ENW = 1), a watchdog timer exception is generated and logged by
setting WIS. This is referred to as a watchdog timer first time out. A watchdog timer interrupt
occurs if enabled by TCR[WIE] and MSR[CE]. To avoid another watchdog timer interrupt once
MSR[CE] is reenabled (assuming TCR[WIE] is not cleared instead), the interrupt handler must
reset TSR[WIS] by executing an mtspr, setting WIS and any other bits to be cleared and a 0 in all
other bits. The data written to the TSR is not direct data, but a mask. A 1 causes the bit to be
cleared; a 0 has no effect.
0 Action on next watchdog timer time-out is to set TSR[ENW].
1 Action on next watchdog timer time-out is governed by TSR[WIS].
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Register model
Table 25. TSR field descriptions (continued)
Bits
Name
Description
WIS
Watchdog timer interrupt status. See the ENW description for more information about how WIS is
used.
0 A watchdog timer event has not occurred.
1 A watchdog timer event occurred. When MSR[CE] = 1 and TCR[WIE] = 1, a watchdog timer
interrupt is taken.
WRS
Watchdog timer reset status. Defined at reset (value = 00). Set to TCR[WRC] when a reset is
caused by the watchdog timer.
00 No watchdog timer reset has occurred.
xx All other values are implementation-dependent.
DIS
Decrementer interrupt status.
0 A decrementer event has not occurred.
1 A decrementer event occurred. When MSR[EE] = TCR[DIE] = 1, a decrementer interrupt is
taken.
37
FIS
Fixed-interval timer interrupt status.
0 A fixed-interval timer event has not occurred.
1 A fixed-interval timer event occurred. When MSR[EE] = 1 and TCR[FIE ]= 1, a fixed-interval
timer interrupt is taken.
38–63
—
Reserved, should be cleared.
33
34–35
36
3.8.3
Time base (TBU and TBL)
The time base (TB), seen below, is composed of two 32-bit registers, the time base upper
(TBU) concatenated on the right with the time base lower (TBL). TB provides timing
functions for the system. TB is a volatile resource and must be initialized during start-up.
Figure 19. Time base upper/lower registers (TBU/TBL)
SPR
269 Read/285 write
268 read/284 write Access: user read supervisor write
32
63 32
63
R
TBU
TBU
W
Reset
All zeros
The TB is interpreted as a 64-bit unsigned integer that is incremented periodically. Each
increment adds 1 to the least-significant bit. The frequency at which the integer is updated is
implementation-dependent.
TBL increments until its value becomes 0xFFFF_FFFF (232 – 1). At the next increment, its
value becomes 0x0000_0000 and TBU is incremented. This process continues until the
TBU value becomes 0xFFFF_FFFF and value TBL value becomes 0xFFFF_FFFF (TB is
interpreted as 0xFFFF_FFFF_FFFF_FFFF (264 – 1)). At the next increment, the TBU value
becomes 0x0000_0000 and the TBL value becomes 0x0000_0000. There is no interrupt (or
any other indication) when this occurs.
The period depends on the driving frequency. For example, if TB is driven by 100 MHz
divided by 32, the TB period is as follows: 
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T TB = 2
64
12
32
 -------------------- = 5.90  10 seconds
10MHz
(approximately 187,000 years)
The TB is implemented such that the following requirements are satisfied:

Loading a GPR from the TB has no effect on the accuracy of the TB

Storing a GPR to the TB replaces the value in the TB with the value in the GPR
Book E does not specify a relationship between the frequency at which the TB is updated
and other frequencies, such as the CPU clock or bus clock in a Book E system. The TB
update frequency is not required to be constant. One of the following is required to ensure
that system software can keep time of day and operate interval timers:
Note:

The system provides an (implementation-dependent) interrupt to software whenever
the update frequency of the TB changes and a way to determine the current update
frequency.

The update frequency of the TB is under the control of system software.
Disabling the TB or making reading the time base privileged prevents the TB from being
used to implement a covert channel in a secure system.
If the operating system initializes the TB on power-on to some reasonable value and the
update frequency of the TB is constant, the TB can be used as a source of values that
increase at a constant rate, such as for time stamps in trace entries.
Even if the update frequency is not constant, values read from the TB are monotonically
increasing (except when the TB wraps from 264 – 1 to 0). If a trace entry is recorded each
time the update frequency changes, the sequence of TB values can be post-processed to
become actual time values.
Successive readings of the TB may return identical values.
It is intended that the TB be useful for timing reasonably short sequences of code (a few
hundred instructions) and for low-overhead time stamps for tracing.
3.8.4
Decrementer register
The 32-bit decrementer (DEC), shown below, is a decrementing counter that is updated at
the same rate as the TB. It provides a way to signal a decrementer interrupt after a specified
period unless one of the following occurs:

DEC is altered by software in the interim.

The TB update frequency changes.
DEC is typically used as a general-purpose software timer. The decrementer auto-reload
register is used to automatically reload a programmed value into DEC, as described in
Section 3.8.5: Decrementer auto-reload register (DECAR).
Figure 20. Decrementer register (DEC)
SPR 2222
Access: Supervisor read/write
32
63
R
Decrementer value
W
Reset
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3.8.5
Register model
Decrementer auto-reload register (DECAR)
The decrementer auto-reload register is shown in figure below. If the auto-reload function is
enabled (TCR[ARE] = 1), the auto-reload value in DECAR is written to DEC when DEC
decrements from 0x0000_0001 to 0x0000_0000. Note that writing DEC with zeros by using
an mtspr[DEC] does not automatically generate a decrementer exception.
Figure 21. Decrementer auto-reload register (DECAR)
SPR 5454
Access: supervisor write-only
32
63
R
W
Decrementer auto-reload value
Reset
All zeros
3.9
Interrupt registers
Section 3.9.1: Interrupt registers defined by book E, describes registers used for interrupt
handling.
3.9.1
Interrupt registers defined by book E
This section describes the following register bits and their fields:
3.9.1.1

Section 3.9.1.1: Save/restore register 0 (SRR0)

Section 3.9.1.2: Save/restore register 1 (SRR1)

Section 3.9.1.3: Critical save/restore register 0 (CSRR0)

Section 3.9.1.4: Critical save/restore register 1 (CSRR1)

Section 3.9.1.5: Data exception address register (DEAR)

Section 3.9.1.6: Interrupt vector prefix register (IVPR)

Section 3.9.1.7: Interrupt vector offset registers (IVORs)

Section 3.9.1.8: Exception syndrome register (ESR)
Save/restore register 0 (SRR0)
On a noncritical interrupt, SRR0, shown in figure below, holds the address of the instruction
where the interrupted process should resume. The instruction is interrupt-specific, although
for instruction-caused exceptions, it is typically the address of the instruction that caused the
interrupt. When rfi executes, instruction execution continues at the address in SRR0.
Figure 22. Save/restore register 0 (SRR0)
SPR 2626
Access: sup[ervisor read/write
32
63
R
Next instruction address
W
Reset
All zeros
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3.9.1.2
RM0004
Save/restore register 1 (SRR1)
SRR1 is provided to save and restore machine state on noncritical interrupts. When a
noncritical interrupt is taken, MSR contents are placed in SRR1. When rfi executes, SRR1
contents are placed into MSR. SRR1 bits that correspond to reserved MSR bits are also
reserved. These registers are not affected by rfci or rfmci. Reserved MSR bits may be
altered by rfi, rfci, or rfmci.
Figure 23. Save/restore register 1 (SRR1)
SPR 2727
Access: supervisor read/write
32
63
R
MSR state information
W
Reset
3.9.1.3
All zeros
Critical save/restore register 0 (CSRR0)
CSRR0, is provided to save and restore machine state on critical interrupts. It is used by
critical interrupts like SRR0 is used for standard interrupts: to hold the address of the
instruction to which control is passed at the end of the interrupt handler. When rfci
executes, instruction execution continues at the address in CSRR0.
Figure 24. Critical save/restore register 0 (CSRR0)
SPR 5827
Access: supervisor read/write
32
63
R
Next instruction address
W
Reset
3.9.1.4
All zeros
Critical save/restore register 1 (CSRR1)
CSRR1, is used to save and restore machine state on critical interrupts. When a critical
interrupt is taken, MSR contents are placed into CSRR1. When rfci executes, CSRR1
contents are restored into the MSR. CSRR1 bits that correspond to reserved MSR bits are
also reserved; reserved MSR bits may be altered.
Figure 25. Critical save/restore register 1 (CSRR1)
SPR 5927
Access: supervisor read/write
32
63
R
MSR state information
W
Reset
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3.9.1.5
Register model
Data exception address register (DEAR)
DEAR, is loaded with the effective address of a data access (caused by a load, store, or
cache management instruction) that results in an alignment, data TLB miss, or DSI
exception.
Figure 26. Data exception address register (DEAR)
SPR 6127
Access: supervisor read/write
32
63
R
Exception address
W
Reset
3.9.1.6
All zeros
Interrupt vector prefix register (IVPR)
IVPR is used with IVORs to determine the vector address. IVPR[32–47] provides the highorder 16 bits of the address of the exception processing routines. The 16-bit vector offsets
are concatenated to the right of IVPR[32–47] to form the address of the exception
processing routine. IVPR[48–63] are reserved.
Figure 27. Interrupt vector prefix register (IVPR)
SPR 6327
32
Access: supervisor read/write
47 48
63
R
Interrupt vector prefix
—
W
Reset
All zeros
3.9.1.7
Interrupt vector offset registers (IVORs)
IVORs, hold the quad-word index from the base address provided by the IVPR for each
interrupt type.
Figure 28. Interrupt vector offset registers (IVOR)
SPR (see Table 26)
32
Access: Supervisor read/write
47 48
59 60
63
R
—
Interrupt vector prefix
—
W
Reset
All zeros
SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR32–IVOR47 and
IVOR60–IVOR63 are reserved. SPR numbers for IVOR32–IVOR63 are allocated for
implementation-dependent use. IVOR assignments are shown in Table 26.
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Table 26. IVOR assignments
IVOR Number
SPR
Interrupt type
IVOR0
400 Critical input
IVOR1
401 Machine check
IVOR2
402 Data storage
IVOR3
403 Instruction storage
IVOR4
404 External input
IVOR5
405 Alignment
IVOR6
406 Program
IVOR7
407 Floating-point unavailable
IVOR8
408 System call
IVOR9
409 Auxiliary processor unavailable (optional)
IVOR10
410 Decrementer
IVOR11
411 Fixed-interval timer interrupt
IVOR12
412 Watchdog timer interrupt
IVOR13
413 Data TLB error
IVOR14
414 Instruction TLB error
IVOR15
415 Debug
IVOR16–
IVOR31
—
Reserved for future architectural use
IVOR36–IVOR63 allocated for implementation dependent use
3.9.1.8
IVOR32
528 SPE APU unavailable
IVOR33
529 (Embedded FP APUs) embedded floating-point data exception
IVOR34
530 (Embedded FP APUs) embedded floating-point round exception
IVOR35
531 (Performance monitor APUs) performance monitor
Exception syndrome register (ESR)
The ESR, provides a syndrome to differentiate between different kinds of exceptions that
can generate the same interrupt type. When such an interrupt is generated, bits
corresponding to the specific exception that generated the interrupt are set and all other
ESR bits are cleared. Other interrupt types do not affect ESR contents. The ESR does not
need to be cleared by software. Table 27 shows ESR bit definitions.
EIS storage defines ESR[DLK] and ESR[ILK] to indicate user cache line locking exceptions,
ESR[XTE] for precise external transaction errors, and ESR[EPID] external PID load and
store exceptions.
The ESR is defined in Book E. Bits architected by EIS storage are defined here.
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Figure 29. Exception syndrome register (ESR)
SPR62
32
35 36 37
Access: Supervisor read/write
38 39 40 41 42
43
44 45
46 47
55 56
57
58
59 61 62 63
R
Book E
—
PIL PPR PTR FP ST — DLK0 DLK1 AP PUO BO
—
W
R
EIS
—
DLK ILK
—
SPE — VLEMI
—
MIF XTE
W
Reset
All zeros
Table 27 describes ESR bit definitions.
Table 27. Exception syndrome register (ESR) definition
Bits
Name
32–35
—
Reserved, should be cleared. (Defined by Book E as allocated.)
—
36
PIL
Illegal instruction exception
Program
37
PPR
Privileged instruction exception
Program
38
PTR
Trap exception
Program
39
FP
Floating-point operations
Alignment, data
storage, data TLB,
program
40
ST
Store operation
Alignment, data 
storage, data TLB
error
41
—
Reserved, should be cleared.
—
DLK
Defined by cache line locking APU. Instruction cache locking attempt.
Set when a DSI occurs because a dcbtls, dcbtstls, or dcblc was
executed in user mode (MSR[PR] = 1) while MSR[UCLE] = 0.
0 Default
1 DSI occurred on an attempt to lock line in data cache when
MSR[UCLE] = 0.
Data storage
43
ILK
Defined by cache line locking APU. Instruction cache locking attempt.
Set when a DSI occurs because an icbtls or icblc was executed in
user mode (MSR[PR] = 1) while MSR[UCLE] = 0.
0 Default
1 DSI occurred on an attempt to lock line in instruction cache when
MSR[UCLE] = 0.
Data storage
44
APU
Auxiliary processor operation. Defined by Book E.
Alignment, data
storage, data TLB,
program
45
PUO
Unimplemented operation exception. Defined by Book E.
Program
46
BO
Byte-ordering exception. Defined by Book E and the VLE extension.
Data storage,
instruction storage
47
PIE
Imprecise exception. Defined by Book E.
Program
48–55
—
Reserved.
—
42
Syndrome
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Table 27. Exception syndrome register (ESR) definition (continued)
Bits
Name
56
SPE
57
—
58
59–61
62
63
Syndrome
Data storage,
Data TLB error,
Defined by SPE, embedded floating-point APU. SPE/embedded
Alignment,
floating-point exception bit
SPE unavailable,
0 Default
1 Any exception caused by an SPE/embedded floating-point instruction Embedded FP
unavailable,
occurred.
Embedded FP data,
Embedded FP round
Reserved, should be cleared
Defined by VLE extension. VLEMI indicates that an interrupt was
caused by a VLE instruction. VLEMI is set on an exception associated
with execution or attempted execution of a VLE instruction.
0 The instruction page associated with the instruction causing the
VLEMI
exception does not have the VLE attribute set or the VLE extension
is not implemented.
1 The instruction page associated with the instruction causing the
exception has the VLE attribute set and the VLE extension is
implemented.
—
Interrupt types
Data storage,
Data TLB error,
Instruction storage,
Program,
System Call,
Alignment,
SPE unavailable,
Embedded FP
unavailable,
Embedded FP data,
Embedded FP round
Reserved. Defined by Book E as allocated.
—
MIF
Defined by the VLE extension. MIF indicates that an interrupt was
caused by a misaligned instruction fetch (NIA62 != 0) and the VLE
attribute is cleared for the page or the second half of a 32-bit VLE
instruction caused an instruction TLB error.
0 Default.
1 NIA62 != 0 and the instruction page associated with NIA does not
have the VLE attribute set or the second half of a 32-bit VLE
instruction caused an instruction TLB error.
Instruction TLB error,
Instruction Storage
XTE
External transaction error. An external transaction reported an error but
the error was handled precisely by the core. The contents of SRR0
Instruction storage,
contain the address of the instruction that initiated the transaction.
Data storage
0 Default. No external transaction error was precisely detected.
1 An external transaction reported an error that was precisely detected.
Note:
ESR information is incomplete, so system software may need to identify the type of
instruction that caused the interrupt and examine the TLB entry and the ESR to fully identify
the exception or exceptions. For example, a data storage interrupt may be caused by both a
protection violation exception and a byte-ordering exception. System software would have
to look beyond ESR[BO], such as the state of MSR[PR] in SRR1 and the TLB entry page
protection bits to determine if a protection violation also occurred.
3.9.1.9
EIS-defined interrupt registers
This section describes machine check save/store and syndrome registers.
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3.9.1.10
Register model
Debug save/restore register 0 (DSRR0)
On a debug interrupt, DSRR0, holds the address of the instruction where the interrupted
process should resume. The instruction is interrupt specific. See Section 5.7.16: Debug
interrupt. When rfdi executes, instruction execution continues at the address in DSRR0.
DSRR0 and DSRR1 are not affected by rfi, rfci, or other return from interrupt instructions
Figure 30. Debug save/restore register 0 (DSRR0)
SPR 574574
Access: Supervisor read/write
32
63
R
Next instruction address
W
Reset
Undefined
3.9.1.11
Debug Save/restore register 1 (DSRR1)
DSRR1, is provided to save and restore machine state on debug interrupts. When a debug
interrupt is taken, MSR contents are placed into DSRR1. When rfdi executes, the contents
of DSRR1 are restored into MSR. DSRR1 bits that correspond to reserved MSR bits are
also reserved. (See Section 3.6.1: Machine state register (MSR), for more information.)
DSRR0 and DSRR1 are not affected by rfi or rfci. Reserved MSR bits may be altered by rfi,
rfci, or rfdi.
Figure 31. Debug save/restore register 1 (DSRR1)
SPR 575574
Access: Supervisor read/write
32
63
R
MSR state information
W
Reset
Implementation-specific
3.9.1.12
Machine check save/restore register 0 (MCSRR0)
When a machine check interrupt is taken, MCSRR0, is set to the address of the instruction
where the interrupted process should resume. The instruction is interrupt-specific, although
typically MCSRR0 holds address of the instruction that caused the interrupt. When rfmci is
executed, instruction execution continues at this address.
Figure 32. Machine check save/restore register 0 (MCSRR0)
SPR 570574
Access: Supervisor read/write
32
63
R
Next instruction address
W
Reset
All zeros
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3.9.1.13
RM0004
Machine check save/restore register 1 (MCSRR1)
MCSRR1 is used to save and restore machine state on machine check interrupts. When a
machine check interrupt is taken, MSR contents are placed into MCSRR1. When rfmci
executes, MCSRR1 contents are restored to MSR. MCSRR1 bits that correspond to
reserved MSR bits are also reserved; reserved MSR bits may be altered.
Figure 33. Machine check save/restore register 1 (MCSRR1)
SPR 571574
Access: Supervisor read/write
32
63
R
MSR state information
W
Reset
3.9.1.14
All zeros
Machine check address register (MCAR/MCARU)
When the core complex takes a machine check interrupt, it updates MCAR, to indicate the
address of the data associated with the machine check. Note that if a machine check
interrupt is caused by a signal, MCAR contents are not meaningful. Errors that cause MCAR
contents to be updated are implementation-dependent. If MCSR[MAV] = 1, the address is
an effective address; if MAV = 0, the address is a real address.
Figure 34. Machine check address register (MCAR/MCARU)
SPR MCAR: 573
MCARU: 569
Access: Supervisor read-only
MCARU
32
R
6332
Machine check address 0–31
63
Machine check address 32–63
W
Reset
All zeros
For 32-bit implementations that support physical addresses greater than 32 bits, MCARU
provides an alias to the upper address bits that reside in MCAR[0–31].
3.9.1.15
Machine check syndrome register (MCSR)
The MCSR, is used to record the cause of the machine check interrupt. In general, machine
check syndrome bits correlating to specific hardware error conditions are implementation
dependent. Consult the users manual for a complete definition of machine check error
syndromes for a specific processor.
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Figure 35. Machine check syndrome register 1 (MCSR)
SPR 572574
32
43 44
Access: Read/w1c
45
46
47
63
R
MCP
—
NMI MAV MEA
—
W
Reset
All zeros
Table 28 describes the MCSR fields.
Table 28. MCSR field descriptions
Bits
32
Description
Machine check input to core. Processor cores with a machine check input pin (signal)
respond to a signal input by producing an asynchronous machine check. The
MCP
existence of such a signal and how such a signal is generated is implementation
dependent and may be tied to a an external pin on the IC package.
33–
42
—
43
NMI
44
MCAR address valid. The address contained in MCAR was updated by the processor
and corresponds to the first detected error condition that contained an associated
address. Any subsequent machine check errors that have associated addresses are
not placed in MCAR unless MAV is 0 when the error is logged.
MAV
0 The address in MCAR is not valid.
1 The address in MCAR is valid.
Note: Software should read MCAR before clearing MAV. MAV should be cleared
before setting MSR[ME].
45
MCAR effective address. Denotes the type of address in MCAR. MEA has meaning
only if MCSR[MAV] is set.
MEA
0 The address in MCAR is a physical address.
1 The address in MCAR is an effective address (untranslated).
46–
63
Note:
Name
—
Implementation-dependent.
Nonmaskable Interrupt. Set if a non-maskable interrupt (NMI) has been sent to the
virtual processor.
Implementation-dependent.
The machine check interrupt handler should always write what is read back to the MCSR
after the error information has been logged. Writing contents that were read from the MCSR
back to the MCSR clears only those status bits that were previously read. Failure to clear all
MCSR bits causes an asynchronous machine check interrupt when MSR[ME] is set.
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3.10
RM0004
Software use sprs (SPRG0–SPRG7 and USPRG0)
Software-use SPRs (SPRG0–SPRG7 and USPRG0), have no defined functionality. These
are shown below:

SPRG0–SPRG2—can be accessed only in supervisor mode.

SPRG3—can be written only in supervisor mode. It is readable in supervisor mode, but
whether it can be read in user mode is implementation-dependent.

SPRG4–SPRG7—can be written only in supervisor mode; readable in supervisor or
user mode.

USPRG0—can be accessed in supervisor or user mode.
Figure 36. Software-use sprs (SPRG0–SPRG7 and USPRG0)
SPRG0
SPRG1
SPRG2
SPRG3
SPRG4
SPR
SPRG5
SPRG6
SPRG7
USPRG0
272
273
274
259
275
260
276
261
277
262
278
263
279
256
Read/write
Read/write
Read/write
Read-only
Read/write
Read-only
Read/write
Read-only
Read/write
Read-only
Read/write
Read-only
Read/write
Read/write
Supervisor
Supervisor
Supervisor
User (Implementation-dependent)/supervisor
Supervisor
User/supervisor
Supervisor
User/supervisor
Supervisor
User/supervisor
Supervisor
User/supervisor
Supervisor
User/supervisor
32
63
R
MSR state information
W
Reset
All zeros
Software-use SPRs are read into a GPR by using mfspr and are written by using mtspr.
3.11
L1 cache registers
The EIS defines registers that provide control and configuration and status information for
the L1 cache implementation.
3.11.1
L1 cache control and status register 0 (L1CSR0)
The L1CSR0, is defined by the EIS. It is used for general control and status of the L1 data
cache.
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Figure 37. L1 cache control and status register 0 (L1CSR0)
SPR 1010Supervisor read/write
Cache way partitioning APU Bits
32
35
36
39
40
41
42
43
46
47
R
WID
WDD
AWID AWDD WAM
—
CPE
W
Reset
All zeros
Cache Line Locking APU Bits
48
49
51
52
53
54
55
56
57
60
61
62
63
CABT CFI
CE
R
CPI
—
CSLC CUL CLO CLFR CLOA
—
W
Reset
All zeros
Table 29 describes the L1CSR0 fields.
Table 29. L1CSR0 field descriptions
Bits
Name
Description
WID
Cache way partitioning APU. Way instruction disable. (bit 32 = way 0, bit 33 = way 1, … bit
35 = way 3).
0 The corresponding way is available for replacement by instruction miss line refills.
1 The corresponding way is not available for replacement by instruction miss line refills.
36–39
WDD
Cache way partitioning APU. Way data disable (bit 36 = way 0, bit 37 = way 1, … bit 39 = way
3).
0 The corresponding way is available for replacement by data miss line refills.
1 The corresponding way is not available for replacement by data miss line refills
40
AWID
Cache way partitioning APU. Additional ways instruction disable.
0 Additional ways beyond 0–3 are available for replacement by instruction miss line fills.
1 Additional ways beyond 0–3 are not available for replacement by instruction miss line fills.
41
AWDD
Cache way partitioning APU. Additional ways data disable.
0 Additional ways beyond 0–3 are available for replacement by data miss line fills.
1 Additional ways beyond 0–3 are not available for replacement by data miss line fills.
42
WAM
43-46
—
47
CPE
DCPE
32–35
Cache way partitioning APU. Way access mode.
0 All ways are available for access.
1 Only ways partitioned for the specific type of access are used for a fetch or read operation.
Reserved for implementation dependent use.
[Data] Cache parity enable.
0 Parity checking of the cache disabled
1 Parity checking of the cache enabled
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Table 29. L1CSR0 field descriptions (continued)
Bits
Name
Description
48
CPI
DCPI
[Data] Cache parity error injection enable.
0 Parity error injection disabled
1 Parity error injection enabled. Note that cache parity must also be enabled
(L1CSR0[CPE] = 1) when this bit is set. If DCPE is not set, results are undefined and erratic
behavior may occur. It is recommended that an attempt to set this bit when L1CSR0[CPE] =
0 cause the bit not to be set (that is, L1CSR0[CPI] = L1CSR0[CPE] & L1CSR0[CPI]).
49–51
—
52
Reserved, should be cleared.
[Data]Cache snoop lock clear. Sticky bit set by hardware if a cache line lock was cleared by a
snoop operation which caused an invalidation. Note that the lock for that line is cleared
CSLC
whenever the line is invalidated. This bit can be cleared only by software.
DCSLC
0 The cache has not encountered a snoop that invalidated a locked line.
1 The cache has encountered a snoop that invalidated a locked line.
53
CUL
DCUL
[Data]Cache unable to lock. Sticky bit set by hardware. This bit can be cleared only by software.
0 Indicates a lock set instruction was effective in the cache
1 Indicates a lock set instruction was not effective in the cache
54
CLO
DCLO
[Data]Cache lock overflow. Sticky bit set by hardware. This bit can be cleared only by software.
0 Indicates a lock overflow condition was not encountered in the cache
1 Indicates a lock overflow condition was encountered in the cache
55
CLFC
DCLFC
[Data]Cache lock bits flash clear. Clearing occurs regardless of the enable (L1CSR0[CE]) value.
0 Default.
1 Hardware initiates a cache lock bits flash clear operation. Cleared when the operation is
complete.
During a flash clear operation, writing a 1 causes undefined results; writing a 0 has no effect
56
[Data]Cache lock overflow allocate. Set by software to allow a lock request to replace a locked
line when a lock overflow situation exists. Implementation of this bit is optional.
CLOA
0 Indicates a lock overflow condition does not replace an existing locked line with the requested
DCLOA
line
1 Indicates a lock overflow condition replaces an existing locked line with the requested line
57–60
61
—
Reserved, should be cleared.
[Data]Cache operation aborted.
CABT
0 No cache operation completed improperly
DCABT
1 Cache operation did not complete properly
62
CFI
DCFI
[Data]Cache flash invalidate. Invalidation occurs regardless of the enable (L1CSR0[CE]) value.
0 No cache invalidate.
1 Cache flash invalidate operation. A cache invalidation operation is initiated by hardware. Once
complete, this bit is cleared.
During an invalidation operation, writing a 1 causes undefined results; writing a 0 has no effect.
63
CE
DCE
[Data]Cache enable.
0 The cache is not enabled. (not accessed or updated)
1 Enables cache operation.
3.11.2
L1 cache control and status register 1 (L1CSR1)
L1CSR1, defined as part of the EIS, is used for general control and status of the L1
instruction cache.
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Figure 38. L1 cache control and status register 1 (L1CSR1)
SPR 10111011
Access: supervisor read/write
Cache line locking APU fields
32
46 47
48 49 51
52
53
54
55
56
57
60
61
62 63
R
—
ICPE ICPI
—
ICSLC ICUL ICLO ICLFR ICLOA
—
ICABT ICFI ICE
W
Reset
All zeros
Table 30 describes the L1CSR1 fields.
Table 30. L1CSR1 field descriptions
Bits
Name
Description
32–42
—
Reserved, should be cleared.
43-46
—
Reserved for implementation dependent use.
47
ICPE
Instruction cache parity enable. See Section 5.7.2: Machine check interrupt.
0 Parity checking of the cache disabled
1 Parity checking of the cache enabled
48
ICPI
Instruction cache parity error injection enable.
0 Parity error injection disabled
1 Parity error injection enabled. Note that cache parity must also be enabled (L1CSR1[ICPE] = 1)
when ICPI is set. If L1CSR0[ICPE] is not set the results are undefined and erratic behavior may
occur. It is recommended that an attempt to set this bit when L1CSR0[ICPE] = 0 causes the bit
not to be set (that is, L1CSR0[ICPI] = L1CSR0[ICPE] & L1CSR0[ICPI]).
49–51
—
Reserved, should be cleared.
52
Cache line locking APU. Instruction cache snoop lock clear. Sticky bit set by hardware if a cache
line lock was cleared by a snoop operation that caused an invalidation. Note that the lock for that
ICSLC line is cleared whenever the line is invalidated. This bit can be cleared only by software.
0 The cache has not encountered a snoop that invalidated a locked line.
1 The cache has encountered a snoop that invalidated a locked line.
53
ICUL
Cache line locking APU. Instruction cache unable to lock. Sticky bit set by hardware. This bit can
be cleared only by software.
0 Indicates a lock set instruction was effective in the cache
1 Indicates a lock set instruction was not effective in the cache
54
Cache line locking APU. Instruction cache lock overflow. Sticky bit set by hardware. This bit can
ICLO be cleared only by software.
DCLO 0 Indicates a lock overflow condition was not encountered in the cache
1 Indicates a lock overflow condition was encountered in the cache
55
Cache line locking APU. Instruction cache lock bits flash clear. Clearing occurs regardless of the
enable (L1CSR1[ICE]) value.
0 Default.
ICLFC
1 Hardware initiates a cache lock bits flash clear operation. This bit is cleared when the operation
is complete.
During a flash clear operation, writing a 1 causes undefined results; writing a 0 has no effect.
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Table 30. L1CSR1 field descriptions (continued)
Bits
Name
Description
Cache line locking APU. Instruction cache lock overflow no allocate. Set by software to prevent a
lock request from replacing a locked line when a lock overflow situation exists. Implementation of
this bit is optional.
ICLOA
0 Indicates a lock overflow condition replaces an existing locked line with the requested line
1 Indicates a lock overflow condition does not replace an existing locked line with the requested
line
56
57–60
—
Reserved, should be cleared.
Instruction cache operation aborted.
ICABT 0 No cache operation completed improperly
1 Cache operation did not complete properly
61
62
ICFI
Instruction cache flash invalidate. Invalidation occurs regardless of the enable (L1CSR1[ICE])
value.
0 No cache invalidate.
1 Cache flash invalidate operation. A cache invalidation operation is initiated by hardware. Once
complete, this bit is cleared.
During an invalidation operation, writing a 1 causes undefined results; writing a 0 has no effect.
63
ICE
Instruction cache enable.
0 The cache is not enabled. (not accessed or updated)
1 Enables cache operation.
3.11.3
L1 cache configuration register 0 (L1CFG0)
The L1CFG0 register, shown below, is defined by the EIS to provide configuration
information for the primary (L1) data cache of the processor. If a processor implements a
unified cache, L1CFG0 applies to the unified cache and L1CFG1 is not implemented.
Figure 39. L1 cache configuration register 0 (L1CFG0)
SPR 515515
32 33
R
34
35
36
CARCH CWPA CFAHA CFISWA
Access: user read-only
37 38 39 40 41 42 43
—
44 45
CBSIZE CREPL CLA CPA
52
CNWAY
W
Reset
Implementation-dependent value
Table 31. L1CFG0 field descriptions
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Name
32–33
CARCH
34
CWPA
Description
Cache architecture
00 Harvard
01 Unified
Cache way partitioning APU available.
0 Unavailable
1 Available
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CSIZE
RM0004
Register model
Table 31. L1CFG0 field descriptions (continued)
Bits
Name
35
CFAHA
36
Direct cache flush APU available. (Cache flush by set and way available.)
CFISWA 0 Unavailable
1 Available
37–38
Cache flush all by hardware available
0 Unavailable
1 Available
Reserved, should be cleared.
CBSIZE
Cache line size
00 32 bytes
01 64 bytes
10 128 bytes
11 Reserved
41–42
CREPL
Cache replacement policy
00 True LRU
01 Pseudo LRU
1x Reserved
43
CLA
Cache line locking APU available
0 Unavailable
1 Available
44
CPA
Cache parity available
0 Unavailable
1 Available
45–52
CNWAY
53–63
CSIZE
39–40
3.11.4
—
Description
Cache number of ways minus 1.
Cache size in Kbytes.
L1 cache configuration register 1 (L1CFG1)
The L1CFG1 register, provides configuration information for the L1 instruction cache. If a
processor implements a unified cache, L1CFG0 applies to the unified cache and L1CFG1 is
not implemented.
Figure 40. L1 cache configuration register 1 (L1CFG1)
SPR 516516
32
R
38 39 40 41 42
—
Access: user read-only
43
44 45
ICBSIZE ICREPL ICLA ICPA
52 53
ICNWAY
63
ICSIZE
W
Reset
Implementation-dependent value
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Table 32. L1CFG1 field descriptions
Bits
Name
32–38
—
Reserved, should be cleared.
ICBSIZ
Instruction cache block size
00 32 bytes
01 64 bytes
10 128 bytes
11 Reserved
41–42
ICREPL
Cache replacement policy
00 True LRU
01 Pseudo LRU
1x Reserved
43
ICLA
Cache line locking APU available
0 Unavailable
1 Available
44
ICPA
Cache parity available
0 Unavailable
1 Available
45–52
ICNWAY
53–63
ICSIZE
39–40
3.11.5
Description
Cache number of ways minus 1.
Cache size in Kbytes.
L1 flush and invalidate control register 0 (L1FINV0)
The direct cache flush APU defines the L1 flush and invalidate control register 0 (L1FINV0),
shown in figure below. The direct cache flush APU allows the programmer to flush and/or
invalidate the cache by specifying the cache set and cache way. The direct cache flush APU
available bit, L1CFG0[CFISWA], is set for implementations that contain the direct cache
flush APU.
To address a specific physical block of the cache, the L1FINV0 is written with the cache set
(L1FINV0[CSET]) and cache way (L1FINV0[CWAY]) of the line that is to be flushed. No tag
match in the cache is required.
Only the L1 data cache (or unified cache) is manipulated by the direct cache flush APU. The
L1 instruction cache or any other caches in the cache hierarchy are not explicitly targeted by
this APU. See Section 9.2: Direct cache flush APU.
Figure 41. L1 flush and invalidate control register 0 (L1FINV0)
SPR 1016
32
Access: supervisor read/write
39 40 41 42
58 59
61 62 63
R
CWAY
—
CSET
W
Reset
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All zeros
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CCMD
RM0004
Register model
Table 33. L1FINV0 fields—L1 direct cache flush
Bits
Name
0–31
—
32–39
40–41
42–58
59–61
62–63
3.12
Descriptions
Reserved, should be cleared.
CWAY Cache way. Specifies the cache way to be selected.
—
Reserved, should be cleared.
CSET Cache set. Specifies the cache set to be selected.
—
Reserved, should be cleared.
Cache flush command.
00 Implementation dependent. If implemented, the action performed on the line
should be synonymous with a dcbi instruction that references the same line.
01 The line specified by CWAY and CSET is flushed if it is modified and valid. It is
implementation dependent whether it remains in the cache, or is invalidated. For
CCMD
an implementation, the action performed on the line should be synonymous with
a dcbst instruction that references the same line.
01 The line specified by CWAY and CSET is flushed if it is modified and valid. It is
then invalidated. For an implementation, the action performed on the line should
be synonymous with a dcbf instruction that references that line.
11 Reserved for future use.
MMU registers
This section describes the following MMU registers and their fields:
3.12.1

Process ID registers (PID0–PID2)

MMU control and status register 0 (MMUCSR0)

MMU configuration register (MMUCFG)

TLB configuration registers (TLBnCFG)

MMU assist registers (MAS0–MAS7)
Process ID registers (PID0–PIDn)
The Book E architecture specifies that a process ID (PID) value be associated with each
effective address (instruction or data) generated by the processor.
System software uses PIDs to identify TLB entries that the processor uses to translate
addresses for loads, stores, and instruction fetches. PID contents are compared to the TID
field in TLB entries as part of selecting appropriate TLB entries for address translation. PID
values are used to construct virtual addresses for accessing memory. Note that individual
processors may not implement all 14 bits of the process ID field.
Book E defines one PID register that holds the PID value for the current process. ST
devices may implement from 1 to 15 PID registers. The number of PIDs implemented is
indicated by the value of MMUCFG[NPIDS]. Consult the user documentation for the
implementation to determine if other PID registers are implemented.
The suggested PID usage is for PID0 to denote private mappings for a process and for other
PIDs to handle mappings that may be common to multiple processes. This method allows
for processes sharing address space to also share TLB entries if the shared space is
mapped at the same virtual address in each process.
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Figure 42. Process ID registers (PID0–PID2)
SPR 48 (PID0: PID in Book E);
SPR 633 PID1
SPR 634 PID2 (PID3–PID14 are currently not assigned to SPR
numbers)
32
Access: Supervisor-only
49 50
63
R
—
Process ID
W
Reset
3.12.2
All zeros
MMU control and status register 0 (MMUCSR0)
The MMUCSR0 register is used for general control of the L1 and L2 MMUs.
Figure 43. MMU control and status register 0 (MMUCSR0)
SPR 1012
Access: supervisor read/write
32
60
61
62
63
R
—
TLB0_FI TLB1_FI —
W
Reset
All zeros
Table 34. MMUCSR0 field descriptions
Bits
Name
32–60
—
Description
Reserved, should be cleared.
61
TLB0 flash invalidate (write 1 to invalidate)
0 No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored.
L2TLB0_FI 1 TLB0 invalidation operation. Hardware initiates a TLB0 invalidation operation. When this
operation is complete, this bit is cleared. Writing a 1 during an invalidation operation causes
TLB0_FI
an undefined operation. If the TLB array supports IPROT, entries that have IPROT set are
not invalidated.
62
TLB1 flash invalidate (write 1 to invalidate)
L2TLB1_FI 0 No flash invalidate. Writing a 0 to this bit during an invalidation operation is ignored.
1 TLB1 invalidation operation. Hardware initiates a TLB1 invalidation operation. When this
TLB1_FI
operation is complete, this bit is cleared. Writing a 1 during an invalidation operation causes
an undefined operation. This invalidation typically takes 1 cycle.
63
100/1025
—
Reserved, should be cleared.
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3.12.3
Register model
MMU configuration register (MMUCFG)
MMUCFG, shown below, gives configuration information about the implementation’s MMU.
Figure 44. MMU configuration register 1 (MMUCFG)
SPR 1015
Access: supervisor read-only
32
48 49
R
—
52 53
NPIDS
57 58 59 60 61 62 63
PIDSIZE
— NTLBS MAVN
W
Reset
Implementation specific
Table 35. MMUCFG field descriptions
Bits
Name
32–48
—
49–52
NPIDS
Description
Reserved, should be cleared.
Number of PID registers, a 4-bit field that indicates the number of PID registers
provided by the processor.
PID register size. The PIDSIZE value is one fewer than the number of bits in each
53–57 PIDSIZE PID register implemented. The processor implements only the least significant
PIDSIZE+1 bits in the PID registers.
58–59
60–61
62–63
—
Reserved, should be cleared.
NTLBS
Number of TLBs. The value of NTLBS is one less than the number of softwareaccessible TLB structures that are implemented by the processor. NTLBS is set to
one less than the number of TLB structures so that its value matches the
maximum value of MAS0[TLBSEL].)
00 1 TLB
01 2 TLBs
10 3 TLBs
11 4 TLBs
MAVN
MMU architecture version number. Indicates the version number of the
architecture of the MMU implemented by the processor.
00 Version 1.0
01 Reserved
10 Reserved
11 Reserved
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RM0004
TLB configuration registers (TLBnCFG)
TLBnCFG registers, shown below, provide information about each specific TLB that is
visible to the programming model. TLB0CFG corresponds to TLB0, TLB1CFG corresponds
to TLB1, etc.
Figure 45. TLB configuration register n (TLB0CFG)
SPR 688 (TLB0CFG)
689 (TLB1CFG)
32
R
39 40
ASSOC
43 44
MINSIZE
Access: Supervisor read-only
47
48
49
50 51 52
MAXSIZE IPROT AVAIL
—
63
NENTRY
W
Reset
Implementation-specific value
Table 36. TLBnCFG field descriptions
Bits
Description
ASSOC
Associativity of TLBn. Number of ways of associativity of TLB array.
0000_0000 Fully associative (A value equal to NENTRY also indicates fully
associative.)
0000_0001 1-way set associative
0000_0002 2-way set associative
…
MINSIZE
Minimum page size of TLBn
0001 Indicates smallest page size is 4 Kbytes
0002 Indicates smallest page size is 8 Kbytes
…
44–47
MAXSIZE
Maximum page size of TLBn
0001 Indicates maximum page size is 4 Kbytes
0002 Indicates maximum page size is 8 Kbytes
…
48
IPROT
Invalidate protect capability of TLBn array.
0 Indicates invalidate protection capability not supported.
1 Indicates invalidate protection capability supported.
49
AVAIL
Page size availability of TLBn array.
0 Fixed selectable page size from MINSIZE to MAXSIZE (all TLB entries are
the same size).
1 Variable page size from MINSIZE to MAXSIZE (each TLB entry can be sized
separately).
50–51
—
52–63
NENTRY
32–39
40–43
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Name
Reserved, should be cleared.
Number of entries in TLBn
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3.12.5
Register model
MMU assist registers (MAS0–MAS7)
MMU assist registers are defined by the EIS and used by the MMU to manage pages and
TLBs. Note that some fields in these registers are redefined by implementations.
3.12.5.1
MAS register 0 (MAS0)
MAS0, is used for MMU read/write and replacement control.
Figure 46. MAS register 0 (MAS0)
SPR 624
Access: Supervisor read/write
47 48
32 33 34 35 36
51 52
61 62 63
R
—
TLBSEL
ESEL
—
NV
W
Reset
All zeros
Table 37. MAS0 field descriptions
Bits
Name
32–33
—
Comments or function when set
Reserved, should be cleared.
Selects TLB for access.
00 TLB0
34–35 TLBSEL 01 TLB1
10 TLB2
11 TLB3
36–47
ESEL
48–51
—
Reserved, should be cleared.
NV
Next victim. For those TLBs that support the NV field, provides a hint to software
to identify the next victim to be targeted for a TLB miss replacement operation. If
the TLB selected by MAS0[TLBSEL] does not support NV, this field is undefined.
The computation of NV is implementation-dependent. NV is updated on TLB error
exceptions (misses), tlbsx hit and miss cases, as shown in Table 194, and on
execution of tlbre if the accessed TLB array supports NV. If NV is updated by a
supported TLB array, NV always presents a value that can be used in
MAS0[ESEL].
52–63
3.12.5.2
Entry select. Identifies an entry in the selected array to be used for tlbwe and
tlbre. Valid values for ESEL are from 0 to TLBnCFG[ASSOC] - 1. That is, ESEL
selects the way from a set of entries determined by MAS3[EPN]. For fully
associative TLB arrays, ESEL ranges from 0 to TLBnCFG[NENTRY] - 1. ESEL is
also updated on TLB error exceptions (misses) and tlbsx hit and miss cases.
MAS register 1 (MAS1)
Below is the format of MAS1.
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Figure 47. MAS register 1 (MAS1) format
SPR 625
32
33
Access: Supervisor read/write
34
47 48
50 51 52
55 56
63
R
V IPROT
TID
—
TS
TSIZE
—
W
Reset
All zeros
Table 38. MAS1 field descriptions—descriptor context and configuration control
Bits
Name
32
V
33
Descriptions
TLB valid bit.
0 This TLB entry is invalid.
1 This TLB entry is valid.
Invalidate protect. Set to protect this TLB entry from invalidate operations due the
execution of tlbivax, broadcast invalidations from another processor, or flash
invalidations. Note that not all TLB arrays are necessarily protected from
IPROT invalidation with IPROT. Arrays that support invalidate protection are denoted as
such in the TLB configuration registers.
0 Entry is not protected from invalidation.
1 Entry is protected from invalidation.
34–35
—
Reserved, should be cleared.
36–47
TID
48–50
—
Reserved, should be cleared.
51
TS
Translation space. During translation, TS is compared with AS (MSR[IS] or
MSR[DS], depending on the type of access) to select a TLB entry.
Translation identity. During translation, TID is compared with the current process
IDs (PIDs) to select a TLB entry. A TID value of 0 defines an entry as global and
matches with all process IDs.
Translation size. Defines the page size of the TLB entry. For TLB arrays that
contain fixed-size TLB entries, TSIZE is ignored. For variable page-size TLB
arrays, the page size is 4TSIZE Kbytes. TSIZE must be between
TLBnCFG[MINSIZE] and TLBnCFG[MINSIZE]. Note that the EIS standard
supports all 16 page sizes defined in Book E.
3.12.5.3
52–55
TSIZE
56–63
—
0001
0010
0011
0100
0101
0110
4 Kbyte
16 Kbyte
64 Kbyte
256 Kbyte
1 Mbyte
4 Mbyte
0111
1000
1001
1010
1011
16 Mbyte
64 Mbyte
256 Mbyte
1 Gbyte
4 Gbyte
Reserved, should be cleared.
MAS register 2 (MAS2)
MAS2, contains fields for specifying the effective page address and the storage attributes
for a TLB entry.
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Figure 48. MAS register 2 (MAS2)
SPR 626
Access: supervisor read/write
32
51 52
55 56 57 58 59 60 61 62 63
R
EPN
—
W
Reset
ACM VLE
W I M G E
X0 X1
Undefined
Table 39. MAS2 field descriptions—EPN and page attributes
Bits
32–51
52–55
56–57
Name
Effective page number. Depending on page size, only the bits associated with a page boundary are
EPN valid. Bits that represent offsets within a page are ignored and should be zero. EPN[0–31] are
accessible only in 64-bit implementations as the upper 32 bits of the logical address of the page.
—
VLE
X1
59
W
61
Reserved, should be cleared.
Alternate coherency mode. Allows an implementation to employ multiple coherency methods. If the
M
attribute (memory coherence required) is not set for a page (M=0), the page has no coherency
ACM
associated with it and ACM is ignored. If the M attribute is set for a page (M=1), ACM determines the
X0
coherency domain (or protocol) used. ACM values are implementation dependent.
Note: Some previous implementations may have a storage bit in the bit 57 position labeled as X0.
58
60
Description
VLE mode. Identifies pages which contain instructions from the VLE instruction set. The VLE
attribute is only implemented if the processor supports the VLE extension. Setting the VLE attribute
to 1 and setting the E attribute to 1 is considered a programming error and an attempt to fetch
instructions from a page so marked produces an instruction storage interrupt byte ordering exception
and sets ESR[BO].
0 Instructions fetched from the page are decoded and executed as PowerPC (and associated EIS
APUs) instructions.
1 Instructions fetched from the page are decoded and executed as VLE (and associated EIS APUs)
instructions.Implementation-dependent page attribute.
Note: Some implementations have a bit in this position labeled as X1. Software should not use the
presence of this bit (the ability to set to 1 and read a 1) to determine if the implementation
supports the VLE extension.
Write-through
0 This page is considered write-back with respect to the caches in the system.
1 All stores performed to this page are written through the caches to main memory.
I
Caching-inhibited
0 Accesses to this page are considered cacheable.
1 The page is considered caching-inhibited. All loads and stores to the page bypass the caches and
are performed directly to main memory. A read or write to a caching-inhibited page affects only
the memory element specified by the operation.
M
Memory coherence required
0 Memory coherence is not required.
1 Memory coherence is required. This allows loads and stores to this page to be coherent with loads
and stores from other processors (and devices) in the system, assuming all such devices are
participating in the coherence protocol.
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Table 39. MAS2 field descriptions—EPN and page attributes (continued)
Bits
Name
62
63
3.12.5.4
Description
G
Guarded
0 Accesses to this page are not guarded and can be performed before it is known if they are
required by the sequential execution model.
1 Loads and stores to this page are performed without speculation (that is, they are known to be
required).
E
Endianness. Determines endianness for the corresponding page. Little-endian operation is true little
endian, which differs from the modified little-endian byte-ordering model optionally available in
previous devices that implement the PowerPC architecture.
0 The page is accessed in big-endian byte order.
1 The page is accessed in true little-endian byte order.
MAS register 3 (MAS3)
MAS3 contains fields for specifying the real page address and the permission attributes for
a TLB entry.
Figure 49. MAS register 3 (MAS3)
SPR 627
Access: Supervisor read/write
32
51 52 53 54
57 58 59 60 61 62 63
R
RPN(32–51)
—
U0–U3
UX SX UWSWUR SR
W
Reset
All zeros
Table 40. MAS3 field descriptions–RPN and access control
Bits
32–51
3.12.5.5
Name
Description
Real page number bits 32–51. Depending on page size, only the bits
associated with a page boundary are valid. Bits that represent offsets within a
RPN[32–51]
page are ignored and should be zero. If the physical address space exceeds
32 bits, RPN[0–31] are accessed through MAS7.
52–53
—
Reserved, should be cleared.
54–57
U0–U3
User bits. Associated with a TLB entry and used by system software. For
example, these bits may be used to hold information useful to a page
scanning algorithm or be used to mark more abstract page attributes.
58–63
UX,SX
UW,SW
UR,SR
Permission bits (UX, SX, UW, SW, UR, SR). User and supervisor read, write,
and execute permission bits. Effects of the permission bits are defined by
Book E.
MAS register 4 (MAS4)
MAS4,contains fields for specifying default information to be pre-loaded on certain MMU
related exceptions.
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Figure 50. MAS register 4 (MAS4)
SPR 628
3233 34
35
43 44
36
Access: Supervisor read/write
47 48
51 52
55 56 57
R
— TLBSELD
—
TIDSELD
—
TSIZED
W
Reset
58
59 60 61 62 63
ACMD VLED
WD ID MD GD ED
X0D X1D
All zeros
The MAS4 fields are described in Table 41.
Table 41. MAS4 field descriptions—hardware replacement assist configuration
Bits
Name
32–33
—
34–35
TLBSELD
36–43
—
Description
Reserved, should be cleared.
TLBSEL default value. Specifies the default value loaded in MAS0[TLBSEL]
on a TLB miss exception.
Reserved, should be cleared.
TID default selection value. Specifies which of the current PID registers
should be used to load MAS1[TID] on a TLB miss exception.
PID registers are addressed as follows:
0000 = PID0 (PID)
0001 = PID1
...
1110 = PID14
A value that references a non-implemented PID register causes a value of 0
to be placed in MAS1[TID]. See the implementations documentation for a list
of supported PIDs.
44–47
TIDSELD
48–51
—
52–55
TSIZED
Default TSIZE value. Specifies the default value loaded into MAS1[TSIZE] on
a TLB miss exception.
56–57
ACMD
Default ACM value Specifies the default value loaded into MAS2[ACM] on a
TLB miss exception.
58
VLED
Default VLE value. Specifies the default value loaded into MAS2[VLE] on a
TLB miss exception.
59
WD
Default W value. Specifies the default value loaded into MAS2[W] on a TLB
miss exception.
60
ID
Default I value. Specifies the default value loaded into MAS2[I] on a TLB miss
exception.
61
MD
Default M value. Specifies the default value loaded into MAS2[M] on a TLB
miss exception.
62
GD
Default G value. Specifies the default value loaded into MAS2[G] on a TLB
miss exception.
63
ED
Default E value. Specifies the default value loaded into MAS2[E] on a TLB
miss exception.
Reserved, should be cleared.
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RM0004
MAS register 5 (MAS5)
The optional MAS5 register, contains fields for specifying PID values to be used when
searching TLB entries with the tlbsx instruction.
Figure 51. MAS register 5 (MAS5)
SPR 629
Access: supervisor read/write
32 33 34
47 48 49 50
63
R
—
SPID2
—
SPID3
W
Reset
All zeros
Table 42. MAS5 field descriptions—extended search pIDs
3.12.5.7
Bits
Name
32–33
—
34–47
SPID2
48–49
—
50–63
SPID3
Description
Reserved, should be cleared.
Search PID2. Specifies the PID2 value used when searching the TLB during
execution of tlbsx. This field is optional and if implemented is valid for only the
number of bits implemented for PID registers.
Reserved, should be cleared.
Search PID3. Specifies the PID3 value used when searching the TLB during
execution of tlbsx. This field is optional and if implemented is valid for only the
number of bits implemented for PID registers.
MAS register 6 (MAS6)
MAS6, contains fields for specifying PID and AS values to be used when searching TLB
entries with the tlbsx instruction.
Figure 52. MAS register 6 (MAS6)
SPR 630
Access: supervisor read/write
32 33 34
47 48 49
62 63
R
—
SPID0
—
SPID1
SAS
W
Reset
All zeros
Table 43. MAS 6 field descriptions—search pids and search AS
Bits
Name
32–33
—
34–47
SPID0
48
—
108/1025
Description
Reserved, should be cleared.
Search PID0. Specifies the value of PID0 used when searching the TLB during execution
of tlbsx. SPID0 is valid for only the number of bits implemented for PID registers.
Reserved, should be cleared.
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Register model
Table 43. MAS 6 field descriptions—search pids and search AS (continued)
Bits
Name
Description
49–62
SPID1
Search PID1. Specifies the value of PID1 used when searching the TLB during execution
of tlbsx.SPID1 is optional, and if implemented is valid for only the number of bits
implemented for PID registers.
63
SAS
Address space value for searches. Specifies the AS value used when executing tlbsx to
search the TLB.
3.12.5.8
MAS register 7 (MAS7)
MAS7, contains the high-order address bits of the RPN only for implementations that
support more than 32 bits of physical address.
Figure 53. MAS register 7 (MAS7)
SPR 944
Access: supervisor read/write
32
59 60
63
R
RPN (0–31)
W
Reset
All zeros
Table 44. MAS 7 field descriptions—high order RPN
3.13
Bits
Name
32–63
RPN[0–31]
Description
Real page number (bits 0–31). RPN[32–63] are accessed through MAS3.
Debug registers
This section describes debug-related registers that are accessible to software running on
the processor. These registers are intended for use by special debug tools and debug
software, and not by general application or operating system code.
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3.13.1
RM0004
Debug control registers (DBCR0–DBCR3)
The debug control registers are used to enable debug events, reset the processor, control
timer operation during debug events, and set the debug mode of the processor.
3.13.1.1
Debug control register 0 (DBCR0)
Below is the DBCR0.
Figure 54. Debug control register 0 (DBCR0)
SPR 308
32
R
Access: Supervisor-only
33
34
35
36
37
38
39
40
41
42
43
IAC2
IAC3
IAC4
44
45
46
47
EDM
IDM
RST
ICMP BRT
IRPT TRAP IAC1
DAC1
DAC2
W
Reset
All zeros
Debug APU
48
49
56
RET
—
Reset
57
58
59
CIRPT CRET VLES
60
62
—
63
FT
All zeros
Table 45. DBCR0 field descriptions
Bits
32
33
34–35
110/1025
Name
Description
EDM
External debug mode. Indicates whether the processor is in external debug
mode.
0 The processor is not in external debug mode.
1 The processor is in external debug mode. In some implementations, if EDM =
1, some debug registers are locked and cannot be accessed. Refer to the
implementation documentation for any additional implementation-specific
behavior.
IDM
Internal debug mode.
0 Debug interrupts are disabled. No debug interrupts are taken and debug events
are not logged.
1 If MSR[DE] = 1, the occurrence of a debug event or the recording of an earlier
debug event in the DBSR when MSR[DE] = 0 or DBCR0[IDM] = 0 causes a
debug interrupt.
Programming note: Software must clear debug event status in the DBSR in the
debug interrupt handler when a debug interrupt is taken before re-enabling
interrupts through MSR[DE]. Otherwise, redundant debug interrupts are taken for
the same debug event.
RST
Reset. Book E defines RST such that 00 is always no action and all other settings
are implementation
0x Default (No action)
1x A hard reset is performed on the processor.
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Register model
Table 45. DBCR0 field descriptions (continued)
Bits
Name
Description
ICMP
Instruction completion debug event enable
0 ICMP debug events are disabled.
1 ICMP debug events are enabled.
Note: Instruction completion does not cause an ICMP debug event if MSR[DE]=0.
37
BRT
Branch taken debug event enable
0 BRT debug events are disabled.
1 BRT debug events are enabled.
Note: Taken branches do not cause a BRT debug event if MSR[DE]=0.
38
IRPT
Interrupt taken debug event enable.
0 IRPT debug events are disabled.
1 IRPT debug events are enabled
39
TRAP
Trap debug event enable
0 TRAP debug events cannot occur.
1 TRAP debug events can occur.
40
IAC1
Instruction address compare 1 debug event enable
0 IAC1 debug events cannot occur.
1 IAC1 debug events can occur.
41
IAC2
Instruction address compare 2 debug event enable.
0 IAC2 debug events cannot occur.
1 IAC2 debug events can occur.
42
IAC3
Defined by Book E as instruction address compare 3 debug event enable
0 IAC3 debug events cannot occur.
1 IAC3 debug events can occur.
43
IAC4
Defined by Book E as instruction address compare 4 debug event enable
0 IAC4 debug events cannot occur.
1 IAC4 debug events can occur.
DAC1
Data address compare 1 debug event enable
00 DAC1 debug events cannot occur.
01 DAC1 debug events can occur only if a store-type data storage access.
10 DAC1 debug events can occur only if a load-type data storage access.
11 DAC1 debug events can occur on any data storage access.
DAC2
Data address compare 2 debug event enable
00 DAC2 debug events cannot occur.
01 DAC2 debug events can occur only if a store-type data storage access.
10 DAC2 debug events can occur only if a load-type data storage access.
11 DAC2 debug events can occur on any data storage access.
36
44–45
46–47
48
RET
49–56
—
Return debug event enable
0 RET debug events cannot occur.
1 RET debug events can occur.
Note: An rfci does not cause an RET debug event if MSR[DE] = 0 at the time that
rfci executes.
Reserved, should be cleared.
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RM0004
Table 45. DBCR0 field descriptions (continued)
Bits
Name
Description
CIRPT
Debug APU, Critical interrupt taken debug event. A critical interrupt taken debug
event occurs when DBCR0[CIRPT] = 1 and a critical interrupt (any interrupt that
uses the critical class, that is, uses CSRR0 and CSRR1) occurs.
0 Critical interrupt taken debug events are disabled.
1 Critical interrupt taken debug events are enabled.
CRET
Debug APU. Critical interrupt return debug event. A critical interrupt return debug
event occurs when DBCR0[CRET] = 1 and a return from critical interrupt (an rfci
instruction is executed) occurs.
0 Critical interrupt return debug events are disabled.
1 Critical interrupt return debug events are enabled.
59
VLES
VLE status. (VLE APU). Undefined for IRPT, CIRPT, DEVT[1,2], DCNT[1,2], and
UDE events.
0 CRET debug events are disabled.
1 An ICMP, BRT, TRAP, RET, CRET, IAC, or DAC debug event occurred on a VLE
instruction.
60–62
—
Reserved
63
FT
Freeze timers on debug event
0 Enable clocking of timers.
1 Disable clocking of timers if any DBSR bit is set (except MRR).
57
58
3.13.1.2
Debug control register 1 (DBCR1)
DBCR1 is shown below.
Figure 55. Debug control register 1 (DBCR1)
SPR 309
32 33
Access: supervisor read/write
34 35 36 37 38 39 40 41 42
47 48 49 50 51 52 53 54 55 56 57 58
63
R
IAC1US IAC1ER IAC2US IAC2ER IAC12M
—
IAC3US IAC3ER IAC4US IAC4ER IAC34M
W
Reset
All zeros
Table 46 provides bit definitions for the DBCR1.
Table 46. DBCR1 field descriptions
Bits
32–33
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Name
IAC1US
Description
Instruction address compare 1 user/supervisor mode
00 IAC1 debug events can occur.
01 Reserved
10 IAC1 debug events can occur only if MSR[PR]=0.
11 IAC1 debug events can occur only if MSR[PR]=1.
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RM0004
Register model
Table 46. DBCR1 field descriptions (continued)
Bits
Name
Description
IAC1ER
Instruction address compare 1 effective/real mode
00 IAC1 debug events are based on effective addresses.
01 IAC1 debug events are based on real addresses.
10 IAC1 debug events are based on effective addresses and can occur only if
MSR[IS]=0.
11 IAC1 debug events are based on effective addresses and can occur only if
MSR[IS]=1.
IAC2US
Instruction address compare 2 user/supervisor mode
00 IAC2 debug events can occur.
01 Reserved
10 IAC2 debug events can occur only if MSR[PR]=0.
11 IAC2 debug events can occur only if MSR[PR]=1.
IAC2ER
Instruction address compare 2 effective/real mode
00 IAC2 debug events are based on effective addresses.
01 IAC2 debug events are based on real addresses.
10 IAC2 debug events are based on effective addresses and can occur only if
MSR[IS]=0.
11 IAC2 debug events are based on effective addresses and can occur only if
MSR[IS]=1.
40–41
IAC12M
Instruction address compare 1/2 mode
00 Exact address compare. IAC1 debug events can occur only if the instruction
fetch address equals the value in IAC1. IAC2 debug events can occur only if
the instruction fetch address equals the value in IAC2.
01 Address bit match. IAC1 and IAC2 debug events can occur only if the
instruction fetch address, ANDed with the contents of IAC2, equals the value
in IAC1, also ANDed with the contents of IAC2.
If IAC1USIAC2US or IAC1ERIAC2ER, results are boundedly undefined.
10 Inclusive address range compare. IAC1 and IAC2 debug events can occur
only if the instruction fetch address lies between the values specified in IAC1
and IAC2.
If IAC1USIAC2US or IAC1ERIAC2ER, results are boundedly undefined.
11 Exclusive address range compare. IAC1 and IAC2 debug events can occur
only if the instruction fetch address lies between the values specified in IAC1
and IAC2.
If IAC1USIAC2US or IAC1ERIAC2ER, results are boundedly undefined.
42–47
—
34–35
36–37
38–39
48–49
50–51
Reserved, should be cleared.
IAC3US
Instruction address compare 3 user/supervisor mode
00 IAC3 debug events can occur.
01 Reserved
10 IAC3 debug events can occur only if MSR[PR]=0.
11 IAC3 debug events can occur only if MSR[PR]=1.
IAC3ER
Instruction address compare 3 effective/real mode
00 IAC3 debug events are based on effective addresses.
01 IAC3 debug events are based on real addresses.
10 IAC3 debug events are based on effective addresses and can occur only if
MSR[IS]=0.
11 IAC3 debug events are based on effective addresses and can occur only if
MSR[IS]=1.
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RM0004
Table 46. DBCR1 field descriptions (continued)
Bits
Name
IAC4US
Instruction address compare 4 user/supervisor mode
00 IAC4 debug events can occur.
01 Reserved
10 IAC4 debug events can occur only if MSR[PR]=0.
11 IAC4 debug events can occur only if MSR[PR]=1.
IAC4ER
Instruction address compare 4 effective/real mode
00 IAC4 debug events are based on effective addresses.
01 IAC4 debug events are based on real addresses.
10 IAC4 debug events are based on effective addresses and can occur only if
MSR[IS]=0.
11 IAC4 debug events are based on effective addresses and can occur only if
MSR[IS]=1.
56–57
IAC34M
Instruction address compare 3/4 mode
00 Exact address compare. IAC3 debug events can occur only if the instruction
fetch address equals the value in IAC3. IAC4 debug events can occur only if
the instruction fetch address equals the value in IAC4.
01 Address bit match. IAC3 and IAC4 debug events can occur only if the data
storage access address, ANDed with the contents of IAC4, equals the value
in IAC3, also ANDed with the contents of IAC4.
If IAC3USIAC4US or IAC3ERIAC4ER, results are boundedly undefined.
10 Inclusive address range compare. IAC3 and IAC4 debug events can occur
only if the instruction fetch address lies between the values specified in IAC3
and IAC4.
If IAC3USIAC4US or IAC3ERIAC4ER, results are boundedly undefined.
11 Exclusive address range compare. IAC3 and IAC4 debug events can occur
only if the instruction fetch address lies between the values specified in IAC3
and IAC4.
If IAC3USIAC4US or IAC3ERIAC4ER, results are boundedly undefined.
58–63
—
52–53
54–55
3.13.1.3
Description
Reserved, should be cleared.
Debug control register 2 (DBCR2)
DBCR2 is shown below.
Figure 56. Debug control register 2 (DBCR2)
SPR 310
32 33 34
R
W
Access: Supervisor read/write
35 36 37 38 39 40 41
42
43
44 45 46 47 48
55 56
DAC1U
DAC2U DAC2E DAC12
D‘AC1ER
DAC1LNK DAC2LNK DVC1MDVC2M DVC1BE
S
S
R
M
Reset
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DVC2BE
RM0004
Register model
Table 47. DBCR2 field descriptions
Bits
32–33
34–35
36–37
38–39
40–41
42
Name
Description
DAC1US
Data address compare 1 user/supervisor mode
00 DAC1 debug events can occur.
01 Reserved
10 DAC1 debug events can occur only if MSR[PR]=0.
11 DAC1 debug events can occur only if MSR[PR]=1.
DAC1ER
Data address compare 1 effective/real mode
00 DAC1 debug events are based on effective addresses.
01 DAC1 debug events are based on real addresses.
10 DAC1 debug events are based on effective addresses and can occur only
if MSR[DS]=0.
11 DAC1 debug events are based on effective addresses and can occur only
if MSR[DS]=1.
DAC2US
Data address compare 2 user/supervisor mode
00 DAC2 debug events can occur.
01 Reserved
10 DAC2 debug events can occur only if MSR[PR]=0.
11 DAC2 debug events can occur only if MSR[PR]=1.
DAC2ER
Data address compare 2 effective/real mode
00 DAC2 debug events are based on effective addresses.
01 DAC2 debug events are based on real addresses.
10 DAC2 debug events are based on effective addresses and can occur only
if MSR[DS]=0.
11 DAC2 debug events are based on effective addresses and can occur only
if MSR[DS]=1.
DAC12M
Data address compare 1/2 mode
00 Exact address compare. DAC1 debug events can occur only if the data
access address equals the value in DAC1. DAC2 debug events can occur
only if the data access address equals the value in DAC2.
01 Address bit match. DAC1 and DAC2 debug events can occur only if the
data access address, ANDed with the contents of DAC2, equals the value
in DAC1, also ANDed with the DAC2 contents.
If DAC1USDAC2US or DAC1ERDAC2ER, results are boundedly
undefined.
10 Inclusive address range compare. DAC1 and DAC2 debug events can
occur only if the data access address lies between the values specified in
DAC1 and DAC2.
If DAC1USDAC2US or DAC1ERDAC2ER, results are boundedly
undefined.
11 Exclusive address range compare. DAC1 and DAC2 debug events can
occur only if the data access address lies between the values specified in
DAC1 and DAC2.
If DAC1USDAC2US or DAC1ERDAC2ER, results are boundedly
undefined.
Data address compare 1 linked
0 No effect
1 DAC1 debug events are linked to IAC1 debug events. IAC1 debug events do
DAC1LNK
not affect DBSR.
When linked to IAC1, DAC1 debug events are conditioned based on whether
the instruction also generated an IAC1 debug event.
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RM0004
Table 47. DBCR2 field descriptions (continued)
Bits
Name
Data address compare 2 linked
0 No effect
1 DAC 2 debug events are linked to IAC3 debug events. IAC3 debug events
do not affect DBSR.
DAC2LNK
When linked to IAC3, DAC2 debug events are conditioned based on whether
the instruction also generated an IAC3 debug event. DAC2 can only be
linked if DAC12M specifies exact address compare because DAC2 debug
events are not generated in the other compare modes.
43
DVC1M
Data value compare 1 mode
00 DAC1 debug events can occur.
01 DAC1 debug events can occur only when all bytes in DBCR2[DVC1BE] in
the data value of the data storage access match their corresponding bytes
in DVC1.
10 DAC1 debug events can occur only when at least one of the bytes in
DBCR2[DVC1BE] in the data value of the data storage access matches its
corresponding byte in DVC1.
11 DAC1 debug events can occur only when all bytes in DBCR2[DVC1BE]
within at least one of the half words of the data value of the data storage
access match their corresponding bytes in DVC1.
46–47
DVC2M
Data value compare 2 mode
00 DAC2 debug events can occur.
01 DAC2 debug events can occur only when all bytes in DBCR2[DVC2BE] in
the data value of the data storage access match their corresponding bytes
in DVC2.
10 DAC2 debug events can occur only when at least one of the bytes in
DBCR2[DVC2BE] in the data value of the data storage access matches its
corresponding byte in DVC2.
11 DAC2 debug events can occur only when all bytes in DBCR2[DVC2BE]
within at least one of the half words of the data value of the data storage
access match their corresponding bytes in DVC2.
48–55
DVC1BE
Data value compare 1 byte enables. Specifies which bytes in the aligned data
value being read or written by the storage access are compared to the
corresponding bytes in DVC1.
56–63
DVC2BE
Data value compare 2 byte enables. Specifies which bytes in the aligned data
value being read or written by the storage access are compared to the
corresponding bytes in DVC2.
44–45
3.13.1.4
Description
Debug control register 3 (DBCR3)
The debug APU defines the DBCR3, however its contents are implementation specific.
Figure 57. Debug control register 3 (DBCR3)
SPR 561
Access: Supervisor-only
32
63
R
Implementation-specific fields
W
Reset
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Register model
Debug status register (DBSR)
3.13.2
The DBSR, provides status debug events information for the most recent processor reset.
Figure 58. Debug status register (DBSR)
SPR: 304
32
33
34
R
IDE UDE MRR
W
w1c
w1c
Reset
0
0
w1c
35
36
Access: Supervisor: w1c
37
38
39
40
41
42
43
44
ICMP BRT IRPT TRAP IAC1 IAC2 IAC3 IAC3 DAC1R
w1c
undefined
45
46
47
DAC1
DAC2
DAC2R
W
W
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
w1c
0
0
0
0
0
0
0
0
0
0
0
0
Debug APU
48
R
49
56
RET
57
58
59
63
CIRPT CRET
—
W
w1c
Reset
0
0
0
0
0
—
0
0
0
0
w1c
w1c
0
0
0
0
0
0
0
The DBSR is set through hardware, but is read through software using mfspr and cleared
by writing ones to them; writing zeros has no effect.
Table 48. DBSR field descriptions
Bits
Name
Description
32
IDE
Imprecise debug event. Set if MSR[DE] = 0 and a debug event causes its respective DBSR
bit to be set.
33
UDE
Unconditional debug event. Set if an unconditional debug event occurred. If the UDE signal
(level sensitive, active low) is asserted, DBSR[UDE] is affected as follows:
MSR[DE]DBCR0[IDM]Action
X
0
No action.
0
1
DBSR[UDE] is set.
1
1
DBSR[UDE] is set and a debug interrupt is taken.
34–35
MRR
Most recent reset. Set when a reset occurs. Undefined at power-up. See the implementation
documentation.
36
ICMP
Instruction complete debug event. Set if an instruction completion debug event occurred and
DBCR0[ICMP] = 1.
37
BRT
Branch taken debug event. Set if a branch taken debug event occurred (DBCR0[BRT]=1).
38
IRPT
Interrupt taken debug event. Set if an interrupt taken debug event occurred
(DBCR0[IRPT]=1).
39
TRAP
Trap instruction debug event. Set if a trap Instruction debug event occurred
(DBCR0[TRAP]=1).
40
IAC1
Instruction address compare 1 debug event. Set if an IAC1 debug event occurred
(DBCR0[IAC1]=1).
41
IAC2
Instruction address compare 2 debug event. Set if an IAC2 debug event occurred
(DBCR0[IAC2]=1).
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RM0004
Table 48. DBSR field descriptions (continued)
Bits
Name
Description
42
IAC3
Instruction address compare 3 debug event. Set if an IAC3 debug event occurred
(DBCR0[IAC3]=1).
43
IAC4
Instruction address compare 4 debug event. Set if an IAC4 debug event occurred
(DBCR0[IAC4]=1).
44
DAC1R
Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurred
(DBCR0[DAC1]=10 or 11).
45
DAC1W
Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurred
(DBCR0[DAC1]=01 or 11).
46
DAC2R
Data address compare 2 read debug event.Set if a read-type DAC2 debug event occurred
(DBCR0[DAC2]=10 or 11).
47
DAC2W
Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurred
(DBCR0[DAC2] =01 or 11).
48
RET
49–56
—
Return debug event. Set if a return debug event occurred (DBCR0[RET]=1).
Reserved, should be cleared.
CIRPT
Debug APU. Critical interrupt taken debug event. A critical interrupt taken debug event
occurs when DBCR0[CIRPT] = 1 and a critical interrupt (any interrupt that uses the critical
class, that is, uses CSRR0 and CSRR1) occurs.
0 No critical interrupt taken debug event has occurred.
1 A critical interrupt taken debug event occurred.
58
CRET
Debug APU. Critical interrupt return debug event. A critical interrupt return debug event
occurs when DBCR0[CRET] = 1 and a return from critical interrupt (an rfci instruction is
executed) occurs.
0 No critical interrupt return debug event has occurred.
1 A critical interrupt return debug event occurred.
59–63
—
57
3.13.3
Reserved, should be cleared.
Instruction address compare registers (IAC1–IAC4)
The instruction address compare registers (IAC1–IAC4) are each 64 bits, with bits 62–63
being reserved.
Figure 59. Instruction address compare registers (IAC1–IAC4)
SPR 312 (IAC1)
313 (IAC2)
314 (IAC3)
315 (IAC4)
Access: supervisor read/write
32
61 62 63
R
instruction address
—
W
Reset
All zeros
A debug event may be enabled to occur upon an attempt to execute an instruction from an
address specified in an IAC, inside or outside a range specified by IAC1 and IAC2 or, inside
or outside a range specified by IAC3 and IAC4, or to blocks of addresses specified by the
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Register model
combination of the IAC1 and IAC2, or to blocks of addresses specified by the combination of
the IAC3 and IAC4. Because all instruction addresses are required to be word-aligned, the
two low-order bits of the IACs are reserved and do not participate in the comparison to the
instruction address.
3.13.4
Data address compare registers (DAC1–DAC2)
The data address compare registers (DAC1 and DAC2), are each 32 bits. A debug event
may be enabled to occur upon loads, stores, or cache operations to an address specified in
either DAC1 or DAC2, inside or outside a range specified by the DAC1 and DAC2, or to
blocks of addresses specified by the combination of the DAC1 and DAC2.
Figure 60. Data address compare registers (DAC1–DAC2)
SPR 316 (DAC1)
317 (DAC2)
Access: Supervisor read/write
32
63
R
Data address
W
Reset
All zeros
The contents of DAC1 or DAC2 are compared to the address generated by a data storage
access instruction.
3.13.5
Data value compare registers (DVC1 and DVC2)
The data value compare registers (DVC1 and DVC2) are shown below. A DAC1R, DAC1W,
DAC2R, or DAC2W debug event may be enabled to occur upon loads or stores of a specific
data value specified in either or both of DVC1 and DVC2. DBCR2[DVC1M] and
DBCR2[DVC1BE] control how the contents of DVC1 is compared with the value and
DBCR2[DVC2M] and DBCR2[DVC2BE] control how the contents of DVC2 is compared with
the value. Table 47 describes the modes provided.
Figure 61. Data value compare registers (DVC1–DVC2)
SPR 318 (DVC1)
319 (DVC2)
Access: Supervisor read/write
32
63
R
Data value
W
Reset
3.14
All zeros
SPE and SPFP APU registers
The SPE and SPFP include the signal processing and embedded floating-point status and
control register (SPEFSCR), which is described in Section 3.14.1: Signal processing,
embedded floating-point status, control register (SPEFSCR), and the SPE implements a 64bit accumulator, described in Section 3.14.2: Accumulator (ACC).
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3.14.1
RM0004
Signal processing, embedded floating-point status, control register
(SPEFSCR)
SPEFSCR, is used by the SPE and by the embedded floating-point APUs. Vector floatingpoint instructions affect both the high element (bits 34-39) and low element floating-point
status flags (bits 50–55). Double- and single-precision floating-point instructions affect only
the low-element floating-point status flags and leave the high-element floating-point status
flags undefined.
Figure 62. Signal processing, embedded floating-point status and control
register (SPEFSCR)
SPR: 512
Access: supervisor-only
High-Word Error Bits
32
33
34
35
36
37
Status Bits
38
39
40
41
42
43
44
45
R
SOVHOVH FGH FXH FINVH FDBZH FUNFH FOVFH
—
FINXS FINVS FDBZS FUNFS
46
FOVF
S
47
MOD
E
W
Reset
0
0 undefined
0
0
0
0
0
0
0
0
0
0
0
0
60
61
62
63
Enable Bits
48
49
50
51
52
53
54
55
56
57
58
59
R
SOV OV FG FX FINV FDBZ FUNF FOVF — FINXE FINVE FDBZE FUNFE FOVFE
FRMC
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 49. SPEFSCR field descriptions
Bits
Name
Description
32
SOVH
(SPE APU) Summary integer overflow high. Set when an SPE instruction sets OVH. This is a
sticky bit that remains set until it is cleared by an mtspr instruction.
33
OVH
(SPE APU) Integer overflow high. Set when an overflow or underflow occurs in the upper
word of the result of an SPE instruction.
FGH
(FP APUs) Embedded floating-point guard bit high. Used by the floating-point round interrupt
handler. FGH is an extension of the low-order bits of the fractional result produced from a
floating-point operation on the high word. FGH is zeroed if an overflow, underflow, or invalid
input error is detected on the high element of a vector floating-point instruction.
Execution of a scalar floating-point instruction leaves FGH undefined.
FXH
(SPFP APU) Embedded floating-point inexact bit high. Used by the floating-point round
interrupt handler. FXH is an extension of the low-order bits of the fractional result produced
from a floating-point operation on the high word. FXH represents the logical OR of all of the
bits shifted right from the guard bit when the fractional result is normalized. FXH is zeroed if
an overflow, underflow, or invalid input error is detected on the high element of a vector
floating-point instruction.
Execution of a scalar floating-point instruction leaves FXH undefined.
34
35
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Register model
Table 49. SPEFSCR field descriptions (continued)
Bits
Name
Description
FINVH
(FP APUs) Embedded floating-point invalid operation/input error high. Set under any of the
following conditions:
Any operand of a high word vector floating-point instruction is Infinity, NaN, or Denorm
The operation is a divide and the dividend and divisor are both 0
A conversion to integer or fractional value overflows.
Execution of a scalar floating-point instruction leaves FINVH undefined.
37
FDBZH
(FP APUs) Embedded floating-point divide by zero high. Set when a vector floating-point
divide instruction is executed with a divisor of 0 in the high word operand and the dividend is
a finite non-zero number.
Execution of a scalar floating-point instruction leaves FDBZH undefined.
38
FUNFH
(FP APUs) Embedded floating-point underflow high. Set when the execution of a vector
floating-point instruction results in an underflow on the high word operation.
Execution of a scalar floating-point instruction leaves FUNFH undefined.
39
FOVFH
(FP APUs) Embedded floating-point overflow high. Set when the execution of a vector
floating-point instruction results in an overflow on the high word operation.
Execution of a scalar floating-point instruction leaves FOVFH undefined.
40–41
—
36
Reserved, should be cleared.
FINXS
(FP APUs) Embedded floating-point inexact sticky flag. Set under the following conditions:
– Execution of any scalar or vector floating-point instruction delivers an inexact result for
either the low or high element and no floating-point data interrupt is taken for either
element
– A floating-point instruction results in overflow (FOVF=1 or FOVFH=1), but floating-point
overflow exceptions are disabled (FOVFE=0).
– A floating-point instruction results in underflow (FUNF=1 or FUNFH=1), but floating-point
underflow exceptions are disabled (FUNFE=0), and no floating-point data interrupt occurs.
FINXS remains set until it is cleared by software.
43
FINVS
(FP APUs) Embedded floating-point invalid operation sticky flag. The sticky result of any
floating-point instruction that causes FINVH or FINV to be set. That is, FINVS <- FINVS |
FINV | FINVH. This action may optionally be performed by hardware. To ensure proper
operation, software should set this bit on the detection of FINV or FINVH set to one. FINVS
remains set until it is cleared by software. (1)
44
FDBZS
(FP APUs) Embedded floating-point divide by zero sticky flag. Set when a floating-point
divide instruction sets FDBZH or FDBZ. That is, FDBZS <- FDBZS | FDBZH | FDBZ. FDBZS
remains set until it is cleared by software.
FUNFS
(FP APUs) Embedded floating-point underflow sticky flag. Defined to be the sticky result of
any floating-point instruction that causes FUNFH or FUNF to be set. That is, FUNFS <FUNFS | FUNF | FUNFH. This action may optionally be performed by hardware. To ensure
proper operation, software should set this bit on the detection of FUNF or FUNFH being set.
FUNFS remains set until it is cleared by software. 1
FOVFS
(FP APUs) Embedded floating-point overflow sticky flag. defined to be the sticky result of any
floating-point instruction that causes FOVH or FOVF to be set. That is, FOVFS <- FOVFS |
FOVF | FOVFH. This action may optionally be performed by hardware. To ensure proper
operation, software should set this bit on the detection of FOVF or FOVFH being set. FOVFS
remains set until it is cleared by software. 1
42
45
46
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Table 49. SPEFSCR field descriptions (continued)
Bits
Name
Description
(FP APUs) Embedded floating-point operating mode. Controls the operating mode of the
embedded floating-point operations defined in the SPE, and the embedded floating-point
APUs.
0 Default hardware results operating mode
1 Reserved.
47
MODE
48
SOV
(SPE APU) Summary integer overflow low. Set when an SPE instruction sets OV. This sticky
bit remains set until an mtspr writes a 0 to this bit.
49
OV
(SPE APU) Integer overflow low. OV is set when an overflow or underflow occurs in the lower
word of the result of an SPE instruction.
FG
(FP APUs) Embedded floating-point guard bit (low/scalar) Used by the floating-point round
interrupt handler. FG is an extension of the low-order bits of the fractional result produced
from a floating-point operation on the low word or any scalar floating-point operation. FG is
cleared if an overflow, underflow, or invalid input error is detected on either the low element of
a vector floating-point instruction or any scalar floating-point instruction.
FX
(FP APUs) Embedded floating-point inexact bit (low/scalar). Used by the floating-point round
interrupt handler. FX is an extension of the low-order bits of the fractional result produced
from a floating-point operation on the low word or any scalar floating-point instruction. FX
represents the logical OR of all of the bits shifted right from the guard bit when the fractional
result is normalized. FX is zeroed if an overflow, underflow, or invalid input error is detected
on either the low element of a vector floating-point instruction or any scalar floating-point
instruction.
50
51
52
FINV
(FP APUs) Embedded floating-point invalid operation/input error (low/scalar). Set by the
following conditions:
– Any operand of a low-word vector or scalar floating-point operation is Infinity, NaN, or
Denorm
– The operation is a divide and the dividend and divisor are both 0
– A conversion to integer or fractional value overflows
53
FDBZ
(FP APUs) Embedded floating-point divide by zero (low/scalar). Set when a scalar or vector
floating-point divide instruction is executed with a divisor of 0 in the low word operand and the
dividend is a finite non-zero number.
54
FUNF
(FP APUs) Embedded floating-point underflow (low/scalar). Set when execution of a scalar
or vector floating-point instruction results in an underflow on the low word operation.
55
FOVF
(FP APUs) Embedded floating-point overflow (low/scalar). Set when the execution of a scalar
or vector floating-point instruction results in an overflow on the low word operation.
56
—
57
58
122/1025
Reserved, should be cleared.
FINXE
(FP APUs) Embedded floating-point round (inexact) exception enable
0 Exception disabled
1 Exception enabled. A floating-point round interrupt is taken if no other interrupt is taken, and
if FG | FGH | FX | FXH (signifying an inexact result) is set as a result of a floating-point
operation.
If a floating-point instruction operation results in overflow or underflow and the corresponding
underflow or overflow exception is disabled, a floating-point round interrupt is taken.
FINVE
(FP APUs) Embedded floating-point invalid operation/input error exception enable
0 Exception disabled
1 Exception enabled. A floating-point data interrupt is taken if a floating-point instruction sets
FINV or FINVH.
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Register model
Table 49. SPEFSCR field descriptions (continued)
Bits
59
60
61
62–63
Name
Description
FDBZE
(FP APUs) Embedded floating-point divide by zero exception enable
0 Exception disabled
1 Exception enabled. A floating-point data interrupt is taken if a floating-point instruction sets
FDBZ or FDBZH.
FUNFE
(FP APUs) Embedded floating-point underflow exception enable
0 Exception disabled
1 Exception enabled. A floating-point data interrupt is taken if a floating-point instruction sets
FUNF or FUNFH.
FOVFE
(FP APUs) Embedded floating-point overflow exception enable
0 Exception disabled
1 Exception enabled. A floating-point data interrupt is taken if a floating-point instruction sets
FOVF or FOVFH.
FRMC
(FP APUs) Embedded floating-point rounding mode control
00 Round to Nearest
01 Round toward Zero
10 Round toward +Infinity. If this mode is not implemented, embedded floating-point round
Interrupts are generated for every floating-point instruction for which rounding is indicated.
11 Round toward -Infinity. If this mode is not implemented, embedded floating-point round
Interrupts are generated for every floating-point instruction for which rounding is indicated.
1. Software note: Software can detect hardware that manages this sticky bit by performing an operation on a NaN and
observing whether hardware sets this sticky bit. In the absence of doing this, if it desired that software written will work on
all processors that support embedded floating-point, software should check the appropriate status bits and set the sticky bit
itself (if hardware also performs this operation, the action is redundant).
3.14.2
Accumulator (ACC)
The 64-bit architectural accumulator register holds the results of the multiply accumulate
(MAC) forms of SPE integer instructions. The accumulator allows back-to-back execution of
dependent MAC instructions, something that is found in the inner loops of DSP code such
as finite impulse response (FIR) filters. The accumulator is partially visible to the
programmer in that its results do not have to be explicitly read to use them. Instead, they are
always copied into a 64-bit destination GPR specified as part of the instruction. The
accumulator, however, has to be explicitly cleared when starting a new MAC loop. Based
upon the type of instruction, an accumulator can hold either a single 64-bit value or a vector
of two 32-bit elements.
The Initialize Accumulator instruction (evmra) is provided to initialize the accumulator. This
instruction is described in Chapter 7: Instruction set.
3.15
Alternate time base registers (ATBL and ATBU)
The alternate time base counter (ATB), is formed by concatenating the upper and lower
alternate time base registers (ATBU and ATBL). ATBL (SPR 526) provides read-only access
to the 64-bit alternate time base counter, which is incremented at an implementation-defined
frequency. ATB registers are accessible in both user and supervisor mode.
Like the TB implementation, ATBL is an aliased name for ATB.
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Figure 63. Alternate time base register lower (ATBL)
SPR 526
Access: User read-only
32
63
R
ATBCL
W
Reset
All zeros
Table 50. ATBL field descriptions
Bits
Name
Description
32–63
ATBCL
Alternate time base counter lower. 
Lower 32 bits of the alternate time base counter
The ATBU register, provides read-only access to the upper 32 bits of the alternate time base
counter. It is accessible in both user and supervisor mode.
Figure 64. Alternate time base register upper (ATBU)
SPR 527
Access: User read-only
32
63
R
ATBCU
W
Reset
All zeros
Table 51. ATBU field descriptions
3.16
Bits
Name
32–63
ATBCU
Description
Alternate time base counter upper. 
Upper 32 bits of the alternate time base counter
Performance monitor registers (PMRs)
The EIS defines a set of register resources used exclusively by the performance monitor.
PMRs are similar to the SPRs defined in the Book E architecture and are accessed by
mtpmr and mfpmr, which are also defined by the EIS. Table 52 lists supervisor-level PMRs.
User-level software that attempts to read or write supervisor-level PMRs causes a privilege
exception.
Table 52. Performance monitor registers—supervisor level
Abbreviation
Register name
PMR
number
PMGC0
Performance monitor global control register 0
400
124/1025
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pmr[0–4] pmr[5–9]
01100
10000
Section/page
Section 3.16.1
on page 126
RM0004
Register model
Table 52. Performance monitor registers—supervisor level (continued)
Abbreviation
PMR
number
Register name
pmr[0–4] pmr[5–9]
PMLCa0
Performance monitor local control a0
144
00100
10000
PMLCa1
Performance monitor local control a1
145
00100
10001
PMLCa2
Performance monitor local control a2
146
00100
10010
PMLCa3
Performance monitor local control a3
147
00100
10011
PMLCb0
Performance monitor local control b0
272
01000
10000
PMLCb1
Performance monitor local control b1
273
01000
10001
PMLCb2
Performance monitor local control b2
274
01000
10010
PMLCb3
Performance monitor local control b3
275
01000
10011
PMC0
Performance monitor counter 0
16
00000
10000
PMC1
Performance monitor counter 1
17
00000
10001
PMC2
Performance monitor counter 2
18
00000
10010
PMC3
Performance monitor counter 3
19
00000
10011
Section/page
Section 3.16.3
on page 127
Section 3.16.5
on page 128
Section 3.16.7
on page 130
User-level PMRs in Table 53 are read-only and are accessed with mfpmr. Attempting to
write user-level registers in supervisor or user mode causes an illegal instruction exception.
Table 53. Performance monitor registers—user level (read-only)
Abbreviation
PMR
number
Register name
pmr[0–4] pmr[5–9]
UPMGC0
User performance monitor global control
register 0
384
01100
00000
UPMLCa0
User performance monitor local control a0
128
00100
00000
UPMLCa1
User performance monitor local control a1
129
00100
00001
UPMLCa2
User performance monitor local control a2
130
00100
00010
UPMLCa3
User performance monitor local control a3
131
00100
00011
UPMLCb0
User performance monitor local control b0
256
01000
00000
UPMLCb1
User performance monitor local control b1
257
01000
00001
UPMLCb2
User performance monitor local control b2
258
01000
00010
UPMLCb3
User performance monitor local control b3
259
01000
00011
UPMC0
User performance monitor counter 0
0
00000
00000
UPMC1
User performance monitor counter 1
1
00000
00001
UPMC2
User performance monitor counter 2
2
00000
00010
UPMC3
User performance monitor counter 3
3
00000
00011
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Section 3.16.3
on page 127
Section 3.16.4
on page 128
Section 3.16.6
on page 130
Section 3.16.7
on page 130
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3.16.1
RM0004
Global control register 0 (PMGC0)
The performance monitor global control register (PMGC0), controls all performance monitor
counters.
3.16.1.1
Performance monitor global control register 0 (PMGC0)/
User performance monitor global control register 0 (UPMGC0)
Figure 65. Global control register 0 (PMGC0)
PMR PMGC0 (PMR400)
UPMGC0 (PMR384)
32
33
34
Access: PMGC0: supervisor-only
UPMGC0: supervisor/user read-only
35
50 51 52 53 54
55
56
63
R
FAC PMIE FCECE
—
TBSEL
—
TBEE
—
W
Reset
All zeros
PMGC0 is cleared by a hard reset. Reading this register does not change its contents.
Table 54. PMGC0 field descriptions
Bits
32
33
34
35–50
51–52
126/1025
Name
Description
FAC
Freeze all counters. When FAC is set by hardware or software, PMLCx[FC]
maintains its current value until it is changed by software.
0 The PMCs are incremented (if permitted by other PM control bits).
1 The PMCs are not incremented.
PMIE
Performance monitor interrupt enable
0 Performance monitor interrupts are disabled.
1 Performance monitor interrupts are enabled and occur when an enabled
condition or event occurs.
Freeze counters on enabled condition or event
0 The PMCs can be incremented (if permitted by other PM control bits).
FCECE 1 The PMCs can be incremented (if permitted by other PM control bits) only until
an enabled condition or event occurs. When an enabled condition or event
occurs, PMGC0[FAC] is set. It is up to software to clear FAC.
—
TBSEL
Reserved, should be cleared.
Time base selector. Selects the time base bit that can cause a time base
transition event (the event occurs when the selected bit changes from 0 to 1).
00 TB[63] (TBL[31])
01 TB[55] (TBL[23])
10 TB[51] (TBL[19])
11 TB[47] (TBL[15])
Time base transition events can be used to periodically collect information about
processor activity. In multiprocessor systems in which TB registers are
synchronized among processors, time base transition events can be used to
correlate the performance monitor data obtained by the several processors. For
this use, software must specify the same TBSEL value for all processors in the
system. Because the time-base frequency is implementation-dependent,
software should invoke a system service program to obtain the frequency before
choosing a value for TBSEL.
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Register model
Table 54. PMGC0 field descriptions (continued)
3.16.2
Bits
Name
53–54
—
55
TBEE
55–63
—
Description
Reserved, should be cleared.
Time base transition event exception enable
0 Exceptions from time base transition events are disabled.
1 Exceptions from time base transition events are enabled. A time base transition
is signalled to the performance monitor if the TB bit specified in
PMGC0[TBSEL] changes from 0 to 1. Time base transition events can be used
to freeze the counters (PMGC0[FCECE]) or signal an exception
(PMGC0[PMIE]).
Changing PMGC0[TBSEL] while PMGC0[TBEE] is enabled may cause a false 0
to 1 transition that signals the specified action (freeze, exception) to occur
immediately. Although the interrupt signal condition may occur with MSR[EE] = 0,
the interrupt cannot be taken until MSR[EE] = 1.
Reserved, should be cleared.
User global control register 0 (UPMGC0)
The contents of PMGC0 are reflected to UPMGC0, which is read by user-level software.
UPMGC0 is read with the mfpmr instruction using PMR384.
3.16.3
Local control A registers (PMLCa0–PMLCa3)
The local control A registers 0–3 (PMLCa0–PMLCa3), function as event selectors and give
local control for the corresponding performance monitor counters. PMLCa works with the
corresponding PMLCb register.
3.16.3.1
Local control A registers (PMLCa0–PMLCa3)/
User local control A registers (UPMLCa0–UPMLCa3)
Figure 66. Local control A registers (PMLCa0–PMLCa3)
PMLCa0 (PMR144)
PMLCa1 (PMR145)
PMLCa2 (PMR146)
PMLCa3 (PMR147)
32 33
34
35
UPMLCa0 (PMR128)
UPMLCa1 (PMR129)
UPMLCa2 (PMR130)
UPMLCa3 (PMR131)
36
37 38
Access: PMLCa0–PMLCa3: supervisor-only
UPMLCa0–UPMLCa3: supervisor/user read-only
40 41
47 48
63
R
FC FCS FCU FCM1 FCM0 CE
—
EVENT
—
W
Reset
All zeros
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Table 55. PMLCa0–PMLCa3 field descriptions
3.16.4
Bits
Name
Description
32
FC
Freeze counter
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented.
33
FCS
Freeze counter in supervisor state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 0.
34
FCU
Freeze counter in user state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 1.
35
FCM1
Freeze counter while mark = 1
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 1.
36
FCM0
Freeze counter while mark = 0
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 0.
37
CE
Condition enable
0 PMCx overflow conditions cannot occur. (PMCx cannot cause interrupts,
cannot freeze counters.)
1 Overflow conditions occur when the most-significant-bit of PMCx is equal to
one.
It is recommended that CE be cleared when counter PMCx is selected for
chaining.
38–40
—
Reserved, should be cleared.
41–47
EVENT
48–63
—
Event selector. Up to 128 events selectable.
Reserved, should be cleared.
User local control A registers (UPMLCa0–UPMLCa3)
The contents of PMLCa0–PMLCa3 are reflected to UPMLCa0–UPMLCa3, which are read
by user-level software with mfpmr using PMR numbers in Table 53.
3.16.5
Local control B registers (PMLCb0–PMLCb3)
Local control B registers (PMLCb0–PMLCb3), specify a threshold value and a multiple to
apply to a threshold event selected for the corresponding performance monitor counter.
PMLCb works with the corresponding PMLCa.
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3.16.5.1
Register model
Local control B registers (PMLCb0–PMLCb3)/User local control B registers
(UPMLCb0–UPMLCb3)
Figure 67. Local control B registers (PMLCb0–PMLCb3)
PMR PMR272 (PMLCb0)
PMR273 (PMLCb1)
PMR274 (PMLCb2)
PMR275 (PMLCb3)
PMR256 (UPMLCb0)
PMR257 (UPMLCb1)
PMR258 (UPMLCb2)
PMR259 (UPMLCb3)
Access: PMLCb0–PMLCb3 Supervisor read/write
UPMLCb0–UPMLCb3 User read-only
32
52 53
R
THRESHMU
L
—
W
Reset
55 56 57 58
—
63
THRESHOLD
All zeros
Table 56. PMLCb0 –PMLCb3 field descriptions
Bits
Name
32–52
—
53–55
56–57
58–63
Description
Reserved, should be cleared.
Threshold multiple
000 Threshold field is multiplied by 1 (PMLCbn[THRESHOLD] * 1)
001 Threshold field is multiplied by 2 (PMLCbn[THRESHOLD] * 2)
010 Threshold field is multiplied by 4 (PMLCbn[THRESHOLD] * 4)
THRESHMUL 011 Threshold field is multiplied by 8 (PMLCbn[THRESHOLD] * 8)
100 Threshold field is multiplied by 16 (PMLCbn[THRESHOLD] * 16)
101 Threshold field is multiplied by 32 (PMLCbn[THRESHOLD] * 32)
110 Threshold field is multiplied by 64 (PMLCbn[THRESHOLD] * 64)
111 Threshold field is multiplied by 128 (PMLCbn[THRESHOLD] * 128)
—
Reserved, should be cleared.
Threshold. Only events that exceed this value are counted. Events to which
a threshold value applies are implementation-dependent as are the
dimension (for example duration in cycles) and the granularity with which
the threshold value is interpreted.
THRESHOLD By varying the threshold value, software can profile event characteristics.
For example, if PMC1 is configured to count cache misses that last longer
than the threshold value, software can obtain the distribution of cache miss
durations for a given program by monitoring the program repeatedly using
a different threshold value each time.
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3.16.6
RM0004
User local control B registers (UPMLCb0–UPMLCb3)
The contents of PMLCb0–PMLCb3 are reflected to UPMLCb0–UPMLCb3, which are read
by user-level software with mfpmr using the PMR numbers in Table 53.
3.16.7
Performance monitor counter registers (PMC0–PMC3)
The performance monitor counter registers PMC0–PMC3, are 32-bit counters that can be
programmed to generate interrupt signals when they overflow. Each counter is enabled to
count 128 events.
3.16.7.1
Performance monitor counter registers (PMC0–PMC3)/User performance
monitor counter registers (UPMC0–UPMC3)
Figure 68. Performance monitor counter registers (PMC0–PMC3)
PMC0 (PMR16)
PMC1 (PMR17)
PMC2 (PMR18)
PMC3 (PMR19)
UPMC0 (PMR0)
UPMC1 (PMR1)
UPMC2 (PMR2)
UPMC3 (PMR3)
Access: PMC0–PMC3: Supervisor-only
UPMC0–UPMC3: Supervisor/user read-only
32 33
63
R
OV
Counter value
W
Reset
All zeros
Table 57. PMC0–PMC3 field descriptions
Bits
Name
32
OV
33–63
Counter Value
Description
Overflow. When this bit is set, it indicates this counter reaches its
maximum value.
Indicates the number of occurrences of the specified event.
Counters overflow when the high-order bit (the sign bit) becomes set; that is, they reach the
value 2,147,483,648 (0x8000_0000). However, an exception is not signaled unless
PMGC0[PMIE] and PMLCax[CE] are also set as appropriate.
The interrupts are masked by clearing MSR[EE]. An interrupt that is signaled while
MSR[EE] is zero is not taken until MSR[EE] is set. Setting PMGC0[FCECE] forces counters
to stop counting when an enabled condition or event occurs.
Software is expected to use mtpmr to explicitly set PMCs to non-overflowed values. Setting
an overflowed value may cause an erroneous exception. For example, if both
PMGC0[PMIE] and PMLCax[CE] are set and the mtpmr loads an overflowed value into
PMCx, an interrupt may be generated without an event counting having taken place.
PMC registers are accessed with mtpmr and mfpmr using the PMR numbers in Table 52.
3.16.8
User performance monitor counter registers (UPMC0–UPMC3)
The contents of PMC0–PMC3 are reflected to UPMC0–UPMC3, which are read by userlevel software with the mfpmr instruction using the PMR numbers in Table 53.
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3.17
Register model
Device control registers (DCRs)
Book E defines the existence of a DCR address space and the instructions to access them,
but does not define particular DCRs. The on-chip DCRs exist architecturally outside the
processor core and thus are not part of Book E.
DCRs may control the use of on-chip peripherals, such as memory controllers (specific DCR
definitions would be provided in the implementation’s user’s manual).
The contents of DCR DCRN can be read into a GPR using mfdcr rD,DCRN. GPR contents
can be written into DCR DCRN using mtdcr DCRN,rS.
If DCRs are implemented, they are described as part of the implementation documentation.
3.18
Book E SPR model
This section describes SPR invalid references, synchronization requirements, and
preserved, reserved, and allocated registers.
3.18.1
Invalid SPR references
System behavior when an invalid SPR is referenced depends on the privilege level.

If the invalid SPR is accessible in user mode (SPR[5] = 0), an illegal instruction
exception is taken.

If the invalid SPR is accessible only in supervisor mode (SPR[5] = 1) and the core
complex is in supervisor mode (MSR[PR] = 0), the results of the attempted access are
boundedly undefined.

If the invalid SPR address is accessible only in supervisor mode (bit 5 of an SPR
number = 1) and the core complex is not in supervisor mode (MSR[PR] = 1), a privilege
exception is taken. These results are summarized in Table 58.
Table 58. System response to an invalid spr reference
SPR address bit 5
MSR[PR]
0 (User)
x
0 (Supervisor)
Response
Illegal exception
Boundedly undefined
1 (Supervisor)
1 (User)
3.18.2
Privilege exception
Synchronization requirements for SPRs
Synchronization requirements for accessing certain SPRs are shown in Table 59. Except for
these SPRs, there are no synchronization requirements for accessing SPRs beyond those
stated in Book E. (Note that requirements may be different for different implementations.)
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Table 59. Synchronization requirements for sprs
3.18.3
Registers
Instruction
Instruction required
before
Instruction required
after
DBCR0
mtspr dbcr0
None
isync
DBCR1
mtspr dbcr1
None
isync
HID0
mtspr hid0
None
isync
HID1
mtspr hid1
None
isync
L1CSR0
mtspr l1csr0
msync, isync
isync
L1CSR1
mtspr l1csr1
None
isync
MASn
mtspr masn
None
isync
MMUCSR0
mtspr mmucsr0
None
isync
PIDn
mtspr pidn
None
isync
SPEFSCR
mtspr spefscr
None
isync
Reserved SPRs
An undefined SPR number in the range 0x000–0x1FF (0–511) that is not preserved is
reserved.
3.18.4
Allocated SPRs
SPR numbers allocated for implementation-dependent use are 0x200–0x3FF (512–1023).
Table 60. Allocated SPRs defined by the EIS
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SPR
Mnemonic
Register
48
PID0(1)
Process ID register 0. This is not truly an allocated SPR; however, Book E
defines only this PID register and refers to it as PID rather than PID0.
512
SPEFSCR
Signal processing and embedded floating-point status and control register
515
L1CFG0
L1 cache configuration register 0
516
L1CFG1
L1 cache configuration register 1
528
IVOR32
SPE APU unavailable exception
529
IVOR33
Embedded floating-point data exception
530
IVOR34
Embedded floating-point round exception
531
IVOR35
Performance monitor Interrupt vector offset register
570
MCSRR0
Machine-check save/restore register 0
571
MCSRR1
Machine-check save/restore register 1
572
MCSR
Machine check syndrome register
573
MCAR
Machine check address register
624
MAS0
MMU assist register 0
625
MAS1
MMU assist register 1
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Register model
Table 60. Allocated SPRs defined by the EIS (continued)
SPR
Mnemonic
Register
626
MAS2
MMU assist register 2
627
MAS3
MMU assist register 3
628
MAS4
MMU assist register 4
629
MAS5
MMU assist register 5
630
MAS6
MMU assist register 6
633
PID1
Process ID register 1
634
PID2
Process ID register 2
…
PIDn
Additional PID registers may be defined in this space
688
TLB0CFG
TLB configuration register 0
689
TLB1CFG
TLB configuration register 1
944
MAS7
MMU assist register 7
1008
HID0
Hardware implementation dependent register 0
1009
HID1
Hardware implementation dependent register 1
1010
L1CSR0
L1 cache control and status register 0
1011
L1CSR1
L1 cache control and status register
1012
MMUCSR0
MMU control and status register 0
1015
MMUCFG
MMU configuration register
1023
SVR
System version register
1. An update to a PID register must always be followed by an isync.
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4
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Instruction model
The architecture specifications allow for different processor implementations, which may
provide extensions to or deviations from the architectural descriptions. This chapter
provides information about the Book E architecture and the Book E implementation
standards (EIS), which defines auxiliary processing units (APUs) and other architectural
extensions that define additional instructions, registers, and interrupts. 
For more information, see Chapter 8: Auxiliary processing units (APUs).
4.1
Operand conventions
This section describes operand conventions as they are represented in the Book E
architecture. These conventions follow the basic descriptions in the classic PowerPC
architecture with some changes in terminology. For example, distinctions between user and
supervisor-level instructions are maintained, but the designations—UISA, VEA, and OEA—
do not apply. Detailed descriptions are provided of conventions used for storing values in
registers and memory, accessing processor registers, and representing data in these
registers.
4.1.1
Data organization in memory and data transfers
Bytes in memory are numbered consecutively starting with 0. Each number is the address of
the corresponding byte.
Memory operands can be bytes, half words, words, or double words or, for the load/store
multiple instruction type and load/store string instructions, a sequence of bytes or words.
The address of a memory operand is the address of its first byte (that is, of its lowestnumbered byte). Operand length is implicit for each instruction.
4.1.2
Alignment and misaligned accesses
The operand of a single-register memory access instruction has an alignment boundary
equal to its length. An operand’s address is misaligned if it is not a multiple of its width.
The concept of alignment is also applied more generally to data in memory. For example, a
12-byte data item is said to be word-aligned if its address is a multiple of four.
Some instructions require their memory operands to have certain alignment. In addition,
alignment can affect performance. For single-register memory access instructions, the best
performance is obtained when memory operands are aligned.
Instructions are 32 bits (one word) long and must be word-aligned. Note, however, that the
VLE extension provides both 16- and 32-bit instructions. 
See Section 4.6.6.10: VLE instruction alignment and byte ordering.
Table 61 lists characteristics for memory operands for single-register memory access
instructions.
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Table 61. Address characteristics of aligned operands
Operand
Operand Length
Addr[60–63] if Aligned
Byte (or string)
8 bits
xxxx(1)
Half word
2 bytes
xxx0
Word
4 bytes
xx00
Double word
8 bytes
x000
1. An x in an address bit position indicates that the bit can be 0 or 1 independent of the state of other bits in the address.
Note that lmw, stmw, lwarx, and stwcx. instructions that are not word aligned cause an
alignment exception.
4.2
Instruction set summary
Instructions are divided into the following functional categories:
Note:

Integer instructions—These include arithmetic and logical instructions. See
Section 4.3.1.1: Integer instructions.

Floating-point instructions—These include floating-point vector and scalar arithmetic
instructions. See Section 4.6.1.2: Embedded vector and scalar floating-point APU
instructions. Note that some implementations do not support Book E–defined floatingpoint instructions or registers.

Load and store instructions—See Section 4.3.1.8: Load and store instructions.

Flow control instructions—These include branching instructions, CR logical
instructions, trap instructions, and other instructions that affect the instruction flow. 
See Section 4.3.1.11: Branch and flow control instructions.

Processor control instructions—These instructions are used for synchronizing memory
accesses. See Section 4.6.6.1: Processor control instructions.

Memory synchronization instructions—These instructions are used for memory
synchronizing. See Section 4.3.1.15: Memory synchronization instructions.

Memory control instructions—These instructions provide control of caches and TLBs.
See Section 4.3.1.17: Memory control instructions, and Section 4.3.2.2: Supervisorlevel memory control instructions.

Signal processing instructions—These include a set of vector arithmetic and logic
instructions optimized for signal processing. See Section 4.6.1: SPE and embedded
floating-point APUs.
Instruction groupings used here do not indicate the execution unit that processes a
particular instruction or group of instructions. This information, which is useful for scheduling
instructions most effectively, is provided in the execution chapter for the implementation.”
Integer instructions operate on word operands. Book E floating-point instructions operate on
single-precision and double-precision floating-point operands. The PowerPC architecture
uses instructions that are 4 bytes long and word-aligned. It provides for byte, half-word, and
word operand loads and stores between memory and a set of 32 general-purpose registers
(GPRs). It provides for word and double-word operand loads and stores between memory
and a set of 32 floating-point registers (FPRs).
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Arithmetic and logical instructions do not read or modify memory. To use the contents of a
memory location in a computation and then modify the same or another location, the
memory contents must be loaded into a register, modified, and then written to the target
location using load and store instructions.
The description of each instruction includes the mnemonic and a formatted list of operands.
To simplify assembly language programming, a set of simplified mnemonics and symbols is
provided for some of the frequently used instructions; see Appendix B: Simplified
mnemonics for PowerPC instructions, for a complete list of simplified mnemonics. Programs
written to be portable across the various assemblers for the PowerPC architecture should
not assume the existence of mnemonics not described in that document.
4.2.1
Classes of instructions
Instructions belong to one of the following four classes:

Defined instructions (See Section 4.2.1.2: Defined instruction class)

Allocated instructions (See Section 4.2.1.3: Allocated instruction class)

Preserved instructions (See Section 4.2.1.4: Preserved instruction class)

Reserved (illegal or no-op) instructions (See Section 4.2.1.5: Reserved instruction
class)
The class is determined by examining the primary opcode and any extended opcode. If the
opcode, or combination of opcode and extended opcode, is not that of a defined, allocated,
preserved, or reserved instruction, the instruction is illegal.
4.2.1.1
Definition of boundedly undefined
If instructions are encoded with incorrectly set bits in reserved fields, the results on
execution can be said to be boundedly undefined. If a user-level program executes the
incorrectly coded instruction, the resulting undefined results are bounded in that a spurious
change from user to supervisor state is not allowed, and the level of privilege exercised by
the program in relation to memory access and other system resources cannot be exceeded.
Boundedly undefined results for a given instruction can vary between implementations and
between execution attempts in the same implementation.
4.2.1.2
Defined instruction class
This class of instructions consists of all the instructions defined in Book E. In general,
defined instructions are guaranteed to be supported within a Book E system as specified by
the architecture, either within the processor implementation itself or within emulation
software supported by the system operating software.
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For implementations that only provide the 32-bit subset of Book E, emulation of the 64-bit
behavior of the defined instructions is not supported. See Appendix D: Guidelines for 32-bit
book E.
Any attempt to execute a defined instruction results in one of the following events:

An illegal instruction exception-type program interrupt, if an implementation does not
recognize the instruction

An unimplemented instruction exception-type program interrupt, if the instruction is
recognized but not supported by the implementation and is not a floating-point
instruction

An unimplemented instruction exception-type program interrupt, if the instruction is
recognized but not supported by the implementation, and is a floating-point instruction
and floating-point processing is enabled

The floating-point unavailable interrupt if the instruction is recognized but is not
supported by the implementation or is a floating-point instruction and floating-point
processing is disabled

The floating-point unavailable interrupt when floating-point processing is disabled and
a floating-point instruction is recognized and is not supported by the implementation

If an instruction is recognized and supported by the implementation, the processor
performs the actions described in the rest of this document. The architected behavior
may cause other exceptions.
A defined instruction may be retained by future versions of Book E as a defined instruction,
or may be reclassified as a preserved instruction (process of removal from the architecture)
and eventually classified as reserved-illegal.
4.2.1.3
Allocated instruction class
This class of instructions contains the set of instructions (a set of primary opcodes, as well
as a set of extended opcodes for certain primary opcodes) used for implementation-specific
instructions. Table 62 lists blocks of opcodes allocated for implementation-dependent use.
.
Table 62. Allocated instructions
Primary opcode
Extended opcodes
0
All instruction encodings (bits 6–31) except 0x0000_0000(1).
4
All instruction encodings (bits 6–31)
SPE and embedded floating-point instructions
19
Extended opcodes (bits 21–30) 0buuuuu_0u11u
31
Extended opcodes (bits 21–30) uuuuu_0u11u
59
Extended opcodes (bits 21–30) uuuuu_0u10u
63
Extended opcodes (bits 21–30) uuuuu_0u10u (except 00000_01100 frsp)
1. Instruction encoding 0x0000_0000 is and always will be reserved-illegal.
Allocated instructions are allocated to purposes that are outside the scope of Book E for
implementation-dependent and application-specific use.
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Any attempt to execute an allocated instruction results in one of the following:

An illegal instruction exception-type program interrupt, if the instruction is not
recognized by the implementation

An unimplemented instruction exception-type program interrupt, if the instruction is
recognized and enabled for execution but the implementation does not support direct
execution of the instruction. This option may be used to allow emulation for
unsupported allocated instructions.

A floating-point unavailable interrupt, if an allocated instruction that extends the
floating-point capabilities is recognized and floating-point processing is disabled

If an allocated instruction is implemented, the processor performs the actions
described in the user’s manual. Implementation-dependent behavior may cause other
exceptions.
An allocated instruction is guaranteed by Book E to remain allocated.
Note:
Some allocated instructions may have associated new process state, and, therefore, may
provide an associated enable bit, similar in function to MSR[FP] for floating-point
instructions. For such instructions, being enabled for execution implies that any associated
enable bit is set to allow, or enable, instruction execution. For such instructions, the
architecture provides an auxiliary processor unavailable interrupt vector in case execution of
such an instruction is attempted when execution is disabled.
For example, MSR[SPE] enables the SPE unavailable interrupt. Other allocated instructions
may not have any associated new state and therefore may not require an associated enable
bit. If supported by an implementation, such instructions are assumed to be always enabled
for execution.
4.2.1.4
Preserved instruction class
The preserved instruction class supports backward compatibility with the PowerPC
architecture. An attempt to execute a preserved instruction results in one of the following:

If the implementation does not recognize the instruction, an illegal instruction
exception-type program interrupt occurs.

If the instruction is recognized and supported by the implementation, the processor
performs the actions defined in the previous version of the architecture.
Future versions of Book E may retain a preserved instruction as a preserved instruction,
may reclassify it as an allocated instruction, or may adopt it as part of Book E.
Preserved opcodes are listed in Table 63.
Table 63. Preserved instructions
Primary opcode
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0
No preserved extended opcodes
4
No preserved extended opcodes
19
No preserved extended opcodes
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Table 63. Preserved instructions (continued)
Primary opcode
4.2.1.5
Extended opcodes
31
Extended opcodes (bits 21–30)
210
0b00110_10010 (mtsr)
242
0b00111_10010 (mtsrin)
370
0b01011_10010 (tlbia)
306
0b01001_10010 (tlbie)
371
0b01011_10011 (mftb)
595
0b10010_10011 (mfsr)
659
0b10100_10011 (mfsrin)
310
0b01001_10110 (eciwx)
438
0b01101_10110 (ecowx)
59
No preserved extended opcodes
63
No preserved extended opcodes
Reserved instruction class
This class of instructions consists of all instruction primary opcodes (and associated
extended opcodes, if applicable) that do not belong to either the defined, allocated, or
preserved instruction classes.
Reserved instructions are available for future extensions of Book E. That is, some future
version of Book E may define any of these instructions to perform new functions or make
them available for implementation-dependent use as allocated instructions. There are two
types of reserved instructions, reserved-illegal and reserved-nop.
Attempts to execute a reserved-illegal instruction cause an illegal instruction exception-type
program interrupt (see Section 5.7.6: Alignment interrupt) on implementations conforming to
the current version of Book E. Reserved-illegal instructions are, therefore, available for
future extensions to Book E that would affect architected state. Such extensions might
include new forms of integer or floating-point arithmetic or new forms of load or store
instructions that write their result in an architected register.
Attempts to execute a reserved-nop instruction either do not affect implementations
conforming to the current version of Book E (that is, treated as a no-operation instruction),
or cause an illegal instruction exception-type program interrupt (see Section 5.7.7: Program
interrupt). Reserved-nop instructions are available for future architecture extensions that do
not affect architected state. Such extensions might include performance-enhancing hints
such as new forms of cache touch instructions and could be added while remaining
functionally compatible with implementations of previous versions of Book E
A reserved-illegal instruction may be retained by future versions of Book E as a reservedillegal instruction, may be subsequently reclassified as an allocated instruction, or may even
be employed in the role of a subsequently defined instruction.
A reserved-nop instruction may be retained by future versions of Book E as a reserved-nop
instruction, may be subsequently reclassified as an allocated instruction, or may even be
employed in the role of a subsequently defined instruction that has no effect on architected
state.
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Instruction forms
This section describes preferred instruction forms, addressing modes, and synchronization.
4.2.2.1
Preferred instruction forms (no-op)
The Or Immediate (ori) instruction has the following preferred form for expressing a no-op:
ori 0,0,0
4.2.2.2
Invalid instruction forms
Some of the defined instructions have invalid forms. An instruction form is invalid if one or
more fields of the instruction, excluding the opcode field(s), are coded incorrectly in a
manner that can be deduced by examining only the instruction encoding.
Attempts to execute an invalid form of an instruction either causes an illegal instruction type
program interrupt or yields boundedly undefined results. Any exceptions to this rule are
stated in the instruction descriptions.
Some kinds of invalid form instructions can be deduced just from examining the instruction
layout. These are listed below.

Field shown as reserved but coded as nonzero

Field shown as containing a particular value but coded as some other value
These invalid forms are not discussed further.
Other invalid instruction forms can be deduced by detecting an invalid encoding of one or
more of the instruction operand fields. These kinds of invalid form are identified in the
instruction descriptions.
4.2.3

Branch conditional and branch conditional extended instructions (undefined encoding
of BO field)

Load with update instructions (rD = rA or rA = 0)

Store with update instructions (rA = 0)

Load multiple instruction (rA or rB in range of registers to be loaded)

Load string immediate instructions (rA in range of registers to be loaded)

Load string indexed instructions (rD = rA or rD = rB)

Load/store floating-point with update instructions (rA = 0)
Addressing modes
This section describes conventions for addressing memory and for calculating effective
addresses (EAs) as defined by the Book E architecture for 32-bit implementations.
4.2.3.1
Memory addressing
A program references memory using the effective address computed by the processor when
it executes a memory access or branch instruction (or other instructions as described in
Section 4.3.1.18: User-level cache instructions, and Section 4.3.2.3: Supervisor-level cache
instruction, or when it fetches the next sequential instruction.
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Memory operands
Bytes in memory are numbered consecutively starting with 0. Each number is the address of
the corresponding byte.
Memory operands may be bytes, half words, words or, for the load/store multiple and
load/store string instructions, a sequence of words or bytes. The address of a memory
operand is the address of its first byte (that is, of its lowest-numbered byte). Byte ordering
can be either big endian or little endian (see Section 4.2.3.4: Byte ordering). The default
byte and bit ordering is big endian.
Operand length is implicit for each instruction with respect to memory alignment. The
operand of a scalar memory access instruction has a natural alignment boundary equal to
the operand length. In other words, the natural address of an operand is an integral multiple
of the operand length. A memory operand is said to be aligned if it is aligned at its natural
boundary; otherwise it is said to be misaligned. For more information about alignment, see
Section 4.1.2: Alignment and misaligned accesses.
4.2.3.3
Effective address calculation
The 32-bit address computed by the processor when executing a memory access or branch
instruction (or certain other instructions described in Section 4.3.1.18: User-level cache
instructions, Section 4.3.2.3: Supervisor-level cache instruction, and Section 4.3.2.4:
Supervisor-level tlb management instructions), or when fetching the next sequential
instruction, is called the effective address (EA) and specifies a byte in memory. For a
memory access instruction, if the sum of the EA and the operand length exceeds the
maximum EA, the memory access is considered to be undefined.
Effective address arithmetic, except for next sequential instruction address computations,
wraps around from the maximum address, 232– 1, to address 0.
Data memory addressing modes
Book E supports the following data memory addressing modes:

Base+displacement addressing mode—The 16-bit D field is sign-extended and added
to the contents of the GPR designated by rA or to zero if rA = 0. Instructions that use
this addressing mode are of the D instruction format.

Base+index addressing mode—The contents of the GPR designated by rB (or the
value 0 for lswi and stswi) are added to the contents of the GPR designated by rA or
to zero if rA = 0. Instructions that use this addressing mode are of the X instruction
format.

Base+displacement extended addressing mode—The 12-bit DE field is sign-extended
and added to the contents of the GPR designated by rA or to zero if rA = 0 to produce
the 32-bit EA. Instructions that use this addressing mode are of the DE instruction
format.

Base+displacement extended scaled addressing mode—The 12-bit DES field is
concatenated on the right with zeros, sign-extended, and added to the contents of the
GPR designated by rA or to zero if rA = 0 to produce the 32-bit EA. Instructions that
use this addressing mode are of the DES instruction format.
In addition, APUs may provide additional addressing modes.
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Instruction memory addressing modes
Instruction memory addressing modes correspond with instructions forms, as follows:

I-form branch instructions—The 24-bit LI field is concatenated on the right with 0b00,
sign-extended, and then added to either the address of the branch instruction if AA = 0,
or to 0 if AA = 1.

Taken B-form branch instructions—The 14-bit BD field is concatenated on the right with
0b00, sign-extended, and then added to either the address of the branch instruction if
AA = 0, or to 0 if AA = 1.

Taken XL-form branch instructions—The contents of bits LR[32–61] or CR[32–61] are
concatenated on the right with 0b00.

Sequential instruction fetching (or non-taken branch instructions)—The value 4 is
added to the address of the current instruction to form the 32-bit EA of the next
instruction. If the address of the current instruction is 0xFFFF_FFFC, the address of the
next sequential instruction is undefined.

Any branch instruction with LK = 1—The value 4 is added to the address of the current
instruction and the 32-bit result is placed into the LR. If the address of the current
instruction is 0xFFFF_FFFC, the result placed into the LR is undefined.
Although some implementations may support next sequential instruction address
computations wrapping from the highest address 0xFFFF_FFFC to 0x0000_0000 as part of
the instruction flow, users are strongly encouraged not to depend on this behavior. Doing so
can reduce the portability of their software. If code must span this boundary, software should
place a non-linking branch at address 0xFFFF_FFFC, which always branches to address
0x0000_0000 (either absolute or relative branches work). 
See also Appendix D: Guidelines for 32-bit book E.
4.2.3.4
Byte ordering
If scalars (individual data items and instructions) were indivisible, there would be no such
concept as byte ordering. It is meaningless to consider the order of bits or groups of bits
within the smallest addressable unit of memory, because nothing can be observed about
such order. Only when scalars, which the programmer and processor regard as indivisible
quantities, can comprise more than one addressable unit of memory does the question of
order arise.
For a machine in which the smallest addressable unit of memory is the 64-bit double word,
there is no question of the ordering of bytes within double words. All transfers of individual
scalars between registers and memory are of double words, and the address of the byte
containing the high-order 8 bits of a scalar is no different from the address of a byte
containing any other part of the scalar.
For Book E, as for most computer architectures currently implemented, the smallest
addressable unit of memory is the 8-bit byte. Many scalars are half words and words
(double words in 64-bit implementations) which consist of groups of bytes. When a wordlength scalar is moved from a register to memory, the scalar occupies four consecutive byte
addresses. It thus becomes meaningful to discuss the order of the byte addresses with
respect to the value of the scalar: which byte contains the highest-order eight bits of the
scalar, which byte contains the next-highest-order 8 bits, and so on.
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Given a scalar that contains multiple bytes, the choice of byte ordering is essentially
arbitrary. There are 4! = 24 ways to specify the ordering of 4 bytes within a word but only two
of these orderings are sensible:

The ordering that assigns the lowest address to the highest-order (left-most) 8 bits of
the scalar, the next sequential address to the next-highest-order eight bits, and so on.
This ordering is called big endian because the big (most-significant) end of the scalar,
considered as a binary number, comes first in memory. The 68000 is an example of a
processor using this byte ordering.

The ordering that assigns the lowest address to the lowest-order (right-most) 8 bits of
the scalar, the next sequential address to the next-lowest-order eight bits, and so on.
This ordering is called little endian because the little (least-significant) end of the scalar,
considered as a binary number, comes first in memory. The Intel 8086 is an example of
a processor using this byte ordering.
Book E provides support for both big- and little-endian byte ordering in the form of a memory
attribute. See Section 6.4.8: Permission attributes, and Section 6.2.1: Memory/Cache
access attributes.
4.2.3.5
Synchronization requirements
This section describes synchronization requirements for special registers and TLBs.
Changing the value in certain system registers and invalidating TLB entries can have the
side effect of altering the context in which data addresses and instruction addresses are
interpreted, and in which instructions are executed. For example, changing MSR[IS] = 0 to
and MSR[IS] = 1 has the side effect of changing address space. Such effects need not
occur in program order (program order refers to the execution of instructions in the strict
order in which they occur in the program), and therefore may require explicit
synchronization by software.
An instruction that alters the context in which data addresses or instruction addresses are
interpreted, or in which instructions are executed, is called context altering. This section
covers all such context-altering instructions. The required software synchronization for each
is shown in Table 64.
The notation ‘CSI’ in the tables means any context-synchronizing instruction (such as, sc,
isync, rfci, or rfi). A context-synchronizing interrupt (that is, any interrupt except nonrecoverable machine check) can be used instead of a context-synchronizing instruction. If it
is, phrases like ‘the synchronizing instruction,’ below, should be interpreted as meaning the
instruction at which the interrupt occurs. If no software synchronization is required before
(after) a context-altering instruction, “the synchronizing instruction before (after) the contextaltering instruction” should be interpreted as meaning the context-altering instruction itself.
The synchronizing instruction before the context-altering instruction ensures that all
instructions up to and including that synchronizing instruction are fetched and executed in
the context that existed before the alteration. The synchronizing instruction after the contextaltering instruction ensures that all instructions after that synchronizing instruction are
fetched and executed in the context established by the alteration. Instructions after the first
synchronizing instruction, up to and including the second synchronizing instruction, may be
fetched or executed in either context.
If a sequence of instructions contains context-altering instructions and contains no
instructions that are affected by any of the context alterations, no software synchronization
is required within the sequence.
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Sometimes advantage can be taken of the fact that certain instructions that occur naturally
in the program, such as the rfi/rfci at the end of an interrupt handler, provide the required
synchronization.
No software synchronization is required before altering the MSR (except perhaps when
altering the WE bit: see the tables), because mtmsr is execution synchronizing. No software
synchronization is required before most of the other alterations shown in the Section :
Instruction fetch and/or execution section in Table 64, because all instructions before the
context-altering instruction are fetched and decoded before the context-altering instruction
executes (the processor must determine whether any of the preceding instructions are
context synchronizing)
Table 64 identifies the software synchronization requirements for data access for all contextaltering instructions.
Table 64. Synchronization requirements
Context altering instruction or event
Required before
Required after
Notes
Data Accesses
interrupt
None
None
mtmsr (DS)
None
CSI
mtmsr (ME)
None
CSI
mtmsr (PR)
None
CSI
mtspr (DAC1, DAC2, DVC1, DVC2)
—
—
(2)
mtspr (DBCR0, DBCR2)
—
—
(2)
mtspr (DBSR)
—
—
(2)
mtspr (PIDn)
CSI
CSI
rfci
None
None
rfi
None
None
sc
None
None
tlbivax
CSI
CSI or msync
(3),(4)
tlbwe
CSI
CSI or msync
(3),(4)
Interrupt
None
None
mtmsr (CE)
None
None
mtmsr (DE)
None
CSI
mtmsr (EE)
None
None
mtmsr (FE0)
None
CSI
mtmsr (FE1)
None
CSI
mtmsr (FP)
None
CSI
mtmsr (IS)
None
CSI
(6)
mtmsr (ME)
None
CSI
(1)
mtmsr (PR)
None
CSI
(1)
Instruction fetch and/or execution
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Table 64. Synchronization requirements (continued)
Context altering instruction or event
Required before
Required after
Notes
mtmsr (WE)
—
—
(7)
mtspr (DBCR0, DBCR1)
—
—
(2)
mtspr (DBSR)
—
—
(2)
mtspr (DEC)
None
None
(8)
mtspr (IAC1, IAC2, IAC3, IAC4)
—
—
(2)
mtspr (IVORi)
None
None
mtspr (IVPR)
None
None
mtspr (PID)
None
CSI
(6)
mtspr (TCR)
None
None
(8)
mtspr (TSR)
None
None
(8)
rfci
None
None
rfi
None
None
sc
None
None
tlbivax
None
CSI or msync
(3),(4)
tlbwe
None
CSI or msync
(3),(4)
wrtee
None
None
(5)
wrteei
None
None
(5)
1. A context synchronizing instruction is required after altering MSR[ME] to ensure that the alteration takes
effect for subsequent machine check interrupts, which may not be recoverable and therefore may not be
context synchronizing.
2. Synchronization requirements for changing any of the debug registers are implementation-dependent and
are specified in the user’s manual for the implementation.
3. For data accesses, the context synchronizing instruction before the tlbwe or tlbivax instruction ensures
that all storage accesses due to preceding instructions have completed to a point at which they have
reported all exceptions they cause.
The context synchronizing instruction after the tlbwe or tlbivax ensures that subsequent storage accesses
(data and instruction) use the updated value in any affected TLB entries. It does not ensure that all storage
accesses previously translated by the TLB entries being updated have completed with respect to storage; if
these completions must be ensured, the tlbwe or tlbivax must be followed by an msync instruction as well
as by a context synchronizing instruction. 
The following sequence shows why it is necessary for data accesses to ensure that all storage accesses
due to instructions before a tlbwe or tlbivax have completed to a point at which they have reported all
exceptions they will cause. Assume that valid TLB entries exist for the target storage location when the
sequence starts. 
1. A program issues a load or store to a page. 
2. The same program executes a tlbwe or tlbivax that invalidates the corresponding TLB entry. 
3. The load or store instruction finally executes, and gets a TLB miss exception. The TLB miss exception is
semantically incorrect. In order to prevent it, a context synchronizing instruction must be executed between
steps 1 and 2.
4. Multiprocessor systems have other requirements to synchronize what is called TLB shoot down’ (that is, to
invalidate one or more TLB entries on all processors in the multiprocessor system and to be able to
determine that the invalidations have completed and that all side effects of the invalidations have taken
effect).
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5. The effect of changing MSR[EE] or MSR[CE] is immediate.
If an mtmsr, wrtee, or wrteei clears MSR[EE], an external input, decrementer, or fixed-interval timer
interrupt does not occur after the instruction executes.
If an mtmsr, wrtee, or wrteei changes MSR[EE] from 0 to 1 when an external input, decrementer, fixedinterval timer, or higher priority enabled exception exists, the corresponding interrupt occurs immediately
after the mtmsr, wrtee, or wrteei executes and before the next instruction is executed in the program that
sets MSR[EE].
If an mtmsr clears MSR[CE], a critical input, or watchdog timer interrupt does not occur after the instruction
is executed. 
If an mtmsr changes MSR[CE] from 0 to 1 when a critical input, watchdog timer, or higher priority enabled
exception exists, the corresponding interrupt occurs immediately after mtmsr executes, and before the next
instruction is executed in the program that set MSR[CE].
6. The alteration must not cause an implicit branch in real address space. Thus the real address of the
context-altering instruction and of each subsequent instruction, up to and including the next context
synchronizing instruction, must be independent of whether the alteration has taken effect.
7. Synchronization requirements for changing the wait state enable are implementation-dependent, and are
specified in the user’s manual for the implementation.
8. The elapsed time between the decrementer reaching zero, or the transition of the selected time base bit for
the fixed-interval timer or the watchdog timer, and the signalling of the decrementer, fixed-interval timer or
the watchdog timer exception is not defined.
4.2.3.6
Context synchronization
An instruction or event is context synchronizing if it satisfies the requirements listed below.
Context-synchronizing operations include instructions isync, sc, rfi, rfci, rfdi, and rfmci,
and most interrupts.
1.
The operation is not initiated or, in the case of isync, does not complete until all
instructions already in execution have completed to a point at which they have reported
all exceptions they cause.
2.
The instructions that precede the operation complete execution in the context
(including such parameters as privilege level, address space, and memory protection)
in which they were initiated.
3.
If the operation directly causes an interrupt (for example, sc directly causes a system
call interrupt) or is an interrupt, the operation is not initiated until no interrupt-causing
exception exists having higher priority than the exception associated with the interrupt.
See Section 5.11: Exception priorities.
4.
The instructions that follow the operation are fetched and executed in the context
established by the operation as required by the sequential execution model. (This
requirement dictates that any prefetched instructions be discarded and that any effects
and side effects of executing them speculatively may also be discarded, except as
described in Section 6.2.2.1: Memory access ordering.
A context-synchronizing operation is necessarily execution synchronizing. Unlike msync
and mbar, such operations do not affect the order of memory accesses with respect to other
mechanisms.
4.2.3.7
Execution synchronization
An instruction is execution synchronizing if it satisfies items (1) and (2) of the definition of
context synchronization .msync is treated like isync with respect to item (1) (that is, the
conditions described in item (1) apply to completion of msync). Execution synchronizing
instructions include msync, mtmsr, wrtee, and wrteei. All context-synchronizing
instructions are execution synchronizing.
Unlike a context-synchronizing operation, an execution synchronizing instruction need not
ensure that the instructions following it execute in the context established by that execution
synchronizing instruction. This new context becomes effective sometime after the execution
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synchronizing instruction completes and before or at a subsequent context-synchronizing
operation.
Instruction-related interrupts
Interrupts are caused either directly by the execution of an instruction or by an
asynchronous event. In either case, an exception may cause one of several types of
interrupts to be invoked.
Examples of interrupts that can be caused directly by the execution of an instruction include
but are not limited to the following:

An attempt to execute a reserved-illegal instruction (illegal instruction exception-type
program interrupt)

An attempt by an application program to execute a privileged instruction (privileged
instruction exception-type program interrupt)

An attempt by an application program to access a privileged SPR (privileged instruction
exception-type program interrupt)

An attempt by an application program to access an SPR that does not exist
(unimplemented operation instruction exception-type program interrupt)

An attempt by a system program to access an SPR that does not exist (boundedly
undefined)

Execution of a defined instruction using an invalid form (illegal instruction exceptiontype program interrupt, unimplemented operation exception-type program interrupt, or
privileged instruction exception-type program interrupt)

An attempt to access a memory location that is either unavailable (instruction TLB error
interrupt or data TLB error interrupt) or not permitted (instruction storage interrupt or
data storage interrupt)

An attempt to access memory with an EA alignment not supported by the
implementation (alignment interrupt)

Execution of a system call instruction (system call interrupt)

Execution of a trap instruction whose trap condition is met (trap type program interrupt)

Execution of a floating-point instruction when floating-point instructions are unavailable
(floating-point unavailable interrupt)

Execution of a floating-point instruction that causes a floating-point enabled exception
to exist (floating-point enabled exception-type program interrupt)

Execution of a defined instruction that is not implemented by the implementation (illegal
instruction exception or unimplemented operation exception-type program interrupt)

Execution of an allocated instruction that is not implemented by the implementation
(illegal instruction exception or unimplemented operation exception-type program
interrupt)

Execution of an allocated instruction when the auxiliary instruction is unavailable
(auxiliary processor unavailable interrupt).

Execution of an allocated instruction that causes an auxiliary enabled exception
(enabled exception-type program interrupt).
APUs, such as the SPE, may define additional instruction-caused exceptions and interrupts.
The invocation of an interrupt is precise, except that if one of the imprecise modes for
invoking the floating-point enabled exception-type program interrupt is in effect the
invocation of the floating-point enabled exception-type program interrupt may be imprecise.
When the interrupt is invoked imprecisely, the excepting instruction does not appear to
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complete before the next instruction starts (because one of the effects of the excepting
instruction, namely the invocation of the interrupt, has not yet occurred).
Chapter 5: Interrupts and exceptions describes interrupt conditions in detail.
4.3
Instruction set overview
This section provides a brief overview of the Book E and Book E instructions.
Note:
4.3.1
Some instructions have the following optional features:
•
CR update—The dot (.) suffix on the mnemonic enables the update of the CR.
•
Overflow option—The o suffix indicates that the overflow bit in the XER is enabled.
Book E user-level instructions
This section discusses the user-level instructions defined in the Book E architecture.
4.3.1.1
Integer instructions
This section describes the integer instructions. These consist of the following:

Integer arithmetic instructions

Integer compare instructions

Integer logical instructions

Integer rotate and shift instructions
Integer instructions use the content of the GPRs as source operands and place results into
GPRs and the XER and CR fields.
4.3.1.2
Integer arithmetic instructions
Table 65 lists the integer arithmetic instructions for the PowerPC processors.
Table 65. Integer arithmetic instructions
Name
Mnemonic
Syntax
add (add. addo addo.)
rD,rA,rB
Add carrying
addc (addc. addco addco.)
rD,rA,rB
Add extended
adde (adde. addeo addeo.)
rD,rA,rB
Add immediate
addi
rD,rA,SIMM
Add immediate carrying
addic
rD,rA,SIMM
Add immediate carrying and record
addic.
rD,rA,SIMM
Add immediate shifted
addis
rD,rA,SIMM
addme (addme. addmeo addmeo.)
rD,rA
addze (addze. addzeo addzeo.)
rD,rA
divw (divw. divwo divwo.)
rD,rA,rB
divwu divwu. divwuo divwuo.
rD,rA,rB
mulhw (mulhw.)
rD,rA,rB
Add
Add to minus one extended
Add to zero extended
Divide word
Divide word unsigned
Multiply high word
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Table 65. Integer arithmetic instructions (continued)
Name
Mnemonic
Syntax
mulhwu (mulhwu.)
rD,rA,rB
mulli
rD,rA,SIMM
mullw (mullw. mullwo mullwo.)
rD,rA,rB
neg (neg. nego nego.)
rD,rA
subf (subf. subfo subfo.)
rD,rA,rB
Subtract from carrying
subfc (subfc. subfco subfco.)
rD,rA,rB
Subtract from extended
subfe (subfe. subfeo subfeo.)
rD,rA,rB
Subtract from immediate carrying
subfic
rD,rA,SIMM
Subtract from minus one extended
subfme (subfme. subfmeo subfmeo.)
rD,rA
subfze (subfze. subfzeo subfzeo.)
rD,rA
Multiply high word unsigned
Multiply low immediate
Multiply low word
Negate
Subtract from
Subtract from zero extended
Although there is no subtract immediate instruction, its effect can be achieved by using an
addi instruction with the immediate operand negated. Simplified mnemonics are provided
that include this negation. Subtract instructions subtract the second operand (rA) from the
third operand (rB). Simplified mnemonics are provided in which the third operand is
subtracted from the second. See Appendix B: Simplified mnemonics for PowerPC
instructions, for examples.
According to Book E, an implementation that executes instructions with the overflow
exception enable bit (OE) set or that sets the carry bit (CA) can either execute these
instructions slowly or prevent execution of the subsequent instruction until the operation
completes. The summary overflow (SO) and overflow (OV) bits in the XER are set to reflect
an overflow condition of a 32-bit result only if the instruction’s OE bit is set.
4.3.1.2.1
Integer compare instructions
The integer compare instructions algebraically or logically compare the contents of register
rA with either the zero-extended value of the UIMM operand, the sign-extended value of
the SIMM operand, or the contents of rB. The comparison is signed for cmpi and cmp and
unsigned for cmpli and cmpl. Table 66 lists integer compare instructions. Note that the L bit
must be 0 for 32-bit implementations.
Table 66. Integer 32-Bit compare instructions (L = 0)
Name
Mnemonic
Syntax
Compare
cmp
crD,L,rA,rB
Compare immediate
cmpi
crD,L,rA,SIMM
Compare logical
cmpl
crD,L,rA,rB
Compare logical immediate
cmpli
crD,L,rA,UIMM
The crD operand can be omitted if the result of the comparison is to be placed in CR0.
Otherwise the target CR field must be specified in crD by using an explicit field number.
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For information on simplified mnemonics for the integer compare instructions see Appendix
B: Simplified mnemonics for PowerPC instructions.
4.3.1.2.2
Integer logical instructions
The logical instructions shown in Table 67 perform bit-parallel operations on the specified
operands. Logical instructions with the CR updating enabled (uses dot suffix) and
instructions andi. and andis. set CR field CR0 to characterize the result of the logical
operation. Logical instructions do not affect XER[SO], XER[OV], or XER[CA].
See Appendix B, for simplified mnemonic examples for integer logical operations.
Table 67. Integer logical instructions
Name
4.3.1.2.3
Mnemonic
Syntax
Implementation notes
AND
and (and.)
rA,rS,rB
—
AND Immediate
andi.
rA,rS,UIM
M
—
AND Immediate Shifted
andis.
rA,rS,UIM
M
—
AND with Complement
andc (andc.)
rA,rS,rB
—
Count Leading Zeros
Word
cntlzw (cntlzw.
rA,rS
)
—
Equivalent
eqv (eqv.)
rA,rS,rB
—
Extend Sign Byte
extsb (extsb.)
rA,rS
—
Extend Sign Half Word
extsh (extsh.)
rA,rS
—
NAND
nand (nand.)
rA,rS,rB
—
NOR
nor (nor.)
rA,rS,rB
—
OR
or (or.)
rA,rS,rB
—
OR Immediate
ori
rA,rS,UIM
M
Book E defines ori r0,r0,0 as the
preferred form for a no-op. The dispatcher
may discard this instruction and dispatch
it only to the completion queue but not to
any execution unit.
OR Immediate Shifted
oris
rA,rS,UIM
M
—
OR with Complement
orc (orc.)
rA,rS,rB
—
XOR
xor (xor.)
rA,rS,rB
—
XOR Immediate
xori
rA,rS,UIM
M
—
XOR Immediate Shifted
xoris
rA,rS,UIM
M
—
Integer rotate and shift instructions
Rotation operations are performed on data from a GPR, and the result, or a portion of the
result, is returned to a GPR. Integer rotate instructions, summarized in Table 68, rotate the
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contents of a register. The result is either inserted into the target register under control of a
mask (if a mask bit is set the associated bit of the rotated data is placed into the target
register, and if the mask bit is cleared the associated bit in the target register is unchanged)
or ANDed with a mask before being placed into the target register. Appendix B: Simplified
mnemonics for PowerPC instructions, lists simplified mnemonics that allow simpler coding
of often used functions such as clearing the left- or right-most bits of a register, left or right
justifying an arbitrary field, and simple rotates and shifts.
Table 68. Integer rotate instructions
Name
Mnemonic
Syntax
Rotate left word Immediate then AND with mask
rlwinm (rlwinm.)
rA,rS,SH,MB,ME
Rotate left word then AND with mask
rlwnm (rlwnm.)
rA,rS,rB,MB,ME
Rotate left word Immediate then mask insert
rlwimi (rlwimi.)
rA,rS,SH,MB,ME
The integer shift instructions (Table 69) perform left and right shifts. Immediate-form logical
(unsigned) shift operations are obtained by specifying masks and shift values for certain
rotate instructions. Simplified mnemonics (shown in Appendix B: Simplified mnemonics for
PowerPC instructions) are provided to simplify coding of such shifts.
Multiple-precision shifts can be programmed as shown in C.2: Multiple-precision shifts. The
integer shift instructions are summarized in Table 69.
Table 69. Integer shift instructions
Name
4.3.1.3
Mnemonic
Syntax
Shift Left Word
slw (slw.)
rA,rS,rB
Shift Right Word
srw (srw.)
rA,rS,rB
Shift Right Algebraic Word Immediate
srawi (srawi.)
rA,rS,SH
Shift Right Algebraic Word
sraw (sraw.)
rA,rS,rB
Floating-point instructions
This section describes the floating-point instructions as they are defined by Book E.
The rules followed in assigning new primary and extended opcodes.

Primary opcode 63 is used for the double-precision arithmetic instructions as well as
miscellaneous instructions (for example, FPSCR manipulation instructions). Primary
opcode 59 is used for the single-precision arithmetic instructions.

The single-precision instructions for which there is a corresponding double-precision
instruction have the same format and extended opcode as that double-precision
instruction.

In assigning new extended opcodes for primary opcode 63, the following regularities
are maintained. In addition, all new X-form instructions in primary opcode 63 have bits
21–22 = 11.
–
Bit 26 = 1 if and only if the instruction is A-form.
–
Bits 26–29 = 0b0000 if and only if the instruction is a comparison or mcrfs (if and
only if the instruction sets an explicitly designated CR field).
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
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–
Bits 26–28 = 0b001 if and only if the instruction explicitly refers to or sets the
FPSCR (that is, is an FPSCR instruction) and is not mcrfs.
–
Bits 26–30 = 0b01000 if and only if the instruction is a move register instruction, or
any other instruction that does not refer to or set the FPSCR.
In assigning extended opcodes for primary opcode 59, the following regularities have
been maintained. They are based on those rules for primary opcode 63 that apply to
the instructions having primary opcode 59. In particular, primary opcode 59 has no
FPSCR instructions, so the corresponding rule does not apply.
–
If there is a corresponding instruction with primary opcode 63, its extended
opcode is used.
–
Bit 26 = 1 if and only if the instruction is A form.
–
Bits 26–30 = 0b01000 if and only if the instruction is a move register instruction, or
any other instruction that does not refer to or set the FPSCR.
Floating-point load instructions
There are two basic forms of load instruction: single-precision and double-precision.
Because the FPRs support only floating-point double format, single-precision load floatingpoint instructions convert single-precision data to double format prior to loading the operand
into the target FPR. The conversion and loading steps are as follows.
Let WORD0:31 be the floating-point single-precision operand accessed from memory.
Normalized Operand
if WORD1:8 > 0 and WORD1:8 < 255 then
FPR(frD)0:1  WORD0:1
FPR(frD)2  WORD1
FPR(frD)3  WORD1
FPR(frD)4  WORD1
FPR(frD)5:63  WORD2:31 || 290
Denormalized Operand
if WORD1:8 = 0 and WORD9:31  0 then
sign  WORD0
exp  -126
frac0:52  0b0 || WORD9:31 || 290
normalize the operand
do while frac0 = 0
frac  frac1:52 || 0b0
exp  exp - 1
FPR(frD)0  sign
FPR(frD)1:11  exp + 1023
FPR(frD)12:63  frac1:52
Zero/Infinity/NaN
if WORD1:8 = 255 or WORD1:31 = 0 then
FPR(frD)0:1  WORD0:1
FPR(frD)2  WORD1
FPR(frD)3  WORD1
FPR(frD)4  WORD1
FPR(frD)5:63  WORD2:31 || 290
For double-precision load floating-point instructions, conversion is not required because the
data from memory is copied directly into the FPR.
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Many floating-point load instructions have an update form, in which GPR(rA) is updated with
the EA. For these forms, if rA0 and rArD, the EA is placed into GPR(rA) and the memory
element (byte, half word, word, or double word) addressed by EA is loaded into FPR(rD). If
rA=0 or rA=rD, the instruction form is invalid.
Floating-point load accesses cause a data storage interrupt if the program is not allowed to
read the location. Floating-point load memory accesses cause a data TLB error interrupt if
the program attempts to access memory that is unavailable. The floating-point load
instruction set is shown in Table 70.
Table 70. Floating-point load instruction set
Instruction
Mnemonic
Syntax
lfd
frD,D(rA)
Load Floating-Point Double with Update
lfdu
frD,D(rA)
Load Floating-Point Double Extended
lfde
frD,DES(rA)
lfdue
frD,DES(rA)
lfdx
frD,rA,rB
Load Floating-Point Double with Update Indexed
lfdux
frD,rA,rB
Load Floating-Point Double Indexed Extended
lfdxe
frD,rA,rB
Load Floating-Point Double with Update Indexed Extended
lfduxe
frD,rA,rB
lfs
frD,D(rA)
Load Floating-Point Single with Update
lfsu
frD,D(rA)
Load Floating-Point Single Extended
lfse
frD,DES(rA)
lfsue
frD,DES(rA)
lfsx
frD,rA,rB
Load Floating-Point Single with Update Indexed
lfsux
frD,rA,rB
Load Floating-Point Single Indexed Extended
lfsxe
frD,rA,rB
lfsuxe
frD,rA,rB
Load Floating-Point Double
Load Floating-Point Double with Update Extended
Load Floating-Point Double Indexed
Load Floating-Point Single
Load Floating-Point Single with Update Extended
Load Floating-Point Single Indexed
Load Floating-Point Single with Update Indexed Extended
4.3.1.3.2
Floating-point store instructions
There are three basic forms of store instruction: single-precision, double-precision, and
integer. The integer form is provided by the optional store floating-point as integer word
instruction (stfiwx), described in Chapter 7: Instruction set. Because the FPRs support only
floating-point double format for floating-point data, single-precision store floating-point
instructions convert double-precision data to single-precision format before storing the
operand. The conversion steps are as follows.
Let WORD0:31 be the word in memory written to.
No Denormalization Required (includes Zero / Infinity / NaN)
if FPR(FRS)1:11 > 896 or FPR(FRS)1:63 = 0 then
WORD0:1  FPR(FRS)0:1
WORD2:31  FPR(FRS)5:34
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Denormalization Required
if 874  FRS1:11  896 then
sign  FPR(FRS)0
exp  FPR(FRS)1:11 – 1023
frac  0b1 || FPR(FRS)12:63
denormalize operand
do while exp < –126
frac  0b0 || frac0:62
exp  exp + 1
WORD0  sign
WORD1:8  0x00
WORD9:31  frac1:23
else WORD  undefined
Note that if the value to be stored by a single-precision store floating-point instruction
exceeds the maximum number representable in single-precision format, the first case above
(no denormalization required) applies. The result stored in WORD is then a well-defined
value, but is not numerically equal to the value in the source register (that is, the result of a
single-precision load floating-point from WORD does not compare equal to the contents of
the original source register).
For double-precision store floating-point instructions and for the Store Floating-Point as
Integer Word instruction, no conversion is required, as the data from the FPR is copied
directly into memory.
Many floating-point store instructions have an update form, in which GPR(rA) is updated
with the EA. For these forms, if rA0, the EA is placed into GPR(rA).
Floating-point store accesses cause a data storage interrupt if the program is not allowed to
write to the location. Integer store accesses cause a data TLB error interrupt if the program
attempts to access memory that is unavailable. Store instructions are shown in Table 71.
Book E supports both big-endian and little-endian byte ordering.
Table 71. Floating-point store instructions
Instruction
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Syntax
Store floating-point double
stfd
frS,D(rA)
Store floating-point double with update
stfdu
frS,D(rA)
Store floating-point double extended
stfde
frS,DES(rA)
Store floating-point double with update extended
stfdue
frS,DES(rA)
Store floating-point double indexed
stfdx
frS,rA,rB
Store floating-point double with update indexed
stfdux
frS,rA,rB
Store floating-point double indexed extended
stfdxe
frS,rA,rB
Store floating-point double with update indexed extended
stfduxe
frS,rA,rB
Store floating-point as integer word indexed
stfiwx
frS,rA,rB
Store floating-point as integer word indexed extended
stfiwxe
frS,rA,rB
Store floating-point single
stfs
frS,D(rA)
Store floating-point single with update
stfsu
frS,D(rA)
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Table 71. Floating-point store instructions (continued)
Instruction
4.3.1.3.3
Mnemonic
Syntax
Store floating-point single extended
stfse
frS,DES(rA)
Store floating-point single with update extended
stfsue
frS,DES(rA)
Store floating-point single indexed
stfsx
frS,rA,rB
Store floating-point single with update indexed
stfsux
frS,rA,rB
Store floating-point single indexed extended
stfsxe
frS,rA,rB
Store floating-point single with update indexed extended
stfsuxe
frS,rA,rB
Floating-point move instructions
Described in Table 72, these instructions copy data from one FPR to another, altering the
sign bit (bit 0) as described below for fneg, fabs, and fnabs. These instructions treat NaNs
just like any other kind of value (for example, the sign bit of a NaN may be altered by fneg,
fabs, and fnabs). These instructions do not alter the FPSCR.
Table 72. Floating-point move instructions
Instruction
4.3.1.4
Mnemonic
Syntax
Floating Absolute Value
fabs[.]
frD,frB
Floating Move Register
fmr[.]
frD,frB
Floating Negative Absolute Value
fnabs[.]
frD,frB
Floating Negate
fneg[.]
frD,frB
Floating-point arithmetic instructions
The following sections describe elementary arithmetic, multiply-add, rounding/conversion,
compare, and status/control instructions.
4.3.1.4.1
Floating-point elementary arithmetic instructions
Table 73 lists mnemonics and syntax of floating-point elementary arithmetic instructions.
Table 73. Floating-point elementary arithmetic instructions
Instruction
Mnemonic
Syntax
Floating add
fadd[.]
frD,frA,frB
Floating add single
fadds[.]
frD,frA,frB
Floating divide
fdiv[.]
frD,frA,frB
Floating divide single
fdivs[.]
frD,frA,frB
Floating multiply
fmul[.]
frD,frA,frC
Floating multiply single
fmuls[.]
frD,frA,frC
fres[.]
frD,frB
frsqrte[.]
frD,frB
Floating reciprocal estimate single
Floating reciprocal square root estimate
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Table 73. Floating-point elementary arithmetic instructions (continued)
Instruction
4.3.1.4.2
Mnemonic
Syntax
Floating square root
fsqrt[.]
frD,frB
Floating square root single
fsqrts[.]
frD,frB
Floating subtract
fsub[.]
frD,frA,frB
Floating subtract single
fsubs[.]
frD,frA,frB
Floating-point multiply-add instructions
These instructions combine a multiply and an add operation without an intermediate
rounding operation. FPSCR status bits, described in Table 74 are set as follows:

Overflow, underflow, and inexact exception bits, the FR, FI, and FPRF fields are set
based on the final result of the operation, not on the result of the multiplication.

Invalid operation exception bits are set as if the multiplication and the addition were
performed using two separate instructions (fmul[s], followed by fadd[s] or fsub[s]).
That is, any of the following actions will cause appropriate exception bits to be set:
–
Multiplication of infinity by 0
–
Multiplication of anything by an SNaN
–
Addition of anything with an SNaN
Table 74. Floating-point multiply-add instructions
Instruction
4.3.1.5
Mnemonic
Instruction
Floating Multiply-Add
fmadd[.]
frD,frA,frB,frC
Floating Multiply-Add Single
fmadds[.]
frD,frA,frB,frC
Floating Multiply-Subtract
fmsub[.]
frD,frA,frB,frC
Floating Multiply-Subtract Single
fmsubs[.]
frD,frA,frB,frC
Floating Negative Multiply-Add
fnmadd[.]
frD,frA,frB,frC
Floating Negative Multiply-Add Single
fnmadds[.]
frD,frA,frB,frC
Floating Negative Multiply-Subtract
fnmsub[.]
frD,frA,frB,frC
Floating Negative Multiply-Subtract Single
fnmsubs[.]
frD,frA,frB,frC
Floating-point rounding and conversion instructions
Table 75. Floating-point rounding and conversion instructions
Instruction
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Mnemonic
Syntax
Floating Convert from Integer Double Word
fcfid
frD,frB
Floating Convert to Integer Double Word
fctid
frD,frB
Floating Convert to Integer Double word and round to Zero
fctidz
frD,frB
Floating Convert to Integer Word
fctiw[.]
frD,frB
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Table 75. Floating-point rounding and conversion instructions (continued)
Instruction
Floating Convert to Integer Word and Round to Zero
Floating Round to Single-Precision
4.3.1.6
Mnemonic
Syntax
fctiwz[.]
frD,frB
frsp[.]
frD,frB
Floating-point compare instructions
The floating-point compare instructions compare the contents of two FPRs. Comparison
ignores the sign of zero (that is, regards +0 as equal to –0). The comparison result can be
ordered or unordered. The comparison sets one bit in the designated CR field and clears the
other three. The floating-point condition code, FPSCR[FPCC], is set in the same way.
The CR field and the FPCC are set as described in Table 76.
Table 76. CR field settings
Bit
Name
Description
0
FL
(frA) < (frB)
1
FG
(frA) > (frB)
2
FE
(frA) = (frB)
3
FU
(frA) ? (frB) (unordered)
The floating-point compare and select instruction set is shown in Table 77.
Table 77. Floating-point compare and select instructions
Instruction
Mnemonic
Syntax
Floating Compare Ordered
fcmpo
crD,frA,frB
Floating Compare Unordered
fcmpu
crD,frA,frB
fsel
fsel.
frD,frA,frB,frC
frD,frA,frB,frC
Floating Select
4.3.1.7
Floating-point status and control register instructions
Every FPSCR instruction synchronizes the effects of all floating-point instructions executed
by a given processor. Executing a FPSCR instruction ensures that all floating-point
instructions previously initiated by the given processor have completed before the FPSCR
instruction is initiated, and that no subsequent floating-point instructions are initiated by the
given processor until the FPSCR instruction completes. In particular:

All exceptions caused by the previously initiated instructions are recorded in the
FPSCR before the FPSCR instruction is initiated.

All invocations of floating-point enabled exception-type program interrupt that will be
caused by the previously initiated instructions have occurred before the FPSCR
instruction is initiated.

No subsequent floating-point instruction that depends on or alters the settings of any
FPSCR bits is initiated until the FPSCR instruction has completed.
Floating-point load and floating-point store instructions (Table 78) are not affected.
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Table 78. Floating-point status and control register instructions
Instruction
Mnemonic
Syntax
mffs
mffs.
frD
frD
Move to FPSCR Bit 0
mtfsb0
mtfsb0.
crbD
crbD
Move to FPSCR Bit 1
mtfsb1
mtfsb1.
crbD
crbD
Move to FPSCR Fields
mtfsf
mtfsf.
FM,frB
FM,frB
Move to FPSCR Field Immediate
mtfsfi
mtfsfi.
crD,IMM
crD,IMM
Move from FPSCR
4.3.1.8
Load and store instructions
Load and store instructions are issued and translated in program order; however, the
accesses can occur out of order. Synchronizing instructions are provided to enforce strict
ordering. The following load and store instructions are defined:
4.3.1.8.1

Integer load instructions

Integer store instructions

Integer load and store with byte-reverse instructions

Integer load and store multiple instructions

Memory synchronization instructions

SPE APU load and store instructions for reading and writing 64-bit GPRs. Some of
these instructions are also implemented by processors that support the embedded
vector single-precision and embedded scalar double-precision floating-point APUs,
which use the extended 64-bit GPRs. See Section 4.6.1: SPE and embedded floatingpoint APUs.
Self-modifying code
When a processor modifies any memory location that can contain an instruction, software
must ensure that the instruction cache is made consistent with data memory and that the
modifications are made visible to the instruction fetching mechanism. This must be done
even if the cache is disabled or if the page is marked caching-inhibited.
The following instruction sequence can be used to accomplish this when the instructions
being modified are in memory that is memory-coherence required and one processor both
modifies the instructions and executes them. (Additional synchronization is needed when
one processor modifies instructions that another processor will execute.)
The following sequence synchronizes the instruction stream (using either dcbst or dcbf):
dcbst
msync
icbi
msync
isync
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|wait for update 
|remove (invalidate) copy in instruction cache
|ensure the ICBI invalidate is complete
|remove copy in own instruction buffer
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These operations are required because the data cache is a write-back cache. Because
instruction fetching bypasses the data cache, changes to items in the data cache cannot be
reflected in memory until the fetch operations complete. The msync after the icbi is
required to ensure that the icbi invalidation has completed in the instruction cache.
Special care must be taken to avoid coherency paradoxes in systems that implement unified
secondary caches, and designers should carefully follow the guidelines for maintaining
cache coherency discussed in the user’s manual.
Integer load and store address generation
Integer load and store operations generate EAs using register indirect with immediate index
mode, register indirect with index mode, or register indirect mode, which are described as
follows:

Register indirect with immediate index addressing for integer loads and stores.
Instructions using this addressing mode contain a signed 16-bit immediate index
(d operand), which is sign extended and added to the contents of a general-purpose
register specified in the instruction (rA operand), to generate the EA. If r0 is specified, a
value of zero is added to the immediate index (d operand) in place of the contents of
r0. The option to specify rA or 0 is shown in the instruction descriptions as (rA|0).
Figure 69 shows how an EA is generated using this mode.
Figure 69. Register indirect with immediate index addressing for integer loads/stores
0
Instruction Encoding:
56
Opcode
10 11
rD/rS
15 16
rA
0
31
d
1516
Sign Extension
31
d
Yes
0
rA=0?
+
No
32
63
0
31
GPR (rA)
Effective Address
32
63
GPR (rD/rS)

Store
Load
Memory
Interface
Register indirect with index addressing for integer loads and stores. Instructions using
this mode cause the contents of two GPRs (specified as operands rA and rB) to be
added in the EA generation. A zero in place of the rA operand causes a zero to be
added to the GPR contents specified in operand rB. The option to specify rA or 0 is
shown in the instruction descriptions as (rA|0). Figure 70 shows how an EA is
generated using this mode.
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Figure 70. Register indirect with index addressing for integer loads/stores
0
Reserved
Instruction Encoding:
5 6
Opcode
10 11
15 16
rD/rS
rA
20 21
rB
30 31
Subopcode
0
0
31
GPR (rB)
Yes
0
rA=0?
+
No
32
63
0
31
GPR (rA)
Effective Address
32
63
Store
Load
GPR (rD/rS)

Memory
Interface
Register indirect addressing for integer loads and stores. Instructions using this
addressing mode use the contents of the GPR specified by the rA operand as the EA.
A zero in the rA operand generates an EA of zero. The option to specify rA or 0 is
shown in the instruction descriptions as (rA|0). Figure 71 shows how an EA is
generated using this mode.
Figure 71. Register indirect addressing for integer loads/stores
Reserved
0
Instruction Encoding:
Yes
Opcode
10 11
rD/rS
15 16
rA
NB
20 21
30 31
Subopcode
0
0
31
00000000000000000000000000000000
rA=0?
32
5 6
No
GPR (rA)
63
0
31
Effective Address
32
63
GPR (rD/rS)
Store
Load
Memory
Interface
See Section 4.2.3.3: Effective address calculation, for information about calculating EAs.
Note that in some implementations, operations that are not naturally aligned can suffer
performance degradation. Section 5.7.6: Alignment interrupt, for additional information
about load and store address alignment interrupts.
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Instruction model
Register indirect integer load instructions
For integer load instructions, the byte, half word, or word addressed by the EA is loaded into
rD. Many integer load instructions have an update form, in which rA is updated with the
generated EA. For these forms, if rA  0 and rA  rD (otherwise invalid), the EA is placed
into rA and the memory element (byte, half word, or word) addressed by the EA is loaded
into rD. Note that the Book E architecture defines load with update instructions with operand
rA = 0 or rA = rD as invalid forms.
4.3.1.10
Integer load instructions
Table 79. Integer load instructions
Name
Mnemonic
Syntax
Load Byte and Zero
lbz
rD,d(rA)
Load Byte and Zero Indexed
lbzx
rD,rA,rB
Load Byte and Zero with Update
lbzu
rD,d(rA)
Load Byte and Zero with Update Indexed
lbzux
rD,rA,rB
Load Half Word and Zero
lhz
rD,d(rA)
Load Half Word and Zero Indexed
lhzx
rD,rA,rB
Load Half Word and Zero with Update
lhzu
rD,d(rA)
Load Half Word and Zero with Update Indexed
lhzux
rD,rA,rB
Load Half Word Algebraic
lha
rD,d(rA)
Load Half Word Algebraic Indexed
lhax
rD,rA,rB
Load Half Word Algebraic with Update
lhau
rD,d(rA)
Load Half Word Algebraic with Update Indexed
lhaux
rD,rA,rB
Load Word and Zero
lwz
rD,d(rA)
Load Word and Zero Indexed
lwzx
rD,rA,rB
Load Word and Zero with Update
lwzu
rD,d(rA)
Load Word and Zero with Update Indexed
lwzux
rD,rA,rB
4.3.1.10.1 Integer store instructions
For integer store instructions, the rS contents are stored into the byte, half word, word or
double word in memory addressed by the EA. Many store instructions have an update form
in which rA is updated with the EA. For these forms, the following rules apply:

If rA  0, the EA is placed into rA.

If rS = rA, the contents of register rS are copied to the target memory element and the
generated EA is placed into rA (rS).
The Book E architecture defines store with update instructions with rA = 0 as an invalid
form. In addition, it defines integer store instructions with the CR update option enabled (Rc
field, bit 31, in the instruction encoding = 1) to be an invalid form. Table 80 summarizes
integer store instructions.
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Table 80. Integer store instructions
Name
Mnemonic
Syntax
Store Byte
stb
rS,d(rA)
Store Byte Indexed
stbx
rS,rA,rB
Store Byte with Update
stbu
rS,d(rA)
Store Byte with Update Indexed
stbux
rS,rA,rB
Store Half Word
sth
rS,d(rA)
Store Half Word Indexed
sthx
rS,rA,rB
Store Half Word with Update
sthu
rS,d(rA)
Store Half Word with Update Indexed
sthux
rS,rA,rB
Store Word
stw
rS,d(rA)
Store Word Indexed
stwx
rS,rA,rB
Store Word with Update
stwu
rS,d(rA)
Store Word with Update Indexed
stwux
rS,rA,rB
4.3.1.10.2 Integer load and store with byte-reverse instructions
Table 81 describes integer load and store with byte-reverse instructions. These books were
defined in part to support the original PowerPC definition of little-endian byte ordering. Note
that Book E supports true little endian on a per-page basis. For more information, see
Section 4.2.3.4: Byte ordering.
Table 81. Integer load and store with byte-reverse instructions
Name
Mnemonic
Syntax
Load Half Word Byte-Reverse Indexed
lhbrx
rD,rA,rB
Load Word Byte-Reverse Indexed
lwbrx
rD,rA,rB
Store Half Word Byte-Reverse Indexed
sthbrx
rS,rA,rB
Store Word Byte-Reverse Indexed
stwbrx
rS,rA,rB
4.3.1.10.3 Integer load and store multiple instructions
The load/store multiple instructions are used to move blocks of data to and from the GPRs.
The load multiple and store multiple instructions can have operands that require memory
accesses crossing a 4-Kbyte page boundary. As a result, these instructions can be
interrupted by a data storage interrupt associated with the address translation of the second
page.
Note:
If one of these instructions is interrupted, it may be restarted, requiring multiple memory
accesses.
The Book E architecture defines the Load Multiple Word (lmw) instruction (Table 82) with rA
in the range of registers to be loaded as an invalid form. Load and store multiple accesses
must be word aligned; otherwise, they cause an alignment exception.
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Table 82. Integer load and store multiple instructions
Name
Mnemonic
Syntax
Load Multiple Word
lmw
rD,d(rA)
Store Multiple Word
stmw
rS,d(rA)
4.3.1.10.4 Integer load and store string instructions
The integer load and store string instructions allow movement of data from memory to
registers or from registers to memory without concern for alignment. These instructions can
be used for a short move between arbitrary memory locations or to initiate a long move
between misaligned memory fields. However, in some implementations, these instructions
are likely to have greater latency and take longer to execute, perhaps much longer, than a
sequence of individual load or store instructions that produce the same results.
Table 83 summarizes the integer load and store string instructions.
Table 83. Integer load and store string instructions
Name
Mnemonic
Syntax
Load String Word Immediate
lswi
rD,rA,NB
Load String Word Indexed
lswx
rD,rA,rB
Store String Word Immediate
stswi
rS,rA,NB
Store String Word Indexed
stswx
rS,rA,rB
Load string and store string instructions can involve operands that are not word-aligned.
4.3.1.10.5 Floating-point load and store address generation
Floating-point load and store operations, listed in Table 84, generate EAs using the register
indirect with immediate index addressing mode and register indirect with index addressing
mode. Floating-point loads and stores are not supported for direct-store accesses. The use
of floating-point loads and stores for direct-store accesses results in an alignment interrupt.
There are two forms of the floating-point load instruction—single-precision and doubleprecision operand formats. Because the FPRs support only the floating-point doubleprecision format, single-precision floating-point load instructions convert single-precision
data to double-precision format before loading an operand into an FPR.
The floating-point load and store indexed instructions (lfsx, lfsux, lfdx, lfdux, stfsx, stfsux,
stfdx, and stfdux) are invalid when the Rc bit is one.
The PowerPC architecture defines load with update with rA = 0 as an invalid form.
Table 84. Floating-point load instructions
Name
Mnemonic
Syntax
Load Floating-Point Single
lfs
frD,d(rA)
Load Floating-Point Single Indexed
lfsx
frD,rA,rB
Load Floating-Point Single with Update
lfsu
frD,d(rA)
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Table 84. Floating-point load instructions (continued)
Name
Mnemonic
Syntax
lfsux
frD,rA,rB
Load Floating-Point Double
lfd
frD,d(rA)
Load Floating-Point Double Indexed
lfdx
frD,rA,rB
Load Floating-Point Double with Update
lfdu
frD,d(rA)
Load Floating-Point Double with Update Indexed
lfdux
frD,rA,rB
Load Floating-Point Single with Update Indexed
4.3.1.10.6 Floating-point store instructions
This section describes floating-point store instructions. There are three basic forms of the
store instruction—single-precision, double-precision, and integer. The integer form is
supported by the optional stfiwx instruction. Because the FPRs support only doubleprecision format for floating-point data, single-precision floating-point store instructions
convert double-precision data to single-precision format before storing the operands.
Table 85 summarizes the floating-point store instructions.
Table 85. Floating-point store instructions
Name
Mnemonic
Syntax
Store Floating-Point Single
stfs
frS,d(rA)
Store Floating-Point Single Indexed
stfsx
frS,r B
Store Floating-Point Single with Update
stfsu
frS,d(rA)
Store Floating-Point Single with Update Indexed
stfsux
frS,r B
Store Floating-Point Double
stfd
frS,d(rA)
Store Floating-Point Double Indexed
stfdx
frS,rB
Store Floating-Point Double with Update
stfdu
frS,d(rA)
stfdux
frS,rB
stfiwx
frS,rB
Store Floating-Point Double with Update Indexed
(1)
Store Floating-Point as Integer Word Indexed
1. The stfiwx instruction is optional to the Book E architecture.
Some floating-point store instructions require conversions in the LSU. Table 86 shows
conversions the LSU makes when executing a Store Floating-Point Single instruction.
Table 86. Store floating-point single behavior
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Data Type
Action
Single
Normalized
Store
Single
Denormalized
Store
Single
Zero, infinity, QNaN
Store
Single
SNaN
Store
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Table 86. Store floating-point single behavior (continued)
FPR Precision
Data Type
Action
Double
Normalized
If (exp  896) then
denormalize and store,
else store
Double
Denormalized
Store zero
Double
Zero, infinity, QNaN
Store
Double
SNaN
Store
Table 87 shows the conversions made when performing a Store Floating-Point Double
instruction. Most entries in the table indicate that the floating-point value is simply stored.
Only in a few cases are any other actions taken.
Table 87. Store floating-point double behavior
4.3.1.11
FPR Precision
Data Type
Action
Single
Normalized
Store
Single
Denormalized
Normalize and store
Single
Zero, infinity, QNaN
Store
Single
SNaN
Store
Double
Normalized
Store
Double
Denormalized
Store
Double
Zero, infinity, QNaN
Store
Double
SNaN
Store
Branch and flow control instructions
Some branch instructions can redirect instruction execution conditionally based on the value
of bits in the CR.
4.3.1.11.1 Branch instruction address calculation
Branch instructions can alter the sequence of instruction execution. Instruction addresses
are always assumed to be word aligned; the Book E processors ignore the two low-order
bits of the generated branch target address. Branch instructions compute the EA of the next
instruction address using the following addressing modes:

Branch relative

Branch conditional to relative address

Branch to absolute address

Branch conditional to absolute address

Branch conditional to link register (LR)

Branch conditional to count register (CTR)
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4.3.1.11.2 Branch relative addressing mode
Instructions that use branch relative addressing generate the next instruction address by
sign extending and appending 0b00 to the immediate displacement operand LI, and adding
the resultant value to the current instruction address. Branches using this mode have the
absolute addressing option disabled (AA field, bit 30, in the instruction encoding = 0). The
LR update option can be enabled (LK field, bit 31, in the instruction encoding = 1). This
causes the EA of the instruction following the branch instruction to be placed in the LR.
Figure 72 shows how the branch target address is generated using this mode.
Figure 72. Branch relative addressing
0
Instruction
Encoding:
5 6
29 30
18
0
LI
5
6
LI
0
AA LK
29 30
Sign Extension
31
0
31
0
31
+
Current Instruction Address
0
31
Branch Target Address
Reserved
4.3.1.11.3 Branch conditional to relative addressing mode
If branch conditions are met, instructions that use the branch conditional to relative
addressing mode generate the next instruction address by sign extending and appending
results to the immediate displacement operand (BD) and adding the resultant value to the
current instruction address. Branches using this mode have the absolute addressing option
disabled (AA field, bit 30, in the instruction encoding = 0). The LR update option can be
enabled (LK field, bit 31, in the instruction encoding = 1). This option causes the EA of the
instruction following the branch instruction to be placed in the LR. Figure 73 shows how the
branch target address is generated using this mode.
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Figure 73. Branch conditional relative addressing
0
Instruction
Encoding:
5 6
29 30
18
LI
0
5
6
AA LK
29 30
Sign Extension
LI
0
31
31
0
0
31
+
Current Instruction Address
0
31
Branch Target Address
Reserved
4.3.1.11.4 Branch to absolute addressing mode
Instructions that use branch to absolute addressing mode generate the next instruction
address by sign extending and appending 0b00 to the LI operand. Branches using this
addressing mode have the absolute addressing option enabled (AA field, bit 30, in the
instruction encoding = 1). The LR update option can be enabled (LK field, bit 31, in the
instruction encoding = 1). This option causes the EA of the instruction following the branch
instruction to be placed in the LR. Figure 74 shows how the branch target address is
generated using this mode.
Figure 74. Branch to absolute addressing
0
Instruction
Encoding:
5 6
29 30 31
18
0
LI
5 6
AA LK
29 30 31
LI
Sign Extension
0
0
0
29 30 31
Branch Target Address
0
0
4.3.1.11.5 Branch conditional to absolute addressing mode
If the branch conditions are met, instructions that use the branch conditional to absolute
addressing mode generate the next instruction address by sign extending and appending
0b00 to the BD operand. Branches using this addressing mode have the absolute
addressing option enabled (AA field, bit 30, in the instruction encoding = 1). The LR update
option can be enabled (bit 31 (LK) in the instruction encoding = 1). This option causes the
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EA of the instruction following the branch instruction to be placed in the LR. Figure 75
shows how the branch target address is generated using this mode.
Figure 75. Branch conditional to absolute addressing
0
Instruction
Encoding:
5 6
16
10 11
BO
15 16
29 30 31
BI
BD
0
No
Condition
Met?
AA LK
Next Sequential Instruction Address
Yes
15 16
0
31
29 30 31
Sign Extension
BD
0
0
0
29 30 31
Branch Target Address
0
0
4.3.1.11.6 Branch conditional to link register addressing mode
If the branch conditions are met, the branch conditional to LR instruction generates the next
instruction address by fetching the contents of the LR and clearing the two low-order bits to
zero. The LR update option can be enabled (LK field, bit 31, in the instruction encoding = 1).
This option causes the EA of the instruction following the branch instruction to be placed in
the LR. Figure 76 shows how the branch target address is generated using this mode.
Figure 76. Branch conditional to link register addressing
0
5 6
Instruction
Encoding:
19
10 11
BO
15 16
BI
00000
Condition
Met?
0
No
30 31
16
LK
0
Reserved
31
Next Sequential Instruction Address
Yes
29
LR
20 21
||
0
30 31
0
0
31
Branch Target Address
4.3.1.11.7 Branch conditional to count register addressing mode
If the branch conditions are met, the branch conditional to count register instruction
generates the next instruction address by fetching the contents of the count register (CTR)
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and clearing the two low-order bits to zero. The LR update option can be enabled (LK field,
bit 31, in the instruction encoding = 1). This option causes the EA of the instruction following
the branch instruction to be placed in the LR. Figure 77 shows how the branch target
address is generated when using this mode.
Figure 77. Branch conditional to count register addressing
0
Instruction
Encoding:
5 6
19
1011
BO
15 16
BI
20 21
00000
30 31
528
0
Condition
Met?
0
No
31
||
CTR
Reserved
Next Sequential Instruction Address
Yes
29
LK
0
30 31
0
0
31
Branch Target Address
4.3.1.12
Conditional branch control
Note:
Some processors do not implement the static branch prediction defined in Book E and
described here. For those processors, the BO operand is ignored for branch prediction.
For branch conditional instructions, the BO operand specifies the conditions under which
the branch is taken. The first four bits of the BO operand specify how the branch is affected
by or affects the condition and count registers. The fifth bit, shown in Table 89 as having the
value y, is used by some implementations for branch prediction as described below.
Table 88. BO bit descriptions
BO Bits
Description
0
Setting this bit causes the CR bit to be ignored.
1
Bit value to test against
2
Setting this causes the decrement to not be decremented.
3
Setting this bit reverses the sense of the CTR test.
4
Used for the y bit, which provides a hint about whether a conditional branch is likely to be
taken and may be used by some implementations to improve performance.
The encodings for the BO operands are shown in Table 89.
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Table 89. BO operand encodings(1)
BO
Description
0000y
Decrement the CTR, then branch if the decremented CTR  0 and the condition is FALSE.
0001y
Decrement the CTR, then branch if the decremented CTR = 0 and the condition is FALSE.
001zy
Branch if the condition is FALSE.
0100y
Decrement the CTR, then branch if the decremented CTR  0 and the condition is TRUE.
0101y
Decrement the CTR, then branch if the decremented CTR = 0 and the condition is TRUE.
011zy
Branch if the condition is TRUE.
1z00y
Decrement the CTR, then branch if the decremented CTR  0.
1z01y
Decrement the CTR, then branch if the decremented CTR = 0.
1z1zz
Branch always.
1. In this table, z indicates a bit that is ignored. Note that the z bits should be cleared, as they may be
assigned a meaning in some future version of the architecture.
The y bit provides a hint about whether a conditional branch is likely to be taken and may be used by some
implementations to improve performance.
The branch always encoding of the BO operand does not have a y bit.
Clearing the y bit indicates a predicted behavior for the branch instruction as follows:

For bcx with a negative value in the displacement operand, the branch is taken.

In all other cases (bcx with a non-negative value in the displacement operand, bclrx, or
bcctrx), the branch is not taken.
Setting the y bit reverses the preceding indications.
The sign of the displacement operand is used as described above even if the target is an
absolute address. The default value for the y bit should be 0 and should be set to 1 only if
software has determined that the prediction corresponding to y = 1 is more likely to be
correct than the prediction corresponding to y = 0. Software that does not compute branch
predictions should clear the y bit.
In most cases, the branch should be predicted to be taken if the value of the following
expression is 1, and predicted to fall through if the value is 0.
((BO[0] & BO[2]) | S)  BO[4]
In the expression above, S (bit 16 of the branch conditional instruction coding) is the sign bit
of the displacement operand if the instruction has a displacement operand and is 0 if the
operand is reserved. BO[4] is the y bit, or 0 for the branch always encoding of the BO
operand. (Advantage is taken of the fact that, for bclrx and bcctrx, bit 16 of the instruction is
part of a reserved operand and therefore must be 0.)
The 5-bit BI operand in branch conditional instructions specifies which CR bit represents the
condition to test. The CR bit selected is BI +32, as shown in Table 17.
If the branch instructions contain immediate addressing operands, the target addresses can
be computed sufficiently ahead of the branch instruction that instructions can be fetched
along the target path. If the branch instructions use the link and count registers, instructions
along the target path can be fetched if the link or count register is loaded sufficiently ahead
of the branch instruction.
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Branching can be conditional or unconditional, and optionally a branch return address is
created by storing the EA of the instruction following the branch instruction in the LR after
the branch target address has been computed. This is done regardless of whether the
branch is taken.
4.3.1.12.1 Branch instructions
Table 90 lists branch instructions provided by the Book E processors. A set of simplified
mnemonics and symbols is provided for the most frequently used forms of branch
conditional, compare, trap, rotate and shift, and certain other instructions. See Appendix B:
Simplified mnemonics for PowerPC instructions.
Table 90. Branch instructions
Name
Mnemonic
Syntax
b (ba bl bla)
target_addr
bc (bca bcl bcla)
BO,BI,target_addr
bclr (bclrl)
BO,BI
bcctr (bcctrl)
BO,BI
Branch
Branch Conditional
Branch Conditional to Link Register
Branch Conditional to Count Register
Note that the EIS defines the Integer Select instruction, isel, which can be used to more
efficiently handle sequences with multiple conditional branches. Its syntax is given in
Section 4.6.2. A detailed description including an example of how isel can be used can be
found in Section 8.1.2.
4.3.1.12.2 Condition register (cr) logical Instructions
CR logical instructions, shown in Table 91, and the Move Condition Register Field (mcrf)
instruction are also defined as flow control instructions.
Table 91. Condition register logical instructions
Name
Mnemonic
Syntax
Condition Register AND
crand
crbD,crbA,crbB
Condition Register OR
cror
crbD,crbA,crbB
Condition Register XOR
crxor
crbD,crbA,crbB
Condition Register NAND
crnand
crbD,crbA,crbB
Condition Register NOR
crnor
crbD,crbA,crbB
Condition Register Equivalent
creqv
crbD,crbA,crbB
Condition Register AND with Complement
crandc
crbD,crbA,crbB
Condition Register OR with Complement
crorc
crbD,crbA,crbB
Move Condition Register Field
mcrf
crfD,crfS
Note that if the LR update option is enabled for any of these instructions, the Book E
architecture defines these forms of the instructions as invalid.
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4.3.1.12.3 Trap instructions
The trap instructions shown in Table 92 test for a specified set of conditions. If any of the
conditions tested by a trap instruction are met, the system trap type program interrupt is
taken. For more information, see Section 5.7.7: Program interrupt. If the tested conditions
are not met, instruction execution continues normally. See Appendix B: Simplified
mnemonics for PowerPC instructions.
Table 92. Trap instructions
4.3.1.13
Name
Mnemonic
Syntax
Trap Word Immediate
twi
TO,rA,SIMM
Trap Word
tw
TO,rA,rB
System linkage instruction
The system call (sc) instruction permits a program to call on the system to perform a
service; see Table 93 and Section 4.3.2.1: System linkage instructions.
Table 93. System linkage instruction
Name
Mnemonic
Syntax
System Call
sc
—
Executing this instruction causes the system call interrupt handler to be invoked. For more
information, see Section 5.7.9.
4.3.1.14
Processor control instructions
Processor control instructions are used to read from and write to the CR, machine state
register (MSR), and special-purpose registers (SPRs).
4.3.1.14.1 Move to/from condition register instructions
Table 94 summarizes the instructions for reading from or writing to the CR.
Table 94. Move to/from condition register instructions
Name
Mnemonic
Syntax
Move to Condition Register Fields
mtcrf
CRM,rS
Move to Condition Register from XER
mcrxr
crD
mfcr
rD
Move from Condition Register
4.3.1.14.2 Move to/from special-purpose register instructions
Table 95 lists the mtspr and mfspr instructions.
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Table 95. Move to/from special-purpose register instructions
Name
Mnemonic
Syntax
Move to Special-Purpose Register
mtspr
SPR,rS
Move from Special-Purpose Register
mfspr
rD,SPR
Table 96 summarizes all SPRs defined in Book E, indicating which are user-level access.
The SPR number column lists register numbers used in the instruction mnemonics.
Table 96. Book E special-purpose registers (by SPR abbreviation)
Defined SPR number
SPR
Name
Deci
mal
Binary
Access
Supervisor
only
Section/
page
CSRR0
Critical save/restore register 0
58
00001 11010
Read/Write
Yes
Section 3.9.1.3
on page 84
CSRR1
Critical save/restore register 1
59
00001 11011
Read/Write
Yes
Section 3.9.1.4
on page 84
CTR
Count register
9
00000 01001
Read/Write
No
Section 3.5.3.1
on page 69
DAC1
Data address compare 1
316
01001 11100
Read/Write
Yes
Section 3.13.4
on page 119
DAC2
Data address compare 2
317
01001 11101
Read/Write
Yes
Section 3.13.4
on page 119
DBCR0
Debug control register 0
308
01001 10100
Read/Write
Yes
Section 3.13.1.1
on page 110
DBCR1
Debug control register 1
309
01001 10101
Read/Write
Yes
Section 3.13.1.2
on page 112
DBCR2
Debug control register 2
310
01001 10110
Read/Write
Yes
Section 3.13.1.3
on page 114
DBSR
Debug status register
304
01001 10000
Read/Clear(1)
Yes
Section 3.13.2
on page 117
DEAR
Data exception address
register
61
00001 11101
Read/Write
Yes
Section 3.9.1.5
on page 85
DEC
Decrementer
22
00000 10110
Read/Write
Yes
Section 3.8.4 on
page 82
DECAR
Decrementer auto-reload
54
00001 10110
Write-only
Yes
Section 3.8.5 on
page 83
DVC1
Data value compare 1
318
01001 11110
Read/Write
Yes
DVC2
Data value compare 2
319
01001 11111
Section 3.13.5
on page 119
ESR
Exception syndrome register
62
00001 11110
Read/Write
Yes
Section 3.9.1.8
on page 86
IAC1
Instruction address compare 1
312
01001 11000
Read/Write
Yes
Section 3.13.3
on page 118
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Table 96. Book E special-purpose registers (by SPR abbreviation) (continued)
Defined SPR number
SPR
Name
Deci
mal
Binary
Access
Supervisor
only
Section/
page
IAC2
Instruction address compare 2
313
01001 11001
Read/Write
Yes
Section 3.13.3
on page 118
IAC3
Instruction address compare 3
314
01001 11010
Read/Write
Yes
Section 3.13.3
on page 118
IAC4
Instruction address compare 4
315
01001 11011
Read/Write
Yes
Section 3.13.3
on page 118
IVOR0
Critical input
400
01100 10000
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR1
Critical input interrupt offset
401
01100 10001
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR2
Data storage interrupt offset
402
01100 10010
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR3
Instruction storage interrupt
offset
403
01100 10011
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR4
External input interrupt offset
404
01100 10100
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR5
Alignment interrupt offset
405
01100 10101
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR6
Program interrupt offset
406
01100 10110
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR7
Floating-point unavailable
interrupt offset
407
01100 10111
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR8
System call interrupt offset
408
01100 11000
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR9
Auxiliary processor
unavailable interrupt offset
409
01100 11001
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR10
Decrementer interrupt offset
410
01100 11010
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR11
Fixed-interval timer interrupt
offset
411
01100 11011
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR12
Watchdog timer interrupt
offset
412
01100 11100
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR13
Data TLB error interrupt offset
413
01100 11101
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR14
Instruction TLB error interrupt
offset
414
01100 11110
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR15
Debug interrupt offset
415
01100 11111
Read/Write
Yes
Section 3.9.1.7
on page 85
IVPR
Interrupt vector
63
00001 11111
Read/Write
Yes
Section 3.13.3
on page 118
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Table 96. Book E special-purpose registers (by SPR abbreviation) (continued)
Defined SPR number
SPR
Name
Deci
mal
Binary
Access
Supervisor
only
Section/
page
LR
Link register
8
00000 01000
Read/Write
No
Section 3.5.2 on
page 68
PID
Process ID register (2)
48
00001 10000
Read/Write
Yes
Section 3.12.1
on page 99
PIR
Processor ID register
286
01000 11110
Read only
Yes
Section 3.7.3 on
page 76
PVR
Processor version register
287
01000 11111
Read only
Yes
Section 3.7.4 on
page 76
SPRG0
SPR general 0
272
01000 10000
Read/Write
Yes
Section 3.10 on
page 92
SPRG1
SPR general 1
273
01000 10001
Read/Write
Yes
Section 3.10 on
page 92
SPRG2
SPR general 2
274
01000 10010
Read/Write
Yes
Section 3.10 on
page 92
259
01000 00011
Read only
No(3)
Section 3.10 on
page 92
275
01000 10011
Read/Write
Yes
Section 3.10 on
page 92
260
01000 00100
Read only
No
Section 3.10 on
page 92
276
01000 10100
Read/Write
Yes
Section 3.10 on
page 92
261
01000 00101
Read only
No
Section 3.10 on
page 92
277
01000 10101
Read/Write
Yes
Section 3.10 on
page 92
262
01000 00110
Read only
No
Section 3.10 on
page 92
278
01000 10110
Read/Write
Yes
Section 3.10 on
page 92
263
01000 00111
Read only
No
Section 3.10 on
page 92
279
01000 10111
Read/Write
Yes
Section 3.10 on
page 92
SPRG3
SPRG4
SPRG5
SPRG6
SPRG7
SPR general 3
SPR general 4
SPR general 5
SPR general 6
SPR general 7
SRR0
Save/restore register 0
26
00000 11010
Read/Write
Yes
Section 3.9.1.1
on page 83
SRR1
Save/restore register 1
27
00000 11011
Read/Write
Yes
Section 3.9.1.2
on page 84
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Table 96. Book E special-purpose registers (by SPR abbreviation) (continued)
Defined SPR number
SPR
TBL
TBU
Name
Access
Supervisor
only
Section/
page
01000 01100
Read only
No
Section 3.8.3 on
page 81
284
01000 11100
Write-only
Yes
Section 3.8.3 on
page 81
269
01000 01101
Read only
No
Section 3.8.3 on
page 81
285
01000 11101
Write-only
Yes
Section 3.8.3 on
page 81
Deci
mal
Binary
268
Time base lower
Time base upper
TCR
Timer control register
340
01010 10100
Read/Write
Yes
Section 3.8.1 on
page 79
TSR
Timer status register
336
01010 10000
Read/Clear(4)
Yes
Section 3.8.2 on
page 80
USPRG0
User SPR general 0(5)
256
01000 00000
Read/Write
No
Section 3.10 on
page 92
XER
Integer exception register
1
00000 00001
Read/Write
No
Section 3.3.2 on
page 57
1. The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits in the GPR can
be cleared using mtspr.
2. Implementations may support more than one PID. If multiple PIDs are implemented, the Book E–defined PID is
implemented as PID0.
3. User-mode read access to SPRG3 is implementation-dependent.
4. The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be
cleared using mtspr.
5. USPRG0 is a separate physical register from SPRG0.
Table 97 lists EIS-specific SPRs, indicating which can be accessed by user-level software.
Compilers should recognize SPR names when parsing instructions.
Table 97. Implementation-specific SPRs (by SPR abbreviation)
SPR
Name
SPR
number
Access
Supervisor
only
Section/page
ATBL
Alternate time base lower
526
Read-only
No
Section 3.15 on
page 123
ATBU
Alternate time base upper
527
Read-only
No
Section 3.15 on
page 123
DSRR0
Debug save/restore register 0
574
R/W
Yes
Section 3.9.1.10
on page 89
DSRR1
Debug save/restore register 1
575
R/W
Yes
Section 3.9.1.10
on page 89
IVOR32
SPE/embedded floating-point APU
unavailable interrupt offset
528
Read/Write
Yes
Section 3.9.1.7
on page 85
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Table 97. Implementation-specific SPRs (by SPR abbreviation) (continued)
SPR
Name
SPR
number
Access
Supervisor
only
Section/page
IVOR33
Embedded floating-point data exception
interrupt offset
529
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR34
Embedded floating-point round exception
interrupt offset
530
Read/Write
Yes
Section 3.9.1.7
on page 85
IVOR35
Performance monitor
531
Read/Write
Yes
Section 3.9.1.7
on page 85
L1CFG0
L1 cache configuration register 0
515
Read-only
No
Section 3.11.3
on page 96
L1CFG1
L1 cache configuration register 1
516
Read-only
No
Section 3.11.3
on page 96
L1CSR0
L1 cache control and status register 0
1010
Read/Write
Yes
Section 3.11.1
on page 92
L1CSR1
L1 cache control and status register 1
1011
Read/Write
Yes
Section 3.11.2
on page 94
L1FINV0
L1 flush and invalidate control register 0
1016
Read/Write
Yes
Section 3.11.5
on page 98
MAS0
MMU assist register 0
624
Read/Write
Yes
Section 3.12.5.1
on page 103
MAS1
MMU assist register 1
625
Read/Write
Yes
Section 3.12.5.1
on page 103
MAS2
MMU assist register 2
626
Read/Write
Yes
Section 3.12.5.1
on page 103
MAS3
MMU assist register 3
627
Read/Write
Yes
Section 3.12.5.4
on page 106
MAS4
MMU assist register 4
628
Read/Write
Yes
Section 3.12.5.4
on page 106
MAS5
MMU assist register 5.
629
Read/Write
Yes
Section 3.12.5.4
on page 106
MAS6
MMU assist register 6
630
Read/Write
Yes
Section 3.12.5.4
on page 106
MAS7
MMU assist register 7
944
Read/Write
Yes
Section 3.12.5.8
on page 109
MCAR
Machine check address register
573
Read-only
Yes
Section 3.12.5.8
on page 109
MCSR
Machine check syndrome register
572
Read/Write
Yes
Section 3.9.1.15
on page 90
MCSRR0
Machine-check save/restore register 0
570
Read/Write
Yes
Section 3.9.1.15
on page 90
MCSRR1
Machine-check save/restore register 1
571
Read/Write
Yes
Section 3.9.1.15
on page 90
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Table 97. Implementation-specific SPRs (by SPR abbreviation) (continued)
SPR
MMUCFG
Name
MMU configuration register
MMUCSR0 MMU control and status register 0
SPR
number
Access
Supervisor
only
Section/page
1015
Read-only
Yes
Section 3.12.3
on page 101
1012
Read/Write
Yes
Section 3.12.2
on page 100
PID0
Process ID register 0. Book E defines only
this PID register and refers to as PID, not
PID0.
48
Read/Write
Yes
Section 3.12.1
on page 99
PID1
Process ID register 1
633
Read/Write
Yes
Section 3.12.1
on page 99
PID2
Process ID register 2
634
Read/Write
Yes
Section 3.12.1
on page 99
SPEFSCR
Signal processing and embedded floatingpoint status and control register
512
Read/Write
No
Section 3.14.1
on page 120
SVR
System version register
1023
Read-only
Yes
Section 3.7.5 on
page 77
TLB0CFG
TLB configuration register 0
688
Read-only
Yes
Section 3.12.4
on page 102
TLB1CFG
TLB configuration register 1
689
Read-only
Yes
Section 3.12.4
on page 102
4.3.1.15
Memory synchronization instructions
Memory synchronization instructions control the order in which memory operations
complete with respect to asynchronous events and the order in which memory operations
are seen by other mechanisms that access memory. See Table 98 for a summary.
Table 98. Memory synchronization instructions
Name
Instruction
synchronize
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Mnemonic
isync
Syntax
—
EIS notes
Refetch serializing. An isync waits for previous instructions
(including any interrupts they generate) to complete before
isync executes, which purges all instructions from the
processor and refetches the next instruction. isync does not
wait for pending stores in the store queue to complete. Any
subsequent instruction sees all effects of instructions before
the isync.
Because it prevents execution of subsequent instructions until
preceding instructions complete, if an isync follows a
conditional branch that depends on the value returned by a
preceding load, the load on which the branch depends is
performed before any loads caused by instructions after the
isync even if the effects of the dependency are independent
of the value loaded (for example, the value is compared to
itself and the branch tests selected, CRn[EQ]), and even if the
branch target is the next sequential instruction to be executed.
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Table 98. Memory synchronization instructions (continued)
Name
Load word
and reserve
indexed
Memory
barrier
Memory
synchronize
Store word
conditional
indexed
4.3.1.16
Mnemonic
Syntax
EIS notes
lwarx
lwarx with stwcx. can emulate semaphore operations such
as test and set, compare and swap, exchange memory, and
fetch and add. Both instructions must use the same EA.
Reservation granularity is implementation-dependent.
rD,rA,rB
Executing lwarx and stwcx. to a page marked write-through
(WIMG = 10xx) or when the data cache is locked may cause a
data storage interrupt. If the location is not word-aligned, an
alignment interrupt occurs.
mbar
MO
mbar provides a pipelined memory barrier. (Note that mbar
uses the same opcode as eieio, which is not defined by Book
E.) The behavior of mbar is affected by the MO field (bits 6–
10) of the instruction.
MO = 0—mbar behaves identically to msync.
MO = 1—mbar is a weaker, faster memory barrier; see the
user’s manual for implementation-specific behavior.
msync
—
Provides an ordering function for the effects of all instructions
executed by the processor executing the msync. Executing
an msync ensures that all previous instructions complete
before it completes and that no subsequent instructions are
initiated until after it completes. It also creates a memory
barrier, which orders the storage accesses associated with
these instructions.
msync cannot complete before storage accesses associated
with previous instructions are performed. msync is execution
synchronizing. Note the following:
msync is used to ensure that all stores into a data structure
caused by store instructions executed in a critical section of a
program are performed with respect to another processor
before the store that releases the lock is performed with
respect to that processor. mbar is preferable in many cases.
On ST Book E devices: Unlike a context-synchronizing
operations, msync does not discard prefetched instructions.
stwcx.
lwarx with stwcx. can emulate semaphore operations such
as test and set, compare and swap, exchange memory, and
fetch and add. Both instructions must use the same EA.
Reservation granularity is implementation-dependent.
rS,rA,rB
Executing lwarx and stwcx. to a page marked write-through
(WIMG = 10xx) or cache-inhibited (WIMG = 01xx) when the
data cache is locked may cause a data storage interrupt. If the
location is not word-aligned, an alignment interrupt occurs.
Atomic update primitives using lwarx and stwcx.
The lwarx and stwcx. instructions together permit atomic update of a memory location.
Book E provides word and double word forms of each of these instructions. Described here
is the operation of lwarx and stwcx.
A specified memory location that may be modified by other processors or mechanisms
requires memory coherence. If the location is in write-through required or caching inhibited
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memory, the implementation determines whether these instructions function correctly or
cause the system data storage error handler to be invoked.
Note the following:

The memory coherence required attribute on other processors and mechanisms
ensures that their stores to the specified location will cause the reservation created by
the lwarx to be cancelled.

Warning: Support for load and reserve and store conditional instructions for which the
specified location is in caching-inhibited memory is being phased out of Book E. It is
likely not to be provided on future implementations. New programs should not use
these instructions to access caching inhibited memory.
A lwarx instruction is a load from a word-aligned location with the following side effects.

A reservation for a subsequent stwcx. instruction is created.

The memory coherence mechanism is notified that a reservation exists for the location
accessed by the lwarx.
The stwcx. is a store to a word-aligned location that is conditioned on the existence of the
reservation created by the lwarx and on whether both instructions specify the same
location. To emulate an atomic operation, both lwarx and stwcx. must access the same
location. lwarx and stwcx. are ordered by a dependence on the reservation, and the
program is not required to insert other instructions to maintain the order of memory
accesses caused by these two instructions.
A stwcx. performs a store to the target location only if the location accessed by the lwarx
that established the reservation has not been stored into by another processor or
mechanism between supplying a value for the lwarx and storing the value supplied by the
stwcx.. If the instructions specify different locations, the store is not necessarily performed.
CR0 is modified to indicate whether the store was performed, as follows:
CR0[LT,GT,EQ,SO] = 0b00 || store_performed || XER[SO]
If a stwcx. completes but does not perform the store because a reservation no longer
exists, CR0 is modified to indicate that the stwcx. completed without altering memory.
A stwcx. that performs its store is said to succeed.
Examples using lwarx and stwcx. are given in Appendix C: Programming examples.
A successful stwcx. to a given location may complete before its store has been performed
with respect to other processors and mechanisms. As a result, a subsequent load or lwarx
from the given location on another processor may return a stale value. However, a
subsequent lwarx from the given location on the other processor followed by a successful
stwcx. on that processor is guaranteed to have returned the value stored by the first
processor’s stwcx. (in the absence of other stores to the given location).
4.3.1.16.1 Reservations
The ability to emulate an atomic operation using lwarx and stwcx. is based on the
conditional behavior of stwcx., the reservation set by lwarx, and the clearing of that
reservation if the target location is modified by another processor or mechanism before the
stwcx. performs its store.
A reservation is held on an aligned unit of real memory called a reservation granule. The
size of the reservation granule is implementation-dependent, but is a multiple of 4 bytes for
lwarx. The reservation granule associated with EA contains the real address to which the
EA maps. (‘real_addr(EA)’ in the RTL for the load and reserve and store conditional
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instructions stands for ‘real address to which EA maps.’) When one processor holds a
reservation and another processor performs a store, the first processor’s reservation is
cleared if the store affects any bytes in the reservation granule.
Note:
One use of lwarx and stwcx. is to emulate a compare and swap primitive like that provided
by the IBM System/370 compare and swap instruction, which checks only that the old and
current values of the word being tested are equal, with the result that programs that use
such a compare and swap to control a shared resource can err if the word has been
modified and the old value is subsequently restored. The use of lwarx and stwcx. improves
on such a compare and swap, because the reservation reliably binds lwarx and stwcx.
together. The reservation is always lost if the word is modified by another processor or
mechanism between the lwarx and stwcx., so the stwcx. never succeeds unless the word
has not been stored into (by another processor or mechanism) since the lwarx.
A processor has at most one reservation at any time. Book E states that a reservation is
established by executing a lwarx and is lost (or may be lost, in the case of the fourth and
fifth bullets) if any of the following occurs.

The processor holding the reservation executes another lwarx; this clears the first
reservation and establishes a new one.

The processor holding the reservation executes any stwcx., regardless of whether the
specified address matches that of the lwarx.

Another processor executes a store or dcbz to the same reservation granule.

Another processor executes a dcbtst, dcbst, or dcbf to the same reservation granule;
whether the reservation is lost is undefined.

Another processor executes a dcba to the reservation granule. The reservation is lost if
the instruction causes the target block to be newly established in the data cache or to
be modified; otherwise, whether the reservation is lost is undefined.

Some other mechanism modifies a location in the same reservation granule.

Other implementation-specific conditions may also cause the reservation to be cleared,
See the core reference manual.
Interrupts are not guaranteed to clear reservations. (However, system software invoked by
interrupts may clear reservations.)
In general, programming conventions must ensure that lwarx and stwcx. specify addresses
that match; a stwcx. should be paired with a specific lwarx to the same location. Situations
in which a stwcx. may erroneously be issued after some lwarx other than that with which it
is intended to be paired must be scrupulously avoided. For example, there must not be a
context switch in which the processor holds a reservation in behalf of the old context, and
the new context resumes after a lwarx and before the paired stwcx.. The stwcx. in the new
context might succeed, which is not what was intended by the programmer.
Such a situation must be prevented by issuing a stwcx. to a dummy writable word-aligned
location as part of the context switch, thereby clearing any reservation established by the
old context. Executing stwcx. to a word-aligned location is enough to clear the reservation,
regardless of whether it was set by lwarx.
4.3.1.16.2 Forward progress
Forward progress in loops that use lwarx and stwcx. is achieved by a cooperative effort
among hardware, operating system software, and application software.
Book E guarantees one of the following when a processor executes a lwarx to obtain a
reservation for location X and then a stwcx. to store a value to location X:
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1.
The stwcx. succeeds and the value is written to location X.
2.
The stwcx. fails because some other processor or mechanism modified location X.
3.
The stwcx. fails because the processor’s reservation was lost for some other reason.
In cases (1) and (2), the system as a whole makes progress in the sense that some
processor successfully modifies location X. Case (3) covers reservation loss required for
correct operation of the rest of the system. This includes cancellation caused by some other
processor writing elsewhere in the reservation granule for X, as well as cancellation caused
by the operating system in managing certain limited resources such as real memory or
context switches. It may also include implementation-dependent causes of reservation loss.
An implementation may make a forward progress guarantee, defining the conditions under
which the system as a whole makes progress. Such a guarantee must specify the possible
causes of reservation loss in case (3). Although Book E alone cannot provide such a
guarantee, the conditions in cases (1) and (2) are necessary for a guarantee. An
implementation and operating system can build on them to provide such a guarantee.
Note that Book E does not guarantee fairness. In competing for a reservation, two
processors can indefinitely lock out a third.
4.3.1.16.3 Reservation loss due to granularity
Lock words should be allocated such that contention for the locks and updates to nearby
data structures do not cause excessive reservation losses due to false indications of sharing
that can occur due to the reservation granularity.
A processor holding a reservation on any word in a reservation granule loses its reservation
if some other processor stores anywhere in that granule. Such problems can be avoided
only by ensuring that few such stores occur. This can most easily be accomplished by
allocating an entire granule for a lock and wasting all but one word.
Reservation granularity may vary for each implementation. There are no architectural
restrictions bounding the granularity implementations must support, so reasonably portable
code must dynamically allocate aligned and padded memory for locks to guarantee absence
of granularity-induced reservation loss.
4.3.1.17
Memory control instructions
Memory control instructions can be classified as follows:

User- and supervisor-level cache management instructions.

Supervisor-level–only translation lookaside buffer management instructions
This section describes the user-level cache management instructions. See Section 4.3.2.2:
Supervisor-level memory control instructions, for information about supervisor-level cache
and translation lookaside buffer management instructions.
This section does not describe the cache-locking APU instructions, which are described in
Section 4.6.4: Cache locking APU.
4.3.1.17.1 Cache management instructions
Cache management instructions obey the sequential execution model except as described
in the example in this section of managing coherence between the instruction and data
caches.
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In the instruction descriptions the statements. “this instruction is treated as a load” and “this
instruction is treated as a store,” mean that the instruction is treated as a load from or a
store to the addressed byte with respect to address translation, memory protection, and the
memory access ordering done by msync, mbar, and the other means described in
Section 6.2.2.1: Memory access ordering.”
If caches are combined, the same value should be given for an instruction cache attribute
and the corresponding data cache attribute.
Each implementation provides an efficient way for software to ensure that all blocks that are
considered to be modified in the data cache have been copied to main memory before the
processor enters any power-saving mode in which data cache contents are not maintained.
The means are described in the reference manual for the implementation.
It is permissible for an implementation to treat any or all of the cache touch instructions
(icbt, dcbt, or dcbtst) as no-operations, even if a cache is implemented.
The instruction cache is not necessarily kept consistent with the data cache or with main
memory. When instructions are modified, software must ensure that the instruction cache is
made consistent with data memory and that the modifications are made visible to the
instruction fetching mechanism. The following instruction sequence can be used to
accomplish this when the instructions being modified are in memory that is memory
coherence required and one program both modifies the instructions and executes them.
(Additional synchronization is needed when one program modifies instructions that another
program will execute.) In this sequence, location ‘instr’ is assumed to contain modified
instructions.
dcbst
instr
# update block in main memory
instr
# invalidate copy in instr cache
msync
icbi
# order update before invalidation
msync
# order invalidation before discarding prefetched instructions
isync
# discard prefetched instructions
Note:
Because the optimal instruction sequence may vary between systems, many operating
systems provide a system service to perform the function described above.
As stated above, the EA is translated using translation resources used for data accesses,
even though the block being invalidated was copied into the instruction cache based on
translation resources used for instruction fetches.
4.3.1.18
User-level cache instructions
The instructions listed in Table 99 help user-level programs manage on-chip caches if they
are implemented. The following sections describe how these operations are treated with
respect to the caches. The EIS supports the following CT values, defined by the EIS:

CT = 0 indicates the L1 cache.

CT = 1 indicates the I/O cache. (Note that some versions of the e500 documentation
refer to the I/O cache as a frontside L2 cache.)

CT = 2 indicates a backside L2 cache.
As with other memory-related instructions, the effects of cache management instructions on
memory are weakly-ordered. If the programmer must ensure that cache or other instructions
have been performed with respect to all other processors and system mechanisms, an
msync must be placed after those instructions.
Section 4.6.4: Cache locking APU, describes cache-locking APU instructions.
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Table 99. User-level cache instructions
Name
Mnemonic
Syntax
Descriptions
Data cache block
allocate
dcba
rA,rB
This instruction is treated as a store with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
A no-op occurs if the cache is disabled or locked, if the page is
marked write-through or cache-inhibited, or if a TLB protection
violation occurs.
An implementation may chose to no-op the instruction.
Data cache block
flush
dcbf
rA,rB
This instruction is treated as a load with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
Data cache block
set to zero
dcbz
rA,rB
This instruction is treated as a store with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
If the block containing the byte addressed by EA is in the data cache,
all bytes of the block are cleared. If the block containing the byte
addressed by EA is not in the data cache and is in storage that is not
caching inhibited, the block is established in the data cache without
fetching the block from main storage and all bytes of the block are
cleared.
If the block containing the byte addressed by EA is not in the data
cache and is in storage that is not caching inhibited and cannot be
established in the cache, then one of the following occurs:
All bytes of the area of main storage that corresponds to the
addressed block are set to zero
An alignment interrupt is taken
If the block containing the byte addressed by EA is in storage that is
caching inhibited or write through required, one of the following
occurs:
All bytes of the area of main storage that corresponds to the
addressed block are set to zero
An alignment interrupt is taken.
Data cache block
store
dcbst
rA,rB
This instruction is treated as a load with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
dcbt
This instruction is treated as a load with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
CT,rA,rB A no-op occurs if the cache is disabled or locked, if the page is
marked write-through or cache-inhibited, or if a TLB protection
violation occurs.
An implementation may chose to no-op the instruction.
Data cache block
touch (1)
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Table 99. User-level cache instructions (continued)
Name
Mnemonic
Syntax
Descriptions
Data cache block
touch for store (1)
dcbtst
Depending on the implementation, this instruction is treated as a load
or store with respect to any memory barriers, synchronization,
translation and protection, and debug address comparisons.
CT,rA,rB A no-op occurs if the cache is disabled or locked, if the page is
marked write-through or cache-inhibited, or if a TLB protection
violation occurs.
An implementation may chose to no-op the instruction.
Instruction cache
block invalidate
icbi
rA,rB
icbt
This instruction is treated as a load with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
CT,rA,rB A no-op occurs if the cache is disabled or locked, if the page is
marked write-through or cache-inhibited, or if a TLB protection
violation occurs.
An implementation may chose to no-op the instruction.
Instruction cache
block touch
This instruction is treated as a load with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
1. A program that uses dcbt and dcbtst improperly is less efficient. To improve performance, HID0[NOPTI] can be set, which
causes dcbt and dcbtst to be no-oped at the cache. They do not cause bus activity and cause only a 1-clock execution
latency. The default state of this bit is zero, which enables the use of these instructions.
4.3.2
Supervisor level instructions
The Book E architecture includes the structure of the memory management model,
supervisor-level registers, and the interrupt model. This section describes the supervisorlevel instructions defined by the EIS.
4.3.2.1
System linkage instructions
This section describes the system linkage instructions (see Table 100). The user-level sc
instruction lets a user program call on the system to perform a service and causes the
processor to take a system call interrupt. The supervisor-level rfi instruction is used for
returning from an interrupt handler. The rfci instruction is used for critical interrupts. The EIS
defines the rfmci for machine check interrupts and rfdi for debug APU interrupts.
Table 100. System linkage instructions—supervisor-level
Name
Mnemonic Syntax
Implementation notes
Return from
interrupt
rfi
—
rfi is context-synchronizing
Return from
debug interrupt
rfdi
—
Debug interrupt APU. When rfdi is executed, the values in
the debug save and restore registers (DSRR0 and DSRR1)
are restored. rfdi is context-synchronizing.
—
Machine check interrupt APU. When rfmci is executed, the
values in the machine check interrupt save and restore
registers (MCSRR0 and MCSRR1) are restored. rfmci is
context-synchronizing.
Return from
machine check
interrupt
rfmci
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Table 100. System linkage instructions—supervisor-level (continued)
Name
Mnemonic Syntax
Implementation notes
Return from
rfci
critical interrupt
—
When rfci executes, the values in the critical interrupt save
and restore registers (CSRR0 and CSRR1) are restored. rfci
is context-synchronizing.
System call
—
The sc instruction is context-synchronizing.
sc
Table 101 lists instructions for accessing the MSR.
Table 101. Move to/from machine state register instructions
Name
Mnemonic Syntax
Description
Move from machine state register
mfmsr
rD
—
Move to machine state register
mtmsr
rS
—
Write MSR external enable
wrtee
rS
Bit 48 of the contents of rS is placed
into MSR[EE]. Other MSR bits are
unaffected.
Write MSR external enable
immediate
wrteei
E
The value of E is placed into MSR[EE].
Other MSR bits are unaffected.
Certain encodings of the SPR field of mtspr and mfspr instructions (shown in Table 95)
provide access to supervisor-level SPRs. Table 96 lists encodings for architecture-defined
SPRs. Encodings for EIS-defined, supervisor-level SPRs are listed in Table 102. Simplified
mnemonics are provided for mtspr and mfspr. Appendix C: Programming examples,
describes context synchronization requirements when altering certain SPRs.
4.3.2.2
Supervisor-level memory control instructions
Memory control instructions include the following:

Cache management instructions (supervisor-level and user-level)

Translation lookaside buffer management instructions
This section describes supervisor-level memory control instructions. Section 4.3.1.17:
Memory control instructions, describes user-level memory control instructions.
4.3.2.3
Supervisor-level cache instruction
Table 102 lists the only supervisor-level cache management instruction.
Table 102. Supervisor-Level cache management instruction
Name
Mnemonic Syntax
Data cache
block
dcbi
invalidate
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Implementation notes
This instruction is treated as a store with respect to any memory
barriers, synchronization, translation and protection, and debug
address comparisons.
An implementation may first perform a dcbst operation before
invalidating the cache block if the memory is marked as
coherency required (WIMG = xx1x).
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See Section 4.3.1.18: User-level cache instructions, for cache instructions that provide userlevel programs the ability to manage the on-chip caches.
4.3.2.4
Supervisor-level tlb management instructions
The address translation mechanism is defined in terms of TLBs and page table
entries (PTEs) Book E processors use to locate the logical-to-physical address
mapping for a particular access. See Section 6.4: Storage model, for more information
about TLB operations. Table 103 summarizes the operation of the TLB instructions.
Table 103. TLB management instructions
Name
TLB
invalidate
virtual
address
indexed
TLB read
entry
TLB search
indexed
Mnemonic Syntax
tlbivax
tlbre
tlbsx
Implementation Notes
rA, rB
A TLB invalidate operation is performed whenever tlbivax is
executed. tlbivax invalidates any TLB entry that corresponds to
the virtual address calculated by this instruction as long as
IPROT is not set; this includes invalidating TLB entries
contained in TLBs on other processors and devices in addition
to the processor executing tlbivax. Thus an invalidate operation
is broadcast throughout the coherent domain of the processor
executing tlbivax. See Section 6.4.
—
tlbre causes the contents of a single TLB entry to be extracted
from the MMU and be placed in the corresponding MAS register
fields. The entry extracted is specified by the TLBSEL, ESEL
and EPN fields of MAS0 and MAS2. The contents extracted
from the MMU are placed in MAS0–MAS3 and MAS7. See
Section 6.4.9.
rA, rB
tlbsx updates MAS conditionally based on the success or
failure of a lookup in the MMU. The lookup is controlled by the
EA provided by GPR[rB] specified in the instruction encoding
and MAS6[SAS,SPID]. The values placed into MAS0–MAS3
and MAS7 differ, depending on whether a successful or
unsuccessful search occurred.
Note that RA=0 is a preferred form for tlbsx and that some ST
implementations take an illegal instruction exception program
interrupt if RA != 0.
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Table 103. TLB management instructions (continued)
Name
Mnemonic Syntax
TLB
tlbsync
synchronize
TLB Write
Entry
4.3.3
tlbwe
Implementation Notes
—
Provides an ordering function for the effects of all tlbivax
instructions executed by the processor executing the tlbsync
instruction, with respect to the memory barrier created by a
subsequent msync instruction executed by the same
processor. Executing a tlbsync instruction ensures that all of the
following occurs:
All TLB invalidations caused by tlbivax instructions preceding
the tlbsync will have completed on any other processor before
any storage accesses associated with data accesses caused by
instructions following the msync instruction are performed with
respect to that processor.
All storage accesses by other processors for which the address
was translated using the translations being invalidated, will have
been performed with respect to the processor executing the
msync instruction, to the extent required by the associated
memory coherence required attributes, before the mbar or
msync instruction’s memory barrier is created.
See Section 6.4.9: Translation lookaside buffer (TLB) arrays.
—
tlbwe causes the contents of certain fields of MAS0, MAS1,
MAS2, and MAS3 to be written into a TLB entry specified by the
TLBSEL, ESEL, and EPN fields of MAS0 and MAS2. If MAS7 is
implemented, execution of tlbwe causes any MAS7[RPN] to be
written to the selected TLB entry. See Section 6.4.9.
Recommended simplified mnemonics
The description of each instruction includes the mnemonic and a formatted list of operands.
Book E–compliant assemblers support the mnemonics and operand lists. To simplify
assembly language programming, a set of simplified mnemonics and symbols is provided
for some of the most frequently used instructions; refer to Appendix B: Simplified
mnemonics for PowerPC instructions, for a complete list. Programs written to be portable
across the various assemblers for the Book E architecture should not assume the existence
of mnemonics not described in this document.
4.3.4
Book E instructions with implementation-specific features
Book E defines several instructions in a general way, leaving the details of the execution up
to the implementation. These are listed in Table 104. This section describes how the EIS
further defines those instructions. See the user documentation for additional
implementation-specific behavior.
Table 104. Implementation-specific instructions summary
Name
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Mnemonic Syntax
Move from APID Indirect
mfapidi
—
Move from Device Control
Register
mfdcr
—
Move to Device Control Register mtdcr
—
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Table 104. Implementation-specific instructions summary (continued)
Name
Mnemonic Syntax
TLB Invalidate Virtual Address
Indexed
tlbivax
rA, rB
TLB Read Entry
tlbre
—
TLB Search Indexed
tlbsx
rA, rB
TLB Write Entry
tlbwe
—
Category
These are described generally in
Section 4.3.2.4: Supervisor-level tlb
management instructions.
A list of user-level instructions defined by both the classic PowerPC architecture and Book E
can be found in Section 4.7.
4.3.5
EIS instructions
The EIS defines the instructions listed in Table 105 (with cross references to more detailed
descriptions) that extend the Book E instruction set in accordance with Book E. SPE and
embedded floating-point APU instructions are listed in Table 108 and Table 117.
Table 105. EIS-defined instructions (except SPE and SPFP instructions)
Name
Mnemonic
Syntax
Section #/page
Data Cache Block Lock Clear
dcblc
CT, rA, rB
Data Cache Block Touch and Lock Set
dcbtls
CT, rA, rB
Data Cache Block Touch for Store and Lock Set
dcbtstls
CT, rA, rB
Instruction Cache Block Lock Clear
icblc
CT, rA, rB
Instruction Cache Block Touch and Lock Set
icbtls
CT, rA, rB
Integer Select
isel
rD, rA, rB, crb
Move from Performance Monitor Register
mfpmr
rD,PMRN
Move to Performance Monitor Register
mtpmr
PMRN,rS
Return from Machine Check Interrupt
rfmci
—
Section 4.6.5
Return from Debug Interrupt
rfdi
—
Section 4.6.5
Section 4.6.4
Section 4.6.2
Section 4.6.3
4.3.6
Context synchronization
Context synchronization is achieved by post- and presynchronizing instructions. An
instruction is presynchronized by completing all instructions before dispatching the
presynchronized instruction. Post-synchronizing is implemented by not dispatching any later
instructions until the post-synchronized instruction is completely finished.
4.4
Instruction fetching
In general, instructions are prefetched from the cache on a cache hit and from memory on a
cache miss. Prefetched instructions may not be executed if the instruction stream is
redirected after instructions are fetched and before they are scheduled for execution.
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Memory synchronization
The msync instruction provides a memory barrier throughout the memory hierarchy. It waits
for preceding data memory accesses to reach the point of coherency (that is, visible to the
entire memory hierarchy); then it is broadcast. No subsequent instructions in the stream are
initiated until after msync completes. Note that msync uses the same opcode as the sync
instruction. The msync instruction is described in Section 4.3.1.15: Memory
synchronization instructions.
See Section 6.2.2.1: Memory access ordering, for detailed information.
4.6
EIS-specific instructions
This section described EIS-defined instructions that are part of APUs or other extensions to
the Book E architecture.
4.6.1
SPE and embedded floating-point APUs
The SPE and the embedded vector single-precision and embedded scalar double-precision
APUs provide an extended GPR file with 32, 64-bit registers. The 32-bit Book E instructions
operate on the lower (least significant) 32 bits of the 64-bit register. SPE APU vector
instructions and embedded vector SPFP treat 64-bit registers as containing two 32-bit
elements or four 16-bit elements as described in Section 4.6.1.1.1: SPE APU instructions.
The embedded double-precision floating-point APU uses the extended GPRs to hold single,
IEEE-compliant double-precision operands.
However, like 32-bit Book E instructions, scalar SPFP APU floating-point instructions use
bits 32–63 of the GPRs to hold 32-bit single-precision operands, as described in
Section 4.6.1.2: Embedded vector and scalar floating-point APU instructions.
There is no record form of SPE or embedded floating-point instructions. Vector compare
instructions store the result of the comparison into the CR. The meaning of the CR bits is
now overloaded for vector operations. Vector compare instructions specify a CR field and
two source registers as well as the type of compare: greater than, less than, or equal. Two
bits in the CR field are written with the result of the vector compare, one for each element.
The two defined bits could be used either by a vector select instruction or by a UISA branch
instruction.
A partially visible accumulator register is architected for the integer and fractional multiply
accumulate SPE instructions. It is described in Section 3.14.2.
Full descriptions of these instructions can be found in Chapter 14: VLE instruction set.
4.6.1.1
SPE APU instruction architecture
This section describes the instruction formats and instructions defined by the SPE APU.
Signed fractions
In signed fractional format, the N-bit operand is represented in a 1.[N–1] format (1 sign bit,
N–1 fraction bits). Signed fractional numbers are in the following range:
– 1.0  SF  1.0 – 2– N – 1 
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The real value of the binary operand SF[0:N-1] is as follows:
N–1
SF = – 1.0  SF  0  +

SF  i   2
–i
i=1
The most negative and positive numbers representable in fractional format are as follows:

The most negative number is represented by SF(0) = 1 and SF[1:N–1] = 0 (that is,
N=32; 0x8000_0000 = –1.0).

The most positive number is represented by SF(0) = 0 and SF[1:N–1] = all 1s (that is,
N=32; 0x7FFF_FFFF = 1.0 - 2–(N–1)).
SPE APU—integer and fractional operations
Figure 78 shows data formats for signed integer and fractional multiplication. Note that low
word versions of signed saturate and signed modulo fractional instructions are not
supported. Attempting to execute an opcode corresponding to these instructions causes
boundedly undefined results.
Figure 78. Integer and fractional operations
Signed Multiplication N  N 2N – 1 Bits
Integer
S
S
Fractional
S
S


Signed Multiplier
S
S
HP
LP
(2N–1)–Bit Product
Sign Extension
2N Bits
4.6.1.1.1
Signed Multiplier
S
HP
LP
0
(2N–1)–Bit Product
Zero fill
2N Bits
SPE APU instructions
SPE APU instructions treat 64-bit GPRs as being composed of a vector of two 32-bit
elements. (Some instructions also read or write 16-bit elements.) The SPE APU supports a
number of forms of multiply and multiply-accumulate operations, and of add and subtract to
accumulator operations. The SPE supports signed and unsigned forms, and optional
fractional forms. For these instructions, the fractional form does not apply to unsigned forms
because integer and fractional forms are identical for unsigned operands.
Table 106 shows how SPE APU vector multiply instruction mnemonics are structured.
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Table 106. SPE APU vector multiply instruction mnemonic structure
Prefix
evm
Multiply element
half odd (16x16->32)
ho half even (16x16->32)
he half odd guarded (16x16>32)
hog
half even guarded (16x16heg
>32)
wh
word high (32x32->32)
wl
word low (32x32->32)
wh
word high guarded (32x32g
>32)
wlg
word low guarded (32x32w
>32)
word (32x32->64)
Data Type element
unsigned saturate
integer
unsigned modulo
integer
signed saturate integer
(1)
signed saturate
smi fractional
smf( signed modulo integer
1)
signed modulo
fractional
usi
umi
ssi
ssf
Accumulate element
a
aa
an
aa
w
an
w
write to ACC
write to ACC & added ACC
write to ACC & negate ACC
write to ACC & ACC in words
write to ACC & negate ACC in
words
1. Low word versions of signed saturate and signed modulo fractional instructions are not supported. Attempting to execute
an opcode corresponding to these instructions causes boundedly undefined results.
Table 107 defines mnemonic extensions for these instructions.
Table 107. Mnemonic extensions for multiply-accumulate instructions
Extension
Meaning
Comments
Multiply form
he
Half word even
161632
heg
Half word even guarded
161632, 64-bit final accumulator result
ho
Half word odd
161632
hog
Half word odd guarded
161632, 64-bit final accumulator result
w
Word
323264
wh
Word high
323232, high-order 32 bits of product
wl
Word low
323232, low-order 32 bits of product
smf
Signed modulo fractional
(Wrap, no saturate)
smi
Signed modulo integer
(Wrap, no saturate)
ssf
Signed saturate fractional
ssi
Signed saturate integer
umi
Unsigned modulo integer
usi
Unsigned saturate integer
Data type
(Wrap, no saturate)
Accumulate options
a
Update accumulator
Update accumulator (no add)
aa
Add to accumulator
Add result to accumulator (64-bit sum)
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Table 107. Mnemonic extensions for multiply-accumulate instructions
Extension
Meaning
Comments
aaw
Add to accumulator (words)
Add word results to accumulator words (pair of 32-bit sums)
an
Add negated
Add negated result to accumulator (64-bit sum)
anw
Add negated to accumulator
(words)
Add negated word results to accumulator words (pair of 32-bit
sums)
Table 108 lists SPE APU instructions.
Table 108. SPE APU vector instructions
Instruction
Mnemonic
Syntax
Bit Reversed Increment
brinc
rD,rA,rB
Initialize Accumulator
evmra
rD,rA
Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and
Accumulate
evmhegsmfaa
rD,rA,rB
Multiply Half Words, Even, Guarded, Signed, Modulo, Fractional and
Accumulate Negative
evmhegsmfan
rD,rA,rB
Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate evmhegsmiaa
rD,rA,rB
Multiply Half Words, Even, Guarded, Signed, Modulo, Integer and Accumulate
evmhegsmian
Negative
rD,rA,rB
Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and
Accumulate
evmhegumiaa
rD,rA,rB
Multiply Half Words, Even, Guarded, Unsigned, Modulo, Integer and
Accumulate Negative
evmhegumian
rD,rA,rB
Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and
Accumulate
evmhogsmfaa
rD,rA,rB
Multiply Half Words, Odd, Guarded, Signed, Modulo, Fractional and
Accumulate Negative
evmhogsmfan
rD,rA,rB
Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate
evmhogsmiaa
rD,rA,rB
Multiply Half Words, Odd, Guarded, Signed, Modulo, Integer and Accumulate
Negative
evmhogsmian
rD,rA,rB
Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and
Accumulate
evmhogumiaa
rD,rA,rB
Multiply Half Words, Odd, Guarded, Unsigned, Modulo, Integer and
Accumulate Negative
evmhogumian
rD,rA,rB
Vector Absolute Value
evabs
rD,rA
Vector Add Immediate Word
evaddiw
rD,rB,UIMM
Vector Add Signed, Modulo, Integer to Accumulator Word
evaddsmiaaw
rD,rA,rB
Vector Add Signed, Saturate, Integer to Accumulator Word
evaddssiaaw
rD,rA
Vector Add Unsigned, Modulo, Integer to Accumulator Word
evaddumiaaw
rD,rA
Vector Add Unsigned, Saturate, Integer to Accumulator Word
evaddusiaaw
rD,rA
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Add Word
evaddw
rD,rA,rB
Vector AND
evand
rD,rA,rB
Vector AND with Complement
evandc
rD,rA,rB
Vector Compare Equal
evcmpeq
crD,rA,rB
Vector Compare Greater Than Signed
evcmpgts
crD,rA,rB
Vector Compare Greater Than Unsigned
evcmpgtu
crD,rA,rB
Vector Compare Less Than Signed
evcmplts
crD,rA,rB
Vector Compare Less Than Unsigned
evcmpltu
crD,rA,rB
Vector Convert Floating-Point from Signed Fraction
evfscfsf
rD,rB
Vector Convert Floating-Point from Signed Integer
evfscfsi
rD,rB
Vector Convert Floating-Point from Unsigned Fraction
evfscfuf
rD,rB
Vector Convert Floating-Point from Unsigned Integer
evfscfui
rD,rB
Vector Convert Floating-Point to Signed Fraction
evfsctsf
rD,rB
Vector Convert Floating-Point to Signed Integer
evfsctsi
rD,rB
Vector Convert Floating-Point to Signed Integer with Round toward Zero
evfsctsiz
rD,rB
Vector Convert Floating-Point to Unsigned Fraction
evfsctuf
rD,rB
Vector Convert Floating-Point to Unsigned Integer
evfsctui
rD,rB
Vector Convert Floating-Point to Unsigned Integer with Round toward Zero
evfsctuiz
rD,rB
Vector Count Leading Sign Bits Word
evcntlsw
rD,rA
Vector Count Leading Zeros Word
evcntlzw
rD,rA
Vector Divide Word Signed
evdivws
rD,rA,rB
Vector Divide Word Unsigned
evdivwu
rD,rA,rB
Vector Equivalent
eveqv
rD,rA,rB
Vector Extend Sign Byte
evextsb
rD,rA
Vector Extend Sign Half Word
evextsh
rD,rA
Vector Floating-Point Absolute Value
evfsabs
rD,rA
Vector Floating-Point Add
evfsadd
rD,rA,rB
Vector Floating-Point Compare Equal
evfscmpeq
crD,rA,rB
Vector Floating-Point Compare Greater Than
evfscmpgt
crD,rA,rB
Vector Floating-Point Compare Less Than
evfscmplt
crD,rA,rB
Vector Floating-Point Divide
evfsdiv
rD,rA,rB
Vector Floating-Point Multiply
evfsmul
rD,rA,rB
Vector Floating-Point Negate
evfsneg
rD,rA
Vector Floating-Point Negative Absolute Value
evfsnabs
rD,rA
Vector Floating-Point Subtract
evfssub
rD,rA,rB
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Floating-Point Test Equal
evfststeq
crD,rA,rB
Vector Floating-Point Test Greater Than
evfststgt
crD,rA,rB
Vector Floating-Point Test Less Than
evfststlt
crD,rA,rB
Vector Load Double into Half Words
evldh
rD,d(rA)
Vector Load Double into Half Words Indexed
evldhx
rD,rA,rB
Vector Load Double into Two Words
evldw
rD,d(rA)
Vector Load Double into Two Words Indexed
evldwx
rD,rA,rB
Vector Load Double Word into Double Word
evldd
rD,d(rA)
Vector Load Double Word into Double Word Indexed
evlddx
rD,rA,rB
Vector Load Half Word into Half Word Odd Signed and Splat
evlhhossplat
rD,d(rA)
Vector Load Half Word into Half Word Odd Signed and Splat Indexed
evlhhossplatx
rD,rA,rB
Vector Load Half Word into Half Word Odd Unsigned and Splat
evlhhousplat
rD,d(rA)
Vector Load Half Word into Half Word Odd Unsigned and Splat Indexed
evlhhousplatx
rD,rA,rB
Vector Load Half Word into Half Words Even and Splat
evlhhesplat
rD,d(rA)
Vector Load Half Word into Half Words Even and Splat Indexed
evlhhesplatx
rD,rA,rB
Vector Load Word into Half Words and Splat
evlwhsplat
rD,d(rA)
Vector Load Word into Half Words and Splat Indexed
evlwhsplatx
rD,rA,rB
Vector Load Word into Half Words Odd Signed (with sign extension)
evlwhos
rD,d(rA)
Vector Load Word into Half Words Odd Signed Indexed (with sign extension)
evlwhosx
rD,rA,rB
Vector Load Word into Two Half Words Even
evlwhe
rD,d(rA)
Vector Load Word into Two Half Words Even Indexed
evlwhex
rD,rA,rB
Vector Load Word into Two Half Words Odd Unsigned (zero-extended)
evlwhou
rD,d(rA)
Vector Load Word into Two Half Words Odd Unsigned Indexed (zero-extended) evlwhoux
rD,rA,rB
Vector Load Word into Word and Splat
evlwwsplat
rD,d(rA)
Vector Load Word into Word and Splat Indexed
evlwwsplatx
rD,rA,rB
Vector Merge High
evmergehi
rD,rA,rB
Vector Merge High/Low
evmergehilo
rD,rA,rB
Vector Merge Low
evmergelo
rD,rA,rB
Vector Merge Low/High
evmergelohi
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Fractional
evmhesmf
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate
into Words
evmhesmfaaw
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Fractional and Accumulate
Negative into Words
evmhesmfanw
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Fractional, Accumulate
evmhesmfa
rD,rA,rB
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Multiply Half Words, Even, Signed, Modulo, Integer
evmhesmi
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate
into Words
evmhesmiaaw
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Integer and Accumulate
Negative into Words
evmhesmianw
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Modulo, Integer, Accumulate
evmhesmia
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Fractional
evmhessf
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate
evmhessfaaw
into Words
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Fractional and Accumulate
evmhessfanw
Negative into Words
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Fractional, Accumulate
evmhessfa
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate
into Words
evmhessiaaw
rD,rA,rB
Vector Multiply Half Words, Even, Signed, Saturate, Integer and Accumulate
Negative into Words
evmhessianw
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer
evmheumi
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate
into Words
evmheumiaaw
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer and Accumulate
Negative into Words
evmheumianw
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Modulo, Integer, Accumulate
evmheumia
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate
evmheusiaaw
into Words
rD,rA,rB
Vector Multiply Half Words, Even, Unsigned, Saturate, Integer and Accumulate
evmheusianw
Negative into Words
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional
evmhosmf
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate
into Words
evmhosmfaaw
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional and Accumulate
Negative into Words
evmhosmfanw
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Fractional, Accumulate
evmhosmfa
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Integer
evmhosmi
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate into
evmhosmiaaw
Words
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Integer and Accumulate
Negative into Words
evmhosmianw
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Modulo, Integer, Accumulate
evmhosmia
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional
evmhossf
rD,rA,rB
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate
evmhossfaaw
into Words
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional and Accumulate
evmhossfanw
Negative into Words
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Saturate, Fractional, Accumulate
evmhossfa
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate
into Words
evmhossiaaw
rD,rA,rB
Vector Multiply Half Words, Odd, Signed, Saturate, Integer and Accumulate
Negative into Words
evmhossianw
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer
evmhoumi
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate
into Words
evmhoumiaaw
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer and Accumulate
Negative into Words
evmhoumianw
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Modulo, Integer, Accumulate
evmhoumia
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate
into Words
evmhousiaaw
rD,rA,rB
Vector Multiply Half Words, Odd, Unsigned, Saturate, Integer and Accumulate
Negative into Words
evmhousianw
rD,rA,rB
Vector Multiply Word High Signed, Modulo, Fractional
evmwhsmf
rD,rA,rB
Vector Multiply Word High Signed, Modulo, Fractional and Accumulate
evmwhsmfa
rD,rA,rB
Vector Multiply Word High Signed, Modulo, Integer
evmwhsmi
rD,rA,rB
Vector Multiply Word High Signed, Modulo, Integer and Accumulate
evmwhsmia
rD,rA,rB
Vector Multiply Word High Signed, Saturate, Fractional
evmwhssf
rD,rA,rB
Vector Multiply Word High Signed, Saturate, Fractional and Accumulate
evmwhssfa
rD,rA,rB
Vector Multiply Word High Unsigned, Modulo, Integer
evmwhumi
rD,rA,rB
Vector Multiply Word High Unsigned, Modulo, Integer and Accumulate
evmwhumia
rD,rA,rB
Vector Multiply Word Low Signed, Modulo, Integer and Accumulate in Words
evmwlsmiaaw
rD,rA,rB
Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in
evmwlsmianw
Words
rD,rA,rB
Vector Multiply Word Low Signed, Saturate, Integer and Accumulate in Words
evmwlssiaaw
rD,rA,rB
Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative
in Words
evmwlssianw
rD,rA,rB
Vector Multiply Word Low Unsigned, Modulo, Integer
evmwlumi
rD,rA,rB
Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate
evmwlumia
rD,rA,rB
Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate in Words evmwlumiaaw
rD,rA,rB
Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative
evmwlumianw
in Words
rD,rA,rB
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate in
Words
evmwlusiaaw
rD,rA,rB
Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate
Negative in Words
evmwlusianw
rD,rA,rB
Vector Multiply Word Signed, Modulo, Fractional
evmwsmf
rD,rA,rB
Vector Multiply Word Signed, Modulo, Fractional and Accumulate
evmwsmfa
rD,rA,rB
Vector Multiply Word Signed, Modulo, Fractional and Accumulate
evmwsmfaa
rD,rA,rB
Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative
evmwsmfan
rD,rA,rB
Vector Multiply Word Signed, Modulo, Integer
evmwsmi
rD,rA,rB
Vector Multiply Word Signed, Modulo, Integer and Accumulate
evmwsmia
rD,rA,rB
Vector Multiply Word Signed, Modulo, Integer and Accumulate
evmwsmiaa
rD,rA,rB
Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative
evmwsmian
rD,rA,rB
Vector Multiply Word Signed, Saturate, Fractional
evmwssf
rD,rA,rB
Vector Multiply Word Signed, Saturate, Fractional and Accumulate
evmwssfa
rD,rA,rB
Vector Multiply Word Signed, Saturate, Fractional and Accumulate
evmwssfaa
rD,rA,rB
Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative
evmwssfan
rD,rA,rB
Vector Multiply Word Unsigned, Modulo, Integer
evmwumi
rD,rA,rB
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate
evmwumia
rD,rA,rB
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate
evmwumiaa
rD,rA,rB
Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative
evmwumian
rD,rA,rB
Vector NAND
evnand
rD,rA,rB
Vector Negate
evneg
rD,rA
Vector NOR
evnor
rD,rA,rB
Vector OR
evor
rD,rA,rB
Vector OR with Complement
evorc
rD,rA,rB
Vector Rotate Left Word
evrlw
rD,rA,rB
Vector Rotate Left Word Immediate
evrlwi
rD,rA,UIMM
Vector Round Word
evrndw
rD,rA
Vector Select
evsel
rD,rA,rB,crS
Vector Shift Left Word
evslw
rD,rA,rB
Vector Shift Left Word Immediate
evslwi
rD,rA,UIMM
Vector Shift Right Word Immediate Signed
evsrwis
rD,rA,UIMM
Vector Shift Right Word Immediate Unsigned
evsrwiu
rD,rA,UIMM
Vector Shift Right Word Signed
evsrws
rD,rA,rB
Vector Shift Right Word Unsigned
evsrwu
rD,rA,rB
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Table 108. SPE APU vector instructions (continued)
Instruction
Mnemonic
Syntax
Vector Splat Fractional Immediate
evsplatfi
rD,SIMM
Vector Splat Immediate
evsplati
rD,SIMM
Vector Store Double of Double
evstdd
rS,d(rA)
Vector Store Double of Double Indexed
evstddx
rS,rA,rB
Vector Store Double of Four Half Words
evstdh
rS,d(rA)
Vector Store Double of Four Half Words Indexed
evstdhx
rS,rA,rB
Vector Store Double of Two Words
evstdw
rS,d(rA)
Vector Store Double of Two Words Indexed
evstdwx
rS,rA,rB
Vector Store Word of Two Half Words from Even
evstwhe
rS,d(rA)
Vector Store Word of Two Half Words from Even Indexed
evstwhex
rS,rA,rB
Vector Store Word of Two Half Words from Odd
evstwho
rS,d(rA)
Vector Store Word of Two Half Words from Odd Indexed
evstwhox
rS,rA,rB
Vector Store Word of Word from Even
evstwwex
rS,d(rA)
Vector Store Word of Word from Even Indexed
evstwwex
rS,rA,rB
Vector Store Word of Word from Odd
evstwwo
rS,d(rA)
Vector Store Word of Word from Odd Indexed
evstwwox
rS,rA,rB
Vector Subtract from Word
evsubfw
rD,rA,rB
Vector Subtract Immediate from Word
evsubifw
rD,UIMM,rB
Vector Subtract Signed, Modulo, Integer to Accumulator Word
evsubfsmiaaw
rD,rA
Vector Subtract Signed, Saturate, Integer to Accumulator Word
evsubfssiaaw
rD,rA
Vector Subtract Unsigned, Modulo, Integer to Accumulator Word
evsubfumiaaw
rD,rA
Vector Subtract Unsigned, Saturate, Integer to Accumulator Word
evsubfusiaaw
rD,rA
Vector XOR
evxor
rD,rA,rB
4.6.1.2
Embedded vector and scalar floating-point APU instructions
The embedded floating-point operations are IEEE-compliant with software exception
handlers and offer a simpler exception model than the floating-point instructions defined by
the PowerPC ISA. Instead of FPRs, these instructions use GPRs to offer improved
performance for converting between floating-point, integer, and fractional values. Sharing
GPRs allows vector floating-point instructions to use SPE load and store instructions.
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The SPFP APUs are described as follows:
Note:

Vector SPFP instructions operate on a vector of two 32-bit, single-precision floatingpoint numbers that reside in the upper and lower halves of the 64-bit GPRs. These
instructions are listed in Table 117 alongside their scalar equivalents.

Scalar SPFP instructions operate on single 32-bit operands that reside in the lower 32bits of the GPRs. These instructions are listed in Table 117.

Scalar DPFP instructions operate on single 64-bit double-precision operands that
reside in the 64-bit GPRs. These instructions are listed in Table 109.
Note that the vector and scalar versions of the instructions have the same syntax.
Table 109. Vector and scalar floating-point APU instructions
Single-precision
Scalar
Vector
Doubleprecision
scalar
—
—
efdcfs
rD,rB
Convert Floating-Point from Signed Fraction
efscfsf
evfscfsf
efdcfsf
rD,rB
Convert Floating-Point from Signed Integer
efscfsi
evfscfsi
efdcfsi
rD,rB
Convert Floating-Point from Unsigned Fraction
efscfuf
evfscfuf
efdcfuf
rD,rB
Convert Floating-Point from Unsigned Integer
efscfui
evfscfui
efdcfui
rD,rB
—
—
efscfd
rD,rB
Convert Floating-Point to Signed Fraction
efsctsf
evfsctsf
efdctsf
rD,rB
Convert Floating-Point to Signed Integer
efsctsi
evfsctsi
efdctsi
rD,rB
Convert Floating-Point to Signed Integer with Round
toward Zero
efsctsiz
evfsctsiz
efdctsiz
rD,rB
Convert Floating-Point to Unsigned Fraction
efsctuf
evfsctuf
efdctuf
rD,rB
Convert Floating-Point to Unsigned Integer
efsctui
evfsctui
efdctui
rD,rB
Convert Floating-Point to Unsigned Integer with Round
toward Zero
efsctuiz
evfsctuiz
efdctuiz
rD,rB
efsabs (1)
evfsabs
efdabs
rD,rA
efsadd
evfsadd
efdadd
rD,rA,rB
Floating-Point Compare Equal
efscmpeq
evfscmpeq
efdcmpeq
crD,rA,rB
Floating-Point Compare Greater Than
efscmpgt
evfscmpgt
efdcmpgt
crD,rA,rB
Floating-Point Compare Less Than
efscmplt
evfscmplt
efdcmplt
crD,rA,rB
Floating-Point Divide
efsdiv
evfsdiv
efddiv
rD,rA,rB
Floating-Point Multiply
efsmul
evfsmul
efdmul
rD,rA,rB
evfsneg
efdneg
rD,rA
evfsnabs
efdnabs
rD,rA
Instruction
Convert Floating-Point Double- from Single-Precision
Convert Floating-Point Single- from Double-Precision
Floating-Point Absolute Value
Floating-Point Add
Floating-Point Negate
Floating-Point Negative Absolute Value
efsneg
(1)
efsnabs
(1)
Syntax
Floating-Point Subtract
efssub
evfssub
efdsub
rD,rA,rB
Floating-Point Test Equal
efststeq
evfststeq
efdtsteq
crD,rA,rB
Floating-Point Test Greater Than
efststgt
evfststgt
efdtstgt
crD,rA,rB
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Instruction model
Table 109. Vector and scalar floating-point APU instructions (continued)
Single-precision
Scalar
Vector
Doubleprecision
scalar
efststlt
evfststlt
efdtstlt
crD,rA,rB
Vector Load Double Word into Double Word
—
evldd
evldd
rD,d(rA)
Vector Load Double Word into Double Word Indexed
—
evlddx
evlddx
rD,rA,rB
Vector Merge High
—
evmergehi
evmergehi
rD,rA,rB
Vector Merge Low
—
evmergelo
evmergelo
rD,rA,rB
Vector Store Double of Double
—
evstdd
evstdd
rS,d(rA)
Vector Store Double of Double Indexed
—
evstddx
evstddx
rS,rA,rB
Instruction
Floating-Point Test Less Than
Syntax
SPE Double Word Load/Store Instructions
On some cores, floating-point operations that produce a result of zero may generate an incorrect sign.
1. Exception detection for these instructions is implementation dependent. On some devices, Infinities, NaNs, and Denorms
are always be treated as Norms. No exceptions are taken if SPEFSCR[FINVE] = 1.
4.6.2
Integer select (isel) APU
The integer select APU consists of the isel instruction, a conditional register move that
helps eliminate branches. Section 8.1: Integer select APU, describes the use of isel.
Table 110. Integer select APU instruction
4.6.3
Name
Mnemonic
Syntax
Integer Select
isel
rD,rA,rB,crB
Performance monitor APU
The EIS defines the performance monitor as an APU. Software communication with the
performance monitor APU is achieved through performance monitor registers (PMRs) rather
than SPRs. New instructions are provided to move to and from these PMRs. Performance
monitor APU instructions are described in Table 111.
Table 111. Performance monitor APU instructions
Name
Mnemonic
Syntax
Move from performance monitor
register
mfpmr
rD,PMRN
Move to performance monitor
register
mtpmr
PMRN,rS
The Book E implementation standards defines a set of register resources used exclusively
by the performance monitor. PMRs are similar to the SPRs defined in the Book E
architecture and are accessed by mtpmr and mfpmr, which are also defined by the EIS.
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Table 112 lists supervisor-level PMRs. User-level software that attempts to read or write
supervisor-level PMRs causes a privilege exception.
Table 112. Performance monitor registers—supervisor level
Abbreviation
Register name
PMR number
pmr[0–4]
pmr[5–9]
Section/page
Section 3.16.1
on page 126
PMGC0
Performance
monitor global
control register 0
400
01100
10000
PMLCa0
Performance
monitor local
control a0
144
00100
10000
PMLCa1
Performance
monitor local
control a1
145
00100
10001
PMLCa2
Performance
monitor local
control a2
146
00100
10010
PMLCa3
Performance
monitor local
control a3
147
00100
10011
PMLCb0
Performance
monitor local
control b0
272
01000
10000
PMLCb1
Performance
monitor local
control b1
273
01000
10001
PMLCb2
Performance
monitor local
control b2
274
01000
10010
PMLCb3
Performance
monitor local
control b3
275
01000
10011
PMC0
Performance
monitor counter 0
16
00000
10000
PMC1
Performance
monitor counter 1
17
00000
10001
PMC2
Performance
monitor counter 2
18
00000
10010
PMC3
Performance
monitor counter 3
19
00000
10011
Section 3.16.3
on page 127
Section 3.16.5
on page 128
Section 3.16.7
on page 130
User-level PMRs in Table 113 are read-only and are accessed with mfpmr. Attempting to
write user-level registers in supervisor or user mode causes an illegal instruction exception.
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Table 113. Performance monitor registers—user level (read-only)
4.6.4
Abbreviation
Register Name
PMR
Number
UPMGC0
User performance monitor global
control register 0
384
01100
00000
UPMLCa0
User performance monitor local
control a0
128
00100
00000
UPMLCa1
User performance monitor local
control a1
129
00100
00001
UPMLCa2
User performance monitor local
control a2
130
00100
00010
UPMLCa3
User performance monitor local
control a3
131
00100
00011
UPMLCb0
User performance monitor local
control b0
256
01000
00000
UPMLCb1
User performance monitor local
control b1
257
01000
00001
UPMLCb2
User performance monitor local
control b2
258
01000
00010
UPMLCb3
User performance monitor local
control b3
259
01000
00011
pmr[0–4] pmr[5–9] Section/Page
Section 3.16.2
on page 127
Section 3.16.4
on page 128
Section 3.16.6
on page 130
UPMC0
User performance monitor
counter 0
0
00000
00000
UPMC1
User performance monitor
counter 1
1
00000
00001
UPMC2
User performance monitor
counter 2
2
00000
00010
UPMC3
User performance monitor
counter 3
3
00000
00011
Section 3.16.8
on page 130
Cache locking APU
This section describes the instructions in the cache locking APU, which consists of the
instructions described in Table 114. Lines are locked into the cache by software using a
series of touch and lock set instructions. The following instructions are provided to lock data
items into the data and instruction cache:

dcbtls—Data Cache Block Touch and Lock Set

dcbtstls—Data Cache Block Touch for Store and Lock Set

icbtls—Instruction Cache Block Touch and Lock Set
The rA and rB operands to these instructions form a EA identifying the line to be locked.
The CT field indicates which cache in the cache hierarchy should be targeted. These
instructions are similar to the dcbt, dcbtst, and icbt instructions, but locking instructions
can not execute speculatively and may cause additional exceptions. For unified caches,
both the instruction lock set and the data lock set target the same cache.
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Similarly, lines are unlocked from the cache by software using a series of lock-clear
instructions. The following instructions are provided to lock instructions into the instruction
cache:

dcblc—Data Cache Block Lock Clear

icblc—Instruction Cache Block Lock Clear
The rA and rB operands to these instructions form an EA identifying the line to be unlocked.
The CT field indicates which cache in the cache hierarchy should be targeted.
Additionally, software may clear all the locks in the cache. For the primary cache, this is
accomplished by setting the CLFC (DCLFC, ICLFC) bit in L1CSR0 (L1CSR1).
Cache lines can also be implicitly unlocked in the following ways:

A locked line is invalidated if it is targeted by a dcbi, dcbf, or icbi instruction.

A snoop hit on a locked line that requires the line to be invalidated. This can occur
because the data the line contains has been modified external to the processor, or
another processor has explicitly invalidated the line.

The entire cache containing the locked line is flash invalidated.
An implementation is not required to unlock lines if data is invalidated in the cache. Although
the data may be invalidated (and thus not in the cache), the cache can keep the lock
associated with that cache line present and fill the line from the memory subsystem when
the next access occurs. If the implementation does not clear locks when the associated line
is invalidated, the method of locking is said to be persistent. An implementation may choose
to implement locks as persistent or not persistent; the preferred method is persistent.
Table 114. Cache locking APU instructions
Name
Mnemonic
Syntax
Description
Data Cache Block Lock
Clear
dcblc
Treated as a load with respect to any memory
CT,rA,rB barriers, synchronization, translation and
protection, and debug address comparisons.
Data Cache Block Touch and
Lock Set
dcbtls
Treated as a load with respect to any memory
CT,rA,rB barriers, synchronization, translation and
protection, and debug address comparisons.
It is implementation dependent whether this
instruction is treated as a load or store with
CT,rA,rB respect to any memory barriers,
synchronization, translation and protection,
and debug address comparisons.
Data Cache Block Touch for
Store and Lock Set
dcbtstls
Instruction Cache Block Lock
Clear
icblc
Treated as a load with respect to any memory
CT,rA,rB barriers, synchronization, translation and
protection, and debug address comparisons.
Instruction Cache Block
Touch and Lock Set
icbtls
Treated as a load with respect to any memory
CT,rA,rB barriers, synchronization, translation and
protection, and debug address comparisons.
The cache-locking APU defines a flash clear for all data cache lock bits (using
L1CSR0[CLFR]) and in the instruction cache (using L1CSR1[ICLFR]). This allows system
software to clear all data cache locking bits without knowing the addresses of the lines
locked.
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Instruction model
Machine check APU
The machine check APU defines a separate interrupt type for machine check interrupts. It
provides additional save and restore SPRs (MCSRR and MCSRR1). The Return from
Machine Check Interrupt instruction (rfmci), is described in Table 115.
Table 115. Machine check APU instruction
Name
Mnemonic Syntax
Return from machine check
interrupt
4.6.6
rfmci
—
Implementation notes
Restores MCSRR0 and MCSRR1 values;
context-synchronizing.
VLE extension
This section lists instructions defined or supported by the VLE extension. Unless otherwise
noted, instructions that are not prefixed with e_ or se_ have identical encodings and
semantics as in Book E or in the EIS. Book E–defined instructions listed in the tables in this
section can be executed when the processor is in VLE mode; Book E instructions not listed
cannot.
A complete list of supported instructions is provided in Section 4.6.6.11: Instruction listings.
4.6.6.1
Processor control instructions
This section lists processor control instructions that can be executed when a processor is in
VLE mode. These instructions are grouped as follows:
4.6.6.1.1

Section 4.6.6.1.1: System linkage instructions

Section 4.6.6.1.2: Processor control register manipulation instructions

Section 4.6.6.2: Instruction synchronization instruction
System linkage instructions
The se_sc, se_rfi, se_rfci, and se_rfdi system linkage instructions, shown in Table 116,
enable a program to call on the system to perform a service (that is, invoke a system call
interrupt), and enable the system to return from performing a service or from processing an
interrupt.
Table 116. System linkage instruction set index
Mnemonic
Instruction
Reference
se_sc
System Call
Section on
page 769
se_rfci`
Return from critical interrupt
Section on
page 767
se_rfdi
Return from debug interrupt
Section on
page 704
se_rfi
Return from interrupt
Section on
page 767
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4.6.6.1.2
RM0004
Processor control register manipulation instructions
In addition to the Book E processor control register manipulation instructions, the VLE
extension provides 16-bit forms of instructions to move to/from the LR and CTR, listed in
Table 117
Table 117. System register manipulation instruction set index
Mnemonic
4.6.6.2
Instruction
Reference
Section on
page 762
se_mfctr rX
Move From Count Register
mfdcr rD,DCRN
Move From Device Control Register
se_mflr rX
Move From Link Register
mfmsr rD
Move From Machine State Register
Book E
mfspr rD,SPRN
Move From Special Purpose Register
Book E
se_mtctr rX
Move To Count Register
mtdcr DCRN,rS
Move To Device Control Register
se_mtlr rX
Move To Link Register
mtmsr rS
Move To Machine State Register
Book E
mtspr SPRN,rS
Move To Special Purpose Register
Book E
wrtee rA
Write MSR External Enable
Book E
wrteei E
Write MSR External Enable Immediate
Book E
Book E
Section on
page 762
Section on
page 763
Book E
Section on
page 763
Instruction synchronization instruction
Table 118 lists the VLE-defined se_isync instruction.
Table 118. Instruction Synchronization Instruction Set Index
4.6.6.3
Mnemonic
Instruction
Reference
se_isync
Instruction Synchronize
Section on
page 757
Branch operation instructions
This section lists branch instructions that can be executed when a processor is in VLE
mode. It also describes the registers that support them.
Registers for branch operations
The sections listed in the following describe the registers that support branch operations:
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
Section 3.5.1: Condition register (CR)

Section 3.5.2: Link register (LR)

Section 3.5.3: Count register (CTR)
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4.6.6.3.1
Instruction model
Branch instructions
The sequence of instruction execution can be changed by the branch instructions. Because
VLE instructions must be aligned on half-word boundaries, the low-order bit of the
generated branch target address is forced to 0 by the processor in performing the branch.
The branch instructions compute the EA of the target in one of the following ways, as
described in Section 11.2: Instruction memory addressing modes.
1.
Adding a displacement to the address of the branch instruction.
2.
Using the address contained in the LR (Branch to Link Register [and Link]).
3.
Using the address contained in the CTR (Branch to Count Register [and Link]).
Branching can be conditional or unconditional, and the return address can optionally be
provided. If the return address is to be provided (LK = 1), the EA of the instruction following
the branch instruction is placed into the LR after the branch target address has been
computed: this is done whether or not the branch is taken.
In branch conditional instructions, the BI32 or BI16 instruction field specifies the CR bit to be
tested. For 32-bit instructions using BI32, CR[32–47] (corresponding to bits in CR0–CR3)
may be specified. For 16-bit instructions using BI16, only CR[32–35] (bits within CR0) may
be specified.
In branch conditional instructions, the BO32 or BO16 field specifies the conditions under
which the branch is taken and how the branch is affected by or affects the CR and CTR.
Note that VLE instructions also have different encodings for the BO32 and BO16 fields than
in Book E’s BO field.
If the BO32 field specifies that the CTR is to be decremented, CTR[32–63] are
decremented. If BO[16,32] specifies a condition that must be TRUE or FALSE, that
condition is obtained from the contents of CR[BI+32]. (Note that CR bits are numbered 32–
63. BI refers to the BI field in the branch instruction encoding. For example, specifying BI = 2
refers to CR[34].)
Encodings for the BO32 field for the VLE extension are shown in Table 120.
Table 119. VLE extension BO32 encodings
BO32
Description
00
Branch if the condition is FALSE.
01
Branch if the condition is TRUE.
10
Decrement CTR[32–63], then branch if the decremented CTR[32–63]0.
11
Decrement CTR[32–63], then branch if the decremented CTR[32–63] = 0.
The encoding for the BO16 field for the VLE extension is shown in Table 120.
Table 120. VLE extension BO16 encodings
BO16
Description
0
Branch if the condition is FALSE.
1
Branch if the condition is TRUE.
The various branch instructions supported by the VLE extension are shown in Table 121.
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Table 121. Branch instruction set index
Mnemonic
4.6.6.4
Instruction
Reference
e_b BD24
e_bl BD24
Branch
Branch & Link
Section
on page
744
se_b BD8
se_bl BD8
Branch
Branch & Link
Section
on page
744
e_bc BO32,BI32,BD15
se_bc BO16,BI16,BD8
e_bcl BO32,BI32,BD15
Branch Conditional
Branch Conditional
Branch Conditional & Link
Section
on page
745
se_bctr
se_bctrl
Branch to Count Register
Branch to Count Register & Link
Section
on page
746
se_blr
se_blrl
Branch to Link Register
Branch to Link Register & Link
Section
on page
747
Condition register instructions
Condition register instructions are provided to transfer values to/from various portions of the
CR. The VLE extension does not introduce any additional functionality beyond that defined
in Book E for CR operations, but does remap the CR-logical and mcrf instruction
functionality into major opcode 31. These instructions operate identically to the Book E
instructions, but are encoded differently. Table 122 lists condition register instructions
supported in VLE mode.
Table 122. Condition register instruction set index
Mnemonic
e_crand crbD,crbA,crbB
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Instruction
Condition Register AND
Reference
Section on
page 753
e_crandc crbD,crbA,crbB Condition Register AND with Complement
Section on
page 753
e_creqv crbD,crbA,crbB
Section on
page 753
Condition Register Equivalent
e_crnand crbD,crbA,crbB Condition Register NAND
Section on
page 754
e_crnor crbD,crbA,crbB
Condition Register NOR
Section on
page 754
e_cror crbD,crbA,crbB
Condition Register OR
Section on
page 755
e_crorc crbD,crbA,crbB
Condition Register OR with Complement
Section on
page 755
e_crxor crbD,crbA,crbB
Condition Register XOR
Section on
page 755
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Instruction model
Table 122. Condition register instruction set index
Mnemonic
4.6.6.5
Instruction
Reference
Section on
page 761
e_mcrf crD,crS
Move Condition Register Field
mcrxr crD
Move to Condition Register from Integer Exception
Register
Book E
mfcr rD
Move From condition register
Book E
mtcrf FXM,rS
Move to Condition Register Fields
Book E
Integer instructions
This section lists the integer instructions supported by the VLE extension.
4.6.6.5.1
Integer load instructions
The integer load instructions, listed in Table 123, compute the EA of the memory to be
accessed as described in Section 11.1: Data memory addressing modes.
The byte, half word, or word in memory addressed by EA is loaded into GPR(rD) or
GPR(rZ).
The VLE extension supports both big- and little-endian byte ordering for data accesses.
Some integer load instructions have an update form in which GPR(rA) is updated with the
EA. For these forms, if rA0 and rA rD, the EA is placed into GPR(rA) and the memory
element (byte, half word, word, or double word) addressed by EA is loaded into GPR(rD). If
rA = 0 or rA = rD, the instruction form is invalid. This is the same behavior as specified for
load with update instructions in Book E.
Table 123. Basic integer load instruction set index
Mnemonic
Instruction
e_lbz rD,D(rA)
e_lbzu rD,D8(rA)
se_lbz rZ,SD4(rX)
Load Byte and Zero
Load Byte and Zero with Update
Load Byte and Zero (16-bit form)
lbzx rD,rA,rB
lbzux rD,rA,rB
Load Byte and Zero Indexed
Load Byte and Zero with Update Indexed
e_lha rD,D(rA)
e_lhau rD,D8(rA)
Load Halfword Algebraic
Load Halfword Algebraic with Update
lhax rD,rA,rB
lhaux rD,rA,rB
Load Halfword Algebraic Indexed
Load Halfword Algebraic with Update Indexed
e_lhz rD,D(rA)
e_lhzu rD,D8(rA)
se_lhz rZ,SD4(rX)
Load Halfword and Zero
Load Halfword and Zero with Update
Load Halfword and Zero (16-bit form)
lhzx rD,rA,rB
lhzux rD,rA,rB
Load Halfword and Zero Indexed
Load Halfword and Zero with Update Indexed
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page 757
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Section on
page 758
Book E
Section on
page 759
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Table 123. Basic integer load instruction set index
Mnemonic
Instruction
e_lwz rD,D(rA)
e_lwzu rD,D8(rA)
se_lwz rZ,SD4(rX)
Load Word and Zero
Load Word and Zero with Update
Load Word and Zero (16-bit form)
lwzx rD,rA,rB
lwzux rD,rA,rB
Load Word and Zero Indexed
Load Word and Zero with Update Indexed
Reference
Section on
page 761
Book E
Integer load byte-reversed instructions are listed in Table 124.
Table 124. Integer load byte-reverse instruction set index
Mnemonic
Instruction
Reference
lhbrx rD,rA,rB
Load Halfword Byte-Reverse Indexed
Book E
lwbrx rD,rA,rB
Load Word Byte-Reverse Indexed
Book E
The VLE-defined integer load multiple instruction is listed in Table 125.
Table 125. Integer load multiple instruction set index
Mnemonic
e_lmw rD,D8(rA)
Instruction
Reference
Section on
page 760
Load Multiple Word
The VLE-defined integer load and reserve instruction is listed in Table 126.
Table 126. Integer load and reserve instruction set index
Mnemonic
lwarx rD,rA,rB
4.6.6.5.2
Instruction
Load Word And Reserve Indexed
Reference
Book E
Integer store instructions
The integer store instructions compute the EA of the memory to be accessed as described
in Section 11.1: Data memory addressing modes.”
The contents of GPR(rS) or GPR(rZ) are stored into the byte, half word, or word in memory
addressed by EA.
The VLE extension supports both big- and little-endian byte ordering for data accesses.
Some integer store instructions have an update form, in which GPR(rA) is updated with the
EA. For these forms, the following rules (from Book E) apply.

If rA0, the EA is placed into GPR(rA).

If rS = rA, the contents of GPR(rS) are copied to the target memory element and then
EA is placed into GPR(rA).
The basic integer store instructions are listed in Table 127.
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Table 127. Basic integer store instruction set index
Mnemonic
Instruction
e_stb rS,D(rA)
e_stbu rS,D8(rA)
se_stb rZ,SD4(rX)
Store Byte
Store Byte with Update
Store Byte (16-bit form)
stbx rS,rA,rB
stbux rS,rA,rB
Store Byte Indexed
Store Byte with Update Indexed
e_sth rS,D(rA)
e_sthu rS,D8(rA)
se_sth rZ,SD4(rX)
Store Halfword
Store Halfword with Update
Store Halfword (16-bit form)
sthx rS,rA,rB
sthux rS,rA,rB
Store Halfword Indexed
Store Halfword with Update Indexed
e_stw rS,D(rA)
e_stwu rS,D8(rA)
se_stw rZ,SD4(rX)
Store Word
Store Word with Update
Store Word (16-bit form)
stwx rS,rA,rB
stwux rS,rA,rB
Store Word Indexed
Store Word with Update Indexed
Reference
Section on
page 773
Book E
Section on
page 773
Book E
Section on
page 775
Book E
The integer store byte-reverse instructions are listed in Table 128.
Table 128. Integer store byte-reverse instruction set index
Mnemonic
Instruction
Reference
sthbrx rS,rA,rB
Store Halfword Byte-Reverse Indexed
Book E
stwbrx rS,rA,rB
Store Word Byte-Reverse Indexed
Book E
The integer store multiple instruction is listed in Table 129.
Table 129. Integer store multiple instruction set index
Mnemonic
e_stmw rS,D8(rA)
Instruction
Store Multiple Word
Reference
Section on page 774
The integer store conditional instruction is listed in Table 130.
Table 130. Integer store conditional instruction set index
Mnemonic
stwcx. rS,rA,rB
4.6.6.5.3
Instruction
Store Word Conditional Indexed
Reference
Book E
Integer arithmetic instructions
The integer arithmetic instructions use the contents of the GPRs as source operands, and
place results into GPRs, into status bits in the XER and into CR0.
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The integer arithmetic instructions treat source operands as signed, two’s complement
integers unless the instruction is explicitly identified as performing an unsigned operation.
The e_add2i. instruction and the OIM5-form instruction, se_subi., set the first three bits of
CR0 to characterize bits 32–63 of the result. These bits are set by signed comparison of bits
32–63 of the result to zero.
e_addic[.] and e_subfic[.] always set CA to reflect the carry out of bit 32.
The integer arithmetic instructions are listed in Table 131.
Table 131. Integer arithmetic instruction set index
Mnemonic
212/1025
Instruction
Reference
add rD,rA,rB
add. rD,rA,rB
addo rD,rA,rB
addo. rD,rA,rB
Add
Book E
se_add rX,rY
Add
Section on
page 741
addc rD,rA,rB
addc. rD,rA,rB
addco rD,rA,rB
addco. rD,rA,rB
Add Carrying
Book E
adde rD,rA,rB
adde. rD,rA,rB
addeo rD,rA,rB
addeo. rD,rA,rB
Add Extended
Book E
e_addi rD,rA,SCI8
e_addi. rD,rA,SCI8
e_add16i rD,rA,SI
e_add2i. rD,SI
se_addi rX,OIMM
Add Immediate
Section on
page 741
e_addic rD,rA,SCI8
e_addic. rD,rA,SCI8
Add Immediate Carrying
Section on
page 743
e_add2is rD,SI
Add Immediate Shifted
Section on
page 741
divw rD,rA,rB
divw. rD,rA,rB
divwo rD,rA,rB
divwo. rD,rA,rB
Divide Word
Book E
divwu rD,rA,rB
divwu. rD,rA,rB
divwuo rD,rA,rB
divwuo. rD,rA,rB
Divide Word Unsigned
Book E
mulhw rD,rA,rB
mulhw. rD,rA,rB
Multiply High Word
Book E
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Instruction model
Table 131. Integer arithmetic instruction set index (continued)
Mnemonic
4.6.6.5.4
Instruction
Reference
mulhwu rD,rA,rB
mulhwu. rD,rA,rB
Multiply High Word Unsigned
e_mulli rD,rA,SCI8
e_mull2i rD,SI
Multiply Low Immediate
mullw rD,rA,rB
mullw. rD,rA,rB
mullwo rD,rA,rB
mullwo. rD,rA,rB
Multiply Low Word
Book E
se_mullw rX,rY
Multiply Low Word
Section on
page 764
neg rD,rA
se_neg rX
neg. rD,rA
nego rD,rA
nego. rD,rA
Negate
Section on
page 764
se_sub rX,rY
Subtract
Section on
page 775
subf rD,rA,rB
subf. rD,rA,rB
subfo rD,rA,rB
subfo. rD,rA,rB
Subtract From
Book E
se_subf rX,rY
Subtract From
Section on
page 776
subfc rD,rA,rB
subfc. rD,rA,rB
subfco rD,rA,rB
subfco. rD,rA,rB
Subtract From Carrying
e_subfic rD,rA,SCI8
e_subfic. rD,rA,SCI8
Subtract From Immediate Carrying
Section on
page 776
se_subi rX,OIMM
se_subi. rX,OIMM
Subtract Immediate
Section on
page 776
Book E
Section on
page 763
Book E
Integer logical and move instructions
Logical instructions perform bit-parallel operations on 32-bit operands or move register or
immediate values into registers. The move instructions move values into a GP from either
another GPR, or an immediate value.
The X-form logical instructions with Rc = 1 and the SCI8-form logical instructions with
Rc = 1 set the first three bits of CR field 0 as described in Section 4.6.6.5.3: Integer
arithmetic instructions. The logical instructions do not change XER[SO,OV,CA].
The integer logical instructions are listed in Table 132.
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Table 132. Integer logical instruction set index
Mnemonic
214/1025
Instruction
Reference
and[.] rA,rS,rB
se_and[.] rX,rY
AND
Section on page
743
andc[.] rA,rS,rB
se_andc rX,rY
AND with Complement
Section on page
743
e_andi[.] rA,rS,SCI8
se_andi rX,UI5
e_and2i. rD,UI
AND Immediate
Section on page
743
e_and2is. rD,UI
AND Immediate Shifted
Section on page
743
se_bclri rX,UI5
Bit Clear
Section on page
746
se_bgeni rX,UI5
Bit Generate
Section on page
747
se_bmski rX,UI5
Bit Mask Generate
Section on page
748
se_bseti rX,UI5
Bit Set
Section on page
748
cntlzw rA,rS
cntlzw. rA,rS
Count Leading Zeros Word
Book E
eqv rA,rS,rB
eqv. rA,rS,rB
Equivalent
Book E
extsb rA,rS
extsb. rA,rS
se_extsb rX
Extend Sign Byte
Section on page
755
extsh rA,rS
extsh. rA,rS
se_extsh rX
Extend Sign Halfword
Section on page
755
se_extzb rX
Extend with Zeros Byte
Section on page
756
se_extzh rX
Extend with Zeros Halfword
Section on page
756
e_li rD,LI20
se_li rX,UI7
Load Immediate
Section on page
760
e_lis rD,UI
Load Immediate Shifted
Section on page
760
se_mfar rX,arY
Move from Alternate Register
Section on page
762
se_mr rX,rY
Move Register
Section on page
762
se_mtar arX,rY
Move to Alternate Register
Section on page
763
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Instruction model
Table 132. Integer logical instruction set index (continued)
Mnemonic
4.6.6.5.5
Instruction
Reference
nand rA,rS,rB
nand. rA,rS,rB
NAND
Book E
nor rA,rS,rB
nor. rA,rS,rB
NOR
Book E
or rA,rS,rB
or. rA,rS,rB
se_or rX,rY
OR
Section on page
765
se_not rX
NOT
Section on page
764
orc rA,rS,rB
orc. rA,rS,rB
OR with Complement
e_ori[.] rA,rS,SCI8
e_or2i rD,UI
OR Immediate
Section on page
765
e_or2is rD,UI
OR Immediate Shifted
Section on page
765
xor rA,rS,rB
xor. rA,rS,rB
XOR
e_xori[.] rA,rS,SCI8
XOR Immediate
Book E
Book E
Section on page
765
Integer compare and bit test instructions
The integer compare instructions compare the contents of GPR(rA) with one of the
following:

The value of the SCI8 field

The zero-extended value of the UI field

The zero-extended value of the UI5 field

The sign-extended value of the SI field

The contents of GPR(rB) or GPR(rY).
The following comparisons are signed: e_cmph, e_cmpi, e_cmp16i, e_cmph16i, se_cmp,
se_cmph, and se_cmpi.
The following comparisons are unsigned: e_cmphl, e_cmpli, e_cmphl16i, e_cmpl16i,
se_cmpli, se_cmpl, and se_cmphl.
When operands are treated as 32-bit signed quantities, GPRn[32] is the sign bit. When
operands are treated as 16-bit signed quantities, GPRn[48] is the sign bit.
For 32-bit implementations, the L field must be zero.
Compare instructions set one of the left-most three bits of the designated CR field and
clears the other two. XER[SO] is copied to bit 3 of the designated CR field.
The CR field is set as shown in Table 133.
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Table 133. CR settings for compare instructions
Bit
Name
Description
0
LT
(rA or rX) < SCI8, SI, UI5, or GPR(rB or rY) (signed comparison)
(rA or rX) <u SCI8, UI, UI5 or GPR(rB or rY) (unsigned comparison)
1
GT
(rA or rX) > SCI8, SI, UI5, or GPR(rB or rY) (signed comparison)
(rA or rX) >u SCI8, UI, UI5 or GPR(rB or rY) (unsigned comparison)
2
EQ
(rA or rX) = SCI8, SI, UI, UI5, or GPR(rB or rY)
3
SO
Summary overflow from the XER
The integer bit test instruction tests the bit specified by the UI5 instruction field and sets the
CR0 field as shown in Table 134.
Table 134. CR settings for integer bit test instructions
Bit
Name
Description
0
LT
Always cleared
1
GT
RXui5 == 1
2
EQ
RXui5 == 0
3
SO
Summary overflow from the XER
Table 135 is an index for integer compare and bit test operations.
Table 135. Integer compare and bit test instruction set index
Mnemonic
Instruction
Reference
se_btsti rX,UI5
Bit Test Immediate
Section on
page 748
cmp crD,L,rA,rB
se_cmp rX,rY
Compare
Section on
page 749
e_cmph crD,rA,rB
se_cmph rX,rY
Compare Halfword
Section on
page 750
e_cmph16i rA,SI16
Compare Halfword Immediate
Section on
page 750
e_cmphl crD,rA,rB
se_cmphl rX,rY
Compare Halfword Logical
Section on
page 751
e_cmphl16i rA,UI16
Compare Halfword Logical Immediate
Section on
page 751
e_cmpi crD,rA,SCI8
e_cmp16i rA,SI16
se_cmpi rX,UI5
Compare Immediate
Section on
page 749
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Table 135. Integer compare and bit test instruction set index (continued)
Mnemonic
Instruction
Reference
cmpl crD,L,rA,rB
se_cmpl rX,rY
Compare Logical
Section on
page 752
e_cmpli crD,rA,SCI8
e_cmpl16i rA,UI16
se_cmpli rX,UI5
Compare Logical Immediate
Section on
page 752
4.6.6.5.6
Integer select instruction
The isel instruction provides a means to select one of two registers and place the result in a
destination register under the control of a predicate value supplied by a CR bit.
The integer select instruction is listed in Table 136.
Table 136. Integer select instruction set index
4.6.6.5.7
Mnemonic
Instruction
Reference
isel rD,rA,rB,crb
Integer Select
EIS
Integer trap instructions
Trap instructions test for a specified set of conditions by comparing the contents of one GPR
with a second GPR. If any of the conditions tested by a Trap instruction are met, a trap
exception type program interrupt is invoked. If none of the tested conditions are met,
instruction execution continues normally.
The contents of GPR(rA) are compared with the contents of GPR(rB). For twi and tw, only
the contents of bits 32–63 of rA (and rB) participate in the comparison.
This comparison results in five conditions that are ANDed with TO. If the result is not 0, the
trap exception type program interrupt is invoked. These conditions are as shown in
Table 137.
Table 137. Integer trap conditions
TO Bit
ANDed with condition
0
Less Than, using signed comparison
1
Greater Than, using signed comparison
2
Equal
3
Less Than, using unsigned comparison
4
Greater Than, using unsigned comparison
The integer trap instruction is listed in Table 138.
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Instruction model
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3
4.6.6.5.8
Table 138. Integer trap instruction set index
Mnemonic
Instruction
Reference
tw TO,rA,rB
Trap Word
Book E
Integer rotate and shift instructions
Instructions are provided that perform shifts and rotates on data from a GPR and return the
result, or a portion of the result, to a GPR.
The rotation operations rotate a 32-bit quantity left by a specified number of bit positions.
Bits that exit from position 32 enter at position 63.
The rotate32 operation is used to rotate a given 32-bit quantity.
Some rotate and shift instructions employ a mask generator. The mask is 32 bits long, and
consists of 1 bits from a start bit, mstart, through and including a stop bit, mstop, and 0-bits
elsewhere. The values of mstart and mstop range from 32 to 63. If mstart > mstop, the 1 bits
wrap around from position 63 to position 0. Thus the mask is formed as follows:
if mstart  mstop then
maskmstart:mstop = ones
maskall other bits = zeros
else
maskmstart:63
mask32:mstop
= ones
= ones
maskall other bits = zeros
There is no way to specify an all-zero mask.
For instructions that use the rotate32 operation, the mask start and stop positions are always
in bits 32–63 of the mask.
The use of the mask is described in following sections.
The rotate word and shift word instructions with Rc = 1 set the first three bits of CR field 0 as
described in Book E. Rotate and shift instructions do not change the OV and SO bits. Rotate
and shift instructions, except algebraic right shifts, do not change the CA bit.
The instructions in Table 139 rotate the contents of a register. Depending on the instruction
type, the amount of the rotation is either specified as an immediate, or contained in a GPR.
Table 139. Integer rotate instruction set index
Mnemonic
Instruction
Reference
e_rlw rA,rS,rB
Rotate Left Word
Section on page
768
e_rlwi rA,rS,SH
Rotate Left Word Immediate
Section on page
768
The instructions in Table 140 rotate the contents of a register. Depending on the instruction
type, the result of the rotation is either inserted into the target register under control of a
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Instruction model
mask (if a mask bit is 1, the associated bit of the rotated data is placed into the target
register; if a mask bit is 0, the associated bit in the target register remains unchanged) or
ANDed with a mask before being placed into the target register.
The rotate left instructions allow right-rotation of the contents of a register to be performed
(in concept) by a left-rotation of 32-n, where n is the number of bits by which to rotate right.
They allow right-rotation of the contents of bits 32–63 of a register to be performed (in
concept) by a left-rotation of 32-n, where n is the number of bits by which to rotate right.
Table 140. Integer rotate with mask instruction set index
Mnemonic
Instruction
Reference
e_rlwimi rA,rS,SH,MB,ME
Rotate Left Word Immediate then Mask Insert
Section on
page 768
e_rlwinm rA,rS,SH,MB,ME
Rotate Left Word Immediate then AND with Mask
Section on
page 769
The integer shift instructions are listed in Table 141.
Table 141. Integer shift instruction set index
Mnemonic
4.6.6.6
Instruction
Reference
slw rA,rS,rB
slw. rA,rS,rB
se_slw rX,rY
Shift Left Word
Section on
page 770
e_slwi rA,rS,SH
se_slwi rX,UI5
Shift Left Word Immediate
Section on
page 770
sraw rA,rS,rB
sraw. rA,rS,rB
se_sraw rX,rY
Shift Right Algebraic Word
Section on
page 771
srawi rA,rS,SH
srawi. rA,rS,SH
se_srawi rX,UI5
Shift Right Algebraic Word Immediate
Section on
page 771
srw rA,rS,rB
srw. rA,rS,rB
se_srw rX,rY
Shift Right Word
Section on
page 772
e_srwi rA,rS,SH
se_srwi rX,UI5
Shift Right Word Immediate
Section on
page 772
Storage control instructions
This section lists storage control instructions, which include the following:

Section 4.6.6.7: Storage synchronization instructions

Section 4.6.6.8: Cache management instructions

Section 4.6.6.9: TLb management instructions
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4.6.6.7
RM0004
Storage synchronization instructions
The memory synchronization instructions implemented by the VLE extension are identical to
those defined in Book E.
The storage synchronization instructions are listed in Table 142.
Table 142. Storage synchronization instruction set index
Mnemonic
4.6.6.8
Instruction
Reference
mbar
Memory Barrier
Book E
msync
Memory Synchronize
Book E
Cache management instructions
Cache management instructions implemented by the VLE extension are identical to those
defined in Book E.
The cache management instructions are listed in Table 143.
Table 143. Cache management instruction set index
Mnemonic
4.6.6.9
Instruction
Reference
dcba rA,rB
Data Cache Block Allocate
Book E
dcbf rA,rB
Data Cache Block Flush
Book E
dcbi rA,rB
Data Cache Block Invalidate
Book E
dcbst rA,rB
Data Cache Block Store
Book E
dcbt CT,rA,rB
Data Cache Block Touch
Book E
dcbtst CT,rA,rB
Data Cache Block Touch for Store
Book E
dcbz rA,rB
Data Cache Block set to Zero
Book E
icbi rA,rB
Instruction Cache Block Invalidate
Book E
icbt CT,rA,rB
Instruction Cache Block Touch
Book E
TLb management instructions
The TLB management instructions implemented by the VLE extension are identical to those
defined in Book E and in the EIS. The TLB management instructions are listed in Table 144.
Table 144. TLB management instruction set index
Mnemonic
220/1025
Instruction
Reference
tlbivax rA,rB
TLB Invalidate Virtual Address Indexed
Book E
tlbre
TLB Read Entry
Book E
tlbsx rA,rB
TLB Search Indexed
Book E
tlbsync
TLB Synchronize
Book E
tlbwe
TLB Write Entry
Book E
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4.6.6.10
Instruction model
VLE instruction alignment and byte ordering
An instruction fetched from memory must be placed in the pipeline with its bytes in the
proper order. Otherwise, the instruction decoder cannot recognize it. Book E allows
instructions to be placed into memory marked as either big- or little-endian. This is
manageable because Book E instructions are always word-size aligned on word
boundaries. The VLE extension includes both half-word– and word-length instructions are
aligned on half-word boundaries. Because of this, only big-endian instruction memory is
supported when executing from a page of VLE instructions. Attempts to execute VLE
instructions from a page marked as little-endian generate an instruction storage interrupt
byte-ordering exception.
4.6.6.11
Instruction listings
This section lists instructions either defined or supported by the VLE extension.
Table 145 lists instructions by instruction name.
Table 145. Instructions listed by name
Instruction
Mnemonic
Reference
Add
add rD,rA,rB
add. rD,rA,rB
addo rD,rA,rB
addo. rD,rA,rB
Book E
Add Carrying
addc rD,rA,rB
addc. rD,rA,rB
addco rD,rA,rB
addco. rD,rA,rB
Book E
Add Extended
adde rD,rA,rB
adde. rD,rA,rB
addeo rD,rA,rB
addeo. rD,rA,rB
Book E
AND with Complement
andc[.] rA,rS,rB
se_andc rX,rY
Book E
Section on
page 743
AND
and[.] rA,rS,rB
se_and[.] rX,rY
Book E
Section on
page 743
Compare
cmp crD,L,rA,rB
se_cmp rX,rY
Book E
Section on
page 749
Compare Logical
cmpl crD,L,rA,rB
se_cmpl rX,rY
Book E
Section on
page 752
Count Leading Zeros Word
cntlzw rA,rS
cntlzw. rA,rS
Book E
Data Cache Block Allocate
dcba rA,rB
Book E
Data Cache Block Flush
dcbf rA,rB
Book E
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Table 145. Instructions listed by name (continued)
Instruction
222/1025
Mnemonic
Reference
Data Cache Block Invalidate
dcbi rA,rB
Book E
Data Cache Block Store
dcbst rA,rB
Book E
Data Cache Block Touch
dcbt CT,rA,rB
Book E
Data Cache Block Touch for Store
dcbtst CT,rA,rB
Book E
Data Cache Block set to Zero
dcbz rA,rB
Book E
Divide Word
divw rD,rA,rB
divw. rD,rA,rB
divwo rD,rA,rB
divwo. rD,rA,rB
Book E
Divide Word Unsigned
divwu rD,rA,rB
divwu. rD,rA,rB
divwuo rD,rA,rB
divwuo. rD,rA,rB
Book E
Equivalent
eqv rA,rS,rB
eqv. rA,rS,rB
Book E
Extend Sign Byte
extsb rA,rS
extsb. rA,rS
se_extsb rX
Book E
Book E
Section on
page 755
Extend Sign Halfword
extsh rA,rS
extsh. rA,rS
se_extsh rX
Book E
Book E
Section on
page 755
Add Immediate Shifted
e_add2is rD,SI
Section on
page 741
Add Immediate
e_addi rD,rA,SCI8
e_addi. rD,rA,SCI8
e_add16i rD,rA,SI
e_add2i. rD,SI
se_addi rX,OIMM
Section on
page 741
Add Immediate Carrying
e_addic rD,rA,SCI8
e_addic. rD,rA,SCI8
Section on
page 743
AND Immediate Shifted
e_and2is. rD,UI
Section on
page 743
AND Immediate
e_andi[.] rA,rS,SCI8
se_andi rX,UI5
e_and2i. rD,UI
Section on
page 743
Branch Conditional
Branch Conditional
Branch Conditional & Link
e_bc BO32,BI32,BD15
se_bc BO16,BI16,BD8
e_bcl BO32,BI32,BD15
Section on
page 745
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Instruction model
Table 145. Instructions listed by name (continued)
Instruction
Mnemonic
Reference
Branch
Branch & Link
e_b BD24
e_bl BD24
Section on
page 744
Compare Halfword
e_cmph crD,rA,rB
se_cmph rX,rY
Section on
page 750
Compare Halfword Immediate
e_cmph16i rA,SI16
Section on
page 750
Compare Halfword Logical
e_cmphl crD,rA,rB
se_cmphl rX,rY
Section on
page 751
Compare Halfword Logical Immediate
e_cmphl16i rA,UI16
Section on
page 751
Compare Immediate
e_cmpi crD,rA,SCI8
e_cmp16i rA,SI16
se_cmpi rX,UI5
Section on
page 749
Compare Logical Immediate
e_cmpli crD,rA,SCI8
e_cmpl16i rA,UI16
se_cmpli rX,UI5
Section on
page 752
Condition Register AND
e_crand crbD,crbA,crbB
Section on
page 753
Condition Register AND with Complement
e_crandc crbD,crbA,crbB
Section on
page 753
Condition Register Equivalent
e_creqv crbD,crbA,crbB
Section on
page 753
Condition Register NAND
e_crnand
crbD,crbA,crbB
Section on
page 754
Condition Register NOR
e_crnor crbD,crbA,crbB
Section on
page 754
Condition Register OR
e_cror crbD,crbA,crbB
Section on
page 755
Condition Register OR with Complement
e_crorc crbD,crbA,crbB
Section on
page 755
Condition Register XOR
e_crxor crbD,crbA,crbB
Section on
page 755
Load Byte and Zero
Load Byte and Zero with Update
Load Byte and Zero (16-bit form)
e_lbz rD,D(rA)
e_lbzu rD,D8(rA)
se_lbz rZ,SD4(rX)
Section on
page 757
Load Halfword Algebraic
Load Halfword Algebraic with Update
e_lha rD,D(rA)
e_lhau rD,D8(rA)
Section on
page 758
Load Halfword and Zero
Load Halfword and Zero with Update
Load Halfword and Zero (16-bit form)
e_lhz rD,D(rA)
e_lhzu rD,D8(rA)
se_lhz rZ,SD4(rX)
Section on
page 759
Load Immediate
e_li rD,LI20
se_li rX,UI7
Section on
page 760
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Table 145. Instructions listed by name (continued)
Instruction
224/1025
Mnemonic
Reference
Load Immediate Shifted
e_lis rD,UI
Section on
page 760
Load Multiple Word
e_lmw rD,D8(rA)
Section on
page 760
Load Word and Zero
Load Word and Zero with Update
Load Word and Zero (16-bit form)
e_lwz rD,D(rA)
e_lwzu rD,D8(rA)
se_lwz rZ,SD4(rX)
Section on
page 761
Move Condition Register Field
e_mcrf crD,crS
Section on
page 761
Multiply Low Immediate
e_mulli rD,rA,SCI8
e_mull2i rD,SI
Section on
page 763
OR Immediate Shifted
e_or2is rD,UI
Section on
page 765
OR Immediate
e_ori[.] rA,rS,SCI8
e_or2i rD,UI
Section on
page 765
Rotate Left Word
e_rlw rA,rS,rB
Section on
page 768
Rotate Left Word Immediate
e_rlwi rA,rS,SH
Section on
page 768
Rotate Left Word Immediate then Mask Insert
e_rlwimi rA,rS,SH,MB,ME
Section on
page 768
Rotate Left Word Immediate then AND with Mask
e_rlwinm
rA,rS,SH,MB,ME
Section on
page 769
Shift Left Word Immediate
e_slwi rA,rS,SH
se_slwi rX,UI5
Section on
page 770
Shift Right Word Immediate
e_srwi rA,rS,SH
se_srwi rX,UI5
Section on
page 772
Store Byte
Store Byte with Update
Store Byte (16-bit form)
e_stb rS,D(rA)
e_stbu rS,D8(rA)
se_stb rZ,SD4(rX)
Section on
page 773
Store Halfword
Store Halfword with Update
Store Halfword (16-bit form)
e_sth rS,D(rA)
e_sthu rS,D8(rA)
se_sth rZ,SD4(rX)
Section on
page 773
Store Multiple Word
e_stmw rS,D8(rA)
Section on
page 774
Store Word
Store Word with Update
Store Word (16-bit form)
e_stw rS,D(rA)
e_stwu rS,D8(rA)
se_stw rZ,SD4(rX)
Section on
page 775
Subtract From Immediate Carrying
e_subfic rD,rA,SCI8
e_subfic. rD,rA,SCI8
Section on
page 776
DocID13694 Rev 2
RM0004
Instruction model
Table 145. Instructions listed by name (continued)
Instruction
Mnemonic
Reference
Section on
page 765
XOR Immediate
e_xori[.] rA,rS,SCI8
Instruction Cache Block Invalidate
icbi rA,rB
Book E
Instruction Cache Block Touch
icbt CT,rA,rB
Book E
Integer Select
isel rD,rA,rB,crb
Load Byte and Zero Indexed
Load Byte and Zero with Update Indexed
lbzx rD,rA,rB
lbzux rD,rA,rB
Book E
Load Halfword Algebraic Indexed
Load Halfword Algebraic with Update Indexed
lhax rD,rA,rB
lhaux rD,rA,rB
Book E
Load Halfword Byte-Reverse Indexed
lhbrx rD,rA,rB
Book E
Load Halfword and Zero Indexed
Load Halfword and Zero with Update Indexed
lhzx rD,rA,rB
lhzux rD,rA,rB
Book E
Load Word And Reserve Indexed
lwarx rD,rA,rB
Book E
Load Word Byte-Reverse Indexed
lwbrx rD,rA,rB
Book E
Load Word and Zero Indexed
Load Word and Zero with Update Indexed
lwzx rD,rA,rB
lwzux rD,rA,rB
Book E
Memory Barrier
mbar
Book E
Move to Condition Register from Integer Exception
Register
mcrxr crD
Book E
Move From condition register
mfcr rD
Book E
Move From Device Control Register
mfdcr rD,DCRN
Book E
Move From Machine State Register
mfmsr rD
Book E
Move From Special Purpose Register
mfspr rD,SPRN
Book E
Memory Synchronize
msync
Book E
Move to Condition Register Fields
mtcrf FXM,rS
Book E
Move To Device Control Register
mtdcr DCRN,rS
Book E
Move To Machine State Register
mtmsr rS
Book E
Move To Special Purpose Register
mtspr SPRN,rS
Book E
Multiply High Word
mulhw rD,rA,rB
mulhw. rD,rA,rB
Book E
Multiply High Word Unsigned
mulhwu rD,rA,rB
mulhwu. rD,rA,rB
Book E
Multiply Low Word
mullw rD,rA,rB
mullw. rD,rA,rB
mullwo rD,rA,rB
mullwo. rD,rA,rB
Book E
NAND
nand rA,rS,rB
nand. rA,rS,rB
Book E
DocID13694 Rev 2
EIS
225/1025
249
Instruction model
RM0004
Table 145. Instructions listed by name (continued)
Instruction
226/1025
Mnemonic
Reference
Negate
neg rD,rA
se_neg rX
neg. rD,rA
nego rD,rA
nego. rD,rA
Book E
Section on
page 764
Book E
Book E
Book E
NOR
nor rA,rS,rB
nor. rA,rS,rB
Book E
OR
or rA,rS,rB
or. rA,rS,rB
se_or rX,rY
Book E
Book E
Section on
page 765
OR with Complement
orc rA,rS,rB
orc. rA,rS,rB
Book E
Add
se_add rX,rY
Section on
page 741
Bit Clear
se_bclri rX,UI5
Section on
page 746
Branch to Count Register
Branch to Count Register & Link
se_bctr
se_bctrl
Section on
page 746
Bit Generate
se_bgeni rX,UI5
Section on
page 747
Branch to Link Register
Branch to Link Register & Link
se_blr
se_blrl
Section on
page 747
Bit Mask Generate
se_bmski rX,UI5
Section on
page 748
Bit Set
se_bseti rX,UI5
Section on
page 748
Branch
Branch & Link
se_b BD8
se_bl BD8
Section on
page 744
Bit Test Immediate
se_btsti rX,UI5
Section on
page 748
Extend with Zeros Byte
se_extzb rX
Section on
page 756
Extend with Zeros Halfword
se_extzh rX
Section on
page 756
Instruction Synchronize
se_isync
Section on
page 757
Move from Alternate Register
se_mfar rX,arY
Section on
page 762
Move From Count Register
se_mfctr rX
Section on
page 762
DocID13694 Rev 2
RM0004
Instruction model
Table 145. Instructions listed by name (continued)
Instruction
Mnemonic
Reference
Move From Link Register
se_mflr rX
Section on
page 762
Move Register
se_mr rX,rY
Section on
page 762
Move to Alternate Register
se_mtar arX,rY
Section on
page 763
Move To Count Register
se_mtctr rX
Section on
page 763
Move To Link Register
se_mtlr rX
Section on
page 763
Multiply Low Word
se_mullw rX,rY
Section on
page 764
NOT
se_not rX
Section on
page 764
Subtract
se_sub rX,rY
Section on
page 775
Subtract From
se_subf rX,rY
Section on
page 776
Subtract Immediate
se_subi rX,OIMM
se_subi. rX,OIMM
Section on
page 776
Shift Left Word
slw rA,rS,rB
slw. rA,rS,rB
se_slw rX,rY
Book E
Book E
Section on
page 770
Shift Right Algebraic Word
sraw rA,rS,rB
sraw. rA,rS,rB
se_sraw rX,rY
Book E
Book E
Section on
page 771
Shift Right Algebraic Word Immediate
srawi rA,rS,SH
srawi. rA,rS,SH
se_srawi rX,UI5
Book E
Book E
Section on
page 771
Shift Right Word
srw rA,rS,rB
srw. rA,rS,rB
se_srw rX,rY
Book E
Book E
Section on
page 772
Store Byte Indexed
Store Byte with Update Indexed
stbx rS,rA,rB
stbux rS,rA,rB
Book E
Store Halfword Byte-Reverse Indexed
sthbrx rS,rA,rB
Book E
Store Halfword Indexed
Store Halfword with Update Indexed
sthx rS,rA,rB
sthux rS,rA,rB
Book E
DocID13694 Rev 2
227/1025
249
Instruction model
RM0004
Table 145. Instructions listed by name (continued)
Instruction
Mnemonic
Reference
Store Word Byte-Reverse Indexed
stwbrx rS,rA,rB
Book E
Store Word Conditional Indexed
stwcx. rS,rA,rB
Book E
Store Word Indexed
Store Word with Update Indexed
stwx rS,rA,rB
stwux rS,rA,rB
Book E
Subtract From
subf rD,rA,rB
subf. rD,rA,rB
subfo rD,rA,rB
subfo. rD,rA,rB
Book E
Subtract From Carrying
subfc rD,rA,rB
subfc. rD,rA,rB
subfco rD,rA,rB
subfco. rD,rA,rB
Book E
TLB Invalidate Virtual Address Indexed
tlbivax rA,rB
Book E
TLB Read Entry
tlbre
Book E
TLB Search Indexed
tlbsx rA,rB
Book E
TLB Synchronize
tlbsync
Book E
TLB Write Entry
tlbwe
Book E
Trap Word
tw TO,rA,rB
Book E
Write MSR External Enable
wrtee rA
Book E
Write MSR External Enable Immediate
wrteei E
Book E
XOR
xor rA,rS,rB
xor. rA,rS,rB
Book E
Table 145 lists instructions that can be executed in VLE mode by mnemonic.
Table 146. Instructions listed by mnemonic
Mnemonic
228/1025
Instruction
Reference
add rD,rA,rB
add. rD,rA,rB
addo rD,rA,rB
addo. rD,rA,rB
Add
Book E
addc rD,rA,rB
addc. rD,rA,rB
addco rD,rA,rB
addco. rD,rA,rB
Add Carrying
Book E
adde rD,rA,rB
adde. rD,rA,rB
addeo rD,rA,rB
addeo. rD,rA,rB
Add Extended
Book E
DocID13694 Rev 2
RM0004
Instruction model
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
Instruction
Reference
andc[.] rA,rS,rB
AND with Complement
Book E
and[.] rA,rS,rB
AND
Book E
cmp crD,L,rA,rB
Compare
Book E
cmpl crD,L,rA,rB
Compare Logical
Book E
cntlzw rA,rS
cntlzw. rA,rS
Count Leading Zeros Word
Book E
dcba rA,rB
Data Cache Block Allocate
Book E
dcbf rA,rB
Data Cache Block Flush
Book E
dcbi rA,rB
Data Cache Block Invalidate
Book E
dcbst rA,rB
Data Cache Block Store
Book E
dcbt CT,rA,rB
Data Cache Block Touch
Book E
dcbtst CT,rA,rB
Data Cache Block Touch for Store
Book E
dcbz rA,rB
Data Cache Block set to Zero
Book E
divw rD,rA,rB
divw. rD,rA,rB
divwo rD,rA,rB
divwo. rD,rA,rB
Divide Word
Book E
divwu rD,rA,rB
divwu. rD,rA,rB
divwuo rD,rA,rB
divwuo. rD,rA,rB
Divide Word Unsigned
Book E
eqv rA,rS,rB
eqv. rA,rS,rB
Equivalent
Book E
extsb rA,rS
extsb. rA,rS
Extend Sign Byte
Book E
extsh rA,rS
extsh. rA,rS
Extend Sign Halfword
Book E
e_add2is rD,SI
Add Immediate Shifted
Section on
page 741
e_addi rD,rA,SCI8
e_addi. rD,rA,SCI8
e_add16i rD,rA,SI
e_add2i. rD,SI
Add Immediate
Section on
page 741
e_addic rD,rA,SCI8
e_addic. rD,rA,SCI8
Add Immediate Carrying
Section on
page 743
e_and2is. rD,UI
AND Immediate Shifted
Section on
page 743
e_andi[.] rA,rS,SCI8
e_and2i. rD,UI
AND Immediate
Section on
page 743
DocID13694 Rev 2
229/1025
249
Instruction model
RM0004
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
230/1025
Instruction
Reference
e_bc BO32,BI32,BD15
e_bcl BO32,BI32,BD15
Branch Conditional
Branch Conditional & Link
e_b BD24
e_bl BD24
Branch
Branch & Link
Section on
page 744
e_cmph crD,rA,rB
Compare Halfword
Section on
page 750
e_cmph16i rA,SI16
Compare Halfword Immediate
Section on
page 750
e_cmphl crD,rA,rB
Compare Halfword Logical
Section on
page 751
e_cmphl16i rA,UI16
Compare Halfword Logical Immediate
Section on
page 751
e_cmpi crD,rA,SCI8
e_cmp16i rA,SI16
Compare Immediate
Section on
page 749
e_cmpli crD,rA,SCI8
e_cmpl16i rA,UI16
Compare Logical Immediate
Section on
page 752
e_crand crbD,crbA,crbB
Condition Register AND
Section on
page 753
e_crandc crbD,crbA,crbB
Condition Register AND with Complement
Section on
page 753
e_creqv crbD,crbA,crbB
Condition Register Equivalent
Section on
page 753
e_crnand crbD,crbA,crbB
Condition Register NAND
Section on
page 754
e_crnor crbD,crbA,crbB
Condition Register NOR
Section on
page 754
e_cror crbD,crbA,crbB
Condition Register OR
Section on
page 755
e_crorc crbD,crbA,crbB
Condition Register OR with Complement
Section on
page 755
e_crxor crbD,crbA,crbB
Condition Register XOR
Section on
page 755
e_lbz rD,D(rA)
e_lbzu rD,D8(rA)
Load Byte and Zero
Load Byte and Zero with Update
Section on
page 757
e_lha rD,D(rA)
e_lhau rD,D8(rA)
Load Halfword Algebraic
Load Halfword Algebraic with Update
Section on
page 758
e_lhz rD,D(rA)
e_lhzu rD,D8(rA)
Load Halfword and Zero
Load Halfword and Zero with Update
Section on
page 759
e_li rD,LI20
Load Immediate
Section on
page 760
DocID13694 Rev 2
Section on
page 745Page
RM0004
Instruction model
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
Instruction
Reference
e_lis rD,UI
Load Immediate Shifted
Section on
page 760
e_lmw rD,D8(rA)
Load Multiple Word
Section on
page 761
e_lwz rD,D(rA)
e_lwzu rD,D8(rA)
Load Word and Zero
Load Word and Zero with Update
Section on
page 761
e_mcrf crD,crS
Move Condition Register Field
Section on
page 763
e_mulli rD,rA,SCI8
e_mull2i rD,SI
Multiply Low Immediate
Section on
page 765
e_or2is rD,UI
OR Immediate Shifted
Section on
page 765
e_ori[.] rA,rS,SCI8
e_or2i rD,UI
OR Immediate
Section on
page 768
e_rlw rA,rS,rB
Rotate Left Word
Section on
page 768
e_rlwi rA,rS,SH
Rotate Left Word Immediate
Section on
page 768
e_rlwimi rA,rS,SH,MB,ME
Rotate Left Word Immediate then Mask Insert
Section on
page 769
e_rlwinm rA,rS,SH,MB,ME
Rotate Left Word Immediate then AND with Mask
Section on
page 770
e_slwi rA,rS,SH
Shift Left Word Immediate
Section on
page 761
e_srwi rA,rS,SH
Shift Right Word Immediate
e_stb rS,D(rA)
e_stbu rS,D8(rA)
Store Byte
Store Byte with Update
Section on
page 773
e_sth rS,D(rA)
e_sthu rS,D8(rA)
Store Halfword
Store Halfword with Update
Section on
page 773
e_stmw rS,D8(rA)
Store Multiple Word
Section on
page 774
e_stw rS,D(rA)
e_stwu rS,D8(rA)
Store Word
Store Word with Update
Section on
page 775
e_subfic rD,rA,SCI8
e_subfic. rD,rA,SCI8
Subtract From Immediate Carrying
Section on
page 776
e_xori[.] rA,rS,SCI8
XOR Immediate
Section on
page 765
icbi rA,rB
Instruction Cache Block Invalidate
Book E
icbt CT,rA,rB
Instruction Cache Block Touch
Book E
isel rD,rA,rB,crb
Integer Select
DocID13694 Rev 2
Book E
EIS
231/1025
249
Instruction model
RM0004
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
232/1025
Instruction
Reference
lbzx rD,rA,rB
lbzux rD,rA,rB
Load Byte and Zero Indexed
Load Byte and Zero with Update Indexed
Book E
lhax rD,rA,rB
lhaux rD,rA,rB
Load Halfword Algebraic Indexed
Load Halfword Algebraic with Update Indexed
Book E
lhbrx rD,rA,rB
Load Halfword Byte-Reverse Indexed
Book E
lhzx rD,rA,rB
lhzux rD,rA,rB
Load Halfword and Zero Indexed
Load Halfword and Zero with Update Indexed
Book E
lwarx rD,rA,rB
Load Word And Reserve Indexed
Book E
lwbrx rD,rA,rB
Load Word Byte-Reverse Indexed
Book E
lwzx rD,rA,rB
lwzux rD,rA,rB
Load Word and Zero Indexed
Load Word and Zero with Update Indexed
Book E
mbar
Memory Barrier
Book E
mcrxr crD
Move to Condition Register from Integer Exception
Register
Book E
mfcr rD
Move From condition register
Book E
mfdcr rD,DCRN
Move From Device Control Register
Book E
mfmsr rD
Move From Machine State Register
Book E
mfspr rD,SPRN
Move From Special Purpose Register
Book E
msync
Memory Synchronize
Book E
mtcrf FXM,rS
Move to Condition Register Fields
Book E
mtdcr DCRN,rS
Move To Device Control Register
Book E
mtmsr rS
Move To Machine State Register
Book E
mtspr SPRN,rS
Move To Special Purpose Register
Book E
mulhw rD,rA,rB
mulhw. rD,rA,rB
Multiply High Word
Book E
mulhwu rD,rA,rB
mulhwu. rD,rA,rB
Multiply High Word Unsigned
Book E
mullw rD,rA,rB
mullw. rD,rA,rB
mullwo rD,rA,rB
mullwo. rD,rA,rB
Multiply Low Word
Book E
nand rA,rS,rB
nand. rA,rS,rB
NAND
Book E
neg rD,rA
neg. rD,rA
nego rD,rA
nego. rD,rA
Negate
Book E
DocID13694 Rev 2
RM0004
Instruction model
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
Instruction
Reference
nor rA,rS,rB
nor. rA,rS,rB
NOR
Book E
or rA,rS,rB
or. rA,rS,rB
OR
Book E
orc rA,rS,rB
orc. rA,rS,rB
OR with Complement
Book E
se_add rX,rY
Add
Section on
page 741
se_addi rX,OIMM
Add Immediate
Section on
page 741
se_andc rX,rY
AND with Complement
Section on
page 743
se_andi rX,UI5
AND Immediate
Section on
page 743
se_and[.] rX,rY
AND
Section on
page 743
se_bc BO16,BI16,BD8
Branch Conditional
Section on
page 745
se_bclri rX,UI5
Bit Clear
Section on
page 746
se_bctr
se_bctrl
Branch to Count Register
Branch to Count Register & Link
Section on
page 746
se_bgeni rX,UI5
Bit Generate
Section on
page 746
se_blr
se_blrl
Branch to Link Register
Branch to Link Register & Link
Section on
page 747
se_bmski rX,UI5
Bit Mask Generate
Section on
page 747
se_bseti rX,UI5
Bit Set
Section on
page 748
se_b BD8
se_bl BD8
Branch
Branch & Link
Section on
page 748
se_btsti rX,UI5
Bit Test Immediate
Section on
page 744
se_cmp rX,rY
Compare
Section on
page 749
se_cmph rX,rY
Compare Halfword
Section on
page 750
se_cmphl rX,rY
Compare Halfword Logical
Section on
page 751
DocID13694 Rev 2
233/1025
249
Instruction model
RM0004
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
234/1025
Instruction
Reference
se_cmpi rX,UI5
Compare Immediate
Section on
page 749
se_cmpl rX,rY
Compare Logical
Section on
page 752
se_cmpli rX,UI5
Compare Logical Immediate
Section on
page 752
se_extsb rX
Extend Sign Byte
Section on
page 755
se_extsh rX
Extend Sign Halfword
Section on
page 755
se_extzb rX
Extend with Zeros Byte
Section on
page 756
se_extzh rX
Extend with Zeros Halfword
Section on
page 756
se_isync
Instruction Synchronize
Section on
page 757
se_lbz rZ,SD4(rX)
Load Byte and Zero (16-bit form)
Section on
page 757
se_lhz rZ,SD4(rX)
Load Halfword and Zero (16-bit form)
Section on
page 759
se_li rX,UI7
Load Immediate
Section on
page 760
se_lwz rZ,SD4(rX)
Load Word and Zero (16-bit form)
Section on
page 761
se_mfar rX,arY
Move from Alternate Register
Section on
page 762
se_mfctr rX
Move From Count Register
Section on
page 762
se_mflr rX
Move From Link Register
Section on
page 762
se_mr rX,rY
Move Register
Section on
page 762
se_mtar arX,rY
Move to Alternate Register
Section on
page 763
se_mtctr rX
Move To Count Register
Section on
page 763
se_mtlr rX
Move To Link Register
Section on
page 763
se_mullw rX,rY
Multiply Low Word
Section on
page 764
se_neg rX
Negate
Section on
page 764
DocID13694 Rev 2
RM0004
Instruction model
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
Instruction
Reference
se_not rX
NOT
Section on
page 764
se_or rX,rY
OR
Section on
page 765
se_slw rX,rY
Shift Left Word
Section on
page 770
se_slwi rX,UI5
Shift Left Word Immediate
Section on
page 770
se_sraw rX,rY
Shift Right Algebraic Word
Section on
page 771
se_srawi rX,UI5
Shift Right Algebraic Word Immediate
Section on
page 771
se_srw rX,rY
Shift Right Word
Section on
page 772
se_srwi rX,UI5
Shift Right Word Immediate
Section on
page 772
se_stb rZ,SD4(rX)
Store Byte (16-bit form)
Section on
page 773
se_sth rZ,SD4(rX)
Store Halfword (16-bit form)
Section on
page 773
se_stw rZ,SD4(rX)
Store Word (16-bit form)
Section on
page 775
se_sub rX,rY
Subtract
Section on
page 775
se_subf rX,rY
Subtract From
Section on
page 776
se_subi rX,OIMM
se_subi. rX,OIMM
Subtract Immediate
Section on
page 776
slw rA,rS,rB
slw. rA,rS,rB
Shift Left Word
Book E
sraw rA,rS,rB
sraw. rA,rS,rB
Shift Right Algebraic Word
Book E
srawi rA,rS,SH
srawi. rA,rS,SH
Shift Right Algebraic Word Immediate
Book E
srw rA,rS,rB
srw. rA,rS,rB
Shift Right Word
Book E
stbx rS,rA,rB
stbux rS,rA,rB
Store Byte Indexed
Store Byte with Update Indexed
Book E
sthbrx rS,rA,rB
Store Halfword Byte-Reverse Indexed
Book E
sthx rS,rA,rB
sthux rS,rA,rB
Store Halfword Indexed
Store Halfword with Update Indexed
Book E
DocID13694 Rev 2
235/1025
249
Instruction model
RM0004
Table 146. Instructions listed by mnemonic (continued)
Mnemonic
4.7
Instruction
Reference
stwbrx rS,rA,rB
Store Word Byte-Reverse Indexed
Book E
stwcx. rS,rA,rB
Store Word Conditional Indexed
Book E
stwx rS,rA,rB
stwux rS,rA,rB
Store Word Indexed
Store Word with Update Indexed
Book E
subf rD,rA,rB
subf. rD,rA,rB
subfo rD,rA,rB
subfo. rD,rA,rB
Subtract From
Book E
subfc rD,rA,rB
subfc. rD,rA,rB
subfco rD,rA,rB
subfco. rD,rA,rB
Subtract From Carrying
Book E
tlbivax rA,rB
TLB Invalidate Virtual Address Indexed
Book E
tlbre
TLB Read Entry
Book E
tlbsx rA,rB
TLB Search Indexed
Book E
tlbsync
TLB Synchronize
Book E
tlbwe
TLB Write Entry
Book E
tw TO,rA,rB
Trap Word
Book E
wrtee rA
Write MSR External Enable
Book E
wrteei E
Write MSR External Enable Immediate
Book E
xor rA,rS,rB
xor. rA,rS,rB
XOR
Book E
Instruction listing
Table 147 lists instructions defined in Book E, in the PowerPC architecture, and by the EIS.
A check mark () or text in a column indicates that the instruction is defined or implemented.
The EIS-specific instructions are indicated by the name of the APU or architectural
extension that defines the instruction.
Table 147. List of instructions
236/1025
Mnemonic
Book E
Classic
EIS
addc[o][.]


e_cmpli
VLE
adde[o][.]


e_crand
VLE
addi


e_crandc
VLE
addic[.]


e_creqv
VLE
addis


e_crnand
VLE
addme[o][.]


e_crnor
VLE
DocID13694 Rev 2
Mnemonic
Book E
Classic
EIS
RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
addze[o][.]


e_cror
VLE
add[o].]


e_crorc
VLE
andc[.]


e_crxor
VLE
andi.


e_lbz
VLE
andis.


e_lbzu
VLE
and[.]


e_lha
VLE
b


e_lhau
VLE
ba


e_lhz
VLE
bc


e_lhzu
VLE
bca


e_li
VLE
bcctr


e_lis
VLE
bcctrl


e_lmw
VLE
bcl


e_lwz
VLE
bcla


e_lwzu
VLE
bclr


e_mcrf
VLE
bclrl


e_mull2i
VLE
bl


e_mulli
VLE
bla


e_or2i
VLE
e_or2is
VLE
SPE
APU
brinc
Mnemonic
Book E
Classic
EIS
cmp


e_ori[.]
VLE
cmpi


e_rlw
VLE
cmpl


e_rlwi
VLE
cmpli


e_rlwimi
VLE
cntlzw[.]


e_rlwinm
VLE
crand


e_slwi
VLE
crandc


e_srwi
VLE
creqv


e_stb
VLE
crnand


e_stbu
VLE
crnor


e_sth
VLE
cror


e_sthu
VLE
crorc


e_stmw
VLE
crxor


e_stw
VLE
dcba


e_stwu
VLE
dcbf


e_subfic
VLE
DocID13694 Rev 2
237/1025
249
Instruction model
RM0004
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
dcbi


Cache
locking
dcblc
Mnemonic
Book E
Classic
VLE
e_xori[.]
VLE


fabs[.]


dcbt


fadds[.]


fadd[.]


fcfid[.]


fcmpo


Cache
locking
dcbtst


Cache
locking
dcbtstls
dcbz


fcmpu


divwu[o][.]


fctidz[.]


divw[o][.]


fctid[.]


eciwx

fctiwz[.]


ecowx

fctiw[.]


efsabs
Scalar
SPFP
fdivs[.]


efsadd
Scalar
SPFP
fdiv[.]


efscfsf
Scalar
SPFP
fmadds[.]


efscfsi
Scalar
SPFP
fmadd[.]


efscfuf
Scalar
SPFP
fmr[.]


efscfui
Scalar
SPFP
fmsubs[.]


efscmpeq
Scalar
SPFP
fmsub[.]


efscmpgt
Scalar
SPFP
fmuls[.]


efscmplt
Scalar
SPFP
fmul[.]


efsctsf
Scalar
SPFP
fnabs[.]


efsctsi
Scalar
SPFP
fneg[.]


efsctsiz
Scalar
SPFP
fnmadds[.]


DocID13694 Rev 2
EIS
e_subfic.
dcbst
dcbtls
238/1025
EIS
RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
Mnemonic
Book E
Classic
efsctuf
Scalar
SPFP
fnmadd[.]


efsctui
Scalar
SPFP
fnmsubs[.]


efsctuiz
Scalar
SPFP
fnmsub[.]


efsdiv
Scalar
SPFP
fres[.]


efsmul
Scalar
SPFP
frsp[.]


efsnabs
Scalar
SPFP
frsqrte[.]


efsneg
Scalar
SPFP
fsel[.]


efssub
Scalar
SPFP
fsqrts[.]


efststeq
Scalar
SPFP
fsqrt[.]


efststgt
Scalar
SPFP
fsubs[.]


efststlt
Scalar
SPFP
fsub[.]




eieio
Now
mbar

icbi
eqv[.]


icblc
EIS
Cache
locking
evabs
SPE
APU
icbt
evaddiw
SPE
APU
icbtls
Cache
locking
evaddsmiaaw
SPE
APU
isel
Integer
select
evaddssiaaw
SPE
APU
isync


evaddumiaaw
SPE
APU
lbz


evaddusiaaw
SPE
APU
lbzu


evaddw
SPE
APU
lbzux


evand
SPE
APU
lbzx


DocID13694 Rev 2

239/1025
249
Instruction model
RM0004
Table 147. List of instructions (continued)
Mnemonic
240/1025
Book E
Classic
EIS
Mnemonic
evandc
SPE
APU
ld

evcmpeq
SPE
APU
ldarx

evcmpgts
SPE
APU
ldu

evcmpgtu
SPE
APU
ldux

evcmplts
SPE
APU
ldx

evcmpltu
SPE
APU
lfd


evcntlsw
SPE
APU
lfdu


evcntlzw
SPE
APU
lfdux


evdivws
SPE
APU
lfdx


evdivwu
SPE
APU
lfs


eveqv
SPE
APU
lfsu


evextsb
SPE
APU
lfsux


evextsh
SPE
APU
lfsx


evfsabs
Vector
SPFP
lha


evfsadd
Vector
SPFP
lhau


evfscfsf
Vector
SPFP
lhaux


evfscfsi
Vector
SPFP
lhax


evfscfuf
Vector
SPFP
lhbrx


evfscfui
Vector
SPFP
lhz


evfscmpeq
Vector
SPFP
lhzu


evfscmpgt
Vector
SPFP
lhzux


DocID13694 Rev 2
Book E
Classic
EIS
RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
Mnemonic
Book E
Classic
evfscmplt
Vector
SPFP
lhzx


evfsctsf
Vector
SPFP
lmw


evfsctsi
Vector
SPFP
lswi


evfsctsiz
Vector
SPFP
lswx


evfsctuf
Vector
SPFP
lwa
evfsctui
Vector
SPFP
lwarx
evfsctuiz
Vector
SPFP
lwaux

evfsdiv
Vector
SPFP
lwax

evfsmul
Vector
SPFP
lwbrx


evfsnabs
Vector
SPFP
lwz


evfsneg
Vector
SPFP
lwzu


evfssub
Vector
SPFP
lwzux


evfststeq
Vector
SPFP
lwzx


evfststgt
Vector
SPFP
mbar

evfststlt
Vector
SPFP
mcrf


evldd
SPE
APU
mcrfs


evlddx
SPE
APU
mcrxr


evldh
SPE
APU
mfapidi

evldhx
SPE
APU
mfcr

evldw
SPE
APU
mfdcr

evldwx
SPE
APU
mffs[.]

DocID13694 Rev 2
EIS





241/1025
249
Instruction model
RM0004
Table 147. List of instructions (continued)
Mnemonic
242/1025
Book E
Classic
EIS
Mnemonic
Book E
Classic
evlhhesplat
SPE
APU
mfmsr


evlhhesplatx
SPE
APU
mfpmr
evlhhossplat
SPE
APU
mfspr
evlhhossplatx
SPE
APU
mfsr

evlhhousplat
SPE
APU
mfsrin

evlhhousplatx
SPE
APU
mftb

evlwhe
SPE
APU
msync

evlwhex
SPE
APU
mtcrf

evlwhos
SPE
APU
mtdcr

evlwhosx
SPE
APU
mtfsb0[.]


evlwhou
SPE
APU
mtfsb1[.]


evlwhoux
SPE
APU
mtfsfi[.]


evlwhsplat
SPE
APU
mtfsf[.]


evlwhsplatx
SPE
APU
mtmsr


evlwwsplat
SPE
APU
mtmsrd
evlwwsplatx
SPE
APU
mtpmr
evmergehi
SPE
APU
mtspr
evmergehilo
SPE
APU
mtsr

evmergelo
SPE
APU
mtsrd

evmergelohi
SPE
APU
mtsrdin

DocID13694 Rev 2
EIS
Performa
nce
monitor



64-bit only
Performa
nce
monitor


RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
Mnemonic
evmhegsmfaa
SPE
APU
mtsrin

evmhegsmfan
SPE
APU
mulhd.

evmhegsmiaa
SPE
APU
mulhdu.

evmhegsmian
SPE
APU
mulhwu[.]


evmhegumiaa
SPE
APU
mulhw[.]


evmhegumian
SPE
APU
mulld.

evmhesmf
SPE
APU
mulldo.

evmhesmfa
SPE
APU
mulli


evmhesmfaaw
SPE
APU
mullw[o][.]


evmhesmfanw
SPE
APU
nand[.]


evmhesmi
SPE
APU
neg[o][.]


evmhesmia
SPE
APU
nor[.]


evmhesmiaaw
SPE
APU
orc[.]


evmhesmianw
SPE
APU
ori


evmhessf
SPE
APU
oris


evmhessfa
SPE
APU
or[.]


evmhessfaaw
SPE
APU
rfci

evmhessfanw
SPE
APU
rfi

evmhessiaaw
SPE
APU
rfid
evmhessianw
SPE
APU
rfmci
evmheumi
SPE
APU
rldcl.
DocID13694 Rev 2
Book E
Classic
EIS


Machine
check

243/1025
249
Instruction model
RM0004
Table 147. List of instructions (continued)
Mnemonic
244/1025
Book E
Classic
EIS
Mnemonic
evmheumia
SPE
APU
rldcr.

evmheumiaaw
SPE
APU
rldic.

evmheumianw
SPE
APU
rldicl.

evmheusiaaw
SPE
APU
rldicr.

evmheusianw
SPE
APU
rldimi.

evmhogsmfaa
SPE
APU
rlwimi[.]


evmhogsmfan
SPE
APU
rlwinm[.]


evmhogsmiaa
SPE
APU
rlwnm[.]


evmhogsmian
SPE
APU
sc


evmhogumiaa
SPE
APU
se_add
VLE
evmhogumian
SPE
APU
se_addi
VLE
evmhosmf
SPE
APU
se_andc
VLE
evmhosmfa
SPE
APU
se_andi
VLE
evmhosmfaaw
SPE
APU
se_and[.]
VLE
evmhosmfanw
SPE
APU
se_b
VLE
evmhosmi
SPE
APU
se_bc
VLE
evmhosmia
SPE
APU
se_bclri
VLE
evmhosmiaaw
SPE
APU
se_bctr
VLE
evmhosmianw
SPE
APU
se_bctrl
VLE
evmhossf
SPE
APU
se_bgeni
VLE
evmhossfa
SPE
APU
se_bl
VLE
DocID13694 Rev 2
Book E
Classic
EIS
RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
Mnemonic
evmhossfaaw
SPE
APU
se_blr
VLE
evmhossfanw
SPE
APU
se_blrl
VLE
evmhossiaaw
SPE
APU
se_bmski
VLE
evmhossianw
SPE
APU
se_bseti
VLE
evmhoumi
SPE
APU
se_btsti
VLE
evmhoumia
SPE
APU
se_cmp
VLE
evmhoumiaaw
SPE
APU
se_cmph
VLE
evmhoumianw
SPE
APU
se_cmphl
VLE
evmhousiaaw
SPE
APU
se_cmpi
VLE
evmhousianw
SPE
APU
se_cmpl
VLE
evmra
SPE
APU
se_cmpli
VLE
evmwhsmf
SPE
APU
se_extsb
VLE
evmwhsmfa
SPE
APU
se_extsh
VLE
evmwhsmi
SPE
APU
se_extzb
VLE
evmwhsmia
SPE
APU
se_extzh
VLE
evmwhssf
SPE
APU
se_isync
VLE
evmwhssfa
SPE
APU
se_lbz
VLE
evmwhumi
SPE
APU
se_lhz
VLE
evmwhumia
SPE
APU
se_li
VLE
evmwlsmiaaw
SPE
APU
se_lwz
VLE
evmwlsmianw
SPE
APU
se_mfar
VLE
DocID13694 Rev 2
Book E
Classic
EIS
245/1025
249
Instruction model
RM0004
Table 147. List of instructions (continued)
Mnemonic
246/1025
Book E
Classic
EIS
Mnemonic
evmwlssiaaw
SPE
APU
se_mfctr
VLE
evmwlssianw
SPE
APU
se_mflr
VLE
evmwlumi
SPE
APU
se_mr
VLE
evmwlumia
SPE
APU
se_mtar
VLE
evmwlumiaaw
SPE
APU
se_mtctr
VLE
evmwlumianw
SPE
APU
se_mtlr
VLE
evmwlusiaaw
SPE
APU
se_mullw
VLE
evmwlusianw
SPE
APU
se_neg
VLE
evmwsmf
SPE
APU
se_not
VLE
evmwsmfa
SPE
APU
se_or
VLE
evmwsmfaa
SPE
APU
se_slw
VLE
evmwsmfan
SPE
APU
se_slwi
VLE
evmwsmi
SPE
APU
se_sraw
VLE
evmwsmia
SPE
APU
se_srawi
VLE
evmwsmiaa
SPE
APU
se_srw
VLE
evmwsmian
SPE
APU
se_srwi
VLE
evmwssf
SPE
APU
se_stb
VLE
evmwssfa
SPE
APU
se_sth
VLE
evmwssfaa
SPE
APU
se_stw
VLE
evmwssfan
SPE
APU
se_sub
VLE
evmwumi
SPE
APU
se_subf
VLE
DocID13694 Rev 2
Book E
Classic
EIS
RM0004
Instruction model
Table 147. List of instructions (continued)
Mnemonic
Book E
Classic
EIS
Mnemonic
evmwumia
SPE
APU
se_subi
VLE
evmwumiaa
SPE
APU
se_subi.
VLE
evmwumian
SPE
APU
slbia

evnand
SPE
APU
slbie

evneg
SPE
APU
sldi

evnor
SPE
APU
slw[.]
evor
SPE
APU
srad.

evorc
SPE
APU
sradi.

evrlw
SPE
APU
srawi[.]


evrlwi
SPE
APU
sraw[.]


evrndw
SPE
APU
srd.
evsel
SPE
APU
srw[.]


evslw
SPE
APU
stb


evslwi
SPE
APU
stbu


evsplatfi
SPE
APU
stbux


evsplati
SPE
APU
stbx


evsrwis
SPE
APU
std

evsrwiu
SPE
APU
stdcx.

evsrws
SPE
APU
stdu

evsrwu
SPE
APU
stdux

evstdd
SPE
APU
stdx

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
Classic
EIS


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Instruction model
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Table 147. List of instructions (continued)
Mnemonic
248/1025
Book E
Classic
EIS
Mnemonic
Book E
Classic
evstddx
SPE
APU
stfd


evstdh
SPE
APU
stfdu


evstdhx
SPE
APU
stfdux


evstdw
SPE
APU
stfdx


evstdwx
SPE
APU
stfiwx


evstwhe
SPE
APU
stfs


evstwhex
SPE
APU
stfsu


evstwho
SPE
APU
stfsux


evstwhox
SPE
APU
stfsx


evstwwex
SPE
APU
sth


evstwwex
SPE
APU
sthbrx


evstwwo
SPE
APU
sthu


evstwwox
SPE
APU
sthux


evsubfsmiaaw
SPE
APU
sthx


evsubfssiaaw
SPE
APU
stmw


evsubfumiaaw
SPE
APU
stswi


evsubfusiaaw
SPE
APU
stswx


evsubfw
SPE
APU
stw


evsubifw
SPE
APU
stwbrx


evxor
SPE
APU
stwcx.


extsb[.]


stwu


extsh[.]


stwux


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Instruction model
Table 147. List of instructions (continued)
Mnemonic
extsw.
Book E
Classic
EIS
64-bit only
Mnemonic
Book E
Classic
stwx


e_add16i
VLE
subfc[o][.]


e_add2i.
VLE
subfe[o][.]


e_add2is
VLE
subfic


e_addi
VLE
subfme[o][.]


e_addi.
VLE
subfze[o][.]


e_addic
VLE
subf[o][.]


e_addic.
VLE
sync
Now
msync

e_and2i.
VLE
tlbia

e_and2is.
VLE
tlbie

e_andi[.]
VLE
tlbivax

e_b
VLE
tlbre

e_bc
VLE
tlbsx

e_bcl
VLE
tlbsync

e_bl
VLE
tlbwe

e_cmp16i
VLE
tw


e_cmph
VLE
twi


e_cmph16i
VLE
wrtee

e_cmphl
VLE
wrteei

e_cmphl16i
VLE
xori[.]


e_cmpi
VLE
xor[.]


e_cmpl16i
VLE
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5
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Interrupts and exceptions
This chapter provides a general description of the Book E exception and interrupt models as
they are implemented on ST processors. It identifies and describes the portions of the
interrupt model that are defined by the Book E architecture and by the Book E
implementation standards (EIS).
Note:
Terminology
The Book E architecture has defined additional resources for interrupt handling. As a result,
the terms ‘interrupt’ and ‘exception’ differ somewhat from their use in previous ST
documentation, such as the Programming Environments Manual. Use of these terms is now
as follows:
•
An interupt is the action in which the processor saves its context (typically the machine
state register (MSR) and next instruction address) and begins execution at a predetermined
interrupt handler address with a modified MSR.
•
An exception is the event that, if enabled, causes the processor to take an interrupt.
Book E describes exceptions as being generated by signals from internal and external
peripherals, instructions, the internal timer facility, debug events, or error conditions.
5.1
Overview
Book E defines are two categories of interrupts, noncritical and critical, for which separate
resources are provided to save state when the interrupt is taken and to restore state when
the interrupt handler returns control to the interrupted program.
Using the model provided by the Book E architecture, the EIS defines additional interrupt
types which may be implemented on ST Book E devices. These are described in Table 148.
Table 148. Interrupt types
Category
Description
Programming resources
Book E defined
First-level interrupts that let the processor
change program flow to handle conditions
generated by external signals, errors, or
Noncritical
unusual conditions arising from program
interrupts
execution or from programmable timerrelated events. These interrupts are largely
identical to those defined by the OEA.
Critical
interrupts
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Book E–defined. Critical input, watchdog
timer, and debug interrupts. these interrupts
can be taken during a noncritical interrupt or
during regular program flow.
Book E defines the critical input, watchdog
timer, debug, and machine check interrupts
as critical interrupts. The EIS defines
additional resources for machine check and
debug interrupts.
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SRR0/SRR1 SPRs and rfi instruction.
Asynchronous noncritical interrupts can
be masked by the external interrupt
enable bit, MSR[EE].
Critical save and restore SPRs
(CSRR0/CSRR1) and the rfci
instruction. Critical input and watchdog
timer critical interrupts can be masked by
the critical enable bit, MSR[CE]. Debug
events can be masked by the debug
enable bit MSR[DE].
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Interrupts and exceptions
Table 148. Interrupt types
Category
Description
Programming resources
EIS defined (consult implementation documentation to 
determine whether these interrupts are implemented)
Machine
check
interrupt
Debug
interrupt
The EIS-defined machine check APU
provides a separate set of resources for the
machine check interrupt, which is similar to
the Book E–defined critical interrupt type.
Machine check save and restore SPRs
(MCSRR0/MCSRR1) and the rfmci
instruction. Can be masked by the
machine check enable bit, MSR[ME].
The EIS-defined debug APU provides a
separate set of resources for the debug
interrupt, which is similar to the Book E–
defined critical interrupt type.
Debug save and restore SPRs
(DSRR0/DSRR1) and the rfdi
instruction. Can be masked by the
machine check enable bit, MSR[DE].
The debug APU extends the Book E
debug register model for more detailed
control of debug resources.
All interrupts except EIS-defined interrupts are ordered within the two categories of
noncritical and critical, such that only one interrupt of each category is reported, and when
an interrupt is processed (taken), no program state is lost. Because save/restore register
pairs are serially reusable, care must be taken to preserve program state that may be lost
when an unordered interrupt is taken. (See Section 5.10.)
All interrupts except the machine check interrupt are context synchronizing as defined in
Section 4.2.3.6: Context synchronization. A machine check interrupt acts like a contextsynchronizing operation with respect to subsequent instructions; that is, a machine check
interrupt need not satisfy items 1 and 2 of Section 4.2.3.6: Context synchronization, but
satisfies items 3 and 4.
5.2
EIs interrupt definitions
This section gives an overview of additions and modifications to the Book E interrupt model
defined by the EIS. Specific details are also provided throughout this chapter. Except for the
following, the core complex reports exceptions as specified in Book E:

The machine check exception differs as follows:
–
It is not processed as a critical interrupt, but uses MCSRR0 and MCSRR1 for
saving the return address and the MSR in case the machine check is recoverable.
–
Return From Machine Check Interrupt instruction (rfmci) is implemented to
support the return to the address saved in MCSRR0.
–
A machine check syndrome register, MCSR, logs the cause of the machine check
(instead of ESR).
The core complex reports the machine check exception as described in Section 5.7.2.

The following interrupts are defined for use with the embedded floating-point and
signal-processing (SPE) APUs:
–
SPE/embedded floating-point unavailable interrupt. IVOR32 (SPR 528) contains
the vector offset. 
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See Section 5.7.17.1: SPE/embedded floating-point APU unavailable interrupt.
–
Embedded floating-point data interrupt. IVOR33 (SPR 529) contains the vector
offset. See Section 5.7.17.2: Embedded floating-point data interrupt.
–
Embedded floating-point round interrupt. IVOR34 (SPR 530) contains the vector
offset. See Section 5.7.17.3: Embedded floating-point round interrupt.
The following additional bits are defined to support SPE and SPFP exceptions:
–
Note:
SPFP instructions require MSR[SPE] to be set. An attempt to execute an SPFP instruction
when MSR[SPE] is 0 causes an SPE APU unavailable interrupt. Section 4.6.1.2: Embedded
vector and scalar floating-point APU instructions, lists affected instructions.
–
5.2.1
MSR[38] is defined as the vector available bit (SPE). If this bit is clear and
software attempts to execute any of the SPE instructions, the SPE unavailable
interrupt is taken. If this bit is set, software can execute any SPE instructions.
ESR[SPE], the SPE exception bit, is set when the processor reports an exception
related to the execution of SPFP or SPE instructions.

The debug exception implementation does not support IAC3, IAC4, DAC3, and DAC4
comparisons.

The core complex supports instruction address compare (IAC1 and IAC2) and data
address compare (DAC1 and DAC2) for effective addresses only. Real-address
support is not provided.

Some implementations do not support the Book E-defined floating-point unavailable
and auxiliary processor unavailable interrupts.

Data value compare (DVC) debug exceptions are not supported.

The interrupt priorities differ from those specified in Book E as described in
Section 5.11.

Alignment exceptions. Vector operations can cause alignment exceptions as described
in Section 5.7.6.

Book E and the machine check APU define sources of externally generated interrupts.
Recoverability from interrupts
All interrupts except some machine check interrupts are recoverable. The state of the core
complex (return address and MSR contents) is saved when a machine check interrupt is
taken. The conditions that cause a machine check may or may not prohibit recovery.
5.3
Interrupt registers
Table 149 summarizes registers used for interrupt handling. These registers are described
in detail in Chapter 3: Register model.
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Interrupts and exceptions
Table 149. Interrupt registers defined by the PowerPC architecture
Register
Description
Book E Interrupt Registers
Save/restore
register 0 (SRR0)
On a noncritical interrupt, SRR0 is set to the current or next instruction
address. When rfi is executed, instruction execution continues at the address
in SRR0. In general, SRR0 contains the address of the instruction that caused
the noncritical interrupt or the address of the instruction to return to after a
noncritical interrupt is serviced.
Save/restore
register 1 (SRR1)
When a noncritical interrupt is taken, MSR contents are placed into SRR1.
When rfi is executed, SRR1 contents are placed into the MSR. SRR1 bits that
correspond to reserved MSR bits are also reserved. Note that an MSR bit that
is reserved may be altered by rfi.
Critical save/restore
register 0 (CSRR0)
When a critical interrupt is taken, CSRR0 is set to the current or next
instruction address. When rfci is executed, instruction execution continues at
the address in CSRR0. In general, CSRR0 contains the address of the
instruction that caused the critical interrupt, or the address of the instruction to
return to after a critical interrupt is serviced.
Critical save/restore
register 1 (CSRR1)
When a critical interrupt is taken, MSR contents are placed into CSRR1. When
rfci is executed, CSRR1 contents are placed into the MSR. CSRR1 bits that
correspond to reserved MSR bits are also reserved. Note that an MSR bit that
is reserved may be altered by rfci.
Data exception
address register
(DEAR)
DEAR contains the address referenced by a load, store, or cache
management instruction that caused an alignment, data TLB miss, or data
storage interrupt.
Interrupt vector
prefix register
(IVPR)
IVPR[32–47] provides the high-order 48 bits of the address of the interrupt
handling routine for each interrupt type. The 16-bit vector offsets are
concatenated to the right of IVPR to form the address of the interrupt handling
routine. IVPR[48–63] are reserved.
Provides a syndrome to differentiate between exceptions that can generate
the same interrupt type. When one of these types of interrupts is generated,
bits corresponding to the specific exception that generated the interrupt are
set and all other ESR bits are cleared. Other interrupt types do not affect the
ESR. ESR does not need to be cleared by software. Section 3.9.1.8:
Exception syndrome register (ESR), shows ESR bit definitions.
An implementation may define additional ESR bits to identify implementationspecific or architected interrupt types; the EIS defines ESR[ILK] and
ESR[SPE].
Exception syndrome Note: System software may need to identify the type of instruction that caused
the interrupt and examine the TLB entry and ESR to fully identify the
register (ESR)
exception or exceptions. For example, because both protection violation
and byte-ordering exception conditions may be present, and either
causes a data storage interrupt, system software would have to look
beyond ESR[BO], such as the state of MSR[PR] in SRR1 and the TLB
entry page protection bits, to determine if a protection violation also
occurred.
The EIS defines ESR[56] as the SPE exception bit (SPE). It is set when the
processor reports an exception related to the execution of an SPFP or SPE
instruction. Note that the EIS definition of the machine check interrupt uses
the machine check syndrome register (MCSR) rather than the ESR.
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Table 149. Interrupt registers defined by the PowerPC architecture (continued)
Register
Description
Holds the quad-word index from the base address provided by the IVPR for
each interrupt type. IVOR0–IVOR15 are provided for defined interrupt types.
SPR numbers corresponding to IVOR16–IVOR31 are reserved. IVOR[32–
47,60–63] are reserved. SPR numbers for IVOR32–IVOR63 are allocated for
implementation-dependent use. (IVOR32–IVOR34 (SPR 528–530) are used
by interrupts defined by the EIS.) IVOR assignments are shown below.
Interrupt vector
offset registers
(IVORs)
Machine state
register (MSR)
Book E–defined interrupts
IVOR NumberInterrupt Type
IVOR0Critical input
IVOR1Machine check
IVOR2Data storage
IVOR3Instruction storage
IVOR4External input
IVOR5Alignment
IVOR6Program
IVOR7Floating-point unavailable
IVOR8System call
IVOR9Auxiliary processor unavailable
IVOR10Decrementer
IVOR11Fixed-interval timer interrupt
IVOR12Watchdog timer interrupt
IVOR13Data TLB error
IVOR14Instruction TLB error
IVOR15Debug
IIVOR16–IVOR31Reserved
EIS-defined interrupts (IVOR32–
IVOR63)
IVOR NumberInterrupt Type
IVOR32SPE APU unavailable
IVOR33Embedded floating-point data
IVOR34Embedded floating-point
round
IVOR35Performance monitor
IVOR36Processor doorbell
IVOR37Processor doorbell critical
MSR[38] is defined as the vector available bit (SPE). It functions as follows:
0: If software attempts to execute an instruction that tries to access the upper
word of a 64-bit GPR, an SPE APU unavailable interrupt is taken.
1: Software can execute any embedded floating-point or SPE instructions.
EIS-Specific Interrupt Registers
When a machine check interrupt is taken, MCSRR0 is set to the current or next
Machine check
save/restore register instruction address. When rfmci is executed, instruction execution continues
0 (MCSRR0)
at the address in MCSRR0. In general, MCSRR0 contains the address of the
instruction that caused the machine check interrupt, or the address of the
instruction to return to after a machine check interrupt is serviced.
Machine check
When a machine check interrupt is taken, MSR contents are placed into
save/restore register MCSRR1. When rfmci is executed, MCSRR1 contents are restored to MSR.
1 (MCSRR1)
MCSRR1 bits that correspond to reserved MSR bits are also reserved. Note
that an MSR bit that is reserved may be altered by rfmci.
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Interrupts and exceptions
Table 149. Interrupt registers defined by the PowerPC architecture (continued)
Register
5.4
Description
Machine check
syndrome register
(MCSR)
When a machine check interrupt is taken, MCSR is updated to differentiate
among machine check conditions. MCSR also indicates whether a machine
check condition is recoverable. ABIST status is logged in MCSR[48–54].
These read-only bits do not initiate machine check (or any other interrupt). An
ABIST bit being set indicates an error being detected in the corresponding
module.
Processors that do not implement the machine check APU use the Book E–
defined ESR for this purpose.
Section 3.9.1.15: Machine check syndrome register (MCSR), shows MCSR bit
definitions.
Machine check
address register
(MCAR)
When a machine check interrupt is taken, MCAR is updated with the address
of the data associated with the machine check. Note that if a machine check
interrupt is caused by a signal, the MCAR contents are not meaningful. See
Section 3.9.1.14: Machine check address register (MCAR/MCARU).
Exceptions
Exceptions are caused directly by instruction execution or by an asynchronous event. In
either case, the exception may cause one of several types of interrupts to be invoked.
The following examples are of exceptions caused directly by instruction execution:

An attempt to execute a reserved-illegal instruction (illegal instruction exception-type
program interrupt)

An attempt by an application program to execute a privileged instruction or to access a
privileged SPR (privileged instruction exception-type program interrupt)

In general, an attempt by an application program to access a nonexistent SPR
(unimplemented operation instruction exception-type program interrupt). Note the
following behavior defined by the EIS:
–
If MSR[PR] = 1 (user mode), SPR bit 5 = 0 (user-accessible SPR), and the SPR
number is invalid, an illegal instruction exception is taken.
–
If MSR[PR] = 0 (supervisor mode) and the SPR number is invalid, an illegal
instruction exception is taken.
–
If MSR[PR] = 1, SPR bit 5 = 1, and invalid SPR address (supervisor-only SPR), a
privileged instruction exception-type program interrupt is taken.

Execution of a defined instruction using an invalid form (illegal instruction exceptiontype program interrupt, unimplemented operation exception-type program interrupt, or
privileged instruction exception-type program interrupt).

An attempt to access a location that is either unavailable (instruction or data TLB error
interrupt) or not permitted (instruction or data storage interrupt)

An attempt to access a location with an effective address alignment not supported by
the implementation (alignment interrupt)

Execution of a System Call (sc) instruction (system call interrupt)

Execution of a trap instruction whose trap condition is met (trap interrupt type)

Execution of a floating-point instruction when floating-point instructions are unavailable
(floating-point unavailable interrupt)
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
Execution of a floating-point instruction that causes a floating-point enabled exception
to exist (enabled exception-type program interrupt)

Execution of a defined instruction that is not implemented (illegal instruction exception
or unimplemented operation exception-type program interrupt)

Execution of an allocated instruction that is not implemented (illegal instruction
exception or unimplemented operation exception-type program interrupt)

Execution of an allocated instruction when the auxiliary instruction is unavailable
(auxiliary unavailable interrupt)

Execution of an allocated instruction that causes an auxiliary enabled exception
(enabled exception-type program interrupt)
Invocation of an interrupt is precise, except that if one of the imprecise modes for invoking a
floating-point enabled exception-type program interrupt is in effect, the invocation may be
imprecise. When the interrupt is invoked imprecisely, the excepting instruction does not
appear to complete before the next instruction starts (because the invocation of the interrupt
required to complete execution has not occurred).
5.5
Interrupt classes
All interrupts except machine check are categorized by two independent characteristics:

Critical/noncritical. Some interrupt types demand immediate attention even if other
interrupt types being processed have not had the opportunity to save the machine state
(that is, return address and captured state of the MSR). To enable taking a critical
interrupt immediately after a noncritical interrupt is taken (that is, before the machine
state is saved), two sets of save/restore register pairs are provided. Critical interrupts
use CSRR0/CSRR1, and noncritical interrupts use SRR0/SRR1.

Asynchronous/synchronous. Asynchronous interrupts are caused by events external to
instruction execution; synchronous interrupts are caused by instruction execution and
are either precise or imprecise. Table 150 describes asynchronous and synchronous
interrupts.
Table 150. Asynchronous and synchronous interrupts
Class
Description
Caused by events independent from instruction execution. For asynchronous
interrupts, the address reported to the interrupt handling routine is the address of
Asynchronous
the instruction that would have executed next, had the asynchronous interrupt not
occurred.
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Table 150. Asynchronous and synchronous interrupts (continued)
5.5.1
Class
Description
Synchronous,
Precise
Caused directly by instruction execution. Synchronous interrupts are precise or
imprecise.
These interrupts precisely indicate the address of the instruction causing the
exception or, for certain synchronous, precise interrupt types, the address of the
immediately following instruction. When the execution or attempted execution of an
instruction causes a synchronous, precise interrupt, the following conditions exist at
the interrupt point:
Whether SRR0 or CSRR0 addresses the instruction causing the exception or the
next instruction is determined by the interrupt type and status bits.
An interrupt is generated such that all instructions before the instruction causing the
exception appear to have completed with respect to the executing processor.
However, some accesses associated with these preceding instructions may not
have been performed with respect to other processors and mechanisms.
The exception-causing instruction may appear not to have begun execution (except
for causing the exception), may be partially executed, or may have completed,
depending on the interrupt type. See Section 5.9.
Architecturally, no instruction beyond the exception-causing instruction executed.
Synchronous,
Imprecise
Imprecise interrupts may indicate the address of the instruction causing the
exception that generated the interrupt or some instruction after that instruction.
When execution or attempted execution of an instruction causes an imprecise
interrupt, the following conditions exist at the interrupt point.
SRR0 or CSRR0 addresses either the exception-causing instruction or some
instruction following the exception-causing instruction that generated the interrupt.
An interrupt is generated such that all instructions preceding the instruction
addressed by SRR0 or CSRR0 appear to have completed with respect to the
executing processor.
If context synchronization forces the imprecise interrupt due to an instruction that
causes another exception that generates an interrupt (for example, alignment or
data storage interrupt), SRR0 addresses the interrupt-forcing instruction, which may
have partially executed (see Section 5.9).
If execution synchronization forces an imprecise interrupt due to an executionsynchronizing instruction other than msync or isync, SRR0 or CSRR0 addresses
the interrupt-forcing instruction, which appears not to have begun execution (except
for its forcing the imprecise interrupt). If the interrupt is forced by msync or isync,
SRR0 or CSRR0 may address msync or isync, or the following instruction.
If context or execution synchronization forces an imprecise interrupt, the instruction
addressed by SRR0 or CSRR0 may have partially executed (see Section 5.9). No
instruction following the instruction addressed by SRR0 or CSRR0 has executed.
Requirements for system reset generation
Book E does not specify a system reset interrupt as was defined in the AIM version of the
PowerPC architecture. A system reset is typically initiated in one of the following ways:

Assertion of a signal that resets the internal state of the core complex

By writing a 1 to DBCR0[34], if MSR[DE] = 1
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5.6
RM0004
Interrupt processing
Associated with each kind of interrupt is an interrupt vector, the address of the initial
instruction that is executed when an interrupt occurs.
Interrupt processing consists of saving a small part of the processor’s state in certain
registers, identifying the cause of the interrupt in another register, and continuing execution
at the corresponding interrupt vector location. When an exception exists that causes an
interrupt to be generated and it has been determined that the interrupt can be taken, the
following steps are performed:
1.
SRR0 (for noncritical class interrupts) or CSRR0 (for critical class interrupts) or
MCSRR0 for machine check interrupts is loaded with an instruction address that
depends on the type of interrupt; see the specific interrupt description for details.
2.
The ESR or MCSR is loaded with information specific to the exception type. Note that
many interrupt types can only be caused by a single type of exception event, and thus
do not need nor use an ESR setting to indicate the cause of the interrupt.
3.
SRR1 (for noncritical class interrupts) or CSRR1 (for critical class interrupts) or
MCSRR1 for machine check interrupts is loaded with a copy of the MSR contents.
4.
New MSR values take effect beginning with the first instruction following the interrupt.
The MSR is updated as follows:
–
MSR[SPE,WE,EE,PR,FP,FE0,FE1,IS,DS] are cleared by all interrupts.
–
MSR[CE,DE] are cleared by critical class interrupts and unchanged by noncritical
class interrupts.
–
MSR[ME] is cleared by machine check interrupts and unchanged by other
interrupts.
–
Other defined MSR bits are unchanged by all interrupts.
MSR fields are described in Section 3.6.1: Machine state register (MSR).
5.
Instruction fetching and execution resumes, using the new MSR value, at a location
specific to the interrupt type (IVPR[32–47] || IVORn[48–59] || 0b0000)
The IVORn for the interrupt type is described in Table 151. IVPR and IVOR contents
are indeterminate upon reset and must be initialized by system software.
Interrupts do not clear reservations obtained with load and reserve instructions. The
operating system should do so at appropriate points, such as at process switch.
At the end of a noncritical interrupt handling routine, executing rfi causes the MSR to be
restored from the SRR1 contents and instruction execution to resume at the address
contained in SRR0. Likewise, rfci and rfmci perform the same function at the end of critical
and machine check interrupt handling routines respectively, using the critical and machine
check save/restore registers.
Note:
In general, at process switch, due to possible process interlocks and possible data
availability requirements, the operating system needs to consider executing the following:
stwcx.—Clears outstanding reservations to prevent pairing a lwarx in the old process with a
stwcx. in the new one
msync—Ensures that memory operations of an interrupted process complete with respect
to other processors before that process begins executing on another processor
rfi, rfci, rfmci, or isync—Ensures that instructions in the new process execute in the new
context
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5.7
Interrupts and exceptions
Interrupt definitions
Table 151 summarizes each interrupt type, the various exception types that may cause that
interrupt, the interrupt classification, which ESR bits can be set, which MSR bits can mask
the interrupt type, and which IVOR is used to specify the vector address.
Table 151. Interrupt and exception types
Exception
Class(1)
ESR(2)
Mask Bits
Notes
Page
A, C
—
MSR[CE]
(3)
on page
261
C
—
MSR[ME]
(4),(5)
on page
262
Access
SP
[SPE],[ST],
[FP,AP]
—
(6)
Load reserve or
store conditional
to write- through
required location
(W = 1)
SP
[ST]
—
(6)
Cache locking
SP
{DLK0,DLK1}
[DLK,ILK],[ST]
—
(7)
Byte ordering
SP
[ST],[FP,AP],BO
—
—
Access
SP
—
—
—
Byte ordering
SP
BO
—
—
A
—
MSR[EE]
(3)
on page
266
SP
[ST],[FP,AP],
[SPE,AP,ST]
—
—
on page
267
Illegal
SP
PIL
—
—
Privileged
SP
PPR,[AP]
—
—
Trap
SP
PTR
—
—
SP, SI
FP,[PIE]
MSR[FE0,FE1]
(8),(9)
Auxiliary
processor enabled
SP
AP
—
(9)
Unimplemented
op
SP
PUO,[FP,AP]
—
(11)
IVOR
Interrupt
Type
IVOR0
Critical input
Critical input
IVOR1
Machine
check
Machine check
IVOR2
IVOR3
Data storage
(DSI)
Instruction
storage (ISI)
IVOR4
External input
IVOR5
Alignment
IVOR6
Program
Exception Type
Floating-point
enabled
IVOR7
Floating-point unavailable
SP
IVOR8
System call
SP
IVOR9
Auxiliary processor unavailable
SP
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268
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270
—
—
on page
263
—
on page
271
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Table 151. Interrupt and exception types (continued)
Exception
Class(1)
ESR(2)
Mask Bits
Notes
Page
IVOR10 Decrementer
A
—
MSR[EE],
TCR[DIE]
—
on page
271
IVOR11 Fixed interval timer
A
—
MSR[EE],
TCR[FIE]
—
on page
272
A, C
—
MSR[CE],
TCR[WIE]
—
on page
273
IVOR
Interrupt
Type
Exception Type
IVOR12 Watchdog
IVOR13
Data TLB
error
Data TLB miss
SP
[SPE],[ST],
[FP,AP]
—
—
on page
273
IVOR14
Instruction
TLB error
Instruction TLB
miss
SP
—
—
—
on page
274
Trap
(synchronous)
A, SP, C
—
MSR[DE],
DBCR0[IDM]
—
Instruction
address compare
(synchronous)
A, SP, C
—
MSR[DE],
DBCR0[IDM]
—
Data address
compare
(synchronous)
A, SP, C
—
MSR[DE],
DBCR0[IDM]
—
Instruction
complete
SP, C
—
MSR[DE],
DBCR0[IDM]
(10)
Branch taken
SP, C
—
MSR[DE],
DBCR0[IDM]
(10)
Return from
interrupt
SP, C
—
MSR[DE],
DBCR0[IDM]
—
Interrupt taken
SI, C
—
MSR[DE],
DBCR0[IDM]
—
Unconditional
debug event
SI, C
—
MSR[DE],
DBCR0[IDM]
—
SPE APU
unavailable
SP
—
—
(11)
on page
275
IVOR15 Debug
SPE /
Embedded
IVOR32
FP APU 
unavailable
on page
275
IVOR33
Embedded
FP data
Embedded FP
data exception
SP
—
—
(11)
on page
276
IVOR34
Embedded
FP round
Embedded FP
round exception
SP
—
—
(11)
on page
276
1. A = asynchronous, C = critical, SI = synchronous, imprecise, SP = synchronous, precise
2. In general, when an interrupt causes an ESR bit or bits to be set (or cleared) as indicated in the table, it also causes all
other ESR bits to be cleared. Special rules may apply for implementation-specific ESR bits
Legend: xxx (no brackets) means ESR[xxx] is set.
[xxx] means ESR[xxx] could be set.
[xxx,yyy] means either ESR[xxx] or ESR[yyy] may be set, but never both.
{xxx,yyy} means either ESR[xxx] or ESR[yyy] may be set, or possibly both.
3. Although not part of Book E, system interrupt controllers commonly provide independent mask and status bits for critical
input and external input interrupt sources.
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4. Machine check interrupts are not asynchronous or synchronous. See Section 5.7.2.
5. Machine check status information is commonly provided as part of the system implementation but is not part of Book E.
6. Software must examine the instruction and the subject TLB entry to determine the exact cause of the interrupt.
7. Cache locking and cache locking exceptions are implementation-dependent.
8. The precision of the floating-point enabled exception type is controlled by MSR[FE0,FE1], as described in Table 161. See
Section 5.7.7. Also, exception status on the exact cause is available in the FPSCR. (See Section 3.4.2: Floating-point
status and control register (FPSCR))
The precision of the auxiliary processor enabled exception type program interrupt is implementation-dependent.
9. Auxiliary processor exception status is commonly provided as part of the implementation and is not part of Book E.
10. Instruction complete and branch taken debug events are defined only for MSR[DE] = 1 for internal debug mode
DBCR0[IDM] = 1. In other words, for internal debug mode with MSR[DE] = 0, instruction complete and branch taken debug
events cannot occur, no DBSR status bits are set, and no subsequent imprecise debug interrupt can occur.
11. EIS-defined exception
5.7.1
Critical input interrupt
A critical input interrupt occurs when no higher priority exception exists, a critical input
exception is presented to the interrupt mechanism, and MSR[CE] = 1. The specific definition
of a critical input exception is implementation-dependent but is typically caused by assertion
of an asynchronous signal that is part of the system. In addition to MSR[CE],
implementations may provide other ways to mask the critical input interrupt.
CSRR0, CSRR1, and MSR are updated as shown in Table 152.
Table 152. Critical input interrupt register settings
Register
Setting
CSRR0
Set to the effective address of the next instruction to be executed
CSRR1
Set to the MSR contents at the time of the interrupt
MSR
ME is unchanged. All other MSR bits are cleared.
Instruction execution resumes at address IVPR[32–47] || IVOR0[48–59] || 0b0000.
Critical interrupt input signals are level sensitive; to guarantee that the core complex can
take a critical input interrupt, the critical input interrupt signal must be asserted until the
interrupt is taken. Otherwise, whether the core complex takes an critical interrupt depends
on whether MSR[CE] is set when the critical interrupt signal is asserted.
Note:
To avoid redundant critical input interrupts, software must take any actions required by the
implementation to clear any critical input exception status before reenabling MSR[CE].
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Machine check interrupt
The EIS defines the machine check APU, which differs from the Book E definition of the
machine check interrupt as follows:

Book E defines machine check interrupts as critical interrupts, but the machine check
APU treats them as a distinct interrupt type.

Machine check is no longer a critical interrupt but uses MCSRR0 and MCSRR1 to save
the return address and the MSR in case the machine check is recoverable.

Return from machine check interrupt instruction (rfmci) is implemented to support the
return to the address saved in MCSRR0.

An address related to the machine check may be stored in MCAR, according to
Table 153.

A machine check syndrome register, MCSR, is used to log the cause of the machine
check (instead of ESR). The MCSR is described in Table 153.
The following general information applies to both the Book E and EIS definitions. A machine
check interrupt occurs when no higher priority exception exists, a machine check exception
is presented to the interrupt mechanism, and MSR[ME] = 1. Specific causes of machine
check exceptions are implementation-dependent, as are the details of the actions taken on
a machine check interrupt.
Machine check interrupts are typically caused by a hardware or memory subsystem failure
or by an attempt to access an invalid address. They may be caused indirectly by execution
of an instruction, but may not be recognized or reported until long after the processor has
executed past the instruction that caused the machine check. As such, machine check
interrupts are not thought of as synchronous or asynchronous nor as precise or imprecise.
The following general rules apply:

No instruction after the one whose address is reported to the machine check interrupt
handler in MCSRR0 has begun execution.

The instruction whose address is reported to the machine check interrupt handler in
MCSRR0 and all prior instructions may or may not have completed successfully. All
instructions certain to complete appear to have done so within the context existing
before the machine check interrupt. No further interrupts (other than possible additional
machine check interrupts) occur as a result of those instructions.
If MSR[ME] is cleared, the processor enters checkstop state immediately on detecting the
machine check condition.
When a machine check interrupt is taken, registers are updated as shown in Table 153.
Table 153. Machine check interrupt settings
Register
Setting
Set to an instruction address. As closely as possible, set to the effective address of an
CSRR0(1) instruction that was executing or about to be executing when the machine check
exception occurred.
CSRR1 (1) Set to the MSR contents at the time of the interrupt
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UCLE, SPE, WE, CE, EE, PR, FP, ME, FE0, FE1, DE, IS, DS, PMM, and RI are cleared.
ESR
Implementation-dependent. The EIS uses the MCSR rather than the ESR.
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Table 153. Machine check interrupt settings (continued)
Register
Setting
Machine Check APU Registers
On a best-effort basis, the core complex sets this to an effective address of some
MCSRR0 instruction that was executing or about to be executing when the machine check
condition occurred.
MCSRR1
MSR[37–38,46–55,57–59,61–63] are loaded with equivalent MSR bits. All other bits are
reserved.
MCAR/
MCARU
When a machine check interrupt is taken, the machine check address register is updated
with the address of the data associated with the machine check. Note that if a machine
check interrupt is caused by a signal, the MCAR contents are not meaningful. See
Section 3.9.1.14: Machine check address register (MCAR/MCARU).
MCARU is an alias to the upper 32 bits of MCAR.
MCSR
Set according to the machine check condition. See Table 20.
1. These registers are used if the machine check APU is not implemented.
Instruction execution resumes at address IVPR[32–47] || IVOR1[48–59] || 0b0000.
Note:
If a memory subsystem error causes a machine check interrupt, the subsystem may return
incorrect data, which may be placed into registers or on-chip caches.
For implementations on which a machine check interrupt is caused by referring to an invalid
physical address, executing dcbz or dcba can cause a delayed machine check interrupt by
establishing a data cache block associated with an invalid physical address. A machine
check interrupt can occur later if and when an attempt is made to write that block to main
memory, for example as the result of executing an instruction that causes a cache miss for
which the block is the target for replacement or as the result of executing dcbst or dcbf.
5.7.3
Data storage interrupt
A data storage interrupt (DSI) occurs when no higher priority exception exists and a data
storage exception is presented to the interrupt mechanism. Table 154 describes exception
conditions for a data storage interrupt as defined by Book E.
Table 154. Data storage interrupt exception conditions
Exception
Read access
control
exception
Cause
Occurs when either of the following conditions exists:
– In user mode (MSR[PR] = 1), a load or load-class cache management instruction
attempts to access a memory location that is not user-mode read enabled (page
access control bit UR = 0).
– In supervisor mode (MSR[PR] = 0), a load or load-class cache management
instruction attempts to access a location that is not supervisor-mode read
enabled (page access control bit SR = 0).
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Table 154. Data storage interrupt exception conditions (continued)
Exception
Cause
Write access
control
exception
Occurs when either of the following conditions exists:
– In user mode (MSR[PR] = 1), a store or store-class cache management
instruction attempts to access a location that is not user-mode write enabled
(page access control bit UW = 0).
– In supervisor mode (MSR[PR] = 0), a store or store-class cache management
instruction attempts to access a location that is not supervisor-mode write
enabled (page access control bit SW = 0).
Byte-ordering
exception
The implementation cannot access data in the byte order specified by the page’s
endian attribute.
Note: The byte-ordering exception is provided to assist implementations that
cannot support dynamically switching byte ordering between consecutive
accesses, the byte order for a class of accesses, or misaligned accesses
using a specific byte order.
Load/store accesses that cross a page boundary such that endianness changes
cause a byte-ordering exception.
Cache locking
exception
(EIS) The locked state of one or more cache lines has the potential to be altered.
This exception is implementation-dependent. A cache locking exception occurs
with the execution of icbtls, icblc, dcbtls, dcbtstls, or dcblc when (MSR[PR] = 1)
and (MSR[UCLE] = 0). ESR is set as follows:
– For icbtls and icblc, ESR[ILK] is set.
– For dcbtls, dcbtstls, or dcblc, ESR[DLK] is set. Book E refers to this as a
cache-locking exception.
Occurs when either of the following conditions exists:
– An attempt is made to execute a load and reserve or store conditional instruction
from or to a location that is write-through required or caching inhibited. (If the
Storage
interrupt does not occur, the instruction executes correctly.)
synchronization – A store conditional instruction produces an effective address for which a normal
exception
store would cause a data storage interrupt but the processor does not have the
reservation from a load and reserve instruction. Book E states that it is
implementation-dependent whether a data storage interrupt occurs. The EIS
defines that the data storage interrupt is taken.
Instructions icbt, dcbt, dcbtst, and dcba, and lswx or stswx with a length of zero cannot
cause a data storage interrupt, regardless of the effective address.
Note:
icbi and icbt are treated as loads from the addressed byte with respect to address
translation and protection. They use MSR[DS], not MSR[IS], to determine translation for
their operands. Instruction storage interrupts and instruction TLB error interrupts are
associated with instruction fetching and not execution. Data storage interrupts and data TLB
error interrupts are associated with the execution of instruction cache management
instructions.
When a data storage interrupt occurs, the processor suppresses execution of the instruction
causing the data storage exception.
SRR0, SRR1, ESR, MSR, and DEAR, are updated as follows:
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Table 155. Data Storage Interrupt Register Settings
Register
Setting
SRR0
Set to the effective address of the instruction causing the interrupt
SRR1
Set to the MSR contents at the time of the interrupt
ESR
FP Set if the instruction causing the interrupt is a floating-point load or store; otherwise
cleared
ST Set if the instruction causing the interrupt is a store or store-class cache management
instruction; otherwise cleared
DLK DLK is set when a DSI occurs because dcbtls, dcbtstls, or dcblc is executed in
user mode and MSR[UCLE] = 0.
AP Set if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise cleared
BO Set if the instruction caused a byte-ordering exception; otherwise cleared
All other defined ESR bits are cleared.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
DEAR
Set to the effective address of a byte that lies both within the range of bytes being
accessed by the access or cache management instruction and within the page whose
access caused the exception
Instruction execution resumes at address IVPR[32–47] || IVOR2[48–59] || 0b0000.
5.7.4
Instruction storage interrupt
An instruction storage interrupt occurs when no higher priority exception exists and an
instruction storage exception is presented to the interrupt mechanism. Instruction storage
exception conditions are described in Table 156.
Table 156. Instruction storage interrupt exception conditions
Exception
Cause
Execute access
control exception
In user mode, an instruction fetch attempts to access a memory location that is
not user mode execute enabled (page access control bit UX = 0).
In supervisor mode, an instruction fetch attempts to access a memory location
that is not supervisor mode execute enabled (page access control bit SX = 0).
Byte-ordering
exception
The implementation cannot fetch the instruction in the byte order specified by the
page’s endian attribute. The EIS defines that accesses that cross a page
boundary such that endianness changes cause a byte-ordering exception.
Note that Book E provides this exception to assist implementations that cannot dynamically
switch byte ordering between consecutive accesses, do not support the byte order for a
class of accesses, or do not support misaligned accesses using a specific byte order.
When an instruction storage interrupt occurs, the processor suppresses execution of the
instruction causing the exception.
SRR0, SRR1, MSR, and ESR are updated as shown in Table 157.
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Table 157. Instruction storage interrupt register settings
Register
Note:
Setting
SRR0
Set to the effective address of the instruction causing the instruction storage interrupt
SRR1
Set to the MSR contents at the time of the interrupt
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR
BO is set if the instruction fetch caused a byte-ordering exception; otherwise cleared. All
other defined ESR bits are cleared.
Permissions violation and byte-ordering exceptions are not mutually exclusive. Even if
ESR[BO] is set, system software must examine the TLB entry accessed by the fetch to
determine whether a permissions violation also may have occurred.
Instruction execution resumes at address IVPR[32–47] || IVOR3[48–59] || 0b0000.
5.7.5
External input interrupt
An external input interrupt occurs when no higher priority exception exists, an external input
exception is presented to the interrupt mechanism, and MSR[EE] = 1. The specific definition
of an external input exception is implementation-dependent and is typically caused by
assertion of an asynchronous signal that is part of the processing system.
To guarantee that the core complex can take an external interrupt, the external interrupt pin
must be asserted until the interrupt is taken. Otherwise, whether the external interrupt is
taken depends on whether MSR[EE] is set when the external interrupt signal is asserted.
In addition to MSR[EE], implementations may provide other ways to mask this interrupt.
SRR0, SRR1, and MSR are updated as shown in Table 158.
Table 158. External input interrupt register settings
Register
Setting
SRR0
Set to the effective address of the next instruction to be executed
SRR1
Set to the MSR contents at the time of the interrupt
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
Instruction execution resumes at address IVPR[32–47] || IVOR4[48–59] || 0b0000.
Note:
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To avoid redundant external input interrupts, software must take any actions required to
clear any external input exception status before reenabling MSR[EE].
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Interrupts and exceptions
Alignment interrupt
An alignment interrupt occurs when no higher priority exception exists and an alignment
exception is presented to the interrupt mechanism. An alignment exception may occur when
an implementation cannot perform a data access for one of the following reasons:

The operand of a load or store is not aligned.

The instruction is a move assist, load multiple, or store multiple.

A dcbz operand is in write-through-required or caching-inhibited memory, or dcbz is
executed in an implementation with no data cache or a write-through data cache.

The operand of a store, except store conditional, is in write-through required memory.
The EIS defines the following alignment exception conditions:

Execution of a dcbz references a page marked as write-through or cache inhibited.

A load multiple word instruction (lmw) reads an address that is not a multiple of four.

A lwarx or stwcx. instruction references an address that is not a multiple of four.

SPFP and SPE APU instructions are not aligned on a natural boundary. A natural
boundary is defined by the size of the data element being accessed.

A vector operation reports an exception if the physical address of the following
instructions is not aligned to the 64-bit boundary: evldd, evlddx, evldw, evldwx,
evldh, evldhx, evstdd, evstddx, evstdw, evstdwx, evstdh, and evstdhx. Table 159
describes additional ESR settings.
For lmw and stmw with a non–word-aligned operand and for load and reserve and store
conditional instructions with an misaligned operand, an implementation may yield boundedly
undefined results instead of causing an alignment interrupt. A store conditional to a writethrough required location may either cause an alignment or data storage interrupt or may
correctly execute the instruction. For all other cases listed above, an implementation may
execute the instruction correctly instead of causing an alignment interrupt. For dcbz, correct
execution means clearing each byte of the block in main memory.
Note:
Book E does not support use of an misaligned effective address by load and reserve and
store conditional instructions. If an misaligned effective address is specified, the alignment
interrupt handler should treat the instruction as a programming error and must not attempt to
emulate the instruction.
When an alignment interrupt occurs, the processor suppresses the execution of the
instruction causing the alignment exception.
SRR0, SRR1, MSR, DEAR, and ESR are updated as shown in Table 159.
Table 159. Alignment interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction causing the alignment interrupt
SRR1
Set to the MSR contents at the time of the interrupt
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
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Table 159. Alignment interrupt register settings (continued)
Register
Setting
DEAR
Set to the EA of a byte that is both within the range of the bytes being accessed by the
memory access or cache management instruction, and within the page whose access
caused the alignment exception
ESR
FP Set if the instruction causing the interrupt is a floating-point load or store; otherwise
cleared
ST Set if the instruction causing the interrupt is a store; otherwise cleared
AP Set if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise cleared
The following bits may be affected for vector alignment exception conditions:
SPE Set
AP Set (May not be supported on all processors)
ST Set only if the instruction causing the exception is a store and is cleared for a load
All other defined ESR bits are cleared.
Instruction execution resumes at address IVPR[32–47] || IVOR5[48–59] || 0b0000.
5.7.7
Program interrupt
A program interrupt occurs when no higher priority exception exists and a program
exception is presented to the interrupt mechanism. A program interrupt is caused when any
of the following exceptions occurs during execution of an instruction.
Table 160. Program interrupt exception conditions
Exception
Cause
Floating-point
enabled exception
Caused when (MSR[FE0] | MSR[FE1]) & FPSCR[FEX] = 1. FPSCR[FEX] is set
by the execution of a floating-point instruction that causes an enabled
exception, including the case of a Move to FPSCR instruction that causes an
exception bit and the corresponding enable bit both to be 1. Note that in this
context, the term ‘enabled exception’ refers to the enabling provided by FPSCR
control bits. See Section 3.4.2: Floating-point status and control register
(FPSCR). Whether the interrupt is precise or imprecise is determined by
MSR[FE0,FE1], as described in Table 20.
Auxiliary processor
Implementation dependent
enabled exception
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Table 160. Program interrupt exception conditions (continued)
Exception
Cause
Illegal instruction
exception
Always occurs when execution of any of the following kinds of instructions is
attempted.
– A reserved-illegal instruction
– In user mode, an mtspr or mfspr that specifies an SPRN value with
SPRN[5] = 0 (user-mode accessible) that represents an unimplemented SPR
– (EIS) If an invalid SPR address is accessible only in supervisor mode and the
processor is in supervisor mode (MSR[PR] = 0), results are undefined.
– (EIS) If the invalid SPR address is accessible only in the supervisor mode and
the processor is in user mode (MSR[PR] = 1), a privileged instruction
exception is taken.
May occur when execution is attempted of any of the following kinds of
instructions. If the exception does not occur, the alternative is shown in
parentheses. See the user’s manual for the implementation.
– An instruction that is in invalid form (boundedly undefined results).
– An lswx instruction for which rA or rB is in the range of registers to be loaded
(boundedly undefined results)
– A reserved no-op instruction (no-operation performed is preferred).
– A defined or allocated instruction that is not implemented (unimplemented
operation exception). Unimplemented Book E instructions take an illegal
instruction exception.
– The EIS defines that an attempt to execute a 64-bit Book E instruction causes
an illegal instruction exception.
Privileged
instruction
exception
Occurs when MSR[PR] = 1 and execution is attempted of any of the following:
– A privileged instruction
– An mtspr or mfspr instruction that specifies a privileged SPR (SPRN[5] = 1)
– (EIS) An mtpmr or mfpmr instruction that specifies a privileged PMR
(PMRN[5] = 1)
Trap exception
Occurs when any of the conditions specified in a trap instruction are met.
Unimplemented
operation
exception
May occur when a defined or allocated instruction is encountered that is not
implemented. Otherwise an illegal instruction exception occurs. See the
reference manual for the implementation.
Whether a floating-point enabled interrupt is precise or imprecise is determined by
MSR[FE0,FE1], as described in Table 161.
Table 161. MSR[FE0,FE1] settings
FE0,FE1
01,10
Description
Imprecise. When such a program interrupt is taken, if the address saved in SRR0 is not
that of the instruction that caused the exception (that is, the instruction that caused
FPSCR[FEX] to be set), ESR[PIE] is set. Note that some implementations may ignore
these bit settings and treat all affected interrupts as precise.
11
Precise.
00
The interrupt is masked and the interrupt subsequently occurs if and when floating-point
enabled exception-type program interrupts are enabled by setting either or both FE0,FE1
and also causes ESR[PIE] to be set.
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SRR0, SRR1, MSR, and ESR are updated as shown in Table 162.
Table 162. Program interrupt register settings
Register
Description
SRR0
For all program interrupts except an enabled exception when in an imprecise mode (see
Table 164), set to the EA of the instruction that caused the interrupt.
For an imprecise enabled exception, set to the EA of the excepting instruction or of some
subsequent instruction that has not been executed (in which case ESR[PIE] is set). If the
instruction is msync or isync, SRR0 does not point more than 4 bytes beyond the msync
or isync.
If FPSCR[FEX] = 1 but both MSR[FE0,FE1] = 00, an enabled exception-type program
interrupt occurs before or at the next synchronizing event if [FE0,FE1] are altered by any
instruction so that the expression (MSR[FE0] | MSR[FE1]) & FPSCR[FEX] is 1. When this
occurs, ESR[PIE] is set and SRR0 is loaded with the EA of the instruction that would have
executed next, not with the EA of the instruction that modified MSR causing the interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR
PIL Set if an illegal instruction exception-type program interrupt; otherwise cleared.
PPR Set if a privileged instruction exception-type program interrupt; otherwise cleared.
PTR Set if a trap exception-type program interrupt; otherwise cleared.
PUO Set if an unimplemented operation exception-type program interrupt; otherwise
cleared.
FP Set if the instruction causing the interrupt is a floating-point instruction; otherwise
cleared.
PIE Set if a floating-point enabled exception-type program interrupt, and the address
saved in SRR0 is not the address of the instruction causing the exception (that is, the
instruction that caused FPSCR[FEX] to be set); otherwise cleared.
AP Set if the instruction causing the interrupt is an auxiliary processor instruction;
otherwise cleared.
All other defined ESR bits are cleared.
Instruction execution resumes at address IVPR[32–47] || IVOR6[48–59] || 0b0000.
5.7.8
Floating-point unavailable interrupt
A floating-point unavailable interrupt occurs when no higher priority exception exists, an
attempt is made to execute a floating-point instruction (including floating-point loads, stores,
and moves), and MSR[FP] = 0.
When a floating-point unavailable interrupt occurs, the processor suppresses execution of
the instruction causing the floating-point unavailable interrupt.
SRR0, SRR1, and MSR are updated as shown in Table 163.
Table 163. Floating-point unavailable interrupt register settings
Register
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Description
SRR0
Set to the effective address of the instruction that caused the interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
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Instruction execution resumes at address IVPR[32–47]||IVOR7[48–59]||0b0000.
5.7.9
System call interrupt
A system call interrupt occurs when no higher priority exception exists and a System Call
(sc) instruction is executed. SRR0, SRR1, and MSR are updated as shown in Table 164.
Table 164. System call interrupt register settings
Register
Description
SRR0
Set to the effective address of the instruction after the sc instruction.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
Instruction execution resumes at address IVPR[32–47] || IVOR8[48–59] || 0b0000.
5.7.10
Auxiliary processor unavailable interrupt
An auxiliary processor unavailable interrupt occurs when no higher priority exception exists,
an attempt is made to execute an auxiliary processor instruction (including auxiliary
processor loads, stores, and moves), the target auxiliary processor is present on the
implementation, and the auxiliary processor is configured as unavailable. Details of the
auxiliary processor and its configuration are implementation-dependent. See the reference
manual for the implementation.
When an auxiliary processor unavailable interrupt occurs, the processor suppresses
execution of the instruction causing the auxiliary processor unavailable interrupt.
Registers SRR0, SRR1, and MSR are updated as shown in Table 165.
Table 165. Auxiliary processor unavailable interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction that caused the interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
Instruction execution resumes at address IVPR[32–47]||IVOR9[48–59]||0b0000.
5.7.11
Decrementer Interrupt
A decrementer interrupt occurs when no higher priority exception exists, a decrementer
exception exists (TSR[DIS] = 1) & the interrupt is enabled (TCR[DIE] = 1 and MSR[EE] = 1).
MSR[EE] also enables external input and fixed-interval timer interrupts.
SRR0, SRR1, MSR, and TSR are updated as shown in Table 166.
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Table 166. Decrementer interrupt register settings
Register
Setting
SRR0
Set to the effective address of the next instruction to be executed.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
TSR
DIS is set.
Instruction execution resumes at address IVPR[32–47] || IVOR10[48–59] || 0b0000.
Note:
To avoid redundant decrementer interrupts, before reenabling MSR[EE], the interrupt
handling routine must clear TSR[DIS] by writing a word to TSR using mtspr with a 1 in any
bit position to be cleared and 0 in all others. The data written to the TSR is not direct data,
but a mask. Writing a 1 to this bit causes it to be cleared; writing a 0 has no effect.
5.7.12
Fixed-interval timer interrupt
A fixed-interval timer interrupt occurs when no higher priority exception exists, a fixedinterval timer exception exists (TSR[FIS] = 1), and the interrupt is enabled (TCR[FIE] = 1
and MSR[EE] = 1).
The fixed-interval timer period is determined by TCR[FP], which, when concatenated with
TCR[FPEXT], specifies one of 64 bit locations of the time base used to signal a fixedinterval timer exception on a transition from 0 to 1.
TCR[FPEXT],TCR[FP] = 000000 selects TBU[32]. TCR[FPEXT],TCR[FP] = 111111 selects
TBL[63].
Note:
MSR[EE] also enables external input and decrementer interrupts.
SRR0, SRR1, MSR, and TSR are updated as shown in Table 167.
Table 167. Fixed-interval timer interrupt register settings
Register
Setting
SRR0
Set to the effective address of the next instruction to be executed.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
TSR
FIS is set.
Instruction execution resumes at address IVPR[32–47] || IVOR11[48–59] || 0b0000.
Note:
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To avoid redundant fixed-interval timer interrupts, before reenabling MSR[EE], the interrupt
handling routine must clear TSR[FIS] by writing a word to TSR using mtspr with a 1 in any
bit position to be cleared and 0 in all others. The data written to the TSR is not direct data,
but a mask. Writing a 1 causes the bit to be cleared; writing a 0 has no effect.
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5.7.13
Interrupts and exceptions
Watchdog timer interrupt
A watchdog timer interrupt occurs when no higher priority exception exists, a watchdog
timer exception exists (TSR[WIS] = 1), and the interrupt is enabled (TCR[WIE] = 1 and
MSR[CE] = 1).
MSR[CE] also enables the critical input interrupt.
CSRR0, CSRR1, MSR, and TSR are updated as shown in Table 168.
Table 168. Watchdog timer interrupt register settings
Register
Setting
CSRR0
Set to the effective address of the next instruction to be executed.
CSRR1
Set to the MSR contents at the time of the interrupt.
MSR
ME is unchanged; all other MSR bits are cleared.
TSR
WIS is set.
Instruction execution resumes at address IVPR[32–47] || IVOR12[48–59] || 0b0000.
Note:
To avoid redundant watchdog timer interrupts, before reenabling MSR[CE], the interrupt
handling routine must clear TSR[WIS] by writing a word to TSR using mtspr with a 1 in any
bit position to be cleared and 0 in all others. The data written to the TSR is not direct data,
but a mask. Writing a 1 to this bit causes it to be cleared; writing a 0 has no effect.
5.7.14
Data tlb error interrupt
A data TLB error interrupt occurs when no higher priority exception exists and the exception
described in Table 169 is presented to the interrupt mechanism.
Table 169. Data tlb error interrupt exception conditions
Exception
Data TLB miss exception
Description
Virtual addresses associated with an instruction fetch do not match any
valid TLB entry.
If a store conditional instruction produces an effective address for which a normal store
would cause a data TLB error interrupt, but the processor does not have the reservation
from a load and reserve instruction, Book E defines it as implementation-dependent
whether a data TLB error interrupt occurs. The EIS defines that the interrupt is taken.
When a data TLB error interrupt occurs, the processor suppresses execution of the
instruction causing the data TLB error exception.
SRR0, SRR1, MSR, DEAR, and ESR are updated as shown in Table 170.
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Table 170. Data tlb error interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction causing the data TLB error interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
DEAR
Set to the EA of a byte that is both within the range of the bytes being accessed by the
memory access or cache management instruction and within the page whose access
caused the data TLB error exception.
ESR
STSet if the instruction causing the interrupt is a store, dcbi, or dcbz instruction;
otherwise cleared.
FPSet if the instruction causing the interrupt is a floating-point load or store; otherwise
cleared.
APSet if the instruction causing the interrupt is an auxiliary processor load or store;
otherwise cleared.
All other defined ESR bits are cleared.
MASn
See Table 193.
Table 192 shows MAS register settings for data and instruction TLB error interrupts.
Section 6.4.11.3: MAS register updates for exceptions, tlbsx, and tlbre, describes how these
values are set as defined by the EIS.
Instruction execution resumes at address IVPR[32–47] || IVOR13[48–59] || 0b0000.
5.7.15
Instruction tlb error interrupt
An instruction TLB error interrupt occurs when no higher priority exception exists and the
exception described in Table 171 is presented to the interrupt mechanism.
Table 171. Instruction TLB error interrupt exception conditions
Exception
Description
Instruction TLB miss exception
The virtual addresses associated with a fetch do not match any valid
TLB entry.
When an instruction TLB error interrupt occurs, the processor suppresses execution of the
instruction causing the instruction TLB miss exception.
SRR0, SRR1, and MSR are updated as shown in Table 172.
Table 172. Instruction TLB error interrupt register settings
Register
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Setting
SRR0
Set to the effective address of the instruction causing the instruction TLB error interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
MASn
See Table 192.
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Instruction execution resumes at address IVPR[32–47] || IVOR14[48–59] || 0b0000.
5.7.16
Debug interrupt
A debug interrupt occurs when no higher priority interrupt exists, a debug exception exists in
the DBSR, and debug interrupts are enabled (DBCR0[IDM] = 1 and MSR[DE] = 1). A debug
exception occurs when a debug event causes a corresponding DBSR bit to be set.
Table 173. Debug interrupt register settings
Register
Setting
CSRR0
For debug exceptions that occur while debug interrupts are enabled (DBCR0[IDM] = 1
and MSR[DE] = 1), CSRR0 is set as follows:
– For instruction address compare (IAC registers), data address compare (DAC1R,
DAC1W, DAC2R, and DAC2W), data value compare (DVC1 and DVC2), trap (TRAP),
or branch taken (BRT) debug exceptions, set to the address of the instruction causing
the debug interrupt.
– For instruction complete (ICMP) debug exceptions, set to the address of the instruction
that would have executed after the one that caused the debug interrupt.
– For unconditional debug event (UDE) debug exceptions, set to the address of the
instruction that would have executed next if the debug interrupt had not occurred.
– For interrupt taken (IRPT) debug exceptions, set to the interrupt vector value of the
interrupt that caused the interrupt taken debug event.
– For return from interrupt (RET) debug exceptions, set to the address of the instruction
that would have executed after the rfi, rfci, or rfmci that caused the debug interrupt.
– For debug exceptions that occur while debug interrupts are disabled (DBCR0[IDM] = 0
or MSR[DE] = 0), a debug interrupt occurs at the next synchronizing event if
DBCR0[IDM] and MSR[DE] are modified such that they are both set and if the debug
exception status is still set in the DBSR. When this occurs, CSRR0 holds the address of
the instruction that would have executed next, not the address of the instruction that
modified DBCR0 or MSR and thus caused the interrupt.
CSRR1
Set to the MSR contents at the time of the interrupt.
MSR
ME is unchanged. All other MSR bits are cleared.
DBSR
Set to indicate type of debug event. 
(See Section 3.13.2.)
CSRR0, CSRR1, MSR, and DBSR are updated as shown in Table 173.
Instruction execution resumes at address IVPR[32–47] || IVOR15[48–59] || 0b0000.
5.7.17
EIS-defined interrupts
The interrupts in this section are defined by the EIS.
5.7.17.1
SPE/embedded floating-point APU unavailable interrupt
An SPE APU unavailable interrupt is taken if MSR[SPE] is cleared and an SPE, embedded
scalar double-precision or embedded vector single-precision floating-point instruction is
executed. It is not used by the embedded scalar single-precision floating-point APU.
When an SPE unavailable interrupt occurs, the processor suppresses execution of the
instruction causing the interrupt. Table 174 describes register settings. If the
SPE/embedded floating-point unavailable interrupt occurs, the processor suppresses
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execution of the instruction causing the exception. The SRR0, SRR1, MSR, and ESR
registers are modified as shown in Table 174.
Table 174. SPE/embedded floating-point APU unavailable interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction causing the interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other bits are cleared.
ESR
SPE (bit 24) is set. All other ESR bits are cleared.
Instruction execution resumes at address IVPR–47] || IVOR32[48–59] || 0b0000.
5.7.17.2
Embedded floating-point data interrupt
An embedded floating-point data interrupt is generated in the following cases:

SPEFSCR[FINVE] = 1 and either SPEFSCR[FINVH,FINV] = 1

SPEFSCR[FDBZE] = 1and either SPEFSCR[FDBZH,FDBZ] = 1

SPEFSCR[FUNFE] = 1 and either SPEFSCR[FUNFH,FUNF] = 1

SPEFSCR[FOVFE] = 1 and either SPEFSCR[FOVFH,FOVF] = 1
Note that although SPEFSCR status bits can be updated by using mtspr, interrupts occur
only if they are set as the result of an arithmetic operation.
When an embedded floating-point data interrupt occurs, the processor suppresses
execution of the instruction causing the interrupt. Table 175 shows register settings.
Table 175. Embedded floating-point data interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction causing the interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other bits are cleared.
ESR
SPE (bit 24) is set. All other ESR bits are cleared.
SPEFSCR
One or more of the FINVH, FINV, FDBZH, FDBZ, FUNFH, FUNF, FOVFH, or FOVF bits
are set to indicate the interrupt type.
Instruction execution resumes at address IVPR[32–47] || IVOR33[48–59] || 0b0000.
5.7.17.3
Embedded floating-point round interrupt
The embedded floating-point round interrupt is taken on any of the following conditions:

SPEFSCR[FINXE] = 1 and any of the SPEFSCR[FGH,FXH,FG,FX] bits = 1

SPEFSCR[FRMC] = 0b10 (+)

SPEFSCR[FRMC] = 0b11 (–)
Note that although these SPEFSCR status bits can be updated by using an
mtspr[SPEFSCR], interrupts occur only if they are set as the result of an arithmetic
operation.
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When an embedded floating-point round interrupt occurs, the unrounded (truncated) result
is placed in the target register. Table 176 describes register settings.
Table 176. Embedded floating-point round interrupt register settings
Register
Setting
SRR0
Set to the effective address of the instruction following the instruction causing the
interrupt.
SRR1
Set to the MSR contents at the time of the interrupt.
MSR
CE, ME, and DE are unchanged. All other MSR bits are cleared.
ESR
SPE (bit 24) is set. All other ESR bits are cleared.
SPEFSCR FGH, FXH, FG, FX, and FRMC are set appropriately to indicate the interrupt type.
Instruction execution resumes at address IVPR[32–47] || IVOR34[48–59] || 0b0000.
5.8
Performance monitor interrupt
The performance monitor provides a performance monitor interrupt that is triggered by an
enabled condition or event. An enabled condition or event is as follows:
A PMCx register overflow condition occurs with the following settings:

PMLCax[CE] = 1; that is, for the given counter the overflow condition is enabled.

PMCx[32] = 1; that is, the given counter indicates an overflow.
For a performance monitor interrupt to be signaled on an enabled condition or event,
PMGC0[PMIE] must be set.
The performance monitor can also freeze the performance monitor counters triggered by an
enabled condition or event. For the performance monitor counters to freeze on an enabled
condition or event, PMGC0[FCECE] must be set.
Although the interrupt condition could occur with MSR[EE] = 0, the interrupt cannot be taken
until MSR[EE] = 1. If a counter overflows while PMGC0[FCECE] = 0, PMLCa[CE] = 1, and
MSR[EE] = 0, it is possible for the counter to wrap around to all zeros again without the
performance monitor interrupt being taken.
The priority of the performance monitor interrupt is below that of the fixed-interval interrupt
and above that of the decrementer interrupt.
5.9
Partially executed instructions
In general, the PowerPC architecture permits load and store instructions to be partially
executed, interrupted, and then restarted from the beginning upon return from the interrupt.
To guarantee that a particular load or store instruction completes without being interrupted
and restarted, software must mark the memory as guarded and use an elementary (nonstring or non-multiple) load or store aligned on an operand-sized boundary.
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To guarantee that load and store instructions can, in general, be restarted and completed
correctly without software intervention, the following rules apply when an execution is
partially executed and then interrupted:

For an elementary load, no part of a target register rD or frD has been altered.

For update forms of load or store, the update register, rA, will not have been altered.
The following effects are permissible when certain instructions are partially executed and
then restarted:

For any store, bytes at the target location may have been altered (if write access to that
page in which bytes were altered is permitted by the access control mechanism). In
addition, for store conditional instructions, CR0 has been set to an undefined value,
and it is undefined whether the reservation has been cleared or not.

For any load, bytes at the addressed location may have been accessed (if read access
to that page in which bytes were accessed is permitted by the access control
mechanism).

For load multiple or load string, some registers in the range to be loaded may have
been altered. Including the addressing registers rA and possibly rB in the range to be
loaded is a programming error, and thus the rules for partial execution do not protect
these registers against overwriting.
In no case is access control violated.
As previously stated, elementary, aligned, guarded loads and stores are the only access
instructions guaranteed not to be interrupted after being partially executed. The following list
identifies the specific instruction types for which interruption after partial execution may
occur, as well as the specific interrupt types that could cause the interruption:
1.
2.
Any load or store (except elementary, aligned, or guarded):
–
Any asynchronous interrupt
–
Machine check
–
Program (imprecise mode floating-point enabled)
–
Program (imprecise mode auxiliary processor enabled)
–
Decrementer
–
Fixed-interval timer
–
Watchdog timer
–
Debug (unconditional debug event)
Misaligned elementary load or store, or any multiple or string:
All of the above listed under item (1), plus the following:
–
Alignment
–
Data storage (if the access crosses a protection boundary)
–
Debug (data address compare, data value compare)
The mtcrf and mfcr instructions can also be partially executed due to the occurrence of any
of the interrupts listed under item (1) at the time mtcrf or mfcr was executing.
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
All instructions before mtcrf or mfcr have completed execution. Some memory
accesses generated by these preceding instructions may not have completed.

No subsequent instruction has begun execution.

The mtcrf or mfcr instruction, whose address was saved in SRR0/CSRR0 at the time
of the interrupt, may appear not to have begun or may have partially executed.
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5.10
Interrupts and exceptions
Interrupt ordering and masking
Multiple exceptions that can each generate an interrupt can exist simultaneously. However,
the PowerPC architecture does not provide for reporting multiple simultaneous interrupts of
the same class (critical or noncritical). Therefore, the PowerPC architecture defines that
interrupts must be ordered with one another and provides a way to mask certain persistent
interrupt types.
When an interrupt type is masked (disabled) and an event causes an exception that would
normally generate an interrupt of that type, the exception persists as a status bit in a register
(which register depends upon the exception type) but no interrupt is generated. Later, if the
interrupt type is enabled (unmasked) and the exception status has not been cleared by
software, the interrupt due to the original exception event is finally generated. (A typical
implementation has such a mechanism for certain debug events. A signal that triggers an
asynchronous interrupt, such as external input, must be asserted until they are taken. There
is no mechanism for saving the external interrupt if the signal is negated before the interrupt
is taken. All interrupts are level-sensitive except for machine check, which is edgetriggered.)
All asynchronous interrupt types and some synchronous interrupt types can be masked. An
example of a maskable synchronous interrupt type is the floating-point enabled exceptiontype program interrupt. The execution of a floating-point instruction that causes
FPSCR[FEX] to be set is considered an exception event, regardless of the setting of
MSR[FE0,FE1]. If MSR[FE0,FE1] are both 0, the floating-point enabled exception-type
program interrupt is masked, but the exception persists in FPSCR[FEX]. Later, if
MSR[FE0,FE1] are enabled, the interrupt is generated.
The PowerPC architecture allows implementations to avoid situations in which an interrupt
would cause state information (saved in save/restore registers) from a previous interrupt to
be overwritten and lost. As a first step, upon any noncritical class interrupt, hardware
automatically disables further asynchronous, noncritical class interrupts (external input) by
clearing MSR[EE]. Likewise, upon any critical class interrupt, hardware automatically
disables further asynchronous interrupts, both critical and noncritical, by clearing MSR[CE]
and MSR[EE]. Critical input, watchdog timer, and debug interrupts are disabled by clearing
MSR[CE,DE]. Note that machine check interrupts, while considered neither asynchronous
nor synchronous, are not maskable by MSR[CE,DE,EE] and could be presented in a
situation that could cause loss of state information.
This first step of clearing MSR[EE] (and MSR[CE,DE] for critical class interrupts) prevents
subsequent asynchronous interrupts from overwriting save/restore registers before software
can save their contents. On any interrupt, hardware also automatically clears
MSR[WE,PR,FP,FE0,FE1,IS,DS], which helps avoid subsequent interrupts of certain other
types. However, guaranteeing that these interrupt types do not occur also requires system
software to avoid executing instructions that could cause (or enable) a subsequent interrupt,
if SRR1 contents have not been saved.
5.10.1
Guidelines for system software
Table 177 lists actions system software must avoid before saving save/restore register
contents.
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Table 177. Operations to avoid
Operation
Reason
Reenabling MSR[EE] (or MSR[CE,DE] in critical
class interrupt handlers)
Prevents any asynchronous interrupts, snd (in
the case of MSR[DE]) any debug interrupts,
including synchronous and asynchronous
types
Branching (or sequential execution) to addresses
not mapped by the TLB, mapped without UX = 1 or
SX = 1 permission, or causing large address or
instruction address overflow exceptions.
Prevents instruction storage, instruction TLB
error, and instruction address overflow
interrupts
Load, store, or cache management instructions to
addresses not mapped by the TLB or not having
required access permissions.
Prevents data storage and data TLB error
interrupts
Execution of system call (sc) or trap (tw, twi, td, tdi)
Prevents system call and trap exception-type
program interrupts
Execution of any floating-point instruction
Prevents floating-point unavailable interrupts.
Note that this interrupt would occur upon
execution of any floating-point instruction, due
to the automatic clearing of MSR[FP].
However, even if software were to reenable
MSR[FP], floating-point instructions must still
be avoided to prevent program interrupts due
to various possible program interrupt
exceptions (floating-point enabled,
unimplemented operation).
Reenabling of MSR[PR]
Prevents privileged instruction exception-type
program interrupts. Alternatively, software
could reenable MSR[PR] but avoid executing
any privileged instructions.
Execution of any auxiliary processor instruction
Prevents auxiliary processor unavailable,
auxiliary processor enabled type, and
unimplemented operation type program
interrupts
Execution of any illegal instructions
Prevents illegal instruction exception-type
program interrupts
Execution of any instruction that could cause an
alignment interrupt
Prevents alignment interrupts, including string
or multiple instructions and misaligned
elementary load or store instructions.
Section 5.7.6: Alignment interrupt, lists
instructions that cause alignment interrupts.
If the machine check APU is not implemented, machine check interrupts are a special case.
Machine checks are critical interrupts, but normal critical interrupts (critical input, watchdog
timer, and debug) do not automatically disable machine checks. Machine checks are
disabled by clearing MSR[ME], and only a machine check interrupt itself automatically
clears this bit. Thus there is always the risk that a machine check interrupt could occur
within a normal critical interrupt handler before it saves the save/restore registers’ contents.
In such a case, the interrupt may not be recoverable.
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It is unnecessary for hardware or software to avoid critical-class interrupts from within
noncritical-class interrupt handlers (hence hardware does not automatically clear
MSR[CE,ME,DE] on a noncritical interrupt), since the two interrupt classes use different
save/restore registers. However, because a critical class interrupt can occur within a
noncritical handler before the noncritical handler saves SRR0/SRR1, hardware and
software must cooperate to avoid both critical and noncritical class interrupts from within
critical class interrupt handlers. Therefore, within the critical class interrupt handler, both
pairs of save/restore registers may contain data necessary to system software.
5.10.2
Interrupt order
Enabled interrupt types for which simultaneous exceptions can exist are prioritized as
follows:
1.
Synchronous (non-debug) interrupts:
–
Data storage
–
Instruction storage
–
Alignment
–
Program
–
Floating-point unit unavailable
–
Auxiliary processor unavailable
–
System call
–
Data TLB error
–
Instruction TLB error
Only one of the above synchronous interrupt types may have an existing exception
generating it at a given time. This is guaranteed by the exception priority mechanism
(see Section 5.11: Exception priorities) and the sequential execution model.
2.
Machine check
3.
Debug
4.
Critical input
5.
Watchdog timer
6.
External input
7.
Fixed-interval timer
8.
Decrementer
Although, as indicated above, noncritical, synchronous exception types listed under item (1)
are generated with higher priority than critical interrupt types in items (2)–(5), noncritical
interrupts are immediately followed by the highest priority existing critical interrupt type,
without executing any instructions at the noncritical interrupt handler. This is because
noncritical interrupt types do not automatically disable MSR mask bits for critical interrupt
types (CE and ME). In all other cases, a particular interrupt type listed above automatically
disables subsequent interrupts of the same type, as well as all lower priority interrupt types.
5.11
Exception priorities
Book E requires all synchronous (precise and imprecise) exceptions to be reported in
program order, as required by the sequential execution model. The one exception to this
rule is the case of multiple synchronous imprecise exceptions. Upon a synchronizing event,
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all previously executed instructions are required to report any synchronous imprecise
interrupt-generating exceptions, and the interrupt is then generated with all of those
exception types reported cumulatively in the ESR and in any status registers associated
with the particular exception type (such as the FPSCR).
For any single instruction attempting to cause multiple exceptions for which the
corresponding synchronous interrupt types are enabled, this section defines the priority
order by which the instruction is permitted to cause a single enabled exception, thus
generating a particular synchronous interrupt. Note that it is this exception priority
mechanism, along with the requirement that synchronous interrupts be generated in
program order, that guarantees that at any given time there exists for consideration only one
of the synchronous interrupt types listed in item 1 of Section 5.10.2: Interrupt order. The
exception priority mechanism also prevents certain debug exceptions from existing in
combination with certain other synchronous interrupt-generating exceptions.
The EIS defines priorities for all exceptions including those defined in optional APUs.
Interrupt types are defined as either synchronous (the interrupt is as a direct result of an
instruction in execution) or asynchronous, (the interrupt results from an event external to the
execution of a particular instruction or an instruction removes a gating condition to a
pending exception). Except for machine check interrupts, which can be either synchronous
or asynchronous, interrupts are either synchronous or asynchronous exclusively.
Because asynchronous interrupts may temporally be sampled either before or after an
instruction is completed, an implementation can order asynchronous interrupts among only
asynchronous interrupts and order synchronous interrupts among only synchronous
interrupt. The distinction is important because synchronous interrupts that require postcompletion actions (such as system call or debug instruction complete exceptions) cannot
be separated from the completion of the instruction. Therefore, asynchronous interrupts
cannot be sampled during the completion and post-completion synchronous exceptions for
a given instruction.
The relative priorities for asynchronous exceptions is given in Table 178 and for
synchronous exceptions in and Table 179. In many cases, certain exceptions cannot occur
at the same time (for example, program-trap and program-Illegal cannot occur on the same
instruction). In general those exceptions are grouped at the same relative priority.
Table 178. EIS asynchronous exception priorities
Relative
priority
0
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Interrupt
level(1)
Interrupt
nature
Machine check Asynch/synch
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Comments
(2)
pre for
synch
Asynchronous
exceptions may
come from processor
or from an external
source.
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Interrupts and exceptions
Table 178. EIS asynchronous exception priorities (continued)
Relative
priority
Exception
Debug—UDE
Debug—IDE
Interrupt
level(1)
Critical/debug
Critical/debug
Interrupt
nature
Pre/post
completion
Asynch
Asynch
N/A
Generally used for an
externally generated
high priority attention
signal.
N/A
Usually taken after
MSR[DE] goes from
0 to 1 via rfdi/rfci or
mtmsr.
N/A
Debug interrupt
taken after original
interrupt changed
NIA and MSR.
Debug interrupt
taken after original
critical interrupt has
changed NIA and
MSR.
1
Debug—interrupt
taken
Critical/debug
Comments
(2)
Asynch
Debug—critical
interrupt taken
Debug
Asynch
N/A
2
Critical input
Critical
Asynch
N/A
3
Watchdog
Critical
Asynch
N/A
4
External input
Base
Asynch
N/A
18
Fixed interval timer
Base
Asynch
N/A
19
Decrementer
Base
Asynch
N/A
20
Performance
Monitor
Base
Asynch
N/A
1. The interrupt level defines the set of save/restore registers used when the interrupt is taken—base
(SRR0/SRR1), critical (CSRR0/CSRR1), debug (DSRR0/DSRR1), and machine check
(MCSRR0/MCSRR1).
2. Pre- or post-completion refers to whether the exception occurs before an instruction completes (pre) and
the corresponding interrupt points to the instruction causing the exception, or if the instruction completes
(post) and the corresponding interrupt points to the next instruction to be executed.
Table 179. EIS synchronous exception priorities
Relative
Interrupt
level(1)
nature
Critical/debug
Synch
pre
ITLB
Base
Synch
pre
ISI
Base
Synch
pre
Exception
priority
5
Pre/post
Interrupt
Debug–instruction
address compare
completion
Comments
(2)
6
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Table 179. EIS synchronous exception priorities (continued)
Relative
Exception
8
9
10
Interrupt
Pre/post
completion
Comments
level(1)
nature
FP unavailable
Base
Synch
pre
AltiVec unavailable
Base
Synch
pre
Defined by the AltiVec
APU.
SPE unavailable
Base
Synch
pre
Defined by the SPE
APU.
Embedded floatingpoint unavailable
Base
Synch
pre
Defined by the
embedded floating point
APUs.
Critical/debug
Synch
pre
Program—illegal
instruction
Base
Synch
pre
Program—
unimplemented
operation
Base
Synch
pre
Program—privileged
instruction
Base
Synch
pre
Program—Trap
Base
Synch
pre
Program—FP enabled
Base
Synch
pre
An FP enabled interrupt
may be imprecise.
(Alignment)
Base
Synch
pre
Alignment may be
handled at either
priority.
DTLB
Base
Synch
pre
Data storage
Base
Synch
pre
Alignment
Base
Synch
pre
Alignment may be
handled at either
priority.
System call
Base
Synch
post
Points SRR0 to
instruction after sc (post
completion).
Embedded FP data
Base
Synch
pre
Defined by the SPE
APU.
priority
7
Interrupt
Debug—trap
(2)
11
12
Embedded FP round
Base
Synch
post
Points SRR0 to the
instruction after the one
causing the exception
(post completion).
Defined by SPE APU.
AltiVec Assist
Base
Synch
pre
Defined by the AltiVec
APU.
13
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Table 179. EIS synchronous exception priorities (continued)
Relative
Exception
Interrupt
Interrupt
Pre/post
completion
Comments
level(1)
nature
Debug—return from
interrupt
Critical/debug
Synch
pre
Debug—Return from
critical interrupt
Debug
Synch
pre
Debug—branch taken
Critical/debug
Synch
pre
15
Debug—DAC
Critical/debug
Synch
pre or post
Preferred method is precompletion.
16
Debug—DVC
Critical/debug
Synch
pre or post
Preferred method is precompletion.
17
Debug—instruction
complete
Critical/debug
Synch
post
priority
14
(2)
Defined by the
enhanced debug APU.
Points [CD]SRR0 to
next instruction (post
completion).
1. The interrupt level defines the set of save/restore registers used when the interrupt is taken—base
(SRR0/SRR1), critical (CSRR0/CSRR1), debug (DSRR0/DSRR1), and machine check
(MCSRR0/MCSRR1).
2. Pre- or post-completion refers to whether the exception occurs before an instruction completes (pre) and
the corresponding interrupt points to the instruction causing the exception, or if the instruction completes
(post) and the corresponding interrupt points to the next instruction to be executed.
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Storage architecture
This chapter describes the cache and MMU portions of the Book E implementation
standards (EIS). Note that not all features that are defined by the EIS storage architecture
are supported on all ST EIS processors; consult the user documentation. This chapter is
organized into three section:
6.1

Section 6.2: Memory and cache coherency”

Section 6.3: Cache model”

Section 6.4: Storage model”
Overview
The Book E architecture memory and cache definitions support a wide variety of embedded
implementations. To provide such flexibility, Book E defines many features in a very general
way, leaving specific details up to the implementation. To ensure consistency among its
Book E cores and devices, ST has defined more specific implementation standards.
However, these standards still leave many details up to individual implementations. To
provide context for those features, this chapter describes aspects of the memory hierarchy
and the memory management model defined by Book E; it also describes the ST EIS.
Note:
This chapter describes some features (in particular, registers) in a very general way that
does not include some details that are important to the programmer. There are also small
differences in how some features are defined here and how they are implemented. For
implementation-specific details, see the user documentation.
Throughout this chapter, references to load instructions include cache management and
other instructions that are stated in the instruction descriptions to be treated as a load, and
references to store instructions include the cache management and other instructions that
are treated as a store.
The following APUs, which are part of the EIS storage architecture, are defined in Section 9:
Storage-related APUs:

Cache line locking APU

Cache way partitioning APU

Direct cache flush APU
These APUs may be implemented independently of each other. They are defined together
in a single specification because it is likely that an implementation will include more than
one of these APUs.
6.2
Memory and cache coherency
The primary objective of a coherent memory system is to provide the same image of
memory to all devices using the system. Coherency allows synchronization and cooperative
use of shared resources. Otherwise, multiple copies of data corresponding to a memory
location, some containing outdated values, could exist in a system, resulting in errors when
the outdated values are used. Each memory-sharing device must follow rules for managing
the state of its cache. This section describes the coherency mechanisms of the Book E
architecture and the cache coherency protocols that the ST Book E devices support.
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Unless specifically noted, the discussion of coherency in this section applies to the core
complex data cache only. The instruction cache is not snooped for general coherency with
other caches; however, it is snooped when the Instruction Cache Block Invalidate (icbi)
instruction is executed by this processor or any processor in the system.
6.2.1
Memory/Cache access attributes
Some memory characteristics can be set on a page basis by using the WIMGE bits in the
translation lookaside buffer (TLB) entries. These bits allow both uniprocessor and
multiprocessor system designs to exploit numerous system-level performance
optimizations. The WIMGE attributes control the following:

Write-through (W bit)

Caching-inhibited (I bit)

Memory-coherency-required (M bit)

Guarded (G bit)

Endianness (E bit)
In addition to the WIMGE bits, the Book E MMU model defines the following attributes on a
page basis:

User-definable (U0, U1, U2, U3)
The EIS defines the following optional attributes, which are manipulated by software through
MMU assist register 2 (MAS2):

Alternate coherency mode (ACM). The ACM attribute, programmed through
MAS2[ACM], allows an implementation to employ multiple coherency methods and to
participate in multiple coherency protocols. If the M attribute (memory coherence
required) is not set for a page (M = 0), the page has no coherency associated with it
and the ACM attribute is ignored. If the M attribute is set for a page (M = 1), the ACM
attribute determines the coherency domain (or protocol) used. ACM values are
implementation dependent.

Variable length encoding (VLE). The VLE attribute, MAS2[VLE], identifies pages that
contain instructions from the VLE instruction set. If VLE = 0, instructions fetched from
the page are decoded and executed as PowerPC (and associated EIS APUs)
instructions. If VLE = 1, instructions fetched from the page are decoded and executed
as Power Embedded instructions.
Consult the user documentation to determine whether the EIS-defined attributes are
implemented.
The WIMGE attributes are programmed by the operating system for each page. The W and
I attributes control how the processor performing an access uses its own cache. The M
attribute ensures that coherency is maintained for all copies of the addressed memory
location. The G attribute prevents speculative loading from the addressed memory location.
(An operation is said to be performed speculatively if, at the time that it is performed, it is not
known to be required by the sequential execution model.) The E attribute defines the order
in which the bytes that comprise a multiple-byte data object are stored in memory (big- or
little-endian).
The WIMGE attributes occupy 5 bits in the TLB entries for page address translation. The
operating system writes the WIMGE bits for each page into the TLB entries in system
memory as it maps translations. For more information, see Section 6.4.10.2: TLB entries.
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All combinations of these attributes are supported except those that simultaneously specify
a region as write-through and caching-inhibited. Write-through and caching-inhibited
attributes are mutually exclusive because the write-through attribute permits the data to be
in the data cache while the caching-inhibited attribute does not.
Memory that is write-through or caching-inhibited is not intended for general-purpose
programming. For example, lwarx and stwcx. instructions may cause the system DSI
exception handler to be invoked if they specify a location in memory having either of these
attributes. Some implementations take a data storage interrupt if the location is writethrough but does not take the interrupt if the location is cache-inhibited. Note that, except
that the guarded bit does not prevent instruction prefetches, the definitions of the WIMG bits
are unchanged
6.2.1.1
Write-through attribute
A page marked W = 0 is considered to be write-back. If some store instructions executed by
a given processor access locations in a block as write-through and other store instructions
executed by the same processor access locations in that block as write-back, software must
ensure that the block cannot be accessed by another processor or mechanism in the
system.
A store to a write-through (W = 1) memory location is performed in main memory and may
cause additional memory locations to be accessed. If a copy of the block containing the
specified location is retained in the data cache, the store is also performed in the data
cache. A store to write-through memory cannot cause a block to be put in a modified state in
the data cache.
Also, if a store instruction that accesses a block in a location marked as write-through is
executed when the block is already considered to be modified in the data cache, the block
may continue to be considered to be modified in the data cache even if the store causes all
modified locations in the block to be written to main memory. In some processors, accesses
caused by separate store instructions that specify locations in write-through memory may be
combined into one access. This is called store-gathering. Such combining does not occur if
the store instructions are separated by an msync or an mbar.
6.2.1.2
Caching-inhibited attribute
A load instruction that specifies a location in caching-inhibited (I = 1) memory is performed
to main memory and may cause additional locations in main memory to be accessed unless
the specified location is also guarded. An instruction fetch from caching-inhibited memory
may cause additional words in main memory to be accessed. No copy of the accessed
locations is placed into the caches.
In some processors, nonoverlapping accesses caused by separate load instructions that
specify locations in caching-inhibited memory may be combined into one access, as may
nonoverlapping accesses caused by separate store instructions to caching-inhibited
memory (that is, store-gathering). Such combining does not occur if the load or store
instructions are separated by an msync instruction, or by an mbar instruction if the memory
is also guarded.
6.2.1.3
Memory-coherence-required attribute
Memory coherence refers to the ordering of stores to a single location. Atomic stores to a
given location are coherent if they are serialized in some order, and no processor or
mechanism is able to observe any subset of those stores as occurring in a conflicting order.
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This serialization order is an abstract sequence of values; the physical location need not
assume each of the values written to it. For example, a processor may update a location
several times before the value is written to physical memory.
The result of a store operation is not available to every processor or mechanism at the same
instant, and it may be that a processor or mechanism observes only some of the values that
are written to a location. However, when a location is accessed atomically and coherently by
all processors and mechanisms, the sequence of values loaded from the location by any
processor or mechanism during any interval of time forms a sub-sequence of the sequence
of values that the location logically held during that interval. That is, a processor or
mechanism can never load a newer value first and then, later, load an older value.
Memory coherence is managed in blocks called coherence blocks. Although a block’s size
is implementation-dependent, it is usually larger than a word and is often the size of a cache
block.
When memory coherence is not required (M = 0), the hardware need not enforce data
coherence for memory accesses initiated by the processor. When memory coherence is
required (M = 1), the hardware must enforce data coherence for memory accesses initiated
by the processor. Hardware support for the memory-coherence-required attribute is optional
for implementations that do not support multiprocessing.
6.2.1.4
Guarded attribute
When the guarded bit is set, the page is designated as guarded. This setting can be used to
protect certain memory areas from read accesses made by the processor that are not
dictated directly by the program. If areas of physical memory are not fully populated (in other
words, there are holes in the physical memory map within this area), this setting can protect
the system from undesired accesses caused by speculative (referred to as ‘out of order’ in
the architecture specification, and described in Section 6.2.1.5: Definition of apeculative and
out-of-order memory accesses) load operations that could lead to the generation of the
machine check exception. Also, the guarded bit can be used to prevent speculative load
operations from occurring to certain peripheral devices that produce undesired results when
accessed in this way.
6.2.1.5
Definition of apeculative and out-of-order memory accesses
In the architecture definition, the term ‘out of order’ replaced the term ‘speculative’ with
respect to memory accesses to avoid a conflict between the word’s meaning in the context
of execution of instructions past unresolved branches. The architecture’s use of out of order
in this context could in turn be confused with the notion of loads and stores being reordered
in a weakly ordered memory system.
In the context of memory accesses, this document uses the terms ‘speculative’ and ‘out of
order’ as follows:

Speculative memory access—An access to memory that occurs before it is known to
be required by the sequential execution model.

Out-of-order memory access—A memory access performed ahead of one that may
have preceded it in the sequential model, such as is allowed by a weakly ordered
memory model.
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Performing operations speculatively
An operation is said to be nonspeculative if it is guaranteed to be required by the sequential
execution model. Any other operation is said to be performed speculatively, which the
architecture specification refers to as out of order.
Operations are performed speculatively by hardware on the expectation that the results will
be needed by an instruction that will be required by the sequential execution model.
Whether the results are needed depends on whether control flow is diverted away from the
instruction by an event such as an exception, branch, trap, system call, return from interrupt
instruction, or anything else that changes the context in which the instruction is executed.
Typically, the hardware performs operations speculatively when it has resources that would
otherwise be idle, so the operation incurs little or no cost. If subsequent events such as
branches or exceptions indicate that the operation would not have been performed, the
processor abandons any results of the operation except as described below.
Most operations can be performed speculatively, as long as the machine appears to follow
the sequential execution model. Certain speculative operations are restricted, as follows:

Stores—A store instruction cannot execute speculatively in a manner such that the
alteration of the target location can be observed by other processors or mechanisms.

Accessing guarded memory—The restrictions for this case are given in
Section 6.2.1.7.1: Speculative accesses to guarded memory.
No error of any kind other than a machine check exception may be reported due to an
operation that is performed speculatively, until such time as it is known that the operation is
required by the sequential execution model. The only other permitted side effect (other than
machine check) of performing an operation speculatively is that nonguarded memory
locations that could be fetched into a cache by nonspeculative execution may be fetched
speculatively into that cache.
6.2.1.7
Guarded memory
Memory is said to be well behaved if the corresponding physical memory exists and is not
defective, and if the effects of a single access to it are indistinguishable from the effects of
multiple identical accesses to it. Data and instructions can be fetched speculatively from
well-behaved memory without causing undesired side effects.
Memory is said to be guarded if the G bit is set for the page. In general, memory that is not
well-behaved should be guarded. Because such memory may represent an I/O device or
include nonexistent locations, a speculative access to such memory may cause an I/O
device to perform incorrect operations or may cause a machine check.
Note that if separate store instructions access memory that is both caching-inhibited and
guarded, the accesses are performed in the order specified by the program. If an aligned
load or store that is not a string or multiple access to caching-inhibited, guarded memory
has accessed main memory and an external, decrementer, or imprecise-mode floating-point
enabled exception is pending, the load or store is completed before the exception is taken.
6.2.1.7.1
Speculative accesses to guarded memory
Accesses for load instructions from guarded memory may be performed speculatively if a
copy of the target location is in a cache; in this case, the location may be accessed from the
cache or from main memory.
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Note that software should ensure that only well-behaved memory is loaded into a cache,
either by marking as caching-inhibited (and guarded) all memory that may not be wellbehaved or by marking such memory caching-allowed (and guarded) and referring only to
cache blocks that are well-behaved.
Instrubction accesses: guarded memory and no-execute memory
The G bit is ignored for instruction fetches, and instructions are speculatively fetched from
guarded pages. To prevent speculative fetches from pages that do not contain instructions
and are not well-behaved, the page should be designated as no-execute (with the UX/SX
page permission bits cleared). If the effective address of the current instruction is mapped to
no-execute memory, an ISI exception is generated.
6.2.1.7.2
Endianness
Objects may be loaded from or stored to memory in byte, half-word, word, or double-word
units. For a particular data length, the load and store operations are symmetrical; a store
followed by a load of the same data object yields an unchanged value. Book E makes no
guarantees about the order in which the bytes that comprise multiple-byte data objects are
stored into memory. The endianness (E) page attribute distinguishes between memory that
is big or little endian, as described in the following subsections.
Except for instruction fetches, it is always permitted to access the same location using two
effective addresses with different E bit settings. Instruction pages must be flushed from any
caches before the E bit can be changed for those addresses. See Section 4.2.3.4: Byte
ordering, for more information about endianness.
6.2.1.7.3
Big-endian pages
If a stored multiple-byte object is probed by reading its component bytes one at a time using
load-byte instructions, the store order may be perceived. If such probing shows that the
lowest memory address contains the highest-order byte of the multiple-byte scalar, the nexthigher sequential address the next-least-significant byte, and so on, the multiple-byte object
is stored in big-endian form. Big-endian memory is defined on a page basis by the
memory/cache attribute, E = 0.
Note that strings are not multiple-byte scalars but are interpreted as a series of single-byte
scalars. Bytes in a string are loaded from memory using a load string word instruction,
starting at the lowest-numbered address, and placed into the target register or registers
starting at the left-most byte of the least-significant word. Bytes in a string are stored using a
store string word instruction from the source register, starting at the left-most byte of the
least-significant word, and placed into memory, starting at the lowest-numbered address.
6.2.1.7.4
Little-endian pages
Alternatively, if the probing shows that the lowest memory address contains the lowest-order
byte of the multiple-byte scalar, the next-higher sequential address the next-most-significant
byte, and so on, the multiple-byte object is stored in little-endian form. Little-endian memory
is defined on a page basis by the memory/cache attribute, E = 1, and for Book E devices is
defined as true little-endian memory.
6.2.1.7.5
Structure mapping examples
The following C programming example defines the data structure S used in this section to
demonstrate how the bytes that comprise each element (a, b, c, d, e, and f) are mapped into
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memory. The structure contains scalars (shown in hexadecimal in the comments) and a
sequence of characters, shown in single quotation marks.
struct {
int
double
char *
char
short
int
a;
b;
c;
d[7];
e;
f;
/* 0x1112_1314
word*/
/* 0x2122_2324_2526_2728double word*/
/* 0x3132_3334
word*/
/* 'L','M','N','O','P','Q','R' array of bytes*/
/* 0x5152
half word*/
/* 0x6162_6364
word*/
} S;
big-endian mapping of the structure ia shown below.
6.2.1.7.6
Big-endian mapping of structure
Contents
11
12
13
14
(x)
(x)
(x)
(x)
Address
00
01
02
03
04
05
06
07
Contents
21
22
23
24
25
26
27
28
Address
08
09
0A
0B
0C
0D
0E
0F
Contents
31
32
33
34
‘L’
‘M’
‘N’
‘O’
Address
10
11
12
13
14
15
16
17
Contents
‘P’
‘Q’
‘R’
(x)
51
52
(x)
(x)
Address
18
19
1A
1B
1C
1D
1E
1F
Contents
61
62
63
64
(x)
(x)
(x)
(x)
Address
20
21
22
23
24
25
26
27
Note that the MSB of each scalar is at the lowest address. The mapping uses padding
(indicated by (x)) to align the scalars—4 bytes between elements a and b, 1 byte between d
and e, and 2 bytes between e and f. Note that the padding is determined by the compiler,
not the architecture.
The structure using little-endian mapping, showing double words laid out with addresses
increasing from right to left.
Little-endian mapping of structure S—alternate view
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Storage architecture
Contents
(x)
(x)
(x)
(x)
11
12
13
14
Address
07
06
05
04
03
02
01
00
Contents
21
22
23
24
25
26
27
28
Address
0F
0E
0D
0C
0B
0A
09
08
Contents
‘O’
‘N’
‘M’
‘L’
31
32
33
34
Address
17
16
15
14
13
12
11
10
Contents
(x)
(x)
51
52
(x)
‘R’
‘Q’
‘P’
Address
1F
1E
1D
1C
1B
1A
19
18
Contents
(x)
(x)
(x)
(x)
61
62
63
64
Address
27
26
25
24
23
22
21
20
Mismatched memory cache attributes
Accesses to the same memory location using two effective addresses for which the writethrough required attribute (W bit) differs meet the memory coherence requirements
described in Section 6.2.1.1: Write-through attribute, if the accesses are performed by a
single processor. If the accesses are performed by two or more processors, coherence is
enforced by the hardware only if the write-through attribute is the same for all the accesses.
Loads, stores, dcbz instructions, and instruction fetches to the same memory location using
two effective addresses for which the caching-inhibited attribute (I bit) differs must meet the
requirement that a copy of the target location of an access to caching-inhibited memory not
be in the cache. Violation of this requirement is considered a programming error; software
must ensure that the location has not previously been brought into the cache or, if it has,
that it has been flushed from the cache. If the programming error occurs, the result of the
access is boundedly undefined. It is not considered a programming error if the target
location of any other cache management instruction to caching-inhibited memory is in the
cache.
Accesses to the same memory location using two effective addresses for which the memory
coherence attribute (M bit) differs may require explicit software synchronization before
accessing the location with M = 1 if the location has previously been accessed with M = 0.
Any such requirement is system-dependent. For example, in some systems that use bus
snooping, no software synchronization may be required. In some directory-based systems,
software may be required to execute dcbf instructions on each processor to flush all cache
entries accessed with M = 0 before accessing those locations with M = 1.
Accesses to the same memory location using two effective addresses for which the guarded
attribute (G bit) differs are always permitted.
Except for instruction fetches, accesses to the same memory location using two effective
addresses for which the endian storage attribute (E bit) differs are always permitted as
described in Section 6.2.1.7.2: Endianness. Instruction memory locations must be flushed
before the endian attribute can be changed for those addresses.
The requirements on mismatched user-defined memory attributes (U0–U3) is
implementation-dependent.
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Coherency paradoxes and WIMGE
Care must be taken with respect to the use of the WIMGE bits if coherent memory support is
desired. Careless programming of these bits may create situations that present coherency
paradoxes to the processor. These paradoxes can occur within a single processor or across
several processors. It is important to note that, in the presence of a paradox, the operating
system software is responsible for correctness.
In particular, a coherency paradox can occur when the state of these bits is changed without
appropriate precautions (such as flushing the pages that correspond to the changed bits
from the caches of all processors in the system) or when the address translations of aliased
real addresses specify different values for certain WIMGE bit values. For more information,
see Section 6.2.1.8: Mismatched memory cache attributes.
Support for M = 1 memory is optional. Cache attribute settings where both W = 1 and I = 1
are not supported. For all supported combinations of the W, I, and M bits, both G and E may
be 0 or 1.
The default setting of the WIMGE bits is 0b01000.
6.2.1.10
Self-modifying code
When a processor modifies any memory location that can contain an instruction, software
must ensure that the instruction cache is made consistent with data memory and that the
modifications are made visible to the instruction fetching mechanism. This must be done
even if the cache is disabled or if the page is marked caching-inhibited.
The following instruction sequence can be used to accomplish this when the instructions
being modified are in memory that is memory-coherence required and one processor both
modifies the instructions and executes them. (Additional synchronization is needed when
one processor modifies instructions that another will execute.)
The following sequence synchronizes the instruction stream (using either dcbst or dcbf):
dcbst (or dcbf)|update memory
msync
|wait for update 
icbi
|remove (invalidate) copy from instruction cache
msync
|ensure that ICBI invalidation at icache has completed
isync
|remove copy in own instruction buffer
6.2.2
Shared memory
The architecture supports sharing memory between programs, between different instances
of the same program, and between processors and other mechanisms. It also supports
access to a memory location by one or more programs using different effective addresses.
In these cases, memory is shared in blocks that are an integral number of pages. When one
physical memory location has different effective addresses, the addresses are said to be
aliases. Each application can be granted separate access privileges to aliased pages.
Section 6.2.2.2: Lock acquisition and import barriers, gives examples of how msync and
mbar are used to control memory access ordering when memory is shared among
programs.
6.2.2.1
Memory access ordering
The memory model in Book E for memory access ordering is weakly consistent. This
provides an opportunity for improved performance over a model with stronger consistency
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rules but places the responsibility on the program to ensure that ordering or synchronization
instructions are properly placed for correct execution of the program.
The order in which a processor accesses memory, the order in which those accesses are
performed with respect to other processors or mechanisms, and the order in which they are
performed in main memory may all be different. Table 180 describes how the architecture
defines requirements for ordering of loads and stores.
Table 180. Load and store ordering
Type of Access
Architecture definition
The architecture guarantees that loads that are both caching-inhibited (I = 1)
and guarded (G = 1) are not reordered with respect to one another.
Load ordering with
respect to other
loads
If a load instruction depends on the value returned by a preceding load
(because the value is used to compute the effective address specified by the
second load), the corresponding memory accesses are performed in program
order with respect to any processor or mechanism to the extent required by the
associated memory coherence required attributes (that is, the memory
coherence required attribute, if any, associated with each access). This applies
even if the dependency does not affect program logic (for example, the value
returned by the first load is ANDed with zero and then added to the effective
address specified by the second load).
If two store instructions specify memory locations that are both caching
Store ordering with
inhibited and guarded, the corresponding memory accesses are performed in
respect to other
program order with respect to any processor or mechanism. Otherwise, stores
stores
are weakly ordered with respect to one another.
Store ordering with The architecture specifies that an msync or mbar must be used to ensure
respect to loads
sequential ordering of loads with respect to stores.
When a processor (P1) executes msync or mbar, a memory barrier is created that
separates applicable memory accesses into two groups, G1 and G2. G1 includes all
applicable memory accesses associated with instructions preceding the barrier-creating
instruction, and G2 includes all applicable memory accesses associated with instructions
following the barrier-creating instruction.
Table 181 shows an example using a two-processor system.
Table 181. Memory barrier when coherency is required (M = 1)
Processor 1 (P1)
Memory access groups G1
and G2
Processor 2 (P2)
Instruction 1
Instruction 2
Instruction 3
G1: Memory accesses
generated by P1 
before the memory barrier
When memory coherence is
required, G1 accesses that
affect P2 are also performed
before the memory barrier.
Instruction 4
Instruction 5 (msync or mbar)—Memory barrier
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and associated accesses.
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Table 181. Memory barrier when coherency is required (M = 1) (continued)
Processor 1 (P1)
Memory access groups G1
and G2
Processor 2 (P2)
Instruction 6
Instruction 7
Instruction 8
Instruction 9
G2: Memory accesses
generated by P1 after the
memory barrier
When memory coherence is
required, G2 accesses that
affect P2 are also performed
after the memory barrier.
Instruction 10
The memory barrier ensures that all memory accesses in G1 are performed with respect to
any processor or mechanism, to the extent required by the associated memory coherence
required attributes (that is, the memory-coherence required attribute, if any, associated with
each access), before any memory accesses in G2 are performed with respect to that
processor or mechanism.
The ordering enforced by a memory barrier is said to be cumulative if it also orders memory
accesses that are performed by processors and mechanisms other than P1, as follows:

G1 includes all applicable memory accesses by any such processor or mechanism that
have been performed with respect to P1 before the memory barrier is created.

G2 includes all applicable memory accesses by any such processor or mechanism that
are performed after a load instruction executed by that processor or mechanism has
returned the value stored by a store that is in G2.
Table 182 shows an example of a cumulative memory barrier in a two-processor system.
Table 182. Cumulative memory barrier
Processor 1 (P1)
Memory access groups G1 and G2
P1 Instruction 1
P1 Instruction 2
P1 Instruction 3
Processor 2 (P2)
P2 Instruction L
G1: Memory accesses generated by P1 and P2 that affect P1.
Includes accesses generated by executing P2 instructions L–O
(assuming that the access generated by instruction O occurs before
P1’s msync is executed).
P1 Instruction 4
P2 Instruction M
P2 Instruction N
P2 Instruction O
P2 Instruction P
P1 Instruction 5 (msync)—Cumulative memory barrier applies to all accesses except those
associated with fetching instructions following msync.
P2 Instruction Q
P2 Instruction R
P1 Instruction 6
P1 Instruction 7
P1 Instruction 8
P1 Instruction 9
P1 Instruction 10
P2 Instruction S
G2: Memory accesses generated by P1 and P2. Includes accesses
generated by P2 instructions P–X (assuming that the access
generated by instruction P occurs after P1’s msync is executed)
performed after a load instruction executed by P2 has returned the
value stored by a store that is in G2.
The msync memory barrier does not affect accesses associated with
instruction fetching that occur after the msync.
P1 Instruction 11
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P2 Instruction U
P2 Instruction V
P2 Instruction W
P2 Instruction X
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A memory barrier created by msync is cumulative and applies to all accesses except those
associated with fetching instructions following the msync. See the definition of mbar in
Section 4.3.1.15: Memory synchronization instructions, for a description of the
corresponding properties of the memory barrier created by that instruction.
6.2.2.1.1
Programming considerations
Because stores cannot be performed out of program order, as described in Book E, if a
store instruction depends on the value returned by a preceding load (because the value the
load returns is needed to compute either the effective address specified by the store or the
value to be stored), the corresponding accesses are guaranteed to be performed in program
order. The same applies whether or not the store instruction executes is dependent upon a
conditional branch that in turn depends on the value returned by a preceding load. For
example, if a conditional branch depends on a preceding load and that branch chooses
between a path that includes a store instruction if the condition is met, that dependent store
is not performed unless and until the condition determined by the load is met.
Because instructions following an isync cannot execute until all instructions preceding
isync have completed, if an isync follows a conditional branch instruction that depends on
the value returned by a preceding load instruction, that load is performed before any loads
caused by instructions following the isync. This is true even if the effects of the dependency
are independent of the value loaded (for example, the value is compared to itself and the
branch tests CRn[EQ]), and even if the branch target is the next sequential instruction.
Except for the cases described above and earlier in this section, data and control
dependencies do not order memory accesses. Examples include the following:

If a load specifies the same memory location as a preceding store and the location is
not caching inhibited, the load may be satisfied from a store queue (a buffer into which
the processor places stored values before presenting them to the memory subsystem)
and not be visible to other processors and mechanisms. As a result, if a subsequent
store depends on the value returned by the load, the two stores need not be performed
in program order with respect to other processors and mechanisms.

Because a store conditional instruction may complete before its store is performed, a
conditional branch instruction that depends on the CR0 value set by a store conditional
instruction does not order that store with respect to memory accesses caused by
instructions that follow the branch.
For example, in the following sequence, the stw is the bc instruction’s target:
stwcx.
bc
stw
To complete, the stwcx. must update the architected CR0 value, even though its store
may not have been performed. The architecture does not require that the store
generated by the stwcx. must be performed before the store generated by the stw.

Because processors may predict branch target addresses and branch condition
resolution, control dependencies (branches, for example) do not order memory
accesses except as described above. For example, when a subroutine returns to its
caller, the return address may be predicted, with the result that loads caused by
instructions at or after the return address may be performed before the load that
obtains the return address is performed.
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Some processors implement nonarchitected duplicates of architected resources such as
GPRs, CR fields, and the LR, so resource dependencies (for example, specification of the
same target register for two load instructions) do not force ordering of memory accesses.
Examples of correct uses of dependencies, msync, and mbar to order memory accesses
can be found in hi.
Because the memory model is weakly consistent, the sequential execution model as applied
to instructions that cause memory accesses guarantees only that those accesses appear to
be performed in program order with respect to the processor executing the instructions. For
example, an instruction may complete, and subsequent instructions may be executed,
before memory accesses caused by the first instruction have been performed. However, for
a sequence of atomic accesses to the same memory location for which memory coherence
is required, the definition of coherence guarantees that the accesses are performed in
program order with respect to any processor or mechanism that accesses the location
coherently, and similarly if the location is one for which caching is inhibited.
Because caching-inhibited memory accesses are performed in main memory, memory
barriers and dependencies on load instructions order such accesses with respect to any
processor or mechanism even if the memory is not marked as requiring memory coherence.
6.2.2.1.2
Programming examples
Example 1 shows cumulative ordering of memory accesses preceding a memory barrier,
Example 2 shows cumulative ordering of memory accesses following a memory barrier. In
both examples, assume that locations X, Y, and Z initially contain the value 0. In both,
cumulative ordering dictates that the value loaded from location X by processor C is 1.
Example 1:

Processor A stores the value 1 to location X.

Processor B loads from location X obtaining the value 1, executes an msync, then
stores the value 2 to location Y.

Processor C loads from location Y obtaining the value 2, executes an msync, then
loads from location X.
Example 2:
6.2.2.2

Processor A stores the value 1 to location X, executes an msync, then stores the value
2 to location Y.

Processor B loops, loading from location Y until the value 2 is obtained, then stores the
value 3 to location Z.

Processor C loads from location Z obtaining the value 3, executes an msync, then
loads from location X.
Lock acquisition and import barriers
An import barrier is an instruction or instruction sequence that prevents memory accesses
caused by instructions following the barrier from being performed before memory accesses
that acquire a lock have been performed. An import barrier can be used to ensure that a
shared data structure protected by a lock is not accessed until the lock has been acquired.
An msync can always be used as an import barrier, but the approaches shown below
generally yield better performance because they order only the relevant memory accesses.
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Acquire lock and import shared memory
If lwarx and stwcx. are used to obtain the lock, an import barrier can be constructed by
placing an isync immediately following the loop containing the lwarx and stwcx.. The
following example uses the compare and swap primitive (see Section C.1.1:
Synchronization primitives) to acquire the lock.
This example assumes that the address of the lock is in GPR 3, the value indicating that the
lock is free is in GPR 4, the value to which the lock should be set is in GPR 5, the old value
of the lock is returned in GPR 6, and the address of the shared data structure is in GPR 9.
loop:lwarxr6,0,r3
# load lock and reserve
cmpw r4,r6
# skip ahead if
bne- wait
# lock not free
stwcx. r5,0,r3
# try to set lock
bne- loop
# loop if lost reservation
isync
# import barrier
lwz r7,data1(r9)
# load shared data
.
.
wait: ...
#wait for lock to free
The second bne- does not complete until CR0 has been set by the stwcx.. The stwcx. does
not set CR0 until it has completed (successfully or unsuccessfully). The lock is acquired
when the stwcx. completes successfully. Together, the second bne- and the subsequent
isync create an import barrier that prevents the load from data1 from being performed until
the branch is resolved to be not taken.
6.2.2.2.2
Obtain pointer and import shared memory
If lwarx and stwcx. are used to obtain a pointer into a shared data structure, an import
barrier is not needed if all the accesses to the shared data structure depend on the value
obtained for the pointer. The following example uses the fetch and add primitive (see
Section C.1.1: Synchronization primitives) to obtain and increment the pointer.
In this example, it is assumed that the address of the pointer is in GPR 3, the value to be
added to the pointer is in GPR 4, and the old value of the pointer is returned in GPR 5.
loop:
lwarx
add
stwcx.
r5,0,r3
r0,r4,r5
r0,0,r3
# load pointer and reserve
# increment the pointer
# try to store new
value
bnelwz
loop
r7,data1(r5)
# loop if lost reservation
# load shared data
The load from data1 cannot be performed until the lwarx loads the pointer value into GPR 5.
The load from data1 may be performed out of order before the stwcx.. But if the stwcx.
fails, the branch is taken and the value returned by the load from data1 is discarded. If the
stwcx. succeeds, the value returned by the load from data1 is valid even if the load is
performed out of order, because the load uses the pointer value returned by the instance of
the lwarx that created the reservation used by the successful stwcx..
An isync could be placed between the bne- and the subsequent lwz, but no isync is
needed if all accesses to the shared data structure depend on the value returned by the
lwarx.
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Atomic memory references
The Book E architecture defines the Load Word and Reserve Indexed (lwarx) and the store
word conditional indexed (stwcx.) instructions to provide an atomic update function for a
single, aligned word of memory. These instructions can be used to develop a rich set of
multiprocessor synchronization primitives. Note that atomic memory references constructed
using lwarx/stwcx. instructions depend on the presence of a coherent memory system for
correct operation. These instructions should not be expected to provide atomic access to
noncoherent memory.
The lwarx instruction performs a load word from memory operation and creates a
reservation for the same reservation granule that contains the accessed word. Reservation
granularity is implementation-dependent.
The lwarx instruction makes a nonspecific reservation with respect to the executing
processor and a specific reservation with respect to other masters. This means that any
subsequent stwcx. executed by the same processor, regardless of address, cancels the
reservation. Also, any bus write or invalidate operation from another processor to an
address that matches the reservation address cancels the reservation.
6.3
Cache model
A cache model in which there is one cache for instructions and another cache for data is
called a ‘Harvard-style’ cache. This is the model assumed by Book E, for example in the
descriptions of the cache management instructions in Section 4: Instruction model. Book E
allows the following additional cache models are defined by the EIS:

Unified cache, in which a cache is shared by both instructions and data

Multi-level caches, which must support the programming model implied by a Harvardstyle cache.
A processor is not required to maintain copies of storage locations in the instruction cache
that are consistent with modifications to those storage locations (that is, modifications by
store instructions).
In general, a location in the data cache is considered to be modified in that cache if the
location has been modified (for example, by a store instruction) and the modified data has
not been written to main storage. The only exception to this rule is described in
Section 6.2.1.1: Write-through attribute.
Cache management instructions are provided so that programs can manage the caches
when needed. For example, program management of the caches is needed when a
program generates or modifies code that will be executed (i.e., when the program modifies
data in storage and then attempts to execute the modified data as instructions). Cache
management instructions are also useful in optimizing the use of memory bandwidth in such
applications as graphics and numerically intensive computing. The functions performed by
these instructions depend on the storage attributes associated with the specified storage
location.
Cache management instructions allow the program to do the following.
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Give a hint that a block of storage should be copied to the instruction cache, so that the
copy of the block is more likely to be in the cache when subsequent accesses to the
block occur, thereby reducing delays (icbt)

Invalidate the copy of storage in an instruction cache block (icbi)
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
Discard prefetched instructions (isync)

Invalidate the copy of storage in a data cache block (dcbi)

Give a hint that a block of storage should be copied to the data cache, so that the copy
of the block is more likely to be in the cache when subsequent accesses to the block
occur, thereby reducing delays (dcbt, dcbtst)

Allocate a data cache block and set the contents of that block to zeros, but nooperation if no access is allowed to the data cache block and do not cause any
exceptions (dcba)

Set the contents of a data cache block to zeros (dcbz)

Copy the contents of a modified data cache block to main storage (dcbst)

Copy the contents of a modified data cache block to main storage and make the copy
of the block in the data cache invalid (dcbf).
Cache programming model
This section summarizes the register and instructions defined to support the cache model.
Full descriptions of these resources are provided in Section 3: Register model, and
Section 4: Instruction model.
6.3.1.1
Cache model registers
The EIS cache model implements the following registers and register fields:

Machine state register (MSR). Defines the processor state (that is, enabling and
disabling of interrupts and debugging exceptions, enabling and disabling of address
translation for instruction and data memory accesses, enabling and disabling some
APUs, and specifying whether the processor is in supervisor or user mode). EIS
storage defines the user cache locking enable bit (MSR[UCLE]) as part of the cache
line locking APU.
Book E and the EIS define the MSR fields described in Table 183. The MSR is
described in detail in Section 3.6.1: Machine state register (MSR).
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Table 183. Storage related MSR fields
Bits
37
58
59
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Name
Description
UCLE
(EIS-defined) User-mode cache lock enable. Used to restrict usermode cache-line locking by the operating system.
0 Any cache lock instruction executed in user-mode takes a
cache-locking exception and data storage interrupt and sets
either ESR[DLK] or ESR[ILK]. This allows the operating system
to manage and track the locking/unlocking of cache lines by
user-mode tasks.
1 Cache-locking instructions can be executed in user-mode and
they do not take a DSI for cache-locking (they may still take a
DSI for access violations though).
IS
(Book E–defined) Instruction address space
0 The processor directs all instruction fetches to address space 0
(TS = 0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1
(TS = 1 in the relevant TLB entry).
DS
(Book E–defined) Data address space
0 The processor directs data memory accesses to address space
0 (TS = 0 in the relevant TLB entry).
1 The processor directs data memory accesses to address space
1 (TS = 1 in the relevant TLB entry).

Exception syndrome register (ESR). The ESR provides a syndrome to differentiate
between different kinds of exceptions that can generate the same interrupt type. When
such an interrupt is generated, bits corresponding to the exception that generated the
interrupt are set and all other ESR bits are cleared. Other interrupt types do not affect
ESR contents. The ESR does not need to be cleared by software.

Book E and the EIS defines the storage-related ESR fields described in Table 184. The
ESR is described in detail in Section 3.9.1.8: Exception syndrome register (ESR).
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Table 184. Exception syndrome register (ESR) definition
Bits
Name
39
FP
(Book E–defined) Floating-point operations
Alignment, data
storage, data TLB,
program
40
ST
(Book E–defined) Store operation
Alignment, data 
storage, data TLB error
DLK
Defined by cache line locking APU. Instruction cache
locking attempt. Set when a DSI occurs because a
dcbtls, dcbtstls, or dcblc was executed in user mode
(MSR[PR] = 1) while MSR[UCLE] = 0.
0 Default
1 DSI occurred on an attempt to lock line in data cache
when MSR[UCLE] = 0.
Data storage
43
ILK
Defined by cache line locking APU. Instruction cache
locking attempt. Set when a DSI occurs because an
icbtls or icblc was executed in user mode (MSR[PR] = 1)
while MSR[UCLE] = 0.
Data storage
0 Default
1 DSI occurred on an attempt to lock line in instruction
cache when MSR[UCLE] = 0.
44
APU
(Book E–defined) Auxiliary processor operation.
46
BO
42
56
58
SPE
Syndrome
Interrupt types
Alignment, data
storage, data TLB,
program
Byte-ordering exception. Defined by Book E and the VLE Data storage,
extension.
instruction storage
Defined by SPE, embedded floating-point APU.
SPE/embedded floating-point exception bit
0 Default
1 Any exception caused by an SPE/embedded floatingpoint instruction occurred.
Data storage,
Data TLB error,
Alignment,
SPE unavailable,
Embedded FP
unavailable,
Embedded FP data,
Embedded FP round
Data storage,
Data TLB error,
Defined by VLE extension. VLEMI indicates that an
interrupt was caused by a VLE instruction. VLEMI is set
Instruction storage,
on an exception associated with execution or attempted
Program,
execution of a VLE instruction.
System Call,
VLEMI 0 The instruction page associated with the instruction
Alignment,
causing the exception does not have the VLE attribute
SPE unavailable,
set or the VLE extension is not implemented.
Embedded FP
1 The instruction page associated with the instruction
causing the exception has the VLE attribute set and the unavailable,
VLE extension is implemented.
Embedded FP data,
Embedded FP round
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Table 184. Exception syndrome register (ESR) definition (continued)
Bits
62
63


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Name
Syndrome
Interrupt types
MIF
Defined by the VLE extension. MIF indicates that an
interrupt was caused by a misaligned instruction fetch
(NIA62 != 0) and the VLE attribute is cleared for the page
or the second half of a 32-bit VLE instruction caused an
instruction TLB error.
Instruction TLB error,
0 Default.
Instruction Storage
1 NIA62 != 0 and the instruction page associated with NIA
does not have the VLE attribute set or the second half
of a 32-bit VLE instruction caused an instruction TLB
error.
XTE
External transaction error. An external transaction
reported an error but the error was handled precisely by
the core. SRR0 holds the address of the instruction that
initiated the transaction.
0 Default. No external transaction error was precisely
detected.
1 An external transaction reported an error that was
precisely detected.
Instruction storage,
Data storage
L1 cache control and status registers (L1CSR0–L1CSR1).
–
L1CSR0 provides general control and status for the processor’s primary data
cache. If a processor implements a unified L1 cache, L1CSR0 applies to the
unified cache and L1CSR1 is not implemented. See Section 3.11.1: L1 cache
control and status register 0 (L1CSR0).
–
L1CSR1 provides general control and status for the processor’s primary
instruction cache. If a processor implements a unified L1 cache, L1CSR0 applies
to the unified cache and L1CSR1 is not implemented. See Section 3.11.2: L1
cache control and status register 1 (L1CSR1).
L1 cache configuration registers (L1CFG0)
–
L1CFG0 provides configuration information for the processor’s primary data
cache. If a processor implements a unified cache, L1CFG0 applies to the unified
cache and L1CFG1 is not implemented. See Section 3.11.3: L1 cache
configuration register 0 (L1CFG0).
–
L1CFG1 provides configuration information for the processor’s primary instruction
cache. If a processor implements a unified cache, L1CFG0 applies to the unified
cache and L1CFG1 is not implemented. L1CFG1 allows software to identify the
organization and capabilities of the primary instruction cache. Section 3.11.4: L1
cache configuration register 1 (L1CFG1).
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Storage architecture
Cache model instructions
The Book E PowerPC architecture defines instructions for controlling both the instruction
and data caches (when they exist).

Data Cache Block Touch (dcbt)

Data Cache Block Touch for Store (dcbtst)

Data Cache Block Zero (dcbz)

Data Cache Block Store (dcbst)

Data Cache Block Flush (dcbf)

Data Cache Block Allocate (dcba)

Data Cache Block Invalidate (dcbi)

Instruction Cache Block Invalidate (icbi)

Instruction Synchronize (isync)

Instruction Cache Block Touch (icbt)
These instructions are described in Section 4.3.1.18: User-level cache instructions, and
Section 4.3.2.3: Supervisor-level cache instruction. Note that the behavior of many of these
instructions is determined by the value of the cache target operand (CT). See
Section 6.3.1.3: CT instruction field. Section 6.4.8.4: Permission control and cache
management instructions, describes conditions in which cache control instructions can
generate protection violations.
The cache block locking APU, defined by the EIS, adds the following instructions:

Data Cache Block Lock Clear (dcblc)

Data Cache Block Touch and Lock Set (dcbtls)

Data Cache Block Touch for Store and Lock Set (dcbtstls)

Instruction Cache Block Lock Clear (icblc)

Instruction Cache Block Touch and Lock Set (icbtls)
These instructions are described in Section 9.1: Cache line locking APU.
6.3.1.3
CT instruction field
Instructions having a CT (cache target) field for specifying a cache hierarchy use the value 0
to specify the primary cache. ST devices interpret this operand as follows:
6.3.2

CT = 0 indicates the L1 cache.

CT = 1 indicates the I/O cache. (Note that some versions of the e500 documentation
refer to the I/O cache as a frontside L2 cache.)

CT = 2 indicates a backside L2 cache.
Primary (L1) cache model
This section describes the L1 cache model defined by the EIS.
6.3.2.1
Types
Primary caches may separate instruction and data caches into two separate structures
(commonly known as Harvard architecture), or they may provide a unified cache combining
instructions and data. Caches are physically tagged.
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Storage attributes and coherency
Primary data caches must support the storage attributes defined by Book E with the
following advisory:
Note:
The primary data cache may be implemented not to snoop (that is, not coherent with
transactions outside the processor). System software is then responsible to maintain
coherency. Thus the setting of the M attribute is meaningless. The preferred implementation
provides snooping for primary data caches.
Primary instruction caches must support the storage attributes defined by Book E with the
following advisory:

The guarded attribute should be ignored for instruction fetch accesses. To prevent
speculative fetch accesses to guarded memory, software should mark those pages as
no-execute.

The cache may be implemented not to snoop (that is, not coherent with transactions
outside the processor). System software is then responsible to maintain coherency.
The preferred implementation does not provide snooping for primary instruction
caches.
As with other memory-related instructions, the effects of cache management instructions on
memory are weakly-ordered. If the programmer must ensure that cache or other instructions
have been performed with respect to all other processors and system mechanisms, an
msync must be placed after those instructions.
6.4
Storage model
This section describes the storage model as it is defined by Book E and by the EIS.
6.4.1
Storage programming model
This section summarizes the register and instructions defined to support the cache model.
Full descriptions of these resources are provided in Chapter 3: Register model, and
Chapter 4: Instruction model.
6.4.1.1
Storage model registers
This section provides an overview of the registers used for programming the MMU. Full
descriptions are provided in Section 3.12: MMU registers. These registers consist of the
following:
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
Process ID registers (PID0–PID2) are used by system software to identify TLB entries
that are used by the processor to accomplish address translation for loads, stores, and
instruction fetches. Book E defines one PID register (PID synonymous with PID0). The
EIS defines 14 additional PID registers, PID1 through PID14. A implementation may
choose to provide any number of PIDs up to a maximum of 15. The number of PIDs
implemented is indicated by the value of MMUCFG[NPIDS] and the number of bits
implemented in each PID register is indicated by the value of MMUCFG[PIDSIZE]. PID
values are used to construct virtual addresses for accessing memory (see
Section 6.4.6: Address translation).

MMU assist registers (MAS0–MAS7) are used to transfer data to and from the TLB
arrays. Software uses mfspr and mtspr to read and write MAS registers. Executing
tlbre causes the TLB entry specified by MAS0[TLBSEL,ESEL] and MAS2[EPN] to be
copied to the MAS registers. Conversely, execution of a tlbwe instruction causes the
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TLB entry specified by MAS0[TLBSEL,ESEL] and MAS2[EPN] to be written with the
MAS register contents. Hardware can also updated MAS registers on the occurrence of
an instruction or data TLB error interrupt or as the result of a tlbsx.
All MAS registers are supervisor level, and all except MAS5 and MAS7 must be
implemented. MAS7 is not required if the processor supports 32 bits or less of physical
address. Implementing MAS5 is implementation dependent.
Processors are required to implement only the necessary bits of any multiple-bit MAS
register field such that only the resources supplied by the processor are represented.
Any non-implemented bits in a field should have no effect when writing and should
always read as zero. For example, a processor that implements only two TLB arrays
would likely implement only the lower-order MAS0[TLBSEL] bits.
–
MAS0, contains fields for identifying and selecting a TLB entry.
–
MAS1, contains fields for selecting a TLB entry during translation.
–
MAS2, contains fields for specifying the effective page address and the storage
attributes for a TLB entry.
–
MAS3, contains fields for specifying the real page address and the permission
attributes for a TLB entry.
–
MAS4, contains fields for specifying default information to be pre-loaded on
certain MMU-related exceptions.
–
The optional MAS5 register, contains fields for specifying PID values to be used
when searching TLB entries with the tlbsx instruction.
–
MAS6, contains fields for specifying PID and AS values used when the tlbsx
instruction is used to search TLB entries.
MAS7, contains the high-order address bits of the RPN for implementations that
support more than 32 bits of physical address. Implementations that support 32 bits or
fewer do not implement MAS7.
6.4.1.2

MMU configuration register (MMUCFG), provides configuration information about the
MMU.

TLB configuration registers (TLBnCFG). One TLBnCFG register, is implemented to
provide information about each TLB implemented. TLB0CFG corresponds to TLB0,
TLB1CFG corresponds to TLB1, etc.

MMU control and status register (MMUCSR0), is used for general control of the MMU
including flash invalidation of the TLB arrays and page sizes for programmable fixed
size arrays. For TLB arrays with programmable fixed sizes, the TLBn_PS fields allow
software to specify the page size.
Storage model instructions
The address translation mechanism is defined in terms of TLBs and page table entries
(PTEs) Book E processors use to locate the logical-to-physical address mapping for a
particular access. Table 103 describes the operation of the TLB instructions, which are
summarized as follows:

TLB Invalidate Virtual Address Indexed (tlbivax)

TLB Read Entry (tlbre)

TLB Search Indexed (tlbsx)

TLB Synchronize (tlbsync)

TLB Write Entry (tlbwe)
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The storage architecture
This section describes the storage model as it is defined by Book E and by the ST EIS.
6.4.2.1
Book E storage architecture
The memory management approach defined by the Book E EIS is suited for desktop
applications and has the simplicity and flexibility necessary for embedded applications.
Book E supports demand-paged virtual memory as well as a variety of other management
schemes that depend on precise control of effective-to-real address translation and flexible
memory protection. Address translation misses and protection faults cause precise
exceptions. Sufficient information is available to correct the fault and restart the faulting
instruction.
Each program on a 32-bit implementation can access 232 bytes of effective address (EA)
space, subject to limitations imposed by the operating system. In a typical Book E system,
each program’s EA space is a subset of a larger virtual address (VA) space managed by the
operating system.
Each effective (logical) address is translated to a real (physical) address before being used
to access physical memory or an I/O device. Hardware does this by using the address
translation mechanism described in Section 6.4.6. The operating system manages the
physically addressed resources of the system by setting up the tables used by the address
translation mechanism.
The Book E architecture divides the effective address space into pages. The page
represents the granularity of effective address translation, permission control, and
memory/cache attributes. Up to 12 page sizes (1, 4, 16, 64, or 256 Kbytes; 1, 4, 16, 64, or
256 Mbytes; or 1 Gbyte) may be simultaneously supported. For an effective-to-real address
translation to exist, a valid entry for the page containing the effective address must be in a
translation lookaside buffer (TLB). Addresses for which no TLB entry exists cause TLB miss
exceptions (instruction or data TLB error interrupts).
The instruction addresses generated by a program and the addresses used by load, store,
and cache management instructions are effective addresses. However, in general, the
physical memory space may not be large enough to map all the virtual pages used by the
currently active applications. With support provided by hardware, the operating system can
attempt to use the available real pages to map enough virtual pages for an application. If a
sufficient set is maintained, paging activity is minimized, therefore maximizing performance.
The operating system can restrict access to virtual pages by selectively granting
permissions for user-state read, write, and execute, and supervisor-state read, write, and
execute on a per-page basis. These permissions can be set up for a particular system (for
example, program code might be execute-only, data structures may be mapped as
read/write/no-execute) and can also be changed by the operating system based on
application requests and operating system policies.
6.4.2.2
EIS storage architecture
The standard for Book E MMUs establishes a common way of implementing Book E
processors to provide a programming model that is consistent across all products in the
family. Having a standard reduces the software efforts required in porting to a new
processor because the common programming model minimizes implementation differences.
Thus, the standard defines configuration information for features such as TLBs, caches, and
other entities that have standard forms, but differing attributes (like cache sizes and
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associativity) such that a single software implementation can be created that works
efficiently for all implementations of a class.
The Book E MMU standard defines functions and structures that are visible to the execution
model of the processor. These consist of the following definitions:

The TLB, from a programming point of view, consists of zero or more TLB arrays, each
of which may have differing characteristics.

The logical-to-physical address translation mechanism

Methods and effects of changing and manipulating TLB arrays

Configuration information available to the operating system that describes the structure
and form of the TLB arrays and translation mechanism
To assist or accelerate translation, implementations may contain other TLB structures not
visible to the programming model. These structures and the methods for using them are not
explicitly defined in the architecture or the ST standard, but they may be considered at the
operating system level because they may affect an implementation’s performance.
6.4.3
Virtual address (VA)
Book E defines a virtual address space composed of the effective address of an access, the
1-bit current address space (AS) of the access and the 32-bit process ID (PID) of an access,
as shown in Figure 79. The following subsections describe the selection of AS and PID for
an effective address, both used to construct the virtual address for an access.
Figure 79. Virtual Address Space in Book E
Effective Address
(Logical)
(Program)
64-bit
6.4.4
Virtual Address
1+
AS
32 +
PID
64 bits
EA
Real Address
(Physical)
64-bit
Address spaces
Instruction accesses are generated by sequential instruction fetches or due to a change in
program flow (branches and interrupts). Data accesses are generated by load, store, and
cache management instructions.
The Book E architecture defines two address spaces for instruction accesses and two
address spaces for data accesses. The current address space for instruction or data
accesses is determined by the value of MSR[IS] and MSR[DS], respectively, as shown in
Figure 80.
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Figure 80. Current address space
MSR[IS]
0
1
0
+
63
Instruction effective address <ea>
0
MSR[DS]
0
1
+
63
Data effective address <ea>
0
If the type of translation performed is an instruction fetch, the value of the AS bit is taken
from the contents of MSR[IS]. If the type of translation performed is a load, store, or other
data translation including target addresses of software-initiated instruction fetch hints and
locks (icbt, icbtls, icbtlc) the value of the AS bit is taken from the contents of MSR[DS].
The address space indicator (MSR[IS] or MSR[DS], as appropriate) is used in addition to
the effective address generated by the processor for translation into a physical address by
the TLB mechanism.
Because MSR[IS] and MSR[DS] are cleared when an interrupt occurs, an address space
value of zero can be used to denote interrupt-related address spaces, or possibly all system
software address spaces; an address space value of one can be used to denote non–
interrupt-related address spaces, or possibly all user address spaces.
Software Note: Although system software is free to use address space bits as it sees fit, on
an interrupt, the MSR[IS] and MSR[DS] are cleared. This encourages software to use
address space 0 for system software and address space 1 for user software.
6.4.4.1
Instruction address spaces
The two effective instruction address spaces are defined by the value of MSR[IS], and
instruction fetch addresses are translated from the effective address space specified by the
current value of MSR[IS]. Changing the value of MSR[IS] is considered a context-altering
operation, requiring a context synchronization operation to follow it. When a context
synchronizing event occurs, any prefetched instructions are discarded and instructions are
refetched using the then-current state of MSR[IS] and the then-current program counter.
See Section 4.2.3.6: Context synchronization, for more information on the definition of
context synchronizing events.
Instructions are not fetched from memory designated by the TLB mechanism as no-execute
(UX = 0 or SX = 0). If the effective address of the current instruction is mapped to noexecute memory, an instruction storage interrupt (ISI) is generated.
Note that mapping a page as no-execute does not affect instruction caches in the system (or
any instructions resident in unified caches). Thus, if an instruction is loaded into a cache
when its effective address is mapped to execute permitted memory, and the execute
permissions for that page are later changed to no-execute, any instructions fetched before
the no-execute mapping remain in the cache until explicitly evicted by an icbi instruction or
through the cache’s replacement policy. However, attempted execution of such instructions
still results in an ISI. Thus, for example, the operating system can change the designation of
an application’s instruction pages to no-execute without having to first flush instruction
cache blocks that map to these pages.
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Data address spaces
The two effective data address spaces are defined by the value of MSR[DS] and data is
accessed to/from the effective address space specified by the current value of MSR[DS]. As
is the case with MSR[IS], changing the value of MSR[DS] is considered a context-altering
operation, requiring a context synchronization operation to follow it. When a context
synchronizing event occurs, subsequent accesses are made using the new state of
MSR[DS] (see Section 4.2.3.6: Context synchronization).
Data can be read from a page, provided the user read (UR) permission bit is set in the TLB
for a user access, or the supervisor read (SR) bit is set for a supervisor access. Likewise,
data write access permissions are determined by the user write (UW) and supervisor write
(SW) permission bits. If permissions are violated, the appropriate interrupt is taken.
6.4.5
Process ID
As described in Section 3.12.1: Process ID registers (PID0–PIDn), Book E defines that a
PID value be associated with each effective address (instruction or data) generated by the
processor. At the Book E level, one 32-bit PID register maintains the PID value for the
current process. This value is used to construct a virtual address for accessing memory.
Figure 81. Current PID Value
PID
0xnnnn_nnnn
0
63
effective address <ea>
System software uses PIDs to identify TLB entries that the processor uses to translate
addresses for loads, stores, and instruction fetches. PID contents are compared to the TID
field in TLB entries as part of selecting appropriate TLB entries for address translation. PID
values are used to construct virtual addresses for accessing memory. Note that individual
processors may not implement all 14 bits of the process ID field.
Book E defines one PID register that holds the PID value for the current process. ST
devices may implement from 1 to 15 PID registers. The number of PIDs implemented is
indicated by the value of MMUCFG[NPIDS]. Consult the user documentation for the
implementation to determine if other PID registers are implemented.
PID registers are more fully described in Section 3.12.1: Process ID registers (PID0–PIDn).
Software Note: The suggested PID usage is for PID0 to denote private mappings for a
process and for other PIDs to handle mappings that may be common to multiple processes.
This method allows for processes sharing address space to also share TLB entries if the
shared address space is mapped at the same virtual address in each process.
6.4.5.1
Process ID (PID) registers
The Book E architecture specifies that a process ID (PID) value be associated with each EA
(instruction or data) generated by the processor.
System software uses PIDs to identify TLB entries that the processor uses to translate
addresses for loads, stores, and instruction fetches. PID contents are compared to the TID
field in TLB entries as part of selecting appropriate TLB entries for address translation. PID
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values are used to construct virtual addresses for accessing memory. Note that individual
processors may not implement all 14 bits of the process ID field.
Book E defines one PID register that holds the PID value for the current process. ST
devices may implement from 1 to 15 PID registers. The number of PIDs implemented is
indicated by the value of MMUCFG[NPIDS]. Consult the user documentation for the
implementation to determine if other PID registers are implemented.
The 15 PID registers supported by the EIS are implemented as SPR registers set by system
software, and collectively reflect the process ID of the currently executing context. The
system maintains multiple PID values in order to allow the sharing of TLB entries for pages
that are shared among multiple execution contexts. For example, system software may
assign PID0 to contain the unique process ID (for private mappings for the current
processes) and may assign PID1 to contain the unique process ID for a common set of
shared libraries.
Note that Book E defines the value of all zeros for a TID field in a TLB entry as an entry that
is globally shared. Thus, when PID values (up to 12 bits for ST devices) are compared to the
TID fields in the TLB arrays for matches, if a TLB entry contains all zeros in the TID field, it
globally matches all PID values. PID registers are more fully described in Section 3.12.1:
Process ID registers (PID0–PIDn).
6.4.5.2
Address space identifiers
The AS bit is the address space identifier. Thus there are two possible address spaces, 0
and 1. The value of the AS bit is determined by the type of translation performed and from
the contents of the MSR when an address is translated. If the type of translation performed
is an instruction fetch, the value of the AS bit is taken from the contents of MSR[IS]. If the
type of translation performed is a load, store, or other data translation including target
addresses of software initiated instruction fetch hints and locks (icbt, icbtls, icbtlc) the
value of the AS bit is taken from the contents of MSR[DS]. The AS bit is defined by Book E.
Note:
Although system software is free to use address space bits as it sees fit, it should be noted
that on interrupt, the MSR[IS] and MSR[DS] bits are cleared. This encourages software to
use address space 0 for system software and address space 1 for user software.
6.4.6
Address translation
The effective address (EA) is the untranslated address for an instruction fetch address or for
a data address that is calculated as a result of a load, store, or cache management
instruction. The EA, concatenated with the MSR[IS] or MSR[DS] address space (AS) value,
is compared to the appropriate number of bits of the EPN field (depending on the page size)
and the TS field of the TLB entry. If a match occurs, that TLB entry is a candidate for a
translation match. In addition to a match in the EPN field and TS, a matching TLB entry
must match with the current process ID of the access.
Figure 82 shows the translation match logic for the effective address plus its attributes
(collectively called the virtual address) and how it is compared with the corresponding fields
in the TLB entries.
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Figure 82. Virtual address and TLB-entry comparison
TLB_entry[V]
TLB entry matches
virtual address
TLB_entry[TS]
=?
AS (from MSR[IS]
or MSR[DS])
Process ID
=?
TLB_entry[TID]
=0?
TLB_entry[EPN]
EA page number bits
private page
shared page
=?
The generation of the physical address occurs as shown in Figure 83.
Figure 83. Effective-to-real address translation
MSR[DS] for data access
MSR[IS] for instruction fetch
32-Bit Effective Address
AS
PID
Effective Page Number (EPN)
32
Offset
n–1 n
63
Virtual Address
TLB
multiple-entry
RPN field of matching entry
Real Page Number (RPN)
32
Offset
n–1 n
32-bit Real Address
63
NOTE: n = 32–log2(page size)
The EA combines with the AS and each PID register to form one virtual address for each
unique PID register value. Also. an implicit virtual address is formed using a PID value of 0.
Thus the following virtual addresses (VAs) are formed:
VA0 AS || 0 || EA
VA1 AS || PID0 || EA

...

VAn+1 AS || PIDn || EA
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Note that a PID register containing a 0 value (or the same value as another PID register)
forms a non-unique VA. Duplicate VAs are ignored.
Each of the unique VAs are compared to all the valid TLB entries by comparing specific
fields of each TLB entry to each of the VAs. The fields of each valid (TLB[V] = 1) TLB entry
are combined to form a set of matching TLB address (TAs):
TA TLBTS || TLBTID || TLBEPN || 120
Each TA is compared to all VAs under a mask based on the page size (TLB[SIZE]) of the
TLB entry. The mask of the comparison of the EA and EPN portions of the virtual and
translation addresses is computed as follows:
mask ~(1024 << (2 * TLBSIZE)) - 1)
where the number of bits in the mask is equal to the number of bits in a TA (or VA). If a TA
matches any VA the TLB entry is said to match. If more than one TA/VA match occurs, it is
considered a serious programming error and the results are undefined. The recommended
behavior is that a machine check interrupt is taken.
Once a match occurs the matching TLB is used for access control, storage attributes, and
effective to real address translation. Access control, storage attributes, and address
translation are defined by Book E (additional storage attributes are defined within this
document).
6.4.7
Address translation and the ST EIS
Translating an effective address to a real address is defined by Book E to require four
elements:

The address space value. Depending on the type of translation (instruction or data),
MSR[IS] or MSR[DS] is used.

The TLB entries in the TLB arrays

The effective address being translated
The following subsections describe these elements as they are further defined by the EIS.
6.4.7.1
Match criteria for TLB entries
TLB arrays contain TLB entries that are used to match any address presented for
translation. All TLB entries for any given implementation are candidates for any given
translation. The TLB itself is unordered with respect to the various elements used in address
translations, and regardless of implementation, should be considered to perform the
translation comparison with all entries in parallel.
There should be only one valid matching translation for a given effective address, PID value,
and address space value. If the TLB contains more than one matching entry, it is considered
a programming error, and the behavior of any such translation is undefined. In this case, the
processor is likely to enter checkstop state or take a machine check interrupt.
The following fields are compared in the TLB entries:
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V—The matching entry must have the V bit set.

TS—The address space identifier used for translation. The appropriate bit of MSR[IS]
or MSR[DS] must match the TS bit for a matching entry.

TID—The contents of a PID register must match the TID field of a matching entry, or
the TID field must be all zeros for a matching entry.
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
EPN—The appropriate number of bits (depending on the page size) of the effective
address being translated is compared to the EPN field of the TLB entry.
If a match occurs on all the fields listed above, the physical address is formed by replacing
the effective page number in the effective address with the value in the RPN field of the
matching TLB entry. The number of bits in the page number depends on the page size for
that TLB entry.
6.4.7.2
Translation algorithms
The following algorithm describes how translation operates at the ST Book E level:
ea = effective address
if translation is an instruction address then
as = MSR[IS]
else
// data address translation
as = MSR[DS]
for all TLB entries
if ! TLBV then
next
// compare next TLB entry
if as != TLBTS then
next
if TLBTID == 0 then
goto pid_match
for all PID registers
if this PID register == TLBTID then
goto pid_match
endfor
next
// no PIDs matched

pid_match:
// translation match
mask = ~((1024 << (2 * TLBTSIZE)) - 01)
if (ea & mask) != TLBEPN then
next
// no address match
real address = TLBRPN | (ea & ~mask) // real address computed
end translation -- success
endfor
end translation -- tlbmiss
The algorithm for the granting of permission is as follows:
if MSRPR == 0 then
x = TLBSX
r = TLBSR
w = TLBSW
else
x = TLBUX
r = TLBUR
w = TLBUW

if instruction fetch address then
if x == 0 then
Instruction Storage Interrupt
else
// data access
if data read (load) then
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if r == 0 then
Data Storage Interrupt
else
// write access (store)
if w == 0 then
Data Storage Interrupt
6.4.7.3
Access control
If address translation results in a match (hit), the matching TLB entry is used to perform
access control (permission checks). These checks are based on the privilege level of the
access (MSR[PR]) and the type of access (fetch for execute, read for loads, and write for
stores). The TLB entry’s permission bits (TLB[US,SX,UW,SW,UR,SR]) determine if the
operation should succeed. If permission is denied, execution of the instruction is
suppressed and an instruction storage interrupt or data storage interrupt occurs as defined
in Book E. Software uses the ESR, SRR0, and the DEAR to determine the type of operation
attempted and then must perform a TLB search if updating the TLB is desired.
The algorithm for determining access control is as follows:
if MSRPR = 0 then
x  TLBSX
r  TLBSR
w  TLBSW
else
x  TLBUX
r  TLBUR
w  TLBUW

if instruction_fetch & x = 0 then
take instruction storage interrupt
else if load &
r = 0 then
take data storage interrupt
else if store &
w = 0 then
take data storage interrupt
else
access permitted
6.4.7.4
Physical (real) address generation
If permission checking is successful, the real address is formed by combining the TLB[RPN]
with the lower order offset bits of the EA based on the page size of the TLB entry.
mask ~(1024 << (2 * TLBSIZE)) - 1)
real_address  ((TLBRPN << 12) & mask) | (EA & ~mask)
Where mask contains the same number of bits as a real address. The real address is then
used to access the memory subsystem using the TLB[ACM,VLE,W,I,M,G,E] fields from the
TLB entry to determine how the location should be accessed.
6.4.7.5
Page size and effective address bits compared
The page size defined for a TLB entry determines how many bits of the effective address
are compared with the corresponding EPN field in the TLB entry as shown in Table 185.
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Table 185. Page size and EPN field comparison
6.4.7.6
SIZE Field
Page Size (4SIZEKbytes)
EA to EPN Comparison (Bits 32–53; 2SIZE)
0b0000
1 Kbyte
EA[32–53] = ? EPN[32–53]
0b0001
4 Kbyte
EA[32–51] = ? EPN[32–51]
0b0010
16 Kbyte
EA[32–49] = ? EPN[0–49]
0b0011
64 Kbyte
EA[32–47] = ? EPN[32–47]
0b0100
256 Kbyte
EA[32–45] = ? EPN[32–45]
0b0101
1 Mbyte
EA[32–43] = ? EPN[32–43]
0b0110
4 Mbyte
EA[32–41] = ? EPN[32–41]
0b0111
16 Mbyte
EA[32–39] = ? EPN[32–39]
0b1000
64 Mbyte
EA[32–37] = ? EPN[32–37]
0b1001
256 Mbyte
EA[32–35] = ? EPN[32–35]
0b1010
1 Gbyte
EA[32–33] = ? EPN[32–33]
Permission attribute comparison
As part of the translation process, the selected TLB entry provides the access permission
bits (UX, SX, UW, SW, UR, SR), and memory/cache attributes (U0, U1, U2, U3, W, I, M, G,
and E) for the access. These bits specify whether or not the access is allowed and how the
access is to be performed.
If a matching TLB entry has been identified, Book E provides an access permission
mechanism that selectively grants shared access, grants execute access, grants read
access, grants write access, and prohibits access to areas of memory based on a number of
criteria. Book E defines the permission bits in TLB entries as follows:

SR—Supervisor read permission

SW—Supervisor write permission

SX—Supervisor execute permission

UR—User read permission

UW—User write permission

UX—User execute permission
If the virtual address translation comparison with TLB entries was successful, the
permission bits for the matching entry are checked as shown in Figure 84. If the access is
not allowed by the access permission mechanism, the processor generates an instruction or
data storage interrupt (ISI or DSI).
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Figure 84. Granting of Access Permission
TLB match (see Figure 82)
access
granted
MSR[PR]
instruction fetch
TLB_entry[UX]
TLB_entry[SX]
load-class data access
TLB_entry[UR]
TLB_entry[SR]
store-class data access
TLB_entry[UW]
TLB_entry[SW]
The permission attributes defined by Book E are defined in detail in Section 6.4.8.
6.4.7.7
Page size and real address generation
If no virtual address match occurs, the translation fails and a TLB miss exception occurs.
Depending on the access type (instruction or data address), either the instruction TLB error
interrupt or the data TLB error interrupt is taken.
Otherwise, the real page number (RPN) field of the matching TLB entry provides the
translation for the effective address of the access. Based on the setting of the SIZE field of
the matching TLB entry, the RPN field replaces the corresponding most-significant n bits of
the effective address where n = 32 - log2(page size). Note that the untranslated bits must be
zero in the RPN field.
Table 186. Real address generation
Size field Page size (4SIZEKbytes)
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RPN bits required to be equal
to 0
Real address
0b0000
1 Kbyte
none
RPN[32–53] || EA[54–63]
0b0001
4 Kbyte
RPN[52–53] = 0
RPN[32–51] || EA[52–63]
0b0010
16 Kbyte
RPN[50–53] = 0
RPN[32–49] || EA[50–63]
0b0011
64 Kbyte
RPN[48–53] = 0
RPN[32–47] || EA[48–63]
0b0100
256 Kbyte
RPN[46–53] = 0
RPN[32–45] || EA[46–63]
0b0101
1 Mbyte
RPN[44–53] = 0
RPN[32–43] || EA[44–63]
0b0110
4 Mbyte
RPN[42–53] = 0
RPN[32–41] || EA[42–63]
0b0111
16 Mbyte
RPN[40–53] = 0
RPN[32–39] || EA[40–63]
0b1000
64 Mbyte
RPN[38–53] = 0
RPN[32–37] || EA[38–63]
0b1001
256 Mbyte
RPN[36–53] = 0
RPN[32–35] || EA[36–63]
0b1010
1 Gbyte
RPN[34–53] = 0
RPN[32–33] || EA[34–63]
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6.4.8
Storage architecture
Permission attributes
The permission attributes defined in Book E are shown in Table 187 and described in the
following subsections.
Table 187. Permission control for instruction, data read, and data write accesses
TLB[UX]
Access type
TLB[UR]
TLB[SR]
TLB[UW]
TLB[SW]
0
1
0
1
0
1
0
1
0
1
0
1
0
—
—
ISI

—
—
—
—
—
—
—
—
1
ISI

—
—
—
—
—
—
—
—
—
—
Data read
(load)
0
—
—
—
—
—
—
DSI

—
—
—
—
1
—
—
—
—
DSI

—
—
—
—
—
—
Data write
(store)
0
—
—
—
—
—
—
—
—
—
—
DSI

1
—
—
—
—
—
—
—
—
DSI

—
—
Instruction fetch
6.4.8.1
TLB[SX]
MSR[PR]
Execute access permission
The UX and SX bits of the TLB entry control execute access to the corresponding page.
Instructions may be fetched and executed from a page in memory if MSR[PR] = 1 (user
mode) if the UX access control bit for that page is set. If the UX access control bit is cleared,
instructions from that page are not fetched and they are not placed into any cache while the
processor is in user mode.
Instructions may be fetched and executed from a page in memory if MSR[PR] = 0
(supervisor mode) and the SX access control bit for that page is set. If the SX access control
bit is cleared, instructions from that page are not fetched and are not placed into any cache
while the processor is in supervisor mode.
If the sequential execution model calls for the execution of an instruction from a page that is
not enabled for execution (that is, UX = 0 when MSR[PR] = 1 or SX = 0 when
MSR[PR] = 0), an execute access control exception-type instruction storage interrupt (ISI) is
taken.
6.4.8.2
Read access permission
The UR and SR bits of the TLB entry control read access to the corresponding page.
Load operations (including load-class cache management instructions) are permitted from a
page in memory while the processor is in user mode (MSR[PR] = 1) if the UR access control
bit for that page is set. If the UR access control bit is cleared, execution of the load
instruction is suppressed and a read access control exception-type data storage interrupt
(DSI) is taken.
Similarly, load operations (including load-class cache management instructions) are
permitted from a page in memory if MSR[PR] = 0 (supervisor mode) and the SR access
control bit for that page is set. If the SR access control bit is cleared, execution of the load
instruction is suppressed and a read access control exception-type data storage interrupt
(DSI) is taken.
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Write access permission
The UW and SW bits of the TLB entry control write access to the corresponding page.
Store operations (including store-class cache management instructions) are permitted to a
page in memory if MSR[PR] = 1 (user mode) and the UW access control bit for that page is
set. If the UW access control bit is cleared, execution of the store instruction is suppressed
and a write access control exception-type data storage interrupt (DSI) is taken.
Similarly, store operations (including store-class cache management instructions) are
permitted to a page in memory if MSR[PR] = 0 (supervisor mode) and the SW access
control bit for that page is set. If the SW access control bit is cleared, execution of the store
instruction is suppressed and a write access control exception-type data storage interrupt
(DSI) is taken.
6.4.8.4
Permission control and cache management instructions
The dcbi and dcbz instructions are treated as stores because they can change data (or
cause loss of data by invalidating a modified line). As such, they both can cause write
access control exception-type DSIs.
The dcba instruction is treated as a store because it can also change data. As such, it can
also cause a write access control exception. However, these exceptions do not result in a
data storage interrupt and if a permission violation occurs, the instruction execution
completes, but the allocate operation is merely cancelled (essentially, a no-op).
The icbi instruction is treated as a load with respect to permissions checking. As such, it
can cause a read access control exception-type data storage interrupt.
The dcbt, dcbtst, and icbt instructions are treated as loads with respect to permissions
checking. As such, they can cause read access control exceptions. However, such
exceptions do not result in data storage interrupts and if a permission violation occurs, the
instruction execution completes, but the operation is cancelled (essentially, a no-op).
The dcbf and dcbst instructions are treated as loads with respect to permissions checking.
Flushing or storing a line from the cache is not considered a store because the store has
already been performed to update the cache and the dcbf or dcbst instruction is only
updating the copy in main memory. Like load instructions, these instructions can cause read
access control exception-type data storage interrupts.
Table 188 summarizes exception cases caused by the cache management instructions due
to permissions violations.
Table 188. Permission control and cache instructions
Instruction
Can cause read permission violation
exception?
Can cause write permission violation
exception?
dcba
No
Yes(1)
dcbf
Yes
No
dcbi
No
Yes
dcbst
Yes
No
(1)
No
dcbtst
Yes(1)
No
dcbz
No
Yes
dcbt
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Storage architecture
Table 188. Permission control and cache instructions (continued)
Instruction
Can cause read permission violation
exception?
Can cause write permission violation
exception?
icbi
Yes
No
icbt
Yes
(1)
No
1. dcba, dcbt, dcbtst, and icbt may cause a read access control exception but does not result in a data
storage interrupt (DSI).
6.4.8.5
Permissions control and string instructions
When the string length is zero, neither lswx nor stswx can cause data storage interrupts
due to permissions violations.
6.4.8.6
Use of permissions to maintain page history
The Book E architecture TLB entry definition does not define bits for maintaining page
history information. The U0–U3 bits in the TLB entries can be used by software for storing
history information, but implementations may ignore these bits internally.
Page changed bit status can be implemented in the system software by disabling write
permissions to all pages. The first attempt to write to the page results in a data storage
interrupt. At this point, system software can record the page changed bit in memory, update
the TLB entry permission to allow writes to that page, and return to the user program
allowing further writes to the page to proceed without exception.
6.4.8.7
Crossing page boundaries
Care must be taken with single instruction accesses (load/stores) that cross page
boundaries. Examples are lmw and stmw instructions and misaligned accesses on
implementations that support misaligned load/stores. Architecturally, each of the parts of the
access that cross the natural boundary of the access size (half word, word, double word)
are treated separately with respect to exception conditions. Additionally, these types of
instructions may optionally partially complete. For example, a store word instruction that
crosses a page boundary because it is misaligned to the last half word of a page might
actually store the first 16 bits because the access was permitted, but produce a DSI or data
TLB error exception because the second 16 bits in the next page were not valid or they were
protected. An implementation may choose to suppress the first 16-bit store or perform it.
6.4.9
Translation lookaside buffer (TLB) arrays
The MMU contains up to four TLB arrays, which are on-chip storage areas for holding TLB
entries. A TLB entry contains effective-to-physical address mappings for loads, stores, and
instruction fetches. A TLB array must contain TLB entries that share the same
characteristics and contains zero or more TLB entries. Each TLB entry has specific fields
that can be addressed by the corresponding fields in the MMU assist registers (see
Section 3.12.5: MMU assist registers (MAS0–MAS7)). Each implemented TLB array has an
associated configuration register (TLBnCFG) describing the size and attributes of the TLB
entries in that array. See Section 3.12.4: TLB configuration registers (TLBnCFG).
The architected fields of a TLB entry are described in Table 189.
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Table 189. TLB entry
Name
V
Description
Valid bit. A 1-bit entry that specifies whether this TLB entry is valid for translation.
(1 = valid).
TID
Translation ID. Identifies which process ID (PID) that this TLB entry is valid for.
Translation IDs are compared with Process IDs (PIDs) during translation to identify
which TLB entry to use for translating an address. A TID value of 0 is considered
global and matches all PID values.
TS
Translation space. Identifies which address space that this TLB entry is valid for. The
translation space field is compared with MSR[IS] for instruction accesses and the
MSR[DS] bit for data accesses. This allows for an efficient change of address space
when a transition from user mode to supervisor mode occurs. This is a 1 bit field.
SIZE
Page size. Describes the size of the page. An implementation is not required to
support variable page sizes or any particular page size. If a TLB array does not
support variable size pages (that is, TLBnCFG[AVAIL] = 0) then this field is ignored.
Page sizes range from 4 Kbytes to 1 Tbyte in powers of 4. EIS does not support 1Kbyte page sizes defined in Book E. Page size encoding is defined by Book E.
EPN
Effective page number. Describes the logical or effective starting address of the page.
The number of bits that are valid (used in translation) depends on the size of the page
and if the processor is a 32- or 64-bit implementation. This field is used to compare
with the EA being translated to identify which TLB entry to use for translation. For 32bit implementations, this field is 2 to 20 bits, depending on the page size (SIZE).
RPN
Real page number. Describes the physical starting address of the page. The real
page number is substituted for the effective page number from the address being
translated which results in the real address. This field is 2 to 52 bits depending on the
page size and the number of bits of real address supported by the implementation.
WIMGE
Storage attributes. Describe the characteristics of any memory/fetch accesses to the
page and the subsequent treatment of those data items with respect to the memory
subsystem (caches and bus transactions). The WIMGE bits are defined by Book E.
ACM
Alternate coherency mode. Optional. An implementation may optionally support
additional coherency models. If such coherency models are provided, they are
encoded in this field. ACM values are implementation dependent. The Alternate
Coherence Mode is used only when the M bit (from WIMGE) is set.
VLE
Variable length encoding. Optional. If an implementation supports the VLE extension,
clearing VLE causes instruction access to this page to decode and execute as
PowerPC Book E (and EIS APUs) instructions, and setting VLE causes instruction
access to this page to decode and execute as VLE (and EIS APU) instructions.
SR,SW,SX,
UR,UW,UX
Permissions. User and supervisor read, write, and execute permission bits.
Supervisor and user permission bits are defined by Book E.
User bits. Implementation dependent. Consult the user’s manual for any
U0,U1,U2,U3 implementation usage. It is strongly recommended to leave these as storage
associated with a TLB entry to be used by system software.
IPROT
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Invalidation protection. Invalidation protection. This entry is protected from all TLB
invalidation mechanisms except the explicit writing of a 0 to the V bit.
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6.4.10
Storage architecture
TLB management
TLB entries are managed by software using the set of MAS registers, which are used to
move data between software and the TLB entries, to identify TLB entries, and to provide
default values when translation or protection faults occur. See Section 3.12.5: MMU assist
registers (MAS0–MAS7).
6.4.10.1
TLB configuration information
Information about the configuration for a given TLB implementation is available to system
software by reading the contents of the MMU configuration SPRs. These SPRs describe the
architectural version of the MMU, the number of TLB arrays, and the characteristics of each
TLB array. MMU architecture version number 1 is defined as these SPRs with the field
definitions as described in this section.
6.4.10.2

MMU configuration register (MMUCFG), implemented by all ST Book E processors,
contains basic information about the MMU architecture for each device. TLB
configuration registers (TLBnCFG). Implemented by all ST Book E processors for each
of the TLBs specified in MMUCFG[NTLBS]. They contain configuration information
about each particular TLB. See Section 3.12.3: MMU configuration register
(MMUCFG).

The TLBnCFG number assignment is the same as the value in MAS0[TLBSEL]. For
example, TLB0CFG provides configuration information about TLB0, and TLB1CFG
provides configuration information about TLB1. See Section 3.12.4: TLB configuration
registers (TLBnCFG).
TLB entries
The software-visible TLB is subdivided into zero or more TLB arrays. Each array must
contain TLB entries that share the same characteristics. Each TLB array contains one or
more TLB entries. Each entry has specific fields that correspond to fields in the seven MMU
assist (MAS) registers, described in Section 3.12.5: MMU assist registers (MAS0–MAS7).
Some TLB fields are architected in Book E and others are architected in the EIS. Note that
Book E architected fields may have restrictions or enhancements imposed by the EIS for
the Book E implementations.
The IPROT TLB entry, architected by the EIS, designates TLB entries as protected from
certain kinds of invalidation. TLB invalidation and the IPROT field are described further in
Section 6.4.10.6: Invalidating TLB entries.
6.4.10.3
Reading and writing TLB entries
All TLB entries are updated by executing tlbwe instructions. At the time of tlbwe execution,
the MMU assist registers (MAS0–MAS6), a set of SPRs defined by the EIS, are used to
index a specific TLB entry. The MAS registers also contain the information that is written to
the indexed entry, such that they serve as the ports into the TLBs, as shown in Figure 85.
The contents of the MAS registers are described in Section 3.12.5: MMU assist registers
(MAS0–MAS7).
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Figure 85. TLBs accessed through MAS registers and TLB instructions
TLB0
TLB1
TLBn
tlbwe, tlbre, tlbsx, tlbivax
MAS Registers
GPR
mtspr
mfspr
GPR
Similarly, TLB entries are read by executing tlbre instructions. At the time of tlbre execution,
the MAS registers are used to index a specific TLB entry and upon completion of the tlbre
instruction, the MAS registers contain the contents of the indexed TLB entry. To read or write
TLB entries, the MAS registers are first loaded by system software using mtspr instructions
and then the desired tlbre or tlbwe instructions must be executed.
Note that RA = 0 is a preferred form for tlbsx and that some Book E implementations take
an illegal instruction exception program interrupt if RA  0.
6.4.10.4
Reading TLB entries
TLB entries are read by executing tlbre instructions. At the time of tlbre execution, the MAS
registers are used to index a specific TLB entry and upon completion of the tlbre, the MAS
registers contain the contents of the indexed TLB entry.
Selection of the TLB entry to read is performed by setting MAS0[TLBSEL], MAS0[ESEL]
and MAS2[EPN] to indicate the entry to read. MAS0[TLBSEL] selects which TLB the entry
should be read from (0 to 3) and MAS2[EPN] selects the set of entries from which
MAS0[ESEL] selects an entry. For fully associative TLBs, MAS2[EPN] is not required since
the value in MAS0[ESEL] fully identifies the TLB entry. Valid values for MAS0[ESEL] are
from 0 to associativity - 1.
The selected TLB entry is then used to update the following fields of the MAS registers: V,
IPROT, TID, TS, TSIZE, EPN, ACM, VLE, WIMGE, RPN, U0—U3, & permissions. If the TLB
array supports NV, it is used to update the NV field in the MAS registers, otherwise the
contents of NV field are undefined. The update of MAS registers as a result of a tlbre
instruction is summarized in Table 191.
No operands are given for the tlbre instruction and the Book E defined implementation
dependent field should be treated as a reserved field.
Specifying invalid values for MAS0[TLBSEL] and MAS0[ESEL] produce boundedly
undefined results.
6.4.10.5
Writing TLB entries
TLB entries are written by executing tlbwe instructions. At the time of tlbwe execution, the
MAS registers are used to index a specific TLB entry and contain the contents to be written
to the indexed TLB entry. Upon completion of the tlbwe instruction, the TLB entry contents
of the MAS registers are written to the indexed TLB entry.
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Selection of the TLB entry to write is performed by setting MAS0[TLBSEL], MAS0[ESEL]
and MAS2[EPN] to indicate the entry to write. MAS0[TLBSEL] selects which TLB the entry
should be written from (0 to 3) and MAS2[EPN] selects the set of entries from which
MAS0[ESEL] selects an entry. For fully associative TLBs, MAS2[EPN] is not used to identify
a TLB entry since the value in MAS0[ESEL] fully identifies the TLB entry. Valid values for
MAS0[ESEL] are from 0 to associativity minus 1.
The selected TLB entry is then written with following fields of the MAS registers: V, IPROT,
TID, TS, TSIZE, EPN, ACM, VLE, WIMGE, RPN, U0—U3, and permissions. If the TLB array
supports NV, it is written with the NV value.
The effects of updating the TLB entry are not guaranteed to be visible to the programming
model until the completion of a context synchronizing operation. Writing a TLB entry that is
used by the programming model prior to a context synchronizing operation produces
undefined behavior.
No operands are given for the tlbwe instruction and the Book E defined implementation
dependent field should be treated as a reserved field.
Specifying invalid values for MAS0[TLBSEL] and MAS0[ESEL] produce boundedly
undefined results.
Note:
Writing TLB entries should be followed by an isync or an rfi before the new entries are to be
used by the programming model.
6.4.10.6
Invalidating TLB entries
TLB entries may be invalidated by any of the following methods:

A TLB entry can be invalidated as the result of a tlbwe instruction that clears MAS0[V]
in the entry.

As a result of a tlbivax instruction or from a received broadcast invalidation resulting
from a tlbivax on another processor in an SMP system.

As a result of a flash invalidate.
In both multiprocessor and uniprocessor systems, invalidations can occur on a wider set of
TLB entries than intended. This are called generous invalidations That is, a virtual address
presented for invalidation may invalidate not only the targeted TLB, but also may invalidate
other TLB entries, depending on the implementation. This is because parts of the translation
mechanism may not be fully specified to the hardware at invalidate time. This is especially
true in SMP systems where the invalidation address must be broadcast globally to all
processors in the system. Hardware may impose other limitations.
The architecture ensures that the intended TLB is invalidated, but does not guarantee that it
is the only one. A TLB entry invalidated by clearing the V bit of the TLB entry by use of a
tlbwe is guaranteed to invalidate only the addressed TLB entry. However, invalidates
occurring from tlbivax instructions or from the multiprocessor broadcasts as a result of
tlbivax instructions may cause generous invalidates.
The architecture provides a method to protect against generous invalidations. This is
important, because certain virtual memory regions (most notably, the code memory region
that serves as the exception handler for MMU faults) must be properly mapped to for
forward progress to occur. If this region does not have a valid mapping, an MMU exception
cannot be handled because the first address of the interrupt handler causes another MMU
exception. To prevent this, the architecture specifies an IPROT bit for TLB entries. Setting
the MAS0[PROT] protects the corresponding TLB entry from invalidations resulting from
tlbivax instructions, as a result of broadcast invalidation from another processor in an SMP
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system, or from flash invalidations. TLB entries with the IPROT field set can be invalidated
only by explicitly writing the TLB entry and specifying a 0 for MAS1[V].
Note:
Software Note: Not all TLB arrays in a given implementation implement the IPROT attribute.
It is likely that implementations that are suitable for demand page environments implement it
for only a single array, while not implementing it for other arrays.
Software Note: Operating systems must use great care when using protected (IPROT) TLB
entries, particularly in SMP systems. An SMP system that contains TLB entries on other
processors requires a cross-processor interrupt or some other synchronization mechanism
to assure that each processor performs the required invalidation by writing its own TLB
entries.
6.4.10.7
Invalidations using tlbivax:
The tlbivax instruction provides a virtual address as a target for invalidation. EA[0–51] are
used to find a TLB entry with a matching EPN field. The page size of the TLB entry is used
to mask the low order bits in the comparison. The comparison is performed only for TLB
entries in the specified TLB array, do not have the IPROT attribute set (if supported by the
TLB array), and are valid. The AS bit does not participate in the comparison. The EA
specified by the rA and rB operands in the tlbivax instruction contains fields in the lower
order bits to augment the invalidation to specific TLB arrays and to flash invalidate those
arrays. Note that TLB entry invalidations resulting from tlbivax instructions do not invalidate
any entry that has IPROT = 1 unless the specified TLB array does not support the IPROT
attribute. The encoding of the EA used by tlbivax is shown in Table 190.
Note:
Software Note: To ensure a TLB entry that is not protected by IPROT is invalidated if
software does not know which TLB array the entry is in, software should issue a tlbivax
instruction targeting each TLB in the implementation with the EA to be invalidated.
Software Note: The preferred form of the tlbivax instruction contains the entire EA in rB and
zero in rA. Some implementations may take an Unimplemented Instruction exception if rA is
non-zero.
EA format for tlbivax ia shown below.
EA Format for tlbivax
0
51 52
EA0:51
EA for tlbivax
58
—
Table 190 describes EA fields for tlbivax.
Table 190. Fields for EA format of tlbivax
Field
Comments or function when set
0–51
EA0:51
The upper bits of the address to invalidate.
52–58
—
Reserved, should be cleared.
TLB
Selects TLB array for invalidation.
00 TLB0
01 TLB1
10 TLB2
11 TLB3
59–60
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61 62
IA
63
—
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Storage architecture
Table 190. Fields for EA format of tlbivax
Field
Name
Comments or function when set
61
IA
Invalidate all entries in selected TLB array.
62–63
—
Reserved, should be cleared.
Flash invalidations using MMUCSR0:
All entries in a TLB array may be flash invalidated using the MMUCSR0 register. Flash
invalidation of an array is started when the corresponding flash invalidate bit is set in
MMUCSR0 (MMUCSR0[TLBn_FI]). The flash invalidation is complete when the
corresponding flash invalidate bit is cleared by the processor. Writing a 0 to a flash
invalidate bit in MMUCSR0 has no effect. Note that TLB entry invalidations resulting from
MMUCSR0 flash invalidations do not invalidate any entry that has IPROT = 1 unless the
specified TLB array does not support the IPROT attribute.
6.4.10.8
Searching TLB Entries
Software may search the MMU by using the tlbsx instruction that is provided by Book E.
The tlbsx instruction uses PID values and an AS value from the MAS registers instead of
the PID registers and the MSR. This allows software to search address spaces that differ
from the current address space defined by the PID registers. This is useful for TLB fault
handling.
To properly execute a search for a TLB, software loads MAS5 and MAS6 registers with PID
and AS values to search for. These are MAS6[SPID0], MAS6[SPID1], MAS5[SPID2],
MAS5[SPID3], MAS6[SAS]. Software then executes a tlbsx instruction. The search
performs the same TA to VA comparison described in Section 6.4.6, except that the PID and
AS values are taken from the MAS registers. If a matching, valid TLB entry is found, the
MAS register are loaded with the information from that TLB entry as if the TLB entry was
read from a tlbre instruction. Software can examine the MAS1[V] bit to determine if the
search was successful. Successful searches cause the valid bit to be set. Table 191
summarizes the update of MAS registers as a result of a tlbsx instruction.
The preferred form of the tlbsx is rA = 0. Some implementations may take an
unimplemented instruction exception or an illegal instruction exception if rA != 0.
6.4.10.9
TLB replacement hardware assist
The architecture provides mechanisms to accelerate software in creating and updating TLB
entries when MMU related exceptions occur. This is called TLB replacement hardware
assist. Hardware updates the MAS registers on the occurrence of a data TLB error interrupt
or instruction TLB error interrupt.
When a TLB error exception (miss) occurs, MAS0, MAS1, and MAS2 are automatically
updated using the defaults specified in MAS4 as well as the AS and EPN values
corresponding to the access that caused the exception. MAS6 is updated to set
MAS6[SPID0] to the value of PID0 and MAS6[SAS] to the value of MSR[DS] or MSR[IS]
depending on the type of access that caused the TLB error. In addition, if MAS4[TLBSELD]
identifies a TLB array that supports NV (next victim), MAS0[ESEL] is loaded with a value
that hardware believes represents the best TLB entry to victimize to create a new TLB entry
and MAS0[NV] is updated with the TLB entry index of what hardware believes to be the next
victim. Thus MAS0[ESEL] identifies the current TLB entry to be replaced, and MAS0[NV]
points to the next victim. When software writes the TLB entry, MAS0[NV] is written to the
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TLB array. The algorithm used by the hardware to determine which TLB entry should be
targeted for replacement is implementation dependent.
The automatic update of MAS registers sets up all the necessary fields for creating a new
TLB entry with the exception of RPN, the U0–U3 attribute bits, and the permission bits. With
the exception of the upper 32 bits of RPN and the page attributes (should software desire to
specify changes from the default attributes), all remaining fields are located in MAS3,
requiring only the single MAS register manipulation by software before writing the TLB entry.
For ISI and DSI related exceptions, the MAS registers are not updated. Software must
explicitly search the TLB to find the appropriate entry.
The update of MAS registers through TLB replacement hardware assist is summarized in
Table 191.
Table 191. MAS register update summary
Value loaded on event
MAS field
updated
TLB error interrupt
MAS0[TLBSEL] MAS4[TLBSELD]
tlbsx hit
tlbsx miss
tlbre
TLB array that hit
MAS4[TLBSELD]
—
MAS0[ESEL]
if MAS4[TLBSELD]
supports next victim
then hardware hint,
else undefined
Number of entry that hit
if MAS4[TLBSELD]
supports next victim
then hardware hint,
else undefined
—
MAS0[NV]
if MAS4[TLBSELD]
supports next victim
then next hardware
hint,
else undefined
if MAS4[TLBSELD]
if MAS4[TLBSELD] supports
supports next victim
next victim then hardware
then next hardware
hint,
hint,
else undefined
else undefined
if
MAS4[TLBSELD]
supports next
victim then
hardware hint,
else undefined
MAS1[V]
1
1
0
TLB[V]
MAS1I[PROT]
0
TLB[IPROT]
0
TLB[IPROT]
MAS1[TID]
if PID[MAS4[TIDSELD]]
implemented then
TLB[TID]
PID[MAS4[TIDSELD]]
else 0
MAS6[SPID0]
TLB[TID]
MAS1[TS]
MSR[IS] or MSR[DS]
TLB[TS]
MAS6[SAS]
TLB[TS]
MAS1[TSIZE]
MAS4[TSIZED]
TLB[SIZE]
MAS4[TSIZED]
TLB[SIZE]
MAS2[EPN]
EA0:51
TLB[EPN]
—
TLB[EPN]
MAS2[ACM]
MAS4[ACMD]
TLB[ACM]
MAS4[ACMD]
TLB[ACM]
MAS2[VLE]
MAS4[VLED]
TLB[VLE]
MAS4[VLED]
TLB[VLE]
MAS2[W]
MAS4[WD]
TLB[W]
MAS4[WD]
TLB[W]
MAS2[I]
MAS4[ID]
TLB[I]
MAS4[ID]
TLB[I]
MAS2[M]
MAS4[MD]
TLB[M]
MAS4[MD]
TLB[M]
MAS2[G]
MAS4[GD]
TLB[G]
MAS4[GD]
TLB[G]
MAS2[E]
MAS4[ED]
TLB[E]
MAS4[ED]
TLB[E]
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Table 191. MAS register update summary (continued)
Value loaded on event
MAS field
updated
TLB error interrupt
tlbsx hit
tlbsx miss
tlbre
TLB[RPN]
(bits 32:51)
0
TLB[RPN]
(bits 32:51)
MAS3[U0,U1,U
—
2,U3]
TLB[U0,U1,U2,U3]
—
TLB[U0,U1,U2,U
3]
MAS3[UX,SX,U
0
W,
SW,UR,SR]
TLB[UX,SX,UW,
SW,UR,SR]
0
TLB[UX,SX,UW,
SW,UR,SR]
MAS4
—
—
—
—
MAS5
—
—
—
—
MAS6[SPID0]
PID0
—
—
—
MAS6[SPID1]
—
—
—
—
MAS6[SAS]
MSR[IS] or MSR[DS]
—
—
—
MAS7[RPN]
0
TLB[RPN]
(bits 0–31)
0
TLB[RPN]
(bits 0–31)
MAS3[RPN]
6.4.11
0
MAS registers and exception handling
When translation-related exceptions occur, hardware preloads the MAS registers with
information that the interrupt handler likely needs to handle the fault. For a TLB miss
exception, some MAS register fields are loaded with default information specified in MAS4.
System software should set up the default information in MAS4 before allowing exceptions.
In most cases, system software sets this up once depending on its scheme for handling
page faults. This simplifies translation-related exception handling. The following subsections
detail specific MAS register fields and the contents loaded for each exception type.
6.4.11.1
TLB miss exception types
The Book E architecture defines that a TLB miss exception is caused when a virtual address
for an access does not match with that of any on-chip TLB entry. This condition causes one
of the following:

An instruction TLB error interrupt

A data TLB error interrupt
6.4.11.1.1 Instruction TLB error interrupt settings
An instruction TLB error interrupt occurs when the virtual address associated with an
instruction address (fetch) does not match any valid entry in the TLB (that is, the address for
the instruction cannot be translated). In addition to the values automatically written to the
MAS registers (described in TLB miss exception MAS register settings), SRR0 contains the
address of the instruction that caused the instruction TLB error. This SRR0 value is used to
identify the EA for handling the exception as well as the address to return to when system
software has resolved the exception condition by writing a new TLB entry.
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6.4.11.1.2 Data TLB error interrupt settings
A data TLB error interrupt occurs when the virtual address associated with a data reference
from a load, store, or cache management instruction does not match any valid entry in the
TLB (that is, the address of the data item of a load or store instruction cannot be translated).
In addition to the values automatically written to the MAS registers (described in TLB miss
exception MAS register settings), the effective address of the data access that caused the
exception is automatically loaded in the data exception address register (DEAR). Also,
SRR0 contains the address of the instruction that caused the data TLB error and its value is
used to identify the address to return to when system software has resolved the exception
condition (by writing a new TLB entry).
TLB miss exception MAS register settings
When either an instruction or data TLB error interrupt occurs, the TLB information and
selection fields of the MAS registers are loaded with default values from other MAS registers
to assist in processing the exception. The intention is that the common case of a page fault
generally requires only system software to load the RPN (corresponding to the physical
address that will be used for this page), and the access permissions and the defaults can be
used for the remaining MAS fields.
The processor may use the next victim (NV) field from the TLB array to select which TLB
entry should be used for the new translation. The method used to select the candidate TLB
for replacement (the next victim) is implementation-dependent and may vary on different
Book E implementations. In any case, software is free to choose any TLB entry for the
replacement (software can overwrite the value in MAS0[ESEL]).
The EIS defines the fields set in the MAS registers at exception time for an instruction or
data TLB error interrupt as shown in Table 192.
Table 192. MAS settings for an instruction or data TLB error interrupt
MAS Field
Value
TLBSEL
Set to value in TLBSELD (default). This defines the TLB array to be used for the new TLB entry that
will be written.
ESEL
May be set to an implementation-dependent value, usually based on the NV field of the array
selected by TLBSELD, if that TLB supports the NV function. If the selected TLB does not support NV,
the value loaded into ESEL is undefined.
NV
Set to an implementation-dependent value to select which TLB entry to replace on the next TLB
miss. The NV field of the TLB array is updated by the value of NV in the MAS registers when tlbwe is
executed.
V
Set
IPROT
Cleared
TID
Set to the contents of the PID register referenced by TIDSELD. That is, if TIDSELD contains the
value 1, the contents of PID1 are written to the TID field.
TS
Set to the value of the IS or DS bit in the MSR at the time of the exception (that is, the MSR that
described the context that was running when the exception occurred).
TSIZE
Set to TSIZED
EPN
Set to the effective page number of the instruction or data address causing the exception. The
number of bits of the page number is implementation-dependent, but should be consistent with the
TLB array selected if the TLB has a fixed page size. If the TLB array selected by TLBSELD contains
variable-sized pages, the value for EPN is undefined.
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Table 192. MAS settings for an instruction or data TLB error interrupt
MAS Field
Value
WIMGE 
and X bits
Set to corresponding default values in the MAS registers
RPN
Cleared
Permissions SR, UR, UW, SW, UX, SX cleared to 0 (no permissions); note that U0–U3 are unchanged.
All other MAS register values are unchanged.
6.4.11.2
Permissions violation exception types
The Book E architecture also defines that a permissions violation exception is caused when
an effective address for an access matches with a TLB entry but the permission attributes in
the matching TLB entry do not allow the access to proceed, as described in Section 6.4.8.
This condition causes an instruction storage interrupt (ISI) or a data storage interrupt (DSI)
Instruction storage interrupt settings
An instruction storage interrupt occurs when the effective address associated with an
instruction address (fetch) matches a valid entry in the TLB but one of the permission bits in
the TLB does not allow the instruction fetch. In addition to the values automatically written to
the MAS registers (described in Permissions violation mas register settings”), SRR0
contains the address of the instruction that caused the instruction TLB error and this value is
used to identify the effective address for handling the exception as well as the address to
return to when system software has resolved the exception condition (by writing a new TLB
entry).
6.4.11.2.1 Data storage interrupt settings
A data storage interrupt occurs when the EA associated with a data reference from a load or
store instruction matches with a valid entry in the TLB but one of the permission bits in the
TLB does not allow the data access. In addition to the values automatically written to the
MAS registers (described in Permissions violation mas register settings), the effective
address of the data access that caused the exception is contained in the data exception
address register (DEAR). This address is used by system software to identify the address
that caused the exception. Also, SRR0 contains the address of the instruction that caused
the data storage interrupt and its value is used to identify the address to return to when
system software has resolved the exception condition by writing a new TLB entry.
Permissions violation mas register settings
When either an instruction or data storage interrupt occurs, only the SPIDx and the SAS
fields are automatically loaded into the MAS registers to assist in processing the interrupt.
System software is required to then execute a tlbsx instruction to load the MAS registers
with the TLB entry associated with the instruction address. System software may then make
any desired changes to the TLB entry prior to writing it. Table 193 describes the fields set in
the MAS registers at exception time for instruction or data storage interrupts.
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Table 193. MAS settings for permissions violation ISI or DSI
Field
Setting
SPID0
Set to PID0
SPID1
Set to PID1
SPID2
Set to PID2
SPID3
Set to PID3
SAS
Set to the value of MSR[IS] (for an instruction storage interrupt) or MSR[DS] (for a
data storage interrupt) at the time of the exception (that is, the MSR that described
the context that was running when the exception occurred).
All other MAS register values are unchanged.
6.4.11.3
MAS register updates for exceptions, tlbsx, and tlbre
Table 194 summarizes MAS register fields updates from the perspective of the EIS as a
result of various events. Note that the implementations further define how certain MAS fields
are set on exceptions.
Table 194. MMU assist register field updates—EIS definition
Value loaded for each case
MASn
bit/field
ITLB/DTLB error
tlbsx hit
tlbsx miss
ISI
DSI
tlbre
tlbwe
TLBSEL
TLBSELD
Which TLB hit
TLBSELD
—
—
—
—
ESEL
If TLBSELD supports
NV:
TLB0[NV]
else, undefined
Number of
entry that hit
If TLBSELD
supports NV:
—
TLB0[NV]
else, undefined
—
—
—
NV
If TLBSELD supports
NV:
next NV (array)
else, undefined
If TLBSEL
supports NV:
NV (array)
else, undefined
If TLBSELD
supports NV:
—
next NV (array)
else, undefined
—
If TLBSEL
supports NV:
—
NV (array)
else, undefined
V
1
1
0
—
V (array)
—
IPROT
0
If TLB that hits
supports
IPROT:
matched
IPROT value;
else, 0
0
—
—
If TLB that hits
supports
IPROT:
matched
IPROT value;
else, 0
—
TID
PIDn values selected
by TIDSELD
TID (array)
SPID0
—
—
TID(array)
—
TS
MSR[IS/DS]
SAS
SAS
—
—
TS (array)
—
TSIZE[0–3]
TSIZED
TSIZE (array)
TSIZED
—
—
TSIZE (array)
—
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Table 194. MMU assist register field updates—EIS definition (continued)
Value loaded for each case
MASn
bit/field
ITLB/DTLB error
If TLBSELD has fixed
page size:
EPN[32–51]
EPN of access
else, undefined
tlbsx hit
DSI
tlbre
tlbwe
—
EPN (array)
X0, X1 (array) X0D, X1D
WIMGE (array) WIMGED
—
—
X0, X1 (array)
—
WIMGE (array)
RPN[32–51] Zeros
RPN(array)
Zeros
—
—
RPN (array)
PERMIS
Zeros
PERMIS (array) Zeros
—
—
PERMIS (array) —
TLBSELD
—
—
—
—
—
—
—
TIDSELD
—
—
—
—
—
—
—
TSIZED
—
—
—
—
—
—
—
WIMGED
—
—
—
—
—
—
—
X0D, X1D
WIMGED
—
ISI
—
X0, X1
WIMGE
EPN (array)
tlbsx miss
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Instruction set
This chapter describes the following instructions:
7.1

Book E instructions defined for 32-bit implementations. This includes instructions not
implemented in all Book E devices.

Instructions defined by the EIS, except for the instructions defined by the VLE
extension. Full descriptions of these instructions are provided in Section 14: VLE
instruction set.
Notation
The following definitions and notation are used throughout this chapter in the instruction
descriptions.
Table 195. Notation conventions
Symbol
Xp
Meaning
Bit p of register/field X
Xfield
The bits composing a defined field of X. For example, Xsign, Xexp, and Xfrac represent the
sign, exponent, and fractional value of a floating-point number X
Xp:q
Bits p through q of register/field X
Xp q ...
X
Field i
Bits p, q,... of register/field X
The one’s complement of the contents of X
Bits 4 i through 4 i + 3 of a register
.
As the last character of an instruction mnemonic, this character indicates that the
instruction records status information in certain fields of the condition register as a side
effect of execution, as described in Section 3.5.1: Condition register (CR).
||
Describes the concatenation of two values. For example, 010 || 111 is the same as 010111.
n
x
x raised to the nth power
nx
The replication of x, n times (i.e., x concatenated to itself n–1 times). n0 and n1 are special
cases: 
n0 means a field of n bits with each bit equal to 0. Thus 50 is equivalent to 0b0_0000.
n
1 means a field of n bits with each bit equal to 1. Thus 51 is equivalent to 0b1_1111.
A reserved field in an instruction or in a register. Each bit and field in instructions, in status
/, //, ///, and control registers (such as the XER or FPSCR), and in SPRs is either defined,
allocated, or reserved, as described in Section 4.2.1: Classes of instructions.
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Instruction set
Instruction fields
Table 196 describes instruction fields.
Table 196. Instruction field descriptions
Field
Description
AA (30)
Absolute address bit.
0 The immediate field represents an address relative to the current instruction address.
For I-form branch instructions the effective address of the branch target is the value 320 ||
(CIA+EXTS(LI||0b00))32–63.
For B-form branch instructions the effective address of the branch target is the value 320 ||
(CIA+EXTS(BD||0b00))32–63.
For I-form branch extended instructions the effective address of the branch target is the
value CIA+EXTS(LI||0b00).
For B-form branch extended instructions the effective address of the branch target is the
value CIA+EXTS(BD||0b00).
1 The immediate field represents an absolute address.
For I-form branch instructions the effective address of the branch target is the value 320 ||
EXTS(LI||0b00)32–63.
For B-form branch instructions the effective address of the branch target is the value 320 ||
EXTS(BD||0b00)32–63.
For I-form branch extended instructions the effective address of the branch target is the
value EXTS(LI||0b00).
For B-form branch extended instructions the effective address of the branch target is the
value EXTS(BD||0b00).
crbA (11–15)
Used to specify a condition register bit to be used as a source
crbB (16–20)
Used to specify a condition register bit to be used as a source
crD (6–8)
Used to specify a CR or FPSCR field to be used as a target
crS (11–13)
Used to specify a CR or FPSCR field to be used as a source
BI (11–15)
Used to specify a condition register bit to be used as the condition of a branch conditional
instruction
BO (6–10)
Used to specify options for branch conditional instructions. See Section 4.3.1.11: Branch
and flow control instructions.
crbD (6–10)
Used to specify a CR or FPSCR bit to be used as a target
CT (6–10)
Used by cache touch instructions (dcbt, dcbtst, and icbt) to specify the target portion of
the cache facility to place the prefetched data or instructions and is implementationdependent
D (16–31)
Immediate field used to specify a 16-bit signed two’s complement integer that is signextended to 64 bits
DCRN(16–20||11–15) Used to specify a device control register for the mtdcr and mfdcr instructions
E (15)
Immediate field used to specify a 1-bit value used by wrteei to place in MSR[EE] (external
input enable bit)
FM (7–14)
Field mask used to identify FPSCR fields that are to be updated by the mtfsf instruction
frA (11–15)
Used to specify an FPR to be used as a source
frB (16–20)
Used to specify an FPR to be used as a source
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Table 196. Instruction field descriptions (continued)
Field
Description
frC (21–25)
Used to specify an FPR to be used as a source
frS (6–10)
Used to specify an FPR to be used as a source
frD (6–10)
Used to specify an FPR to be used as a target
CRM (12–19)
Field mask used to identify the condition register fields to be updated by the mtcrf
instruction
LI (6–29)
Immediate field specifying a 24-bit signed two’s complement integer that is concatenated
on the right with 0b00 and sign-extended to 64 bits
LK (31)
LINK bit. Indicates whether the link register (LR) is set.
0Do not set the LR.
1Set the LR. The sum of the value 4 and the address of the branch instruction is placed
into the LR.
MB (21–25) and ME
(26–30)
Fields used in M-form rotate instructions to specify a 64-bit mask consisting of 1 bits from
bit MB+32 through bit ME+32 inclusive and 0 bits elsewhere.
MO (6–10)
Used to specify the subset of memory accesses ordered by a Memory Barrier instruction
(mbar).
NB (16–20)
Used to specify the number of bytes to move in an immediate Move Assist instruction
OPCD (0–5)
Primary opcode field
rA (11–15)
Used to specify a GPR to be used as a source or as a target
rB (16–20)
Used to specify a GPR to be used as a source
Rc (31)
Record bit.
0Do not alter the condition register.
1Set condition register field 0 or field 1.
RS (6–10)
Used to specify a GPR to be used as a source
rD (6–10)
Used to specify a GPR to be used as a target
SH (16–20)
SIMM (16–31)
Used to specify a shift amount in rotate word immediate and shift word immediate
instructions
Immediate field used to specify a 16-bit signed integer
SPRN (16–20||11–15) Used to specify an SPR for mtspr and mfspr instructions
TO (6–10)
Used to specify the conditions on which to trap. The encoding is described in Table 92:
Trap instructions.
U (16–19)
Immediate field used as the data to be placed into a field in the FPSCR
UIMM (16–31)
Immediate field used to specify a 16-bit unsigned integer
XO (21–29, 21–30,
22–30, 26–30, 27–29, Extended opcode field
27–30, 28–31)
7.3
Description of instruction operations
The operation of most instructions is described by a series of statements using a semiformal
language at the register transfer level (RTL), which uses the general notation given in
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Table 195 and Table 196 and the RTL-specific conventions in Table 197. See the example
in Figure 86. Some of this notation is used in the formal descriptions of instructions.
The RTL descriptions cover the normal execution of the instruction, except that ‘standard’
setting of the condition register, integer exception register, and floating-point status and
control register are not always shown. (Non-standard setting of these registers, such as the
setting of condition register field 0 by the stwcx. instruction, is shown.) The RTL
descriptions do not cover all cases in which exceptions may occur, or for which the results
are boundedly undefined, and may not cover all invalid forms.
RTL descriptions specify the architectural transformation performed by the execution of an
instruction. They do not imply any particular implementation.
Table 197. RTL notation
Notation
Meaning

Assignment
f
Assignment in which the data may be reformatted in the target location

NOT logical operator (one’s complement)
+
Two’s complement addition
–
Two’s complement subtraction, unary minus

Multiplication

Division (yielding quotient)
+dp
Floating-point addition, double precision
–dp
Floating-point subtraction, double precision
dp
Floating-point multiplication, double precision
dp
Floating-point division quotient, double precision
+sp
Floating-point addition, single precision
–sp
Floating-point subtraction, single precision
sf
Signed fractional multiplication. Result of multiplying two quantities having bit
lengths x and y taking the least significant x+y–1 bits of the product and
concatenating a 0 to the least significant bit forming a signed fractional result of
x+y bits.
si
Signed integer multiplication
sp
Floating-point multiplication, single precision
sp
Floating-point division, single precision
fp
Floating-point multiplication to infinite precision (no rounding)
ui
Unsigned integer multiplication
FPSquareRootDouble(x)
Floating-point
x , result rounded to double-precision
FPSquareRootSingle(x)
Floating-point
x , result rounded to single-precision
FPReciprocalEstimate(x)
1
Floating-point estimate of --x
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Table 197. RTL notation (continued)
Notation
FPReciprocal-SquareRootEstimate(x)
Allocate-DataCacheBlock(x)
Flush-DataCacheBlock(x)
Meaning
1
Floating-point estimate of ------x
If the block containing the byte addressed by x does not exist in the data cache,
allocate a block in the data cache and set the contents of the block to 0.
If the block containing the byte addressed by x exists in the data cache and is
dirty, the block is written to main memory and is removed from the data cache.
Invalidate-DataCacheBlock(x)
If the block containing the byte addressed by x exists in the data cache, the block
is removed from the data cache.
Store-DataCacheBlock(x)
If the block containing the byte addressed by x exists the data cache and is dirty,
the block is written to main memory but may remain in the data cache.
Prefetch-DataCacheBlock(x,y)
If the block containing the byte addressed by x does not exist in the portion of the
data cache specified by y, the block in memory is copied into the data cache.
Prefetch-ForStoreDataCache-Block(x,y)
If the block containing the byte addressed by x does not exist in the portion of the
data cache specified by y, the block in memory is copied into the data cache and
made exclusive to the processor executing the instruction.
ZeroDataCacheBlock(x)
The contents of the block containing the byte addressed by x in the data cache is
cleared.
Invalidate-InstructionCacheBlock(x)
If the block containing the byte addressed by x is in the instruction cache, the
block is removed from the instruction cache.
Prefetch-InstructionCacheBlock(x,y)
If the block containing the byte addressed by x does not exist in the portion of the
instruction cache specified by y, the block in memory is copied into the instruction
cache.
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=, 
Equals, Not Equals relations
<, , >, 
Signed comparison relations
<u, >u
Unsigned comparison relations
?
Unordered comparison relation
&, |
AND, OR logical operators
, 
Exclusive OR, Equivalence logical operators ((ab) = (ab))
>>, <<
Shift right or left logical
ABS(x)
Absolute value of x
APID(x)
Returns an implementation-dependent information on the presence and status of
the auxiliary processing extensions specified by x
CEIL(x)
Least integer  x
DCREG(x)
Device control register x
DOUBLE(x)
Result of converting x from floating-point single format to floating-point double
format
EXTS(x)
Result of extending x on the left with signed bits
EXTZ(x)
Result of extending x on the left with zeros
FPR(x)
Floating-point register x
GPR(x)
General-purpose register x
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Instruction set
Table 197. RTL notation (continued)
Notation
MASK(x, y)
MEM(x,1)
MEM(x,y)
(for y={2,4,8})
MOD(x,y)
ROTL32(x, y)
Meaning
Mask having 1s in bit positions x through y (wrapping if x>y) and 0s elsewhere
Contents of the byte of memory located at address x
Contents of y bytes of memory starting at address x.
If big-endian memory, the byte at address x is the MSB and the byte at address
x+y–1 is the LSB of the value being accessed.
If little-endian memory, the byte at address x is the LSB and the byte at address
x+y–1 is the MSB of the value being accessed.
Modulo y of x (remainder of x divided by y)
Result of rotating the value x left y positions, where x is 32 bits long
SINGLE(x)
Result of converting x from floating-point double format to floating-point single
format
SPREG(x)
Special-purpose register x
TRAP
characterization
Invoke a trap-type program interrupt
Reference to the setting of status bits in a standard way that is explained in the
text
undefined
An undefined value. The value may vary between implementations and between
different executions on the same implementation.
CIA
Current instruction address, the address of the instruction being described in
RTL. Used by relative branches to set the next instruction address (NIA) and by
branch instructions with LK=1 to set the LR. CIA does not correspond to any
architected register.
NIA
Next instruction address, the address of the next instruction to be executed. For a
successful branch, the next instruction address is the branch target address: in
RTL, this is indicated by assigning a value to NIA. For other instructions that
cause non-sequential instruction fetching, the RTL is similar. For instructions that
do not branch, and do not otherwise cause instruction fetching to be nonsequential, the next instruction address is CIA+4. NIA does not correspond to any
architected register.
if … then …
else …
do
leave
Conditional execution, indenting shows range; else is optional
Do loop, indenting shows range. ‘To’ and/or ‘by’ clauses specify incrementing an
iteration variable, and a ‘while’ clause gives termination conditions.
Leave innermost do loop, or do loop described in leave statement.
Precedence rules for RTL operators are summarized in Table 198. Operators higher in the
table are applied before those lower in the table. Operators at the same level in the table
associate from left to right, from right to left, or not at all, as shown. (For example, –
associates from left to right, so a–b–c = (a–b)–c.) Parentheses are used to override the
evaluation order implied by the table or to increase clarity; parenthesized expressions are
evaluated before serving as operands.
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Table 198. Operator precedence
Operators
7.3.1
Associativity
Subscript, function evaluation
Left to right
Pre-superscript (replication), post-superscript (exponentiation)
Right to left
unary –, 
Right to left
, 
Left to right
+, –
Left to right
||
Left to right
=, , <, , >, , <u, >u, ?
Left to right
&, , 
Left to right
|
Left to right
: (range)
None

None
SPE APU saturation and bit-reverse models
For saturation and bit reversal, the pseudo RTL is provided here to more accurately
describe those functions that are referenced in the instruction pseudo RTL.
Saturation
SATURATE(overflow, carry, saturated_underflow, saturated_overflow, value)
if overflow then
if carry then
return saturated_underflow
else
return saturated_overflow
else
return value
Bit reverse
BITREVERSE(value)
result  0
mask 
shift 31
cnt 32
while cnt > 0 then do
t data & mask
if shift >= 0 then
result t << shift) | result
else
result t >> -shift) | result
cnt cnt - 1
shift shift - 2
mask mask << 1
return result
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7.3.2
Instruction set
Embedded floating-point conversion models
The embedded floating-point instructions defined by the signal processing engine (SPE)
APU and the single-precision floating-point (SPFP) APUs contain floating-point conversion
to and from integer and fractional type instructions. The floating-point to-and-from non–
floating-point conversion model pseudo RTL is provided here as a group of functions that is
called from the individual instruction pseudo RTL descriptions.
Table 199. Conversion models
Function
Name
Reference
Common functions
Round a 32-bit value
Round32(fp,guard,sticky)
on page 343
Round a 64-bit value
Round64(fp,guard,sticky)
on page 342
Signal floating-point error
SignalFPError
on page 342
Is a 32-bit value a NaN or Infinity?
Isa32NaNorInfinity(fp)
on page 341
Convert from single-precision
floating-point to integer word with
saturation
CnvtFP32ToI32Sat(fp,signed,upper_lower,rou
nd,fractional)
on page 343
Convert from double-precision
floating-point to integer word with
saturation
CnvtFP64ToI32Sat(fp,signed,round,fractional)
on page 345
Floating-point conversions
Convert from double-precision
floating-point to integer double word CnvtFP64ToI64Sat(fp,signed,round)
with saturation
on page 346
Convert to single-precision floatingpoint from integer word with
saturation
on page 348
CnvtI32ToFP32Sat(v,signed,upper_lower,fract
ional)
Convert to double-precision floatingpoint from integer double word with CnvtI64ToFP64Sat(v,signed)
saturation
on page 349
Integer Saturate
Integer saturate
SATURATE(ovf,carry,neg_sat,pos_sat,value)
on page 342
Common embedded floating-point functions
This section includes common functions used by the functions in subsequent sections.
32-Bit NaN or Infinity Test
// Determine if fp value is a NaN or Infinity
Isa32NaNorInfinity(fp)
return (fpexp = 255)
Isa32NaN(fp)
return ((fpexp = 255) & (fpfrac  0))
Isa32Infinity(fp)
return ((fpexp = 255) & (fpfrac = 0))
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// Determine if fp value is denormalized
Isa32Denorm(fp)
return ((fpexp = 0) & (fpfrac  0))
// Determine if fp value is a NaN or Infinity
Isa64NaNorInfinity(fp)
return (fpexp = 2047)
Isa64NaN(fp)
return ((fpexp = 2047) & (fpfrac  0))
Isa64Infinity(fp)
return ((fpexp = 2047) & (fpfrac = 0))
// Determine if fp value is denormalized
Isa64Denorm(fp)
return ((fpexp = 0) & (fpfrac  0))
Signal Floating-Point Error
// Signal a Floating-Point Error in the SPEFSCR
SignalFPError(upper_lower, bits)
if (upper_lower = UPPER) then
bits  bits << 15
SPEFSCR  SPEFSCR | bits
bits  (FG | FX)
if (upper_lower = UPPER) then
bits  bits << 15
SPEFSCR  SPEFSCR & bits
Round a 32-Bit Value
// Round a result
Round32(fp, guard, sticky)
FP32format fp;
if (SPEFSCRFINXE = 0) then
if (SPEFSCRFRMC = 0b00) then // nearest
if (guard) then
if (sticky | fpfrac[22]) then
v[0:23]  fpfrac + 1
if v[0] then
if (fpexp >= 254) then
// overflow
fp  fpsign || 0b11111110 || 231
else
fpexp  fpexp + 1
fpfrac  v1:23
else
fpfrac  v[1:23]
else if ((SPEFSCRFRMC & 0b10) = 0b10) then
// implementation dependent
return fp
Round a 64-Bit Value
// Round a result
Round64(fp, guard, sticky)
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// infinity modes
RM0004
Instruction set
FP32format fp;
if (SPEFSCRFINXE = 0) then
if (SPEFSCRFRMC = 0b00) then // nearest
if (guard) then
if (sticky | fpfrac[51]) then
v[0:52]  fpfrac + 1
if v[0] then
if (fpexp >= 2046) then
// overflow
fp  fpsign || 0b11111111110 || 521
else
fpexp  fpexp + 1
fpfrac  v1:52
else
fpfrac  v1:52
else if ((SPEFSCRFRMC & 0b10) = 0b10) then // infinity modes
// implementation dependent
return fp
Convert from single-precision floating-point to integer word
with saturation
// Convert 32-bit floating point to integer/factional
// signed = SIGN or UNSIGN
// upper_lower = UPPER or LOWER
// round = ROUND or TRUNC
// fractional = F (fractional) or I (integer)
CnvtFP32ToI32Sat(fp, signed, upper_lower, round, fractional)
FP32format fp;
if (Isa32NaNorInfinity(fp)) then // SNaN, QNaN, +-INF
SignalFPError(upper_lower, FINV)
if (Isa32NaN(fp)) then
return 0x00000000 // all NaNs
if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000
else
return 0x7fffffff
else
if (fpsign = 1) then
return 0x00000000
else
return 0xffffffff
if (Isa32Denorm(fp)) then
SignalFPError(upper_lower, FINV)
return 0x00000000 // regardless of sign
if ((signed = UNSIGN) & (fpsign = 1)) then
SignalFPError(upper_lower, FOVF) // overflow
return 0x00000000
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if ((fpexp = 0) & (fpfrac = 0)) then
return 0x00000000 // all zero values
if (fractional = I) then // convert to integer
max_exp  158
shift  158 - fpexp
if (signed = SIGN) then
if ((fpexp  158) | (fpfrac  0) | (fpsign  1)) then
max_exp  max_exp - 1
else
// fractional conversion
max_exp  126
shift  126 - fpexp
if (signed = SIGN) then
shift  shift + 1
if (fpexp > max_exp) then
SignalFPError(upper_lower, FOVF) // overflow
if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000
else
return 0x7fffffff
else
return 0xffffffff
result  0b1 || fpfrac || 0b00000000 // add U to frac
guard  0
sticky  0
for (n  0; n < shift; n  n + 1) do
sticky  sticky | guard
guard  result & 0x00000001
result  result > 1
// Report sticky and guard bits
if (upper_lower = UPPER) then
SPEFSCRFGH  guard
SPEFSCRFXH  sticky
else
SPEFSCRFG  guard
SPEFSCRFX  sticky

if (guard | sticky) then
SPEFSCRFINXS  1
// Round the integer result
if ((round = ROUND) & (SPEFSCRFINXE = 0)) then
if (SPEFSCRFRMC = 0b00) then // nearest
if (guard) then
if (sticky | (result & 0x00000001)) then
result  result + 1
else if ((SPEFSCRFRMC & 0b10) = 0b10) then // infinity modes
// implementation dependent
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if (signed = SIGN) then
if (fpsign = 1) then
result  result + 1
return result
Convert from double-precision floating-point to integer word
with saturation
// Convert 64-bit floating point to integer/fractional
// signed = SIGN or UNSIGN
// round = ROUND or TRUNC
// fractional = F (fractional) or I (integer)
CnvtFP64ToI32Sat(fp, signed, round, fractional)
FP64format fp;
if (Isa64NaNorInfinity(fp)) then // SNaN, QNaN, +-INF
SignalFPError(LOWER, FINV)
if (Isa64NaN(fp)) then
return 0x00000000 // all NaNs
if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000
else
return 0x7fffffff
else
if (fpsign = 1) then
return 0x00000000
else
return 0xffffffff
if (Isa64Denorm(fp)) then
SignalFPError(LOWER, FINV)
return 0x00000000 // regardless of sign
if ((signed = UNSIGN) & (fpsign = 1)) then
SignalFPError(LOWER, FOVF) // overflow
return 0x00000000
if ((fpexp = 0) & (fpfrac = 0)) then
return 0x00000000 // all zero values
if (fractional = I) then // convert to integer
max_exp  1054
shift  1054 - fpexp
if (signed  SIGN) then
if ((fpexp  1054) | (fpfrac  0) | (fpsign  1)) then
max_exp  max_exp - 1
else
// fractional conversion
max_exp  1022
shift  1022 - fpexp
if (signed = SIGN) then
shift  shift + 1
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if (fpexp > max_exp) then
SignalFPError(LOWER, FOVF) // overflow
if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000
else
return 0x7fffffff
else
return 0xffffffff
result  0b1 || fpfrac[0:30] // add U to frac
guard  fpfrac[31]
sticky  (fpfrac[32:63]  0)
for (n  0; n < shift; n  n + 1) do
sticky  sticky | guard
guard  result & 0x00000001
result  result > 1
// Report sticky and guard bits

SPEFSCRFG  guard
SPEFSCRFX  sticky

if (guard | sticky) then
SPEFSCRFINXS  1
// Round the result
if ((round = ROUND) & (SPEFSCRFINXE = 0)) then
if (SPEFSCRFRMC = 0b00) then // nearest
if (guard) then
if (sticky | (result & 0x00000001)) then
result  result + 1
else if ((SPEFSCRFRMC & 0b10) = 0b10) then // infinity modes
// implementation dependent
if (signed = SIGN) then
if (fpsign = 1) then
result  result + 1
return result
Convert from double-precision floating-point to integer double
word with saturation
// Convert 64-bit floating point to integer/fractional
// signed = SIGN or UNSIGN
// round = ROUND or TRUNC
CnvtFP64ToI64Sat(fp, signed, round)
FP64format fp;
if (Isa64NaNorInfinity(fp)) then // SNaN, QNaN, +-INF
SignalFPError(LOWER, FINV)
if (Isa64NaN(fp)) then
return 0x00000000_00000000 // all NaNs
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if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000_00000000
else
return 0x7fffffff_ffffffff
else
if (fpsign = 1) then
return 0x00000000_00000000
else
return 0xffffffff_ffffffff
if (Isa64Denorm(fp)) then
SignalFPError(LOWER, FINV)
return 0x00000000_00000000 // regardless of sign
if ((signed = UNSIGN) & (fpsign = 1)) then
SignalFPError(LOWER, FOVF) // overflow
return 0x00000000_00000000
if ((fpexp = 0) & (fpfrac = 0)) then
return 0x00000000_00000000
// all zero values
max_exp  1086
shift  1086 - fpexp
if (signed = SIGN) then
if ((fpexp  1086) | (fpfrac  0) | (fpsign  1)) then
max_exp  max_exp - 1
if (fpexp > max_exp) then
SignalFPError(LOWER, FOVF) // overflow
if (signed = SIGN) then
if (fpsign = 1) then
return 0x80000000_00000000
else
return 0x7fffffff_ffffffff
else
return 0xffffffff_ffffffff
result  0b1 || fpfrac || 0b00000000000 // add U to frac
guard  0
sticky  0
for (n  0; n < shift; n  n + 1) do
sticky  sticky | guard
guard  result & 0x00000000_00000001
result  result > 1
// Report sticky and guard bits

SPEFSCRFG  guard
SPEFSCRFX  sticky
if (guard | sticky) then
SPEFSCRFINXS  1
// Round the result
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if ((round = ROUND) & (SPEFSCRFINXE = 0)) then
if (SPEFSCRFRMC = 0b00) then // nearest
if (guard) then
if (sticky | (result & 0x00000000_00000001)) then
result  result + 1
else if ((SPEFSCRFRMC & 0b10) = 0b10) then // infinity modes
// implementation dependent
if (signed = SIGN) then
if (fpsign = 1) then
result  result + 1
return result
Convert to single-precision floating-point from integer word
with saturation
// Convert from integer/factional to 32-bit floating point
// signed = SIGN or UNSIGN
// upper_lower = UPPER or LOWER
// fractional = F (fractional) or I (integer)
CnvtI32ToFP32Sat(v, signed, upper_lower, fractional)
FP32format result;
resultsign  0
if (v = 0) then
result  0
if (upper_lower = UPPER) then
SPEFSCRFGH  0
SPEFSCRFXH  0
else
SPEFSCRFG  0
SPEFSCRFX  0
else
if (signed = SIGN) then
if (v0 = 1) then
v  v + 1
resultsign  1
if (fractional = F) then // fractional bit pos alignment
maxexp  127
if (signed = UNSIGN) then
maxexp  maxexp - 1
else
maxexp  158 // integer bit pos alignment
sc  0
while (v0 = 0)
v  v << 1
sc  sc + 1
v0  0 // clear U bit
resultexp  maxexp - sc
guard  v24
sticky  (v25:31  0)
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// Report sticky and guard bits
if (upper_lower = UPPER) then
SPEFSCRFGH  guard
SPEFSCRFXH  sticky
else
SPEFSCRFG  guard
SPEFSCRFX  sticky
if (guard | sticky) then
SPEFSCRFINXS  1
// Round the result

resultfrac  v1:23
result  Round32(result, guard, sticky)
return result
Convert to double-precision floating-point from integer word
with saturation
// Convert from integer/factional to 64-bit floating point
// signed = SIGN or UNSIGN
// fractional = F (fractional) or I (integer)
CnvtI32ToFP64Sat(v, signed, fractional)
FP64format result;
resultsign  0
if (v = 0) then
result  0
SPEFSCRFG  0
SPEFSCRFX  0
else
if (signed = SIGN) then
if (v[0] = 1) then
v  v + 1
resultsign  1
if (fractional = F) then // fractional bit pos alignment
maxexp  1023
if (signed = UNSIGN) then
maxexp  maxexp - 1
else
maxexp  1054 // integer bit pos alignment
sc  0
while (v0 = 0)
v  v << 1
sc  sc + 1
v0  0 // clear U bit
resultexp  maxexp - sc
// Report sticky and guard bits
SPEFSCRFG  0
SPEFSCRFX  0
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
resultfrac  v1:31 || 210
return result
Convert to double-precision floating-point from integer double
word with saturation
// Convert from 64 integer to 64-bit floating point
// signed = SIGN or UNSIGN
CnvtI64ToFP64Sat(v, signed)
FP64format result;
resultsign  0
if (v = 0) then
result  0
SPEFSCRFG  0
SPEFSCRFX  0
else
if (signed = SIGN) then
if (v0 = 1) then
v  v + 1
resultsign  1
maxexp  1054
sc  0
while (v0 = 0)
v  v << 1
sc  sc + 1
v0  0 // clear U bit
resultexp  maxexp - sc
guard  v53
sticky  (v54:63  0)
// Report sticky and guard bits
SPEFSCRFG  guard
SPEFSCRFX  sticky
if (guard | sticky) then
SPEFSCRFINXS  1
// Round the result

resultfrac  v1:52
result  Round64(result, guard, sticky)
return result
7.3.3
Integer saturation models
// Saturate after addition

SATURATE(ovf, carry, neg_sat, pos_sat, value)

if ovf then
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if carry then
return neg_sat
else
return pos_sat
else
return value
7.3.4
Embedded floating-point results
Appendix E: Embedded floating-point results , summarizes results of various types of SPE
and SPFP floating-point operations on various combinations of input operands.
7.4
Instruction set
The rest of this chapter describes individual instructions, which are listed in alphabetical
order by mnemonic. Figure 86 shows the format for instruction description pages.
Figure 86. Instruction description
Key:
User/Supervisor access
Architecture
Instruction mnemonic
Instruction name
Instruction syntax
Instruction encoding
add
Add
add
add.
addo
addo.
0
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
5 6
0 1 1 1 1 1
RTL description of
instruction operation
Text description of
instruction operation
Registers altered by
instruction
Note:
add
Book E User
10 11
rD
15 16
rA
(OE=0, Rc=0)
(OE=0, Rc=1)
(OE=1, Rc=0)
(OE=1, Rc=1)
20 21
rB
OE
30 31
1 0 0 0 0 1 0 1 0 Rc
carry0–63  Carry(rA + rB)
sum0–63

rA + rB
if OE=1 then do
OV
 carry32  carry33
SO
 SO | (carry32  carry33)
if Rc=1 then do
LT  sum32–63 < 0
GT  sum32–63 > 0
EQ  sum32–63 = 0
CR0  LT || GT || EQ || SO
rD  sum
The sum of the contents of rA and rB is placed into rD.
Other registers altered:
•
CR0 (if Rc=1)
SO OV (if OE=1)
The execution unit that executes the instruction may not be the same for all processors.
DocID13694 Rev 2
351/1025
666
Instruction set
RM0004
add
Book E
add
User
Add
add
rD,rA,rB
(OE=0, Rc=0)
add.
rD,rA,rB
(OE=0, Rc=1)
addo
rD,rA,rB
(OE=1, Rc=0)
addo.
rD,rA,rB
(OE=1, Rc=1)
0
5 6
0 1 1 1 1 1
10 11
rD
15 16
rA
20 21 22
rB
30 31
O
1 0 0 0 0 1 0 1 0 Rc
E
carry0:63  Carry(rA + rB)
sum0:63 
rA + rB
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
carry0:63  Carry(rA + rB)
sum0:63 
rA + rB
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
The sum of the contents of rA and rB is placed into rD.
Other registers altered:

CR0 (if Rc=1)
SO OV (if OE=1)
_addx
VLE
User
Add
se_add
352/1025
rX, rY
DocID13694 Rev 2
addx
RM0004
Instruction set
0
5
0
0
0
0
0
6
1
10
0 0
11
RY
15
RX
sum32:63  GPR(RX) + GPR(RY)
GPR(RX)  sum32:63
The sum of the contents of GPR(rX) and the contents of GPR(rY) is placed into GPR(rX).
Special Registers Altered: None
addc
Book E
addc
User
Add Carrying
add
rD,rA,rB
(OE=0, Rc=0)
add.
rD,rA,rB
(OE=0, Rc=1)
addo
rD,rA,rB
(OE=1, Rc=0)
addo.
rD,rA,rB
(OE=1, Rc=1)
0
5 6
0 1 1 1 1 1
10 11
rD
15 16
rA
20 21 22
rB
30 31
O
0 0 0 0 0 1 0 1 0 Rc
E
carry0:63  Carry(rA + rB)
sum0:63  rA + rB
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
CA
 carry32
The sum of the contents of rA and rB is placed into rD.
Other registers altered:

CA 
CR0 (if Rc=1)
SO OV (if OE=1)
DocID13694 Rev 2
353/1025
666
Instruction set
RM0004
adde
Book E
adde
User
Add Extended
adde
rD,rA,rB
(OE=0, Rc=0)
adde.
rD,rA,rB
(OE=0, Rc=1)
addeo
rD,rA,rB
(OE=1, Rc=0)
addeo.
rD,rA,rB
(OE=1, Rc=1)
0
5 6
0 1 1 1 1 1
10 11
rD
15 16
rA
20 21 22
rB
30 31
O
0 1 0 0 0 1 0 1 0 Rc
E
if E=0 then Cin  CA 
carry0:63  Carry(rA + rB + Cin)
sum0:63 
rA + rB + Cin
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
CA
 carry32
For adde[o][.], the sum of the contents of rA, the contents of rB, and CA is placed into rD.
Other registers altered:

354/1025
CA 
CR0 (if Rc=1)
SO OV (if OE=1)
DocID13694 Rev 2
RM0004
Instruction set
addi
Book E
addi
User
Add immediate [shifted]
addi
rD,rA,SIMM
(S=0)
addis
rD,rA,SIMM
(S=1)
0
4 5 6
10 11
0 0 1 1 1 S
rD
15 16
31
rA
SIMM
if rA=0 then a  640 else a  rA
if s=0 then b  EXTS(SIMM)
if s=1 then b  EXTS(SIMM || 160)
rD  a + b
If addi and rA=0, the sign-extended value of the SIMM field is placed into rD.
If addi and rA0, the sum of the contents of rA and the sign-extended value of field SIMM is
placed into rD.
If addis and rA=0, the sign-extended value of the SIMM field, concatenated with 16 zeros,
is placed into rD.
If addis and rA0, the sum of the contents of rA and the sign-extended value of the SIMM
field concatenated with 16 zeros, is placed into rD.
Other registers altered: None
_addix
VLE
_addix
User
Add [2 operand] Immediate [Shifted][and Record]
e_add16i
rD,rA,SI
0
0
5
0
0
1
1
6
10 11
1
RD
15 16
31
RA
SI
a  GPR(RA)
b  EXTS(SI)
GPR(RD)  a + b
The sum of the contents of GPR(rA) and the sign-extended value of field SI is placed into
GPR(rD).
Special Registers Altered: None
e_add2i
rA,SI
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
SI0:4
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RA
1
DocID13694 Rev 2
0
0
0
1
SI5:15
355/1025
666
Instruction set
RM0004
SI  SI0:4 || SI5:15
sum32:63 
GPR(RA) + EXTS(SI)
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
GPR(RA)  sum32:63
The sum of the contents of GPR(rA) and the sign-extended value of SI is placed into
GPR(rA).
Special Registers Altered: CR0
e_add2is
rA,SI
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI0:4
RA
1
0
0
1
SI5:15
0
SI  SI0:4 || SI5:15 
sum32:63  GPR(RD) + (SI || 160)
GPR(RA)  sum32:63
The sum of the contents of GPR(rA) and the value of SI concatenated with 16 zeros is
placed into GPR(rAarav2006).
Special Registers Altered: None
e_addi
rD,rA,SCI8
(Rc=0)
e_addi.
rD,rA,SCI8
(Rc=1)
0
1
2
3
4
5
0
0
0
1
1
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RD
RA
1
0
0
0 Rc F
SCL
UI8
imm  SCI8(F,SCL,UI8)
sum32:63 
GPR(RA) + imm
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
GPR(RD)  sum32:63
The sum of the contents of GPR(rA) and the value of SCI8 is placed into GPR(rD).
Special Registers Altered: CR0 (if Rc = 1)
se_addi
rX,OIMM
0
1
2
3
4
5
6
0
0
1
0
0
0
0
7
1. OIMM = OIM5 +1.
356/1025
DocID13694 Rev 2
8
9
OIM5(1)
10
11
12
13
14
RX
15
RM0004
Instruction set
GPR(RX)  GPR(RX) + (270 || OFFSET(OIM5))
The sum of the contents of GPR(rX) and the zero-extended offset value of OIM5 (a final
value in the range 1–32), is placed into GPR(rX).
Special Registers Altered: None
addic
Book E
addic
User
Add immediate carrying [and record]
addic
rD,rA,SIMM
(Rc=0)
addic.
rD,rA,SIMM
(Rc=1)
0
1
2
3
4
5
6
7
0 0 1 1 0 Rc
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
SIMM
carry0:63  Carry(rA + EXTS(SIMM))
sum0:63 
rA + EXTS(SIMM)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  rA+EXTS(SIMM)
CA
 carry32
The sum of the contents of rA and the sign-extended value of the SIMM field is placed into
rD.
Other registers altered:

CA 
CR0 (if Rc=1)
_addicx
VLE
_addicx
User
Add immediate Carrying [and record]
e_addic
rD,rA,SCI8
(Rc=0)
e_addic.
rD,rA,SCI8
(Rc=1)
0
1
2
3
4
5
0
0
0
1
1
0
6
7
8
RD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RA
1
0
0
1 Rc F
SCL
UI8
imm  SCI8(F,SCL,UI8)
carry32:63  Carry(GPR(RA) + imm)
sum32:63 
GPR(RA) + imm
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
DocID13694 Rev 2
357/1025
666
Instruction set
RM0004
GPR(RD)  sum32:63
CA
 carry32
The sum of the contents of GPR(rA) and the value of SCI8 is placed into GPR(rD).
Special Registers Altered: CA, CR0 (if Rc=1)
addme
Book E
addme
User
Add to minus one extended
addme
rD,rA
(OE=0, Rc=0)
addme.
rD,rA
(OE=0, Rc=1)
addmeo
rD,rA
(OE=1, Rc=0)
addmeo.
rD,rA
(OE=1, Rc=1)
0
1
2
3
4
5
6
7
0 1 1 1 1 1
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
///
O
0 1 1 1 0 1 0 1 0 Rc
E
if E=0 then Cin  CA 
carry0:63  Carry(rA + Cin + 0xFFFF_FFFF_FFFF_FFFF)
sum0:63 
rA + Cin + 0xFFFF_FFFF_FFFF_FFFF
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
CA
 carry32
For addme[o][.], the sum of the contents of rA, CA, and 641 is placed into rD.
Other registers altered:

358/1025
CA 
CR0 (if Rc=1)
SO OV (if OE=1)
DocID13694 Rev 2
RM0004
Instruction set
addze
Book E
addze
User
Add to zero extended
addze
rD,rA
(OE=0, Rc=0)
addze.
rD,rA
(OE=0, Rc=1)
addzeo
rD,rA
(OE=1, Rc=0)
addzeo.
rD,rA
(OE=1, Rc=1)
0
1
2
3
4
5
6
7
0 1 1 1 1 1
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
///
O
0 1 1 0 0 1 0 1 0 Rc
E
if E=0 then Cin  CA 
carry0:63  Carry(rA + Cin)
sum0:63 
rA + Cin
if OE=1 then do
OV  carry32  carry33
SO  SO | (carry32  carry33)
if Rc=1 then do
LT  sum32:63 < 0
GT  sum32:63 > 0
EQ  sum32:63 = 0
CR0  LT || GT || EQ || SO
rD  sum
CA
 carry32
For addze[o][.], the sum of the contents of rA and CA is placed into rD.
Other registers altered:

CA 
CR0 (if Rc=1)
SO OV (if OE=1)
and
Book E
and
User
AND [Immediate [Shifted] | with Complement]
and
rA,rS,rB
(Rc=0)
and.
rA,rS,rB
(Rc=1)
0
1
2
3
4
5
0 1 1 1 1 1
6
7
8
rS
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
DocID13694 Rev 2
rB
0 0 0 0 0 1 1 1 0 0 Rc
359/1025
666
Instruction set
RM0004
andi
rA,rS,UIMM
(S=0, Rc=1)
andis.
rA,rS,UIMM
(S=1, Rc=1)
0
1
2
3
4
5
6
7
0 1 1 1 0 S
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rS
rA
UIMM
andc
rA,rS,rB
(Rc=0)
andc.
rA,rS,rB
(Rc=1)
0
1
2
3
4
5
6
7
0 1 1 1 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rS
rA
rB
0 0 0 0 1 1 1 1 0 0 Rc
if ‘andi.’ then b  480 || UIMM
if ‘andis.’ then b  320 || UIMM || 160
if ‘and[.]’ then b  rB
if ‘andc[.]’ then b  rB
result0:63  rS & b
if Rc=1 then do
LT  result32:63 < 0
GT  result32:63 > 0
EQ  result32:63 = 0
CR0  LT || GT || EQ || SO
rA  result
For andi., the contents of rS are ANDed with 480 || UIMM.
For andis., the contents of rS are ANDed with 320 || UIMM || 160.
For and[.], the contents of rS are ANDed with the contents of rB.
For andc[.], the contents of rS are ANDed with the one’s complement of the contents of rB.
The result is placed into rA.
Other registers altered: CR0 (if Rc=1)
_andx
VLE
_andx
User
AND [2 operand] [Immediate | with Complement] [and Record]
se_and
rX,rY
(Rc=0)
se_and.
rX,rY
(Rc=1)
0
1
2
3
4
5
6
7
0
1
0
0
0
1
1
Rc
e_and2i
360/1025
rD,U
DocID13694 Rev 2
8
9
10
RY
11
12
13
14
RX
15
RM0004
Instruction set
I
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UI0:4
RD
e_and2is
1
1
0
0
UI5:15
1
rD,U
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UI0:4
RD
1
1
1
0
UI5:15
1
e_andi
rA,rS,SCI8
(Rc=0)
e_andi.
rA,rS,SCI8
(Rc=1)
0
1
2
3
4
5
0
0
0
1
1
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RS
e_andi
0
1
0
1
se_andc
1
0
0 Rc F
SCL
UI8
1
5
6
1
1
7
11
12
UI5
15
RX
rX,rY
0
0
1
rX,UI5
0
0
RA
0
0
0
5
6
7
1
0
1
8
11
12
RY
15
RX
if ‘e_andi[.]’ then b  SCI8(F,SCL,UI8)
if ‘se_andi’ then b  UI5
if ‘se_and[.]’ then b  GPR(RY)
if ‘se_andc’ then b  GPR(RY)
if ‘e_and2i.’ then b  160 || UI0:4 || UI5:15
if ‘e_and2is.’ then b  UI0:4 || UI5:15 || 160
result32:63  GPR(RS or RD or RX) & b
if Rc=1 then do
LT  result32:63 < 0
GT  result32:63 > 0
EQ  result32:63 = 0
CR0  LT || GT || EQ || SO
if ‘se_and[ci]’ then GPR(RX)  result32:63 else GPR(RA or RD)  result32:63
For e_andi[.], the contents of GPR(rS) are ANDed with the value of SCI8.
For e_and2i., the contents of GPR(rD) are ANDed with 160 || UI.
For e_and2is., the contents of GPR(rD) are ANDed with UI || 160.
For se_andi, the contents of GPR(rX) are ANDed with the value of UI5.
For se_and[.], the contents of GPR(rX) are ANDed with the contents of GPR(rY).
For se_andc, the contents of GPR(rX) are ANDed with the one’s complement of the
contents of GPR(rY).
DocID13694 Rev 2
361/1025
666
Instruction set
RM0004
The result is placed into GPR(rA) or GPR(rX) (se_and[ic][.])
Special Registers Altered: CR0 (if Rc = 1)
b
Book E
b
User
Branch [and Link] [Absolute]
b
LI
(AA=0, LK=0)
ba
LI
(AA=1, LK=0)
bl
LI
(AA=0, LK=1)
bla
LI
(AA=1, LK=1)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 1 0 0 1 0
LI
AA LK
if AA=1 then a  640 else a  CIA
if E=0 then NIA  320 || (a + EXTS(LI||0b00))32:63
if LK=1 then LR  CIA + 4
The branch target effective address (BTEA) is calculated as follows:

For 32-bit implementations, BTEA is bits 32–63 of the sum of the current instruction
address (CIA), or 32 zeros if AA=1, and the sign-extended value of the LI instruction
field concatenated with 0b00
BTEA is the address of the next instruction to be executed.
If LK=1, the sum CIA+4 is placed into the LR.
Other registers altered: LR (if LK=1)
_bx
VLE
_bx
User
Branch [and Link]
e_b
BD24
(LK=0)
e_bx
BD24
(LK=1)
0
1
2
3
4
5
6
0
1
1
1
1
0
0
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BD24
a  CIA
NIA  (a + EXTS(BD24||0b0))32:63
if LK=1 then LR  CIA + 4
Let the BTEA be calculated as follows:

362/1025
For e_b[l], let BTEA be the sum of the CIA and the sign-extended value of the BD24
instruction field concatenated with 0b0.
DocID13694 Rev 2
LK
RM0004
Instruction set
The BTEA is the address of the next instruction to be executed.
If LK = 1, the sum CIA+4 is placed into the LR.
Special Registers Altered: LR (if LK = 1)
se_b
BD8
(LK=0)
se_bl
BD8
(LK=1)
0
1
2
3
4
5
6
7
1
1
1
0
1
0
0
LK
8
9
10
11
12
13
14
15
BD8
a  CIA
NIA  (a + EXTS(BD8||0b0))32:63
if LK=1 then LR  CIA + 2
Let the BTEA be calculated as follows:

For se_b[l], let BTEA be the sum of the CIA and the sign-extended value of the BD8
instruction field concatenated with 0b0.
The BTEA is the address of the next instruction to be executed.
If LK = 1, the sum CIA+2 is placed into the LR.
Special Registers Altered: LR (if LK = 1)
bc
Book E
bc
User
Branch conditional [and link] [absolute]
bc
BO,BI,BD
(AA=0, LK=0)
bca
BO,BI,BD
(AA=1, LK=0)
bcl
BO,BI,BD
(AA=0, LK=1)
bcla
BO,BI,BD
(AA=1, LK=1)
0
1
2
3
4
5
0 1 0 0 0 0
6
7
8
BO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BI
BD
AA LK
if BO2 then CTR32:63  CTR32:63 : 1
ctr_ok  BO2 | ((CTR32:63  0)  BO3)
cond_ok  BO0 | (CRBI+32  BO1)
if ctr_ok & cond_ok then
if AA=1 then a  640 else a  CIA
if E=0 then NIA  320 || (a + EXTS(BD||0b00))32:63
else
NIA  CIA + 4
if LK=1 then LR  CIA + 4
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Instruction set
RM0004
The branch target effective address (BTEA) is calculated as follows:

For 32-bit implementations, BTEA is bits 32–63 of the sum of the current instruction
address (CIA), or 32 zeros if AA=1, and the sign-extended value of the LI instruction
field concatenated with 0b00
The BO instruction field specifies any conditions that must be met for the branch to be
taken, as defined in Section 4.3.1.12: Conditional branch control. The sum BI+32 specifies
the CR bit to be used.
The BI field specifies the CR bit used as the condition of the branch, as shown in Table 200.
Table 200. BI operand settings for CR fields
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CRn Bits
CR Bits
BI
Description
CR0[0]
32
00000 Negative (LT)—Set when the result is negative.
CR0[1]
33
00001 Positive (GT)—Set when the result is positive (and not zero).
CR0[2]
34
00010 Zero (EQ)—Set when the result is zero.
CR0[3]
35
00011
CR1[0]
36
00100 Copy of FPSCR[FX] at the instruction’s completion.
CR1[1]
37
00101 Copy of FPSCR[FEX] at the instruction’s completion.
CR1[2]
38
00110 Copy of FPSCR[VX] at the instruction’s completion.
CR1[3]
39
00111 Copy of FPSCR[OX] at the instruction’s completion.
CRn[0]
40
44
48
52
56
60
01000
01100
10000
10100
11000
11100
Less than or floating-point less than (LT, FL).
For integer compare instructions:
rA < SIMM or rB (signed comparison) or rA < UIMM or rB (unsigned
comparison).
For floating-point compare instructions:frA < frB.
CRn[1]
41
45
49
53
57
61
01001
01101
10001
10101
11001
11101
Greater than or floating-point greater than (GT, FG).
For integer compare instructions:
rA > SIMM or rB (signed comparison) or rA > UIMM or rB (unsigned
comparison).
For floating-point compare instructions:frA > frB.
CRn[2]
42
46
50
54
58
62
01010
01110
Equal or floating-point equal (EQ, FE).
10010
For integer compare instructions: rA = SIMM, UIMM, or rB.
10110
For floating-point compare instructions: frA = frB.
11010
11110
CRn[3]
43
47
51
55
59
63
01011
01111
10011
10111
11011
11111
Summary overflow (SO). Copy of XER[SO] at the instruction’s
completion.
Summary overflow or floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of XER[SO] at the
completion of the instruction.
For floating-point compare instructions, one or both of frA and frB is a
NaN.
DocID13694 Rev 2
RM0004
Instruction set
If the branch conditions are met, the BTEA is the address of the next instruction to be
executed.
If LK=1, the sum CIA + 4 is placed into the LR.
Other registers altered:

CTR(if BO2=0) 
LR(if LK=1)
_bcx
VLE
_bcx
User
Branch Conditional [and Link]
e_bc
BO32,BI32,BD15
(LK=0)
e_bcl
BO32,BI32,BD15
(LK=1)
0
1
2
3
4
5
0
1
1
1
1
0
6
7
8
1 0 0 0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BO32
BI32
BD15
LK
if BO320 then CTR32:63  CTR32:63 – 1
ctr_ok  BO320 | ((CTR32:63  0)  BO321)
cond_ok  BO320 | (CRBI32+32  BO321)
if ctr_ok & cond_ok then
NIA  (CIA + EXTS(BD15 || 0b0))32:63
else
NIA  CIA + 4
if LK=1 then LR  CIA + 4
Let the BTEA be calculated as follows:

For e_bc[l], let BTEA be the sum of the CIA and the sign-extended value of the BD15
instruction field concatenated with 0b0.
BO32 specifies any conditions that must be met for the branch to be taken, as defined in
Section 13.2.2: Branch instructions. The sum BI32+32 specifies the CR bit. Only CR[32–47]
may be specified.
If the branch conditions are met, the BTEA is the address of the next instruction to be
executed.
If LK = 1, the sum CIA + 4 is placed into the LR.
Special Registers Altered: CTR (if BO320 = 1) 
LR (if LK = 1)
se_bc
BO16,BI16,BD8
0
1
1
1
0
4
5
0
BO16
6
7
8
BI16
15
BD8
cond_ok  (CRBI16+32  BO16)
if cond_ok then
NIA  (CIA + EXTS(BD8 || 0b0))32:63
else
NIA  CIA + 2
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Instruction set
RM0004
Let the BTEA be calculated as follows:

For se_bc, BTEA is the sum of the CIA and the sign-extended value of the BD8
instruction field concatenated with 0b0.
BO16 specifies any conditions that must be met for the branch to be taken, as defined in
Section 13.2.2: Branch instructions. The sum BI16+32 specifies CR bit; only CR[32–35]
may be specified.
If the branch conditions are met, the BTEA is the address of the next instruction to be
executed.
Special Registers Altered: None
bcctr
Book E
bcctr
User
Branch conditional to count register [and link]
bcctr
BO,BI
(LK=0)
bcctrl
BO,BI
(LK=1)
0
1
2
3
4
5
6
0 1 0 0 1 1
7
8
BO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BI
///
1 0 0 0 0 1 0 0 0 0 LK
cond_ok  BO0 | (CRBI+32  BO1)
if cond_ok & E=0 then NIA  320 || CTR32:61 || 0b00
if cond_ok
then NIA  CIA + 4
if LK=1 then LR  CIA + 4
The branch target effective address (BTEA) is calculated as follows:

For bcctr[l], BTEA is the contents of CTR[32–61] concatenated with 0b00.
BO specifies conditions that must be met for the branch to be taken. BI+32 specifies the CR
bit to be used; see Table 201.
Table 201. BI operand settings for CR fields
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CRn Bits
CR Bits
BI
Description
CR0[0]
32
00000 Negative (LT)—Set when the result is negative.
CR0[1]
33
00001 Positive (GT)—Set when the result is positive (and not zero).
CR0[2]
34
00010 Zero (EQ)—Set when the result is zero.
CR0[3]
35
00011
CR1[0]
36
00100 Copy of FPSCR[FX] at the instruction’s completion.
CR1[1]
37
00101 Copy of FPSCR[FEX] at the instruction’s completion.
CR1[2]
38
00110 Copy of FPSCR[VX] at the instruction’s completion.
CR1[3]
39
00111 Copy of FPSCR[OX] at the instruction’s completion.
Summary overflow (SO). Copy of XER[SO] at the instruction’s
completion.
DocID13694 Rev 2
RM0004
Instruction set
Table 201. BI operand settings for CR fields (continued)
CRn Bits
CR Bits
BI
Description
CRn[0]
40
44
48
52
56
60
01000
01100
10000
10100
11000
11100
Less than or floating-point less than (LT, FL).
For integer compare instructions:
rA < SIMM or rB (signed comparison) or rA < UIMM or rB (unsigned
comparison).
For floating-point compare instructions:frA < frB.
CRn[1]
41
45
49
53
57
61
01001
01101
10001
10101
11001
11101
Greater than or floating-point greater than (GT, FG).
For integer compare instructions:
rA > SIMM or rB (signed comparison) or rA > UIMM or rB (unsigned
comparison).
For floating-point compare instructions: frA > frB.
CRn[2]
42
46
50
54
58
62
01010
01110
Equal or floating-point equal (EQ, FE).
10010
For integer compare instructions: rA = SIMM, UIMM, or rB.
10110
For floating-point compare instructions: frA = frB.
11010
11110
CRn[3]
43
47
51
55
59
63
01011
01111
10011
10111
11011
11111
Summary overflow or floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of XER[SO] at the
completion of the instruction.
For floating-point compare instructions, one or both of frA and frB is a
NaN.
If the condition is met, the BTEA is the address of the next instruction to be executed.
If LK=1, the sum CIA + 4 is placed into the LR.
If the decrement and test CTR option is specified (BO[2]=0), the instruction form is invalid.
Other registers altered: LR (if LK=1)
bclr
Book E
bclr
User
Branch conditional to link register [and link]
bclr
BO,BI
(LK=0)
bclrl
BO,BI
(LK=1)
0
1
2
3
4
5
0 1 0 0 1 1
6
7
8
BO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
BI
///
0 0 0 0 0 1 0 0 0 0 LK
if BO2 then CTR32:63  CTR32:63 - 1
ctr_ok  BO2 | ((CTR32:63  0)  BO3)
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Instruction set
RM0004
cond_ok  BO0 | (CRBI+32  BO1)
if ctr_ok & cond_ok & E=0 then NIA  320 || LR32:61 || 0b00
if (ctr_ok & cond_ok)
then NIA  CIA + 4
if LK=1 then LR  CIA + 4
The branch target effective address (BTEA) is calculated as follows:

For bclr[l], BTEA is the contents of LR[32–61] concatenated with 0b00.
The BO field specifies any conditions that must be met for the branch to be taken, as
defined in Section 4.3.1.12: Conditional branch control. The sum BI+32 specifies the CR bit
to be used.
The BI field specifies the CR bit used as the condition of the branch, as shown in Table 202.
Table 202. BI operand settings for CR fields
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CRn Bits
CR Bits
BI
Description
CR0[0]
32
00000 Negative (LT)—Set when the result is negative.
CR0[1]
33
00001 Positive (GT)—Set when the result is positive (and not zero).
CR0[2]
34
00010 Zero (EQ)—Set when the result is zero.
CR0[3]
35
00011
CR1[0]
36
00100 Copy of FPSCR[FX] at the instruction’s completion.
CR1[1]
37
00101 Copy of FPSCR[FEX] at the instruction’s completion.
CR1[2]
38
00110 Copy of FPSCR[VX] at the instruction’s completion.
CR1[3]
39
00111 Copy of FPSCR[OX] at the instruction’s completion.
CRn[0]
40
44
48
52
56
60
01000
01100
10000
10100
11000
11100
Less than or floating-point less than (LT, FL).
For integer compare instructions:
rA < SIMM or rB (signed comparison) or rA < UIMM or rB (unsigned
comparison).
For floating-point compare instructions: frA < frB.
CRn[1]
41
45
49
53
57
61
01001
01101
10001
10101
11001
11101
Greater than or floating-point greater than (GT, FG).
For integer compare instructions:
rA > SIMM or rB (signed comparison) or rA > UIMM or rB (unsigned
comparison).
For floating-point compare instructions: frA > frB.
CRn[2]
42
46
50
54
58
62
01010
01110
Equal or floating-point equal (EQ, FE).
10010
For integer compare instructions: rA = SIMM, UIMM, or rB.
10110
For floating-point compare instructions: frA = frB.
11010
11110
Summary overflow (SO). Copy of XER[SO] at the instruction’s
completion.
DocID13694 Rev 2
RM0004
Instruction set
Table 202. BI operand settings for CR fields (continued)
CRn Bits
CR Bits
BI
Description
CRn[3]
43
47
51
55
59
63
01011
01111
10011
10111
11011
11111
Summary overflow or floating-point unordered (SO, FU).
For integer compare instructions, this is a copy of XER[SO] at the
completion of the instruction.
For floating-point compare instructions, one or both of frA and frB is a
NaN.
If the condition is met, the BTEA is the address of the next instruction to be executed.
If LK=1, the sum CIA + 4 is placed into the LR.
Other registers altered:

CTR (if BO2=0) 
LR (if LK=1)
_bclri
VLE
_bclri
User
Bit Clear Immediate
se_bclri
rX,UI5
0
0
1
1
0
0
5
6
0
0
7
11
12
15
UI5
RX
a  UI5
b  a1 || 0 || 31-a1
result32:63  GPR(RX) & b
GPR(RX)  result32:63
For se_bclri, the bit of GPR(rX) specified by the value of UI5 is cleared and all other bits in
GPR(rX) remain unaffected.
Special Registers Altered: None
_bctrx
VLE
_bctrx
User
Branch to Count Register [and Link]
se_bctr
se_bctrl
(LK = 0)
(LK = 1)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
14
15
1
LK
NIA  CTR32:62 || 0b0
if LK=1 then LR  CIA + 2
Let the BTEA be calculated as follows:

For se_bctr[l], let BTEA be bits 32–62 of the contents of the CTR concatenated with
0b0.
The BTEA is the address of the next instruction to be executed.
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Instruction set
RM0004
If LK = 1, the sum CIA + 2 is placed into the LR.
Special Registers Altered: LR (if LK = 1)
_bgeni
VLE
_bgeni
User
Bit Generate Immediate
se_bgeni
rX,UI5
0
1
2
3
4
5
6
0
1
1
0
0
0
1
7
8
9
10
11
12
13
UI5
14
15
RX
a  UI5
b  a0 || 1 || 31-a0
GPR(RX)  b
For se_bgeni, a constant value consisting of a single ‘1’ bit surrounded by ‘0’s is generated
and the value is placed into GPR(rX). The position of the ‘1’ bit is specified by the UI5 field.
Special Registers Altered: None
_blrx
VLE
_blrx
User
Branch to Link Register [and Link]
se_blr
se_blrl
(LK = 0)
(LK = 1)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
LK
NIA  LR32:62 || 0b0
if LK=1 then LR  CIA + 2
Let the BTEA be calculated as follows:

For se_blr[l], let BTEA be bits 32–62 of the contents of the LR concatenated with 0b0.
The BTEA is the address of the next instruction to be executed.
If LK = 1, the sum CIA + 2 is placed into the LR.
Special Registers Altered: LR (if LK = 1)
_bmaski
VLE
_bmaski
User
Bit Mask Generate Immediate
se_bmaski
rX,UI5
0
1
2
3
4
5
6
0
0
1
0
1
1
0
a  UI5
if a = 0 then b  321 else
GPR(RX)  b
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8
b  32-a0 || a1
DocID13694 Rev 2
9
UI5
10
11
12
13
14
RX
15
RM0004
Instruction set
For se_bmaski, a constant value consisting of a mask of low-order ’1’ bits that is zeroextended to 32 bits is generated, and the value is placed into GPR(rX). The number of loworder ’1’ bits is specified by the UI5 field. If UI5 is 0b00000, a value of all ’1’s is generated
Special Registers Altered: None
brinc
SPE APU
brinc
User
Bit reversed increment
brinc
0
rD,rA,rB
1
2
3
4
5
6
0 0 0 1 0 0
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0 1 0 0 0 0 0 1 1 1 1
n  MASKBITS
mask  rB64-n:63
register
a  rA64-n:63
d  bitreverse(1 + bitreverse(a | (mask)))
rD  rA0:63-n || (d & mask)
// Imp dependent # of mask bits
// Least sig. n bits of
brinc provides a way for software to access FFT data in a bit-reversed manner. rA contains
the index into a buffer that contains data on which FFT is to be performed. rB contains a
mask that allows the index to be updated with bit-reversed addressing. Typically this
instruction precedes a load with index instruction; for example,
brinc r2, r3, r4
lhax r8, r5, r2
rB contains a bit-mask that is based on the number of points in an FFT. To access a buffer
containing n byte sized data that is to be accessed with bit-reversed addressing, the mask
has log2n 1s in the least significant bit positions and 0s in the remaining most significant bit
positions. If, however, the data size is a multiple of a half word or a word, the mask is
constructed so that the 1s are shifted left by log2 (size of the data) and 0s are placed in the
least significant bit positions. Table 203 shows example values of masks for different data
sizes and number of data.
Table 203. Data samples and sizes
Number of
data
samples
Data size
Byte
Half word
Word
Double word
8
000...00000111
000...00001110
000...000011100
000...0000111000
16
000...00001111
000...00011110
000...000111100
000...0001111000
32
000...00011111
000...00111110
000...001111100
000...0011111000
64
000...00111111
000...01111110
000...011111100
000...0111111000
_bseti
VLE
User
_bseti
Bit Set Immediate
se_bseti
rX,UI5
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Instruction set
RM0004
0
1
2
3
4
5
6
0
1
1
0
0
1
0
7
8
9
10
11
12
13
UI5
14
15
RX
a  UI5
b  a0 || 1 || 31-a0
result32:63  GPR(RX) | b
GPR(RX)  result32:63
For se_bseti, the bit of GPR(rX) specified by the value of UI5 is set, and all other bits in
GPR(rX) remain unaffected.
Special Registers Altered: None
_btsti
VLE
_btsti
User
Bit Test Immediate
se_btsti
rX,UI5
0
1
2
3
4
5
6
0
1
1
0
0
1
1
7
8
9
10
11
12
UI5
13
14
15
RX
a  UI5
b  a0 || 1 || 31-a0
c  GPR(RX) & b
if c = 320 then d  0b001 else d  0b010
CR0:3  d || XERSO
For se_btsti, the bit of GPR(rX) specified by the value of UI5 is tested for equality to ’1’. The
result of the test is recorded in the CR. EQ is set if the tested bit is clear, LT is cleared, and
GT is set to the inverse value of EQ.
Special Registers Altered: CR[0–3]
cmp
Book E
cmp
User
Compare [immediate]
cmp
0
1
crD,L,rA,rB
2
3
4
5
6
0 1 1 1 1 1
7
8
crD
/ L
cmpi
0
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
0 0 0 0 0 0 0 0 0 0 /
crD,L,rA,SIMM
2
3
4
5
0 0 1 0 1 1
6
7
crD
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
/ L
rA
if L=0 then a  EXTS(rA32:63)
else
a  rA
if ‘cmpi’
then b  EXTS(SIMM)
if ‘cmp’ & L=0 then b  EXTS(rB32:63)
if ‘cmp’ & L=1 then b  rB
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DocID13694 Rev 2
SIMM
RM0004
Instruction set
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR4crD+32:4crD+35  c || XERSO
If cmp and L=0, the contents of rA[32–63] are compared with the contents of rB[32–63],
treating the operands as signed integers.
If cmpi and L=0, the contents of rA[32–63] are compared with the sign-extended value of
the SIMM field, treating the operands as signed integers.
The result of the comparison is placed into CR field crD.
Other registers altered: CR field crD
_cmp
VLE
cmp
User
Compare [Immediate]
e_cmp16i
rA,SI
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI0:4
RA
e_cmpi
1
0
0
1
SI5:15
1
crD32,rA,SCI8
0
1
2
3
4
5
6
7
8
0
0
0
1
1
0
0
0
0 CRD32
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RA
1
0
1
0
1
F
SCL
UI8
a  GPR(RA)32:63
if ‘e_cmpi’ then b  SCI8(F,SCL,UI8)
if ‘e_cmp16i’ then b  EXTS(SI0:4 || SI5:15)
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
if ‘e_cmpi’ then CR4CRD32+32:4CRD32+35  c || XERSO // only CR0-CR3
if ‘e_cmp16i’ then CR32:35  c || XERSO // only CR0
If e_cmpi, GPR(rA) contents are compared with the value of SCI8, treating operands as
signed integers.
If e_cmp16i, GPR(rA) contents are compared with the sign-extended value of the SI field,
treating operands as signed integers.
The result of the comparison is placed into CR field crD (crD32). For e_cmpi, only CR0–
CR3 may be specified. For e_cmp16i, only CR0 may be specified.
Special Registers Altered: CR field crD (crD32) (CR0 for e_cmp16i)
se_cmp
rX,rY
0
1
2
3
4
5
6
7
0
0
0
0
1
1
0
0
7
se_cmpi
8
9
10
11
12
13
RY
14
15
14
15
RX
rX,UI5
0
1
2
3
4
5
6
0
0
1
0
1
0
1
DocID13694 Rev 2
8
9
UI5
10
11
12
13
RX
373/1025
666
Instruction set
RM0004
a  GPR(RX)32:63
if ‘se_cmpi’ then b  270 || UI5
if ‘se_cmp’ then b  GPR(RY)32:63
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR0:3  c || XERSO
If se_cmp, the contents of GPR(rX) are compared with the contents of GPR(rY), treating
the operands as signed integers. The result of the comparison is placed into CR field 0.
If se_cmpi, the contents of GPR(rX) are compared with the value of the zero-extended UI5
field, treating the operands as signed integers. The result of the comparison is placed into
CR field 0.
Special Registers Altered: CR[0–3]
_cmph
VLE
_cmph
User
Compare Halfword [Immediate]
e_cmph
crD,rA,rB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRD
/
RA
RB
0
0
0
0
0
0
1
1
1
0
/
a  EXTS(GPR(RA)48:63)
b  EXTS(GPR(RB)48:63)
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR4CRD+32:4CRD+35  c || XERSO
For e_cmph, the contents of the low-order 16 bits of GPR(rA) and GPR(rB) are compared,
treating the operands as signed integers. The result of the comparison is placed into CR
field CRD.
Special Registers Altered: CR field CRD
se_cmph
rX,rY
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
0
8
9
10
RY
11
12
13
14
15
RX
a  EXTS(GPR(RX)48:63)
b  EXTS(GPR(RY)48:63)
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR0:3  c || XERSO
For se_cmph, the contents of the low-order 16 bits of GPR(rX) and GPR(rY) are compared,
treating the operands as signed integers. The result of the comparison is placed into CR
field 0.
Special Registers Altered: CR[0–3]
e_cmph16i
374/1025
rA,SI
DocID13694 Rev 2
RM0004
Instruction set
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SI0:4
RA
1
0
1
1
SI5:15
0
a  EXTS(GPR(RA)48:63)
b  EXTS(SI0:4 || SI5:15)
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR32:35  c || XERSO // only CR0
The contents of the lower 16-bits of GPR(rA) are sign-extended and compared with the
sign-extended value of the SI field, treating the operands as signed integers.
The result of the comparison is placed into CR0.
Special Registers Altered: CR0
_cmphl
_cmphl _cmphl _cmphl _cmphl
VLE
_cmphl
User
Compare Halfword Logical [Immediate]
e_cmphl
crD,rA,rB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRD
/
RA
RB
0
0
0
0
1
0
1
1
1
0
/
a  EXTZ(GPR(RA)48:63)
b  EXTZ(GPR(RB)48:63)
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR4CRD+32:4CRD+35  c || XERSO
For e_cmphl, the contents of the low-order 16 bits of GPR(rA) and GPR(rB) are compared,
treating the operands as unsigned integers. The result of the comparison is placed into CR
field CRD.
Special Registers Altered: CR field CRD
se_cmphl
rX,rY
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
8
9
10
RY
11
12
13
14
15
RX
a  GPR(RX)48:63
b  GPR(RY)48:63
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR0:3  c || XERSO
For se_cmphl, the contents of the low-order 16 bits of GPR(rX) and GPR(rY) are
compared, treating the operands as unsigned integers. The result of the comparison is
placed into CR field 0.
Special Registers Altered: CR[0–3]
DocID13694 Rev 2
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Instruction set
RM0004
e_cmphl16i
rA,UI
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UI0:4
RA
1
0
1
1
UI5:15
1
a  160 || GPR(RA)48:63)
b  160 || UI0:4 || UI5:15
if a < b then c  0b100
if a > b then c  0b010
if a = b then c  0b001
CR32:35  c || XERSO // only CR0
The contents of the lower 16-bits of GPR(rA) are zero-extended and compared with the
zero-extended value of the UI field, treating the operands as unsigned integers.
The result of the comparison is placed into CR0.
Special Registers Altered: CR0
cmpl
Book E
cmpl
User
Compare logical [immediate]
cmpl
0
1
crD,L,rA,rB
2
3
4
5
6
0 1 1 1 1 1
7
8
crD
/ L
cmpli
0
1
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0 0 0 0 1 0 0 0 0 0 /
crD,L,rA,UIMM
2
3
4
5
0 0 1 0 1 0
6
7
crD
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
/ L
rA
UIMM
if L=0 then a  320 || rA32:63
else
a  rA
if ‘cmpli’
then b  480 || UIMM
if ‘cmpl’ & L=0 then b  320 || rB32:63
if ‘cmpl’ & L=1 then b  rB
if a <u b then c  0b100
if a >u b then c  0b010
if a = b then c  0b001
CR4crD+32:4crD+35  c || XERSO
If cmpl and L=0, the contents of rA[32–63] are compared with the contents of rB[32–63],
treating the operands as unsigned integers.
If cmpli and L=0, the contents of rA[32–63] are compared with the zero-extended value of
the UIMM field, treating the operands as unsigned integers.
The result of the comparison is placed into CR field crD.
Other registers altered: CR field crD
376/1025
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RM0004
Instruction set
_cmpl
VLE
_cmpl
User
_cmpl _cmpl _cmpl _cmpl
Compare Logical [Immediate]
e_cmpl16i
rA,UI
0
1
2
3
4
5
0
1
1
1
0
0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UI0:4
RA
e_cmpli
1
0
1
0
UI5:15
1
crD32,rA,SCI8
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
1
1
0
0
0
1 CRD32
RA
1
0
1
0
1
F
SCL
UI8
a  GPR(RA)32:63
if ‘e_cmpli’ then b  SCI8(F,SCL,UI8)
if ‘e_cmpl16i’ then b  160 || UI0:4 || UI5:15
if a <u b then c  0b100
if a >u b then c  0b010
if a = b then c  0b001
if ‘e_cmpli’ then CR4CRD32+32:4CRD32+35  c || XERSO // only CR0-CR3
if ‘e_cmp16i’ then CR32:35  c || XERSO // only CR0
If e_cmpi, the contents of bits 32–63 of GPR(rA) are compared with the value of SCI8,
treating the operands as unsigned integers.
L must be 0 for 32-bit implementations
If e_cmpl16i, the contents of GPR(rA) are compared with the zero-extended value of the UI
field, treating the operands as unsigned integers.
The result of the comparison is placed into CR field CRD (CRD32). For e_cmpli, only CR0–
CR3 may be specified. For e_cmpl16i, only CR0 may be specified.
Special Registers Altered: CR field CRD (CRD32) (CR0 for e_cmpl16i)
se_cmpl
rX,rY
0
0
0
0
0
1
se_cmpli
0
6
7
1
0
1
8
11
12
RY
15
RX
rX,OIMM
0
0
5
1
0
0
5
6
0
1
7
11
OIM5(1)
12
15
RX
1. OIMM = OIM5 +1
a  GPR(RX)32:63
if ‘se_cmpli’ then b  270 || OFFSET(OIM5)
if ‘se_cmpl’ then b  GPR(RY)32:63
if a <u b then c  0b100
if a >u b then c  0b010
if a = b then c  0b001
CR0:3  c || XERSO
DocID13694 Rev 2
377/1025
666
Instruction set
RM0004
If se_cmpl, the contents of GPR(rX) are compared with the contents of GPR(rY), treating
the operands as unsigned integers. The result of the comparison is placed into CR field 0.
If se_cmpli, the contents of GPR(rX) are compared with the value of the zero-extended
offset value of the OIM5 field (a final value in the range 1–32), treating the operands as
unsigned integers. The result of the comparison is placed into CR field 0.
Special Registers Altered: CR[0–3]
cntlzw
Book E
User
cntlzw
Count leading zeros (word)
cntlzw
rA,rS(Z=0, Rc=0)
cntlzw.
rS(Z=0, Rc=1)
0
1
2
3
4
5
6
7
0 1 1 1 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rS
rA
///
0 0 0 0 Z 1 1 0 1 0 Rc
if ‘cntlzd’ then n  0 else n  32
i  0
do while n < 64
if rSn = 1 then leave
n  n + 1
i  i + 1
rA  i
if Rc=1 then do
GT  i > 0
EQ  i = 0
CR0  0b0 || GT || EQ || SO
For cntlzw[.], a count of the number of consecutive zero bits starting at rS[32] is placed into
rA. This number ranges from 0 to 32, inclusive. If Rc=1, CR field 0 is set to reflect the result.
Other registers altered: CR0 (if Rc=1)
crand
Book E
User
crand
Condition register AND
crand
0
1
crbD,crbA,crbB
2
3
4
5
0 1 0 0 1 1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 1 0 0 0 0 0 0 0 1 /
CRcrbD+32  CRcrbA+32 & CRcrbB+32
The content of bit crbA+32 of CR is ANDed with the content of bit crbB+32 of CR, and the
result is placed into bit crbD+32 of CR.
Other registers altered: CR
378/1025
DocID13694 Rev 2
RM0004
Instruction set
_crand
VLE
_crand
User
_crand _crand _crand _crand
Condition Register AND
e_crand
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
1
0
0
0
0
0
0
0
1
/
CRBT+32  CRBA+32 & CRBB+32
The content of bit CRBA+32 of the CR is ANDed with the content of bit CRBB+32 of the CR,
and the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
Condition Register AND with Complement
e_crandc
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
0
1
0
0
0
0
0
0
1
/
CRBT+32  CRBA+32 & CRBB+32
The content of bit CRBA+32 of the CR is ANDed with the one’s complement of the content
of bit CRBB+32 of the CR, and the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
CR Equivalent
e_creqv
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
1
0
0
1
0
0
0
0
1
/
CRBT+32  CRBA+32  CRBB+32
The content of bit CRBA+32 of the CR is XORed with the content of bit CRBB+32 of the CR,
and the one’s complement of result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
crandc
Book E
User
crandc
Condition register AND with complement
crandc
0
1
2
crbD,crbA,crbB
3
4
5
0 1 0 0 1 1
6
7
8
crbD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbA
DocID13694 Rev 2
crbB
0 0 1 0 0 0 0 0 0 1 /
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Instruction set
RM0004
CRcrbD+32  CRcrbA+32 & CRcrbB+32
The content of bit crbA+32 of CR is ANDed with the one’s complement of the content of bit
crbB+32 of CR, and the result is placed into bit crbD+32 of CR.
Other registers altered: CR
creqv
Book E
creqv
User
Condition register equivalent
creqv
0
1
crbD,crbA,crbB
2
3
4
5
6
7
0 1 0 0 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 1 0 0 1 0 0 0 0 1 /
CRcrbD+32  CRcrbA+32  CRcrbB+32
The content of bit crbA + 32 of CR is XORed with the content of bit crbB + 32 of CR, and
the one’s complement of result is placed into bit crbD+32 of CR.
Other registers altered: CR
crnand
Book E
crnand
User
Condition register NAND
crnand
0
1
2
crbD,crbA,crbB
3
4
5
6
7
0 1 0 0 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 0 1 1 1 0 0 0 0 1 /
CRcrbD+32  (CRcrbA+32 & CRcrbB+32)
The content of bit crbA+32 of CR is ANDed with the content of bit crbB+32 of CR, and the
one’s complement of the result is placed into bit crbD+32 of CR.
Other registers altered: CR
_crnand
VLE
_crnand _crnand _crnand _crnand
_crnand
User
Condition Register NAND
e_crnand
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
CRBD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBA
CRBT+32  (CRBA+32 & CRBB+32)
380/1025
DocID13694 Rev 2
CRBB
0
0
1
1
1
0
0
0
0
1
/
RM0004
Instruction set
The content of bit CRBA+32 of the CR is ANDed with the content of bit CRBB+32 of the CR,
and the one’s complement of the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
crnor
Book E
crnor
User
Condition register NOR
crnor
0
crbD,crbA,crbB
1
2
3
4
5
6
7
0 1 0 0 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 0 0 0 1 0 0 0 0 1 /
CRcrbD+32  (CRcrbA+32 | CRcrbB+32)
The content of bit crbA+32 of CR is ORed with the content of bit crbB+32 of CR, and the
one’s complement of the result is placed into bit crbD+32 of CR.
Other registers altered: CR
_crnor
VLE
_crnor
User
Condition Register NOR
e_crnor
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
0
0
0
1
0
0
0
0
1
/
CRBT+32  (CRBA+32 | CRBB+32)
The content of bit CRBA+32 of the CR is ORed with the content of bit CRBB+32 of the CR,
and the one’s complement of the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
cror
Book E
User
cror
Condition register OR
cror
0
crbD,crbA,crbB
1
2
3
4
5
0 1 0 0 1 1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 1 1 1 0 0 0 0 0 1 /
CRcrbD+32  CRcrbA+32 | CRcrbB+32
The content of bit crbA+32 of CR is ORed with the content of bit crbB+32 of CR, and the
result is placed into bit crbD+32 of CR.
Other registers altered: CR
_cror
VLE
User
_cror
Condition Register OR
DocID13694 Rev 2
381/1025
666
Instruction set
RM0004
e_cror
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
1
1
1
0
0
0
0
0
1
/
CRBT+32  CRBA+32 | CRBB+32
The content of bit CRBA+32 of the CR is ORed with the content of bit CRBB+32 of the CR,
and the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
crorc
Book E
crorc
User
Condition register OR with complement
crorc
0
1
crbD,crbA,crbB
2
3
4
5
6
7
0 1 0 0 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbD
crbA
crbB
0 1 1 0 1 0 0 0 0 1 /
CRcrbD+32  CRcrbA+32 | CRcrbB+32
The content of bit crbA+32 of CR is ORed with the one’s complement of the content of bit
crbB+32 of CR, and the result is placed into bit crbD+32 of CR.
Other registers altered: CR
_crorc
_crorc _crorc _crorc _crorc
VLE
_crorc
User
Condition Register OR with Complement
e_crorc
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
1
1
0
1
0
0
0
0
1
/
CRBT+32  CRBA+32 | CRBB+32
The content of bit CRBA+32 of the CR is ORed with the one’s complement of the content of
bit CRBB+32 of the CR, and the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
crxor
Book E
User
crxor
Condition register XOR
crxor
0
1
crbD,crbA,crbB
2
3
4
5
0 1 0 0 1 1
382/1025
6
7
8
crbD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
crbA
DocID13694 Rev 2
crbB
0 0 1 1 0 0 0 0 0 1 /
RM0004
Instruction set
CRcrbD+32  CRcrbA+32  CRcrbB+32
The content of bit crbA+32 of CR is XORed with the content of bit crbB+32 of CR, and the
result is placed into bit crbD+32 of CR.
Other registers altered: CR
_crxor
_crxor _crxor _crxor _crxor
VLE
_crxor
User
Condition Register XOR
e_crxor
crbD,crbA,crbB
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CRBD
CRBA
CRBB
0
0
1
1
0
0
0
0
0
1
/
CRcrbD+32  CRBA+32  CRBB+32
The content of bit CRBA+32 of the CR is XORed with the content of bit CRBB+32 of the CR,
and the result is placed into bit CRBD+32 of the CR.
Special Registers Altered: CR
dcba
Book E
dcba
User
Data cache block allocate
dcba
0
1
rA,rB
2
3
4
5
6
7
0 1 1 1 1 1
8
///
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1 0 1 1 1 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
AllocateDataCacheBlock(EA)
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
dcba is a hint that performance would likely improve if the block containing the byte
addressed by EA is established in the data cache without fetching the block from main
memory, because the program is likely to soon store into a portion of the block and the
contents of the rest of the block are not meaningful to the program. If the hint is honored, the
contents of the block are undefined when the instruction completes. The hint is ignored if the
block is caching-inhibited.
If the block containing the byte addressed by EA is in memory that is memory-coherence
required and the block exists in a data cache of any other processors, it is kept coherent in
those caches.
This instruction is treated as a storeexcept that an interrupt is not taken for a translation or
protection violation.
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Instruction set
RM0004
This instruction may establish a block in the data cache without verifying that the associated
real address is valid. This can cause a delayed machine check interrupt.
Other registers altered: None
dcbf
Book E
dcbf
User
Data cache block flush
dcbf
0
1
rA,rB
2
3
4
5
6
7
0 1 1 1 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
///
rA
rB
0 0 0 1 0 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
FlushDataCacheBlock( EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
If the block containing the byte addressed by EA is in memory that is memory-coherence
required, a block containing the byte addressed by EA is in the data cache of any processor,
and any locations in the block are considered to be modified there, then those locations are
written to main memory. Additional locations in the block may also be written to main
memory. The block is invalidated in the data caches of all processors.
If the block containing the byte addressed by EA is in memory that is not memorycoherence required, a block containing the byte addressed by EA is in the data cache of this
processor and any locations in the block are considered to be modified there, then those
locations are written to main memory. Additional locations in the block may also be written to
main memory. The block is invalidated in the data cache of this processor.
On some implementations, HID1[ABE] must be set to allow management of external L2
caches (for implementations with L2 caches) as well as other L1 caches in the system.
The function of this instruction is independent of whether the block containing the byte
addressed by EA is in memory that is write-through required or caching-inhibited.
This instruction is treated as a load. See Section 4.6.6.8: Cache management instructions.
Other registers altered: None
dcbi
Book E
User
dcbi
Data cache block invalidate
dcbi
0
1
rA,rB
2
3
4
5
0 1 1 1 1 1
384/1025
6
7
8
///
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
DocID13694 Rev 2
rB
0 1 1 1 0 1 0 1 1 0 /
RM0004
Instruction set
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
InvalidateDataCacheBlock( EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
If the block containing the byte addressed by EA is in is coherence-required memory and
any block containing the addressed byte is any processors’ data cache is invalidated in
those caches. On some implementations, before the block is invalidated, if any locations in
the block are considered to be modified in any such data cache, those locations are written
to main memory and additional locations in the block may be written to main memory.
If the block containing the byte addressed by EA is not coherence-required memory and a
block containing the byte addressed by EA is in the data cache of this processor, then the
block is invalidated in that data cache. On some implementations, before the block is
invalidated, any locations in the block considered modified in that data cache are written to
main memory; additional locations in the block may be written to main memory.
dcbi is treated as a store on implementations that invalidate a block without first writing to
main memory all locations in the block that are considered to be modified in the data cache,
except that the invalidation is not ordered by mbar. On other implementations this
instruction is treated as a load.
Additional information about this instruction is as follows.

The data cache block size for dcbi is the same as for dcbf.

If a processor holds a reservation and some other processor executes a dcbi to the
same reservation granule, whether the reservation is lost is undefined.
Other registers altered: None
dcblc
dcblc
Cache locking APU User
Data cache block lock clear
dcblc
0
1
CT,rA,rB Form: X
2
3
4
5
0 1 1 1 1 1
6
7
8
CT
9
10
11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
rA
rB
0 1 1 0 0 0 0 1 1 0
31
/
if rA = 0 then a 640else a GPR(rA)
if Mode32 then EA 320 || (a + GPR(rB))32:63
if Mode64 then EA a + GPR(rB)
DataCacheBlockClearLock(CT, EA)
EA calculation:
EA for rA=0EA for rA0
320 || GPR(rB)
32
32:63 0 ||
(GPR(rA)+GPR(rB))32:63
The data cache specified by CT has the cache line corresponding to EA unlocked allowing
the line to participate in the normal replacement policy.
Cache lock clear instructions remove locks previously set by cache lock set instructions.
Section 4.3.1.18: User-level cache instructions, lists supported CT values. An
implementation may use other CT values to enable software to target specific,
implementation-dependent portions of its cache hierarchy or structure.
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Instruction set
RM0004
The instruction is treated as a load with respect to translation and memory protection and
can cause DSI and DTLB error interrupts accordingly.
An unable-to-unlock condition is said to occur any of the following conditions exist:

The target address is marked cache-inhibited, or the storage attributes of the address
uses a coherency protocol that does not support locking.

The target cache is disabled or not present.

The CT field of the instructions contains a value not supported by the implementation.

The target address is not in the cache or is present in the cache but is not locked.
If an unable-to-unlock condition occurs, no cache operation is performed.
EIS Specifics
Clearing and then setting L1CSR0[CLFR] allows system software to clear all L1 data cache
locking bits without knowing the addresses of the lines locked.
dcbst
Book E
dcbst
User
Data Cache Block Store
dcbst
0
1
rA,rB
2
3
4
5
0 1 1 1 1 1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
///
rA
rB
0 0 0 0 1 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
StoreDataCacheBlock( EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
If the block containing the byte addressed by EA is in memory that is memory-coherence
required and a block containing the byte addressed by EA is in the data cache of any
processor, and any locations in the block are considered to be modified there, those
locations are written to main memory. Additional locations in the block may be written to
main memory. The block ceases to be considered to be modified in that data cache.
If the block containing the byte addressed by EA is in memory that is not memorycoherence required and a block containing the byte addressed by EA is in the data cache of
this processor and any locations in the block are considered to be modified there, those
locations are written to main memory. Additional locations in the block may be written to
main memory. The block ceases to be considered to be modified in that cache.
The function of this instruction is independent of whether the block containing the byte
addressed by EA is in memory that is write-through required or caching-inhibited.
This instruction is treated as a load.
On some implementations, HID1[ABE] must be set to allow management of external L2
caches (for implementations with L2 caches) as well as other L1 caches in the system.
Other registers altered: None
dcbt
Book E
Data cache block touch
386/1025
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User
dcbt
RM0004
Instruction set
dcbt
0
CT,rA,rB
1
2
3
4
5
6
7
0 1 1 1 1 1
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CT
rA
rB
0 1 0 0 0 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
PrefetchDataCacheBlock( CT, EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
Section 4.3.1.18: User-level cache instructions, lists supported CT values. An
implementation may use other CT values to enable software to target specific,
implementation-dependent portions of its cache hierarchy or structure.
Implementations should perform no operation when CT specifies a value not supported by
the implementation.
The hint is ignored if the block is caching-inhibited.
This instruction is treated as a load except that an interrupt is not taken for a translation or
protection violation.
Other registers altered: None
dcbtls
dcbtls
Cache locking APU User
Data cache block touch and lock set
dcbtls
0
1
2
CT,rA,rB
3
4
5
0 1 1 1 1 1
6
7
8
9
Form: X
10
11 12 13 14 15
CT
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
rA
rB
31
0 0 1 0 1 0 0 1 1 0
/
if rA = 0 then a 640else a GPR(rA)
if Mode32 then EA 320 || (a + GPR(rB))32:63
if Mode64 then EA a + GPR(rB)
PrefetchDataCacheBlockLockSet(CT, EA)
EA calculation:
EA for rA=0EA for rA0
320 || GPR(rB)
32
32:63 0 ||
(GPR(rA)+GPR(rB))32:63
The data cache specified by CT has the cache line corresponding to EA loaded and locked
into the cache. If the line already exists in the cache, it is locked without being refetched.
Cache touch and lock set instructions let software lock cache lines into the cache to provide
lower latency for critical cache accesses and more deterministic behavior. Locked lines do
not participate in the normal replacement policy when a line must be victimized for
replacement.
Section 4.3.1.18: User-level cache instructions, lists supported CT values. An
implementation may use other CT values to enable software to target specific,
implementation-dependent portions of its cache hierarchy or structure.
The instruction is treated as a load with respect to translation and memory protection and
can cause DSI and DTLB error interrupts accordingly.
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Instruction set
RM0004
An unable to lock condition is said to occur any of the following conditions exist:

The target address is marked cache-inhibited, or the storage attributes of the address
uses a coherency protocol that does not support locking.

The target cache is disabled or not present.

The CT field of the instructions contains a value not supported by the implementation.
If an unable to lock condition occurs, no cache operation is performed and LICSR0[DCUL] is
set appropriately.
Overlocking is said to exist is all available ways for a given cache index are already locked.
If overlocking occurs for dcbtls and if the lock was targeted for the primary cache (CT = 0),
the requested line is not locked into the cache. When overlock occurs, L1CSR1[DCLO] is
set. If L1CSR1[DCLOA] is set, the requested line is locked into the cache and
implementation dependent line currently locked in the cache is evicted.
The results of overlocking and unable to lock conditions for caches other than the primary
cache and secondary cache are defined as part of the architecture for the specific cache
hierarchy designated by CT.
Other registers altered:

L1CSR0[DCUL] if unable to lock occurs

L1CSR0[DCLO] (L2CSR[L2CLO]) if lock overflow occurs
dcbtst
Book E
dcbtst
User
Data cache block touch for store
dcbtst
0
1
2
CT,rA,rB
3
4
5
0 1 1 1 1 1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
CT
rA
rB
0 0 1 1 1 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
PrefetchForstoreDataCacheBlock( CT, EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
If CT=0, this instruction is a hint that performance would likely be improved if the block
containing the byte addressed by EA is fetched into the data cache, because the program
will probably soon store into the addressed byte.
Section 4.3.1.18: User-level cache instructions, lists supported CT values. An
implementation may use other CT values to enable software to target specific,
implementation-dependent portions of its cache hierarchy or structure.
Implementations should perform no operation when CT specifies a value not supported by
the implementation.
The hint is ignored if the block is caching-inhibited.
This instruction is treated as a load , except that an interrupt is not taken for a translation or
protection violation.
Other registers altered: None
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RM0004
Instruction set
dcbtstls
Cache locking APU User
dcbtstls
Data cache block touch for store and lock set
dcbtstls
0
1
2
3
CT,rA,rB
4
5
0 1 1 1 1 1
6
7
8
CT
9
10
11 12 13 14 15
Form: X
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
rA
rB
31
0 0 1 0 0 0 0 1 1 0
/
if rA = 0 then a 640else a GPR(rA)
if Mode32 then EA 320 || (a + GPR(rB))32:63
if Mode64 then EA a + GPR(rB)
PrefetchDataCacheBlockLockSet(CT, EA)
EA calculation:
EA for rA=0EA for rA0
32
0 || GPR(rB)32:63320 || (GPR(rA)+GPR(rB))32:63
The data cache specified by CT has the cache line corresponding to EA loaded and locked
into the cache. If the line already exists in the cache, it is locked without refetching from
memory.
Cache touch and lock set instructions allow software to lock lines into the cache to shorten
latency for critical cache accesses and more deterministic behavior. Lines locked in the
cache do not participate in the normal replacement policy when a line must be victimized for
replacement.
Section 4.3.1.18: User-level cache instructions, lists supported CT values. An
implementation may use other CT values to enable software to target specific,
implementation-dependent portions of its cache hierarchy or structure.
Table 114 describes how this instruction is treated with respect to translation and memory
protection.
For unable-to-lock conditions, described in Section 9.1.1.4: Unable-to-lock conditions, no
cache operation is performed and LICSR0[DCUL] is set.
Overlocking occurs when all available ways for a given cache index are already locked. If an
overlocking condition occurs for a dcbtstls instruction and if the lock was targeted for the
primary cache or secondary cache (CT = 0 or CT = 2), the requested line is not locked into
the cache. When overlock occurs, L1CSR1[DCLO] (L2CSR[L2CLO] for CT = 2) is set. If
L1CSR1[DCLOA] is set (or L2CSR[L2CLOA] for CT = 2), the requested line is locked into
the cache and implementation dependent line currently locked in the cache is evicted. If
system software wants to precisely determine if an overlock event has occurred in the L1
data cache, it must perform the following code sequence:
dcbtstls
msync
mfspr (L1CSR0)
(check L1CSR0[DCUL] bit for data cache index unable-to-lock condition)
(check L1CSR0[DCLO] bit for data cache index overlock condition)
Results of overlocking and unable-to-lock conditions for caches other than the primary and
secondary cache are defined as part of the architecture for the cache hierarchy designated
by CT.
Other registers altered:

L1CSR0[DCUL] if unable to lock occurs

L1CSR0[DCLO] (L2CSR[L2CLO]) if lock overflow occurs
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Instruction set
RM0004
EIS specifics:
Clearing and then setting L1CSR0[CLFR] allows system software to clear all data cache
locking bits without knowing the addresses of the lines locked.
dcbz
Book E
dcbz
User
Data cache block set to zero
dcbzrThe data cache specified by CT has theA,rB
0
1
2
3
4
5
0 1 1 1 1 1
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
///
rA
rB
1 1 1 1 1 1 0 1 1 0 /
if rA=0 then a  640 else a  rA
EA  320 || (a + rB)32:63
ZeroDataCacheBlock( EA )
EA calculation:
Addressing ModeEA for rA=0EA for rA0
32
0 || rB32:63320 || (rA+rB)32:63
If the block containing the addressed byte is in the data cache, all bytes of the block are
cleared.
If the block containing the byte addressed by EA is not in the data cache and is in memory
that is not caching-inhibited, the block is established in the data cache without fetching the
block from main memory, and all bytes of the block are cleared.
If the block containing the byte addressed by EA is not in the data cache and is in storage
that is not caching inhibited and cannot be established in the cache, then one of the
following occurs:

All bytes of the area of main storage that corresponds to the addressed block are set to
zero

An alignment interrupt is taken
If the block containing the byte addressed by EA is in storage that is caching inhibited or
write through required, one of the following occurs:

All bytes of the area of main storage that corresponds to the addressed block are set to
zero

An alignment interrupt is taken.
If the block containing the byte addressed by EA is in memory-coherence required memory
and the block exists in any other processors’ data cache, it is kept coherent in those caches.
dcbz may establish a block in the data cache without verifying that the associated real
address is valid. This can cause a delayed machine check interrupt.
dcbz is treated as a store.

On some implementations, HID1[ABE] must be set to allow management of external L2
caches (for implementations with L2 caches) as well as other L1 caches in the system.

dcbz may cause a cache-locking exception on some implementations. See the user
documentation.
Other registers altered: None
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RM0004
Instruction set
Programming note: If the block containing the byte addressed by EA is in memory that is
caching-inhibited or write-through required, the alignment interrupt handler should clear all
bytes of the area of main memory that corresponds to the addressed block.
divw
Book E
User
divw
Divide word
divw
divw.
divwo
divwo.
0
1
2
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
3
4
5
6
7
0 1 1 1 1 1
8
(OE=0, Rc=0)
(OE=0, Rc=1)
(OE=1, Rc=0)
(OE=1, Rc=1)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
O
1 1 1 1 0 1 0 1 1 Rc
E
dividend0:31  rA32:63
divisor0:31  rB32:63
quotient0:31  dividend  divisor
if OE=1 then do
OV  ( (rA32:63=-231) & (rB32:63=-1) ) | (rB32:63=0)
SO  SO | OV
if Rc=1 then do
LT  quotient < 0
GT  quotient > 0
EQ  quotient = 0
CR0  LT || GT || EQ || SO
rD32:63  quotient
rD0:31  undefined
The 32-bit quotient of the contents of rA[32–63] divided by the contents of rB[32–63] is
placed into rD[32–63]. rD[0–31] are undefined. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as signed integers. The quotient is the
unique signed integer that satisfies the following:
dividend = (quotient  divisor) + r
Here, 0  r < |divisor| if the dividend is nonnegative and –|divisor| < r  0 if it is negative.
If any of the following divisions is attempted, the contents of rD are undefined as are (if
Rc=1) the contents of the CR0[LT,GT,EQ]. In these cases, if OE=1, OV is set.
0x8000_0000  –1
<anything>  0
Other registers altered:

CR0 (if Rc=1)
SO OV (if OE=1)
divwu
Book E
User
divwu
Divide word unsigned
divwu
divwu.
rD,rA,rB
rD,rA,rB
DocID13694 Rev 2
(OE=0, Rc=0)
(OE=0, Rc=1)
391/1025
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Instruction set
RM0004
divwuo
divwuo.
0
1
2
rD,rA,rB
rD,rA,rB
3
4
5
6
7
0 1 1 1 1 1
8
(OE=1, Rc=0)
(OE=1, Rc=1)
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
O
1 1 1 0 0 1 0 1 1 Rc
E
dividend0:31  rA32:63
divisor0:31  rB32:63
quotient0:31  dividend  divisor
if OE=1 then do
OV  (rB32:63=0)
SO  SO | OV
if Rc=1 then do
LT  quotient < 0
GT  quotient > 0
EQ  quotient = 0
CR0  LT || GT || EQ || SO
rD32:63  quotient
rD0:31  undefined
The 32-bit quotient of the contents of rA[32–63] divided by the contents of rB[32–63] is
placed into rD[32–63]. rD[0–31] are undefined. The remainder is not supplied as a result.
Both operands and the quotient are interpreted as unsigned integers, except that if Rc=1 the
first three bits of CR field 0 are set by signed comparison of the result to zero. The quotient
is the unique unsigned integer that satisfies the following:
dividend = (quotient  divisor) + r
Here, 0  r < divisor.
If an attempt is made to perform the following division, the contents of rD are undefined as
are (if Rc=1) the contents of the LT, GT, and EQ bits of CR0. In this case, if OE=1 OV is set.
<anything>  0
Other registers altered:

CR0 (if Rc=1)

SO
OV (if OE=1)
efdabs
Scalar DPFP APU User
efdabs
Floating-point double-precision absolute value
efdabs
0
1
2
rD,rA
3
4
5
0 0 0 1 0 0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 0
rD0:63  0b0 || rA1:63
The sign bit of rA is set to 0 and the result is placed into rD.
Exceptions:
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RM0004
Instruction set
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the sign bit operation. If the implementation does not detect exceptions, or if
exception detection is disabled, the computation can be carried out in one of two ways, as a
sign bit operation ignoring the rest of the contents of the source register, or by examining the
input and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: If
rA is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and FG and FX are cleared. If
floating-point invalid input exceptions are enabled, an interrupt is taken and the destination
register is not updated.
efdadd
Scalar DPFP APU User
efdadd
Floating-point double-precision add
efdadd
0
1
2
rD,rA,rB
3
4
5
6
7
0 0 0 1 0 0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0 1 0 1 1 1 0 0 0 0 0
rD0:63  rA0:63 +dp rB0:63
rA is added to rB and the result is stored in rD. If rA is NaN or infinity, the result is either
pmax (asign==0), or nmax (asign==1). Otherwise, If rB is NaN or infinity, the result is either
pmax (bsign==0), or nmax (bsign==1). Otherwise, if an overflow occurs, pmax or nmax (as
appropriate) is stored in rD. If an underflow occurs, +0 (for rounding modes RN, RZ, RP) or
-0 (for rounding mode RM) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and the destination register is not updated.
Otherwise, if an overflow occurs, SPEFSCR[FOVF] is set, or if an underflow occurs,
SPEFSCR[FUNF] is set. If either underflow or overflow exceptions are enabled and the
corresponding bit is set, an interrupt is taken. If any of these interrupts are taken, the
destination register is not updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result, the FG and
FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
efdcfs
Scalar DPFP APU User
efdcfs
Floating-point double-precision convert from single-precision
efdcfs
0
1
rD,rB
2
3
4
5
0 0 0 1 0 0
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
DocID13694 Rev 2
rB
0 1 0 1 1 1 0 1 1 1 1
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Instruction set
RM0004
FP32format f;
FP64format result;
f  rB32:63
if (fexp = 0) & (ffrac = 0)) then
result  fsign || 630 // signed zero value
else if Isa32NaNorInfinity(f) | Isa32Denorm(f) then
SPEFSCRFINV  1
result  fsign || 0b11111111110 || 521 // max value
else if Isa32Denorm(f) then
SPEFSCRFINV  1
result  fsign || 630
else
resultsign  fsign
resultexp  fexp - 127 + 1023
resultfrac  ffrac || 290

rD0:63 = result
The single-precision floating-point value in the low element of rB is converted to a doubleprecision floating-point value and the result is placed into rD. The rounding mode is not
used since this conversion is always exact.
Exceptions:
If the low element of rB is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and the destination register is not updated.
FG and FX are always cleared.
Note:
Architecture Note: This instruction is optional if neither the embedded scalar singleprecision floating-point APU or the embedded vector single-precision floating-point APU are
implemented.
efdcfsf
Scalar DPFP APU User
efdcfsf
Convert floating-point double-precision from signed fraction
efdcfsf
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 0 1 1
rD0:63CnvtI32ToFP64(rB32:63, SIGN, F)
The signed fractional low element in rB is converted to a double-precision floating-point
value using the current rounding mode and the result is placed into rD.
Exceptions:
None.
efdcfsi
Scalar DPFP APU User
Convert floating-point double-precision from signed integer
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efdcfsi
RM0004
Instruction set
efdcfsi
0
1
2
rD,rB
3
4
5
6
7
0 0 0 1 0 0
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 0 0 1

rD0:63CnvtSI32ToFP64(rB32:63, SIGN, I)
The signed integer low element in rB is converted to a double-precision floating-point value
using the current rounding mode and the result is placed into rD.
Exceptions:
None.
efdcfsid
efdcfsid
Scalar DPFP APU User
Convert floating-point double-precision from signed integer doubleword
efdcfsid
rD,rB
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
1
0
0
0
1
1
rD0:63CnvtI64ToFP64(rB0:63, SIGN)
The signed integer doubleword in rB is converted to a double-precision floating-point value
using the current rounding mode and the result is placed into rD.
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
This instruction may only be implemented for 64-bit implementations.
efdcfuf
Scalar DPFP APU User
efdcfuf
Convert floating-point double-precision from unsigned fraction
efdcfuf
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 0 1 0
rD0:63CnvtI32ToFP64(rB32:63, UNSIGN, F)
The unsigned fractional low element in rB is converted to a double-precision floating-point
value using the current rounding mode and the result is placed into rD.
Exceptions:
None.
DocID13694 Rev 2
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Instruction set
RM0004
efdcfui
efdcfui
Scalar DPFP APU User
Convert floating-point double-precision from unsigned integer
efdcfui
0
1
2
rD,rB
3
4
5
6
7
0 0 0 1 0 0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 0 0 0
rD0:63CnvtSI32ToFP64(rB32:63, UNSIGN, I)
The unsigned integer low element in rB is converted to a double-precision floating-point
value using the current rounding mode and the result is placed into rD.
Exceptions:
None.
efdcfuid
Scalar DPFP APU User
efdcfuid
Convert floating-point double-precision from unsigned integer doubleword
efdcfuid
0
1
2
rD,rB
3
4
5
6
7
0 0 0 1 0 0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
0 0 0 0 0
rB
0 1 0 1 1 1 0 0 0 1 0
rD0:63CnvtI64ToFP64(rB0:63, UNSIGN)
The unsigned integer doubleword in rB is converted to a double-precision floating-point
value using the current rounding mode and the result is placed into rD.
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
This instruction may only be implemented for 64-bit implementations.
efdcmpeq
Scalar DPFP APU User
efdcmpeq
Floating-point double-precision compare equal
efdcmpeq
0
1
2
3
crfD,rA,rB
4
5
0 0 0 1 0 0
6
7
crfD
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0
rA
alrA0:63
blrB0:63
if (al = bl) then cl1
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rB
0 1 0 1 1 1 0 1 1 1 0
RM0004
Instruction set
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
rA is compared against rB. If rA is equal to rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0).
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and the
FGH FXH, FG and FX bits are cleared. If floating-point invalid input exceptions are enabled,
an interrupt is taken and the condition register is not updated. Otherwise, the comparison
proceeds after treating NaNs, Infinities, and Denorms as normalized numbers, using their
values of ‘e’ and ‘f’ directly.
efdcmpgt
Scalar DPFP APU User
efdcmpgt
Floating-point double-precision compare greater than
efdcmpgt
0
1
2
3
crfD,rA,rB
4
5
6
0 0 0 1 0 0
7
8
crfD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0
rA
rB
0 1 0 1 1 1 0 1 1 0 0
alrA0:63
blrB0:63
if (al > bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
rA is compared against rB. If rA is greater than rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0).
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and the
FGH FXH, FG and FX bits are cleared. If floating-point invalid input exceptions are enabled,
an interrupt is taken and the condition register is not updated. Otherwise, the comparison
proceeds after treating NaNs, Infinities, and Denorms as normalized numbers, using their
values of ‘e’ and ‘f’ directly.
efdcmplt
efdcmplt
Floating-point double-precision compare less than
efdcmplt
0
1
2
crfD,rA,rB
3
4
5
0 0 0 1 0 0
6
7
crfD
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0
rA
rB
0 1 0 1 1 1 0 1 1 0 1
alrA0:63
blrB0:63
if (al < bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
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Instruction set
RM0004
rA is compared against rB. If rA is less than rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0).
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and the
FGH FXH, FG and FX bits are cleared. If floating-point invalid input exceptions are enabled,
an interrupt is taken and the condition register is not updated. Otherwise, the comparison
proceeds after treating NaNs, Infinities, and Denorms as normalized numbers, using their
values of ‘e’ and ‘f’ directly.
efdctsf
efdctsf
Scalar DPFP APU User
Convert floating-point double-precision to signed fraction
efdctsf
0
1
2
rD,rB
3
4
5
6
7
0 0 0 1 0 0
rD32:63 
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 1 1 1
CnvtFP64ToI32Sat(rB0:63, SIGN, ROUND, F)
The double-precision floating-point value in rB is converted to a signed fraction using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit
fraction. NaNs are converted as though they were zero.
Exceptions:
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
and the destination register is not updated.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
efdctsi
Scalar DPFP APU User
efdctsi
Convert floating-point double-precision to signed integer
efdctsi
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
rD32:63 
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 1 0 1
CnvtFP64ToI32Sat(rB0:63, SIGN, ROUND, I)
The double-precision floating-point value in rB is converted to a signed integer using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit
integer. NaNs are converted as though they were zero.
Exceptions:
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RM0004
Instruction set
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
the destination register is not updated, and no other status bits are set.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
efdctsidz
efdctsidz
Scalar DPFP APU User
Convert floating-point double-precision to signed integer doubleword with round
toward zero
efdctsidz
0
1
2
3
rD,rB
4
5
6
7
0 0 0 1 0 0
rD0:63 
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 0 1 0 1 1
CnvtFP64ToI64Sat(rB0:63, SIGN, TRUNC)
The double-precision floating-point value in rB is converted to a signed integer doubleword
using the rounding mode Round toward Zero and the result is saturated if it cannot be
represented in a 64-bit integer. NaNs are converted as though they were zero.
Exceptions:
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
the destination register is not updated, and no other status bits are set.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
This instruction may only be implemented for 64-bit implementations.
efdctsiz
efdctsiz
Scalar DPFP APU User
Convert floating-point double-precision to signed integer with round toward zero
efdctsiz
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
rD32:63 
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 1 0 1 0
CnvtFP64ToI32Sat(rB0:63, SIGN, TRUNC, I
The double-precision floating-point value in rB is converted to a signed integer using the
rounding mode Round toward Zero and the result is saturated if it cannot be represented in
a 32-bit integer. NaNs are converted as though they were zero.
Exceptions:
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Instruction set
RM0004
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
the destination register is not updated, and no other status bits are set.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
efdctuf
efdctuf
Scalar DPFP APU User
Convert floating-point double-precision to unsigned fraction
efdctuf
0
1
2
rD,rB
3
4
5
6
7
0 0 0 1 0 0
rD32:63 
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 1 1 0
CnvtFP64ToI32Sat(rB0:63, UNSIGN, ROUND, F)
The double-precision floating-point value in rB is converted to an unsigned fraction using
the current rounding mode and the result is saturated if it cannot be represented in a 32-bit
unsigned fraction. NaNs are converted as though they were zero.
Exceptions:
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
and the destination register is not updated.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
Floating-Point Round Interrupt vector. In this case, the destination register is updated with
the truncated result, the FG and FX bits are properly updated to allow rounding to be
performed in the interrupt handler.
efdctui
efdctui
Scalar DPFP APU User
Convert floating-point double-precision to unsigned integer
efdctui
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
rD32:63 
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 0 1 0 0
CnvtFP64ToI32Sat(rB0:63, UNSIGN, ROUND, I
The double-precision floating-point value in rB is converted to an unsigned integer using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit
integer. NaNs are converted as though they were zero.
Exceptions:
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RM0004
Instruction set
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
and the destination register is not updated.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
efdctuidz
Scalar DPFP APU User
efdctuidz
Convert floating-point double-precision to unsigned integer doubleword with round
toward zero
efdctuidz
0
1
2
3
rD,rB
4
5
6
7
0 0 0 1 0 0
rD0:63 
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 0 1 0 1 0
CnvtFP64ToI64Sat(rB0:63, UNSIGN, TRUNC)
The double-precision floating-point value in rB is converted to an unsigned integer
doubleword using the rounding mode Round toward Zero and the result is saturated if it
cannot be represented in a 64-bit integer. NaNs are converted as though they were zero.
Exceptions:
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
and the destination register is not updated.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
This instruction may only be implemented for 64-bit implementations.
efdctuiz
efdctuiz
Scalar DPFP APU User
Convert floating-point double-precision to unsigned integer with round toward zero
efdctuiz
0
1
2
rD,rB
3
4
5
0 0 0 1 0 0
rD32:63 
6
7
8
rD
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0 0 0 0 0
rB
0 1 0 1 1 1 1 1 0 0 0
CnvtFP64ToI32Sat(rB0:63, UNSIGN, TRUNC, I)
The double-precision floating-point value in rB is converted to an unsigned integer using the
rounding mode Round toward Zero and the result is saturated if it cannot be represented in
a 32-bit integer. NaNs are converted as though they were zero.
Exceptions:
DocID13694 Rev 2
401/1025
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Instruction set
RM0004
If the contents of rB are Infinity, Denorm, or NaN, or if an overflow occurs, SPEFSCR[FINV]
is set, and the FG, and FX bits are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken,
and the destination register is not updated.
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversion is
not exact. If the floating-point inexact exception is enabled, an interrupt is taken using the
floating-point round interrupt vector. In this case, the destination register is updated with the
truncated result, the FG and FX bits are properly updated to allow rounding to be performed
in the interrupt handler.
efddiv
efddiv
Scalar DPFP APU User
Floating-point double-precision divide
efddiv
0
1
rD,rA,rB
2
3
4
5
6
7
0 0 0 1 0 0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0 1 0 1 1 1 0 1 0 0 0
rD0:63rA0:63 dp rB0:63
rA is divided by rB and the result is stored in rD. If rB is a NaN or infinity, the result is a
properly signed zero. Otherwise, if rB is a zero (or a denormalized number optionally
transformed to zero by the implementation), or if rA is either NaN or infinity, the result is
either pmax (asign==bsign), or nmax (asign!=bsign). Otherwise, if an overflow occurs, pmax
or nmax (as appropriate) is stored in rD. If an underflow occurs, +0 or -0 (as appropriate) is
stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, or if both rA and rB are +/-0,
SPEFSCR[FINV] is set. If SPEFSCR[FINVE] is set, an interrupt is taken, and the destination
register is not updated. Otherwise, if the content of rB is +/-0 and the content of rA is a finite
normalized non-zero number, SPEFSCR[FDBZ] is set. If floating-point divide by zero
Exceptions are enabled, an interrupt is then taken. Otherwise, if an overflow occurs,
SPEFSCR[FOVF] is set, or if an underflow occurs, SPEFSCR[FUNF] is set. If either
underflow or overflow exceptions are enabled and the corresponding bit is set, an interrupt
is taken. If any of these interrupts are taken, the destination register is not updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result, the FG and
FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, divide by zero, or invalid operation/input
error is signaled, regardless of enabled exceptions.
efdmul
Scalar DPFP APU User
efdmul
Floating-point double-precision multiply
efdmul
0
402/1025
1
2
rD,rA,rB
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
DocID13694 Rev 2
RM0004
Instruction set
0 0 0 1 0 0
rD
rA
rB
0 1 0 1 1 1 0 1 0 0 0
rD0:63rA0:63 dp rB0:63
rA is multiplied by rB and the result is stored in rD. If rA or rB are zero (or a denormalized
number optionally transformed to zero by the implementation), the result is a properly
signed zero. Otherwise, if rA or rB are either NaN or infinity, the result is either pmax
(asign==bsign), or nmax (asign!=bsign). Otherwise, if an overflow occurs, pmax or nmax (as
appropriate) is stored in rD. If an underflow occurs, +0 or -0 (as appropriate) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and the destination register is not updated.
Otherwise, if an overflow occurs, SPEFSCR[FOVF] is set, or if an underflow occurs,
SPEFSCR[FUNF] is set. If either underflow or overflow exceptions are enabled and the
corresponding bit is set, an interrupt is taken. If any of these interrupts are taken, the
destination register is not updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result, the FG and
FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
efdnabs
Scalar DPFP APU User
efdnabs
Floating-point double-precision negative absolute value
efdnabs
0
1
2
rD,rA
3
4
5
0 0 0 1 0 0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0 0 0 0 0 0 1 0 1 1 1 0 0 1 0 1
rD0:63  0b1 || rA1:63
The sign bit of rA is set to 1 and the result is placed into rD.
Exceptions:
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the sign bit operation. If the implementation does not detect exceptions, or if
exception detection is disabled, the computation can be carried out in one of two ways, as a
sign bit operation ignoring the rest of the contents of the source register, or by examining the
input and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: If
rA is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and FG and FX are cleared. If
floating-point invalid input exceptions are enabled, an interrupt is taken and the destination
register is not updated.
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efdneg
efdneg
Scalar DPFP APU User
Floating-point double-precision negate
efdneg
0
1
2
rD,rA
3
4
5
6
7
0 0 0 1 0 0
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0 0 0 0 0 0 1 0 1 1 1 0 0 1 1 0
rD0:63  ¬rA0 || rA1:63
The sign bit of rA is complemented and the result is placed into rD.
Exceptions:
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the sign bit operation. If the implementation does not detect exceptions, or if
exception detection is disabled, the computation can be carried out in one of two ways, as a
sign bit operation ignoring the rest of the contents of the source register, or by examining the
input and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: If
rA is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and FG and FX are cleared. If
floating-point invalid input exceptions are enabled, an interrupt is taken and the destination
register is not updated.
efdsub
efdsub
Scalar DPFP APU User
Floating-point double-precision subtract
efdsub
0
1
2
rD,rA,rB
3
4
5
0 0 0 1 0 0
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0 1 0 1 1 1 0 0 0 0 1
rD0:63  rA0:63 -dp rB0:63
rB is subtracted from rA and the result is stored in rD. If rA is NaN or infinity, the result is
either pmax (asign==0), or nmax (asign==1). Otherwise, If rB is NaN or infinity, the result is
either nmax (bsign==0), or pmax (bsign==1). Otherwise, if an overflow occurs, pmax or
nmax (as appropriate) is stored in rD. If an underflow occurs, +0 (for rounding modes RN,
RZ, RP) or -0 (for rounding mode RM) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and the destination register is not updated.
Otherwise, if an overflow occurs, SPEFSCR[FOVF] is set, or if an underflow occurs,
SPEFSCR[FUNF] is set. If either underflow or overflow exceptions are enabled and the
corresponding bit is set, an interrupt is taken. If any of these interrupts are taken, the
destination register is not updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
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Instruction set
vector. In this case, the destination register is updated with the truncated result, the FG and
FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
efdtsteq
efdtsteq
Scalar DPFP APU User
Floating-point double-precision test equal
efdtsteq
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
8
crfD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
1
1
1
1
1
0
alrA0:63
blrB0:63
if (al = bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
rA is compared against rB. If rA is equal to rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0). The comparison proceeds after treating
NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’
directly.
No exceptions are generated during the execution of efdtsteq If strict IEEE 754 compliance
is required, the program should use efdcmpeq.
Implementation note: In an implementation, the execution of efdtsteq is likely to be faster
than the execution of efdcmpeq.
efdtstgt
efdtstgt
Scalar DPFP APU User
Floating-point double-precision test greater than
efdtstgt
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
crfD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
1
1
1
1
0
0
alrA0:63
blrB0:63
if (al > bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
rA is compared against rB. If rA is greater than rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0). The comparison proceeds after treating
NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’
directly.
No exceptions are generated during the execution of efdtstgt. If strict IEEE 754 compliance
is required, the program should use efdcmpgt.
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Note:
RM0004
Implementation note: In an implementation, the execution of efdtstgt is likely to be faster
than the execution of efdcmpgt.
efdtstlt
efdtstlt
Scalar DPFP APU User
Floating-point double-precision test less than
efdtstlt
0
1
2
3
4
5
0
0
0
1
0
0
crfD,rA,rB
6
7
8
crfD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
1
1
1
1
0
1
alrA0:63
blrB0:63
if (al < bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
rA is compared against rB. If rA is less than rB, the bit in the crfD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = -0). The comparison proceeds after treating
NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and ‘f’
directly.
No exceptions are generated during the execution of efdtstlt. If strict IEEE 754 compliance
is required, the program should use efdcmplt.
Implementation note: In an implementation, the execution of efdtstlt is likely to be faster
than the execution of efdcmplt.
efsabs
Scalar SPFP APU
efsabs
User
Floating-Point Absolute Value
efsabs
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
0
rD32:63  0b0 || rA33:63
The sign bit of rA is cleared and the result is placed into rD.
It is implementation dependent if invalid values for rA (NaN, Denorm, Infinity) are detected
and exceptions are taken.
efsadd
Scalar SPFP APU
efsadd
User
Floating-Point Add
efsadd
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
rD32:63  rA32:63 +sp rB32:63
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1
0
1
1
0
0
0
0
0
0
RM0004
Instruction set
The single-precision floating-point value of rA is added to rB and the result is stored in rD.
If an overflow condition is detected or the contents of rA or rB are NaN or Infinity, the result
is an appropriately signed maximum floating-point value.
If an underflow condition is detected, the result is an appropriately signed floating-point 0.
The following status bits are set in the SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm, or NaN

FOFV if an overflow occurs

FUNF if an underflow occurs

FINXS, FG, FX if the result is inexact or overflow occurred and overflow exceptions are
disabled
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RM0004
efscfsf
Scalar SPFP APU
efscfsf
User
Convert Floating-Point from Signed Fraction
efscfsf
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
0
1
1
rD32:63CnvtI32ToFP32Sat(rB32:63, SIGN, LOWER, F)
The signed fractional value in rB is converted to the nearest single-precision floating-point
value using the current rounding mode and placed into rD.
The following status bits are set in the SPEFSCR:

FINXS, FG, FX if the result is inexact
efscfsi
Scalar SPFP APU
efscfsi
User
Convert Floating-Point from Signed Integer
efscfsi
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
0
0
1
rD32:63CnvtSI32ToFP32Sat(rB32:63, SIGN, LOWER, I)
The signed integer value in rB is converted to the nearest single-precision floating-point
value using the current rounding mode and placed into rD.
The following status bits are set in the SPEFSCR:

FINXS, FG, FX if the result is inexact
efscfuf
Scalar SPFP APU
efscfuf
User
Convert Floating-Point from Unsigned Fraction
efscfuf
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
0
1
0
rD32:63CnvtI32ToFP32Sat(rB32:63, UNSIGN, LOWER, F)
The unsigned fractional value in rB is converted to the nearest single-precision floating-point
value using the current rounding mode and placed into rD.
The following status bits are set in the SPEFSCR:

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Instruction set
efscfui
Scalar SPFP APU
efscfui
User
Convert Floating-Point from Unsigned Integer
efscfui
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
0
0
0
rD32:63CnvtI32ToFP32Sat(rB32:63, UNSIGN, LOWER, I)
The unsigned integer value in rB is converted to the nearest single-precision floating-point
value using the current rounding mode and placed into rD.
The following status bits are set in the SPEFSCR:

FINXS, FG, FX if the result is inexact
efscmpeq
Scalar SPFP APU
efscmpeq
User
Floating-Point Compare Equal
efscmpeq
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
8
crD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
0
1
1
1
0
alrA32:63
blrB32:63
if (al = bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
The value in rA is compared against rB. If rA equals rB, the crD bit is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = –0).
If either operand contains a NaN, infinity, or a denorm and floating-point invalid exceptions
are enabled in the SPEFSCR, the exception is taken. If the exception is not enabled, the
comparison treats NaNs, infinities, and denorms as normalized numbers.
The following status bits are set in SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm or NaN
efscmpgt
Scalar SPFP APU
efscmpgt
User
Floating-Point Compare Greater Than
efscmpgt
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
0
1
1
0
0
alrA32:63
blrB32:63
if (al > bl) then cl1
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else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
The value in rA is compared against rB. If rA is greater than rB, the bit in the crD is set,
otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –0).
If either operand contains a NaN, infinity, or a denorm and floating-point invalid exceptions
are enabled in the SPEFSCR, the exception is taken. If the exception is not enabled, the
comparison treats NaNs, infinities, and denorms as normalized numbers.
The following status bits are set in SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm or NaN
efscmplt
Scalar SPFP APU
efscmplt
User
Floating-Point Compare Less Than
efscmplt
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
8
crD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
0
1
1
0
1
alrA32:63
blrB32:63
if (al < bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
The value in rA is compared against rB. If rA is less than rB, the bit in the crD is set,
otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –0).
If either operand contains a NaN, infinity, or a denorm and floating-point invalid exceptions
are enabled in the SPEFSCR, the exception is taken. If the exception is not enabled, the
comparison treats NaNs, infinities, and denorms as normalized numbers.
The following status bits are set in SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm or NaN
efsctsf
Scalar SPFP APU
efsctsf
User
Convert Floating-Point to Signed Fraction
efsctsf
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
1
1
1
rD32:63CnvtFP32ToISat(rB32:63, SIGN, LOWER, ROUND, F)
The single-precision floating-point value in rB is converted to a signed fraction using the
current rounding mode. The result saturates if it cannot be represented in a 32-bit fraction.
NaNs are converted to 0.
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Instruction set
The following status bits are set in the SPEFSCR:

FINV if the contents of rB are +infinity., –infinity, denorm, or NaN, or rB cannot be
represented in the target format

FINXS, FG, FX if the result is inexact
efsctsi
Scalar SPFP APU
efsctsi
User
Convert Floating-Point to Signed Integer
efsctsi
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
1
0
1
rD32:63CnvtFP32ToISat(rB32:63, SIGN, LOWER, ROUND, I)
The single-precision floating-point value in rB is converted to a signed integer using the
current rounding mode. The result saturates if it cannot be represented in a 32-bit integer.
NaNs are converted to 0.
The following status bits are set in the SPEFSCR:

FINV if the contents of rB are +infinity, –infinity, denorm, or NaN, or rB cannot be
represented in the target format

FINXS, FG, FX if the result is inexact
efsctsiz
Scalar SPFP APU
efsctsiz
User
Convert Floating-Point to Signed Integer with Round toward Zero
efsctsiz
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
1
0
1
0
rD32–63CnvtFP32ToISat(rB32:63, SIGN, LOWER, TRUNC, I)
The single-precision floating-point value in rB is converted to a signed integer using the
rounding mode Round towards Zero. The result saturates if it cannot be represented in a
32-bit integer. NaNs are converted to 0.
efsctuf
Scalar SPFP APU
efsctuf
User
Convert Floating-Point to Unsigned Fraction
efsctuf
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
1
1
0
rD32:63CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, ROUND, F)
The single-precision floating-point value in rB is converted to an unsigned fraction using the
current rounding mode. The result saturates if it cannot be represented in a 32-bit unsigned
fraction. NaNs are converted to 0.
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The following status bits are set in the SPEFSCR:

FINV if the contents of rB are +infinity, –infinity, denorm, or NaN, or rB cannot be
represented in the target format

FINXS, FG, FX if the result is inexact
efsctui
Scalar SPFP APU
efsctui
User
Convert Floating-Point to Unsigned Integer
efsctui
0
1
2
3
4
5
0
0
0
1
0
0
rD,rB
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
0
1
0
0
rD32:63CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, ROUND, I)
The single-precision floating-point value in rB is converted to an unsigned integer using the
current rounding mode. The result saturates if it cannot be represented in a 32-bit unsigned
integer. NaNs are converted to 0.
The following status bits are set in the SPEFSCR:

FINV if the contents of rB are +infinity, –infinity, denorm, or NaN, or rB cannot be
represented in the target format

FINXS, FG, FX if the result is inexact
efsctuiz
Scalar SPFP APU
efsctuiz
User
Convert Floating-Point to Unsigned Integer with Round toward Zero
efsctuiz
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
0
1
0
1
1
0
1
1
0
0
0
rD32:63CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, TRUNC, I)
The single-precision floating-point value in rB is converted to an unsigned integer using the
rounding mode Round toward Zero. The result saturates if it cannot be represented in a 32bit unsigned integer. NaNs are converted to 0.
The following status bits are set in the SPEFSCR:
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
FINV if the contents of rB are +infinity, –infinity, denorm, or NaN, or rB cannot be
represented in the target format

FINXS, FG, FX if the result is inexact
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Instruction set
efsdiv
Scalar SPFP APU
efsdiv
User
Floating-Point Divide
efsdiv
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
1
1
0
0
1
0
0
1
rD32:63rA32:63 sp rB32:63
The single-precision floating-point value in rA is divided by rB and the result is stored in rD.
If an overflow is detected, or rB is a denorm (or 0 value), or rA is a NaN or Infinity and rB is
a normalized number, the result is an appropriately signed maximum floating-point value.
If an underflow is detected or rB is a NaN or Infinity, the result is an appropriately signed
floating-point 0.
The following status bits are set in the SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm, or NaN

FOFV if an overflow occurs

FUNV if an underflow occurs

FDBZS, FDBZ if a divide by zero occurs

FINXS, FG, FX if the result is inexact or overflow occurred and overflow exceptions are
disabled
efsmul
Scalar SPFP APU
efsmul
User
Floating-Point Multiply
efsmul
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
0
1
1
0
0
1
0
0
0
rD32:63rA32:63 sp rB32:63
The single-precision floating-point value in rA is multiplied by rB and the result is stored in
rD.
If an overflow is detected the result is an appropriately signed maximum floating-point value.
If one of rA or rB is a NaN or an Infinity and the other is not a denorm or zero, the result is an
appropriately signed maximum floating-point value.
If an underflow is detected, or rA or rB is a denorm, the result is an appropriately signed
floating-point 0.
The following status bits are set in the SPEFSCR:

FINV if the contents of rA or rB are +infinity, –infinity, denorm, or NaN

FOFV if an overflow occurs

FUNV if an underflow occurs

FINXS, FG, FX if the result is inexact or overflow occurred and overflow exceptions are
disabled
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Instruction set
RM0004
efsnabs
Scalar SPFP APU
efsnabs
User
Floating-Point Negative Absolute Value
efsnabs
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
rD32:630b1 || rA33:63
The sign bit of rA is set and the result is stored in rD. It is implementation dependent if
invalid values for rA (NaN, Denorm, Infinity) are detected and exceptions are taken.
efsneg
Scalar SPFP APU
efsneg
User
Floating-Point Negate
efsneg
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
rD32:63¬rA32 || rA33:63
The sign bit of rA is complemented and the result is stored in rD. It is implementation
dependent if invalid values for rA (NaN, Denorm, Infinity) are detected and exceptions are
taken.
efssub
Scalar SPFP APU
efssub
User
Floating-Point Subtract
efssub
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
0
1
1
0
0
0
0
0
1
rD32:63rA32:63 -sp rB32:63
The single-precision floating-point value in rB is subtracted from that in rA and the result is
stored in rD.
If an overflow condition is detected or the contents of rA or rB are NaN or Infinity, the result
is an appropriately signed maximum floating-point value.
If an underflow condition is detected, the result is an appropriately signed floating-point 0.
The following status bits are set in the SPEFSCR:
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
FINV if the contents of rA or rB are +infinity, –infinity, denorm, or NaN

FOFV if an overflow occurs

FUNF if an underflow occurs

FINXS, FG, FX if the result is inexact or overflow occurred and overflow exceptions are
disabled
DocID13694 Rev 2
RM0004
Instruction set
efststeq
Scalar SPFP APU
efststeq
User
Floating-Point Test Equal
efststeq
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
8
crD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
1
1
1
1
0
alrA32:63
blrB32:63
if (al = bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
The value in rA is compared against rB. If rA equals rB, the bit in crD is set, otherwise it is
cleared. Comparison ignores the sign of 0 (+0 = –0). The comparison treats NaNs, infinities,
and denorms as normalized numbers.
No exceptions are taken during execution of efststeq. If strict IEEE 754 compliance is
required, the program should use efscmpeq.
efststgt
Scalar SPFP APU
efststgt
User
Floating-Point Test Greater Than
efststgt
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
8
crD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
1
1
1
0
0
alrA32:63
blrB32:63
if (al > bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
If rA is greater than rB, the bit in crD is set, otherwise it is cleared. Comparison ignores the
sign of 0 (+0 = –0). The comparison treats NaNs, infinities, and denorms as normalized
numbers.
No exceptions are taken during the execution of efststgt. If strict IEEE 754 compliance is
required, the program should use efscmpgt.
efststlt
Scalar SPFP APU
efststlt
User
Floating-Point Test Less Than
efststlt
0
1
2
3
4
5
0
0
0
1
0
0
crD,rA,rB
6
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
1
1
0
1
1
1
0
1
alrA32:63
blrB32:63
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Instruction set
RM0004
if (al < bl) then cl1
else cl0
CR4*crD:4*crD+3undefined || cl || undefined || undefined
If rA is less than rB, the bit in the crD is set, otherwise it is cleared. Comparison ignores the
sign of 0 (+0 = –0). The comparison treats NaNs, infinities, and denorms as normalized
numbers.
No exceptions are taken during the execution of efststlt. If strict IEEE 754 compliance is
required, the program should use efscmplt.
eqv
Book E
eqv
User
Equivalent
eqv
eqv.
rA,rS,rB(Rc=0)
rA,rS,rB(Rc=1)
0
1
2
3
4
5
0
1
1
1
1
1
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rS
rA
result0:63  rS  rB
if Rc=1 then do
rB
0
1
0
0
0
1
1
1
0
0
Rc
LT  result32:63 < 0
GT  result32:63 > 0
EQ  result32:63 = 0
CR0  LT || GT || EQ || SO
rA  result
The contents of rS are XORed with the contents of rB and the one’s complement of the
result is placed into rA.
Other registers altered:

CR0 (if Rc=1)
evabs
SPE APU
evabs
User
Vector absolute value
evabs
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
rD0:31ABS(rA0:31)
rD32:63ABS(rA32:63)
The absolute value of each element of rA is placed in the corresponding elements of rD. An
absolute value of 0x8000_0000 (most negative number) returns 0x8000_0000. No overflow
is detected.
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DocID13694 Rev 2
RM0004
Instruction set
Figure 87. Vector absolute value (evabs)
0
31
32
63
rA
ABS
ABS
rD
evaddiw
SPE APU
evaddiw
User
Vector add immediate word
evaddiw
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB,UIMM
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UIMM
rB
0
rD0:31rB0:31 + EXTZ(UIMM
rD32:63rB32:63 + EXTZ(UIMM)
1
0
0
)
0
0
0
0
0
1
0
// Modulo sum
// Modulo sum
UIMM is zero-extended and added to both the high and low elements of rB and the results
are placed in rD. Note that the same value is added to both elements of the register. UIMM
is 5 bits.
Figure 88. Vector add immediate word (evaddiw)
0
31
32
63
rB
UIMM
UIMM
+
+
rD
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Instruction set
RM0004
evaddsmiaaw
SPE APU
evaddsmiaaw
User
Vector add signed, modulo, integer to accumulator word
evaddsmiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
1

rD0:31ACC0:31 + rA0:31
rD32:63ACC32:63 + rA32:63

ACC0:63rD0:63
Each word element in rA is added to the corresponding element in the accumulator and the
results are placed in rD and into the accumulator.
Other registers altered: ACC
Figure 89. Vector add signed, modulo, integer to accumulator word (evaddsmiaaw)
0
31
32
63
rA
Accumulator
+
+
rD and Accumulator
evaddssiaaw
SPE APU
evaddssiaaw
User
Vector add signed, saturate, integer to accumulator word
evaddssiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
0
0
0
0
0
1
0
0
1
1
0
// high
temp0:63 EXTS(ACC0:31) + EXTS(rA0:31)
ovh temp31  temp32
rD0:31 SATURATE(ovh, temp31, 0x80000000, 0x7fffffff, temp32:63)
// low
temp0:63 EXTS(ACC32:63) + EXTS(rA32:63)
ovl temp31  temp32
rD32:63 SATURATE(ovl, temp31, 0x80000000, 0x7fffffff, temp32:63)
418/1025
DocID13694 Rev 2
0
0
0
0
1
RM0004
Instruction set

ACC0:63 rD0:63

SPEFSCROVH ovh
SPEFSCROV ovl
SPEFSCRSOVH SPEFSCRSOVH | ovh
SPEFSCRSOV SPEFSCRSOV | ovl
Each signed integer word element in rA is sign-extended and added to the corresponding
sign-extended element in the accumulator, saturating if overflow or underflow occurs, and
the results are placed in rD and the accumulator. Any overflow or underflow is recorded in
the SPEFSCR overflow and summary overflow bits.
Other registers altered: SPEFSCR ACC
Figure 90. Vector add signed, saturate, integer to accumulator word (evaddssiaaw)
0
31
32
63
rA
Accumulator
+
+
rD and Accumulator
evaddumiaaw
SPE APU
evaddumiaaw
User
Vector add unsigned, modulo, integer to accumulator word
evaddumiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
1
0
0
1
1
0
0
1
0
0
0

rD0:31ACC0:31 + rA0:31
rD32:63ACC32:63 + rA32:63

ACC0:63rD0:63
Each unsigned integer word element in rA is added to the corresponding element in the
accumulator and the results are placed in rD and the accumulator.
Other registers altered: ACC
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Instruction set
RM0004
Figure 91. Vector add unsigned, modulo, integer to accumulator word (evaddumiaaw)
0
31
32
63
rA
Accumulator
+
+
rD and Accumulator
evaddusiaaw
SPE APU
evaddusiaaw
User
Vector add unsigned, saturate, integer to accumulator word
evaddusiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0

// high
temp0:63 EXTZ(ACC0:31) + EXTZ(rA0:31)
ovh temp31
rD0:31 SATURATE(ovh, temp31, 0xffffffff, 0xffffffff, temp32:63)
// low
temp0:63 EXTZ(ACC32:63) + EXTZ(rA32:63)
ovl temp31
rD32:63 SATURATE(ovl, temp31, 0xffffffff, 0xffffffff, temp32:63)

ACC0:63 rD0:63

SPEFSCROVH ovh
SPEFSCROV ovl
SPEFSCRSOVH SPEFSCRSOVH | ovh
SPEFSCRSOV SPEFSCRSOV | ovl
Each unsigned integer word element in rA is zero-extended and added to the corresponding
zero-extended element in the accumulator, saturating if overflow occurs, and the results are
placed in rD and the accumulator. Any overflow is recorded in the SPEFSCR overflow and
summary overflow bits.
Other registers altered: SPEFSCR ACC
420/1025
DocID13694 Rev 2
RM0004
Instruction set
Figure 92. Vector add unsigned, saturate, integer to accumulator word (evaddusiaaw)
0
31
32
63
rA
Accumulator
+
+
rD and Accumulator
evaddw
SPE APU
evaddw
User
Vector add word
evaddw
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
rD0:31rA0:31 + rB0:31
rD32:63rA32:63 + rB32:63
0
0
0
0
0
0
0
0
// Modulo sum
// Modulo sum
The corresponding elements of rA and rB are added and the results are placed in rD. The
sum is a modulo sum.
Figure 93. Vector add word (evaddw)
0
31
32
63
rA
rB
+
+
rD
DocID13694 Rev 2
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Instruction set
RM0004
evand
SPE APU
evand
User
Vector AND
evand
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
rD0:31rA0:31 & rB0:31
rD32:63rA32:63 & rB32:63
0
0
1
0
0
0
1
// Bitwise AND
// Bitwise AND
The corresponding elements of rA and rB are ANDed bitwise and the results are placed in
the corresponding element of rD.
Figure 94. Vector AND (evand)
0
31
32
63
rA
rB
&
&
rD
evandc
SPE APU
evandc
User
Vector AND with complement
evandc
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
rD0:31rA0:31 & (¬rB0:31)
rD32:63rA32:63 & (¬rB32:63)
0
1
0
0
0
0
1
0
0
1
0
// Bitwise ANDC
// Bitwise ANDC
The word elements of rA and are ANDed bitwise with the complement of the corresponding
elements of rB. The results are placed in the corresponding element of rD.
422/1025
DocID13694 Rev 2
RM0004
Instruction set
Figure 95. Vector AND with complement (evandc)
0
31
32
63
rA
rB
¬
¬
AND
AND
rD
evcmpeq
SPE APU
Vector compare equal
evcmpeq
0
1
2
3
4
5
0
0
0
1
0
0
6
7
crD
8
evcmpeq
User
crD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
0
0
1
1
0
1
0
0
ahrA0:31
alrA32:63
bhrB0:31
blrB32:63
if (ah = bh) then ch1
else ch0
if (al = bl) then cl1
else cl0
CR4*crD:4*crD+3ch || cl || (ch | cl) || (ch & cl)
The most significant bit in crD is set if the high-order element of rA is equal to the high-order
element of rB; it is cleared otherwise. The next bit in crD is set if the low-order element of rA
is equal to the low-order element of rB and cleared otherwise. The last two bits of crD are
set to the OR and AND of the result of the compare of the high and low elements.
DocID13694 Rev 2
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Instruction set
RM0004
Figure 96. Vector Compare Equal (evcmpeq)
0
31
32
63
rA
rB
=
=
crD
OR
AND
evcmpgts
SPE APU
evcmpgts
User
Vector compare greater than signed
evcmpgts
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
0
0
1
1
0
0
0
1
ahrA0:31
alrA32:63
bhrB0:31
blrB32:63
if (ah > bh) then ch1
else ch0
if (al > bl) then cl1
else cl0
CR4*crD:4*crD+3ch || cl || (ch | cl) || (ch & cl)
The most significant bit in crD is set if the high-order element of rA is greater than the highorder element of rB; it is cleared otherwise. The next bit in crD is set if the low-order element
of rA is greater than the low-order element of rB and cleared otherwise. The last two bits of
crD are set to the OR and AND of the result of the compare of the high and low elements.
424/1025
DocID13694 Rev 2
RM0004
Instruction set
Figure 97. Vector compare greater than signed (evcmpgts)
0
31
32
63
rA
rB
>
>
crD
OR
AND
evcmpgtu
SPE APU
evcmpgtu
User
Vector compare greater than unsigned
evcmpgtu
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
0
0
1
1
0
0
0
0
ahrA0:31
alrA32:63
bhrB0:31
blrB32:63
if (ah >U bh) then ch1
else ch0
if (al >U bl) then cl1
else cl0
CR4*crD:4*crD+3ch || cl || (ch | cl) || (ch & cl)
The most significant bit in crD is set if the high-order element of rA is greater than the highorder element of rB; it is cleared otherwise. The next bit in crD is set if the low-order element
of rA is greater than the low-order element of rB and cleared otherwise. The last two bits of
crD are set to the OR and AND of the result of the compare of the high and low elements.
DocID13694 Rev 2
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666
Instruction set
RM0004
Figure 98. Vector compare greater than unsigned (evcmpgtu)
0
31
32
63
rA
rB
>
>
crD
OR
AND
evcmplts
SPE APU
evcmplts
User
Vector compare less than signed
evcmplts
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
0
0
1
1
0
0
1
1
ahrA0:31
alrA32:63
bhrB0:31
blrB32:63
if (ah < bh) then ch1
else ch0
if (al < bl) then cl1
else cl0
CR4*crD:4*crD+3ch || cl || (ch | cl) || (ch & cl)
The most significant bit in crD is set if the high-order element of rA is less than the highorder element of rB; it is cleared otherwise. The next bit in crD is set if the low-order element
of rA is less than the low-order element of rB and cleared otherwise. The last two bits of crD
are set to the OR and AND of the result of the compare of the high and low elements.
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RM0004
Instruction set
Figure 99. Vector compare less than signed (evcmplts)
0
31
32
63
rA
rB
<
<
crD
OR
AND
evcmpltu
SPE APU
evcmpltu
User
Vector compare less than unsigned
evcmpltu
0
1
2
3
4
5
0
0
0
1
0
0
6
crD,rA,rB
7
crD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
0
1
0
0
0
1
1
0
0
1
0
ahrA0:31
alrA32:63
bhrB0:31
blrB32:63
if (ah <U bh) then ch1
else ch0
if (al <U bl) then cl1
else cl0
CR4*crD:4*crD+3ch || cl || (ch | cl) || (ch & cl)
The most significant bit in crD is set if the high-order element of rA is less than the highorder element of rB; it is cleared otherwise. The next bit in crD is set if the low-order element
of rA is less than the low-order element of rB and cleared otherwise. The last two bits of crD
are set to the OR and AND of the result of the compare of the high and low elements.
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Instruction set
RM0004
Figure 100. Vector compare less than unsigned (evcmpltu)
0
31
32
63
rA
rB
<
<
crD
OR
AND
evcntlsw
SPE APU
evcntlsw
User
Vector count leading signed bits word
evcntlsw
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
The leading sign bits in each element of rA are counted, and the respective count is placed
into each element of rD.
evcntlzw is used for unsigned operands; evcntlsw is used for signed operands.
Figure 101. Vector count leading signed bits word (evcntlsw)
0
31
ssss_sss...
32
ssss_sss...
count of leading signed bits
63
rA
count of leading signed bits
rD
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RM0004
Instruction set
evcntlzw
SPE APU
evcntlzw
User
Vector count leading zeros word
evcntlzw
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
1
The leading zero bits in each element of rA are counted, and the respective count is placed
into each element of rD.
Figure 102. Vector count leading zeros word (evcntlzw)
0
31
0000_000...
32
63
rA
0000_000...
count of leading zeros
count of leading zeros
rD
evdivws
SPE APU
evdivws
User
Vector divide word signed
evdivws
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
0
1
1
0
0
0
1
1
0
dividendhrA0:31
dividendlrA32:63
divisorhrB0:31
divisorlrB32:63
rD0:31dividendh divisorh
rD32:63dividendl divisorl
ovh0
ovl0
if ((dividendh < 0) & (divisorh = 0)) then
rD0:310x80000000
ovh1
else if ((dividendh >= 0) & (divisorh = 0)) then
rD0:310x7FFFFFFF
ovh1
else if ((dividendh = 0x80000000) & (divisorh = 0xFFFF_FFFF)) then
rD0:310x7FFFFFFF
ovh1
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Instruction set
RM0004
if ((dividendl < 0) & (divisorl = 0)) then
rD32:630x80000000
ovl1
else if ((dividendl >= 0) & (divisorl = 0)) then
rD32:630x7FFFFFFF
ovl1
else if ((dividendl = 0x80000000) & (divisorl = 0xFFFF_FFFF)) then
rD32:630x7FFFFFFF
ovl1
SPEFSCROVHovh
SPEFSCROVovl
SPEFSCRSOVHSPEFSCRSOVH | ovh
SPEFSCRSOVSPEFSCRSOV | ovl
The two dividends are the two elements of the contents of rA. The two divisors are the two
elements of the contents of rB. The resulting two 32-bit quotients on each element are
placed into rD. The remainders are not supplied. The operands and quotients are
interpreted as signed integers. If overflow, underflow, or divide by zero occurs, the overflow
and summary overflow SPEFSCR bits are set. Note that any overflow indication is always
set as a side effect of this instruction. No form is defined that disables the setting of the
overflow bits. In case of overflow, a saturated value is delivered into the destination register.
Figure 103. Vector divide word signed (evdivws)
0
31
32
63
rA (dividends)
rB (divisors)
rA/rB
rA/rB
rD
evdivwu
SPE APU
evdivwu
User
Vector divide word unsigned
evdivwu
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
dividendhrA0:31
dividendl  rA32:63
divisorh  rB0:31
divisorl  rB32:63
rD0:31  dividendh divisorh
rD32:63  dividendl divisorl
ovh  0
ovl  0
if (divisorh = 0) then
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1
0
0
1
1
0
0
0
1
1
1
RM0004
Instruction set
rD0:31 = 0xFFFFFFFF
ovh  1
if (divisorl = 0) then
rD32:63  0xFFFFFFFF
ovl  1
SPEFSCROVH  ovh
SPEFSCROV  ovl
SPEFSCRSOVH  SPEFSCRSOVH | ovh
SPEFSCRSOV  SPEFSCRSOV | ovl
The two dividends are the two elements of the contents of rA. The two divisors are the two
elements of the contents of rB. Two 32-bit quotients are formed as a result of the division on
each of the high and low elements and the quotients are placed into rD. Remainders are not
supplied. Operands and quotients are interpreted as unsigned integers. If a divide by zero
occurs, the overflow and summary overflow SPEFSCR bits are set. Note that any overflow
indication is always set as a side effect of this instruction. No form is defined that disables
the setting of the overflow bits. In case of overflow, a saturated value is delivered into the
destination register.
Figure 104. Vector divide word unsigned (evdivwu)
0
31
32
63
rA (dividends)
rB (divisors)
rArB
rArB
rD
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Instruction set
RM0004
eveqv
SPE APU
eveqv
User
Vector equivalent
eveqv
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
rD0:31  rA0:31  rB0:31
rD32:63  rA32:63  rB32:63
0
0
1
1
0
0
1
// Bitwise XNOR
// Bitwise XNOR
The corresponding elements of rA & rB are XNORed bitwise, & the results are placed in rD.
Figure 105. Vector equivalent (eveqv)
0
31
32
63
rA
rB
XNOR
XNOR
rD
evextsb
SPE APU
evextsb
User
Vector extend sign byte
evextsb
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
rD0:31  EXTS(rA24:31)
rD32:63  EXTS(rA56:63)
The signs of the byte in each of the elements in rA are extended, and the results are placed
in rD.
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RM0004
Instruction set
Figure 106. Vector extend sign byte (evextsb)
0
23 24
31 32
55 56 57
s
ssss_ssss_ssss_ssss_ssss_ssss
s
evextsh
ssss_ssss_ssss_ssss_ssss_ssss
SPE APU
63
s
rA
s
rD
evextsh
User
Vector extend sign half word
evextsh
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
rD0:31  EXTS(rA16:31)
rD32:63  EXTS(rA48:63)
The signs of the half words in each of the elements in rA are extended, and the results are
placed in rD.
Figure 107. Vector extend sign half word (evextsh)
0
15 16 17
31
32
47 48 49
s
ssss_ssss_ssss_ssss
s
ssss_ssss_ssss_ssss
s
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63
rA
rD
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Instruction set
RM0004
evfsabs
Vector SPFP APU
evfsabs
User
Vector floating-point single-precision absolute value
evfsabs
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
0
rD0:31  0b0 || rA1:31
rD32:63  0b0 || rA33:63
The sign bit of each element in rA is set to 0 and the results are placed into rD.
Exceptions:
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the computation. If the implementation does not detect exceptions, or if exception
detection is disabled, the computation can be carried out in one of two ways, as a sign bit
operation ignoring the rest of the contents of the source register, or by examining the input
and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: if
the contents of either element of rA are Infinity, Denorm, or NaN, SPEFSCR[FINV,FINVH]
are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are cleared appropriately. If floatingpoint invalid input exceptions are enabled, an interrupt is taken and the destination register
is not updated.
evfsadd
Vector SPFP APU
evfsadd
User
Vector floating-point single-precision add
evfsadd
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
0
1
0
0
0
0
0
0
0
rD0:31  rA0:31 +sp rB0:31
rD32:63  rA32:63 +sp rB32:63
Each single-precision floating-point element of rA is added to the corresponding element of
rB and the results are stored in rD. If an element of rA is NaN or infinity, the corresponding
result is either pmax (asign==0), or nmax (asign==1). Otherwise, if an element of rB is NaN
or infinity, the corresponding result is either pmax (bsign==0), or nmax (bsign==1).
Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the
corresponding element of rD. If an underflow occurs, +0 (for rounding modes RN, RZ, RP)
or –0 (for rounding mode RM) is stored in the corresponding element of rD.
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken and the destination
register is not updated. Otherwise, if an overflow occurs, SPEFSCR[FOVF,FOVFH] are set
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RM0004
Instruction set
appropriately, or if an underflow occurs, SPEFSCR[FUNF,FUNFH] are set appropriately. If
either underflow or overflow exceptions are enabled and a corresponding status bit is set,
an interrupt is taken. If any of these interrupts are taken, the destination register is not
updated.
If either result element of this instruction is inexact, or overflows but overflow exceptions are
disabled, and no other interrupt is taken, or underflows but underflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS,FINXSH] is set. If the floatingpoint inexact exception is enabled, an interrupt is taken using the floating-point round
interrupt vector. In this case, the destination register is updated with the truncated result(s).
The FG and FX bits are properly updated to allow rounding to be performed in the interrupt
handler.
FG and FX (FGH and FXH) are cleared if an overflow or underflow interrupt is taken, or if an
invalid operation/input error is signaled for the low (high) element (regardless of FINVE).
evfscfsf
Vector SPFP APU
evfscfsf
User
Vector convert floating-point single-precision from signed fraction
evfscfsf
rD,rB
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0011

rD0:31CnvtI32ToFP32Sat(rB0:31, SIGN, UPPER, F)
rD32:63CnvtI32ToFP32Sat(rB32:63, SIGN, LOWER, F)
Each signed fractional element of rB is converted to a single-precision floating-point value
using the current rounding mode and the results are placed into the corresponding elements
of rD.
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversions
are not exact. If the floating-point inexact exception is enabled, an interrupt is taken using
the floating-point round interrupt vector. In this case, the destination register is updated with
the truncated result(s). The FGH, FXH, FG and FX bits are properly updated to allow
rounding to be performed in the interrupt handler.
evfscfsi
Vector SPFP APU
evfscfsi
User
Vector convert floating-point single-precision from signed integer
evfscfsi
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0001
rD0:31CnvtSI32ToFP32Sat(rB0:31, SIGN, UPPER, I)
rD32:63CnvtSI32ToFP32Sat(rB32:63, SIGN, LOWER, I)
Each signed integer element of rB is converted to the nearest single-precision floating-point
value using the current rounding mode and the results are placed into the corresponding
element of rD.
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Instruction set
RM0004
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversions
are not exact. If the floating-point inexact exception is enabled, an interrupt is taken using
the floating-point round interrupt vector. In this case, the destination register is updated with
the truncated result(s). The FGH, FXH, FG and FX bits are properly updated to allow
rounding to be performed in the interrupt handler.
evfscfuf
Vector SPFP APU
evfscfuf
User
Vector convert floating-point single-precision from unsigned fraction
evfscfuf
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0010

rD0:31CnvtI32ToFP32Sat(rB0:31, UNSIGN, UPPER, F)
rD32:63CnvtI32ToFP32Sat(rB32:63, UNSIGN, LOWER, F)
Each unsigned fractional element of rB is converted to a single-precision floating-point value
using the current rounding mode and the results are placed into the corresponding elements
of rD.
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversions
are not exact. If the floating-point inexact exception is enabled, an interrupt is taken using
the floating-point round interrupt vector. In this case, the destination register is updated with
the truncated result(s). The FGH, FXH, FG and FX bits are properly updated to allow
rounding to be performed in the interrupt handler.
evfscfui
Vector SPFP APU
evfscfui
User
Vector convert floating-point single-precision from unsigned integer
evfscfui
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0000

rD0:31CnvtI32ToFP32Sat(rB031, UNSIGN, UPPER, I)
rD32:63CnvtI32ToFP32Sat(rB32:63, UNSIGN, LOWER, I)
Each unsigned integer element of rB is converted to the nearest single-precision floatingpoint value using the current rounding mode and the results are placed into the
corresponding elements of rD.
Exceptions:
This instruction can signal an inexact status and set SPEFSCR[FINXS] if the conversions
are not exact. If the floating-point inexact exception is enabled, an interrupt is taken using
the floating-point round interrupt vector. In this case, the destination register is updated with
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RM0004
Instruction set
the truncated result(s). The FGH, FXH, FG and FX bits are properly updated to allow
rounding to be performed in the interrupt handler.
evfscmpeq
Vector SPFP APU
evfscmpeq
User
Vector floating-point single-precision compare equal
evfscmpeq
0
1
2
3
4
5
0
0
0
1
0
0
6
7
crfD,rA,rB
8
crfD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1000 1110
ah  rA0:31
al  rA32:63
bh  rB0:31
bl  rB32:63
if (ah = bh) then ch  1
else ch  0
if (al = bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
Each element of rA is compared against the corresponding element of rB. If rA equals rB,
the crfD bit is set, otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –0).
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If floating-point invalid input exceptions are enabled, an interrupt is
taken, and the condition register is not updated. Otherwise, the comparison proceeds after
treating NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’ and
‘f’ directly.
evfscmpgt
Vector SPFP APU
evfscmpgt
User
Vector floating-point single-precision compare greater than
evfscmpgt
0
1
2
3
4
5
0
0
0
1
0
0
6
7
crfD
crfD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1000 1100
ah  rA0:31
al  rA32:63
bh  rB0:31
bl  rB32:63
if (ah > bh) then ch  1
else ch  0
if (al > bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
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Instruction set
RM0004
Each element of rA is compared against the corresponding element of rB. If rA is greater
than rB, the bit in the crfD is set, otherwise it is cleared. Comparison ignores the sign of 0
(+0 = –0).
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If floating-point invalid input exceptions are enabled then an interrupt
is taken, and the condition register is not updated. Otherwise, the comparison proceeds
after treating NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’
and ‘f’ directly.
evfscmplt
Vector SPFP APU
User
evfscmplt
Vector floating-point single-precision compare less than
evfscmplt
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
crfD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1000 1101
ah  rA0:31
al  rA32:63
bh  rB0:31
bl  rB32:63
if (ah < bh) then ch  1
else ch  0
if (al < bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
Each element of rA is compared against the corresponding element of rB. If rA is less than
rB, the bit in the crfD is set, otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –
0).
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If floating-point invalid input exceptions are enabled then an interrupt
is taken, and the condition register is not updated. Otherwise, the comparison proceeds
after treating NaNs, Infinities, and Denorms as normalized numbers, using their values of ‘e’
and ‘f’ directly.
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Instruction set
evfsctsf
Vector SPFP APU
evfsctsf
User
Vector convert floating-point single-precision to signed fraction
evfsctsf
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0111
rD0:31  CnvtFP32ToISat(rB0:31, SIGN, UPPER, ROUND, F)
rD32:63  CnvtFP32ToISat(rB32:63, SIGN, LOWER, ROUND, F)
Each single-precision floating-point element in rB is converted to a signed fraction using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit
signed fraction. NaNs are converted as though they were zero.
Exceptions:
If either element of rB is Infinity, Denorm, or NaN, or if an overflow occurs,
SPEFSCR[FINV,FINVH] are set appropriately and SPEFSCR[FGH,FXH,FG,FX] are cleared
appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken, the destination register is not
updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsctsi
Vector SPFP APU
evfsctsi
User
Vector convert floating-point single-precision to signed integer
evfsctsi
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0101

rD0:31  CnvtFP32ToISat(rB0:31, SIGN, UPPER, ROUND, I)
rD32:63  CnvtFP32ToISat(rB32:63, SIGN, LOWER, ROUND, I)
Each single-precision floating-point element in rB is converted to a signed integer using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit
integer. NaNs are converted as though they were zero.
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RM0004
Exceptions:
If the contents of either element of rB are Infinity, Denorm, or NaN, or if an overflow occurs
on conversion, SPEFSCR[FINV,FINVH] are set appropriately, and
SPEFSCR[FGH,FXH,FG,FX] are cleared appropriately. If SPEFSCR[FINVE] is set, an
interrupt is taken, the destination register is not updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsctsiz
Vector SPFP APU
evfsctsiz
User
Vector convert floating-point single-precision to signed integer 
with round toward zero
evfsctsiz
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 1010
rD0:31  CnvtFP32ToISat(rB0:31, SIGN, UPPER, TRUNC, I)
rD32:63  CnvtFP32ToISat(rB32:63, SIGN, LOWER, TRUNC, I)
Each single-precision floating-point element in rB is converted to a signed integer using the
rounding mode Round toward Zero and the result is saturated if it cannot be represented in
a 32-bit integer. NaNs are converted as though they were zero.
Exceptions:
If either element of rB is Infinity, Denorm, or NaN, or if an overflow occurs,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken, the destination
register is not updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsctuf
Vector SPFP APU
evfsctuf
User
Vector convert floating-point single-precision to unsigned fraction
evfsctuf
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0110
rD0:31  CnvtFP32ToISat(rB0:31, UNSIGN, UPPER, ROUND, F)
rD32:63  CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, ROUND, F)
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Instruction set
Each single-precision floating-point element in rB is converted to an unsigned fraction using
the current rounding mode and the result is saturated if it cannot be represented in a 32-bit
fraction. NaNs are converted as though they were zero.
Exceptions:
If either element of rB is Infinity, Denorm, or NaN, or if an overflow occurs,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken, the destination
register is not updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsctui
Vector SPFP APU
evfsctui
User
Vector convert floating-point single-precision to unsigned integer
evfsctui
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
010 1001 0100
rD0:31  CnvtFP32ToISat(rB0:31, UNSIGN, UPPER, ROUND, I)
rD32:63  CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, ROUND, I)
Each single-precision floating-point element in rB is converted to an unsigned integer using
the current rounding mode and the result is saturated if it cannot be represented in a 32-bit
integer. NaNs are converted as though they were zero.
Exceptions:
If either element of rB is Infinity, Denorm, or NaN, or if an overflow occurs,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken, the destination
register is not updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsctuiz
Vector SPFP APU
User
evfsctuiz
Vector convert floating-point single-precision to unsigned integer with round toward
zero
evfsctuiz
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
0
0
0
rB
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Instruction set
RM0004
rD0:31  CnvtFP32ToISat(rB0:31, UNSIGN, UPPER, TRUNC, I)
rD32:63  CnvtFP32ToISat(rB32:63, UNSIGN, LOWER, TRUNC, I)
Each single-precision floating-point element in rB is converted to an unsigned integer using
the rounding mode Round toward Zero and the result is saturated if it cannot be represented
in a 32-bit integer. NaNs are converted as though they were zero.
Exceptions:
If either element of rB is Infinity, Denorm, or NaN, or if an overflow occurs,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken, the destination
register is not updated, and no other status bits are set.
If either result element of this instruction is inexact and no other interrupt is taken,
SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, an interrupt is
taken using the floating-point round interrupt vector. In this case, the destination register is
updated with the truncated result. The FGH, FXH, FG and FX bits are properly updated to
allow rounding to be performed in the interrupt handler.
evfsdiv
Vector SPFP APU
evfsdiv
User
Vector floating-point single-precision divide
evfsdiv
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
0
1
0
0
0
1
0
0
1
rD0:31  rA0:31 sp rB0:31
rD32:63  rA32:63 sp rB32:63
Each single-precision floating-point element of rA is divided by the corresponding element
of rB and the result is stored in rD. If an element of rB is a NaN or infinity, the corresponding
result is a properly signed zero. Otherwise, if an element of rB is a zero (or a denormalized
number optionally transformed to zero by the implementation), or if an element of rA is
either NaN or infinity, the corresponding result is either pmax (asign==bsign), or nmax
(asign!=bsign). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in
the corresponding element of rD. If an underflow occurs, +0 or –0 (as appropriate) is stored
in the corresponding element of rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, or if both rA and rB are ±0,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken and the destination
register is not updated. Otherwise, if the content of rB is ±0 and the content of rA is a finite
normalized non-zero number, SPEFSCR[FDBZ,FDBZH] are set appropriately. If floatingpoint divide-by-zero exceptions are enabled, an interrupt is then taken. Otherwise, if an
overflow occurs, SPEFSCR[FOVF,FOVFH] are set appropriately, or if an underflow occurs,
SPEFSCR[FUNF,FUNFH] are set appropriately. If either underflow or overflow exceptions
are enabled and a corresponding bit is set, an interrupt is taken. If any of these interrupts
are taken, the destination register is not updated.
If either result element of this instruction is inexact, or overflows but overflow exceptions are
disabled, and no other interrupt is taken, or underflows but underflow exceptions are
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Instruction set
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result(s). The FG
and FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX (FGH and FXH) are cleared if an overflow or underflow interrupt is taken, or if an
invalid operation/input error is signaled for the low (high) element (regardless of FINVE).
evfsmul
Vector SPFP APU
evfsmul
User
Vector floating-point single-precision multiply
evfsmul
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
0
1
0
0
0
1
0
0
0
rD0:31  rA0:31 sp rB0:31
rD32:63  rA32:63 sp rB32:63
Each single-precision floating-point element of rA is multiplied with the corresponding
element of rB and the result is stored in rD. If an element of rA or rB are either zero (or a
denormalized number optionally transformed to zero by the implementation), the
corresponding result is a properly signed zero. Otherwise, if an element of rA or rB are
either NaN or infinity, the corresponding result is either pmax (asign==bsign), or nmax
(asign!=bsign). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in
the corresponding element of rD. If an underflow occurs, +0 or –0 (as appropriate) is stored
in the corresponding element of rD.
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken and the destination
register is not updated. Otherwise, if an overflow occurs, SPEFSCR[FOVF,FOVFH] are set
appropriately, or if an underflow occurs, SPEFSCR[FUNF,FUNFH] are set appropriately. If
either underflow or overflow exceptions are enabled and a corresponding status bit is set,
an interrupt is taken. If any of these interrupts are taken, the destination register is not
updated.
If either result element of this instruction is inexact, or overflows but overflow exceptions are
disabled, and no other interrupt is taken, or underflows but underflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result(s). The FG
and FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX (FGH and FXH) are cleared if an overflow or underflow exception is taken, or if
an invalid operation/input error is signaled for the low (high) element (regardless of FINVE).
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RM0004
evfsnabs
Vector SPFP APU
evfsnabs
User
Vector floating-point single-precision negative absolute value
evfsnabs
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
rD0:31  0b1 || rA1:31
rD32:63  0b1 || rA33:63
The sign bit of each element in rA is set to 1 and the results are placed into rD.
Exceptions:
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the sign bit operation. If the implementation does not detect exceptions, or if
exception detection is disabled, the computation can be carried out in one of two ways, as a
sign bit operation ignoring the rest of the contents of the source register, or by examining the
input and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: if
the contents of either element of rA are Infinity, Denorm, or NaN, SPEFSCR[FINV,FINVH]
are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are cleared appropriately. If floatingpoint invalid input exceptions are enabled then an interrupt is taken, and the destination
register is not updated.
evfsneg
Vector SPFP APU
evfsneg
User
Vector floating-point single-precision negate
evfsneg
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
0
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
rD0:31  ¬rA0 || rA1:31
rD32:63  ¬rA32 || rA33:63
The sign bit of each element in rA is complemented and the results are placed into rD.
Exceptions:
Exception detection for embedded floating-point absolute value operations is
implementation dependent. An implementation may choose to not detect exceptions and
carry out the sign bit operation. If the implementation does not detect exceptions, or if
exception detection is disabled, the computation can be carried out in one of two ways, as a
sign bit operation ignoring the rest of the contents of the source register, or by examining the
input and appropriately saturating the input prior to performing the operation.
If an implementation chooses to handle exceptions, the exception is handled as follows: if
the contents of either element of rA are Infinity, Denorm, or NaN, SPEFSCR[FINV,FINVH]
are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are cleared appropriately. If floating-
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Instruction set
point invalid input exceptions are enabled then an interrupt is taken, and the destination
register is not updated.
evfssub
Vector SPFP APU
evfssub
User
Vector floating-point single-precision subtract
evfssub
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
1
0
0
0
0
0
0
1
rD0:31  rA0:31 -sp rB0:31
rD32:63  rA32:63 -sp rB32:63
Each single-precision floating-point element of rB is subtracted from the corresponding
element of rA and the results are stored in rD. If an element of rA is NaN or infinity, the
corresponding result is either pmax (asign==0), or nmax (asign==1). Otherwise, if an
element of rB is NaN or infinity, the corresponding result is either nmax (bsign==0), or pmax
(bsign==1). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored in the
corresponding element of rD. If an underflow occurs, +0 (for rounding modes RN, RZ, RP)
or –0 (for rounding mode RM) is stored in the corresponding element of rD.
Exceptions:
If the contents of either element of rA or rB are Infinity, Denorm, or NaN,
SPEFSCR[FINV,FINVH] are set appropriately, and SPEFSCR[FGH,FXH,FG,FX] are
cleared appropriately. If SPEFSCR[FINVE] is set, an interrupt is taken and the destination
register is not updated. Otherwise, if an overflow occurs, SPEFSCR[FOVF,FOVFH] are set
appropriately, or if an underflow occurs, SPEFSCR[FUNF,FUNFH] are set appropriately. If
either underflow or overflow exceptions are enabled and a corresponding status bit is set,
an interrupt is taken. If any of these interrupts are taken, the destination register is not
updated.
If either result element of this instruction is inexact, or overflows but overflow exceptions are
disabled, and no other interrupt is taken, or underflows but underflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point
inexact exception is enabled, an interrupt is taken using the floating-point round interrupt
vector. In this case, the destination register is updated with the truncated result(s). The FG
and FX bits are properly updated to allow rounding to be performed in the interrupt handler.
FG and FX (FGH and FXH) are cleared if an overflow or underflow interrupt is taken, or if an
invalid operation/input error is signaled for the low (high) element (regardless of FINVE).
evfststeq
Vector SPFP APU
User
evfststeq
Vector floating-point single-precision test equal
evfststeq
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
crfD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1001 1110
ah  rA0:31
al  rA32:63
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RM0004
bh  rB0:31
bl  rB32:63
if (ah = bh) then ch  1
else ch  0
if (al = bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
Each element of rA is compared against the corresponding element of rB. If rA equals rB,
the bit in crfD is set, otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –0). The
comparison proceeds after treating NaNs, Infinities, and Denorms as normalized numbers,
using their values of ‘e’ and ‘f’ directly.
No exceptions are taken during the execution of evfststeq. If strict IEEE 754 compliance is
required, the program should use evfscmpeq.
Implementation note: In an implementation, the execution of evfststeq is likely to be faster
than the execution of evfscmpeq.
evfststgt
Vector SPFP APU
User
evfststgt
Vector floating-point single-precision test greater than
evfststgt
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
crfD
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1001 1100
ah  rA0:31
al  rA32:63
bh  rB0:31
bl  rB32:63
if (ah > bh) then ch  1
else ch  0
if (al > bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
Each element of rA is compared against the corresponding element of rB. If rA is greater
than rB, the bit in crfD is set, otherwise it is cleared. Comparison ignores the sign of 0
(+0 = –0). The comparison proceeds after treating NaNs, Infinities, and Denorms as
normalized numbers, using their values of ‘e’ and ‘f’ directly.
No exceptions are taken during the execution of evfststgt. If strict IEEE 754 compliance is
required, the program should use evfscmpgt.
Implementation note: In an implementation, the execution of evfststgt is likely to be faster
than the execution of evfscmpgt.
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Instruction set
evfststlt
Vector SPFP APU
evfststlt
User
Vector floating-point single-precision test less than
evfststlt
0
1
2
3
4
5
0
0
0
1
0
0
6
crfD,rA,rB
7
8
crfD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
0
0
rA
rB
010 1001 1101
ah  rA0:31
al  rA32:63
bh  rB0:31
bl  rB32:63
if (ah < bh) then ch  1
else ch  0
if (al < bl) then cl  1
else cl  0
CR4*crD:4*crD+3  ch || cl || (ch | cl) || (ch & cl)
Each element of rA is compared with the corresponding element of rB. If rA is less than rB,
the bit in the crfD is set, otherwise it is cleared. Comparison ignores the sign of 0 (+0 = –0).
The comparison proceeds after treating NaNs, Infinities, and Denorms as normalized
numbers, using their values of ‘e’ and ‘f’ directly.
No exceptions are taken during the execution of evfststlt. If strict IEEE 754 compliance is
required, the program should use evfscmplt.
Implementation note: In an implementation, the execution of evfststlt is likely to be faster
than the execution of evfscmplt.
evldd
SPE, Vector SPFP, Scalar DPFP APUs
evldd
User
Vector load double word into double word
evldd
0
1
2
3
4
5
0
0
0
1
0
0
rD,d(rA)
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
UIMM(1)
0
1
1
0
0
0
0
0
0
0
1
1. d = UIMM * 8
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*8)
rD  MEM(EA, 8)
The double word addressed by EA is loaded from memory and placed in rD.
Figure 108 shows how bytes are loaded into rD as determined by the endian mode.
DocID13694 Rev 2
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Instruction set
RM0004
Figure 108. evldd results in big- and little-endian modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
h
g
f
e
d
c
b
a
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
evlddx
SPE, Vector SPFP, Scalar DPFP APUs
evlddx
User
Vector load double word into double word indexed
evlddx
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
0
0
0
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD  MEM(EA, 8)
The double word addressed by EA is loaded from memory and placed in rD.
Figure 109 shows how bytes are loaded into rD as determined by the endian mode.
Figure 109. evlddx results in big- and little-endian modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
h
g
f
e
d
c
b
a
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
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DocID13694 Rev 2
RM0004
Instruction set
evldh
SPE APU
evldh
User
Vector load double into four half words
evldh
0
1
2
3
4
5
0
0
0
1
0
0
rD,d(rA)
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UIMM(1)
rA
0
1
1
0
0
0
0
0
1
0
1
1. d = UIMM * 8
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*8)
rD0:15  MEM(EA, 2)
rD16:31  MEM(EA+2,2)
rD32:47  MEM(EA+4,2)
rD48:63  MEM(EA+6,2)
The double word addressed by EA is loaded from memory and placed in rD.
The Figure 110 shows how bytes are loaded into rD as determined by the endian mode.
Figure 110. evldh Results in Big- and Little-Endian Modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
b
a
d
c
f
e
h
g
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
evldhx
SPE APU
evldhx
User
Vector Load Double into Four Half Words Indexed
evldhx
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
1
0
0
0
0
0
1
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  MEM(EA, 2)
rD16:31  MEM(EA+2,2)
rD32:47  MEM(EA+4,2)
rD48:63  MEM(EA+6,2)
DocID13694 Rev 2
449/1025
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Instruction set
RM0004
The double word addressed by EA is loaded from memory and placed in rD.
Figure 111 shows how bytes are loaded into rD as determined by the endian mode.
Figure 111. evldhx results in big- and little-endian modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
b
a
d
c
f
e
h
g
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
evldw
SPE APU
evldw
User
Vector load double into two words
evldw
0
1
2
3
4
5
0
0
0
1
0
0
rD,d(rA)
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UIMM(1)
rA
0
1
1
0
0
0
0
0
0
1
1
1. d = UIMM * 8
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*8)
rD0:31  MEM(EA, 4)
rD32:63  MEM(EA+4, 4)
The double word addressed by EA is loaded from memory and placed in rD.
Figure 112 shows how bytes are loaded into rD as determined by the endian mode.
Figure 112. evldw results in big- and little-endian modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
d
c
b
a
h
g
f
e
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
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RM0004
Instruction set
evldwx
SPE APU
evldwx
User
Vector load double into two words indexed
evldwx
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
rD
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
1
0
0
0
0
0
0
1
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:31  MEM(EA, 4)
rD32:63  MEM(EA+4, 4)
The double word addressed by EA is loaded from memory and placed in rD.
Figure 113 shows how bytes are loaded into rD as determined by the endian mode.
Figure 113. evldwx results in big- and little-endian modes
Byte address
0
1
2
3
4
5
6
7
Memory
a
b
c
d
e
f
g
h
GPR in big endian
a
b
c
d
e
f
g
h
GPR in little endian
d
c
b
a
h
g
f
e
Implementation note: If the EA is not double-word aligned, an alignment exception occurs.
evlhhesplat
SPE APU
evlhhesplat
User
Vector load half word into half words even and splat
evlhhesplat
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,d(rA)
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
UIMM(1)
0
1
1
0
0
0
0
1
0
0
1
1. d = UIMM * 2
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*2)
rD0:15  MEM(EA,2)
rD16:31  0x0000
rD32:47  MEM(EA,2)
rD48:63  0x0000
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Instruction set
RM0004
The half word addressed by EA is loaded from memory and placed in the even half words of
each element of rD.
Figure 114 shows how bytes are loaded into rD as determined by the endian mode.
Figure 114. evlhhesplat results in big- and little-endian modes
Byte address
0
Memory
a
b
GPR in big endian
a
b
Z
Z
a
b
Z
Z
Z = zero
GPR in little endian
b
a
Z
Z
b
a
Z
Z
Z = zero
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlhhesplatx
SPE APU
evlhhesplatx
User
Vector load half word into half words even and splat indexed
evlhhesplatx
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
0
1
0
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  MEM(EA,2)
rD16:31  0x0000
rD32:47  MEM(EA,2)
rD48:63  0x0000
The half word addressed by EA is loaded from memory and placed in the even half words of
each element of rD.
Figure 115 shows how bytes are loaded into rD as determined by the endian mode.
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RM0004
Instruction set
Figure 115. evlhhesplatx results in big- and little-endian modes
Byte address
0
1
Memory
a
b
GPR in big endian
a
b
Z
Z
a
b
Z
Z
Z = zero
GPR in little endian
b
a
Z
Z
b
a
Z
Z
Z = zero
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlhhossplat
SPE APU
evlhhossplat
User
Vector load half word into half word odd signed and splat
evlhhossplat
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,d(rA)
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
UIMM(1)
rA
0
1
1
0
0
0
0
1
1
1
1
1. d = UIMM * 2
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*2)
rD0:31  EXTS(MEM(EA,2))
rD32:63  EXTS(MEM(EA,2))
The half word addressed by EA is loaded from memory and placed in the odd half words
sign extended in each element of rD.
Figure 116 shows how bytes are loaded into rD as determined by the endian mode.
Figure 116. evlhhossplat results in big- and little-endian modes
Byte address
0
1
Memory
a
b
GPR in big endian
S
S
a
b
S
S
a
b
S = sign
GPR in little endian
S
S
b
a
S
S
b
a
S = sign
In big-endian memory, the msb of a is sign extended. In little-endian memory, the msb of b is
sign extended.
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Instruction set
RM0004
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlhhossplatx
SPE APU
evlhhossplatx
User
Vector load half word into half word odd signed and splat indexed
evlhhossplatx
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
0
1
1
1
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:31  EXTS(MEM(EA,2))
rD32:63  EXTS(MEM(EA,2))
The half word addressed by EA is loaded from memory and placed in the odd half words
sign extended in each element of rD.
Figure 117 shows how bytes are loaded into rD as determined by the endian mode.
Figure 117. evlhhossplatx results in big- and little-endian modes
Byte address
0
1
Memory
a
b
GPR in big endian
S
S
a
b
S
S
a
b
S = sign
GPR in little endian
S
S
b
a
S
S
b
a
S = sign
In big-endian memory, the msb of a is sign extended. In little-endian memory, the msb of b is
sign extended.
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlhhousplat
SPE APU
evlhhousplat
User
Vector load half word into half word odd unsigned and splat
evlhhousplat
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,d(rA)
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
UIMM(1)
1. d = UIMM * 2
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*2)
rD0:15  0x0000
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0
1
1
0
0
0
0
1
1
0
1
RM0004
Instruction set
rD16:31  MEM(EA,2)
rD32:47  0x0000
rD48:63  MEM(EA,2)
The half word addressed by EA is loaded from memory and placed in the odd half words
zero extended in each element of rD.
Figure 118 shows how bytes are loaded into rD as determined by the endian mode.
Figure 118. evlhhousplat results in big- and little-endian modes
Byte address
0
1
Memory
a
b
GPR in big endian
Z
Z
a
b
Z
Z
a
b
Z = zero
GPR in little endian
Z
Z
b
a
Z
Z
b
a
Z = zero
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlhhousplatx
SPE APU
evlhhousplatx
User
Vector load half word into half word odd unsigned and splat indexed
evlhhousplatx
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
0
1
1
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  0x0000
rD16:31  MEM(EA,2)
rD32:47  0x0000
rD48:63  MEM(EA,2)
The half word addressed by EA is loaded from memory and placed in the odd half words
zero extended in each element of rD.
Figure 119 shows how bytes are loaded into rD as determined by the endian mode.
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Instruction set
RM0004
Figure 119. evlhhousplatx results in big- and little-endian modes
Byte address
0
1
Memory
a
b
GPR in big endian
Z
Z
a
b
Z
Z
a
b
Z = zero
GPR in little endian
Z
Z
b
a
Z
Z
b
a
Z = zero
Implementation note: If the EA is not half-word aligned, an alignment exception occurs.
evlwhe
SPE APU
evlwhe
User
Vector load word into two half words even
evlwhe
0
1
2
3
4
5
0
0
0
1
0
0
rD,d(rA)
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
UIMM(1)
rA
0
1
1
0
0
0
1
0
0
0
1. d = UIMM * 4
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*4)
rD0:15  MEM(EA,2)
rD16:31  0x0000
rD32:47  MEM(EA+2,2)
rD48:63  0x0000
The word addressed by EA is loaded from memory and placed in the even half words in
each element of rD.
Figure 120 shows how bytes are loaded into rD as determined by the endian mode.
Figure 120. evlwhe results in big- and little-endian modes
456/1025
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
Z
Z
c
d
Z
Z
Z = zero
GPR in little endian
b
a
Z
Z
d
c
Z
Z
Z = zero
DocID13694 Rev 2
1
RM0004
Instruction set
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhex
SPE APU
evlwhex
User
Vector load word into two half words even indexed
evlwhex
0
1
2
3
4
5
0
0
0
1
0
0
rD,rA,rB
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
1
0
0
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  MEM(EA,2)
rD16:31  0x0000
rD32:47  MEM(EA+2,2)
rD48:63  0x0000
The word addressed by EA is loaded from memory and placed in the even half words in
each element of rD.
Figure 121 shows how bytes are loaded into rD as determined by the endian mode.
Figure 121. evlwhex results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
Z
Z
c
d
Z
Z
Z = zero
GPR in little endian
b
a
Z
Z
d
c
Z
Z
Z = zero
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhos
SPE APU
evlwhos
User
Vector load word into two half words odd signed (with sign extension)
evlwhos
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,d(rA)
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
UIMM(1)
0
1
1
0
0
0
1
0
1
1
1
1. d = UIMM * 4
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*4)
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Instruction set
RM0004
rD0:31  EXTS(MEM(EA,2))
rD32:63  EXTS(MEM(EA+2,2))
The word addressed by EA is loaded from memory and placed in the odd half words sign
extended in each element of rD.
Figure 122 shows how bytes are loaded into rD as determined by the endian mode.
Figure 122. evlwhos results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
S
S
a
b
S
S
c
d
S = sign
GPR in little endian
S
S
b
a
S
S
d
c
S = sign
In big-endian memory, the most significant bits of a and c are sign extended. In little-endian
memory, the most significant bits of b and d are sign extended.
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhosx
SPE APU
evlwhosx
User
Vector load word into two half words odd signed indexed (with sign extension)
evlwhosx
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
1
0
0
0
1
0
1
1
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:31  EXTS(MEM(EA,2))
rD32:63  EXTS(MEM(EA+2,2))
The word addressed by EA is loaded from memory and placed in the odd half words sign
extended in each element of rD.
Figure 123 shows how bytes are loaded into rD as determined by the endian mode.
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0
RM0004
Instruction set
Figure 123. evlwhosx results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
S
S
a
b
S
S
c
d
S = sign
GPR in little endian
S
S
b
a
S
S
d
c
S = sign
In big-endian memory, the most significant bits of a and c are sign extended. In little-endian
memory, the most significant bits of b and d are sign extended.
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhou
SPE APU
evlwhou
User
Vector load word into two half words odd unsigned (zero-extended)
evlwhou
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,d(rA)
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
UIMM(1)
rA
0
1
1
0
0
0
1
0
1
0
1
1. d = UIMM * 4
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*4)
rD0:15  0x0000
rD16:31  MEM(EA,2)
rD32:47  0x0000
rD48:63  MEM(EA+2,2)
The word addressed by EA is loaded from memory and placed in the odd half words zero
extended in each element of rD.
Figure 124 shows how bytes are loaded into rD as determined by the endian mode.
Figure 124. evlwhou results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
Z
Z
a
b
Z
Z
c
d
Z = zero
GPR in little endian
Z
Z
b
a
Z
Z
d
c
Z = zero
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Instruction set
RM0004
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhoux
SPE APU
evlwhoux
User
Vector load word into two half words odd unsigned indexed (zero-extended)
evlwhoux
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
1
0
1
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  0x0000
rD16:31  MEM(EA,2)
rD32:47  0x0000
rD48:63  MEM(EA+2,2)
The word addressed by EA is loaded from memory and placed in the odd half words zero
extended in each element of rD.
Figure 125 shows how bytes are loaded into rD as determined by the endian mode.
Figure 125. evlwhoux results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
Z
Z
a
b
Z
Z
c
d
Z = zero
GPR in little endian
Z
Z
b
a
Z
Z
d
c
Z = zero
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhsplat
SPE APU
evlwhsplat
User
Vector load word into two half words and splat
evlwhsplat
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,d(rA)
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
UIMM(1)
1. d = UIMM * 4
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*4)
rD0:15  MEM(EA,2)
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0
1
1
0
0
0
1
1
1
0
1
RM0004
Instruction set
rD16:31  MEM(EA,2)
rD32:47  MEM(EA+2,2)
rD48:63  MEM(EA+2,2)
The word addressed by EA is loaded from memory and placed in both the even and odd half
words in each element of rD.
Figure 126 shows how bytes are loaded into rD as determined by the endian mode.
Figure 126. evlwhsplat results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
a
b
c
d
c
d
GPR in little endian
b
a
b
a
d
c
d
c
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwhsplatx
SPE APU
evlwhsplatx
User
Vector load word into two half words and splat indexed
evlwhsplatx
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
0
1
1
0
0
0
1
1
1
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:15  MEM(EA,2)
rD16:31  MEM(EA,2)
rD32:47  MEM(EA+2,2)
rD48:63  MEM(EA+2,2)
The word addressed by EA is loaded from memory and placed in both the even and odd half
words in each element of rD.
Figure 127 shows how bytes are loaded into rD as determined by the endian mode.
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Instruction set
RM0004
Figure 127. evlwhsplatx results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
a
b
c
d
c
d
GPR in little endian
b
a
b
a
d
c
d
c
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evlwwsplat
SPE APU
evlwwsplat
User
Vector load word into word and splat
evlwwsplat
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,d(rA)
8
rD
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
UIMM(1)
rA
0
1
1
0
0
0
1
1
0
0
1. d = UIMM * 4
if (rA = 0) then b  0
else b  (rA)
EA  b + EXTZ(UIMM*4)
rD0:31  MEM(EA,4)
rD32:63  MEM(EA,4)
The word addressed by EA is loaded from memory and placed in both elements of rD.
Figure 128 shows how bytes are loaded into rD as determined by the endian mode.
Figure 128. evlwwsplat results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
c
d
a
b
c
d
GPR in little endian
d
c
b
a
d
c
b
a
Implementation note: If the EA is not word aligned, an alignment exception occurs.
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1
RM0004
Instruction set
evlwwsplatx
SPE APU
evlwwsplatx
User
Vector load word into word and splat indexed
evlwwsplatx
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
1
0
0
0
1
1
0
0
0
if (rA = 0) then b  0
else b  (rA)
EA  b + (rB)
rD0:31  MEM(EA,4)
rD32:63  MEM(EA,4)
The word addressed by EA is loaded from memory and placed in both elements of rD.
Figure 129 shows how bytes are loaded into rD as determined by the endian mode.
Figure 129. evlwwsplatx results in big- and little-endian modes
Byte address
0
1
2
3
Memory
a
b
c
d
GPR in big endian
a
b
c
d
a
b
c
d
GPR in little endian
d
c
b
a
d
c
b
a
Implementation note: If the EA is not word aligned, an alignment exception occurs.
evmergehi
SPE, Ve;ctor SPFP, scalar DPFP APUs
evmergehi
User
Vector merge high
evmergehi
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
0
1
0
1
1
0
0
rD0:31  rA0:31
rD32:63  rB0:31
The high-order elements of rA and rB are merged and placed into rD, as shown in
Figure 130.
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Instruction set
RM0004
Figure 130. High order element merging (evmergehi)
0
31
32
63
rA
rB
rD
Note:
A vector splat high can be performed by specifying the same register in rA and rB.
evmergehilo SPE, Vector SPFP, Scalar DPFP APUs User
evmergehilo
Vector merge high/low
evmergehilo
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
0
1
0
1
1
1
0
rD0:31  rA0:31
rD32:63  rB32:63
The high-order element of rA and the low-order element of rB are merged and placed into
rD, as shown in Figure 131.
Figure 131. High order element merging (evmergehilo)
0
31
32
63
rA
rB
rD
Application note: With appropriate specification of rA and rB, evmergehi, evmergelo,
evmergehilo, and evmergelohi provide a full 32-bit permute of two source operands.
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DocID13694 Rev 2
RM0004
Instruction set
evmergelo
SPE APU
evmergelo
User
Vector merge low
evmergelo
0
1
2
3
4
5
0
0
0
1
0
0
6
rD,rA,rB
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
0
1
0
1
1
0
1
rD0:31  rA32:63
rD32:63  rB32:63
The low-order elements of rA and rB are merged and placed in rD, as shown in Figure 132.
Figure 132. Low order element merging (evmergelo)
0
31
32
63
rA
rB
rD
Note:
A vector splat low can be performed by specifying the same register in rA and rB.
evmergelohi
SPE APU
evmergelohi
User
Vector merge low/high
evmergelohi
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
0
1
0
0
0
1
0
1
1
1
1
rD0:31  rA32:63
rD32:63  rB0:31
The low-order element of rA and the high-order element of rB are merged and placed into
rD, as shown in Figure 133.
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Instruction set
RM0004
Figure 133. Low order element merging (evmergelohi)
0
31
32
63
rA
rB
rD
Note:
A vector swap can be performed by specifying the same register in rA and rB.
evmhegsmfaa
SPE APU
evmhegsmfaa
User
Vector multiply half words, even, guarded, signed, modulo, fractional and accumulate
evmhegsmfaa
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
0
0
1
0
1
0
1
1
temp0:31  rA32:47 sf rB32:47
temp0:63  EXTS(temp0:31) 
rD0:63  ACC0:63 + temp0:63 

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered, half-word signed fractional elements in rA and rB
are multiplied. The product is added to the contents of the 64-bit accumulator and the result
is placed into rD and the accumulator.
Note:
466/1025
This is a modulo sum. There is no overflow check and no saturation is performed. Any
overflow of the 64-bit sum is not recorded into the SPEFSCR.
DocID13694 Rev 2
RM0004
Instruction set
Figure 134. evmhegsmfaa (even form)
0
31
32
47
48
63
rA
rB
X
ssss_ssss_ssss_ssss...ssss
Intermediate product
Accumulator
+
rD and Accumulator
evmhegsmfan
SPE APU
evmhegsmfan
User
Vector multiply half words, even, guarded, signed, modulo, fractional and accumulate
negative
evmhegsmfan
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
1
0
1
0
1
0
1
1
temp0:31  rA32:47 sf rB32:47
temp0:63  EXTS(temp0:31)
rD0:63  ACC0:63 - temp0:63

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered, half-word signed fractional elements in rA and rB
are multiplied. The product is subtracted from the contents of the 64-bit accumulator and the
result is placed into rD and the accumulator.
Note:
This is a modulo difference. There is no overflow check and no saturation is performed. Any
overflow of the 64-bit difference is not recorded into the SPEFSCR.
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Instruction set
RM0004
Figure 135. evmhegsmfan (even form)
0
31
47
32
48
63
rA
rB
X
ssss_ssss_ssss_ssss...sss
Intermediate product
Accumulator
–
rD and Accumulator
evmhegsmiaa
SPE APU
evmhegsmiaa
User
Vector multiply half words, even, guarded, signed, modulo, integer and accumulate
evmhegsmiaa
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
0
0
1
0
1
0
0
1
temp0:31  rA32:47 si rB32:47
temp0:63  EXTS(temp0:31)
rD0:63  ACC0:63 + temp0:63

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered half-word signed integer elements in rA and rB are
multiplied. The intermediate product is sign-extended and added to the contents of the 64bit accumulator, and the resulting sum is placed into rD and into the accumulator.
Note:
468/1025
This is a modulo sum. There is no overflow check and no saturation is performed. Any
overflow of the 64-bit sum is not recorded into the SPEFSCR.
DocID13694 Rev 2
RM0004
Instruction set
Figure 136. evmhegsmiaa (even form)
0
31
32
47
48
63
rA
rB
X
ssss_ssss_ssss_ssss...ssss
Intermediate product
Accumulator
+
rD and Accumulator
evmhegsmian
SPE APU
evmhegsmian
User
Vector multiply half words, even, guarded, signed, modulo, integer and accumulate
negative
evmhegsmian
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
1
0
1
0
1
0
0
1
temp0:31  rA32:47 si rB32:47
temp0:63  EXTS(temp0:31)
rD0:63  ACC0:63 - temp0:63

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered half-word signed integer elements in rA and rB are
multiplied. The intermediate product is sign-extended and subtracted from the contents of
the 64-bit accumulator, and the result is placed into rD and into the accumulator.
Note: This is a modulo difference. There is no check for overflow and no saturation is
performed. Any overflow of the 64-bit difference is not recorded into the SPEFSCR.
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Instruction set
RM0004
Figure 137. evmhegsmian (even form)
0
31
32
47
48
63
rA
rB
X
ssss_ssss_ssss_ssss...ssss
Intermediate product
Accumulator
–
rD and Accumulator
evmhegumiaa
SPE APU
evmhegumiaa
User
Vector multiply half words, even, guarded, unsigned, modulo, integer and accumulate
evmhegumiaa
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
0
0
1
0
1
0
0
0
temp0:31  rA32:47 ui rB32:47
temp0:63  EXTZ(temp0:31)
rD0:63  ACC0:63 + temp0:63

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered half-word unsigned integer elements in rA and rB
are multiplied. The intermediate product is zero-extended and added to the contents of the
64-bit accumulator. The resulting sum is placed into rD and into the accumulator.
Note: This is a modulo sum. There is no overflow check and no saturation is performed. Any
overflow of the 64-bit sum is not recorded into the SPEFSCR.
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RM0004
Instruction set
Figure 138. evmhegumiaa (even form)
0
31
32
47
48
63
rA
rB
X
0000_0000_0000_0000...000
Intermediate product
Accumulator
+
rD and Accumulator
evmhegumian
SPE APU
evmhegumian
User
Vector multiply half words, even, guarded, unsigned, modulo, integer and accumulate
negative
evmhegumian
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
1
0
1
0
1
0
0
0
temp0:31  rA32:47 ui rB32:47
temp0:63  EXTZ(temp0:31)
rD0:63  ACC0:63 - temp0:63

// update accumulator
ACC0:63  rD0:63
The corresponding low even-numbered unsigned integer elements in rA and rB are
multiplied. The intermediate product is zero-extended and subtracted from the contents of
the 64-bit accumulator. The result is placed into rD and into the accumulator.
Note: This is a modulo difference. There is no check for overflow and no saturation is
performed. Any overflow of the 64-bit difference is not recorded into the SPEFSCR.
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Instruction set
RM0004
Figure 139. evmhegumian (even form)
0
31
32
47
48
63
rA
rB
X
0000_0000_0000_0000...000
Intermediate product
Accumulator
–
rD and Accumulator
evmhesmf
SPE APU
evmhesmf
User
Vector multiply half words, even, signed, modulo, fractional (to accumulator)
evmhesmf
evmhesmfa
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
rD,rA,rB
8
rD
9
(A = 0)
(A = 1)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
0
0
0 A 0
1
0
1
// high
rD0:31 rA0:15 sf rB0:15) 

// low
rD32:63rA32:47 sf rB32:47) 

// update accumulator
if A = 1 then ACC0:63 rD0:63
The corresponding even-numbered half-word signed fractional elements in rA and rB are
multiplied then placed into the corresponding words of rD.
If A = 1, the result in rD is also placed into the accumulator.
Other registers altered: ACC (If A = 1)
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1
RM0004
Instruction set
Figure 140. Even multiply of two signed modulo fractional elements (to
accumulator) (evmhesmf)
15
0
16
31
47
32
48
63
rA
rB
X
X
rD
(and accumulator
if evmhesmfa)
evmhesmfaaw
SPE APU
evmhesmfaaw
User
Vector multiply half words, even, signed, modulo, fractional and accumulate into
words
evmhesmfaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
0
0
0
0
1
0
1
1
// high
temp0:31  (rA0:15 sf rB0:15) 
rD0:31  ACC0:31 + temp0:31 

// low
temp0:31  (rA32:47 sf rB32:47) 
rD32:63  ACC32:63 + temp0:31 

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
signed fractional elements in rA and rB are multiplied. The 32 bits of each intermediate
product are added to the contents of the accumulator words to form intermediate sums,
which are placed into the corresponding rD words and into the accumulator.
Other registers altered: ACC
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Instruction set
RM0004
Figure 141. Even form of vector half-word multiply (evmhesmfaaw)
15
0
16
31
47
32
48
63
rA
rB
X
X
Intermediate product
Accumulator
+
+
rD and Accumulator
evmhesmfanw
SPE APU
evmhesmfanw
User
Vector multiply half words, even, signed, modulo, fractional and accumulate negative
into words
evmhesmfanw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
1
0
0
0
1
0
1
1
// high
temp0:31  rA0:15 sf rB0:15 
rD0:31  ACC0:31 - temp0:31

// low
temp0:31  rA32:47 sf rB32:47 
rD32:63 ACC32:63 - temp0:31

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
signed fractional elements in rA and rB are multiplied. The 32-bit intermediate products are
subtracted from the contents of the accumulator words to form intermediate differences,
which are placed into the corresponding rD words and into the accumulator.
Other registers altered: ACC
474/1025
DocID13694 Rev 2
RM0004
Instruction set
Figure 142. Even form of vector half-word multiply (evmhesmfanw)
0
15
16
31
32
47
48
63
rA
rB
X
X
Intermediate product
Accumulator
–
–
rD and Accumulator
evmhesmi
SPE APU
evmhesmi
User
Vector multiply half words, even, signed, modulo, integer (to accumulator)
evmhesmi
evmhesmia
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
rD,rA,rB
8
rD
9
(A = 0)
(A = 1)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
0
0
0 A 0
1
0
0
1
// high
rD0:31 rA0:15 si rB0:15 

// low
rD32:63 rA32:47 si rB32:47 

// update accumulator
if A = 1, then ACC0:63 rD0:63
The corresponding even-numbered half-word signed integer elements in rA and rB are
multiplied. The two 32-bit products are placed into the corresponding words of rD.
If A = 1, the result in rD is also placed into the accumulator.
Other registers altered: ACC (If A = 1)
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Instruction set
RM0004
Figure 143. Even form for vector multiply (to accumulator) (evmhesmi)
0
15
16
31
32
47
48
63
rA
rB
X
X
rD (and accumulator
for evmhesmia)
evmhesmiaaw
SPE APU
evmhesmiaaw
User
Vector multiply half words, even, signed, modulo, integer and accumulate into words
evmhesmiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
0
0
0
0
1
0
0
// high
temp0:31  rA0:15 si rB0:15 
rD0:31  ACC0:31 + temp0:31

// low
temp0:31  rA32:47 si rB32:47 
rD32:63  ACC32:63 + temp0:31

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
signed integer elements in rA and rB are multiplied. Each intermediate 32-bit product is
added to the contents of the accumulator words to form intermediate sums, which are
placed into the corresponding rD words and into the accumulator.
Other registers altered: ACC
476/1025
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1
RM0004
Instruction set
Figure 144. Even form of vector half-word multiply (evmhesmiaaw)
15
0
16
31
47
32
48
63
rA
rB
X
X
Intermediate product
Accumulator
+
+
rD and Accumulator
evmhesmianw
SPE APU
evmhesmianw
User
Vector multiply half words, even, signed, modulo, integer and accumulate negative
into words
evmhesmianw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
1
0
0
0
1
0
0
1
// high
temp00:31 rA0:15 si rB0:15 
rD0:31  ACC0:31 - temp00:31

// low
temp10:31  rA32:47 si rB32:47 
rD32:63  ACC32:63 - temp10:31

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
signed integer elements in rA and rB are multiplied. Each intermediate 32-bit product is
subtracted from the contents of the accumulator words to form intermediate differences,
which are placed into the corresponding rD words and into the accumulator.
Other registers altered: ACC
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Instruction set
RM0004
Figure 145. Even form of vector half-word multiply (evmhesmianw)
0
15
16
31
32
47
48
63
rA
rB
X
X
Intermediate product
Accumulator
–
–
rD and Accumulator
evmhessf
SPE APU
evmhessf
User
Vector multiply half words, even, signed, saturate, fractional (to accumulator)
evmhessf
evmhessfa
0
1
2
3
4
5
0
0
0
1
0
0
6
7
rD,rA,rB
rD,rA,rB
8
rD
9
(A = 0)
(A = 1)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
// high
temp0:31 rA0:15 sf rB0:15 
if (rA0:15 = 0x8000)  (rB0:15 = 0x8000) then
rD0:31 0x7FFF_FFFF //saturate 
movh 1
else
rD0:31 temp0:31
movh 0

// low
temp0:31 rA32:47 sf rB32:47 
if (rA32:47 = 0x8000)  (rB32:47 = 0x8000) then
rD32:63 0x7FFF_FFFF //saturate
movl 1
else
rD32:63 temp0:31
movl 0

// update accumulator
478/1025
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1
0
0
0
0 A 0
0
0
1
1
RM0004
Instruction set
if A = 1 then ACC0:63 rD0:63

// update SPEFSCR
SPEFSCROVH movh
SPEFSCROV movl
SPEFSCRSOVH SPEFSCRSOVH | movh
SPEFSCRSOV SPEFSCRSOV | movl
The corresponding even-numbered half-word signed fractional elements in rA and rB are
multiplied. The 32 bits of each product are placed into the corresponding words of rD. If both
inputs are –1.0, the result saturates to the largest positive signed fraction and the overflow
and summary overflow bits are recorded in the SPEFSCR.
If A = 1, the result in rD is also placed into the accumulator.
Other registers altered:
SPEFSCR 
ACC (If A = 1)
Figure 146. Even multiply of two signed saturate fractional elements (to
accumulator) (evmhessf)
15
0
16
31
47
32
48
63
rA
rB
X
X
rD (and accumulator
if evmhessa)
evmhessfaaw
SPE APU
evmhessfaaw
User
Vector multiply half words, even, signed, saturate, fractional and accumulate into
words
evmhessfaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
0
0
0
0
0
0
1
1
// high
temp0:31 rA0:15 sf rB0:15 
if (rA0:15 = 0x8000)  (rB0:15 = 0x8000) then
temp0:31 0x7FFF_FFFF //saturate 
movh 1
else
movh 0
temp0:63 EXTS(ACC0:31) + EXTS(temp0:31)
ovh (temp31  temp32)
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Instruction set
RM0004
rD0:31 SATURATE(ovh, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// low
temp0:31 rA32:47 sf rB32:47 
if (rA32:47 = 0x8000)  (rB32:47 = 0x8000) then
temp0:31 0x7FFF_FFFF //saturate 
movl 1
else
movl 0
temp0:63 EXTS(ACC32:63) + EXTS(temp0:31)
ovl (temp31  temp32)
rD32:63 SATURATE(ovl, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// update accumulator
ACC0:63 rD0:63

// update SPEFSCR
SPEFSCROVH movh
SPEFSCROV movl
SPEFSCRSOVH SPEFSCRSOVH | ovh | movh
SPEFSCRSOV SPEFSCRSOV | ovl| movl
The corresponding even-numbered half-word signed fractional elements in rA and rB are
multiplied producing a 32-bit product. If both inputs are –1.0, the result saturates to
0x7FFF_FFFF. Each 32-bit product is then added to the corresponding word in the
accumulator, saturating if overflow or underflow occurs, and the result is placed in rD and
the accumulator.
If there is an overflow or underflow from either the multiply or the addition, the overflow and
summary overflow bits are recorded in the SPEFSCR.
Other registers altered: SPEFSCR ACC
Figure 147. Even form of vector half-word multiply (evmhessfaaw)
0
15
16
X
31
32
47
48
63
rA
rB
X
Intermediate product
Accumulator
+
+
rD and Accumulator
480/1025
DocID13694 Rev 2
RM0004
Instruction set
evmhessfanw
SPE APU
evmhessfanw
User
Vector multiply half words, even, signed, saturate, fractional and accumulate
negative into words
evmhessfanw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
1
1
0
0
0
0
0
1
1
++The corresponding even-numbered half-word signed fractional elements in rA and rB are
multiplied producing a 32-bit product. If both inputs are –1.0, the result saturates to
0x7FFF_FFFF. Each 32-bit product is then subtracted from the corresponding word in the
accumulator, saturating if overflow or underflow occurs, and the result is placed in rD and
the accumulator.
If there is an overflow or underflow from either the multiply or the addition, the overflow and
summary overflow bits are recorded in the SPEFSCR.
Other registers altered: SPEFSCR ACC
Figure 148. Even form of vector half-word multiply (evmhessfanw)
0
15
16
31
32
X
47
48
63
rA
rB
X
Intermediate product
Accumulator
+
+
rD and Accumulator
evmhessiaaw
SPE APU
evmhessiaaw
User
Vector multiply half words, even, signed, saturate, integer and accumulate into words
evmhessiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
0
0
0
0
0
0
0
1
// high
temp0:31 rA0:15 si rB0:15 
temp0:63 EXTS(ACC0:31) + EXTS(temp0:31)
ovh (temp31  temp32)
rD0:31 SATURATE(ovh, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// low
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Instruction set
RM0004
temp0:31 rA32:47 si rB32:47 
temp0:63 EXTS(ACC32:63) + EXTS(temp0:31)
ovl (temp31  temp32)
rD32:63 SATURATE(ovl, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// update accumulator
ACC0:63 rD0:63

// update SPEFSCR
SPEFSCROVH ovh
SPEFSCROV ovl
SPEFSCRSOVH SPEFSCRSOVH | ovh
SPEFSCRSOV SPEFSCRSOV | ovl
The corresponding even-numbered half-word signed integer elements in rA and rB are
multiplied producing a 32-bit product. Each 32-bit product is then added to the
corresponding word in the accumulator, saturating if overflow occurs, and the result is
placed in rD and the accumulator.
If there is an overflow or underflow from either the multiply or the addition, the overflow and
summary overflow bits are recorded in the SPEFSCR.
Other registers altered: SPEFSCR ACC
Figure 149. Even form of vector half-word multiply (evmhessiaaw)
15 16
0
31
47 48
32
63
rA
rB
X
X
Intermediate product
Accumulator
+
+
rD and Accumulator
evmhessianw
SPE APU
evmhessianw
User
Vector multiply half words, even, signed, saturate, integer and accumulate negative
into words
evmhessianw
0
1
2
3
4
5
0
0
0
1
0
0
482/1025
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7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
DocID13694 Rev 2
1
0
1
1
0
0
0
0
0
0
1
RM0004
Instruction set
// high
temp0:31 rA0:15 si rB0:15 
temp0:63 EXTS(ACC0:31) - EXTS(temp0:31)
ovh (temp31  temp32)
rD0:31 SATURATE(ovh, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// low
temp0:31 rA32:47 si rB32:47 
temp0:63 EXTS(ACC32:63) - EXTS(temp0:31)
ovl (temp31  temp32)
rD32:63 SATURATE(ovl, temp31, 0x8000_0000, 0x7FFF_FFFF, temp32:63) 

// update accumulator
ACC0:63 rD0:63

// update SPEFSCR
SPEFSCROVH ovh
SPEFSCROV ovl
SPEFSCRSOVH SPEFSCRSOVH | ovh
SPEFSCRSOV SPEFSCRSOV | ovl
The corresponding even-numbered half-word signed integer elements in rA and rB are
multiplied producing a 32-bit product. Each 32-bit product is then subtracted from the
corresponding word in the accumulator, saturating if overflow occurs, and the result is
placed in rD and the accumulator.
If there is an overflow or underflow from either the multiply or the addition, the overflow and
summary overflow bits are recorded in the SPEFSCR.
Other registers altered: SPEFSCR ACC
Figure 150. Even form of vector half-word multiply (evmhessianw)
15 16
0
47 48
31 32
63
rA
rB
X
X
Intermediate product
Accumulator
–
–
rD and Accumulator
DocID13694 Rev 2
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Instruction set
RM0004
evmheumi
SPE APU
evmheumi
User
Vector multiply half words, even, unsigned, modulo, integer (to accumulator)
evmheumi
evmheumia
0
1
2
3
4
5
6
0
0
0
1
0
0
7
rD,rA,rB
rD,rA,rB
8
9
(A = 0)
(A = 1)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rD
rA
rB
1
0
0
0
0 A 0
1
0
0
0
// high
rD0:31 rA0:15 ui rB0:15 

// low
rD32:63 rA32:47 ui rB32:47 

// update accumulator
if A = 1 then ACC0:63 rD0:63
The corresponding even-numbered half-word unsigned integer elements in rA and rB are
multiplied. The two 32-bit products are placed into the corresponding words of rD.
If A = 1, the result in rD is also placed into the accumulator.
Figure 151. Vector multiply half words, even, unsigned, modulo, integer (to
accumulator) (evmheumi)
15
0
16
31
47
32
48
63
rA
rB
X
X
rD (and accumulator
if evmheumia)
evmheumiaaw
SPE APU
evmheumiaaw
User
Vector multiply half words, even, unsigned, modulo, integer and accumulate into
words
evmheumiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
// high
temp0:31  rA0:15 ui rB0:15
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1
0
1
0
0
0
0
1
0
0
0
RM0004
Instruction set
rD0:31  ACC0:31 + temp0:31

// low
temp0:31  rA32:47 ui rB32:47
rD32:63  ACC32:63 + temp0:31

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
unsigned integer elements in rA and rB are multiplied. Each intermediate product is added
to the contents of the corresponding accumulator words and the sums are placed into the
corresponding rD and accumulator words.
Other registers altered: ACC
Figure 152. Even form of vector half-word multiply (evmheumiaaw)
15
0
16
31
47
32
48
63
rA
rB
X
X
Intermediate product
Accumulator
+
+
rD and Accumulator
evmheumianw
evmheumianw
SPE APU
User
Vector multiply half words, even, unsigned, modulo, integer and accumulate negative
into words
evmheumianw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
1
0
0
0
1
0
0
0
// high
temp0:31  rA0:15 ui rB0:15
rD0:31  ACC0:31 - temp0:31
DocID13694 Rev 2
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Instruction set
RM0004

// low
temp0:31  rA32:47 ui rB32:47
rD32:63  ACC32:63 - temp0:31

// update accumulator
ACC0:63  rD0:63
For each word element in the accumulator, the corresponding even-numbered half-word
unsigned integer elements in rA and rB are multiplied. Each intermediate product is
subtracted from the contents of the corresponding accumulator words. The differences are
placed into the corresponding rD and accumulator words.
Other registers altered: ACC
Figure 153. Even form of vector half-word multiply (evmheumianw)
0
15
16
31
32
47
48
63
rA
rB
X
X
Intermediate product
Accumulator
-
rD and Accumulator
evmheusiaaw
SPE APU
evmheusiaaw
User
Vector multiply half words, even, unsigned, saturate, integer and accumulate into
words
evmheusiaaw
0
1
2
3
4
5
0
0
0
1
0
0
6
7
8
rD
rD,rA,rB
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
rA
rB
1
0
1
0
0
0
0
// high
temp0:31  rA0:15 ui rB0:15 
temp0:63  EXTZ(ACC0:31) + EXTZ(temp0:31)
ovh  temp31
rD0:31  SATURATE(ovh, 0, 0xFFFF_FFFF, 0xFFFF_FFFF, temp32:63) 
486/1025
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0
0
0
0
RM0004
Instruction set

//low
temp0:31  rA32:47 ui rB32:47 
temp0:63  EXTZ(ACC32:63) + EXTZ(temp0:31)
ovl  temp31
rD32:63  SATURATE(ovl, 0, 0xFFFF_FFFF, 0xFFFF_FFFF, temp32:63)

// update accumulator
ACC0:63  rD0:63

// update SPEFSCR
SPEFSCROVH  ovh
SPEFSCROV  ovl
SPEFSCRSOVH  SPEFSCRSOVH | ovh
SPEFSCRSOV  SPEFSCRSOV | ovl
For each word element in the accumulator, corresponding even-numbered half-word
unsigned integer elements in rA and rB are multiplied producing a 32-bit product. Each 32bit product is then added to the corresponding word in the accumulator, saturating if
overflow occurs, and the result is placed in rD and the accumulator.
If the addition causes overflow, the overflow and summary overflow bits are recorded in the
SPEFSCR.
Other registers altered: SPEFSCR ACC
Figure 154. Even form of vector half-word multiply (evmheusiaaw)
15
0
16
31
47
32
48
63
rA
rB
X
X
Intermediate product
Accumulator
+
+
rD and Accumulator
DocID13694 Rev 2">