Motorola PowerPC Microprocessor Family Pocket Reference Guide

SA14-2093-00' ©
eh Gites Hrurripes)
MPCPRGREF/D
(Motorola Order Number)
PowerPC™ Microprocessor Family:
The Programmer’s
Pocket Reference Guide
Pa2werPl (M) MOTOROLA
Introduction
This document provides an overview of the PowerPC™ registers, instructions, and
exceptions for 32-bit implementations. A more detailed account of the following topics or
the PowerPC architecture in general, may be obtained from the PowerPC Microprocessor
Family: The Programming Environments User's Manual, referred to as The Programming
Environments Manual (Motorola order number MPCFPE/AD and IBM order number
MPRPPCFPE-02). For further information, refer to The PowerPC Architecture: A
Specification for a New Family of RISC Processors which remains the defining document
for the PowerPC architecture,
This document contains information on the following topics:
MSR bit settings
State of MSR at power-up
PTE bit definitions
Exceptions and conditions
PowerPC instruction set
+ a. a + + € E E E E #
Floating-point exception mode bits
PowerPC programming model-registers
Memory management registers
Encodings for the branch options field
BAT register bit/field definitions and area lengths
Segment register bit definitions and instructions
~~
SUPERVISOR MODEL
N
Configuration Registers
General-Purpose
Registers
GPRO
GPR1
GPR31
Floating-Peint
Registers
FPRO
FPR1
FPR31
Condition Register
CR
Floating-Point Status
and Control Register
Processor
State Register Version Register
MSR PVR | SPR 287
—— _ Machi
( USER MODEL NN Regis
Memory Management Registers
Instruction BAT Data BAT Registers
Registers
DBATOU | SPR 536
IBATOU | ЗРЯ 528 | DBATOL | SPR537
IBATOL | SPR529 |" DBATIU | SPRE5SS
IBATIU |SPRSSO | DBATIL | SPR 539
IBATIL | $РА 531 |DpAu | sPRs40
IBAT2U | SPRS32 | DBATL | SPR541
IBAT2L | SPRS33 | DBAT3U | SPR 542
IBAT3U | SPR534 "DpATL | SPR 543
IBATSL | SPR 565 Segment Registers !
SDR Register SRO
°
+
5815
N
FPSCR Exception Handling Registers
Data Address
XER Register Register DSISR Register
XER SPR 1 DAR | sPR19 | DSISR | ЗРЯ 18
Link Register SPRG Registers ) save and Restore. CL
egisters
SPR 8 SPRGO | SPR 272
SPRG1 | SPR 273 SRRO SPR 26
Count Register SPRG2 |¡ SPR 274 SRA1 SPR 27
CTR SPR 9 SPRG3 | SPR275
Time Base Facility Miscellaneous Registers
(Read-Only) Time Base Facility Data Address
met] TBR 268 (Write-Only) Breakpoint Register
TBU TBR 269 TBL SPR 284 DABR | SPR 1013
\_ TBU | SPR285
т External Address
Decrementer Register
1" These registers are in 32-bit implementations only.
2 These registers are optional in the PowerPC architecture.
PowerPC Programming Model
Segment Register Bit Definition for Page Address Translation
Bis) Name Description
0 T T = 0 selects this format
1 Ks Supervisor-state protection key
2 Kp User-state protection key
3 N No-execute protection bit
4-7 — Reserved
8-31 VSID Virtual segment ID
Segment Register Bit Definitions for Direct-Store Segments
Bit(s) Name Description
0 T Т = 1 selects this format.
1 Ks Supervisor-state protection key
2 Kp User-state protection key
3-11 BUID Bus unit ID
12-31 — Device specific data for I/O controller
PTE Bit Definitions
Word Bit(s) Name Description
0 0 V Entry valid (V = 1} or invalid (V = 0}
1-24 VSID Virtual segment ID
25 H Hash function identifier
26-31 API Abbreviated page index
1 0-19 RPN Physical page number
20-22 — Reserved
23 R Referenced bit
24 с Changed bit
25-28 WIMG Memory/cache control bits
29 — Reserved
30-31 PP Page protection bits
Exceptions and Conditions
Exception Vector Offset Causing Conditions
Type (hex)
Reserved 00000 —
System reset 00100 The causes of system reset exceptions are
implementation-dependent.
Machine check 00200 The causes for machine check exceptions are
implementation-dependent, but typically these
causes are related to conditions such as bus
parity errors or attempting to access an invalid
physical address.
DS! 00300 A DSI exception occurs when a data memory
access cannot be performed.
ISI 00400 An ISI exception occurs when an instruction
fetch cannot be performed.
External interrupt 00500 An externa! interrupt is generated only when
an external exception is pending (typically
signaled by a signal defined by the
imptementation) and the interrupt is enabled
(MSRIEE] = 1).
Alignment 00600 An alignment exception may occur when the
processor cannot perform a memory access
ecause of alignment or endian reasons.
Program 00700 A program exception is caused by conditions
which correspond to bit settings in SRR1 and
arise during execution of an instruction.
Floating-point 00800 A floating-point unavailable
unavailable exception is caused by an attempt to execute a
floating-point instruction (including floating-
point load, store, and move instructions} when
the floating-point available bit is cleared,
Decrementer 00900 The decrementer interrupt exception is taken if
the interrupt is enabled and the exception is
pending. The exception is created when the
most significant bit changes from Qto 1. If itis
not enabled, the exception remains pending
until it is taken.
Reserved 00AQQ Reserved for implementation-specific
exceptions.
Reserved 00800 oe
System call 00C00 À system call exception occurs when a System
Call (sc) instruction is executed.
Trace 00000 The trace exception is optional. It occurs if
either the MSRISE] = | and any instruction
(except гп successful completed or MSRIBE]J
= 1 anda branch instruction is completed.
Floating-point 00Е00 The floating-point assist
assist exception is optional. This exception can be
used to provide software assistance for
infrequent and complex floating-point
operations such as denormalization.
Reserved Q0E10-00FFF —
Reserved 01000-02FFF Reserved for implementation-specific
exceptions.
Name © 6 7 8 9 101112 13 14 15 16 17 18 19 20 21 2223242526272829 30 31
inmsubsx | 59 | D A B o 30 Ac
fresx * 59 D 00000 B 00000 | 24 Re
frspx D 00000 B 12 Re
frsgrtex * 63 D 00000 B 00000 26 Вс
tselx 4 63 D A B с 23 Re
fsqrtx * 63 D 00000 B 00000 22 Вс
fsqrtsx* 59 D 00000 B 00000 22 Re
fsubx 63 D A B 60000 20 Re
fsubsx 59 D A B 00000 20 Re
ichi a1 00000 A B 982 D
isync 19 00000 00000 00000 150 0
ibz 34 D A d
ibzu 35 D A d
Ibzux 31 D A B | 119 | 0
Ibzx 31 D A 8 | 87 | 0
Hd 50 D A d
Нач 51 D A d a
lfdux 31 D A B | 631 | q
нах 31 D A B | | 599 | 0
Ив 48 D A d
lísu 49 D A d -
Ивих 31 D A B | 567 - O
lfsx 31 D A B | 535 [O
Iha 42 D A d
lhau 43 D À d
thaux 31 D A B 375 0
lhax 31 о А B 343
Inbrx 31 D A B 790 0
Ihz 40 о А d
thzu 41 D A d ‘
Ihzux 31 D A B | 311 [a
Ihzx 31 D A B | 279 ©
лу 3 46 D A d
Iswi 3 ai D A NB 597 0 | 0
Iswx 3 31 D A B 533 0
Iwarx 31 D A B 20
Iwbrx 31 о А B 534 о
Iwz 32 D A d |
lwzu 33 D A d
wzux 31 D A B 55 0
мах 31 D A B 23 0
merf 19 ern Foo} crfs [00 00000 0 o
merfs 63 cfd | 90| си$ | 00| 00000 64 0
merxr 31 cri [OO 00000 00000 512 0
mfcr 31 D 00000 00000 19 0
mitsx 83 D 00000 | 00000 503 Re
mfmer! 31 D 00000 00000 83 q
mispr2 31 D spr 339 o
misr 15 31 D jo) sR | 00000 595 «|»
mfsrin 15 31 D 00000 | B 659 0
mith 31 D tor 371 o.
mterf 31 $ 0] CRM 0 144 0
mtfsb0x 63 crbD 00000 00000 70 Re
mtfsbix 63 erbD 00000 00000 38 [Re
mtfsfx 63 o FM lo B 711 [me
mtfsfix 63 cdD [00 | 00000 IMM lo 134 [Re
mtmsr * 31 s 00000 00000 146 0
mtspr 2 31 $ spr 467 N D
mtsr 15 31 s [0] SR 00000 210 0
mtsrin 15 31 $ E 00000 B 242 0
mulhwx 31 D A B [© { 75 Re
mulhwux 31 D A B ol 11 Fic
mulli 7 D A SIMM
mullwx 31 D A в ОЕ 235 Re
nandx 31 5 A 8 476 Re
x 31 D A 00000 DE 104 Re
X 31 $ А в 124 Rc
x 31 5 А B 444 |Re
7
Auorpeey y — “siequint ys 10751581 17920)
WEN
{1 puow) 31d
{орюм) З1а
, MAL
y (Mai
eva
e Ever
e YE
HAd
¿NEL
¿ Mar
ya
VHS
LEHS
OHHS
1905
030
HVO
небо
H1D
m
H3X
[L = 5
lo = 1s
HEN
HOSdJ
Ho
VHdD
WEN
ÁS EJ 5 к Vo
YOU OMAN E ÁUO-0UMZ SISQUAU HIS [BUCIHOPE JO EMS SIUsUasug DUptnuefosd St 01 JE0H4 | - ISSION
IE OF 62 92 12 92 ST YX € 2 IZ A 6 S Z Y SL Y eZ IL O 6 8 L 9 $ Y E 2 L 0 JAQUIN
dd |o|! DIM lola} 000 | ман
lay IH | ISA | A
naL 892 WAL
(Mar 892 WAL
ua | MO | 19 | avo Elo) uds
dé | 91 TT 0000000000 | мана 625 HdS
da | sa 18 | 9000 | 1438 825 HdS
uo | СТ 152 Наб
naL SZ HdS
(aL 9% HAS
ay | 0000000000000000000000000 | 3 | aseuds
UDYdS 22 YdS
LES 22 Uds
00 | OHHS 93 HIS
HSYMEYLH | 0000000 SUOBYLH 62 наб
030 га наб
uva 61 MS
HSIST 81 Наб
LO 6445
sosIppy ива в наб
уго) 93 i 0000000000000000000000 voisolos| 1Hds
UORBULIGU] SORA -J8I0AN0D | ang cu | sx | 1
argh | 0000 JN [du[sx| 1
31| 8 | 00 |uo|ui oi | © |134) зе | a8 omg aw ] ua | 53 [an | 9 lod 0000000000000
Ni | в | эх = | n | 30 | 34 XALTDALCOA e Judd | le es ta onto) || || ss
449 #89 SHO Уно 189 | 049
=
IE OC 62 92 22 % ST ve € 2 12 02 El 81 ZI 9L SL pL € 2 lL Ol 6 8 2 9 $ Y € = L 0 90
\_ pamesay 777
suonejuswadu 19-7€—epint) soualajey AID /
suonejuewa|du
1g-c€
opino
JUDY
то
2амотг
PowerPC Instruction List Sorted by Mnemonic
This table lists the instructions implemented in the PowerPC architecture in
alphabetical order by mnemaonic.
Name © 6 7 8 9 101112 1314 15 16 17 18 19 20 21 2223242526272829 30 31
addx 31 D A B OE 266 Re
addex 31 D A B OE 10 Ac
addex 31 D A B OE 138 Re
addi 14 D A SIMM
addic 12 D A SIMM
addic. 13 D A SIMM
addis 15 D A SIMM
addmex 31 D A 00000 OF 234 Rc
addzex 31 D A 00000 oF 202 Re
andx 31 5 А B 28 Re
andex 31 5 A B 60 Re
andi. 28 $ А UIMM
andis. 29 $ А UIMM
bx 18 Li [AA LK
bex 16 BO BI BD [AA LK
bectrx 19 BO Bl 00000 528 LK
belrx 19 BO Bl 00000 16 LK
cmp 31 ertd& |oÏL A B 0 q
стр! 11 edd [OÏL A SIMM
empl 31 cr [O]L A B 32 0
empli 10 edd [oil A N UIMM
cntlzwx 31 5 А 00000 | 26 Re
trand 19 со crbA crb8 257 0
crandc 19 crbD crbA crbB 129 o |
creqv 19 erbD СТА crbB 289 a
ernand 19 стор crb crbB 225 0
crnor 19 crbD crbA crbB 33 о
cror 19 crbD crbA crbB 449 D
crore 19 crbD crbA crbB 417 о
crxor 19 crbD crbA crbB 193 о
debf 31 90000 A B 86 0
debi * 31 00000 A B 470 q
debst 31 00000 A B 54 Te
debt 31 00000 A B 278 0
debtst 31 00000 A B 246 0
debz 31 00000 A B 1014 0
divwx 31 D A B OE 491 Re
divwux at D A B = 459 Re
eciwx 31 D A B 310 a
ecowx 31 5 А B 438 0
eieio 31 06000 00000 00600 854 o
equx at 5 А В 284 Rc
extsbx at $ А 00000 954 Re
extshx 31 $ А 00000 922 Вс
fabsx 63 D 00000 B 264 Re
faddx 63 D A 8 00000 | 21 Вс
faddsx 59 D A B 80000 | 21 Re
fempo 63 criD | 00 A B 32 0
fempu 63 cD [DO A B 0 0
fctiwx 63 D 09000 B 14 Rc
fetiwzx 63 D | 00000 В 15 Re
fdivx 63 D À в 00000 18 Re
fdivsx 59 D A B 050000 18 Rc
tmaddx 63 D A 8 с 29 Re
fmaddsx 59 D A B с 29 Вс
fmrx 63 D 00000 в 72 Вс
fmsubx 63 D A B с 28 Re
fmsubsx 59 D A B с 28 Ac
fmuix 63 о А 00000 с 25 Re
fraulsx 59 D A 00000 с 25 Re
fnabsx 63 D 00000 B 136 Re
fnegx 63 D 00000 ‘ 40 Re
fnmaddx 63 D A B с al Rc
fnmaddsx 59 D A B с 31 Re
fnmsubx 63 D A B с 30 Re
MSR Bit Settings (Continued)
Bit(s) Name Description
23 FE1 Floating-point exception mode 1
24 — Reserved. Full function.
25 IP Exception prefix. The setting of this bit specifies whether
an exception vector offset is prepended with Fs or 0s. In
the following description, nnnnn is the offset of the
exception.
0 Exceptions are vectored to the physical address
0x000n_nnnn in 32-bit implementations and
0x0000_0000_000n_nnnn in 64-bit
implementations.
Exceptions are vectored to the physical address
OxFFFn_nnnn in 32-bit implementations and
OxFFFF_FFFF_FFFn_nnnnin 64-bit
implementations.
Instruction address translation
0 Instruction address translation is disabled.
1 Instruction address translation is enabled.
Data address translation
0 Data address translation is disabled.
1 Data address translation is enabled.
Reserved. Full function.
Recoverable exception (for system reset and machine
check exceptions).
0 Exception is not recoverable.
1 Exception is recoverable.
Littie-endian mode enable
0 The processor runs in big-endian mode.
1 The processor runs in little-endian mode.
Note: Full function reserved bits are saved in SRR1 when an exception occurs; partial
function reserved bits are not saved.
—
26 IR
27 DR
28-29 —
30 RI
31 LE
Floating-Point Exception Mode Bits
FEO FE! Mode
0 0 Floating-point exceptions disabled
0 1 Fioating-point imprecise nonrecoverable
1 0 Floating-point imprecise recoverable
1 1 Floating-point precise mode
State of MSR at Power Up
Bit(s) Name Description Bit(s) Name Description
0-12 — Unspecified! 22 BE 0
13 PO 0 23 FE1 0
14 — Unspecified’ 24 — Unspecified!
15 ILE 0 25 IP 12
16 EE 0 26 IR 0
17 PR 0 27 DR 0
18 FP 0 28-29 — Unspecified!
19 ME 0 30 RI 0
20 FEO 0 31 LE 0
21 SE 0
Notes:
1. Unspecified can be either 0 or 1 2. 1 is typical, but might be 0
BAT Registers
Upper BAT Register
Bit(s) Name Description
0-14 BEPI Block effective page index
15-18 — Reserved
19-29 BL Block length
30 Vs Supervisor mode valid bit
31 Vp User mode valid bit
Lower BAT Register
Bit(s) Name Description
0-14 BRPN This field is used in conjunction with the BL field to generate
high-order bits of the physical address of the block.
15-24 — Reserved
25-28 WIMG Memory/cache access mode bits
W Write-through
| Caching-inhibited
M Memory coherence
G Guarded
29 — Reserved
30-31 PP Protection bits for block
BAT Area Lengths
BAT Area Length BL Encoding BAT Area Length BL Encoding
128 Kbytes 000 0000 0000 8 Mbytes 000 0011 1111
256 Kbytes 000 0000 0001 16 Mbytes 000 0111 1111
512 Kbytes 000 0000 0011 32 Mbytes 0001111 1111
1 Mbyte 000 0000 0111 64 Mbytes 001 1111 1111
2 Mbytes 000 0000 1111 128 Mbytes Oii 11171 1111
4 Mbytes 000 0001 1111 256 Mbytes 1111111 1111
Name © 6 7 8 8 1011 12 19 14 15 16 17 18 19 20 21 2223242526272929 30 31
orex 31 5 А B ) #12 |Re}
ой 24 5 А UIMM
oris 25 s A "UMM
hi! 19 00000 | 00000 | 00000 50 q
riwimix 20 5 А SH MB ME [Re
riwinmx 21 5 А SH MB ME Вс
riwamx 23 $ А B MB ME Вс
sc 17 00000 00000 00000000000000 1 0
slwx 31 $ А В 24 Rc
srawx 31 S A - B 792 Re
srawix 31 s À SH 824 Rc
srwx 31 $ А —B 536 Re
sth 38 E A а
stbu 39 $ А d
stbux 31 E A B | 247 [o
stbx 31 s A в | 215 lo
stfd 54 5 А а
stfdu 55 5 А d
stfdux 31 $ CA B 759 a
sifdx 31 s A B 727 0
stfiwx 4 31 $ А B 983 0
stfs 52 5 А d
stisu 53 $ А d
stfsux 31 $ А - | 695 | 6
stfsx 31 $ А B | 663 Lo
sth 44 5 А d
sthbrx 31 ES A B | 918 | 0
sthu 45 5 А d
sthux 31 $ А B | 439 Lo
sthx 31 Ss A B | 407 | 0
stmw 3 47 $ А а
stswi 3 31 s A NB | 725 a
stswx 3 ai 5 А B | 661 a
stw 96 5 А d
stwbrx 31 8 A B | 662 [o
stwex. 31 5 А 8 | 150 | 1
stwu 37 5 A d
stwux 31 $ А B 183
stwx 31 s A B 151 a
subfx a" D A B OF] 40 Fic
subfex 31 D A B oF 8 Re
subfex 31 D A B OF] 136 Re
subfic 08 D. A SIMM
subfmex 31 D A | 00000 log 232 Вс
subfzex 31 D A 00060 OF] 200 Вс
sync 31 00000 00000 00000 598 0
tibla 14 31 00000 | 00000 | 00000 370 0
tible ™| at | 00000 | 00000 B — 906 о
tibsync!* 31 00000 00000 00000 566 o
tw 31 TO A B 4 0
twi 03 TO A SIMM
xorx 31 $ А B 316 Re
xori 26 5 А UIMM
xoris 27 5 А UIMM
! Supervisor-level instruction
? Supervisor- and user-leval instruction
* Load and store string or multiple instruction
* Optional instruction
5 32-bit instruction only
Memory Management Registers
Instruction BAT Registers Data BAT Registers
IBATOU SPR 528 DBATOU SPR 536
IBATOL SPR 529 DBATOL SPR 537
IBAT1U SPR 530 DBAT1U SPR 538
IBATIL SPR 531 DBAT1L SPR 539
IBAT2U SPR 532 DBAT2U SPR 540
IBAT2L SPR 533 DBAT2L SPR 541
IBAT3U SPR 534 DBAT3U SPR 542
IBATSL SPR 535 DBATSL SPR 543
Encodings for the Branch Options Field
BO Description
0000y Decrement the CTR, then branch if the decremented CTR = 0 and
the condition is FALSE.
0001y Decrement the CTR, then branch if the decremented CTR = 0 and
the condition is FALSE.
001zy Branch if the condition is FALSE.
0100y Decrement the CTR, then branch if the decremented CTR = 0 and
the condition is TRUE.
0101y Decrement the CTR, then branch if the decremented CTR = 0 and
the condition is TRUE.
0112y Branch if the condition is TRUE.
1200y Decrement the CTR, then branch if the decremented CTR = 0.
1701y Decrement the CTR, then branch if the decremented CTR = 0.
17177 Branch always.
Notes:
The zindicates a bit that is ignored. The z bits should be cleared to zero, as they
may be assigned a meaning in some future version of the PowerPC architecture.
The y bit provides a hint about whether a conditional branch is likely to be taken
and is used by some PowerPC implementations to improve performance. Other
implementations may ignore the y bit.
MSR Bit Settings
Bit(s)
0
1-4
5-9
10-12
13
Name Description
— Reserved. Full function.”
— Reserved. Partial function.”
— Reserved. Full function.
— Reserved. Partial function.
POW Power management enable
0 Power management disabled (normal operation
mode).
1 Power management enabled (reduced power
mode).
Note: Power management functions are implementation-dependent. If the function is
not implemented, t
— Reserved--Implementation-specific
14
15
16
17
18
19
20
21
is bit is treated as reserved.
ILE Exception little-endian mode. When an exception
occurs, this bit is copied into MSRILE] to select the
endian mode for the context established by the
exception.
EE External interrupt enable
O While the hit is cleared the processor delays
recognition of external interrupts and decrementer
exception conditions.
1 The processor Is enabled to take an external
interrupt or the decrementer exception.
PR Privilege level
0 The processor can execute both user- and
supervisor-level instructions.
1 The processor can only execute user-level
instructions.
FP Floating-point available
0 The processor prevents dispatch of floating-point
instructions, including floating-point loads, stores,
and moves.
1 The processor can execute floating-point
instructions.
ME Machine check enable
0 Machine check exceptions are disabled.
1 Machine check exceptions are enabled.
FEO Floating-point exception mode 0
SE Single-step trace enable (Optional)
0 The processor executes instructions normally.
1 The processor generates a single-step trace
exception upon the succassful execution of the next
instruction.
Note: If the function is not implemented, this bit is treated as reserved.
E
22
Branch trace enable (Optional)
0 The processor executes branch instructions
normally.
The processor generates a branch trace exception
after completing the execution of a branc
instruction, regardless of whether or not the branch
was taken.
—
Note: If the function is not implemented, this bit is treated as reserved.
PowerPT
© Motorola Inc., 1996. All rights reserved
Portions hereof g International Business Machines Corporation, 1991-1996, AN rights reserved,
Information in this document is provided solely lo enable system and software implementers to use PowerPC
microprocessors, Thare are no express or implied copyright or patent licenses granted hereunder by Motorola or
IBM to design, modify the design of, or fabricate circuits based on the information in this document.
The PowerPC 60x microprocessors embady Ihe intallaclual property of Motorola and of IBM. However, neither
Motorola nor IBM assumes any responsibility or liability as to any aspects of the performance, operation, or ofher
attributes of the microprocessor as marketed by tha other party or by any third party. Neither Motorola nor IBM is to be
considered an agent or representative of the other, and neilher has assumed, created, or granted hereby any right or
authority to the other, or lo any third party, to assume or create any express ог implied obiigations on lts behalf.
information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules,
and support, for the product may vary as between parties selfing the product. Accordingly, customers wishing to learn
more information about the products as marketed by a given party should contact that party.
Both Motorola and IBM reserve the right to modify this documant and/or any of the products as described herein
without further notice. NOTHING IN THIS DOCUMENT, NOR IN ANY OF THE ERRATA SHEETS, DATA SHEETS,
AND OTHER SUPFORTING DOCUMENTATION, SHALL BE INTERPRETED AS THE CONVEYANCE BY
MOTOROLA OR IBM OF AN EXPRESS WARRANTY OF ANY KIND OR IMPLIED WARRANTY,
REPRESENTATION, CR GUARANTEE REGARDING THE MERCHANTABILITY OR FITNESS OF THE PRODUCTS
FOR ANY PARTICULAR PURPOSE. Neither Motorola nor [BM assumes any Hability or obligation for damages of any
kind arising out of the application or use of these materials. Any warranty or other obligations as to {he products
described herein shalt be undertaken solely by the marketing party to Ihe customer, under a separate sale agreement
between the marketing party and the customer. In the absence of such an agreement, no liability is assumed by
Motorola, IBM, or the marketing party for any damages, actual or otherwise,
“Typical” paramelars can and do vary In diffarent applications. All operating parametars, including “Typicals,” must be
validated lor each customer application by customer's technical experts, Neither Motorola nor IBM convey any license
under their respective intelteclual proparty rights nor the rights of olhars. Neither Motorola nor [BM makes any claim,
warranty, or representation, express or Implied, that the products described In this document are dasigned, intanded,
or authorized for use as components in systems intended for surgical implant Into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the product could create a situation
where personal injury or death may occur, Should customer purchase or use the products for any such unintended or
unauthorized application, customer shall indemnify and hold Motorola and IBM and their respective officers,
employees, subsidiaries, affiliates, and distributors harmless against alt claims, costs, damages, and expenses, and
reasonable attorney's fees arising out of, directly or indireclly, any claim of personal injury or death associated with
such unintended or unaulhorizad use, even If such claim alleges that Motorola or IBM was negligent regarding the
design or manufacture of lhe part.
Motorola and А, are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Cpportunity/Affirmative
Action Employar. —
IBM, the IBM logo, and IBM Microetactronics are trademarks of Internalional Business Machines Corporation.
The PowerPC name and the PowerPC logolype are Irademarks of International Business Machines Corporation, used
by Motorola under license from international Business Machines Corporation, International Business Machines
Corporation is an Equal Opportunity/Affirmative Action Employer.
(M) MOTOROLA
International Business Machines Corporation: Motorola Literature Distribution Centers:
IBM Microelectronics Division, 1580 Route 52, USA/EUROPE: Motorola Literature Distribution:
Bidg. 504, Hopewell Junction, NY 12533-6531; P.Q. Box 20912; Phoenix, Arizona 85036;
Tel. (800) PowerPC Tel.; 1-800-441-2447
World Wide Web Address: JAPAN: Nippon Motorola Lid.; Tatsumi-SPD-JLDC,
http://www.chips.ibm.com/praducts/ppc Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center,
http://www.ibm.com 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan;
Tel.: 03-3521-8315
HONG KONG: Motorola Samiconductors H.K. Ltc.:
8B Tai Ping Industrlal Park, 51 Ting Kok Road,
Tai Po, N.T., Hong Kong; Tel.: 852-26629298
MFAX: RMFAX0@ email.sps.mot.com;
TOUCHTONE (602) 244-6609
INTERNET: http://Design-NET.com
Technical Information:
Motorola Inc. SPS Customer Support Center;
(800) 521-6274.
Document Comments: FAX (512) 891-2638,
Attn: RISC Applications Engineering.
World Wide Web Address:
http:Z/wanw.mot.com/powerpc/
SA14-2093-00 MPCPRGREF/D
COE ALE LATE NOAA CAE RTE 0 CAT EA RRA ROO МЫ
TATX95209-0 PRINTED IN USA 8/96 IMPERIAL LITHO 23784 5,000 RISC YGAHAA
">